+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _RESET_H
unsigned int count;
};
-#ifdef CONFIG_DM_RESET
+#if CONFIG_IS_ENABLED(DM_RESET)
/**
* reset_get_by_index - Get/request a reset signal by integer index.
*
return -ENOTSUPP;
}
-static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+static inline int reset_get_bulk(struct udevice *dev,
+ struct reset_ctl_bulk *bulk)
{
return -ENOTSUPP;
}
return 0;
}
-static inline int reset_release_bulk(struct clk_bulk *bulk)
+static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
{
return 0;
}