]> git.sur5r.net Git - u-boot/commit
fsl-layerscape: Consolidate registers space defination for CCI-400 bus
authorAshish Kumar <Ashish.Kumar@nxp.com>
Fri, 11 Aug 2017 05:39:14 +0000 (11:09 +0530)
committerYork Sun <york.sun@nxp.com>
Mon, 11 Sep 2017 14:55:36 +0000 (07:55 -0700)
commit63b2316c5c4ba0e47d1f69ef1372db4fd89b6bf5
tree065b8277ffa5951efbff0a53bdb8a6f797d7b884
parent584f316f115df52fd09a6cf699b29dcf824b4da5
fsl-layerscape: Consolidate registers space defination for CCI-400 bus

CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>
15 files changed:
README
arch/arm/cpu/armv7/ls102xa/Kconfig
arch/arm/cpu/armv7/ls102xa/soc.c
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
arch/arm/cpu/armv8/fsl-layerscape/soc.c
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
board/freescale/ls1012afrdm/ls1012afrdm.c
board/freescale/ls1012aqds/ls1012aqds.c
board/freescale/ls1012ardb/ls1012ardb.c
board/freescale/ls1021aqds/ls1021aqds.c
include/fsl_immap.h
scripts/config_whitelist.txt