]> git.sur5r.net Git - u-boot/commit
MIPS: fix iand optimize setup of CP0 registers
authorDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Sun, 7 Feb 2016 23:37:59 +0000 (00:37 +0100)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Wed, 30 Nov 2016 15:11:46 +0000 (16:11 +0100)
commit65d297af7c6a08ec65bf005fa9bd5cdb955efe39
treede9839a98dd41a56a6a93cf61230c6c0d3ec43ea
parent345490fcd68d830adef7fcfa4ef5bf5681c29546
MIPS: fix iand optimize setup of CP0 registers

Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.

Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.

Initialize cp0 count as early as possible to get the most
accurate boot timing.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
arch/mips/cpu/start.S
arch/mips/include/asm/mipsregs.h