]> git.sur5r.net Git - u-boot/commit
spi: cadence_qspi_apb: Make flash writes 32 bit aligned
authorVignesh R <vigneshr@ti.com>
Wed, 24 Jan 2018 05:14:07 +0000 (10:44 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Wed, 24 Jan 2018 06:41:36 +0000 (12:11 +0530)
commitaaa21d3ffc023623a3a8247e5fa25d0db2bfb630
treeec98c877478e4ec2028f1fd5192461023db8f8ca
parenta743e2ba3837db5e8499b03f0f57c3610d03a570
spi: cadence_qspi_apb: Make flash writes 32 bit aligned

Make flash writes 32 bit aligned by using bounce buffers to deal with
non 32 bit aligned buffers.
This is required because as per TI K2G TRM[1], the external master is
only permitted to issue 32-bit data interface writes until the last word
of an indirect transfer. Otherwise indirect writes is known to fail
sometimes.

[1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
drivers/spi/cadence_qspi_apb.c