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(parent: c5b8412) | patch
MIPS: Clear hazard between TagLo writes & cache ops
authorPaul Burton <paul.burton@imgtec.com>
Wed, 21 Sep 2016 10:18:58 +0000 (11:18 +0100)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Wed, 21 Sep 2016 13:04:04 +0000 (15:04 +0200)
commitd608254b0aa23607df1dcb5a7ca07de9a8ec9bb0
tree08974b3c02079cc147794c9a28eab7f35e0cd156tree | snapshot
parentc5b8412d60e22b49348a63848cbf7b6ab5ccb16ecommit | diff
MIPS: Clear hazard between TagLo writes & cache ops

Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
arch/mips/lib/cache_init.S diff | blob | history
Cloned from git://git.denx.de/u-boot.git