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(parent: 1038e03) | patch
clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock
authorPatrice Chotard <patrice.chotard@st.com>
Thu, 8 Feb 2018 16:20:49 +0000 (17:20 +0100)
committerTom Rini <trini@konsulko.com>
Wed, 14 Mar 2018 01:45:37 +0000 (21:45 -0400)
commite8fb9ed2542ab6ca1946bec34a5232bde785f141
tree95e115e585b41b95a80b4f702ecf1be2d7619896tree | snapshot
parent1038e033e1e999b11568c8daf0a4e19b31086266commit | diff
clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock

Configure SAI PLL configuration to generate LTDC pixel clock on
the PLLSAIR output.

PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
drivers/clk/clk_stm32f.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git