]> git.sur5r.net Git - u-boot/commit
arm64: zynqmp: mp: Correct the R5 release sequence
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tue, 1 Aug 2017 10:54:52 +0000 (16:24 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 28 Nov 2017 15:08:56 +0000 (16:08 +0100)
commitf322ad604e7e1418f8deb7646aa5d2b0a2bae83e
treeb606391076fa4b607c306a1e6711127e05d6ea9d
parent62e950fad3cc8c9bee0d4499e580d4ff80945028
arm64: zynqmp: mp: Correct the R5 release sequence

This patch corrects the R5 release sequence by adding the
below steps.
1. Flush dcache to ensure that image loaded into memory.
2. Keep R5 reset just to ensure R5 in reset.
3. Disable caches before accessing TCM as with out this
   A53 can do speculative and may result in ECC failures
   if TCM's are not initialized. So, it is always better
   to disable dcaches before accessing TCM and enable back.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/cpu/armv8/zynqmp/mp.c