]> git.sur5r.net Git - u-boot/commit
7450 and 86xx L2 cache invalidate bug corrections
authorWheatley Travis <Travis.Wheatley@freescale.com>
Fri, 2 May 2008 20:35:15 +0000 (13:35 -0700)
committerWolfgang Denk <wd@denx.de>
Fri, 9 May 2008 18:46:48 +0000 (20:46 +0200)
commitf5a24259190c388c2527bdc49fee34577d862cc7
treee77d0df2fc72dfd1a26c993785dae2250738eb2d
parent4d31cdc45d3592a5545a649fb5a24b458a4e4b72
7450 and 86xx L2 cache invalidate bug corrections

The 7610 and related parts have an L2IP bit in the L2CR that is
monitored to signal when the L2 cache invalidate is complete whereas the
7450 and related parts utilize L2I for this purpose. However, the
current code does not account for this difference. Additionally the 86xx
L2 cache invalidate code used an "andi" instruction where an "andis"
instruction should have been used.

This patch addresses both of these bugs.

Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
Acked-By: Jon Loeliger <jdl@freescale.com>
cpu/74xx_7xx/cache.S
cpu/mpc86xx/cache.S