]> git.sur5r.net Git - u-boot/commit
armv8/ls1043a: fixup GIC offset for ls1043a rev1
authorWenbin Song <wenbin.song@nxp.com>
Tue, 17 Jan 2017 10:31:15 +0000 (18:31 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 18 Jan 2017 17:29:21 +0000 (09:29 -0800)
commitfa18ed76589a684fc9ba14b68d7b917b1bea16cf
treee04efffdb1fe39b70fb1ba88deb9c53d444b9661
parent435cca167149d19a9740806f63a3f58388280507
armv8/ls1043a: fixup GIC offset for ls1043a rev1

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.

The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.

If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.

Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.

The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
arch/arm/include/asm/arch-fsl-layerscape/config.h
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
arch/arm/include/asm/arch-fsl-layerscape/soc.h