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u-boot
7 years agoomap3: i2c: correct register
Adam Ford [Sat, 8 Apr 2017 22:34:29 +0000 (17:34 -0500)]
omap3: i2c: correct register

The register names and offset were not correct as per the TRM for OMAP3530
and OMAP3630.  Correct the naing and offsets per the documentation

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
7 years agoMerge git://git.denx.de/u-boot-sunxi
Tom Rini [Tue, 25 Apr 2017 20:12:42 +0000 (16:12 -0400)]
Merge git://git.denx.de/u-boot-sunxi

7 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 25 Apr 2017 20:11:35 +0000 (16:11 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Tue, 25 Apr 2017 13:00:18 +0000 (09:00 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Tue, 25 Apr 2017 12:59:56 +0000 (08:59 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

7 years agoehci-ppc4xx: Prepare for usage of readl()/writel() accessors
Alexey Brodkin [Mon, 17 Apr 2017 16:13:17 +0000 (19:13 +0300)]
ehci-ppc4xx: Prepare for usage of readl()/writel() accessors

We used to have opencoded ehci_readl()/writel() which required no
external functions to be called.

Now with attempt to switch to generic readl()/writel() accessors
we see a missing declaration of those accessors in ehci-ppc4xx.
Something like that happens if applied
http://patchwork.ozlabs.org/patch/726714/:
---------------->8---------------
  CC      drivers/usb/host/ehci-ppc4xx.o
drivers/usb/host/ehci-ppc4xx.c: In function 'ehci_hcd_init':
drivers/usb/host/ehci-ppc4xx.c:23:3: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
   HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
   ^
---------------->8---------------

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agousb: musb: avoid out of bound access in udc_setup_ep
Heinrich Schuchardt [Sat, 15 Apr 2017 12:29:54 +0000 (14:29 +0200)]
usb: musb: avoid out of bound access in udc_setup_ep

For id = 15 an out of bound access occurs in udc_setup_ep().
Increase the size of epinfo[] from 30 to 32 to encompass
ids 0..15.

The problem was highlighted by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agomusb: properly detect failed initialization of controller
Heinrich Schuchardt [Sat, 15 Apr 2017 11:46:22 +0000 (13:46 +0200)]
musb: properly detect failed initialization of controller

We want to check the result of musb_init_controller
and not the address were the result is stored.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agoarm: socfpga: add cyclone5 based de10-nano board
Dalon Westergreen [Tue, 18 Apr 2017 15:11:16 +0000 (08:11 -0700)]
arm: socfpga: add cyclone5 based de10-nano board

Add support for the Terasic DE10-Nano board.  The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
7 years agosunxi: fix the default value of CONS_INDEX on non-A23/A33 SUN8I
Icenowy Zheng [Mon, 24 Apr 2017 17:39:51 +0000 (01:39 +0800)]
sunxi: fix the default value of CONS_INDEX on non-A23/A33 SUN8I

Only A23/A33 in SUN8I want a default value of CONS_INDEX of 5, for other
chips the default value is 1 like other Allwinner SoCs.

Fix this default value.

The original wrong value has lead to wrong console on H3 Orange Pi
boards.

Fixes: 7095f8641863 ("sunxi: Convert CONS_INDEX to Kconfig")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-uniphier
Tom Rini [Tue, 25 Apr 2017 01:08:42 +0000 (21:08 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-uniphier

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Tue, 25 Apr 2017 01:08:10 +0000 (21:08 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

7 years agoarmv8: layerscape: Fix DDR size calcuation for SPL build
York Sun [Thu, 20 Apr 2017 23:04:23 +0000 (16:04 -0700)]
armv8: layerscape: Fix DDR size calcuation for SPL build

Commit 088454cd dropped return value from initram(), setting
gd->ram_size directly. Three boards were missed for SPL boot.

Signed-off-by: York Sun <york.sun@nxp.com>
7 years agoarm: psci: make psci usable on single core socs
Yuantian Tang [Wed, 19 Apr 2017 05:27:39 +0000 (13:27 +0800)]
arm: psci: make psci usable on single core socs

PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.

Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls104xardb: Secure Boot: enable PPA support for eMMC/SD and NAND boot
Sumit Garg [Wed, 19 Apr 2017 23:39:13 +0000 (05:09 +0530)]
armv8: ls104xardb: Secure Boot: enable PPA support for eMMC/SD and NAND boot

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-layerscape: Add validation of PPA image from NAND and SD
Sumit Garg [Wed, 19 Apr 2017 23:39:12 +0000 (05:09 +0530)]
armv8: fsl-layerscape: Add validation of PPA image from NAND and SD

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND Flash
Sumit Garg [Wed, 19 Apr 2017 23:39:11 +0000 (05:09 +0530)]
armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND Flash

Add Kconfig option to support loading PPA header from eMMC/SD and
NAND Flash.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1046aqds: Integrate FSL PPA
Hou Zhiqiang [Fri, 14 Apr 2017 06:48:23 +0000 (14:48 +0800)]
armv8: ls1046aqds: Integrate FSL PPA

The PPA is a EL3 firmware, which support PSCI, hotplug,
power-management features etc.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1043aqds: enable FSL PPA
Hou Zhiqiang [Fri, 14 Apr 2017 06:48:22 +0000 (14:48 +0800)]
armv8: ls1043aqds: enable FSL PPA

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1043aqds: Integrate FSL PPA
Hou Zhiqiang [Fri, 14 Apr 2017 06:48:21 +0000 (14:48 +0800)]
armv8: ls1043aqds: Integrate FSL PPA

The PPA is a EL3 firmware, which support PSCI, hotplug,
power-management features etc.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls2080ardb: Add phy number for serdes1 protocol 0x4b
Santan Kumar [Thu, 13 Apr 2017 10:01:09 +0000 (15:31 +0530)]
armv8: ls2080ardb: Add phy number for serdes1 protocol 0x4b

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033
Alison Wang [Tue, 11 Apr 2017 07:02:13 +0000 (15:02 +0800)]
arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033

Since commit ce412b7, RGMII TX clock internal delay is not enabled
for AR8033 unconditionally. On LS1021ATWR board, the third port
eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to
be enabled.

This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX
clock internal delay for AR8033 on the third port.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agosunxi: Fix arm64 fdtfile variable
Andreas Färber [Fri, 14 Apr 2017 16:44:47 +0000 (18:44 +0200)]
sunxi: Fix arm64 fdtfile variable

Currently $fdtfile is constructed from CONFIG_DEFAULT_TREE, containing
the filename. However on arm64 that file is located in an allwinner
subdirectory.

To avoid the need for users/distros symlinking the .dtb files, prepend
the vendor directory for ARM64.

This aligns Pine64 with other boards such as Raspberry Pi 3.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agomips: qemu-mips/64: Expand malloc pool for CONFIG_SYS_BOOTPARAMS_LEN
Kyle Edwards [Thu, 13 Apr 2017 02:42:32 +0000 (22:42 -0400)]
mips: qemu-mips/64: Expand malloc pool for CONFIG_SYS_BOOTPARAMS_LEN

Before this patch, CONFIG_SYS_BOOTPARAMS_LEN was the same size as
CONFIG_SYS_MALLOC_LEN. So, if malloc() had previously been called, and
initr_malloc_bootparams() was called, it would fail with an out-of-
memory error. This patch fixes this issue by expanding the malloc pool
to 256KB.

Signed-off-by: Kyle Edwards <kyleedwardsny@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
7 years agomips: qemu-mips/64: Remove obsolete CONFIG_SYS_MONITOR_LEN from config
Kyle Edwards [Thu, 13 Apr 2017 02:42:31 +0000 (22:42 -0400)]
mips: qemu-mips/64: Remove obsolete CONFIG_SYS_MONITOR_LEN from config

This fixes an issue with the saveenv command causing U-Boot to no
longer work on the QEMU Mips pseudoboard. Because the offset of the
environment was being determined by CONFIG_SYS_MONITOR_LEN, and this
value was less than the actual size of U-Boot, saveenv was overwriting
parts of the U-Boot code. Because CONFIG_SYS_MONITOR_LEN is no longer
used on MIPS, this patch removes it and places the environment at the
end of the pseudoboard's 4MB flash.

Signed-off-by: Kyle Edwards <kyleedwardsny@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
7 years agosunxi: add support for Lichee Pi Zero
Icenowy Zheng [Sat, 8 Apr 2017 07:30:14 +0000 (15:30 +0800)]
sunxi: add support for Lichee Pi Zero

Lichee Pi Zero is a development board with a V3s SoC, which features
64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not
soldered in production batch), a 40-pin RGB LCD connector and some extra
pins available as 2.54mm pins or stamp holes.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: add DTSI file for V3s
Icenowy Zheng [Sat, 8 Apr 2017 07:30:13 +0000 (15:30 +0800)]
sunxi: add DTSI file for V3s

As we have now V3s support in board code, the V3s DTSI file should also
be added.

Add also some CCU include headers to satisfy the DTSI file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: add basic V3s support
Icenowy Zheng [Sat, 8 Apr 2017 07:30:12 +0000 (15:30 +0800)]
sunxi: add basic V3s support

Basic U-Boot support is now present for V3s.

Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.

As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoARM: dts: uniphier: sync Device Tree with Linux
Masahiro Yamada [Thu, 20 Apr 2017 07:54:44 +0000 (16:54 +0900)]
ARM: dts: uniphier: sync Device Tree with Linux

- Use - instead of @ for OPP tables
 - Add input-delay properties to Cadence eMMC nodes
 - Restore full license text because code-diff is annoying
 - Fix NAND compatible strings

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: show STM (SCP) status on boot and pinmon command
Masahiro Yamada [Thu, 20 Apr 2017 07:54:43 +0000 (16:54 +0900)]
ARM: uniphier: show STM (SCP) status on boot and pinmon command

The SCP (System Control Processor) or what we call STM (Stand-by
MPU) is integrated in LD4, Pro4, sLD8, LD6b, LD11, and LD20.
For these SoCs, show the information if STM is enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: enable PSCI sysreset for uniphier_v8_defconfig
Masahiro Yamada [Thu, 20 Apr 2017 07:54:42 +0000 (16:54 +0900)]
ARM: uniphier: enable PSCI sysreset for uniphier_v8_defconfig

This configuration is supposed to be used with ARM Trusted Firmware,
so the SYSTEM_RESET is implemented in BL31.  Invoke PSCI instead of
U-Boot's own reset code because we need to coordinate with SCP
(System Control Processor) for the system-level power management.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: setup EHCI PHY paramters for LD11
Masahiro Yamada [Fri, 14 Apr 2017 02:30:05 +0000 (11:30 +0900)]
ARM: uniphier: setup EHCI PHY paramters for LD11

Set the same PHY parameters as the Boot ROM uses.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agosunxi: Add clock support for DE2/HDMI/TCON on newer SoCs
Jernej Skrabec [Mon, 27 Mar 2017 17:22:31 +0000 (19:22 +0200)]
sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

This is needed for HDMI, which will be added later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: video: Convert lcdc to use struct display_timing
Jernej Skrabec [Mon, 27 Mar 2017 17:22:30 +0000 (19:22 +0200)]
sunxi: video: Convert lcdc to use struct display_timing

Video driver for older Allwinner SoCs uses cfb console framework which
in turn uses struct ctfb_res_modes to hold timing informations. However,
DM video framework uses different structure - struct display_timing.

It makes more sense to convert lcdc to use new timing structure because
all new drivers should use DM video framework and older drivers might be
rewritten to use new framework too.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: video: Split out TCON code
Jernej Skrabec [Mon, 27 Mar 2017 17:22:29 +0000 (19:22 +0200)]
sunxi: video: Split out TCON code

TCON unit has similar layout and functionality also on newer SoCs. This
commit splits out TCON code for easier reuse later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Add support for Bananapi M2 Ultra
Chen-Yu Tsai [Fri, 2 Dec 2016 08:12:32 +0000 (16:12 +0800)]
sunxi: Add support for Bananapi M2 Ultra

The Bananapi M2 Ultra is the first publicly available development board
featuring the R40 SoC.

This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra,
as well as a defconfig for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Add PSCI support for R40
Chen-Yu Tsai [Wed, 1 Mar 2017 03:03:15 +0000 (11:03 +0800)]
sunxi: Add PSCI support for R40

The R40's CPU controls are a combination of sun6i and sun7i.

All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.

Last, the R40 does not have a secure SRAM block.

This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Fix CPUCFG address for R40
Chen-Yu Tsai [Wed, 1 Mar 2017 05:52:09 +0000 (13:52 +0800)]
sunxi: Fix CPUCFG address for R40

The R40 has the CPUCFG block at the same address as the A20.
Fix it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Enable SPL for R40
Chen-Yu Tsai [Fri, 2 Dec 2016 08:09:49 +0000 (16:09 +0800)]
sunxi: Enable SPL for R40

Now that we can do DRAM initialization for the R40, we can enable
SPL support for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Use H3/A64 DRAM initialization code for R40
Chen-Yu Tsai [Thu, 1 Dec 2016 11:09:57 +0000 (19:09 +0800)]
sunxi: Use H3/A64 DRAM initialization code for R40

The R40 seems to have a variant of the memory controller found in
the H3 and A64 SoCs. Adapt the code for use on the R40. The changes
are based on released DRAM code and comparing register dumps from
boot0.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agogpio: sunxi: Add compatible string for R40 PIO
Chen-Yu Tsai [Wed, 30 Nov 2016 09:23:52 +0000 (17:23 +0800)]
gpio: sunxi: Add compatible string for R40 PIO

The PIO on the R40 SoC is mostly compatible with the A20.
Only a few pin functions for mmc2 were added to the PC
pingroup, to support 8 bit eMMCs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Provide defaults for R40 DRAM settings
Chen-Yu Tsai [Wed, 30 Nov 2016 08:58:35 +0000 (16:58 +0800)]
sunxi: Provide defaults for R40 DRAM settings

These values were taken from the Banana Pi M2 Ultra fex file
found in the released vendor BSP. This is the only publicly
available R40 device at the time of this writing.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Set PLL lock enable bits for R40
Chen-Yu Tsai [Wed, 30 Nov 2016 08:54:34 +0000 (16:54 +0800)]
sunxi: Set PLL lock enable bits for R40

According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.

This patch enables it for all the PLLs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Add mmc[1-3] pinmux settings for R40
Chen-Yu Tsai [Wed, 30 Nov 2016 08:28:34 +0000 (16:28 +0800)]
sunxi: Add mmc[1-3] pinmux settings for R40

The PIO is generally compatible with the A20, except that it routes the
full 8 bits and eMMC reset pins for mmc2.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Fix watchdog reset function for R40
Chen-Yu Tsai [Wed, 30 Nov 2016 08:27:14 +0000 (16:27 +0800)]
sunxi: Fix watchdog reset function for R40

The watchdog found on the R40 SoC is the older variant found on the A20.
Add the proper "#if defines" to make it work.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Enable AXP221s in I2C mode with the R40 SoC
Chen-Yu Tsai [Wed, 30 Nov 2016 07:30:30 +0000 (15:30 +0800)]
sunxi: Enable AXP221s in I2C mode with the R40 SoC

The R40 SoC uses the AXP221s in I2C mode to supply power.

Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Add initial support for R40
Chen-Yu Tsai [Wed, 30 Nov 2016 06:57:32 +0000 (14:57 +0800)]
sunxi: Add initial support for R40

The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.

The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.

The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Split up long Kconfig lines
Chen-Yu Tsai [Thu, 2 Mar 2017 08:03:06 +0000 (16:03 +0800)]
sunxi: Split up long Kconfig lines

Currently we have some lines in board/sunxi/Kconfig that are very long.
These line either provide default values for a set of SoCs, or limit
some option to a subset of sunxi SoCs.

Fortunately Kconfig makes it easy to split them. The Kconfig language
document states

    If multiple dependencies are defined, they are connected with '&&'.

This means we can split existing dependencies at "&&" symbols. This
applies to both the "depends on" lines and "if" expressions.

This patch splits them up to one symbol per line. This will make it
easier to add, remove, or modify one item at a time.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Convert CONS_INDEX to Kconfig
Mylène Josserand [Sun, 2 Apr 2017 10:59:11 +0000 (12:59 +0200)]
sunxi: Convert CONS_INDEX to Kconfig

Convert the CONS_INDEX configuration to Kconfig.
Update sunxi's defconfigs to remove SYS_EXTRA_OPTIONS variable not
needed anymore.
Default value is 1 except for sun5i (equals 2) and sun8i (equals 5).

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
[Maxime: Added a depends on ARCH_SUNXI to avoid build breakages]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Convert CONFIG_MACPWR to Kconfig
Mylène Josserand [Sun, 2 Apr 2017 10:59:10 +0000 (12:59 +0200)]
sunxi: Convert CONFIG_MACPWR to Kconfig

Convert the CONFIG_MACPWR to Kconfig and update all the sunxi defconfigs
that used it in SYS_EXTRA_OPTIONS.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Convert CONFIG_SATAPWR to Kconfig
Mylène Josserand [Sun, 2 Apr 2017 10:59:09 +0000 (12:59 +0200)]
sunxi: Convert CONFIG_SATAPWR to Kconfig

Convert the CONFIG_SATAPWR into kconfig.
Thanks to that, many SYS_EXTRA_OPTIONS can be removed from some
defconfigs.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Convert CONFIG_RGMII to Kconfig
Mylène Josserand [Sun, 2 Apr 2017 10:59:08 +0000 (12:59 +0200)]
sunxi: Convert CONFIG_RGMII to Kconfig

Convert CONFIG_RGMII to Kconfig. Thanks to that, it is possible to
update defconfig files of SYS_EXTRA_OPTIONS accordingly and
remove it when it is possible.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Convert SUNXI_EMAC to Kconfig
Mylène Josserand [Sun, 2 Apr 2017 10:59:07 +0000 (12:59 +0200)]
sunxi: Convert SUNXI_EMAC to Kconfig

Convert the SUNXI_EMAC config to Kconfig. Remove it from SYS_EXTRA_OPTIONS
from many sunxi defconfig and renamed it into SUN4I_EMAC to not confuse it
with SUN8I_EMAC.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: mk802_defconfig: Remove SYS_EXTRA_OPTIONS
Mylène Josserand [Sun, 2 Apr 2017 10:59:06 +0000 (12:59 +0200)]
sunxi: mk802_defconfig: Remove SYS_EXTRA_OPTIONS

The USB_EHCI configuration is already set in this defconfig
using kconfig's config. This configuration in SYS_EXTRA_OPTIONS
must be removed and so the SYS_EXTRA_OPTIONS.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: icnova-a20-swac_defconfig: Remove CMD_BMP from
Mylène Josserand [Sun, 2 Apr 2017 10:59:05 +0000 (12:59 +0200)]
sunxi: icnova-a20-swac_defconfig: Remove CMD_BMP from

This configuration is not necessary in a defconfig file so
it is removed from the SYS_EXTRA_OPTIONS.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: icnova-a20-swac_defconfig: Remove AXP209_POWER
Mylène Josserand [Sun, 2 Apr 2017 10:59:04 +0000 (12:59 +0200)]
sunxi: icnova-a20-swac_defconfig: Remove AXP209_POWER

Remove the AXP209_POWER option from SYS_EXTRA_OPTIONS.
As this configuration already exists on Kconfig, we just need
to remove it from defconfig.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agosunxi: Move SUNXI_GMAC to Kconfig
Mylène Josserand [Sun, 2 Apr 2017 10:59:03 +0000 (12:59 +0200)]
sunxi: Move SUNXI_GMAC to Kconfig

Move the SUNXI_GMAC config option to Kconfig, remove it
from SYS_EXTRA_OPTIONS and rename it into SUN7I_GMAC.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 18 Apr 2017 15:36:06 +0000 (11:36 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq

7 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Tue, 18 Apr 2017 14:31:46 +0000 (10:31 -0400)]
Merge git://git.denx.de/u-boot-x86

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-ubi
Tom Rini [Tue, 18 Apr 2017 14:31:39 +0000 (10:31 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-ubi

7 years agoboard: Remove orphan SPARC boards
Tom Rini [Tue, 18 Apr 2017 14:30:09 +0000 (10:30 -0400)]
board: Remove orphan SPARC boards

Since 936478e797a8 SPARC as been removed as an architecture.  Remove
these now orphan boards.

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agorockchip: Print a message when returning to the bootrom
Simon Glass [Sat, 15 Apr 2017 19:11:31 +0000 (13:11 -0600)]
rockchip: Print a message when returning to the bootrom

At present if the return to bootrom fails (e.g. because you are not using
the Rockchip's bootrom's pointer table in MMC) then the board prints
SPL message and hangs. Print a message first if we can, to help in
understanding what happened when it hangs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
7 years agodrivers/crypto/fsl: remove redundant logical contraint
xypron.glpk@gmx.de [Sat, 15 Apr 2017 14:37:54 +0000 (16:37 +0200)]
drivers/crypto/fsl: remove redundant logical contraint

'A || (!A && B)' is equivalent to 'A || B'.
Let's reduce the complexity of the statement in start_jr0().

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agofsl/sata: correctly identify failed malloc
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:31:53 +0000 (15:31 +0200)]
fsl/sata: correctly identify failed malloc

After allocating sata->cmd_hdr_tbl_offset we have to check
this variable and not variable sata.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoddr: fsl: incorrect logical constraint in populate_memctl_options
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:23:49 +0000 (15:23 +0200)]
ddr: fsl: incorrect logical constraint in populate_memctl_options

(pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40)
is always true.

We should use && here.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoFPGA: drivers/fpga/ivm_core.c: incorrect printf
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:15:40 +0000 (15:15 +0200)]
FPGA: drivers/fpga/ivm_core.c: incorrect printf

The number of arguments for printf does not match the
format string.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agousbtty: avoid potential NULL pointer dereference
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:05:46 +0000 (15:05 +0200)]
usbtty: avoid potential NULL pointer dereference

If current_urb is NULL it should not be dereferenced.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoyaffs2: remove redundant condition
xypron.glpk@gmx.de [Sat, 15 Apr 2017 11:28:13 +0000 (13:28 +0200)]
yaffs2: remove redundant condition

If !parent, the changed line is not reached.
So there is no need to check the value again.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agotools/env: avoid memory leak in fw_setenv
xypron.glpk@gmx.de [Sat, 15 Apr 2017 11:05:40 +0000 (13:05 +0200)]
tools/env: avoid memory leak in fw_setenv

If realloc fails we should release the old buffer.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoarm: omap-common: add missing va_end()
xypron.glpk@gmx.de [Sat, 15 Apr 2017 10:29:20 +0000 (12:29 +0200)]
arm: omap-common: add missing va_end()

Each call of va_start must be matched by a call of va_end.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agotravis-ci: Switch over to Linaro gcc-6.3.1 toolchains for ARM
Tom Rini [Fri, 14 Apr 2017 23:47:51 +0000 (19:47 -0400)]
travis-ci: Switch over to Linaro gcc-6.3.1 toolchains for ARM

Linaro provides a number of pre-built GCC toolchains for both 32 and
64bit ARM.  Switch to their 2017.02 release of gcc-6.3.1 for both.

Cc: Koen Kooi <koen.kooi@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agobuildman: Allow 'gnueabihf' toolchains for ARM
Tom Rini [Fri, 14 Apr 2017 23:47:50 +0000 (19:47 -0400)]
buildman: Allow 'gnueabihf' toolchains for ARM

Many toolchains for ARM use the 'gnueabihf' suffix rather than just
'gnueabi', so allow these to be used, but with a lower priority than
'gnueabi' ones.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agosysreset: psci: support system reset in a generic way with PSCI
Masahiro Yamada [Fri, 14 Apr 2017 02:10:24 +0000 (11:10 +0900)]
sysreset: psci: support system reset in a generic way with PSCI

If the system is running PSCI firmware, the System Reset function
(func ID: 0x80000009) is supposed to be handled by PSCI, that is,
the SoC/board specific reset implementation should be moved to PSCI.
U-Boot should call the PSCI service according to the arm-smccc
manner.

The arm-smccc is supported on ARMv7 or later.  Especially, ARMv8
generation SoCs are likely to run ARM Trusted Firmware BL31.  In
this case, U-Boot is a non-secure world boot loader, so it should
not be able to reset the system directly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: adjust arm-smccc code for use in U-Boot
Masahiro Yamada [Fri, 14 Apr 2017 02:10:23 +0000 (11:10 +0900)]
ARM: adjust arm-smccc code for use in U-Boot

Adjust ARM SMC Calling Convention code for U-Boot:
  - Replace the license block with SPDX
  - Change path to asm-offsets.h
  - Define UNWIND() as no-op
  - Add Kconfig entry
  - Add asm-offsets

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: import arm-smccc code from Linux 4.11-rc6
Masahiro Yamada [Fri, 14 Apr 2017 02:10:22 +0000 (11:10 +0900)]
ARM: import arm-smccc code from Linux 4.11-rc6

Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
The files have been copied as follows:

[Linux]                           [U-Boot]
arch/arm/kernel/smccc-call.S   -> arch/arm/cpu/armv7/smccc-call.S
arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S
arch/arm/include/asm/opcodes*  -> arch/arm/include/asm/opcodes*
include/linux/arm-smccc.h      -> include/linux/arm-smccc.h

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoblackfin: ibf-dsp561: remove orphan Blackfin board
Masahiro Yamada [Fri, 14 Apr 2017 02:05:48 +0000 (11:05 +0900)]
blackfin: ibf-dsp561: remove orphan Blackfin board

This is a Blackfin board that commit ea3310e8aafa ("Blackfin:
Remove") missed to remove.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agodrivers: remove Blackfin specific drivers
Masahiro Yamada [Fri, 14 Apr 2017 01:55:00 +0000 (10:55 +0900)]
drivers: remove Blackfin specific drivers

These drivers have no user since commit ea3310e8aafa ("Blackfin:
Remove").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
7 years agocmd: remove Blackfin specific commands
Masahiro Yamada [Fri, 14 Apr 2017 01:54:59 +0000 (10:54 +0900)]
cmd: remove Blackfin specific commands

These commands have no user since commit ea3310e8aafa ("Blackfin:
Remove").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agotools: moveconfig: remove GCC prefix of obsolete architecture
Masahiro Yamada [Fri, 14 Apr 2017 01:53:56 +0000 (10:53 +0900)]
tools: moveconfig: remove GCC prefix of obsolete architecture

Recently, U-Boot removed support for these architectures.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agocramfs: basic symlink support
Tyler Hall [Wed, 12 Apr 2017 20:29:17 +0000 (16:29 -0400)]
cramfs: basic symlink support

Handle symlinks to files in the current directory. Other cases could be
handled with additional code, but this is a start.

Add explicit errors for absolute paths and links found in the middle of
a path (directories). Other cases like '..' or '.' will result with the
file not being found as when those path components are explicitly
provided.

Add a helper to decompress a null-terminated link name which is shared
with cramfs_list_inode.

Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
7 years agocramfs: block pointers are 32 bits
Tyler Hall [Wed, 12 Apr 2017 20:29:16 +0000 (16:29 -0400)]
cramfs: block pointers are 32 bits

Using a variably-sized type is incorrect here since we're reading a
fixed file format. Fixes cramfs on 64-bit platforms.

Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
7 years agocmd: cramfs: use map_sysmem for sandbox support
Tyler Hall [Wed, 12 Apr 2017 20:29:15 +0000 (16:29 -0400)]
cmd: cramfs: use map_sysmem for sandbox support

As with most other commands, this needs to factor in the sysmem offset
in the sandbox or it will try to dereference the simulated physical
address directly.

Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
7 years agox86: config: Enable dhrystone command for link
Simon Glass [Sun, 19 Mar 2017 18:59:22 +0000 (12:59 -0600)]
x86: config: Enable dhrystone command for link

Enable this command so we can get an approximate performance measurement.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7 years agox86: Display the SPL banner only once
Simon Glass [Sun, 19 Mar 2017 18:59:21 +0000 (12:59 -0600)]
x86: Display the SPL banner only once

At present on a cold reboot we must reset the CPU to get it to full speed.
With 64-bit U-Boot this happens in SPL. At present we print the banner
before doing this, the end result being that we print the banner twice.
Print the banner a little later (after the CPU is ready) to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
7 years agox86: Drop leading spaces in cpu_x86_get_desc()
Simon Glass [Sun, 19 Mar 2017 18:59:20 +0000 (12:59 -0600)]
x86: Drop leading spaces in cpu_x86_get_desc()

The Intel CPU name can have leading spaces. Remove them since they are not
useful.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7 years agosunxi: Add maintainer of the NanoPi NEO Air
Jelle van der Waa [Fri, 3 Mar 2017 20:25:10 +0000 (21:25 +0100)]
sunxi: Add maintainer of the NanoPi NEO Air

Add myself as maintainer of the NanoPi NEO Air board.

Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agocmd: ubi: remove unnecessary logical constraint
xypron.glpk@gmx.de [Sat, 15 Apr 2017 14:25:25 +0000 (16:25 +0200)]
cmd: ubi: remove unnecessary logical constraint

A size_t variable can never be negative.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
7 years agoPrepare v2017.05-rc2 v2017.05-rc2
Tom Rini [Mon, 17 Apr 2017 22:16:49 +0000 (18:16 -0400)]
Prepare v2017.05-rc2

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agopowerpc/board/t1024rdb: enable board-level reset when issuing reset command
Shengzhou Liu [Mon, 10 Apr 2017 08:00:08 +0000 (16:00 +0800)]
powerpc/board/t1024rdb: enable board-level reset when issuing reset command

As board-specific reset logic, it needs to issue reset signal
via CPLD when issuing 'reset' command in u-boot, this patch
solves the issue of reset command not working on T1024RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agopowerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram
Ruchika Gupta [Thu, 2 Mar 2017 08:42:41 +0000 (14:12 +0530)]
powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

For E6500 cores, L2 cache has been used as init_ram. L1 cache is a
write through cache on E6500.If lines are not locked in both L1 and
L2 caches, crashes are observed during secure boot. This patch locks/
unlocks both L1 and L2 cache to prevent the crash.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQ
Yangbo Lu [Mon, 10 Apr 2017 07:04:11 +0000 (15:04 +0800)]
armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQ

Current sysclk fixing would fix all clocks with 'fixed-clock' compatible.
This patch is to fix sysclk by path to avoid any incorrect fixing.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups
Ashish kumar [Fri, 7 Apr 2017 06:10:32 +0000 (11:40 +0530)]
armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups

Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls2080a: Add serdes2 protocol 0x51 support
Santan Kumar [Wed, 5 Apr 2017 09:04:32 +0000 (14:34 +0530)]
armv8: ls2080a: Add serdes2 protocol 0x51 support

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoC
Shengzhou Liu [Thu, 23 Mar 2017 10:14:40 +0000 (18:14 +0800)]
arm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoC

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1046aqds: enable ppa in default config
tang yuantian [Fri, 10 Mar 2017 06:49:25 +0000 (14:49 +0800)]
armv8: ls1046aqds: enable ppa in default config

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv7: ls1021a: Drop macro CONFIG_LS102XA
York Sun [Mon, 27 Mar 2017 18:41:03 +0000 (11:41 -0700)]
armv7: ls1021a: Drop macro CONFIG_LS102XA

Use CONFIG_ARCH_LS1021A instead.

Signed-off-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1043a: Drop macro CONFIG_LS1043A
York Sun [Mon, 27 Mar 2017 18:41:02 +0000 (11:41 -0700)]
armv8: ls1043a: Drop macro CONFIG_LS1043A

Use CONFIG_ARCH_LS1043A instead.

Signed-off-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls2080a: Drop macro CONFIG_LS2080A
York Sun [Mon, 27 Mar 2017 18:41:01 +0000 (11:41 -0700)]
armv8: ls2080a: Drop macro CONFIG_LS2080A

Use CONFIG_ARCH_LS2080A instead.

Signed-off-by: York Sun <york.sun@nxp.com>
7 years agoarm: ls1046ardb: Add SD secure boot target
Ruchika Gupta [Mon, 17 Apr 2017 12:37:19 +0000 (18:07 +0530)]
arm: ls1046ardb: Add SD secure boot target

- Add SD secure boot target for ls1046ardb.
- Change the u-boot size defined by a macro for copying the main
  U-Boot by SPL to also include the u-boot Secure Boot header size
  as header is appended to u-boot image. So header will also be
  copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
  (128K) where 32K are reserved for use by boot ROM and 6K for the
  header.
- Reduce the size of CAAM driver for SPL Blobification functions
  and descriptors, that are not required at the time of SPL are
  disabled. Further error code conversion to strings is disabled
  for SPL build.

Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarm: ls1043ardb: Add NAND secure boot target
Ruchika Gupta [Mon, 17 Apr 2017 12:37:18 +0000 (18:07 +0530)]
arm: ls1043ardb: Add NAND secure boot target

Add NAND secure boot target for ls1043ardb.

- Change the u-boot size defined by a macro for copying the main
  U-Boot by SPL to also include the u-boot Secure Boot header size as
  header is appended to u-boot image. So header will also be copied
  from SD to DDR.
- MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript
  from NAND to DDR. Offsets for Bootscript on NAND and DDR have been
  also defined.

Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>