2 ******************************************************************************
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3 * @file stm32l1xx_hal_dma.h
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4 * @author MCD Application Team
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5 * @brief Header file of DMA HAL module.
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6 ******************************************************************************
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9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
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10 * All rights reserved.</center></h2>
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12 * This software component is licensed by ST under BSD 3-Clause license,
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13 * the "License"; You may not use this file except in compliance with the
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14 * License. You may obtain a copy of the License at:
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15 * opensource.org/licenses/BSD-3-Clause
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17 ******************************************************************************
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20 /* Define to prevent recursive inclusion -------------------------------------*/
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21 #ifndef STM32L1xx_HAL_DMA_H
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22 #define STM32L1xx_HAL_DMA_H
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28 /* Includes ------------------------------------------------------------------*/
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29 #include "stm32l1xx_hal_def.h"
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31 /** @addtogroup STM32L1xx_HAL_Driver
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39 /* Exported types ------------------------------------------------------------*/
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40 /** @defgroup DMA_Exported_Types DMA Exported Types
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45 * @brief DMA Configuration Structure definition
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49 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
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50 from memory to memory or from peripheral to memory.
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51 This parameter can be a value of @ref DMA_Data_transfer_direction */
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53 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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54 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
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56 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
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57 This parameter can be a value of @ref DMA_Memory_incremented_mode */
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59 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
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60 This parameter can be a value of @ref DMA_Peripheral_data_size */
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62 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
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63 This parameter can be a value of @ref DMA_Memory_data_size */
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65 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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66 This parameter can be a value of @ref DMA_mode
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67 @note The circular buffer mode cannot be used if the memory-to-memory
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68 data transfer is configured on the selected Channel */
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70 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
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71 This parameter can be a value of @ref DMA_Priority_level */
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75 * @brief HAL DMA State structures definition
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79 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
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80 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
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81 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
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82 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
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83 }HAL_DMA_StateTypeDef;
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86 * @brief HAL DMA Error Code structure definition
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90 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
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91 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
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92 }HAL_DMA_LevelCompleteTypeDef;
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96 * @brief HAL DMA Callback ID structure definition
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100 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
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101 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
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102 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
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103 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
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104 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
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105 }HAL_DMA_CallbackIDTypeDef;
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108 * @brief DMA handle Structure definition
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110 typedef struct __DMA_HandleTypeDef
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112 DMA_Channel_TypeDef *Instance; /*!< Register base address */
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114 DMA_InitTypeDef Init; /*!< DMA communication parameters */
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116 HAL_LockTypeDef Lock; /*!< DMA locking object */
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118 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
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120 void *Parent; /*!< Parent object state */
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122 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
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124 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
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126 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
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128 void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
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130 __IO uint32_t ErrorCode; /*!< DMA Error code */
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132 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
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134 uint32_t ChannelIndex; /*!< DMA Channel Index */
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136 }DMA_HandleTypeDef;
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142 /* Exported constants --------------------------------------------------------*/
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144 /** @defgroup DMA_Exported_Constants DMA Exported Constants
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148 /** @defgroup DMA_Error_Code DMA Error Code
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151 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
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152 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
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153 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
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154 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
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155 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
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161 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
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164 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
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165 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
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166 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
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171 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
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174 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
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175 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
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180 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
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183 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
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184 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
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189 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
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192 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
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193 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
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194 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
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199 /** @defgroup DMA_Memory_data_size DMA Memory data size
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202 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
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203 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
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204 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
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209 /** @defgroup DMA_mode DMA mode
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212 #define DMA_NORMAL 0x00000000U /*!< Normal mode */
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213 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
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218 /** @defgroup DMA_Priority_level DMA Priority level
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221 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
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222 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
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223 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
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224 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
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230 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
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233 #define DMA_IT_TC DMA_CCR_TCIE
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234 #define DMA_IT_HT DMA_CCR_HTIE
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235 #define DMA_IT_TE DMA_CCR_TEIE
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240 /** @defgroup DMA_flag_definitions DMA flag definitions
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243 #define DMA_FLAG_GL1 DMA_ISR_GIF1
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244 #define DMA_FLAG_TC1 DMA_ISR_TCIF1
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245 #define DMA_FLAG_HT1 DMA_ISR_HTIF1
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246 #define DMA_FLAG_TE1 DMA_ISR_TEIF1
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247 #define DMA_FLAG_GL2 DMA_ISR_GIF2
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248 #define DMA_FLAG_TC2 DMA_ISR_TCIF2
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249 #define DMA_FLAG_HT2 DMA_ISR_HTIF2
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250 #define DMA_FLAG_TE2 DMA_ISR_TEIF2
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251 #define DMA_FLAG_GL3 DMA_ISR_GIF3
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252 #define DMA_FLAG_TC3 DMA_ISR_TCIF3
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253 #define DMA_FLAG_HT3 DMA_ISR_HTIF3
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254 #define DMA_FLAG_TE3 DMA_ISR_TEIF3
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255 #define DMA_FLAG_GL4 DMA_ISR_GIF4
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256 #define DMA_FLAG_TC4 DMA_ISR_TCIF4
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257 #define DMA_FLAG_HT4 DMA_ISR_HTIF4
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258 #define DMA_FLAG_TE4 DMA_ISR_TEIF4
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259 #define DMA_FLAG_GL5 DMA_ISR_GIF5
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260 #define DMA_FLAG_TC5 DMA_ISR_TCIF5
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261 #define DMA_FLAG_HT5 DMA_ISR_HTIF5
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262 #define DMA_FLAG_TE5 DMA_ISR_TEIF5
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263 #define DMA_FLAG_GL6 DMA_ISR_GIF6
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264 #define DMA_FLAG_TC6 DMA_ISR_TCIF6
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265 #define DMA_FLAG_HT6 DMA_ISR_HTIF6
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266 #define DMA_FLAG_TE6 DMA_ISR_TEIF6
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267 #define DMA_FLAG_GL7 DMA_ISR_GIF7
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268 #define DMA_FLAG_TC7 DMA_ISR_TCIF7
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269 #define DMA_FLAG_HT7 DMA_ISR_HTIF7
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270 #define DMA_FLAG_TE7 DMA_ISR_TEIF7
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279 /* Exported macros -----------------------------------------------------------*/
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280 /** @defgroup DMA_Exported_Macros DMA Exported Macros
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284 /** @brief Reset DMA handle state.
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285 * @param __HANDLE__ DMA handle
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288 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
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291 * @brief Enable the specified DMA Channel.
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292 * @param __HANDLE__ DMA handle
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295 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
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298 * @brief Disable the specified DMA Channel.
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299 * @param __HANDLE__ DMA handle
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302 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
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305 /* Interrupt & Flag management */
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306 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
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307 defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
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308 defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
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311 * @brief Return the current DMA Channel transfer complete flag.
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312 * @param __HANDLE__ DMA handle
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313 * @retval The specified transfer complete flag index.
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316 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
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317 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
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318 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
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319 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
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320 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
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321 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
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322 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
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323 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
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324 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
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325 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
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326 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
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327 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
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331 * @brief Return the current DMA Channel half transfer complete flag.
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332 * @param __HANDLE__ DMA handle
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333 * @retval The specified half transfer complete flag index.
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335 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
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336 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
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337 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
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338 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
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339 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
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340 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
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341 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
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342 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
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343 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
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344 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
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345 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
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346 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
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350 * @brief Return the current DMA Channel transfer error flag.
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351 * @param __HANDLE__ DMA handle
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352 * @retval The specified transfer error flag index.
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354 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
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355 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
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356 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
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357 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
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358 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
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359 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
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360 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
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361 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
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362 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
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363 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
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364 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
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365 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
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369 * @brief Return the current DMA Channel Global interrupt flag.
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370 * @param __HANDLE__ DMA handle
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371 * @retval The specified transfer error flag index.
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373 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
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374 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
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375 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
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376 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
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377 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
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378 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
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379 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
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380 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
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381 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
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382 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
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383 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
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384 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
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388 * @brief Get the DMA Channel pending flags.
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389 * @param __HANDLE__ DMA handle
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390 * @param __FLAG__ Get the specified flag.
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391 * This parameter can be any combination of the following values:
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392 * @arg DMA_FLAG_TCx: Transfer complete flag
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393 * @arg DMA_FLAG_HTx: Half transfer complete flag
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394 * @arg DMA_FLAG_TEx: Transfer error flag
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395 * @arg DMA_FLAG_GLx: Global interrupt flag
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396 * Where x can be from 1 to 7 to select the DMA Channel x flag.
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397 * @retval The state of FLAG (SET or RESET).
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399 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
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400 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
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403 * @brief Clear the DMA Channel pending flags.
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404 * @param __HANDLE__ DMA handle
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405 * @param __FLAG__ specifies the flag to clear.
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406 * This parameter can be any combination of the following values:
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407 * @arg DMA_FLAG_TCx: Transfer complete flag
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408 * @arg DMA_FLAG_HTx: Half transfer complete flag
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409 * @arg DMA_FLAG_TEx: Transfer error flag
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410 * @arg DMA_FLAG_GLx: Global interrupt flag
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411 * Where x can be from 1 to 7 to select the DMA Channel x flag.
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414 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
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415 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
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419 * @brief Return the current DMA Channel transfer complete flag.
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420 * @param __HANDLE__ DMA handle
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421 * @retval The specified transfer complete flag index.
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424 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
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425 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
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426 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
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427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
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428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
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429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
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430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
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434 * @brief Return the current DMA Channel half transfer complete flag.
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435 * @param __HANDLE__ DMA handle
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436 * @retval The specified half transfer complete flag index.
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438 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
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439 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
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440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
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441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
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442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
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443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
\r
444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
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448 * @brief Return the current DMA Channel transfer error flag.
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449 * @param __HANDLE__ DMA handle
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450 * @retval The specified transfer error flag index.
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452 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
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453 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
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454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
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455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
\r
456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
\r
457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
\r
458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
\r
462 * @brief Return the current DMA Channel Global interrupt flag.
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463 * @param __HANDLE__ DMA handle
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464 * @retval The specified transfer error flag index.
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466 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
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467 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
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468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
\r
469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
\r
470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
\r
471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
\r
472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
\r
476 * @brief Get the DMA Channel pending flags.
\r
477 * @param __HANDLE__ DMA handle
\r
478 * @param __FLAG__ Get the specified flag.
\r
479 * This parameter can be any combination of the following values:
\r
480 * @arg DMA_FLAG_TCIFx: Transfer complete flag
\r
481 * @arg DMA_FLAG_HTIFx: Half transfer complete flag
\r
482 * @arg DMA_FLAG_TEIFx: Transfer error flag
\r
483 * @arg DMA_ISR_GIFx: Global interrupt flag
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484 * Where x can be from 1 to 7 to select the DMA Channel x flag.
\r
485 * @retval The state of FLAG (SET or RESET).
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487 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
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490 * @brief Clear the DMA Channel pending flags.
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491 * @param __HANDLE__ DMA handle
\r
492 * @param __FLAG__ specifies the flag to clear.
\r
493 * This parameter can be any combination of the following values:
\r
494 * @arg DMA_FLAG_TCx: Transfer complete flag
\r
495 * @arg DMA_FLAG_HTx: Half transfer complete flag
\r
496 * @arg DMA_FLAG_TEx: Transfer error flag
\r
497 * @arg DMA_FLAG_GLx: Global interrupt flag
\r
498 * Where x can be from 1 to 7 to select the DMA Channel x flag.
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501 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
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503 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
506 * @brief Enable the specified DMA Channel interrupts.
\r
507 * @param __HANDLE__ DMA handle
\r
508 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
\r
509 * This parameter can be any combination of the following values:
\r
510 * @arg DMA_IT_TC: Transfer complete interrupt mask
\r
511 * @arg DMA_IT_HT: Half transfer complete interrupt mask
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512 * @arg DMA_IT_TE: Transfer error interrupt mask
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515 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
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518 * @brief Disable the specified DMA Channel interrupts.
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519 * @param __HANDLE__ DMA handle
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520 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
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521 * This parameter can be any combination of the following values:
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522 * @arg DMA_IT_TC: Transfer complete interrupt mask
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523 * @arg DMA_IT_HT: Half transfer complete interrupt mask
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524 * @arg DMA_IT_TE: Transfer error interrupt mask
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527 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
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530 * @brief Check whether the specified DMA Channel interrupt is enabled or not.
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531 * @param __HANDLE__ DMA handle
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532 * @param __INTERRUPT__ specifies the DMA interrupt source to check.
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533 * This parameter can be one of the following values:
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534 * @arg DMA_IT_TC: Transfer complete interrupt mask
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535 * @arg DMA_IT_HT: Half transfer complete interrupt mask
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536 * @arg DMA_IT_TE: Transfer error interrupt mask
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537 * @retval The state of DMA_IT (SET or RESET).
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539 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
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542 * @brief Return the number of remaining data units in the current DMA Channel transfer.
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543 * @param __HANDLE__ DMA handle
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544 * @retval The number of remaining data units in the current DMA Channel transfer.
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546 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
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552 /* Exported functions --------------------------------------------------------*/
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554 /** @addtogroup DMA_Exported_Functions
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558 /** @addtogroup DMA_Exported_Functions_Group1
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561 /* Initialization and de-initialization functions *****************************/
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562 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
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563 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
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568 /** @addtogroup DMA_Exported_Functions_Group2
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571 /* IO operation functions *****************************************************/
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572 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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573 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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574 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
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575 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
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576 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
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577 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
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578 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
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579 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
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585 /** @addtogroup DMA_Exported_Functions_Group3
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588 /* Peripheral State and Error functions ***************************************/
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589 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
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590 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
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599 /* Private macros ------------------------------------------------------------*/
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600 /** @defgroup DMA_Private_Macros DMA Private Macros
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604 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
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605 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
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606 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
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608 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
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610 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
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611 ((STATE) == DMA_PINC_DISABLE))
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613 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
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614 ((STATE) == DMA_MINC_DISABLE))
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616 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
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617 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
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618 ((SIZE) == DMA_PDATAALIGN_WORD))
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620 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
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621 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
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622 ((SIZE) == DMA_MDATAALIGN_WORD ))
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624 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
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625 ((MODE) == DMA_CIRCULAR))
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627 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
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628 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
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629 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
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630 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
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636 /* Private functions ---------------------------------------------------------*/
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650 #endif /* STM32L1xx_HAL_DMA_H */
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652 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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