3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h>
19 #include <asm/arch/mxc_hdmi.h>
20 #include <asm/arch/crm_regs.h>
22 #define VDDPU_MASK (0x1f << 9)
40 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
41 u32 reg = readl(&anatop->digprog_sololite);
42 u32 type = ((reg >> 16) & 0xff);
44 if (type != MXC_CPU_MX6SL) {
45 reg = readl(&anatop->digprog);
46 type = ((reg >> 16) & 0xff);
47 if (type == MXC_CPU_MX6DL) {
48 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
49 u32 cfg = readl(&scu->config) & 3;
52 type = MXC_CPU_MX6SOLO;
55 reg &= 0xff; /* mx6 silicon revision */
56 return (type << 12) | (reg + 0x10);
59 #ifdef CONFIG_REVISION_TAG
60 u32 __weak get_board_rev(void)
62 u32 cpurev = get_cpu_rev();
63 u32 type = ((cpurev >> 12) & 0xff);
64 if (type == MXC_CPU_MX6SOLO)
65 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
73 struct aipstz_regs *aips1, *aips2;
75 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
76 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
79 * Set all MPROTx to be non-bufferable, trusted for R/W,
80 * not forced to user-mode.
82 writel(0x77777777, &aips1->mprot0);
83 writel(0x77777777, &aips1->mprot1);
84 writel(0x77777777, &aips2->mprot0);
85 writel(0x77777777, &aips2->mprot1);
88 * Set all OPACRx to be non-bufferable, not require
89 * supervisor privilege level for access,allow for
90 * write access and untrusted master access.
92 writel(0x00000000, &aips1->opacr0);
93 writel(0x00000000, &aips1->opacr1);
94 writel(0x00000000, &aips1->opacr2);
95 writel(0x00000000, &aips1->opacr3);
96 writel(0x00000000, &aips1->opacr4);
97 writel(0x00000000, &aips2->opacr0);
98 writel(0x00000000, &aips2->opacr1);
99 writel(0x00000000, &aips2->opacr2);
100 writel(0x00000000, &aips2->opacr3);
101 writel(0x00000000, &aips2->opacr4);
104 static void clear_ldo_ramp(void)
106 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
109 /* ROM may modify LDO ramp up time according to fuse setting, so in
110 * order to be in the safe side we neeed to reset these settings to
111 * match the reset value: 0'b00
113 reg = readl(&anatop->ana_misc2);
114 reg &= ~(0x3f << 24);
115 writel(reg, &anatop->ana_misc2);
121 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
122 * them to the specified millivolt level.
123 * Possible values are from 0.725V to 1.450V in steps of
126 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
128 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
129 u32 val, step, old, reg = readl(&anatop->reg_core);
133 val = 0x00; /* Power gated off */
135 val = 0x1F; /* Power FET switched full on. No regulation */
137 val = (mv - 700) / 25;
155 old = (reg & (0x1F << shift)) >> shift;
156 step = abs(val - old);
160 reg = (reg & ~(0x1F << shift)) | (val << shift);
161 writel(reg, &anatop->reg_core);
164 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
172 static void imx_set_wdog_powerdown(bool enable)
174 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
175 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
177 /* Write to the PDE (Power Down Enable) bit */
178 writew(enable, &wdog1->wmcr);
179 writew(enable, &wdog2->wmcr);
182 static void imx_set_vddpu_power_down(void)
184 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
185 struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
190 * Disable the brown out detection since we are going to be
193 reg = readl(&anatop->ana_misc2);
194 reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
195 writel(reg, &anatop->ana_misc2);
197 /* need to power down xPU in GPC before turning off PU LDO */
198 reg = readl(&gpc->gpu_ctrl);
199 writel(reg | 0x1, &gpc->gpu_ctrl);
201 reg = readl(&gpc->ctrl);
202 writel(reg | 0x1, &gpc->ctrl);
203 while (readl(&gpc->ctrl) & 0x1)
206 /* Mask the ANATOP brown out interrupt in the GPC. */
207 reg = readl(&gpc->imr4);
209 writel(reg, &gpc->imr4);
212 writel(VDDPU_MASK, &anatop->reg_core_clr);
214 /* Clear the BO interrupt in the ANATOP. */
215 reg = readl(&anatop->ana_misc1);
217 writel(reg, &anatop->ana_misc1);
220 int arch_cpu_init(void)
224 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
225 imx_set_vddpu_power_down();
227 #ifdef CONFIG_APBH_DMA
235 int board_postclk_init(void)
237 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
242 #ifndef CONFIG_SYS_DCACHE_OFF
243 void enable_caches(void)
245 /* Avoid random hang when download by usb */
246 invalidate_dcache_all();
247 /* Enable D-cache. I-cache is already enabled in start.S */
252 #if defined(CONFIG_FEC_MXC)
253 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
255 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
256 struct fuse_bank *bank = &ocotp->bank[4];
257 struct fuse_bank4_regs *fuse =
258 (struct fuse_bank4_regs *)bank->fuse_regs;
260 u32 value = readl(&fuse->mac_addr_high);
261 mac[0] = (value >> 8);
264 value = readl(&fuse->mac_addr_low);
265 mac[2] = value >> 24 ;
266 mac[3] = value >> 16 ;
267 mac[4] = value >> 8 ;
273 void boot_mode_apply(unsigned cfg_val)
276 struct src *psrc = (struct src *)SRC_BASE_ADDR;
277 writel(cfg_val, &psrc->gpr9);
278 reg = readl(&psrc->gpr10);
283 writel(reg, &psrc->gpr10);
286 * cfg_val will be used for
287 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
288 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
289 * to SBMR1, which will determine the boot device.
291 const struct boot_mode soc_boot_modes[] = {
292 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
293 /* reserved value should start rom usb */
294 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
295 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
296 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
297 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
298 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
299 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
300 /* 4 bit bus width */
301 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
302 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
303 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
304 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
310 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
311 int is_6q = is_cpu_type(MXC_CPU_MX6Q);
315 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
316 * to make sure PFD is working right, otherwise, PFDs may
317 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
318 * workaround in ROM code, as bus clock need it
321 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
322 ANATOP_PFD_CLKGATE_MASK(1) |
323 ANATOP_PFD_CLKGATE_MASK(2) |
324 ANATOP_PFD_CLKGATE_MASK(3);
325 mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
326 ANATOP_PFD_CLKGATE_MASK(1) |
327 ANATOP_PFD_CLKGATE_MASK(3);
330 * Don't reset PFD2 on DL/S
333 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
334 writel(mask480, &anatop->pfd_480_set);
335 writel(mask528, &anatop->pfd_528_set);
336 writel(mask480, &anatop->pfd_480_clr);
337 writel(mask528, &anatop->pfd_528_clr);
340 #ifdef CONFIG_IMX_HDMI
341 void imx_enable_hdmi_phy(void)
343 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
345 reg = readb(&hdmi->phy_conf0);
346 reg |= HDMI_PHY_CONF0_PDZ_MASK;
347 writeb(reg, &hdmi->phy_conf0);
349 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
350 writeb(reg, &hdmi->phy_conf0);
352 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
353 writeb(reg, &hdmi->phy_conf0);
354 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
357 void imx_setup_hdmi(void)
359 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
360 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
363 /* Turn on HDMI PHY clock */
364 reg = readl(&mxc_ccm->CCGR2);
365 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
366 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
367 writel(reg, &mxc_ccm->CCGR2);
368 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
369 reg = readl(&mxc_ccm->chsccdr);
370 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
371 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
372 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
373 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
374 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
375 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
376 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
377 writel(reg, &mxc_ccm->chsccdr);