]> git.sur5r.net Git - u-boot/commitdiff
Merge branch 'master' of git://git.denx.de/u-boot-arm
authorTom Rini <trini@ti.com>
Fri, 10 Jan 2014 15:56:00 +0000 (10:56 -0500)
committerTom Rini <trini@ti.com>
Fri, 10 Jan 2014 15:56:00 +0000 (10:56 -0500)
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.

Conflicts:
include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
15 files changed:
1  2 
Makefile
arch/arm/lib/bootm.c
boards.cfg
common/board_f.c
common/fdt_support.c
include/configs/arndale.h
include/configs/balloon3.h
include/configs/exynos5-dt.h
include/configs/lp8x4x.h
include/configs/palmld.h
include/configs/palmtc.h
include/configs/zipitz2.h
spl/Makefile
tools/Makefile
tools/mxsimage.c

diff --cc Makefile
index cbd45a7f178d75801661c586559ae2bb6ad6b774,dc5ba046164110bab85f41b15ef38b2d3da9952e..e6f6edbb3a6d459a121d6c8d284f5343bf05a0a2
+++ b/Makefile
@@@ -336,8 -356,9 +347,9 @@@ ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-
  ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin
  ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
  ifneq ($(CONFIG_SPL_TARGET),)
 -ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
 +ALL-$(CONFIG_SPL) += $(obj)$(CONFIG_SPL_TARGET:"%"=%)
  endif
+ ALL-$(CONFIG_REMAKE_ELF) += $(obj)u-boot.elf
  
  # enable combined SPL/u-boot/dtb rules for tegra
  ifneq ($(CONFIG_TEGRA),)
@@@ -497,10 -523,24 +512,22 @@@ $(obj)u-boot-img.bin: $(obj)spl/u-boot-
  # at the start padded up to the start of the SPL image. And then concat
  # the SPL image to the end.
  $(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 -              tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_UBOOT_PAD_TO) \
 -                      of=$(obj)u-boot-pad.img 2>/dev/null
 -              dd if=$(obj)u-boot.img of=$(obj)u-boot-pad.img \
 -                      conv=notrunc 2>/dev/null
 -              cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@
 +              $(OBJCOPY) -I binary -O binary --pad-to=$(CONFIG_UBOOT_PAD_TO) \
 +                       --gap-fill=0xff $(obj)u-boot.img $@
 +              cat $(obj)spl/u-boot-spl.bin >> $@
  
+ # Create a new ELF from a raw binary file.  This is useful for arm64
+ # where static relocation needs to be performed on the raw binary,
+ # but certain simulators only accept an ELF file (but don't do the
+ # relocation).
+ # FIXME refactor dts/Makefile to share target/arch detection
+ $(obj)u-boot.elf: $(obj)u-boot.bin
+       @$(OBJCOPY)  -B aarch64 -I binary -O elf64-littleaarch64 \
+               $< $(obj)u-boot-elf.o
+       @$(LD) $(obj)u-boot-elf.o -o $@ \
+               --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \
+               -Ttext=$(CONFIG_SYS_TEXT_BASE)
  ifeq ($(CONFIG_SANDBOX),y)
  GEN_UBOOT = \
                cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
Simple merge
diff --cc boards.cfg
Simple merge
index c2f47bc18892a2f381d24ea8b114833c0c96484d,d918e4bb16fe39dc8539163e8554c89999f8905e..aa70c3e57de67e5041225abd88b6080fa46ca692
@@@ -1008,8 -1004,18 +1003,19 @@@ void board_init_f(ulong boot_flags
        gd = &data;
  #endif
  
+       /*
+        * Clear global data before it is accessed at debug print
+        * in initcall_run_list. Otherwise the debug print probably
+        * get the wrong vaule of gd->have_console.
+        */
+ #if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
+               !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
+               !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
+       zero_global_data();
+ #endif
        gd->flags = boot_flags;
 +      gd->have_console = 0;
  
        if (initcall_run_list(init_sequence_f))
                hang();
Simple merge
Simple merge
Simple merge
index 0000000000000000000000000000000000000000,d684790f8e501be8d388cd59aef52bb68a504308..414db420dc30684ebc8d42614198a951fe195a52
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,290 +1,291 @@@
+ /*
+  * Copyright (C) 2013 Samsung Electronics
+  *
+  * Configuration settings for the SAMSUNG EXYNOS5 board.
+  *
+  * SPDX-License-Identifier:   GPL-2.0+
+  */
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
+ /* High Level Configuration Options */
+ #define CONFIG_SAMSUNG                        /* in a SAMSUNG core */
+ #define CONFIG_S5P                    /* S5P Family */
+ #define CONFIG_EXYNOS5                        /* which is in a Exynos5 Family */
+ #include <asm/arch/cpu.h>             /* get chip and board defs */
+ #define CONFIG_SYS_GENERIC_BOARD
+ #define CONFIG_ARCH_CPU_INIT
+ #define CONFIG_DISPLAY_CPUINFO
+ #define CONFIG_DISPLAY_BOARDINFO
+ #define CONFIG_BOARD_COMMON
+ #define CONFIG_ARCH_EARLY_INIT_R
+ #define CONFIG_EXYNOS_SPL
+ /* Enable fdt support for Exynos5250 */
+ #define CONFIG_OF_CONTROL
+ #define CONFIG_OF_SEPARATE
+ /* Allow tracing to be enabled */
+ #define CONFIG_TRACE
+ #define CONFIG_CMD_TRACE
+ #define CONFIG_TRACE_BUFFER_SIZE      (16 << 20)
+ #define CONFIG_TRACE_EARLY_SIZE               (8 << 20)
+ #define CONFIG_TRACE_EARLY
+ #define CONFIG_TRACE_EARLY_ADDR               0x50000000
+ /* Keep L2 Cache Disabled */
+ #define CONFIG_SYS_DCACHE_OFF
+ #define CONFIG_SYS_CACHELINE_SIZE     64
+ /* Enable ACE acceleration for SHA1 and SHA256 */
+ #define CONFIG_EXYNOS_ACE_SHA
+ #define CONFIG_SHA_HW_ACCEL
+ /* input clock of PLL: SMDK5250 has 24MHz input clock */
+ #define CONFIG_SYS_CLK_FREQ           24000000
+ #define CONFIG_SETUP_MEMORY_TAGS
+ #define CONFIG_CMDLINE_TAG
+ #define CONFIG_INITRD_TAG
+ #define CONFIG_CMDLINE_EDITING
+ /* Power Down Modes */
+ #define S5P_CHECK_SLEEP                       0x00000BAD
+ #define S5P_CHECK_DIDLE                       0xBAD00000
+ #define S5P_CHECK_LPA                 0xABAD0000
+ /* Offset for inform registers */
+ #define INFORM0_OFFSET                        0x800
+ #define INFORM1_OFFSET                        0x804
+ #define INFORM2_OFFSET                        0x808
+ #define INFORM3_OFFSET                        0x80c
+ /* Size of malloc() pool */
+ #define CONFIG_SYS_MALLOC_LEN         (CONFIG_ENV_SIZE + (4 << 20))
+ /* select serial console configuration */
+ #define CONFIG_BAUDRATE                       115200
+ #define EXYNOS5_DEFAULT_UART_OFFSET   0x010000
+ #define CONFIG_SILENT_CONSOLE
+ /* Enable keyboard */
+ #define CONFIG_CROS_EC                /* CROS_EC protocol */
+ #define CONFIG_CROS_EC_SPI            /* Support CROS_EC over SPI */
+ #define CONFIG_CROS_EC_I2C            /* Support CROS_EC over I2C */
+ #define CONFIG_CROS_EC_KEYB   /* CROS_EC keyboard input */
+ #define CONFIG_CMD_CROS_EC
+ #define CONFIG_KEYBOARD
+ /* Console configuration */
+ #define CONFIG_CONSOLE_MUX
+ #define CONFIG_SYS_CONSOLE_IS_IN_ENV
+ #define EXYNOS_DEVICE_SETTINGS \
+               "stdin=serial,cros-ec-keyb\0" \
+               "stdout=serial,lcd\0" \
+               "stderr=serial,lcd\0"
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+       EXYNOS_DEVICE_SETTINGS
+ /* SD/MMC configuration */
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_MMC
+ #define CONFIG_SDHCI
+ #define CONFIG_S5P_SDHCI
+ #define CONFIG_DWMMC
+ #define CONFIG_EXYNOS_DWMMC
+ #define CONFIG_SUPPORT_EMMC_BOOT
++#define CONFIG_BOUNCE_BUFFER
+ #define CONFIG_BOARD_EARLY_INIT_F
+ #define CONFIG_SKIP_LOWLEVEL_INIT
+ /* PWM */
+ #define CONFIG_PWM
+ /* allow to overwrite serial and ethaddr */
+ #define CONFIG_ENV_OVERWRITE
+ /* Command definition*/
+ #include <config_cmd_default.h>
+ #define CONFIG_CMD_PING
+ #define CONFIG_CMD_ELF
+ #define CONFIG_CMD_MMC
+ #define CONFIG_CMD_EXT2
+ #define CONFIG_CMD_FAT
+ #define CONFIG_CMD_NET
+ #define CONFIG_CMD_HASH
+ #define CONFIG_BOOTDELAY              3
+ #define CONFIG_ZERO_BOOTDELAY_CHECK
+ /* Thermal Management Unit */
+ #define CONFIG_EXYNOS_TMU
+ #define CONFIG_CMD_DTT
+ #define CONFIG_TMU_CMD_DTT
+ /* TPM */
+ #define CONFIG_TPM
+ #define CONFIG_CMD_TPM
+ #define CONFIG_TPM_TIS_I2C
+ #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
+ #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
+ /* MMC SPL */
+ #define CONFIG_SPL
+ #define COPY_BL2_FNPTR_ADDR   0x02020030
+ #define CONFIG_SPL_LIBCOMMON_SUPPORT
+ #define CONFIG_SPL_GPIO_SUPPORT
+ /* specific .lds file */
+ #define CONFIG_SPL_LDSCRIPT   "board/samsung/common/exynos-uboot-spl.lds"
+ #define CONFIG_SPL_MAX_FOOTPRINT      (14 * 1024)
+ /* Miscellaneous configurable options */
+ #define CONFIG_SYS_LONGHELP           /* undef to save memory */
+ #define CONFIG_SYS_HUSH_PARSER                /* use "hush" command parser    */
+ #define CONFIG_SYS_CBSIZE             256     /* Console I/O Buffer Size */
+ #define CONFIG_SYS_PBSIZE             384     /* Print Buffer Size */
+ #define CONFIG_SYS_MAXARGS            16      /* max number of command args */
+ #define CONFIG_DEFAULT_CONSOLE                "console=ttySAC1,115200n8\0"
+ /* Boot Argument Buffer Size */
+ #define CONFIG_SYS_BARGSIZE           CONFIG_SYS_CBSIZE
+ /* memtest works on */
+ #define CONFIG_SYS_MEMTEST_START      CONFIG_SYS_SDRAM_BASE
+ #define CONFIG_SYS_MEMTEST_END                (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+ #define CONFIG_SYS_LOAD_ADDR          (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+ #define CONFIG_RD_LVL
+ #define CONFIG_NR_DRAM_BANKS  8
+ #define SDRAM_BANK_SIZE               (256UL << 20UL) /* 256 MB */
+ #define PHYS_SDRAM_1          CONFIG_SYS_SDRAM_BASE
+ #define PHYS_SDRAM_1_SIZE     SDRAM_BANK_SIZE
+ #define PHYS_SDRAM_2          (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+ #define PHYS_SDRAM_2_SIZE     SDRAM_BANK_SIZE
+ #define PHYS_SDRAM_3          (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+ #define PHYS_SDRAM_3_SIZE     SDRAM_BANK_SIZE
+ #define PHYS_SDRAM_4          (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+ #define PHYS_SDRAM_4_SIZE     SDRAM_BANK_SIZE
+ #define PHYS_SDRAM_5          (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+ #define PHYS_SDRAM_5_SIZE     SDRAM_BANK_SIZE
+ #define PHYS_SDRAM_6          (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+ #define PHYS_SDRAM_6_SIZE     SDRAM_BANK_SIZE
+ #define PHYS_SDRAM_7          (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+ #define PHYS_SDRAM_7_SIZE     SDRAM_BANK_SIZE
+ #define PHYS_SDRAM_8          (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+ #define PHYS_SDRAM_8_SIZE     SDRAM_BANK_SIZE
+ #define CONFIG_SYS_MONITOR_BASE       0x00000000
+ /* FLASH and environment organization */
+ #define CONFIG_SYS_NO_FLASH
+ #undef CONFIG_CMD_IMLS
+ #define CONFIG_SYS_MMC_ENV_DEV                0
+ #define CONFIG_SECURE_BL1_ONLY
+ /* Secure FW size configuration */
+ #ifdef CONFIG_SECURE_BL1_ONLY
+ #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+ #else
+ #define CONFIG_SEC_FW_SIZE 0
+ #endif
+ /* Configuration of BL1, BL2, ENV Blocks on mmc */
+ #define CONFIG_RES_BLOCK_SIZE (512)
+ #define CONFIG_BL1_SIZE       (16 << 10) /*16 K reserved for BL1*/
+ #define CONFIG_BL2_SIZE       (512UL << 10UL) /* 512 KB */
+ #define CONFIG_ENV_SIZE       (16 << 10) /* 16 KB */
+ #define CONFIG_BL1_OFFSET     (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+ #define CONFIG_BL2_OFFSET     (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+ #define CONFIG_ENV_OFFSET     (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+ /* U-boot copy size from boot Media to DRAM.*/
+ #define BL2_START_OFFSET      (CONFIG_BL2_OFFSET/512)
+ #define BL2_SIZE_BLOC_COUNT   (CONFIG_BL2_SIZE/512)
+ #define CONFIG_SPI_BOOTING
+ #define EXYNOS_COPY_SPI_FNPTR_ADDR    0x02020058
+ #define SPI_FLASH_UBOOT_POS   (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_EFI_PARTITION
+ #define CONFIG_CMD_PART
+ #define CONFIG_PARTITION_UUIDS
+ /* I2C */
+ #define CONFIG_SYS_I2C_INIT_BOARD
+ #define CONFIG_SYS_I2C
+ #define CONFIG_CMD_I2C
+ #define CONFIG_SYS_I2C_S3C24X0_SPEED  100000          /* 100 Kbps */
+ #define CONFIG_SYS_I2C_S3C24X0
+ #define CONFIG_I2C_MULTI_BUS
+ #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
+ #define CONFIG_I2C_EDID
+ /* SPI */
+ #define CONFIG_ENV_IS_IN_SPI_FLASH
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_ENV_SPI_BASE   0x12D30000
+ #ifdef CONFIG_SPI_FLASH
+ #define CONFIG_EXYNOS_SPI
+ #define CONFIG_CMD_SF
+ #define CONFIG_CMD_SPI
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SF_DEFAULT_MODE                SPI_MODE_0
+ #define CONFIG_SF_DEFAULT_SPEED               50000000
+ #define EXYNOS5_SPI_NUM_CONTROLLERS   5
+ #define CONFIG_OF_SPI
+ #endif
+ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ #define CONFIG_ENV_SPI_MODE   SPI_MODE_0
+ #define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
+ #define CONFIG_ENV_SPI_BUS    1
+ #define CONFIG_ENV_SPI_MAX_HZ 50000000
+ #endif
+ /* PMIC */
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ /* Ethernet Controllor Driver */
+ #ifdef CONFIG_CMD_NET
+ #define CONFIG_SMC911X
+ #define CONFIG_SMC911X_BASE           0x5000000
+ #define CONFIG_SMC911X_16_BIT
+ #define CONFIG_ENV_SROM_BANK          1
+ #endif /*CONFIG_CMD_NET*/
+ /* Enable PXE Support */
+ #ifdef CONFIG_CMD_NET
+ #define CONFIG_CMD_PXE
+ #define CONFIG_MENU
+ #endif
+ /* Enable devicetree support */
+ #define CONFIG_OF_LIBFDT
+ /* SHA hashing */
+ #define CONFIG_CMD_HASH
+ #define CONFIG_HASH_VERIFY
+ #define CONFIG_SHA1
+ #define CONFIG_SHA256
+ /* Enable Time Command */
+ #define CONFIG_CMD_TIME
+ #define CONFIG_CMD_BOOTZ
+ #endif        /* __CONFIG_H */
Simple merge
Simple merge
Simple merge
Simple merge
diff --cc spl/Makefile
Simple merge
diff --cc tools/Makefile
Simple merge
Simple merge