1 #include "skeleton.dtsi"
4 model = "Atmel SAMA5D2 family SoC";
5 compatible = "atmel,sama5d2";
15 slow_xtal: slow_xtal {
16 compatible = "fixed-clock";
18 clock-frequency = <0>;
21 main_xtal: main_xtal {
22 compatible = "fixed-clock";
24 clock-frequency = <0>;
29 compatible = "simple-bus";
35 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
36 reg = <0x00400000 0x100000>;
37 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
38 clock-names = "ohci_clk", "hclk", "uhpck";
43 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
44 reg = <0x00500000 0x100000>;
45 clocks = <&utmi>, <&uhphs_clk>;
46 clock-names = "usb_clk", "ehci_clk";
50 sdmmc0: sdio-host@a0000000 {
51 compatible = "atmel,sama5d2-sdhci";
52 reg = <0xa0000000 0x300>;
53 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
54 clock-names = "hclock", "multclk", "baseclk";
58 sdmmc1: sdio-host@b0000000 {
59 compatible = "atmel,sama5d2-sdhci";
60 reg = <0xb0000000 0x300>;
61 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
62 clock-names = "hclock", "multclk", "baseclk";
67 compatible = "simple-bus";
73 compatible = "atmel,sama5d2-pmc", "syscon";
74 reg = <0xf0014000 0x160>;
77 #interrupt-cells = <1>;
81 compatible = "atmel,at91sam9x5-clk-main";
87 compatible = "atmel,sama5d3-clk-pll";
91 atmel,clk-input-range = <12000000 12000000>;
92 #atmel,pll-clk-output-range-cells = <4>;
93 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
98 compatible = "atmel,at91sam9x5-clk-plldiv";
103 audio_pll_frac: audiopll_fracck {
104 compatible = "atmel,sama5d2-clk-audio-pll-frac";
109 audio_pll_pad: audiopll_padck {
110 compatible = "atmel,sama5d2-clk-audio-pll-pad";
112 clocks = <&audio_pll_frac>;
115 audio_pll_pmc: audiopll_pmcck {
116 compatible = "atmel,sama5d2-clk-audio-pll-pmc";
118 clocks = <&audio_pll_frac>;
122 compatible = "atmel,at91sam9x5-clk-utmi";
129 compatible = "atmel,at91sam9x5-clk-master";
131 clocks = <&main>, <&plladiv>, <&utmi>;
132 atmel,clk-output-range = <124000000 166000000>;
133 atmel,clk-divisors = <1 2 4 3>;
139 compatible = "atmel,sama5d4-clk-h32mx";
145 compatible = "atmel,at91sam9x5-clk-usb";
147 clocks = <&plladiv>, <&utmi>;
151 compatible = "atmel,at91sam9x5-clk-programmable";
152 #address-cells = <1>;
154 interrupt-parent = <&pmc>;
155 clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
174 compatible = "atmel,at91rm9200-clk-system";
175 #address-cells = <1>;
228 compatible = "atmel,at91sam9x5-clk-peripheral";
229 #address-cells = <1>;
234 macb0_clk: macb0_clk@5 {
237 atmel,clk-output-range = <0 83000000>;
240 tdes_clk: tdes_clk@11 {
243 atmel,clk-output-range = <0 83000000>;
246 matrix1_clk: matrix1_clk@14 {
251 hsmc_clk: hsmc_clk@17 {
256 pioA_clk: pioA_clk@18 {
259 atmel,clk-output-range = <0 83000000>;
263 flx0_clk: flx0_clk@19 {
266 atmel,clk-output-range = <0 83000000>;
269 flx1_clk: flx1_clk@20 {
272 atmel,clk-output-range = <0 83000000>;
275 flx2_clk: flx2_clk@21 {
278 atmel,clk-output-range = <0 83000000>;
281 flx3_clk: flx3_clk@22 {
284 atmel,clk-output-range = <0 83000000>;
287 flx4_clk: flx4_clk@23 {
290 atmel,clk-output-range = <0 83000000>;
293 uart0_clk: uart0_clk@24 {
296 atmel,clk-output-range = <0 83000000>;
299 uart1_clk: uart1_clk@25 {
302 atmel,clk-output-range = <0 83000000>;
306 uart2_clk: uart2_clk@26 {
309 atmel,clk-output-range = <0 83000000>;
312 uart3_clk: uart3_clk@27 {
315 atmel,clk-output-range = <0 83000000>;
318 uart4_clk: uart4_clk@28 {
321 atmel,clk-output-range = <0 83000000>;
324 twi0_clk: twi0_clk@29 {
327 atmel,clk-output-range = <0 83000000>;
330 twi1_clk: twi1_clk@30 {
333 atmel,clk-output-range = <0 83000000>;
336 spi0_clk: spi0_clk@33 {
339 atmel,clk-output-range = <0 83000000>;
343 spi1_clk: spi1_clk@34 {
346 atmel,clk-output-range = <0 83000000>;
349 tcb0_clk: tcb0_clk@35 {
352 atmel,clk-output-range = <0 83000000>;
355 tcb1_clk: tcb1_clk@36 {
358 atmel,clk-output-range = <0 83000000>;
361 pwm_clk: pwm_clk@38 {
364 atmel,clk-output-range = <0 83000000>;
367 adc_clk: adc_clk@40 {
370 atmel,clk-output-range = <0 83000000>;
373 uhphs_clk: uhphs_clk@41 {
376 atmel,clk-output-range = <0 83000000>;
379 udphs_clk: udphs_clk@42 {
382 atmel,clk-output-range = <0 83000000>;
385 ssc0_clk: ssc0_clk@43 {
388 atmel,clk-output-range = <0 83000000>;
391 ssc1_clk: ssc1_clk@44 {
394 atmel,clk-output-range = <0 83000000>;
397 trng_clk: trng_clk@47 {
400 atmel,clk-output-range = <0 83000000>;
403 pdmic_clk: pdmic_clk@48 {
406 atmel,clk-output-range = <0 83000000>;
409 i2s0_clk: i2s0_clk@54 {
412 atmel,clk-output-range = <0 83000000>;
415 i2s1_clk: i2s1_clk@55 {
418 atmel,clk-output-range = <0 83000000>;
421 can0_clk: can0_clk@56 {
424 atmel,clk-output-range = <0 83000000>;
427 can1_clk: can1_clk@57 {
430 atmel,clk-output-range = <0 83000000>;
433 classd_clk: classd_clk@59 {
436 atmel,clk-output-range = <0 83000000>;
441 compatible = "atmel,at91sam9x5-clk-peripheral";
442 #address-cells = <1>;
447 dma0_clk: dma0_clk@6 {
452 dma1_clk: dma1_clk@7 {
462 aesb_clk: aesb_clk@10 {
467 sha_clk: sha_clk@12 {
472 mpddr_clk: mpddr_clk@13 {
477 matrix0_clk: matrix0_clk@15 {
482 sdmmc0_hclk: sdmmc0_hclk@31 {
488 sdmmc1_hclk: sdmmc1_hclk@32 {
494 lcdc_clk: lcdc_clk@45 {
499 isc_clk: isc_clk@46 {
504 qspi0_clk: qspi0_clk@52 {
509 qspi1_clk: qspi1_clk@53 {
516 compatible = "atmel,sama5d2-clk-generated";
517 #address-cells = <1>;
519 interrupt-parent = <&pmc>;
520 clocks = <&main>, <&plla>, <&utmi>, <&mck>;
523 sdmmc0_gclk: sdmmc0_gclk@31 {
529 sdmmc1_gclk: sdmmc1_gclk@32 {
535 tcb0_gclk: tcb0_gclk@35 {
538 atmel,clk-output-range = <0 83000000>;
541 tcb1_gclk: tcb1_gclk@36 {
544 atmel,clk-output-range = <0 83000000>;
547 pwm_gclk: pwm_gclk@38 {
550 atmel,clk-output-range = <0 83000000>;
553 pdmic_gclk: pdmic_gclk@48 {
558 i2s0_gclk: i2s0_gclk@54 {
563 i2s1_gclk: i2s1_gclk@55 {
568 can0_gclk: can0_gclk@56 {
571 atmel,clk-output-range = <0 80000000>;
574 can1_gclk: can1_gclk@57 {
577 atmel,clk-output-range = <0 80000000>;
580 classd_gclk: classd_gclk@59 {
583 atmel,clk-output-range = <0 100000000>;
588 qspi0: spi@f0020000 {
589 compatible = "atmel,sama5d2-qspi";
590 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
591 reg-names = "qspi_base", "qspi_mmap";
592 #address-cells = <1>;
594 clocks = <&qspi0_clk>;
599 compatible = "atmel,at91rm9200-spi";
600 reg = <0xf8000000 0x100>;
601 clocks = <&spi0_clk>;
602 clock-names = "spi_clk";
603 #address-cells = <1>;
608 macb0: ethernet@f8008000 {
609 compatible = "cdns,macb";
610 reg = <0xf8008000 0x1000>;
611 #address-cells = <1>;
613 clocks = <&macb0_clk>, <&macb0_clk>;
614 clock-names = "hclk", "pclk";
618 uart1: serial@f8020000 {
619 compatible = "atmel,at91sam9260-usart";
620 reg = <0xf8020000 0x100>;
621 clocks = <&uart1_clk>;
622 clock-names = "usart";
627 compatible = "atmel,sama5d2-i2c";
628 reg = <0xf8028000 0x100>;
629 #address-cells = <1>;
631 clocks = <&twi0_clk>;
636 compatible = "atmel,at91sam9x5-sckc";
637 reg = <0xf8048050 0x4>;
639 slow_rc_osc: slow_rc_osc {
640 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
642 clock-frequency = <32768>;
643 clock-accuracy = <250000000>;
644 atmel,startup-time-usec = <75>;
648 compatible = "atmel,at91sam9x5-clk-slow-osc";
650 clocks = <&slow_xtal>;
651 atmel,startup-time-usec = <1200000>;
655 compatible = "atmel,at91sam9x5-clk-slow";
657 clocks = <&slow_rc_osc &slow_osc>;
662 compatible = "atmel,at91rm9200-spi";
663 reg = <0xfc000000 0x100>;
664 #address-cells = <1>;
670 compatible = "atmel,sama5d2-i2c";
671 reg = <0xfc028000 0x100>;
672 #address-cells = <1>;
674 clocks = <&twi1_clk>;
678 pioA: gpio@fc038000 {
679 compatible = "atmel,sama5d2-gpio";
680 reg = <0xfc038000 0x600>;
681 clocks = <&pioA_clk>;
687 compatible = "atmel,sama5d2-pinctrl";