2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
22 #include "../common/qixis.h"
23 #include "../common/vsc3316_3308.h"
25 #include "t4240qds_qixis.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
30 {8, 8}, {9, 9}, {14, 14}, {15, 15} };
32 static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
33 {10, 10}, {11, 11}, {12, 12}, {13, 13} };
35 static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
36 {10, 11}, {11, 10}, {12, 2}, {13, 3} };
38 static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
39 {8, 9}, {9, 8}, {14, 1}, {15, 0} };
45 struct cpu_type *cpu = gd->arch.cpu;
46 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
49 printf("Board: %sQDS, ", cpu->name);
50 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
51 QIXIS_READ(id), QIXIS_READ(arch));
53 sw = QIXIS_READ(brdcfg[0]);
54 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
57 printf("vBank: %d\n", sw);
63 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
65 printf("FPGA: v%d (%s), build %d",
66 (int)QIXIS_READ(scver), qixis_read_tag(buf),
67 (int)qixis_read_minor());
68 /* the timestamp string contains "\n" at the end */
69 printf(" on %s", qixis_read_time(buf));
71 /* Display the RCW, so that no one gets confused as to what RCW
72 * we're actually using for this boot.
74 puts("Reset Configuration Word (RCW):");
75 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
76 u32 rcw = in_be32(&gur->rcwsr[i]);
79 printf("\n %08x:", i * 4);
85 * Display the actual SERDES reference clocks as configured by the
86 * dip switches on the board. Note that the SWx registers could
87 * technically be set to force the reference clocks to match the
88 * values that the SERDES expects (or vice versa). For now, however,
89 * we just display both values and hope the user notices when they
92 puts("SERDES Reference Clocks: ");
93 sw = QIXIS_READ(brdcfg[2]);
94 for (i = 0; i < MAX_SERDES; i++) {
95 static const char *freq[] = {
96 "100", "125", "156.25", "161.1328125"};
97 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
99 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
106 int select_i2c_ch_pca9547(u8 ch)
110 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
112 puts("PCA: failed to select proper channel\n");
120 * read_voltage from sensor on I2C bus
121 * We use average of 4 readings, waiting for 532us befor another reading
123 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
124 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
126 static inline int read_voltage(void)
128 int i, ret, voltage_read = 0;
131 for (i = 0; i < NUM_READINGS; i++) {
132 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
133 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
135 printf("VID: failed to read core voltage\n");
138 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
139 printf("VID: Core voltage sensor error\n");
142 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
144 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
145 udelay(WAIT_FOR_ADC);
147 /* calculate the average */
148 voltage_read /= NUM_READINGS;
154 * We need to calculate how long before the voltage starts to drop or increase
155 * It returns with the loop count. Each loop takes several readings (532us)
157 static inline int wait_for_voltage_change(int vdd_last)
159 int timeout, vdd_current;
161 vdd_current = read_voltage();
162 /* wait until voltage starts to drop */
163 for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
164 timeout < 100; timeout++) {
165 vdd_current = read_voltage();
167 if (timeout >= 100) {
168 printf("VID: Voltage adjustment timeout\n");
175 * argument 'wait' is the time we know the voltage difference can be measured
176 * this function keeps reading the voltage until it is stable
178 static inline int wait_for_voltage_stable(int wait)
180 int timeout, vdd_current, vdd_last;
182 vdd_last = read_voltage();
183 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
184 /* wait until voltage is stable */
185 vdd_current = read_voltage();
186 for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
187 timeout < 100; timeout++) {
188 vdd_last = vdd_current;
189 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
190 vdd_current = read_voltage();
192 if (timeout >= 100) {
193 printf("VID: Voltage adjustment timeout\n");
200 static inline int set_voltage(u8 vid)
204 vdd_last = read_voltage();
205 QIXIS_WRITE(brdcfg[6], vid);
206 wait = wait_for_voltage_change(vdd_last);
209 debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
210 wait = wait ? wait : 1;
212 vdd_last = wait_for_voltage_stable(wait);
215 debug("VID: Current voltage is %d mV\n", vdd_last);
221 static int adjust_vdd(ulong vdd_override)
223 int re_enable = disable_interrupts();
224 ccsr_gur_t __iomem *gur =
225 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
228 int vdd_target, vdd_current, vdd_last;
230 unsigned long vdd_string_override;
232 static const uint16_t vdd[32] = {
265 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
267 debug("VID: I2c failed to switch channel\n");
272 /* get the voltage ID from fuse status register */
273 fusesr = in_be32(&gur->dcfg_fusesr);
274 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
275 FSL_CORENET_DCFG_FUSESR_VID_MASK;
276 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
277 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
278 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
280 vdd_target = vdd[vid];
282 /* check override variable for overriding VDD */
283 vdd_string = getenv("t4240qds_vdd_mv");
284 if (vdd_override == 0 && vdd_string &&
285 !strict_strtoul(vdd_string, 10, &vdd_string_override))
286 vdd_override = vdd_string_override;
287 if (vdd_override >= 819 && vdd_override <= 1212) {
288 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
289 debug("VDD override is %lu\n", vdd_override);
290 } else if (vdd_override != 0) {
291 printf("Invalid value.\n");
294 if (vdd_target == 0) {
295 debug("VID: VID not used\n");
299 /* round up and divice by 10 to get a value in mV */
300 vdd_target = DIV_ROUND_UP(vdd_target, 10);
301 debug("VID: vid = %d mV\n", vdd_target);
305 * Check current board VID setting
306 * Voltage regulator support output to 6.250mv step
307 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
308 * the lowest is (vid=0x7f) 0.81875V
310 vid_current = QIXIS_READ(brdcfg[6]);
311 vdd_current = 121250 - (vid_current - 0x40) * 625;
312 debug("VID: Current vid setting is (0x%x) %d mV\n",
313 vid_current, vdd_current/100);
316 * Read voltage monitor to check real voltage.
317 * Voltage monitor LSB is 4mv.
319 vdd_last = read_voltage();
321 printf("VID: Could not read voltage sensor abort VID adjustment\n");
325 debug("VID: Core voltage is at %d mV\n", vdd_last);
327 * Adjust voltage to at or 8mV above target.
328 * Each step of adjustment is 6.25mV.
329 * Stepping down too fast may cause over current.
331 while (vdd_last > 0 && vid_current < 0x80 &&
332 vdd_last > (vdd_target + 8)) {
334 vdd_last = set_voltage(vid_current);
337 * Check if we need to step up
338 * This happens when board voltage switch was set too low
340 while (vdd_last > 0 && vid_current >= 0x40 &&
341 vdd_last < vdd_target + 2) {
343 vdd_last = set_voltage(vid_current);
346 printf("VID: Core voltage %d mV\n", vdd_last);
356 /* Configure Crossbar switches for Front-Side SerDes Ports */
357 int config_frontside_crossbar_vsc3316(void)
359 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
360 u32 srds_prtcl_s1, srds_prtcl_s2;
363 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
367 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
368 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
369 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
371 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
374 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
379 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
380 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
381 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
383 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
386 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
394 int config_backside_crossbar_mux(void)
396 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
397 u32 srds_prtcl_s3, srds_prtcl_s4;
400 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
401 FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
402 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
403 switch (srds_prtcl_s3) {
405 /* SerDes3 is not enabled */
410 /* SD3(0:7) => SLOT5(0:7) */
411 brdcfg = QIXIS_READ(brdcfg[12]);
412 brdcfg &= ~BRDCFG12_SD3MX_MASK;
413 brdcfg |= BRDCFG12_SD3MX_SLOT5;
414 QIXIS_WRITE(brdcfg[12], brdcfg);
425 /* SD3(4:7) => SLOT6(0:3) */
426 brdcfg = QIXIS_READ(brdcfg[12]);
427 brdcfg &= ~BRDCFG12_SD3MX_MASK;
428 brdcfg |= BRDCFG12_SD3MX_SLOT6;
429 QIXIS_WRITE(brdcfg[12], brdcfg);
432 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
437 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
438 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
439 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
440 switch (srds_prtcl_s4) {
442 /* SerDes4 is not enabled */
445 /* 10b, SD4(0:7) => SLOT7(0:7) */
446 brdcfg = QIXIS_READ(brdcfg[12]);
447 brdcfg &= ~BRDCFG12_SD4MX_MASK;
448 brdcfg |= BRDCFG12_SD4MX_SLOT7;
449 QIXIS_WRITE(brdcfg[12], brdcfg);
454 /* x1b, SD4(4:7) => SLOT8(0:3) */
455 brdcfg = QIXIS_READ(brdcfg[12]);
456 brdcfg &= ~BRDCFG12_SD4MX_MASK;
457 brdcfg |= BRDCFG12_SD4MX_SLOT8;
458 QIXIS_WRITE(brdcfg[12], brdcfg);
465 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
466 brdcfg = QIXIS_READ(brdcfg[12]);
467 brdcfg &= ~BRDCFG12_SD4MX_MASK;
468 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
469 QIXIS_WRITE(brdcfg[12], brdcfg);
472 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
480 int board_early_init_r(void)
482 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
483 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
486 * Remap Boot flash + PROMJET region to caching-inhibited
487 * so that flash can be erased properly.
490 /* Flush d-cache and invalidate i-cache of any FLASH data */
494 /* invalidate existing TLB entry for flash + promjet */
495 disable_tlb(flash_esel);
497 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
498 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
499 0, flash_esel, BOOKE_PAGESZ_256M, 1);
502 #ifdef CONFIG_SYS_DPAA_QBMAN
506 /* Disable remote I2C connection to qixis fpga */
507 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
510 * Adjust core voltage according to voltage ID
511 * This function changes I2C mux to channel 2.
514 printf("Warning: Adjusting core voltage failed.\n");
516 /* Configure board SERDES ports crossbar */
517 config_frontside_crossbar_vsc3316();
518 config_backside_crossbar_mux();
519 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
524 unsigned long get_board_sys_clk(void)
526 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
527 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
528 /* use accurate clock measurement */
529 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
530 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
535 debug("SYS Clock measurement is: %d\n", val);
538 printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
542 switch (sysclk_conf & 0x0F) {
543 case QIXIS_SYSCLK_83:
545 case QIXIS_SYSCLK_100:
547 case QIXIS_SYSCLK_125:
549 case QIXIS_SYSCLK_133:
551 case QIXIS_SYSCLK_150:
553 case QIXIS_SYSCLK_160:
555 case QIXIS_SYSCLK_166:
561 unsigned long get_board_ddr_clk(void)
563 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
564 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
565 /* use accurate clock measurement */
566 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
567 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
572 debug("DDR Clock measurement is: %d\n", val);
575 printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
579 switch ((ddrclk_conf & 0x30) >> 4) {
580 case QIXIS_DDRCLK_100:
582 case QIXIS_DDRCLK_125:
584 case QIXIS_DDRCLK_133:
590 static const char *serdes_clock_to_string(u32 clock)
593 case SRDS_PLLCR0_RFCK_SEL_100:
595 case SRDS_PLLCR0_RFCK_SEL_125:
597 case SRDS_PLLCR0_RFCK_SEL_156_25:
599 case SRDS_PLLCR0_RFCK_SEL_161_13:
600 return "161.1328125";
606 int misc_init_r(void)
609 serdes_corenet_t *srds_regs =
610 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
611 u32 actual[MAX_SERDES];
614 sw = QIXIS_READ(brdcfg[2]);
615 for (i = 0; i < MAX_SERDES; i++) {
616 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
619 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
622 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
625 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
628 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
633 for (i = 0; i < MAX_SERDES; i++) {
634 u32 pllcr0 = srds_regs->bank[i].pllcr0;
635 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
636 if (expected != actual[i]) {
637 printf("Warning: SERDES%u expects reference clock"
638 " %sMHz, but actual is %sMHz\n", i + 1,
639 serdes_clock_to_string(expected),
640 serdes_clock_to_string(actual[i]));
647 void ft_board_setup(void *blob, bd_t *bd)
652 ft_cpu_setup(blob, bd);
654 base = getenv_bootm_low();
655 size = getenv_bootm_size();
657 fdt_fixup_memory(blob, (u64)base, (u64)size);
660 pci_of_setup(blob, bd);
663 fdt_fixup_liodn(blob);
664 fdt_fixup_dr_usb(blob, bd);
666 #ifdef CONFIG_SYS_DPAA_FMAN
667 fdt_fixup_fman_ethernet(blob);
668 fdt_fixup_board_enet(blob);
673 * This function is called by bdinfo to print detail board information.
674 * As an exmaple for future board, we organize the messages into
675 * several sections. If applicable, the message is in the format of
677 * It should aligned with normal output of bdinfo command.
679 * Voltage: Core, DDR and another configurable voltages
680 * Clock : Critical clocks which are not printed already
681 * RCW : RCW source if not printed already
682 * Misc : Other important information not in above catagories
684 void board_detail(void)
687 u8 brdcfg[16], dutcfg[16], rst_ctl;
689 static const char * const clk[] = {"66.67", "100", "125", "133.33"};
691 for (i = 0; i < 16; i++) {
692 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
693 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
697 if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
698 vdd = read_voltage();
700 printf("Core voltage= %d mV\n", vdd);
701 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
704 printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
707 printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
708 clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
711 rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
712 puts("RCW source = ");
720 puts("16-bit NOR\n");
726 puts("SPI 16-bit addressing\n");
729 puts("SPI 24-bit addressing\n");
732 puts("I2C normal addressing\n");
735 puts("I2C extended addressing\n");
741 puts("8-bit NAND, 2KB\n");
744 if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
745 puts("Hard-coded RCW\n");
746 else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
747 puts("8-bit NAND, 4KB\n");
754 rst_ctl = QIXIS_READ(rst_ctl);
755 puts("HRESET_REQ = ");
756 switch (rst_ctl & 0x30) {
761 puts("Assert HRESET\n");
764 puts("Reset system\n");
773 * Reverse engineering switch settings.
774 * Some bits cannot be figured out. They will be displayed as
775 * underscore in binary format. mask[] has those bits.
776 * Some bits are calculated differently than the actual switches
777 * if booting with overriding by FPGA.
779 void qixis_dump_switch(void)
785 * Any bit with 1 means that bit cannot be reverse engineered.
786 * It will be displayed as _ in binary format.
788 static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
790 u8 brdcfg[16], dutcfg[16];
792 for (i = 0; i < 16; i++) {
793 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
794 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
798 sw[1] = (dutcfg[1] << 0x07) | \
799 ((dutcfg[12] & 0xC0) >> 1) | \
800 ((dutcfg[11] & 0xE0) >> 3) | \
801 ((dutcfg[6] & 0x80) >> 6) | \
802 ((dutcfg[1] & 0x80) >> 7);
803 sw[2] = ((brdcfg[1] & 0x0f) << 4) | \
804 ((brdcfg[1] & 0x30) >> 2) | \
805 ((brdcfg[1] & 0x40) >> 5) | \
806 ((brdcfg[1] & 0x80) >> 7);
808 sw[4] = ((dutcfg[2] & 0x01) << 7) | \
809 ((dutcfg[2] & 0x06) << 4) | \
810 ((~QIXIS_READ(present)) & 0x10) | \
811 ((brdcfg[3] & 0x80) >> 4) | \
812 ((brdcfg[3] & 0x01) << 2) | \
813 ((brdcfg[6] == 0x62) ? 3 : \
814 ((brdcfg[6] == 0x5a) ? 2 : \
815 ((brdcfg[6] == 0x5e) ? 1 : 0)));
816 sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
817 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
818 ((brdcfg[0] & 0x40) >> 5);
819 sw[6] = (brdcfg[11] & 0x20) |
820 ((brdcfg[5] & 0x02) << 3);
821 sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
822 ((brdcfg[5] & 0x10) << 2);
823 sw[8] = ((brdcfg[12] & 0x08) << 4) | \
824 ((brdcfg[12] & 0x03) << 5);
826 puts("DIP switch (reverse-engineering)\n");
827 for (i = 0; i < 9; i++) {
828 printf("SW%d = 0b%s (0x%02x)\n",
829 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
833 static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
838 return CMD_RET_USAGE;
839 if (!strict_strtoul(argv[1], 10, &override))
840 adjust_vdd(override); /* the value is checked by callee */
842 return CMD_RET_USAGE;
848 vdd_override, 2, 0, do_vdd_adjust,
850 "- override with the voltage specified in mV, eg. 1050"