2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
11 #include <stm32_rcc.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/arch/stm32_pwr.h>
17 #include <dt-bindings/mfd/stm32f7-rcc.h>
19 #define RCC_CR_HSION BIT(0)
20 #define RCC_CR_HSEON BIT(16)
21 #define RCC_CR_HSERDY BIT(17)
22 #define RCC_CR_HSEBYP BIT(18)
23 #define RCC_CR_CSSON BIT(19)
24 #define RCC_CR_PLLON BIT(24)
25 #define RCC_CR_PLLRDY BIT(25)
26 #define RCC_CR_PLLSAION BIT(28)
27 #define RCC_CR_PLLSAIRDY BIT(29)
29 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
30 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
31 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
32 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
33 #define RCC_PLLCFGR_PLLSRC BIT(22)
34 #define RCC_PLLCFGR_PLLM_SHIFT 0
35 #define RCC_PLLCFGR_PLLN_SHIFT 6
36 #define RCC_PLLCFGR_PLLP_SHIFT 16
37 #define RCC_PLLCFGR_PLLQ_SHIFT 24
39 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
40 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
41 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
42 #define RCC_CFGR_SW0 BIT(0)
43 #define RCC_CFGR_SW1 BIT(1)
44 #define RCC_CFGR_SW_MASK GENMASK(1, 0)
45 #define RCC_CFGR_SW_HSI 0
46 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
47 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
48 #define RCC_CFGR_SWS0 BIT(2)
49 #define RCC_CFGR_SWS1 BIT(3)
50 #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
51 #define RCC_CFGR_SWS_HSI 0
52 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
53 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
54 #define RCC_CFGR_HPRE_SHIFT 4
55 #define RCC_CFGR_PPRE1_SHIFT 10
56 #define RCC_CFGR_PPRE2_SHIFT 13
58 #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
59 #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
60 #define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
61 #define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
62 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
63 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
64 #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
65 #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
66 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
67 #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
68 #define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
70 #define RCC_DCKCFGRX_TIMPRE BIT(24)
71 #define RCC_DCKCFGRX_CK48MSEL BIT(27)
72 #define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
73 #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
75 #define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
76 #define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
77 #define RCC_DCKCFGR_PLLSAIDIVR_2 0
80 * RCC AHB1ENR specific definitions
82 #define RCC_AHB1ENR_ETHMAC_EN BIT(25)
83 #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
84 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
87 * RCC APB1ENR specific definitions
89 #define RCC_APB1ENR_TIM2EN BIT(0)
90 #define RCC_APB1ENR_PWREN BIT(28)
93 * RCC APB2ENR specific definitions
95 #define RCC_APB2ENR_SYSCFGEN BIT(14)
96 #define RCC_APB2ENR_SAI1EN BIT(22)
104 static const struct stm32_clk_info stm32f4_clk_info = {
110 .ahb_psc = AHB_PSC_1,
111 .apb1_psc = APB_PSC_4,
112 .apb2_psc = APB_PSC_2,
114 .has_overdrive = false,
118 static const struct stm32_clk_info stm32f7_clk_info = {
124 .ahb_psc = AHB_PSC_1,
125 .apb1_psc = APB_PSC_4,
126 .apb2_psc = APB_PSC_2,
128 .has_overdrive = true,
133 struct stm32_rcc_regs *base;
134 struct stm32_pwr_regs *pwr_regs;
135 struct stm32_clk_info info;
136 unsigned long hse_rate;
139 static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
141 static int configure_clocks(struct udevice *dev)
143 struct stm32_clk *priv = dev_get_priv(dev);
144 struct stm32_rcc_regs *regs = priv->base;
145 struct stm32_pwr_regs *pwr = priv->pwr_regs;
146 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
148 /* Reset RCC configuration */
149 setbits_le32(®s->cr, RCC_CR_HSION);
150 writel(0, ®s->cfgr); /* Reset CFGR */
151 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
152 | RCC_CR_PLLON | RCC_CR_PLLSAION));
153 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
154 clrbits_le32(®s->cr, RCC_CR_HSEBYP);
155 writel(0, ®s->cir); /* Disable all interrupts */
157 /* Configure for HSE+PLL operation */
158 setbits_le32(®s->cr, RCC_CR_HSEON);
159 while (!(readl(®s->cr) & RCC_CR_HSERDY))
162 setbits_le32(®s->cfgr, ((
163 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
164 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
165 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
167 /* Configure the main PLL */
168 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
169 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
170 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
171 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
172 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
173 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
174 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
175 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
176 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
178 /* configure SDMMC clock */
179 if (priv->info.v2) { /*stm32f7 case */
180 /* select PLLQ as 48MHz clock source */
181 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
183 /* select 48MHz as SDMMC1 clock source */
184 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
186 /* select 48MHz as SDMMC2 clock source */
187 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
188 } else { /* stm32f4 case */
189 /* select PLLQ as 48MHz clock source */
190 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
192 /* select 48MHz as SDMMC1 clock source */
193 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
196 #ifdef CONFIG_VIDEO_STM32
198 * Configure the SAI PLL to generate LTDC pixel clock
200 clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
201 RCC_PLLSAICFGR_PLLSAIR_3);
202 clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
203 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
205 clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
206 RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
208 /* Enable the main PLL */
209 setbits_le32(®s->cr, RCC_CR_PLLON);
210 while (!(readl(®s->cr) & RCC_CR_PLLRDY))
213 #ifdef CONFIG_VIDEO_STM32
214 /* Enable the SAI PLL */
215 setbits_le32(®s->cr, RCC_CR_PLLSAION);
216 while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
219 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
221 if (priv->info.has_overdrive) {
223 * Enable high performance mode
224 * System frequency up to 200 MHz
226 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
228 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
230 /* Enable the Over-drive switch */
231 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
233 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
237 stm32_flash_latency_cfg(5);
238 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
239 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
241 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
245 #ifdef CONFIG_ETH_DESIGNWARE
246 /* gate the SYSCFG clock, needed to set RMII ethernet interface */
247 setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN);
253 static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
255 struct stm32_rcc_regs *regs = priv->base;
257 if (priv->info.v2) /*stm32f7 case */
258 return readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
261 return readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
264 static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
266 struct stm32_rcc_regs *regs = priv->base;
269 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
270 pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
271 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
273 return ((priv->hse_rate / pllm) * pllsain);
276 static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
277 enum pllsai_div output)
279 struct stm32_rcc_regs *regs = priv->base;
284 pll_div_output = ((((readl(®s->pllsaicfgr)
285 & RCC_PLLSAICFGR_PLLSAIP_MASK)
286 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
289 pll_div_output = (readl(®s->pllsaicfgr)
290 & RCC_PLLSAICFGR_PLLSAIQ_MASK)
291 >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
294 pll_div_output = (readl(®s->pllsaicfgr)
295 & RCC_PLLSAICFGR_PLLSAIR_MASK)
296 >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
299 pr_err("incorrect PLLSAI output %d\n", output);
303 return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
306 static bool stm32_get_timpre(struct stm32_clk *priv)
308 struct stm32_rcc_regs *regs = priv->base;
311 if (priv->info.v2) /*stm32f7 case */
312 val = readl(®s->dckcfgr2);
314 val = readl(®s->dckcfgr);
315 /* get timer prescaler */
316 return !!(val & RCC_DCKCFGRX_TIMPRE);
319 static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
322 /* Prescaler table lookups for clock computation */
323 u8 ahb_psc_table[16] = {
324 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
327 shift = ahb_psc_table[(
328 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
329 >> RCC_CFGR_HPRE_SHIFT)];
331 return sysclk >> shift;
334 static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
336 /* Prescaler table lookups for clock computation */
337 u8 apb_psc_table[8] = {
338 0, 0, 0, 0, 1, 2, 3, 4
342 return apb_psc_table[(
343 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
344 >> RCC_CFGR_PPRE1_SHIFT)];
346 return apb_psc_table[(
347 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
348 >> RCC_CFGR_PPRE2_SHIFT)];
351 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
354 struct stm32_rcc_regs *regs = priv->base;
355 u8 shift = stm32_get_apb_shift(regs, apb);
357 if (stm32_get_timpre(priv))
359 * if APB prescaler is configured to a
360 * division factor of 1, 2 or 4
366 return stm32_get_hclk_rate(regs, sysclk);
368 return (sysclk >> shift) * 4;
372 * if APB prescaler is configured to a
373 * division factor of 1
378 return (sysclk >> shift) * 2;
381 static ulong stm32_clk_get_rate(struct clk *clk)
383 struct stm32_clk *priv = dev_get_priv(clk->dev);
384 struct stm32_rcc_regs *regs = priv->base;
390 u16 pllm, plln, pllp, pllq;
392 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
394 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
395 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
396 >> RCC_PLLCFGR_PLLN_SHIFT);
397 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
398 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
399 pllq = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
400 >> RCC_PLLCFGR_PLLQ_SHIFT);
401 vco = (priv->hse_rate / pllm) * plln;
409 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
410 * AHB1, AHB2 and AHB3
412 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
413 return stm32_get_hclk_rate(regs, sysclk);
415 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
416 /* For timer clock, an additionnal prescaler is used*/
418 case STM32F7_APB1_CLOCK(TIM2):
419 case STM32F7_APB1_CLOCK(TIM3):
420 case STM32F7_APB1_CLOCK(TIM4):
421 case STM32F7_APB1_CLOCK(TIM5):
422 case STM32F7_APB1_CLOCK(TIM6):
423 case STM32F7_APB1_CLOCK(TIM7):
424 case STM32F7_APB1_CLOCK(TIM12):
425 case STM32F7_APB1_CLOCK(TIM13):
426 case STM32F7_APB1_CLOCK(TIM14):
427 return stm32_get_timer_rate(priv, sysclk, APB1);
429 return (sysclk >> stm32_get_apb_shift(regs, APB1));
432 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
435 * particular case for SDMMC1 and SDMMC2 :
436 * 48Mhz source clock can be from main PLL or from
439 case STM32F7_APB2_CLOCK(SDMMC1):
440 case STM32F7_APB2_CLOCK(SDMMC2):
441 if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
442 sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
444 sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
446 if (readl(®s->dckcfgr2) & sdmmcxsel_bit)
447 /* System clock is selected as SDMMC1 clock */
450 * 48 MHz can be generated by either PLLSAIP
451 * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
453 if (stm32_clk_get_ck48msel(priv))
454 return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
459 /* For timer clock, an additionnal prescaler is used*/
460 case STM32F7_APB2_CLOCK(TIM1):
461 case STM32F7_APB2_CLOCK(TIM8):
462 case STM32F7_APB2_CLOCK(TIM9):
463 case STM32F7_APB2_CLOCK(TIM10):
464 case STM32F7_APB2_CLOCK(TIM11):
465 return stm32_get_timer_rate(priv, sysclk, APB2);
468 /* particular case for LTDC clock */
469 case STM32F7_APB2_CLOCK(LTDC):
470 saidivr = readl(®s->dckcfgr);
471 saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
472 >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
473 pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
475 return pllsai_rate / pllsaidivr_table[saidivr];
477 return (sysclk >> stm32_get_apb_shift(regs, APB2));
480 pr_err("clock index %ld out of range\n", clk->id);
485 static ulong stm32_set_rate(struct clk *clk, ulong rate)
490 static int stm32_clk_enable(struct clk *clk)
492 struct stm32_clk *priv = dev_get_priv(clk->dev);
493 struct stm32_rcc_regs *regs = priv->base;
494 u32 offset = clk->id / 32;
495 u32 bit_index = clk->id % 32;
497 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
498 __func__, clk->id, offset, bit_index);
499 setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
504 static int stm32_clk_probe(struct udevice *dev)
506 struct ofnode_phandle_args args;
507 struct udevice *fixed_clock_dev = NULL;
511 debug("%s\n", __func__);
513 struct stm32_clk *priv = dev_get_priv(dev);
516 addr = dev_read_addr(dev);
517 if (addr == FDT_ADDR_T_NONE)
520 priv->base = (struct stm32_rcc_regs *)addr;
522 switch (dev_get_driver_data(dev)) {
524 memcpy(&priv->info, &stm32f4_clk_info,
525 sizeof(struct stm32_clk_info));
528 memcpy(&priv->info, &stm32f7_clk_info,
529 sizeof(struct stm32_clk_info));
535 /* retrieve HSE frequency (external oscillator) */
536 err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
540 pr_err("Can't find fixed clock (%d)", err);
544 err = clk_request(fixed_clock_dev, &clk);
546 pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
552 * set pllm factor accordingly to the external oscillator
553 * frequency (HSE). For STM32F4 and STM32F7, we want VCO
555 * if input PLL frequency is 25Mhz, divide it by 25
558 priv->hse_rate = clk_get_rate(&clk);
560 if (priv->hse_rate < 1000000) {
561 pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
566 priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
568 if (priv->info.has_overdrive) {
569 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
572 debug("%s: can't find syscon device (%d)\n", __func__,
577 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
580 configure_clocks(dev);
585 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
587 debug("%s(clk=%p)\n", __func__, clk);
589 if (args->args_count != 2) {
590 debug("Invaild args_count: %d\n", args->args_count);
594 if (args->args_count)
595 clk->id = args->args[1];
602 static struct clk_ops stm32_clk_ops = {
603 .of_xlate = stm32_clk_of_xlate,
604 .enable = stm32_clk_enable,
605 .get_rate = stm32_clk_get_rate,
606 .set_rate = stm32_set_rate,
609 U_BOOT_DRIVER(stm32fx_clk) = {
610 .name = "stm32fx_rcc_clock",
612 .ops = &stm32_clk_ops,
613 .probe = stm32_clk_probe,
614 .priv_auto_alloc_size = sizeof(struct stm32_clk),
615 .flags = DM_FLAG_PRE_RELOC,