2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/grf_rk322x.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/periph.h>
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 /* GRF_GPIO0A_IOMUX */
23 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
29 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
35 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
41 GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
46 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
51 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
56 /* GRF_GPIO0B_IOMUX */
59 GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
64 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
70 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
76 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
82 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
93 /* GRF_GPIO0C_IOMUX */
96 GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
101 GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
107 /* GRF_GPIO0D_IOMUX */
110 GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
116 GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
121 GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
126 GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
131 /* GRF_GPIO1A_IOMUX */
139 /* GRF_GPIO1B_IOMUX */
142 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
147 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
152 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
158 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
164 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
170 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
176 /* GRF_GPIO1C_IOMUX */
179 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
182 GPIO1C7_EMMC_RSTNOUT,
185 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
191 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
197 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
203 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
209 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
215 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
220 GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
222 GPIO1C0_SDMMC_CLKOUT,
225 /* GRF_GPIO1D_IOMUX */
228 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
234 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
240 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
246 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
252 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
258 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
264 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
270 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
276 /* GRF_GPIO2A_IOMUX */
279 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
285 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
291 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
297 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
303 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
309 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
315 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
321 /* GRF_GPIO2B_IOMUX */
324 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
329 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
335 GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
340 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
345 GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
350 GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
355 GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
360 GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
363 GPIO2B0_MAC_SPEED_IOUT,
366 /* GRF_GPIO2C_IOMUX */
369 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
374 GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
379 GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
385 GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
391 GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
396 GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
401 GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
406 GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
411 /* GRF_GPIO2D_IOMUX */
414 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
424 /* GRF_GPIO3C_IOMUX */
427 GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
432 GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
437 GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
442 /* GRF_GPIO3D_IOMUX */
445 GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
452 CON_IOMUX_GMACSEL_SHIFT = 15,
453 CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT,
454 CON_IOMUX_GMACSEL_1 = 1,
455 CON_IOMUX_UART1SEL_SHIFT = 11,
456 CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
457 CON_IOMUX_UART2SEL_SHIFT = 8,
458 CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
459 CON_IOMUX_UART2SEL_2 = 0,
460 CON_IOMUX_UART2SEL_21,
461 CON_IOMUX_EMMCSEL_SHIFT = 7,
462 CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
463 CON_IOMUX_PWM3SEL_SHIFT = 3,
464 CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
465 CON_IOMUX_PWM2SEL_SHIFT = 2,
466 CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
467 CON_IOMUX_PWM1SEL_SHIFT = 1,
468 CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
469 CON_IOMUX_PWM0SEL_SHIFT = 0,
470 CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
473 struct rk322x_pinctrl_priv {
474 struct rk322x_grf *grf;
477 static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
479 u32 mux_con = readl(&grf->con_iomux);
483 if (mux_con & CON_IOMUX_PWM0SEL_MASK)
484 rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
485 GPIO3C5_PWM10 << GPIO3C5_SHIFT);
487 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
488 GPIO0D2_PWM0 << GPIO0D2_SHIFT);
491 if (mux_con & CON_IOMUX_PWM1SEL_MASK)
492 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
493 GPIO0D6_PWM11 << GPIO0D6_SHIFT);
495 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
496 GPIO0D3_PWM1 << GPIO0D3_SHIFT);
499 if (mux_con & CON_IOMUX_PWM2SEL_MASK)
500 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
501 GPIO1B4_PWM12 << GPIO1B4_SHIFT);
503 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
504 GPIO0D4_PWM2 << GPIO0D4_SHIFT);
507 if (mux_con & CON_IOMUX_PWM3SEL_MASK)
508 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
509 GPIO1B3_PWM13 << GPIO1B3_SHIFT);
511 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
512 GPIO3D2_PWM3 << GPIO3D2_SHIFT);
515 debug("pwm id = %d iomux error!\n", pwm_id);
520 static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
524 rk_clrsetreg(&grf->gpio0a_iomux,
525 GPIO0A1_MASK | GPIO0A0_MASK,
526 GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
527 GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
531 rk_clrsetreg(&grf->gpio0a_iomux,
532 GPIO0A3_MASK | GPIO0A2_MASK,
533 GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
534 GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
537 rk_clrsetreg(&grf->gpio2c_iomux,
538 GPIO2C5_MASK | GPIO2C4_MASK,
539 GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
540 GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
543 rk_clrsetreg(&grf->gpio0a_iomux,
544 GPIO0A7_MASK | GPIO0A6_MASK,
545 GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
546 GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
552 static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
556 rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
557 GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
560 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
561 GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
564 rk_clrsetreg(&grf->gpio0b_iomux,
565 GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
566 GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
567 GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
568 GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
571 static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
573 u32 mux_con = readl(&grf->con_iomux);
576 case PERIPH_ID_UART1:
577 if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
578 rk_clrsetreg(&grf->gpio1b_iomux,
579 GPIO1B1_MASK | GPIO1B2_MASK,
580 GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
581 GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
583 case PERIPH_ID_UART2:
584 if (mux_con & CON_IOMUX_UART2SEL_MASK)
585 rk_clrsetreg(&grf->gpio1b_iomux,
586 GPIO1B1_MASK | GPIO1B2_MASK,
587 GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
588 GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
590 rk_clrsetreg(&grf->gpio1c_iomux,
591 GPIO1C3_MASK | GPIO1C2_MASK,
592 GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
593 GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
598 static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
602 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
603 GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
604 GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
605 GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
606 GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
607 GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
608 GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
609 GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
610 GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
611 rk_clrsetreg(&grf->gpio2a_iomux,
612 GPIO2A5_MASK | GPIO2A7_MASK,
613 GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
614 GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
615 rk_clrsetreg(&grf->gpio1c_iomux,
616 GPIO1C6_MASK | GPIO1C7_MASK,
617 GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
618 GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
620 case PERIPH_ID_SDCARD:
621 rk_clrsetreg(&grf->gpio1b_iomux,
622 GPIO1B6_MASK | GPIO1B7_MASK,
623 GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
624 GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT);
625 rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
626 GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
627 GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
628 GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
629 GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
630 GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
631 GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
636 static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
638 struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
640 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
646 pinctrl_rk322x_pwm_config(priv->grf, func);
651 pinctrl_rk322x_i2c_config(priv->grf, func);
654 pinctrl_rk322x_spi_config(priv->grf, flags);
656 case PERIPH_ID_UART0:
657 case PERIPH_ID_UART1:
658 case PERIPH_ID_UART2:
659 pinctrl_rk322x_uart_config(priv->grf, func);
661 case PERIPH_ID_SDMMC0:
662 case PERIPH_ID_SDMMC1:
663 pinctrl_rk322x_sdmmc_config(priv->grf, func);
672 static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
673 struct udevice *periph)
678 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
679 "interrupts", cell, ARRAY_SIZE(cell));
685 return PERIPH_ID_SDCARD;
687 return PERIPH_ID_EMMC;
689 return PERIPH_ID_I2C0;
691 return PERIPH_ID_I2C1;
693 return PERIPH_ID_I2C2;
695 return PERIPH_ID_SPI0;
697 return PERIPH_ID_PWM0;
699 return PERIPH_ID_UART0;
701 return PERIPH_ID_UART1;
703 return PERIPH_ID_UART2;
708 static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
709 struct udevice *periph)
713 func = rk322x_pinctrl_get_periph_id(dev, periph);
716 return rk322x_pinctrl_request(dev, func, 0);
719 static struct pinctrl_ops rk322x_pinctrl_ops = {
720 .set_state_simple = rk322x_pinctrl_set_state_simple,
721 .request = rk322x_pinctrl_request,
722 .get_periph_id = rk322x_pinctrl_get_periph_id,
725 static int rk322x_pinctrl_probe(struct udevice *dev)
727 struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
729 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
730 debug("%s: grf=%p\n", __func__, priv->grf);
734 static const struct udevice_id rk322x_pinctrl_ids[] = {
735 { .compatible = "rockchip,rk3228-pinctrl" },
739 U_BOOT_DRIVER(pinctrl_rk3228) = {
740 .name = "pinctrl_rk3228",
741 .id = UCLASS_PINCTRL,
742 .of_match = rk322x_pinctrl_ids,
743 .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
744 .ops = &rk322x_pinctrl_ops,
745 .bind = dm_scan_fdt_dev,
746 .probe = rk322x_pinctrl_probe,