]> git.sur5r.net Git - u-boot/commitdiff
rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver
authorDavid Wu <david.wu@rock-chips.com>
Sat, 13 Jan 2018 06:04:26 +0000 (14:04 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sun, 28 Jan 2018 16:12:38 +0000 (17:12 +0100)
Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
arch/arm/include/asm/arch-rockchip/grf_rk322x.h
arch/arm/mach-rockchip/rk322x-board-spl.c
arch/arm/mach-rockchip/rk322x-board.c
drivers/pinctrl/rockchip/pinctrl_rk322x.c

index c0c0d84cf1675d35c3d717fda8993b82478185ba..52e5a0a0d5318ad0218c430c9ad636fe93504761 100644 (file)
@@ -88,461 +88,6 @@ struct rk322x_sgrf {
        unsigned int busdmac_con[4];
 };
 
-/* GRF_GPIO0A_IOMUX */
-enum {
-       GPIO0A7_SHIFT           = 14,
-       GPIO0A7_MASK            = 3 << GPIO0A7_SHIFT,
-       GPIO0A7_GPIO            = 0,
-       GPIO0A7_I2C3_SDA,
-       GPIO0A7_HDMI_DDCSDA,
-
-       GPIO0A6_SHIFT           = 12,
-       GPIO0A6_MASK            = 3 << GPIO0A6_SHIFT,
-       GPIO0A6_GPIO            = 0,
-       GPIO0A6_I2C3_SCL,
-       GPIO0A6_HDMI_DDCSCL,
-
-       GPIO0A3_SHIFT           = 6,
-       GPIO0A3_MASK            = 3 << GPIO0A3_SHIFT,
-       GPIO0A3_GPIO            = 0,
-       GPIO0A3_I2C1_SDA,
-       GPIO0A3_SDIO_CMD,
-
-       GPIO0A2_SHIFT           = 4,
-       GPIO0A2_MASK            = 3 << GPIO0A2_SHIFT,
-       GPIO0A2_GPIO            = 0,
-       GPIO0A2_I2C1_SCL,
-
-       GPIO0A1_SHIFT           = 2,
-       GPIO0A1_MASK            = 3 << GPIO0A1_SHIFT,
-       GPIO0A1_GPIO            = 0,
-       GPIO0A1_I2C0_SDA,
-
-       GPIO0A0_SHIFT           = 0,
-       GPIO0A0_MASK            = 3 << GPIO0A0_SHIFT,
-       GPIO0A0_GPIO            = 0,
-       GPIO0A0_I2C0_SCL,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
-       GPIO0B7_SHIFT           = 14,
-       GPIO0B7_MASK            = 3 << GPIO0B7_SHIFT,
-       GPIO0B7_GPIO            = 0,
-       GPIO0B7_HDMI_HDP,
-
-       GPIO0B6_SHIFT           = 12,
-       GPIO0B6_MASK            = 3 << GPIO0B6_SHIFT,
-       GPIO0B6_GPIO            = 0,
-       GPIO0B6_I2S_SDI,
-       GPIO0B6_SPI_CSN0,
-
-       GPIO0B5_SHIFT           = 10,
-       GPIO0B5_MASK            = 3 << GPIO0B5_SHIFT,
-       GPIO0B5_GPIO            = 0,
-       GPIO0B5_I2S_SDO,
-       GPIO0B5_SPI_RXD,
-
-       GPIO0B3_SHIFT           = 6,
-       GPIO0B3_MASK            = 3 << GPIO0B3_SHIFT,
-       GPIO0B3_GPIO            = 0,
-       GPIO0B3_I2S1_LRCKRX,
-       GPIO0B3_SPI_TXD,
-
-       GPIO0B1_SHIFT           = 2,
-       GPIO0B1_MASK            = 3 << GPIO0B1_SHIFT,
-       GPIO0B1_GPIO            = 0,
-       GPIO0B1_I2S_SCLK,
-       GPIO0B1_SPI_CLK,
-
-       GPIO0B0_SHIFT           = 0,
-       GPIO0B0_MASK            = 3,
-       GPIO0B0_GPIO            = 0,
-       GPIO0B0_I2S_MCLK,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
-       GPIO0C4_SHIFT           = 8,
-       GPIO0C4_MASK            = 3 << GPIO0C4_SHIFT,
-       GPIO0C4_GPIO            = 0,
-       GPIO0C4_HDMI_CECSDA,
-
-       GPIO0C1_SHIFT           = 2,
-       GPIO0C1_MASK            = 3 << GPIO0C1_SHIFT,
-       GPIO0C1_GPIO            = 0,
-       GPIO0C1_UART0_RSTN,
-       GPIO0C1_CLK_OUT1,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
-       GPIO0D6_SHIFT           = 12,
-       GPIO0D6_MASK            = 3 << GPIO0D6_SHIFT,
-       GPIO0D6_GPIO            = 0,
-       GPIO0D6_SDIO_PWREN,
-       GPIO0D6_PWM11,
-
-
-       GPIO0D4_SHIFT           = 8,
-       GPIO0D4_MASK            = 3 << GPIO0D4_SHIFT,
-       GPIO0D4_GPIO            = 0,
-       GPIO0D4_PWM2,
-
-       GPIO0D3_SHIFT           = 6,
-       GPIO0D3_MASK            = 3 << GPIO0D3_SHIFT,
-       GPIO0D3_GPIO            = 0,
-       GPIO0D3_PWM1,
-
-       GPIO0D2_SHIFT           = 4,
-       GPIO0D2_MASK            = 3 << GPIO0D2_SHIFT,
-       GPIO0D2_GPIO            = 0,
-       GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
-       GPIO1A7_SHIFT           = 14,
-       GPIO1A7_MASK            = 1,
-       GPIO1A7_GPIO            = 0,
-       GPIO1A7_SDMMC_WRPRT,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
-       GPIO1B7_SHIFT           = 14,
-       GPIO1B7_MASK            = 3 << GPIO1B7_SHIFT,
-       GPIO1B7_GPIO            = 0,
-       GPIO1B7_SDMMC_CMD,
-
-       GPIO1B6_SHIFT           = 12,
-       GPIO1B6_MASK            = 3 << GPIO1B6_SHIFT,
-       GPIO1B6_GPIO            = 0,
-       GPIO1B6_SDMMC_PWREN,
-
-       GPIO1B4_SHIFT           = 8,
-       GPIO1B4_MASK            = 3 << GPIO1B4_SHIFT,
-       GPIO1B4_GPIO            = 0,
-       GPIO1B4_SPI_CSN1,
-       GPIO1B4_PWM12,
-
-       GPIO1B3_SHIFT           = 6,
-       GPIO1B3_MASK            = 3 << GPIO1B3_SHIFT,
-       GPIO1B3_GPIO            = 0,
-       GPIO1B3_UART1_RSTN,
-       GPIO1B3_PWM13,
-
-       GPIO1B2_SHIFT           = 4,
-       GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
-       GPIO1B2_GPIO            = 0,
-       GPIO1B2_UART1_SIN,
-       GPIO1B2_UART21_SIN,
-
-       GPIO1B1_SHIFT           = 2,
-       GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
-       GPIO1B1_GPIO            = 0,
-       GPIO1B1_UART1_SOUT,
-       GPIO1B1_UART21_SOUT,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
-       GPIO1C7_SHIFT           = 14,
-       GPIO1C7_MASK            = 3 << GPIO1C7_SHIFT,
-       GPIO1C7_GPIO            = 0,
-       GPIO1C7_NAND_CS3,
-       GPIO1C7_EMMC_RSTNOUT,
-
-       GPIO1C6_SHIFT           = 12,
-       GPIO1C6_MASK            = 3 << GPIO1C6_SHIFT,
-       GPIO1C6_GPIO            = 0,
-       GPIO1C6_NAND_CS2,
-       GPIO1C6_EMMC_CMD,
-
-
-       GPIO1C5_SHIFT           = 10,
-       GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
-       GPIO1C5_GPIO            = 0,
-       GPIO1C5_SDMMC_D3,
-       GPIO1C5_JTAG_TMS,
-
-       GPIO1C4_SHIFT           = 8,
-       GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
-       GPIO1C4_GPIO            = 0,
-       GPIO1C4_SDMMC_D2,
-       GPIO1C4_JTAG_TCK,
-
-       GPIO1C3_SHIFT           = 6,
-       GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
-       GPIO1C3_GPIO            = 0,
-       GPIO1C3_SDMMC_D1,
-       GPIO1C3_UART2_SIN,
-
-       GPIO1C2_SHIFT           = 4,
-       GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT ,
-       GPIO1C2_GPIO            = 0,
-       GPIO1C2_SDMMC_D0,
-       GPIO1C2_UART2_SOUT,
-
-       GPIO1C1_SHIFT           = 2,
-       GPIO1C1_MASK            = 3 << GPIO1C1_SHIFT,
-       GPIO1C1_GPIO            = 0,
-       GPIO1C1_SDMMC_DETN,
-
-       GPIO1C0_SHIFT           = 0,
-       GPIO1C0_MASK            = 3 << GPIO1C0_SHIFT,
-       GPIO1C0_GPIO            = 0,
-       GPIO1C0_SDMMC_CLKOUT,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
-       GPIO1D7_SHIFT           = 14,
-       GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
-       GPIO1D7_GPIO            = 0,
-       GPIO1D7_NAND_D7,
-       GPIO1D7_EMMC_D7,
-
-       GPIO1D6_SHIFT           = 12,
-       GPIO1D6_MASK            = 3 << GPIO1D6_SHIFT,
-       GPIO1D6_GPIO            = 0,
-       GPIO1D6_NAND_D6,
-       GPIO1D6_EMMC_D6,
-
-       GPIO1D5_SHIFT           = 10,
-       GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
-       GPIO1D5_GPIO            = 0,
-       GPIO1D5_NAND_D5,
-       GPIO1D5_EMMC_D5,
-
-       GPIO1D4_SHIFT           = 8,
-       GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
-       GPIO1D4_GPIO            = 0,
-       GPIO1D4_NAND_D4,
-       GPIO1D4_EMMC_D4,
-
-       GPIO1D3_SHIFT           = 6,
-       GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
-       GPIO1D3_GPIO            = 0,
-       GPIO1D3_NAND_D3,
-       GPIO1D3_EMMC_D3,
-
-       GPIO1D2_SHIFT           = 4,
-       GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
-       GPIO1D2_GPIO            = 0,
-       GPIO1D2_NAND_D2,
-       GPIO1D2_EMMC_D2,
-
-       GPIO1D1_SHIFT           = 2,
-       GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
-       GPIO1D1_GPIO            = 0,
-       GPIO1D1_NAND_D1,
-       GPIO1D1_EMMC_D1,
-
-       GPIO1D0_SHIFT           = 0,
-       GPIO1D0_MASK            = 3 << GPIO1D0_SHIFT,
-       GPIO1D0_GPIO            = 0,
-       GPIO1D0_NAND_D0,
-       GPIO1D0_EMMC_D0,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
-       GPIO2A7_SHIFT           = 14,
-       GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
-       GPIO2A7_GPIO            = 0,
-       GPIO2A7_NAND_DQS,
-       GPIO2A7_EMMC_CLKOUT,
-
-       GPIO2A5_SHIFT           = 10,
-       GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
-       GPIO2A5_GPIO            = 0,
-       GPIO2A5_NAND_WP,
-       GPIO2A5_EMMC_PWREN,
-
-       GPIO2A4_SHIFT           = 8,
-       GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
-       GPIO2A4_GPIO            = 0,
-       GPIO2A4_NAND_RDY,
-       GPIO2A4_EMMC_CMD,
-
-       GPIO2A3_SHIFT           = 6,
-       GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
-       GPIO2A3_GPIO            = 0,
-       GPIO2A3_NAND_RDN,
-       GPIO2A4_SPI1_CSN1,
-
-       GPIO2A2_SHIFT           = 4,
-       GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
-       GPIO2A2_GPIO            = 0,
-       GPIO2A2_NAND_WRN,
-       GPIO2A4_SPI1_CSN0,
-
-       GPIO2A1_SHIFT           = 2,
-       GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
-       GPIO2A1_GPIO            = 0,
-       GPIO2A1_NAND_CLE,
-       GPIO2A1_SPI1_TXD,
-
-       GPIO2A0_SHIFT           = 0,
-       GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
-       GPIO2A0_GPIO            = 0,
-       GPIO2A0_NAND_ALE,
-       GPIO2A0_SPI1_RXD,
-};
-
-/* GRF_GPIO2B_IOMUX */
-enum {
-       GPIO2B7_SHIFT           = 14,
-       GPIO2B7_MASK            = 3 << GPIO2B7_SHIFT,
-       GPIO2B7_GPIO            = 0,
-       GPIO2B7_GMAC_RXER,
-
-       GPIO2B6_SHIFT           = 12,
-       GPIO2B6_MASK            = 3 << GPIO2B6_SHIFT,
-       GPIO2B6_GPIO            = 0,
-       GPIO2B6_GMAC_CLK,
-       GPIO2B6_MAC_LINK,
-
-       GPIO2B5_SHIFT           = 10,
-       GPIO2B5_MASK            = 3 << GPIO2B5_SHIFT,
-       GPIO2B5_GPIO            = 0,
-       GPIO2B5_GMAC_TXEN,
-
-       GPIO2B4_SHIFT           = 8,
-       GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
-       GPIO2B4_GPIO            = 0,
-       GPIO2B4_GMAC_MDIO,
-
-       GPIO2B3_SHIFT           = 6,
-       GPIO2B3_MASK            = 3 << GPIO2B3_SHIFT,
-       GPIO2B3_GPIO            = 0,
-       GPIO2B3_GMAC_RXCLK,
-
-       GPIO2B2_SHIFT           = 4,
-       GPIO2B2_MASK            = 3 << GPIO2B2_SHIFT,
-       GPIO2B2_GPIO            = 0,
-       GPIO2B2_GMAC_CRS,
-
-       GPIO2B1_SHIFT           = 2,
-       GPIO2B1_MASK            = 3 << GPIO2B1_SHIFT,
-       GPIO2B1_GPIO            = 0,
-       GPIO2B1_GMAC_TXCLK,
-
-
-       GPIO2B0_SHIFT           = 0,
-       GPIO2B0_MASK            = 3 << GPIO2B0_SHIFT,
-       GPIO2B0_GPIO            = 0,
-       GPIO2B0_GMAC_RXDV,
-       GPIO2B0_MAC_SPEED_IOUT,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
-       GPIO2C7_SHIFT           = 14,
-       GPIO2C7_MASK            = 3 << GPIO2C7_SHIFT,
-       GPIO2C7_GPIO            = 0,
-       GPIO2C7_GMAC_TXD3,
-
-       GPIO2C6_SHIFT           = 12,
-       GPIO2C6_MASK            = 3 << GPIO2C6_SHIFT,
-       GPIO2C6_GPIO            = 0,
-       GPIO2C6_GMAC_TXD2,
-
-       GPIO2C5_SHIFT           = 10,
-       GPIO2C5_MASK            = 3 << GPIO2C5_SHIFT,
-       GPIO2C5_GPIO            = 0,
-       GPIO2C5_I2C2_SCL,
-       GPIO2C5_GMAC_RXD2,
-
-       GPIO2C4_SHIFT           = 8,
-       GPIO2C4_MASK            = 3 << GPIO2C4_SHIFT,
-       GPIO2C4_GPIO            = 0,
-       GPIO2C4_I2C2_SDA,
-       GPIO2C4_GMAC_RXD3,
-
-       GPIO2C3_SHIFT           = 6,
-       GPIO2C3_MASK            = 3 << GPIO2C3_SHIFT,
-       GPIO2C3_GPIO            = 0,
-       GPIO2C3_GMAC_TXD0,
-
-       GPIO2C2_SHIFT           = 4,
-       GPIO2C2_MASK            = 3 << GPIO2C2_SHIFT,
-       GPIO2C2_GPIO            = 0,
-       GPIO2C2_GMAC_TXD1,
-
-       GPIO2C1_SHIFT           = 2,
-       GPIO2C1_MASK            = 3 << GPIO2C1_SHIFT,
-       GPIO2C1_GPIO            = 0,
-       GPIO2C1_GMAC_RXD0,
-
-       GPIO2C0_SHIFT           = 0,
-       GPIO2C0_MASK            = 3 << GPIO2C0_SHIFT,
-       GPIO2C0_GPIO            = 0,
-       GPIO2C0_GMAC_RXD1,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
-       GPIO2D1_SHIFT           = 2,
-       GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
-       GPIO2D1_GPIO            = 0,
-       GPIO2D1_GMAC_MDC,
-
-       GPIO2D0_SHIFT           = 0,
-       GPIO2D0_MASK            = 3,
-       GPIO2D0_GPIO            = 0,
-       GPIO2D0_GMAC_COL,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
-       GPIO3C6_SHIFT           = 12,
-       GPIO3C6_MASK            = 3 << GPIO3C6_SHIFT,
-       GPIO3C6_GPIO            = 0,
-       GPIO3C6_DRV_VBUS1,
-
-       GPIO3C5_SHIFT           = 10,
-       GPIO3C5_MASK            = 3 << GPIO3C5_SHIFT,
-       GPIO3C5_GPIO            = 0,
-       GPIO3C5_PWM10,
-
-       GPIO3C1_SHIFT           = 2,
-       GPIO3C1_MASK            = 3 << GPIO3C1_SHIFT,
-       GPIO3C1_GPIO            = 0,
-       GPIO3C1_DRV_VBUS,
-};
-
-/* GRF_GPIO3D_IOMUX */
-enum {
-       GPIO3D2_SHIFT   = 4,
-       GPIO3D2_MASK    = 3 << GPIO3D2_SHIFT,
-       GPIO3D2_GPIO    = 0,
-       GPIO3D2_PWM3,
-};
-
-/* GRF_CON_IOMUX */
-enum {
-       CON_IOMUX_GMAC_SHIFT            = 15,
-       CON_IOMUX_GMAC_MASK     = 1 << CON_IOMUX_GMAC_SHIFT,
-       CON_IOMUX_UART1SEL_SHIFT        = 11,
-       CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
-       CON_IOMUX_UART2SEL_SHIFT        = 8,
-       CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
-       CON_IOMUX_UART2SEL_2    = 0,
-       CON_IOMUX_UART2SEL_21,
-       CON_IOMUX_EMMCSEL_SHIFT = 7,
-       CON_IOMUX_EMMCSEL_MASK  = 1 << CON_IOMUX_EMMCSEL_SHIFT,
-       CON_IOMUX_PWM3SEL_SHIFT = 3,
-       CON_IOMUX_PWM3SEL_MASK  = 1 << CON_IOMUX_PWM3SEL_SHIFT,
-       CON_IOMUX_PWM2SEL_SHIFT = 2,
-       CON_IOMUX_PWM2SEL_MASK  = 1 << CON_IOMUX_PWM2SEL_SHIFT,
-       CON_IOMUX_PWM1SEL_SHIFT = 1,
-       CON_IOMUX_PWM1SEL_MASK  = 1 << CON_IOMUX_PWM1SEL_SHIFT,
-       CON_IOMUX_PWM0SEL_SHIFT = 0,
-       CON_IOMUX_PWM0SEL_MASK  = 1 << CON_IOMUX_PWM0SEL_SHIFT,
-};
-
 /* GRF_MACPHY_CON0 */
 enum {
        MACPHY_CFG_ENABLE_SHIFT = 0,
index 35f4f978c4e37dfbf57ef4d78b43047aec3d0c63..206abfafcd971249c8c1a511b693ffe0e260ce2f 100644 (file)
@@ -30,7 +30,27 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void board_debug_uart_init(void)
 {
-static struct rk322x_grf * const grf = (void *)GRF_BASE;
+       static struct rk322x_grf * const grf = (void *)GRF_BASE;
+       enum {
+               GPIO1B2_SHIFT           = 4,
+               GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
+               GPIO1B2_GPIO            = 0,
+               GPIO1B2_UART1_SIN,
+               GPIO1B2_UART21_SIN,
+
+               GPIO1B1_SHIFT           = 2,
+               GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
+               GPIO1B1_GPIO            = 0,
+               GPIO1B1_UART1_SOUT,
+               GPIO1B1_UART21_SOUT,
+       };
+       enum {
+               CON_IOMUX_UART2SEL_SHIFT= 8,
+               CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+               CON_IOMUX_UART2SEL_2    = 0,
+               CON_IOMUX_UART2SEL_21,
+       };
+
        /* Enable early UART2 channel 1 on the RK322x */
        rk_clrsetreg(&grf->gpio1b_iomux,
                     GPIO1B1_MASK | GPIO1B2_MASK,
index e71847de8799b4d1bc2bdff26e634c381b8455a5..8642a903359134eb6bb51807eff4698bb5137427 100644 (file)
@@ -34,6 +34,24 @@ int board_init(void)
        /* Enable early UART2 channel 1 on the RK322x */
 #define GRF_BASE       0x11000000
        struct rk322x_grf * const grf = (void *)GRF_BASE;
+       enum {
+               GPIO1B2_SHIFT           = 4,
+               GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
+               GPIO1B2_GPIO            = 0,
+               GPIO1B2_UART21_SIN,
+
+               GPIO1B1_SHIFT           = 2,
+               GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
+               GPIO1B1_GPIO            = 0,
+               GPIO1B1_UART1_SOUT,
+               GPIO1B1_UART21_SOUT,
+       };
+       enum {
+               CON_IOMUX_UART2SEL_SHIFT= 8,
+               CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+               CON_IOMUX_UART2SEL_2    = 0,
+               CON_IOMUX_UART2SEL_21,
+       };
 
        rk_clrsetreg(&grf->gpio1b_iomux,
                     GPIO1B1_MASK | GPIO1B2_MASK,
index 576b03739fa845b93eecae1ba56bd1b30fbe7836..28d999633bcef7a9a6a63131c1ab428a087ceecc 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* GRF_GPIO0A_IOMUX */
+enum {
+       GPIO0A7_SHIFT           = 14,
+       GPIO0A7_MASK            = 3 << GPIO0A7_SHIFT,
+       GPIO0A7_GPIO            = 0,
+       GPIO0A7_I2C3_SDA,
+       GPIO0A7_HDMI_DDCSDA,
+
+       GPIO0A6_SHIFT           = 12,
+       GPIO0A6_MASK            = 3 << GPIO0A6_SHIFT,
+       GPIO0A6_GPIO            = 0,
+       GPIO0A6_I2C3_SCL,
+       GPIO0A6_HDMI_DDCSCL,
+
+       GPIO0A3_SHIFT           = 6,
+       GPIO0A3_MASK            = 3 << GPIO0A3_SHIFT,
+       GPIO0A3_GPIO            = 0,
+       GPIO0A3_I2C1_SDA,
+       GPIO0A3_SDIO_CMD,
+
+       GPIO0A2_SHIFT           = 4,
+       GPIO0A2_MASK            = 3 << GPIO0A2_SHIFT,
+       GPIO0A2_GPIO            = 0,
+       GPIO0A2_I2C1_SCL,
+
+       GPIO0A1_SHIFT           = 2,
+       GPIO0A1_MASK            = 3 << GPIO0A1_SHIFT,
+       GPIO0A1_GPIO            = 0,
+       GPIO0A1_I2C0_SDA,
+
+       GPIO0A0_SHIFT           = 0,
+       GPIO0A0_MASK            = 3 << GPIO0A0_SHIFT,
+       GPIO0A0_GPIO            = 0,
+       GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+       GPIO0B7_SHIFT           = 14,
+       GPIO0B7_MASK            = 3 << GPIO0B7_SHIFT,
+       GPIO0B7_GPIO            = 0,
+       GPIO0B7_HDMI_HDP,
+
+       GPIO0B6_SHIFT           = 12,
+       GPIO0B6_MASK            = 3 << GPIO0B6_SHIFT,
+       GPIO0B6_GPIO            = 0,
+       GPIO0B6_I2S_SDI,
+       GPIO0B6_SPI_CSN0,
+
+       GPIO0B5_SHIFT           = 10,
+       GPIO0B5_MASK            = 3 << GPIO0B5_SHIFT,
+       GPIO0B5_GPIO            = 0,
+       GPIO0B5_I2S_SDO,
+       GPIO0B5_SPI_RXD,
+
+       GPIO0B3_SHIFT           = 6,
+       GPIO0B3_MASK            = 3 << GPIO0B3_SHIFT,
+       GPIO0B3_GPIO            = 0,
+       GPIO0B3_I2S1_LRCKRX,
+       GPIO0B3_SPI_TXD,
+
+       GPIO0B1_SHIFT           = 2,
+       GPIO0B1_MASK            = 3 << GPIO0B1_SHIFT,
+       GPIO0B1_GPIO            = 0,
+       GPIO0B1_I2S_SCLK,
+       GPIO0B1_SPI_CLK,
+
+       GPIO0B0_SHIFT           = 0,
+       GPIO0B0_MASK            = 3,
+       GPIO0B0_GPIO            = 0,
+       GPIO0B0_I2S_MCLK,
+};
+
+/* GRF_GPIO0C_IOMUX */
+enum {
+       GPIO0C4_SHIFT           = 8,
+       GPIO0C4_MASK            = 3 << GPIO0C4_SHIFT,
+       GPIO0C4_GPIO            = 0,
+       GPIO0C4_HDMI_CECSDA,
+
+       GPIO0C1_SHIFT           = 2,
+       GPIO0C1_MASK            = 3 << GPIO0C1_SHIFT,
+       GPIO0C1_GPIO            = 0,
+       GPIO0C1_UART0_RSTN,
+       GPIO0C1_CLK_OUT1,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+       GPIO0D6_SHIFT           = 12,
+       GPIO0D6_MASK            = 3 << GPIO0D6_SHIFT,
+       GPIO0D6_GPIO            = 0,
+       GPIO0D6_SDIO_PWREN,
+       GPIO0D6_PWM11,
+
+       GPIO0D4_SHIFT           = 8,
+       GPIO0D4_MASK            = 3 << GPIO0D4_SHIFT,
+       GPIO0D4_GPIO            = 0,
+       GPIO0D4_PWM2,
+
+       GPIO0D3_SHIFT           = 6,
+       GPIO0D3_MASK            = 3 << GPIO0D3_SHIFT,
+       GPIO0D3_GPIO            = 0,
+       GPIO0D3_PWM1,
+
+       GPIO0D2_SHIFT           = 4,
+       GPIO0D2_MASK            = 3 << GPIO0D2_SHIFT,
+       GPIO0D2_GPIO            = 0,
+       GPIO0D2_PWM0,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+       GPIO1A7_SHIFT           = 14,
+       GPIO1A7_MASK            = 1,
+       GPIO1A7_GPIO            = 0,
+       GPIO1A7_SDMMC_WRPRT,
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+       GPIO1B7_SHIFT           = 14,
+       GPIO1B7_MASK            = 3 << GPIO1B7_SHIFT,
+       GPIO1B7_GPIO            = 0,
+       GPIO1B7_SDMMC_CMD,
+
+       GPIO1B6_SHIFT           = 12,
+       GPIO1B6_MASK            = 3 << GPIO1B6_SHIFT,
+       GPIO1B6_GPIO            = 0,
+       GPIO1B6_SDMMC_PWREN,
+
+       GPIO1B4_SHIFT           = 8,
+       GPIO1B4_MASK            = 3 << GPIO1B4_SHIFT,
+       GPIO1B4_GPIO            = 0,
+       GPIO1B4_SPI_CSN1,
+       GPIO1B4_PWM12,
+
+       GPIO1B3_SHIFT           = 6,
+       GPIO1B3_MASK            = 3 << GPIO1B3_SHIFT,
+       GPIO1B3_GPIO            = 0,
+       GPIO1B3_UART1_RSTN,
+       GPIO1B3_PWM13,
+
+       GPIO1B2_SHIFT           = 4,
+       GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
+       GPIO1B2_GPIO            = 0,
+       GPIO1B2_UART1_SIN,
+       GPIO1B2_UART21_SIN,
+
+       GPIO1B1_SHIFT           = 2,
+       GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
+       GPIO1B1_GPIO            = 0,
+       GPIO1B1_UART1_SOUT,
+       GPIO1B1_UART21_SOUT,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+       GPIO1C7_SHIFT           = 14,
+       GPIO1C7_MASK            = 3 << GPIO1C7_SHIFT,
+       GPIO1C7_GPIO            = 0,
+       GPIO1C7_NAND_CS3,
+       GPIO1C7_EMMC_RSTNOUT,
+
+       GPIO1C6_SHIFT           = 12,
+       GPIO1C6_MASK            = 3 << GPIO1C6_SHIFT,
+       GPIO1C6_GPIO            = 0,
+       GPIO1C6_NAND_CS2,
+       GPIO1C6_EMMC_CMD,
+
+       GPIO1C5_SHIFT           = 10,
+       GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
+       GPIO1C5_GPIO            = 0,
+       GPIO1C5_SDMMC_D3,
+       GPIO1C5_JTAG_TMS,
+
+       GPIO1C4_SHIFT           = 8,
+       GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
+       GPIO1C4_GPIO            = 0,
+       GPIO1C4_SDMMC_D2,
+       GPIO1C4_JTAG_TCK,
+
+       GPIO1C3_SHIFT           = 6,
+       GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
+       GPIO1C3_GPIO            = 0,
+       GPIO1C3_SDMMC_D1,
+       GPIO1C3_UART2_SIN,
+
+       GPIO1C2_SHIFT           = 4,
+       GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT,
+       GPIO1C2_GPIO            = 0,
+       GPIO1C2_SDMMC_D0,
+       GPIO1C2_UART2_SOUT,
+
+       GPIO1C1_SHIFT           = 2,
+       GPIO1C1_MASK            = 3 << GPIO1C1_SHIFT,
+       GPIO1C1_GPIO            = 0,
+       GPIO1C1_SDMMC_DETN,
+
+       GPIO1C0_SHIFT           = 0,
+       GPIO1C0_MASK            = 3 << GPIO1C0_SHIFT,
+       GPIO1C0_GPIO            = 0,
+       GPIO1C0_SDMMC_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+       GPIO1D7_SHIFT           = 14,
+       GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
+       GPIO1D7_GPIO            = 0,
+       GPIO1D7_NAND_D7,
+       GPIO1D7_EMMC_D7,
+
+       GPIO1D6_SHIFT           = 12,
+       GPIO1D6_MASK            = 3 << GPIO1D6_SHIFT,
+       GPIO1D6_GPIO            = 0,
+       GPIO1D6_NAND_D6,
+       GPIO1D6_EMMC_D6,
+
+       GPIO1D5_SHIFT           = 10,
+       GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
+       GPIO1D5_GPIO            = 0,
+       GPIO1D5_NAND_D5,
+       GPIO1D5_EMMC_D5,
+
+       GPIO1D4_SHIFT           = 8,
+       GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
+       GPIO1D4_GPIO            = 0,
+       GPIO1D4_NAND_D4,
+       GPIO1D4_EMMC_D4,
+
+       GPIO1D3_SHIFT           = 6,
+       GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
+       GPIO1D3_GPIO            = 0,
+       GPIO1D3_NAND_D3,
+       GPIO1D3_EMMC_D3,
+
+       GPIO1D2_SHIFT           = 4,
+       GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
+       GPIO1D2_GPIO            = 0,
+       GPIO1D2_NAND_D2,
+       GPIO1D2_EMMC_D2,
+
+       GPIO1D1_SHIFT           = 2,
+       GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
+       GPIO1D1_GPIO            = 0,
+       GPIO1D1_NAND_D1,
+       GPIO1D1_EMMC_D1,
+
+       GPIO1D0_SHIFT           = 0,
+       GPIO1D0_MASK            = 3 << GPIO1D0_SHIFT,
+       GPIO1D0_GPIO            = 0,
+       GPIO1D0_NAND_D0,
+       GPIO1D0_EMMC_D0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+       GPIO2A7_SHIFT           = 14,
+       GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
+       GPIO2A7_GPIO            = 0,
+       GPIO2A7_NAND_DQS,
+       GPIO2A7_EMMC_CLKOUT,
+
+       GPIO2A5_SHIFT           = 10,
+       GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
+       GPIO2A5_GPIO            = 0,
+       GPIO2A5_NAND_WP,
+       GPIO2A5_EMMC_PWREN,
+
+       GPIO2A4_SHIFT           = 8,
+       GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
+       GPIO2A4_GPIO            = 0,
+       GPIO2A4_NAND_RDY,
+       GPIO2A4_EMMC_CMD,
+
+       GPIO2A3_SHIFT           = 6,
+       GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
+       GPIO2A3_GPIO            = 0,
+       GPIO2A3_NAND_RDN,
+       GPIO2A4_SPI1_CSN1,
+
+       GPIO2A2_SHIFT           = 4,
+       GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
+       GPIO2A2_GPIO            = 0,
+       GPIO2A2_NAND_WRN,
+       GPIO2A4_SPI1_CSN0,
+
+       GPIO2A1_SHIFT           = 2,
+       GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
+       GPIO2A1_GPIO            = 0,
+       GPIO2A1_NAND_CLE,
+       GPIO2A1_SPI1_TXD,
+
+       GPIO2A0_SHIFT           = 0,
+       GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
+       GPIO2A0_GPIO            = 0,
+       GPIO2A0_NAND_ALE,
+       GPIO2A0_SPI1_RXD,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+       GPIO2B7_SHIFT           = 14,
+       GPIO2B7_MASK            = 3 << GPIO2B7_SHIFT,
+       GPIO2B7_GPIO            = 0,
+       GPIO2B7_GMAC_RXER,
+
+       GPIO2B6_SHIFT           = 12,
+       GPIO2B6_MASK            = 3 << GPIO2B6_SHIFT,
+       GPIO2B6_GPIO            = 0,
+       GPIO2B6_GMAC_CLK,
+       GPIO2B6_MAC_LINK,
+
+       GPIO2B5_SHIFT           = 10,
+       GPIO2B5_MASK            = 3 << GPIO2B5_SHIFT,
+       GPIO2B5_GPIO            = 0,
+       GPIO2B5_GMAC_TXEN,
+
+       GPIO2B4_SHIFT           = 8,
+       GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
+       GPIO2B4_GPIO            = 0,
+       GPIO2B4_GMAC_MDIO,
+
+       GPIO2B3_SHIFT           = 6,
+       GPIO2B3_MASK            = 3 << GPIO2B3_SHIFT,
+       GPIO2B3_GPIO            = 0,
+       GPIO2B3_GMAC_RXCLK,
+
+       GPIO2B2_SHIFT           = 4,
+       GPIO2B2_MASK            = 3 << GPIO2B2_SHIFT,
+       GPIO2B2_GPIO            = 0,
+       GPIO2B2_GMAC_CRS,
+
+       GPIO2B1_SHIFT           = 2,
+       GPIO2B1_MASK            = 3 << GPIO2B1_SHIFT,
+       GPIO2B1_GPIO            = 0,
+       GPIO2B1_GMAC_TXCLK,
+
+       GPIO2B0_SHIFT           = 0,
+       GPIO2B0_MASK            = 3 << GPIO2B0_SHIFT,
+       GPIO2B0_GPIO            = 0,
+       GPIO2B0_GMAC_RXDV,
+       GPIO2B0_MAC_SPEED_IOUT,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+       GPIO2C7_SHIFT           = 14,
+       GPIO2C7_MASK            = 3 << GPIO2C7_SHIFT,
+       GPIO2C7_GPIO            = 0,
+       GPIO2C7_GMAC_TXD3,
+
+       GPIO2C6_SHIFT           = 12,
+       GPIO2C6_MASK            = 3 << GPIO2C6_SHIFT,
+       GPIO2C6_GPIO            = 0,
+       GPIO2C6_GMAC_TXD2,
+
+       GPIO2C5_SHIFT           = 10,
+       GPIO2C5_MASK            = 3 << GPIO2C5_SHIFT,
+       GPIO2C5_GPIO            = 0,
+       GPIO2C5_I2C2_SCL,
+       GPIO2C5_GMAC_RXD2,
+
+       GPIO2C4_SHIFT           = 8,
+       GPIO2C4_MASK            = 3 << GPIO2C4_SHIFT,
+       GPIO2C4_GPIO            = 0,
+       GPIO2C4_I2C2_SDA,
+       GPIO2C4_GMAC_RXD3,
+
+       GPIO2C3_SHIFT           = 6,
+       GPIO2C3_MASK            = 3 << GPIO2C3_SHIFT,
+       GPIO2C3_GPIO            = 0,
+       GPIO2C3_GMAC_TXD0,
+
+       GPIO2C2_SHIFT           = 4,
+       GPIO2C2_MASK            = 3 << GPIO2C2_SHIFT,
+       GPIO2C2_GPIO            = 0,
+       GPIO2C2_GMAC_TXD1,
+
+       GPIO2C1_SHIFT           = 2,
+       GPIO2C1_MASK            = 3 << GPIO2C1_SHIFT,
+       GPIO2C1_GPIO            = 0,
+       GPIO2C1_GMAC_RXD0,
+
+       GPIO2C0_SHIFT           = 0,
+       GPIO2C0_MASK            = 3 << GPIO2C0_SHIFT,
+       GPIO2C0_GPIO            = 0,
+       GPIO2C0_GMAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+       GPIO2D1_SHIFT           = 2,
+       GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
+       GPIO2D1_GPIO            = 0,
+       GPIO2D1_GMAC_MDC,
+
+       GPIO2D0_SHIFT           = 0,
+       GPIO2D0_MASK            = 3,
+       GPIO2D0_GPIO            = 0,
+       GPIO2D0_GMAC_COL,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+       GPIO3C6_SHIFT           = 12,
+       GPIO3C6_MASK            = 3 << GPIO3C6_SHIFT,
+       GPIO3C6_GPIO            = 0,
+       GPIO3C6_DRV_VBUS1,
+
+       GPIO3C5_SHIFT           = 10,
+       GPIO3C5_MASK            = 3 << GPIO3C5_SHIFT,
+       GPIO3C5_GPIO            = 0,
+       GPIO3C5_PWM10,
+
+       GPIO3C1_SHIFT           = 2,
+       GPIO3C1_MASK            = 3 << GPIO3C1_SHIFT,
+       GPIO3C1_GPIO            = 0,
+       GPIO3C1_DRV_VBUS,
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+       GPIO3D2_SHIFT   = 4,
+       GPIO3D2_MASK    = 3 << GPIO3D2_SHIFT,
+       GPIO3D2_GPIO    = 0,
+       GPIO3D2_PWM3,
+};
+
+/* GRF_CON_IOMUX */
+enum {
+       CON_IOMUX_GMACSEL_SHIFT = 15,
+       CON_IOMUX_GMACSEL_MASK  = 1 << CON_IOMUX_GMACSEL_SHIFT,
+       CON_IOMUX_GMACSEL_1     = 1,
+       CON_IOMUX_UART1SEL_SHIFT        = 11,
+       CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
+       CON_IOMUX_UART2SEL_SHIFT        = 8,
+       CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+       CON_IOMUX_UART2SEL_2    = 0,
+       CON_IOMUX_UART2SEL_21,
+       CON_IOMUX_EMMCSEL_SHIFT = 7,
+       CON_IOMUX_EMMCSEL_MASK  = 1 << CON_IOMUX_EMMCSEL_SHIFT,
+       CON_IOMUX_PWM3SEL_SHIFT = 3,
+       CON_IOMUX_PWM3SEL_MASK  = 1 << CON_IOMUX_PWM3SEL_SHIFT,
+       CON_IOMUX_PWM2SEL_SHIFT = 2,
+       CON_IOMUX_PWM2SEL_MASK  = 1 << CON_IOMUX_PWM2SEL_SHIFT,
+       CON_IOMUX_PWM1SEL_SHIFT = 1,
+       CON_IOMUX_PWM1SEL_MASK  = 1 << CON_IOMUX_PWM1SEL_SHIFT,
+       CON_IOMUX_PWM0SEL_SHIFT = 0,
+       CON_IOMUX_PWM0SEL_MASK  = 1 << CON_IOMUX_PWM0SEL_SHIFT,
+};
+
 struct rk322x_pinctrl_priv {
        struct rk322x_grf *grf;
 };