git.sur5r.net Git - openocd/blob - src/target/arm720t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "arm720t.h"
  28 #include "time_support.h"
  29 #include "target_type.h"
  30 #include "register.h"
  31
  32
  33 /*
  34  * ARM720 is an ARM7TDMI-S with MMU and ETM7.  For information, see
  35  * ARM DDI 0229C especially Chapter 9 about debug support.
  36  */
  37
  38 #if 0
  39 #define _DEBUG_INSTRUCTION_EXECUTION_
  40 #endif
  41
  42 static int arm720t_scan_cp15(struct target *target,
  43                 uint32_t out, uint32_t *in, int instruction, int clock)
  44 {
  45         int retval;
  46         struct arm720t_common *arm720t = target_to_arm720(target);
  47         struct arm_jtag *jtag_info;
  48         struct scan_field fields[2];
  49         uint8_t out_buf[4];
  50         uint8_t instruction_buf = instruction;
  51
  52         jtag_info = &arm720t->arm7_9_common.jtag_info;
  53
  54         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  55
  56         jtag_set_end_state(TAP_DRPAUSE);
  57         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  58         {
  59                 return retval;
  60         }
  61         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
  62         {
  63                 return retval;
  64         }
  65
  66         fields[0].tap = jtag_info->tap;
  67         fields[0].num_bits = 1;
  68         fields[0].out_value = &instruction_buf;
  69         fields[0].in_value = NULL;
  70
  71         fields[1].tap = jtag_info->tap;
  72         fields[1].num_bits = 32;
  73         fields[1].out_value = out_buf;
  74         fields[1].in_value = NULL;
  75
  76         if (in)
  77         {
  78                 fields[1].in_value = (uint8_t *)in;
  79                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
  80                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
  81         } else
  82         {
  83                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
  84         }
  85
  86         if (clock)
  87                 jtag_add_runtest(0, jtag_get_end_state());
  88
  89 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  90         if ((retval = jtag_execute_queue()) != ERROR_OK)
  91         {
  92                 return retval;
  93         }
  94
  95         if (in)
  96                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  97         else
  98                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
  99 #else
 100                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
 101 #endif
 102
 103         return ERROR_OK;
 104 }
 105
 106 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
 107 {
 108         /* fetch CP15 opcode */
 109         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 110         /* "DECODE" stage */
 111         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 112         /* "EXECUTE" stage (1) */
 113         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 114         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 115         /* "EXECUTE" stage (2) */
 116         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 117         /* "EXECUTE" stage (3), CDATA is read */
 118         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 119
 120         return ERROR_OK;
 121 }
 122
 123 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
 124 {
 125         /* fetch CP15 opcode */
 126         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 127         /* "DECODE" stage */
 128         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 129         /* "EXECUTE" stage (1) */
 130         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 131         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 132         /* "EXECUTE" stage (2) */
 133         arm720t_scan_cp15(target, value, NULL, 0, 1);
 134         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 135
 136         return ERROR_OK;
 137 }
 138
 139 static uint32_t arm720t_get_ttb(struct target *target)
 140 {
 141         uint32_t ttb = 0x0;
 142
 143         arm720t_read_cp15(target, 0xee120f10, &ttb);
 144         jtag_execute_queue();
 145
 146         ttb &= 0xffffc000;
 147
 148         return ttb;
 149 }
 150
 151 static void arm720t_disable_mmu_caches(struct target *target,
 152                 int mmu, int d_u_cache, int i_cache)
 153 {
 154         uint32_t cp15_control;
 155
 156         /* read cp15 control register */
 157         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 158         jtag_execute_queue();
 159
 160         if (mmu)
 161                 cp15_control &= ~0x1U;
 162
 163         if (d_u_cache || i_cache)
 164                 cp15_control &= ~0x4U;
 165
 166         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 167 }
 168
 169 static void arm720t_enable_mmu_caches(struct target *target,
 170                 int mmu, int d_u_cache, int i_cache)
 171 {
 172         uint32_t cp15_control;
 173
 174         /* read cp15 control register */
 175         arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 176         jtag_execute_queue();
 177
 178         if (mmu)
 179                 cp15_control |= 0x1U;
 180
 181         if (d_u_cache || i_cache)
 182                 cp15_control |= 0x4U;
 183
 184         arm720t_write_cp15(target, 0xee010f10, cp15_control);
 185 }
 186
 187 static void arm720t_post_debug_entry(struct target *target)
 188 {
 189         struct arm720t_common *arm720t = target_to_arm720(target);
 190
 191         /* examine cp15 control reg */
 192         arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 193         jtag_execute_queue();
 194         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 195
 196         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 197         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 198         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 199
 200         /* save i/d fault status and address register */
 201         arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 202         arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 203         jtag_execute_queue();
 204 }
 205
 206 static void arm720t_pre_restore_context(struct target *target)
 207 {
 208         struct arm720t_common *arm720t = target_to_arm720(target);
 209
 210         /* restore i/d fault status and address register */
 211         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 212         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 213 }
 214
 215 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 216                 struct arm720t_common *arm720t)
 217 {
 218         if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
 219                 command_print(cmd_ctx, "target is not an ARM720");
 220                 return ERROR_TARGET_INVALID;
 221         }
 222         return ERROR_OK;
 223 }
 224
 225 static int arm720t_arch_state(struct target *target)
 226 {
 227         struct arm720t_common *arm720t = target_to_arm720(target);
 228         struct arm *armv4_5;
 229
 230         static const char *state[] =
 231         {
 232                 "disabled", "enabled"
 233         };
 234
 235         armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 236
 237         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 238                         "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 239                         "MMU: %s, Cache: %s",
 240                          armv4_5_state_strings[armv4_5->core_state],
 241                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 242                          arm_mode_name(armv4_5->core_mode),
 243                          buf_get_u32(armv4_5->cpsr->value, 0, 32),
 244                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 245                          state[arm720t->armv4_5_mmu.mmu_enabled],
 246                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 247
 248         return ERROR_OK;
 249 }
 250
 251 static int arm720_mmu(struct target *target, int *enabled)
 252 {
 253         if (target->state != TARGET_HALTED) {
 254                 LOG_ERROR("%s: target not halted", __func__);
 255                 return ERROR_TARGET_INVALID;
 256         }
 257
 258         *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
 259         return ERROR_OK;
 260 }
 261
 262 static int arm720_virt2phys(struct target *target,
 263                 uint32_t virt, uint32_t *phys)
 264 {
 265         /** @todo Implement this!  */
 266         LOG_ERROR("%s: not implemented", __func__);
 267         return ERROR_FAIL;
 268 }
 269
 270 static int arm720t_read_memory(struct target *target,
 271                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 272 {
 273         int retval;
 274         struct arm720t_common *arm720t = target_to_arm720(target);
 275
 276         /* disable cache, but leave MMU enabled */
 277         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 278                 arm720t_disable_mmu_caches(target, 0, 1, 0);
 279
 280         retval = arm7_9_read_memory(target, address, size, count, buffer);
 281
 282         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 283                 arm720t_enable_mmu_caches(target, 0, 1, 0);
 284
 285         return retval;
 286 }
 287
 288 static int arm720t_read_phys_memory(struct target *target,
 289                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 290 {
 291         struct arm720t_common *arm720t = target_to_arm720(target);
 292
 293         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 294 }
 295
 296 static int arm720t_write_phys_memory(struct target *target,
 297                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 298 {
 299         struct arm720t_common *arm720t = target_to_arm720(target);
 300
 301         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 302 }
 303
 304 static int arm720t_soft_reset_halt(struct target *target)
 305 {
 306         int retval = ERROR_OK;
 307         struct arm720t_common *arm720t = target_to_arm720(target);
 308         struct reg *dbg_stat = &arm720t->arm7_9_common
 309                         .eice_cache->reg_list[EICE_DBG_STAT];
 310         struct arm *armv4_5 = &arm720t->arm7_9_common
 311                         .armv4_5_common;
 312
 313         if ((retval = target_halt(target)) != ERROR_OK)
 314         {
 315                 return retval;
 316         }
 317
 318         long long then = timeval_ms();
 319         int timeout;
 320         while (!(timeout = ((timeval_ms()-then) > 1000)))
 321         {
 322                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 323                 {
 324                         embeddedice_read_reg(dbg_stat);
 325                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 326                         {
 327                                 return retval;
 328                         }
 329                 } else
 330                 {
 331                         break;
 332                 }
 333                 if (debug_level >= 3)
 334                 {
 335                         alive_sleep(100);
 336                 } else
 337                 {
 338                         keep_alive();
 339                 }
 340         }
 341         if (timeout)
 342         {
 343                 LOG_ERROR("Failed to halt CPU after 1 sec");
 344                 return ERROR_TARGET_TIMEOUT;
 345         }
 346
 347         target->state = TARGET_HALTED;
 348
 349         /* SVC, ARM state, IRQ and FIQ disabled */
 350         uint32_t cpsr;
 351
 352         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
 353         cpsr &= ~0xff;
 354         cpsr |= 0xd3;
 355         arm_set_cpsr(armv4_5, cpsr);
 356         armv4_5->cpsr->dirty = 1;
 357
 358         /* start fetching from 0x0 */
 359         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 360         armv4_5->core_cache->reg_list[15].dirty = 1;
 361         armv4_5->core_cache->reg_list[15].valid = 1;
 362
 363         arm720t_disable_mmu_caches(target, 1, 1, 1);
 364         arm720t->armv4_5_mmu.mmu_enabled = 0;
 365         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 366         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 367
 368         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 369         {
 370                 return retval;
 371         }
 372
 373         return ERROR_OK;
 374 }
 375
 376 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
 377 {
 378         return arm7tdmi_init_target(cmd_ctx, target);
 379 }
 380
 381 /* FIXME remove forward decls */
 382 static int arm720t_mrc(struct target *target, int cpnum,
 383                 uint32_t op1, uint32_t op2,
 384                 uint32_t CRn, uint32_t CRm,
 385                 uint32_t *value);
 386 static int arm720t_mcr(struct target *target, int cpnum,
 387                 uint32_t op1, uint32_t op2,
 388                 uint32_t CRn, uint32_t CRm,
 389                 uint32_t value);
 390
 391 static int arm720t_init_arch_info(struct target *target,
 392                 struct arm720t_common *arm720t, struct jtag_tap *tap)
 393 {
 394         struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
 395
 396         arm7_9->armv4_5_common.mrc = arm720t_mrc;
 397         arm7_9->armv4_5_common.mcr = arm720t_mcr;
 398
 399         arm7tdmi_init_arch_info(target, arm7_9, tap);
 400
 401         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 402
 403         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 404         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 405
 406         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 407         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 408         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 409         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 410         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 411         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 412         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 413         arm720t->armv4_5_mmu.mmu_enabled = 0;
 414
 415         return ERROR_OK;
 416 }
 417
 418 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
 419 {
 420         struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
 421
 422         arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
 423         return arm720t_init_arch_info(target, arm720t, target->tap);
 424 }
 425
 426 COMMAND_HANDLER(arm720t_handle_cp15_command)
 427 {
 428         int retval;
 429         struct target *target = get_current_target(CMD_CTX);
 430         struct arm720t_common *arm720t = target_to_arm720(target);
 431         struct arm_jtag *jtag_info;
 432
 433         retval = arm720t_verify_pointer(CMD_CTX, arm720t);
 434         if (retval != ERROR_OK)
 435                 return retval;
 436
 437         jtag_info = &arm720t->arm7_9_common.jtag_info;
 438
 439         if (target->state != TARGET_HALTED)
 440         {
 441                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 442                 return ERROR_OK;
 443         }
 444
 445         /* one or more argument, access a single register (write if second argument is given */
 446         if (CMD_ARGC >= 1)
 447         {
 448                 uint32_t opcode;
 449                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
 450
 451                 if (CMD_ARGC == 1)
 452                 {
 453                         uint32_t value;
 454                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 455                         {
 456                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 457                                 return ERROR_OK;
 458                         }
 459
 460                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 461                         {
 462                                 return retval;
 463                         }
 464
 465                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 466                 }
 467                 else if (CMD_ARGC == 2)
 468                 {
 469                         uint32_t value;
 470                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 471
 472                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 473                         {
 474                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 475                                 return ERROR_OK;
 476                         }
 477                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 478                 }
 479         }
 480
 481         return ERROR_OK;
 482 }
 483
 484 static int arm720t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 485 {
 486         if (cpnum!=15)
 487         {
 488                 LOG_ERROR("Only cp15 is supported");
 489                 return ERROR_FAIL;
 490         }
 491
 492         return arm720t_read_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
 493
 494 }
 495
 496 static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 497 {
 498         if (cpnum!=15)
 499         {
 500                 LOG_ERROR("Only cp15 is supported");
 501                 return ERROR_FAIL;
 502         }
 503
 504         return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
 505 }
 506
 507 static const struct command_registration arm720t_exec_command_handlers[] = {
 508         {
 509                 .name = "cp15",
 510                 .handler = arm720t_handle_cp15_command,
 511                 .mode = COMMAND_EXEC,
 512                 .usage = "<opcode> [value]",
 513                 .help = "display/modify cp15 register",
 514         },
 515         COMMAND_REGISTRATION_DONE
 516 };
 517
 518 static const struct command_registration arm720t_command_handlers[] = {
 519         {
 520                 .chain = arm7_9_command_handlers,
 521         },
 522         {
 523                 .name = "arm720t",
 524                 .mode = COMMAND_ANY,
 525                 .help = "arm720t command group",
 526                 .chain = arm720t_exec_command_handlers,
 527         },
 528         COMMAND_REGISTRATION_DONE
 529 };
 530
 531 /** Holds methods for ARM720 targets. */
 532 struct target_type arm720t_target =
 533 {
 534         .name = "arm720t",
 535
 536         .poll = arm7_9_poll,
 537         .arch_state = arm720t_arch_state,
 538
 539         .halt = arm7_9_halt,
 540         .resume = arm7_9_resume,
 541         .step = arm7_9_step,
 542
 543         .assert_reset = arm7_9_assert_reset,
 544         .deassert_reset = arm7_9_deassert_reset,
 545         .soft_reset_halt = arm720t_soft_reset_halt,
 546
 547         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 548
 549         .read_memory = arm720t_read_memory,
 550         .write_memory = arm7_9_write_memory,
 551         .read_phys_memory = arm720t_read_phys_memory,
 552         .write_phys_memory = arm720t_write_phys_memory,
 553         .mmu = arm720_mmu,
 554         .virt2phys = arm720_virt2phys,
 555
 556         .bulk_write_memory = arm7_9_bulk_write_memory,
 557
 558         .checksum_memory = arm_checksum_memory,
 559         .blank_check_memory = arm_blank_check_memory,
 560
 561         .run_algorithm = armv4_5_run_algorithm,
 562
 563         .add_breakpoint = arm7_9_add_breakpoint,
 564         .remove_breakpoint = arm7_9_remove_breakpoint,
 565         .add_watchpoint = arm7_9_add_watchpoint,
 566         .remove_watchpoint = arm7_9_remove_watchpoint,
 567
 568         .commands = arm720t_command_handlers,
 569         .target_create = arm720t_target_create,
 570         .init_target = arm720t_init_target,
 571         .examine = arm7_9_examine,
 572 };