fsl-layerscape: Consolidate registers space defination for CCI-400 bus

[u-boot] / README

diff --git a/README b/README
index fc40ddfb27604ade74c216aa6328b8bb2a56f5f5..c0c8b559f9bcac54a706cad7f4adf0a70550b1a2 100644 (file)
--- a/README
+++ b/README
@@ -312,6 +312,15 @@ Many of the options are named exactly as the corresponding Linux
 kernel configuration options. The intention is to make it easier to
 build a config tool - later.
 
+- ARM Platform Bus Type(CCI):
+               CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+               provides full cache coherency between two clusters of multi-core
+               CPUs and I/O coherency for devices and I/O masters
+
+               CONFIG_SYS_FSL_HAS_CCI400
+
+               Defined For SoC that has cache coherent interconnect
+               CCN-400
 
 The following options need to be configured:
 
@@ -776,7 +785,7 @@ The following options need to be configured:
                binary in its image. This device tree file should be in the
                board directory and called <soc>-<board>.dts. The binary file
                is then picked up in board_init_f() and made available through
-               the global data structure as gd->blob.
+               the global data structure as gd->fdt_blob.
 
                CONFIG_OF_SEPARATE
                If this variable is defined, U-Boot will build a device tree