fsl-layerscape: Consolidate registers space defination for CCI-400 bus

[u-boot] / arch / arm / cpu / armv7 / ls102xa / Kconfig

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 9ffb90eff945279927fc1c6ace3dc5dc25571824..90d99e6cc30ed05e1b44cd2b6b7b7446e2216774 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
+       select SYS_FSL_HAS_CCI400
        select SYS_FSL_SRDS_1
        select SYS_HAS_SERDES
        select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -14,10 +15,20 @@ config ARCH_LS1021A
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_LE
+       imply SCSI
+       imply CMD_PCI
 
 menu "LS102xA architecture"
        depends on ARCH_LS1021A
 
+config FSL_PCIE_COMPAT
+       string "PCIe compatible of Kernel DT"
+       depends on PCIE_LAYERSCAPE
+       default "fsl,ls1021a-pcie" if ARCH_LS1021A
+       help
+         This compatible is used to find pci controller node in Kernel DT
+         to complete fixup.
+
 config LS1_DEEP_SLEEP
        bool "Deep sleep"
        depends on ARCH_LS1021A
@@ -39,9 +50,20 @@ config SECURE_BOOT
                Enable Freescale Secure Boot feature. Normally selected
                by defconfig. If unsure, do not change.
 
+config SYS_CCI400_OFFSET
+       hex "Offset for CCI400 base"
+       depends on SYS_FSL_HAS_CCI400
+       default 0x180000
+       help
+         Offset for CCI400 base.
+         CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_HAS_CCI400
+       bool
+
 config SYS_FSL_SRDS_1
        bool