fsl-layerscape: Consolidate registers space defination for CCI-400 bus

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / soc.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index c0fd1a616d8a06a27e70a2ba2193e46f98a6a2ee..339ff0c4c708e6047da60d718f54e341a24b3402 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <fsl_immap.h>
 #include <fsl_ifc.h>
 #include <ahci.h>
 #include <scsi.h>
@@ -95,7 +96,7 @@ static void erratum_a008514(void)
 
 static unsigned long get_internval_val_mhz(void)
 {
-       char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
+       char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
        /*
         *  interval is the number of platform cycles(MHz) between
         *  wake up events generated by EPU.
@@ -134,7 +135,7 @@ void erratum_a009635(void)
 
 static void erratum_rcw_src(void)
 {
-#if defined(CONFIG_SPL)
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
        u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
        u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
        u32 val;
@@ -152,6 +153,7 @@ static void erratum_rcw_src(void)
  * This erratum requires setting glitch_en bit to enable
  * digital glitch filter to improve clock stability.
  */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 static void erratum_a009203(void)
 {
        u8 __iomem *ptr;
@@ -178,6 +180,7 @@ static void erratum_a009203(void)
 #endif
 #endif
 }
+#endif
 
 void bypass_smmu(void)
 {
@@ -191,7 +194,9 @@ void fsl_lsch3_early_init_f(void)
 {
        erratum_rcw_src();
        init_early_memctl_regs();       /* tighten IFC timing */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
        erratum_a009203();
+#endif
        erratum_a008514();
        erratum_a008336();
 #ifdef CONFIG_CHAIN_OF_TRUST
@@ -213,13 +218,15 @@ int sata_init(void)
        ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
        ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
        ahci_init((void __iomem *)CONFIG_SYS_SATA1);
-       scsi_scan(0);
+       scsi_scan(false);
 
        return 0;
 }
@@ -231,16 +238,14 @@ int sata_init(void)
 {
        struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
-#ifdef CONFIG_ARCH_LS1046A
        /* Disable SATA ECC */
        out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
-#endif
        out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
        out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
        out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
        ahci_init((void __iomem *)CONFIG_SYS_SATA);
-       scsi_scan(0);
+       scsi_scan(false);
 
        return 0;
 }
@@ -281,9 +286,14 @@ static void erratum_a008850_early(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
        /* part 1 of 2 */
-       struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+                                               CONFIG_SYS_CCI400_OFFSET);
        struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 
+       /* Skip if running at lower exception level */
+       if (current_el() < 3)
+               return;
+
        /* disables propagation of barrier transactions to DDRC from CCI400 */
        out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 
@@ -296,10 +306,15 @@ void erratum_a008850_post(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
        /* part 2 of 2 */
-       struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+                                               CONFIG_SYS_CCI400_OFFSET);
        struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
        u32 tmp;
 
+       /* Skip if running at lower exception level */
+       if (current_el() < 3)
+               return;
+
        /* enable propagation of barrier transactions to DDRC from CCI400 */
        out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 
@@ -427,7 +442,8 @@ int setup_chip_volt(void)
 
 void fsl_lsch2_early_init_f(void)
 {
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+                                       CONFIG_SYS_CCI400_OFFSET);
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
@@ -451,8 +467,10 @@ void fsl_lsch2_early_init_f(void)
         * Enable snoop requests and DVM message requests for
         * Slave insterface S4 (A53 core cluster)
         */
-       out_le32(&cci->slave[4].snoop_ctrl,
-                CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+       if (current_el() == 3) {
+               out_le32(&cci->slave[4].snoop_ctrl,
+                        CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+       }
 
        /* Erratum */
        erratum_a008850_early(); /* part 1 of 2 */