arm64: zynqmp: Move dts zcu102 to zcu102-revA

[u-boot] / arch / arm / dts / rk3036.dtsi

diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi
index 0daae1ec309663b6fa5bf2a7a53b26518bc9747c..ca1d5ac12ecd8d980cda2968582826ca32b49410 100644 (file)
--- a/arch/arm/dts/rk3036.dtsi
+++ b/arch/arm/dts/rk3036.dtsi
@@ -23,6 +23,7 @@
                serial1 = &uart1;
                serial2 = &uart2;
                mmc0 = &emmc;
+               mmc1 = &sdmmc;
        };
 
        memory {
@@ -243,7 +244,7 @@
        emmc: dwmmc@1021c000 {
                compatible = "rockchip,rk3288-dw-mshc";
                clock-frequency = <37500000>;
-               clock-freq-min-max = <400000 37500000>;
+               max-frequency = <37500000>;
                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
                <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -257,6 +258,7 @@
                cap-mmc-highspeed;
                mmc-ddr-1_8v;
                disable-wp;
+               fifo-mode;
                non-removable;
                num-slots = <1>;
                default-sample-phase = <158>;
@@ -264,6 +266,18 @@
                pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
        };
 
+       sdmmc: dwmmc@10214000 {
+               compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x10214000 0x4000>;
+               clock-frequency = <37500000>;
+               max-frequency = <37500000>;
+               clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+               clock-names = "biu", "ciu";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3036-pinctrl";
                rockchip,grf = <&grf>;