]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/dts/uniphier-sld3.dtsi
arm64: zynqmp: Move dts zcu102 to zcu102-revA
[u-boot] / arch / arm / dts / uniphier-sld3.dtsi
index f5c54875348a7811a0afb0b6b86aee322c65d46c..2bb2e029eeeb21c2678e2277c5dd577b98624097 100644 (file)
@@ -4,13 +4,13 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:    GPL-2.0+        X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
-/include/ "skeleton.dtsi"
-
 / {
        compatible = "socionext,uniphier-sld3";
+       #address-cells = <1>;
+       #size-cells = <1>;
 
        cpus {
                #address-cells = <1>;
                        compatible = "fixed-clock";
                        clock-frequency = <50000000>;
                };
-
-               iobus_clk: iobus_clk {
-                       #clock-cells = <0>;
-                       compatible = "fixed-clock";
-                       clock-frequency = <100000000>;
-               };
        };
 
        soc {
                        interrupts = <0 33 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart0>;
+                       clocks = <&sys_clk 0>;
                        clock-frequency = <36864000>;
                };
 
                        interrupts = <0 35 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart1>;
+                       clocks = <&sys_clk 0>;
                        clock-frequency = <36864000>;
                };
 
                        interrupts = <0 37 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_uart2>;
+                       clocks = <&sys_clk 0>;
                        clock-frequency = <36864000>;
                };
 
                        interrupts = <0 41 1>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_i2c0>;
-                       clocks = <&iobus_clk>;
+                       clocks = <&sys_clk 1>;
                        clock-frequency = <100000>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        interrupts = <0 42 1>;
-                       clocks = <&iobus_clk>;
+                       clocks = <&sys_clk 1>;
                        clock-frequency = <100000>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        interrupts = <0 43 1>;
-                       clocks = <&iobus_clk>;
+                       clocks = <&sys_clk 1>;
                        clock-frequency = <100000>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        interrupts = <0 44 1>;
-                       clocks = <&iobus_clk>;
+                       clocks = <&sys_clk 1>;
                        clock-frequency = <100000>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        interrupts = <0 45 1>;
-                       clocks = <&iobus_clk>;
+                       clocks = <&sys_clk 1>;
                        clock-frequency = <400000>;
                };
 
                        #size-cells = <1>;
                };
 
-               smpctrl@59800000 {
+               smpctrl@59801000 {
                        compatible = "socionext,uniphier-smpctrl";
                        reg = <0x59801000 0x400>;
                };
 
                mioctrl@59810000 {
-                       compatible = "socionext,uniphier-mioctrl",
+                       compatible = "socionext,uniphier-sld3-mioctrl",
                                     "simple-mfd", "syscon";
                        reg = <0x59810000 0x800>;
                        u-boot,dm-pre-reloc;
                        pinctrl-0 = <&pinctrl_emmc>;
                        pinctrl-1 = <&pinctrl_emmc_1v8>;
                        clocks = <&mio_clk 1>;
+                       reset-names = "host", "bridge";
                        resets = <&mio_rst 1>, <&mio_rst 4>;
                        bus-width = <8>;
                        non-removable;
+                       cap-mmc-highspeed;
+                       cap-mmc-hw-reset;
                };
 
                sd: sdhc@5a500000 {
                        pinctrl-0 = <&pinctrl_sd>;
                        pinctrl-1 = <&pinctrl_sd_1v8>;
                        clocks = <&mio_clk 0>;
+                       reset-names = "host", "bridge";
                        resets = <&mio_rst 0>, <&mio_rst 3>;
                        bus-width = <4>;
+                       cap-sd-highspeed;
+                       sd-uhs-sdr12;
+                       sd-uhs-sdr25;
+                       sd-uhs-sdr50;
                };
 
                usb0: usb@5a800100 {
                };
 
                soc-glue@5f800000 {
-                       compatible = "simple-mfd", "syscon";
+                       compatible = "socionext,uniphier-sld3-soc-glue",
+                                    "simple-mfd", "syscon";
                        reg = <0x5f800000 0x2000>;
                        u-boot,dm-pre-reloc;
 
                };
 
                sysctrl@f1840000 {
-                       compatible = "socionext,uniphier-sysctrl",
+                       compatible = "socionext,uniphier-sld3-sysctrl",
                                     "simple-mfd", "syscon";
-                       reg = <0xf1840000 0x4000>;
+                       reg = <0xf1840000 0x10000>;
 
                        sys_clk: clock {
                                compatible = "socionext,uniphier-sld3-clock";
                };
 
                nand: nand@f8000000 {
-                       compatible = "denali,denali-nand-dt";
-                       reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+                       compatible = "socionext,uniphier-denali-nand-v5a";
+                       status = "disabled";
                        reg-names = "nand_data", "denali_reg";
+                       reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+                       interrupts = <0 65 4>;
+                       clocks = <&sys_clk 2>;
+                       nand-ecc-strength = <8>;
                };
        };
 };