Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / arch / arm / include / asm / arch-am33xx / cpu.h

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 73e6db89984584850f988decb9b7dc9038065d35..9febfa2719a94273efc8d90911ff38d302ba4535 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -38,6 +38,16 @@
 #define AM335X                         0xB944
 #define TI81XX                         0xB81E
 #define DEVICE_ID                      (CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK                 0x1FFF
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300                 0x1FEF
+#define AM335X_ZCZ_600                 0x1FAF
+#define AM335X_ZCZ_720                 0x1F2F
+#define AM335X_ZCZ_800                 0x1E2F
+#define AM335X_ZCZ_1000                        0x1C2F
+#define AM335X_ZCE_300                 0x1FDF
+#define AM335X_ZCE_600                 0x1F9F
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK                   (BIT(0) | BIT(1) | BIT(2)\
@@ -227,6 +237,14 @@ struct cm_perpll {
        unsigned int cpswclkstctrl;     /* offset 0x144 */
        unsigned int lcdcclkstctrl;     /* offset 0x148 */
 };
+
+/* Encapsulating Display pll registers */
+struct cm_dpll {
+       unsigned int resv1[2];
+       unsigned int clktimer2clk;      /* offset 0x08 */
+       unsigned int resv2[10];
+       unsigned int clklcdcpixelclk;   /* offset 0x34 */
+};
 #else
 /* Encapsulating core pll registers */
 struct cm_wkuppll {
@@ -382,15 +400,17 @@ struct cm_perpll {
        unsigned int resv40[7];
        unsigned int cpgmac0clkctrl;    /* offset 0xB20 */
 };
-#endif /* CONFIG_AM43XX */
 
-/* Encapsulating Display pll registers */
+struct cm_device_inst {
+       unsigned int cm_clkout1_ctrl;
+       unsigned int cm_dll_ctrl;
+};
+
 struct cm_dpll {
-       unsigned int resv1[2];
-       unsigned int clktimer2clk;      /* offset 0x08 */
-       unsigned int resv2[10];
-       unsigned int clklcdcpixelclk;   /* offset 0x34 */
+       unsigned int resv1;
+       unsigned int clktimer2clk;      /* offset 0x04 */
 };
+#endif /* CONFIG_AM43XX */
 
 /* Control Module RTC registers */
 struct cm_rtc {
@@ -447,15 +467,6 @@ struct gptimer {
        unsigned int tcar2;             /* offset 0x58 */
 };
 
-/* RTC Registers */
-struct rtc_regs {
-       unsigned int res[21];
-       unsigned int osc;               /* offset 0x54 */
-       unsigned int res2[5];
-       unsigned int kick0r;            /* offset 0x6c */
-       unsigned int kick1r;            /* offset 0x70 */
-};
-
 /* UART Registers */
 struct uart_sys {
        unsigned int resv1[21];
@@ -474,6 +485,8 @@ struct ctrl_stat {
        unsigned int statusreg;         /* ofset 0x40 */
        unsigned int resv2[51];
        unsigned int secure_emif_sdram_config;  /* offset 0x0110 */
+       unsigned int resv3[319];
+       unsigned int dev_attr;
 };
 
 /* AM33XX GPIO registers */
@@ -509,6 +522,8 @@ struct ctrl_dev {
        unsigned int macid1h;           /* offset 0x3c */
        unsigned int resv4[4];
        unsigned int miisel;            /* offset 0x50 */
+       unsigned int resv5[106];
+       unsigned int efuse_sma;         /* offset 0x1FC */
 };
 
 /* gmii_sel register defines */