Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / arch / arm / include / asm / arch-am33xx / cpu.h

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index f77ac1e844d49191ac53d7ae54ac8e8b95be2479..9febfa2719a94273efc8d90911ff38d302ba4535 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -38,6 +38,16 @@
 #define AM335X                         0xB944
 #define TI81XX                         0xB81E
 #define DEVICE_ID                      (CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK                 0x1FFF
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300                 0x1FEF
+#define AM335X_ZCZ_600                 0x1FAF
+#define AM335X_ZCZ_720                 0x1F2F
+#define AM335X_ZCZ_800                 0x1E2F
+#define AM335X_ZCZ_1000                        0x1C2F
+#define AM335X_ZCE_300                 0x1FDF
+#define AM335X_ZCE_600                 0x1F9F
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK                   (BIT(0) | BIT(1) | BIT(2)\
@@ -46,6 +56,26 @@
 #define PRM_RSTCTRL_RESET              0x01
 #define PRM_RSTST_WARM_RESET_MASK      0x232
 
+/*
+ * Watchdog:
+ * Using the prescaler, the OMAP watchdog could go for many
+ * months before firing.  These limits work without scaling,
+ * with the 60 second default assumed by most tools and docs.
+ */
+#define TIMER_MARGIN_MAX       (24 * 60 * 60)  /* 1 day */
+#define TIMER_MARGIN_DEFAULT   60      /* 60 secs */
+#define TIMER_MARGIN_MIN       1
+
+#define PTV                    0       /* prescale */
+#define GET_WLDR_VAL(secs)     (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
+#define WDT_WWPS_PEND_WCLR     BIT(0)
+#define WDT_WWPS_PEND_WLDR     BIT(2)
+#define WDT_WWPS_PEND_WTGR     BIT(3)
+#define WDT_WWPS_PEND_WSPR     BIT(4)
+
+#define WDT_WCLR_PRE           BIT(5)
+#define WDT_WCLR_PTV_OFF       2
+
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct gpmc_cs {
@@ -193,7 +223,8 @@ struct cm_perpll {
        unsigned int dcan1clkctrl;      /* offset 0xC4 */
        unsigned int resv6[2];
        unsigned int emiffwclkctrl;     /* offset 0xD0 */
-       unsigned int resv7[2];
+       unsigned int epwmss0clkctrl;    /* offset 0xD4 */
+       unsigned int epwmss2clkctrl;    /* offset 0xD8 */
        unsigned int l3instrclkctrl;    /* offset 0xDC */
        unsigned int l3clkctrl;         /* Offset 0xE0 */
        unsigned int resv8[4];
@@ -204,6 +235,15 @@ struct cm_perpll {
        unsigned int l4hsclkctrl;       /* offset 0x120 */
        unsigned int resv10[8];
        unsigned int cpswclkstctrl;     /* offset 0x144 */
+       unsigned int lcdcclkstctrl;     /* offset 0x148 */
+};
+
+/* Encapsulating Display pll registers */
+struct cm_dpll {
+       unsigned int resv1[2];
+       unsigned int clktimer2clk;      /* offset 0x08 */
+       unsigned int resv2[10];
+       unsigned int clklcdcpixelclk;   /* offset 0x34 */
 };
 #else
 /* Encapsulating core pll registers */
@@ -360,13 +400,17 @@ struct cm_perpll {
        unsigned int resv40[7];
        unsigned int cpgmac0clkctrl;    /* offset 0xB20 */
 };
-#endif /* CONFIG_AM43XX */
 
-/* Encapsulating Display pll registers */
+struct cm_device_inst {
+       unsigned int cm_clkout1_ctrl;
+       unsigned int cm_dll_ctrl;
+};
+
 struct cm_dpll {
-       unsigned int resv1[2];
-       unsigned int clktimer2clk;      /* offset 0x08 */
+       unsigned int resv1;
+       unsigned int clktimer2clk;      /* offset 0x04 */
 };
+#endif /* CONFIG_AM43XX */
 
 /* Control Module RTC registers */
 struct cm_rtc {
@@ -423,15 +467,6 @@ struct gptimer {
        unsigned int tcar2;             /* offset 0x58 */
 };
 
-/* RTC Registers */
-struct rtc_regs {
-       unsigned int res[21];
-       unsigned int osc;               /* offset 0x54 */
-       unsigned int res2[5];
-       unsigned int kick0r;            /* offset 0x6c */
-       unsigned int kick1r;            /* offset 0x70 */
-};
-
 /* UART Registers */
 struct uart_sys {
        unsigned int resv1[21];
@@ -450,6 +485,8 @@ struct ctrl_stat {
        unsigned int statusreg;         /* ofset 0x40 */
        unsigned int resv2[51];
        unsigned int secure_emif_sdram_config;  /* offset 0x0110 */
+       unsigned int resv3[319];
+       unsigned int dev_attr;
 };
 
 /* AM33XX GPIO registers */
@@ -485,6 +522,8 @@ struct ctrl_dev {
        unsigned int macid1h;           /* offset 0x3c */
        unsigned int resv4[4];
        unsigned int miisel;            /* offset 0x50 */
+       unsigned int resv5[106];
+       unsigned int efuse_sma;         /* offset 0x1FC */
 };
 
 /* gmii_sel register defines */
@@ -505,6 +544,35 @@ struct ctrl_dev {
 #define RGMII_INT_DELAY                (RGMII1_IDMODE | RGMII2_IDMODE)
 #define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
 
+/* PWMSS */
+struct pwmss_regs {
+       unsigned int idver;
+       unsigned int sysconfig;
+       unsigned int clkconfig;
+       unsigned int clkstatus;
+};
+#define ECAP_CLK_EN            BIT(0)
+#define ECAP_CLK_STOP_REQ      BIT(1)
+
+struct pwmss_ecap_regs {
+       unsigned int tsctr;
+       unsigned int ctrphs;
+       unsigned int cap1;
+       unsigned int cap2;
+       unsigned int cap3;
+       unsigned int cap4;
+       unsigned int resv1[4];
+       unsigned short ecctl1;
+       unsigned short ecctl2;
+};
+
+/* Capture Control register 2 */
+#define ECTRL2_SYNCOSEL_MASK   (0x03 << 6)
+#define ECTRL2_MDSL_ECAP       BIT(9)
+#define ECTRL2_CTRSTP_FREERUN  BIT(4)
+#define ECTRL2_PLSL_LOW                BIT(10)
+#define ECTRL2_SYNC_EN         BIT(5)
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */