[MIPS] cpu/mips/cache.S: Add dcache_enable

[u-boot] / cpu / mips / cache.S

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index e6f31751bfff9870fd473dee8d0af04e67124596..428d251bf126022d56bf22477662cfdc67321094 100644 (file)
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -1,5 +1,5 @@
 /*
- *  Cache-handling routined for MIPS 4K CPUs
+ *  Cache-handling routined for MIPS CPUs
  *
  *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
  *
@@ -32,10 +32,14 @@
 
 #define RA             t8
 
-       /* 16KB is the maximum size of instruction and data caches on
-        * MIPS 4K.
-        */
-#define MIPS_MAX_CACHE_SIZE    0x4000
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE    0x10000
 
 #define INDEX_BASE     KSEG0
 
@@ -278,9 +282,25 @@ LEAF(dcache_disable)
        and     t0, t0, t1
        ori     t0, t0, CONF_CM_UNCACHED
        mtc0    t0, CP0_CONFIG
-       j       ra
+       jr      ra
        END(dcache_disable)
 
+/*******************************************************************************
+*
+* dcache_enable - enable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_enable)
+       mfc0    t0, CP0_CONFIG
+       ori     t0, CONF_CM_CMASK
+       xori    t0, CONF_CM_CMASK
+       ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+       mtc0    t0, CP0_CONFIG
+       jr      ra
+       END(dcache_enable)
+
 #ifdef CFG_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
 *
@@ -304,7 +324,7 @@ mips_cache_lock:
        move    a1, a2
        icacheop(a0,a1,a2,a3,0x1d)
 
-       j       ra
+       jr      ra
 
        .end    mips_cache_lock
 #endif /* CFG_INIT_RAM_LOCK_MIPS */