]> git.sur5r.net Git - u-boot/commitdiff
[MIPS] cpu/mips/cache.S: Add dcache_enable
authorShinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Sat, 3 May 2008 04:51:28 +0000 (13:51 +0900)
committerShinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Sat, 3 May 2008 04:51:28 +0000 (13:51 +0900)
Recent bootelf command fixes (017e9b7925f74878d0e9475388cca9bda5ef9482,
"allow ports to override bootelf behavior") requires ports to have this
function.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
cpu/mips/cache.S

index f5939683208f03ccf985b0f0025a4cd70efd02c1..428d251bf126022d56bf22477662cfdc67321094 100644 (file)
@@ -285,6 +285,22 @@ LEAF(dcache_disable)
        jr      ra
        END(dcache_disable)
 
+/*******************************************************************************
+*
+* dcache_enable - enable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_enable)
+       mfc0    t0, CP0_CONFIG
+       ori     t0, CONF_CM_CMASK
+       xori    t0, CONF_CM_CMASK
+       ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+       mtc0    t0, CP0_CONFIG
+       jr      ra
+       END(dcache_enable)
+
 #ifdef CFG_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
 *