+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2009 Michal Simek
* (C) Copyright 2003 Xilinx Inc.
*
* Michal SIMEK <monstr@monstr.eu>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <phy.h>
#include <miiphy.h>
#include <fdtdec.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
#include <linux/kernel.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long start = get_timer(0);
while (1) {
- val = readl(reg);
+ val = __raw_readl(reg);
if (!set)
val = ~val;
if (mdio_wait(regs))
return 1;
- u32 ctrl_reg = in_be32(®s->mdioctrl);
- out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK |
- ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
- out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+ u32 ctrl_reg = __raw_readl(®s->mdioctrl);
+ __raw_writel(XEL_MDIOADDR_OP_MASK
+ | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
+ | registernum), ®s->mdioaddr);
+ __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
if (mdio_wait(regs))
return 1;
/* Read data */
- *data = in_be32(®s->mdiord);
+ *data = __raw_readl(®s->mdiord);
return 0;
}
* Data register. Finally, set the Status bit in the MDIO Control
* register to start a MDIO write transaction.
*/
- u32 ctrl_reg = in_be32(®s->mdioctrl);
- out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
- ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
- out_be32(®s->mdiowr, data);
- out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
+ u32 ctrl_reg = __raw_readl(®s->mdioctrl);
+ __raw_writel(~XEL_MDIOADDR_OP_MASK
+ & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
+ | registernum), ®s->mdioaddr);
+ __raw_writel(data, ®s->mdiowr);
+ __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
if (mdio_wait(regs))
return 1;
static int setup_phy(struct udevice *dev)
{
- int i;
+ int i, ret;
u16 phyreg;
struct xemaclite *emaclite = dev_get_priv(dev);
struct phy_device *phydev;
phydev->advertising = supported;
emaclite->phydev = phydev;
phy_config(phydev);
- phy_startup(phydev);
+ ret = phy_startup(phydev);
+ if (ret)
+ return ret;
if (!phydev->link) {
printf("%s: No link.\n", phydev->dev->name);
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
- out_be32(®s->tx_ping_tsr, 0);
+ __raw_writel(0, ®s->tx_ping_tsr);
/* Copy MAC address */
xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
ENET_ADDR_LENGTH);
/* Set the length */
- out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH);
+ __raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr);
/* Update the MAC address in the EMAC Lite */
- out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
+ __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr);
/* Wait for EMAC Lite to finish with the MAC address update */
- while ((in_be32 (®s->tx_ping_tsr) &
+ while ((__raw_readl(®s->tx_ping_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
if (emaclite->txpp) {
/* The same operation with PONG TX */
- out_be32(®s->tx_pong_tsr, 0);
+ __raw_writel(0, ®s->tx_pong_tsr);
xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
ENET_ADDR_LENGTH);
- out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH);
- out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
- while ((in_be32(®s->tx_pong_tsr) &
+ __raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr);
+ __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr);
+ while ((__raw_readl(®s->tx_pong_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
}
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
- out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
+ __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr);
if (emaclite->rxpp)
- out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
+ __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr);
- out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
- if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
+ __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl);
+ if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
if (!setup_phy(dev))
return -1;
* Read the other buffer register
* and determine if the other buffer is available
*/
- tmp = ~in_be32(®s->tx_ping_tsr);
+ tmp = ~__raw_readl(®s->tx_ping_tsr);
if (emaclite->txpp)
- tmp |= ~in_be32(®s->tx_pong_tsr);
+ tmp |= ~__raw_readl(®s->tx_pong_tsr);
return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
}
if (!maxtry) {
printf("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
- out_be32(®s->tx_ping_tsr, 0);
+ __raw_writel(0, ®s->tx_ping_tsr);
if (emaclite->txpp) {
- out_be32(®s->tx_pong_tsr, 0);
+ __raw_writel(0, ®s->tx_pong_tsr);
}
return -1;
}
/* Determine if the expected buffer address is empty */
- reg = in_be32(®s->tx_ping_tsr);
+ reg = __raw_readl(®s->tx_ping_tsr);
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
debug("Send packet from tx_ping buffer\n");
/* Write the frame to the buffer */
xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
- out_be32(®s->tx_ping_tplr, len &
- (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
- reg = in_be32(®s->tx_ping_tsr);
+ __raw_writel(len
+ & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
+ ®s->tx_ping_tplr);
+ reg = __raw_readl(®s->tx_ping_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
- out_be32(®s->tx_ping_tsr, reg);
+ __raw_writel(reg, ®s->tx_ping_tsr);
return 0;
}
if (emaclite->txpp) {
/* Determine if the expected buffer address is empty */
- reg = in_be32(®s->tx_pong_tsr);
+ reg = __raw_readl(®s->tx_pong_tsr);
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
debug("Send packet from tx_pong buffer\n");
/* Write the frame to the buffer */
xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
- out_be32(®s->tx_pong_tplr, len &
+ __raw_writel(len &
(XEL_TPLR_LENGTH_MASK_HI |
- XEL_TPLR_LENGTH_MASK_LO));
- reg = in_be32(®s->tx_pong_tsr);
+ XEL_TPLR_LENGTH_MASK_LO),
+ ®s->tx_pong_tplr);
+ reg = __raw_readl(®s->tx_pong_tsr);
reg |= XEL_TSR_XMIT_BUSY_MASK;
- out_be32(®s->tx_pong_tsr, reg);
+ __raw_writel(reg, ®s->tx_pong_tsr);
return 0;
}
}
try_again:
if (!emaclite->use_rx_pong_buffer_next) {
- reg = in_be32(®s->rx_ping_rsr);
+ reg = __raw_readl(®s->rx_ping_rsr);
debug("Testing data at rx_ping\n");
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
debug("Data found in rx_ping buffer\n");
goto try_again;
}
} else {
- reg = in_be32(®s->rx_pong_rsr);
+ reg = __raw_readl(®s->rx_pong_rsr);
debug("Testing data at rx_pong\n");
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
debug("Data found in rx_pong buffer\n");
length - first_read);
/* Acknowledge the frame */
- reg = in_be32(ack);
+ reg = __raw_readl(ack);
reg &= ~XEL_RSR_RECV_DONE_MASK;
- out_be32(ack, reg);
+ __raw_writel(reg, ack);
debug("Packet receive from 0x%p, length %dB\n", addr, length);
*packetp = etherrxbuff;
emaclite->bus->read = emaclite_miiphy_read;
emaclite->bus->write = emaclite_miiphy_write;
emaclite->bus->priv = emaclite;
- strcpy(emaclite->bus->name, "emaclite");
- ret = mdio_register(emaclite->bus);
+ ret = mdio_register_seq(emaclite->bus, dev->seq);
if (ret)
return ret;
struct xemaclite *emaclite = dev_get_priv(dev);
int offset = 0;
- pdata->iobase = (phys_addr_t)dev_get_addr(dev);
- emaclite->regs = (struct emaclite_regs *)pdata->iobase;
+ pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
+ emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
+ 0x10000);
emaclite->phyaddr = -1;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
"reg", -1);
- emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,tx-ping-pong", 0);
- emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,rx-ping-pong", 0);
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,