]> git.sur5r.net Git - u-boot/commitdiff
x86: timer: tsc: Allow specifying clock rate from device tree again
authorBin Meng <bmeng.cn@gmail.com>
Sat, 23 Jun 2018 10:03:47 +0000 (03:03 -0700)
committerBin Meng <bmeng.cn@gmail.com>
Mon, 2 Jul 2018 01:23:28 +0000 (09:23 +0800)
With the introduction of early timer support in the TSC driver,
the capability of getting clock rate from device tree was lost
unfortunately. Now we bring such functionality back, but with a
limitation that when TSC is used as early timer, specifying clock
rate from device tree does not work.

This fixes random boot failures seen on QEMU targets: printing "TSC
frequency is ZERO" and reset forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
drivers/timer/tsc_timer.c

index cf869998bf9cc1da3e3d5f1a28c732996bbc8f63..747f190d3845a60fac6d1e1e5d90071525d9b028 100644 (file)
@@ -377,14 +377,23 @@ static int tsc_timer_probe(struct udevice *dev)
 {
        struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 
-       tsc_timer_ensure_setup();
-       uc_priv->clock_rate = gd->arch.clock_rate;
+       if (!uc_priv->clock_rate) {
+               tsc_timer_ensure_setup();
+               uc_priv->clock_rate = gd->arch.clock_rate;
+       } else {
+               gd->arch.tsc_base = rdtsc();
+       }
 
        return 0;
 }
 
 unsigned long notrace timer_early_get_rate(void)
 {
+       /*
+        * When TSC timer is used as the early timer, be warned that the timer
+        * clock rate can only be calibrated via some hardware ways. Specifying
+        * it in the device tree won't work for the early timer.
+        */
        tsc_timer_ensure_setup();
 
        return gd->arch.clock_rate;