din_8 = din;
while (bytelen) {
- ret = wait_for_bit(__func__, ®->ctrl,
- MVEBU_SPI_A3700_XFER_RDY, true, 100, false);
+ ret = wait_for_bit_le32(®->ctrl,
+ MVEBU_SPI_A3700_XFER_RDY,
+ true,100, false);
if (ret)
return ret;
writel(pending_dout, ®->dout);
if (din) {
- ret = wait_for_bit(__func__, ®->ctrl,
- MVEBU_SPI_A3700_XFER_RDY,
- true, 100, false);
+ ret = wait_for_bit_le32(®->ctrl,
+ MVEBU_SPI_A3700_XFER_RDY,
+ true, 100, false);
if (ret)
return ret;
/* Deactivate CS */
if (flags & SPI_XFER_END) {
- ret = wait_for_bit(__func__, ®->ctrl,
- MVEBU_SPI_A3700_XFER_RDY, true, 100, false);
+ ret = wait_for_bit_le32(®->ctrl,
+ MVEBU_SPI_A3700_XFER_RDY,
+ true, 100, false);
if (ret)
return ret;
/* Flush read/write FIFO */
data = readl(®->cfg);
writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, ®->cfg);
- ret = wait_for_bit(__func__, ®->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
- false, 1000, false);
+ ret = wait_for_bit_le32(®->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
+ false, 1000, false);
if (ret)
return ret;
{
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
- plat->spireg = (struct spi_reg *)dev_get_addr(bus);
+ plat->spireg = (struct spi_reg *)devfdt_get_addr(bus);
/*
* FIXME
* it should be used to read the input clock and the DT property
* can be removed.
*/
- plat->clock = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"clock-frequency", 160000);
- plat->frequency = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ plat->frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"spi-max-frequency", 40000);
return 0;