85xx/86xx: Rename DDR init address and init extended address register

[u-boot] / include / asm-ppc / immap_86xx.h

diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index a15c6ec12ab0633f54588f270673571c3ff102e0..4287cf463e394543bac7e69d342ca8dcffcca6c8 100644 (file)
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -126,7 +126,7 @@ typedef struct ccsr_ddr {
        uint    sdram_ocd_cntl;         /* 0x2140 - DDR SDRAM OCD Control */
        uint    sdram_ocd_status;       /* 0x2144 - DDR SDRAM OCD Status */
        uint    init_addr;              /* 0x2148 - DDR training initialzation address */
-       uint    init_addr_ext;          /* 0x214C - DDR training initialzation extended address */
+       uint    init_ext_addr;          /* 0x214C - DDR training initialzation extended address */
        char    res10[2728];
        uint    ip_rev1;                /* 0x2BF8 - DDR IP Block Revision 1 */
        uint    ip_rev2;                /* 0x2BFC - DDR IP Block Revision 2 */
@@ -1256,12 +1256,16 @@ typedef struct ccsr_rio {
 typedef struct ccsr_gur {
        uint    porpllsr;       /* 0xe0000 - POR PLL ratio status register */
        uint    porbmsr;        /* 0xe0004 - POR boot mode status register */
-#define MPC86xx_PORBMSR_HA      0x00060000
-#define MPC85xx_PORBMSR_HA             0x00070000
+#define MPC8610_PORBMSR_HA      0x00070000
+#define MPC8610_PORBMSR_HA_SHIFT       16
+#define MPC8641_PORBMSR_HA      0x00060000
+#define MPC8641_PORBMSR_HA_SHIFT       17
        uint    porimpscr;      /* 0xe0008 - POR I/O impedance status and control register */
        uint    pordevsr;       /* 0xe000c - POR I/O device status regsiter */
-#define MPC86xx_PORDEVSR_IO_SEL                0x000F0000
-#define MPC85xx_PORDEVSR_IO_SEL                0x00380000 /* 85xx platform type */
+#define MPC8610_PORDEVSR_IO_SEL                0x00380000
+#define MPC8610_PORDEVSR_IO_SEL_SHIFT          19
+#define MPC8641_PORDEVSR_IO_SEL                0x000F0000
+#define MPC8641_PORDEVSR_IO_SEL_SHIFT          16
 #define MPC86xx_PORDEVSR_CORE1TE       0x00000080 /* ASMP (Core1 addr trans) */
        uint    pordbgmsr;      /* 0xe0010 - POR debug mode status register */
        char    res1[12];