]> git.sur5r.net Git - u-boot/commitdiff
85xx/86xx: Rename DDR init address and init extended address register
authorKumar Gala <galak@kernel.crashing.org>
Tue, 29 Apr 2008 15:28:34 +0000 (10:28 -0500)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Tue, 29 Apr 2008 16:42:05 +0000 (11:42 -0500)
Rename init_addr and init_ext_addr to match the docs between
85xx and 86xx.  Both now use 'init_addr' and 'init_ext_addr'.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
include/asm-ppc/immap_85xx.h
include/asm-ppc/immap_86xx.h

index dc6e278ff4300e6c91772c033808d80d65bfafd9..da97cd4c8cbebda461759370137b510691515802 100644 (file)
@@ -106,8 +106,8 @@ typedef struct ccsr_ddr {
        char    res6[4];
        uint    sdram_clk_cntl;         /* 0x2130 - DDR SDRAM Clock Control */
        char    res7[20];
-       uint    init_address;           /* 0x2148 - DDR training initialization address */
-       uint    init_ext_address;       /* 0x214C - DDR training initialization extended address */
+       uint    init_addr;              /* 0x2148 - DDR training initialization address */
+       uint    init_ext_addr;          /* 0x214C - DDR training initialization extended address */
        char    res8_1[16];
        uint    timing_cfg_4;           /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
        uint    timing_cfg_5;           /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
index 7526061d5ab7c11240561785701b489523198142..4287cf463e394543bac7e69d342ca8dcffcca6c8 100644 (file)
@@ -126,7 +126,7 @@ typedef struct ccsr_ddr {
        uint    sdram_ocd_cntl;         /* 0x2140 - DDR SDRAM OCD Control */
        uint    sdram_ocd_status;       /* 0x2144 - DDR SDRAM OCD Status */
        uint    init_addr;              /* 0x2148 - DDR training initialzation address */
-       uint    init_addr_ext;          /* 0x214C - DDR training initialzation extended address */
+       uint    init_ext_addr;          /* 0x214C - DDR training initialzation extended address */
        char    res10[2728];
        uint    ip_rev1;                /* 0x2BF8 - DDR IP Block Revision 1 */
        uint    ip_rev2;                /* 0x2BFC - DDR IP Block Revision 2 */