target: rename cortex_m3 to cortex_m

[openocd] / tcl / target / stellaris.cfg

diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 3ab5c0b97d01c3d34965914c575972d5de3a51bb..9804bde79172a6ce4e8c152dff5142fbb53a6c8e 100644 (file)
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -6,7 +6,7 @@
 
 global _DEVICECLASS
 
-if { [info exists DEVICECLASS ] } {
+if { [info exists DEVICECLASS] } {
    set _DEVICECLASS $DEVICECLASS
 } else {
    set _DEVICECLASS 0xff
@@ -20,18 +20,19 @@ source [find target/swj-dp.tcl]
 # are usable only for ISP style initial flash programming.
 
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME lm3s
+   set _CHIPNAME lm3s
 }
 
 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
-# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
+# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
+# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
 # ... we'll ignore the JTAG version field, rather than list every
 # chip revision that turns up.
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x0ba00477
@@ -43,19 +44,19 @@ if { [info exists CPUTAPID ] } {
 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
        -expected-id $_CPUTAPID -ignore-version
 
-if { [info exists WORKAREASIZE ] } {
+if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   # default to 8K working area
-   set _WORKAREASIZE 0x2000
+   # default to 2K working area
+   set _WORKAREASIZE 0x800
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
 # 8K working area at base of ram, not backed up
 #
-# NOTE:  you may need or want to reconfigure the work area;
+# NOTE: you may need or want to reconfigure the work area;
 # some parts have just 6K, and you may want to use other
 # addresses (at end of mem not beginning) or back it up.
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
@@ -63,7 +64,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
 # LM3S parts don't support RTCK
 #
-# NOTE:  this may be increased by a reset-init handler, after it
+# NOTE: this may be increased by a reset-init handler, after it
 # configures and enables the PLL.  Or you might need to decrease
 # this, if you're using a slower clock.
 adapter_khz 500
@@ -132,7 +133,7 @@ proc reset_peripherals {family} {
 $_TARGETNAME configure -event reset-start {
        adapter_khz 500
 
-       #       
+       #
        # When nRST is asserted on most Stellaris devices, it clears some of
        # the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
        # and OpenOCD depends on those TRMs.  So we won't use SRST on those
@@ -156,11 +157,11 @@ $_TARGETNAME configure -event reset-start {
        if {$device_class == 0 || $device_class == 1 ||
                $device_class == 3 || $device_class == 5} {
                # Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
-               cortex_m3 reset_config sysresetreq
+               cortex_m reset_config sysresetreq
        } else {
                # Tempest and Firestorm default to using NVIC VECTRESET
                # peripherals will need reseting manually, see proc reset_peripherals
-               cortex_m3 reset_config vectreset
+               cortex_m reset_config vectreset
 
                # reset peripherals, based on code in
                # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf