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(parent: bf8e20a) | patch
Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting...
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Mon, 17 Dec 2018 00:01:36 +0000 (00:01 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Mon, 17 Dec 2018 00:01:36 +0000 (00:01 +0000)
commit5c08a1d2661e1293aca3e46875a790e3ece7ac0c
treee7d58c212bb01cfdbbdc2280edd27b154f7ce810tree | snapshot
parentbf8e20a60bb367f516b003a181090b42f579659dcommit | diff
Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2605 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-igloo2.ld diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-ram.ld diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.c diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_plic.h diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/full_demo/main_full.c diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/main.c diff | blob | history
FreeRTOS imported from SF.net SVN