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(parent: 7382d17) | patch
ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is on
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Wed, 10 Aug 2016 07:08:46 +0000 (16:08 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Thu, 11 Aug 2016 08:49:44 +0000 (17:49 +0900)
commit8fca073271706f3d856c6554c2b5400ac9c83c10
tree06c882eb921d1931b3fea21dbd0ec81fd3452f86tree | snapshot
parent7382d1782648e6e8e5be878e9b9a3cbfd1912001commit | diff
ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is on

The UniPhier outer cache (L2 cache on ARMv7 SoCs) has 128 byte line
length and its tags are also managed per 128 byte line.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
include/configs/uniphier.h diff | blob | history
Cloned from git://git.denx.de/u-boot.git