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[MIPS] Initialize CP0 Cause before setting up CP0 Status register
authorShinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Tue, 25 Mar 2008 12:30:07 +0000 (21:30 +0900)
committerShinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Tue, 25 Mar 2008 12:30:07 +0000 (21:30 +0900)
commitd43d43ef2845af309c25a64bb9c2c5fb3261bc23
tree8110ca5dee67d093aebfee728e838e3fdd89f7d5tree | snapshot
parent26138623230ca2bad3c78e05a65527ea70c8b688commit | diff
[MIPS] Initialize CP0 Cause before setting up CP0 Status register

Without this change, we'll be suffering from deffered WATCH exception
once Status.EXL is cleared. Make sure Cause.WP is cleared.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
cpu/mips/start.S diff | blob | history
Cloned from git://git.denx.de/u-boot.git