spl mxc nand: Set symmetric mode

Set the spl mxc nand driver for IP 1.1 in symmetric mode, like the mtd driver.
In this way, for both drivers, one input clock period of the NFC IP will produce
one R/W cycle.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c
index 059969ba9a5e5aeeacce9a93506dbfd2d00720ea..842943c651b598e610bb6e65005d379d9267c145 100644 (file)
--- a/nand_spl/nand_boot_fsl_nfc.c
+++ b/nand_spl/nand_boot_fsl_nfc.c
@@ -57,7 +57,8 @@ static void nfc_nand_init(void)
        writew(0x2, &nfc->config);
 
        /* hardware ECC checking and correct */
-       config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK | NFC_FP_INT;
+       config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK |
+                       NFC_ONE_CYCLE | NFC_FP_INT;
        /*
         * if spare size is larger that 16 bytes per 512 byte hunk
         * then use 8 symbol correction instead of 4