--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?>\r
+\r
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
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+ <externalSettings/>\r
+ <extensions>\r
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
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+ </extensions>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
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+ <builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.ifx.XMC4000.toolchainBuilder.1543365862" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="XMC Builder" superClass="com.ifx.XMC4000.toolchainBuilder"/>\r
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+ <listOptionValue builtIn="false" value=""${eclipse_home}/../CMSIS/Include""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Common_Demo_Source/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/ARM_CM4F}""/>\r
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+ </option>\r
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+ </tool>\r
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+ <listOptionValue builtIn="false" value=""${eclipse_home}/../CMSIS/Infineon/Include""/>\r
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+ </option>\r
+ </tool>\r
+ <tool id="com.ifx.xmc4000.appDebug.assembler.1113299181" name="ARM-GCC Assembler" superClass="com.ifx.xmc4000.appDebug.assembler">\r
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+ </option>\r
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+ </tool>\r
+ <tool id="com.ifx.xmc4000.appDebug.linker.540417974" name="ARM-GCC C Linker" superClass="com.ifx.xmc4000.appDebug.linker">\r
+ <option id="com.ifx.xmc4000.appLinker.option.scriptfile.1274916363" name="Script file (-T)" superClass="com.ifx.xmc4000.appLinker.option.scriptfile" value="../LinkerScripts/RTOSDemo_XMC4500.ld" valueType="string"/>\r
+ <inputType id="com.ifx.xmc4000.appLinker.inputType.193148015" name="ARM-GCC for XMC Linker Input Type" superClass="com.ifx.xmc4000.appLinker.inputType">\r
+ <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
+ <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
+ </inputType>\r
+ </tool>\r
+ <tool id="com.ifx.xmc4000.appDebug.cpplinker.1425994416" name="ARM-GCC C++ Linker" superClass="com.ifx.xmc4000.appDebug.cpplinker"/>\r
+ <tool id="com.ifx.xmc4000.libLinker.1022326266" name="ARM-GCC Archiver" superClass="com.ifx.xmc4000.libLinker"/>\r
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+ <tool id="com.ifx.xmc4000.printsize.1124241582" name="ARM-GCC Print Size" superClass="com.ifx.xmc4000.printsize"/>\r
+ </toolChain>\r
+ </folderInfo>\r
+ </configuration>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+ </cconfiguration>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
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+ </storageModule>\r
+ <storageModule moduleId="scannerConfiguration">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+ <scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appRelease.1833453587;com.ifx.xmc4000.appRelease.1833453587.;com.ifx.xmc4000.appRelease.compiler.1453708254;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.403412067">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>\r
+ </scannerConfigBuildInfo>\r
+ <scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appRelease.1833453587;com.ifx.xmc4000.appRelease.1833453587.;com.ifx.xmc4000.appRelease.assembler.1016067260;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.1614170329">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>\r
+ </scannerConfigBuildInfo>\r
+ <scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appDebug.607051084;com.ifx.xmc4000.appDebug.607051084.;com.ifx.xmc4000.appDebug.compiler.1635621846;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.c.compiler.base.input.947657962">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>\r
+ </scannerConfigBuildInfo>\r
+ <scannerConfigBuildInfo instanceId="com.ifx.xmc4000.appDebug.607051084;com.ifx.xmc4000.appDebug.607051084.;com.ifx.xmc4000.appDebug.assembler.1113299181;org.eclipse.cdt.cross.arm.gnu.sourcery.windows.assembler.base.input.859825253">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.arm.gnu.ARM_CS_GCCWinManagedMakePerProjectProfileC"/>\r
+ </scannerConfigBuildInfo>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.language.mapping">\r
+ <project-mappings/>\r
+ </storageModule>\r
+ <storageModule moduleId="refreshScope"/>\r
+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ <dictionary>\r
+ <key>?name?</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.append_environment</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.autoBuildTarget</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+ <value></value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+ <value>"${ARM_GCC_HOME}/bin/make"</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+ <value>${workspace_loc:/RTOSDemo/Debug}</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>\r
+ <value>clean</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.contents</key>\r
+ <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+ <value>false</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.fullBuildTarget</key>\r
+ <value>all</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ <dictionary>\r
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+ <value>true</value>\r
+ </dictionary>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>com.ifx.xmc4000.xmc4000Nature</nature>\r
+ <nature>com.dave.common.daveBenchNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
+</projectDescription>\r
--- /dev/null
+ACTIVE_CONFIG_NAME=Debug\r
+MBS_PROVIDER_ID_KEY=com.dave.mbs.xmc4000.xmc4000MbsFactory\r
+eclipse.preferences.version=1\r
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="UNSPECIFIED"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+REM This file should be executed from the command line prior to the first\r
+REM build. It will be necessary to refresh the Eclipse project once the\r
+REM .bat file has been executed (normally just press F5 to refresh).\r
+\r
+REM Copies all the required files from their location within the standard\r
+REM FreeRTOS directory structure to under the Eclipse project directory.\r
+REM This permits the Eclipse project to be used in 'managed' mode and without\r
+REM having to setup any linked resources.\r
+\r
+REM Standard paths\r
+SET FREERTOS_SOURCE=..\..\Source\r
+SET COMMON_SOURCE=..\Common\minimal\r
+SET COMMON_INCLUDE=..\Common\include\r
+\r
+REM Have the files already been copied?\r
+IF EXIST FreeRTOS_Source Goto END\r
+\r
+ REM Create the required directory structure.\r
+ MD FreeRTOS_Source\r
+ MD FreeRTOS_Source\include\r
+ MD FreeRTOS_Source\portable\r
+ MD FreeRTOS_Source\portable\GCC\r
+ MD FreeRTOS_Source\portable\GCC\ARM_CM4F\r
+ MD FreeRTOS_Source\portable\MemMang \r
+ MD Common_Demo_Source\r
+ MD Common_Demo_Source\include\r
+ \r
+ REM Copy the core kernel files into the SDK projects directory\r
+ copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source\r
+ copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source\r
+ copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source\r
+ copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source\r
+\r
+ REM Copy the common header files into the SDK projects directory\r
+ copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include\r
+ \r
+ REM Copy the portable layer files into the projects directory\r
+ copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM4F\*.* FreeRTOS_Source\portable\GCC\ARM_CM4F\r
+ \r
+ REM Copy the basic memory allocation files into the SDK projects directory\r
+ copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c FreeRTOS_Source\portable\MemMang\r
+\r
+ REM Copy the files that define the common demo tasks.\r
+ copy %COMMON_SOURCE%\dynamic.c Common_Demo_Source\r
+ copy %COMMON_SOURCE%\blocktim.c Common_Demo_Source\r
+ copy %COMMON_SOURCE%\semtest.c Common_Demo_Source\r
+ copy %COMMON_SOURCE%\GenQTest.c Common_Demo_Source\r
+ copy %COMMON_SOURCE%\recmutex.c Common_Demo_Source\r
+ copy %COMMON_SOURCE%\sp_flop.c Common_Demo_Source\r
+ copy %COMMON_SOURCE%\countsem.c Common_Demo_Source\r
+ \r
+ REM Copy the common demo file headers.\r
+ copy %COMMON_INCLUDE%\*.h Common_Demo_Source\include\r
+ \r
+: END\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+extern uint32_t SystemCoreClock;\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 6 /* 63 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+ \r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } \r
+ \r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+\r
+/* Demo application specific settings. */\r
+#if UC_ID == 4502\r
+ /* Hardware includes. */\r
+ #include "XMC4500.h"\r
+ #include "System_XMC4500.h"\r
+\r
+ /* Configure pin P3.9 for the LED. */\r
+ #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )\r
+ /* To toggle the single LED */\r
+ #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 )\r
+#elif defined( PART_XMC4400 )\r
+ /* Hardware includes. */\r
+ #include "XMC4400.h"\r
+ #include "System_XMC4200.h"\r
+\r
+ /* Configure pin P5.2 for the LED. */\r
+ #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )\r
+ /* To toggle the single LED */\r
+ #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 )\r
+#elif defined( PART_XMC4200 )\r
+ /* Hardware includes. */\r
+ #include "XMC4200.h"\r
+ #include "System_XMC4200.h"\r
+\r
+ /* Configure pin P2.1 for the LED. */\r
+ #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL\r
+ /* To toggle the single LED */\r
+ #define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 )\r
+#else\r
+ #error Part number not specified in project options\r
+#endif\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+/* Generated automatically for XMC4500_QFP144 on: Mon Jan 14 10:10:13 2013*/\r
+\r
+#include <XMC4500.h>\r
+\r
+#define INPUT 0x00U\r
+#define INPUT_PD 0x08U\r
+#define INPUT_PU 0x10U\r
+#define INPUT_PPS 0x18U\r
+#define INPUT_INV 0x20U\r
+#define INPUT_INV_PD 0x28U\r
+#define INPUT_INV_PU 0x30U\r
+#define INPUT_INV_PPS 0x38U\r
+#define OUTPUT_PP_GP 0x80U\r
+#define OUTPUT_PP_AF1 0x88U\r
+#define OUTPUT_PP_AF2 0x90U\r
+#define OUTPUT_PP_AF3 0x98U\r
+#define OUTPUT_PP_AF4 0xA0U\r
+#define OUTPUT_OD_GP 0xC0U\r
+#define OUTPUT_OD_AF1 0xC8U\r
+#define OUTPUT_OD_AF2 0xD0U\r
+#define OUTPUT_OD_AF3 0xD8U\r
+#define OUTPUT_OD_AF4 0XE0U\r
+\r
+#define WEAK 0x7UL\r
+#define MEDIUM 0x4UL\r
+#define STRONG 0x2UL\r
+#define VERYSTRONG 0x0UL\r
+\r
+#define SOFTWARE 0x0UL\r
+#define HW0 0x1UL\r
+#define HW1 0x2UL\r
+\r
+__STATIC_INLINE void P0_0_set_mode(uint8_t mode){\r
+ PORT0->IOCR0 &= ~0x000000f8UL;\r
+ PORT0->IOCR0 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P0_0_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR0 &= ~0x00000007UL;\r
+ PORT0->PDR0 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P0_0_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x00000003UL;\r
+ PORT0->HWSEL |= config << 0;\r
+}\r
+\r
+__STATIC_INLINE void P0_0_set(void){\r
+ PORT0->OMR = 0x00000001UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_0_reset(void){\r
+ PORT0->OMR = 0x00010000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_0_toggle(void){\r
+ PORT0->OMR = 0x00010001UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_0_read(void){\r
+ return(PORT0->IN & 0x00000001UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_1_set_mode(uint8_t mode){\r
+ PORT0->IOCR0 &= ~0x0000f800UL;\r
+ PORT0->IOCR0 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P0_1_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR0 &= ~0x00000070UL;\r
+ PORT0->PDR0 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P0_1_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x0000000cUL;\r
+ PORT0->HWSEL |= config << 2;\r
+}\r
+\r
+__STATIC_INLINE void P0_1_set(void){\r
+ PORT0->OMR = 0x00000002UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_1_reset(void){\r
+ PORT0->OMR = 0x00020000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_1_toggle(void){\r
+ PORT0->OMR = 0x00020002UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_1_read(void){\r
+ return(PORT0->IN & 0x00000002UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_2_set_mode(uint8_t mode){\r
+ PORT0->IOCR0 &= ~0x00f80000UL;\r
+ PORT0->IOCR0 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P0_2_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR0 &= ~0x00000700UL;\r
+ PORT0->PDR0 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P0_2_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x00000030UL;\r
+ PORT0->HWSEL |= config << 4;\r
+}\r
+\r
+__STATIC_INLINE void P0_2_set(void){\r
+ PORT0->OMR = 0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_2_reset(void){\r
+ PORT0->OMR = 0x00040000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_2_toggle(void){\r
+ PORT0->OMR = 0x00040004UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_2_read(void){\r
+ return(PORT0->IN & 0x00000004UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_3_set_mode(uint8_t mode){\r
+ PORT0->IOCR0 &= ~0xf8000000UL;\r
+ PORT0->IOCR0 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P0_3_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR0 &= ~0x00007000UL;\r
+ PORT0->PDR0 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P0_3_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x000000c0UL;\r
+ PORT0->HWSEL |= config << 6;\r
+}\r
+\r
+__STATIC_INLINE void P0_3_set(void){\r
+ PORT0->OMR = 0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_3_reset(void){\r
+ PORT0->OMR = 0x00080000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_3_toggle(void){\r
+ PORT0->OMR = 0x00080008UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_3_read(void){\r
+ return(PORT0->IN & 0x00000008UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_4_set_mode(uint8_t mode){\r
+ PORT0->IOCR4 &= ~0x000000f8UL;\r
+ PORT0->IOCR4 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P0_4_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR0 &= ~0x00070000UL;\r
+ PORT0->PDR0 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P0_4_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x00000300UL;\r
+ PORT0->HWSEL |= config << 8;\r
+}\r
+\r
+__STATIC_INLINE void P0_4_set(void){\r
+ PORT0->OMR = 0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_4_reset(void){\r
+ PORT0->OMR = 0x00100000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_4_toggle(void){\r
+ PORT0->OMR = 0x00100010UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_4_read(void){\r
+ return(PORT0->IN & 0x00000010UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_5_set_mode(uint8_t mode){\r
+ PORT0->IOCR4 &= ~0x0000f800UL;\r
+ PORT0->IOCR4 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P0_5_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR0 &= ~0x00700000UL;\r
+ PORT0->PDR0 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P0_5_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x00000c00UL;\r
+ PORT0->HWSEL |= config << 10;\r
+}\r
+\r
+__STATIC_INLINE void P0_5_set(void){\r
+ PORT0->OMR = 0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_5_reset(void){\r
+ PORT0->OMR = 0x00200000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_5_toggle(void){\r
+ PORT0->OMR = 0x00200020UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_5_read(void){\r
+ return(PORT0->IN & 0x00000020UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_6_set_mode(uint8_t mode){\r
+ PORT0->IOCR4 &= ~0x00f80000UL;\r
+ PORT0->IOCR4 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P0_6_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR0 &= ~0x07000000UL;\r
+ PORT0->PDR0 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P0_6_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x00003000UL;\r
+ PORT0->HWSEL |= config << 12;\r
+}\r
+\r
+__STATIC_INLINE void P0_6_set(void){\r
+ PORT0->OMR = 0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_6_reset(void){\r
+ PORT0->OMR = 0x00400000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_6_toggle(void){\r
+ PORT0->OMR = 0x00400040UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_6_read(void){\r
+ return(PORT0->IN & 0x00000040UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_7_set_mode(uint8_t mode){\r
+ PORT0->IOCR4 &= ~0xf8000000UL;\r
+ PORT0->IOCR4 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P0_7_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR0 &= ~0x70000000UL;\r
+ PORT0->PDR0 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P0_7_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x0000c000UL;\r
+ PORT0->HWSEL |= config << 14;\r
+}\r
+\r
+__STATIC_INLINE void P0_7_set(void){\r
+ PORT0->OMR = 0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_7_reset(void){\r
+ PORT0->OMR = 0x00800000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_7_toggle(void){\r
+ PORT0->OMR = 0x00800080UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_7_read(void){\r
+ return(PORT0->IN & 0x00000080UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_8_set_mode(uint8_t mode){\r
+ PORT0->IOCR8 &= ~0x000000f8UL;\r
+ PORT0->IOCR8 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P0_8_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR1 &= ~0x00000007UL;\r
+ PORT0->PDR1 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P0_8_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x00030000UL;\r
+ PORT0->HWSEL |= config << 16;\r
+}\r
+\r
+__STATIC_INLINE void P0_8_set(void){\r
+ PORT0->OMR = 0x00000100UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_8_reset(void){\r
+ PORT0->OMR = 0x01000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_8_toggle(void){\r
+ PORT0->OMR = 0x01000100UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_8_read(void){\r
+ return(PORT0->IN & 0x00000100UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_9_set_mode(uint8_t mode){\r
+ PORT0->IOCR8 &= ~0x0000f800UL;\r
+ PORT0->IOCR8 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P0_9_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR1 &= ~0x00000070UL;\r
+ PORT0->PDR1 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P0_9_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x000c0000UL;\r
+ PORT0->HWSEL |= config << 18;\r
+}\r
+\r
+__STATIC_INLINE void P0_9_set(void){\r
+ PORT0->OMR = 0x00000200UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_9_reset(void){\r
+ PORT0->OMR = 0x02000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_9_toggle(void){\r
+ PORT0->OMR = 0x02000200UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_9_read(void){\r
+ return(PORT0->IN & 0x00000200UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_10_set_mode(uint8_t mode){\r
+ PORT0->IOCR8 &= ~0x00f80000UL;\r
+ PORT0->IOCR8 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P0_10_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR1 &= ~0x00000700UL;\r
+ PORT0->PDR1 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P0_10_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x00300000UL;\r
+ PORT0->HWSEL |= config << 20;\r
+}\r
+\r
+__STATIC_INLINE void P0_10_set(void){\r
+ PORT0->OMR = 0x00000400UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_10_reset(void){\r
+ PORT0->OMR = 0x04000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_10_toggle(void){\r
+ PORT0->OMR = 0x04000400UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_10_read(void){\r
+ return(PORT0->IN & 0x00000400UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_11_set_mode(uint8_t mode){\r
+ PORT0->IOCR8 &= ~0xf8000000UL;\r
+ PORT0->IOCR8 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P0_11_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR1 &= ~0x00007000UL;\r
+ PORT0->PDR1 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P0_11_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x00c00000UL;\r
+ PORT0->HWSEL |= config << 22;\r
+}\r
+\r
+__STATIC_INLINE void P0_11_set(void){\r
+ PORT0->OMR = 0x00000800UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_11_reset(void){\r
+ PORT0->OMR = 0x08000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_11_toggle(void){\r
+ PORT0->OMR = 0x08000800UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_11_read(void){\r
+ return(PORT0->IN & 0x00000800UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_12_set_mode(uint8_t mode){\r
+ PORT0->IOCR12 &= ~0x000000f8UL;\r
+ PORT0->IOCR12 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P0_12_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR1 &= ~0x00070000UL;\r
+ PORT0->PDR1 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P0_12_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x03000000UL;\r
+ PORT0->HWSEL |= config << 24;\r
+}\r
+\r
+__STATIC_INLINE void P0_12_set(void){\r
+ PORT0->OMR = 0x00001000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_12_reset(void){\r
+ PORT0->OMR = 0x10000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_12_toggle(void){\r
+ PORT0->OMR = 0x10001000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_12_read(void){\r
+ return(PORT0->IN & 0x00001000UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_13_set_mode(uint8_t mode){\r
+ PORT0->IOCR12 &= ~0x0000f800UL;\r
+ PORT0->IOCR12 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P0_13_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR1 &= ~0x00700000UL;\r
+ PORT0->PDR1 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P0_13_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x0c000000UL;\r
+ PORT0->HWSEL |= config << 26;\r
+}\r
+\r
+__STATIC_INLINE void P0_13_set(void){\r
+ PORT0->OMR = 0x00002000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_13_reset(void){\r
+ PORT0->OMR = 0x20000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_13_toggle(void){\r
+ PORT0->OMR = 0x20002000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_13_read(void){\r
+ return(PORT0->IN & 0x00002000UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_14_set_mode(uint8_t mode){\r
+ PORT0->IOCR12 &= ~0x00f80000UL;\r
+ PORT0->IOCR12 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P0_14_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR1 &= ~0x07000000UL;\r
+ PORT0->PDR1 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P0_14_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0x30000000UL;\r
+ PORT0->HWSEL |= config << 28;\r
+}\r
+\r
+__STATIC_INLINE void P0_14_set(void){\r
+ PORT0->OMR = 0x00004000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_14_reset(void){\r
+ PORT0->OMR = 0x40000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_14_toggle(void){\r
+ PORT0->OMR = 0x40004000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_14_read(void){\r
+ return(PORT0->IN & 0x00004000UL);\r
+}\r
+\r
+__STATIC_INLINE void P0_15_set_mode(uint8_t mode){\r
+ PORT0->IOCR12 &= ~0xf8000000UL;\r
+ PORT0->IOCR12 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P0_15_set_driver_strength(uint8_t strength){\r
+ PORT0->PDR1 &= ~0x70000000UL;\r
+ PORT0->PDR1 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P0_15_set_hwsel(uint32_t config){\r
+ PORT0->HWSEL &= ~0xc0000000UL;\r
+ PORT0->HWSEL |= config << 30;\r
+}\r
+\r
+__STATIC_INLINE void P0_15_set(void){\r
+ PORT0->OMR = 0x00008000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_15_reset(void){\r
+ PORT0->OMR = 0x80000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P0_15_toggle(void){\r
+ PORT0->OMR = 0x80008000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P0_15_read(void){\r
+ return(PORT0->IN & 0x00008000UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_0_set_mode(uint8_t mode){\r
+ PORT1->IOCR0 &= ~0x000000f8UL;\r
+ PORT1->IOCR0 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P1_0_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR0 &= ~0x00000007UL;\r
+ PORT1->PDR0 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P1_0_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x00000003UL;\r
+ PORT1->HWSEL |= config << 0;\r
+}\r
+\r
+__STATIC_INLINE void P1_0_set(void){\r
+ PORT1->OMR = 0x00000001UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_0_reset(void){\r
+ PORT1->OMR = 0x00010000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_0_toggle(void){\r
+ PORT1->OMR = 0x00010001UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_0_read(void){\r
+ return(PORT1->IN & 0x00000001UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_1_set_mode(uint8_t mode){\r
+ PORT1->IOCR0 &= ~0x0000f800UL;\r
+ PORT1->IOCR0 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P1_1_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR0 &= ~0x00000070UL;\r
+ PORT1->PDR0 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P1_1_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x0000000cUL;\r
+ PORT1->HWSEL |= config << 2;\r
+}\r
+\r
+__STATIC_INLINE void P1_1_set(void){\r
+ PORT1->OMR = 0x00000002UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_1_reset(void){\r
+ PORT1->OMR = 0x00020000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_1_toggle(void){\r
+ PORT1->OMR = 0x00020002UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_1_read(void){\r
+ return(PORT1->IN & 0x00000002UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_2_set_mode(uint8_t mode){\r
+ PORT1->IOCR0 &= ~0x00f80000UL;\r
+ PORT1->IOCR0 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P1_2_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR0 &= ~0x00000700UL;\r
+ PORT1->PDR0 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P1_2_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x00000030UL;\r
+ PORT1->HWSEL |= config << 4;\r
+}\r
+\r
+__STATIC_INLINE void P1_2_set(void){\r
+ PORT1->OMR = 0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_2_reset(void){\r
+ PORT1->OMR = 0x00040000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_2_toggle(void){\r
+ PORT1->OMR = 0x00040004UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_2_read(void){\r
+ return(PORT1->IN & 0x00000004UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_3_set_mode(uint8_t mode){\r
+ PORT1->IOCR0 &= ~0xf8000000UL;\r
+ PORT1->IOCR0 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P1_3_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR0 &= ~0x00007000UL;\r
+ PORT1->PDR0 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P1_3_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x000000c0UL;\r
+ PORT1->HWSEL |= config << 6;\r
+}\r
+\r
+__STATIC_INLINE void P1_3_set(void){\r
+ PORT1->OMR = 0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_3_reset(void){\r
+ PORT1->OMR = 0x00080000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_3_toggle(void){\r
+ PORT1->OMR = 0x00080008UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_3_read(void){\r
+ return(PORT1->IN & 0x00000008UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_4_set_mode(uint8_t mode){\r
+ PORT1->IOCR4 &= ~0x000000f8UL;\r
+ PORT1->IOCR4 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P1_4_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR0 &= ~0x00070000UL;\r
+ PORT1->PDR0 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P1_4_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x00000300UL;\r
+ PORT1->HWSEL |= config << 8;\r
+}\r
+\r
+__STATIC_INLINE void P1_4_set(void){\r
+ PORT1->OMR = 0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_4_reset(void){\r
+ PORT1->OMR = 0x00100000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_4_toggle(void){\r
+ PORT1->OMR = 0x00100010UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_4_read(void){\r
+ return(PORT1->IN & 0x00000010UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_5_set_mode(uint8_t mode){\r
+ PORT1->IOCR4 &= ~0x0000f800UL;\r
+ PORT1->IOCR4 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P1_5_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR0 &= ~0x00700000UL;\r
+ PORT1->PDR0 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P1_5_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x00000c00UL;\r
+ PORT1->HWSEL |= config << 10;\r
+}\r
+\r
+__STATIC_INLINE void P1_5_set(void){\r
+ PORT1->OMR = 0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_5_reset(void){\r
+ PORT1->OMR = 0x00200000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_5_toggle(void){\r
+ PORT1->OMR = 0x00200020UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_5_read(void){\r
+ return(PORT1->IN & 0x00000020UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_6_set_mode(uint8_t mode){\r
+ PORT1->IOCR4 &= ~0x00f80000UL;\r
+ PORT1->IOCR4 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P1_6_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR0 &= ~0x07000000UL;\r
+ PORT1->PDR0 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P1_6_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x00003000UL;\r
+ PORT1->HWSEL |= config << 12;\r
+}\r
+\r
+__STATIC_INLINE void P1_6_set(void){\r
+ PORT1->OMR = 0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_6_reset(void){\r
+ PORT1->OMR = 0x00400000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_6_toggle(void){\r
+ PORT1->OMR = 0x00400040UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_6_read(void){\r
+ return(PORT1->IN & 0x00000040UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_7_set_mode(uint8_t mode){\r
+ PORT1->IOCR4 &= ~0xf8000000UL;\r
+ PORT1->IOCR4 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P1_7_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR0 &= ~0x70000000UL;\r
+ PORT1->PDR0 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P1_7_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x0000c000UL;\r
+ PORT1->HWSEL |= config << 14;\r
+}\r
+\r
+__STATIC_INLINE void P1_7_set(void){\r
+ PORT1->OMR = 0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_7_reset(void){\r
+ PORT1->OMR = 0x00800000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_7_toggle(void){\r
+ PORT1->OMR = 0x00800080UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_7_read(void){\r
+ return(PORT1->IN & 0x00000080UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_8_set_mode(uint8_t mode){\r
+ PORT1->IOCR8 &= ~0x000000f8UL;\r
+ PORT1->IOCR8 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P1_8_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR1 &= ~0x00000007UL;\r
+ PORT1->PDR1 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P1_8_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x00030000UL;\r
+ PORT1->HWSEL |= config << 16;\r
+}\r
+\r
+__STATIC_INLINE void P1_8_set(void){\r
+ PORT1->OMR = 0x00000100UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_8_reset(void){\r
+ PORT1->OMR = 0x01000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_8_toggle(void){\r
+ PORT1->OMR = 0x01000100UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_8_read(void){\r
+ return(PORT1->IN & 0x00000100UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_9_set_mode(uint8_t mode){\r
+ PORT1->IOCR8 &= ~0x0000f800UL;\r
+ PORT1->IOCR8 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P1_9_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR1 &= ~0x00000070UL;\r
+ PORT1->PDR1 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P1_9_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x000c0000UL;\r
+ PORT1->HWSEL |= config << 18;\r
+}\r
+\r
+__STATIC_INLINE void P1_9_set(void){\r
+ PORT1->OMR = 0x00000200UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_9_reset(void){\r
+ PORT1->OMR = 0x02000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_9_toggle(void){\r
+ PORT1->OMR = 0x02000200UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_9_read(void){\r
+ return(PORT1->IN & 0x00000200UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_10_set_mode(uint8_t mode){\r
+ PORT1->IOCR8 &= ~0x00f80000UL;\r
+ PORT1->IOCR8 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P1_10_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR1 &= ~0x00000700UL;\r
+ PORT1->PDR1 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P1_10_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x00300000UL;\r
+ PORT1->HWSEL |= config << 20;\r
+}\r
+\r
+__STATIC_INLINE void P1_10_set(void){\r
+ PORT1->OMR = 0x00000400UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_10_reset(void){\r
+ PORT1->OMR = 0x04000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_10_toggle(void){\r
+ PORT1->OMR = 0x04000400UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_10_read(void){\r
+ return(PORT1->IN & 0x00000400UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_11_set_mode(uint8_t mode){\r
+ PORT1->IOCR8 &= ~0xf8000000UL;\r
+ PORT1->IOCR8 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P1_11_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR1 &= ~0x00007000UL;\r
+ PORT1->PDR1 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P1_11_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x00c00000UL;\r
+ PORT1->HWSEL |= config << 22;\r
+}\r
+\r
+__STATIC_INLINE void P1_11_set(void){\r
+ PORT1->OMR = 0x00000800UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_11_reset(void){\r
+ PORT1->OMR = 0x08000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_11_toggle(void){\r
+ PORT1->OMR = 0x08000800UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_11_read(void){\r
+ return(PORT1->IN & 0x00000800UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_12_set_mode(uint8_t mode){\r
+ PORT1->IOCR12 &= ~0x000000f8UL;\r
+ PORT1->IOCR12 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P1_12_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR1 &= ~0x00070000UL;\r
+ PORT1->PDR1 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P1_12_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x03000000UL;\r
+ PORT1->HWSEL |= config << 24;\r
+}\r
+\r
+__STATIC_INLINE void P1_12_set(void){\r
+ PORT1->OMR = 0x00001000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_12_reset(void){\r
+ PORT1->OMR = 0x10000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_12_toggle(void){\r
+ PORT1->OMR = 0x10001000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_12_read(void){\r
+ return(PORT1->IN & 0x00001000UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_13_set_mode(uint8_t mode){\r
+ PORT1->IOCR12 &= ~0x0000f800UL;\r
+ PORT1->IOCR12 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P1_13_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR1 &= ~0x00700000UL;\r
+ PORT1->PDR1 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P1_13_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x0c000000UL;\r
+ PORT1->HWSEL |= config << 26;\r
+}\r
+\r
+__STATIC_INLINE void P1_13_set(void){\r
+ PORT1->OMR = 0x00002000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_13_reset(void){\r
+ PORT1->OMR = 0x20000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_13_toggle(void){\r
+ PORT1->OMR = 0x20002000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_13_read(void){\r
+ return(PORT1->IN & 0x00002000UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_14_set_mode(uint8_t mode){\r
+ PORT1->IOCR12 &= ~0x00f80000UL;\r
+ PORT1->IOCR12 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P1_14_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR1 &= ~0x07000000UL;\r
+ PORT1->PDR1 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P1_14_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0x30000000UL;\r
+ PORT1->HWSEL |= config << 28;\r
+}\r
+\r
+__STATIC_INLINE void P1_14_set(void){\r
+ PORT1->OMR = 0x00004000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_14_reset(void){\r
+ PORT1->OMR = 0x40000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_14_toggle(void){\r
+ PORT1->OMR = 0x40004000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_14_read(void){\r
+ return(PORT1->IN & 0x00004000UL);\r
+}\r
+\r
+__STATIC_INLINE void P1_15_set_mode(uint8_t mode){\r
+ PORT1->IOCR12 &= ~0xf8000000UL;\r
+ PORT1->IOCR12 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P1_15_set_driver_strength(uint8_t strength){\r
+ PORT1->PDR1 &= ~0x70000000UL;\r
+ PORT1->PDR1 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P1_15_set_hwsel(uint32_t config){\r
+ PORT1->HWSEL &= ~0xc0000000UL;\r
+ PORT1->HWSEL |= config << 30;\r
+}\r
+\r
+__STATIC_INLINE void P1_15_set(void){\r
+ PORT1->OMR = 0x00008000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_15_reset(void){\r
+ PORT1->OMR = 0x80000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P1_15_toggle(void){\r
+ PORT1->OMR = 0x80008000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P1_15_read(void){\r
+ return(PORT1->IN & 0x00008000UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_0_set_mode(uint8_t mode){\r
+ PORT2->IOCR0 &= ~0x000000f8UL;\r
+ PORT2->IOCR0 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P2_0_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR0 &= ~0x00000007UL;\r
+ PORT2->PDR0 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P2_0_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x00000003UL;\r
+ PORT2->HWSEL |= config << 0;\r
+}\r
+\r
+__STATIC_INLINE void P2_0_set(void){\r
+ PORT2->OMR = 0x00000001UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_0_reset(void){\r
+ PORT2->OMR = 0x00010000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_0_toggle(void){\r
+ PORT2->OMR = 0x00010001UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_0_read(void){\r
+ return(PORT2->IN & 0x00000001UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_1_set_mode(uint8_t mode){\r
+ PORT2->IOCR0 &= ~0x0000f800UL;\r
+ PORT2->IOCR0 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P2_1_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR0 &= ~0x00000070UL;\r
+ PORT2->PDR0 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P2_1_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x0000000cUL;\r
+ PORT2->HWSEL |= config << 2;\r
+}\r
+\r
+__STATIC_INLINE void P2_1_set(void){\r
+ PORT2->OMR = 0x00000002UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_1_reset(void){\r
+ PORT2->OMR = 0x00020000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_1_toggle(void){\r
+ PORT2->OMR = 0x00020002UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_1_read(void){\r
+ return(PORT2->IN & 0x00000002UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_2_set_mode(uint8_t mode){\r
+ PORT2->IOCR0 &= ~0x00f80000UL;\r
+ PORT2->IOCR0 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P2_2_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR0 &= ~0x00000700UL;\r
+ PORT2->PDR0 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P2_2_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x00000030UL;\r
+ PORT2->HWSEL |= config << 4;\r
+}\r
+\r
+__STATIC_INLINE void P2_2_set(void){\r
+ PORT2->OMR = 0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_2_reset(void){\r
+ PORT2->OMR = 0x00040000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_2_toggle(void){\r
+ PORT2->OMR = 0x00040004UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_2_read(void){\r
+ return(PORT2->IN & 0x00000004UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_3_set_mode(uint8_t mode){\r
+ PORT2->IOCR0 &= ~0xf8000000UL;\r
+ PORT2->IOCR0 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P2_3_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR0 &= ~0x00007000UL;\r
+ PORT2->PDR0 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P2_3_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x000000c0UL;\r
+ PORT2->HWSEL |= config << 6;\r
+}\r
+\r
+__STATIC_INLINE void P2_3_set(void){\r
+ PORT2->OMR = 0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_3_reset(void){\r
+ PORT2->OMR = 0x00080000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_3_toggle(void){\r
+ PORT2->OMR = 0x00080008UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_3_read(void){\r
+ return(PORT2->IN & 0x00000008UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_4_set_mode(uint8_t mode){\r
+ PORT2->IOCR4 &= ~0x000000f8UL;\r
+ PORT2->IOCR4 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P2_4_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR0 &= ~0x00070000UL;\r
+ PORT2->PDR0 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P2_4_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x00000300UL;\r
+ PORT2->HWSEL |= config << 8;\r
+}\r
+\r
+__STATIC_INLINE void P2_4_set(void){\r
+ PORT2->OMR = 0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_4_reset(void){\r
+ PORT2->OMR = 0x00100000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_4_toggle(void){\r
+ PORT2->OMR = 0x00100010UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_4_read(void){\r
+ return(PORT2->IN & 0x00000010UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_5_set_mode(uint8_t mode){\r
+ PORT2->IOCR4 &= ~0x0000f800UL;\r
+ PORT2->IOCR4 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P2_5_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR0 &= ~0x00700000UL;\r
+ PORT2->PDR0 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P2_5_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x00000c00UL;\r
+ PORT2->HWSEL |= config << 10;\r
+}\r
+\r
+__STATIC_INLINE void P2_5_set(void){\r
+ PORT2->OMR = 0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_5_reset(void){\r
+ PORT2->OMR = 0x00200000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_5_toggle(void){\r
+ PORT2->OMR = 0x00200020UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_5_read(void){\r
+ return(PORT2->IN & 0x00000020UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_6_set_mode(uint8_t mode){\r
+ PORT2->IOCR4 &= ~0x00f80000UL;\r
+ PORT2->IOCR4 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P2_6_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR0 &= ~0x07000000UL;\r
+ PORT2->PDR0 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P2_6_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x00003000UL;\r
+ PORT2->HWSEL |= config << 12;\r
+}\r
+\r
+__STATIC_INLINE void P2_6_set(void){\r
+ PORT2->OMR = 0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_6_reset(void){\r
+ PORT2->OMR = 0x00400000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_6_toggle(void){\r
+ PORT2->OMR = 0x00400040UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_6_read(void){\r
+ return(PORT2->IN & 0x00000040UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_7_set_mode(uint8_t mode){\r
+ PORT2->IOCR4 &= ~0xf8000000UL;\r
+ PORT2->IOCR4 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P2_7_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR0 &= ~0x70000000UL;\r
+ PORT2->PDR0 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P2_7_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x0000c000UL;\r
+ PORT2->HWSEL |= config << 14;\r
+}\r
+\r
+__STATIC_INLINE void P2_7_set(void){\r
+ PORT2->OMR = 0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_7_reset(void){\r
+ PORT2->OMR = 0x00800000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_7_toggle(void){\r
+ PORT2->OMR = 0x00800080UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_7_read(void){\r
+ return(PORT2->IN & 0x00000080UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_8_set_mode(uint8_t mode){\r
+ PORT2->IOCR8 &= ~0x000000f8UL;\r
+ PORT2->IOCR8 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P2_8_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR1 &= ~0x00000007UL;\r
+ PORT2->PDR1 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P2_8_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x00030000UL;\r
+ PORT2->HWSEL |= config << 16;\r
+}\r
+\r
+__STATIC_INLINE void P2_8_set(void){\r
+ PORT2->OMR = 0x00000100UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_8_reset(void){\r
+ PORT2->OMR = 0x01000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_8_toggle(void){\r
+ PORT2->OMR = 0x01000100UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_8_read(void){\r
+ return(PORT2->IN & 0x00000100UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_9_set_mode(uint8_t mode){\r
+ PORT2->IOCR8 &= ~0x0000f800UL;\r
+ PORT2->IOCR8 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P2_9_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR1 &= ~0x00000070UL;\r
+ PORT2->PDR1 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P2_9_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x000c0000UL;\r
+ PORT2->HWSEL |= config << 18;\r
+}\r
+\r
+__STATIC_INLINE void P2_9_set(void){\r
+ PORT2->OMR = 0x00000200UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_9_reset(void){\r
+ PORT2->OMR = 0x02000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_9_toggle(void){\r
+ PORT2->OMR = 0x02000200UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_9_read(void){\r
+ return(PORT2->IN & 0x00000200UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_10_set_mode(uint8_t mode){\r
+ PORT2->IOCR8 &= ~0x00f80000UL;\r
+ PORT2->IOCR8 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P2_10_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR1 &= ~0x00000700UL;\r
+ PORT2->PDR1 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P2_10_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x00300000UL;\r
+ PORT2->HWSEL |= config << 20;\r
+}\r
+\r
+__STATIC_INLINE void P2_10_set(void){\r
+ PORT2->OMR = 0x00000400UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_10_reset(void){\r
+ PORT2->OMR = 0x04000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_10_toggle(void){\r
+ PORT2->OMR = 0x04000400UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_10_read(void){\r
+ return(PORT2->IN & 0x00000400UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_11_set_mode(uint8_t mode){\r
+ PORT2->IOCR8 &= ~0xf8000000UL;\r
+ PORT2->IOCR8 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P2_11_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR1 &= ~0x00007000UL;\r
+ PORT2->PDR1 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P2_11_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x00c00000UL;\r
+ PORT2->HWSEL |= config << 22;\r
+}\r
+\r
+__STATIC_INLINE void P2_11_set(void){\r
+ PORT2->OMR = 0x00000800UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_11_reset(void){\r
+ PORT2->OMR = 0x08000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_11_toggle(void){\r
+ PORT2->OMR = 0x08000800UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_11_read(void){\r
+ return(PORT2->IN & 0x00000800UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_12_set_mode(uint8_t mode){\r
+ PORT2->IOCR12 &= ~0x000000f8UL;\r
+ PORT2->IOCR12 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P2_12_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR1 &= ~0x00070000UL;\r
+ PORT2->PDR1 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P2_12_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x03000000UL;\r
+ PORT2->HWSEL |= config << 24;\r
+}\r
+\r
+__STATIC_INLINE void P2_12_set(void){\r
+ PORT2->OMR = 0x00001000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_12_reset(void){\r
+ PORT2->OMR = 0x10000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_12_toggle(void){\r
+ PORT2->OMR = 0x10001000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_12_read(void){\r
+ return(PORT2->IN & 0x00001000UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_13_set_mode(uint8_t mode){\r
+ PORT2->IOCR12 &= ~0x0000f800UL;\r
+ PORT2->IOCR12 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P2_13_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR1 &= ~0x00700000UL;\r
+ PORT2->PDR1 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P2_13_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x0c000000UL;\r
+ PORT2->HWSEL |= config << 26;\r
+}\r
+\r
+__STATIC_INLINE void P2_13_set(void){\r
+ PORT2->OMR = 0x00002000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_13_reset(void){\r
+ PORT2->OMR = 0x20000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_13_toggle(void){\r
+ PORT2->OMR = 0x20002000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_13_read(void){\r
+ return(PORT2->IN & 0x00002000UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_14_set_mode(uint8_t mode){\r
+ PORT2->IOCR12 &= ~0x00f80000UL;\r
+ PORT2->IOCR12 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P2_14_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR1 &= ~0x07000000UL;\r
+ PORT2->PDR1 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P2_14_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0x30000000UL;\r
+ PORT2->HWSEL |= config << 28;\r
+}\r
+\r
+__STATIC_INLINE void P2_14_set(void){\r
+ PORT2->OMR = 0x00004000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_14_reset(void){\r
+ PORT2->OMR = 0x40000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_14_toggle(void){\r
+ PORT2->OMR = 0x40004000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_14_read(void){\r
+ return(PORT2->IN & 0x00004000UL);\r
+}\r
+\r
+__STATIC_INLINE void P2_15_set_mode(uint8_t mode){\r
+ PORT2->IOCR12 &= ~0xf8000000UL;\r
+ PORT2->IOCR12 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P2_15_set_driver_strength(uint8_t strength){\r
+ PORT2->PDR1 &= ~0x70000000UL;\r
+ PORT2->PDR1 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P2_15_set_hwsel(uint32_t config){\r
+ PORT2->HWSEL &= ~0xc0000000UL;\r
+ PORT2->HWSEL |= config << 30;\r
+}\r
+\r
+__STATIC_INLINE void P2_15_set(void){\r
+ PORT2->OMR = 0x00008000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_15_reset(void){\r
+ PORT2->OMR = 0x80000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P2_15_toggle(void){\r
+ PORT2->OMR = 0x80008000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P2_15_read(void){\r
+ return(PORT2->IN & 0x00008000UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_0_set_mode(uint8_t mode){\r
+ PORT3->IOCR0 &= ~0x000000f8UL;\r
+ PORT3->IOCR0 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P3_0_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR0 &= ~0x00000007UL;\r
+ PORT3->PDR0 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P3_0_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x00000003UL;\r
+ PORT3->HWSEL |= config << 0;\r
+}\r
+\r
+__STATIC_INLINE void P3_0_set(void){\r
+ PORT3->OMR = 0x00000001UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_0_reset(void){\r
+ PORT3->OMR = 0x00010000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_0_toggle(void){\r
+ PORT3->OMR = 0x00010001UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_0_read(void){\r
+ return(PORT3->IN & 0x00000001UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_1_set_mode(uint8_t mode){\r
+ PORT3->IOCR0 &= ~0x0000f800UL;\r
+ PORT3->IOCR0 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P3_1_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR0 &= ~0x00000070UL;\r
+ PORT3->PDR0 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P3_1_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x0000000cUL;\r
+ PORT3->HWSEL |= config << 2;\r
+}\r
+\r
+__STATIC_INLINE void P3_1_set(void){\r
+ PORT3->OMR = 0x00000002UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_1_reset(void){\r
+ PORT3->OMR = 0x00020000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_1_toggle(void){\r
+ PORT3->OMR = 0x00020002UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_1_read(void){\r
+ return(PORT3->IN & 0x00000002UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_2_set_mode(uint8_t mode){\r
+ PORT3->IOCR0 &= ~0x00f80000UL;\r
+ PORT3->IOCR0 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P3_2_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR0 &= ~0x00000700UL;\r
+ PORT3->PDR0 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P3_2_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x00000030UL;\r
+ PORT3->HWSEL |= config << 4;\r
+}\r
+\r
+__STATIC_INLINE void P3_2_set(void){\r
+ PORT3->OMR = 0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_2_reset(void){\r
+ PORT3->OMR = 0x00040000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_2_toggle(void){\r
+ PORT3->OMR = 0x00040004UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_2_read(void){\r
+ return(PORT3->IN & 0x00000004UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_3_set_mode(uint8_t mode){\r
+ PORT3->IOCR0 &= ~0xf8000000UL;\r
+ PORT3->IOCR0 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P3_3_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR0 &= ~0x00007000UL;\r
+ PORT3->PDR0 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P3_3_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x000000c0UL;\r
+ PORT3->HWSEL |= config << 6;\r
+}\r
+\r
+__STATIC_INLINE void P3_3_set(void){\r
+ PORT3->OMR = 0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_3_reset(void){\r
+ PORT3->OMR = 0x00080000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_3_toggle(void){\r
+ PORT3->OMR = 0x00080008UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_3_read(void){\r
+ return(PORT3->IN & 0x00000008UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_4_set_mode(uint8_t mode){\r
+ PORT3->IOCR4 &= ~0x000000f8UL;\r
+ PORT3->IOCR4 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P3_4_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR0 &= ~0x00070000UL;\r
+ PORT3->PDR0 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P3_4_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x00000300UL;\r
+ PORT3->HWSEL |= config << 8;\r
+}\r
+\r
+__STATIC_INLINE void P3_4_set(void){\r
+ PORT3->OMR = 0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_4_reset(void){\r
+ PORT3->OMR = 0x00100000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_4_toggle(void){\r
+ PORT3->OMR = 0x00100010UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_4_read(void){\r
+ return(PORT3->IN & 0x00000010UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_5_set_mode(uint8_t mode){\r
+ PORT3->IOCR4 &= ~0x0000f800UL;\r
+ PORT3->IOCR4 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P3_5_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR0 &= ~0x00700000UL;\r
+ PORT3->PDR0 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P3_5_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x00000c00UL;\r
+ PORT3->HWSEL |= config << 10;\r
+}\r
+\r
+__STATIC_INLINE void P3_5_set(void){\r
+ PORT3->OMR = 0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_5_reset(void){\r
+ PORT3->OMR = 0x00200000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_5_toggle(void){\r
+ PORT3->OMR = 0x00200020UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_5_read(void){\r
+ return(PORT3->IN & 0x00000020UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_6_set_mode(uint8_t mode){\r
+ PORT3->IOCR4 &= ~0x00f80000UL;\r
+ PORT3->IOCR4 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P3_6_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR0 &= ~0x07000000UL;\r
+ PORT3->PDR0 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P3_6_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x00003000UL;\r
+ PORT3->HWSEL |= config << 12;\r
+}\r
+\r
+__STATIC_INLINE void P3_6_set(void){\r
+ PORT3->OMR = 0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_6_reset(void){\r
+ PORT3->OMR = 0x00400000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_6_toggle(void){\r
+ PORT3->OMR = 0x00400040UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_6_read(void){\r
+ return(PORT3->IN & 0x00000040UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_7_set_mode(uint8_t mode){\r
+ PORT3->IOCR4 &= ~0xf8000000UL;\r
+ PORT3->IOCR4 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P3_7_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR0 &= ~0x70000000UL;\r
+ PORT3->PDR0 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P3_7_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x0000c000UL;\r
+ PORT3->HWSEL |= config << 14;\r
+}\r
+\r
+__STATIC_INLINE void P3_7_set(void){\r
+ PORT3->OMR = 0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_7_reset(void){\r
+ PORT3->OMR = 0x00800000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_7_toggle(void){\r
+ PORT3->OMR = 0x00800080UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_7_read(void){\r
+ return(PORT3->IN & 0x00000080UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_8_set_mode(uint8_t mode){\r
+ PORT3->IOCR8 &= ~0x000000f8UL;\r
+ PORT3->IOCR8 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P3_8_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR1 &= ~0x00000007UL;\r
+ PORT3->PDR1 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P3_8_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x00030000UL;\r
+ PORT3->HWSEL |= config << 16;\r
+}\r
+\r
+__STATIC_INLINE void P3_8_set(void){\r
+ PORT3->OMR = 0x00000100UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_8_reset(void){\r
+ PORT3->OMR = 0x01000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_8_toggle(void){\r
+ PORT3->OMR = 0x01000100UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_8_read(void){\r
+ return(PORT3->IN & 0x00000100UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_9_set_mode(uint8_t mode){\r
+ PORT3->IOCR8 &= ~0x0000f800UL;\r
+ PORT3->IOCR8 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P3_9_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR1 &= ~0x00000070UL;\r
+ PORT3->PDR1 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P3_9_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x000c0000UL;\r
+ PORT3->HWSEL |= config << 18;\r
+}\r
+\r
+__STATIC_INLINE void P3_9_set(void){\r
+ PORT3->OMR = 0x00000200UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_9_reset(void){\r
+ PORT3->OMR = 0x02000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_9_toggle(void){\r
+ PORT3->OMR = 0x02000200UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_9_read(void){\r
+ return(PORT3->IN & 0x00000200UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_10_set_mode(uint8_t mode){\r
+ PORT3->IOCR8 &= ~0x00f80000UL;\r
+ PORT3->IOCR8 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P3_10_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR1 &= ~0x00000700UL;\r
+ PORT3->PDR1 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P3_10_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x00300000UL;\r
+ PORT3->HWSEL |= config << 20;\r
+}\r
+\r
+__STATIC_INLINE void P3_10_set(void){\r
+ PORT3->OMR = 0x00000400UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_10_reset(void){\r
+ PORT3->OMR = 0x04000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_10_toggle(void){\r
+ PORT3->OMR = 0x04000400UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_10_read(void){\r
+ return(PORT3->IN & 0x00000400UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_11_set_mode(uint8_t mode){\r
+ PORT3->IOCR8 &= ~0xf8000000UL;\r
+ PORT3->IOCR8 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P3_11_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR1 &= ~0x00007000UL;\r
+ PORT3->PDR1 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P3_11_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x00c00000UL;\r
+ PORT3->HWSEL |= config << 22;\r
+}\r
+\r
+__STATIC_INLINE void P3_11_set(void){\r
+ PORT3->OMR = 0x00000800UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_11_reset(void){\r
+ PORT3->OMR = 0x08000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_11_toggle(void){\r
+ PORT3->OMR = 0x08000800UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_11_read(void){\r
+ return(PORT3->IN & 0x00000800UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_12_set_mode(uint8_t mode){\r
+ PORT3->IOCR12 &= ~0x000000f8UL;\r
+ PORT3->IOCR12 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P3_12_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR1 &= ~0x00070000UL;\r
+ PORT3->PDR1 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P3_12_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x03000000UL;\r
+ PORT3->HWSEL |= config << 24;\r
+}\r
+\r
+__STATIC_INLINE void P3_12_set(void){\r
+ PORT3->OMR = 0x00001000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_12_reset(void){\r
+ PORT3->OMR = 0x10000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_12_toggle(void){\r
+ PORT3->OMR = 0x10001000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_12_read(void){\r
+ return(PORT3->IN & 0x00001000UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_13_set_mode(uint8_t mode){\r
+ PORT3->IOCR12 &= ~0x0000f800UL;\r
+ PORT3->IOCR12 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P3_13_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR1 &= ~0x00700000UL;\r
+ PORT3->PDR1 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P3_13_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x0c000000UL;\r
+ PORT3->HWSEL |= config << 26;\r
+}\r
+\r
+__STATIC_INLINE void P3_13_set(void){\r
+ PORT3->OMR = 0x00002000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_13_reset(void){\r
+ PORT3->OMR = 0x20000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_13_toggle(void){\r
+ PORT3->OMR = 0x20002000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_13_read(void){\r
+ return(PORT3->IN & 0x00002000UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_14_set_mode(uint8_t mode){\r
+ PORT3->IOCR12 &= ~0x00f80000UL;\r
+ PORT3->IOCR12 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P3_14_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR1 &= ~0x07000000UL;\r
+ PORT3->PDR1 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P3_14_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0x30000000UL;\r
+ PORT3->HWSEL |= config << 28;\r
+}\r
+\r
+__STATIC_INLINE void P3_14_set(void){\r
+ PORT3->OMR = 0x00004000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_14_reset(void){\r
+ PORT3->OMR = 0x40000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_14_toggle(void){\r
+ PORT3->OMR = 0x40004000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_14_read(void){\r
+ return(PORT3->IN & 0x00004000UL);\r
+}\r
+\r
+__STATIC_INLINE void P3_15_set_mode(uint8_t mode){\r
+ PORT3->IOCR12 &= ~0xf8000000UL;\r
+ PORT3->IOCR12 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P3_15_set_driver_strength(uint8_t strength){\r
+ PORT3->PDR1 &= ~0x70000000UL;\r
+ PORT3->PDR1 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P3_15_set_hwsel(uint32_t config){\r
+ PORT3->HWSEL &= ~0xc0000000UL;\r
+ PORT3->HWSEL |= config << 30;\r
+}\r
+\r
+__STATIC_INLINE void P3_15_set(void){\r
+ PORT3->OMR = 0x00008000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_15_reset(void){\r
+ PORT3->OMR = 0x80000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P3_15_toggle(void){\r
+ PORT3->OMR = 0x80008000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P3_15_read(void){\r
+ return(PORT3->IN & 0x00008000UL);\r
+}\r
+\r
+__STATIC_INLINE void P4_0_set_mode(uint8_t mode){\r
+ PORT4->IOCR0 &= ~0x000000f8UL;\r
+ PORT4->IOCR0 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P4_0_set_driver_strength(uint8_t strength){\r
+ PORT4->PDR0 &= ~0x00000007UL;\r
+ PORT4->PDR0 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P4_0_set_hwsel(uint32_t config){\r
+ PORT4->HWSEL &= ~0x00000003UL;\r
+ PORT4->HWSEL |= config << 0;\r
+}\r
+\r
+__STATIC_INLINE void P4_0_set(void){\r
+ PORT4->OMR = 0x00000001UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_0_reset(void){\r
+ PORT4->OMR = 0x00010000UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_0_toggle(void){\r
+ PORT4->OMR = 0x00010001UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P4_0_read(void){\r
+ return(PORT4->IN & 0x00000001UL);\r
+}\r
+\r
+__STATIC_INLINE void P4_1_set_mode(uint8_t mode){\r
+ PORT4->IOCR0 &= ~0x0000f800UL;\r
+ PORT4->IOCR0 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P4_1_set_driver_strength(uint8_t strength){\r
+ PORT4->PDR0 &= ~0x00000070UL;\r
+ PORT4->PDR0 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P4_1_set_hwsel(uint32_t config){\r
+ PORT4->HWSEL &= ~0x0000000cUL;\r
+ PORT4->HWSEL |= config << 2;\r
+}\r
+\r
+__STATIC_INLINE void P4_1_set(void){\r
+ PORT4->OMR = 0x00000002UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_1_reset(void){\r
+ PORT4->OMR = 0x00020000UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_1_toggle(void){\r
+ PORT4->OMR = 0x00020002UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P4_1_read(void){\r
+ return(PORT4->IN & 0x00000002UL);\r
+}\r
+\r
+__STATIC_INLINE void P4_2_set_mode(uint8_t mode){\r
+ PORT4->IOCR0 &= ~0x00f80000UL;\r
+ PORT4->IOCR0 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P4_2_set_driver_strength(uint8_t strength){\r
+ PORT4->PDR0 &= ~0x00000700UL;\r
+ PORT4->PDR0 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P4_2_set_hwsel(uint32_t config){\r
+ PORT4->HWSEL &= ~0x00000030UL;\r
+ PORT4->HWSEL |= config << 4;\r
+}\r
+\r
+__STATIC_INLINE void P4_2_set(void){\r
+ PORT4->OMR = 0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_2_reset(void){\r
+ PORT4->OMR = 0x00040000UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_2_toggle(void){\r
+ PORT4->OMR = 0x00040004UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P4_2_read(void){\r
+ return(PORT4->IN & 0x00000004UL);\r
+}\r
+\r
+__STATIC_INLINE void P4_3_set_mode(uint8_t mode){\r
+ PORT4->IOCR0 &= ~0xf8000000UL;\r
+ PORT4->IOCR0 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P4_3_set_driver_strength(uint8_t strength){\r
+ PORT4->PDR0 &= ~0x00007000UL;\r
+ PORT4->PDR0 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P4_3_set_hwsel(uint32_t config){\r
+ PORT4->HWSEL &= ~0x000000c0UL;\r
+ PORT4->HWSEL |= config << 6;\r
+}\r
+\r
+__STATIC_INLINE void P4_3_set(void){\r
+ PORT4->OMR = 0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_3_reset(void){\r
+ PORT4->OMR = 0x00080000UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_3_toggle(void){\r
+ PORT4->OMR = 0x00080008UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P4_3_read(void){\r
+ return(PORT4->IN & 0x00000008UL);\r
+}\r
+\r
+__STATIC_INLINE void P4_4_set_mode(uint8_t mode){\r
+ PORT4->IOCR4 &= ~0x000000f8UL;\r
+ PORT4->IOCR4 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P4_4_set_driver_strength(uint8_t strength){\r
+ PORT4->PDR0 &= ~0x00070000UL;\r
+ PORT4->PDR0 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P4_4_set_hwsel(uint32_t config){\r
+ PORT4->HWSEL &= ~0x00000300UL;\r
+ PORT4->HWSEL |= config << 8;\r
+}\r
+\r
+__STATIC_INLINE void P4_4_set(void){\r
+ PORT4->OMR = 0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_4_reset(void){\r
+ PORT4->OMR = 0x00100000UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_4_toggle(void){\r
+ PORT4->OMR = 0x00100010UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P4_4_read(void){\r
+ return(PORT4->IN & 0x00000010UL);\r
+}\r
+\r
+__STATIC_INLINE void P4_5_set_mode(uint8_t mode){\r
+ PORT4->IOCR4 &= ~0x0000f800UL;\r
+ PORT4->IOCR4 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P4_5_set_driver_strength(uint8_t strength){\r
+ PORT4->PDR0 &= ~0x00700000UL;\r
+ PORT4->PDR0 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P4_5_set_hwsel(uint32_t config){\r
+ PORT4->HWSEL &= ~0x00000c00UL;\r
+ PORT4->HWSEL |= config << 10;\r
+}\r
+\r
+__STATIC_INLINE void P4_5_set(void){\r
+ PORT4->OMR = 0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_5_reset(void){\r
+ PORT4->OMR = 0x00200000UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_5_toggle(void){\r
+ PORT4->OMR = 0x00200020UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P4_5_read(void){\r
+ return(PORT4->IN & 0x00000020UL);\r
+}\r
+\r
+__STATIC_INLINE void P4_6_set_mode(uint8_t mode){\r
+ PORT4->IOCR4 &= ~0x00f80000UL;\r
+ PORT4->IOCR4 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P4_6_set_driver_strength(uint8_t strength){\r
+ PORT4->PDR0 &= ~0x07000000UL;\r
+ PORT4->PDR0 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P4_6_set_hwsel(uint32_t config){\r
+ PORT4->HWSEL &= ~0x00003000UL;\r
+ PORT4->HWSEL |= config << 12;\r
+}\r
+\r
+__STATIC_INLINE void P4_6_set(void){\r
+ PORT4->OMR = 0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_6_reset(void){\r
+ PORT4->OMR = 0x00400000UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_6_toggle(void){\r
+ PORT4->OMR = 0x00400040UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P4_6_read(void){\r
+ return(PORT4->IN & 0x00000040UL);\r
+}\r
+\r
+__STATIC_INLINE void P4_7_set_mode(uint8_t mode){\r
+ PORT4->IOCR4 &= ~0xf8000000UL;\r
+ PORT4->IOCR4 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P4_7_set_driver_strength(uint8_t strength){\r
+ PORT4->PDR0 &= ~0x70000000UL;\r
+ PORT4->PDR0 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P4_7_set_hwsel(uint32_t config){\r
+ PORT4->HWSEL &= ~0x0000c000UL;\r
+ PORT4->HWSEL |= config << 14;\r
+}\r
+\r
+__STATIC_INLINE void P4_7_set(void){\r
+ PORT4->OMR = 0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_7_reset(void){\r
+ PORT4->OMR = 0x00800000UL;\r
+}\r
+\r
+__STATIC_INLINE void P4_7_toggle(void){\r
+ PORT4->OMR = 0x00800080UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P4_7_read(void){\r
+ return(PORT4->IN & 0x00000080UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_0_set_mode(uint8_t mode){\r
+ PORT5->IOCR0 &= ~0x000000f8UL;\r
+ PORT5->IOCR0 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P5_0_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR0 &= ~0x00000007UL;\r
+ PORT5->PDR0 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P5_0_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x00000003UL;\r
+ PORT5->HWSEL |= config << 0;\r
+}\r
+\r
+__STATIC_INLINE void P5_0_set(void){\r
+ PORT5->OMR = 0x00000001UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_0_reset(void){\r
+ PORT5->OMR = 0x00010000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_0_toggle(void){\r
+ PORT5->OMR = 0x00010001UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_0_read(void){\r
+ return(PORT5->IN & 0x00000001UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_1_set_mode(uint8_t mode){\r
+ PORT5->IOCR0 &= ~0x0000f800UL;\r
+ PORT5->IOCR0 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P5_1_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR0 &= ~0x00000070UL;\r
+ PORT5->PDR0 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P5_1_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x0000000cUL;\r
+ PORT5->HWSEL |= config << 2;\r
+}\r
+\r
+__STATIC_INLINE void P5_1_set(void){\r
+ PORT5->OMR = 0x00000002UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_1_reset(void){\r
+ PORT5->OMR = 0x00020000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_1_toggle(void){\r
+ PORT5->OMR = 0x00020002UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_1_read(void){\r
+ return(PORT5->IN & 0x00000002UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_2_set_mode(uint8_t mode){\r
+ PORT5->IOCR0 &= ~0x00f80000UL;\r
+ PORT5->IOCR0 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P5_2_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR0 &= ~0x00000700UL;\r
+ PORT5->PDR0 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P5_2_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x00000030UL;\r
+ PORT5->HWSEL |= config << 4;\r
+}\r
+\r
+__STATIC_INLINE void P5_2_set(void){\r
+ PORT5->OMR = 0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_2_reset(void){\r
+ PORT5->OMR = 0x00040000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_2_toggle(void){\r
+ PORT5->OMR = 0x00040004UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_2_read(void){\r
+ return(PORT5->IN & 0x00000004UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_3_set_mode(uint8_t mode){\r
+ PORT5->IOCR0 &= ~0xf8000000UL;\r
+ PORT5->IOCR0 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P5_3_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR0 &= ~0x00007000UL;\r
+ PORT5->PDR0 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P5_3_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x000000c0UL;\r
+ PORT5->HWSEL |= config << 6;\r
+}\r
+\r
+__STATIC_INLINE void P5_3_set(void){\r
+ PORT5->OMR = 0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_3_reset(void){\r
+ PORT5->OMR = 0x00080000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_3_toggle(void){\r
+ PORT5->OMR = 0x00080008UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_3_read(void){\r
+ return(PORT5->IN & 0x00000008UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_4_set_mode(uint8_t mode){\r
+ PORT5->IOCR4 &= ~0x000000f8UL;\r
+ PORT5->IOCR4 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P5_4_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR0 &= ~0x00070000UL;\r
+ PORT5->PDR0 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P5_4_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x00000300UL;\r
+ PORT5->HWSEL |= config << 8;\r
+}\r
+\r
+__STATIC_INLINE void P5_4_set(void){\r
+ PORT5->OMR = 0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_4_reset(void){\r
+ PORT5->OMR = 0x00100000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_4_toggle(void){\r
+ PORT5->OMR = 0x00100010UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_4_read(void){\r
+ return(PORT5->IN & 0x00000010UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_5_set_mode(uint8_t mode){\r
+ PORT5->IOCR4 &= ~0x0000f800UL;\r
+ PORT5->IOCR4 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P5_5_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR0 &= ~0x00700000UL;\r
+ PORT5->PDR0 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P5_5_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x00000c00UL;\r
+ PORT5->HWSEL |= config << 10;\r
+}\r
+\r
+__STATIC_INLINE void P5_5_set(void){\r
+ PORT5->OMR = 0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_5_reset(void){\r
+ PORT5->OMR = 0x00200000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_5_toggle(void){\r
+ PORT5->OMR = 0x00200020UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_5_read(void){\r
+ return(PORT5->IN & 0x00000020UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_6_set_mode(uint8_t mode){\r
+ PORT5->IOCR4 &= ~0x00f80000UL;\r
+ PORT5->IOCR4 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P5_6_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR0 &= ~0x07000000UL;\r
+ PORT5->PDR0 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P5_6_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x00003000UL;\r
+ PORT5->HWSEL |= config << 12;\r
+}\r
+\r
+__STATIC_INLINE void P5_6_set(void){\r
+ PORT5->OMR = 0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_6_reset(void){\r
+ PORT5->OMR = 0x00400000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_6_toggle(void){\r
+ PORT5->OMR = 0x00400040UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_6_read(void){\r
+ return(PORT5->IN & 0x00000040UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_7_set_mode(uint8_t mode){\r
+ PORT5->IOCR4 &= ~0xf8000000UL;\r
+ PORT5->IOCR4 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P5_7_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR0 &= ~0x70000000UL;\r
+ PORT5->PDR0 |= strength << 28;\r
+}\r
+\r
+__STATIC_INLINE void P5_7_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x0000c000UL;\r
+ PORT5->HWSEL |= config << 14;\r
+}\r
+\r
+__STATIC_INLINE void P5_7_set(void){\r
+ PORT5->OMR = 0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_7_reset(void){\r
+ PORT5->OMR = 0x00800000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_7_toggle(void){\r
+ PORT5->OMR = 0x00800080UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_7_read(void){\r
+ return(PORT5->IN & 0x00000080UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_8_set_mode(uint8_t mode){\r
+ PORT5->IOCR8 &= ~0x000000f8UL;\r
+ PORT5->IOCR8 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P5_8_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR1 &= ~0x00000007UL;\r
+ PORT5->PDR1 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P5_8_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x00030000UL;\r
+ PORT5->HWSEL |= config << 16;\r
+}\r
+\r
+__STATIC_INLINE void P5_8_set(void){\r
+ PORT5->OMR = 0x00000100UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_8_reset(void){\r
+ PORT5->OMR = 0x01000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_8_toggle(void){\r
+ PORT5->OMR = 0x01000100UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_8_read(void){\r
+ return(PORT5->IN & 0x00000100UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_9_set_mode(uint8_t mode){\r
+ PORT5->IOCR8 &= ~0x0000f800UL;\r
+ PORT5->IOCR8 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P5_9_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR1 &= ~0x00000070UL;\r
+ PORT5->PDR1 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P5_9_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x000c0000UL;\r
+ PORT5->HWSEL |= config << 18;\r
+}\r
+\r
+__STATIC_INLINE void P5_9_set(void){\r
+ PORT5->OMR = 0x00000200UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_9_reset(void){\r
+ PORT5->OMR = 0x02000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_9_toggle(void){\r
+ PORT5->OMR = 0x02000200UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_9_read(void){\r
+ return(PORT5->IN & 0x00000200UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_10_set_mode(uint8_t mode){\r
+ PORT5->IOCR8 &= ~0x00f80000UL;\r
+ PORT5->IOCR8 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P5_10_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR1 &= ~0x00000700UL;\r
+ PORT5->PDR1 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P5_10_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x00300000UL;\r
+ PORT5->HWSEL |= config << 20;\r
+}\r
+\r
+__STATIC_INLINE void P5_10_set(void){\r
+ PORT5->OMR = 0x00000400UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_10_reset(void){\r
+ PORT5->OMR = 0x04000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_10_toggle(void){\r
+ PORT5->OMR = 0x04000400UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_10_read(void){\r
+ return(PORT5->IN & 0x00000400UL);\r
+}\r
+\r
+__STATIC_INLINE void P5_11_set_mode(uint8_t mode){\r
+ PORT5->IOCR8 &= ~0xf8000000UL;\r
+ PORT5->IOCR8 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P5_11_set_driver_strength(uint8_t strength){\r
+ PORT5->PDR1 &= ~0x00007000UL;\r
+ PORT5->PDR1 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P5_11_set_hwsel(uint32_t config){\r
+ PORT5->HWSEL &= ~0x00c00000UL;\r
+ PORT5->HWSEL |= config << 22;\r
+}\r
+\r
+__STATIC_INLINE void P5_11_set(void){\r
+ PORT5->OMR = 0x00000800UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_11_reset(void){\r
+ PORT5->OMR = 0x08000000UL;\r
+}\r
+\r
+__STATIC_INLINE void P5_11_toggle(void){\r
+ PORT5->OMR = 0x08000800UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P5_11_read(void){\r
+ return(PORT5->IN & 0x00000800UL);\r
+}\r
+\r
+__STATIC_INLINE void P6_0_set_mode(uint8_t mode){\r
+ PORT6->IOCR0 &= ~0x000000f8UL;\r
+ PORT6->IOCR0 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P6_0_set_driver_strength(uint8_t strength){\r
+ PORT6->PDR0 &= ~0x00000007UL;\r
+ PORT6->PDR0 |= strength << 0;\r
+}\r
+\r
+__STATIC_INLINE void P6_0_set_hwsel(uint32_t config){\r
+ PORT6->HWSEL &= ~0x00000003UL;\r
+ PORT6->HWSEL |= config << 0;\r
+}\r
+\r
+__STATIC_INLINE void P6_0_set(void){\r
+ PORT6->OMR = 0x00000001UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_0_reset(void){\r
+ PORT6->OMR = 0x00010000UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_0_toggle(void){\r
+ PORT6->OMR = 0x00010001UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P6_0_read(void){\r
+ return(PORT6->IN & 0x00000001UL);\r
+}\r
+\r
+__STATIC_INLINE void P6_1_set_mode(uint8_t mode){\r
+ PORT6->IOCR0 &= ~0x0000f800UL;\r
+ PORT6->IOCR0 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P6_1_set_driver_strength(uint8_t strength){\r
+ PORT6->PDR0 &= ~0x00000070UL;\r
+ PORT6->PDR0 |= strength << 4;\r
+}\r
+\r
+__STATIC_INLINE void P6_1_set_hwsel(uint32_t config){\r
+ PORT6->HWSEL &= ~0x0000000cUL;\r
+ PORT6->HWSEL |= config << 2;\r
+}\r
+\r
+__STATIC_INLINE void P6_1_set(void){\r
+ PORT6->OMR = 0x00000002UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_1_reset(void){\r
+ PORT6->OMR = 0x00020000UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_1_toggle(void){\r
+ PORT6->OMR = 0x00020002UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P6_1_read(void){\r
+ return(PORT6->IN & 0x00000002UL);\r
+}\r
+\r
+__STATIC_INLINE void P6_2_set_mode(uint8_t mode){\r
+ PORT6->IOCR0 &= ~0x00f80000UL;\r
+ PORT6->IOCR0 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P6_2_set_driver_strength(uint8_t strength){\r
+ PORT6->PDR0 &= ~0x00000700UL;\r
+ PORT6->PDR0 |= strength << 8;\r
+}\r
+\r
+__STATIC_INLINE void P6_2_set_hwsel(uint32_t config){\r
+ PORT6->HWSEL &= ~0x00000030UL;\r
+ PORT6->HWSEL |= config << 4;\r
+}\r
+\r
+__STATIC_INLINE void P6_2_set(void){\r
+ PORT6->OMR = 0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_2_reset(void){\r
+ PORT6->OMR = 0x00040000UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_2_toggle(void){\r
+ PORT6->OMR = 0x00040004UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P6_2_read(void){\r
+ return(PORT6->IN & 0x00000004UL);\r
+}\r
+\r
+__STATIC_INLINE void P6_3_set_mode(uint8_t mode){\r
+ PORT6->IOCR0 &= ~0xf8000000UL;\r
+ PORT6->IOCR0 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P6_3_set_driver_strength(uint8_t strength){\r
+ PORT6->PDR0 &= ~0x00007000UL;\r
+ PORT6->PDR0 |= strength << 12;\r
+}\r
+\r
+__STATIC_INLINE void P6_3_set_hwsel(uint32_t config){\r
+ PORT6->HWSEL &= ~0x000000c0UL;\r
+ PORT6->HWSEL |= config << 6;\r
+}\r
+\r
+__STATIC_INLINE void P6_3_set(void){\r
+ PORT6->OMR = 0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_3_reset(void){\r
+ PORT6->OMR = 0x00080000UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_3_toggle(void){\r
+ PORT6->OMR = 0x00080008UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P6_3_read(void){\r
+ return(PORT6->IN & 0x00000008UL);\r
+}\r
+\r
+__STATIC_INLINE void P6_4_set_mode(uint8_t mode){\r
+ PORT6->IOCR4 &= ~0x000000f8UL;\r
+ PORT6->IOCR4 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P6_4_set_driver_strength(uint8_t strength){\r
+ PORT6->PDR0 &= ~0x00070000UL;\r
+ PORT6->PDR0 |= strength << 16;\r
+}\r
+\r
+__STATIC_INLINE void P6_4_set_hwsel(uint32_t config){\r
+ PORT6->HWSEL &= ~0x00000300UL;\r
+ PORT6->HWSEL |= config << 8;\r
+}\r
+\r
+__STATIC_INLINE void P6_4_set(void){\r
+ PORT6->OMR = 0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_4_reset(void){\r
+ PORT6->OMR = 0x00100000UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_4_toggle(void){\r
+ PORT6->OMR = 0x00100010UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P6_4_read(void){\r
+ return(PORT6->IN & 0x00000010UL);\r
+}\r
+\r
+__STATIC_INLINE void P6_5_set_mode(uint8_t mode){\r
+ PORT6->IOCR4 &= ~0x0000f800UL;\r
+ PORT6->IOCR4 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P6_5_set_driver_strength(uint8_t strength){\r
+ PORT6->PDR0 &= ~0x00700000UL;\r
+ PORT6->PDR0 |= strength << 20;\r
+}\r
+\r
+__STATIC_INLINE void P6_5_set_hwsel(uint32_t config){\r
+ PORT6->HWSEL &= ~0x00000c00UL;\r
+ PORT6->HWSEL |= config << 10;\r
+}\r
+\r
+__STATIC_INLINE void P6_5_set(void){\r
+ PORT6->OMR = 0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_5_reset(void){\r
+ PORT6->OMR = 0x00200000UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_5_toggle(void){\r
+ PORT6->OMR = 0x00200020UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P6_5_read(void){\r
+ return(PORT6->IN & 0x00000020UL);\r
+}\r
+\r
+__STATIC_INLINE void P6_6_set_mode(uint8_t mode){\r
+ PORT6->IOCR4 &= ~0x00f80000UL;\r
+ PORT6->IOCR4 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P6_6_set_driver_strength(uint8_t strength){\r
+ PORT6->PDR0 &= ~0x07000000UL;\r
+ PORT6->PDR0 |= strength << 24;\r
+}\r
+\r
+__STATIC_INLINE void P6_6_set_hwsel(uint32_t config){\r
+ PORT6->HWSEL &= ~0x00003000UL;\r
+ PORT6->HWSEL |= config << 12;\r
+}\r
+\r
+__STATIC_INLINE void P6_6_set(void){\r
+ PORT6->OMR = 0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_6_reset(void){\r
+ PORT6->OMR = 0x00400000UL;\r
+}\r
+\r
+__STATIC_INLINE void P6_6_toggle(void){\r
+ PORT6->OMR = 0x00400040UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P6_6_read(void){\r
+ return(PORT6->IN & 0x00000040UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_0_set_mode(uint8_t mode){\r
+ PORT14->IOCR0 &= ~0x000000f8UL;\r
+ PORT14->IOCR0 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P14_0_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000001UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_0_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000001UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_0_read(void){\r
+ return(PORT14->IN & 0x00000001UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_1_set_mode(uint8_t mode){\r
+ PORT14->IOCR0 &= ~0x0000f800UL;\r
+ PORT14->IOCR0 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P14_1_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000002UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_1_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000002UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_1_read(void){\r
+ return(PORT14->IN & 0x00000002UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_2_set_mode(uint8_t mode){\r
+ PORT14->IOCR0 &= ~0x00f80000UL;\r
+ PORT14->IOCR0 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P14_2_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_2_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_2_read(void){\r
+ return(PORT14->IN & 0x00000004UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_3_set_mode(uint8_t mode){\r
+ PORT14->IOCR0 &= ~0xf8000000UL;\r
+ PORT14->IOCR0 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P14_3_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_3_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_3_read(void){\r
+ return(PORT14->IN & 0x00000008UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_4_set_mode(uint8_t mode){\r
+ PORT14->IOCR4 &= ~0x000000f8UL;\r
+ PORT14->IOCR4 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P14_4_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_4_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_4_read(void){\r
+ return(PORT14->IN & 0x00000010UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_5_set_mode(uint8_t mode){\r
+ PORT14->IOCR4 &= ~0x0000f800UL;\r
+ PORT14->IOCR4 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P14_5_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_5_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_5_read(void){\r
+ return(PORT14->IN & 0x00000020UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_6_set_mode(uint8_t mode){\r
+ PORT14->IOCR4 &= ~0x00f80000UL;\r
+ PORT14->IOCR4 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P14_6_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_6_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_6_read(void){\r
+ return(PORT14->IN & 0x00000040UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_7_set_mode(uint8_t mode){\r
+ PORT14->IOCR4 &= ~0xf8000000UL;\r
+ PORT14->IOCR4 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P14_7_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_7_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_7_read(void){\r
+ return(PORT14->IN & 0x00000080UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_8_set_mode(uint8_t mode){\r
+ PORT14->IOCR8 &= ~0x000000f8UL;\r
+ PORT14->IOCR8 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P14_8_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000100UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_8_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000100UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_8_read(void){\r
+ return(PORT14->IN & 0x00000100UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_9_set_mode(uint8_t mode){\r
+ PORT14->IOCR8 &= ~0x0000f800UL;\r
+ PORT14->IOCR8 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P14_9_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00000200UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_9_disable_digital(void){\r
+ PORT14->PDISC |= 0x00000200UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_9_read(void){\r
+ return(PORT14->IN & 0x00000200UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_12_set_mode(uint8_t mode){\r
+ PORT14->IOCR12 &= ~0x000000f8UL;\r
+ PORT14->IOCR12 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P14_12_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00001000UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_12_disable_digital(void){\r
+ PORT14->PDISC |= 0x00001000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_12_read(void){\r
+ return(PORT14->IN & 0x00001000UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_13_set_mode(uint8_t mode){\r
+ PORT14->IOCR12 &= ~0x0000f800UL;\r
+ PORT14->IOCR12 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P14_13_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00002000UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_13_disable_digital(void){\r
+ PORT14->PDISC |= 0x00002000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_13_read(void){\r
+ return(PORT14->IN & 0x00002000UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_14_set_mode(uint8_t mode){\r
+ PORT14->IOCR12 &= ~0x00f80000UL;\r
+ PORT14->IOCR12 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P14_14_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00004000UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_14_disable_digital(void){\r
+ PORT14->PDISC |= 0x00004000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_14_read(void){\r
+ return(PORT14->IN & 0x00004000UL);\r
+}\r
+\r
+__STATIC_INLINE void P14_15_set_mode(uint8_t mode){\r
+ PORT14->IOCR12 &= ~0xf8000000UL;\r
+ PORT14->IOCR12 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P14_15_enable_digital(void){\r
+ PORT14->PDISC &= ~0x00008000UL;\r
+}\r
+\r
+__STATIC_INLINE void P14_15_disable_digital(void){\r
+ PORT14->PDISC |= 0x00008000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P14_15_read(void){\r
+ return(PORT14->IN & 0x00008000UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_2_set_mode(uint8_t mode){\r
+ PORT15->IOCR0 &= ~0x00f80000UL;\r
+ PORT15->IOCR0 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P15_2_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_2_disable_digital(void){\r
+ PORT15->PDISC |= 0x00000004UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_2_read(void){\r
+ return(PORT15->IN & 0x00000004UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_3_set_mode(uint8_t mode){\r
+ PORT15->IOCR0 &= ~0xf8000000UL;\r
+ PORT15->IOCR0 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P15_3_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_3_disable_digital(void){\r
+ PORT15->PDISC |= 0x00000008UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_3_read(void){\r
+ return(PORT15->IN & 0x00000008UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_4_set_mode(uint8_t mode){\r
+ PORT15->IOCR4 &= ~0x000000f8UL;\r
+ PORT15->IOCR4 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P15_4_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_4_disable_digital(void){\r
+ PORT15->PDISC |= 0x00000010UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_4_read(void){\r
+ return(PORT15->IN & 0x00000010UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_5_set_mode(uint8_t mode){\r
+ PORT15->IOCR4 &= ~0x0000f800UL;\r
+ PORT15->IOCR4 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P15_5_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_5_disable_digital(void){\r
+ PORT15->PDISC |= 0x00000020UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_5_read(void){\r
+ return(PORT15->IN & 0x00000020UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_6_set_mode(uint8_t mode){\r
+ PORT15->IOCR4 &= ~0x00f80000UL;\r
+ PORT15->IOCR4 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P15_6_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_6_disable_digital(void){\r
+ PORT15->PDISC |= 0x00000040UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_6_read(void){\r
+ return(PORT15->IN & 0x00000040UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_7_set_mode(uint8_t mode){\r
+ PORT15->IOCR4 &= ~0xf8000000UL;\r
+ PORT15->IOCR4 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P15_7_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_7_disable_digital(void){\r
+ PORT15->PDISC |= 0x00000080UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_7_read(void){\r
+ return(PORT15->IN & 0x00000080UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_8_set_mode(uint8_t mode){\r
+ PORT15->IOCR8 &= ~0x000000f8UL;\r
+ PORT15->IOCR8 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P15_8_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00000100UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_8_disable_digital(void){\r
+ PORT15->PDISC |= 0x00000100UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_8_read(void){\r
+ return(PORT15->IN & 0x00000100UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_9_set_mode(uint8_t mode){\r
+ PORT15->IOCR8 &= ~0x0000f800UL;\r
+ PORT15->IOCR8 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P15_9_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00000200UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_9_disable_digital(void){\r
+ PORT15->PDISC |= 0x00000200UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_9_read(void){\r
+ return(PORT15->IN & 0x00000200UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_12_set_mode(uint8_t mode){\r
+ PORT15->IOCR12 &= ~0x000000f8UL;\r
+ PORT15->IOCR12 |= mode << 0;\r
+}\r
+\r
+__STATIC_INLINE void P15_12_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00001000UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_12_disable_digital(void){\r
+ PORT15->PDISC |= 0x00001000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_12_read(void){\r
+ return(PORT15->IN & 0x00001000UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_13_set_mode(uint8_t mode){\r
+ PORT15->IOCR12 &= ~0x0000f800UL;\r
+ PORT15->IOCR12 |= mode << 8;\r
+}\r
+\r
+__STATIC_INLINE void P15_13_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00002000UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_13_disable_digital(void){\r
+ PORT15->PDISC |= 0x00002000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_13_read(void){\r
+ return(PORT15->IN & 0x00002000UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_14_set_mode(uint8_t mode){\r
+ PORT15->IOCR12 &= ~0x00f80000UL;\r
+ PORT15->IOCR12 |= mode << 16;\r
+}\r
+\r
+__STATIC_INLINE void P15_14_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00004000UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_14_disable_digital(void){\r
+ PORT15->PDISC |= 0x00004000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_14_read(void){\r
+ return(PORT15->IN & 0x00004000UL);\r
+}\r
+\r
+__STATIC_INLINE void P15_15_set_mode(uint8_t mode){\r
+ PORT15->IOCR12 &= ~0xf8000000UL;\r
+ PORT15->IOCR12 |= mode << 24;\r
+}\r
+\r
+__STATIC_INLINE void P15_15_enable_digital(void){\r
+ PORT15->PDISC &= ~0x00008000UL;\r
+}\r
+\r
+__STATIC_INLINE void P15_15_disable_digital(void){\r
+ PORT15->PDISC |= 0x00008000UL;\r
+}\r
+\r
+__STATIC_INLINE uint32_t P15_15_read(void){\r
+ return(PORT15->IN & 0x00008000UL);\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* Generated Linker Script file */\r
+/*\r
+ * Template Version 1.0 dated 11 Oct 2012\r
+ */\r
+\r
+OUTPUT_FORMAT("elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+ENTRY(__Xmc4500_reset_cortex_m)\r
+GROUP(-lxmclibcstubs)\r
+\r
+MEMORY\r
+{\r
+ FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x100000\r
+ FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x100000\r
+ PSRAM_1(!RX) : ORIGIN = 0x10000000, LENGTH = 0x10000\r
+ DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x10000\r
+ DSRAM_2_comm(!RX) : ORIGIN = 0x30000000, LENGTH = 0x8000\r
+}\r
+\r
+stack_size = 2048;\r
+\r
+SECTIONS\r
+{\r
+ /* TEXT section */\r
+\r
+ .text : AT(ORIGIN(FLASH_1_uncached))\r
+ {\r
+ sText = .;\r
+ *(.Xmc4500.reset);\r
+ *(.Xmc4500.postreset);\r
+ *(.XmcStartup);\r
+ *(.text .text.* .gnu.linkonce.t.*);\r
+\r
+ /* ARM <->THUMB interworking */\r
+ *(.glue*)\r
+ *(.v4*)\r
+ *(.vfp11_veneer)\r
+\r
+ /* C++ Support */\r
+ KEEP(*(.init))\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+ KEEP(*(.fini))\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+\r
+ /* Exception handling support */\r
+ __extab_start = .;\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ . = ALIGN(4);\r
+ __extab_end = ABSOLUTE(.);\r
+ } > FLASH_1_cached\r
+\r
+ /* Exception handling, exidx needs a dedicated section */\r
+ .ARM.exidx ABSOLUTE(__extab_end): AT(__extab_end | 0x04000000)\r
+ {\r
+ __exidx_start = .;\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ . = ALIGN(4);\r
+ __exidx_end = ABSOLUTE(.);\r
+ } > FLASH_1_cached\r
+\r
+ /* CONST data section */\r
+ .rodata ABSOLUTE(__exidx_end): AT(__exidx_end | 0x04000000)\r
+ {\r
+ *(.rodata .rodata.*)\r
+ *(.gnu.linkonce.r*)\r
+ } > FLASH_1_cached\r
+\r
+ . = ALIGN(16);\r
+\r
+ /* End of RO-DATA and start of LOAD region for DATA */\r
+ eROData = . | 0x04000000;\r
+\r
+ /* DSRAM layout (Lowest to highest)*/\r
+ /* Fully Descending Stack <-> BSS <-> DATA <-> HEAP */\r
+ /* Dummy section for stack */\r
+ Stack (NOLOAD) : \r
+ {\r
+ . = . + stack_size;\r
+ __Xmc4500_stack = .;\r
+ } > DSRAM_1_system\r
+\r
+ Communication_Buffers :\r
+ {\r
+ *DMA_Descriptors.o (COMMON);\r
+ } > DSRAM_2_comm\r
+\r
+ /* BSS section */\r
+ .bss : \r
+ {\r
+ __Xmc4500_sBSS = .;\r
+ * (.bss);\r
+ * (.bss*);\r
+ * (EXCLUDE_FILE(*DMA_Descriptors.o) COMMON);\r
+ *(.gnu.linkonce.b*)\r
+ __Xmc4500_eBSS = ALIGN(4);\r
+ } > DSRAM_1_system\r
+ /* Yes, the size must be kept outside */\r
+ __Xmc4500_BSS_Size = __Xmc4500_eBSS - __Xmc4500_sBSS;\r
+\r
+ /* Standard DATA and user defined DATA/BSS/CONST sections */\r
+ .data ABSOLUTE(ALIGN(16)): AT(eROData)\r
+ {\r
+ __Xmc4500_sData = .;\r
+ * (.data);\r
+ * (.data*);\r
+ *(*.data);\r
+ *(.gnu.linkonce.d*)\r
+ __Xmc4500_eData = ALIGN(4);\r
+ } > DSRAM_1_system\r
+ /* Yes, the size must be kept outside */\r
+ __Xmc4500_Data_Size = __Xmc4500_eData - __Xmc4500_sData;\r
+\r
+ /* Heap - Bank1*/\r
+ __Xmc4500_heap_start = ALIGN(8);\r
+ __Xmc4500_heap_end = ORIGIN(DSRAM_1_system) + LENGTH (DSRAM_1_system);\r
+ Heap_Bank1_Start = __Xmc4500_heap_start;\r
+ Heap_Bank1_Size = __Xmc4500_heap_end - __Xmc4500_heap_start;\r
+ Heap_Bank1_End = ABSOLUTE(__Xmc4500_heap_end);\r
+\r
+ /* Heap - Bank2 */\r
+ DSRAM2_Heap :\r
+ {\r
+ /* To host DATA in DSRAM2 above heap, please be sure to augment\r
+ * program loader code in the startup file */\r
+ Heap_Bank2_Start = .;\r
+ } > DSRAM_2_comm\r
+ Heap_Bank2_Size = LENGTH(DSRAM_2_comm) - (Heap_Bank2_Start - ORIGIN(DSRAM_2_comm));\r
+\r
+ /* Heap - Bank3 */\r
+ PSRAM_Heap :\r
+ {\r
+ /* To host DATA in PSRAM above heap, please be sure to augment\r
+ * program loader code in the startup file */\r
+ Heap_Bank3_Start = .;\r
+ } > PSRAM_1\r
+ Heap_Bank3_Size = LENGTH(PSRAM_1) - (Heap_Bank3_Start - ORIGIN(PSRAM_1));\r
+\r
+ /DISCARD/ :\r
+ {\r
+ *(.comment)\r
+ }\r
+\r
+ .stab 0 (NOLOAD) : { *(.stab) }\r
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }\r
+\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }\r
+\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+\r
+ /* DWARF 2.1 */\r
+ .debug_ranges 0 : { *(.debug_ranges) }\r
+\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+\r
+ /* Build attributes */\r
+ .build_attributes 0 : { *(.ARM.attributes) }\r
+}\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">\r
+<booleanAttribute key="com.tasking.debug.cdt.core.ATTR_RUN_IN_SEPARATE_PROCESS" value="true"/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>\r
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (SWD)"/>\r
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>\r
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>\r
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>\r
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>\r
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>\r
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="Infineon Hexagon Application Kit XMC4500 Series"/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>\r
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>\r
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>\r
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fARMv7M.sre"/>\r
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>\r
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>\r
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>\r
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList/>"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>\r
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\RTOSDemo.elf"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo"/>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">\r
+<listEntry value="/RTOSDemo"/>\r
+</listAttribute>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">\r
+<listEntry value="4"/>\r
+</listAttribute>\r
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>\r
+</launchConfiguration>\r
--- /dev/null
+/*****************************************************************************/
+/* Startup_XMC4500.s: Startup file for XMC4500 device series */
+/*****************************************************************************/
+
+/* ********************* Version History *********************************** */
+/* ***************************************************************************
+V1.0 , July 2011, First version for XIP profile
+V1.1 , Oct 2011, Program loading code included (GH: b to main changed)
+V1.2 , Nov, 01, 2011 GH :Removed second definition of section .Xmc4500.reset
+ at line 186.
+V1.3 , Nov, 16, 2011 GH :Removed PMU0_1_IRQHandler and respective weak function
+ declaration.
+V1.4 , Dec, 16, 2011 PKB:Jump to __Xmc4500_start_c reinstated for RTOS integration
+V1.5 , Jan, 10, 2012 PKB:Migrated to GCC from ARM
+V1.6 , Jan, 16, 2012 PKB:Branch prediction turned off, Parity errors cleared.
+V1.7 , Apr, 17, 2012 PKB:Added decision function for PLL initialization
+V1.8 , Apr, 20, 2012 PKB:Handshake with DAVE code engine added
+V1.9 , Jun, 14, 2012 PKB:Removed the handshake protocol towards simplification
+V1.10, Aug, 13, 2012 PKB:Flash Wait states handling
+V1.11, Oct, 11, 2012 PKB:C++ support. Call to global constructors
+V1.12, Jan, 23, 2013 PKB:XMC4 Prefetch bug workaround
+**************************************************************************** */
+/**
+* @file Startup_XMC4500.s
+* XMC4000 Device Series
+* @version V1.12
+* @date Jan 2013
+*
+Copyright (C) 2013 Infineon Technologies AG. All rights reserved.
+*
+*
+* @par
+* Infineon Technologies AG (Infineon) is supplying this software for use with
+* Infineon's microcontrollers. This file can be freely distributed
+* within development tools that are supporting such microcontrollers.
+*
+* @par
+* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+*
+******************************************************************************/
+#include <uc_id.inc>
+
+/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
+/*
+ * STEP_AB and below have the prefetch bug. A veneer defined below will first
+ * be executed which in turn branches to the final exception handler.
+ *
+ * In addition to defining the veneers, the vector table must for these buggy
+ * devices contain the veneers.
+ */
+
+/* A macro to setup a vector table entry based on STEP ID */
+.macro Entry Handler
+ #if (UC_STEP > STEP_AB)
+ .long \Handler
+ #else
+ .long \Handler\()_Veneer
+ #endif
+.endm
+
+/* A macro to ease definition of the various handlers based on STEP ID */
+#if (UC_STEP <= STEP_AB)
+ /* First define the final exception handler */
+ .macro Insert_ExceptionHandler Handler_Func
+ .weak \Handler_Func
+ .type \Handler_Func, %function
+ \Handler_Func:
+ B .
+ .size \Handler_Func, . - \Handler_Func
+
+ /* And then define a veneer that will branch to the final excp handler */
+ .weak \Handler_Func\()_Veneer
+ .type \Handler_Func\()_Veneer, %function
+ \Handler_Func\()_Veneer:
+ LDR R0, =\Handler_Func
+ PUSH {LR}
+ BLX R0
+ POP {PC}
+ .size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer
+ .endm
+#else
+ /* No prefetch bug, hence define only the final exception handler */
+ .macro Insert_ExceptionHandler Handler_Func
+ .weak \Handler_Func
+ .type \Handler_Func, %function
+ \Handler_Func:
+ B .
+ .size \Handler_Func, . - \Handler_Func
+ .endm
+#endif
+/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */
+
+/* ================== START OF VECTOR TABLE DEFINITION ====================== */
+/* Vector Table - This gets programed into VTOR register by onchip BootROM */
+ .syntax unified
+
+ .section ".Xmc4500.reset"
+ .globl __Xmc4500_interrupt_vector_cortex_m
+ .type __Xmc4500_interrupt_vector_cortex_m, %object
+
+__Xmc4500_interrupt_vector_cortex_m:
+ .long __Xmc4500_stack /* Top of Stack */
+ .long __Xmc4500_reset_cortex_m /* Reset Handler */
+
+ Entry NMI_Handler /* NMI Handler */
+ Entry HardFault_Handler /* Hard Fault Handler */
+ Entry MemManage_Handler /* MPU Fault Handler */
+ Entry BusFault_Handler /* Bus Fault Handler */
+ Entry UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ Entry DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals */
+ Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */
+ Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
+ Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
+ Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
+ Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
+ Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
+ Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
+ Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
+ Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
+ .long 0 /* Not Available */
+ .long 0 /* Not Available */
+ .long 0 /* Not Available */
+ Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
+ .long 0 /* Not Available */
+ Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
+ Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
+ Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
+ Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
+ Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
+ Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
+ Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
+ Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
+ Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
+ Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
+ Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
+ Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
+ Entry VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */
+ Entry VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */
+ Entry VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */
+ Entry VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */
+ Entry VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */
+ Entry VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */
+ Entry VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */
+ Entry VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */
+ Entry DSD0_0_IRQHandler /* Handler name for SR DSD0_0 */
+ Entry DSD0_1_IRQHandler /* Handler name for SR DSD0_1 */
+ Entry DSD0_2_IRQHandler /* Handler name for SR DSD0_2 */
+ Entry DSD0_3_IRQHandler /* Handler name for SR DSD0_3 */
+ Entry DSD0_4_IRQHandler /* Handler name for SR DSD0_4 */
+ Entry DSD0_5_IRQHandler /* Handler name for SR DSD0_5 */
+ Entry DSD0_6_IRQHandler /* Handler name for SR DSD0_6 */
+ Entry DSD0_7_IRQHandler /* Handler name for SR DSD0_7 */
+ Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
+ Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_0 */
+ Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
+ Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
+ Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
+ Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
+ Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
+ Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
+ Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
+ Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
+ Entry CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */
+ Entry CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */
+ Entry CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */
+ Entry CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */
+ Entry CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */
+ Entry CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */
+ Entry CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */
+ Entry CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */
+ Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
+ Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
+ Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
+ Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
+ Entry CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */
+ Entry CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */
+ Entry CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */
+ Entry CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */
+ Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
+ Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
+ Entry POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */
+ Entry POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */
+ .long 0 /* Not Available */
+ .long 0 /* Not Available */
+ .long 0 /* Not Available */
+ .long 0 /* Not Available */
+ Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
+ Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
+ Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
+ Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
+ Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
+ Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
+ Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
+ Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
+ Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
+ Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
+ Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
+ Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
+ Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
+ Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
+ Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
+ Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
+ Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
+ Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
+ Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
+ Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
+ Entry USIC2_0_IRQHandler /* Handler name for SR USIC2_0 */
+ Entry USIC2_1_IRQHandler /* Handler name for SR USIC2_1 */
+ Entry USIC2_2_IRQHandler /* Handler name for SR USIC2_2 */
+ Entry USIC2_3_IRQHandler /* Handler name for SR USIC2_3 */
+ Entry USIC2_4_IRQHandler /* Handler name for SR USIC2_4 */
+ Entry USIC2_5_IRQHandler /* Handler name for SR USIC2_5 */
+ Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
+ .long 0 /* Not Available */
+ Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
+ Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
+ Entry SDMMC0_0_IRQHandler /* Handler name for SR SDMMC0_0 */
+ Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */
+ Entry ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */
+ .long 0 /* Not Available */
+ Entry GPDMA1_0_IRQHandler /* Handler name for SR GPDMA1_0 */
+ .long 0 /* Not Available */
+
+ .size __Xmc4500_interrupt_vector_cortex_m, . - __Xmc4500_interrupt_vector_cortex_m
+/* ================== END OF VECTOR TABLE DEFINITION ======================= */
+
+/* ================== START OF VECTOR ROUTINES ============================= */
+ .thumb
+/* ======================================================================== */
+/* Reset Handler */
+
+ .thumb_func
+ .globl __Xmc4500_reset_cortex_m
+ .type __Xmc4500_reset_cortex_m, %function
+__Xmc4500_reset_cortex_m:
+ .fnstart
+
+ /* C routines are likely to be called. Setup the stack now */
+ /* This is already setup by BootROM,hence this step is optional */
+ LDR SP,=__Xmc4500_stack
+
+ /* Clock tree, External memory setup etc may be done here */
+ LDR R0, =SystemInit
+ BLX R0
+
+/*
+ SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is
+ weakly defined here though for a potential override.
+*/
+ LDR R0, =SystemInit_DAVE3
+ BLX R0
+
+ B __Xmc4500_Program_Loader
+
+ .pool
+ .cantunwind
+ .fnend
+ .size __Xmc4500_reset_cortex_m,.-__Xmc4500_reset_cortex_m
+/* ======================================================================== */
+/* __Xmc4500_reset must yield control to __Xmc4500_Program_Loader before control
+ to C land is given */
+ .section .Xmc4500.postreset,"x",%progbits
+ __Xmc4500_Program_Loader:
+ .fnstart
+ /* Memories are accessible now*/
+
+ /* DATA COPY */
+ /* R0 = Start address, R1 = Destination address, R2 = Size */
+ LDR R0, =eROData
+ LDR R1, =__Xmc4500_sData
+ LDR R2, =__Xmc4500_Data_Size
+
+ /* Is there anything to be copied? */
+ CMP R2,#0
+ BEQ SKIPCOPY
+
+ /* For bytecount less than 4, at least 1 word must be copied */
+ CMP R2,#4
+ BCS STARTCOPY
+
+ /* Byte count < 4 ; so bump it up */
+ MOV R2,#4
+
+STARTCOPY:
+ /*
+ R2 contains byte count. Change it to word count. It is ensured in the
+ linker script that the length is always word aligned.
+ */
+ LSR R2,R2,#2 /* Divide by 4 to obtain word count */
+
+ /* The proverbial loop from the schooldays */
+COPYLOOP:
+ LDR R3,[R0]
+ STR R3,[R1]
+ SUBS R2,#1
+ BEQ SKIPCOPY
+ ADD R0,#4
+ ADD R1,#4
+ B COPYLOOP
+
+SKIPCOPY:
+ /* BSS CLEAR */
+ LDR R0, =__Xmc4500_sBSS /* Start of BSS */
+ LDR R1, =__Xmc4500_BSS_Size /* BSS size in bytes */
+
+ /* Find out if there are items assigned to BSS */
+ CMP R1,#0
+ BEQ SKIPCLEAR
+
+ /* At least 1 word must be copied */
+ CMP R1,#4
+ BCS STARTCLEAR
+
+ /* Byte count < 4 ; so bump it up to a word*/
+ MOV R1,#4
+
+STARTCLEAR:
+ LSR R1,R1,#2 /* BSS size in words */
+
+ MOV R2,#0
+CLEARLOOP:
+ STR R2,[R0]
+ SUBS R1,#1
+ BEQ SKIPCLEAR
+ ADD R0,#4
+ B CLEARLOOP
+
+SKIPCLEAR:
+ /* Remap vector table */
+ /* This is already setup by BootROM,hence this step is optional */
+ LDR R0, =__Xmc4500_interrupt_vector_cortex_m
+ LDR R1, =SCB_VTOR
+ STR R0,[R1]
+
+ /* Update System Clock */
+ LDR R0,=SystemCoreClockUpdate
+ BLX R0
+
+ /* C++ : Call global constructors */
+ LDR R0,=__libc_init_array
+ BLX R0
+
+ /* Reset stack pointer before zipping off to user application, Optional */
+ LDR SP,=__Xmc4500_stack
+ MOV R0,#0
+ MOV R1,#0
+ LDR PC, =main
+ .pool
+ .cantunwind
+ .fnend
+ .size __Xmc4500_Program_Loader,.-__Xmc4500_Program_Loader
+/* ======================================================================== */
+/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
+
+
+/* Default exception Handlers - Users may override this default functionality by
+ defining handlers of the same name in their C code */
+ .thumb
+ .text
+
+ Insert_ExceptionHandler NMI_Handler
+/* ======================================================================== */
+ Insert_ExceptionHandler HardFault_Handler
+/* ======================================================================== */
+ Insert_ExceptionHandler MemManage_Handler
+/* ======================================================================== */
+ Insert_ExceptionHandler BusFault_Handler
+/* ======================================================================== */
+ Insert_ExceptionHandler UsageFault_Handler
+/* ======================================================================== */
+ Insert_ExceptionHandler SVC_Handler
+/* ======================================================================== */
+ Insert_ExceptionHandler DebugMon_Handler
+/* ======================================================================== */
+ Insert_ExceptionHandler PendSV_Handler
+/* ======================================================================== */
+ Insert_ExceptionHandler SysTick_Handler
+
+/* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
+
+/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+/* IRQ Handlers */
+ Insert_ExceptionHandler SCU_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler ERU0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler ERU0_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler ERU0_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler ERU0_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler ERU1_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler ERU1_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler ERU1_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler ERU1_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler PMU0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_C0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_C0_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_C0_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_C0_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G0_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G0_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G0_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G1_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G1_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G1_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G1_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G2_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G2_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G2_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G2_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G3_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G3_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G3_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler VADC0_G3_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DSD0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DSD0_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DSD0_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DSD0_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DSD0_4_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DSD0_5_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DSD0_6_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DSD0_7_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DAC0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler DAC0_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU40_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU40_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU40_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU40_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU41_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU41_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU41_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU41_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU42_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU42_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU42_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU42_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU43_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU43_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU43_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU43_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU80_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU80_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU80_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU80_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU81_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU81_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU81_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CCU81_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler POSIF0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler POSIF0_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler POSIF1_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler POSIF1_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CAN0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CAN0_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CAN0_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CAN0_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CAN0_4_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CAN0_5_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CAN0_6_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler CAN0_7_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC0_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC0_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC0_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC0_4_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC0_5_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC1_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC1_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC1_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC1_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC1_4_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC1_5_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC2_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC2_1_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC2_2_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC2_3_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC2_4_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USIC2_5_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler LEDTS0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler FCE0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler GPDMA0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler SDMMC0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler USB0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler ETH0_0_IRQHandler
+/* ======================================================================== */
+ Insert_ExceptionHandler GPDMA1_0_IRQHandler
+/* ======================================================================== */
+/* ======================================================================== */
+
+/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */
+
+/* ======== Decision function queried by CMSIS startup for PLL setup ====== */
+/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock
+ tree setup.
+
+ This decision routine defined here will always return TRUE.
+
+ When overridden by a definition defined in DAVE code engine, this routine
+ returns FALSE indicating that the code engine has performed the clock setup
+*/
+ .weak AllowPLLInitByStartup
+ .type AllowPLLInitByStartup, %function
+AllowPLLInitByStartup:
+ MOV R0,#1
+ BX LR
+ .size AllowPLLInitByStartup, . - AllowPLLInitByStartup
+
+/* ====== Definition of the default weak SystemInit_DAVE3 function =========
+If DAVE3 requires an extended SystemInit it will create its own version of
+SystemInit_DAVE3 which overrides this weak definition. Example includes
+setting up of external memory interfaces.
+*/
+ .section ".XmcStartup"
+ .weak SystemInit_DAVE3
+ .type SystemInit_DAVE3, %function
+SystemInit_DAVE3:
+ NOP
+ BX LR
+ .size SystemInit_DAVE3, . - SystemInit_DAVE3
+/* ======================================================================== */
+/* ======================================================================== */
+
+/* ======================== Data references =============================== */
+.equ SCB_VTOR, 0xE000ED08
+.equ PREF_PCON, 0x58004000
+.equ SCU_GCU_PEEN, 0x5000413C
+.equ SCU_GCU_PEFLAG, 0x50004150
+.equ FLASH_FCON, 0x58002014
+
+ .end
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_XMC4500.c\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the Infineon XMC4500 Device Series\r
+ * @version V3.0.1 Alpha\r
+ * @date 17. September 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include "system_XMC4500.h"\r
+#include <XMC4500.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL 1\r
+#define SCU_CLOCK_BACK_UP_FACTORY 2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC 3\r
+\r
+\r
+#define HIB_CLOCK_FOSI 1 \r
+#define HIB_CLOCK_OSCULP 2\r
+\r
+\r
+\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+\r
+\r
+/*--------------------- Watchdog Configuration -------------------------------\r
+//\r
+// <e> Watchdog Configuration\r
+// <o1.0> Disable Watchdog\r
+//\r
+// </e>\r
+*/\r
+#define WDT_SETUP 1\r
+#define WDTENB_nVal 0x00000001\r
+\r
+/*--------------------- CLOCK Configuration -------------------------------\r
+//\r
+// <e> Main Clock Configuration\r
+// <o1.0..1> CPU clock divider\r
+// <0=> fCPU = fSYS \r
+// <1=> fCPU = fSYS / 2\r
+// <o2.0..1> Peripheral Bus clock divider\r
+// <0=> fPB = fCPU\r
+// <1=> fPB = fCPU / 2\r
+// <o3.0..1> CCU Bus clock divider\r
+// <0=> fCCU = fCPU\r
+// <1=> fCCU = fCPU / 2\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCK_SETUP 1\r
+#define SCU_CPUCLKCR_DIV 0x00000000\r
+#define SCU_PBCLKCR_DIV 0x00000000\r
+#define SCU_CCUCLKCR_DIV 0x00000000\r
+/* not avalible in config wizzard*/\r
+/* \r
+* mandatory clock parameters ************************************************** \r
+* \r
+* source for clock generation \r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) \r
+* \r
+**************************************************************************************/ \r
+// Selection of imput lock for PLL \r
+/*************************************************************************************/\r
+#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY\r
+//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP\r
+//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS 120000000\r
+#define CLOCK_CRYSTAL_FREQUENCY 12000000 \r
+#define CLOCK_BACK_UP 24000000 \r
+ \r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */ \r
+/*************************************************************************************/\r
+#define SCU_OSC_HP_MODE 0xF0\r
+#define SCU_OSCHPWDGDIV 2 \r
+ \r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */ \r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz \r
+/*************************************************************************************/\r
+#define SCU_PLL_K1DIV 1\r
+#define SCU_PLL_K2DIV 3\r
+#define SCU_PLL_PDIV 1\r
+#define SCU_PLL_NDIV 79\r
+ \r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define SCU_PLL_K1DIV 1 \r
+//#define SCU_PLL_K2DIV 3 \r
+//#define SCU_PLL_PDIV 3 \r
+//#define SCU_PLL_NDIV 79 \r
+/*************************************************************************************/\r
+\r
+/*--------------------- USB CLOCK Configuration ---------------------------\r
+//\r
+// <e> USB Clock Configuration\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_USB_CLOCK_SETUP 0\r
+/* not avalible in config wizzard*/\r
+#define SCU_USBPLL_PDIV 0 \r
+#define SCU_USBPLL_NDIV 31 \r
+#define SCU_USBDIV 3 \r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+// <o1.0..3> Flash Wait State\r
+// <0=> 3 WS\r
+// <1=> 4 WS\r
+// <2=> 5 WS \r
+// <3=> 6 WS\r
+// </e>\r
+// \r
+*/\r
+\r
+#define PMU_FLASH 1\r
+#define PMU_FLASH_WS 0x00000000\r
+\r
+\r
+/*--------------------- CLOCKOUT Configuration -------------------------------\r
+//\r
+// <e> Clock OUT Configuration\r
+// <o1.0..1> Clockout Source Selection\r
+// <0=> System Clock\r
+// <2=> Divided value of USB PLL output\r
+// <3=> Divided value of PLL Clock\r
+// <o2.0..4> Clockout divider <1-10><#-1>\r
+// <o3.0..1> Clockout Pin Selection\r
+// <0=> P1.15\r
+// <1=> P0.8\r
+// \r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCKOUT_SETUP 0\r
+#define SCU_CLOCKOUT_SOURCE 0x00000003\r
+#define SCU_CLOCKOUT_DIV 0x00000009\r
+#define SCU_CLOCKOUT_PIN 0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ static functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void);\r
+#endif\r
+\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void);\r
+#endif\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the PLL and update the \r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+int temp;\r
+ \r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
+ (3UL << 11*2) ); /* set CP11 Full Access */\r
+#endif\r
+\r
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+ \r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
+\r
+WDT->CTR &= ~WDTENB_nVal; \r
+\r
+#endif\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON; \r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+ \r
+/* Setup the clockout */\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16;\r
+\r
+if (SCU_CLOCKOUT_PIN) {\r
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+ //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */\r
+ }\r
+else {\r
+ PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/* Setup the System clock */ \r
+#if SCU_CLOCK_SETUP\r
+SystemClockSetup();\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/* Setup the USB PL */ \r
+#if SCU_USB_CLOCK_SETUP\r
+USBClockSetup();\r
+#endif\r
+\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+if (SCU_CLK->SYSCLKCR == 0x00010000)\r
+{\r
+ if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+ /* check if PLL is locked */\r
+ /* read back divider settings */\r
+ PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+ NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+ K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+ if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+ /* the selected clock is the Backup clock fofi */\r
+ VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* the selected clock is the PLL external oscillator */ \r
+ VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+ SystemCoreClock = VCO/K2DIV;\r
+ /* in case the sysclock div is used */\r
+ SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+ } \r
+ \r
+ \r
+ }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief -\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void)\r
+{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV; \r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+ \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+/* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+\r
+}\r
+\r
+/* Enable OSC_HP if not already on*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use external crystal for PLL clock input */\r
+ /********************************************************************************************************************/\r
+\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
+\r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ do \r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+\r
+ }\r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use factory trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ }\r
+ else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+ {\r
+ /********************************************************************************************************************/\r
+ /* Use automatic trimming Back-up clock for PLL clock input */\r
+ /********************************************************************************************************************/\r
+ /* check for HIB Domain enabled */\r
+ if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+ SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+ /* check for HIB Domain is not in reset state */\r
+ if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+ SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+ /* PLL Back up clock selected */\r
+ SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ \r
+ if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fOSI as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ }\r
+ else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+ {\r
+ /****************************************************************************************************************/\r
+ /* Use fULP as source of the standby clock */\r
+ /****************************************************************************************************************/\r
+ /*check OSCUL if running correct*/\r
+ if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+ {\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+ SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+ /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+ /* select OSCUL clock for RTC*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*enable OSCULP WDG Alarm Enable*/\r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ /*wait now for clock is stable */\r
+ do\r
+ {\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ }\r
+ while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
+\r
+ SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+ } \r
+ // now OSCULP is running and can be used \r
+ SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+ while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+ \r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+ /*TRIAL for delay loop*/\r
+ for(temp=0;temp<=0xFFFF;temp++);\r
+ \r
+ }\r
+ }\r
+\r
+ /********************************************************************************************************************/\r
+ /* Setup and look the main PLL */\r
+ /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+ /* Systen is still running from internal clock */\r
+ /* select FOFI as system clock */\r
+ if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/24000000)-1; \r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ /* disconnect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ /* connect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ /* setup time out loop */\r
+ /* Timeout for wait loo ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ \r
+ while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+\r
+ if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+ {\r
+ /* Go back to the Main PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ }\r
+ else return(0);\r
+ \r
+ \r
+ /*********************************************************\r
+ here we need to setup the system clock divider\r
+ *********************************************************/\r
+ \r
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; \r
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+ \r
+\r
+ /* Switch system clock to PLL */\r
+ SCU_CLK->SYSCLKCR |= 0x00010000; \r
+ \r
+ /* we may have to reset OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ \r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /*********************************************************/\r
+\r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 60MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 60000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ \r
+ stepping_K2DIV = (VCO/60000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+\r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
+ /*********************************************************\r
+ here the ramp up of the system clock starts FSys < 90MHz\r
+ *********************************************************/\r
+ if (CLOCK_FSYS > 90000000){\r
+ /*calulation for stepping*/\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+ if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+ VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+ stepping_K2DIV = (VCO/90000000)-1; \r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ }\r
+ else\r
+ {\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ return(1);\r
+ }\r
+ \r
+ /*********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /*********************************************************/\r
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ \r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+ \r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+ \r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+ }\r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief -\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
+{\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+\r
+ /* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
+\r
+/* check and if not already running enable OSC_HP */\r
+ if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+ /* check if Main PLL is switched on for OSC WD*/\r
+ if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+ /* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+ }\r
+ SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); \r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
+ \r
+ /* Timeout for wait loop ~150ms */\r
+ /********************************/\r
+ SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ \r
+ do \r
+ {\r
+ ;/* wait for ~150ms */\r
+ }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+ return(0);/* Return Error */\r
+ \r
+ }\r
+\r
+\r
+/* Setup USB PLL */\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
+ /* disconnect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+ /* Setup USBDIV settings USB clock */\r
+ SCU_CLK->USBCLKCR = SCU_USBDIV;\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
+ /* connect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
+ \r
+ }/* end this weak function enables DAVE3 clock App usage */ \r
+ return(1);\r
+\r
+}\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ *\r
+ * \r
+ * Additional code:\r
+ * \r
+ * This demo does not contain a non-kernel interrupt service routine that\r
+ * can be used as an example for application writers to use as a reference.\r
+ * Therefore, the framework of a dummy (not installed) handler is provided\r
+ * in this file. The dummy function is called Dummy_IRQHandler(). Please\r
+ * ensure to read the comments in the function itself, but more importantly,\r
+ * the notes on the function contained on the documentation page for this demo\r
+ * that is found on the FreeRTOS.org web site.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Set up the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/* \r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. \r
+ */\r
+extern void main_blinky( void );\r
+extern void main_full( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Prepare the hardware to run this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ configCONFIGURE_LED();\r
+\r
+ /* Ensure all priority bits are assigned as preemption priority bits. */\r
+ NVIC_SetPriorityGrouping( 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if \r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef JUST_AN_EXAMPLE_ISR\r
+\r
+void Dummy_IRQHandler(void)\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Clear the interrupt if necessary. */\r
+ Dummy_ClearITPendingBit();\r
+ \r
+ /* This interrupt does nothing more than demonstrate how to synchronise a\r
+ task with an interrupt. A semaphore is used for this purpose. Note\r
+ lHigherPriorityTaskWoken is initialised to zero. */\r
+ xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
+ \r
+ /* If there was a task that was blocked on the semaphore, and giving the\r
+ semaphore caused the task to unblock, and the unblocked task has a priority\r
+ higher than the current Running state task (the task that this interrupt\r
+ interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE\r
+ internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the \r
+ portEND_SWITCHING_ISR() macro will result in a context switch being pended to\r
+ ensure this interrupt returns directly to the unblocked, higher priority, \r
+ task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */\r
+ portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
+\r
+#endif /* JUST_AN_EXAMPLE_ISR */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles the LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* Values passed to the two tasks just to check the task parameter\r
+functionality. */\r
+#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
+#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again.\r
+ The block time is specified in ticks, the constant used converts ticks\r
+ to ms. While in the Blocked state this task will not consume any CPU\r
+ time. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ configTOGGLE_LED();\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and a software timer, then\r
+ * starts the scheduler. The web documentation provides more details of the \r
+ * standard demo application tasks, which provide no particular functionality, \r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" timer - The check software timer period is initially set to three\r
+ * seconds. The callback function associated with the check software timer\r
+ * checks that all the standard demo tasks, and the register check tasks, are\r
+ * not only still executing, but are executing without reporting any errors. If\r
+ * the check software timer discovers that a task has either stalled, or\r
+ * reported an error, then it changes its own execution period from the initial\r
+ * three seconds, to just 200ms. The check software timer callback function\r
+ * also toggles the single LED each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "flop.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the FPU registers, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly file.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters ) __attribute__((naked));\r
+static void prvRegTest2Task( void *pvParameters ) __attribute__((naked));\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check software timer. If the variables keep\r
+incrementing, then the register check tasks has not discovered any errors. If\r
+a variable stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+xTimerHandle xCheckTimer = NULL;\r
+\r
+ /* Start all the other standard demo/test tasks. The have not particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartDynamicPriorityTasks();\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ \r
+ /* Create the register check tasks, as described at the top of this\r
+ file */\r
+ xTaskCreate( prvRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ ); \r
+ \r
+ if( xCheckTimer != NULL )\r
+ {\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* If all is well, the scheduler will now be running, and the following line\r
+ will never be reached. If the following line does execute, then there was\r
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+ to be created. See the memory management section on the FreeRTOS web site\r
+ for more details. */\r
+ for( ;; ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ \r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ configTOGGLE_LED(); \r
+ \r
+ /* Have any errors been latch in ulErrorFound? If so, shorten the\r
+ period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+ This will result in an increase in the rate at which mainCHECK_LED\r
+ toggles. */\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+ \r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is a naked function. */\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ __asm volatile\r
+ (\r
+ " /* Fill the core registers with known values. */ \n"\r
+ " mov r0, #100 \n"\r
+ " mov r1, #101 \n"\r
+ " mov r2, #102 \n"\r
+ " mov r3, #103 \n"\r
+ " mov r4, #104 \n"\r
+ " mov r5, #105 \n"\r
+ " mov r6, #106 \n"\r
+ " mov r7, #107 \n"\r
+ " mov r8, #108 \n"\r
+ " mov r9, #109 \n"\r
+ " mov r10, #110 \n"\r
+ " mov r11, #111 \n"\r
+ " mov r12, #112 \n"\r
+ " \n"\r
+ " /* Fill the VFP registers with known values. */ \n"\r
+ " vmov d0, r0, r1 \n"\r
+ " vmov d1, r2, r3 \n"\r
+ " vmov d2, r4, r5 \n"\r
+ " vmov d3, r6, r7 \n"\r
+ " vmov d4, r8, r9 \n"\r
+ " vmov d5, r10, r11 \n"\r
+ " vmov d6, r0, r1 \n"\r
+ " vmov d7, r2, r3 \n"\r
+ " vmov d8, r4, r5 \n"\r
+ " vmov d9, r6, r7 \n"\r
+ " vmov d10, r8, r9 \n"\r
+ " vmov d11, r10, r11 \n"\r
+ " vmov d12, r0, r1 \n"\r
+ " vmov d13, r2, r3 \n"\r
+ " vmov d14, r4, r5 \n"\r
+ " vmov d15, r6, r7 \n"\r
+ " \n"\r
+ "reg1_loop: \n"\r
+ " /* Check all the VFP registers still contain the values set above.\n"\r
+ " First save registers that are clobbered by the test. */ \n"\r
+ " push { r0-r1 } \n"\r
+ " \n"\r
+ " vmov r0, r1, d0 \n"\r
+ " cmp r0, #100 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #101 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d1 \n"\r
+ " cmp r0, #102 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #103 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d2 \n"\r
+ " cmp r0, #104 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #105 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d3 \n"\r
+ " cmp r0, #106 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #107 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d4 \n"\r
+ " cmp r0, #108 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #109 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d5 \n"\r
+ " cmp r0, #110 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #111 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d6 \n"\r
+ " cmp r0, #100 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #101 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d7 \n"\r
+ " cmp r0, #102 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #103 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d8 \n"\r
+ " cmp r0, #104 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #105 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d9 \n"\r
+ " cmp r0, #106 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #107 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d10 \n"\r
+ " cmp r0, #108 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #109 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d11 \n"\r
+ " cmp r0, #110 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #111 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d12 \n"\r
+ " cmp r0, #100 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #101 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d13 \n"\r
+ " cmp r0, #102 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #103 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d14 \n"\r
+ " cmp r0, #104 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #105 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " vmov r0, r1, d15 \n"\r
+ " cmp r0, #106 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " cmp r1, #107 \n"\r
+ " bne reg1_error_loopf \n"\r
+ " \n"\r
+ " /* Restore the registers that were clobbered by the test. */\n"\r
+ " pop {r0-r1} \n"\r
+ " \n"\r
+ " /* VFP register test passed. Jump to the core register test. */\n"\r
+ " b reg1_loopf_pass \n"\r
+ " \n"\r
+ "reg1_error_loopf: \n"\r
+ " /* If this line is hit then a VFP register value was found to be\n"\r
+ " incorrect. */ \n"\r
+ " b reg1_error_loopf \n"\r
+ " \n"\r
+ "reg1_loopf_pass: \n"\r
+ " \n"\r
+ " cmp r0, #100 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r1, #101 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r2, #102 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r3, #103 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r4, #104 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r5, #105 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r6, #106 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r7, #107 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r8, #108 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r9, #109 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r10, #110 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r11, #111 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r12, #112 \n"\r
+ " bne reg1_error_loop \n"\r
+ " \n"\r
+ " /* Everything passed, increment the loop counter. */ \n"\r
+ " push { r0-r1 } \n"\r
+ " ldr r0, =ulRegTest1LoopCounter \n"\r
+ " ldr r1, [r0] \n"\r
+ " adds r1, r1, #1 \n"\r
+ " str r1, [r0] \n"\r
+ " pop { r0-r1 } \n"\r
+ " \n"\r
+ " /* Start again. */ \n"\r
+ " b reg1_loop \n"\r
+ " \n"\r
+ "reg1_error_loop: \n"\r
+ " /* If this line is hit then there was an error in a core register value.\n"\r
+ " The loop ensures the loop counter stops incrementing. */\n"\r
+ " b reg1_error_loop \n"\r
+ " nop "\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is a naked function. */\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ __asm volatile\r
+ (\r
+ " /* Set all the core registers to known values. */ \n"\r
+ " mov r0, #-1 \n"\r
+ " mov r1, #1 \n"\r
+ " mov r2, #2 \n"\r
+ " mov r3, #3 \n"\r
+ " mov r4, #4 \n"\r
+ " mov r5, #5 \n"\r
+ " mov r6, #6 \n"\r
+ " mov r7, #7 \n"\r
+ " mov r8, #8 \n"\r
+ " mov r9, #9 \n"\r
+ " mov r10, #10 \n"\r
+ " mov r11, #11 \n"\r
+ " mov r12, #12 \n"\r
+ " \n"\r
+ " /* Set all the VFP to known values. */ \n"\r
+ " vmov d0, r0, r1 \n"\r
+ " vmov d1, r2, r3 \n"\r
+ " vmov d2, r4, r5 \n"\r
+ " vmov d3, r6, r7 \n"\r
+ " vmov d4, r8, r9 \n"\r
+ " vmov d5, r10, r11 \n"\r
+ " vmov d6, r0, r1 \n"\r
+ " vmov d7, r2, r3 \n"\r
+ " vmov d8, r4, r5 \n"\r
+ " vmov d9, r6, r7 \n"\r
+ " vmov d10, r8, r9 \n"\r
+ " vmov d11, r10, r11 \n"\r
+ " vmov d12, r0, r1 \n"\r
+ " vmov d13, r2, r3 \n"\r
+ " vmov d14, r4, r5 \n"\r
+ " vmov d15, r6, r7 \n"\r
+ " \n"\r
+ "reg2_loop: \n"\r
+ " \n"\r
+ " /* Check all the VFP registers still contain the values set above.\n"\r
+ " First save registers that are clobbered by the test. */ \n"\r
+ " push { r0-r1 } \n"\r
+ " \n"\r
+ " vmov r0, r1, d0 \n"\r
+ " cmp r0, #-1 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #1 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d1 \n"\r
+ " cmp r0, #2 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #3 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d2 \n"\r
+ " cmp r0, #4 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #5 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d3 \n"\r
+ " cmp r0, #6 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #7 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d4 \n"\r
+ " cmp r0, #8 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #9 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d5 \n"\r
+ " cmp r0, #10 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #11 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d6 \n"\r
+ " cmp r0, #-1 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #1 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d7 \n"\r
+ " cmp r0, #2 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #3 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d8 \n"\r
+ " cmp r0, #4 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #5 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d9 \n"\r
+ " cmp r0, #6 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #7 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d10 \n"\r
+ " cmp r0, #8 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #9 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d11 \n"\r
+ " cmp r0, #10 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #11 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d12 \n"\r
+ " cmp r0, #-1 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #1 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d13 \n"\r
+ " cmp r0, #2 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #3 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d14 \n"\r
+ " cmp r0, #4 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #5 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " vmov r0, r1, d15 \n"\r
+ " cmp r0, #6 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " cmp r1, #7 \n"\r
+ " bne reg2_error_loopf \n"\r
+ " \n"\r
+ " /* Restore the registers that were clobbered by the test. */\n"\r
+ " pop {r0-r1} \n"\r
+ " \n"\r
+ " /* VFP register test passed. Jump to the core register test. */\n"\r
+ " b reg2_loopf_pass \n"\r
+ " \n"\r
+ "reg2_error_loopf: \n"\r
+ " /* If this line is hit then a VFP register value was found to be\n"\r
+ " incorrect. */ \n"\r
+ " b reg2_error_loopf \n"\r
+ " \n"\r
+ "reg2_loopf_pass: \n"\r
+ " \n"\r
+ " cmp r0, #-1 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r1, #1 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r2, #2 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r3, #3 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r4, #4 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r5, #5 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r6, #6 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r7, #7 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r8, #8 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r9, #9 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r10, #10 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r11, #11 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r12, #12 \n"\r
+ " bne reg2_error_loop \n"\r
+ " \n"\r
+ " /* Increment the loop counter to indicate this test is still functioning\n"\r
+ " correctly. */ \n"\r
+ " push { r0-r1 } \n"\r
+ " ldr r0, =ulRegTest2LoopCounter \n"\r
+ " ldr r1, [r0] \n"\r
+ " adds r1, r1, #1 \n"\r
+ " str r1, [r0] \n"\r
+ " pop { r0-r1 } \n"\r
+ " \n"\r
+ " /* Start again. */ \n"\r
+ " b reg2_loop \n"\r
+ " \n"\r
+ "reg2_error_loop: \n"\r
+ " /* If this line is hit then there was an error in a core register value.\n"\r
+ " This loop ensures the loop counter variable stops incrementing. */\n"\r
+ " b reg2_error_loop \n"\r
+ " nop \n"\r
+ );\r
+}\r
projects / freertos / commitdiff