]> git.sur5r.net Git - u-boot/commitdiff
Convert socfpga: select CONFIG_HW_WATCHDOG support for ARCH_SOCFPGA
authorLukasz Majewski <lukma@denx.de>
Tue, 13 Feb 2018 05:34:13 +0000 (06:34 +0100)
committerMarek Vasut <marex@denx.de>
Thu, 15 Feb 2018 12:45:16 +0000 (13:45 +0100)
All Socfpga boards from ./include/configs/socfpga_* define
CONFIG_HW_WATCHDOG.
To ease CONFIG_HW_WATCHDOG conversion to Kconfig select it in
config ARCH_SOCFPGA (arch/arm/Kconfig) section.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
13 files changed:
arch/arm/Kconfig
include/configs/socfpga_arria10_socdk.h
include/configs/socfpga_arria5_socdk.h
include/configs/socfpga_cyclone5_socdk.h
include/configs/socfpga_de0_nano_soc.h
include/configs/socfpga_de10_nano.h
include/configs/socfpga_de1_soc.h
include/configs/socfpga_is1.h
include/configs/socfpga_mcvevk.h
include/configs/socfpga_sockit.h
include/configs/socfpga_socrates.h
include/configs/socfpga_sr1500.h
include/configs/socfpga_vining_fpga.h

index 7b618d6881759697aaa9b24f3c3758d2fdae25df..f6e43c6a2aaf99b215f01b414f07674ab093631e 100644 (file)
@@ -701,6 +701,7 @@ config ARCH_SOCFPGA
        select DM_SPI_FLASH
        select DM_SPI
        select ENABLE_ARM_SOC_BOOT0_HOOK
+       select HW_WATCHDOG
        select ARCH_EARLY_INIT_R
        select ARCH_MISC_INIT
        select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
index 83718dd2c9cb9864e77079a859f7bc8890acc2f8..82bb48b2777022c92b0e197dab16c17459d80208 100644 (file)
@@ -9,8 +9,6 @@
 
 #include <asm/arch/base_addr_a10.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Booting Linux */
 #define CONFIG_LOADADDR                0x01000000
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
index 6b6d54b97b1a571e06391d3aeacf5736219fc683..cd5aac65e922115d186709bd0e18c19fa4122fef 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */
 
index 018a0c3bb48a494de01937740f620f26fa30521b..9c5bd648e3d4d82d756519b2fc1adde8e2b70eda 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */
 
index 275ed7ffebbdbbc8dafc14cc4e3e14e5bb918cc1..e5db00e36612a8accb51712f265764ecf987c22a 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB */
 
index bb50fcf1ff02600d06404a7e9bfd9e9c30696aee..656af1104dd7e17a3c99a841434641cd2954c219 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB */
 
index 05975c9bde4b458d877543dbdd8eb5c6b9953b2a..f57b9504259eccd7a2e9f2f84538b266f940fa7f 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB */
 
index 46f5f135dd5d9a0df7fcc25f9b4bf38fce61a942..dc318e50dc9b2f7b1c2a2aad4fd1f56f193a29f9 100644 (file)
@@ -9,8 +9,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x10000000
 
index 404f064e948a42918e35817446e3cc242f61c5d6..f13463b8b0681f814de946bfe900a2872e531669 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on MCV */
 
index b4f31c42c5083fe20af894095e044d6d13e2cc5e..0bbc7e010541d1347d454d9037939b98df37d6a0 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCDK */
 
index ebb9ac588d7b270b158d2ba38ee24c4317b8ab1c..b66108d0ccd49f7fecfb1ef33dfaae0ee0ba17e0 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SoCrates */
 
index 39bf612291f46e42676b28d59d7020c19a74802f..871f587d458337b13d0decf4b5180d057b496447 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SR1500 */
 
index 0c76a775256de18e5446ac7bff9d78941d703bb6..1197b40b58b2286a09b07492fd10afdc063dc38b 100644 (file)
@@ -8,8 +8,6 @@
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on VINING_FPGA */