All Socfpga boards from ./include/configs/socfpga_* define
CONFIG_HW_WATCHDOG.
To ease CONFIG_HW_WATCHDOG conversion to Kconfig select it in
config ARCH_SOCFPGA (arch/arm/Kconfig) section.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
13 files changed:
select DM_SPI_FLASH
select DM_SPI
select ENABLE_ARM_SOC_BOOT0_HOOK
select DM_SPI_FLASH
select DM_SPI
select ENABLE_ARM_SOC_BOOT0_HOOK
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
#include <asm/arch/base_addr_a10.h>
#include <asm/arch/base_addr_a10.h>
-#define CONFIG_HW_WATCHDOG
-
/* Booting Linux */
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Booting Linux */
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x10000000
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x10000000
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
#include <asm/arch/base_addr_ac5.h>
#include <asm/arch/base_addr_ac5.h>
-#define CONFIG_HW_WATCHDOG
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */