<listOptionValue builtIn="false" value="CORE_M3"/>\r
<listOptionValue builtIn="false" value="__LPC18XX__"/>\r
</option>\r
- <option id="gnu.c.compiler.option.misc.other.732935978" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -Wextra" valueType="string"/>\r
+ <option id="gnu.c.compiler.option.misc.other.732935978" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -std=gnu99" valueType="string"/>\r
<option id="com.crt.advproject.gcc.hdrlib.1620518189" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.codered" valueType="enumerated"/>\r
<option id="gnu.c.compiler.option.include.paths.1643954527" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Examples/Ethernet/EchoClients}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Examples/Ethernet/UDP-Trace-Macros/Example1}""/>\r
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Examples/USB_CDC}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/LPCUSBLib/Drivers/USB}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_board/board_common}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_common}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/CMSIS/Include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_ip}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_chip/chip_18xx_43xx}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/LPCOpen/lpc_core/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830}""/>\r
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/TraceRecorderSrc/Include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Plus_CLI}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Examples/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/USB_CDC/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/ARM_CM3}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Plus_UDP/include}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Plus_UDP/portable/Compiler/GCC}""/>\r
- <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS-Plus-CLI}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS-Source/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS-Source/portable/GCC/ARM_CM3}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS-Plus-UDP/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS-Plus-UDP/portable/Compiler/GCC}""/>\r
</option>\r
<inputType id="com.crt.advproject.compiler.input.927112517" superClass="com.crt.advproject.compiler.input"/>\r
</tool>\r
</option>\r
<option id="com.crt.advproject.link.gcc.hdrlib.2006557555" name="Use C library" superClass="com.crt.advproject.link.gcc.hdrlib" value="com.crt.advproject.gcc.link.hdrlib.codered.nohost" valueType="enumerated"/>\r
<option id="gnu.c.link.option.nodeflibs.2072403274" name="Do not use default libraries (-nodefaultlibs)" superClass="gnu.c.link.option.nodeflibs" value="false" valueType="boolean"/>\r
+ <option id="com.crt.advproject.link.gcc.multicore.slave.1593308693" name="Multicore slave" superClass="com.crt.advproject.link.gcc.multicore.slave"/>\r
<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.1085761099" superClass="cdt.managedbuild.tool.gnu.c.linker.input">\r
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
<additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
<tool id="com.crt.advproject.link.exe.debug.953255510" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug.1212311005"/>\r
</toolChain>\r
</folderInfo>\r
- <folderInfo id="com.crt.advproject.config.exe.debug.56486929.1781697322" name="/" resourcePath="ThirdParty/CMSISv2p10_LPC18xx_DriverLib">\r
- <toolChain id="com.crt.advproject.toolchain.exe.debug.222538953" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug" unusedChildren="">\r
- <tool id="com.crt.advproject.cpp.exe.debug.906161578" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug.359174792"/>\r
- <tool id="com.crt.advproject.gcc.exe.debug.1015468334" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.517029683">\r
- <option id="com.crt.advproject.gcc.exe.debug.option.optimization.level.2021633161" superClass="com.crt.advproject.gcc.exe.debug.option.optimization.level" value="gnu.c.optimization.level.size" valueType="enumerated"/>\r
- <inputType id="com.crt.advproject.compiler.input.1878730423" superClass="com.crt.advproject.compiler.input"/>\r
- </tool>\r
- <tool id="com.crt.advproject.gas.exe.debug.253843695" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug.281614531">\r
- <inputType id="cdt.managedbuild.tool.gnu.assembler.input.1935362347" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>\r
- <inputType id="com.crt.advproject.assembler.input.190369423" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>\r
- </tool>\r
- <tool id="com.crt.advproject.link.cpp.exe.debug.1715304950" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug.1490011469"/>\r
- <tool id="com.crt.advproject.link.exe.debug.536813209" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug.1212311005"/>\r
- </toolChain>\r
- </folderInfo>\r
- <folderInfo id="com.crt.advproject.config.exe.debug.56486929.2106668528" name="/" resourcePath="ThirdParty/USB_CDC">\r
- <toolChain id="com.crt.advproject.toolchain.exe.debug.1865989435" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug" unusedChildren="">\r
- <targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>\r
- <tool id="com.crt.advproject.cpp.exe.debug.1158267972" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug.359174792"/>\r
- <tool id="com.crt.advproject.gcc.exe.debug.1784372430" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug.517029683">\r
- <option id="com.crt.advproject.gcc.exe.debug.option.optimization.level.369260631" name="Optimization Level" superClass="com.crt.advproject.gcc.exe.debug.option.optimization.level" value="gnu.c.optimization.level.size" valueType="enumerated"/>\r
- <inputType id="com.crt.advproject.compiler.input.466388069" superClass="com.crt.advproject.compiler.input"/>\r
- </tool>\r
- <tool id="com.crt.advproject.gas.exe.debug.401476199" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug.281614531">\r
- <inputType id="cdt.managedbuild.tool.gnu.assembler.input.1255426283" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>\r
- <inputType id="com.crt.advproject.assembler.input.882456885" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>\r
- </tool>\r
- <tool id="com.crt.advproject.link.cpp.exe.debug.2009352548" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug.1490011469"/>\r
- <tool id="com.crt.advproject.link.exe.debug.1734116997" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug.1212311005"/>\r
- </toolChain>\r
- </folderInfo>\r
<fileInfo id="com.crt.advproject.config.exe.debug.56486929.src/cr_startup_lpc18xx.cpp" name="cr_startup_lpc18xx.cpp" rcbsApplicability="disable" resourcePath="src/cr_startup_lpc18xx.cpp" toolsToInvoke=""/>\r
<sourceEntries>\r
- <entry excluding="ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_wwdt.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_utils.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_uart.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_timer.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_ssp.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_sct.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rtc.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_rit.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_qei.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_pwr.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_nvic.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_mcpwm.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_libcfg_default.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_lcd.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2s.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_i2c.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_gpdma.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_evrt.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_emc.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_dac.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_can.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_atimer.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/lpc18xx_adc.c|ThirdParty/CMSISv2p10_LPC18xx_DriverLib/src/debug_frmwrk.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
+ <entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>\r
</sourceEntries>\r
</configuration>\r
</storageModule>\r
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
</natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>FreeRTOS-Plus-CLI</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Examples/Ethernet</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/FreeRTOS_DHCP.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DHCP.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/FreeRTOS_DNS.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_DNS.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/FreeRTOS_Sockets.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_Sockets.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/FreeRTOS_UDP_IP.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/FreeRTOS_UDP_IP.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/include</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/include</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/portable</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/include</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/include</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/list.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/list.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/portable</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/queue.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/queue.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/tasks.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/tasks.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/timers.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/timers.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Examples/Ethernet/EchoClients</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Examples/Ethernet/UDP-Trace-Macros</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/portable/BufferManagement</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/portable/Compiler</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/portable/NetworkInterface</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/portable/GCC</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/portable/MemMang</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Examples/Ethernet/UDP-Trace-Macros/Example1</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_2.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/BufferManagement/BufferAllocation_2.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/portable/Compiler/GCC</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/Compiler/GCC</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/portable/NetworkInterface/LPC18xx</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/portable/GCC/ARM_CM3</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/portable/GCC/ARM_CM3</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS-Source/portable/MemMang/heap_4.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source/portable/MemMang/heap_4.c</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+ <variableList>\r
+ <variable>\r
+ <name>FREERTOS_ROOT</name>\r
+ <value>$%7BPARENT-3-PROJECT_LOC%7D</value>\r
+ </variable>\r
+ </variableList>\r
</projectDescription>\r
+++ /dev/null
-REM This file should be executed from the command line prior to the first\r
-REM build. It will be necessary to refresh the Eclipse project once the\r
-REM .bat file has been executed (normally just press F5 to refresh).\r
-\r
-REM Copies all the required files from their location within the standard\r
-REM FreeRTOS directory structure to under the Eclipse project directory.\r
-REM This permits the Eclipse project to be used in 'managed' mode and without\r
-REM having to setup any linked resources.\r
-\r
-REM Standard paths\r
-SET FREERTOS_SOURCE=..\..\..\FreeRTOS\Source\r
-SET FREERTOS_UDP_SOURCE=..\..\Source\FreeRTOS-Plus-UDP\r
-SET FREERTOS_CLI_SOURCE=..\..\Source\FreeRTOS-Plus-CLI\r
-\r
-REM Have the files already been copied?\r
-IF EXIST FreeRTOS_Source Goto END\r
-\r
- REM Create the required directory structure.\r
- MD FreeRTOS_Source\r
- MD FreeRTOS_Source\include\r
- MD FreeRTOS_Source\portable\\r
- MD FreeRTOS_Source\portable\GCC\r
- MD FreeRTOS_Source\portable\GCC\ARM_CM3\r
- MD FreeRTOS_Source\portable\MemMang\r
- MD FreeRTOS_Plus_UDP\r
- MD FreeRTOS_Plus_UDP\include\r
- MD FreeRTOS_Plus_UDP\portable\r
- MD FreeRTOS_Plus_UDP\portable\Compiler\r
- MD FreeRTOS_Plus_UDP\portable\Compiler\GCC\r
- MD FreeRTOS_Plus_UDP\portable\BufferManagement\r
- MD FreeRTOS_Plus_UDP\portable\NetworkInterface\r
- MD FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx\r
- MD FreeRTOS_Plus_CLI\r
- MD Examples\Ethernet\r
-\r
- REM Copy the core kernel files into the SDK projects directory\r
- copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source\r
- copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source\r
- copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source\r
- copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source\r
-\r
- REM Copy the common header files into the SDK projects directory\r
- copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include\r
-\r
- REM Copy the portable layer files into the projects directory\r
- copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM3\*.* FreeRTOS_Source\portable\GCC\ARM_CM3\r
-\r
- REM Copy the memory allocation file into the project's directory\r
- copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c FreeRTOS_Source\portable\MemMang\r
-\r
- REM Copy the FreeRTOS+UDP core files\r
- copy %FREERTOS_UDP_SOURCE%\*.c FreeRTOS_Plus_UDP\r
- copy %FREERTOS_UDP_SOURCE%\include\*.h FreeRTOS_Plus_UDP\r
- copy %FREERTOS_UDP_SOURCE%\readme.txt FreeRTOS_Plus_UDP\r
- copy %FREERTOS_UDP_SOURCE%\include\*.* FreeRTOS_Plus_UDP\include\r
-\r
- REM Copy the FreeRTOS+UDP portable layer files\r
- copy %FREERTOS_UDP_SOURCE%\portable\NetworkInterface\LPC18xx\*.* FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx\r
- copy %FREERTOS_UDP_SOURCE%\portable\BufferManagement\BufferAllocation_2.c FreeRTOS_Plus_UDP\portable\BufferManagement\r
- copy %FREERTOS_UDP_SOURCE%\portable\Compiler\GCC\*.* FreeRTOS_Plus_UDP\portable\Compiler\GCC\r
-\r
- REM Copy the FreeRTOS+CLI files\r
- copy %FREERTOS_CLI_SOURCE%\*.* FreeRTOS_Plus_CLI\r
-\r
- REM Copy the echo client example implementation\r
- copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.c Examples\Ethernet\r
- copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.h Examples\include\r
-\r
- REM Copy the example IP trace macro implementation\r
- copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.c Examples\Ethernet\r
- copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.h Examples\include\r
-\r
- REM Copy the CLI commands implementation into the project directory.\r
- copy ..\Common\FreeRTOS_Plus_UDP_Demos\CLICommands\CLI-commands.c .\r
-\r
-: END\r
/* Standard includes. */\r
#include "string.h"\r
#include "stdio.h"\r
+#include "limits.h"\r
\r
/* FreeRTOS includes. */\r
#include "FreeRTOS.h"\r
#include "task.h"\r
#include "semphr.h"\r
\r
-/* Driver includes. */\r
-#include "usbhw.h"\r
-#include "cdcuser.h"\r
-#include "usbcfg.h"\r
-#include "usbuser.h"\r
+/* LPCUSB includes. */\r
+#include "USB.h"\r
+#include "Descriptors.h"\r
\r
/* Example includes. */\r
#include "FreeRTOS_CLI.h"\r
static void prvCDCCommandConsoleTask( void *pvParameters );\r
\r
/*\r
- * Obtain a character from the CDC input. The calling task will be held in the\r
- * Blocked state (so other tasks can execute) until a character is avilable.\r
+ * Some USB processing is deferred from LPCUSB interrupt service routines to\r
+ * LPCUSB functions that are called from a FreeRTOS task.\r
+ * prvNotifyTaskofUSBEvent() is used from interrupt event callback functions.\r
+ * It uses a semaphore to unblock the handling task whenever task level\r
+ * processing might be required.\r
*/\r
-int8_t cGetCDCChar( void );\r
-\r
-/*\r
- * Initialise the third party virtual comport files driver\r
- */\r
-static void prvSetupUSBDrivers( void );\r
+static void prvNotifyTaskOfUSBEvent( void );\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* 'Given' by the CDC interrupt to unblock the receiving task when new data\r
-is available. */\r
-static xSemaphoreHandle xNewDataSemaphore = NULL;\r
+/* 'Given' by the CDC interrupt to unblock the command console task when CDC\r
+events are potentially waiting to be processed. */\r
+static xSemaphoreHandle xCDCEventSemaphore = NULL;\r
\r
/* Used to guard access to the CDC output, which is used by more than one\r
task. */\r
static xSemaphoreHandle xCDCMutex = NULL;\r
\r
/* Const messages output by the command console. */\r
-static const uint8_t * const pcWelcomeMessage = ( uint8_t * ) "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";\r
-static const uint8_t * const pcEndOfOutputMessage = ( uint8_t * ) "\r\n[Press ENTER to execute the previous command again]\r\n>";\r
-static const uint8_t * const pcNewLine = ( uint8_t * ) "\r\n";\r
+static const char * const pcWelcomeMessage = "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";\r
+static const char * const pcEndOfOutputMessage = "\r\n[Press ENTER to execute the previous command again]\r\n>";\r
+static const char * const pcNewLine = "\r\n";\r
+\r
+/* LPCUSBlib CDC Class driver interface configuration and state information. */\r
+static USB_ClassInfo_CDC_Device_t xVirtualCOMPort = {\r
+ .Config = {\r
+ .ControlInterfaceNumber = 0,\r
+\r
+ .DataINEndpointNumber = CDC_TX_EPNUM,\r
+ .DataINEndpointSize = CDC_TXRX_EPSIZE,\r
+ .DataINEndpointDoubleBank = false,\r
+\r
+ .DataOUTEndpointNumber = CDC_RX_EPNUM,\r
+ .DataOUTEndpointSize = CDC_TXRX_EPSIZE,\r
+ .DataOUTEndpointDoubleBank = false,\r
+\r
+ .NotificationEndpointNumber = CDC_NOTIFICATION_EPNUM,\r
+ .NotificationEndpointSize = CDC_NOTIFICATION_EPSIZE,\r
+ .NotificationEndpointDoubleBank = false,\r
+ .PortNumber = 0,\r
+ },\r
+};\r
\r
/*-----------------------------------------------------------*/\r
\r
{\r
/* Create the semaphores and mutexes used by the CDC to task interface. */\r
xCDCMutex = xSemaphoreCreateMutex();\r
- vSemaphoreCreateBinary( xNewDataSemaphore );\r
+ xCDCEventSemaphore = xSemaphoreCreateCounting( UINT_MAX, 0 );\r
configASSERT( xCDCMutex );\r
- configASSERT( xNewDataSemaphore );\r
+ configASSERT( xCDCEventSemaphore );\r
\r
/* Add the semaphore and mutex to the queue registry for viewing in the\r
kernel aware state viewer. */\r
vQueueAddToRegistry( xCDCMutex, ( signed char * ) "CDCMu" );\r
- vQueueAddToRegistry( xNewDataSemaphore, ( signed char * ) "CDCDat" );\r
+ vQueueAddToRegistry( xCDCEventSemaphore, ( signed char * ) "CDCDat" );\r
\r
/* Create that task that handles the console itself. */\r
xTaskCreate( prvCDCCommandConsoleTask, /* The task that implements the command console. */\r
\r
static void prvCDCCommandConsoleTask( void *pvParameters )\r
{\r
-int8_t cRxedChar, cInputIndex = 0, *pcOutputString;\r
-static int8_t cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];\r
-portBASE_TYPE xReturned;\r
+char cRxedChar, *pcOutputString;\r
+static char cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];\r
+portBASE_TYPE xReturned, xInputIndex = 0;\r
\r
+ /* Just to avoid warnings about unused parameters. */\r
( void ) pvParameters;\r
\r
+ /* Initialise LPCUSB CDC driver. */\r
+ USB_Init( xVirtualCOMPort.Config.PortNumber, USB_MODE_Device );\r
+\r
/* Obtain the address of the output buffer. Note there is no mutual\r
exclusion on this buffer as it is assumed only one command console\r
interface will be used at any one time. */\r
- pcOutputString = FreeRTOS_CLIGetOutputBuffer();\r
-\r
- /* Initialise the virtual com port (CDC) interface. */\r
- prvSetupUSBDrivers();\r
+ pcOutputString = ( char * ) FreeRTOS_CLIGetOutputBuffer();\r
\r
/* Send the welcome message. This probably won't be seen as the console\r
- will not have been connected yet. */\r
- USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcWelcomeMessage, strlen( ( const char * ) pcWelcomeMessage ) );\r
+ will not have been connected yet (the console cannot be connected until the\r
+ virtual COM port has enumerated). */\r
+ CDC_Device_SendData( &xVirtualCOMPort, pcWelcomeMessage, strlen( ( const char * ) pcWelcomeMessage ) );\r
\r
for( ;; )\r
{\r
- /* No characters received yet for the current input string. */\r
- cRxedChar = 0;\r
+ /* Wait for new events to originate from the LPCUSB interrupts. */\r
+// xSemaphoreTake( xCDCEventSemaphore, 100 );\r
\r
- /* Only interested in reading one character at a time. */\r
- cRxedChar = cGetCDCChar();\r
+ /* LPCUSB function to process events latched by the USB interrupts. */\r
+ CDC_Device_USBTask( &xVirtualCOMPort );\r
+ USB_USBTask( xVirtualCOMPort.Config.PortNumber, USB_MODE_Device );\r
\r
+ /* Ensure no other tasks are using the COM port. */\r
if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )\r
{\r
- /* Echo the character back. */\r
- USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) &cRxedChar, sizeof( uint8_t ) );\r
-\r
- /* Was it the end of the line? */\r
- if( cRxedChar == '\n' || cRxedChar == '\r' )\r
+ /* Have any characters been received? */\r
+ if( CDC_Device_BytesReceived( &xVirtualCOMPort ) != 0 )\r
{\r
- /* Just to space the output from the input. */\r
- USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcNewLine, strlen( ( const char * ) pcNewLine ) );\r
+ /* Only interested in reading one character at a time. */\r
+ cRxedChar = CDC_Device_ReceiveByte( &xVirtualCOMPort );\r
\r
- /* See if the command is empty, indicating that the last command is\r
- to be executed again. */\r
- if( cInputIndex == 0 )\r
- {\r
- /* Copy the last command back into the input string. */\r
- strcpy( ( char * ) cInputString, ( char * ) cLastInputString );\r
- }\r
+ /* Echo the character back. */\r
+ CDC_Device_SendData( &xVirtualCOMPort, &cRxedChar, sizeof( uint8_t ) );\r
\r
- /* Pass the received command to the command interpreter. The\r
- command interpreter is called repeatedly until it returns pdFALSE\r
- (indicating there is no more output) as it might generate more than\r
- one string. */\r
- do\r
+ /* Was it an end of line character? */\r
+ if( cRxedChar == '\n' || cRxedChar == '\r' )\r
{\r
- /* Get the next output string from the command interpreter. */\r
- xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );\r
+ /* Just to space the output from the input. */\r
+ CDC_Device_SendData( &xVirtualCOMPort, pcNewLine, strlen( ( const char * ) pcNewLine ) );\r
\r
- /* Write the generated string to the CDC. */\r
- USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcOutputString, strlen( ( const char * ) pcOutputString ) );\r
- vTaskDelay( 1 );\r
+ /* See if the command is empty, indicating that the last\r
+ command is to be executed again. */\r
+ if( xInputIndex == 0 )\r
+ {\r
+ /* Copy the last command back into the input string. */\r
+ strcpy( ( char * ) cInputString, ( char * ) cLastInputString );\r
+ }\r
\r
- } while( xReturned != pdFALSE );\r
+ /* Pass the received command to the command interpreter.\r
+ The command interpreter is called repeatedly until it\r
+ returns pdFALSE (indicating there is no more output) as it\r
+ might generate more than one string. */\r
+ do\r
+ {\r
+ /* Get the next output string from the command\r
+ interpreter. */\r
+ xReturned = FreeRTOS_CLIProcessCommand( ( const int8_t * const ) cInputString, ( int8_t * ) pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );\r
\r
- /* All the strings generated by the input command have been sent.\r
- Clear the input string ready to receive the next command. Remember\r
- the command that was just processed first in case it is to be\r
- processed again. */\r
- strcpy( ( char * ) cLastInputString, ( char * ) cInputString );\r
- cInputIndex = 0;\r
- memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );\r
+ /* Write the generated string to the CDC. */\r
+ CDC_Device_SendData( &xVirtualCOMPort, pcOutputString, strlen( ( const char * ) pcOutputString ) );\r
\r
- USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcEndOfOutputMessage, strlen( ( const char * ) pcEndOfOutputMessage ) );\r
- }\r
- else\r
- {\r
- if( cRxedChar == '\r' )\r
- {\r
- /* Ignore the character. */\r
+ } while( xReturned != pdFALSE );\r
+\r
+ /* All the strings generated by the input command have been\r
+ sent. Clear the input string ready to receive the next\r
+ command. Remember the command that was just processed first\r
+ in case it is to be processed again. */\r
+ strcpy( ( char * ) cLastInputString, ( char * ) cInputString );\r
+ xInputIndex = 0;\r
+ memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );\r
+\r
+ CDC_Device_SendData( &xVirtualCOMPort, pcEndOfOutputMessage, strlen( ( const char * ) pcEndOfOutputMessage ) );\r
}\r
- else if( cRxedChar == '\b' )\r
+ else\r
{\r
- /* Backspace was pressed. Erase the last character in the\r
- string - if any. */\r
- if( cInputIndex > 0 )\r
+ if( cRxedChar == '\r' )\r
{\r
- cInputIndex--;\r
- cInputString[ cInputIndex ] = '\0';\r
+ /* Ignore the character. */\r
}\r
- }\r
- else\r
- {\r
- /* A character was entered. Add it to the string\r
- entered so far. When a \n is entered the complete\r
- string will be passed to the command interpreter. */\r
- if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )\r
+ else if( cRxedChar == '\b' )\r
{\r
- if( cInputIndex < cmdMAX_INPUT_SIZE )\r
+ /* Backspace was pressed. Erase the last character in\r
+ thestring - if any. */\r
+ if( xInputIndex > 0 )\r
{\r
- cInputString[ cInputIndex ] = cRxedChar;\r
- cInputIndex++;\r
+ xInputIndex--;\r
+ cInputString[ xInputIndex ] = '\0';\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* A character was entered. Add it to the string\r
+ entered so far. When a \n is entered the complete\r
+ string will be passed to the command interpreter. */\r
+ if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )\r
+ {\r
+ if( xInputIndex < cmdMAX_INPUT_SIZE )\r
+ {\r
+ cInputString[ xInputIndex ] = cRxedChar;\r
+ xInputIndex++;\r
+ }\r
}\r
}\r
}\r
{\r
if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )\r
{\r
- USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pucMessage, strlen( ( const char * ) pucMessage ) );\r
+ CDC_Device_SendData( &xVirtualCOMPort, ( const char * const ) pucMessage, strlen( ( const char * ) pucMessage ) );\r
xSemaphoreGive( xCDCMutex );\r
}\r
}\r
/*-----------------------------------------------------------*/\r
\r
-int8_t cGetCDCChar( void )\r
+static void prvNotifyTaskOfUSBEvent( void )\r
{\r
-int32_t lAvailableBytes, xBytes = 0;\r
-int8_t cInputChar;\r
-\r
- do\r
- {\r
- /* Are there any characters already available? */\r
- CDC_OutBufAvailChar( &lAvailableBytes );\r
- if( lAvailableBytes > 0 )\r
- {\r
- if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )\r
- {\r
- /* Attempt to read one character. */\r
- xBytes = 1;\r
- xBytes = CDC_RdOutBuf( ( char * ) &cInputChar, &xBytes );\r
-\r
- xSemaphoreGive( xCDCMutex );\r
- }\r
- }\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
\r
- if( xBytes == 0 )\r
- {\r
- /* A character was not available. Wait until signalled by the\r
- CDC Rx callback function that new data has arrived. */\r
- xSemaphoreTake( xNewDataSemaphore, portMAX_DELAY );\r
- }\r
+ /* 'Give' the semaphore that signals the arrival of new data to the command\r
+ console task. */\r
+ configASSERT( xCDCEventSemaphore );\r
+ xSemaphoreGiveFromISR( xCDCEventSemaphore, &xHigherPriorityTaskWoken );\r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
- } while( xBytes == 0 );\r
+/* Standard LPCUSB event handler. */\r
+void EVENT_USB_Device_ConfigurationChanged( void )\r
+{\r
+ CDC_Device_ConfigureEndpoints( &xVirtualCOMPort );\r
+ prvNotifyTaskOfUSBEvent();\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
- return cInputChar;\r
+/* Standard LPCUSB event handler. */\r
+void EVENT_USB_Device_ControlRequest( void )\r
+{\r
+ CDC_Device_ProcessControlRequest( &xVirtualCOMPort );\r
+ prvNotifyTaskOfUSBEvent();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* Callback function executed by the USB interrupt when new data arrives. */\r
-void vCDCNewDataNotify( void )\r
+/* Standard LPCUSB event handler. */\r
+void EVENT_USB_Device_Connect(void)\r
{\r
-portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ prvNotifyTaskOfUSBEvent();\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
- configASSERT( xNewDataSemaphore );\r
+/* Standard LPCUSB event handler. */\r
+void EVENT_USB_Device_Disconnect(void)\r
+{\r
+ prvNotifyTaskOfUSBEvent();\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
- /* 'Give' the semaphore that signals the arrival of new data to the command\r
- console task. */\r
- xSemaphoreGiveFromISR( xNewDataSemaphore, &xHigherPriorityTaskWoken );\r
- portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+/* Standard LPCUSB event handler. */\r
+void EVENT_CDC_Device_LineEncodingChanged(USB_ClassInfo_CDC_Device_t *const CDCInterfaceInfo)\r
+{\r
+ prvNotifyTaskOfUSBEvent();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvSetupUSBDrivers( void )\r
+/* Standard LPCUSB event handler. */\r
+void EVENT_CDC_Device_ControLineStateChanged(USB_ClassInfo_CDC_Device_t *const CDCInterfaceInfo)\r
{\r
-LPC_USBDRV_INIT_T xUSBCallback;\r
-\r
- /* Initialise the callback structure. */\r
- memset( ( void * ) &xUSBCallback, 0, sizeof( LPC_USBDRV_INIT_T ) );\r
- xUSBCallback.USB_Reset_Event = USB_Reset_Event;\r
- xUSBCallback.USB_P_EP[ 0 ] = USB_EndPoint0;\r
- xUSBCallback.USB_P_EP[ 1 ] = USB_EndPoint1;\r
- xUSBCallback.USB_P_EP[ 2 ] = USB_EndPoint2;\r
- xUSBCallback.ep0_maxp = USB_MAX_PACKET0;\r
-\r
- /* Initialise then connect the USB. */\r
- USB_Init( &xUSBCallback );\r
- USB_Connect( pdTRUE );\r
+ prvNotifyTaskOfUSBEvent();\r
}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+\r
+ >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+ details. You should have received a copy of the GNU General Public License\r
+ and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
+ viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+ writing to Real Time Engineers Ltd., contact details for whom are available\r
+ on the FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+ fully thread aware and reentrant UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
+ indemnification and middleware, under the OpenRTOS brand.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+*/\r
+\r
+#ifndef CDC_COMMAND_CONSOLE_H\r
+#define CDC_COMMAND_CONSOLE_H\r
+\r
+/*\r
+ * Create the task that implements a command console using the USB virtual com\r
+ * port driver for intput and output.\r
+ */\r
+void vCDCCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority );\r
+\r
+#endif /* CDC_COMMAND_CONSOLE_H */\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Device Descriptors, for library use when in USB device mode. Descriptors are special\r
+ * computer-readable structures which the host requests upon device enumeration, to determine\r
+ * the device's capabilities and functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "Descriptors.h"\r
+\r
+/* On some devices, there is a factory set internal serial number which can be automatically sent to the host as\r
+ * the device's serial number when the Device Descriptor's .SerialNumStrIndex entry is set to USE_INTERNAL_SERIAL.\r
+ * This allows the host to track a device across insertions on different ports, allowing them to retain allocated\r
+ * resources like COM port numbers and drivers. On demos using this feature, give a warning on unsupported devices\r
+ * so that the user can supply their own serial number descriptor instead or remove the USE_INTERNAL_SERIAL value\r
+ * from the Device Descriptor (forcing the host to generate a serial number for each device from the VID, PID and\r
+ * port location).\r
+ */\r
+\r
+/*****************************************************************************\r
+ * Private types/enumerations/variables\r
+ ****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Public types/enumerations/variables\r
+ ****************************************************************************/\r
+\r
+/** Device descriptor structure. This descriptor, located in FLASH memory, describes the overall\r
+ * device characteristics, including the supported USB version, control endpoint size and the\r
+ * number of device configurations. The descriptor is read out by the USB host when the enumeration\r
+ * process begins.\r
+ */\r
+USB_Descriptor_Device_t DeviceDescriptor = {\r
+ .Header = {.Size = sizeof(USB_Descriptor_Device_t), .Type = DTYPE_Device},\r
+\r
+ .USBSpecification = VERSION_BCD(01.10),\r
+ .Class = CDC_CSCP_CDCClass,\r
+ .SubClass = CDC_CSCP_NoSpecificSubclass,\r
+ .Protocol = CDC_CSCP_NoSpecificProtocol,\r
+\r
+ .Endpoint0Size = FIXED_CONTROL_ENDPOINT_SIZE,\r
+\r
+ .VendorID = 0x1fc9, /* NXP */\r
+ .ProductID = 0x2047,\r
+ .ReleaseNumber = VERSION_BCD(00.01),\r
+\r
+ .ManufacturerStrIndex = 0x01,\r
+ .ProductStrIndex = 0x02,\r
+ .SerialNumStrIndex = USE_INTERNAL_SERIAL,\r
+\r
+ .NumberOfConfigurations = FIXED_NUM_CONFIGURATIONS\r
+};\r
+\r
+/** Configuration descriptor structure. This descriptor, located in FLASH memory, describes the usage\r
+ * of the device in one of its supported configurations, including information about any device interfaces\r
+ * and endpoints. The descriptor is read out by the USB host during the enumeration process when selecting\r
+ * a configuration so that the host may correctly communicate with the USB device.\r
+ */\r
+USB_Descriptor_Configuration_t ConfigurationDescriptor = {\r
+ .Config = {\r
+ .Header = {.Size = sizeof(USB_Descriptor_Configuration_Header_t), .Type = DTYPE_Configuration},\r
+\r
+ .TotalConfigurationSize = sizeof(USB_Descriptor_Configuration_t) - 1, // termination byte not included in size\r
+ .TotalInterfaces = 2,\r
+\r
+ .ConfigurationNumber = 1,\r
+ .ConfigurationStrIndex = NO_DESCRIPTOR,\r
+\r
+ .ConfigAttributes = (USB_CONFIG_ATTR_BUSPOWERED | USB_CONFIG_ATTR_SELFPOWERED),\r
+\r
+ .MaxPowerConsumption = USB_CONFIG_POWER_MA(100)\r
+ },\r
+\r
+ .CDC_CCI_Interface = {\r
+ .Header = {.Size = sizeof(USB_Descriptor_Interface_t), .Type = DTYPE_Interface},\r
+\r
+ .InterfaceNumber = 0,\r
+ .AlternateSetting = 0,\r
+\r
+ .TotalEndpoints = 1,\r
+\r
+ .Class = CDC_CSCP_CDCClass,\r
+ .SubClass = CDC_CSCP_ACMSubclass,\r
+ .Protocol = CDC_CSCP_ATCommandProtocol,\r
+\r
+ .InterfaceStrIndex = NO_DESCRIPTOR\r
+ },\r
+\r
+ .CDC_Functional_Header = {\r
+ .Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalHeader_t), .Type = DTYPE_CSInterface},\r
+ .Subtype = CDC_DSUBTYPE_CSInterface_Header,\r
+\r
+ .CDCSpecification = VERSION_BCD(01.10),\r
+ },\r
+\r
+ .CDC_Functional_ACM = {\r
+ .Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalACM_t), .Type = DTYPE_CSInterface},\r
+ .Subtype = CDC_DSUBTYPE_CSInterface_ACM,\r
+\r
+ .Capabilities = 0x06,\r
+ },\r
+\r
+ .CDC_Functional_Union = {\r
+ .Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalUnion_t), .Type = DTYPE_CSInterface},\r
+ .Subtype = CDC_DSUBTYPE_CSInterface_Union,\r
+\r
+ .MasterInterfaceNumber = 0,\r
+ .SlaveInterfaceNumber = 1,\r
+ },\r
+\r
+ .CDC_NotificationEndpoint = {\r
+ .Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},\r
+\r
+ // .EndpointAddress = (ENDPOINT_DESCRIPTOR_DIR_IN | CDC_NOTIFICATION_EPNUM),\r
+ .EndpointAddress = (ENDPOINT_DIR_IN | CDC_NOTIFICATION_EPNUM),\r
+ .Attributes = (EP_TYPE_INTERRUPT | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),\r
+ .EndpointSize = CDC_NOTIFICATION_EPSIZE,\r
+ .PollingIntervalMS = 0xFF\r
+ },\r
+\r
+ .CDC_DCI_Interface = {\r
+ .Header = {.Size = sizeof(USB_Descriptor_Interface_t), .Type = DTYPE_Interface},\r
+\r
+ .InterfaceNumber = 1,\r
+ .AlternateSetting = 0,\r
+\r
+ .TotalEndpoints = 2,\r
+\r
+ .Class = CDC_CSCP_CDCDataClass,\r
+ .SubClass = CDC_CSCP_NoDataSubclass,\r
+ .Protocol = CDC_CSCP_NoDataProtocol,\r
+\r
+ .InterfaceStrIndex = NO_DESCRIPTOR\r
+ },\r
+\r
+ .CDC_DataOutEndpoint = {\r
+ .Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},\r
+\r
+ // .EndpointAddress = (ENDPOINT_DESCRIPTOR_DIR_OUT | CDC_RX_EPNUM),\r
+ .EndpointAddress = (ENDPOINT_DIR_OUT | CDC_RX_EPNUM),\r
+ .Attributes = (EP_TYPE_BULK | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),\r
+ .EndpointSize = CDC_TXRX_EPSIZE,\r
+ .PollingIntervalMS = 0x01\r
+ },\r
+\r
+ .CDC_DataInEndpoint = {\r
+ .Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},\r
+\r
+ // .EndpointAddress = (ENDPOINT_DESCRIPTOR_DIR_IN | CDC_TX_EPNUM),\r
+ .EndpointAddress = (ENDPOINT_DIR_IN | CDC_TX_EPNUM),\r
+ .Attributes = (EP_TYPE_BULK | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),\r
+ .EndpointSize = CDC_TXRX_EPSIZE,\r
+ .PollingIntervalMS = 0x01\r
+ },\r
+ .CDC_Termination = 0x00\r
+};\r
+\r
+/** Language descriptor structure. This descriptor, located in FLASH memory, is returned when the host requests\r
+ * the string descriptor with index 0 (the first index). It is actually an array of 16-bit integers, which indicate\r
+ * via the language ID table available at USB.org what languages the device supports for its string descriptors.\r
+ */\r
+uint8_t LanguageString[] = {\r
+ USB_STRING_LEN(1),\r
+ DTYPE_String,\r
+ WBVAL(LANGUAGE_ID_ENG),\r
+};\r
+USB_Descriptor_String_t *LanguageStringPtr = (USB_Descriptor_String_t *) LanguageString;\r
+\r
+/** Manufacturer descriptor string. This is a Unicode string containing the manufacturer's details in human readable\r
+ * form, and is read out upon request by the host when the appropriate string ID is requested, listed in the Device\r
+ * Descriptor.\r
+ */\r
+uint8_t ManufacturerString[] = {\r
+ USB_STRING_LEN(3),\r
+ DTYPE_String,\r
+ WBVAL('N'),\r
+ WBVAL('X'),\r
+ WBVAL('P'),\r
+};\r
+USB_Descriptor_String_t *ManufacturerStringPtr = (USB_Descriptor_String_t *) ManufacturerString;\r
+\r
+/** Product descriptor string. This is a Unicode string containing the product's details in human readable form,\r
+ * and is read out upon request by the host when the appropriate string ID is requested, listed in the Device\r
+ * Descriptor.\r
+ */\r
+uint8_t ProductString[] = {\r
+ USB_STRING_LEN(18),\r
+ DTYPE_String,\r
+ WBVAL('L'),\r
+ WBVAL('P'),\r
+ WBVAL('C'),\r
+ WBVAL('U'),\r
+ WBVAL('S'),\r
+ WBVAL('B'),\r
+ WBVAL('l'),\r
+ WBVAL('i'),\r
+ WBVAL('b'),\r
+ WBVAL(' '),\r
+ WBVAL('C'),\r
+ WBVAL('D'),\r
+ WBVAL('C'),\r
+ WBVAL(' '),\r
+ WBVAL('D'),\r
+ WBVAL('e'),\r
+ WBVAL('m'),\r
+ WBVAL('o'),\r
+};\r
+USB_Descriptor_String_t *ProductStringPtr = (USB_Descriptor_String_t *) ProductString;\r
+\r
+/*****************************************************************************\r
+ * Private functions\r
+ ****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Public functions\r
+ ****************************************************************************/\r
+\r
+/** This function is called by the library when in device mode, and must be overridden (see library "USB Descriptors"\r
+ * documentation) by the application code so that the address and size of a requested descriptor can be given\r
+ * to the USB library. When the device receives a Get Descriptor request on the control endpoint, this function\r
+ * is called so that the descriptor details can be passed back and the appropriate descriptor sent back to the\r
+ * USB host.\r
+ */\r
+uint16_t CALLBACK_USB_GetDescriptor(uint8_t corenum,\r
+ const uint16_t wValue,\r
+ const uint8_t wIndex,\r
+ const void * *const DescriptorAddress)\r
+{\r
+ const uint8_t DescriptorType = (wValue >> 8);\r
+ const uint8_t DescriptorNumber = (wValue & 0xFF);\r
+\r
+ const void *Address = NULL;\r
+ uint16_t Size = NO_DESCRIPTOR;\r
+\r
+ switch (DescriptorType) {\r
+ case DTYPE_Device:\r
+ Address = &DeviceDescriptor;\r
+ Size = sizeof(USB_Descriptor_Device_t);\r
+ break;\r
+\r
+ case DTYPE_Configuration:\r
+ Address = &ConfigurationDescriptor;\r
+ Size = sizeof(USB_Descriptor_Configuration_t);\r
+ break;\r
+\r
+ case DTYPE_String:\r
+ switch (DescriptorNumber) {\r
+ case 0x00:\r
+ Address = LanguageStringPtr;\r
+ Size = pgm_read_byte(&LanguageStringPtr->Header.Size);\r
+ break;\r
+\r
+ case 0x01:\r
+ Address = ManufacturerStringPtr;\r
+ Size = pgm_read_byte(&ManufacturerStringPtr->Header.Size);\r
+ break;\r
+\r
+ case 0x02:\r
+ Address = ProductStringPtr;\r
+ Size = pgm_read_byte(&ProductStringPtr->Header.Size);\r
+ break;\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ *DescriptorAddress = Address;\r
+ return Size;\r
+}\r
--- /dev/null
+/*\r
+ * @brief Virtual Serial device class declarations, definitions for using in application\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __DESCRIPTORS_H_\r
+#define __DESCRIPTORS_H_\r
+\r
+#include "USB.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup Virtual_Serial_Device_Descriptor Class descriptors\r
+ * @ingroup USB_Virtual_Serial_Device_18xx43xx USB_Virtual_Serial_Device_17xx40xx USB_Virtual_Serial_Device_11Uxx\r
+ * @{\r
+ */\r
+\r
+/** Endpoint number of the CDC device-to-host notification IN endpoint. */\r
+#define CDC_NOTIFICATION_EPNUM 1\r
+\r
+/** Endpoint number of the CDC device-to-host data IN endpoint. */\r
+#define CDC_TX_EPNUM 2\r
+\r
+/** Endpoint number of the CDC host-to-device data OUT endpoint. */\r
+#if defined(__LPC175X_6X__) || defined(__LPC177X_8X__) || defined(__LPC407X_8X__)\r
+ #define CDC_RX_EPNUM 5\r
+#else\r
+ #define CDC_RX_EPNUM 3\r
+#endif\r
+\r
+/** Size in bytes of the CDC device-to-host notification IN endpoint. */\r
+#define CDC_NOTIFICATION_EPSIZE 8\r
+\r
+/** Size in bytes of the CDC data IN and OUT endpoints. */\r
+#define CDC_TXRX_EPSIZE 16\r
+\r
+/** @brief Type define for the device configuration descriptor structure. This must be defined in the\r
+ * application code, as the configuration descriptor contains several sub-descriptors which\r
+ * vary between devices, and which describe the device's usage to the host.\r
+ */\r
+typedef struct {\r
+ USB_Descriptor_Configuration_Header_t Config;\r
+ USB_Descriptor_Interface_t CDC_CCI_Interface;\r
+ USB_CDC_Descriptor_FunctionalHeader_t CDC_Functional_Header;\r
+ USB_CDC_Descriptor_FunctionalACM_t CDC_Functional_ACM;\r
+ USB_CDC_Descriptor_FunctionalUnion_t CDC_Functional_Union;\r
+ USB_Descriptor_Endpoint_t CDC_NotificationEndpoint;\r
+ USB_Descriptor_Interface_t CDC_DCI_Interface;\r
+ USB_Descriptor_Endpoint_t CDC_DataOutEndpoint;\r
+ USB_Descriptor_Endpoint_t CDC_DataInEndpoint;\r
+ unsigned char CDC_Termination;\r
+} USB_Descriptor_Configuration_t;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __DESCRIPTORS_H_ */\r
--- /dev/null
+;************************************************************\r
+; Windows USB CDC ACM Setup File\r
+; Copyright (c) 2000 Microsoft Corporation\r
+\r
+\r
+[Version]\r
+Signature="$Windows NT$"\r
+Class=Ports\r
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}\r
+Provider=%MFGNAME%\r
+LayoutFile=layout.inf\r
+CatalogFile=%MFGFILENAME%.cat\r
+DriverVer=11/15/2007,5.1.2600.0\r
+\r
+[Manufacturer]\r
+%MFGNAME%=DeviceList, NTamd64\r
+\r
+[DestinationDirs]\r
+DefaultDestDir=12\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+; Windows 2000/XP/Vista-32bit Sections\r
+;------------------------------------------------------------------------------\r
+\r
+[DriverInstall.nt]\r
+include=mdmcpq.inf\r
+CopyFiles=DriverCopyFiles.nt\r
+AddReg=DriverInstall.nt.AddReg\r
+\r
+[DriverCopyFiles.nt]\r
+usbser.sys,,,0x20\r
+\r
+[DriverInstall.nt.AddReg]\r
+HKR,,DevLoader,,*ntkern\r
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys\r
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"\r
+\r
+[DriverInstall.nt.Services]\r
+AddService=usbser, 0x00000002, DriverService.nt\r
+\r
+[DriverService.nt]\r
+DisplayName=%SERVICE%\r
+ServiceType=1\r
+StartType=3\r
+ErrorControl=1\r
+ServiceBinary=%12%\%DRIVERFILENAME%.sys\r
+\r
+;------------------------------------------------------------------------------\r
+; Vista-64bit Sections\r
+;------------------------------------------------------------------------------\r
+\r
+[DriverInstall.NTamd64]\r
+include=mdmcpq.inf\r
+CopyFiles=DriverCopyFiles.NTamd64\r
+AddReg=DriverInstall.NTamd64.AddReg\r
+\r
+[DriverCopyFiles.NTamd64]\r
+%DRIVERFILENAME%.sys,,,0x20\r
+\r
+[DriverInstall.NTamd64.AddReg]\r
+HKR,,DevLoader,,*ntkern\r
+HKR,,NTMPDriver,,%DRIVERFILENAME%.sys\r
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"\r
+\r
+[DriverInstall.NTamd64.Services]\r
+AddService=usbser, 0x00000002, DriverService.NTamd64\r
+\r
+[DriverService.NTamd64]\r
+DisplayName=%SERVICE%\r
+ServiceType=1\r
+StartType=3\r
+ErrorControl=1\r
+ServiceBinary=%12%\%DRIVERFILENAME%.sys\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+; Vendor and Product ID Definitions\r
+;------------------------------------------------------------------------------\r
+; When developing your USB device, the VID and PID used in the PC side\r
+; application program and the firmware on the microcontroller must match.\r
+; Modify the below line to use your VID and PID. Use the format as shown below.\r
+; Note: One INF file can be used for multiple devices with different VID and PIDs.\r
+; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line.\r
+;------------------------------------------------------------------------------\r
+[SourceDisksFiles]\r
+[SourceDisksNames]\r
+[DeviceList]\r
+%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_2047\r
+\r
+[DeviceList.NTamd64]\r
+%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_2047\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+; String Definitions\r
+;------------------------------------------------------------------------------\r
+;Modify these strings to customize your device\r
+;------------------------------------------------------------------------------\r
+[Strings]\r
+MFGFILENAME="CDC_vista"\r
+DRIVERFILENAME ="usbser"\r
+MFGNAME="http://www.lpcware.com/content/project/nxpusblib"\r
+INSTDISK="nxpUSBlib CDC Driver Installer"\r
+DESCRIPTION="Communications Port"\r
+SERVICE="USB RS-232 Emulation Driver"
\ No newline at end of file
+++ /dev/null
-/*\r
- FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
-\r
- >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
- details. You should have received a copy of the GNU General Public License\r
- and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
- viewed here: http://www.freertos.org/a00114.html and also obtained by\r
- writing to Real Time Engineers Ltd., contact details for whom are available\r
- on the FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
- fully thread aware and reentrant UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems, who sell the code with commercial support,\r
- indemnification and middleware, under the OpenRTOS brand.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-*/\r
-\r
-#ifndef CDC_COMMAND_CONSOLE_H\r
-#define CDC_COMMAND_CONSOLE_H\r
-\r
-/*\r
- * Create the task that implements a command console using the USB virtual com\r
- * port driver for intput and output.\r
- */\r
-void vCDCCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority );\r
-\r
-#endif /* CDC_COMMAND_CONSOLE_H */\r
-\r
-\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
-\r
- >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
- details. You should have received a copy of the GNU General Public License\r
- and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
- viewed here: http://www.freertos.org/a00114.html and also obtained by\r
- writing to Real Time Engineers Ltd., contact details for whom are available\r
- on the FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
- fully thread aware and reentrant UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
- indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
- mission critical applications that require provable dependability.\r
-*/\r
-\r
-/*\r
- * This file, along with DemoIPTrace.h, provides a basic example use of the\r
- * FreeRTOS+UDP trace macros. The statistics gathered here can be viewed in\r
- * the command line interface.\r
- * See http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml\r
- */\r
-\r
-#ifndef DEMO_IP_TRACE_MACROS_H\r
-#define DEMO_IP_TRACE_MACROS_H\r
-\r
-typedef void ( *vTraceAction_t )( uint32_t *, uint32_t );\r
-\r
-/* Type that defines each statistic being gathered. */\r
-typedef struct ExampleDebugStatEntry\r
-{\r
- uint8_t ucIdentifier; /* Unique identifier for statistic. */\r
- const uint8_t * const pucDescription; /* Text description for the statistic. */\r
- vTraceAction_t vPerformAction; /* Action to perform when the statistic is updated (increment counter, store minimum value, store maximum value, etc. */\r
- uint32_t ulData; /* The meaning of this data is dependent on the trace macro ID. */\r
-} xExampleDebugStatEntry_t;\r
-\r
-/* Unique identifiers used to locate the entry for each trace macro in the\r
-xIPTraceValues[] table defined in DemoIPTrace.c. */\r
-#define iptraceID_NETWORK_BUFFER_OBTAINED 1\r
-#define iptraceID_NETWORK_BUFFER_OBTAINED_FROM_ISR 2\r
-#define iptraceID_NETWORK_EVENT_RECEIVED 3\r
-#define iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER 4\r
-#define iptraceID_ARP_TABLE_ENTRY_EXPIRED 5\r
-#define iptraceID_PACKET_DROPPED_TO_GENERATE_ARP 6\r
-#define iptraceID_FAILED_TO_CREATE_SOCKET 7\r
-#define iptraceID_RECVFROM_DISCARDING_BYTES 8\r
-#define iptraceID_ETHERNET_RX_EVENT_LOST 9\r
-#define iptraceID_STACK_TX_EVENT_LOST 10\r
-#define ipconfigID_BIND_FAILED 11\r
-#define iptraceID_NETWORK_INTERFACE_TRANSMIT 12\r
-#define iptraceID_RECVFROM_TIMEOUT 13\r
-#define iptraceID_SENDTO_DATA_TOO_LONG 14\r
-#define iptraceID_SENDTO_SOCKET_NOT_BOUND 15\r
-#define iptraceID_NO_BUFFER_FOR_SENDTO 16\r
-#define iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR 17\r
-#define iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP 18\r
-\r
-/* It is possible to remove the trace macros using the\r
-configINCLUDE_DEMO_DEBUG_STATS setting in FreeRTOSIPConfig.h. */\r
-#if configINCLUDE_DEMO_DEBUG_STATS == 1\r
-\r
- /* The trace macro definitions themselves. Any trace macros left undefined\r
- will default to be empty macros. */\r
- #define iptraceNETWORK_BUFFER_OBTAINED( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) )\r
- #define iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) )\r
-\r
- #define iptraceNETWORK_EVENT_RECEIVED( eEvent ) { \\r
- uint16_t usSpace; \\r
- usSpace = ( uint16_t ) uxQueueMessagesWaiting( xNetworkEventQueue ); \\r
- /* Minus one as an event was removed before the space was queried. */ \\r
- usSpace = ( ipconfigEVENT_QUEUE_LENGTH - usSpace ) - 1; \\r
- vExampleDebugStatUpdate( iptraceID_NETWORK_EVENT_RECEIVED, usSpace ); \\r
- }\r
-\r
- #define iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER() vExampleDebugStatUpdate( iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER, 0 )\r
- #define iptraceARP_TABLE_ENTRY_EXPIRED( ulIPAddress ) vExampleDebugStatUpdate( iptraceID_ARP_TABLE_ENTRY_EXPIRED, 0 )\r
- #define iptracePACKET_DROPPED_TO_GENERATE_ARP( ulIPAddress ) vExampleDebugStatUpdate( iptraceID_PACKET_DROPPED_TO_GENERATE_ARP, 0 )\r
- #define iptraceFAILED_TO_CREATE_SOCKET() vExampleDebugStatUpdate( iptraceID_FAILED_TO_CREATE_SOCKET, 0 )\r
- #define iptraceRECVFROM_DISCARDING_BYTES( xNumberOfBytesDiscarded ) vExampleDebugStatUpdate( iptraceID_RECVFROM_DISCARDING_BYTES, 0 )\r
- #define iptraceETHERNET_RX_EVENT_LOST() vExampleDebugStatUpdate( iptraceID_ETHERNET_RX_EVENT_LOST, 0 )\r
- #define iptraceSTACK_TX_EVENT_LOST( xEvent ) vExampleDebugStatUpdate( iptraceID_STACK_TX_EVENT_LOST, 0 )\r
- #define iptraceBIND_FAILED( xSocket, usPort ) vExampleDebugStatUpdate( ipconfigID_BIND_FAILED, 0 )\r
- #define iptraceNETWORK_INTERFACE_TRANSMIT() vExampleDebugStatUpdate( iptraceID_NETWORK_INTERFACE_TRANSMIT, 0 )\r
- #define iptraceRECVFROM_TIMEOUT() vExampleDebugStatUpdate( iptraceID_RECVFROM_TIMEOUT, 0 )\r
- #define iptraceSENDTO_DATA_TOO_LONG() vExampleDebugStatUpdate( iptraceID_SENDTO_DATA_TOO_LONG, 0 )\r
- #define iptraceSENDTO_SOCKET_NOT_BOUND() vExampleDebugStatUpdate( iptraceID_SENDTO_SOCKET_NOT_BOUND, 0 )\r
- #define iptraceNO_BUFFER_FOR_SENDTO() vExampleDebugStatUpdate( iptraceID_NO_BUFFER_FOR_SENDTO, 0 )\r
- #define iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() vExampleDebugStatUpdate( iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR, 0 )\r
- #define iptraceFAILED_TO_NOTIFY_SELECT_GROUP( xSocket ) vExampleDebugStatUpdate( iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP, 0 )\r
-\r
- /*\r
- * The function that updates a line in the xIPTraceValues table.\r
- */\r
- void vExampleDebugStatUpdate( uint8_t ucIdentifier, uint32_t ulValue );\r
-\r
- /*\r
- * Returns the number of entries in the xIPTraceValues table.\r
- */\r
- portBASE_TYPE xExampleDebugStatEntries( void );\r
-\r
-#endif /* configINCLUDE_DEMO_DEBUG_STATS == 1 */\r
-\r
-\r
-#endif /* DEMO_IP_TRACE_MACROS_H */\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
-\r
- >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
- details. You should have received a copy of the GNU General Public License\r
- and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
- viewed here: http://www.freertos.org/a00114.html and also obtained by\r
- writing to Real Time Engineers Ltd., contact details for whom are available\r
- on the FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
- fully thread aware and reentrant UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
- indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
- mission critical applications that require provable dependability.\r
-*/\r
-\r
-#ifndef TWO_ECHO_CLIENTS_H\r
-#define TWO_ECHO_CLIENTS_H\r
-\r
-/*\r
- * Create the two UDP echo client tasks. One task uses the standard interface\r
- * to send to and receive from an echo server. The other task uses the zero\r
- * copy interface to send to and receive from an echo server.\r
- */\r
-void vStartEchoClientTasks( uint16_t usTaskStackSize, unsigned portBASE_TYPE uxTaskPriority );\r
-\r
-#endif /* TWO_ECHO_CLIENTS_H */\r
\r
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
standard names. */\r
-#define vPortSVCHandler SVCall_Handler\r
+#define vPortSVCHandler SVC_Handler\r
#define xPortPendSVHandler PendSV_Handler\r
#define xPortSysTickHandler SysTick_Handler\r
\r
\r
/* The address of an echo server that will be used by the two demo echo client\r
tasks.\r
-http://localhost/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */\r
+http://FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */\r
#define configECHO_SERVER_ADDR0 172\r
#define configECHO_SERVER_ADDR1 25\r
#define configECHO_SERVER_ADDR2 218\r
-#define configECHO_SERVER_ADDR3 103\r
+#define configECHO_SERVER_ADDR3 100\r
\r
/* MAC address configuration. In a deployed production system this would\r
probably be read from an EEPROM. In the demo it is just hard coded. Make sure\r
\r
/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or\r
ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */\r
-#define configIP_ADDR0 192\r
-#define configIP_ADDR1 168\r
-#define configIP_ADDR2 1\r
-#define configIP_ADDR3 125\r
+#define configIP_ADDR0 172\r
+#define configIP_ADDR1 25\r
+#define configIP_ADDR2 218\r
+#define configIP_ADDR3 200\r
\r
/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to\r
0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */\r
#include "timers.h"\r
\r
/* Library includes. */\r
-#include "lpc18xx_gpio.h"\r
-#include "lpc18xx_scu.h"\r
-#include "lpc18xx_cgu.h"\r
+#include "board.h"\r
\r
#define ledTOGGLE_RATE ( 500 / portTICK_RATE_MS )\r
\r
{\r
static xTimerHandle xLEDToggleTimer = NULL;\r
\r
- /* Set the LED pin-muxing and configure as output. */\r
- scu_pinmux( 0x2 , 11, MD_PUP, FUNC0 );\r
- scu_pinmux( 0x2 , 12, MD_PUP, FUNC0 );\r
- GPIO_SetDir( ledLED0_PORT, ledLED0_BIT, 1 );\r
- GPIO_SetDir( ledLED1_PORT, ledLED1_BIT, 1 );\r
-\r
/* Create the timer used to toggle LED0. */\r
xLEDToggleTimer = xTimerCreate( ( const int8_t * ) "LEDTmr", /* Just a text name to associate with the timer, useful for debugging, but not used by the kernel. */\r
ledTOGGLE_RATE, /* The period of the timer. */\r
( void ) xTimer;\r
\r
/* Just toggle an LED to show the program is running. */\r
- if( ucState == 0 )\r
- {\r
- GPIO_SetValue( ledLED0_PORT, ledLED0_BIT );\r
- }\r
- else\r
- {\r
- GPIO_ClearValue( ledLED0_PORT, ledLED0_BIT );\r
- }\r
-\r
+ Board_LED_Set( ledLED0_PORT, ucState );\r
ucState = !ucState;\r
}\r
\r
--- /dev/null
+/*\r
+ * @brief LPCUSB library's configurations\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+ \r
+/** @defgroup USB_Config USB Configuration\r
+ * @ingroup LPCUSBlib\r
+* @{\r
+*/\r
+\r
+#ifndef LPCUSBLIB_CONFIG_H_\r
+#define LPCUSBLIB_CONFIG_H_\r
+\r
+/** Define NXPUSBLIB_DEBUG to allow the library prints out diagnostic messages */\r
+//#define NXPUSBLIB_DEBUG\r
+\r
+/** Available configuration number in a device */\r
+#define FIXED_NUM_CONFIGURATIONS 1\r
+\r
+/** Control endpoint max packet size */\r
+#define FIXED_CONTROL_ENDPOINT_SIZE 64\r
+\r
+//#define __TEST__ /* Test development */\r
+\r
+/** Size of share memory that a device uses to store data transfer to/ receive from host\r
+ * or a host uses to store data transfer to/ receive from device.\r
+ */\r
+#define USBRAM_BUFFER_SIZE (4*1024)\r
+\r
+/** This option effects only on high speed parts that need to test full speed activities */\r
+#define USB_FORCED_FULLSPEED 0\r
+\r
+/** Define USE_USB_ROM_STACK = 1 to use MCU's internal ROM stack, 0 if otherwise */\r
+#define USE_USB_ROM_STACK 0\r
+\r
+#endif /* NXPUSBLIB_CONFIG_H_ */\r
+\r
+/**\r
+* @}\r
+*/\r
--- /dev/null
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
--- /dev/null
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+ return(op1);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
+++ /dev/null
-CMSIS : Cortex Microcontroller Software Interface Standard\r
-==========================================================\r
-\r
-Introduction\r
-~~~~~~~~~~~~\r
-CMSIS defines for a Cortex-M Microcontroller System:\r
-\r
- * A common way to access peripheral registers and a \r
- common way to define exception vectors.\r
- * The register names of the Core Peripherals and the \r
- names of the Core Exception Vectors.\r
- * An device independent interface for RTOS Kernels \r
- including a debug channel.\r
-\r
-By using CMSIS compliant software components, the user can \r
-easier re-use template code. CMSIS is intended to enable the\r
-combination of software components from multiple middleware \r
-vendors. \r
-\r
-This project contains appropriate files for this MCU family \r
-taken from CMSIS. A full copy of the CMSIS files, together\r
-with additional information on CMSIS can be found at:\r
-\r
- http://www.onarm.com/\r
- http://www.arm.com/\r
-\r
-Documentation\r
-~~~~~~~~~~~~~\r
-The standard CMSIS documentation can be found within the\r
-Code Red IDE help system, via:\r
-\r
-Help -> Help Contents -> Code Red Product Documentation -> CMSIS\r
-\r
-More information on the use of CMSIS within the Code Red IDE\r
-can be found in the Support area of the Code Red website at\r
-\r
- http://www.code-red-tech.com/\r
-\r
-At the time of writing, the CMSIS FAQ can be found directly\r
-at:\r
-\r
- http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS\r
-\r
-\r
+++ /dev/null
-RELEASE CMSIS for REV A 20111209\r
-1/ New LPC18xx.h header file. Changes GPIO structure.\r
-2/ Addition of lpc18xx_emc.c and lpc18xx_emc.h to configure memory on Hitex board.\r
-3/ Addition of spifi_rom_api.h, spifi_drv_M3.lib and SPIFI_ROM_support.doc SPIFI driver package\r
-4/ Updated SPIFI programming driver for Keil MDK which uses the SPIFI lib\r
-5/ New BOOTFAST example shows how to boot from external flash or QSPI and ramp to 180 MHz\r
-\r
-RELEASE CMSIS for REV A 20111130\r
-1./ lpc18xx_lcd.h LCD_CFG_type add member pcd, lpc18xx_lcd.c add init pcd in LCD_Init function\r
-2./ protect MAX and MIN macro in lpc_types.h\r
-3./ Add getPC function to ARM,GNU, IAR startup_lpc18xx.s\r
-4./ Add VTOR init in SystemInit function\r
-5./ Change All ADC examples to use ADC port 0\r
-6./ These example: CortexM3_Mpu, Pwr_DeepPowerDown, Timer_FreqMeasure, SCT_SimpleMatch and all USBDEV_ROM examples Keil project was adjusted\r
-7./ SDRAM example and LCD example was changed not to use uint64_t in NS2CLK function\r
-8./ Nvic_VectorTableRelocation.c\r
-removed: \r
-#if __RAM_MODE__//Run in RAM mode\r
- memcpy((void *)VTOR_OFFSET, (const void *)0x10000000, 256*4);\r
-#else\r
- memcpy((void *)VTOR_OFFSET, (const void *)0x1C000000, 256*4);\r
-#endif\r
-\r
-added:\r
-memcpy((void *)VTOR_OFFSET, (const void *)(getPC()& 0xFF000000), 256*4);\r
-9./ Pwr_PowerDown change method for testing this feature\r
-\r
-\r
-RELEASE CMSIS for REV A 20111028\r
-1./ Add GNU support\r
-2./ Addition of new Keil flash drivers for eFlash and SPIFI\r
-3./ Change of Keil projects to support eFlash and SPIFI operation\r
-\r
-PRE-RELEASE CMSIS for REV A 20111011\r
-1/ PowerDown Example IAR issue fixed\r
-2/ Upgraded CMSIS to version 2.10\r
-3/ Upgraded Core header to Rev A\r
-4/ lpc18xx_can.h remove all bitrates from 8Mhz, add bitrates from 12Mhz\r
- /** Bitrate: 100K */\r
- #define CAN_BITRATE100K12MHZ 0x00004509\r
- /** Bitrate: 125K */\r
- #define CAN_BITRATE125K12MHZ 0x00004507\r
- /** Bitrate: 250K */\r
- #define CAN_BITRATE250K12MHZ 0x00004503\r
- /** Bitrate: 500K */\r
- #define CAN_BITRATE500K12MHZ 0x00004501\r
- /** Bitrate: 1000K */\r
- #define CAN_BITRATE1000K12MHZ 0x00004500\r
-5./ lpc18xx_cgu.* add PLL audio clock, modify alloc connect table and CGU_Entity_ControlReg_Offset\r
-6./ lpc18xx_evrt.h\r
- add EVRT_SRC_SDIO\r
-7./ lpc18xx_i2s.h separate LPC_I2S0 and LPC_I2S1\r
-8./ lpc18xx_scu.h\r
- redefine, add pin modes and add pin functions 4->7\r
-9./ debug_frmwrk.c\r
- changed pin mode for UART RXD0 and UART RXD1\r
-10./ lpc_can.c replace LPC_CAN by LPC_CAN0\r
-11./ lpc18xx_i2c.* replace i2c pin configurations\r
-12./ lpc18xx_ssp.c down default clock speed to 100kHz\r
-13./ Examples\CCAN\CCan_SimpleTxRx\CCan_SimpleTxRx.c change RD pin mode to enable input buffer\r
-14./ Examples\EMAC\Emac_EasyWeb\emac.c\r
- replace MII and RMII pin setting by source from CodeBundle\r
-15./ Examples\EMC\Emc_Sdram\SDRAM_Init.c and Examples\EMC\Emc_NorFlash\SST39VF320.c\r
- replace EMC pin setting to be compatible with Rev A\r
-16./ Examples\I2S\I2s_Audio\I2s_Audio.c\r
- replace I2S pin setting to be compatible with Rev A\r
- replace I2S to I2S0\r
-17./ Examples\LCD\Lcd_Demo\IS42S16400D.c\r
- replace EMC pin setting to be compatible with Rev A\r
-18./ Examples\SSP\All SSP examples: replace SSP pin setting to be compatible with Rev A\r
-19./ Timer_Capture and Timer_FreqMeasure: replace Capture input pin setting to be compatible with Rev A\r
-20./ Examples\UART\All UART examples: replace UART pin setting to be compatible with Rev A\r
-21./ Examples\USBDEV\USB_*\usbhw.c\r
- replace USB pin setting to be compatible with Rev A\r
- correct clock in Init function\r
-\r
-RELEASE: LPC1800CMSIS_20110829\r
-1./ Add GNU Support\r
-modify pasting in can.c to be compatible with GCC\r
-\r
-RELEASE: LPC1800CMSIS_20110729\r
-1./ IAR flash support is moved to Tools folder\r
-2./ ADC.h fixed macro ADC_CR_BITACC\r
-3./ I2S.h fixed comment\r
- from #endif /* LPC17XX_SSP_H_ */\r
- to #endif /* LPC18XX_I2S_H_ */\r
-4./ ADC.c fix ADC_Init Clock by rounding clk div value\r
-5./ i2s.c fixed some comment\r
-6./ EMC Nor Flash renamed file flash programing function\r
-7./ SDRAM can run at MAX EMC Speed\r
-8./ Removed flash programing support for LHF00L28\r
-\r
-RELEASE: LPC1800CMSIS_20110627\r
-1./ Fix abstract\r
-2./ Fix I2S FreqConfig mistake\r
-3./ Add DFU Driver and App\r
-\r
-\r
-RELEASE: LPC1800CMSIS_20110613\r
-1./ Add DSP Document\r
-2./ Speed Up External FLash Mode\r
-3./ Add IAR Flash Support\r
-4./ Fix GPDMA Flash transfer issue in IAR\r
-5./ Set default taget is EXFLASH(Keil only)\r
-\r
-************************************************************************************************************************************************\r
-RELEASE: LPC1800CMSIS_20110603\r
-1./ Add DSP_lib into Core folder\r
-2./ Update core_cmFunc.h and core_cmInstr.h for solving conflict with IAR EWARM version 6.20 or later\r
-3./ add IAR startup file and IAR support files in Core\DeviceSupport\NXP\LPC18xx\r
-4./ Modify SystemInit function to support RAM mode\r
- #if (__RAM_MODE__)\r
- SCB->VTOR = 0x10000000;\r
- #endif\r
-5./ Modify CCU1 and CCU2 struct in LPC18xx.h\r
-6./ Fix bug in uart_set_divisors function\r
-7./ Change UART clock source from XTAL to PLL1 in uart driver\r
-8./ Fix RTC bugs\r
-9./ Modify lpc18xx_GPDMA.c to support IAR compiler\r
-10./ Modify lpc18xx_cgu.c to support IAR compiler\r
-11./ Update lpc_types.h to support IAR compiler\r
-12./ Fix bugs in I2S driver\r
-13./ Remove Warnings\r
-14./ Change new header, add more comments\r
-15./ Standalize example, project, output names\r
-16./ Support IAR EWARM (RAM mode)\r
-17./ SUpport Hitex Board as default\r
-18./ Modify hardware configuration in abstract files\r
-19./ Set default Target to RAM mode\r
-\r
-************************************************************************************************************************************************\r
-RELEASE: LPC1800CMSIS_20110514\r
-1./ Change all Keil example projects from device Cortex M3 to LPC1850\r
-2./ change all examples to support Hitex board only\r
-3./ Verify all project option\r
-4./ separated CGU and PWR into 2 independent drivers\r
-\r
-************************************************************************************************************************************************\r
-RELEASE: LPC1800CMSIS_20110421\r
-1./ Add CAN driver:\r
- Drivers/include/lpc18xx_can.h\r
- Drivers/source/lpc18xx_can.c\r
-\r
-2./ Add CAN example for simple Transceiver\r
- Examples\C_CAN\simpleTxRx\r
-\r
-3./ Add 4 USB Rom examples:\r
- USB_DFU\r
- USB_HID\r
- USB_MassStorage\r
- USB_Composite\r
-\r
-4./ Enable _printf function\r
- debug_frmwrk.h:\r
- uncomment _printf function declaration\r
- debug_frmwrk.c:\r
- uncomment _printf function\r
-\r
-************************************************************************************************************************************************\r
-RELEASE: LPC1800CMSIS_20110401\r
-\r
-1./ Change all Keil example proiects from device NXP LPC1768 to ARM Cortex-M3\r
-\r
-2./ Fix bug in I2C driver (customer feedback)\r
- Problem description: \r
- I2C_MasterTransferData() is not able to \r
- (1) Send, \r
- (2) doing a repeated Start and \r
- (3) starting to receive with one function call. \r
- Problem is that the repeated start is not generated, but a retransmission of the \r
- last word is startet. \r
- Solve: change \r
- I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; \r
- I2Cx->I2CONSET = I2C_I2CONSET_STA; \r
- to \r
- I2Cx->I2CONSET = I2C_I2CONSET_STA; \r
- I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; \r
- in function I2C_Start ()\r
-\r
-3./ lpc18xx_timer.c:\r
- Function TIM_ClearIntPending():\r
- Change TIMx->IR |= TIM_IR_CLR(IntFlag);\r
- To TIMx->IR = TIM_IR_CLR(IntFlag);\r
- Function TIM_ClearIntCapturePending():\r
- Change TIMx->IR |= (1<<(4+IntFlag));\r
- To TIMx->IR = (1<<(4+IntFlag));\r
- Function TIM_GetCaptureValue(): \r
- Add return 0;\r
-\r
-4./ EMC - Nor Flash: remove example build target for FLASH mode as it only can run in RAM mode.\r
-\r
-5./ SCT: update Fizzim tool to version 1.1\r
-\r
-6./ Tools:\r
- Update Flash burning for LHF00L28 and SST39X320X\r
-\r
-************************************************************************************************************************************************\r
-\r
-RELEASE: LPC1800CMSIS_20110324\r
-\r
-1./ Current support hardwares:\r
- - NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA'\r
- - Hitex LPC1800 Board through definition 'BOARD_HITEX_LPC1800'\r
- Some examples can run on LPC1800 Evaluation board, some can run on Hitex board...Please refer to abstract.txt\r
-\r
-2./ Addin new flash support under Tools/Flash/SST39X320X\r
-\r
-3./ lpc18xx_evrt.c:\r
- Change EVRTx->SET_EN |= (1<<(uint8_t)EVRT_Src);\r
- To EVRTx->SET_EN = (1<<(uint8_t)EVRT_Src);\r
- Purpose: prevent clearing other set bits as writing '0' has no effect\r
-\r
-4./ Fix ATIMER_WIC example:\r
- - Configure 32KHZ osc in lpc18xx_atimer.c\r
- - Call the configuration function in atimer_wic.c\r
-\r
-5./ Fix RTC_Alarm example:\r
- - Configure 32KHZ osc in lpc18xx_rtc.c\r
- - Update Rtc_Alarm.c\r
-\r
-6./ Add in PWR_PowerDown example\r
-\r
-7./ Add in PWR_DeepPowerDown example\r
-\r
-8./ All example in PWR are modified to wait for '1' sent from PC's COM port to start\r
-\r
-9./ Fix LCD Logic4.3 example to run on Hitex LPC1800 Board\r
-\r
-10./ Add in GPDMA Flash_2_Ram_Test example\r
-\r
-11./ EMC EXT_SDRAM example: join IS42S16400D.c and MT48LC4M32B2.c into SDRAM_Init.c\r
-\r
-12./ lpc18xx_i2s.c: update I2S_FreqConfig() function\r
-\r
-************************************************************************************************************************************************\r
-\r
-RELEASE: LPC1800CMSIS_20110311\r
-\r
-1./ This package is compliant to CMSIS 2.0\r
-\r
-2./ Add in 'Tools' folder which contains neccessary material for building project, examples like flash burning,..\r
-\r
-3./ Examples are given in Keil uVision 4 project\r
-\r
-4./ Current support hardwares:\r
- - NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA'\r
-\r
-5./ Examples can run:\r
- - RAM (debug) mode\r
- - ROM (Flash, stand alone) mode\r
- + External Nor Flash. Flash Part supporting:\r
- 1) LHF00L28\r
-\r
-6./ Each example folder has an 'abstract.txt' file, this is where user can start\r
-\r
-7./ Below is list of drivers and examples:\r
- - ADC (lpc18xx_adc):\r
- + ADC_Interrupt\r
- + ADC_Polling\r
- + ADC_Burst\r
- + ADC_Dma\r
- - ATIMER (lpc18xx_atimer):\r
- + ATIMER_interrupt\r
- - PWR (lpc18xx_clkpwr):\r
- + CLKPWR_Sleep\r
- + CLKPWR_DeepSleep\r
- - DAC (lpc18xx_dac):\r
- + DAC_WaveGenerator\r
- + DAC_Dma\r
- - EMAC (lpc18xx_emac):\r
- + EMAC_EasyWeb\r
- - EMC (no driver):\r
- + EXT_SDRAM\r
- + NOR_FLASH\r
- - GPDMA (lpc18xx_gpdma):\r
- + GPDMA_Ram2Ram\r
- + GPDMA_LinkList\r
- - GPIO (lpc18xx_gpio):\r
- + GPIO_LedBlinky\r
- - I2C (lpc18xx_i2c):\r
- + I2C_Master\r
- - I2S (lpc18xx_i2s):\r
- + I2S_Audio\r
- - LCD (lpc18xx_lcd)\r
- - MCPWM (lpc18xx_mcpwm):\r
- + MCPWM_Simple\r
- - SCU (lpc18xx_scu)\r
- - QEI (lpc18xx_qei):\r
- + QEI_Velo\r
- - RIT (lpc18xx_rit):\r
- + RIT_Interrupt\r
- - RTC (lpc18xx_rtc):\r
- + RTC_Calib\r
- + RTC_Alarm\r
- - SSP (lpc18xx_ssp):\r
- + SSP_SPI\r
- + SSP_Microwire\r
- + SSP_TI\r
- - TIMER (lpc18xx_timer):\r
- + TIMER_Capture\r
- + TIMER_MatchInterrupt\r
- + TIMER_FreqMeasure\r
- - UART (lpc18xx_uart):\r
- + UART_Autobaud\r
- + UART_Dma\r
- + UART_Interrupt\r
- + UART_Polling\r
- + UART_RS485\r
- - SCT(LPC18xx_SCT):\r
- + SCT_Capture\r
- + SCT_Match\r
- - WWDT (lpc18xx_wwdt):\r
- + WWDT_Interrupt\r
- - CORTEXM3 (no driver):\r
- + CORTEXM3_BitBanding\r
- + CORTEXM3_MPU\r
- + CORTEXM3_PriviledgeMode\r
- - USBDEV (no driver):\r
- + USBDEV_VirtualCOM\r
- + USBDEV_MassStorage\r
- - NVIC (no driver):\r
- + NVIC_Priority\r
- + NVIC_VecRelocation\r
- - EVRT (lpc18xx_evrt)\r
-
\ No newline at end of file
+++ /dev/null
-NXP's documentation for their peripheral driver library can be found\r
-as a Microsoft Compiled HTML Help file (.chm) within the LPC18xx \r
-CMSIS Standard Peripheral Driver Library download on NXP's website.\r
-\r
-At the time of writing, this can be found at the following link:\r
-\r
-http://lpcware.com/file_filter/nxp?term_node_tid_depth=All&term_node_tid_depth_1=103\r
-\r
-\r
+++ /dev/null
-\r
-/****************************************************************************************************//**\r
- * @file LPC18xx.h\r
- *\r
- * @status EXPERIMENTAL\r
- *\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for\r
- * default LPC18xx Device Series\r
- *\r
- * @version V18\r
- * @date 1. December 2011\r
- *\r
- * @note Generated with SVDConv V2.6 Build 6c on Thursday, 01.12.2011 08:48:39\r
- *\r
- * from CMSIS SVD File 'LPC18xxv18.xml' Version 18,\r
- * created on Tuesday, 22.11.2011 18:06:23, last modified on Tuesday, 22.11.2011 18:38:38\r
- *\r
- *******************************************************************************************************/\r
-\r
-\r
-\r
-/** @addtogroup (null)\r
- * @{\r
- */\r
-\r
-/** @addtogroup LPC18xx\r
- * @{\r
- */\r
-\r
-#ifndef __LPC18XX_H__\r
-#define __LPC18XX_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-\r
-\r
-/********************************************\r
-** Start of section using anonymous unions **\r
-*********************************************/\r
-\r
-#if defined(__ARMCC_VERSION)\r
- #pragma push\r
- #pragma anon_unions\r
-#elif defined(__CWCC__)\r
- #pragma push\r
- #pragma cpp_extensions on\r
-#elif defined(__GNUC__)\r
- /* anonymous unions are enabled by default */\r
-#elif defined(__IAR_SYSTEMS_ICC__)\r
- #pragma push\r
- #pragma language=extended\r
-#else\r
- #error Not supported compiler type\r
-#endif\r
-\r
-\r
- /* Interrupt Number Definition */\r
-\r
-typedef enum {\r
-// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------\r
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */\r
- MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */\r
- BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */\r
- UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */\r
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
-// --------------------------- LPC18xx Specific Interrupt Numbers -------------------------------\r
- DAC_IRQn = 0, /*!< 0 DAC */\r
- RESERVED0_IRQn = 1, /*!< 1 M0a */\r
- DMA_IRQn = 2, /*!< 2 DMA */\r
- RESERVED1_IRQn = 3, /*!< 3 EZH/EDM */\r
- RESERVED2_IRQn = 4,\r
- ETHERNET_IRQn = 5, /*!< 5 ETHERNET */\r
- SDIO_IRQn = 6, /*!< 6 SDIO */\r
- LCD_IRQn = 7, /*!< 7 LCD */\r
- USB0_IRQn = 8, /*!< 8 USB0 */\r
- USB1_IRQn = 9, /*!< 9 USB1 */\r
- SCT_IRQn = 10, /*!< 10 SCT */\r
- RITIMER_IRQn = 11, /*!< 11 RITIMER */\r
- TIMER0_IRQn = 12, /*!< 12 TIMER0 */\r
- TIMER1_IRQn = 13, /*!< 13 TIMER1 */\r
- TIMER2_IRQn = 14, /*!< 14 TIMER2 */\r
- TIMER3_IRQn = 15, /*!< 15 TIMER3 */\r
- MCPWM_IRQn = 16, /*!< 16 MCPWM */\r
- ADC0_IRQn = 17, /*!< 17 ADC0 */\r
- I2C0_IRQn = 18, /*!< 18 I2C0 */\r
- I2C1_IRQn = 19, /*!< 19 I2C1 */\r
- RESERVED3_IRQn = 20,\r
- ADC1_IRQn = 21, /*!< 21 ADC1 */\r
- SSP0_IRQn = 22, /*!< 22 SSP0 */\r
- SSP1_IRQn = 23, /*!< 23 SSP1 */\r
- USART0_IRQn = 24, /*!< 24 USART0 */\r
- UART1_IRQn = 25, /*!< 25 UART1 */\r
- USART2_IRQn = 26, /*!< 26 USART2 */\r
- USART3_IRQn = 27, /*!< 27 USART3 */\r
- I2S0_IRQn = 28, /*!< 28 I2S0 */\r
- I2S1_IRQn = 29, /*!< 29 I2S1 */\r
- RESERVED4_IRQn = 30,\r
- RESERVED5_IRQn = 31,\r
- PIN_INT0_IRQn = 32, /*!< 32 PIN_INT0 */\r
- PIN_INT1_IRQn = 33, /*!< 33 PIN_INT1 */\r
- PIN_INT2_IRQn = 34, /*!< 34 PIN_INT2 */\r
- PIN_INT3_IRQn = 35, /*!< 35 PIN_INT3 */\r
- PIN_INT4_IRQn = 36, /*!< 36 PIN_INT4 */\r
- PIN_INT5_IRQn = 37, /*!< 37 PIN_INT5 */\r
- PIN_INT6_IRQn = 38, /*!< 38 PIN_INT6 */\r
- PIN_INT7_IRQn = 39, /*!< 39 PIN_INT7 */\r
- GINT0_IRQn = 40, /*!< 40 GINT0 */\r
- GINT1_IRQn = 41, /*!< 41 GINT1 */\r
- EVENTROUTER_IRQn = 42, /*!< 42 EVENTROUTER */\r
- C_CAN1_IRQn = 43, /*!< 43 C_CAN1 */\r
- RESERVED6_IRQn = 44,\r
- RESERVED7_IRQn = 45, /*!< 45 VADC */\r
- ATIMER_IRQn = 46, /*!< 46 ATIMER */\r
- RTC_IRQn = 47, /*!< 47 RTC */\r
- RESERVED8_IRQn = 48,\r
- WWDT_IRQn = 49, /*!< 49 WWDT */\r
- RESERVED9_IRQn = 50,\r
- C_CAN0_IRQn = 51, /*!< 51 C_CAN0 */\r
- QEI_IRQn = 52, /*!< 52 QEI */\r
-} IRQn_Type;\r
-\r
- /* Event Router Input (ERI) Number Definitions */\r
-typedef enum {\r
- WAKEUP0_ERIn = 0,\r
- WAKEUP1_ERIn = 1,\r
- WAKEUP2_ERIn = 2,\r
- WAKEUP3_ERIn = 3,\r
- ATIMER_ERIn = 4,\r
- RTC_ERIn = 5,\r
- BOD1_ERIn = 6, /* Bod trip 1 */\r
- WWDT_ERIn = 7,\r
- ETH_ERIn = 8,\r
- USB0_ERIn = 9,\r
- USB1_ERIn = 10,\r
- SDIO_ERIn = 11,\r
- CAN_ERIn = 12, /* CAN0/1 or'ed */\r
- TIM2_ERIn = 13,\r
- TIM6_ERIn = 14,\r
- QEI_ERIn = 15,\r
- TIM14_ERIn = 16,\r
- RESERVED0_ERIn = 17, /* M0s */\r
- RESERVED1_ERIn = 18, /* M3/M4 */\r
- RESET_ERIn = 19\r
-}ERIn_Type;\r
-\r
-/** @addtogroup Configuration_of_CMSIS\r
- * @{\r
- */\r
-\r
-/* Processor and Core Peripheral Section */ /* Configuration of the Template Processor and Core Peripherals */\r
-\r
-#define __CM3_REV 0x0101 /*!< Cortex-M3 Core Revision */\r
-#define __MPU_PRESENT 1 /*!< MPU present or not */\r
-#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */\r
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
-/** @} */ /* End of group Configuration_of_CMSIS */\r
-\r
-#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */\r
-//#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */\r
-\r
-#include "system_LPC18xx.h" /*!< LPC18xx System */\r
-\r
-/** @addtogroup Device_Peripheral_Registers\r
- * @{\r
- */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- SCT -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)\r
- */\r
-\r
-#define CONFIG_SCT_nEV (16) /* Number of events */\r
-#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */\r
-#define CONFIG_SCT_nOU (16) /* Number of outputs */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CONFIG; /* 0x000 Configuration Register */\r
- union {\r
- __IO uint32_t CTRL_U; /* 0x004 Control Register */\r
- struct {\r
- __IO uint16_t CTRL_L; /* 0x004 low control register */\r
- __IO uint16_t CTRL_H; /* 0x006 high control register */\r
- };\r
- };\r
- __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */\r
- __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */\r
- __IO uint16_t HALT_L; /* 0x00C halt register for counter L */\r
- __IO uint16_t HALT_H; /* 0x00E halt register for counter H */\r
- __IO uint16_t STOP_L; /* 0x010 stop register for counter L */\r
- __IO uint16_t STOP_H; /* 0x012 stop register for counter H */\r
- __IO uint16_t START_L; /* 0x014 start register for counter L */\r
- __IO uint16_t START_H; /* 0x016 start register for counter H */\r
- uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */\r
- union {\r
- __IO uint32_t COUNT_U; /* 0x040 counter register */\r
- struct {\r
- __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */\r
- __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */\r
- };\r
- };\r
- __IO uint16_t STATE_L; /* 0x044 state register for counter L */\r
- __IO uint16_t STATE_H; /* 0x046 state register for counter H */\r
- __I uint32_t INPUT; /* 0x048 input register */\r
- __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */\r
- __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */\r
- __IO uint32_t OUTPUT; /* 0x050 output register */\r
- __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */\r
- __IO uint32_t RES; /* 0x058 conflict resolution register */\r
- __IO uint32_t DMA0REQUEST; /* 0x05C DMA0 Request Register */\r
- __IO uint32_t DMA1REQUEST; /* 0x060 DMA1 Request Register */\r
- uint32_t RESERVED2[35]; /* 0x064-0x0EC reserved */\r
- __IO uint32_t EVEN; /* 0x0F0 event enable register */\r
- __IO uint32_t EVFLAG; /* 0x0F4 event flag register */\r
- __IO uint32_t CONEN; /* 0x0F8 conflict enable register */\r
- __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */\r
-\r
- union {\r
- __IO union { /* 0x100-... Match / Capture value */\r
- uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */\r
- struct {\r
- uint16_t L; /* SCTMATCH[i].L Access to L value */\r
- uint16_t H; /* SCTMATCH[i].H Access to H value */\r
- };\r
- } MATCH[CONFIG_SCT_nRG];\r
- __I union {\r
- uint32_t U; /* SCTCAP[i].U Unified 32-bit register */\r
- struct {\r
- uint16_t L; /* SCTCAP[i].L Access to H value */\r
- uint16_t H; /* SCTCAP[i].H Access to H value */\r
- };\r
- } CAP[CONFIG_SCT_nRG];\r
- };\r
-\r
- uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */\r
-\r
- union {\r
- __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */\r
- __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */\r
- };\r
- uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */\r
- union {\r
- __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */\r
- __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */\r
- };\r
- uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */\r
-\r
- union {\r
- __IO union { /* 0x200-... Match Reload / Capture Control value */\r
- uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */\r
- struct {\r
- uint16_t L; /* SCTMATCHREL[i].L Access to L value */\r
- uint16_t H; /* SCTMATCHREL[i].H Access to H value */\r
- };\r
- } MATCHREL[CONFIG_SCT_nRG];\r
- __IO union {\r
- uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */\r
- struct {\r
- uint16_t L; /* SCTCAPCTRL[i].L Access to H value */\r
- uint16_t H; /* SCTCAPCTRL[i].H Access to H value */\r
- };\r
- } CAPCTRL[CONFIG_SCT_nRG];\r
- };\r
-\r
- uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */\r
-\r
- union {\r
- __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */\r
- __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */\r
- };\r
- uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */\r
- union {\r
- __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */\r
- __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */\r
- };\r
- uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */\r
-\r
- __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/\r
- uint32_t STATE; /* Event State Register */\r
- uint32_t CTRL; /* Event Control Register */\r
- } EVENT[CONFIG_SCT_nEV];\r
-\r
- uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */\r
-\r
- __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */\r
- uint32_t SET; /* Output n Set Register */\r
- uint32_t CLR; /* Output n Clear Register */\r
- } OUT[CONFIG_SCT_nOU];\r
-\r
- uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */\r
-\r
- __I uint32_t MODULECONTENT; /* 0x7FC Module Content */\r
-\r
-} LPC_SCT_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GPDMA -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (GPDMA)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40002000) GPDMA Structure */\r
- __I uint32_t INTSTAT; /*!< (@ 0x40002000) DMA Interrupt Status Register */\r
- __I uint32_t INTTCSTAT; /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */\r
- __O uint32_t INTTCCLEAR; /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */\r
- __I uint32_t INTERRSTAT; /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */\r
- __O uint32_t INTERRCLR; /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */\r
- __I uint32_t RAWINTTCSTAT; /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */\r
- __I uint32_t RAWINTERRSTAT; /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */\r
- __I uint32_t ENBLDCHNS; /*!< (@ 0x4000201C) DMA Enabled Channel Register */\r
- __IO uint32_t SOFTBREQ; /*!< (@ 0x40002020) DMA Software Burst Request Register */\r
- __IO uint32_t SOFTSREQ; /*!< (@ 0x40002024) DMA Software Single Request Register */\r
- __IO uint32_t SOFTLBREQ; /*!< (@ 0x40002028) DMA Software Last Burst Request Register */\r
- __IO uint32_t SOFTLSREQ; /*!< (@ 0x4000202C) DMA Software Last Single Request Register */\r
- __IO uint32_t CONFIG; /*!< (@ 0x40002030) DMA Configuration Register */\r
- __IO uint32_t SYNC; /*!< (@ 0x40002034) DMA Synchronization Register */\r
- __I uint32_t RESERVED0[50];\r
- __IO uint32_t C0SRCADDR; /*!< (@ 0x40002100) DMA Channel Source Address Register */\r
- __IO uint32_t C0DESTADDR; /*!< (@ 0x40002104) DMA Channel Destination Address Register */\r
- __IO uint32_t C0LLI; /*!< (@ 0x40002108) DMA Channel Linked List Item Register */\r
- __IO uint32_t C0CONTROL; /*!< (@ 0x4000210C) DMA Channel Control Register */\r
- __IO uint32_t C0CONFIG; /*!< (@ 0x40002110) DMA Channel Configuration Register */\r
- __I uint32_t RESERVED1[3];\r
- __IO uint32_t C1SRCADDR; /*!< (@ 0x40002120) DMA Channel Source Address Register */\r
- __IO uint32_t C1DESTADDR; /*!< (@ 0x40002124) DMA Channel Destination Address Register */\r
- __IO uint32_t C1LLI; /*!< (@ 0x40002128) DMA Channel Linked List Item Register */\r
- __IO uint32_t C1CONTROL; /*!< (@ 0x4000212C) DMA Channel Control Register */\r
- __IO uint32_t C1CONFIG; /*!< (@ 0x40002130) DMA Channel Configuration Register */\r
- __I uint32_t RESERVED2[3];\r
- __IO uint32_t C2SRCADDR; /*!< (@ 0x40002140) DMA Channel Source Address Register */\r
- __IO uint32_t C2DESTADDR; /*!< (@ 0x40002144) DMA Channel Destination Address Register */\r
- __IO uint32_t C2LLI; /*!< (@ 0x40002148) DMA Channel Linked List Item Register */\r
- __IO uint32_t C2CONTROL; /*!< (@ 0x4000214C) DMA Channel Control Register */\r
- __IO uint32_t C2CONFIG; /*!< (@ 0x40002150) DMA Channel Configuration Register */\r
- __I uint32_t RESERVED3[3];\r
- __IO uint32_t C3SRCADDR; /*!< (@ 0x40002160) DMA Channel Source Address Register */\r
- __IO uint32_t C3DESTADDR; /*!< (@ 0x40002164) DMA Channel Destination Address Register */\r
- __IO uint32_t C3LLI; /*!< (@ 0x40002168) DMA Channel Linked List Item Register */\r
- __IO uint32_t C3CONTROL; /*!< (@ 0x4000216C) DMA Channel Control Register */\r
- __IO uint32_t C3CONFIG; /*!< (@ 0x40002170) DMA Channel Configuration Register */\r
- __I uint32_t RESERVED4[3];\r
- __IO uint32_t C4SRCADDR; /*!< (@ 0x40002180) DMA Channel Source Address Register */\r
- __IO uint32_t C4DESTADDR; /*!< (@ 0x40002184) DMA Channel Destination Address Register */\r
- __IO uint32_t C4LLI; /*!< (@ 0x40002188) DMA Channel Linked List Item Register */\r
- __IO uint32_t C4CONTROL; /*!< (@ 0x4000218C) DMA Channel Control Register */\r
- __IO uint32_t C4CONFIG; /*!< (@ 0x40002190) DMA Channel Configuration Register */\r
- __I uint32_t RESERVED5[3];\r
- __IO uint32_t C5SRCADDR; /*!< (@ 0x400021A0) DMA Channel Source Address Register */\r
- __IO uint32_t C5DESTADDR; /*!< (@ 0x400021A4) DMA Channel Destination Address Register */\r
- __IO uint32_t C5LLI; /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */\r
- __IO uint32_t C5CONTROL; /*!< (@ 0x400021AC) DMA Channel Control Register */\r
- __IO uint32_t C5CONFIG; /*!< (@ 0x400021B0) DMA Channel Configuration Register */\r
- __I uint32_t RESERVED6[3];\r
- __IO uint32_t C6SRCADDR; /*!< (@ 0x400021C0) DMA Channel Source Address Register */\r
- __IO uint32_t C6DESTADDR; /*!< (@ 0x400021C4) DMA Channel Destination Address Register */\r
- __IO uint32_t C6LLI; /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */\r
- __IO uint32_t C6CONTROL; /*!< (@ 0x400021CC) DMA Channel Control Register */\r
- __IO uint32_t C6CONFIG; /*!< (@ 0x400021D0) DMA Channel Configuration Register */\r
- __I uint32_t RESERVED7[3];\r
- __IO uint32_t C7SRCADDR; /*!< (@ 0x400021E0) DMA Channel Source Address Register */\r
- __IO uint32_t C7DESTADDR; /*!< (@ 0x400021E4) DMA Channel Destination Address Register */\r
- __IO uint32_t C7LLI; /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */\r
- __IO uint32_t C7CONTROL; /*!< (@ 0x400021EC) DMA Channel Control Register */\r
- __IO uint32_t C7CONFIG; /*!< (@ 0x400021F0) DMA Channel Configuration Register */\r
-} LPC_GPDMA_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- SDMMC -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a (SDMMC)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40004000) SDMMC Structure */\r
- __IO uint32_t CTRL; /*!< (@ 0x40004000) Control Register */\r
- __IO uint32_t PWREN; /*!< (@ 0x40004004) Power Enable Register */\r
- __IO uint32_t CLKDIV; /*!< (@ 0x40004008) Clock Divider Register */\r
- __IO uint32_t CLKSRC; /*!< (@ 0x4000400C) SD Clock Source Register */\r
- __IO uint32_t CLKENA; /*!< (@ 0x40004010) Clock Enable Register */\r
- __IO uint32_t TMOUT; /*!< (@ 0x40004014) Timeout Register */\r
- __IO uint32_t CTYPE; /*!< (@ 0x40004018) Card Type Register */\r
- __IO uint32_t BLKSIZ; /*!< (@ 0x4000401C) Block Size Register */\r
- __IO uint32_t BYTCNT; /*!< (@ 0x40004020) Byte Count Register */\r
- __IO uint32_t INTMASK; /*!< (@ 0x40004024) Interrupt Mask Register */\r
- __IO uint32_t CMDARG; /*!< (@ 0x40004028) Command Argument Register */\r
- __IO uint32_t CMD; /*!< (@ 0x4000402C) Command Register */\r
- __I uint32_t RESP0; /*!< (@ 0x40004030) Response Register 0 */\r
- __I uint32_t RESP1; /*!< (@ 0x40004034) Response Register 1 */\r
- __I uint32_t RESP2; /*!< (@ 0x40004038) Response Register 2 */\r
- __I uint32_t RESP3; /*!< (@ 0x4000403C) Response Register 3 */\r
- __I uint32_t MINTSTS; /*!< (@ 0x40004040) Masked Interrupt Status Register */\r
- __IO uint32_t RINTSTS; /*!< (@ 0x40004044) Raw Interrupt Status Register */\r
- __I uint32_t STATUS; /*!< (@ 0x40004048) Status Register */\r
- __IO uint32_t FIFOTH; /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */\r
- __I uint32_t CDETECT; /*!< (@ 0x40004050) Card Detect Register */\r
- __I uint32_t WRTPRT; /*!< (@ 0x40004054) Write Protect Register */\r
- __IO uint32_t GPIO; /*!< (@ 0x40004058) General Purpose Input/Output Register */\r
- __I uint32_t TCBCNT; /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */\r
- __I uint32_t TBBCNT; /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */\r
- __IO uint32_t DEBNCE; /*!< (@ 0x40004064) Debounce Count Register */\r
- __IO uint32_t USRID; /*!< (@ 0x40004068) User ID Register */\r
- __I uint32_t VERID; /*!< (@ 0x4000406C) Version ID Register */\r
- __I uint32_t RESERVED0;\r
- __IO uint32_t UHS_REG; /*!< (@ 0x40004074) UHS-1 Register */\r
- __IO uint32_t RST_N; /*!< (@ 0x40004078) Hardware Reset */\r
- __I uint32_t RESERVED1;\r
- __IO uint32_t BMOD; /*!< (@ 0x40004080) Bus Mode Register */\r
- __O uint32_t PLDMND; /*!< (@ 0x40004084) Poll Demand Register */\r
- __IO uint32_t DBADDR; /*!< (@ 0x40004088) Descriptor List Base Address Register */\r
- __IO uint32_t IDSTS; /*!< (@ 0x4000408C) Internal DMAC Status Register */\r
- __IO uint32_t IDINTEN; /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */\r
- __I uint32_t DSCADDR; /*!< (@ 0x40004094) Current Host Descriptor Address Register */\r
- __I uint32_t BUFADDR; /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */\r
-} LPC_SDMMC_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- EMC -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7 (EMC)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40005000) EMC Structure */\r
- __IO uint32_t CONTROL; /*!< (@ 0x40005000) Controls operation of the memory controller. */\r
- __I uint32_t STATUS; /*!< (@ 0x40005004) Provides EMC status information. */\r
- __IO uint32_t CONFIG; /*!< (@ 0x40005008) Configures operation of the memory controller. */\r
- __I uint32_t RESERVED0[5];\r
- __IO uint32_t DYNAMICCONTROL; /*!< (@ 0x40005020) Controls dynamic memory operation. */\r
- __IO uint32_t DYNAMICREFRESH; /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */\r
- __IO uint32_t DYNAMICREADCONFIG; /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */\r
- __I uint32_t RESERVED1;\r
- __IO uint32_t DYNAMICRP; /*!< (@ 0x40005030) Selects the precharge command period. */\r
- __IO uint32_t DYNAMICRAS; /*!< (@ 0x40005034) Selects the active to precharge command period. */\r
- __IO uint32_t DYNAMICSREX; /*!< (@ 0x40005038) Selects the self-refresh exit time. */\r
- __IO uint32_t DYNAMICAPR; /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */\r
- __IO uint32_t DYNAMICDAL; /*!< (@ 0x40005040) Selects the data-in to active command time. */\r
- __IO uint32_t DYNAMICWR; /*!< (@ 0x40005044) Selects the write recovery time. */\r
- __IO uint32_t DYNAMICRC; /*!< (@ 0x40005048) Selects the active to active command period. */\r
- __IO uint32_t DYNAMICRFC; /*!< (@ 0x4000504C) Selects the auto-refresh period. */\r
- __IO uint32_t DYNAMICXSR; /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */\r
- __IO uint32_t DYNAMICRRD; /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */\r
- __IO uint32_t DYNAMICMRD; /*!< (@ 0x40005058) Selects the load mode register to active command time. */\r
- __I uint32_t RESERVED2[9];\r
- __IO uint32_t STATICEXTENDEDWAIT; /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */\r
- __I uint32_t RESERVED3[31];\r
- __IO uint32_t DYNAMICCONFIG0; /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */\r
- __IO uint32_t DYNAMICRASCAS0; /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
- __I uint32_t RESERVED4[6];\r
- __IO uint32_t DYNAMICCONFIG1; /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */\r
- __IO uint32_t DYNAMICRASCAS1; /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
- __I uint32_t RESERVED5[6];\r
- __IO uint32_t DYNAMICCONFIG2; /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */\r
- __IO uint32_t DYNAMICRASCAS2; /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
- __I uint32_t RESERVED6[6];\r
- __IO uint32_t DYNAMICCONFIG3; /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */\r
- __IO uint32_t DYNAMICRASCAS3; /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
- __I uint32_t RESERVED7[38];\r
- __IO uint32_t STATICCONFIG0; /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */\r
- __IO uint32_t STATICWAITWEN0; /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */\r
- __IO uint32_t STATICWAITOEN0; /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
- __IO uint32_t STATICWAITRD0; /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */\r
- __IO uint32_t STATICWAITPAG0; /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
- __IO uint32_t STATICWAITWR0; /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */\r
- __IO uint32_t STATICWAITTURN0; /*!< (@ 0x40005218) Selects bus turnaround cycles */\r
- __I uint32_t RESERVED8;\r
- __IO uint32_t STATICCONFIG1; /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */\r
- __IO uint32_t STATICWAITWEN1; /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */\r
- __IO uint32_t STATICWAITOEN1; /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
- __IO uint32_t STATICWAITRD1; /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */\r
- __IO uint32_t STATICWAITPAG1; /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
- __IO uint32_t STATICWAITWR1; /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */\r
- __IO uint32_t STATICWAITTURN1; /*!< (@ 0x40005238) Selects bus turnaround cycles */\r
- __I uint32_t RESERVED9;\r
- __IO uint32_t STATICCONFIG2; /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */\r
- __IO uint32_t STATICWAITWEN2; /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */\r
- __IO uint32_t STATICWAITOEN2; /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
- __IO uint32_t STATICWAITRD2; /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */\r
- __IO uint32_t STATICWAITPAG2; /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
- __IO uint32_t STATICWAITWR2; /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */\r
- __IO uint32_t STATICWAITTURN2; /*!< (@ 0x40005258) Selects bus turnaround cycles */\r
- __I uint32_t RESERVED10;\r
- __IO uint32_t STATICCONFIG3; /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */\r
- __IO uint32_t STATICWAITWEN3; /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */\r
- __IO uint32_t STATICWAITOEN3; /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
- __IO uint32_t STATICWAITRD3; /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */\r
- __IO uint32_t STATICWAITPAG3; /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
- __IO uint32_t STATICWAITWR3; /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */\r
- __IO uint32_t STATICWAITTURN3; /*!< (@ 0x40005278) Selects bus turnaround cycles */\r
-} LPC_EMC_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- USB0 -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB0)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40006000) USB0 Structure */\r
- __I uint32_t RESERVED0[64];\r
- __I uint32_t CAPLENGTH; /*!< (@ 0x40006100) Capability register length */\r
- __I uint32_t HCSPARAMS; /*!< (@ 0x40006104) Host controller structural parameters */\r
- __I uint32_t HCCPARAMS; /*!< (@ 0x40006108) Host controller capability parameters */\r
- __I uint32_t RESERVED1[5];\r
- __I uint32_t DCIVERSION; /*!< (@ 0x40006120) Device interface version number */\r
- __I uint32_t RESERVED2[7];\r
-\r
- union {\r
- __IO uint32_t USBCMD_H; /*!< (@ 0x40006140) USB command (host mode) */\r
- __IO uint32_t USBCMD_D; /*!< (@ 0x40006140) USB command (device mode) */\r
- };\r
-\r
- union {\r
- __IO uint32_t USBSTS_H; /*!< (@ 0x40006144) USB status (host mode) */\r
- __IO uint32_t USBSTS_D; /*!< (@ 0x40006144) USB status (device mode) */\r
- };\r
-\r
- union {\r
- __IO uint32_t USBINTR_H; /*!< (@ 0x40006148) USB interrupt enable (host mode) */\r
- __IO uint32_t USBINTR_D; /*!< (@ 0x40006148) USB interrupt enable (device mode) */\r
- };\r
-\r
- union {\r
- __IO uint32_t FRINDEX_H; /*!< (@ 0x4000614C) USB frame index (host mode) */\r
- __IO uint32_t FRINDEX_D; /*!< (@ 0x4000614C) USB frame index (device mode) */\r
- };\r
- __I uint32_t RESERVED3;\r
-\r
- union {\r
- __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40006154) Frame list base address (host mode) */\r
- __IO uint32_t DEVICEADDR; /*!< (@ 0x40006154) USB device address (device mode) */\r
- };\r
-\r
- union {\r
- __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */\r
- __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */\r
- };\r
- __IO uint32_t TTCTRL; /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */\r
- __IO uint32_t BURSTSIZE; /*!< (@ 0x40006160) Programmable burst size */\r
- __IO uint32_t TXFILLTUNING; /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */\r
- __I uint32_t RESERVED4[3];\r
- __IO uint32_t BINTERVAL; /*!< (@ 0x40006174) Length of virtual frame */\r
- __IO uint32_t ENDPTNAK; /*!< (@ 0x40006178) Endpoint NAK (device mode) */\r
- __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */\r
- __I uint32_t RESERVED5;\r
-\r
- union {\r
- __IO uint32_t PORTSC1_H; /*!< (@ 0x40006184) Port 1 status/control (host mode) */\r
- __IO uint32_t PORTSC1_D; /*!< (@ 0x40006184) Port 1 status/control (device mode) */\r
- };\r
- __I uint32_t RESERVED6[7];\r
- __IO uint32_t OTGSC; /*!< (@ 0x400061A4) OTG status and control */\r
-\r
- union {\r
- __IO uint32_t USBMODE_H; /*!< (@ 0x400061A8) USB mode (host mode) */\r
- __IO uint32_t USBMODE_D; /*!< (@ 0x400061A8) USB device mode (device mode) */\r
- };\r
- __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400061AC) Endpoint setup status */\r
- __IO uint32_t ENDPTPRIME; /*!< (@ 0x400061B0) Endpoint initialization */\r
- __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400061B4) Endpoint de-initialization */\r
- __I uint32_t ENDPTSTAT; /*!< (@ 0x400061B8) Endpoint status */\r
- __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400061BC) Endpoint complete */\r
- __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400061C0) Endpoint control 0 */\r
- __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400061C4) Endpoint control */\r
- __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400061C8) Endpoint control */\r
- __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400061CC) Endpoint control */\r
- __IO uint32_t ENDPTCTRL4; /*!< (@ 0x400061D0) Endpoint control */\r
- __IO uint32_t ENDPTCTRL5; /*!< (@ 0x400061D4) Endpoint control */\r
-} LPC_USB0_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- USB1 -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB1)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40007000) USB1 Structure */\r
- __I uint32_t RESERVED0[64];\r
- __I uint32_t CAPLENGTH; /*!< (@ 0x40007100) Capability register length */\r
- __I uint32_t HCSPARAMS; /*!< (@ 0x40007104) Host controller structural parameters */\r
- __I uint32_t HCCPARAMS; /*!< (@ 0x40007108) Host controller capability parameters */\r
- __I uint32_t RESERVED1[5];\r
- __I uint32_t DCIVERSION; /*!< (@ 0x40007120) Device interface version number */\r
- __I uint32_t RESERVED2[7];\r
-\r
- union {\r
- __IO uint32_t USBCMD_H; /*!< (@ 0x40007140) USB command (host mode) */\r
- __IO uint32_t USBCMD_D; /*!< (@ 0x40007140) USB command (device mode) */\r
- };\r
-\r
- union {\r
- __IO uint32_t USBSTS_H; /*!< (@ 0x40007144) USB status (host mode) */\r
- __IO uint32_t USBSTS_D; /*!< (@ 0x40007144) USB status (device mode) */\r
- };\r
-\r
- union {\r
- __IO uint32_t USBINTR_H; /*!< (@ 0x40007148) USB interrupt enable (host mode) */\r
- __IO uint32_t USBINTR_D; /*!< (@ 0x40007148) USB interrupt enable (device mode) */\r
- };\r
-\r
- union {\r
- __IO uint32_t FRINDEX_H; /*!< (@ 0x4000714C) USB frame index (host mode) */\r
- __I uint32_t FRINDEX_D; /*!< (@ 0x4000714C) USB frame index (device mode) */\r
- };\r
- __I uint32_t RESERVED3;\r
-\r
- union {\r
- __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40007154) Frame list base address */\r
- __IO uint32_t DEVICEADDR; /*!< (@ 0x40007154) USB device address */\r
- };\r
-\r
- union {\r
- __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */\r
- __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */\r
- };\r
- __IO uint32_t TTCTRL; /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */\r
- __IO uint32_t BURSTSIZE; /*!< (@ 0x40007160) Programmable burst size */\r
- __IO uint32_t TXFILLTUNING; /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */\r
- __I uint32_t RESERVED4[2];\r
- __IO uint32_t ULPIVIEWPORT; /*!< (@ 0x40007170) ULPI viewport */\r
- __IO uint32_t BINTERVAL; /*!< (@ 0x40007174) Length of virtual frame */\r
- __IO uint32_t ENDPTNAK; /*!< (@ 0x40007178) Endpoint NAK (device mode) */\r
- __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */\r
- __I uint32_t RESERVED5;\r
-\r
- union {\r
- __IO uint32_t PORTSC1_H; /*!< (@ 0x40007184) Port 1 status/control (host mode) */\r
- __IO uint32_t PORTSC1_D; /*!< (@ 0x40007184) Port 1 status/control (device mode) */\r
- };\r
- __I uint32_t RESERVED6[8];\r
-\r
- union {\r
- __IO uint32_t USBMODE_H; /*!< (@ 0x400071A8) USB mode (host mode) */\r
- __IO uint32_t USBMODE_D; /*!< (@ 0x400071A8) USB mode (device mode) */\r
- };\r
- __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400071AC) Endpoint setup status */\r
- __IO uint32_t ENDPTPRIME; /*!< (@ 0x400071B0) Endpoint initialization */\r
- __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400071B4) Endpoint de-initialization */\r
- __I uint32_t ENDPTSTAT; /*!< (@ 0x400071B8) Endpoint status */\r
- __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400071BC) Endpoint complete */\r
- __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400071C0) Endpoint control 0 */\r
- __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400071C4) Endpoint control */\r
- __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400071C8) Endpoint control */\r
- __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400071CC) Endpoint control */\r
-} LPC_USB1_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- LCD -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7 (LCD)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40008000) LCD Structure */\r
- __IO uint32_t TIMH; /*!< (@ 0x40008000) Horizontal Timing Control register */\r
- __IO uint32_t TIMV; /*!< (@ 0x40008004) Vertical Timing Control register */\r
- __IO uint32_t POL; /*!< (@ 0x40008008) Clock and Signal Polarity Control register */\r
- __IO uint32_t LE; /*!< (@ 0x4000800C) Line End Control register */\r
- __IO uint32_t UPBASE; /*!< (@ 0x40008010) Upper Panel Frame Base Address register */\r
- __IO uint32_t LPBASE; /*!< (@ 0x40008014) Lower Panel Frame Base Address register */\r
- __IO uint32_t CTRL; /*!< (@ 0x40008018) LCD Control register */\r
- __IO uint32_t INTMSK; /*!< (@ 0x4000801C) Interrupt Mask register */\r
- __I uint32_t INTRAW; /*!< (@ 0x40008020) Raw Interrupt Status register */\r
- __I uint32_t INTSTAT; /*!< (@ 0x40008024) Masked Interrupt Status register */\r
- __O uint32_t INTCLR; /*!< (@ 0x40008028) Interrupt Clear register */\r
- __I uint32_t UPCURR; /*!< (@ 0x4000802C) Upper Panel Current Address Value register */\r
- __I uint32_t LPCURR; /*!< (@ 0x40008030) Lower Panel Current Address Value register */\r
- __I uint32_t RESERVED0[115];\r
- __IO uint32_t PAL[256]; /*!< (@ 0x40008200) 256x16-bit Color Palette registers */\r
- __I uint32_t RESERVED1[128];\r
- __IO uint32_t CRSR_IMG[256]; /*!< (@ 0x40008800) Cursor Image registers */\r
- __IO uint32_t CRSR_CTRL; /*!< (@ 0x40008C00) Cursor Control register */\r
- __IO uint32_t CRSR_CFG; /*!< (@ 0x40008C04) Cursor Configuration register */\r
- __IO uint32_t CRSR_PAL0; /*!< (@ 0x40008C08) Cursor Palette register 0 */\r
- __IO uint32_t CRSR_PAL1; /*!< (@ 0x40008C0C) Cursor Palette register 1 */\r
- __IO uint32_t CRSR_XY; /*!< (@ 0x40008C10) Cursor XY Position register */\r
- __IO uint32_t CRSR_CLIP; /*!< (@ 0x40008C14) Cursor Clip Position register */\r
- __I uint32_t RESERVED2[2];\r
- __IO uint32_t CRSR_INTMSK; /*!< (@ 0x40008C20) Cursor Interrupt Mask register */\r
- __O uint32_t CRSR_INTCLR; /*!< (@ 0x40008C24) Cursor Interrupt Clear register */\r
- __I uint32_t CRSR_INTRAW; /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */\r
- __I uint32_t CRSR_INTSTAT; /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */\r
-} LPC_LCD_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- ETHERNET -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=1/20/2011 Major revision=0 Minor revision=7 (ETHERNET)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40010000) ETHERNET Structure */\r
- __IO uint32_t MAC_CONFIG; /*!< (@ 0x40010000) MAC configuration register */\r
- __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x40010004) MAC frame filter */\r
- __IO uint32_t MAC_HASHTABLE_HIGH; /*!< (@ 0x40010008) Hash table high register */\r
- __IO uint32_t MAC_HASHTABLE_LOW; /*!< (@ 0x4001000C) Hash table low register */\r
- __IO uint32_t MAC_MII_ADDR; /*!< (@ 0x40010010) MII address register */\r
- __IO uint32_t MAC_MII_DATA; /*!< (@ 0x40010014) MII data register */\r
- __IO uint32_t MAC_FLOW_CTRL; /*!< (@ 0x40010018) Flow control register */\r
- __IO uint32_t MAC_VLAN_TAG; /*!< (@ 0x4001001C) VLAN tag register */\r
- __I uint32_t RESERVED0;\r
- __IO uint32_t MAC_DEBUG; /*!< (@ 0x40010024) Debug register */\r
- __IO uint32_t MAC_RWAKE_FRFLT; /*!< (@ 0x40010028) Remote wake-up frame filter */\r
- __IO uint32_t MAC_PMT_CTRL_STAT; /*!< (@ 0x4001002C) PMT control and status */\r
- __I uint32_t RESERVED1[2];\r
- __IO uint32_t MAC_INTR; /*!< (@ 0x40010038) Interrupt status register */\r
- __IO uint32_t MAC_INTR_MASK; /*!< (@ 0x4001003C) Interrupt mask register */\r
- __IO uint32_t MAC_ADDR0_HIGH; /*!< (@ 0x40010040) MAC address 0 high register */\r
- __IO uint32_t MAC_ADDR0_LOW; /*!< (@ 0x40010044) MAC address 0 low register */\r
- __I uint32_t RESERVED2[430];\r
- __IO uint32_t MAC_TIMESTP_CTRL; /*!< (@ 0x40010700) Time stamp control register */\r
- __I uint32_t RESERVED3[575];\r
- __IO uint32_t DMA_BUS_MODE; /*!< (@ 0x40011000) Bus Mode Register */\r
- __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< (@ 0x40011004) Transmit poll demand register */\r
- __IO uint32_t DMA_REC_POLL_DEMAND; /*!< (@ 0x40011008) Receive poll demand register */\r
- __IO uint32_t DMA_REC_DES_ADDR; /*!< (@ 0x4001100C) Receive descriptor list address register */\r
- __IO uint32_t DMA_TRANS_DES_ADDR; /*!< (@ 0x40011010) Transmit descriptor list address register */\r
- __IO uint32_t DMA_STAT; /*!< (@ 0x40011014) Status register */\r
- __IO uint32_t DMA_OP_MODE; /*!< (@ 0x40011018) Operation mode register */\r
- __IO uint32_t DMA_INT_EN; /*!< (@ 0x4001101C) Interrupt enable register */\r
- __IO uint32_t DMA_MFRM_BUFOF; /*!< (@ 0x40011020) Missed frame and buffer overflow register */\r
- __IO uint32_t DMA_REC_INT_WDT; /*!< (@ 0x40011024) Receive interrupt watchdog timer register */\r
- __I uint32_t RESERVED4[8];\r
- __IO uint32_t DMA_CURHOST_TRANS_DES; /*!< (@ 0x40011048) Current host transmit descriptor register */\r
- __IO uint32_t DMA_CURHOST_REC_DES; /*!< (@ 0x4001104C) Current host receive descriptor register */\r
- __IO uint32_t DMA_CURHOST_TRANS_BUF; /*!< (@ 0x40011050) Current host transmit buffer address register */\r
- __IO uint32_t DMA_CURHOST_REC_BUF; /*!< (@ 0x40011054) Current host receive buffer address register */\r
-} LPC_ETHERNET_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- ATIMER -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6 (ATIMER)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40040000) ATIMER Structure */\r
- __IO uint32_t DOWNCOUNTER; /*!< (@ 0x40040000) Downcounter register */\r
- __IO uint32_t PRESET; /*!< (@ 0x40040004) Preset value register */\r
- __I uint32_t RESERVED0[1012];\r
- __O uint32_t CLR_EN; /*!< (@ 0x40040FD8) Interrupt clear enable register */\r
- __O uint32_t SET_EN; /*!< (@ 0x40040FDC) Interrupt set enable register */\r
- __I uint32_t STATUS; /*!< (@ 0x40040FE0) Status register */\r
- __I uint32_t ENABLE; /*!< (@ 0x40040FE4) Enable register */\r
- __O uint32_t CLR_STAT; /*!< (@ 0x40040FE8) Clear register */\r
- __O uint32_t SET_STAT; /*!< (@ 0x40040FEC) Set register */\r
-} LPC_ATIMER_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- REGFILE -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7 (REGFILE)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40041000) REGFILE Structure */\r
- __IO uint32_t REGFILE[64]; /*!< (@ 0x40041000) General purpose storage register */\r
-} LPC_REGFILE_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- PMC -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (PMC)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40042000) PMC Structure */\r
- __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< (@ 0x40042000) Hardware sleep event enable register */\r
- __I uint32_t RESERVED0[6];\r
- __IO uint32_t PD0_SLEEP0_MODE; /*!< (@ 0x4004201C) Sleep power mode register */\r
-} LPC_PMC_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- CREG -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Configuration Registers (CREG) Modification date=8/19/2011 Major revision=0 Minor revision=14 (CREG)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40043000) CREG Structure */\r
- __I uint32_t IRCTRM; /*!< (@ 0x40043000) IRC trim register */\r
- __IO uint32_t CREG0; /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */\r
- __IO uint32_t PMUCON; /*!< (@ 0x40043008) Power mode control register. */\r
- __I uint32_t RESERVED0[61];\r
- __IO uint32_t M3MEMMAP; /*!< (@ 0x40043100) ARM Cortex-M3 memory mapping */\r
- __I uint32_t RESERVED1[5];\r
- __IO uint32_t CREG5; /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */\r
- __IO uint32_t DMAMUX; /*!< (@ 0x4004311C) DMA muxing control */\r
- __I uint32_t RESERVED2[2];\r
- __IO uint32_t ETBCFG; /*!< (@ 0x40043128) ETB RAM configuration */\r
- __IO uint32_t CREG6; /*!< (@ 0x4004312C) Chip configuration register 6 */\r
- __I uint32_t RESERVED3[52];\r
- __I uint32_t CHIPID; /*!< (@ 0x40043200) Part ID */\r
-} LPC_CREG_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- EVENTROUTER -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Event router Modification date=1/20/2011 Major revision=0 Minor revision=7 (EVENTROUTER)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40044000) EVENTROUTER Structure */\r
- __IO uint32_t HILO; /*!< (@ 0x40044000) Level configuration register */\r
- __IO uint32_t EDGE; /*!< (@ 0x40044004) Edge configuration */\r
- __I uint32_t RESERVED0[1012];\r
- __O uint32_t CLR_EN; /*!< (@ 0x40044FD8) Event clear enable register */\r
- __O uint32_t SET_EN; /*!< (@ 0x40044FDC) Event set enable register */\r
- __I uint32_t STATUS; /*!< (@ 0x40044FE0) Status register */\r
- __I uint32_t ENABLE; /*!< (@ 0x40044FE4) Enable register */\r
- __O uint32_t CLR_STAT; /*!< (@ 0x40044FE8) Clear register */\r
- __O uint32_t SET_STAT; /*!< (@ 0x40044FEC) Set register */\r
-} LPC_EVENTROUTER_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- RTC -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (RTC)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40046000) RTC Structure */\r
- __O uint32_t ILR; /*!< (@ 0x40046000) Interrupt Location Register */\r
- __I uint32_t RESERVED0;\r
- __IO uint32_t CCR; /*!< (@ 0x40046008) Clock Control Register */\r
- __IO uint32_t CIIR; /*!< (@ 0x4004600C) Counter Increment Interrupt Register */\r
- __IO uint32_t AMR; /*!< (@ 0x40046010) Alarm Mask Register */\r
- __I uint32_t CTIME0; /*!< (@ 0x40046014) Consolidated Time Register 0 */\r
- __I uint32_t CTIME1; /*!< (@ 0x40046018) Consolidated Time Register 1 */\r
- __I uint32_t CTIME2; /*!< (@ 0x4004601C) Consolidated Time Register 2 */\r
- __IO uint32_t SEC; /*!< (@ 0x40046020) Seconds Register */\r
- __IO uint32_t MIN; /*!< (@ 0x40046024) Minutes Register */\r
- __IO uint32_t HRS; /*!< (@ 0x40046028) Hours Register */\r
- __IO uint32_t DOM; /*!< (@ 0x4004602C) Day of Month Register */\r
- __IO uint32_t DOW; /*!< (@ 0x40046030) Day of Week Register */\r
- __IO uint32_t DOY; /*!< (@ 0x40046034) Day of Year Register */\r
- __IO uint32_t MONTH; /*!< (@ 0x40046038) Months Register */\r
- __IO uint32_t YEAR; /*!< (@ 0x4004603C) Years Register */\r
- __IO uint32_t CALIBRATION; /*!< (@ 0x40046040) Calibration Value Register */\r
- __I uint32_t RESERVED1[7];\r
- __IO uint32_t ASEC; /*!< (@ 0x40046060) Alarm value for Seconds */\r
- __IO uint32_t AMIN; /*!< (@ 0x40046064) Alarm value for Minutes */\r
- __IO uint32_t AHRS; /*!< (@ 0x40046068) Alarm value for Hours */\r
- __IO uint32_t ADOM; /*!< (@ 0x4004606C) Alarm value for Day of Month */\r
- __IO uint32_t ADOW; /*!< (@ 0x40046070) Alarm value for Day of Week */\r
- __IO uint32_t ADOY; /*!< (@ 0x40046074) Alarm value for Day of Year */\r
- __IO uint32_t AMON; /*!< (@ 0x40046078) Alarm value for Months */\r
- __IO uint32_t AYRS; /*!< (@ 0x4004607C) Alarm value for Year */\r
-} LPC_RTC_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- CGU -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1 (CGU)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40050000) CGU Structure */\r
- __I uint32_t RESERVED0[5];\r
- __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */\r
- __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */\r
- __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0 (USB) status register */\r
- __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0 (USB) control register */\r
- __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0 (USB) M-divider register */\r
- __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */\r
- __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0 (audio) status register */\r
- __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0 (audio) control register */\r
- __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0 (audio) M-divider register */\r
- __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */\r
- __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */\r
- __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */\r
- __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */\r
- __IO uint32_t IDIVA_CTRL; /*!< (@ 0x40050048) Integer divider A control register */\r
- __IO uint32_t IDIVB_CTRL; /*!< (@ 0x4005004C) Integer divider B control register */\r
- __IO uint32_t IDIVC_CTRL; /*!< (@ 0x40050050) Integer divider C control register */\r
- __IO uint32_t IDIVD_CTRL; /*!< (@ 0x40050054) Integer divider D control register */\r
- __IO uint32_t IDIVE_CTRL; /*!< (@ 0x40050058) Integer divider E control register */\r
- __IO uint32_t BASE_SAFE_CLK; /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */\r
- __IO uint32_t BASE_USB0_CLK; /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */\r
- __IO uint32_t BASE_PERIPH_CLK; /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */\r
- __IO uint32_t BASE_USB1_CLK; /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */\r
- __IO uint32_t BASE_M3_CLK; /*!< (@ 0x4005006C) Output stage control register */\r
- __IO uint32_t BASE_SPIFI_CLK; /*!< (@ 0x40050070) Output stage control register */\r
- __IO uint32_t BASE_SPI_CLK; /*!< (@ 0x40050074) Output stage control register */\r
- __IO uint32_t BASE_PHY_RX_CLK; /*!< (@ 0x40050078) Output stage control register */\r
- __IO uint32_t BASE_PHY_TX_CLK; /*!< (@ 0x4005007C) Output stage control register */\r
- __IO uint32_t BASE_APB1_CLK; /*!< (@ 0x40050080) Output stage control register */\r
- __IO uint32_t BASE_APB3_CLK; /*!< (@ 0x40050084) Output stage control register */\r
- __IO uint32_t BASE_LCD_CLK; /*!< (@ 0x40050088) Output stage control register */\r
- __IO uint32_t RESERVED2;\r
- __IO uint32_t BASE_SDIO_CLK; /*!< (@ 0x40050090) Output stage control register */\r
- __IO uint32_t BASE_SSP0_CLK; /*!< (@ 0x40050094) Output stage control register */\r
- __IO uint32_t BASE_SSP1_CLK; /*!< (@ 0x40050098) Output stage control register */\r
- __IO uint32_t BASE_UART0_CLK; /*!< (@ 0x4005009C) Output stage control register */\r
- __IO uint32_t BASE_UART1_CLK; /*!< (@ 0x400500A0) Output stage control register */\r
- __IO uint32_t BASE_UART2_CLK; /*!< (@ 0x400500A4) Output stage control register */\r
- __IO uint32_t BASE_UART3_CLK; /*!< (@ 0x400500A8) Output stage control register */\r
- __IO uint32_t BASE_OUT_CLK; /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */\r
- __I uint32_t RESERVED3[4];\r
- __IO uint32_t BASE_APLL_CLK; /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */\r
- __IO uint32_t BASE_CGU_OUT0_CLK; /*!< (@ 0x400500C4) Output stage 26 control register for base clock BASE_CGU_OUT0_CLK */\r
- __IO uint32_t BASE_CGU_OUT1_CLK; /*!< (@ 0x400500C8) Output stage 27 control register for base clock BASE_CGU_OUT1_CLK */\r
-} LPC_CGU_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- CCU1 -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU1)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40051000) CCU1 Structure */\r
- __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */\r
- __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */\r
- __I uint32_t RESERVED0[62];\r
- __IO uint32_t CLK_APB3_BUS_CFG; /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */\r
- __I uint32_t CLK_APB3_BUS_STAT; /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */\r
- __IO uint32_t CLK_APB3_I2C1_CFG; /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */\r
- __I uint32_t CLK_APB3_I2C1_STAT; /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */\r
- __IO uint32_t CLK_APB3_DAC_CFG; /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */\r
- __I uint32_t CLK_APB3_DAC_STAT; /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */\r
- __IO uint32_t CLK_APB3_ADC0_CFG; /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */\r
- __I uint32_t CLK_APB3_ADC0_STAT; /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */\r
- __IO uint32_t CLK_APB3_ADC1_CFG; /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */\r
- __I uint32_t CLK_APB3_ADC1_STAT; /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */\r
- __IO uint32_t CLK_APB3_CAN0_CFG; /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */\r
- __I uint32_t CLK_APB3_CAN0_STAT; /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */\r
- __I uint32_t RESERVED1[52];\r
- __IO uint32_t CLK_APB1_BUS_CFG; /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */\r
- __I uint32_t CLK_APB1_BUS_STAT; /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */\r
- __IO uint32_t CLK_APB1_MOTOCONPWM_CFG; /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */\r
- __I uint32_t CLK_APB1_MOTOCONPWM_STAT; /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */\r
- __IO uint32_t CLK_ABP1_I2C0_CFG; /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */\r
- __I uint32_t CLK_APB1_I2C0_STAT; /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */\r
- __IO uint32_t CLK_APB1_I2S_CFG; /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */\r
- __I uint32_t CLK_APB1_I2S_STAT; /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */\r
- __IO uint32_t CLK_APB1_CAN1_CFG; /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */\r
- __I uint32_t CLK_APB1_CAN1_STAT; /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */\r
- __I uint32_t RESERVED2[54];\r
- __IO uint32_t CLK_SPIFI_CFG; /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */\r
- __I uint32_t CLK_SPIFI_STAT; /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */\r
- __I uint32_t RESERVED3[62];\r
- __IO uint32_t CLK_M3_BUS_CFG; /*!< (@ 0x40051400) CLK_M3_BUS clock configuration register */\r
- __I uint32_t CLK_M3_BUS_STAT; /*!< (@ 0x40051404) CLK_M3_BUSclock status register */\r
- __IO uint32_t CLK_M3_SPIFI_CFG; /*!< (@ 0x40051408) CLK_M3_SPIFI clock configuration register */\r
- __I uint32_t CLK_M3_SPIFI_STAT; /*!< (@ 0x4005140C) CLK_M3_SPIFI clock status register */\r
- __IO uint32_t CLK_M3_GPIO_CFG; /*!< (@ 0x40051410) CLK_M3_GPIO clock configuration register */\r
- __I uint32_t CLK_M3_GPIO_STAT; /*!< (@ 0x40051414) CLK_M3_GPIO clock status register */\r
- __IO uint32_t CLK_M3_LCD_CFG; /*!< (@ 0x40051418) CLK_M3_LCD clock configuration register */\r
- __I uint32_t CLK_M3_LCD_STAT; /*!< (@ 0x4005141C) CLK_M3_LCD clock status register */\r
- __IO uint32_t CLK_M3_ETHERNET_CFG; /*!< (@ 0x40051420) CLK_M3_ETHERNET clock configuration register */\r
- __I uint32_t CLK_M3_ETHERNET_STAT; /*!< (@ 0x40051424) CLK_M3_ETHERNET clock status register */\r
- __IO uint32_t CLK_M3_USB0_CFG; /*!< (@ 0x40051428) CLK_M3_USB0 clock configuration register */\r
- __I uint32_t CLK_M3_USB0_STAT; /*!< (@ 0x4005142C) CLK_M3_USB0 clock status register */\r
- __IO uint32_t CLK_M3_EMC_CFG; /*!< (@ 0x40051430) CLK_M3_EMC clock configuration register */\r
- __I uint32_t CLK_M3_EMC_STAT; /*!< (@ 0x40051434) CLK_M3_EMC clock status register */\r
- __IO uint32_t CLK_M3_SDIO_CFG; /*!< (@ 0x40051438) CLK_M3_SDIO clock configuration register */\r
- __I uint32_t CLK_M3_SDIO_STAT; /*!< (@ 0x4005143C) CLK_M3_SDIO clock status register */\r
- __IO uint32_t CLK_M3_DMA_CFG; /*!< (@ 0x40051440) CLK_M3_DMA clock configuration register */\r
- __I uint32_t CLK_M3_DMA_STAT; /*!< (@ 0x40051444) CLK_M3_DMA clock status register */\r
- __IO uint32_t CLK_M3_M3CORE_CFG; /*!< (@ 0x40051448) CLK_M3_M3CORE clock configuration register */\r
- __I uint32_t CLK_M3_M3CORE_STAT; /*!< (@ 0x4005144C) CLK_M3_M3CORE clock status register */\r
- __I uint32_t RESERVED4[6];\r
- __IO uint32_t CLK_M3_SCT_CFG; /*!< (@ 0x40051468) CLK_M3_SCT clock configuration register */\r
- __I uint32_t CLK_M3_SCT_STAT; /*!< (@ 0x4005146C) CLK_M3_SCT clock status register */\r
- __IO uint32_t CLK_M3_USB1_CFG; /*!< (@ 0x40051470) CLK_M3_USB1 clock configuration register */\r
- __I uint32_t CLK_M3_USB1_STAT; /*!< (@ 0x40051474) CLK_M3_USB1 clock status register */\r
- __IO uint32_t CLK_M3_EMCDIV_CFG; /*!< (@ 0x40051478) CLK_M3_EMCDIV clock configuration register */\r
- __I uint32_t CLK_M3_EMCDIV_STAT; /*!< (@ 0x4005147C) CLK_M3_EMCDIV clock status register */\r
- __I uint32_t RESERVED5[32];\r
- __IO uint32_t CLK_M3_WWDT_CFG; /*!< (@ 0x40051500) CLK_M3_WWDT clock configuration register */\r
- __I uint32_t CLK_M3_WWDT_STAT; /*!< (@ 0x40051504) CLK_M3_WWDT clock status register */\r
- __IO uint32_t CLK_M3_USART0_CFG; /*!< (@ 0x40051508) CLK_M3_USART0 clock configuration register */\r
- __I uint32_t CLK_M3_USART0_STAT; /*!< (@ 0x4005150C) CLK_M3_USART0 clock status register */\r
- __IO uint32_t CLK_M3_UART1_CFG; /*!< (@ 0x40051510) CLK_M3_UART1 clock configuration register */\r
- __I uint32_t CLK_M3_UART1_STAT; /*!< (@ 0x40051514) CLK_M3_UART1 clock status register */\r
- __IO uint32_t CLK_M3_SSP0_CFG; /*!< (@ 0x40051518) CLK_M3_SSP0 clock configuration register */\r
- __I uint32_t CLK_M3_SSP0_STAT; /*!< (@ 0x4005151C) CLK_M3_SSP0 clock status register */\r
- __IO uint32_t CLK_M3_TIMER0_CFG; /*!< (@ 0x40051520) CLK_M3_TIMER0 clock configuration register */\r
- __I uint32_t CLK_M3_TIMER0_STAT; /*!< (@ 0x40051524) CLK_M3_TIMER0 clock status register */\r
- __IO uint32_t CLK_M3_TIMER1_CFG; /*!< (@ 0x40051528) CLK_M3_TIMER1clock configuration register */\r
- __I uint32_t CLK_M3_TIMER1_STAT; /*!< (@ 0x4005152C) CLK_M3_TIMER1 clock status register */\r
- __IO uint32_t CLK_M3_SCU_CFG; /*!< (@ 0x40051530) CLK_M3_SCU clock configuration register */\r
- __I uint32_t CLK_M3_SCU_STAT; /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */\r
- __IO uint32_t CLK_M3_CREG_CFG; /*!< (@ 0x40051538) CLK_M3_CREGclock configuration register */\r
- __I uint32_t CLK_M3_CREG_STAT; /*!< (@ 0x4005153C) CLK_M3_CREG clock status register */\r
- __I uint32_t RESERVED6[48];\r
- __IO uint32_t CLK_M3_RITIMER_CFG; /*!< (@ 0x40051600) CLK_M3_RITIMER clock configuration register */\r
- __I uint32_t CLK_M3_RITIMER_STAT; /*!< (@ 0x40051604) CLK_M3_RITIMER clock status register */\r
- __IO uint32_t CLK_M3_USART2_CFG; /*!< (@ 0x40051608) CLK_M3_USART2 clock configuration register */\r
- __I uint32_t CLK_M3_USART2_STAT; /*!< (@ 0x4005160C) CLK_M3_USART2 clock status register */\r
- __IO uint32_t CLK_M3_USART3_CFG; /*!< (@ 0x40051610) CLK_M3_USART3 clock configuration register */\r
- __I uint32_t CLK_M3_USART3_STAT; /*!< (@ 0x40051614) CLK_M3_USART3 clock status register */\r
- __IO uint32_t CLK_M3_TIMER2_CFG; /*!< (@ 0x40051618) CLK_M3_TIMER2 clock configuration register */\r
- __I uint32_t CLK_M3_TIMER2_STAT; /*!< (@ 0x4005161C) CLK_M3_TIMER2 clock status register */\r
- __IO uint32_t CLK_M3_TIMER3_CFG; /*!< (@ 0x40051620) CLK_M3_TIMER3 clock configuration register */\r
- __I uint32_t CLK_M3_TIMER3_STAT; /*!< (@ 0x40051624) CLK_M3_TIMER3 clock status register */\r
- __IO uint32_t CLK_M3_SSP1_CFG; /*!< (@ 0x40051628) CLK_M3_SSP1 clock configuration register */\r
- __I uint32_t CLK_M3_SSP1_STAT; /*!< (@ 0x4005162C) CLK_M3_SSP1 clock status register */\r
- __IO uint32_t CLK_M3_QEI_CFG; /*!< (@ 0x40051630) CLK_M3_QEIclock configuration register */\r
- __I uint32_t CLK_M3_QEI_STAT; /*!< (@ 0x40051634) CLK_M3_QEI clock status register */\r
- __I uint32_t RESERVED7[114];\r
- __IO uint32_t CLK_USB0_CFG; /*!< (@ 0x40051800) CLK_M3_USB0 clock configuration register */\r
- __I uint32_t CLK_USB0_STAT; /*!< (@ 0x40051804) CLK_USB0 clock status register */\r
- __I uint32_t RESERVED8[62];\r
- __IO uint32_t CLK_USB1_CFG; /*!< (@ 0x40051900) CLK_USB1 clock configuration register */\r
- __I uint32_t CLK_USB1_STAT; /*!< (@ 0x40051904) CLK_USB1 clock status register */\r
- __I uint32_t RESERVED9[126];\r
- __IO uint32_t CLK_VADC_CFG; /*!< (@ 0x40051B00) CLK_VADC clock configuration register */\r
- __I uint32_t CLK_VADC_STAT; /*!< (@ 0x40051B04) CLK_VADC clock status register */\r
-} LPC_CCU1_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- CCU2 -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU2)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40052000) CCU2 Structure */\r
- __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */\r
- __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */\r
- __I uint32_t RESERVED0[62];\r
- __IO uint32_t CLK_APLL_CFG; /*!< (@ 0x40052100) CLK_APLL clock configuration register */\r
- __I uint32_t CLK_APLL_STAT; /*!< (@ 0x40052104) CLK_APLL clock status register */\r
- __I uint32_t RESERVED1[62];\r
- __IO uint32_t CLK_APB2_USART3_CFG; /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */\r
- __I uint32_t CLK_APB2_USART3_STAT; /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */\r
- __I uint32_t RESERVED2[62];\r
- __IO uint32_t CLK_APB2_USART2_CFG; /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */\r
- __I uint32_t CLK_APB2_USART2_STAT; /*!< (@ 0x40052304) CLK_APB2_USART clock status register */\r
- __I uint32_t RESERVED3[62];\r
- __IO uint32_t CLK_APB0_UART1_CFG; /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */\r
- __I uint32_t CLK_APB0_UART1_STAT; /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */\r
- __I uint32_t RESERVED4[62];\r
- __IO uint32_t CLK_APB0_USART0_CFG; /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */\r
- __I uint32_t CLK_APB0_USART0_STAT; /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */\r
- __I uint32_t RESERVED5[62];\r
- __IO uint32_t CLK_APB2_SSP1_CFG; /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */\r
- __I uint32_t CLK_APB2_SSP1_STAT; /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */\r
- __I uint32_t RESERVED6[62];\r
- __IO uint32_t CLK_APB0_SSP0_CFG; /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */\r
- __I uint32_t CLK_APB0_SSP0_STAT; /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */\r
- __I uint32_t RESERVED7[62];\r
- __IO uint32_t CLK_SDIO_CFG; /*!< (@ 0x40052800) CLK_SDIO clock configuration register */\r
- __I uint32_t CLK_SDIO_STAT; /*!< (@ 0x40052804) CLK_SDIO clock status register */\r
-} LPC_CCU2_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- RGU -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13 (RGU)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40053000) RGU Structure */\r
- __I uint32_t RESERVED0[64];\r
- __O uint32_t RESET_CTRL0; /*!< (@ 0x40053100) Reset control register 0 */\r
- __O uint32_t RESET_CTRL1; /*!< (@ 0x40053104) Reset control register 1 */\r
- __I uint32_t RESERVED1[2];\r
- __IO uint32_t RESET_STATUS0; /*!< (@ 0x40053110) Reset status register 0 */\r
- __IO uint32_t RESET_STATUS1; /*!< (@ 0x40053114) Reset status register 1 */\r
- __IO uint32_t RESET_STATUS2; /*!< (@ 0x40053118) Reset status register 2 */\r
- __IO uint32_t RESET_STATUS3; /*!< (@ 0x4005311C) Reset status register 3 */\r
- __I uint32_t RESERVED2[12];\r
- __I uint32_t RESET_ACTIVE_STATUS0; /*!< (@ 0x40053150) Reset active status register 0 */\r
- __I uint32_t RESET_ACTIVE_STATUS1; /*!< (@ 0x40053154) Reset active status register 1 */\r
- __I uint32_t RESERVED3[170];\r
- __IO uint32_t RESET_EXT_STAT0; /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */\r
- __IO uint32_t RESET_EXT_STAT1; /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */\r
- __IO uint32_t RESET_EXT_STAT2; /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */\r
- __I uint32_t RESERVED4;\r
- __IO uint32_t RESET_EXT_STAT4; /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */\r
- __IO uint32_t RESET_EXT_STAT5; /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */\r
- __I uint32_t RESERVED5[2];\r
- __IO uint32_t RESET_EXT_STAT8; /*!< (@ 0x40053420) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT9; /*!< (@ 0x40053424) Reset external status register */\r
- __I uint32_t RESERVED6[3];\r
- __IO uint32_t RESET_EXT_STAT13; /*!< (@ 0x40053434) Reset external status register */\r
- __I uint32_t RESERVED7[2];\r
- __IO uint32_t RESET_EXT_STAT16; /*!< (@ 0x40053440) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT17; /*!< (@ 0x40053444) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT18; /*!< (@ 0x40053448) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT19; /*!< (@ 0x4005344C) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT20; /*!< (@ 0x40053450) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT21; /*!< (@ 0x40053454) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT22; /*!< (@ 0x40053458) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT23; /*!< (@ 0x4005345C) Reset external status register */\r
- __I uint32_t RESERVED8[4];\r
- __IO uint32_t RESET_EXT_STAT28; /*!< (@ 0x40053470) Reset external status register */\r
- __I uint32_t RESERVED9[3];\r
- __IO uint32_t RESET_EXT_STAT32; /*!< (@ 0x40053480) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT33; /*!< (@ 0x40053484) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT34; /*!< (@ 0x40053488) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT35; /*!< (@ 0x4005348C) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT36; /*!< (@ 0x40053490) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT37; /*!< (@ 0x40053494) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT38; /*!< (@ 0x40053498) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT39; /*!< (@ 0x4005349C) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT40; /*!< (@ 0x400534A0) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT41; /*!< (@ 0x400534A4) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT42; /*!< (@ 0x400534A8) Reset external status register */\r
- __I uint32_t RESERVED10;\r
- __IO uint32_t RESET_EXT_STAT44; /*!< (@ 0x400534B0) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT45; /*!< (@ 0x400534B4) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT46; /*!< (@ 0x400534B8) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT47; /*!< (@ 0x400534BC) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT48; /*!< (@ 0x400534C0) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT49; /*!< (@ 0x400534C4) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT50; /*!< (@ 0x400534C8) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT51; /*!< (@ 0x400534CC) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT52; /*!< (@ 0x400534D0) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT53; /*!< (@ 0x400534D4) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT54; /*!< (@ 0x400534D8) Reset external status register */\r
- __IO uint32_t RESET_EXT_STAT55; /*!< (@ 0x400534DC) Reset external status register */\r
-} LPC_RGU_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- WWDT -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (WWDT)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40080000) WWDT Structure */\r
- __IO uint32_t MOD; /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */\r
- __IO uint32_t TC; /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */\r
- __O uint32_t FEED; /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */\r
- __I uint32_t TV; /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */\r
- __I uint32_t RESERVED0;\r
- __IO uint32_t WARNINT; /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */\r
- __IO uint32_t WINDOW; /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */\r
-} LPC_WWDT_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- USARTn -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (USARTn)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400xx000) USARTn Structure */\r
-\r
- union {\r
- __IO uint32_t DLL; /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */\r
- __O uint32_t THR; /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */\r
- __I uint32_t RBR; /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */\r
- };\r
-\r
- union {\r
- __IO uint32_t IER; /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */\r
- __IO uint32_t DLM; /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */\r
- };\r
-\r
- union {\r
- __O uint32_t FCR; /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */\r
- __I uint32_t IIR; /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */\r
- };\r
- __IO uint32_t LCR; /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */\r
- __I uint32_t RESERVED0[1];\r
- __I uint32_t LSR; /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */\r
- __I uint32_t RESERVED1[1];\r
- __IO uint32_t SCR; /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */\r
- __IO uint32_t ACR; /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */\r
- __IO uint32_t ICR; /*!< (@ 0x400xx024) IrDA control register (UART3 only) */\r
- __IO uint32_t FDR; /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */\r
- __IO uint32_t OSR; /*!< (@ 0x400xx02C) Oversampling Register. Controls the degree of oversampling during each bit time. */\r
- __I uint32_t RESERVED2[4];\r
- __IO uint32_t HDEN; /*!< (@ 0x400xx03C) Half-duplex enable Register */\r
- __I uint32_t RESERVED3[1];\r
- __IO uint32_t SCICTRL; /*!< (@ 0x400xx048) Smart card interface control register */\r
- __IO uint32_t RS485CTRL; /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */\r
- __IO uint32_t RS485ADRMATCH; /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */\r
- __IO uint32_t RS485DLY; /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */\r
- __IO uint32_t SYNCCTRL; /*!< (@ 0x400xx058) Synchronous mode control register. */\r
- __IO uint32_t TER; /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */\r
-} LPC_USARTn_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- UART1 -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (UART1)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40082000) UART1 Structure */\r
-\r
- union {\r
- __IO uint32_t DLL; /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */\r
- __O uint32_t THR; /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */\r
- __I uint32_t RBR; /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */\r
- };\r
-\r
- union {\r
- __IO uint32_t IER; /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */\r
- __IO uint32_t DLM; /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */\r
- };\r
-\r
- union {\r
- __O uint32_t FCR; /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */\r
- __I uint32_t IIR; /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */\r
- };\r
- __IO uint32_t LCR; /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */\r
- __IO uint32_t MCR; /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */\r
- __I uint32_t LSR; /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */\r
- __I uint32_t MSR; /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */\r
- __IO uint32_t SCR; /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */\r
- __IO uint32_t ACR; /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */\r
- __I uint32_t RESERVED0;\r
- __IO uint32_t FDR; /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */\r
- __I uint32_t RESERVED1;\r
- __IO uint32_t TER; /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */\r
- __I uint32_t RESERVED2[6];\r
- __IO uint32_t RS485CTRL; /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */\r
- __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */\r
- __IO uint32_t RS485DLY; /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */\r
- __I uint32_t FIFOLVL; /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */\r
-} LPC_UART1_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- SSPn -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (SSP0)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400xx000) SSPn Structure */\r
- __IO uint32_t CR0; /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */\r
- __IO uint32_t CR1; /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */\r
- __IO uint32_t DR; /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */\r
- __I uint32_t SR; /*!< (@ 0x400xx00C) Status Register */\r
- __IO uint32_t CPSR; /*!< (@ 0x400xx010) Clock Prescale Register */\r
- __IO uint32_t IMSC; /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */\r
- __I uint32_t RIS; /*!< (@ 0x400xx018) Raw Interrupt Status Register */\r
- __I uint32_t MIS; /*!< (@ 0x400xx01C) Masked Interrupt Status Register */\r
- __O uint32_t ICR; /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */\r
- __IO uint32_t DMACR; /*!< (@ 0x400xx024) SSPn DMA control register */\r
-} LPC_SSPn_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- TIMERn -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (TIMERn)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400xx000) TIMERn Structure */\r
- __IO uint32_t IR; /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */\r
- __IO uint32_t TCR; /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */\r
- __IO uint32_t TC; /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */\r
- __IO uint32_t PR; /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */\r
- __IO uint32_t PC; /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */\r
- __IO uint32_t MCR; /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */\r
- __IO uint32_t MR[4]; /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */\r
- __IO uint32_t CCR; /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */\r
- __IO uint32_t CR[4]; /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */\r
- __IO uint32_t EMR; /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */\r
- __I uint32_t RESERVED0[12];\r
- __IO uint32_t CTCR; /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */\r
-} LPC_TIMERn_Type;\r
-\r
-\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- SCU -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10 (SCU)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40086000) SCU Structure */\r
- __IO uint32_t SFSP0_0; /*!< (@ 0x40086000) Pin configuration register for pins P0 */\r
- __IO uint32_t SFSP0_1; /*!< (@ 0x40086004) Pin configuration register for pins P0 */\r
- __I uint32_t RESERVED0[30];\r
- __IO uint32_t SFSP1_0; /*!< (@ 0x40086080) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_1; /*!< (@ 0x40086084) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_2; /*!< (@ 0x40086088) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_3; /*!< (@ 0x4008608C) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_4; /*!< (@ 0x40086090) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_5; /*!< (@ 0x40086094) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_6; /*!< (@ 0x40086098) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_7; /*!< (@ 0x4008609C) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_8; /*!< (@ 0x400860A0) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_9; /*!< (@ 0x400860A4) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_10; /*!< (@ 0x400860A8) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_11; /*!< (@ 0x400860AC) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_12; /*!< (@ 0x400860B0) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_13; /*!< (@ 0x400860B4) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_14; /*!< (@ 0x400860B8) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_15; /*!< (@ 0x400860BC) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_16; /*!< (@ 0x400860C0) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_17; /*!< (@ 0x400860C4) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_18; /*!< (@ 0x400860C8) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_19; /*!< (@ 0x400860CC) Pin configuration register for pins P1 */\r
- __IO uint32_t SFSP1_20; /*!< (@ 0x400860D0) Pin configuration register for pins P1 */\r
- __I uint32_t RESERVED1[11];\r
- __IO uint32_t SFSP2_0; /*!< (@ 0x40086100) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_1; /*!< (@ 0x40086104) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_2; /*!< (@ 0x40086108) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_3; /*!< (@ 0x4008610C) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_4; /*!< (@ 0x40086110) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_5; /*!< (@ 0x40086114) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_6; /*!< (@ 0x40086118) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_7; /*!< (@ 0x4008611C) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_8; /*!< (@ 0x40086120) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_9; /*!< (@ 0x40086124) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_10; /*!< (@ 0x40086128) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_11; /*!< (@ 0x4008612C) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_12; /*!< (@ 0x40086130) Pin configuration register for pins P2 */\r
- __IO uint32_t SFSP2_13; /*!< (@ 0x40086134) Pin configuration register for pins P2 */\r
- __I uint32_t RESERVED2[18];\r
- __IO uint32_t SFSP3_0; /*!< (@ 0x40086180) Pin configuration register for pins P3 */\r
- __IO uint32_t SFSP3_1; /*!< (@ 0x40086184) Pin configuration register for pins P3 */\r
- __IO uint32_t SFSP3_2; /*!< (@ 0x40086188) Pin configuration register for pins P3 */\r
- __IO uint32_t SFSP3_3; /*!< (@ 0x4008618C) Pin configuration register for pins P3 */\r
- __IO uint32_t SFSP3_4; /*!< (@ 0x40086190) Pin configuration register for pins P3 */\r
- __IO uint32_t SFSP3_5; /*!< (@ 0x40086194) Pin configuration register for pins P3 */\r
- __IO uint32_t SFSP3_6; /*!< (@ 0x40086198) Pin configuration register for pins P3 */\r
- __IO uint32_t SFSP3_7; /*!< (@ 0x4008619C) Pin configuration register for pins P3 */\r
- __IO uint32_t SFSP3_8; /*!< (@ 0x400861A0) Pin configuration register for pins P3 */\r
- __I uint32_t RESERVED3[23];\r
- __IO uint32_t SFSP4_0; /*!< (@ 0x40086200) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_1; /*!< (@ 0x40086204) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_2; /*!< (@ 0x40086208) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_3; /*!< (@ 0x4008620C) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_4; /*!< (@ 0x40086210) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_5; /*!< (@ 0x40086214) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_6; /*!< (@ 0x40086218) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_7; /*!< (@ 0x4008621C) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_8; /*!< (@ 0x40086220) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_9; /*!< (@ 0x40086224) Pin configuration register for pins P4 */\r
- __IO uint32_t SFSP4_10; /*!< (@ 0x40086228) Pin configuration register for pins P4 */\r
- __I uint32_t RESERVED4[21];\r
- __IO uint32_t SFSP5_0; /*!< (@ 0x40086280) Pin configuration register for pins P5 */\r
- __IO uint32_t SFSP5_1; /*!< (@ 0x40086284) Pin configuration register for pins P5 */\r
- __IO uint32_t SFSP5_2; /*!< (@ 0x40086288) Pin configuration register for pins P5 */\r
- __IO uint32_t SFSP5_3; /*!< (@ 0x4008628C) Pin configuration register for pins P5 */\r
- __IO uint32_t SFSP5_4; /*!< (@ 0x40086290) Pin configuration register for pins P5 */\r
- __IO uint32_t SFSP5_5; /*!< (@ 0x40086294) Pin configuration register for pins P5 */\r
- __IO uint32_t SFSP5_6; /*!< (@ 0x40086298) Pin configuration register for pins P5 */\r
- __IO uint32_t SFSP5_7; /*!< (@ 0x4008629C) Pin configuration register for pins P5 */\r
- __I uint32_t RESERVED5[24];\r
- __IO uint32_t SFSP6_0; /*!< (@ 0x40086300) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_1; /*!< (@ 0x40086304) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_2; /*!< (@ 0x40086308) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_3; /*!< (@ 0x4008630C) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_4; /*!< (@ 0x40086310) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_5; /*!< (@ 0x40086314) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_6; /*!< (@ 0x40086318) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_7; /*!< (@ 0x4008631C) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_8; /*!< (@ 0x40086320) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_9; /*!< (@ 0x40086324) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_10; /*!< (@ 0x40086328) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_11; /*!< (@ 0x4008632C) Pin configuration register for pins P6 */\r
- __IO uint32_t SFSP6_12; /*!< (@ 0x40086330) Pin configuration register for pins P6 */\r
- __I uint32_t RESERVED6[19];\r
- __IO uint32_t SFSP7_0; /*!< (@ 0x40086380) Pin configuration register for pins P7 */\r
- __IO uint32_t SFSP7_1; /*!< (@ 0x40086384) Pin configuration register for pins P7 */\r
- __IO uint32_t SFSP7_2; /*!< (@ 0x40086388) Pin configuration register for pins P7 */\r
- __IO uint32_t SFSP7_3; /*!< (@ 0x4008638C) Pin configuration register for pins P7 */\r
- __IO uint32_t SFSP7_4; /*!< (@ 0x40086390) Pin configuration register for pins P7 */\r
- __IO uint32_t SFSP7_5; /*!< (@ 0x40086394) Pin configuration register for pins P7 */\r
- __IO uint32_t SFSP7_6; /*!< (@ 0x40086398) Pin configuration register for pins P7 */\r
- __IO uint32_t SFSP7_7; /*!< (@ 0x4008639C) Pin configuration register for pins P7 */\r
- __I uint32_t RESERVED7[24];\r
- __IO uint32_t SFSP8_0; /*!< (@ 0x40086400) Pin configuration register for pins P8 */\r
- __IO uint32_t SFSP8_1; /*!< (@ 0x40086404) Pin configuration register for pins P8 */\r
- __IO uint32_t SFSP8_2; /*!< (@ 0x40086408) Pin configuration register for pins P8 */\r
- __IO uint32_t SFSP8_3; /*!< (@ 0x4008640C) Pin configuration register for pins P8 */\r
- __IO uint32_t SFSP8_4; /*!< (@ 0x40086410) Pin configuration register for pins P8 */\r
- __IO uint32_t SFSP8_5; /*!< (@ 0x40086414) Pin configuration register for pins P8 */\r
- __IO uint32_t SFSP8_6; /*!< (@ 0x40086418) Pin configuration register for pins P8 */\r
- __IO uint32_t SFSP8_7; /*!< (@ 0x4008641C) Pin configuration register for pins P8 */\r
- __IO uint32_t SFSP8_8; /*!< (@ 0x40086420) Pin configuration register for pins P8 */\r
- __I uint32_t RESERVED8[23];\r
- __IO uint32_t SFSP9_0; /*!< (@ 0x40086480) Pin configuration register for pins P9 */\r
- __IO uint32_t SFSP9_1; /*!< (@ 0x40086484) Pin configuration register for pins P9 */\r
- __IO uint32_t SFSP9_2; /*!< (@ 0x40086488) Pin configuration register for pins P9 */\r
- __IO uint32_t SFSP9_3; /*!< (@ 0x4008648C) Pin configuration register for pins P9 */\r
- __IO uint32_t SFSP9_4; /*!< (@ 0x40086490) Pin configuration register for pins P9 */\r
- __IO uint32_t SFSP9_5; /*!< (@ 0x40086494) Pin configuration register for pins P9 */\r
- __IO uint32_t SFSP9_6; /*!< (@ 0x40086498) Pin configuration register for pins P9 */\r
- __I uint32_t RESERVED9[25];\r
- __IO uint32_t SFSPA_0; /*!< (@ 0x40086500) Pin configuration register for pins PA */\r
- __IO uint32_t SFSPA_1; /*!< (@ 0x40086504) Pin configuration register for pins PA */\r
- __IO uint32_t SFSPA_2; /*!< (@ 0x40086508) Pin configuration register for pins PA */\r
- __IO uint32_t SFSPA_3; /*!< (@ 0x4008650C) Pin configuration register for pins PA */\r
- __IO uint32_t SFSPA_4; /*!< (@ 0x40086510) Pin configuration register for pins PA */\r
- __I uint32_t RESERVED10[27];\r
- __IO uint32_t SFSPB_0; /*!< (@ 0x40086580) Pin configuration register for pins PB */\r
- __IO uint32_t SFSPB_1; /*!< (@ 0x40086584) Pin configuration register for pins PB */\r
- __IO uint32_t SFSPB_2; /*!< (@ 0x40086588) Pin configuration register for pins PB */\r
- __IO uint32_t SFSPB_3; /*!< (@ 0x4008658C) Pin configuration register for pins PB */\r
- __IO uint32_t SFSPB_4; /*!< (@ 0x40086590) Pin configuration register for pins PB */\r
- __IO uint32_t SFSPB_5; /*!< (@ 0x40086594) Pin configuration register for pins PB */\r
- __IO uint32_t SFSPB_6; /*!< (@ 0x40086598) Pin configuration register for pins PB */\r
- __I uint32_t RESERVED11[25];\r
- __IO uint32_t SFSPC_0; /*!< (@ 0x40086600) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_1; /*!< (@ 0x40086604) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_2; /*!< (@ 0x40086608) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_3; /*!< (@ 0x4008660C) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_4; /*!< (@ 0x40086610) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_5; /*!< (@ 0x40086614) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_6; /*!< (@ 0x40086618) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_7; /*!< (@ 0x4008661C) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_8; /*!< (@ 0x40086620) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_9; /*!< (@ 0x40086624) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_10; /*!< (@ 0x40086628) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_11; /*!< (@ 0x4008662C) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_12; /*!< (@ 0x40086630) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_13; /*!< (@ 0x40086634) Pin configuration register for pins PC */\r
- __IO uint32_t SFSPC_14; /*!< (@ 0x40086638) Pin configuration register for pins PC */\r
- __I uint32_t RESERVED12[17];\r
- __IO uint32_t SFSPD_0; /*!< (@ 0x40086680) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_1; /*!< (@ 0x40086684) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_2; /*!< (@ 0x40086688) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_3; /*!< (@ 0x4008668C) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_4; /*!< (@ 0x40086690) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_5; /*!< (@ 0x40086694) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_6; /*!< (@ 0x40086698) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_7; /*!< (@ 0x4008669C) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_8; /*!< (@ 0x400866A0) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_9; /*!< (@ 0x400866A4) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_10; /*!< (@ 0x400866A8) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_11; /*!< (@ 0x400866AC) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_12; /*!< (@ 0x400866B0) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_13; /*!< (@ 0x400866B4) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_14; /*!< (@ 0x400866B8) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_15; /*!< (@ 0x400866BC) Pin configuration register for pins PD */\r
- __IO uint32_t SFSPD_16; /*!< (@ 0x400866C0) Pin configuration register for pins PD */\r
- __I uint32_t RESERVED13[15];\r
- __IO uint32_t SFSPE_0; /*!< (@ 0x40086700) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_1; /*!< (@ 0x40086704) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_2; /*!< (@ 0x40086708) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_3; /*!< (@ 0x4008670C) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_4; /*!< (@ 0x40086710) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_5; /*!< (@ 0x40086714) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_6; /*!< (@ 0x40086718) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_7; /*!< (@ 0x4008671C) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_8; /*!< (@ 0x40086720) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_9; /*!< (@ 0x40086724) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_10; /*!< (@ 0x40086728) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_11; /*!< (@ 0x4008672C) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_12; /*!< (@ 0x40086730) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_13; /*!< (@ 0x40086734) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_14; /*!< (@ 0x40086738) Pin configuration register for pins PE */\r
- __IO uint32_t SFSPE_15; /*!< (@ 0x4008673C) Pin configuration register for pins PE */\r
- __I uint32_t RESERVED14[16];\r
- __IO uint32_t SFSPF_0; /*!< (@ 0x40086780) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_1; /*!< (@ 0x40086784) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_2; /*!< (@ 0x40086788) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_3; /*!< (@ 0x4008678C) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_4; /*!< (@ 0x40086790) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_5; /*!< (@ 0x40086794) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_6; /*!< (@ 0x40086798) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_7; /*!< (@ 0x4008679C) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_8; /*!< (@ 0x400867A0) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_9; /*!< (@ 0x400867A4) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_10; /*!< (@ 0x400867A8) Pin configuration register for pins PF */\r
- __IO uint32_t SFSPF_11; /*!< (@ 0x400867AC) Pin configuration register for pins PF */\r
- __I uint32_t RESERVED15[276];\r
- __IO uint32_t SFSCLK_0; /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */\r
- __IO uint32_t SFSCLK_1; /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */\r
- __IO uint32_t SFSCLK_2; /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */\r
- __IO uint32_t SFSCLK_3; /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */\r
- __I uint32_t RESERVED16[28];\r
- __IO uint32_t SFSUSB; /*!< (@ 0x40086C80) Pin configuration register for */\r
- __IO uint32_t SFSI2C0; /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */\r
- __IO uint32_t ENAIO0; /*!< (@ 0x40086C88) ADC0 function select register */\r
- __IO uint32_t ENAIO1; /*!< (@ 0x40086C8C) ADC1 function select register */\r
- __IO uint32_t ENAIO2; /*!< (@ 0x40086C90) Analog function select register */\r
- __I uint32_t RESERVED17[27];\r
- __IO uint32_t EMCDELAYCLK; /*!< (@ 0x40086D00) EMC clock delay register */\r
- __I uint32_t RESERVED18[63];\r
- __IO uint32_t PINTSEL0; /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */\r
- __IO uint32_t PINTSEL1; /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */\r
-} LPC_SCU_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GPIO_PIN_INT -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief GPIO pin interrupt (GPIO_PIN_INT)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40087000) GPIO_PIN_INT Structure */\r
- __IO uint32_t ISEL; /*!< (@ 0x40087000) Pin Interrupt Mode register */\r
- __IO uint32_t IENR; /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */\r
- __O uint32_t SIENR; /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */\r
- __O uint32_t CIENR; /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */\r
- __IO uint32_t IENF; /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */\r
- __O uint32_t SIENF; /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */\r
- __O uint32_t CIENF; /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */\r
- __IO uint32_t RISE; /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */\r
- __IO uint32_t FALL; /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */\r
- __IO uint32_t IST; /*!< (@ 0x40087024) Pin Interrupt Status register */\r
-} LPC_GPIO_PIN_INT_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GPIO_GROUP_INTn -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */\r
- __IO uint32_t CTRL; /*!< (@ 0x40088000) GPIO grouped interrupt control register */\r
- __I uint32_t RESERVED0[7];\r
- __IO uint32_t PORT_POL0; /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */\r
- __IO uint32_t PORT_POL1; /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */\r
- __IO uint32_t PORT_POL2; /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */\r
- __IO uint32_t PORT_POL3; /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */\r
- __IO uint32_t PORT_POL4; /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */\r
- __IO uint32_t PORT_POL5; /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */\r
- __IO uint32_t PORT_POL6; /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */\r
- __IO uint32_t PORT_POL7; /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */\r
- __IO uint32_t PORT_ENA0; /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */\r
- __IO uint32_t PORT_ENA1; /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */\r
- __IO uint32_t PORT_ENA2; /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */\r
- __IO uint32_t PORT_ENA3; /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */\r
- __IO uint32_t PORT_ENA4; /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */\r
- __IO uint32_t PORT_ENA5; /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */\r
- __IO uint32_t PORT_ENA6; /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */\r
- __IO uint32_t PORT_ENA7; /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */\r
-} LPC_GPIO_GROUP_INTn_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- MCPWM -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7 (MCPWM)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400A0000) MCPWM Structure */\r
- __I uint32_t CON; /*!< (@ 0x400A0000) PWM Control read address */\r
- __O uint32_t CON_SET; /*!< (@ 0x400A0004) PWM Control set address */\r
- __O uint32_t CON_CLR; /*!< (@ 0x400A0008) PWM Control clear address */\r
- __I uint32_t CAPCON; /*!< (@ 0x400A000C) Capture Control read address */\r
- __O uint32_t CAPCON_SET; /*!< (@ 0x400A0010) Capture Control set address */\r
- __O uint32_t CAPCON_CLR; /*!< (@ 0x400A0014) Event Control clear address */\r
- __IO uint32_t TC[3]; /*!< (@ 0x400A0018) Timer Counter register */\r
- __IO uint32_t LIM[3]; /*!< (@ 0x400A0024) Limit register */\r
- __IO uint32_t MAT[3]; /*!< (@ 0x400A0030) Match register */\r
- __IO uint32_t DT; /*!< (@ 0x400A003C) Dead time register */\r
- __IO uint32_t CCP; /*!< (@ 0x400A0040) Communication Pattern register */\r
- __I uint32_t CAP[3]; /*!< (@ 0x400A0044) Capture register */\r
- __I uint32_t INTEN; /*!< (@ 0x400A0050) Interrupt Enable read address */\r
- __O uint32_t INTEN_SET; /*!< (@ 0x400A0054) Interrupt Enable set address */\r
- __O uint32_t INTEN_CLR; /*!< (@ 0x400A0058) Interrupt Enable clear address */\r
- __I uint32_t CNTCON; /*!< (@ 0x400A005C) Count Control read address */\r
- __O uint32_t CNTCON_SET; /*!< (@ 0x400A0060) Count Control set address */\r
- __O uint32_t CNTCON_CLR; /*!< (@ 0x400A0064) Count Control clear address */\r
- __I uint32_t INTF; /*!< (@ 0x400A0068) Interrupt flags read address */\r
- __O uint32_t INTF_SET; /*!< (@ 0x400A006C) Interrupt flags set address */\r
- __O uint32_t INTF_CLR; /*!< (@ 0x400A0070) Interrupt flags clear address */\r
- __O uint32_t CAP_CLR; /*!< (@ 0x400A0074) Capture clear address */\r
-} LPC_MCPWM_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- I2C0 -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx I2C0/1-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Cn)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400xx000) I2C0 Structure */\r
- __IO uint32_t CONSET; /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */\r
- __I uint32_t STAT; /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */\r
- __IO uint32_t DAT; /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */\r
- __IO uint32_t ADR0; /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
- __IO uint32_t SCLH; /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */\r
- __IO uint32_t SCLL; /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */\r
- __O uint32_t CONCLR; /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */\r
- __IO uint32_t MMCTRL; /*!< (@ 0x400xx01C) Monitor mode control register. */\r
- __IO uint32_t ADR1; /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
- __IO uint32_t ADR2; /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
- __IO uint32_t ADR3; /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
- __I uint32_t DATA_BUFFER; /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */\r
- __IO uint32_t MASK[4]; /*!< (@ 0x400xx030) I2C Slave address mask register */\r
-} LPC_I2Cn_Type;\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- I2Sn -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Sn)\r
- 0x400A2000 / 0x400A3000\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400Ax000) I2S Structure */\r
- __IO uint32_t DAO; /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */\r
- __IO uint32_t DAI; /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */\r
- __O uint32_t TXFIFO; /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */\r
- __I uint32_t RXFIFO; /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */\r
- __I uint32_t STATE; /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */\r
- __IO uint32_t DMA1; /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */\r
- __IO uint32_t DMA2; /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */\r
- __IO uint32_t IRQ; /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */\r
- __IO uint32_t TXRATE; /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */\r
- __IO uint32_t RXRATE; /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */\r
- __IO uint32_t TXBITRATE; /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */\r
- __IO uint32_t RXBITRATE; /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */\r
- __IO uint32_t TXMODE; /*!< (@ 0x400Ax030) I2S Transmit mode control. */\r
- __IO uint32_t RXMODE; /*!< (@ 0x400Ax034) I2S Receive mode control. */\r
-} LPC_I2Sn_Type;\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- C_CANn -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7 (C_CANn)\r
- 0x400A4000 / 0x400E2000\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400E2000) C_CAN Structure */\r
- __IO uint32_t CNTL; /*!< (@ 0x400E2000) CAN control */\r
- __IO uint32_t STAT; /*!< (@ 0x400E2004) Status register */\r
- __I uint32_t EC; /*!< (@ 0x400E2008) Error counter */\r
- __IO uint32_t BT; /*!< (@ 0x400E200C) Bit timing register */\r
- __I uint32_t INT; /*!< (@ 0x400E2010) Interrupt register */\r
- __IO uint32_t TEST; /*!< (@ 0x400E2014) Test register */\r
- __IO uint32_t BRPE; /*!< (@ 0x400E2018) Baud rate prescaler extension register */\r
- __I uint32_t RESERVED0;\r
- __IO uint32_t IF1_CMDREQ; /*!< (@ 0x400E2020) Message interface command request */\r
-\r
- union {\r
- __IO uint32_t IF1_CMDMSK_R; /*!< (@ 0x400E2024) Message interface command mask (read direction) */\r
- __IO uint32_t IF1_CMDMSK_W; /*!< (@ 0x400E2024) Message interface command mask (write direction) */\r
- };\r
- __IO uint32_t IF1_MSK1; /*!< (@ 0x400E2028) Message interface mask 1 */\r
- __IO uint32_t IF1_MSK2; /*!< (@ 0x400E202C) Message interface 1 mask 2 */\r
- __IO uint32_t IF1_ARB1; /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */\r
- __IO uint32_t IF1_ARB2; /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */\r
- __IO uint32_t IF1_MCTRL; /*!< (@ 0x400E2038) Message interface 1 message control */\r
- __IO uint32_t IF1_DA1; /*!< (@ 0x400E203C) Message interface data A1 */\r
- __IO uint32_t IF1_DA2; /*!< (@ 0x400E2040) Message interface 1 data A2 */\r
- __IO uint32_t IF1_DB1; /*!< (@ 0x400E2044) Message interface 1 data B1 */\r
- __IO uint32_t IF1_DB2; /*!< (@ 0x400E2048) Message interface 1 data B2 */\r
- __I uint32_t RESERVED1[13];\r
- __IO uint32_t IF2_CMDREQ; /*!< (@ 0x400E2080) Message interface command request */\r
-\r
- union {\r
- __IO uint32_t IF2_CMDMSK_R; /*!< (@ 0x400E2084) Message interface command mask (read direction) */\r
- __IO uint32_t IF2_CMDMSK_W; /*!< (@ 0x400E2084) Message interface command mask (write direction) */\r
- };\r
- __IO uint32_t IF2_MSK1; /*!< (@ 0x400E2088) Message interface mask 1 */\r
- __IO uint32_t IF2_MSK2; /*!< (@ 0x400E208C) Message interface 1 mask 2 */\r
- __IO uint32_t IF2_ARB1; /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */\r
- __IO uint32_t IF2_ARB2; /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */\r
- __IO uint32_t IF2_MCTRL; /*!< (@ 0x400E2098) Message interface 1 message control */\r
- __IO uint32_t IF2_DA1; /*!< (@ 0x400E209C) Message interface data A1 */\r
- __IO uint32_t IF2_DA2; /*!< (@ 0x400E20A0) Message interface 1 data A2 */\r
- __IO uint32_t IF2_DB1; /*!< (@ 0x400E20A4) Message interface 1 data B1 */\r
- __IO uint32_t IF2_DB2; /*!< (@ 0x400E20A8) Message interface 1 data B2 */\r
- __I uint32_t RESERVED2[21];\r
- __I uint32_t TXREQ1; /*!< (@ 0x400E2100) Transmission request 1 */\r
- __I uint32_t TXREQ2; /*!< (@ 0x400E2104) Transmission request 2 */\r
- __I uint32_t RESERVED3[6];\r
- __I uint32_t ND1; /*!< (@ 0x400E2120) New data 1 */\r
- __I uint32_t ND2; /*!< (@ 0x400E2124) New data 2 */\r
- __I uint32_t RESERVED4[6];\r
- __I uint32_t IR1; /*!< (@ 0x400E2140) Interrupt pending 1 */\r
- __I uint32_t IR2; /*!< (@ 0x400E2144) Interrupt pending 2 */\r
- __I uint32_t RESERVED5[6];\r
- __I uint32_t MSGV1; /*!< (@ 0x400E2160) Message valid 1 */\r
- __I uint32_t MSGV2; /*!< (@ 0x400E2164) Message valid 2 */\r
- __I uint32_t RESERVED6[6];\r
- __IO uint32_t CLKDIV; /*!< (@ 0x400E2180) CAN clock divider register */\r
-} LPC_C_CANn_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- RITIMER -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (RITIMER)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400C0000) RITIMER Structure */\r
- __IO uint32_t COMPVAL; /*!< (@ 0x400C0000) Compare register */\r
- __IO uint32_t MASK; /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */\r
- __IO uint32_t CTRL; /*!< (@ 0x400C0008) Control register. */\r
- __IO uint32_t COUNTER; /*!< (@ 0x400C000C) 32-bit counter */\r
-} LPC_RITIMER_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- QEI -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7 (QEI)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400C6000) QEI Structure */\r
- __O uint32_t CON; /*!< (@ 0x400C6000) Control register */\r
- __I uint32_t STAT; /*!< (@ 0x400C6004) Encoder status register */\r
- __IO uint32_t CONF; /*!< (@ 0x400C6008) Configuration register */\r
- __I uint32_t POS; /*!< (@ 0x400C600C) Position register */\r
- __IO uint32_t MAXPOS; /*!< (@ 0x400C6010) Maximum position register */\r
- __IO uint32_t CMPOS0; /*!< (@ 0x400C6014) position compare register 0 */\r
- __IO uint32_t CMPOS1; /*!< (@ 0x400C6018) position compare register 1 */\r
- __IO uint32_t CMPOS2; /*!< (@ 0x400C601C) position compare register 2 */\r
- __I uint32_t INXCNT; /*!< (@ 0x400C6020) Index count register */\r
- __IO uint32_t INXCMP0; /*!< (@ 0x400C6024) Index compare register 0 */\r
- __IO uint32_t LOAD; /*!< (@ 0x400C6028) Velocity timer reload register */\r
- __I uint32_t TIME; /*!< (@ 0x400C602C) Velocity timer register */\r
- __I uint32_t VEL; /*!< (@ 0x400C6030) Velocity counter register */\r
- __I uint32_t CAP; /*!< (@ 0x400C6034) Velocity capture register */\r
- __IO uint32_t VELCOMP; /*!< (@ 0x400C6038) Velocity compare register */\r
- __IO uint32_t FILTERPHA; /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */\r
- __IO uint32_t FILTERPHB; /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */\r
- __IO uint32_t FILTERINX; /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */\r
- __IO uint32_t WINDOW; /*!< (@ 0x400C6048) Index acceptance window register */\r
- __IO uint32_t INXCMP1; /*!< (@ 0x400C604C) Index compare register 1 */\r
- __IO uint32_t INXCMP2; /*!< (@ 0x400C6050) Index compare register 2 */\r
- __I uint32_t RESERVED0[993];\r
- __O uint32_t IEC; /*!< (@ 0x400C6FD8) Interrupt enable clear register */\r
- __O uint32_t IES; /*!< (@ 0x400C6FDC) Interrupt enable set register */\r
- __I uint32_t INTSTAT; /*!< (@ 0x400C6FE0) Interrupt status register */\r
- __I uint32_t IE; /*!< (@ 0x400C6FE4) Interrupt enable register */\r
- __O uint32_t CLR; /*!< (@ 0x400C6FE8) Interrupt status clear register */\r
- __O uint32_t SET; /*!< (@ 0x400C6FEC) Interrupt status set register */\r
-} LPC_QEI_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GIMA -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=Falcon Chapter title=Global Input Multiplexer Array (GIMA) Modification date=3/25/2011 Major revision=0 Minor revision=4 (GIMA)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400C7000) GIMA Structure */\r
- __IO uint32_t CAP0_0_IN; /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */\r
- __IO uint32_t CAP0_1_IN; /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */\r
- __IO uint32_t CAP0_2_IN; /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */\r
- __IO uint32_t CAP0_3_IN; /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */\r
- __IO uint32_t CAP1_0_IN; /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */\r
- __IO uint32_t CAP1_1_IN; /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */\r
- __IO uint32_t CAP1_2_IN; /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */\r
- __IO uint32_t CAP1_3_IN; /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */\r
- __IO uint32_t CAP2_0_IN; /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */\r
- __IO uint32_t CAP2_1_IN; /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */\r
- __IO uint32_t CAP2_2_IN; /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */\r
- __IO uint32_t CAP2_3_IN; /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */\r
- __IO uint32_t CAP3_0_IN; /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */\r
- __IO uint32_t CAP3_1_IN; /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */\r
- __IO uint32_t CAP3_2_IN; /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */\r
- __IO uint32_t CAP3_3_IN; /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */\r
- __IO uint32_t CTIN_0_IN; /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */\r
- __IO uint32_t CTIN_1_IN; /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */\r
- __IO uint32_t CTIN_2_IN; /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */\r
- __IO uint32_t CTIN_3_IN; /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */\r
- __IO uint32_t CTIN_4_IN; /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */\r
- __IO uint32_t CTIN_5_IN; /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */\r
- __IO uint32_t CTIN_6_IN; /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */\r
- __IO uint32_t CTIN_7_IN; /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */\r
- __IO uint32_t VADC_TRIGGER_IN; /*!< (@ 0x400C7060) VADC trigger input multiplexer (GIMA output 24) */\r
- __IO uint32_t EVENTROUTER_13_IN; /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */\r
- __IO uint32_t EVENTROUTER_14_IN; /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */\r
- __IO uint32_t EVENTROUTER_16_IN; /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */\r
- __IO uint32_t ADCSTART0_IN; /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */\r
- __IO uint32_t ADCSTART1_IN; /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */\r
-} LPC_GIMA_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- DAC -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7 (DAC)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400E1000) DAC Structure */\r
- __IO uint32_t CR; /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */\r
- __IO uint32_t CTRL; /*!< (@ 0x400E1004) DAC control register. */\r
- __IO uint32_t CNTVAL; /*!< (@ 0x400E1008) DAC counter value register. */\r
-} LPC_DAC_Type;\r
-\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- ADCn -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7 (ADCn)\r
- 0x400E3000 / 0x400E4000\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400Ex000) ADCn Structure */\r
- __IO uint32_t CR; /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */\r
- __I uint32_t GDR; /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */\r
- __I uint32_t RESERVED0;\r
- __IO uint32_t INTEN; /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */\r
- __I uint32_t DR[8]; /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */\r
- __I uint32_t STAT; /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */\r
-} LPC_ADCn_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GPIO_PORT -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
- * @brief GPIO port (GPIO_PORT)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x400F4000) GPIO_PORT Structure */\r
- __IO uint8_t B[256]; /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */\r
- __I uint32_t RESERVED0[960];\r
- __IO uint32_t W[256]; /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */\r
- __I uint32_t RESERVED1[768];\r
- __IO uint32_t DIR[8]; /*!< (@ 0x400F6000) Direction registers port n */\r
- __I uint32_t RESERVED2[24];\r
- __IO uint32_t MASK[8]; /*!< (@ 0x400F6080) Mask register port n */\r
- __I uint32_t RESERVED3[24];\r
- __IO uint32_t PIN[8]; /*!< (@ 0x400F6100) Portpin register port n */\r
- __I uint32_t RESERVED4[24];\r
- __IO uint32_t MPIN[8]; /*!< (@ 0x400F6180) Masked port register port n */\r
- __I uint32_t RESERVED5[24];\r
- __IO uint32_t SET[8]; /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */\r
- __I uint32_t RESERVED6[24];\r
- __O uint32_t CLR[8]; /*!< (@ 0x400F6280) Clear port n */\r
- __I uint32_t RESERVED7[24];\r
- __O uint32_t NOT[8]; /*!< (@ 0x400F6300) Toggle port n */\r
-} LPC_GPIO_PORT_Type;\r
-\r
-\r
-\r
-/********************************************\r
-** End of section using anonymous unions **\r
-*********************************************/\r
-\r
-#if defined(__ARMCC_VERSION)\r
- #pragma pop\r
-#elif defined(__CWCC__)\r
- #pragma pop\r
-#elif defined(__GNUC__)\r
- /* leave anonymous unions enabled */\r
-#elif defined(__IAR_SYSTEMS_ICC__)\r
- #pragma pop\r
-#else\r
- #error Not supported compiler type\r
-#endif\r
-\r
-\r
-#ifdef CMSIS_BITPOSITIONS\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- SCT Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- SCT_CONFIG -------------------------------------------\r
-#define SCT_CONFIG_UNIFY_Pos 0 /*!< SCT CONFIG: UNIFY Position */\r
-#define SCT_CONFIG_UNIFY_Msk (0x01UL << SCT_CONFIG_UNIFY_Pos) /*!< SCT CONFIG: UNIFY Mask */\r
-#define SCT_CONFIG_CLKMODE_Pos 1 /*!< SCT CONFIG: CLKMODE Position */\r
-#define SCT_CONFIG_CLKMODE_Msk (0x03UL << SCT_CONFIG_CLKMODE_Pos) /*!< SCT CONFIG: CLKMODE Mask */\r
-#define SCT_CONFIG_CLKSEL_Pos 3 /*!< SCT CONFIG: CLKSEL Position */\r
-#define SCT_CONFIG_CLKSEL_Msk (0x0fUL << SCT_CONFIG_CLKSEL_Pos) /*!< SCT CONFIG: CLKSEL Mask */\r
-#define SCT_CONFIG_NORELAODL_NORELOADU_Pos 7 /*!< SCT CONFIG: NORELAODL_NORELOADU Position */\r
-#define SCT_CONFIG_NORELAODL_NORELOADU_Msk (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos) /*!< SCT CONFIG: NORELAODL_NORELOADU Mask */\r
-#define SCT_CONFIG_NORELOADH_Pos 8 /*!< SCT CONFIG: NORELOADH Position */\r
-#define SCT_CONFIG_NORELOADH_Msk (0x01UL << SCT_CONFIG_NORELOADH_Pos) /*!< SCT CONFIG: NORELOADH Mask */\r
-#define SCT_CONFIG_INSYNCn_Pos 9 /*!< SCT CONFIG: INSYNCn Position */\r
-#define SCT_CONFIG_INSYNCn_Msk (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos) /*!< SCT CONFIG: INSYNCn Mask */\r
-\r
-// ---------------------------------------- SCT_CTRL --------------------------------------------\r
-#define SCT_CTRL_DOWN_L_Pos 0 /*!< SCT CTRL: DOWN_L Position */\r
-#define SCT_CTRL_DOWN_L_Msk (0x01UL << SCT_CTRL_DOWN_L_Pos) /*!< SCT CTRL: DOWN_L Mask */\r
-#define SCT_CTRL_STOP_L_Pos 1 /*!< SCT CTRL: STOP_L Position */\r
-#define SCT_CTRL_STOP_L_Msk (0x01UL << SCT_CTRL_STOP_L_Pos) /*!< SCT CTRL: STOP_L Mask */\r
-#define SCT_CTRL_HALT_L_Pos 2 /*!< SCT CTRL: HALT_L Position */\r
-#define SCT_CTRL_HALT_L_Msk (0x01UL << SCT_CTRL_HALT_L_Pos) /*!< SCT CTRL: HALT_L Mask */\r
-#define SCT_CTRL_CLRCTR_L_Pos 3 /*!< SCT CTRL: CLRCTR_L Position */\r
-#define SCT_CTRL_CLRCTR_L_Msk (0x01UL << SCT_CTRL_CLRCTR_L_Pos) /*!< SCT CTRL: CLRCTR_L Mask */\r
-#define SCT_CTRL_BIDIR_L_Pos 4 /*!< SCT CTRL: BIDIR_L Position */\r
-#define SCT_CTRL_BIDIR_L_Msk (0x01UL << SCT_CTRL_BIDIR_L_Pos) /*!< SCT CTRL: BIDIR_L Mask */\r
-#define SCT_CTRL_PRE_L_Pos 5 /*!< SCT CTRL: PRE_L Position */\r
-#define SCT_CTRL_PRE_L_Msk (0x000000ffUL << SCT_CTRL_PRE_L_Pos) /*!< SCT CTRL: PRE_L Mask */\r
-#define SCT_CTRL_DOWN_H_Pos 16 /*!< SCT CTRL: DOWN_H Position */\r
-#define SCT_CTRL_DOWN_H_Msk (0x01UL << SCT_CTRL_DOWN_H_Pos) /*!< SCT CTRL: DOWN_H Mask */\r
-#define SCT_CTRL_STOP_H_Pos 17 /*!< SCT CTRL: STOP_H Position */\r
-#define SCT_CTRL_STOP_H_Msk (0x01UL << SCT_CTRL_STOP_H_Pos) /*!< SCT CTRL: STOP_H Mask */\r
-#define SCT_CTRL_HALT_H_Pos 18 /*!< SCT CTRL: HALT_H Position */\r
-#define SCT_CTRL_HALT_H_Msk (0x01UL << SCT_CTRL_HALT_H_Pos) /*!< SCT CTRL: HALT_H Mask */\r
-#define SCT_CTRL_CLRCTR_H_Pos 19 /*!< SCT CTRL: CLRCTR_H Position */\r
-#define SCT_CTRL_CLRCTR_H_Msk (0x01UL << SCT_CTRL_CLRCTR_H_Pos) /*!< SCT CTRL: CLRCTR_H Mask */\r
-#define SCT_CTRL_BIDIR_H_Pos 20 /*!< SCT CTRL: BIDIR_H Position */\r
-#define SCT_CTRL_BIDIR_H_Msk (0x01UL << SCT_CTRL_BIDIR_H_Pos) /*!< SCT CTRL: BIDIR_H Mask */\r
-#define SCT_CTRL_PRE_H_Pos 21 /*!< SCT CTRL: PRE_H Position */\r
-#define SCT_CTRL_PRE_H_Msk (0x000000ffUL << SCT_CTRL_PRE_H_Pos) /*!< SCT CTRL: PRE_H Mask */\r
-\r
-// ---------------------------------------- SCT_LIMIT -------------------------------------------\r
-#define SCT_LIMIT_LIMMSK_L_Pos 0 /*!< SCT LIMIT: LIMMSK_L Position */\r
-#define SCT_LIMIT_LIMMSK_L_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos) /*!< SCT LIMIT: LIMMSK_L Mask */\r
-#define SCT_LIMIT_LIMMSK_H_Pos 16 /*!< SCT LIMIT: LIMMSK_H Position */\r
-#define SCT_LIMIT_LIMMSK_H_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos) /*!< SCT LIMIT: LIMMSK_H Mask */\r
-\r
-// ---------------------------------------- SCT_HALT --------------------------------------------\r
-#define SCT_HALT_HALTMSK_L_Pos 0 /*!< SCT HALT: HALTMSK_L Position */\r
-#define SCT_HALT_HALTMSK_L_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos) /*!< SCT HALT: HALTMSK_L Mask */\r
-#define SCT_HALT_HALTMSK_H_Pos 16 /*!< SCT HALT: HALTMSK_H Position */\r
-#define SCT_HALT_HALTMSK_H_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos) /*!< SCT HALT: HALTMSK_H Mask */\r
-\r
-// ---------------------------------------- SCT_STOP --------------------------------------------\r
-#define SCT_STOP_STOPMSK_L_Pos 0 /*!< SCT STOP: STOPMSK_L Position */\r
-#define SCT_STOP_STOPMSK_L_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos) /*!< SCT STOP: STOPMSK_L Mask */\r
-#define SCT_STOP_STOPMSK_H_Pos 16 /*!< SCT STOP: STOPMSK_H Position */\r
-#define SCT_STOP_STOPMSK_H_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos) /*!< SCT STOP: STOPMSK_H Mask */\r
-\r
-// ---------------------------------------- SCT_START -------------------------------------------\r
-#define SCT_START_STARTMSK_L_Pos 0 /*!< SCT START: STARTMSK_L Position */\r
-#define SCT_START_STARTMSK_L_Msk (0x0000ffffUL << SCT_START_STARTMSK_L_Pos) /*!< SCT START: STARTMSK_L Mask */\r
-#define SCT_START_STARTMSK_H_Pos 16 /*!< SCT START: STARTMSK_H Position */\r
-#define SCT_START_STARTMSK_H_Msk (0x0000ffffUL << SCT_START_STARTMSK_H_Pos) /*!< SCT START: STARTMSK_H Mask */\r
-\r
-// ---------------------------------------- SCT_COUNT -------------------------------------------\r
-#define SCT_COUNT_CTR_L_Pos 0 /*!< SCT COUNT: CTR_L Position */\r
-#define SCT_COUNT_CTR_L_Msk (0x0000ffffUL << SCT_COUNT_CTR_L_Pos) /*!< SCT COUNT: CTR_L Mask */\r
-#define SCT_COUNT_CTR_H_Pos 16 /*!< SCT COUNT: CTR_H Position */\r
-#define SCT_COUNT_CTR_H_Msk (0x0000ffffUL << SCT_COUNT_CTR_H_Pos) /*!< SCT COUNT: CTR_H Mask */\r
-\r
-// ---------------------------------------- SCT_STATE -------------------------------------------\r
-#define SCT_STATE_STATE_L_Pos 0 /*!< SCT STATE: STATE_L Position */\r
-#define SCT_STATE_STATE_L_Msk (0x1fUL << SCT_STATE_STATE_L_Pos) /*!< SCT STATE: STATE_L Mask */\r
-#define SCT_STATE_STATE_H_Pos 16 /*!< SCT STATE: STATE_H Position */\r
-#define SCT_STATE_STATE_H_Msk (0x1fUL << SCT_STATE_STATE_H_Pos) /*!< SCT STATE: STATE_H Mask */\r
-\r
-// ---------------------------------------- SCT_INPUT -------------------------------------------\r
-#define SCT_INPUT_AIN0_Pos 0 /*!< SCT INPUT: AIN0 Position */\r
-#define SCT_INPUT_AIN0_Msk (0x01UL << SCT_INPUT_AIN0_Pos) /*!< SCT INPUT: AIN0 Mask */\r
-#define SCT_INPUT_AIN1_Pos 1 /*!< SCT INPUT: AIN1 Position */\r
-#define SCT_INPUT_AIN1_Msk (0x01UL << SCT_INPUT_AIN1_Pos) /*!< SCT INPUT: AIN1 Mask */\r
-#define SCT_INPUT_AIN2_Pos 2 /*!< SCT INPUT: AIN2 Position */\r
-#define SCT_INPUT_AIN2_Msk (0x01UL << SCT_INPUT_AIN2_Pos) /*!< SCT INPUT: AIN2 Mask */\r
-#define SCT_INPUT_AIN3_Pos 3 /*!< SCT INPUT: AIN3 Position */\r
-#define SCT_INPUT_AIN3_Msk (0x01UL << SCT_INPUT_AIN3_Pos) /*!< SCT INPUT: AIN3 Mask */\r
-#define SCT_INPUT_AIN4_Pos 4 /*!< SCT INPUT: AIN4 Position */\r
-#define SCT_INPUT_AIN4_Msk (0x01UL << SCT_INPUT_AIN4_Pos) /*!< SCT INPUT: AIN4 Mask */\r
-#define SCT_INPUT_AIN5_Pos 5 /*!< SCT INPUT: AIN5 Position */\r
-#define SCT_INPUT_AIN5_Msk (0x01UL << SCT_INPUT_AIN5_Pos) /*!< SCT INPUT: AIN5 Mask */\r
-#define SCT_INPUT_AIN6_Pos 6 /*!< SCT INPUT: AIN6 Position */\r
-#define SCT_INPUT_AIN6_Msk (0x01UL << SCT_INPUT_AIN6_Pos) /*!< SCT INPUT: AIN6 Mask */\r
-#define SCT_INPUT_AIN7_Pos 7 /*!< SCT INPUT: AIN7 Position */\r
-#define SCT_INPUT_AIN7_Msk (0x01UL << SCT_INPUT_AIN7_Pos) /*!< SCT INPUT: AIN7 Mask */\r
-#define SCT_INPUT_SIN0_Pos 16 /*!< SCT INPUT: SIN0 Position */\r
-#define SCT_INPUT_SIN0_Msk (0x01UL << SCT_INPUT_SIN0_Pos) /*!< SCT INPUT: SIN0 Mask */\r
-#define SCT_INPUT_SIN1_Pos 17 /*!< SCT INPUT: SIN1 Position */\r
-#define SCT_INPUT_SIN1_Msk (0x01UL << SCT_INPUT_SIN1_Pos) /*!< SCT INPUT: SIN1 Mask */\r
-#define SCT_INPUT_SIN2_Pos 18 /*!< SCT INPUT: SIN2 Position */\r
-#define SCT_INPUT_SIN2_Msk (0x01UL << SCT_INPUT_SIN2_Pos) /*!< SCT INPUT: SIN2 Mask */\r
-#define SCT_INPUT_SIN3_Pos 19 /*!< SCT INPUT: SIN3 Position */\r
-#define SCT_INPUT_SIN3_Msk (0x01UL << SCT_INPUT_SIN3_Pos) /*!< SCT INPUT: SIN3 Mask */\r
-#define SCT_INPUT_SIN4_Pos 20 /*!< SCT INPUT: SIN4 Position */\r
-#define SCT_INPUT_SIN4_Msk (0x01UL << SCT_INPUT_SIN4_Pos) /*!< SCT INPUT: SIN4 Mask */\r
-#define SCT_INPUT_SIN5_Pos 21 /*!< SCT INPUT: SIN5 Position */\r
-#define SCT_INPUT_SIN5_Msk (0x01UL << SCT_INPUT_SIN5_Pos) /*!< SCT INPUT: SIN5 Mask */\r
-#define SCT_INPUT_SIN6_Pos 22 /*!< SCT INPUT: SIN6 Position */\r
-#define SCT_INPUT_SIN6_Msk (0x01UL << SCT_INPUT_SIN6_Pos) /*!< SCT INPUT: SIN6 Mask */\r
-#define SCT_INPUT_SIN7_Pos 23 /*!< SCT INPUT: SIN7 Position */\r
-#define SCT_INPUT_SIN7_Msk (0x01UL << SCT_INPUT_SIN7_Pos) /*!< SCT INPUT: SIN7 Mask */\r
-\r
-// --------------------------------------- SCT_REGMODE ------------------------------------------\r
-#define SCT_REGMODE_REGMOD_L0_Pos 0 /*!< SCT REGMODE: REGMOD_L0 Position */\r
-#define SCT_REGMODE_REGMOD_L0_Msk (0x01UL << SCT_REGMODE_REGMOD_L0_Pos) /*!< SCT REGMODE: REGMOD_L0 Mask */\r
-#define SCT_REGMODE_REGMOD_L1_Pos 1 /*!< SCT REGMODE: REGMOD_L1 Position */\r
-#define SCT_REGMODE_REGMOD_L1_Msk (0x01UL << SCT_REGMODE_REGMOD_L1_Pos) /*!< SCT REGMODE: REGMOD_L1 Mask */\r
-#define SCT_REGMODE_REGMOD_L2_Pos 2 /*!< SCT REGMODE: REGMOD_L2 Position */\r
-#define SCT_REGMODE_REGMOD_L2_Msk (0x01UL << SCT_REGMODE_REGMOD_L2_Pos) /*!< SCT REGMODE: REGMOD_L2 Mask */\r
-#define SCT_REGMODE_REGMOD_L3_Pos 3 /*!< SCT REGMODE: REGMOD_L3 Position */\r
-#define SCT_REGMODE_REGMOD_L3_Msk (0x01UL << SCT_REGMODE_REGMOD_L3_Pos) /*!< SCT REGMODE: REGMOD_L3 Mask */\r
-#define SCT_REGMODE_REGMOD_L4_Pos 4 /*!< SCT REGMODE: REGMOD_L4 Position */\r
-#define SCT_REGMODE_REGMOD_L4_Msk (0x01UL << SCT_REGMODE_REGMOD_L4_Pos) /*!< SCT REGMODE: REGMOD_L4 Mask */\r
-#define SCT_REGMODE_REGMOD_L5_Pos 5 /*!< SCT REGMODE: REGMOD_L5 Position */\r
-#define SCT_REGMODE_REGMOD_L5_Msk (0x01UL << SCT_REGMODE_REGMOD_L5_Pos) /*!< SCT REGMODE: REGMOD_L5 Mask */\r
-#define SCT_REGMODE_REGMOD_L6_Pos 6 /*!< SCT REGMODE: REGMOD_L6 Position */\r
-#define SCT_REGMODE_REGMOD_L6_Msk (0x01UL << SCT_REGMODE_REGMOD_L6_Pos) /*!< SCT REGMODE: REGMOD_L6 Mask */\r
-#define SCT_REGMODE_REGMOD_L7_Pos 7 /*!< SCT REGMODE: REGMOD_L7 Position */\r
-#define SCT_REGMODE_REGMOD_L7_Msk (0x01UL << SCT_REGMODE_REGMOD_L7_Pos) /*!< SCT REGMODE: REGMOD_L7 Mask */\r
-#define SCT_REGMODE_REGMOD_L8_Pos 8 /*!< SCT REGMODE: REGMOD_L8 Position */\r
-#define SCT_REGMODE_REGMOD_L8_Msk (0x01UL << SCT_REGMODE_REGMOD_L8_Pos) /*!< SCT REGMODE: REGMOD_L8 Mask */\r
-#define SCT_REGMODE_REGMOD_L9_Pos 9 /*!< SCT REGMODE: REGMOD_L9 Position */\r
-#define SCT_REGMODE_REGMOD_L9_Msk (0x01UL << SCT_REGMODE_REGMOD_L9_Pos) /*!< SCT REGMODE: REGMOD_L9 Mask */\r
-#define SCT_REGMODE_REGMOD_L10_Pos 10 /*!< SCT REGMODE: REGMOD_L10 Position */\r
-#define SCT_REGMODE_REGMOD_L10_Msk (0x01UL << SCT_REGMODE_REGMOD_L10_Pos) /*!< SCT REGMODE: REGMOD_L10 Mask */\r
-#define SCT_REGMODE_REGMOD_L11_Pos 11 /*!< SCT REGMODE: REGMOD_L11 Position */\r
-#define SCT_REGMODE_REGMOD_L11_Msk (0x01UL << SCT_REGMODE_REGMOD_L11_Pos) /*!< SCT REGMODE: REGMOD_L11 Mask */\r
-#define SCT_REGMODE_REGMOD_L12_Pos 12 /*!< SCT REGMODE: REGMOD_L12 Position */\r
-#define SCT_REGMODE_REGMOD_L12_Msk (0x01UL << SCT_REGMODE_REGMOD_L12_Pos) /*!< SCT REGMODE: REGMOD_L12 Mask */\r
-#define SCT_REGMODE_REGMOD_L13_Pos 13 /*!< SCT REGMODE: REGMOD_L13 Position */\r
-#define SCT_REGMODE_REGMOD_L13_Msk (0x01UL << SCT_REGMODE_REGMOD_L13_Pos) /*!< SCT REGMODE: REGMOD_L13 Mask */\r
-#define SCT_REGMODE_REGMOD_L14_Pos 14 /*!< SCT REGMODE: REGMOD_L14 Position */\r
-#define SCT_REGMODE_REGMOD_L14_Msk (0x01UL << SCT_REGMODE_REGMOD_L14_Pos) /*!< SCT REGMODE: REGMOD_L14 Mask */\r
-#define SCT_REGMODE_REGMOD_L15_Pos 15 /*!< SCT REGMODE: REGMOD_L15 Position */\r
-#define SCT_REGMODE_REGMOD_L15_Msk (0x01UL << SCT_REGMODE_REGMOD_L15_Pos) /*!< SCT REGMODE: REGMOD_L15 Mask */\r
-#define SCT_REGMODE_REGMOD_H16_Pos 16 /*!< SCT REGMODE: REGMOD_H16 Position */\r
-#define SCT_REGMODE_REGMOD_H16_Msk (0x01UL << SCT_REGMODE_REGMOD_H16_Pos) /*!< SCT REGMODE: REGMOD_H16 Mask */\r
-#define SCT_REGMODE_REGMOD_H17_Pos 17 /*!< SCT REGMODE: REGMOD_H17 Position */\r
-#define SCT_REGMODE_REGMOD_H17_Msk (0x01UL << SCT_REGMODE_REGMOD_H17_Pos) /*!< SCT REGMODE: REGMOD_H17 Mask */\r
-#define SCT_REGMODE_REGMOD_H18_Pos 18 /*!< SCT REGMODE: REGMOD_H18 Position */\r
-#define SCT_REGMODE_REGMOD_H18_Msk (0x01UL << SCT_REGMODE_REGMOD_H18_Pos) /*!< SCT REGMODE: REGMOD_H18 Mask */\r
-#define SCT_REGMODE_REGMOD_H19_Pos 19 /*!< SCT REGMODE: REGMOD_H19 Position */\r
-#define SCT_REGMODE_REGMOD_H19_Msk (0x01UL << SCT_REGMODE_REGMOD_H19_Pos) /*!< SCT REGMODE: REGMOD_H19 Mask */\r
-#define SCT_REGMODE_REGMOD_H20_Pos 20 /*!< SCT REGMODE: REGMOD_H20 Position */\r
-#define SCT_REGMODE_REGMOD_H20_Msk (0x01UL << SCT_REGMODE_REGMOD_H20_Pos) /*!< SCT REGMODE: REGMOD_H20 Mask */\r
-#define SCT_REGMODE_REGMOD_H21_Pos 21 /*!< SCT REGMODE: REGMOD_H21 Position */\r
-#define SCT_REGMODE_REGMOD_H21_Msk (0x01UL << SCT_REGMODE_REGMOD_H21_Pos) /*!< SCT REGMODE: REGMOD_H21 Mask */\r
-#define SCT_REGMODE_REGMOD_H22_Pos 22 /*!< SCT REGMODE: REGMOD_H22 Position */\r
-#define SCT_REGMODE_REGMOD_H22_Msk (0x01UL << SCT_REGMODE_REGMOD_H22_Pos) /*!< SCT REGMODE: REGMOD_H22 Mask */\r
-#define SCT_REGMODE_REGMOD_H23_Pos 23 /*!< SCT REGMODE: REGMOD_H23 Position */\r
-#define SCT_REGMODE_REGMOD_H23_Msk (0x01UL << SCT_REGMODE_REGMOD_H23_Pos) /*!< SCT REGMODE: REGMOD_H23 Mask */\r
-#define SCT_REGMODE_REGMOD_H24_Pos 24 /*!< SCT REGMODE: REGMOD_H24 Position */\r
-#define SCT_REGMODE_REGMOD_H24_Msk (0x01UL << SCT_REGMODE_REGMOD_H24_Pos) /*!< SCT REGMODE: REGMOD_H24 Mask */\r
-#define SCT_REGMODE_REGMOD_H25_Pos 25 /*!< SCT REGMODE: REGMOD_H25 Position */\r
-#define SCT_REGMODE_REGMOD_H25_Msk (0x01UL << SCT_REGMODE_REGMOD_H25_Pos) /*!< SCT REGMODE: REGMOD_H25 Mask */\r
-#define SCT_REGMODE_REGMOD_H26_Pos 26 /*!< SCT REGMODE: REGMOD_H26 Position */\r
-#define SCT_REGMODE_REGMOD_H26_Msk (0x01UL << SCT_REGMODE_REGMOD_H26_Pos) /*!< SCT REGMODE: REGMOD_H26 Mask */\r
-#define SCT_REGMODE_REGMOD_H27_Pos 27 /*!< SCT REGMODE: REGMOD_H27 Position */\r
-#define SCT_REGMODE_REGMOD_H27_Msk (0x01UL << SCT_REGMODE_REGMOD_H27_Pos) /*!< SCT REGMODE: REGMOD_H27 Mask */\r
-#define SCT_REGMODE_REGMOD_H28_Pos 28 /*!< SCT REGMODE: REGMOD_H28 Position */\r
-#define SCT_REGMODE_REGMOD_H28_Msk (0x01UL << SCT_REGMODE_REGMOD_H28_Pos) /*!< SCT REGMODE: REGMOD_H28 Mask */\r
-#define SCT_REGMODE_REGMOD_H29_Pos 29 /*!< SCT REGMODE: REGMOD_H29 Position */\r
-#define SCT_REGMODE_REGMOD_H29_Msk (0x01UL << SCT_REGMODE_REGMOD_H29_Pos) /*!< SCT REGMODE: REGMOD_H29 Mask */\r
-#define SCT_REGMODE_REGMOD_H30_Pos 30 /*!< SCT REGMODE: REGMOD_H30 Position */\r
-#define SCT_REGMODE_REGMOD_H30_Msk (0x01UL << SCT_REGMODE_REGMOD_H30_Pos) /*!< SCT REGMODE: REGMOD_H30 Mask */\r
-#define SCT_REGMODE_REGMOD_H31_Pos 31 /*!< SCT REGMODE: REGMOD_H31 Position */\r
-#define SCT_REGMODE_REGMOD_H31_Msk (0x01UL << SCT_REGMODE_REGMOD_H31_Pos) /*!< SCT REGMODE: REGMOD_H31 Mask */\r
-\r
-// --------------------------------------- SCT_OUTPUT -------------------------------------------\r
-#define SCT_OUTPUT_OUT0_Pos 0 /*!< SCT OUTPUT: OUT0 Position */\r
-#define SCT_OUTPUT_OUT0_Msk (0x01UL << SCT_OUTPUT_OUT0_Pos) /*!< SCT OUTPUT: OUT0 Mask */\r
-#define SCT_OUTPUT_OUT1_Pos 1 /*!< SCT OUTPUT: OUT1 Position */\r
-#define SCT_OUTPUT_OUT1_Msk (0x01UL << SCT_OUTPUT_OUT1_Pos) /*!< SCT OUTPUT: OUT1 Mask */\r
-#define SCT_OUTPUT_OUT2_Pos 2 /*!< SCT OUTPUT: OUT2 Position */\r
-#define SCT_OUTPUT_OUT2_Msk (0x01UL << SCT_OUTPUT_OUT2_Pos) /*!< SCT OUTPUT: OUT2 Mask */\r
-#define SCT_OUTPUT_OUT3_Pos 3 /*!< SCT OUTPUT: OUT3 Position */\r
-#define SCT_OUTPUT_OUT3_Msk (0x01UL << SCT_OUTPUT_OUT3_Pos) /*!< SCT OUTPUT: OUT3 Mask */\r
-#define SCT_OUTPUT_OUT4_Pos 4 /*!< SCT OUTPUT: OUT4 Position */\r
-#define SCT_OUTPUT_OUT4_Msk (0x01UL << SCT_OUTPUT_OUT4_Pos) /*!< SCT OUTPUT: OUT4 Mask */\r
-#define SCT_OUTPUT_OUT5_Pos 5 /*!< SCT OUTPUT: OUT5 Position */\r
-#define SCT_OUTPUT_OUT5_Msk (0x01UL << SCT_OUTPUT_OUT5_Pos) /*!< SCT OUTPUT: OUT5 Mask */\r
-#define SCT_OUTPUT_OUT6_Pos 6 /*!< SCT OUTPUT: OUT6 Position */\r
-#define SCT_OUTPUT_OUT6_Msk (0x01UL << SCT_OUTPUT_OUT6_Pos) /*!< SCT OUTPUT: OUT6 Mask */\r
-#define SCT_OUTPUT_OUT7_Pos 7 /*!< SCT OUTPUT: OUT7 Position */\r
-#define SCT_OUTPUT_OUT7_Msk (0x01UL << SCT_OUTPUT_OUT7_Pos) /*!< SCT OUTPUT: OUT7 Mask */\r
-#define SCT_OUTPUT_OUT8_Pos 8 /*!< SCT OUTPUT: OUT8 Position */\r
-#define SCT_OUTPUT_OUT8_Msk (0x01UL << SCT_OUTPUT_OUT8_Pos) /*!< SCT OUTPUT: OUT8 Mask */\r
-#define SCT_OUTPUT_OUT9_Pos 9 /*!< SCT OUTPUT: OUT9 Position */\r
-#define SCT_OUTPUT_OUT9_Msk (0x01UL << SCT_OUTPUT_OUT9_Pos) /*!< SCT OUTPUT: OUT9 Mask */\r
-#define SCT_OUTPUT_OUT10_Pos 10 /*!< SCT OUTPUT: OUT10 Position */\r
-#define SCT_OUTPUT_OUT10_Msk (0x01UL << SCT_OUTPUT_OUT10_Pos) /*!< SCT OUTPUT: OUT10 Mask */\r
-#define SCT_OUTPUT_OUT11_Pos 11 /*!< SCT OUTPUT: OUT11 Position */\r
-#define SCT_OUTPUT_OUT11_Msk (0x01UL << SCT_OUTPUT_OUT11_Pos) /*!< SCT OUTPUT: OUT11 Mask */\r
-#define SCT_OUTPUT_OUT12_Pos 12 /*!< SCT OUTPUT: OUT12 Position */\r
-#define SCT_OUTPUT_OUT12_Msk (0x01UL << SCT_OUTPUT_OUT12_Pos) /*!< SCT OUTPUT: OUT12 Mask */\r
-#define SCT_OUTPUT_OUT13_Pos 13 /*!< SCT OUTPUT: OUT13 Position */\r
-#define SCT_OUTPUT_OUT13_Msk (0x01UL << SCT_OUTPUT_OUT13_Pos) /*!< SCT OUTPUT: OUT13 Mask */\r
-#define SCT_OUTPUT_OUT14_Pos 14 /*!< SCT OUTPUT: OUT14 Position */\r
-#define SCT_OUTPUT_OUT14_Msk (0x01UL << SCT_OUTPUT_OUT14_Pos) /*!< SCT OUTPUT: OUT14 Mask */\r
-#define SCT_OUTPUT_OUT15_Pos 15 /*!< SCT OUTPUT: OUT15 Position */\r
-#define SCT_OUTPUT_OUT15_Msk (0x01UL << SCT_OUTPUT_OUT15_Pos) /*!< SCT OUTPUT: OUT15 Mask */\r
-\r
-// ------------------------------------ SCT_OUTPUTDIRCTRL ---------------------------------------\r
-#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos 0 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos 2 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos 4 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos 6 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos 8 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos 10 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos 12 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos 14 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos 16 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos 18 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos 20 /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos 22 /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos 24 /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos 26 /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos 28 /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos 30 /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */\r
-#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask */\r
-\r
-// ----------------------------------------- SCT_RES --------------------------------------------\r
-#define SCT_RES_O0RES_Pos 0 /*!< SCT RES: O0RES Position */\r
-#define SCT_RES_O0RES_Msk (0x03UL << SCT_RES_O0RES_Pos) /*!< SCT RES: O0RES Mask */\r
-#define SCT_RES_O1RES_Pos 2 /*!< SCT RES: O1RES Position */\r
-#define SCT_RES_O1RES_Msk (0x03UL << SCT_RES_O1RES_Pos) /*!< SCT RES: O1RES Mask */\r
-#define SCT_RES_O2RES_Pos 4 /*!< SCT RES: O2RES Position */\r
-#define SCT_RES_O2RES_Msk (0x03UL << SCT_RES_O2RES_Pos) /*!< SCT RES: O2RES Mask */\r
-#define SCT_RES_O3RES_Pos 6 /*!< SCT RES: O3RES Position */\r
-#define SCT_RES_O3RES_Msk (0x03UL << SCT_RES_O3RES_Pos) /*!< SCT RES: O3RES Mask */\r
-#define SCT_RES_O4RES_Pos 8 /*!< SCT RES: O4RES Position */\r
-#define SCT_RES_O4RES_Msk (0x03UL << SCT_RES_O4RES_Pos) /*!< SCT RES: O4RES Mask */\r
-#define SCT_RES_O5RES_Pos 10 /*!< SCT RES: O5RES Position */\r
-#define SCT_RES_O5RES_Msk (0x03UL << SCT_RES_O5RES_Pos) /*!< SCT RES: O5RES Mask */\r
-#define SCT_RES_O6RES_Pos 12 /*!< SCT RES: O6RES Position */\r
-#define SCT_RES_O6RES_Msk (0x03UL << SCT_RES_O6RES_Pos) /*!< SCT RES: O6RES Mask */\r
-#define SCT_RES_O7RES_Pos 14 /*!< SCT RES: O7RES Position */\r
-#define SCT_RES_O7RES_Msk (0x03UL << SCT_RES_O7RES_Pos) /*!< SCT RES: O7RES Mask */\r
-#define SCT_RES_O8RES_Pos 16 /*!< SCT RES: O8RES Position */\r
-#define SCT_RES_O8RES_Msk (0x03UL << SCT_RES_O8RES_Pos) /*!< SCT RES: O8RES Mask */\r
-#define SCT_RES_O9RES_Pos 18 /*!< SCT RES: O9RES Position */\r
-#define SCT_RES_O9RES_Msk (0x03UL << SCT_RES_O9RES_Pos) /*!< SCT RES: O9RES Mask */\r
-#define SCT_RES_O10RES_Pos 20 /*!< SCT RES: O10RES Position */\r
-#define SCT_RES_O10RES_Msk (0x03UL << SCT_RES_O10RES_Pos) /*!< SCT RES: O10RES Mask */\r
-#define SCT_RES_O11RES_Pos 22 /*!< SCT RES: O11RES Position */\r
-#define SCT_RES_O11RES_Msk (0x03UL << SCT_RES_O11RES_Pos) /*!< SCT RES: O11RES Mask */\r
-#define SCT_RES_O12RES_Pos 24 /*!< SCT RES: O12RES Position */\r
-#define SCT_RES_O12RES_Msk (0x03UL << SCT_RES_O12RES_Pos) /*!< SCT RES: O12RES Mask */\r
-#define SCT_RES_O13RES_Pos 26 /*!< SCT RES: O13RES Position */\r
-#define SCT_RES_O13RES_Msk (0x03UL << SCT_RES_O13RES_Pos) /*!< SCT RES: O13RES Mask */\r
-#define SCT_RES_O14RES_Pos 28 /*!< SCT RES: O14RES Position */\r
-#define SCT_RES_O14RES_Msk (0x03UL << SCT_RES_O14RES_Pos) /*!< SCT RES: O14RES Mask */\r
-#define SCT_RES_O15RES_Pos 30 /*!< SCT RES: O15RES Position */\r
-#define SCT_RES_O15RES_Msk (0x03UL << SCT_RES_O15RES_Pos) /*!< SCT RES: O15RES Mask */\r
-\r
-// --------------------------------------- SCT_DMAREQ0 ------------------------------------------\r
-#define SCT_DMAREQ0_DEV_0_0_Pos 0 /*!< SCT DMAREQ0: DEV_0_0 Position */\r
-#define SCT_DMAREQ0_DEV_0_0_Msk (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos) /*!< SCT DMAREQ0: DEV_0_0 Mask */\r
-#define SCT_DMAREQ0_DEV_0_1_Pos 1 /*!< SCT DMAREQ0: DEV_0_1 Position */\r
-#define SCT_DMAREQ0_DEV_0_1_Msk (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos) /*!< SCT DMAREQ0: DEV_0_1 Mask */\r
-#define SCT_DMAREQ0_DEV_0_2_Pos 2 /*!< SCT DMAREQ0: DEV_0_2 Position */\r
-#define SCT_DMAREQ0_DEV_0_2_Msk (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos) /*!< SCT DMAREQ0: DEV_0_2 Mask */\r
-#define SCT_DMAREQ0_DEV_0_3_Pos 3 /*!< SCT DMAREQ0: DEV_0_3 Position */\r
-#define SCT_DMAREQ0_DEV_0_3_Msk (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos) /*!< SCT DMAREQ0: DEV_0_3 Mask */\r
-#define SCT_DMAREQ0_DEV_0_4_Pos 4 /*!< SCT DMAREQ0: DEV_0_4 Position */\r
-#define SCT_DMAREQ0_DEV_0_4_Msk (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos) /*!< SCT DMAREQ0: DEV_0_4 Mask */\r
-#define SCT_DMAREQ0_DEV_0_5_Pos 5 /*!< SCT DMAREQ0: DEV_0_5 Position */\r
-#define SCT_DMAREQ0_DEV_0_5_Msk (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos) /*!< SCT DMAREQ0: DEV_0_5 Mask */\r
-#define SCT_DMAREQ0_DEV_0_6_Pos 6 /*!< SCT DMAREQ0: DEV_0_6 Position */\r
-#define SCT_DMAREQ0_DEV_0_6_Msk (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos) /*!< SCT DMAREQ0: DEV_0_6 Mask */\r
-#define SCT_DMAREQ0_DEV_0_7_Pos 7 /*!< SCT DMAREQ0: DEV_0_7 Position */\r
-#define SCT_DMAREQ0_DEV_0_7_Msk (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos) /*!< SCT DMAREQ0: DEV_0_7 Mask */\r
-#define SCT_DMAREQ0_DEV_0_8_Pos 8 /*!< SCT DMAREQ0: DEV_0_8 Position */\r
-#define SCT_DMAREQ0_DEV_0_8_Msk (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos) /*!< SCT DMAREQ0: DEV_0_8 Mask */\r
-#define SCT_DMAREQ0_DEV_0_9_Pos 9 /*!< SCT DMAREQ0: DEV_0_9 Position */\r
-#define SCT_DMAREQ0_DEV_0_9_Msk (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos) /*!< SCT DMAREQ0: DEV_0_9 Mask */\r
-#define SCT_DMAREQ0_DEV_0_10_Pos 10 /*!< SCT DMAREQ0: DEV_0_10 Position */\r
-#define SCT_DMAREQ0_DEV_0_10_Msk (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos) /*!< SCT DMAREQ0: DEV_0_10 Mask */\r
-#define SCT_DMAREQ0_DEV_0_11_Pos 11 /*!< SCT DMAREQ0: DEV_0_11 Position */\r
-#define SCT_DMAREQ0_DEV_0_11_Msk (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos) /*!< SCT DMAREQ0: DEV_0_11 Mask */\r
-#define SCT_DMAREQ0_DEV_0_12_Pos 12 /*!< SCT DMAREQ0: DEV_0_12 Position */\r
-#define SCT_DMAREQ0_DEV_0_12_Msk (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos) /*!< SCT DMAREQ0: DEV_0_12 Mask */\r
-#define SCT_DMAREQ0_DEV_0_13_Pos 13 /*!< SCT DMAREQ0: DEV_0_13 Position */\r
-#define SCT_DMAREQ0_DEV_0_13_Msk (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos) /*!< SCT DMAREQ0: DEV_0_13 Mask */\r
-#define SCT_DMAREQ0_DEV_0_14_Pos 14 /*!< SCT DMAREQ0: DEV_0_14 Position */\r
-#define SCT_DMAREQ0_DEV_0_14_Msk (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos) /*!< SCT DMAREQ0: DEV_0_14 Mask */\r
-#define SCT_DMAREQ0_DEV_0_15_Pos 15 /*!< SCT DMAREQ0: DEV_0_15 Position */\r
-#define SCT_DMAREQ0_DEV_0_15_Msk (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos) /*!< SCT DMAREQ0: DEV_0_15 Mask */\r
-#define SCT_DMAREQ0_DRL0_Pos 30 /*!< SCT DMAREQ0: DRL0 Position */\r
-#define SCT_DMAREQ0_DRL0_Msk (0x01UL << SCT_DMAREQ0_DRL0_Pos) /*!< SCT DMAREQ0: DRL0 Mask */\r
-#define SCT_DMAREQ0_DRQ0_Pos 31 /*!< SCT DMAREQ0: DRQ0 Position */\r
-#define SCT_DMAREQ0_DRQ0_Msk (0x01UL << SCT_DMAREQ0_DRQ0_Pos) /*!< SCT DMAREQ0: DRQ0 Mask */\r
-\r
-// --------------------------------------- SCT_DMAREQ1 ------------------------------------------\r
-#define SCT_DMAREQ1_DEV_1_0_Pos 0 /*!< SCT DMAREQ1: DEV_1_0 Position */\r
-#define SCT_DMAREQ1_DEV_1_0_Msk (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos) /*!< SCT DMAREQ1: DEV_1_0 Mask */\r
-#define SCT_DMAREQ1_DEV_1_1_Pos 1 /*!< SCT DMAREQ1: DEV_1_1 Position */\r
-#define SCT_DMAREQ1_DEV_1_1_Msk (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos) /*!< SCT DMAREQ1: DEV_1_1 Mask */\r
-#define SCT_DMAREQ1_DEV_1_2_Pos 2 /*!< SCT DMAREQ1: DEV_1_2 Position */\r
-#define SCT_DMAREQ1_DEV_1_2_Msk (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos) /*!< SCT DMAREQ1: DEV_1_2 Mask */\r
-#define SCT_DMAREQ1_DEV_1_3_Pos 3 /*!< SCT DMAREQ1: DEV_1_3 Position */\r
-#define SCT_DMAREQ1_DEV_1_3_Msk (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos) /*!< SCT DMAREQ1: DEV_1_3 Mask */\r
-#define SCT_DMAREQ1_DEV_1_4_Pos 4 /*!< SCT DMAREQ1: DEV_1_4 Position */\r
-#define SCT_DMAREQ1_DEV_1_4_Msk (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos) /*!< SCT DMAREQ1: DEV_1_4 Mask */\r
-#define SCT_DMAREQ1_DEV_1_5_Pos 5 /*!< SCT DMAREQ1: DEV_1_5 Position */\r
-#define SCT_DMAREQ1_DEV_1_5_Msk (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos) /*!< SCT DMAREQ1: DEV_1_5 Mask */\r
-#define SCT_DMAREQ1_DEV_1_6_Pos 6 /*!< SCT DMAREQ1: DEV_1_6 Position */\r
-#define SCT_DMAREQ1_DEV_1_6_Msk (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos) /*!< SCT DMAREQ1: DEV_1_6 Mask */\r
-#define SCT_DMAREQ1_DEV_1_7_Pos 7 /*!< SCT DMAREQ1: DEV_1_7 Position */\r
-#define SCT_DMAREQ1_DEV_1_7_Msk (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos) /*!< SCT DMAREQ1: DEV_1_7 Mask */\r
-#define SCT_DMAREQ1_DEV_1_8_Pos 8 /*!< SCT DMAREQ1: DEV_1_8 Position */\r
-#define SCT_DMAREQ1_DEV_1_8_Msk (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos) /*!< SCT DMAREQ1: DEV_1_8 Mask */\r
-#define SCT_DMAREQ1_DEV_1_9_Pos 9 /*!< SCT DMAREQ1: DEV_1_9 Position */\r
-#define SCT_DMAREQ1_DEV_1_9_Msk (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos) /*!< SCT DMAREQ1: DEV_1_9 Mask */\r
-#define SCT_DMAREQ1_DEV_1_10_Pos 10 /*!< SCT DMAREQ1: DEV_1_10 Position */\r
-#define SCT_DMAREQ1_DEV_1_10_Msk (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos) /*!< SCT DMAREQ1: DEV_1_10 Mask */\r
-#define SCT_DMAREQ1_DEV_1_11_Pos 11 /*!< SCT DMAREQ1: DEV_1_11 Position */\r
-#define SCT_DMAREQ1_DEV_1_11_Msk (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos) /*!< SCT DMAREQ1: DEV_1_11 Mask */\r
-#define SCT_DMAREQ1_DEV_1_12_Pos 12 /*!< SCT DMAREQ1: DEV_1_12 Position */\r
-#define SCT_DMAREQ1_DEV_1_12_Msk (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos) /*!< SCT DMAREQ1: DEV_1_12 Mask */\r
-#define SCT_DMAREQ1_DEV_1_13_Pos 13 /*!< SCT DMAREQ1: DEV_1_13 Position */\r
-#define SCT_DMAREQ1_DEV_1_13_Msk (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos) /*!< SCT DMAREQ1: DEV_1_13 Mask */\r
-#define SCT_DMAREQ1_DEV_1_14_Pos 14 /*!< SCT DMAREQ1: DEV_1_14 Position */\r
-#define SCT_DMAREQ1_DEV_1_14_Msk (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos) /*!< SCT DMAREQ1: DEV_1_14 Mask */\r
-#define SCT_DMAREQ1_DEV_1_15_Pos 15 /*!< SCT DMAREQ1: DEV_1_15 Position */\r
-#define SCT_DMAREQ1_DEV_1_15_Msk (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos) /*!< SCT DMAREQ1: DEV_1_15 Mask */\r
-#define SCT_DMAREQ1_DRL1_Pos 30 /*!< SCT DMAREQ1: DRL1 Position */\r
-#define SCT_DMAREQ1_DRL1_Msk (0x01UL << SCT_DMAREQ1_DRL1_Pos) /*!< SCT DMAREQ1: DRL1 Mask */\r
-#define SCT_DMAREQ1_DRQ1_Pos 31 /*!< SCT DMAREQ1: DRQ1 Position */\r
-#define SCT_DMAREQ1_DRQ1_Msk (0x01UL << SCT_DMAREQ1_DRQ1_Pos) /*!< SCT DMAREQ1: DRQ1 Mask */\r
-\r
-// ---------------------------------------- SCT_EVEN --------------------------------------------\r
-#define SCT_EVEN_IEN0_Pos 0 /*!< SCT EVEN: IEN0 Position */\r
-#define SCT_EVEN_IEN0_Msk (0x01UL << SCT_EVEN_IEN0_Pos) /*!< SCT EVEN: IEN0 Mask */\r
-#define SCT_EVEN_IEN1_Pos 1 /*!< SCT EVEN: IEN1 Position */\r
-#define SCT_EVEN_IEN1_Msk (0x01UL << SCT_EVEN_IEN1_Pos) /*!< SCT EVEN: IEN1 Mask */\r
-#define SCT_EVEN_IEN2_Pos 2 /*!< SCT EVEN: IEN2 Position */\r
-#define SCT_EVEN_IEN2_Msk (0x01UL << SCT_EVEN_IEN2_Pos) /*!< SCT EVEN: IEN2 Mask */\r
-#define SCT_EVEN_IEN3_Pos 3 /*!< SCT EVEN: IEN3 Position */\r
-#define SCT_EVEN_IEN3_Msk (0x01UL << SCT_EVEN_IEN3_Pos) /*!< SCT EVEN: IEN3 Mask */\r
-#define SCT_EVEN_IEN4_Pos 4 /*!< SCT EVEN: IEN4 Position */\r
-#define SCT_EVEN_IEN4_Msk (0x01UL << SCT_EVEN_IEN4_Pos) /*!< SCT EVEN: IEN4 Mask */\r
-#define SCT_EVEN_IEN5_Pos 5 /*!< SCT EVEN: IEN5 Position */\r
-#define SCT_EVEN_IEN5_Msk (0x01UL << SCT_EVEN_IEN5_Pos) /*!< SCT EVEN: IEN5 Mask */\r
-#define SCT_EVEN_IEN6_Pos 6 /*!< SCT EVEN: IEN6 Position */\r
-#define SCT_EVEN_IEN6_Msk (0x01UL << SCT_EVEN_IEN6_Pos) /*!< SCT EVEN: IEN6 Mask */\r
-#define SCT_EVEN_IEN7_Pos 7 /*!< SCT EVEN: IEN7 Position */\r
-#define SCT_EVEN_IEN7_Msk (0x01UL << SCT_EVEN_IEN7_Pos) /*!< SCT EVEN: IEN7 Mask */\r
-#define SCT_EVEN_IEN8_Pos 8 /*!< SCT EVEN: IEN8 Position */\r
-#define SCT_EVEN_IEN8_Msk (0x01UL << SCT_EVEN_IEN8_Pos) /*!< SCT EVEN: IEN8 Mask */\r
-#define SCT_EVEN_IEN9_Pos 9 /*!< SCT EVEN: IEN9 Position */\r
-#define SCT_EVEN_IEN9_Msk (0x01UL << SCT_EVEN_IEN9_Pos) /*!< SCT EVEN: IEN9 Mask */\r
-#define SCT_EVEN_IEN10_Pos 10 /*!< SCT EVEN: IEN10 Position */\r
-#define SCT_EVEN_IEN10_Msk (0x01UL << SCT_EVEN_IEN10_Pos) /*!< SCT EVEN: IEN10 Mask */\r
-#define SCT_EVEN_IEN11_Pos 11 /*!< SCT EVEN: IEN11 Position */\r
-#define SCT_EVEN_IEN11_Msk (0x01UL << SCT_EVEN_IEN11_Pos) /*!< SCT EVEN: IEN11 Mask */\r
-#define SCT_EVEN_IEN12_Pos 12 /*!< SCT EVEN: IEN12 Position */\r
-#define SCT_EVEN_IEN12_Msk (0x01UL << SCT_EVEN_IEN12_Pos) /*!< SCT EVEN: IEN12 Mask */\r
-#define SCT_EVEN_IEN13_Pos 13 /*!< SCT EVEN: IEN13 Position */\r
-#define SCT_EVEN_IEN13_Msk (0x01UL << SCT_EVEN_IEN13_Pos) /*!< SCT EVEN: IEN13 Mask */\r
-#define SCT_EVEN_IEN14_Pos 14 /*!< SCT EVEN: IEN14 Position */\r
-#define SCT_EVEN_IEN14_Msk (0x01UL << SCT_EVEN_IEN14_Pos) /*!< SCT EVEN: IEN14 Mask */\r
-#define SCT_EVEN_IEN15_Pos 15 /*!< SCT EVEN: IEN15 Position */\r
-#define SCT_EVEN_IEN15_Msk (0x01UL << SCT_EVEN_IEN15_Pos) /*!< SCT EVEN: IEN15 Mask */\r
-\r
-// --------------------------------------- SCT_EVFLAG -------------------------------------------\r
-#define SCT_EVFLAG_FLAG0_Pos 0 /*!< SCT EVFLAG: FLAG0 Position */\r
-#define SCT_EVFLAG_FLAG0_Msk (0x01UL << SCT_EVFLAG_FLAG0_Pos) /*!< SCT EVFLAG: FLAG0 Mask */\r
-#define SCT_EVFLAG_FLAG1_Pos 1 /*!< SCT EVFLAG: FLAG1 Position */\r
-#define SCT_EVFLAG_FLAG1_Msk (0x01UL << SCT_EVFLAG_FLAG1_Pos) /*!< SCT EVFLAG: FLAG1 Mask */\r
-#define SCT_EVFLAG_FLAG2_Pos 2 /*!< SCT EVFLAG: FLAG2 Position */\r
-#define SCT_EVFLAG_FLAG2_Msk (0x01UL << SCT_EVFLAG_FLAG2_Pos) /*!< SCT EVFLAG: FLAG2 Mask */\r
-#define SCT_EVFLAG_FLAG3_Pos 3 /*!< SCT EVFLAG: FLAG3 Position */\r
-#define SCT_EVFLAG_FLAG3_Msk (0x01UL << SCT_EVFLAG_FLAG3_Pos) /*!< SCT EVFLAG: FLAG3 Mask */\r
-#define SCT_EVFLAG_FLAG4_Pos 4 /*!< SCT EVFLAG: FLAG4 Position */\r
-#define SCT_EVFLAG_FLAG4_Msk (0x01UL << SCT_EVFLAG_FLAG4_Pos) /*!< SCT EVFLAG: FLAG4 Mask */\r
-#define SCT_EVFLAG_FLAG5_Pos 5 /*!< SCT EVFLAG: FLAG5 Position */\r
-#define SCT_EVFLAG_FLAG5_Msk (0x01UL << SCT_EVFLAG_FLAG5_Pos) /*!< SCT EVFLAG: FLAG5 Mask */\r
-#define SCT_EVFLAG_FLAG6_Pos 6 /*!< SCT EVFLAG: FLAG6 Position */\r
-#define SCT_EVFLAG_FLAG6_Msk (0x01UL << SCT_EVFLAG_FLAG6_Pos) /*!< SCT EVFLAG: FLAG6 Mask */\r
-#define SCT_EVFLAG_FLAG7_Pos 7 /*!< SCT EVFLAG: FLAG7 Position */\r
-#define SCT_EVFLAG_FLAG7_Msk (0x01UL << SCT_EVFLAG_FLAG7_Pos) /*!< SCT EVFLAG: FLAG7 Mask */\r
-#define SCT_EVFLAG_FLAG8_Pos 8 /*!< SCT EVFLAG: FLAG8 Position */\r
-#define SCT_EVFLAG_FLAG8_Msk (0x01UL << SCT_EVFLAG_FLAG8_Pos) /*!< SCT EVFLAG: FLAG8 Mask */\r
-#define SCT_EVFLAG_FLAG9_Pos 9 /*!< SCT EVFLAG: FLAG9 Position */\r
-#define SCT_EVFLAG_FLAG9_Msk (0x01UL << SCT_EVFLAG_FLAG9_Pos) /*!< SCT EVFLAG: FLAG9 Mask */\r
-#define SCT_EVFLAG_FLAG10_Pos 10 /*!< SCT EVFLAG: FLAG10 Position */\r
-#define SCT_EVFLAG_FLAG10_Msk (0x01UL << SCT_EVFLAG_FLAG10_Pos) /*!< SCT EVFLAG: FLAG10 Mask */\r
-#define SCT_EVFLAG_FLAG11_Pos 11 /*!< SCT EVFLAG: FLAG11 Position */\r
-#define SCT_EVFLAG_FLAG11_Msk (0x01UL << SCT_EVFLAG_FLAG11_Pos) /*!< SCT EVFLAG: FLAG11 Mask */\r
-#define SCT_EVFLAG_FLAG12_Pos 12 /*!< SCT EVFLAG: FLAG12 Position */\r
-#define SCT_EVFLAG_FLAG12_Msk (0x01UL << SCT_EVFLAG_FLAG12_Pos) /*!< SCT EVFLAG: FLAG12 Mask */\r
-#define SCT_EVFLAG_FLAG13_Pos 13 /*!< SCT EVFLAG: FLAG13 Position */\r
-#define SCT_EVFLAG_FLAG13_Msk (0x01UL << SCT_EVFLAG_FLAG13_Pos) /*!< SCT EVFLAG: FLAG13 Mask */\r
-#define SCT_EVFLAG_FLAG14_Pos 14 /*!< SCT EVFLAG: FLAG14 Position */\r
-#define SCT_EVFLAG_FLAG14_Msk (0x01UL << SCT_EVFLAG_FLAG14_Pos) /*!< SCT EVFLAG: FLAG14 Mask */\r
-#define SCT_EVFLAG_FLAG15_Pos 15 /*!< SCT EVFLAG: FLAG15 Position */\r
-#define SCT_EVFLAG_FLAG15_Msk (0x01UL << SCT_EVFLAG_FLAG15_Pos) /*!< SCT EVFLAG: FLAG15 Mask */\r
-\r
-// ---------------------------------------- SCT_CONEN -------------------------------------------\r
-#define SCT_CONEN_NCEN0_Pos 0 /*!< SCT CONEN: NCEN0 Position */\r
-#define SCT_CONEN_NCEN0_Msk (0x01UL << SCT_CONEN_NCEN0_Pos) /*!< SCT CONEN: NCEN0 Mask */\r
-#define SCT_CONEN_NCEN1_Pos 1 /*!< SCT CONEN: NCEN1 Position */\r
-#define SCT_CONEN_NCEN1_Msk (0x01UL << SCT_CONEN_NCEN1_Pos) /*!< SCT CONEN: NCEN1 Mask */\r
-#define SCT_CONEN_NCEN2_Pos 2 /*!< SCT CONEN: NCEN2 Position */\r
-#define SCT_CONEN_NCEN2_Msk (0x01UL << SCT_CONEN_NCEN2_Pos) /*!< SCT CONEN: NCEN2 Mask */\r
-#define SCT_CONEN_NCEN3_Pos 3 /*!< SCT CONEN: NCEN3 Position */\r
-#define SCT_CONEN_NCEN3_Msk (0x01UL << SCT_CONEN_NCEN3_Pos) /*!< SCT CONEN: NCEN3 Mask */\r
-#define SCT_CONEN_NCEN4_Pos 4 /*!< SCT CONEN: NCEN4 Position */\r
-#define SCT_CONEN_NCEN4_Msk (0x01UL << SCT_CONEN_NCEN4_Pos) /*!< SCT CONEN: NCEN4 Mask */\r
-#define SCT_CONEN_NCEN5_Pos 5 /*!< SCT CONEN: NCEN5 Position */\r
-#define SCT_CONEN_NCEN5_Msk (0x01UL << SCT_CONEN_NCEN5_Pos) /*!< SCT CONEN: NCEN5 Mask */\r
-#define SCT_CONEN_NCEN6_Pos 6 /*!< SCT CONEN: NCEN6 Position */\r
-#define SCT_CONEN_NCEN6_Msk (0x01UL << SCT_CONEN_NCEN6_Pos) /*!< SCT CONEN: NCEN6 Mask */\r
-#define SCT_CONEN_NCEN7_Pos 7 /*!< SCT CONEN: NCEN7 Position */\r
-#define SCT_CONEN_NCEN7_Msk (0x01UL << SCT_CONEN_NCEN7_Pos) /*!< SCT CONEN: NCEN7 Mask */\r
-#define SCT_CONEN_NCEN8_Pos 8 /*!< SCT CONEN: NCEN8 Position */\r
-#define SCT_CONEN_NCEN8_Msk (0x01UL << SCT_CONEN_NCEN8_Pos) /*!< SCT CONEN: NCEN8 Mask */\r
-#define SCT_CONEN_NCEN9_Pos 9 /*!< SCT CONEN: NCEN9 Position */\r
-#define SCT_CONEN_NCEN9_Msk (0x01UL << SCT_CONEN_NCEN9_Pos) /*!< SCT CONEN: NCEN9 Mask */\r
-#define SCT_CONEN_NCEN10_Pos 10 /*!< SCT CONEN: NCEN10 Position */\r
-#define SCT_CONEN_NCEN10_Msk (0x01UL << SCT_CONEN_NCEN10_Pos) /*!< SCT CONEN: NCEN10 Mask */\r
-#define SCT_CONEN_NCEN11_Pos 11 /*!< SCT CONEN: NCEN11 Position */\r
-#define SCT_CONEN_NCEN11_Msk (0x01UL << SCT_CONEN_NCEN11_Pos) /*!< SCT CONEN: NCEN11 Mask */\r
-#define SCT_CONEN_NCEN12_Pos 12 /*!< SCT CONEN: NCEN12 Position */\r
-#define SCT_CONEN_NCEN12_Msk (0x01UL << SCT_CONEN_NCEN12_Pos) /*!< SCT CONEN: NCEN12 Mask */\r
-#define SCT_CONEN_NCEN13_Pos 13 /*!< SCT CONEN: NCEN13 Position */\r
-#define SCT_CONEN_NCEN13_Msk (0x01UL << SCT_CONEN_NCEN13_Pos) /*!< SCT CONEN: NCEN13 Mask */\r
-#define SCT_CONEN_NCEN14_Pos 14 /*!< SCT CONEN: NCEN14 Position */\r
-#define SCT_CONEN_NCEN14_Msk (0x01UL << SCT_CONEN_NCEN14_Pos) /*!< SCT CONEN: NCEN14 Mask */\r
-#define SCT_CONEN_NCEN15_Pos 15 /*!< SCT CONEN: NCEN15 Position */\r
-#define SCT_CONEN_NCEN15_Msk (0x01UL << SCT_CONEN_NCEN15_Pos) /*!< SCT CONEN: NCEN15 Mask */\r
-\r
-// --------------------------------------- SCT_CONFLAG ------------------------------------------\r
-#define SCT_CONFLAG_NCFLAG0_Pos 0 /*!< SCT CONFLAG: NCFLAG0 Position */\r
-#define SCT_CONFLAG_NCFLAG0_Msk (0x01UL << SCT_CONFLAG_NCFLAG0_Pos) /*!< SCT CONFLAG: NCFLAG0 Mask */\r
-#define SCT_CONFLAG_NCFLAG1_Pos 1 /*!< SCT CONFLAG: NCFLAG1 Position */\r
-#define SCT_CONFLAG_NCFLAG1_Msk (0x01UL << SCT_CONFLAG_NCFLAG1_Pos) /*!< SCT CONFLAG: NCFLAG1 Mask */\r
-#define SCT_CONFLAG_NCFLAG2_Pos 2 /*!< SCT CONFLAG: NCFLAG2 Position */\r
-#define SCT_CONFLAG_NCFLAG2_Msk (0x01UL << SCT_CONFLAG_NCFLAG2_Pos) /*!< SCT CONFLAG: NCFLAG2 Mask */\r
-#define SCT_CONFLAG_NCFLAG3_Pos 3 /*!< SCT CONFLAG: NCFLAG3 Position */\r
-#define SCT_CONFLAG_NCFLAG3_Msk (0x01UL << SCT_CONFLAG_NCFLAG3_Pos) /*!< SCT CONFLAG: NCFLAG3 Mask */\r
-#define SCT_CONFLAG_NCFLAG4_Pos 4 /*!< SCT CONFLAG: NCFLAG4 Position */\r
-#define SCT_CONFLAG_NCFLAG4_Msk (0x01UL << SCT_CONFLAG_NCFLAG4_Pos) /*!< SCT CONFLAG: NCFLAG4 Mask */\r
-#define SCT_CONFLAG_NCFLAG5_Pos 5 /*!< SCT CONFLAG: NCFLAG5 Position */\r
-#define SCT_CONFLAG_NCFLAG5_Msk (0x01UL << SCT_CONFLAG_NCFLAG5_Pos) /*!< SCT CONFLAG: NCFLAG5 Mask */\r
-#define SCT_CONFLAG_NCFLAG6_Pos 6 /*!< SCT CONFLAG: NCFLAG6 Position */\r
-#define SCT_CONFLAG_NCFLAG6_Msk (0x01UL << SCT_CONFLAG_NCFLAG6_Pos) /*!< SCT CONFLAG: NCFLAG6 Mask */\r
-#define SCT_CONFLAG_NCFLAG7_Pos 7 /*!< SCT CONFLAG: NCFLAG7 Position */\r
-#define SCT_CONFLAG_NCFLAG7_Msk (0x01UL << SCT_CONFLAG_NCFLAG7_Pos) /*!< SCT CONFLAG: NCFLAG7 Mask */\r
-#define SCT_CONFLAG_NCFLAG8_Pos 8 /*!< SCT CONFLAG: NCFLAG8 Position */\r
-#define SCT_CONFLAG_NCFLAG8_Msk (0x01UL << SCT_CONFLAG_NCFLAG8_Pos) /*!< SCT CONFLAG: NCFLAG8 Mask */\r
-#define SCT_CONFLAG_NCFLAG9_Pos 9 /*!< SCT CONFLAG: NCFLAG9 Position */\r
-#define SCT_CONFLAG_NCFLAG9_Msk (0x01UL << SCT_CONFLAG_NCFLAG9_Pos) /*!< SCT CONFLAG: NCFLAG9 Mask */\r
-#define SCT_CONFLAG_NCFLAG10_Pos 10 /*!< SCT CONFLAG: NCFLAG10 Position */\r
-#define SCT_CONFLAG_NCFLAG10_Msk (0x01UL << SCT_CONFLAG_NCFLAG10_Pos) /*!< SCT CONFLAG: NCFLAG10 Mask */\r
-#define SCT_CONFLAG_NCFLAG11_Pos 11 /*!< SCT CONFLAG: NCFLAG11 Position */\r
-#define SCT_CONFLAG_NCFLAG11_Msk (0x01UL << SCT_CONFLAG_NCFLAG11_Pos) /*!< SCT CONFLAG: NCFLAG11 Mask */\r
-#define SCT_CONFLAG_NCFLAG12_Pos 12 /*!< SCT CONFLAG: NCFLAG12 Position */\r
-#define SCT_CONFLAG_NCFLAG12_Msk (0x01UL << SCT_CONFLAG_NCFLAG12_Pos) /*!< SCT CONFLAG: NCFLAG12 Mask */\r
-#define SCT_CONFLAG_NCFLAG13_Pos 13 /*!< SCT CONFLAG: NCFLAG13 Position */\r
-#define SCT_CONFLAG_NCFLAG13_Msk (0x01UL << SCT_CONFLAG_NCFLAG13_Pos) /*!< SCT CONFLAG: NCFLAG13 Mask */\r
-#define SCT_CONFLAG_NCFLAG14_Pos 14 /*!< SCT CONFLAG: NCFLAG14 Position */\r
-#define SCT_CONFLAG_NCFLAG14_Msk (0x01UL << SCT_CONFLAG_NCFLAG14_Pos) /*!< SCT CONFLAG: NCFLAG14 Mask */\r
-#define SCT_CONFLAG_NCFLAG15_Pos 15 /*!< SCT CONFLAG: NCFLAG15 Position */\r
-#define SCT_CONFLAG_NCFLAG15_Msk (0x01UL << SCT_CONFLAG_NCFLAG15_Pos) /*!< SCT CONFLAG: NCFLAG15 Mask */\r
-#define SCT_CONFLAG_BUSERRL_Pos 30 /*!< SCT CONFLAG: BUSERRL Position */\r
-#define SCT_CONFLAG_BUSERRL_Msk (0x01UL << SCT_CONFLAG_BUSERRL_Pos) /*!< SCT CONFLAG: BUSERRL Mask */\r
-#define SCT_CONFLAG_BUSERRH_Pos 31 /*!< SCT CONFLAG: BUSERRH Position */\r
-#define SCT_CONFLAG_BUSERRH_Msk (0x01UL << SCT_CONFLAG_BUSERRH_Pos) /*!< SCT CONFLAG: BUSERRH Mask */\r
-\r
-// --------------------------------------- SCT_MATCH0 -------------------------------------------\r
-#define SCT_MATCH0_MATCHn_L_Pos 0 /*!< SCT MATCH0: MATCHn_L Position */\r
-#define SCT_MATCH0_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos) /*!< SCT MATCH0: MATCHn_L Mask */\r
-#define SCT_MATCH0_MATCHn_H_Pos 16 /*!< SCT MATCH0: MATCHn_H Position */\r
-#define SCT_MATCH0_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos) /*!< SCT MATCH0: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP0 --------------------------------------------\r
-#define SCT_CAP0_CAPn_L_Pos 0 /*!< SCT CAP0: CAPn_L Position */\r
-#define SCT_CAP0_CAPn_L_Msk (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos) /*!< SCT CAP0: CAPn_L Mask */\r
-#define SCT_CAP0_CAPn_H_Pos 16 /*!< SCT CAP0: CAPn_H Position */\r
-#define SCT_CAP0_CAPn_H_Msk (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos) /*!< SCT CAP0: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH1 -------------------------------------------\r
-#define SCT_MATCH1_MATCHn_L_Pos 0 /*!< SCT MATCH1: MATCHn_L Position */\r
-#define SCT_MATCH1_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos) /*!< SCT MATCH1: MATCHn_L Mask */\r
-#define SCT_MATCH1_MATCHn_H_Pos 16 /*!< SCT MATCH1: MATCHn_H Position */\r
-#define SCT_MATCH1_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos) /*!< SCT MATCH1: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP1 --------------------------------------------\r
-#define SCT_CAP1_CAPn_L_Pos 0 /*!< SCT CAP1: CAPn_L Position */\r
-#define SCT_CAP1_CAPn_L_Msk (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos) /*!< SCT CAP1: CAPn_L Mask */\r
-#define SCT_CAP1_CAPn_H_Pos 16 /*!< SCT CAP1: CAPn_H Position */\r
-#define SCT_CAP1_CAPn_H_Msk (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos) /*!< SCT CAP1: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH2 -------------------------------------------\r
-#define SCT_MATCH2_MATCHn_L_Pos 0 /*!< SCT MATCH2: MATCHn_L Position */\r
-#define SCT_MATCH2_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos) /*!< SCT MATCH2: MATCHn_L Mask */\r
-#define SCT_MATCH2_MATCHn_H_Pos 16 /*!< SCT MATCH2: MATCHn_H Position */\r
-#define SCT_MATCH2_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos) /*!< SCT MATCH2: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP2 --------------------------------------------\r
-#define SCT_CAP2_CAPn_L_Pos 0 /*!< SCT CAP2: CAPn_L Position */\r
-#define SCT_CAP2_CAPn_L_Msk (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos) /*!< SCT CAP2: CAPn_L Mask */\r
-#define SCT_CAP2_CAPn_H_Pos 16 /*!< SCT CAP2: CAPn_H Position */\r
-#define SCT_CAP2_CAPn_H_Msk (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos) /*!< SCT CAP2: CAPn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP3 --------------------------------------------\r
-#define SCT_CAP3_CAPn_L_Pos 0 /*!< SCT CAP3: CAPn_L Position */\r
-#define SCT_CAP3_CAPn_L_Msk (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos) /*!< SCT CAP3: CAPn_L Mask */\r
-#define SCT_CAP3_CAPn_H_Pos 16 /*!< SCT CAP3: CAPn_H Position */\r
-#define SCT_CAP3_CAPn_H_Msk (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos) /*!< SCT CAP3: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH3 -------------------------------------------\r
-#define SCT_MATCH3_MATCHn_L_Pos 0 /*!< SCT MATCH3: MATCHn_L Position */\r
-#define SCT_MATCH3_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos) /*!< SCT MATCH3: MATCHn_L Mask */\r
-#define SCT_MATCH3_MATCHn_H_Pos 16 /*!< SCT MATCH3: MATCHn_H Position */\r
-#define SCT_MATCH3_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos) /*!< SCT MATCH3: MATCHn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH4 -------------------------------------------\r
-#define SCT_MATCH4_MATCHn_L_Pos 0 /*!< SCT MATCH4: MATCHn_L Position */\r
-#define SCT_MATCH4_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos) /*!< SCT MATCH4: MATCHn_L Mask */\r
-#define SCT_MATCH4_MATCHn_H_Pos 16 /*!< SCT MATCH4: MATCHn_H Position */\r
-#define SCT_MATCH4_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos) /*!< SCT MATCH4: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP4 --------------------------------------------\r
-#define SCT_CAP4_CAPn_L_Pos 0 /*!< SCT CAP4: CAPn_L Position */\r
-#define SCT_CAP4_CAPn_L_Msk (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos) /*!< SCT CAP4: CAPn_L Mask */\r
-#define SCT_CAP4_CAPn_H_Pos 16 /*!< SCT CAP4: CAPn_H Position */\r
-#define SCT_CAP4_CAPn_H_Msk (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos) /*!< SCT CAP4: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH5 -------------------------------------------\r
-#define SCT_MATCH5_MATCHn_L_Pos 0 /*!< SCT MATCH5: MATCHn_L Position */\r
-#define SCT_MATCH5_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos) /*!< SCT MATCH5: MATCHn_L Mask */\r
-#define SCT_MATCH5_MATCHn_H_Pos 16 /*!< SCT MATCH5: MATCHn_H Position */\r
-#define SCT_MATCH5_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos) /*!< SCT MATCH5: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP5 --------------------------------------------\r
-#define SCT_CAP5_CAPn_L_Pos 0 /*!< SCT CAP5: CAPn_L Position */\r
-#define SCT_CAP5_CAPn_L_Msk (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos) /*!< SCT CAP5: CAPn_L Mask */\r
-#define SCT_CAP5_CAPn_H_Pos 16 /*!< SCT CAP5: CAPn_H Position */\r
-#define SCT_CAP5_CAPn_H_Msk (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos) /*!< SCT CAP5: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH6 -------------------------------------------\r
-#define SCT_MATCH6_MATCHn_L_Pos 0 /*!< SCT MATCH6: MATCHn_L Position */\r
-#define SCT_MATCH6_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos) /*!< SCT MATCH6: MATCHn_L Mask */\r
-#define SCT_MATCH6_MATCHn_H_Pos 16 /*!< SCT MATCH6: MATCHn_H Position */\r
-#define SCT_MATCH6_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos) /*!< SCT MATCH6: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP6 --------------------------------------------\r
-#define SCT_CAP6_CAPn_L_Pos 0 /*!< SCT CAP6: CAPn_L Position */\r
-#define SCT_CAP6_CAPn_L_Msk (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos) /*!< SCT CAP6: CAPn_L Mask */\r
-#define SCT_CAP6_CAPn_H_Pos 16 /*!< SCT CAP6: CAPn_H Position */\r
-#define SCT_CAP6_CAPn_H_Msk (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos) /*!< SCT CAP6: CAPn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP7 --------------------------------------------\r
-#define SCT_CAP7_CAPn_L_Pos 0 /*!< SCT CAP7: CAPn_L Position */\r
-#define SCT_CAP7_CAPn_L_Msk (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos) /*!< SCT CAP7: CAPn_L Mask */\r
-#define SCT_CAP7_CAPn_H_Pos 16 /*!< SCT CAP7: CAPn_H Position */\r
-#define SCT_CAP7_CAPn_H_Msk (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos) /*!< SCT CAP7: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH7 -------------------------------------------\r
-#define SCT_MATCH7_MATCHn_L_Pos 0 /*!< SCT MATCH7: MATCHn_L Position */\r
-#define SCT_MATCH7_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos) /*!< SCT MATCH7: MATCHn_L Mask */\r
-#define SCT_MATCH7_MATCHn_H_Pos 16 /*!< SCT MATCH7: MATCHn_H Position */\r
-#define SCT_MATCH7_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos) /*!< SCT MATCH7: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP8 --------------------------------------------\r
-#define SCT_CAP8_CAPn_L_Pos 0 /*!< SCT CAP8: CAPn_L Position */\r
-#define SCT_CAP8_CAPn_L_Msk (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos) /*!< SCT CAP8: CAPn_L Mask */\r
-#define SCT_CAP8_CAPn_H_Pos 16 /*!< SCT CAP8: CAPn_H Position */\r
-#define SCT_CAP8_CAPn_H_Msk (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos) /*!< SCT CAP8: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH8 -------------------------------------------\r
-#define SCT_MATCH8_MATCHn_L_Pos 0 /*!< SCT MATCH8: MATCHn_L Position */\r
-#define SCT_MATCH8_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos) /*!< SCT MATCH8: MATCHn_L Mask */\r
-#define SCT_MATCH8_MATCHn_H_Pos 16 /*!< SCT MATCH8: MATCHn_H Position */\r
-#define SCT_MATCH8_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos) /*!< SCT MATCH8: MATCHn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH9 -------------------------------------------\r
-#define SCT_MATCH9_MATCHn_L_Pos 0 /*!< SCT MATCH9: MATCHn_L Position */\r
-#define SCT_MATCH9_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos) /*!< SCT MATCH9: MATCHn_L Mask */\r
-#define SCT_MATCH9_MATCHn_H_Pos 16 /*!< SCT MATCH9: MATCHn_H Position */\r
-#define SCT_MATCH9_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos) /*!< SCT MATCH9: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP9 --------------------------------------------\r
-#define SCT_CAP9_CAPn_L_Pos 0 /*!< SCT CAP9: CAPn_L Position */\r
-#define SCT_CAP9_CAPn_L_Msk (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos) /*!< SCT CAP9: CAPn_L Mask */\r
-#define SCT_CAP9_CAPn_H_Pos 16 /*!< SCT CAP9: CAPn_H Position */\r
-#define SCT_CAP9_CAPn_H_Msk (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos) /*!< SCT CAP9: CAPn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP10 -------------------------------------------\r
-#define SCT_CAP10_CAPn_L_Pos 0 /*!< SCT CAP10: CAPn_L Position */\r
-#define SCT_CAP10_CAPn_L_Msk (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos) /*!< SCT CAP10: CAPn_L Mask */\r
-#define SCT_CAP10_CAPn_H_Pos 16 /*!< SCT CAP10: CAPn_H Position */\r
-#define SCT_CAP10_CAPn_H_Msk (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos) /*!< SCT CAP10: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH10 ------------------------------------------\r
-#define SCT_MATCH10_MATCHn_L_Pos 0 /*!< SCT MATCH10: MATCHn_L Position */\r
-#define SCT_MATCH10_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos) /*!< SCT MATCH10: MATCHn_L Mask */\r
-#define SCT_MATCH10_MATCHn_H_Pos 16 /*!< SCT MATCH10: MATCHn_H Position */\r
-#define SCT_MATCH10_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos) /*!< SCT MATCH10: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP11 -------------------------------------------\r
-#define SCT_CAP11_CAPn_L_Pos 0 /*!< SCT CAP11: CAPn_L Position */\r
-#define SCT_CAP11_CAPn_L_Msk (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos) /*!< SCT CAP11: CAPn_L Mask */\r
-#define SCT_CAP11_CAPn_H_Pos 16 /*!< SCT CAP11: CAPn_H Position */\r
-#define SCT_CAP11_CAPn_H_Msk (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos) /*!< SCT CAP11: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH11 ------------------------------------------\r
-#define SCT_MATCH11_MATCHn_L_Pos 0 /*!< SCT MATCH11: MATCHn_L Position */\r
-#define SCT_MATCH11_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos) /*!< SCT MATCH11: MATCHn_L Mask */\r
-#define SCT_MATCH11_MATCHn_H_Pos 16 /*!< SCT MATCH11: MATCHn_H Position */\r
-#define SCT_MATCH11_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos) /*!< SCT MATCH11: MATCHn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH12 ------------------------------------------\r
-#define SCT_MATCH12_MATCHn_L_Pos 0 /*!< SCT MATCH12: MATCHn_L Position */\r
-#define SCT_MATCH12_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos) /*!< SCT MATCH12: MATCHn_L Mask */\r
-#define SCT_MATCH12_MATCHn_H_Pos 16 /*!< SCT MATCH12: MATCHn_H Position */\r
-#define SCT_MATCH12_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos) /*!< SCT MATCH12: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP12 -------------------------------------------\r
-#define SCT_CAP12_CAPn_L_Pos 0 /*!< SCT CAP12: CAPn_L Position */\r
-#define SCT_CAP12_CAPn_L_Msk (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos) /*!< SCT CAP12: CAPn_L Mask */\r
-#define SCT_CAP12_CAPn_H_Pos 16 /*!< SCT CAP12: CAPn_H Position */\r
-#define SCT_CAP12_CAPn_H_Msk (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos) /*!< SCT CAP12: CAPn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP13 -------------------------------------------\r
-#define SCT_CAP13_CAPn_L_Pos 0 /*!< SCT CAP13: CAPn_L Position */\r
-#define SCT_CAP13_CAPn_L_Msk (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos) /*!< SCT CAP13: CAPn_L Mask */\r
-#define SCT_CAP13_CAPn_H_Pos 16 /*!< SCT CAP13: CAPn_H Position */\r
-#define SCT_CAP13_CAPn_H_Msk (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos) /*!< SCT CAP13: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH13 ------------------------------------------\r
-#define SCT_MATCH13_MATCHn_L_Pos 0 /*!< SCT MATCH13: MATCHn_L Position */\r
-#define SCT_MATCH13_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos) /*!< SCT MATCH13: MATCHn_L Mask */\r
-#define SCT_MATCH13_MATCHn_H_Pos 16 /*!< SCT MATCH13: MATCHn_H Position */\r
-#define SCT_MATCH13_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos) /*!< SCT MATCH13: MATCHn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH14 ------------------------------------------\r
-#define SCT_MATCH14_MATCHn_L_Pos 0 /*!< SCT MATCH14: MATCHn_L Position */\r
-#define SCT_MATCH14_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos) /*!< SCT MATCH14: MATCHn_L Mask */\r
-#define SCT_MATCH14_MATCHn_H_Pos 16 /*!< SCT MATCH14: MATCHn_H Position */\r
-#define SCT_MATCH14_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos) /*!< SCT MATCH14: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP14 -------------------------------------------\r
-#define SCT_CAP14_CAPn_L_Pos 0 /*!< SCT CAP14: CAPn_L Position */\r
-#define SCT_CAP14_CAPn_L_Msk (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos) /*!< SCT CAP14: CAPn_L Mask */\r
-#define SCT_CAP14_CAPn_H_Pos 16 /*!< SCT CAP14: CAPn_H Position */\r
-#define SCT_CAP14_CAPn_H_Msk (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos) /*!< SCT CAP14: CAPn_H Mask */\r
-\r
-// --------------------------------------- SCT_MATCH15 ------------------------------------------\r
-#define SCT_MATCH15_MATCHn_L_Pos 0 /*!< SCT MATCH15: MATCHn_L Position */\r
-#define SCT_MATCH15_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos) /*!< SCT MATCH15: MATCHn_L Mask */\r
-#define SCT_MATCH15_MATCHn_H_Pos 16 /*!< SCT MATCH15: MATCHn_H Position */\r
-#define SCT_MATCH15_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos) /*!< SCT MATCH15: MATCHn_H Mask */\r
-\r
-// ---------------------------------------- SCT_CAP15 -------------------------------------------\r
-#define SCT_CAP15_CAPn_L_Pos 0 /*!< SCT CAP15: CAPn_L Position */\r
-#define SCT_CAP15_CAPn_L_Msk (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos) /*!< SCT CAP15: CAPn_L Mask */\r
-#define SCT_CAP15_CAPn_H_Pos 16 /*!< SCT CAP15: CAPn_H Position */\r
-#define SCT_CAP15_CAPn_H_Msk (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos) /*!< SCT CAP15: CAPn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL0 -----------------------------------------\r
-#define SCT_MATCHREL0_RELOADn_L_Pos 0 /*!< SCT MATCHREL0: RELOADn_L Position */\r
-#define SCT_MATCHREL0_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos) /*!< SCT MATCHREL0: RELOADn_L Mask */\r
-#define SCT_MATCHREL0_RELOADn_H_Pos 16 /*!< SCT MATCHREL0: RELOADn_H Position */\r
-#define SCT_MATCHREL0_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos) /*!< SCT MATCHREL0: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL0 ------------------------------------------\r
-#define SCT_CAPCTRL0_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL0: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos) /*!< SCT CAPCTRL0: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL0: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos) /*!< SCT CAPCTRL0: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL0: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos) /*!< SCT CAPCTRL0: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL0: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos) /*!< SCT CAPCTRL0: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL0: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos) /*!< SCT CAPCTRL0: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL0: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos) /*!< SCT CAPCTRL0: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL0: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos) /*!< SCT CAPCTRL0: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL0: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos) /*!< SCT CAPCTRL0: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL0: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos) /*!< SCT CAPCTRL0: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL0: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos) /*!< SCT CAPCTRL0: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL0: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos) /*!< SCT CAPCTRL0: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL0: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos) /*!< SCT CAPCTRL0: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL0: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos) /*!< SCT CAPCTRL0: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL0: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos) /*!< SCT CAPCTRL0: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL0: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos) /*!< SCT CAPCTRL0: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL0: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL0_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos) /*!< SCT CAPCTRL0: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL0_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL0: CAPCONn_H Position */\r
-#define SCT_CAPCTRL0_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos) /*!< SCT CAPCTRL0: CAPCONn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL1 -----------------------------------------\r
-#define SCT_MATCHREL1_RELOADn_L_Pos 0 /*!< SCT MATCHREL1: RELOADn_L Position */\r
-#define SCT_MATCHREL1_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos) /*!< SCT MATCHREL1: RELOADn_L Mask */\r
-#define SCT_MATCHREL1_RELOADn_H_Pos 16 /*!< SCT MATCHREL1: RELOADn_H Position */\r
-#define SCT_MATCHREL1_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos) /*!< SCT MATCHREL1: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL1 ------------------------------------------\r
-#define SCT_CAPCTRL1_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL1: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos) /*!< SCT CAPCTRL1: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL1: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos) /*!< SCT CAPCTRL1: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL1: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos) /*!< SCT CAPCTRL1: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL1: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos) /*!< SCT CAPCTRL1: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL1: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos) /*!< SCT CAPCTRL1: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL1: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos) /*!< SCT CAPCTRL1: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL1: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos) /*!< SCT CAPCTRL1: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL1: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos) /*!< SCT CAPCTRL1: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL1: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos) /*!< SCT CAPCTRL1: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL1: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos) /*!< SCT CAPCTRL1: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL1: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos) /*!< SCT CAPCTRL1: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL1: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos) /*!< SCT CAPCTRL1: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL1: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos) /*!< SCT CAPCTRL1: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL1: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos) /*!< SCT CAPCTRL1: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL1: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos) /*!< SCT CAPCTRL1: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL1: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL1_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos) /*!< SCT CAPCTRL1: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL1_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL1: CAPCONn_H Position */\r
-#define SCT_CAPCTRL1_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos) /*!< SCT CAPCTRL1: CAPCONn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL2 -----------------------------------------\r
-#define SCT_MATCHREL2_RELOADn_L_Pos 0 /*!< SCT MATCHREL2: RELOADn_L Position */\r
-#define SCT_MATCHREL2_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos) /*!< SCT MATCHREL2: RELOADn_L Mask */\r
-#define SCT_MATCHREL2_RELOADn_H_Pos 16 /*!< SCT MATCHREL2: RELOADn_H Position */\r
-#define SCT_MATCHREL2_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos) /*!< SCT MATCHREL2: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL2 ------------------------------------------\r
-#define SCT_CAPCTRL2_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL2: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos) /*!< SCT CAPCTRL2: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL2: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos) /*!< SCT CAPCTRL2: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL2: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos) /*!< SCT CAPCTRL2: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL2: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos) /*!< SCT CAPCTRL2: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL2: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos) /*!< SCT CAPCTRL2: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL2: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos) /*!< SCT CAPCTRL2: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL2: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos) /*!< SCT CAPCTRL2: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL2: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos) /*!< SCT CAPCTRL2: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL2: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos) /*!< SCT CAPCTRL2: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL2: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos) /*!< SCT CAPCTRL2: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL2: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos) /*!< SCT CAPCTRL2: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL2: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos) /*!< SCT CAPCTRL2: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL2: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos) /*!< SCT CAPCTRL2: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL2: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos) /*!< SCT CAPCTRL2: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL2: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos) /*!< SCT CAPCTRL2: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL2: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL2_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos) /*!< SCT CAPCTRL2: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL2_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL2: CAPCONn_H Position */\r
-#define SCT_CAPCTRL2_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos) /*!< SCT CAPCTRL2: CAPCONn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL3 -----------------------------------------\r
-#define SCT_MATCHREL3_RELOADn_L_Pos 0 /*!< SCT MATCHREL3: RELOADn_L Position */\r
-#define SCT_MATCHREL3_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos) /*!< SCT MATCHREL3: RELOADn_L Mask */\r
-#define SCT_MATCHREL3_RELOADn_H_Pos 16 /*!< SCT MATCHREL3: RELOADn_H Position */\r
-#define SCT_MATCHREL3_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos) /*!< SCT MATCHREL3: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL3 ------------------------------------------\r
-#define SCT_CAPCTRL3_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL3: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos) /*!< SCT CAPCTRL3: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL3: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos) /*!< SCT CAPCTRL3: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL3: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos) /*!< SCT CAPCTRL3: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL3: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos) /*!< SCT CAPCTRL3: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL3: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos) /*!< SCT CAPCTRL3: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL3: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos) /*!< SCT CAPCTRL3: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL3: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos) /*!< SCT CAPCTRL3: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL3: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos) /*!< SCT CAPCTRL3: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL3: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos) /*!< SCT CAPCTRL3: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL3: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos) /*!< SCT CAPCTRL3: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL3: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos) /*!< SCT CAPCTRL3: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL3: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos) /*!< SCT CAPCTRL3: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL3: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos) /*!< SCT CAPCTRL3: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL3: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos) /*!< SCT CAPCTRL3: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL3: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos) /*!< SCT CAPCTRL3: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL3: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL3_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos) /*!< SCT CAPCTRL3: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL3_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL3: CAPCONn_H Position */\r
-#define SCT_CAPCTRL3_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos) /*!< SCT CAPCTRL3: CAPCONn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL4 ------------------------------------------\r
-#define SCT_CAPCTRL4_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL4: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos) /*!< SCT CAPCTRL4: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL4: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos) /*!< SCT CAPCTRL4: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL4: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos) /*!< SCT CAPCTRL4: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL4: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos) /*!< SCT CAPCTRL4: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL4: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos) /*!< SCT CAPCTRL4: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL4: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos) /*!< SCT CAPCTRL4: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL4: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos) /*!< SCT CAPCTRL4: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL4: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos) /*!< SCT CAPCTRL4: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL4: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos) /*!< SCT CAPCTRL4: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL4: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos) /*!< SCT CAPCTRL4: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL4: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos) /*!< SCT CAPCTRL4: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL4: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos) /*!< SCT CAPCTRL4: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL4: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos) /*!< SCT CAPCTRL4: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL4: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos) /*!< SCT CAPCTRL4: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL4: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos) /*!< SCT CAPCTRL4: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL4: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL4_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos) /*!< SCT CAPCTRL4: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL4_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL4: CAPCONn_H Position */\r
-#define SCT_CAPCTRL4_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos) /*!< SCT CAPCTRL4: CAPCONn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL4 -----------------------------------------\r
-#define SCT_MATCHREL4_RELOADn_L_Pos 0 /*!< SCT MATCHREL4: RELOADn_L Position */\r
-#define SCT_MATCHREL4_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos) /*!< SCT MATCHREL4: RELOADn_L Mask */\r
-#define SCT_MATCHREL4_RELOADn_H_Pos 16 /*!< SCT MATCHREL4: RELOADn_H Position */\r
-#define SCT_MATCHREL4_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos) /*!< SCT MATCHREL4: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL5 ------------------------------------------\r
-#define SCT_CAPCTRL5_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL5: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos) /*!< SCT CAPCTRL5: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL5: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos) /*!< SCT CAPCTRL5: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL5: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos) /*!< SCT CAPCTRL5: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL5: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos) /*!< SCT CAPCTRL5: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL5: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos) /*!< SCT CAPCTRL5: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL5: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos) /*!< SCT CAPCTRL5: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL5: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos) /*!< SCT CAPCTRL5: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL5: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos) /*!< SCT CAPCTRL5: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL5: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos) /*!< SCT CAPCTRL5: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL5: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos) /*!< SCT CAPCTRL5: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL5: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos) /*!< SCT CAPCTRL5: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL5: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos) /*!< SCT CAPCTRL5: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL5: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos) /*!< SCT CAPCTRL5: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL5: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos) /*!< SCT CAPCTRL5: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL5: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos) /*!< SCT CAPCTRL5: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL5: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL5_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos) /*!< SCT CAPCTRL5: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL5_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL5: CAPCONn_H Position */\r
-#define SCT_CAPCTRL5_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos) /*!< SCT CAPCTRL5: CAPCONn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL5 -----------------------------------------\r
-#define SCT_MATCHREL5_RELOADn_L_Pos 0 /*!< SCT MATCHREL5: RELOADn_L Position */\r
-#define SCT_MATCHREL5_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos) /*!< SCT MATCHREL5: RELOADn_L Mask */\r
-#define SCT_MATCHREL5_RELOADn_H_Pos 16 /*!< SCT MATCHREL5: RELOADn_H Position */\r
-#define SCT_MATCHREL5_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos) /*!< SCT MATCHREL5: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL6 -----------------------------------------\r
-#define SCT_MATCHREL6_RELOADn_L_Pos 0 /*!< SCT MATCHREL6: RELOADn_L Position */\r
-#define SCT_MATCHREL6_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos) /*!< SCT MATCHREL6: RELOADn_L Mask */\r
-#define SCT_MATCHREL6_RELOADn_H_Pos 16 /*!< SCT MATCHREL6: RELOADn_H Position */\r
-#define SCT_MATCHREL6_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos) /*!< SCT MATCHREL6: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL6 ------------------------------------------\r
-#define SCT_CAPCTRL6_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL6: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos) /*!< SCT CAPCTRL6: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL6: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos) /*!< SCT CAPCTRL6: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL6: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos) /*!< SCT CAPCTRL6: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL6: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos) /*!< SCT CAPCTRL6: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL6: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos) /*!< SCT CAPCTRL6: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL6: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos) /*!< SCT CAPCTRL6: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL6: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos) /*!< SCT CAPCTRL6: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL6: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos) /*!< SCT CAPCTRL6: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL6: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos) /*!< SCT CAPCTRL6: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL6: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos) /*!< SCT CAPCTRL6: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL6: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos) /*!< SCT CAPCTRL6: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL6: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos) /*!< SCT CAPCTRL6: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL6: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos) /*!< SCT CAPCTRL6: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL6: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos) /*!< SCT CAPCTRL6: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL6: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos) /*!< SCT CAPCTRL6: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL6: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL6_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos) /*!< SCT CAPCTRL6: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL6_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL6: CAPCONn_H Position */\r
-#define SCT_CAPCTRL6_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos) /*!< SCT CAPCTRL6: CAPCONn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL7 ------------------------------------------\r
-#define SCT_CAPCTRL7_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL7: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos) /*!< SCT CAPCTRL7: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL7: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos) /*!< SCT CAPCTRL7: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL7: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos) /*!< SCT CAPCTRL7: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL7: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos) /*!< SCT CAPCTRL7: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL7: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos) /*!< SCT CAPCTRL7: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL7: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos) /*!< SCT CAPCTRL7: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL7: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos) /*!< SCT CAPCTRL7: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL7: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos) /*!< SCT CAPCTRL7: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL7: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos) /*!< SCT CAPCTRL7: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL7: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos) /*!< SCT CAPCTRL7: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL7: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos) /*!< SCT CAPCTRL7: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL7: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos) /*!< SCT CAPCTRL7: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL7: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos) /*!< SCT CAPCTRL7: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL7: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos) /*!< SCT CAPCTRL7: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL7: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos) /*!< SCT CAPCTRL7: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL7: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL7_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos) /*!< SCT CAPCTRL7: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL7_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL7: CAPCONn_H Position */\r
-#define SCT_CAPCTRL7_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos) /*!< SCT CAPCTRL7: CAPCONn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL7 -----------------------------------------\r
-#define SCT_MATCHREL7_RELOADn_L_Pos 0 /*!< SCT MATCHREL7: RELOADn_L Position */\r
-#define SCT_MATCHREL7_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos) /*!< SCT MATCHREL7: RELOADn_L Mask */\r
-#define SCT_MATCHREL7_RELOADn_H_Pos 16 /*!< SCT MATCHREL7: RELOADn_H Position */\r
-#define SCT_MATCHREL7_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos) /*!< SCT MATCHREL7: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL8 ------------------------------------------\r
-#define SCT_CAPCTRL8_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL8: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos) /*!< SCT CAPCTRL8: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL8: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos) /*!< SCT CAPCTRL8: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL8: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos) /*!< SCT CAPCTRL8: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL8: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos) /*!< SCT CAPCTRL8: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL8: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos) /*!< SCT CAPCTRL8: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL8: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos) /*!< SCT CAPCTRL8: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL8: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos) /*!< SCT CAPCTRL8: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL8: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos) /*!< SCT CAPCTRL8: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL8: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos) /*!< SCT CAPCTRL8: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL8: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos) /*!< SCT CAPCTRL8: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL8: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos) /*!< SCT CAPCTRL8: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL8: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos) /*!< SCT CAPCTRL8: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL8: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos) /*!< SCT CAPCTRL8: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL8: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos) /*!< SCT CAPCTRL8: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL8: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos) /*!< SCT CAPCTRL8: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL8: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL8_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos) /*!< SCT CAPCTRL8: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL8_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL8: CAPCONn_H Position */\r
-#define SCT_CAPCTRL8_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos) /*!< SCT CAPCTRL8: CAPCONn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL8 -----------------------------------------\r
-#define SCT_MATCHREL8_RELOADn_L_Pos 0 /*!< SCT MATCHREL8: RELOADn_L Position */\r
-#define SCT_MATCHREL8_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos) /*!< SCT MATCHREL8: RELOADn_L Mask */\r
-#define SCT_MATCHREL8_RELOADn_H_Pos 16 /*!< SCT MATCHREL8: RELOADn_H Position */\r
-#define SCT_MATCHREL8_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos) /*!< SCT MATCHREL8: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_MATCHREL9 -----------------------------------------\r
-#define SCT_MATCHREL9_RELOADn_L_Pos 0 /*!< SCT MATCHREL9: RELOADn_L Position */\r
-#define SCT_MATCHREL9_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos) /*!< SCT MATCHREL9: RELOADn_L Mask */\r
-#define SCT_MATCHREL9_RELOADn_H_Pos 16 /*!< SCT MATCHREL9: RELOADn_H Position */\r
-#define SCT_MATCHREL9_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos) /*!< SCT MATCHREL9: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL9 ------------------------------------------\r
-#define SCT_CAPCTRL9_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL9: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos) /*!< SCT CAPCTRL9: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL9: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos) /*!< SCT CAPCTRL9: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL9: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos) /*!< SCT CAPCTRL9: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL9: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos) /*!< SCT CAPCTRL9: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL9: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos) /*!< SCT CAPCTRL9: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL9: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos) /*!< SCT CAPCTRL9: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL9: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos) /*!< SCT CAPCTRL9: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL9: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos) /*!< SCT CAPCTRL9: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL9: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos) /*!< SCT CAPCTRL9: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL9: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos) /*!< SCT CAPCTRL9: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL9: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos) /*!< SCT CAPCTRL9: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL9: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos) /*!< SCT CAPCTRL9: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL9: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos) /*!< SCT CAPCTRL9: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL9: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos) /*!< SCT CAPCTRL9: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL9: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos) /*!< SCT CAPCTRL9: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL9: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL9_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos) /*!< SCT CAPCTRL9: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL9_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL9: CAPCONn_H Position */\r
-#define SCT_CAPCTRL9_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos) /*!< SCT CAPCTRL9: CAPCONn_H Mask */\r
-\r
-// ------------------------------------- SCT_MATCHREL10 -----------------------------------------\r
-#define SCT_MATCHREL10_RELOADn_L_Pos 0 /*!< SCT MATCHREL10: RELOADn_L Position */\r
-#define SCT_MATCHREL10_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos) /*!< SCT MATCHREL10: RELOADn_L Mask */\r
-#define SCT_MATCHREL10_RELOADn_H_Pos 16 /*!< SCT MATCHREL10: RELOADn_H Position */\r
-#define SCT_MATCHREL10_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos) /*!< SCT MATCHREL10: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL10 -----------------------------------------\r
-#define SCT_CAPCTRL10_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL10: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos) /*!< SCT CAPCTRL10: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL10: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos) /*!< SCT CAPCTRL10: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL10: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos) /*!< SCT CAPCTRL10: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL10: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos) /*!< SCT CAPCTRL10: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL10: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos) /*!< SCT CAPCTRL10: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL10: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos) /*!< SCT CAPCTRL10: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL10: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos) /*!< SCT CAPCTRL10: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL10: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos) /*!< SCT CAPCTRL10: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL10: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos) /*!< SCT CAPCTRL10: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL10: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos) /*!< SCT CAPCTRL10: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL10: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos) /*!< SCT CAPCTRL10: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL10: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos) /*!< SCT CAPCTRL10: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL10: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos) /*!< SCT CAPCTRL10: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL10: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos) /*!< SCT CAPCTRL10: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL10: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos) /*!< SCT CAPCTRL10: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL10: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL10_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos) /*!< SCT CAPCTRL10: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL10_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL10: CAPCONn_H Position */\r
-#define SCT_CAPCTRL10_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos) /*!< SCT CAPCTRL10: CAPCONn_H Mask */\r
-\r
-// ------------------------------------- SCT_MATCHREL11 -----------------------------------------\r
-#define SCT_MATCHREL11_RELOADn_L_Pos 0 /*!< SCT MATCHREL11: RELOADn_L Position */\r
-#define SCT_MATCHREL11_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos) /*!< SCT MATCHREL11: RELOADn_L Mask */\r
-#define SCT_MATCHREL11_RELOADn_H_Pos 16 /*!< SCT MATCHREL11: RELOADn_H Position */\r
-#define SCT_MATCHREL11_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos) /*!< SCT MATCHREL11: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL11 -----------------------------------------\r
-#define SCT_CAPCTRL11_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL11: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos) /*!< SCT CAPCTRL11: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL11: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos) /*!< SCT CAPCTRL11: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL11: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos) /*!< SCT CAPCTRL11: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL11: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos) /*!< SCT CAPCTRL11: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL11: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos) /*!< SCT CAPCTRL11: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL11: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos) /*!< SCT CAPCTRL11: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL11: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos) /*!< SCT CAPCTRL11: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL11: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos) /*!< SCT CAPCTRL11: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL11: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos) /*!< SCT CAPCTRL11: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL11: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos) /*!< SCT CAPCTRL11: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL11: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos) /*!< SCT CAPCTRL11: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL11: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos) /*!< SCT CAPCTRL11: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL11: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos) /*!< SCT CAPCTRL11: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL11: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos) /*!< SCT CAPCTRL11: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL11: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos) /*!< SCT CAPCTRL11: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL11: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL11_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos) /*!< SCT CAPCTRL11: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL11_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL11: CAPCONn_H Position */\r
-#define SCT_CAPCTRL11_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos) /*!< SCT CAPCTRL11: CAPCONn_H Mask */\r
-\r
-// ------------------------------------- SCT_MATCHREL12 -----------------------------------------\r
-#define SCT_MATCHREL12_RELOADn_L_Pos 0 /*!< SCT MATCHREL12: RELOADn_L Position */\r
-#define SCT_MATCHREL12_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos) /*!< SCT MATCHREL12: RELOADn_L Mask */\r
-#define SCT_MATCHREL12_RELOADn_H_Pos 16 /*!< SCT MATCHREL12: RELOADn_H Position */\r
-#define SCT_MATCHREL12_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos) /*!< SCT MATCHREL12: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL12 -----------------------------------------\r
-#define SCT_CAPCTRL12_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL12: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos) /*!< SCT CAPCTRL12: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL12: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos) /*!< SCT CAPCTRL12: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL12: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos) /*!< SCT CAPCTRL12: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL12: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos) /*!< SCT CAPCTRL12: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL12: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos) /*!< SCT CAPCTRL12: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL12: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos) /*!< SCT CAPCTRL12: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL12: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos) /*!< SCT CAPCTRL12: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL12: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos) /*!< SCT CAPCTRL12: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL12: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos) /*!< SCT CAPCTRL12: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL12: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos) /*!< SCT CAPCTRL12: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL12: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos) /*!< SCT CAPCTRL12: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL12: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos) /*!< SCT CAPCTRL12: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL12: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos) /*!< SCT CAPCTRL12: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL12: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos) /*!< SCT CAPCTRL12: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL12: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos) /*!< SCT CAPCTRL12: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL12: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL12_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos) /*!< SCT CAPCTRL12: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL12_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL12: CAPCONn_H Position */\r
-#define SCT_CAPCTRL12_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos) /*!< SCT CAPCTRL12: CAPCONn_H Mask */\r
-\r
-// ------------------------------------- SCT_MATCHREL13 -----------------------------------------\r
-#define SCT_MATCHREL13_RELOADn_L_Pos 0 /*!< SCT MATCHREL13: RELOADn_L Position */\r
-#define SCT_MATCHREL13_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos) /*!< SCT MATCHREL13: RELOADn_L Mask */\r
-#define SCT_MATCHREL13_RELOADn_H_Pos 16 /*!< SCT MATCHREL13: RELOADn_H Position */\r
-#define SCT_MATCHREL13_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos) /*!< SCT MATCHREL13: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL13 -----------------------------------------\r
-#define SCT_CAPCTRL13_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL13: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos) /*!< SCT CAPCTRL13: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL13: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos) /*!< SCT CAPCTRL13: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL13: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos) /*!< SCT CAPCTRL13: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL13: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos) /*!< SCT CAPCTRL13: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL13: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos) /*!< SCT CAPCTRL13: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL13: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos) /*!< SCT CAPCTRL13: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL13: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos) /*!< SCT CAPCTRL13: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL13: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos) /*!< SCT CAPCTRL13: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL13: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos) /*!< SCT CAPCTRL13: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL13: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos) /*!< SCT CAPCTRL13: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL13: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos) /*!< SCT CAPCTRL13: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL13: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos) /*!< SCT CAPCTRL13: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL13: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos) /*!< SCT CAPCTRL13: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL13: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos) /*!< SCT CAPCTRL13: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL13: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos) /*!< SCT CAPCTRL13: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL13: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL13_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos) /*!< SCT CAPCTRL13: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL13_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL13: CAPCONn_H Position */\r
-#define SCT_CAPCTRL13_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos) /*!< SCT CAPCTRL13: CAPCONn_H Mask */\r
-\r
-// ------------------------------------- SCT_MATCHREL14 -----------------------------------------\r
-#define SCT_MATCHREL14_RELOADn_L_Pos 0 /*!< SCT MATCHREL14: RELOADn_L Position */\r
-#define SCT_MATCHREL14_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos) /*!< SCT MATCHREL14: RELOADn_L Mask */\r
-#define SCT_MATCHREL14_RELOADn_H_Pos 16 /*!< SCT MATCHREL14: RELOADn_H Position */\r
-#define SCT_MATCHREL14_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos) /*!< SCT MATCHREL14: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL14 -----------------------------------------\r
-#define SCT_CAPCTRL14_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL14: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos) /*!< SCT CAPCTRL14: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL14: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos) /*!< SCT CAPCTRL14: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL14: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos) /*!< SCT CAPCTRL14: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL14: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos) /*!< SCT CAPCTRL14: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL14: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos) /*!< SCT CAPCTRL14: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL14: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos) /*!< SCT CAPCTRL14: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL14: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos) /*!< SCT CAPCTRL14: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL14: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos) /*!< SCT CAPCTRL14: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL14: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos) /*!< SCT CAPCTRL14: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL14: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos) /*!< SCT CAPCTRL14: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL14: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos) /*!< SCT CAPCTRL14: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL14: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos) /*!< SCT CAPCTRL14: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL14: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos) /*!< SCT CAPCTRL14: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL14: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos) /*!< SCT CAPCTRL14: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL14: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos) /*!< SCT CAPCTRL14: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL14: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL14_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos) /*!< SCT CAPCTRL14: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL14_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL14: CAPCONn_H Position */\r
-#define SCT_CAPCTRL14_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos) /*!< SCT CAPCTRL14: CAPCONn_H Mask */\r
-\r
-// ------------------------------------- SCT_MATCHREL15 -----------------------------------------\r
-#define SCT_MATCHREL15_RELOADn_L_Pos 0 /*!< SCT MATCHREL15: RELOADn_L Position */\r
-#define SCT_MATCHREL15_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos) /*!< SCT MATCHREL15: RELOADn_L Mask */\r
-#define SCT_MATCHREL15_RELOADn_H_Pos 16 /*!< SCT MATCHREL15: RELOADn_H Position */\r
-#define SCT_MATCHREL15_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos) /*!< SCT MATCHREL15: RELOADn_H Mask */\r
-\r
-// -------------------------------------- SCT_CAPCTRL15 -----------------------------------------\r
-#define SCT_CAPCTRL15_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL15: CAPCONn_L0 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos) /*!< SCT CAPCTRL15: CAPCONn_L0 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL15: CAPCONn_L1 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos) /*!< SCT CAPCTRL15: CAPCONn_L1 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL15: CAPCONn_L2 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos) /*!< SCT CAPCTRL15: CAPCONn_L2 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL15: CAPCONn_L3 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos) /*!< SCT CAPCTRL15: CAPCONn_L3 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL15: CAPCONn_L4 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos) /*!< SCT CAPCTRL15: CAPCONn_L4 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL15: CAPCONn_L5 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos) /*!< SCT CAPCTRL15: CAPCONn_L5 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL15: CAPCONn_L6 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos) /*!< SCT CAPCTRL15: CAPCONn_L6 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL15: CAPCONn_L7 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos) /*!< SCT CAPCTRL15: CAPCONn_L7 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL15: CAPCONn_L8 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos) /*!< SCT CAPCTRL15: CAPCONn_L8 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL15: CAPCONn_L9 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos) /*!< SCT CAPCTRL15: CAPCONn_L9 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL15: CAPCONn_L10 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos) /*!< SCT CAPCTRL15: CAPCONn_L10 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL15: CAPCONn_L11 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos) /*!< SCT CAPCTRL15: CAPCONn_L11 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL15: CAPCONn_L12 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos) /*!< SCT CAPCTRL15: CAPCONn_L12 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL15: CAPCONn_L13 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos) /*!< SCT CAPCTRL15: CAPCONn_L13 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL15: CAPCONn_L14 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos) /*!< SCT CAPCTRL15: CAPCONn_L14 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL15: CAPCONn_L15 Position */\r
-#define SCT_CAPCTRL15_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos) /*!< SCT CAPCTRL15: CAPCONn_L15 Mask */\r
-#define SCT_CAPCTRL15_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL15: CAPCONn_H Position */\r
-#define SCT_CAPCTRL15_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos) /*!< SCT CAPCTRL15: CAPCONn_H Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK0 ----------------------------------------\r
-#define SCT_EVSTATEMSK0_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK0: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK0: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK0: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK0: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK0: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK0: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK0: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK0: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK0: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK0: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK0: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK0: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK0: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK0: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK0: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK0: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK0: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK0: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK0: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK0: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK0: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK0: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK0: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK0: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK0: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK0: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK0: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK0: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK0: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK0: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK0: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK0_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK0: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK0_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL0 ------------------------------------------\r
-#define SCT_EVCTRL0_MATCHSEL_Pos 0 /*!< SCT EVCTRL0: MATCHSEL Position */\r
-#define SCT_EVCTRL0_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos) /*!< SCT EVCTRL0: MATCHSEL Mask */\r
-#define SCT_EVCTRL0_HEVENT_Pos 4 /*!< SCT EVCTRL0: HEVENT Position */\r
-#define SCT_EVCTRL0_HEVENT_Msk (0x01UL << SCT_EVCTRL0_HEVENT_Pos) /*!< SCT EVCTRL0: HEVENT Mask */\r
-#define SCT_EVCTRL0_OUTSEL_Pos 5 /*!< SCT EVCTRL0: OUTSEL Position */\r
-#define SCT_EVCTRL0_OUTSEL_Msk (0x01UL << SCT_EVCTRL0_OUTSEL_Pos) /*!< SCT EVCTRL0: OUTSEL Mask */\r
-#define SCT_EVCTRL0_IOSEL_Pos 6 /*!< SCT EVCTRL0: IOSEL Position */\r
-#define SCT_EVCTRL0_IOSEL_Msk (0x0fUL << SCT_EVCTRL0_IOSEL_Pos) /*!< SCT EVCTRL0: IOSEL Mask */\r
-#define SCT_EVCTRL0_IOCOND_Pos 10 /*!< SCT EVCTRL0: IOCOND Position */\r
-#define SCT_EVCTRL0_IOCOND_Msk (0x03UL << SCT_EVCTRL0_IOCOND_Pos) /*!< SCT EVCTRL0: IOCOND Mask */\r
-#define SCT_EVCTRL0_COMBMODE_Pos 12 /*!< SCT EVCTRL0: COMBMODE Position */\r
-#define SCT_EVCTRL0_COMBMODE_Msk (0x03UL << SCT_EVCTRL0_COMBMODE_Pos) /*!< SCT EVCTRL0: COMBMODE Mask */\r
-#define SCT_EVCTRL0_STATELD_Pos 14 /*!< SCT EVCTRL0: STATELD Position */\r
-#define SCT_EVCTRL0_STATELD_Msk (0x01UL << SCT_EVCTRL0_STATELD_Pos) /*!< SCT EVCTRL0: STATELD Mask */\r
-#define SCT_EVCTRL0_STATEV_Pos 15 /*!< SCT EVCTRL0: STATEV Position */\r
-#define SCT_EVCTRL0_STATEV_Msk (0x1fUL << SCT_EVCTRL0_STATEV_Pos) /*!< SCT EVCTRL0: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK1 ----------------------------------------\r
-#define SCT_EVSTATEMSK1_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK1: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK1: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK1: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK1: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK1: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK1: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK1: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK1: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK1: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK1: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK1: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK1: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK1: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK1: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK1: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK1: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK1: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK1: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK1: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK1: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK1: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK1: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK1: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK1: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK1: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK1: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK1: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK1: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK1: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK1: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK1: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK1_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK1: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK1_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL1 ------------------------------------------\r
-#define SCT_EVCTRL1_MATCHSEL_Pos 0 /*!< SCT EVCTRL1: MATCHSEL Position */\r
-#define SCT_EVCTRL1_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos) /*!< SCT EVCTRL1: MATCHSEL Mask */\r
-#define SCT_EVCTRL1_HEVENT_Pos 4 /*!< SCT EVCTRL1: HEVENT Position */\r
-#define SCT_EVCTRL1_HEVENT_Msk (0x01UL << SCT_EVCTRL1_HEVENT_Pos) /*!< SCT EVCTRL1: HEVENT Mask */\r
-#define SCT_EVCTRL1_OUTSEL_Pos 5 /*!< SCT EVCTRL1: OUTSEL Position */\r
-#define SCT_EVCTRL1_OUTSEL_Msk (0x01UL << SCT_EVCTRL1_OUTSEL_Pos) /*!< SCT EVCTRL1: OUTSEL Mask */\r
-#define SCT_EVCTRL1_IOSEL_Pos 6 /*!< SCT EVCTRL1: IOSEL Position */\r
-#define SCT_EVCTRL1_IOSEL_Msk (0x0fUL << SCT_EVCTRL1_IOSEL_Pos) /*!< SCT EVCTRL1: IOSEL Mask */\r
-#define SCT_EVCTRL1_IOCOND_Pos 10 /*!< SCT EVCTRL1: IOCOND Position */\r
-#define SCT_EVCTRL1_IOCOND_Msk (0x03UL << SCT_EVCTRL1_IOCOND_Pos) /*!< SCT EVCTRL1: IOCOND Mask */\r
-#define SCT_EVCTRL1_COMBMODE_Pos 12 /*!< SCT EVCTRL1: COMBMODE Position */\r
-#define SCT_EVCTRL1_COMBMODE_Msk (0x03UL << SCT_EVCTRL1_COMBMODE_Pos) /*!< SCT EVCTRL1: COMBMODE Mask */\r
-#define SCT_EVCTRL1_STATELD_Pos 14 /*!< SCT EVCTRL1: STATELD Position */\r
-#define SCT_EVCTRL1_STATELD_Msk (0x01UL << SCT_EVCTRL1_STATELD_Pos) /*!< SCT EVCTRL1: STATELD Mask */\r
-#define SCT_EVCTRL1_STATEV_Pos 15 /*!< SCT EVCTRL1: STATEV Position */\r
-#define SCT_EVCTRL1_STATEV_Msk (0x1fUL << SCT_EVCTRL1_STATEV_Pos) /*!< SCT EVCTRL1: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK2 ----------------------------------------\r
-#define SCT_EVSTATEMSK2_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK2: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK2: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK2: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK2: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK2: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK2: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK2: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK2: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK2: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK2: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK2: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK2: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK2: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK2: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK2: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK2: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK2: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK2: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK2: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK2: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK2: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK2: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK2: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK2: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK2: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK2: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK2: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK2: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK2: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK2: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK2: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK2_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK2: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK2_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL2 ------------------------------------------\r
-#define SCT_EVCTRL2_MATCHSEL_Pos 0 /*!< SCT EVCTRL2: MATCHSEL Position */\r
-#define SCT_EVCTRL2_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos) /*!< SCT EVCTRL2: MATCHSEL Mask */\r
-#define SCT_EVCTRL2_HEVENT_Pos 4 /*!< SCT EVCTRL2: HEVENT Position */\r
-#define SCT_EVCTRL2_HEVENT_Msk (0x01UL << SCT_EVCTRL2_HEVENT_Pos) /*!< SCT EVCTRL2: HEVENT Mask */\r
-#define SCT_EVCTRL2_OUTSEL_Pos 5 /*!< SCT EVCTRL2: OUTSEL Position */\r
-#define SCT_EVCTRL2_OUTSEL_Msk (0x01UL << SCT_EVCTRL2_OUTSEL_Pos) /*!< SCT EVCTRL2: OUTSEL Mask */\r
-#define SCT_EVCTRL2_IOSEL_Pos 6 /*!< SCT EVCTRL2: IOSEL Position */\r
-#define SCT_EVCTRL2_IOSEL_Msk (0x0fUL << SCT_EVCTRL2_IOSEL_Pos) /*!< SCT EVCTRL2: IOSEL Mask */\r
-#define SCT_EVCTRL2_IOCOND_Pos 10 /*!< SCT EVCTRL2: IOCOND Position */\r
-#define SCT_EVCTRL2_IOCOND_Msk (0x03UL << SCT_EVCTRL2_IOCOND_Pos) /*!< SCT EVCTRL2: IOCOND Mask */\r
-#define SCT_EVCTRL2_COMBMODE_Pos 12 /*!< SCT EVCTRL2: COMBMODE Position */\r
-#define SCT_EVCTRL2_COMBMODE_Msk (0x03UL << SCT_EVCTRL2_COMBMODE_Pos) /*!< SCT EVCTRL2: COMBMODE Mask */\r
-#define SCT_EVCTRL2_STATELD_Pos 14 /*!< SCT EVCTRL2: STATELD Position */\r
-#define SCT_EVCTRL2_STATELD_Msk (0x01UL << SCT_EVCTRL2_STATELD_Pos) /*!< SCT EVCTRL2: STATELD Mask */\r
-#define SCT_EVCTRL2_STATEV_Pos 15 /*!< SCT EVCTRL2: STATEV Position */\r
-#define SCT_EVCTRL2_STATEV_Msk (0x1fUL << SCT_EVCTRL2_STATEV_Pos) /*!< SCT EVCTRL2: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK3 ----------------------------------------\r
-#define SCT_EVSTATEMSK3_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK3: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK3: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK3: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK3: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK3: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK3: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK3: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK3: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK3: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK3: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK3: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK3: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK3: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK3: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK3: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK3: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK3: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK3: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK3: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK3: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK3: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK3: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK3: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK3: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK3: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK3: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK3: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK3: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK3: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK3: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK3: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK3_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK3: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK3_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL3 ------------------------------------------\r
-#define SCT_EVCTRL3_MATCHSEL_Pos 0 /*!< SCT EVCTRL3: MATCHSEL Position */\r
-#define SCT_EVCTRL3_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos) /*!< SCT EVCTRL3: MATCHSEL Mask */\r
-#define SCT_EVCTRL3_HEVENT_Pos 4 /*!< SCT EVCTRL3: HEVENT Position */\r
-#define SCT_EVCTRL3_HEVENT_Msk (0x01UL << SCT_EVCTRL3_HEVENT_Pos) /*!< SCT EVCTRL3: HEVENT Mask */\r
-#define SCT_EVCTRL3_OUTSEL_Pos 5 /*!< SCT EVCTRL3: OUTSEL Position */\r
-#define SCT_EVCTRL3_OUTSEL_Msk (0x01UL << SCT_EVCTRL3_OUTSEL_Pos) /*!< SCT EVCTRL3: OUTSEL Mask */\r
-#define SCT_EVCTRL3_IOSEL_Pos 6 /*!< SCT EVCTRL3: IOSEL Position */\r
-#define SCT_EVCTRL3_IOSEL_Msk (0x0fUL << SCT_EVCTRL3_IOSEL_Pos) /*!< SCT EVCTRL3: IOSEL Mask */\r
-#define SCT_EVCTRL3_IOCOND_Pos 10 /*!< SCT EVCTRL3: IOCOND Position */\r
-#define SCT_EVCTRL3_IOCOND_Msk (0x03UL << SCT_EVCTRL3_IOCOND_Pos) /*!< SCT EVCTRL3: IOCOND Mask */\r
-#define SCT_EVCTRL3_COMBMODE_Pos 12 /*!< SCT EVCTRL3: COMBMODE Position */\r
-#define SCT_EVCTRL3_COMBMODE_Msk (0x03UL << SCT_EVCTRL3_COMBMODE_Pos) /*!< SCT EVCTRL3: COMBMODE Mask */\r
-#define SCT_EVCTRL3_STATELD_Pos 14 /*!< SCT EVCTRL3: STATELD Position */\r
-#define SCT_EVCTRL3_STATELD_Msk (0x01UL << SCT_EVCTRL3_STATELD_Pos) /*!< SCT EVCTRL3: STATELD Mask */\r
-#define SCT_EVCTRL3_STATEV_Pos 15 /*!< SCT EVCTRL3: STATEV Position */\r
-#define SCT_EVCTRL3_STATEV_Msk (0x1fUL << SCT_EVCTRL3_STATEV_Pos) /*!< SCT EVCTRL3: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK4 ----------------------------------------\r
-#define SCT_EVSTATEMSK4_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK4: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK4: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK4: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK4: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK4: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK4: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK4: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK4: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK4: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK4: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK4: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK4: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK4: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK4: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK4: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK4: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK4: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK4: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK4: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK4: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK4: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK4: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK4: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK4: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK4: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK4: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK4: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK4: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK4: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK4: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK4: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK4_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK4: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK4_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL4 ------------------------------------------\r
-#define SCT_EVCTRL4_MATCHSEL_Pos 0 /*!< SCT EVCTRL4: MATCHSEL Position */\r
-#define SCT_EVCTRL4_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos) /*!< SCT EVCTRL4: MATCHSEL Mask */\r
-#define SCT_EVCTRL4_HEVENT_Pos 4 /*!< SCT EVCTRL4: HEVENT Position */\r
-#define SCT_EVCTRL4_HEVENT_Msk (0x01UL << SCT_EVCTRL4_HEVENT_Pos) /*!< SCT EVCTRL4: HEVENT Mask */\r
-#define SCT_EVCTRL4_OUTSEL_Pos 5 /*!< SCT EVCTRL4: OUTSEL Position */\r
-#define SCT_EVCTRL4_OUTSEL_Msk (0x01UL << SCT_EVCTRL4_OUTSEL_Pos) /*!< SCT EVCTRL4: OUTSEL Mask */\r
-#define SCT_EVCTRL4_IOSEL_Pos 6 /*!< SCT EVCTRL4: IOSEL Position */\r
-#define SCT_EVCTRL4_IOSEL_Msk (0x0fUL << SCT_EVCTRL4_IOSEL_Pos) /*!< SCT EVCTRL4: IOSEL Mask */\r
-#define SCT_EVCTRL4_IOCOND_Pos 10 /*!< SCT EVCTRL4: IOCOND Position */\r
-#define SCT_EVCTRL4_IOCOND_Msk (0x03UL << SCT_EVCTRL4_IOCOND_Pos) /*!< SCT EVCTRL4: IOCOND Mask */\r
-#define SCT_EVCTRL4_COMBMODE_Pos 12 /*!< SCT EVCTRL4: COMBMODE Position */\r
-#define SCT_EVCTRL4_COMBMODE_Msk (0x03UL << SCT_EVCTRL4_COMBMODE_Pos) /*!< SCT EVCTRL4: COMBMODE Mask */\r
-#define SCT_EVCTRL4_STATELD_Pos 14 /*!< SCT EVCTRL4: STATELD Position */\r
-#define SCT_EVCTRL4_STATELD_Msk (0x01UL << SCT_EVCTRL4_STATELD_Pos) /*!< SCT EVCTRL4: STATELD Mask */\r
-#define SCT_EVCTRL4_STATEV_Pos 15 /*!< SCT EVCTRL4: STATEV Position */\r
-#define SCT_EVCTRL4_STATEV_Msk (0x1fUL << SCT_EVCTRL4_STATEV_Pos) /*!< SCT EVCTRL4: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK5 ----------------------------------------\r
-#define SCT_EVSTATEMSK5_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK5: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK5: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK5: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK5: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK5: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK5: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK5: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK5: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK5: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK5: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK5: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK5: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK5: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK5: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK5: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK5: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK5: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK5: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK5: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK5: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK5: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK5: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK5: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK5: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK5: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK5: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK5: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK5: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK5: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK5: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK5: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK5_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK5: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK5_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL5 ------------------------------------------\r
-#define SCT_EVCTRL5_MATCHSEL_Pos 0 /*!< SCT EVCTRL5: MATCHSEL Position */\r
-#define SCT_EVCTRL5_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos) /*!< SCT EVCTRL5: MATCHSEL Mask */\r
-#define SCT_EVCTRL5_HEVENT_Pos 4 /*!< SCT EVCTRL5: HEVENT Position */\r
-#define SCT_EVCTRL5_HEVENT_Msk (0x01UL << SCT_EVCTRL5_HEVENT_Pos) /*!< SCT EVCTRL5: HEVENT Mask */\r
-#define SCT_EVCTRL5_OUTSEL_Pos 5 /*!< SCT EVCTRL5: OUTSEL Position */\r
-#define SCT_EVCTRL5_OUTSEL_Msk (0x01UL << SCT_EVCTRL5_OUTSEL_Pos) /*!< SCT EVCTRL5: OUTSEL Mask */\r
-#define SCT_EVCTRL5_IOSEL_Pos 6 /*!< SCT EVCTRL5: IOSEL Position */\r
-#define SCT_EVCTRL5_IOSEL_Msk (0x0fUL << SCT_EVCTRL5_IOSEL_Pos) /*!< SCT EVCTRL5: IOSEL Mask */\r
-#define SCT_EVCTRL5_IOCOND_Pos 10 /*!< SCT EVCTRL5: IOCOND Position */\r
-#define SCT_EVCTRL5_IOCOND_Msk (0x03UL << SCT_EVCTRL5_IOCOND_Pos) /*!< SCT EVCTRL5: IOCOND Mask */\r
-#define SCT_EVCTRL5_COMBMODE_Pos 12 /*!< SCT EVCTRL5: COMBMODE Position */\r
-#define SCT_EVCTRL5_COMBMODE_Msk (0x03UL << SCT_EVCTRL5_COMBMODE_Pos) /*!< SCT EVCTRL5: COMBMODE Mask */\r
-#define SCT_EVCTRL5_STATELD_Pos 14 /*!< SCT EVCTRL5: STATELD Position */\r
-#define SCT_EVCTRL5_STATELD_Msk (0x01UL << SCT_EVCTRL5_STATELD_Pos) /*!< SCT EVCTRL5: STATELD Mask */\r
-#define SCT_EVCTRL5_STATEV_Pos 15 /*!< SCT EVCTRL5: STATEV Position */\r
-#define SCT_EVCTRL5_STATEV_Msk (0x1fUL << SCT_EVCTRL5_STATEV_Pos) /*!< SCT EVCTRL5: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK6 ----------------------------------------\r
-#define SCT_EVSTATEMSK6_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK6: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK6: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK6: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK6: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK6: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK6: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK6: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK6: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK6: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK6: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK6: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK6: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK6: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK6: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK6: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK6: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK6: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK6: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK6: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK6: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK6: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK6: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK6: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK6: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK6: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK6: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK6: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK6: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK6: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK6: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK6: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK6_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK6: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK6_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL6 ------------------------------------------\r
-#define SCT_EVCTRL6_MATCHSEL_Pos 0 /*!< SCT EVCTRL6: MATCHSEL Position */\r
-#define SCT_EVCTRL6_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos) /*!< SCT EVCTRL6: MATCHSEL Mask */\r
-#define SCT_EVCTRL6_HEVENT_Pos 4 /*!< SCT EVCTRL6: HEVENT Position */\r
-#define SCT_EVCTRL6_HEVENT_Msk (0x01UL << SCT_EVCTRL6_HEVENT_Pos) /*!< SCT EVCTRL6: HEVENT Mask */\r
-#define SCT_EVCTRL6_OUTSEL_Pos 5 /*!< SCT EVCTRL6: OUTSEL Position */\r
-#define SCT_EVCTRL6_OUTSEL_Msk (0x01UL << SCT_EVCTRL6_OUTSEL_Pos) /*!< SCT EVCTRL6: OUTSEL Mask */\r
-#define SCT_EVCTRL6_IOSEL_Pos 6 /*!< SCT EVCTRL6: IOSEL Position */\r
-#define SCT_EVCTRL6_IOSEL_Msk (0x0fUL << SCT_EVCTRL6_IOSEL_Pos) /*!< SCT EVCTRL6: IOSEL Mask */\r
-#define SCT_EVCTRL6_IOCOND_Pos 10 /*!< SCT EVCTRL6: IOCOND Position */\r
-#define SCT_EVCTRL6_IOCOND_Msk (0x03UL << SCT_EVCTRL6_IOCOND_Pos) /*!< SCT EVCTRL6: IOCOND Mask */\r
-#define SCT_EVCTRL6_COMBMODE_Pos 12 /*!< SCT EVCTRL6: COMBMODE Position */\r
-#define SCT_EVCTRL6_COMBMODE_Msk (0x03UL << SCT_EVCTRL6_COMBMODE_Pos) /*!< SCT EVCTRL6: COMBMODE Mask */\r
-#define SCT_EVCTRL6_STATELD_Pos 14 /*!< SCT EVCTRL6: STATELD Position */\r
-#define SCT_EVCTRL6_STATELD_Msk (0x01UL << SCT_EVCTRL6_STATELD_Pos) /*!< SCT EVCTRL6: STATELD Mask */\r
-#define SCT_EVCTRL6_STATEV_Pos 15 /*!< SCT EVCTRL6: STATEV Position */\r
-#define SCT_EVCTRL6_STATEV_Msk (0x1fUL << SCT_EVCTRL6_STATEV_Pos) /*!< SCT EVCTRL6: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK7 ----------------------------------------\r
-#define SCT_EVSTATEMSK7_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK7: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK7: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK7: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK7: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK7: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK7: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK7: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK7: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK7: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK7: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK7: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK7: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK7: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK7: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK7: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK7: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK7: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK7: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK7: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK7: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK7: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK7: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK7: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK7: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK7: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK7: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK7: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK7: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK7: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK7: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK7: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK7_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK7: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK7_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL7 ------------------------------------------\r
-#define SCT_EVCTRL7_MATCHSEL_Pos 0 /*!< SCT EVCTRL7: MATCHSEL Position */\r
-#define SCT_EVCTRL7_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos) /*!< SCT EVCTRL7: MATCHSEL Mask */\r
-#define SCT_EVCTRL7_HEVENT_Pos 4 /*!< SCT EVCTRL7: HEVENT Position */\r
-#define SCT_EVCTRL7_HEVENT_Msk (0x01UL << SCT_EVCTRL7_HEVENT_Pos) /*!< SCT EVCTRL7: HEVENT Mask */\r
-#define SCT_EVCTRL7_OUTSEL_Pos 5 /*!< SCT EVCTRL7: OUTSEL Position */\r
-#define SCT_EVCTRL7_OUTSEL_Msk (0x01UL << SCT_EVCTRL7_OUTSEL_Pos) /*!< SCT EVCTRL7: OUTSEL Mask */\r
-#define SCT_EVCTRL7_IOSEL_Pos 6 /*!< SCT EVCTRL7: IOSEL Position */\r
-#define SCT_EVCTRL7_IOSEL_Msk (0x0fUL << SCT_EVCTRL7_IOSEL_Pos) /*!< SCT EVCTRL7: IOSEL Mask */\r
-#define SCT_EVCTRL7_IOCOND_Pos 10 /*!< SCT EVCTRL7: IOCOND Position */\r
-#define SCT_EVCTRL7_IOCOND_Msk (0x03UL << SCT_EVCTRL7_IOCOND_Pos) /*!< SCT EVCTRL7: IOCOND Mask */\r
-#define SCT_EVCTRL7_COMBMODE_Pos 12 /*!< SCT EVCTRL7: COMBMODE Position */\r
-#define SCT_EVCTRL7_COMBMODE_Msk (0x03UL << SCT_EVCTRL7_COMBMODE_Pos) /*!< SCT EVCTRL7: COMBMODE Mask */\r
-#define SCT_EVCTRL7_STATELD_Pos 14 /*!< SCT EVCTRL7: STATELD Position */\r
-#define SCT_EVCTRL7_STATELD_Msk (0x01UL << SCT_EVCTRL7_STATELD_Pos) /*!< SCT EVCTRL7: STATELD Mask */\r
-#define SCT_EVCTRL7_STATEV_Pos 15 /*!< SCT EVCTRL7: STATEV Position */\r
-#define SCT_EVCTRL7_STATEV_Msk (0x1fUL << SCT_EVCTRL7_STATEV_Pos) /*!< SCT EVCTRL7: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK8 ----------------------------------------\r
-#define SCT_EVSTATEMSK8_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK8: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK8: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK8: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK8: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK8: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK8: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK8: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK8: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK8: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK8: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK8: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK8: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK8: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK8: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK8: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK8: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK8: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK8: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK8: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK8: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK8: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK8: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK8: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK8: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK8: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK8: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK8: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK8: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK8: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK8: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK8: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK8_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK8: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK8_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL8 ------------------------------------------\r
-#define SCT_EVCTRL8_MATCHSEL_Pos 0 /*!< SCT EVCTRL8: MATCHSEL Position */\r
-#define SCT_EVCTRL8_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos) /*!< SCT EVCTRL8: MATCHSEL Mask */\r
-#define SCT_EVCTRL8_HEVENT_Pos 4 /*!< SCT EVCTRL8: HEVENT Position */\r
-#define SCT_EVCTRL8_HEVENT_Msk (0x01UL << SCT_EVCTRL8_HEVENT_Pos) /*!< SCT EVCTRL8: HEVENT Mask */\r
-#define SCT_EVCTRL8_OUTSEL_Pos 5 /*!< SCT EVCTRL8: OUTSEL Position */\r
-#define SCT_EVCTRL8_OUTSEL_Msk (0x01UL << SCT_EVCTRL8_OUTSEL_Pos) /*!< SCT EVCTRL8: OUTSEL Mask */\r
-#define SCT_EVCTRL8_IOSEL_Pos 6 /*!< SCT EVCTRL8: IOSEL Position */\r
-#define SCT_EVCTRL8_IOSEL_Msk (0x0fUL << SCT_EVCTRL8_IOSEL_Pos) /*!< SCT EVCTRL8: IOSEL Mask */\r
-#define SCT_EVCTRL8_IOCOND_Pos 10 /*!< SCT EVCTRL8: IOCOND Position */\r
-#define SCT_EVCTRL8_IOCOND_Msk (0x03UL << SCT_EVCTRL8_IOCOND_Pos) /*!< SCT EVCTRL8: IOCOND Mask */\r
-#define SCT_EVCTRL8_COMBMODE_Pos 12 /*!< SCT EVCTRL8: COMBMODE Position */\r
-#define SCT_EVCTRL8_COMBMODE_Msk (0x03UL << SCT_EVCTRL8_COMBMODE_Pos) /*!< SCT EVCTRL8: COMBMODE Mask */\r
-#define SCT_EVCTRL8_STATELD_Pos 14 /*!< SCT EVCTRL8: STATELD Position */\r
-#define SCT_EVCTRL8_STATELD_Msk (0x01UL << SCT_EVCTRL8_STATELD_Pos) /*!< SCT EVCTRL8: STATELD Mask */\r
-#define SCT_EVCTRL8_STATEV_Pos 15 /*!< SCT EVCTRL8: STATEV Position */\r
-#define SCT_EVCTRL8_STATEV_Msk (0x1fUL << SCT_EVCTRL8_STATEV_Pos) /*!< SCT EVCTRL8: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_EVSTATEMSK9 ----------------------------------------\r
-#define SCT_EVSTATEMSK9_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK9: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK9: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK9: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK9: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK9: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK9: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK9: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK9: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK9: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK9: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK9: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK9: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK9: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK9: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK9: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK9: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK9: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK9: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK9: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK9: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK9: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK9: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK9: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK9: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK9: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK9: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK9: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK9: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK9: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK9: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK9: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK9_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK9: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK9_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn31 Mask */\r
-\r
-// --------------------------------------- SCT_EVCTRL9 ------------------------------------------\r
-#define SCT_EVCTRL9_MATCHSEL_Pos 0 /*!< SCT EVCTRL9: MATCHSEL Position */\r
-#define SCT_EVCTRL9_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos) /*!< SCT EVCTRL9: MATCHSEL Mask */\r
-#define SCT_EVCTRL9_HEVENT_Pos 4 /*!< SCT EVCTRL9: HEVENT Position */\r
-#define SCT_EVCTRL9_HEVENT_Msk (0x01UL << SCT_EVCTRL9_HEVENT_Pos) /*!< SCT EVCTRL9: HEVENT Mask */\r
-#define SCT_EVCTRL9_OUTSEL_Pos 5 /*!< SCT EVCTRL9: OUTSEL Position */\r
-#define SCT_EVCTRL9_OUTSEL_Msk (0x01UL << SCT_EVCTRL9_OUTSEL_Pos) /*!< SCT EVCTRL9: OUTSEL Mask */\r
-#define SCT_EVCTRL9_IOSEL_Pos 6 /*!< SCT EVCTRL9: IOSEL Position */\r
-#define SCT_EVCTRL9_IOSEL_Msk (0x0fUL << SCT_EVCTRL9_IOSEL_Pos) /*!< SCT EVCTRL9: IOSEL Mask */\r
-#define SCT_EVCTRL9_IOCOND_Pos 10 /*!< SCT EVCTRL9: IOCOND Position */\r
-#define SCT_EVCTRL9_IOCOND_Msk (0x03UL << SCT_EVCTRL9_IOCOND_Pos) /*!< SCT EVCTRL9: IOCOND Mask */\r
-#define SCT_EVCTRL9_COMBMODE_Pos 12 /*!< SCT EVCTRL9: COMBMODE Position */\r
-#define SCT_EVCTRL9_COMBMODE_Msk (0x03UL << SCT_EVCTRL9_COMBMODE_Pos) /*!< SCT EVCTRL9: COMBMODE Mask */\r
-#define SCT_EVCTRL9_STATELD_Pos 14 /*!< SCT EVCTRL9: STATELD Position */\r
-#define SCT_EVCTRL9_STATELD_Msk (0x01UL << SCT_EVCTRL9_STATELD_Pos) /*!< SCT EVCTRL9: STATELD Mask */\r
-#define SCT_EVCTRL9_STATEV_Pos 15 /*!< SCT EVCTRL9: STATEV Position */\r
-#define SCT_EVCTRL9_STATEV_Msk (0x1fUL << SCT_EVCTRL9_STATEV_Pos) /*!< SCT EVCTRL9: STATEV Mask */\r
-\r
-// ------------------------------------ SCT_EVSTATEMSK10 ----------------------------------------\r
-#define SCT_EVSTATEMSK10_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK10: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK10: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK10: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK10: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK10: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK10: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK10: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK10: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK10: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK10: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK10: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK10: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK10: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK10: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK10: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK10: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK10: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK10: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK10: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK10: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK10: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK10: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK10: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK10: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK10: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK10: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK10: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK10: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK10: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK10: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK10: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK10_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK10: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK10_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn31 Mask */\r
-\r
-// -------------------------------------- SCT_EVCTRL10 ------------------------------------------\r
-#define SCT_EVCTRL10_MATCHSEL_Pos 0 /*!< SCT EVCTRL10: MATCHSEL Position */\r
-#define SCT_EVCTRL10_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos) /*!< SCT EVCTRL10: MATCHSEL Mask */\r
-#define SCT_EVCTRL10_HEVENT_Pos 4 /*!< SCT EVCTRL10: HEVENT Position */\r
-#define SCT_EVCTRL10_HEVENT_Msk (0x01UL << SCT_EVCTRL10_HEVENT_Pos) /*!< SCT EVCTRL10: HEVENT Mask */\r
-#define SCT_EVCTRL10_OUTSEL_Pos 5 /*!< SCT EVCTRL10: OUTSEL Position */\r
-#define SCT_EVCTRL10_OUTSEL_Msk (0x01UL << SCT_EVCTRL10_OUTSEL_Pos) /*!< SCT EVCTRL10: OUTSEL Mask */\r
-#define SCT_EVCTRL10_IOSEL_Pos 6 /*!< SCT EVCTRL10: IOSEL Position */\r
-#define SCT_EVCTRL10_IOSEL_Msk (0x0fUL << SCT_EVCTRL10_IOSEL_Pos) /*!< SCT EVCTRL10: IOSEL Mask */\r
-#define SCT_EVCTRL10_IOCOND_Pos 10 /*!< SCT EVCTRL10: IOCOND Position */\r
-#define SCT_EVCTRL10_IOCOND_Msk (0x03UL << SCT_EVCTRL10_IOCOND_Pos) /*!< SCT EVCTRL10: IOCOND Mask */\r
-#define SCT_EVCTRL10_COMBMODE_Pos 12 /*!< SCT EVCTRL10: COMBMODE Position */\r
-#define SCT_EVCTRL10_COMBMODE_Msk (0x03UL << SCT_EVCTRL10_COMBMODE_Pos) /*!< SCT EVCTRL10: COMBMODE Mask */\r
-#define SCT_EVCTRL10_STATELD_Pos 14 /*!< SCT EVCTRL10: STATELD Position */\r
-#define SCT_EVCTRL10_STATELD_Msk (0x01UL << SCT_EVCTRL10_STATELD_Pos) /*!< SCT EVCTRL10: STATELD Mask */\r
-#define SCT_EVCTRL10_STATEV_Pos 15 /*!< SCT EVCTRL10: STATEV Position */\r
-#define SCT_EVCTRL10_STATEV_Msk (0x1fUL << SCT_EVCTRL10_STATEV_Pos) /*!< SCT EVCTRL10: STATEV Mask */\r
-\r
-// ------------------------------------ SCT_EVSTATEMSK11 ----------------------------------------\r
-#define SCT_EVSTATEMSK11_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK11: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK11: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK11: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK11: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK11: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK11: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK11: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK11: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK11: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK11: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK11: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK11: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK11: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK11: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK11: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK11: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK11: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK11: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK11: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK11: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK11: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK11: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK11: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK11: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK11: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK11: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK11: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK11: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK11: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK11: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK11: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK11_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK11: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK11_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn31 Mask */\r
-\r
-// -------------------------------------- SCT_EVCTRL11 ------------------------------------------\r
-#define SCT_EVCTRL11_MATCHSEL_Pos 0 /*!< SCT EVCTRL11: MATCHSEL Position */\r
-#define SCT_EVCTRL11_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos) /*!< SCT EVCTRL11: MATCHSEL Mask */\r
-#define SCT_EVCTRL11_HEVENT_Pos 4 /*!< SCT EVCTRL11: HEVENT Position */\r
-#define SCT_EVCTRL11_HEVENT_Msk (0x01UL << SCT_EVCTRL11_HEVENT_Pos) /*!< SCT EVCTRL11: HEVENT Mask */\r
-#define SCT_EVCTRL11_OUTSEL_Pos 5 /*!< SCT EVCTRL11: OUTSEL Position */\r
-#define SCT_EVCTRL11_OUTSEL_Msk (0x01UL << SCT_EVCTRL11_OUTSEL_Pos) /*!< SCT EVCTRL11: OUTSEL Mask */\r
-#define SCT_EVCTRL11_IOSEL_Pos 6 /*!< SCT EVCTRL11: IOSEL Position */\r
-#define SCT_EVCTRL11_IOSEL_Msk (0x0fUL << SCT_EVCTRL11_IOSEL_Pos) /*!< SCT EVCTRL11: IOSEL Mask */\r
-#define SCT_EVCTRL11_IOCOND_Pos 10 /*!< SCT EVCTRL11: IOCOND Position */\r
-#define SCT_EVCTRL11_IOCOND_Msk (0x03UL << SCT_EVCTRL11_IOCOND_Pos) /*!< SCT EVCTRL11: IOCOND Mask */\r
-#define SCT_EVCTRL11_COMBMODE_Pos 12 /*!< SCT EVCTRL11: COMBMODE Position */\r
-#define SCT_EVCTRL11_COMBMODE_Msk (0x03UL << SCT_EVCTRL11_COMBMODE_Pos) /*!< SCT EVCTRL11: COMBMODE Mask */\r
-#define SCT_EVCTRL11_STATELD_Pos 14 /*!< SCT EVCTRL11: STATELD Position */\r
-#define SCT_EVCTRL11_STATELD_Msk (0x01UL << SCT_EVCTRL11_STATELD_Pos) /*!< SCT EVCTRL11: STATELD Mask */\r
-#define SCT_EVCTRL11_STATEV_Pos 15 /*!< SCT EVCTRL11: STATEV Position */\r
-#define SCT_EVCTRL11_STATEV_Msk (0x1fUL << SCT_EVCTRL11_STATEV_Pos) /*!< SCT EVCTRL11: STATEV Mask */\r
-\r
-// ------------------------------------ SCT_EVSTATEMSK12 ----------------------------------------\r
-#define SCT_EVSTATEMSK12_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK12: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK12: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK12: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK12: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK12: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK12: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK12: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK12: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK12: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK12: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK12: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK12: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK12: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK12: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK12: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK12: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK12: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK12: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK12: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK12: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK12: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK12: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK12: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK12: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK12: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK12: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK12: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK12: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK12: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK12: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK12: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK12_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK12: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK12_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn31 Mask */\r
-\r
-// -------------------------------------- SCT_EVCTRL12 ------------------------------------------\r
-#define SCT_EVCTRL12_MATCHSEL_Pos 0 /*!< SCT EVCTRL12: MATCHSEL Position */\r
-#define SCT_EVCTRL12_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos) /*!< SCT EVCTRL12: MATCHSEL Mask */\r
-#define SCT_EVCTRL12_HEVENT_Pos 4 /*!< SCT EVCTRL12: HEVENT Position */\r
-#define SCT_EVCTRL12_HEVENT_Msk (0x01UL << SCT_EVCTRL12_HEVENT_Pos) /*!< SCT EVCTRL12: HEVENT Mask */\r
-#define SCT_EVCTRL12_OUTSEL_Pos 5 /*!< SCT EVCTRL12: OUTSEL Position */\r
-#define SCT_EVCTRL12_OUTSEL_Msk (0x01UL << SCT_EVCTRL12_OUTSEL_Pos) /*!< SCT EVCTRL12: OUTSEL Mask */\r
-#define SCT_EVCTRL12_IOSEL_Pos 6 /*!< SCT EVCTRL12: IOSEL Position */\r
-#define SCT_EVCTRL12_IOSEL_Msk (0x0fUL << SCT_EVCTRL12_IOSEL_Pos) /*!< SCT EVCTRL12: IOSEL Mask */\r
-#define SCT_EVCTRL12_IOCOND_Pos 10 /*!< SCT EVCTRL12: IOCOND Position */\r
-#define SCT_EVCTRL12_IOCOND_Msk (0x03UL << SCT_EVCTRL12_IOCOND_Pos) /*!< SCT EVCTRL12: IOCOND Mask */\r
-#define SCT_EVCTRL12_COMBMODE_Pos 12 /*!< SCT EVCTRL12: COMBMODE Position */\r
-#define SCT_EVCTRL12_COMBMODE_Msk (0x03UL << SCT_EVCTRL12_COMBMODE_Pos) /*!< SCT EVCTRL12: COMBMODE Mask */\r
-#define SCT_EVCTRL12_STATELD_Pos 14 /*!< SCT EVCTRL12: STATELD Position */\r
-#define SCT_EVCTRL12_STATELD_Msk (0x01UL << SCT_EVCTRL12_STATELD_Pos) /*!< SCT EVCTRL12: STATELD Mask */\r
-#define SCT_EVCTRL12_STATEV_Pos 15 /*!< SCT EVCTRL12: STATEV Position */\r
-#define SCT_EVCTRL12_STATEV_Msk (0x1fUL << SCT_EVCTRL12_STATEV_Pos) /*!< SCT EVCTRL12: STATEV Mask */\r
-\r
-// ------------------------------------ SCT_EVSTATEMSK13 ----------------------------------------\r
-#define SCT_EVSTATEMSK13_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK13: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK13: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK13: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK13: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK13: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK13: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK13: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK13: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK13: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK13: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK13: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK13: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK13: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK13: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK13: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK13: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK13: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK13: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK13: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK13: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK13: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK13: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK13: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK13: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK13: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK13: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK13: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK13: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK13: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK13: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK13: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK13_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK13: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK13_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn31 Mask */\r
-\r
-// -------------------------------------- SCT_EVCTRL13 ------------------------------------------\r
-#define SCT_EVCTRL13_MATCHSEL_Pos 0 /*!< SCT EVCTRL13: MATCHSEL Position */\r
-#define SCT_EVCTRL13_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos) /*!< SCT EVCTRL13: MATCHSEL Mask */\r
-#define SCT_EVCTRL13_HEVENT_Pos 4 /*!< SCT EVCTRL13: HEVENT Position */\r
-#define SCT_EVCTRL13_HEVENT_Msk (0x01UL << SCT_EVCTRL13_HEVENT_Pos) /*!< SCT EVCTRL13: HEVENT Mask */\r
-#define SCT_EVCTRL13_OUTSEL_Pos 5 /*!< SCT EVCTRL13: OUTSEL Position */\r
-#define SCT_EVCTRL13_OUTSEL_Msk (0x01UL << SCT_EVCTRL13_OUTSEL_Pos) /*!< SCT EVCTRL13: OUTSEL Mask */\r
-#define SCT_EVCTRL13_IOSEL_Pos 6 /*!< SCT EVCTRL13: IOSEL Position */\r
-#define SCT_EVCTRL13_IOSEL_Msk (0x0fUL << SCT_EVCTRL13_IOSEL_Pos) /*!< SCT EVCTRL13: IOSEL Mask */\r
-#define SCT_EVCTRL13_IOCOND_Pos 10 /*!< SCT EVCTRL13: IOCOND Position */\r
-#define SCT_EVCTRL13_IOCOND_Msk (0x03UL << SCT_EVCTRL13_IOCOND_Pos) /*!< SCT EVCTRL13: IOCOND Mask */\r
-#define SCT_EVCTRL13_COMBMODE_Pos 12 /*!< SCT EVCTRL13: COMBMODE Position */\r
-#define SCT_EVCTRL13_COMBMODE_Msk (0x03UL << SCT_EVCTRL13_COMBMODE_Pos) /*!< SCT EVCTRL13: COMBMODE Mask */\r
-#define SCT_EVCTRL13_STATELD_Pos 14 /*!< SCT EVCTRL13: STATELD Position */\r
-#define SCT_EVCTRL13_STATELD_Msk (0x01UL << SCT_EVCTRL13_STATELD_Pos) /*!< SCT EVCTRL13: STATELD Mask */\r
-#define SCT_EVCTRL13_STATEV_Pos 15 /*!< SCT EVCTRL13: STATEV Position */\r
-#define SCT_EVCTRL13_STATEV_Msk (0x1fUL << SCT_EVCTRL13_STATEV_Pos) /*!< SCT EVCTRL13: STATEV Mask */\r
-\r
-// ------------------------------------ SCT_EVSTATEMSK14 ----------------------------------------\r
-#define SCT_EVSTATEMSK14_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK14: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK14: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK14: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK14: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK14: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK14: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK14: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK14: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK14: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK14: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK14: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK14: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK14: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK14: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK14: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK14: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK14: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK14: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK14: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK14: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK14: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK14: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK14: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK14: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK14: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK14: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK14: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK14: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK14: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK14: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK14: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK14_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK14: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK14_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn31 Mask */\r
-\r
-// -------------------------------------- SCT_EVCTRL14 ------------------------------------------\r
-#define SCT_EVCTRL14_MATCHSEL_Pos 0 /*!< SCT EVCTRL14: MATCHSEL Position */\r
-#define SCT_EVCTRL14_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos) /*!< SCT EVCTRL14: MATCHSEL Mask */\r
-#define SCT_EVCTRL14_HEVENT_Pos 4 /*!< SCT EVCTRL14: HEVENT Position */\r
-#define SCT_EVCTRL14_HEVENT_Msk (0x01UL << SCT_EVCTRL14_HEVENT_Pos) /*!< SCT EVCTRL14: HEVENT Mask */\r
-#define SCT_EVCTRL14_OUTSEL_Pos 5 /*!< SCT EVCTRL14: OUTSEL Position */\r
-#define SCT_EVCTRL14_OUTSEL_Msk (0x01UL << SCT_EVCTRL14_OUTSEL_Pos) /*!< SCT EVCTRL14: OUTSEL Mask */\r
-#define SCT_EVCTRL14_IOSEL_Pos 6 /*!< SCT EVCTRL14: IOSEL Position */\r
-#define SCT_EVCTRL14_IOSEL_Msk (0x0fUL << SCT_EVCTRL14_IOSEL_Pos) /*!< SCT EVCTRL14: IOSEL Mask */\r
-#define SCT_EVCTRL14_IOCOND_Pos 10 /*!< SCT EVCTRL14: IOCOND Position */\r
-#define SCT_EVCTRL14_IOCOND_Msk (0x03UL << SCT_EVCTRL14_IOCOND_Pos) /*!< SCT EVCTRL14: IOCOND Mask */\r
-#define SCT_EVCTRL14_COMBMODE_Pos 12 /*!< SCT EVCTRL14: COMBMODE Position */\r
-#define SCT_EVCTRL14_COMBMODE_Msk (0x03UL << SCT_EVCTRL14_COMBMODE_Pos) /*!< SCT EVCTRL14: COMBMODE Mask */\r
-#define SCT_EVCTRL14_STATELD_Pos 14 /*!< SCT EVCTRL14: STATELD Position */\r
-#define SCT_EVCTRL14_STATELD_Msk (0x01UL << SCT_EVCTRL14_STATELD_Pos) /*!< SCT EVCTRL14: STATELD Mask */\r
-#define SCT_EVCTRL14_STATEV_Pos 15 /*!< SCT EVCTRL14: STATEV Position */\r
-#define SCT_EVCTRL14_STATEV_Msk (0x1fUL << SCT_EVCTRL14_STATEV_Pos) /*!< SCT EVCTRL14: STATEV Mask */\r
-\r
-// ------------------------------------ SCT_EVSTATEMSK15 ----------------------------------------\r
-#define SCT_EVSTATEMSK15_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK15: STATEMSKn0 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn0 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK15: STATEMSKn1 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn1 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK15: STATEMSKn2 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn2 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK15: STATEMSKn3 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn3 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK15: STATEMSKn4 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn4 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK15: STATEMSKn5 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn5 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK15: STATEMSKn6 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn6 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK15: STATEMSKn7 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn7 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK15: STATEMSKn8 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn8 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK15: STATEMSKn9 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn9 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK15: STATEMSKn10 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn10 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK15: STATEMSKn11 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn11 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK15: STATEMSKn12 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn12 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK15: STATEMSKn13 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn13 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK15: STATEMSKn14 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn14 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK15: STATEMSKn15 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn15 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK15: STATEMSKn16 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn16 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK15: STATEMSKn17 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn17 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK15: STATEMSKn18 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn18 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK15: STATEMSKn19 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn19 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK15: STATEMSKn20 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn20 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK15: STATEMSKn21 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn21 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK15: STATEMSKn22 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn22 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK15: STATEMSKn23 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn23 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK15: STATEMSKn24 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn24 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK15: STATEMSKn25 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn25 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK15: STATEMSKn26 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn26 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK15: STATEMSKn27 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn27 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK15: STATEMSKn28 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn28 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK15: STATEMSKn29 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn29 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK15: STATEMSKn30 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn30 Mask */\r
-#define SCT_EVSTATEMSK15_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK15: STATEMSKn31 Position */\r
-#define SCT_EVSTATEMSK15_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn31 Mask */\r
-\r
-// -------------------------------------- SCT_EVCTRL15 ------------------------------------------\r
-#define SCT_EVCTRL15_MATCHSEL_Pos 0 /*!< SCT EVCTRL15: MATCHSEL Position */\r
-#define SCT_EVCTRL15_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos) /*!< SCT EVCTRL15: MATCHSEL Mask */\r
-#define SCT_EVCTRL15_HEVENT_Pos 4 /*!< SCT EVCTRL15: HEVENT Position */\r
-#define SCT_EVCTRL15_HEVENT_Msk (0x01UL << SCT_EVCTRL15_HEVENT_Pos) /*!< SCT EVCTRL15: HEVENT Mask */\r
-#define SCT_EVCTRL15_OUTSEL_Pos 5 /*!< SCT EVCTRL15: OUTSEL Position */\r
-#define SCT_EVCTRL15_OUTSEL_Msk (0x01UL << SCT_EVCTRL15_OUTSEL_Pos) /*!< SCT EVCTRL15: OUTSEL Mask */\r
-#define SCT_EVCTRL15_IOSEL_Pos 6 /*!< SCT EVCTRL15: IOSEL Position */\r
-#define SCT_EVCTRL15_IOSEL_Msk (0x0fUL << SCT_EVCTRL15_IOSEL_Pos) /*!< SCT EVCTRL15: IOSEL Mask */\r
-#define SCT_EVCTRL15_IOCOND_Pos 10 /*!< SCT EVCTRL15: IOCOND Position */\r
-#define SCT_EVCTRL15_IOCOND_Msk (0x03UL << SCT_EVCTRL15_IOCOND_Pos) /*!< SCT EVCTRL15: IOCOND Mask */\r
-#define SCT_EVCTRL15_COMBMODE_Pos 12 /*!< SCT EVCTRL15: COMBMODE Position */\r
-#define SCT_EVCTRL15_COMBMODE_Msk (0x03UL << SCT_EVCTRL15_COMBMODE_Pos) /*!< SCT EVCTRL15: COMBMODE Mask */\r
-#define SCT_EVCTRL15_STATELD_Pos 14 /*!< SCT EVCTRL15: STATELD Position */\r
-#define SCT_EVCTRL15_STATELD_Msk (0x01UL << SCT_EVCTRL15_STATELD_Pos) /*!< SCT EVCTRL15: STATELD Mask */\r
-#define SCT_EVCTRL15_STATEV_Pos 15 /*!< SCT EVCTRL15: STATEV Position */\r
-#define SCT_EVCTRL15_STATEV_Msk (0x1fUL << SCT_EVCTRL15_STATEV_Pos) /*!< SCT EVCTRL15: STATEV Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET0 -----------------------------------------\r
-#define SCT_OUTPUTSET0_SETn0_Pos 0 /*!< SCT OUTPUTSET0: SETn0 Position */\r
-#define SCT_OUTPUTSET0_SETn0_Msk (0x01UL << SCT_OUTPUTSET0_SETn0_Pos) /*!< SCT OUTPUTSET0: SETn0 Mask */\r
-#define SCT_OUTPUTSET0_SETn1_Pos 1 /*!< SCT OUTPUTSET0: SETn1 Position */\r
-#define SCT_OUTPUTSET0_SETn1_Msk (0x01UL << SCT_OUTPUTSET0_SETn1_Pos) /*!< SCT OUTPUTSET0: SETn1 Mask */\r
-#define SCT_OUTPUTSET0_SETn2_Pos 2 /*!< SCT OUTPUTSET0: SETn2 Position */\r
-#define SCT_OUTPUTSET0_SETn2_Msk (0x01UL << SCT_OUTPUTSET0_SETn2_Pos) /*!< SCT OUTPUTSET0: SETn2 Mask */\r
-#define SCT_OUTPUTSET0_SETn3_Pos 3 /*!< SCT OUTPUTSET0: SETn3 Position */\r
-#define SCT_OUTPUTSET0_SETn3_Msk (0x01UL << SCT_OUTPUTSET0_SETn3_Pos) /*!< SCT OUTPUTSET0: SETn3 Mask */\r
-#define SCT_OUTPUTSET0_SETn4_Pos 4 /*!< SCT OUTPUTSET0: SETn4 Position */\r
-#define SCT_OUTPUTSET0_SETn4_Msk (0x01UL << SCT_OUTPUTSET0_SETn4_Pos) /*!< SCT OUTPUTSET0: SETn4 Mask */\r
-#define SCT_OUTPUTSET0_SETn5_Pos 5 /*!< SCT OUTPUTSET0: SETn5 Position */\r
-#define SCT_OUTPUTSET0_SETn5_Msk (0x01UL << SCT_OUTPUTSET0_SETn5_Pos) /*!< SCT OUTPUTSET0: SETn5 Mask */\r
-#define SCT_OUTPUTSET0_SETn6_Pos 6 /*!< SCT OUTPUTSET0: SETn6 Position */\r
-#define SCT_OUTPUTSET0_SETn6_Msk (0x01UL << SCT_OUTPUTSET0_SETn6_Pos) /*!< SCT OUTPUTSET0: SETn6 Mask */\r
-#define SCT_OUTPUTSET0_SETn7_Pos 7 /*!< SCT OUTPUTSET0: SETn7 Position */\r
-#define SCT_OUTPUTSET0_SETn7_Msk (0x01UL << SCT_OUTPUTSET0_SETn7_Pos) /*!< SCT OUTPUTSET0: SETn7 Mask */\r
-#define SCT_OUTPUTSET0_SETn8_Pos 8 /*!< SCT OUTPUTSET0: SETn8 Position */\r
-#define SCT_OUTPUTSET0_SETn8_Msk (0x01UL << SCT_OUTPUTSET0_SETn8_Pos) /*!< SCT OUTPUTSET0: SETn8 Mask */\r
-#define SCT_OUTPUTSET0_SETn9_Pos 9 /*!< SCT OUTPUTSET0: SETn9 Position */\r
-#define SCT_OUTPUTSET0_SETn9_Msk (0x01UL << SCT_OUTPUTSET0_SETn9_Pos) /*!< SCT OUTPUTSET0: SETn9 Mask */\r
-#define SCT_OUTPUTSET0_SETn10_Pos 10 /*!< SCT OUTPUTSET0: SETn10 Position */\r
-#define SCT_OUTPUTSET0_SETn10_Msk (0x01UL << SCT_OUTPUTSET0_SETn10_Pos) /*!< SCT OUTPUTSET0: SETn10 Mask */\r
-#define SCT_OUTPUTSET0_SETn11_Pos 11 /*!< SCT OUTPUTSET0: SETn11 Position */\r
-#define SCT_OUTPUTSET0_SETn11_Msk (0x01UL << SCT_OUTPUTSET0_SETn11_Pos) /*!< SCT OUTPUTSET0: SETn11 Mask */\r
-#define SCT_OUTPUTSET0_SETn12_Pos 12 /*!< SCT OUTPUTSET0: SETn12 Position */\r
-#define SCT_OUTPUTSET0_SETn12_Msk (0x01UL << SCT_OUTPUTSET0_SETn12_Pos) /*!< SCT OUTPUTSET0: SETn12 Mask */\r
-#define SCT_OUTPUTSET0_SETn13_Pos 13 /*!< SCT OUTPUTSET0: SETn13 Position */\r
-#define SCT_OUTPUTSET0_SETn13_Msk (0x01UL << SCT_OUTPUTSET0_SETn13_Pos) /*!< SCT OUTPUTSET0: SETn13 Mask */\r
-#define SCT_OUTPUTSET0_SETn14_Pos 14 /*!< SCT OUTPUTSET0: SETn14 Position */\r
-#define SCT_OUTPUTSET0_SETn14_Msk (0x01UL << SCT_OUTPUTSET0_SETn14_Pos) /*!< SCT OUTPUTSET0: SETn14 Mask */\r
-#define SCT_OUTPUTSET0_SETn15_Pos 15 /*!< SCT OUTPUTSET0: SETn15 Position */\r
-#define SCT_OUTPUTSET0_SETn15_Msk (0x01UL << SCT_OUTPUTSET0_SETn15_Pos) /*!< SCT OUTPUTSET0: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR0 -----------------------------------------\r
-#define SCT_OUTPUTCLR0_CLRn0_Pos 0 /*!< SCT OUTPUTCLR0: CLRn0 Position */\r
-#define SCT_OUTPUTCLR0_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos) /*!< SCT OUTPUTCLR0: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn1_Pos 1 /*!< SCT OUTPUTCLR0: CLRn1 Position */\r
-#define SCT_OUTPUTCLR0_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos) /*!< SCT OUTPUTCLR0: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn2_Pos 2 /*!< SCT OUTPUTCLR0: CLRn2 Position */\r
-#define SCT_OUTPUTCLR0_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos) /*!< SCT OUTPUTCLR0: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn3_Pos 3 /*!< SCT OUTPUTCLR0: CLRn3 Position */\r
-#define SCT_OUTPUTCLR0_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos) /*!< SCT OUTPUTCLR0: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn4_Pos 4 /*!< SCT OUTPUTCLR0: CLRn4 Position */\r
-#define SCT_OUTPUTCLR0_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos) /*!< SCT OUTPUTCLR0: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn5_Pos 5 /*!< SCT OUTPUTCLR0: CLRn5 Position */\r
-#define SCT_OUTPUTCLR0_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos) /*!< SCT OUTPUTCLR0: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn6_Pos 6 /*!< SCT OUTPUTCLR0: CLRn6 Position */\r
-#define SCT_OUTPUTCLR0_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos) /*!< SCT OUTPUTCLR0: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn7_Pos 7 /*!< SCT OUTPUTCLR0: CLRn7 Position */\r
-#define SCT_OUTPUTCLR0_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos) /*!< SCT OUTPUTCLR0: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn8_Pos 8 /*!< SCT OUTPUTCLR0: CLRn8 Position */\r
-#define SCT_OUTPUTCLR0_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos) /*!< SCT OUTPUTCLR0: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn9_Pos 9 /*!< SCT OUTPUTCLR0: CLRn9 Position */\r
-#define SCT_OUTPUTCLR0_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos) /*!< SCT OUTPUTCLR0: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn10_Pos 10 /*!< SCT OUTPUTCLR0: CLRn10 Position */\r
-#define SCT_OUTPUTCLR0_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos) /*!< SCT OUTPUTCLR0: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn11_Pos 11 /*!< SCT OUTPUTCLR0: CLRn11 Position */\r
-#define SCT_OUTPUTCLR0_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos) /*!< SCT OUTPUTCLR0: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn12_Pos 12 /*!< SCT OUTPUTCLR0: CLRn12 Position */\r
-#define SCT_OUTPUTCLR0_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos) /*!< SCT OUTPUTCLR0: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn13_Pos 13 /*!< SCT OUTPUTCLR0: CLRn13 Position */\r
-#define SCT_OUTPUTCLR0_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos) /*!< SCT OUTPUTCLR0: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn14_Pos 14 /*!< SCT OUTPUTCLR0: CLRn14 Position */\r
-#define SCT_OUTPUTCLR0_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos) /*!< SCT OUTPUTCLR0: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR0_CLRn15_Pos 15 /*!< SCT OUTPUTCLR0: CLRn15 Position */\r
-#define SCT_OUTPUTCLR0_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos) /*!< SCT OUTPUTCLR0: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET1 -----------------------------------------\r
-#define SCT_OUTPUTSET1_SETn0_Pos 0 /*!< SCT OUTPUTSET1: SETn0 Position */\r
-#define SCT_OUTPUTSET1_SETn0_Msk (0x01UL << SCT_OUTPUTSET1_SETn0_Pos) /*!< SCT OUTPUTSET1: SETn0 Mask */\r
-#define SCT_OUTPUTSET1_SETn1_Pos 1 /*!< SCT OUTPUTSET1: SETn1 Position */\r
-#define SCT_OUTPUTSET1_SETn1_Msk (0x01UL << SCT_OUTPUTSET1_SETn1_Pos) /*!< SCT OUTPUTSET1: SETn1 Mask */\r
-#define SCT_OUTPUTSET1_SETn2_Pos 2 /*!< SCT OUTPUTSET1: SETn2 Position */\r
-#define SCT_OUTPUTSET1_SETn2_Msk (0x01UL << SCT_OUTPUTSET1_SETn2_Pos) /*!< SCT OUTPUTSET1: SETn2 Mask */\r
-#define SCT_OUTPUTSET1_SETn3_Pos 3 /*!< SCT OUTPUTSET1: SETn3 Position */\r
-#define SCT_OUTPUTSET1_SETn3_Msk (0x01UL << SCT_OUTPUTSET1_SETn3_Pos) /*!< SCT OUTPUTSET1: SETn3 Mask */\r
-#define SCT_OUTPUTSET1_SETn4_Pos 4 /*!< SCT OUTPUTSET1: SETn4 Position */\r
-#define SCT_OUTPUTSET1_SETn4_Msk (0x01UL << SCT_OUTPUTSET1_SETn4_Pos) /*!< SCT OUTPUTSET1: SETn4 Mask */\r
-#define SCT_OUTPUTSET1_SETn5_Pos 5 /*!< SCT OUTPUTSET1: SETn5 Position */\r
-#define SCT_OUTPUTSET1_SETn5_Msk (0x01UL << SCT_OUTPUTSET1_SETn5_Pos) /*!< SCT OUTPUTSET1: SETn5 Mask */\r
-#define SCT_OUTPUTSET1_SETn6_Pos 6 /*!< SCT OUTPUTSET1: SETn6 Position */\r
-#define SCT_OUTPUTSET1_SETn6_Msk (0x01UL << SCT_OUTPUTSET1_SETn6_Pos) /*!< SCT OUTPUTSET1: SETn6 Mask */\r
-#define SCT_OUTPUTSET1_SETn7_Pos 7 /*!< SCT OUTPUTSET1: SETn7 Position */\r
-#define SCT_OUTPUTSET1_SETn7_Msk (0x01UL << SCT_OUTPUTSET1_SETn7_Pos) /*!< SCT OUTPUTSET1: SETn7 Mask */\r
-#define SCT_OUTPUTSET1_SETn8_Pos 8 /*!< SCT OUTPUTSET1: SETn8 Position */\r
-#define SCT_OUTPUTSET1_SETn8_Msk (0x01UL << SCT_OUTPUTSET1_SETn8_Pos) /*!< SCT OUTPUTSET1: SETn8 Mask */\r
-#define SCT_OUTPUTSET1_SETn9_Pos 9 /*!< SCT OUTPUTSET1: SETn9 Position */\r
-#define SCT_OUTPUTSET1_SETn9_Msk (0x01UL << SCT_OUTPUTSET1_SETn9_Pos) /*!< SCT OUTPUTSET1: SETn9 Mask */\r
-#define SCT_OUTPUTSET1_SETn10_Pos 10 /*!< SCT OUTPUTSET1: SETn10 Position */\r
-#define SCT_OUTPUTSET1_SETn10_Msk (0x01UL << SCT_OUTPUTSET1_SETn10_Pos) /*!< SCT OUTPUTSET1: SETn10 Mask */\r
-#define SCT_OUTPUTSET1_SETn11_Pos 11 /*!< SCT OUTPUTSET1: SETn11 Position */\r
-#define SCT_OUTPUTSET1_SETn11_Msk (0x01UL << SCT_OUTPUTSET1_SETn11_Pos) /*!< SCT OUTPUTSET1: SETn11 Mask */\r
-#define SCT_OUTPUTSET1_SETn12_Pos 12 /*!< SCT OUTPUTSET1: SETn12 Position */\r
-#define SCT_OUTPUTSET1_SETn12_Msk (0x01UL << SCT_OUTPUTSET1_SETn12_Pos) /*!< SCT OUTPUTSET1: SETn12 Mask */\r
-#define SCT_OUTPUTSET1_SETn13_Pos 13 /*!< SCT OUTPUTSET1: SETn13 Position */\r
-#define SCT_OUTPUTSET1_SETn13_Msk (0x01UL << SCT_OUTPUTSET1_SETn13_Pos) /*!< SCT OUTPUTSET1: SETn13 Mask */\r
-#define SCT_OUTPUTSET1_SETn14_Pos 14 /*!< SCT OUTPUTSET1: SETn14 Position */\r
-#define SCT_OUTPUTSET1_SETn14_Msk (0x01UL << SCT_OUTPUTSET1_SETn14_Pos) /*!< SCT OUTPUTSET1: SETn14 Mask */\r
-#define SCT_OUTPUTSET1_SETn15_Pos 15 /*!< SCT OUTPUTSET1: SETn15 Position */\r
-#define SCT_OUTPUTSET1_SETn15_Msk (0x01UL << SCT_OUTPUTSET1_SETn15_Pos) /*!< SCT OUTPUTSET1: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR1 -----------------------------------------\r
-#define SCT_OUTPUTCLR1_CLRn0_Pos 0 /*!< SCT OUTPUTCLR1: CLRn0 Position */\r
-#define SCT_OUTPUTCLR1_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos) /*!< SCT OUTPUTCLR1: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn1_Pos 1 /*!< SCT OUTPUTCLR1: CLRn1 Position */\r
-#define SCT_OUTPUTCLR1_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos) /*!< SCT OUTPUTCLR1: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn2_Pos 2 /*!< SCT OUTPUTCLR1: CLRn2 Position */\r
-#define SCT_OUTPUTCLR1_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos) /*!< SCT OUTPUTCLR1: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn3_Pos 3 /*!< SCT OUTPUTCLR1: CLRn3 Position */\r
-#define SCT_OUTPUTCLR1_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos) /*!< SCT OUTPUTCLR1: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn4_Pos 4 /*!< SCT OUTPUTCLR1: CLRn4 Position */\r
-#define SCT_OUTPUTCLR1_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos) /*!< SCT OUTPUTCLR1: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn5_Pos 5 /*!< SCT OUTPUTCLR1: CLRn5 Position */\r
-#define SCT_OUTPUTCLR1_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos) /*!< SCT OUTPUTCLR1: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn6_Pos 6 /*!< SCT OUTPUTCLR1: CLRn6 Position */\r
-#define SCT_OUTPUTCLR1_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos) /*!< SCT OUTPUTCLR1: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn7_Pos 7 /*!< SCT OUTPUTCLR1: CLRn7 Position */\r
-#define SCT_OUTPUTCLR1_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos) /*!< SCT OUTPUTCLR1: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn8_Pos 8 /*!< SCT OUTPUTCLR1: CLRn8 Position */\r
-#define SCT_OUTPUTCLR1_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos) /*!< SCT OUTPUTCLR1: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn9_Pos 9 /*!< SCT OUTPUTCLR1: CLRn9 Position */\r
-#define SCT_OUTPUTCLR1_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos) /*!< SCT OUTPUTCLR1: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn10_Pos 10 /*!< SCT OUTPUTCLR1: CLRn10 Position */\r
-#define SCT_OUTPUTCLR1_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos) /*!< SCT OUTPUTCLR1: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn11_Pos 11 /*!< SCT OUTPUTCLR1: CLRn11 Position */\r
-#define SCT_OUTPUTCLR1_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos) /*!< SCT OUTPUTCLR1: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn12_Pos 12 /*!< SCT OUTPUTCLR1: CLRn12 Position */\r
-#define SCT_OUTPUTCLR1_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos) /*!< SCT OUTPUTCLR1: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn13_Pos 13 /*!< SCT OUTPUTCLR1: CLRn13 Position */\r
-#define SCT_OUTPUTCLR1_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos) /*!< SCT OUTPUTCLR1: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn14_Pos 14 /*!< SCT OUTPUTCLR1: CLRn14 Position */\r
-#define SCT_OUTPUTCLR1_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos) /*!< SCT OUTPUTCLR1: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR1_CLRn15_Pos 15 /*!< SCT OUTPUTCLR1: CLRn15 Position */\r
-#define SCT_OUTPUTCLR1_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos) /*!< SCT OUTPUTCLR1: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET2 -----------------------------------------\r
-#define SCT_OUTPUTSET2_SETn0_Pos 0 /*!< SCT OUTPUTSET2: SETn0 Position */\r
-#define SCT_OUTPUTSET2_SETn0_Msk (0x01UL << SCT_OUTPUTSET2_SETn0_Pos) /*!< SCT OUTPUTSET2: SETn0 Mask */\r
-#define SCT_OUTPUTSET2_SETn1_Pos 1 /*!< SCT OUTPUTSET2: SETn1 Position */\r
-#define SCT_OUTPUTSET2_SETn1_Msk (0x01UL << SCT_OUTPUTSET2_SETn1_Pos) /*!< SCT OUTPUTSET2: SETn1 Mask */\r
-#define SCT_OUTPUTSET2_SETn2_Pos 2 /*!< SCT OUTPUTSET2: SETn2 Position */\r
-#define SCT_OUTPUTSET2_SETn2_Msk (0x01UL << SCT_OUTPUTSET2_SETn2_Pos) /*!< SCT OUTPUTSET2: SETn2 Mask */\r
-#define SCT_OUTPUTSET2_SETn3_Pos 3 /*!< SCT OUTPUTSET2: SETn3 Position */\r
-#define SCT_OUTPUTSET2_SETn3_Msk (0x01UL << SCT_OUTPUTSET2_SETn3_Pos) /*!< SCT OUTPUTSET2: SETn3 Mask */\r
-#define SCT_OUTPUTSET2_SETn4_Pos 4 /*!< SCT OUTPUTSET2: SETn4 Position */\r
-#define SCT_OUTPUTSET2_SETn4_Msk (0x01UL << SCT_OUTPUTSET2_SETn4_Pos) /*!< SCT OUTPUTSET2: SETn4 Mask */\r
-#define SCT_OUTPUTSET2_SETn5_Pos 5 /*!< SCT OUTPUTSET2: SETn5 Position */\r
-#define SCT_OUTPUTSET2_SETn5_Msk (0x01UL << SCT_OUTPUTSET2_SETn5_Pos) /*!< SCT OUTPUTSET2: SETn5 Mask */\r
-#define SCT_OUTPUTSET2_SETn6_Pos 6 /*!< SCT OUTPUTSET2: SETn6 Position */\r
-#define SCT_OUTPUTSET2_SETn6_Msk (0x01UL << SCT_OUTPUTSET2_SETn6_Pos) /*!< SCT OUTPUTSET2: SETn6 Mask */\r
-#define SCT_OUTPUTSET2_SETn7_Pos 7 /*!< SCT OUTPUTSET2: SETn7 Position */\r
-#define SCT_OUTPUTSET2_SETn7_Msk (0x01UL << SCT_OUTPUTSET2_SETn7_Pos) /*!< SCT OUTPUTSET2: SETn7 Mask */\r
-#define SCT_OUTPUTSET2_SETn8_Pos 8 /*!< SCT OUTPUTSET2: SETn8 Position */\r
-#define SCT_OUTPUTSET2_SETn8_Msk (0x01UL << SCT_OUTPUTSET2_SETn8_Pos) /*!< SCT OUTPUTSET2: SETn8 Mask */\r
-#define SCT_OUTPUTSET2_SETn9_Pos 9 /*!< SCT OUTPUTSET2: SETn9 Position */\r
-#define SCT_OUTPUTSET2_SETn9_Msk (0x01UL << SCT_OUTPUTSET2_SETn9_Pos) /*!< SCT OUTPUTSET2: SETn9 Mask */\r
-#define SCT_OUTPUTSET2_SETn10_Pos 10 /*!< SCT OUTPUTSET2: SETn10 Position */\r
-#define SCT_OUTPUTSET2_SETn10_Msk (0x01UL << SCT_OUTPUTSET2_SETn10_Pos) /*!< SCT OUTPUTSET2: SETn10 Mask */\r
-#define SCT_OUTPUTSET2_SETn11_Pos 11 /*!< SCT OUTPUTSET2: SETn11 Position */\r
-#define SCT_OUTPUTSET2_SETn11_Msk (0x01UL << SCT_OUTPUTSET2_SETn11_Pos) /*!< SCT OUTPUTSET2: SETn11 Mask */\r
-#define SCT_OUTPUTSET2_SETn12_Pos 12 /*!< SCT OUTPUTSET2: SETn12 Position */\r
-#define SCT_OUTPUTSET2_SETn12_Msk (0x01UL << SCT_OUTPUTSET2_SETn12_Pos) /*!< SCT OUTPUTSET2: SETn12 Mask */\r
-#define SCT_OUTPUTSET2_SETn13_Pos 13 /*!< SCT OUTPUTSET2: SETn13 Position */\r
-#define SCT_OUTPUTSET2_SETn13_Msk (0x01UL << SCT_OUTPUTSET2_SETn13_Pos) /*!< SCT OUTPUTSET2: SETn13 Mask */\r
-#define SCT_OUTPUTSET2_SETn14_Pos 14 /*!< SCT OUTPUTSET2: SETn14 Position */\r
-#define SCT_OUTPUTSET2_SETn14_Msk (0x01UL << SCT_OUTPUTSET2_SETn14_Pos) /*!< SCT OUTPUTSET2: SETn14 Mask */\r
-#define SCT_OUTPUTSET2_SETn15_Pos 15 /*!< SCT OUTPUTSET2: SETn15 Position */\r
-#define SCT_OUTPUTSET2_SETn15_Msk (0x01UL << SCT_OUTPUTSET2_SETn15_Pos) /*!< SCT OUTPUTSET2: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR2 -----------------------------------------\r
-#define SCT_OUTPUTCLR2_CLRn0_Pos 0 /*!< SCT OUTPUTCLR2: CLRn0 Position */\r
-#define SCT_OUTPUTCLR2_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos) /*!< SCT OUTPUTCLR2: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn1_Pos 1 /*!< SCT OUTPUTCLR2: CLRn1 Position */\r
-#define SCT_OUTPUTCLR2_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos) /*!< SCT OUTPUTCLR2: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn2_Pos 2 /*!< SCT OUTPUTCLR2: CLRn2 Position */\r
-#define SCT_OUTPUTCLR2_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos) /*!< SCT OUTPUTCLR2: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn3_Pos 3 /*!< SCT OUTPUTCLR2: CLRn3 Position */\r
-#define SCT_OUTPUTCLR2_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos) /*!< SCT OUTPUTCLR2: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn4_Pos 4 /*!< SCT OUTPUTCLR2: CLRn4 Position */\r
-#define SCT_OUTPUTCLR2_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos) /*!< SCT OUTPUTCLR2: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn5_Pos 5 /*!< SCT OUTPUTCLR2: CLRn5 Position */\r
-#define SCT_OUTPUTCLR2_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos) /*!< SCT OUTPUTCLR2: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn6_Pos 6 /*!< SCT OUTPUTCLR2: CLRn6 Position */\r
-#define SCT_OUTPUTCLR2_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos) /*!< SCT OUTPUTCLR2: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn7_Pos 7 /*!< SCT OUTPUTCLR2: CLRn7 Position */\r
-#define SCT_OUTPUTCLR2_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos) /*!< SCT OUTPUTCLR2: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn8_Pos 8 /*!< SCT OUTPUTCLR2: CLRn8 Position */\r
-#define SCT_OUTPUTCLR2_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos) /*!< SCT OUTPUTCLR2: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn9_Pos 9 /*!< SCT OUTPUTCLR2: CLRn9 Position */\r
-#define SCT_OUTPUTCLR2_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos) /*!< SCT OUTPUTCLR2: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn10_Pos 10 /*!< SCT OUTPUTCLR2: CLRn10 Position */\r
-#define SCT_OUTPUTCLR2_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos) /*!< SCT OUTPUTCLR2: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn11_Pos 11 /*!< SCT OUTPUTCLR2: CLRn11 Position */\r
-#define SCT_OUTPUTCLR2_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos) /*!< SCT OUTPUTCLR2: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn12_Pos 12 /*!< SCT OUTPUTCLR2: CLRn12 Position */\r
-#define SCT_OUTPUTCLR2_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos) /*!< SCT OUTPUTCLR2: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn13_Pos 13 /*!< SCT OUTPUTCLR2: CLRn13 Position */\r
-#define SCT_OUTPUTCLR2_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos) /*!< SCT OUTPUTCLR2: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn14_Pos 14 /*!< SCT OUTPUTCLR2: CLRn14 Position */\r
-#define SCT_OUTPUTCLR2_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos) /*!< SCT OUTPUTCLR2: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR2_CLRn15_Pos 15 /*!< SCT OUTPUTCLR2: CLRn15 Position */\r
-#define SCT_OUTPUTCLR2_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos) /*!< SCT OUTPUTCLR2: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET3 -----------------------------------------\r
-#define SCT_OUTPUTSET3_SETn0_Pos 0 /*!< SCT OUTPUTSET3: SETn0 Position */\r
-#define SCT_OUTPUTSET3_SETn0_Msk (0x01UL << SCT_OUTPUTSET3_SETn0_Pos) /*!< SCT OUTPUTSET3: SETn0 Mask */\r
-#define SCT_OUTPUTSET3_SETn1_Pos 1 /*!< SCT OUTPUTSET3: SETn1 Position */\r
-#define SCT_OUTPUTSET3_SETn1_Msk (0x01UL << SCT_OUTPUTSET3_SETn1_Pos) /*!< SCT OUTPUTSET3: SETn1 Mask */\r
-#define SCT_OUTPUTSET3_SETn2_Pos 2 /*!< SCT OUTPUTSET3: SETn2 Position */\r
-#define SCT_OUTPUTSET3_SETn2_Msk (0x01UL << SCT_OUTPUTSET3_SETn2_Pos) /*!< SCT OUTPUTSET3: SETn2 Mask */\r
-#define SCT_OUTPUTSET3_SETn3_Pos 3 /*!< SCT OUTPUTSET3: SETn3 Position */\r
-#define SCT_OUTPUTSET3_SETn3_Msk (0x01UL << SCT_OUTPUTSET3_SETn3_Pos) /*!< SCT OUTPUTSET3: SETn3 Mask */\r
-#define SCT_OUTPUTSET3_SETn4_Pos 4 /*!< SCT OUTPUTSET3: SETn4 Position */\r
-#define SCT_OUTPUTSET3_SETn4_Msk (0x01UL << SCT_OUTPUTSET3_SETn4_Pos) /*!< SCT OUTPUTSET3: SETn4 Mask */\r
-#define SCT_OUTPUTSET3_SETn5_Pos 5 /*!< SCT OUTPUTSET3: SETn5 Position */\r
-#define SCT_OUTPUTSET3_SETn5_Msk (0x01UL << SCT_OUTPUTSET3_SETn5_Pos) /*!< SCT OUTPUTSET3: SETn5 Mask */\r
-#define SCT_OUTPUTSET3_SETn6_Pos 6 /*!< SCT OUTPUTSET3: SETn6 Position */\r
-#define SCT_OUTPUTSET3_SETn6_Msk (0x01UL << SCT_OUTPUTSET3_SETn6_Pos) /*!< SCT OUTPUTSET3: SETn6 Mask */\r
-#define SCT_OUTPUTSET3_SETn7_Pos 7 /*!< SCT OUTPUTSET3: SETn7 Position */\r
-#define SCT_OUTPUTSET3_SETn7_Msk (0x01UL << SCT_OUTPUTSET3_SETn7_Pos) /*!< SCT OUTPUTSET3: SETn7 Mask */\r
-#define SCT_OUTPUTSET3_SETn8_Pos 8 /*!< SCT OUTPUTSET3: SETn8 Position */\r
-#define SCT_OUTPUTSET3_SETn8_Msk (0x01UL << SCT_OUTPUTSET3_SETn8_Pos) /*!< SCT OUTPUTSET3: SETn8 Mask */\r
-#define SCT_OUTPUTSET3_SETn9_Pos 9 /*!< SCT OUTPUTSET3: SETn9 Position */\r
-#define SCT_OUTPUTSET3_SETn9_Msk (0x01UL << SCT_OUTPUTSET3_SETn9_Pos) /*!< SCT OUTPUTSET3: SETn9 Mask */\r
-#define SCT_OUTPUTSET3_SETn10_Pos 10 /*!< SCT OUTPUTSET3: SETn10 Position */\r
-#define SCT_OUTPUTSET3_SETn10_Msk (0x01UL << SCT_OUTPUTSET3_SETn10_Pos) /*!< SCT OUTPUTSET3: SETn10 Mask */\r
-#define SCT_OUTPUTSET3_SETn11_Pos 11 /*!< SCT OUTPUTSET3: SETn11 Position */\r
-#define SCT_OUTPUTSET3_SETn11_Msk (0x01UL << SCT_OUTPUTSET3_SETn11_Pos) /*!< SCT OUTPUTSET3: SETn11 Mask */\r
-#define SCT_OUTPUTSET3_SETn12_Pos 12 /*!< SCT OUTPUTSET3: SETn12 Position */\r
-#define SCT_OUTPUTSET3_SETn12_Msk (0x01UL << SCT_OUTPUTSET3_SETn12_Pos) /*!< SCT OUTPUTSET3: SETn12 Mask */\r
-#define SCT_OUTPUTSET3_SETn13_Pos 13 /*!< SCT OUTPUTSET3: SETn13 Position */\r
-#define SCT_OUTPUTSET3_SETn13_Msk (0x01UL << SCT_OUTPUTSET3_SETn13_Pos) /*!< SCT OUTPUTSET3: SETn13 Mask */\r
-#define SCT_OUTPUTSET3_SETn14_Pos 14 /*!< SCT OUTPUTSET3: SETn14 Position */\r
-#define SCT_OUTPUTSET3_SETn14_Msk (0x01UL << SCT_OUTPUTSET3_SETn14_Pos) /*!< SCT OUTPUTSET3: SETn14 Mask */\r
-#define SCT_OUTPUTSET3_SETn15_Pos 15 /*!< SCT OUTPUTSET3: SETn15 Position */\r
-#define SCT_OUTPUTSET3_SETn15_Msk (0x01UL << SCT_OUTPUTSET3_SETn15_Pos) /*!< SCT OUTPUTSET3: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR3 -----------------------------------------\r
-#define SCT_OUTPUTCLR3_CLRn0_Pos 0 /*!< SCT OUTPUTCLR3: CLRn0 Position */\r
-#define SCT_OUTPUTCLR3_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos) /*!< SCT OUTPUTCLR3: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn1_Pos 1 /*!< SCT OUTPUTCLR3: CLRn1 Position */\r
-#define SCT_OUTPUTCLR3_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos) /*!< SCT OUTPUTCLR3: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn2_Pos 2 /*!< SCT OUTPUTCLR3: CLRn2 Position */\r
-#define SCT_OUTPUTCLR3_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos) /*!< SCT OUTPUTCLR3: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn3_Pos 3 /*!< SCT OUTPUTCLR3: CLRn3 Position */\r
-#define SCT_OUTPUTCLR3_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos) /*!< SCT OUTPUTCLR3: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn4_Pos 4 /*!< SCT OUTPUTCLR3: CLRn4 Position */\r
-#define SCT_OUTPUTCLR3_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos) /*!< SCT OUTPUTCLR3: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn5_Pos 5 /*!< SCT OUTPUTCLR3: CLRn5 Position */\r
-#define SCT_OUTPUTCLR3_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos) /*!< SCT OUTPUTCLR3: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn6_Pos 6 /*!< SCT OUTPUTCLR3: CLRn6 Position */\r
-#define SCT_OUTPUTCLR3_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos) /*!< SCT OUTPUTCLR3: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn7_Pos 7 /*!< SCT OUTPUTCLR3: CLRn7 Position */\r
-#define SCT_OUTPUTCLR3_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos) /*!< SCT OUTPUTCLR3: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn8_Pos 8 /*!< SCT OUTPUTCLR3: CLRn8 Position */\r
-#define SCT_OUTPUTCLR3_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos) /*!< SCT OUTPUTCLR3: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn9_Pos 9 /*!< SCT OUTPUTCLR3: CLRn9 Position */\r
-#define SCT_OUTPUTCLR3_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos) /*!< SCT OUTPUTCLR3: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn10_Pos 10 /*!< SCT OUTPUTCLR3: CLRn10 Position */\r
-#define SCT_OUTPUTCLR3_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos) /*!< SCT OUTPUTCLR3: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn11_Pos 11 /*!< SCT OUTPUTCLR3: CLRn11 Position */\r
-#define SCT_OUTPUTCLR3_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos) /*!< SCT OUTPUTCLR3: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn12_Pos 12 /*!< SCT OUTPUTCLR3: CLRn12 Position */\r
-#define SCT_OUTPUTCLR3_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos) /*!< SCT OUTPUTCLR3: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn13_Pos 13 /*!< SCT OUTPUTCLR3: CLRn13 Position */\r
-#define SCT_OUTPUTCLR3_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos) /*!< SCT OUTPUTCLR3: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn14_Pos 14 /*!< SCT OUTPUTCLR3: CLRn14 Position */\r
-#define SCT_OUTPUTCLR3_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos) /*!< SCT OUTPUTCLR3: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR3_CLRn15_Pos 15 /*!< SCT OUTPUTCLR3: CLRn15 Position */\r
-#define SCT_OUTPUTCLR3_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos) /*!< SCT OUTPUTCLR3: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET4 -----------------------------------------\r
-#define SCT_OUTPUTSET4_SETn0_Pos 0 /*!< SCT OUTPUTSET4: SETn0 Position */\r
-#define SCT_OUTPUTSET4_SETn0_Msk (0x01UL << SCT_OUTPUTSET4_SETn0_Pos) /*!< SCT OUTPUTSET4: SETn0 Mask */\r
-#define SCT_OUTPUTSET4_SETn1_Pos 1 /*!< SCT OUTPUTSET4: SETn1 Position */\r
-#define SCT_OUTPUTSET4_SETn1_Msk (0x01UL << SCT_OUTPUTSET4_SETn1_Pos) /*!< SCT OUTPUTSET4: SETn1 Mask */\r
-#define SCT_OUTPUTSET4_SETn2_Pos 2 /*!< SCT OUTPUTSET4: SETn2 Position */\r
-#define SCT_OUTPUTSET4_SETn2_Msk (0x01UL << SCT_OUTPUTSET4_SETn2_Pos) /*!< SCT OUTPUTSET4: SETn2 Mask */\r
-#define SCT_OUTPUTSET4_SETn3_Pos 3 /*!< SCT OUTPUTSET4: SETn3 Position */\r
-#define SCT_OUTPUTSET4_SETn3_Msk (0x01UL << SCT_OUTPUTSET4_SETn3_Pos) /*!< SCT OUTPUTSET4: SETn3 Mask */\r
-#define SCT_OUTPUTSET4_SETn4_Pos 4 /*!< SCT OUTPUTSET4: SETn4 Position */\r
-#define SCT_OUTPUTSET4_SETn4_Msk (0x01UL << SCT_OUTPUTSET4_SETn4_Pos) /*!< SCT OUTPUTSET4: SETn4 Mask */\r
-#define SCT_OUTPUTSET4_SETn5_Pos 5 /*!< SCT OUTPUTSET4: SETn5 Position */\r
-#define SCT_OUTPUTSET4_SETn5_Msk (0x01UL << SCT_OUTPUTSET4_SETn5_Pos) /*!< SCT OUTPUTSET4: SETn5 Mask */\r
-#define SCT_OUTPUTSET4_SETn6_Pos 6 /*!< SCT OUTPUTSET4: SETn6 Position */\r
-#define SCT_OUTPUTSET4_SETn6_Msk (0x01UL << SCT_OUTPUTSET4_SETn6_Pos) /*!< SCT OUTPUTSET4: SETn6 Mask */\r
-#define SCT_OUTPUTSET4_SETn7_Pos 7 /*!< SCT OUTPUTSET4: SETn7 Position */\r
-#define SCT_OUTPUTSET4_SETn7_Msk (0x01UL << SCT_OUTPUTSET4_SETn7_Pos) /*!< SCT OUTPUTSET4: SETn7 Mask */\r
-#define SCT_OUTPUTSET4_SETn8_Pos 8 /*!< SCT OUTPUTSET4: SETn8 Position */\r
-#define SCT_OUTPUTSET4_SETn8_Msk (0x01UL << SCT_OUTPUTSET4_SETn8_Pos) /*!< SCT OUTPUTSET4: SETn8 Mask */\r
-#define SCT_OUTPUTSET4_SETn9_Pos 9 /*!< SCT OUTPUTSET4: SETn9 Position */\r
-#define SCT_OUTPUTSET4_SETn9_Msk (0x01UL << SCT_OUTPUTSET4_SETn9_Pos) /*!< SCT OUTPUTSET4: SETn9 Mask */\r
-#define SCT_OUTPUTSET4_SETn10_Pos 10 /*!< SCT OUTPUTSET4: SETn10 Position */\r
-#define SCT_OUTPUTSET4_SETn10_Msk (0x01UL << SCT_OUTPUTSET4_SETn10_Pos) /*!< SCT OUTPUTSET4: SETn10 Mask */\r
-#define SCT_OUTPUTSET4_SETn11_Pos 11 /*!< SCT OUTPUTSET4: SETn11 Position */\r
-#define SCT_OUTPUTSET4_SETn11_Msk (0x01UL << SCT_OUTPUTSET4_SETn11_Pos) /*!< SCT OUTPUTSET4: SETn11 Mask */\r
-#define SCT_OUTPUTSET4_SETn12_Pos 12 /*!< SCT OUTPUTSET4: SETn12 Position */\r
-#define SCT_OUTPUTSET4_SETn12_Msk (0x01UL << SCT_OUTPUTSET4_SETn12_Pos) /*!< SCT OUTPUTSET4: SETn12 Mask */\r
-#define SCT_OUTPUTSET4_SETn13_Pos 13 /*!< SCT OUTPUTSET4: SETn13 Position */\r
-#define SCT_OUTPUTSET4_SETn13_Msk (0x01UL << SCT_OUTPUTSET4_SETn13_Pos) /*!< SCT OUTPUTSET4: SETn13 Mask */\r
-#define SCT_OUTPUTSET4_SETn14_Pos 14 /*!< SCT OUTPUTSET4: SETn14 Position */\r
-#define SCT_OUTPUTSET4_SETn14_Msk (0x01UL << SCT_OUTPUTSET4_SETn14_Pos) /*!< SCT OUTPUTSET4: SETn14 Mask */\r
-#define SCT_OUTPUTSET4_SETn15_Pos 15 /*!< SCT OUTPUTSET4: SETn15 Position */\r
-#define SCT_OUTPUTSET4_SETn15_Msk (0x01UL << SCT_OUTPUTSET4_SETn15_Pos) /*!< SCT OUTPUTSET4: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR4 -----------------------------------------\r
-#define SCT_OUTPUTCLR4_CLRn0_Pos 0 /*!< SCT OUTPUTCLR4: CLRn0 Position */\r
-#define SCT_OUTPUTCLR4_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos) /*!< SCT OUTPUTCLR4: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn1_Pos 1 /*!< SCT OUTPUTCLR4: CLRn1 Position */\r
-#define SCT_OUTPUTCLR4_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos) /*!< SCT OUTPUTCLR4: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn2_Pos 2 /*!< SCT OUTPUTCLR4: CLRn2 Position */\r
-#define SCT_OUTPUTCLR4_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos) /*!< SCT OUTPUTCLR4: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn3_Pos 3 /*!< SCT OUTPUTCLR4: CLRn3 Position */\r
-#define SCT_OUTPUTCLR4_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos) /*!< SCT OUTPUTCLR4: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn4_Pos 4 /*!< SCT OUTPUTCLR4: CLRn4 Position */\r
-#define SCT_OUTPUTCLR4_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos) /*!< SCT OUTPUTCLR4: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn5_Pos 5 /*!< SCT OUTPUTCLR4: CLRn5 Position */\r
-#define SCT_OUTPUTCLR4_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos) /*!< SCT OUTPUTCLR4: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn6_Pos 6 /*!< SCT OUTPUTCLR4: CLRn6 Position */\r
-#define SCT_OUTPUTCLR4_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos) /*!< SCT OUTPUTCLR4: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn7_Pos 7 /*!< SCT OUTPUTCLR4: CLRn7 Position */\r
-#define SCT_OUTPUTCLR4_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos) /*!< SCT OUTPUTCLR4: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn8_Pos 8 /*!< SCT OUTPUTCLR4: CLRn8 Position */\r
-#define SCT_OUTPUTCLR4_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos) /*!< SCT OUTPUTCLR4: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn9_Pos 9 /*!< SCT OUTPUTCLR4: CLRn9 Position */\r
-#define SCT_OUTPUTCLR4_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos) /*!< SCT OUTPUTCLR4: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn10_Pos 10 /*!< SCT OUTPUTCLR4: CLRn10 Position */\r
-#define SCT_OUTPUTCLR4_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos) /*!< SCT OUTPUTCLR4: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn11_Pos 11 /*!< SCT OUTPUTCLR4: CLRn11 Position */\r
-#define SCT_OUTPUTCLR4_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos) /*!< SCT OUTPUTCLR4: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn12_Pos 12 /*!< SCT OUTPUTCLR4: CLRn12 Position */\r
-#define SCT_OUTPUTCLR4_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos) /*!< SCT OUTPUTCLR4: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn13_Pos 13 /*!< SCT OUTPUTCLR4: CLRn13 Position */\r
-#define SCT_OUTPUTCLR4_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos) /*!< SCT OUTPUTCLR4: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn14_Pos 14 /*!< SCT OUTPUTCLR4: CLRn14 Position */\r
-#define SCT_OUTPUTCLR4_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos) /*!< SCT OUTPUTCLR4: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR4_CLRn15_Pos 15 /*!< SCT OUTPUTCLR4: CLRn15 Position */\r
-#define SCT_OUTPUTCLR4_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos) /*!< SCT OUTPUTCLR4: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET5 -----------------------------------------\r
-#define SCT_OUTPUTSET5_SETn0_Pos 0 /*!< SCT OUTPUTSET5: SETn0 Position */\r
-#define SCT_OUTPUTSET5_SETn0_Msk (0x01UL << SCT_OUTPUTSET5_SETn0_Pos) /*!< SCT OUTPUTSET5: SETn0 Mask */\r
-#define SCT_OUTPUTSET5_SETn1_Pos 1 /*!< SCT OUTPUTSET5: SETn1 Position */\r
-#define SCT_OUTPUTSET5_SETn1_Msk (0x01UL << SCT_OUTPUTSET5_SETn1_Pos) /*!< SCT OUTPUTSET5: SETn1 Mask */\r
-#define SCT_OUTPUTSET5_SETn2_Pos 2 /*!< SCT OUTPUTSET5: SETn2 Position */\r
-#define SCT_OUTPUTSET5_SETn2_Msk (0x01UL << SCT_OUTPUTSET5_SETn2_Pos) /*!< SCT OUTPUTSET5: SETn2 Mask */\r
-#define SCT_OUTPUTSET5_SETn3_Pos 3 /*!< SCT OUTPUTSET5: SETn3 Position */\r
-#define SCT_OUTPUTSET5_SETn3_Msk (0x01UL << SCT_OUTPUTSET5_SETn3_Pos) /*!< SCT OUTPUTSET5: SETn3 Mask */\r
-#define SCT_OUTPUTSET5_SETn4_Pos 4 /*!< SCT OUTPUTSET5: SETn4 Position */\r
-#define SCT_OUTPUTSET5_SETn4_Msk (0x01UL << SCT_OUTPUTSET5_SETn4_Pos) /*!< SCT OUTPUTSET5: SETn4 Mask */\r
-#define SCT_OUTPUTSET5_SETn5_Pos 5 /*!< SCT OUTPUTSET5: SETn5 Position */\r
-#define SCT_OUTPUTSET5_SETn5_Msk (0x01UL << SCT_OUTPUTSET5_SETn5_Pos) /*!< SCT OUTPUTSET5: SETn5 Mask */\r
-#define SCT_OUTPUTSET5_SETn6_Pos 6 /*!< SCT OUTPUTSET5: SETn6 Position */\r
-#define SCT_OUTPUTSET5_SETn6_Msk (0x01UL << SCT_OUTPUTSET5_SETn6_Pos) /*!< SCT OUTPUTSET5: SETn6 Mask */\r
-#define SCT_OUTPUTSET5_SETn7_Pos 7 /*!< SCT OUTPUTSET5: SETn7 Position */\r
-#define SCT_OUTPUTSET5_SETn7_Msk (0x01UL << SCT_OUTPUTSET5_SETn7_Pos) /*!< SCT OUTPUTSET5: SETn7 Mask */\r
-#define SCT_OUTPUTSET5_SETn8_Pos 8 /*!< SCT OUTPUTSET5: SETn8 Position */\r
-#define SCT_OUTPUTSET5_SETn8_Msk (0x01UL << SCT_OUTPUTSET5_SETn8_Pos) /*!< SCT OUTPUTSET5: SETn8 Mask */\r
-#define SCT_OUTPUTSET5_SETn9_Pos 9 /*!< SCT OUTPUTSET5: SETn9 Position */\r
-#define SCT_OUTPUTSET5_SETn9_Msk (0x01UL << SCT_OUTPUTSET5_SETn9_Pos) /*!< SCT OUTPUTSET5: SETn9 Mask */\r
-#define SCT_OUTPUTSET5_SETn10_Pos 10 /*!< SCT OUTPUTSET5: SETn10 Position */\r
-#define SCT_OUTPUTSET5_SETn10_Msk (0x01UL << SCT_OUTPUTSET5_SETn10_Pos) /*!< SCT OUTPUTSET5: SETn10 Mask */\r
-#define SCT_OUTPUTSET5_SETn11_Pos 11 /*!< SCT OUTPUTSET5: SETn11 Position */\r
-#define SCT_OUTPUTSET5_SETn11_Msk (0x01UL << SCT_OUTPUTSET5_SETn11_Pos) /*!< SCT OUTPUTSET5: SETn11 Mask */\r
-#define SCT_OUTPUTSET5_SETn12_Pos 12 /*!< SCT OUTPUTSET5: SETn12 Position */\r
-#define SCT_OUTPUTSET5_SETn12_Msk (0x01UL << SCT_OUTPUTSET5_SETn12_Pos) /*!< SCT OUTPUTSET5: SETn12 Mask */\r
-#define SCT_OUTPUTSET5_SETn13_Pos 13 /*!< SCT OUTPUTSET5: SETn13 Position */\r
-#define SCT_OUTPUTSET5_SETn13_Msk (0x01UL << SCT_OUTPUTSET5_SETn13_Pos) /*!< SCT OUTPUTSET5: SETn13 Mask */\r
-#define SCT_OUTPUTSET5_SETn14_Pos 14 /*!< SCT OUTPUTSET5: SETn14 Position */\r
-#define SCT_OUTPUTSET5_SETn14_Msk (0x01UL << SCT_OUTPUTSET5_SETn14_Pos) /*!< SCT OUTPUTSET5: SETn14 Mask */\r
-#define SCT_OUTPUTSET5_SETn15_Pos 15 /*!< SCT OUTPUTSET5: SETn15 Position */\r
-#define SCT_OUTPUTSET5_SETn15_Msk (0x01UL << SCT_OUTPUTSET5_SETn15_Pos) /*!< SCT OUTPUTSET5: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR5 -----------------------------------------\r
-#define SCT_OUTPUTCLR5_CLRn0_Pos 0 /*!< SCT OUTPUTCLR5: CLRn0 Position */\r
-#define SCT_OUTPUTCLR5_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos) /*!< SCT OUTPUTCLR5: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn1_Pos 1 /*!< SCT OUTPUTCLR5: CLRn1 Position */\r
-#define SCT_OUTPUTCLR5_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos) /*!< SCT OUTPUTCLR5: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn2_Pos 2 /*!< SCT OUTPUTCLR5: CLRn2 Position */\r
-#define SCT_OUTPUTCLR5_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos) /*!< SCT OUTPUTCLR5: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn3_Pos 3 /*!< SCT OUTPUTCLR5: CLRn3 Position */\r
-#define SCT_OUTPUTCLR5_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos) /*!< SCT OUTPUTCLR5: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn4_Pos 4 /*!< SCT OUTPUTCLR5: CLRn4 Position */\r
-#define SCT_OUTPUTCLR5_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos) /*!< SCT OUTPUTCLR5: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn5_Pos 5 /*!< SCT OUTPUTCLR5: CLRn5 Position */\r
-#define SCT_OUTPUTCLR5_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos) /*!< SCT OUTPUTCLR5: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn6_Pos 6 /*!< SCT OUTPUTCLR5: CLRn6 Position */\r
-#define SCT_OUTPUTCLR5_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos) /*!< SCT OUTPUTCLR5: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn7_Pos 7 /*!< SCT OUTPUTCLR5: CLRn7 Position */\r
-#define SCT_OUTPUTCLR5_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos) /*!< SCT OUTPUTCLR5: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn8_Pos 8 /*!< SCT OUTPUTCLR5: CLRn8 Position */\r
-#define SCT_OUTPUTCLR5_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos) /*!< SCT OUTPUTCLR5: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn9_Pos 9 /*!< SCT OUTPUTCLR5: CLRn9 Position */\r
-#define SCT_OUTPUTCLR5_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos) /*!< SCT OUTPUTCLR5: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn10_Pos 10 /*!< SCT OUTPUTCLR5: CLRn10 Position */\r
-#define SCT_OUTPUTCLR5_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos) /*!< SCT OUTPUTCLR5: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn11_Pos 11 /*!< SCT OUTPUTCLR5: CLRn11 Position */\r
-#define SCT_OUTPUTCLR5_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos) /*!< SCT OUTPUTCLR5: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn12_Pos 12 /*!< SCT OUTPUTCLR5: CLRn12 Position */\r
-#define SCT_OUTPUTCLR5_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos) /*!< SCT OUTPUTCLR5: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn13_Pos 13 /*!< SCT OUTPUTCLR5: CLRn13 Position */\r
-#define SCT_OUTPUTCLR5_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos) /*!< SCT OUTPUTCLR5: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn14_Pos 14 /*!< SCT OUTPUTCLR5: CLRn14 Position */\r
-#define SCT_OUTPUTCLR5_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos) /*!< SCT OUTPUTCLR5: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR5_CLRn15_Pos 15 /*!< SCT OUTPUTCLR5: CLRn15 Position */\r
-#define SCT_OUTPUTCLR5_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos) /*!< SCT OUTPUTCLR5: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET6 -----------------------------------------\r
-#define SCT_OUTPUTSET6_SETn0_Pos 0 /*!< SCT OUTPUTSET6: SETn0 Position */\r
-#define SCT_OUTPUTSET6_SETn0_Msk (0x01UL << SCT_OUTPUTSET6_SETn0_Pos) /*!< SCT OUTPUTSET6: SETn0 Mask */\r
-#define SCT_OUTPUTSET6_SETn1_Pos 1 /*!< SCT OUTPUTSET6: SETn1 Position */\r
-#define SCT_OUTPUTSET6_SETn1_Msk (0x01UL << SCT_OUTPUTSET6_SETn1_Pos) /*!< SCT OUTPUTSET6: SETn1 Mask */\r
-#define SCT_OUTPUTSET6_SETn2_Pos 2 /*!< SCT OUTPUTSET6: SETn2 Position */\r
-#define SCT_OUTPUTSET6_SETn2_Msk (0x01UL << SCT_OUTPUTSET6_SETn2_Pos) /*!< SCT OUTPUTSET6: SETn2 Mask */\r
-#define SCT_OUTPUTSET6_SETn3_Pos 3 /*!< SCT OUTPUTSET6: SETn3 Position */\r
-#define SCT_OUTPUTSET6_SETn3_Msk (0x01UL << SCT_OUTPUTSET6_SETn3_Pos) /*!< SCT OUTPUTSET6: SETn3 Mask */\r
-#define SCT_OUTPUTSET6_SETn4_Pos 4 /*!< SCT OUTPUTSET6: SETn4 Position */\r
-#define SCT_OUTPUTSET6_SETn4_Msk (0x01UL << SCT_OUTPUTSET6_SETn4_Pos) /*!< SCT OUTPUTSET6: SETn4 Mask */\r
-#define SCT_OUTPUTSET6_SETn5_Pos 5 /*!< SCT OUTPUTSET6: SETn5 Position */\r
-#define SCT_OUTPUTSET6_SETn5_Msk (0x01UL << SCT_OUTPUTSET6_SETn5_Pos) /*!< SCT OUTPUTSET6: SETn5 Mask */\r
-#define SCT_OUTPUTSET6_SETn6_Pos 6 /*!< SCT OUTPUTSET6: SETn6 Position */\r
-#define SCT_OUTPUTSET6_SETn6_Msk (0x01UL << SCT_OUTPUTSET6_SETn6_Pos) /*!< SCT OUTPUTSET6: SETn6 Mask */\r
-#define SCT_OUTPUTSET6_SETn7_Pos 7 /*!< SCT OUTPUTSET6: SETn7 Position */\r
-#define SCT_OUTPUTSET6_SETn7_Msk (0x01UL << SCT_OUTPUTSET6_SETn7_Pos) /*!< SCT OUTPUTSET6: SETn7 Mask */\r
-#define SCT_OUTPUTSET6_SETn8_Pos 8 /*!< SCT OUTPUTSET6: SETn8 Position */\r
-#define SCT_OUTPUTSET6_SETn8_Msk (0x01UL << SCT_OUTPUTSET6_SETn8_Pos) /*!< SCT OUTPUTSET6: SETn8 Mask */\r
-#define SCT_OUTPUTSET6_SETn9_Pos 9 /*!< SCT OUTPUTSET6: SETn9 Position */\r
-#define SCT_OUTPUTSET6_SETn9_Msk (0x01UL << SCT_OUTPUTSET6_SETn9_Pos) /*!< SCT OUTPUTSET6: SETn9 Mask */\r
-#define SCT_OUTPUTSET6_SETn10_Pos 10 /*!< SCT OUTPUTSET6: SETn10 Position */\r
-#define SCT_OUTPUTSET6_SETn10_Msk (0x01UL << SCT_OUTPUTSET6_SETn10_Pos) /*!< SCT OUTPUTSET6: SETn10 Mask */\r
-#define SCT_OUTPUTSET6_SETn11_Pos 11 /*!< SCT OUTPUTSET6: SETn11 Position */\r
-#define SCT_OUTPUTSET6_SETn11_Msk (0x01UL << SCT_OUTPUTSET6_SETn11_Pos) /*!< SCT OUTPUTSET6: SETn11 Mask */\r
-#define SCT_OUTPUTSET6_SETn12_Pos 12 /*!< SCT OUTPUTSET6: SETn12 Position */\r
-#define SCT_OUTPUTSET6_SETn12_Msk (0x01UL << SCT_OUTPUTSET6_SETn12_Pos) /*!< SCT OUTPUTSET6: SETn12 Mask */\r
-#define SCT_OUTPUTSET6_SETn13_Pos 13 /*!< SCT OUTPUTSET6: SETn13 Position */\r
-#define SCT_OUTPUTSET6_SETn13_Msk (0x01UL << SCT_OUTPUTSET6_SETn13_Pos) /*!< SCT OUTPUTSET6: SETn13 Mask */\r
-#define SCT_OUTPUTSET6_SETn14_Pos 14 /*!< SCT OUTPUTSET6: SETn14 Position */\r
-#define SCT_OUTPUTSET6_SETn14_Msk (0x01UL << SCT_OUTPUTSET6_SETn14_Pos) /*!< SCT OUTPUTSET6: SETn14 Mask */\r
-#define SCT_OUTPUTSET6_SETn15_Pos 15 /*!< SCT OUTPUTSET6: SETn15 Position */\r
-#define SCT_OUTPUTSET6_SETn15_Msk (0x01UL << SCT_OUTPUTSET6_SETn15_Pos) /*!< SCT OUTPUTSET6: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR6 -----------------------------------------\r
-#define SCT_OUTPUTCLR6_CLRn0_Pos 0 /*!< SCT OUTPUTCLR6: CLRn0 Position */\r
-#define SCT_OUTPUTCLR6_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos) /*!< SCT OUTPUTCLR6: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn1_Pos 1 /*!< SCT OUTPUTCLR6: CLRn1 Position */\r
-#define SCT_OUTPUTCLR6_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos) /*!< SCT OUTPUTCLR6: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn2_Pos 2 /*!< SCT OUTPUTCLR6: CLRn2 Position */\r
-#define SCT_OUTPUTCLR6_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos) /*!< SCT OUTPUTCLR6: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn3_Pos 3 /*!< SCT OUTPUTCLR6: CLRn3 Position */\r
-#define SCT_OUTPUTCLR6_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos) /*!< SCT OUTPUTCLR6: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn4_Pos 4 /*!< SCT OUTPUTCLR6: CLRn4 Position */\r
-#define SCT_OUTPUTCLR6_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos) /*!< SCT OUTPUTCLR6: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn5_Pos 5 /*!< SCT OUTPUTCLR6: CLRn5 Position */\r
-#define SCT_OUTPUTCLR6_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos) /*!< SCT OUTPUTCLR6: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn6_Pos 6 /*!< SCT OUTPUTCLR6: CLRn6 Position */\r
-#define SCT_OUTPUTCLR6_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos) /*!< SCT OUTPUTCLR6: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn7_Pos 7 /*!< SCT OUTPUTCLR6: CLRn7 Position */\r
-#define SCT_OUTPUTCLR6_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos) /*!< SCT OUTPUTCLR6: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn8_Pos 8 /*!< SCT OUTPUTCLR6: CLRn8 Position */\r
-#define SCT_OUTPUTCLR6_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos) /*!< SCT OUTPUTCLR6: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn9_Pos 9 /*!< SCT OUTPUTCLR6: CLRn9 Position */\r
-#define SCT_OUTPUTCLR6_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos) /*!< SCT OUTPUTCLR6: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn10_Pos 10 /*!< SCT OUTPUTCLR6: CLRn10 Position */\r
-#define SCT_OUTPUTCLR6_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos) /*!< SCT OUTPUTCLR6: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn11_Pos 11 /*!< SCT OUTPUTCLR6: CLRn11 Position */\r
-#define SCT_OUTPUTCLR6_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos) /*!< SCT OUTPUTCLR6: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn12_Pos 12 /*!< SCT OUTPUTCLR6: CLRn12 Position */\r
-#define SCT_OUTPUTCLR6_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos) /*!< SCT OUTPUTCLR6: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn13_Pos 13 /*!< SCT OUTPUTCLR6: CLRn13 Position */\r
-#define SCT_OUTPUTCLR6_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos) /*!< SCT OUTPUTCLR6: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn14_Pos 14 /*!< SCT OUTPUTCLR6: CLRn14 Position */\r
-#define SCT_OUTPUTCLR6_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos) /*!< SCT OUTPUTCLR6: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR6_CLRn15_Pos 15 /*!< SCT OUTPUTCLR6: CLRn15 Position */\r
-#define SCT_OUTPUTCLR6_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos) /*!< SCT OUTPUTCLR6: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET7 -----------------------------------------\r
-#define SCT_OUTPUTSET7_SETn0_Pos 0 /*!< SCT OUTPUTSET7: SETn0 Position */\r
-#define SCT_OUTPUTSET7_SETn0_Msk (0x01UL << SCT_OUTPUTSET7_SETn0_Pos) /*!< SCT OUTPUTSET7: SETn0 Mask */\r
-#define SCT_OUTPUTSET7_SETn1_Pos 1 /*!< SCT OUTPUTSET7: SETn1 Position */\r
-#define SCT_OUTPUTSET7_SETn1_Msk (0x01UL << SCT_OUTPUTSET7_SETn1_Pos) /*!< SCT OUTPUTSET7: SETn1 Mask */\r
-#define SCT_OUTPUTSET7_SETn2_Pos 2 /*!< SCT OUTPUTSET7: SETn2 Position */\r
-#define SCT_OUTPUTSET7_SETn2_Msk (0x01UL << SCT_OUTPUTSET7_SETn2_Pos) /*!< SCT OUTPUTSET7: SETn2 Mask */\r
-#define SCT_OUTPUTSET7_SETn3_Pos 3 /*!< SCT OUTPUTSET7: SETn3 Position */\r
-#define SCT_OUTPUTSET7_SETn3_Msk (0x01UL << SCT_OUTPUTSET7_SETn3_Pos) /*!< SCT OUTPUTSET7: SETn3 Mask */\r
-#define SCT_OUTPUTSET7_SETn4_Pos 4 /*!< SCT OUTPUTSET7: SETn4 Position */\r
-#define SCT_OUTPUTSET7_SETn4_Msk (0x01UL << SCT_OUTPUTSET7_SETn4_Pos) /*!< SCT OUTPUTSET7: SETn4 Mask */\r
-#define SCT_OUTPUTSET7_SETn5_Pos 5 /*!< SCT OUTPUTSET7: SETn5 Position */\r
-#define SCT_OUTPUTSET7_SETn5_Msk (0x01UL << SCT_OUTPUTSET7_SETn5_Pos) /*!< SCT OUTPUTSET7: SETn5 Mask */\r
-#define SCT_OUTPUTSET7_SETn6_Pos 6 /*!< SCT OUTPUTSET7: SETn6 Position */\r
-#define SCT_OUTPUTSET7_SETn6_Msk (0x01UL << SCT_OUTPUTSET7_SETn6_Pos) /*!< SCT OUTPUTSET7: SETn6 Mask */\r
-#define SCT_OUTPUTSET7_SETn7_Pos 7 /*!< SCT OUTPUTSET7: SETn7 Position */\r
-#define SCT_OUTPUTSET7_SETn7_Msk (0x01UL << SCT_OUTPUTSET7_SETn7_Pos) /*!< SCT OUTPUTSET7: SETn7 Mask */\r
-#define SCT_OUTPUTSET7_SETn8_Pos 8 /*!< SCT OUTPUTSET7: SETn8 Position */\r
-#define SCT_OUTPUTSET7_SETn8_Msk (0x01UL << SCT_OUTPUTSET7_SETn8_Pos) /*!< SCT OUTPUTSET7: SETn8 Mask */\r
-#define SCT_OUTPUTSET7_SETn9_Pos 9 /*!< SCT OUTPUTSET7: SETn9 Position */\r
-#define SCT_OUTPUTSET7_SETn9_Msk (0x01UL << SCT_OUTPUTSET7_SETn9_Pos) /*!< SCT OUTPUTSET7: SETn9 Mask */\r
-#define SCT_OUTPUTSET7_SETn10_Pos 10 /*!< SCT OUTPUTSET7: SETn10 Position */\r
-#define SCT_OUTPUTSET7_SETn10_Msk (0x01UL << SCT_OUTPUTSET7_SETn10_Pos) /*!< SCT OUTPUTSET7: SETn10 Mask */\r
-#define SCT_OUTPUTSET7_SETn11_Pos 11 /*!< SCT OUTPUTSET7: SETn11 Position */\r
-#define SCT_OUTPUTSET7_SETn11_Msk (0x01UL << SCT_OUTPUTSET7_SETn11_Pos) /*!< SCT OUTPUTSET7: SETn11 Mask */\r
-#define SCT_OUTPUTSET7_SETn12_Pos 12 /*!< SCT OUTPUTSET7: SETn12 Position */\r
-#define SCT_OUTPUTSET7_SETn12_Msk (0x01UL << SCT_OUTPUTSET7_SETn12_Pos) /*!< SCT OUTPUTSET7: SETn12 Mask */\r
-#define SCT_OUTPUTSET7_SETn13_Pos 13 /*!< SCT OUTPUTSET7: SETn13 Position */\r
-#define SCT_OUTPUTSET7_SETn13_Msk (0x01UL << SCT_OUTPUTSET7_SETn13_Pos) /*!< SCT OUTPUTSET7: SETn13 Mask */\r
-#define SCT_OUTPUTSET7_SETn14_Pos 14 /*!< SCT OUTPUTSET7: SETn14 Position */\r
-#define SCT_OUTPUTSET7_SETn14_Msk (0x01UL << SCT_OUTPUTSET7_SETn14_Pos) /*!< SCT OUTPUTSET7: SETn14 Mask */\r
-#define SCT_OUTPUTSET7_SETn15_Pos 15 /*!< SCT OUTPUTSET7: SETn15 Position */\r
-#define SCT_OUTPUTSET7_SETn15_Msk (0x01UL << SCT_OUTPUTSET7_SETn15_Pos) /*!< SCT OUTPUTSET7: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR7 -----------------------------------------\r
-#define SCT_OUTPUTCLR7_CLRn0_Pos 0 /*!< SCT OUTPUTCLR7: CLRn0 Position */\r
-#define SCT_OUTPUTCLR7_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos) /*!< SCT OUTPUTCLR7: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn1_Pos 1 /*!< SCT OUTPUTCLR7: CLRn1 Position */\r
-#define SCT_OUTPUTCLR7_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos) /*!< SCT OUTPUTCLR7: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn2_Pos 2 /*!< SCT OUTPUTCLR7: CLRn2 Position */\r
-#define SCT_OUTPUTCLR7_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos) /*!< SCT OUTPUTCLR7: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn3_Pos 3 /*!< SCT OUTPUTCLR7: CLRn3 Position */\r
-#define SCT_OUTPUTCLR7_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos) /*!< SCT OUTPUTCLR7: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn4_Pos 4 /*!< SCT OUTPUTCLR7: CLRn4 Position */\r
-#define SCT_OUTPUTCLR7_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos) /*!< SCT OUTPUTCLR7: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn5_Pos 5 /*!< SCT OUTPUTCLR7: CLRn5 Position */\r
-#define SCT_OUTPUTCLR7_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos) /*!< SCT OUTPUTCLR7: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn6_Pos 6 /*!< SCT OUTPUTCLR7: CLRn6 Position */\r
-#define SCT_OUTPUTCLR7_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos) /*!< SCT OUTPUTCLR7: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn7_Pos 7 /*!< SCT OUTPUTCLR7: CLRn7 Position */\r
-#define SCT_OUTPUTCLR7_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos) /*!< SCT OUTPUTCLR7: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn8_Pos 8 /*!< SCT OUTPUTCLR7: CLRn8 Position */\r
-#define SCT_OUTPUTCLR7_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos) /*!< SCT OUTPUTCLR7: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn9_Pos 9 /*!< SCT OUTPUTCLR7: CLRn9 Position */\r
-#define SCT_OUTPUTCLR7_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos) /*!< SCT OUTPUTCLR7: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn10_Pos 10 /*!< SCT OUTPUTCLR7: CLRn10 Position */\r
-#define SCT_OUTPUTCLR7_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos) /*!< SCT OUTPUTCLR7: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn11_Pos 11 /*!< SCT OUTPUTCLR7: CLRn11 Position */\r
-#define SCT_OUTPUTCLR7_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos) /*!< SCT OUTPUTCLR7: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn12_Pos 12 /*!< SCT OUTPUTCLR7: CLRn12 Position */\r
-#define SCT_OUTPUTCLR7_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos) /*!< SCT OUTPUTCLR7: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn13_Pos 13 /*!< SCT OUTPUTCLR7: CLRn13 Position */\r
-#define SCT_OUTPUTCLR7_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos) /*!< SCT OUTPUTCLR7: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn14_Pos 14 /*!< SCT OUTPUTCLR7: CLRn14 Position */\r
-#define SCT_OUTPUTCLR7_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos) /*!< SCT OUTPUTCLR7: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR7_CLRn15_Pos 15 /*!< SCT OUTPUTCLR7: CLRn15 Position */\r
-#define SCT_OUTPUTCLR7_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos) /*!< SCT OUTPUTCLR7: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET8 -----------------------------------------\r
-#define SCT_OUTPUTSET8_SETn0_Pos 0 /*!< SCT OUTPUTSET8: SETn0 Position */\r
-#define SCT_OUTPUTSET8_SETn0_Msk (0x01UL << SCT_OUTPUTSET8_SETn0_Pos) /*!< SCT OUTPUTSET8: SETn0 Mask */\r
-#define SCT_OUTPUTSET8_SETn1_Pos 1 /*!< SCT OUTPUTSET8: SETn1 Position */\r
-#define SCT_OUTPUTSET8_SETn1_Msk (0x01UL << SCT_OUTPUTSET8_SETn1_Pos) /*!< SCT OUTPUTSET8: SETn1 Mask */\r
-#define SCT_OUTPUTSET8_SETn2_Pos 2 /*!< SCT OUTPUTSET8: SETn2 Position */\r
-#define SCT_OUTPUTSET8_SETn2_Msk (0x01UL << SCT_OUTPUTSET8_SETn2_Pos) /*!< SCT OUTPUTSET8: SETn2 Mask */\r
-#define SCT_OUTPUTSET8_SETn3_Pos 3 /*!< SCT OUTPUTSET8: SETn3 Position */\r
-#define SCT_OUTPUTSET8_SETn3_Msk (0x01UL << SCT_OUTPUTSET8_SETn3_Pos) /*!< SCT OUTPUTSET8: SETn3 Mask */\r
-#define SCT_OUTPUTSET8_SETn4_Pos 4 /*!< SCT OUTPUTSET8: SETn4 Position */\r
-#define SCT_OUTPUTSET8_SETn4_Msk (0x01UL << SCT_OUTPUTSET8_SETn4_Pos) /*!< SCT OUTPUTSET8: SETn4 Mask */\r
-#define SCT_OUTPUTSET8_SETn5_Pos 5 /*!< SCT OUTPUTSET8: SETn5 Position */\r
-#define SCT_OUTPUTSET8_SETn5_Msk (0x01UL << SCT_OUTPUTSET8_SETn5_Pos) /*!< SCT OUTPUTSET8: SETn5 Mask */\r
-#define SCT_OUTPUTSET8_SETn6_Pos 6 /*!< SCT OUTPUTSET8: SETn6 Position */\r
-#define SCT_OUTPUTSET8_SETn6_Msk (0x01UL << SCT_OUTPUTSET8_SETn6_Pos) /*!< SCT OUTPUTSET8: SETn6 Mask */\r
-#define SCT_OUTPUTSET8_SETn7_Pos 7 /*!< SCT OUTPUTSET8: SETn7 Position */\r
-#define SCT_OUTPUTSET8_SETn7_Msk (0x01UL << SCT_OUTPUTSET8_SETn7_Pos) /*!< SCT OUTPUTSET8: SETn7 Mask */\r
-#define SCT_OUTPUTSET8_SETn8_Pos 8 /*!< SCT OUTPUTSET8: SETn8 Position */\r
-#define SCT_OUTPUTSET8_SETn8_Msk (0x01UL << SCT_OUTPUTSET8_SETn8_Pos) /*!< SCT OUTPUTSET8: SETn8 Mask */\r
-#define SCT_OUTPUTSET8_SETn9_Pos 9 /*!< SCT OUTPUTSET8: SETn9 Position */\r
-#define SCT_OUTPUTSET8_SETn9_Msk (0x01UL << SCT_OUTPUTSET8_SETn9_Pos) /*!< SCT OUTPUTSET8: SETn9 Mask */\r
-#define SCT_OUTPUTSET8_SETn10_Pos 10 /*!< SCT OUTPUTSET8: SETn10 Position */\r
-#define SCT_OUTPUTSET8_SETn10_Msk (0x01UL << SCT_OUTPUTSET8_SETn10_Pos) /*!< SCT OUTPUTSET8: SETn10 Mask */\r
-#define SCT_OUTPUTSET8_SETn11_Pos 11 /*!< SCT OUTPUTSET8: SETn11 Position */\r
-#define SCT_OUTPUTSET8_SETn11_Msk (0x01UL << SCT_OUTPUTSET8_SETn11_Pos) /*!< SCT OUTPUTSET8: SETn11 Mask */\r
-#define SCT_OUTPUTSET8_SETn12_Pos 12 /*!< SCT OUTPUTSET8: SETn12 Position */\r
-#define SCT_OUTPUTSET8_SETn12_Msk (0x01UL << SCT_OUTPUTSET8_SETn12_Pos) /*!< SCT OUTPUTSET8: SETn12 Mask */\r
-#define SCT_OUTPUTSET8_SETn13_Pos 13 /*!< SCT OUTPUTSET8: SETn13 Position */\r
-#define SCT_OUTPUTSET8_SETn13_Msk (0x01UL << SCT_OUTPUTSET8_SETn13_Pos) /*!< SCT OUTPUTSET8: SETn13 Mask */\r
-#define SCT_OUTPUTSET8_SETn14_Pos 14 /*!< SCT OUTPUTSET8: SETn14 Position */\r
-#define SCT_OUTPUTSET8_SETn14_Msk (0x01UL << SCT_OUTPUTSET8_SETn14_Pos) /*!< SCT OUTPUTSET8: SETn14 Mask */\r
-#define SCT_OUTPUTSET8_SETn15_Pos 15 /*!< SCT OUTPUTSET8: SETn15 Position */\r
-#define SCT_OUTPUTSET8_SETn15_Msk (0x01UL << SCT_OUTPUTSET8_SETn15_Pos) /*!< SCT OUTPUTSET8: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR8 -----------------------------------------\r
-#define SCT_OUTPUTCLR8_CLRn0_Pos 0 /*!< SCT OUTPUTCLR8: CLRn0 Position */\r
-#define SCT_OUTPUTCLR8_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos) /*!< SCT OUTPUTCLR8: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn1_Pos 1 /*!< SCT OUTPUTCLR8: CLRn1 Position */\r
-#define SCT_OUTPUTCLR8_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos) /*!< SCT OUTPUTCLR8: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn2_Pos 2 /*!< SCT OUTPUTCLR8: CLRn2 Position */\r
-#define SCT_OUTPUTCLR8_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos) /*!< SCT OUTPUTCLR8: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn3_Pos 3 /*!< SCT OUTPUTCLR8: CLRn3 Position */\r
-#define SCT_OUTPUTCLR8_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos) /*!< SCT OUTPUTCLR8: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn4_Pos 4 /*!< SCT OUTPUTCLR8: CLRn4 Position */\r
-#define SCT_OUTPUTCLR8_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos) /*!< SCT OUTPUTCLR8: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn5_Pos 5 /*!< SCT OUTPUTCLR8: CLRn5 Position */\r
-#define SCT_OUTPUTCLR8_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos) /*!< SCT OUTPUTCLR8: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn6_Pos 6 /*!< SCT OUTPUTCLR8: CLRn6 Position */\r
-#define SCT_OUTPUTCLR8_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos) /*!< SCT OUTPUTCLR8: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn7_Pos 7 /*!< SCT OUTPUTCLR8: CLRn7 Position */\r
-#define SCT_OUTPUTCLR8_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos) /*!< SCT OUTPUTCLR8: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn8_Pos 8 /*!< SCT OUTPUTCLR8: CLRn8 Position */\r
-#define SCT_OUTPUTCLR8_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos) /*!< SCT OUTPUTCLR8: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn9_Pos 9 /*!< SCT OUTPUTCLR8: CLRn9 Position */\r
-#define SCT_OUTPUTCLR8_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos) /*!< SCT OUTPUTCLR8: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn10_Pos 10 /*!< SCT OUTPUTCLR8: CLRn10 Position */\r
-#define SCT_OUTPUTCLR8_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos) /*!< SCT OUTPUTCLR8: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn11_Pos 11 /*!< SCT OUTPUTCLR8: CLRn11 Position */\r
-#define SCT_OUTPUTCLR8_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos) /*!< SCT OUTPUTCLR8: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn12_Pos 12 /*!< SCT OUTPUTCLR8: CLRn12 Position */\r
-#define SCT_OUTPUTCLR8_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos) /*!< SCT OUTPUTCLR8: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn13_Pos 13 /*!< SCT OUTPUTCLR8: CLRn13 Position */\r
-#define SCT_OUTPUTCLR8_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos) /*!< SCT OUTPUTCLR8: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn14_Pos 14 /*!< SCT OUTPUTCLR8: CLRn14 Position */\r
-#define SCT_OUTPUTCLR8_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos) /*!< SCT OUTPUTCLR8: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR8_CLRn15_Pos 15 /*!< SCT OUTPUTCLR8: CLRn15 Position */\r
-#define SCT_OUTPUTCLR8_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos) /*!< SCT OUTPUTCLR8: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET9 -----------------------------------------\r
-#define SCT_OUTPUTSET9_SETn0_Pos 0 /*!< SCT OUTPUTSET9: SETn0 Position */\r
-#define SCT_OUTPUTSET9_SETn0_Msk (0x01UL << SCT_OUTPUTSET9_SETn0_Pos) /*!< SCT OUTPUTSET9: SETn0 Mask */\r
-#define SCT_OUTPUTSET9_SETn1_Pos 1 /*!< SCT OUTPUTSET9: SETn1 Position */\r
-#define SCT_OUTPUTSET9_SETn1_Msk (0x01UL << SCT_OUTPUTSET9_SETn1_Pos) /*!< SCT OUTPUTSET9: SETn1 Mask */\r
-#define SCT_OUTPUTSET9_SETn2_Pos 2 /*!< SCT OUTPUTSET9: SETn2 Position */\r
-#define SCT_OUTPUTSET9_SETn2_Msk (0x01UL << SCT_OUTPUTSET9_SETn2_Pos) /*!< SCT OUTPUTSET9: SETn2 Mask */\r
-#define SCT_OUTPUTSET9_SETn3_Pos 3 /*!< SCT OUTPUTSET9: SETn3 Position */\r
-#define SCT_OUTPUTSET9_SETn3_Msk (0x01UL << SCT_OUTPUTSET9_SETn3_Pos) /*!< SCT OUTPUTSET9: SETn3 Mask */\r
-#define SCT_OUTPUTSET9_SETn4_Pos 4 /*!< SCT OUTPUTSET9: SETn4 Position */\r
-#define SCT_OUTPUTSET9_SETn4_Msk (0x01UL << SCT_OUTPUTSET9_SETn4_Pos) /*!< SCT OUTPUTSET9: SETn4 Mask */\r
-#define SCT_OUTPUTSET9_SETn5_Pos 5 /*!< SCT OUTPUTSET9: SETn5 Position */\r
-#define SCT_OUTPUTSET9_SETn5_Msk (0x01UL << SCT_OUTPUTSET9_SETn5_Pos) /*!< SCT OUTPUTSET9: SETn5 Mask */\r
-#define SCT_OUTPUTSET9_SETn6_Pos 6 /*!< SCT OUTPUTSET9: SETn6 Position */\r
-#define SCT_OUTPUTSET9_SETn6_Msk (0x01UL << SCT_OUTPUTSET9_SETn6_Pos) /*!< SCT OUTPUTSET9: SETn6 Mask */\r
-#define SCT_OUTPUTSET9_SETn7_Pos 7 /*!< SCT OUTPUTSET9: SETn7 Position */\r
-#define SCT_OUTPUTSET9_SETn7_Msk (0x01UL << SCT_OUTPUTSET9_SETn7_Pos) /*!< SCT OUTPUTSET9: SETn7 Mask */\r
-#define SCT_OUTPUTSET9_SETn8_Pos 8 /*!< SCT OUTPUTSET9: SETn8 Position */\r
-#define SCT_OUTPUTSET9_SETn8_Msk (0x01UL << SCT_OUTPUTSET9_SETn8_Pos) /*!< SCT OUTPUTSET9: SETn8 Mask */\r
-#define SCT_OUTPUTSET9_SETn9_Pos 9 /*!< SCT OUTPUTSET9: SETn9 Position */\r
-#define SCT_OUTPUTSET9_SETn9_Msk (0x01UL << SCT_OUTPUTSET9_SETn9_Pos) /*!< SCT OUTPUTSET9: SETn9 Mask */\r
-#define SCT_OUTPUTSET9_SETn10_Pos 10 /*!< SCT OUTPUTSET9: SETn10 Position */\r
-#define SCT_OUTPUTSET9_SETn10_Msk (0x01UL << SCT_OUTPUTSET9_SETn10_Pos) /*!< SCT OUTPUTSET9: SETn10 Mask */\r
-#define SCT_OUTPUTSET9_SETn11_Pos 11 /*!< SCT OUTPUTSET9: SETn11 Position */\r
-#define SCT_OUTPUTSET9_SETn11_Msk (0x01UL << SCT_OUTPUTSET9_SETn11_Pos) /*!< SCT OUTPUTSET9: SETn11 Mask */\r
-#define SCT_OUTPUTSET9_SETn12_Pos 12 /*!< SCT OUTPUTSET9: SETn12 Position */\r
-#define SCT_OUTPUTSET9_SETn12_Msk (0x01UL << SCT_OUTPUTSET9_SETn12_Pos) /*!< SCT OUTPUTSET9: SETn12 Mask */\r
-#define SCT_OUTPUTSET9_SETn13_Pos 13 /*!< SCT OUTPUTSET9: SETn13 Position */\r
-#define SCT_OUTPUTSET9_SETn13_Msk (0x01UL << SCT_OUTPUTSET9_SETn13_Pos) /*!< SCT OUTPUTSET9: SETn13 Mask */\r
-#define SCT_OUTPUTSET9_SETn14_Pos 14 /*!< SCT OUTPUTSET9: SETn14 Position */\r
-#define SCT_OUTPUTSET9_SETn14_Msk (0x01UL << SCT_OUTPUTSET9_SETn14_Pos) /*!< SCT OUTPUTSET9: SETn14 Mask */\r
-#define SCT_OUTPUTSET9_SETn15_Pos 15 /*!< SCT OUTPUTSET9: SETn15 Position */\r
-#define SCT_OUTPUTSET9_SETn15_Msk (0x01UL << SCT_OUTPUTSET9_SETn15_Pos) /*!< SCT OUTPUTSET9: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR9 -----------------------------------------\r
-#define SCT_OUTPUTCLR9_CLRn0_Pos 0 /*!< SCT OUTPUTCLR9: CLRn0 Position */\r
-#define SCT_OUTPUTCLR9_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos) /*!< SCT OUTPUTCLR9: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn1_Pos 1 /*!< SCT OUTPUTCLR9: CLRn1 Position */\r
-#define SCT_OUTPUTCLR9_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos) /*!< SCT OUTPUTCLR9: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn2_Pos 2 /*!< SCT OUTPUTCLR9: CLRn2 Position */\r
-#define SCT_OUTPUTCLR9_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos) /*!< SCT OUTPUTCLR9: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn3_Pos 3 /*!< SCT OUTPUTCLR9: CLRn3 Position */\r
-#define SCT_OUTPUTCLR9_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos) /*!< SCT OUTPUTCLR9: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn4_Pos 4 /*!< SCT OUTPUTCLR9: CLRn4 Position */\r
-#define SCT_OUTPUTCLR9_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos) /*!< SCT OUTPUTCLR9: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn5_Pos 5 /*!< SCT OUTPUTCLR9: CLRn5 Position */\r
-#define SCT_OUTPUTCLR9_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos) /*!< SCT OUTPUTCLR9: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn6_Pos 6 /*!< SCT OUTPUTCLR9: CLRn6 Position */\r
-#define SCT_OUTPUTCLR9_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos) /*!< SCT OUTPUTCLR9: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn7_Pos 7 /*!< SCT OUTPUTCLR9: CLRn7 Position */\r
-#define SCT_OUTPUTCLR9_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos) /*!< SCT OUTPUTCLR9: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn8_Pos 8 /*!< SCT OUTPUTCLR9: CLRn8 Position */\r
-#define SCT_OUTPUTCLR9_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos) /*!< SCT OUTPUTCLR9: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn9_Pos 9 /*!< SCT OUTPUTCLR9: CLRn9 Position */\r
-#define SCT_OUTPUTCLR9_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos) /*!< SCT OUTPUTCLR9: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn10_Pos 10 /*!< SCT OUTPUTCLR9: CLRn10 Position */\r
-#define SCT_OUTPUTCLR9_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos) /*!< SCT OUTPUTCLR9: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn11_Pos 11 /*!< SCT OUTPUTCLR9: CLRn11 Position */\r
-#define SCT_OUTPUTCLR9_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos) /*!< SCT OUTPUTCLR9: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn12_Pos 12 /*!< SCT OUTPUTCLR9: CLRn12 Position */\r
-#define SCT_OUTPUTCLR9_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos) /*!< SCT OUTPUTCLR9: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn13_Pos 13 /*!< SCT OUTPUTCLR9: CLRn13 Position */\r
-#define SCT_OUTPUTCLR9_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos) /*!< SCT OUTPUTCLR9: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn14_Pos 14 /*!< SCT OUTPUTCLR9: CLRn14 Position */\r
-#define SCT_OUTPUTCLR9_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos) /*!< SCT OUTPUTCLR9: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR9_CLRn15_Pos 15 /*!< SCT OUTPUTCLR9: CLRn15 Position */\r
-#define SCT_OUTPUTCLR9_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos) /*!< SCT OUTPUTCLR9: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET10 ----------------------------------------\r
-#define SCT_OUTPUTSET10_SETn0_Pos 0 /*!< SCT OUTPUTSET10: SETn0 Position */\r
-#define SCT_OUTPUTSET10_SETn0_Msk (0x01UL << SCT_OUTPUTSET10_SETn0_Pos) /*!< SCT OUTPUTSET10: SETn0 Mask */\r
-#define SCT_OUTPUTSET10_SETn1_Pos 1 /*!< SCT OUTPUTSET10: SETn1 Position */\r
-#define SCT_OUTPUTSET10_SETn1_Msk (0x01UL << SCT_OUTPUTSET10_SETn1_Pos) /*!< SCT OUTPUTSET10: SETn1 Mask */\r
-#define SCT_OUTPUTSET10_SETn2_Pos 2 /*!< SCT OUTPUTSET10: SETn2 Position */\r
-#define SCT_OUTPUTSET10_SETn2_Msk (0x01UL << SCT_OUTPUTSET10_SETn2_Pos) /*!< SCT OUTPUTSET10: SETn2 Mask */\r
-#define SCT_OUTPUTSET10_SETn3_Pos 3 /*!< SCT OUTPUTSET10: SETn3 Position */\r
-#define SCT_OUTPUTSET10_SETn3_Msk (0x01UL << SCT_OUTPUTSET10_SETn3_Pos) /*!< SCT OUTPUTSET10: SETn3 Mask */\r
-#define SCT_OUTPUTSET10_SETn4_Pos 4 /*!< SCT OUTPUTSET10: SETn4 Position */\r
-#define SCT_OUTPUTSET10_SETn4_Msk (0x01UL << SCT_OUTPUTSET10_SETn4_Pos) /*!< SCT OUTPUTSET10: SETn4 Mask */\r
-#define SCT_OUTPUTSET10_SETn5_Pos 5 /*!< SCT OUTPUTSET10: SETn5 Position */\r
-#define SCT_OUTPUTSET10_SETn5_Msk (0x01UL << SCT_OUTPUTSET10_SETn5_Pos) /*!< SCT OUTPUTSET10: SETn5 Mask */\r
-#define SCT_OUTPUTSET10_SETn6_Pos 6 /*!< SCT OUTPUTSET10: SETn6 Position */\r
-#define SCT_OUTPUTSET10_SETn6_Msk (0x01UL << SCT_OUTPUTSET10_SETn6_Pos) /*!< SCT OUTPUTSET10: SETn6 Mask */\r
-#define SCT_OUTPUTSET10_SETn7_Pos 7 /*!< SCT OUTPUTSET10: SETn7 Position */\r
-#define SCT_OUTPUTSET10_SETn7_Msk (0x01UL << SCT_OUTPUTSET10_SETn7_Pos) /*!< SCT OUTPUTSET10: SETn7 Mask */\r
-#define SCT_OUTPUTSET10_SETn8_Pos 8 /*!< SCT OUTPUTSET10: SETn8 Position */\r
-#define SCT_OUTPUTSET10_SETn8_Msk (0x01UL << SCT_OUTPUTSET10_SETn8_Pos) /*!< SCT OUTPUTSET10: SETn8 Mask */\r
-#define SCT_OUTPUTSET10_SETn9_Pos 9 /*!< SCT OUTPUTSET10: SETn9 Position */\r
-#define SCT_OUTPUTSET10_SETn9_Msk (0x01UL << SCT_OUTPUTSET10_SETn9_Pos) /*!< SCT OUTPUTSET10: SETn9 Mask */\r
-#define SCT_OUTPUTSET10_SETn10_Pos 10 /*!< SCT OUTPUTSET10: SETn10 Position */\r
-#define SCT_OUTPUTSET10_SETn10_Msk (0x01UL << SCT_OUTPUTSET10_SETn10_Pos) /*!< SCT OUTPUTSET10: SETn10 Mask */\r
-#define SCT_OUTPUTSET10_SETn11_Pos 11 /*!< SCT OUTPUTSET10: SETn11 Position */\r
-#define SCT_OUTPUTSET10_SETn11_Msk (0x01UL << SCT_OUTPUTSET10_SETn11_Pos) /*!< SCT OUTPUTSET10: SETn11 Mask */\r
-#define SCT_OUTPUTSET10_SETn12_Pos 12 /*!< SCT OUTPUTSET10: SETn12 Position */\r
-#define SCT_OUTPUTSET10_SETn12_Msk (0x01UL << SCT_OUTPUTSET10_SETn12_Pos) /*!< SCT OUTPUTSET10: SETn12 Mask */\r
-#define SCT_OUTPUTSET10_SETn13_Pos 13 /*!< SCT OUTPUTSET10: SETn13 Position */\r
-#define SCT_OUTPUTSET10_SETn13_Msk (0x01UL << SCT_OUTPUTSET10_SETn13_Pos) /*!< SCT OUTPUTSET10: SETn13 Mask */\r
-#define SCT_OUTPUTSET10_SETn14_Pos 14 /*!< SCT OUTPUTSET10: SETn14 Position */\r
-#define SCT_OUTPUTSET10_SETn14_Msk (0x01UL << SCT_OUTPUTSET10_SETn14_Pos) /*!< SCT OUTPUTSET10: SETn14 Mask */\r
-#define SCT_OUTPUTSET10_SETn15_Pos 15 /*!< SCT OUTPUTSET10: SETn15 Position */\r
-#define SCT_OUTPUTSET10_SETn15_Msk (0x01UL << SCT_OUTPUTSET10_SETn15_Pos) /*!< SCT OUTPUTSET10: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR10 ----------------------------------------\r
-#define SCT_OUTPUTCLR10_CLRn0_Pos 0 /*!< SCT OUTPUTCLR10: CLRn0 Position */\r
-#define SCT_OUTPUTCLR10_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos) /*!< SCT OUTPUTCLR10: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn1_Pos 1 /*!< SCT OUTPUTCLR10: CLRn1 Position */\r
-#define SCT_OUTPUTCLR10_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos) /*!< SCT OUTPUTCLR10: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn2_Pos 2 /*!< SCT OUTPUTCLR10: CLRn2 Position */\r
-#define SCT_OUTPUTCLR10_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos) /*!< SCT OUTPUTCLR10: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn3_Pos 3 /*!< SCT OUTPUTCLR10: CLRn3 Position */\r
-#define SCT_OUTPUTCLR10_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos) /*!< SCT OUTPUTCLR10: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn4_Pos 4 /*!< SCT OUTPUTCLR10: CLRn4 Position */\r
-#define SCT_OUTPUTCLR10_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos) /*!< SCT OUTPUTCLR10: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn5_Pos 5 /*!< SCT OUTPUTCLR10: CLRn5 Position */\r
-#define SCT_OUTPUTCLR10_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos) /*!< SCT OUTPUTCLR10: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn6_Pos 6 /*!< SCT OUTPUTCLR10: CLRn6 Position */\r
-#define SCT_OUTPUTCLR10_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos) /*!< SCT OUTPUTCLR10: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn7_Pos 7 /*!< SCT OUTPUTCLR10: CLRn7 Position */\r
-#define SCT_OUTPUTCLR10_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos) /*!< SCT OUTPUTCLR10: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn8_Pos 8 /*!< SCT OUTPUTCLR10: CLRn8 Position */\r
-#define SCT_OUTPUTCLR10_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos) /*!< SCT OUTPUTCLR10: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn9_Pos 9 /*!< SCT OUTPUTCLR10: CLRn9 Position */\r
-#define SCT_OUTPUTCLR10_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos) /*!< SCT OUTPUTCLR10: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn10_Pos 10 /*!< SCT OUTPUTCLR10: CLRn10 Position */\r
-#define SCT_OUTPUTCLR10_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos) /*!< SCT OUTPUTCLR10: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn11_Pos 11 /*!< SCT OUTPUTCLR10: CLRn11 Position */\r
-#define SCT_OUTPUTCLR10_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos) /*!< SCT OUTPUTCLR10: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn12_Pos 12 /*!< SCT OUTPUTCLR10: CLRn12 Position */\r
-#define SCT_OUTPUTCLR10_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos) /*!< SCT OUTPUTCLR10: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn13_Pos 13 /*!< SCT OUTPUTCLR10: CLRn13 Position */\r
-#define SCT_OUTPUTCLR10_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos) /*!< SCT OUTPUTCLR10: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn14_Pos 14 /*!< SCT OUTPUTCLR10: CLRn14 Position */\r
-#define SCT_OUTPUTCLR10_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos) /*!< SCT OUTPUTCLR10: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR10_CLRn15_Pos 15 /*!< SCT OUTPUTCLR10: CLRn15 Position */\r
-#define SCT_OUTPUTCLR10_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos) /*!< SCT OUTPUTCLR10: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET11 ----------------------------------------\r
-#define SCT_OUTPUTSET11_SETn0_Pos 0 /*!< SCT OUTPUTSET11: SETn0 Position */\r
-#define SCT_OUTPUTSET11_SETn0_Msk (0x01UL << SCT_OUTPUTSET11_SETn0_Pos) /*!< SCT OUTPUTSET11: SETn0 Mask */\r
-#define SCT_OUTPUTSET11_SETn1_Pos 1 /*!< SCT OUTPUTSET11: SETn1 Position */\r
-#define SCT_OUTPUTSET11_SETn1_Msk (0x01UL << SCT_OUTPUTSET11_SETn1_Pos) /*!< SCT OUTPUTSET11: SETn1 Mask */\r
-#define SCT_OUTPUTSET11_SETn2_Pos 2 /*!< SCT OUTPUTSET11: SETn2 Position */\r
-#define SCT_OUTPUTSET11_SETn2_Msk (0x01UL << SCT_OUTPUTSET11_SETn2_Pos) /*!< SCT OUTPUTSET11: SETn2 Mask */\r
-#define SCT_OUTPUTSET11_SETn3_Pos 3 /*!< SCT OUTPUTSET11: SETn3 Position */\r
-#define SCT_OUTPUTSET11_SETn3_Msk (0x01UL << SCT_OUTPUTSET11_SETn3_Pos) /*!< SCT OUTPUTSET11: SETn3 Mask */\r
-#define SCT_OUTPUTSET11_SETn4_Pos 4 /*!< SCT OUTPUTSET11: SETn4 Position */\r
-#define SCT_OUTPUTSET11_SETn4_Msk (0x01UL << SCT_OUTPUTSET11_SETn4_Pos) /*!< SCT OUTPUTSET11: SETn4 Mask */\r
-#define SCT_OUTPUTSET11_SETn5_Pos 5 /*!< SCT OUTPUTSET11: SETn5 Position */\r
-#define SCT_OUTPUTSET11_SETn5_Msk (0x01UL << SCT_OUTPUTSET11_SETn5_Pos) /*!< SCT OUTPUTSET11: SETn5 Mask */\r
-#define SCT_OUTPUTSET11_SETn6_Pos 6 /*!< SCT OUTPUTSET11: SETn6 Position */\r
-#define SCT_OUTPUTSET11_SETn6_Msk (0x01UL << SCT_OUTPUTSET11_SETn6_Pos) /*!< SCT OUTPUTSET11: SETn6 Mask */\r
-#define SCT_OUTPUTSET11_SETn7_Pos 7 /*!< SCT OUTPUTSET11: SETn7 Position */\r
-#define SCT_OUTPUTSET11_SETn7_Msk (0x01UL << SCT_OUTPUTSET11_SETn7_Pos) /*!< SCT OUTPUTSET11: SETn7 Mask */\r
-#define SCT_OUTPUTSET11_SETn8_Pos 8 /*!< SCT OUTPUTSET11: SETn8 Position */\r
-#define SCT_OUTPUTSET11_SETn8_Msk (0x01UL << SCT_OUTPUTSET11_SETn8_Pos) /*!< SCT OUTPUTSET11: SETn8 Mask */\r
-#define SCT_OUTPUTSET11_SETn9_Pos 9 /*!< SCT OUTPUTSET11: SETn9 Position */\r
-#define SCT_OUTPUTSET11_SETn9_Msk (0x01UL << SCT_OUTPUTSET11_SETn9_Pos) /*!< SCT OUTPUTSET11: SETn9 Mask */\r
-#define SCT_OUTPUTSET11_SETn10_Pos 10 /*!< SCT OUTPUTSET11: SETn10 Position */\r
-#define SCT_OUTPUTSET11_SETn10_Msk (0x01UL << SCT_OUTPUTSET11_SETn10_Pos) /*!< SCT OUTPUTSET11: SETn10 Mask */\r
-#define SCT_OUTPUTSET11_SETn11_Pos 11 /*!< SCT OUTPUTSET11: SETn11 Position */\r
-#define SCT_OUTPUTSET11_SETn11_Msk (0x01UL << SCT_OUTPUTSET11_SETn11_Pos) /*!< SCT OUTPUTSET11: SETn11 Mask */\r
-#define SCT_OUTPUTSET11_SETn12_Pos 12 /*!< SCT OUTPUTSET11: SETn12 Position */\r
-#define SCT_OUTPUTSET11_SETn12_Msk (0x01UL << SCT_OUTPUTSET11_SETn12_Pos) /*!< SCT OUTPUTSET11: SETn12 Mask */\r
-#define SCT_OUTPUTSET11_SETn13_Pos 13 /*!< SCT OUTPUTSET11: SETn13 Position */\r
-#define SCT_OUTPUTSET11_SETn13_Msk (0x01UL << SCT_OUTPUTSET11_SETn13_Pos) /*!< SCT OUTPUTSET11: SETn13 Mask */\r
-#define SCT_OUTPUTSET11_SETn14_Pos 14 /*!< SCT OUTPUTSET11: SETn14 Position */\r
-#define SCT_OUTPUTSET11_SETn14_Msk (0x01UL << SCT_OUTPUTSET11_SETn14_Pos) /*!< SCT OUTPUTSET11: SETn14 Mask */\r
-#define SCT_OUTPUTSET11_SETn15_Pos 15 /*!< SCT OUTPUTSET11: SETn15 Position */\r
-#define SCT_OUTPUTSET11_SETn15_Msk (0x01UL << SCT_OUTPUTSET11_SETn15_Pos) /*!< SCT OUTPUTSET11: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR11 ----------------------------------------\r
-#define SCT_OUTPUTCLR11_CLRn0_Pos 0 /*!< SCT OUTPUTCLR11: CLRn0 Position */\r
-#define SCT_OUTPUTCLR11_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos) /*!< SCT OUTPUTCLR11: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn1_Pos 1 /*!< SCT OUTPUTCLR11: CLRn1 Position */\r
-#define SCT_OUTPUTCLR11_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos) /*!< SCT OUTPUTCLR11: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn2_Pos 2 /*!< SCT OUTPUTCLR11: CLRn2 Position */\r
-#define SCT_OUTPUTCLR11_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos) /*!< SCT OUTPUTCLR11: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn3_Pos 3 /*!< SCT OUTPUTCLR11: CLRn3 Position */\r
-#define SCT_OUTPUTCLR11_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos) /*!< SCT OUTPUTCLR11: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn4_Pos 4 /*!< SCT OUTPUTCLR11: CLRn4 Position */\r
-#define SCT_OUTPUTCLR11_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos) /*!< SCT OUTPUTCLR11: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn5_Pos 5 /*!< SCT OUTPUTCLR11: CLRn5 Position */\r
-#define SCT_OUTPUTCLR11_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos) /*!< SCT OUTPUTCLR11: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn6_Pos 6 /*!< SCT OUTPUTCLR11: CLRn6 Position */\r
-#define SCT_OUTPUTCLR11_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos) /*!< SCT OUTPUTCLR11: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn7_Pos 7 /*!< SCT OUTPUTCLR11: CLRn7 Position */\r
-#define SCT_OUTPUTCLR11_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos) /*!< SCT OUTPUTCLR11: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn8_Pos 8 /*!< SCT OUTPUTCLR11: CLRn8 Position */\r
-#define SCT_OUTPUTCLR11_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos) /*!< SCT OUTPUTCLR11: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn9_Pos 9 /*!< SCT OUTPUTCLR11: CLRn9 Position */\r
-#define SCT_OUTPUTCLR11_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos) /*!< SCT OUTPUTCLR11: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn10_Pos 10 /*!< SCT OUTPUTCLR11: CLRn10 Position */\r
-#define SCT_OUTPUTCLR11_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos) /*!< SCT OUTPUTCLR11: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn11_Pos 11 /*!< SCT OUTPUTCLR11: CLRn11 Position */\r
-#define SCT_OUTPUTCLR11_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos) /*!< SCT OUTPUTCLR11: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn12_Pos 12 /*!< SCT OUTPUTCLR11: CLRn12 Position */\r
-#define SCT_OUTPUTCLR11_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos) /*!< SCT OUTPUTCLR11: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn13_Pos 13 /*!< SCT OUTPUTCLR11: CLRn13 Position */\r
-#define SCT_OUTPUTCLR11_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos) /*!< SCT OUTPUTCLR11: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn14_Pos 14 /*!< SCT OUTPUTCLR11: CLRn14 Position */\r
-#define SCT_OUTPUTCLR11_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos) /*!< SCT OUTPUTCLR11: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR11_CLRn15_Pos 15 /*!< SCT OUTPUTCLR11: CLRn15 Position */\r
-#define SCT_OUTPUTCLR11_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos) /*!< SCT OUTPUTCLR11: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET12 ----------------------------------------\r
-#define SCT_OUTPUTSET12_SETn0_Pos 0 /*!< SCT OUTPUTSET12: SETn0 Position */\r
-#define SCT_OUTPUTSET12_SETn0_Msk (0x01UL << SCT_OUTPUTSET12_SETn0_Pos) /*!< SCT OUTPUTSET12: SETn0 Mask */\r
-#define SCT_OUTPUTSET12_SETn1_Pos 1 /*!< SCT OUTPUTSET12: SETn1 Position */\r
-#define SCT_OUTPUTSET12_SETn1_Msk (0x01UL << SCT_OUTPUTSET12_SETn1_Pos) /*!< SCT OUTPUTSET12: SETn1 Mask */\r
-#define SCT_OUTPUTSET12_SETn2_Pos 2 /*!< SCT OUTPUTSET12: SETn2 Position */\r
-#define SCT_OUTPUTSET12_SETn2_Msk (0x01UL << SCT_OUTPUTSET12_SETn2_Pos) /*!< SCT OUTPUTSET12: SETn2 Mask */\r
-#define SCT_OUTPUTSET12_SETn3_Pos 3 /*!< SCT OUTPUTSET12: SETn3 Position */\r
-#define SCT_OUTPUTSET12_SETn3_Msk (0x01UL << SCT_OUTPUTSET12_SETn3_Pos) /*!< SCT OUTPUTSET12: SETn3 Mask */\r
-#define SCT_OUTPUTSET12_SETn4_Pos 4 /*!< SCT OUTPUTSET12: SETn4 Position */\r
-#define SCT_OUTPUTSET12_SETn4_Msk (0x01UL << SCT_OUTPUTSET12_SETn4_Pos) /*!< SCT OUTPUTSET12: SETn4 Mask */\r
-#define SCT_OUTPUTSET12_SETn5_Pos 5 /*!< SCT OUTPUTSET12: SETn5 Position */\r
-#define SCT_OUTPUTSET12_SETn5_Msk (0x01UL << SCT_OUTPUTSET12_SETn5_Pos) /*!< SCT OUTPUTSET12: SETn5 Mask */\r
-#define SCT_OUTPUTSET12_SETn6_Pos 6 /*!< SCT OUTPUTSET12: SETn6 Position */\r
-#define SCT_OUTPUTSET12_SETn6_Msk (0x01UL << SCT_OUTPUTSET12_SETn6_Pos) /*!< SCT OUTPUTSET12: SETn6 Mask */\r
-#define SCT_OUTPUTSET12_SETn7_Pos 7 /*!< SCT OUTPUTSET12: SETn7 Position */\r
-#define SCT_OUTPUTSET12_SETn7_Msk (0x01UL << SCT_OUTPUTSET12_SETn7_Pos) /*!< SCT OUTPUTSET12: SETn7 Mask */\r
-#define SCT_OUTPUTSET12_SETn8_Pos 8 /*!< SCT OUTPUTSET12: SETn8 Position */\r
-#define SCT_OUTPUTSET12_SETn8_Msk (0x01UL << SCT_OUTPUTSET12_SETn8_Pos) /*!< SCT OUTPUTSET12: SETn8 Mask */\r
-#define SCT_OUTPUTSET12_SETn9_Pos 9 /*!< SCT OUTPUTSET12: SETn9 Position */\r
-#define SCT_OUTPUTSET12_SETn9_Msk (0x01UL << SCT_OUTPUTSET12_SETn9_Pos) /*!< SCT OUTPUTSET12: SETn9 Mask */\r
-#define SCT_OUTPUTSET12_SETn10_Pos 10 /*!< SCT OUTPUTSET12: SETn10 Position */\r
-#define SCT_OUTPUTSET12_SETn10_Msk (0x01UL << SCT_OUTPUTSET12_SETn10_Pos) /*!< SCT OUTPUTSET12: SETn10 Mask */\r
-#define SCT_OUTPUTSET12_SETn11_Pos 11 /*!< SCT OUTPUTSET12: SETn11 Position */\r
-#define SCT_OUTPUTSET12_SETn11_Msk (0x01UL << SCT_OUTPUTSET12_SETn11_Pos) /*!< SCT OUTPUTSET12: SETn11 Mask */\r
-#define SCT_OUTPUTSET12_SETn12_Pos 12 /*!< SCT OUTPUTSET12: SETn12 Position */\r
-#define SCT_OUTPUTSET12_SETn12_Msk (0x01UL << SCT_OUTPUTSET12_SETn12_Pos) /*!< SCT OUTPUTSET12: SETn12 Mask */\r
-#define SCT_OUTPUTSET12_SETn13_Pos 13 /*!< SCT OUTPUTSET12: SETn13 Position */\r
-#define SCT_OUTPUTSET12_SETn13_Msk (0x01UL << SCT_OUTPUTSET12_SETn13_Pos) /*!< SCT OUTPUTSET12: SETn13 Mask */\r
-#define SCT_OUTPUTSET12_SETn14_Pos 14 /*!< SCT OUTPUTSET12: SETn14 Position */\r
-#define SCT_OUTPUTSET12_SETn14_Msk (0x01UL << SCT_OUTPUTSET12_SETn14_Pos) /*!< SCT OUTPUTSET12: SETn14 Mask */\r
-#define SCT_OUTPUTSET12_SETn15_Pos 15 /*!< SCT OUTPUTSET12: SETn15 Position */\r
-#define SCT_OUTPUTSET12_SETn15_Msk (0x01UL << SCT_OUTPUTSET12_SETn15_Pos) /*!< SCT OUTPUTSET12: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR12 ----------------------------------------\r
-#define SCT_OUTPUTCLR12_CLRn0_Pos 0 /*!< SCT OUTPUTCLR12: CLRn0 Position */\r
-#define SCT_OUTPUTCLR12_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos) /*!< SCT OUTPUTCLR12: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn1_Pos 1 /*!< SCT OUTPUTCLR12: CLRn1 Position */\r
-#define SCT_OUTPUTCLR12_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos) /*!< SCT OUTPUTCLR12: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn2_Pos 2 /*!< SCT OUTPUTCLR12: CLRn2 Position */\r
-#define SCT_OUTPUTCLR12_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos) /*!< SCT OUTPUTCLR12: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn3_Pos 3 /*!< SCT OUTPUTCLR12: CLRn3 Position */\r
-#define SCT_OUTPUTCLR12_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos) /*!< SCT OUTPUTCLR12: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn4_Pos 4 /*!< SCT OUTPUTCLR12: CLRn4 Position */\r
-#define SCT_OUTPUTCLR12_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos) /*!< SCT OUTPUTCLR12: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn5_Pos 5 /*!< SCT OUTPUTCLR12: CLRn5 Position */\r
-#define SCT_OUTPUTCLR12_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos) /*!< SCT OUTPUTCLR12: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn6_Pos 6 /*!< SCT OUTPUTCLR12: CLRn6 Position */\r
-#define SCT_OUTPUTCLR12_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos) /*!< SCT OUTPUTCLR12: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn7_Pos 7 /*!< SCT OUTPUTCLR12: CLRn7 Position */\r
-#define SCT_OUTPUTCLR12_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos) /*!< SCT OUTPUTCLR12: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn8_Pos 8 /*!< SCT OUTPUTCLR12: CLRn8 Position */\r
-#define SCT_OUTPUTCLR12_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos) /*!< SCT OUTPUTCLR12: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn9_Pos 9 /*!< SCT OUTPUTCLR12: CLRn9 Position */\r
-#define SCT_OUTPUTCLR12_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos) /*!< SCT OUTPUTCLR12: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn10_Pos 10 /*!< SCT OUTPUTCLR12: CLRn10 Position */\r
-#define SCT_OUTPUTCLR12_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos) /*!< SCT OUTPUTCLR12: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn11_Pos 11 /*!< SCT OUTPUTCLR12: CLRn11 Position */\r
-#define SCT_OUTPUTCLR12_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos) /*!< SCT OUTPUTCLR12: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn12_Pos 12 /*!< SCT OUTPUTCLR12: CLRn12 Position */\r
-#define SCT_OUTPUTCLR12_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos) /*!< SCT OUTPUTCLR12: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn13_Pos 13 /*!< SCT OUTPUTCLR12: CLRn13 Position */\r
-#define SCT_OUTPUTCLR12_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos) /*!< SCT OUTPUTCLR12: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn14_Pos 14 /*!< SCT OUTPUTCLR12: CLRn14 Position */\r
-#define SCT_OUTPUTCLR12_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos) /*!< SCT OUTPUTCLR12: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR12_CLRn15_Pos 15 /*!< SCT OUTPUTCLR12: CLRn15 Position */\r
-#define SCT_OUTPUTCLR12_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos) /*!< SCT OUTPUTCLR12: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET13 ----------------------------------------\r
-#define SCT_OUTPUTSET13_SETn0_Pos 0 /*!< SCT OUTPUTSET13: SETn0 Position */\r
-#define SCT_OUTPUTSET13_SETn0_Msk (0x01UL << SCT_OUTPUTSET13_SETn0_Pos) /*!< SCT OUTPUTSET13: SETn0 Mask */\r
-#define SCT_OUTPUTSET13_SETn1_Pos 1 /*!< SCT OUTPUTSET13: SETn1 Position */\r
-#define SCT_OUTPUTSET13_SETn1_Msk (0x01UL << SCT_OUTPUTSET13_SETn1_Pos) /*!< SCT OUTPUTSET13: SETn1 Mask */\r
-#define SCT_OUTPUTSET13_SETn2_Pos 2 /*!< SCT OUTPUTSET13: SETn2 Position */\r
-#define SCT_OUTPUTSET13_SETn2_Msk (0x01UL << SCT_OUTPUTSET13_SETn2_Pos) /*!< SCT OUTPUTSET13: SETn2 Mask */\r
-#define SCT_OUTPUTSET13_SETn3_Pos 3 /*!< SCT OUTPUTSET13: SETn3 Position */\r
-#define SCT_OUTPUTSET13_SETn3_Msk (0x01UL << SCT_OUTPUTSET13_SETn3_Pos) /*!< SCT OUTPUTSET13: SETn3 Mask */\r
-#define SCT_OUTPUTSET13_SETn4_Pos 4 /*!< SCT OUTPUTSET13: SETn4 Position */\r
-#define SCT_OUTPUTSET13_SETn4_Msk (0x01UL << SCT_OUTPUTSET13_SETn4_Pos) /*!< SCT OUTPUTSET13: SETn4 Mask */\r
-#define SCT_OUTPUTSET13_SETn5_Pos 5 /*!< SCT OUTPUTSET13: SETn5 Position */\r
-#define SCT_OUTPUTSET13_SETn5_Msk (0x01UL << SCT_OUTPUTSET13_SETn5_Pos) /*!< SCT OUTPUTSET13: SETn5 Mask */\r
-#define SCT_OUTPUTSET13_SETn6_Pos 6 /*!< SCT OUTPUTSET13: SETn6 Position */\r
-#define SCT_OUTPUTSET13_SETn6_Msk (0x01UL << SCT_OUTPUTSET13_SETn6_Pos) /*!< SCT OUTPUTSET13: SETn6 Mask */\r
-#define SCT_OUTPUTSET13_SETn7_Pos 7 /*!< SCT OUTPUTSET13: SETn7 Position */\r
-#define SCT_OUTPUTSET13_SETn7_Msk (0x01UL << SCT_OUTPUTSET13_SETn7_Pos) /*!< SCT OUTPUTSET13: SETn7 Mask */\r
-#define SCT_OUTPUTSET13_SETn8_Pos 8 /*!< SCT OUTPUTSET13: SETn8 Position */\r
-#define SCT_OUTPUTSET13_SETn8_Msk (0x01UL << SCT_OUTPUTSET13_SETn8_Pos) /*!< SCT OUTPUTSET13: SETn8 Mask */\r
-#define SCT_OUTPUTSET13_SETn9_Pos 9 /*!< SCT OUTPUTSET13: SETn9 Position */\r
-#define SCT_OUTPUTSET13_SETn9_Msk (0x01UL << SCT_OUTPUTSET13_SETn9_Pos) /*!< SCT OUTPUTSET13: SETn9 Mask */\r
-#define SCT_OUTPUTSET13_SETn10_Pos 10 /*!< SCT OUTPUTSET13: SETn10 Position */\r
-#define SCT_OUTPUTSET13_SETn10_Msk (0x01UL << SCT_OUTPUTSET13_SETn10_Pos) /*!< SCT OUTPUTSET13: SETn10 Mask */\r
-#define SCT_OUTPUTSET13_SETn11_Pos 11 /*!< SCT OUTPUTSET13: SETn11 Position */\r
-#define SCT_OUTPUTSET13_SETn11_Msk (0x01UL << SCT_OUTPUTSET13_SETn11_Pos) /*!< SCT OUTPUTSET13: SETn11 Mask */\r
-#define SCT_OUTPUTSET13_SETn12_Pos 12 /*!< SCT OUTPUTSET13: SETn12 Position */\r
-#define SCT_OUTPUTSET13_SETn12_Msk (0x01UL << SCT_OUTPUTSET13_SETn12_Pos) /*!< SCT OUTPUTSET13: SETn12 Mask */\r
-#define SCT_OUTPUTSET13_SETn13_Pos 13 /*!< SCT OUTPUTSET13: SETn13 Position */\r
-#define SCT_OUTPUTSET13_SETn13_Msk (0x01UL << SCT_OUTPUTSET13_SETn13_Pos) /*!< SCT OUTPUTSET13: SETn13 Mask */\r
-#define SCT_OUTPUTSET13_SETn14_Pos 14 /*!< SCT OUTPUTSET13: SETn14 Position */\r
-#define SCT_OUTPUTSET13_SETn14_Msk (0x01UL << SCT_OUTPUTSET13_SETn14_Pos) /*!< SCT OUTPUTSET13: SETn14 Mask */\r
-#define SCT_OUTPUTSET13_SETn15_Pos 15 /*!< SCT OUTPUTSET13: SETn15 Position */\r
-#define SCT_OUTPUTSET13_SETn15_Msk (0x01UL << SCT_OUTPUTSET13_SETn15_Pos) /*!< SCT OUTPUTSET13: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR13 ----------------------------------------\r
-#define SCT_OUTPUTCLR13_CLRn0_Pos 0 /*!< SCT OUTPUTCLR13: CLRn0 Position */\r
-#define SCT_OUTPUTCLR13_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos) /*!< SCT OUTPUTCLR13: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn1_Pos 1 /*!< SCT OUTPUTCLR13: CLRn1 Position */\r
-#define SCT_OUTPUTCLR13_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos) /*!< SCT OUTPUTCLR13: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn2_Pos 2 /*!< SCT OUTPUTCLR13: CLRn2 Position */\r
-#define SCT_OUTPUTCLR13_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos) /*!< SCT OUTPUTCLR13: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn3_Pos 3 /*!< SCT OUTPUTCLR13: CLRn3 Position */\r
-#define SCT_OUTPUTCLR13_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos) /*!< SCT OUTPUTCLR13: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn4_Pos 4 /*!< SCT OUTPUTCLR13: CLRn4 Position */\r
-#define SCT_OUTPUTCLR13_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos) /*!< SCT OUTPUTCLR13: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn5_Pos 5 /*!< SCT OUTPUTCLR13: CLRn5 Position */\r
-#define SCT_OUTPUTCLR13_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos) /*!< SCT OUTPUTCLR13: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn6_Pos 6 /*!< SCT OUTPUTCLR13: CLRn6 Position */\r
-#define SCT_OUTPUTCLR13_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos) /*!< SCT OUTPUTCLR13: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn7_Pos 7 /*!< SCT OUTPUTCLR13: CLRn7 Position */\r
-#define SCT_OUTPUTCLR13_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos) /*!< SCT OUTPUTCLR13: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn8_Pos 8 /*!< SCT OUTPUTCLR13: CLRn8 Position */\r
-#define SCT_OUTPUTCLR13_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos) /*!< SCT OUTPUTCLR13: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn9_Pos 9 /*!< SCT OUTPUTCLR13: CLRn9 Position */\r
-#define SCT_OUTPUTCLR13_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos) /*!< SCT OUTPUTCLR13: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn10_Pos 10 /*!< SCT OUTPUTCLR13: CLRn10 Position */\r
-#define SCT_OUTPUTCLR13_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos) /*!< SCT OUTPUTCLR13: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn11_Pos 11 /*!< SCT OUTPUTCLR13: CLRn11 Position */\r
-#define SCT_OUTPUTCLR13_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos) /*!< SCT OUTPUTCLR13: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn12_Pos 12 /*!< SCT OUTPUTCLR13: CLRn12 Position */\r
-#define SCT_OUTPUTCLR13_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos) /*!< SCT OUTPUTCLR13: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn13_Pos 13 /*!< SCT OUTPUTCLR13: CLRn13 Position */\r
-#define SCT_OUTPUTCLR13_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos) /*!< SCT OUTPUTCLR13: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn14_Pos 14 /*!< SCT OUTPUTCLR13: CLRn14 Position */\r
-#define SCT_OUTPUTCLR13_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos) /*!< SCT OUTPUTCLR13: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR13_CLRn15_Pos 15 /*!< SCT OUTPUTCLR13: CLRn15 Position */\r
-#define SCT_OUTPUTCLR13_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos) /*!< SCT OUTPUTCLR13: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET14 ----------------------------------------\r
-#define SCT_OUTPUTSET14_SETn0_Pos 0 /*!< SCT OUTPUTSET14: SETn0 Position */\r
-#define SCT_OUTPUTSET14_SETn0_Msk (0x01UL << SCT_OUTPUTSET14_SETn0_Pos) /*!< SCT OUTPUTSET14: SETn0 Mask */\r
-#define SCT_OUTPUTSET14_SETn1_Pos 1 /*!< SCT OUTPUTSET14: SETn1 Position */\r
-#define SCT_OUTPUTSET14_SETn1_Msk (0x01UL << SCT_OUTPUTSET14_SETn1_Pos) /*!< SCT OUTPUTSET14: SETn1 Mask */\r
-#define SCT_OUTPUTSET14_SETn2_Pos 2 /*!< SCT OUTPUTSET14: SETn2 Position */\r
-#define SCT_OUTPUTSET14_SETn2_Msk (0x01UL << SCT_OUTPUTSET14_SETn2_Pos) /*!< SCT OUTPUTSET14: SETn2 Mask */\r
-#define SCT_OUTPUTSET14_SETn3_Pos 3 /*!< SCT OUTPUTSET14: SETn3 Position */\r
-#define SCT_OUTPUTSET14_SETn3_Msk (0x01UL << SCT_OUTPUTSET14_SETn3_Pos) /*!< SCT OUTPUTSET14: SETn3 Mask */\r
-#define SCT_OUTPUTSET14_SETn4_Pos 4 /*!< SCT OUTPUTSET14: SETn4 Position */\r
-#define SCT_OUTPUTSET14_SETn4_Msk (0x01UL << SCT_OUTPUTSET14_SETn4_Pos) /*!< SCT OUTPUTSET14: SETn4 Mask */\r
-#define SCT_OUTPUTSET14_SETn5_Pos 5 /*!< SCT OUTPUTSET14: SETn5 Position */\r
-#define SCT_OUTPUTSET14_SETn5_Msk (0x01UL << SCT_OUTPUTSET14_SETn5_Pos) /*!< SCT OUTPUTSET14: SETn5 Mask */\r
-#define SCT_OUTPUTSET14_SETn6_Pos 6 /*!< SCT OUTPUTSET14: SETn6 Position */\r
-#define SCT_OUTPUTSET14_SETn6_Msk (0x01UL << SCT_OUTPUTSET14_SETn6_Pos) /*!< SCT OUTPUTSET14: SETn6 Mask */\r
-#define SCT_OUTPUTSET14_SETn7_Pos 7 /*!< SCT OUTPUTSET14: SETn7 Position */\r
-#define SCT_OUTPUTSET14_SETn7_Msk (0x01UL << SCT_OUTPUTSET14_SETn7_Pos) /*!< SCT OUTPUTSET14: SETn7 Mask */\r
-#define SCT_OUTPUTSET14_SETn8_Pos 8 /*!< SCT OUTPUTSET14: SETn8 Position */\r
-#define SCT_OUTPUTSET14_SETn8_Msk (0x01UL << SCT_OUTPUTSET14_SETn8_Pos) /*!< SCT OUTPUTSET14: SETn8 Mask */\r
-#define SCT_OUTPUTSET14_SETn9_Pos 9 /*!< SCT OUTPUTSET14: SETn9 Position */\r
-#define SCT_OUTPUTSET14_SETn9_Msk (0x01UL << SCT_OUTPUTSET14_SETn9_Pos) /*!< SCT OUTPUTSET14: SETn9 Mask */\r
-#define SCT_OUTPUTSET14_SETn10_Pos 10 /*!< SCT OUTPUTSET14: SETn10 Position */\r
-#define SCT_OUTPUTSET14_SETn10_Msk (0x01UL << SCT_OUTPUTSET14_SETn10_Pos) /*!< SCT OUTPUTSET14: SETn10 Mask */\r
-#define SCT_OUTPUTSET14_SETn11_Pos 11 /*!< SCT OUTPUTSET14: SETn11 Position */\r
-#define SCT_OUTPUTSET14_SETn11_Msk (0x01UL << SCT_OUTPUTSET14_SETn11_Pos) /*!< SCT OUTPUTSET14: SETn11 Mask */\r
-#define SCT_OUTPUTSET14_SETn12_Pos 12 /*!< SCT OUTPUTSET14: SETn12 Position */\r
-#define SCT_OUTPUTSET14_SETn12_Msk (0x01UL << SCT_OUTPUTSET14_SETn12_Pos) /*!< SCT OUTPUTSET14: SETn12 Mask */\r
-#define SCT_OUTPUTSET14_SETn13_Pos 13 /*!< SCT OUTPUTSET14: SETn13 Position */\r
-#define SCT_OUTPUTSET14_SETn13_Msk (0x01UL << SCT_OUTPUTSET14_SETn13_Pos) /*!< SCT OUTPUTSET14: SETn13 Mask */\r
-#define SCT_OUTPUTSET14_SETn14_Pos 14 /*!< SCT OUTPUTSET14: SETn14 Position */\r
-#define SCT_OUTPUTSET14_SETn14_Msk (0x01UL << SCT_OUTPUTSET14_SETn14_Pos) /*!< SCT OUTPUTSET14: SETn14 Mask */\r
-#define SCT_OUTPUTSET14_SETn15_Pos 15 /*!< SCT OUTPUTSET14: SETn15 Position */\r
-#define SCT_OUTPUTSET14_SETn15_Msk (0x01UL << SCT_OUTPUTSET14_SETn15_Pos) /*!< SCT OUTPUTSET14: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR14 ----------------------------------------\r
-#define SCT_OUTPUTCLR14_CLRn0_Pos 0 /*!< SCT OUTPUTCLR14: CLRn0 Position */\r
-#define SCT_OUTPUTCLR14_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos) /*!< SCT OUTPUTCLR14: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn1_Pos 1 /*!< SCT OUTPUTCLR14: CLRn1 Position */\r
-#define SCT_OUTPUTCLR14_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos) /*!< SCT OUTPUTCLR14: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn2_Pos 2 /*!< SCT OUTPUTCLR14: CLRn2 Position */\r
-#define SCT_OUTPUTCLR14_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos) /*!< SCT OUTPUTCLR14: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn3_Pos 3 /*!< SCT OUTPUTCLR14: CLRn3 Position */\r
-#define SCT_OUTPUTCLR14_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos) /*!< SCT OUTPUTCLR14: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn4_Pos 4 /*!< SCT OUTPUTCLR14: CLRn4 Position */\r
-#define SCT_OUTPUTCLR14_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos) /*!< SCT OUTPUTCLR14: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn5_Pos 5 /*!< SCT OUTPUTCLR14: CLRn5 Position */\r
-#define SCT_OUTPUTCLR14_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos) /*!< SCT OUTPUTCLR14: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn6_Pos 6 /*!< SCT OUTPUTCLR14: CLRn6 Position */\r
-#define SCT_OUTPUTCLR14_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos) /*!< SCT OUTPUTCLR14: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn7_Pos 7 /*!< SCT OUTPUTCLR14: CLRn7 Position */\r
-#define SCT_OUTPUTCLR14_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos) /*!< SCT OUTPUTCLR14: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn8_Pos 8 /*!< SCT OUTPUTCLR14: CLRn8 Position */\r
-#define SCT_OUTPUTCLR14_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos) /*!< SCT OUTPUTCLR14: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn9_Pos 9 /*!< SCT OUTPUTCLR14: CLRn9 Position */\r
-#define SCT_OUTPUTCLR14_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos) /*!< SCT OUTPUTCLR14: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn10_Pos 10 /*!< SCT OUTPUTCLR14: CLRn10 Position */\r
-#define SCT_OUTPUTCLR14_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos) /*!< SCT OUTPUTCLR14: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn11_Pos 11 /*!< SCT OUTPUTCLR14: CLRn11 Position */\r
-#define SCT_OUTPUTCLR14_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos) /*!< SCT OUTPUTCLR14: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn12_Pos 12 /*!< SCT OUTPUTCLR14: CLRn12 Position */\r
-#define SCT_OUTPUTCLR14_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos) /*!< SCT OUTPUTCLR14: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn13_Pos 13 /*!< SCT OUTPUTCLR14: CLRn13 Position */\r
-#define SCT_OUTPUTCLR14_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos) /*!< SCT OUTPUTCLR14: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn14_Pos 14 /*!< SCT OUTPUTCLR14: CLRn14 Position */\r
-#define SCT_OUTPUTCLR14_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos) /*!< SCT OUTPUTCLR14: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR14_CLRn15_Pos 15 /*!< SCT OUTPUTCLR14: CLRn15 Position */\r
-#define SCT_OUTPUTCLR14_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos) /*!< SCT OUTPUTCLR14: CLRn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTSET15 ----------------------------------------\r
-#define SCT_OUTPUTSET15_SETn0_Pos 0 /*!< SCT OUTPUTSET15: SETn0 Position */\r
-#define SCT_OUTPUTSET15_SETn0_Msk (0x01UL << SCT_OUTPUTSET15_SETn0_Pos) /*!< SCT OUTPUTSET15: SETn0 Mask */\r
-#define SCT_OUTPUTSET15_SETn1_Pos 1 /*!< SCT OUTPUTSET15: SETn1 Position */\r
-#define SCT_OUTPUTSET15_SETn1_Msk (0x01UL << SCT_OUTPUTSET15_SETn1_Pos) /*!< SCT OUTPUTSET15: SETn1 Mask */\r
-#define SCT_OUTPUTSET15_SETn2_Pos 2 /*!< SCT OUTPUTSET15: SETn2 Position */\r
-#define SCT_OUTPUTSET15_SETn2_Msk (0x01UL << SCT_OUTPUTSET15_SETn2_Pos) /*!< SCT OUTPUTSET15: SETn2 Mask */\r
-#define SCT_OUTPUTSET15_SETn3_Pos 3 /*!< SCT OUTPUTSET15: SETn3 Position */\r
-#define SCT_OUTPUTSET15_SETn3_Msk (0x01UL << SCT_OUTPUTSET15_SETn3_Pos) /*!< SCT OUTPUTSET15: SETn3 Mask */\r
-#define SCT_OUTPUTSET15_SETn4_Pos 4 /*!< SCT OUTPUTSET15: SETn4 Position */\r
-#define SCT_OUTPUTSET15_SETn4_Msk (0x01UL << SCT_OUTPUTSET15_SETn4_Pos) /*!< SCT OUTPUTSET15: SETn4 Mask */\r
-#define SCT_OUTPUTSET15_SETn5_Pos 5 /*!< SCT OUTPUTSET15: SETn5 Position */\r
-#define SCT_OUTPUTSET15_SETn5_Msk (0x01UL << SCT_OUTPUTSET15_SETn5_Pos) /*!< SCT OUTPUTSET15: SETn5 Mask */\r
-#define SCT_OUTPUTSET15_SETn6_Pos 6 /*!< SCT OUTPUTSET15: SETn6 Position */\r
-#define SCT_OUTPUTSET15_SETn6_Msk (0x01UL << SCT_OUTPUTSET15_SETn6_Pos) /*!< SCT OUTPUTSET15: SETn6 Mask */\r
-#define SCT_OUTPUTSET15_SETn7_Pos 7 /*!< SCT OUTPUTSET15: SETn7 Position */\r
-#define SCT_OUTPUTSET15_SETn7_Msk (0x01UL << SCT_OUTPUTSET15_SETn7_Pos) /*!< SCT OUTPUTSET15: SETn7 Mask */\r
-#define SCT_OUTPUTSET15_SETn8_Pos 8 /*!< SCT OUTPUTSET15: SETn8 Position */\r
-#define SCT_OUTPUTSET15_SETn8_Msk (0x01UL << SCT_OUTPUTSET15_SETn8_Pos) /*!< SCT OUTPUTSET15: SETn8 Mask */\r
-#define SCT_OUTPUTSET15_SETn9_Pos 9 /*!< SCT OUTPUTSET15: SETn9 Position */\r
-#define SCT_OUTPUTSET15_SETn9_Msk (0x01UL << SCT_OUTPUTSET15_SETn9_Pos) /*!< SCT OUTPUTSET15: SETn9 Mask */\r
-#define SCT_OUTPUTSET15_SETn10_Pos 10 /*!< SCT OUTPUTSET15: SETn10 Position */\r
-#define SCT_OUTPUTSET15_SETn10_Msk (0x01UL << SCT_OUTPUTSET15_SETn10_Pos) /*!< SCT OUTPUTSET15: SETn10 Mask */\r
-#define SCT_OUTPUTSET15_SETn11_Pos 11 /*!< SCT OUTPUTSET15: SETn11 Position */\r
-#define SCT_OUTPUTSET15_SETn11_Msk (0x01UL << SCT_OUTPUTSET15_SETn11_Pos) /*!< SCT OUTPUTSET15: SETn11 Mask */\r
-#define SCT_OUTPUTSET15_SETn12_Pos 12 /*!< SCT OUTPUTSET15: SETn12 Position */\r
-#define SCT_OUTPUTSET15_SETn12_Msk (0x01UL << SCT_OUTPUTSET15_SETn12_Pos) /*!< SCT OUTPUTSET15: SETn12 Mask */\r
-#define SCT_OUTPUTSET15_SETn13_Pos 13 /*!< SCT OUTPUTSET15: SETn13 Position */\r
-#define SCT_OUTPUTSET15_SETn13_Msk (0x01UL << SCT_OUTPUTSET15_SETn13_Pos) /*!< SCT OUTPUTSET15: SETn13 Mask */\r
-#define SCT_OUTPUTSET15_SETn14_Pos 14 /*!< SCT OUTPUTSET15: SETn14 Position */\r
-#define SCT_OUTPUTSET15_SETn14_Msk (0x01UL << SCT_OUTPUTSET15_SETn14_Pos) /*!< SCT OUTPUTSET15: SETn14 Mask */\r
-#define SCT_OUTPUTSET15_SETn15_Pos 15 /*!< SCT OUTPUTSET15: SETn15 Position */\r
-#define SCT_OUTPUTSET15_SETn15_Msk (0x01UL << SCT_OUTPUTSET15_SETn15_Pos) /*!< SCT OUTPUTSET15: SETn15 Mask */\r
-\r
-// ------------------------------------- SCT_OUTPUTCLR15 ----------------------------------------\r
-#define SCT_OUTPUTCLR15_CLRn0_Pos 0 /*!< SCT OUTPUTCLR15: CLRn0 Position */\r
-#define SCT_OUTPUTCLR15_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos) /*!< SCT OUTPUTCLR15: CLRn0 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn1_Pos 1 /*!< SCT OUTPUTCLR15: CLRn1 Position */\r
-#define SCT_OUTPUTCLR15_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos) /*!< SCT OUTPUTCLR15: CLRn1 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn2_Pos 2 /*!< SCT OUTPUTCLR15: CLRn2 Position */\r
-#define SCT_OUTPUTCLR15_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos) /*!< SCT OUTPUTCLR15: CLRn2 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn3_Pos 3 /*!< SCT OUTPUTCLR15: CLRn3 Position */\r
-#define SCT_OUTPUTCLR15_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos) /*!< SCT OUTPUTCLR15: CLRn3 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn4_Pos 4 /*!< SCT OUTPUTCLR15: CLRn4 Position */\r
-#define SCT_OUTPUTCLR15_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos) /*!< SCT OUTPUTCLR15: CLRn4 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn5_Pos 5 /*!< SCT OUTPUTCLR15: CLRn5 Position */\r
-#define SCT_OUTPUTCLR15_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos) /*!< SCT OUTPUTCLR15: CLRn5 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn6_Pos 6 /*!< SCT OUTPUTCLR15: CLRn6 Position */\r
-#define SCT_OUTPUTCLR15_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos) /*!< SCT OUTPUTCLR15: CLRn6 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn7_Pos 7 /*!< SCT OUTPUTCLR15: CLRn7 Position */\r
-#define SCT_OUTPUTCLR15_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos) /*!< SCT OUTPUTCLR15: CLRn7 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn8_Pos 8 /*!< SCT OUTPUTCLR15: CLRn8 Position */\r
-#define SCT_OUTPUTCLR15_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos) /*!< SCT OUTPUTCLR15: CLRn8 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn9_Pos 9 /*!< SCT OUTPUTCLR15: CLRn9 Position */\r
-#define SCT_OUTPUTCLR15_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos) /*!< SCT OUTPUTCLR15: CLRn9 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn10_Pos 10 /*!< SCT OUTPUTCLR15: CLRn10 Position */\r
-#define SCT_OUTPUTCLR15_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos) /*!< SCT OUTPUTCLR15: CLRn10 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn11_Pos 11 /*!< SCT OUTPUTCLR15: CLRn11 Position */\r
-#define SCT_OUTPUTCLR15_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos) /*!< SCT OUTPUTCLR15: CLRn11 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn12_Pos 12 /*!< SCT OUTPUTCLR15: CLRn12 Position */\r
-#define SCT_OUTPUTCLR15_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos) /*!< SCT OUTPUTCLR15: CLRn12 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn13_Pos 13 /*!< SCT OUTPUTCLR15: CLRn13 Position */\r
-#define SCT_OUTPUTCLR15_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos) /*!< SCT OUTPUTCLR15: CLRn13 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn14_Pos 14 /*!< SCT OUTPUTCLR15: CLRn14 Position */\r
-#define SCT_OUTPUTCLR15_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos) /*!< SCT OUTPUTCLR15: CLRn14 Mask */\r
-#define SCT_OUTPUTCLR15_CLRn15_Pos 15 /*!< SCT OUTPUTCLR15: CLRn15 Position */\r
-#define SCT_OUTPUTCLR15_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos) /*!< SCT OUTPUTCLR15: CLRn15 Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GPDMA Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// -------------------------------------- GPDMA_INTSTAT -----------------------------------------\r
-#define GPDMA_INTSTAT_INTSTAT0_Pos 0 /*!< GPDMA INTSTAT: INTSTAT0 Position */\r
-#define GPDMA_INTSTAT_INTSTAT0_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos) /*!< GPDMA INTSTAT: INTSTAT0 Mask */\r
-#define GPDMA_INTSTAT_INTSTAT1_Pos 1 /*!< GPDMA INTSTAT: INTSTAT1 Position */\r
-#define GPDMA_INTSTAT_INTSTAT1_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos) /*!< GPDMA INTSTAT: INTSTAT1 Mask */\r
-#define GPDMA_INTSTAT_INTSTAT2_Pos 2 /*!< GPDMA INTSTAT: INTSTAT2 Position */\r
-#define GPDMA_INTSTAT_INTSTAT2_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos) /*!< GPDMA INTSTAT: INTSTAT2 Mask */\r
-#define GPDMA_INTSTAT_INTSTAT3_Pos 3 /*!< GPDMA INTSTAT: INTSTAT3 Position */\r
-#define GPDMA_INTSTAT_INTSTAT3_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos) /*!< GPDMA INTSTAT: INTSTAT3 Mask */\r
-#define GPDMA_INTSTAT_INTSTAT4_Pos 4 /*!< GPDMA INTSTAT: INTSTAT4 Position */\r
-#define GPDMA_INTSTAT_INTSTAT4_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos) /*!< GPDMA INTSTAT: INTSTAT4 Mask */\r
-#define GPDMA_INTSTAT_INTSTAT5_Pos 5 /*!< GPDMA INTSTAT: INTSTAT5 Position */\r
-#define GPDMA_INTSTAT_INTSTAT5_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos) /*!< GPDMA INTSTAT: INTSTAT5 Mask */\r
-#define GPDMA_INTSTAT_INTSTAT6_Pos 6 /*!< GPDMA INTSTAT: INTSTAT6 Position */\r
-#define GPDMA_INTSTAT_INTSTAT6_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos) /*!< GPDMA INTSTAT: INTSTAT6 Mask */\r
-#define GPDMA_INTSTAT_INTSTAT7_Pos 7 /*!< GPDMA INTSTAT: INTSTAT7 Position */\r
-#define GPDMA_INTSTAT_INTSTAT7_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos) /*!< GPDMA INTSTAT: INTSTAT7 Mask */\r
-\r
-// ------------------------------------- GPDMA_INTTCSTAT ----------------------------------------\r
-#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos 0 /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos 1 /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos 2 /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos 3 /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos 4 /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos 5 /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos 6 /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos 7 /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */\r
-#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask */\r
-\r
-// ------------------------------------ GPDMA_INTTCCLEAR ----------------------------------------\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos 0 /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos 1 /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos 2 /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos 3 /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos 4 /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos 5 /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos 6 /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos 7 /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */\r
-#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask */\r
-\r
-// ------------------------------------ GPDMA_INTERRSTAT ----------------------------------------\r
-#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos 0 /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos 1 /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos 2 /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos 3 /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos 4 /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos 5 /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos 6 /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos 7 /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */\r
-#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask */\r
-\r
-// ------------------------------------- GPDMA_INTERRCLR ----------------------------------------\r
-#define GPDMA_INTERRCLR_INTERRCLR0_Pos 0 /*!< GPDMA INTERRCLR: INTERRCLR0 Position */\r
-#define GPDMA_INTERRCLR_INTERRCLR0_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos) /*!< GPDMA INTERRCLR: INTERRCLR0 Mask */\r
-#define GPDMA_INTERRCLR_INTERRCLR1_Pos 1 /*!< GPDMA INTERRCLR: INTERRCLR1 Position */\r
-#define GPDMA_INTERRCLR_INTERRCLR1_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos) /*!< GPDMA INTERRCLR: INTERRCLR1 Mask */\r
-#define GPDMA_INTERRCLR_INTERRCLR2_Pos 2 /*!< GPDMA INTERRCLR: INTERRCLR2 Position */\r
-#define GPDMA_INTERRCLR_INTERRCLR2_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos) /*!< GPDMA INTERRCLR: INTERRCLR2 Mask */\r
-#define GPDMA_INTERRCLR_INTERRCLR3_Pos 3 /*!< GPDMA INTERRCLR: INTERRCLR3 Position */\r
-#define GPDMA_INTERRCLR_INTERRCLR3_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos) /*!< GPDMA INTERRCLR: INTERRCLR3 Mask */\r
-#define GPDMA_INTERRCLR_INTERRCLR4_Pos 4 /*!< GPDMA INTERRCLR: INTERRCLR4 Position */\r
-#define GPDMA_INTERRCLR_INTERRCLR4_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos) /*!< GPDMA INTERRCLR: INTERRCLR4 Mask */\r
-#define GPDMA_INTERRCLR_INTERRCLR5_Pos 5 /*!< GPDMA INTERRCLR: INTERRCLR5 Position */\r
-#define GPDMA_INTERRCLR_INTERRCLR5_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos) /*!< GPDMA INTERRCLR: INTERRCLR5 Mask */\r
-#define GPDMA_INTERRCLR_INTERRCLR6_Pos 6 /*!< GPDMA INTERRCLR: INTERRCLR6 Position */\r
-#define GPDMA_INTERRCLR_INTERRCLR6_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos) /*!< GPDMA INTERRCLR: INTERRCLR6 Mask */\r
-#define GPDMA_INTERRCLR_INTERRCLR7_Pos 7 /*!< GPDMA INTERRCLR: INTERRCLR7 Position */\r
-#define GPDMA_INTERRCLR_INTERRCLR7_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos) /*!< GPDMA INTERRCLR: INTERRCLR7 Mask */\r
-\r
-// ----------------------------------- GPDMA_RAWINTTCSTAT ---------------------------------------\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos 0 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos 1 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos 2 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos 3 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos 4 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos 5 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos 6 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos 7 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */\r
-#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */\r
-\r
-// ----------------------------------- GPDMA_RAWINTERRSTAT --------------------------------------\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos 0 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos 1 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos 2 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos 3 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos 4 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos 5 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos 6 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos 7 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */\r
-#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */\r
-\r
-// ------------------------------------- GPDMA_ENBLDCHNS ----------------------------------------\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos 0 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos 1 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos 2 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos 3 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos 4 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos 5 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos 6 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos 7 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */\r
-#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */\r
-\r
-// ------------------------------------- GPDMA_SOFTBREQ -----------------------------------------\r
-#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos 0 /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos 1 /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos 2 /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos 3 /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos 4 /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos 5 /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos 6 /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos 7 /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos 8 /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos 9 /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos 10 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos 11 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos 12 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos 13 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos 14 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos 15 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */\r
-#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask */\r
-\r
-// ------------------------------------- GPDMA_SOFTSREQ -----------------------------------------\r
-#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos 0 /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos 1 /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos 2 /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos 3 /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos 4 /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos 5 /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos 6 /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos 7 /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos 8 /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos 9 /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos 10 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos 11 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos 12 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos 13 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos 14 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos 15 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */\r
-#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask */\r
-\r
-// ------------------------------------- GPDMA_SOFTLBREQ ----------------------------------------\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos 0 /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos 1 /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos 2 /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos 3 /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos 4 /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos 5 /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos 6 /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos 7 /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos 8 /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos 9 /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos 10 /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos 11 /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos 12 /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos 13 /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos 14 /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos 15 /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */\r
-#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask */\r
-\r
-// ------------------------------------- GPDMA_SOFTLSREQ ----------------------------------------\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos 0 /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos 1 /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos 2 /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos 3 /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos 4 /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos 5 /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos 6 /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos 7 /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos 8 /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos 9 /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos 10 /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos 11 /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos 12 /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos 13 /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos 14 /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos 15 /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */\r
-#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask */\r
-\r
-// -------------------------------------- GPDMA_CONFIG ------------------------------------------\r
-#define GPDMA_CONFIG_E_Pos 0 /*!< GPDMA CONFIG: E Position */\r
-#define GPDMA_CONFIG_E_Msk (0x01UL << GPDMA_CONFIG_E_Pos) /*!< GPDMA CONFIG: E Mask */\r
-#define GPDMA_CONFIG_M0_Pos 1 /*!< GPDMA CONFIG: M0 Position */\r
-#define GPDMA_CONFIG_M0_Msk (0x01UL << GPDMA_CONFIG_M0_Pos) /*!< GPDMA CONFIG: M0 Mask */\r
-#define GPDMA_CONFIG_M1_Pos 2 /*!< GPDMA CONFIG: M1 Position */\r
-#define GPDMA_CONFIG_M1_Msk (0x01UL << GPDMA_CONFIG_M1_Pos) /*!< GPDMA CONFIG: M1 Mask */\r
-\r
-// --------------------------------------- GPDMA_SYNC -------------------------------------------\r
-#define GPDMA_SYNC_DMACSYNC0_Pos 0 /*!< GPDMA SYNC: DMACSYNC0 Position */\r
-#define GPDMA_SYNC_DMACSYNC0_Msk (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos) /*!< GPDMA SYNC: DMACSYNC0 Mask */\r
-#define GPDMA_SYNC_DMACSYNC1_Pos 1 /*!< GPDMA SYNC: DMACSYNC1 Position */\r
-#define GPDMA_SYNC_DMACSYNC1_Msk (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos) /*!< GPDMA SYNC: DMACSYNC1 Mask */\r
-#define GPDMA_SYNC_DMACSYNC2_Pos 2 /*!< GPDMA SYNC: DMACSYNC2 Position */\r
-#define GPDMA_SYNC_DMACSYNC2_Msk (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos) /*!< GPDMA SYNC: DMACSYNC2 Mask */\r
-#define GPDMA_SYNC_DMACSYNC3_Pos 3 /*!< GPDMA SYNC: DMACSYNC3 Position */\r
-#define GPDMA_SYNC_DMACSYNC3_Msk (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos) /*!< GPDMA SYNC: DMACSYNC3 Mask */\r
-#define GPDMA_SYNC_DMACSYNC4_Pos 4 /*!< GPDMA SYNC: DMACSYNC4 Position */\r
-#define GPDMA_SYNC_DMACSYNC4_Msk (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos) /*!< GPDMA SYNC: DMACSYNC4 Mask */\r
-#define GPDMA_SYNC_DMACSYNC5_Pos 5 /*!< GPDMA SYNC: DMACSYNC5 Position */\r
-#define GPDMA_SYNC_DMACSYNC5_Msk (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos) /*!< GPDMA SYNC: DMACSYNC5 Mask */\r
-#define GPDMA_SYNC_DMACSYNC6_Pos 6 /*!< GPDMA SYNC: DMACSYNC6 Position */\r
-#define GPDMA_SYNC_DMACSYNC6_Msk (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos) /*!< GPDMA SYNC: DMACSYNC6 Mask */\r
-#define GPDMA_SYNC_DMACSYNC7_Pos 7 /*!< GPDMA SYNC: DMACSYNC7 Position */\r
-#define GPDMA_SYNC_DMACSYNC7_Msk (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos) /*!< GPDMA SYNC: DMACSYNC7 Mask */\r
-#define GPDMA_SYNC_DMACSYNC8_Pos 8 /*!< GPDMA SYNC: DMACSYNC8 Position */\r
-#define GPDMA_SYNC_DMACSYNC8_Msk (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos) /*!< GPDMA SYNC: DMACSYNC8 Mask */\r
-#define GPDMA_SYNC_DMACSYNC9_Pos 9 /*!< GPDMA SYNC: DMACSYNC9 Position */\r
-#define GPDMA_SYNC_DMACSYNC9_Msk (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos) /*!< GPDMA SYNC: DMACSYNC9 Mask */\r
-#define GPDMA_SYNC_DMACSYNC10_Pos 10 /*!< GPDMA SYNC: DMACSYNC10 Position */\r
-#define GPDMA_SYNC_DMACSYNC10_Msk (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos) /*!< GPDMA SYNC: DMACSYNC10 Mask */\r
-#define GPDMA_SYNC_DMACSYNC11_Pos 11 /*!< GPDMA SYNC: DMACSYNC11 Position */\r
-#define GPDMA_SYNC_DMACSYNC11_Msk (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos) /*!< GPDMA SYNC: DMACSYNC11 Mask */\r
-#define GPDMA_SYNC_DMACSYNC12_Pos 12 /*!< GPDMA SYNC: DMACSYNC12 Position */\r
-#define GPDMA_SYNC_DMACSYNC12_Msk (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos) /*!< GPDMA SYNC: DMACSYNC12 Mask */\r
-#define GPDMA_SYNC_DMACSYNC13_Pos 13 /*!< GPDMA SYNC: DMACSYNC13 Position */\r
-#define GPDMA_SYNC_DMACSYNC13_Msk (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos) /*!< GPDMA SYNC: DMACSYNC13 Mask */\r
-#define GPDMA_SYNC_DMACSYNC14_Pos 14 /*!< GPDMA SYNC: DMACSYNC14 Position */\r
-#define GPDMA_SYNC_DMACSYNC14_Msk (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos) /*!< GPDMA SYNC: DMACSYNC14 Mask */\r
-#define GPDMA_SYNC_DMACSYNC15_Pos 15 /*!< GPDMA SYNC: DMACSYNC15 Position */\r
-#define GPDMA_SYNC_DMACSYNC15_Msk (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos) /*!< GPDMA SYNC: DMACSYNC15 Mask */\r
-\r
-// ------------------------------------- GPDMA_C0SRCADDR ----------------------------------------\r
-#define GPDMA_C0SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C0SRCADDR: SRCADDR Position */\r
-#define GPDMA_C0SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos) /*!< GPDMA C0SRCADDR: SRCADDR Mask */\r
-\r
-// ------------------------------------ GPDMA_C0DESTADDR ----------------------------------------\r
-#define GPDMA_C0DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C0DESTADDR: DESTADDR Position */\r
-#define GPDMA_C0DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos) /*!< GPDMA C0DESTADDR: DESTADDR Mask */\r
-\r
-// --------------------------------------- GPDMA_C0LLI ------------------------------------------\r
-#define GPDMA_C0LLI_LM_Pos 0 /*!< GPDMA C0LLI: LM Position */\r
-#define GPDMA_C0LLI_LM_Msk (0x01UL << GPDMA_C0LLI_LM_Pos) /*!< GPDMA C0LLI: LM Mask */\r
-#define GPDMA_C0LLI_R_Pos 1 /*!< GPDMA C0LLI: R Position */\r
-#define GPDMA_C0LLI_R_Msk (0x01UL << GPDMA_C0LLI_R_Pos) /*!< GPDMA C0LLI: R Mask */\r
-#define GPDMA_C0LLI_LLI_Pos 2 /*!< GPDMA C0LLI: LLI Position */\r
-#define GPDMA_C0LLI_LLI_Msk (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos) /*!< GPDMA C0LLI: LLI Mask */\r
-\r
-// ------------------------------------- GPDMA_C0CONTROL ----------------------------------------\r
-#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */\r
-#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask */\r
-#define GPDMA_C0CONTROL_SBSIZE_Pos 12 /*!< GPDMA C0CONTROL: SBSIZE Position */\r
-#define GPDMA_C0CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos) /*!< GPDMA C0CONTROL: SBSIZE Mask */\r
-#define GPDMA_C0CONTROL_DBSIZE_Pos 15 /*!< GPDMA C0CONTROL: DBSIZE Position */\r
-#define GPDMA_C0CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos) /*!< GPDMA C0CONTROL: DBSIZE Mask */\r
-#define GPDMA_C0CONTROL_SWIDTH_Pos 18 /*!< GPDMA C0CONTROL: SWIDTH Position */\r
-#define GPDMA_C0CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos) /*!< GPDMA C0CONTROL: SWIDTH Mask */\r
-#define GPDMA_C0CONTROL_DWIDTH_Pos 21 /*!< GPDMA C0CONTROL: DWIDTH Position */\r
-#define GPDMA_C0CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos) /*!< GPDMA C0CONTROL: DWIDTH Mask */\r
-#define GPDMA_C0CONTROL_S_Pos 24 /*!< GPDMA C0CONTROL: S Position */\r
-#define GPDMA_C0CONTROL_S_Msk (0x01UL << GPDMA_C0CONTROL_S_Pos) /*!< GPDMA C0CONTROL: S Mask */\r
-#define GPDMA_C0CONTROL_D_Pos 25 /*!< GPDMA C0CONTROL: D Position */\r
-#define GPDMA_C0CONTROL_D_Msk (0x01UL << GPDMA_C0CONTROL_D_Pos) /*!< GPDMA C0CONTROL: D Mask */\r
-#define GPDMA_C0CONTROL_SI_Pos 26 /*!< GPDMA C0CONTROL: SI Position */\r
-#define GPDMA_C0CONTROL_SI_Msk (0x01UL << GPDMA_C0CONTROL_SI_Pos) /*!< GPDMA C0CONTROL: SI Mask */\r
-#define GPDMA_C0CONTROL_DI_Pos 27 /*!< GPDMA C0CONTROL: DI Position */\r
-#define GPDMA_C0CONTROL_DI_Msk (0x01UL << GPDMA_C0CONTROL_DI_Pos) /*!< GPDMA C0CONTROL: DI Mask */\r
-#define GPDMA_C0CONTROL_PROT1_Pos 28 /*!< GPDMA C0CONTROL: PROT1 Position */\r
-#define GPDMA_C0CONTROL_PROT1_Msk (0x01UL << GPDMA_C0CONTROL_PROT1_Pos) /*!< GPDMA C0CONTROL: PROT1 Mask */\r
-#define GPDMA_C0CONTROL_PROT2_Pos 29 /*!< GPDMA C0CONTROL: PROT2 Position */\r
-#define GPDMA_C0CONTROL_PROT2_Msk (0x01UL << GPDMA_C0CONTROL_PROT2_Pos) /*!< GPDMA C0CONTROL: PROT2 Mask */\r
-#define GPDMA_C0CONTROL_PROT3_Pos 30 /*!< GPDMA C0CONTROL: PROT3 Position */\r
-#define GPDMA_C0CONTROL_PROT3_Msk (0x01UL << GPDMA_C0CONTROL_PROT3_Pos) /*!< GPDMA C0CONTROL: PROT3 Mask */\r
-#define GPDMA_C0CONTROL_I_Pos 31 /*!< GPDMA C0CONTROL: I Position */\r
-#define GPDMA_C0CONTROL_I_Msk (0x01UL << GPDMA_C0CONTROL_I_Pos) /*!< GPDMA C0CONTROL: I Mask */\r
-\r
-// ------------------------------------- GPDMA_C0CONFIG -----------------------------------------\r
-#define GPDMA_C0CONFIG_E_Pos 0 /*!< GPDMA C0CONFIG: E Position */\r
-#define GPDMA_C0CONFIG_E_Msk (0x01UL << GPDMA_C0CONFIG_E_Pos) /*!< GPDMA C0CONFIG: E Mask */\r
-#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */\r
-#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask */\r
-#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */\r
-#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */\r
-#define GPDMA_C0CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C0CONFIG: FLOWCNTRL Position */\r
-#define GPDMA_C0CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C0CONFIG: FLOWCNTRL Mask */\r
-#define GPDMA_C0CONFIG_IE_Pos 14 /*!< GPDMA C0CONFIG: IE Position */\r
-#define GPDMA_C0CONFIG_IE_Msk (0x01UL << GPDMA_C0CONFIG_IE_Pos) /*!< GPDMA C0CONFIG: IE Mask */\r
-#define GPDMA_C0CONFIG_ITC_Pos 15 /*!< GPDMA C0CONFIG: ITC Position */\r
-#define GPDMA_C0CONFIG_ITC_Msk (0x01UL << GPDMA_C0CONFIG_ITC_Pos) /*!< GPDMA C0CONFIG: ITC Mask */\r
-#define GPDMA_C0CONFIG_L_Pos 16 /*!< GPDMA C0CONFIG: L Position */\r
-#define GPDMA_C0CONFIG_L_Msk (0x01UL << GPDMA_C0CONFIG_L_Pos) /*!< GPDMA C0CONFIG: L Mask */\r
-#define GPDMA_C0CONFIG_A_Pos 17 /*!< GPDMA C0CONFIG: A Position */\r
-#define GPDMA_C0CONFIG_A_Msk (0x01UL << GPDMA_C0CONFIG_A_Pos) /*!< GPDMA C0CONFIG: A Mask */\r
-#define GPDMA_C0CONFIG_H_Pos 18 /*!< GPDMA C0CONFIG: H Position */\r
-#define GPDMA_C0CONFIG_H_Msk (0x01UL << GPDMA_C0CONFIG_H_Pos) /*!< GPDMA C0CONFIG: H Mask */\r
-\r
-// ------------------------------------- GPDMA_C1SRCADDR ----------------------------------------\r
-#define GPDMA_C1SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C1SRCADDR: SRCADDR Position */\r
-#define GPDMA_C1SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos) /*!< GPDMA C1SRCADDR: SRCADDR Mask */\r
-\r
-// ------------------------------------ GPDMA_C1DESTADDR ----------------------------------------\r
-#define GPDMA_C1DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C1DESTADDR: DESTADDR Position */\r
-#define GPDMA_C1DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos) /*!< GPDMA C1DESTADDR: DESTADDR Mask */\r
-\r
-// --------------------------------------- GPDMA_C1LLI ------------------------------------------\r
-#define GPDMA_C1LLI_LM_Pos 0 /*!< GPDMA C1LLI: LM Position */\r
-#define GPDMA_C1LLI_LM_Msk (0x01UL << GPDMA_C1LLI_LM_Pos) /*!< GPDMA C1LLI: LM Mask */\r
-#define GPDMA_C1LLI_R_Pos 1 /*!< GPDMA C1LLI: R Position */\r
-#define GPDMA_C1LLI_R_Msk (0x01UL << GPDMA_C1LLI_R_Pos) /*!< GPDMA C1LLI: R Mask */\r
-#define GPDMA_C1LLI_LLI_Pos 2 /*!< GPDMA C1LLI: LLI Position */\r
-#define GPDMA_C1LLI_LLI_Msk (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos) /*!< GPDMA C1LLI: LLI Mask */\r
-\r
-// ------------------------------------- GPDMA_C1CONTROL ----------------------------------------\r
-#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */\r
-#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask */\r
-#define GPDMA_C1CONTROL_SBSIZE_Pos 12 /*!< GPDMA C1CONTROL: SBSIZE Position */\r
-#define GPDMA_C1CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos) /*!< GPDMA C1CONTROL: SBSIZE Mask */\r
-#define GPDMA_C1CONTROL_DBSIZE_Pos 15 /*!< GPDMA C1CONTROL: DBSIZE Position */\r
-#define GPDMA_C1CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos) /*!< GPDMA C1CONTROL: DBSIZE Mask */\r
-#define GPDMA_C1CONTROL_SWIDTH_Pos 18 /*!< GPDMA C1CONTROL: SWIDTH Position */\r
-#define GPDMA_C1CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos) /*!< GPDMA C1CONTROL: SWIDTH Mask */\r
-#define GPDMA_C1CONTROL_DWIDTH_Pos 21 /*!< GPDMA C1CONTROL: DWIDTH Position */\r
-#define GPDMA_C1CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos) /*!< GPDMA C1CONTROL: DWIDTH Mask */\r
-#define GPDMA_C1CONTROL_S_Pos 24 /*!< GPDMA C1CONTROL: S Position */\r
-#define GPDMA_C1CONTROL_S_Msk (0x01UL << GPDMA_C1CONTROL_S_Pos) /*!< GPDMA C1CONTROL: S Mask */\r
-#define GPDMA_C1CONTROL_D_Pos 25 /*!< GPDMA C1CONTROL: D Position */\r
-#define GPDMA_C1CONTROL_D_Msk (0x01UL << GPDMA_C1CONTROL_D_Pos) /*!< GPDMA C1CONTROL: D Mask */\r
-#define GPDMA_C1CONTROL_SI_Pos 26 /*!< GPDMA C1CONTROL: SI Position */\r
-#define GPDMA_C1CONTROL_SI_Msk (0x01UL << GPDMA_C1CONTROL_SI_Pos) /*!< GPDMA C1CONTROL: SI Mask */\r
-#define GPDMA_C1CONTROL_DI_Pos 27 /*!< GPDMA C1CONTROL: DI Position */\r
-#define GPDMA_C1CONTROL_DI_Msk (0x01UL << GPDMA_C1CONTROL_DI_Pos) /*!< GPDMA C1CONTROL: DI Mask */\r
-#define GPDMA_C1CONTROL_PROT1_Pos 28 /*!< GPDMA C1CONTROL: PROT1 Position */\r
-#define GPDMA_C1CONTROL_PROT1_Msk (0x01UL << GPDMA_C1CONTROL_PROT1_Pos) /*!< GPDMA C1CONTROL: PROT1 Mask */\r
-#define GPDMA_C1CONTROL_PROT2_Pos 29 /*!< GPDMA C1CONTROL: PROT2 Position */\r
-#define GPDMA_C1CONTROL_PROT2_Msk (0x01UL << GPDMA_C1CONTROL_PROT2_Pos) /*!< GPDMA C1CONTROL: PROT2 Mask */\r
-#define GPDMA_C1CONTROL_PROT3_Pos 30 /*!< GPDMA C1CONTROL: PROT3 Position */\r
-#define GPDMA_C1CONTROL_PROT3_Msk (0x01UL << GPDMA_C1CONTROL_PROT3_Pos) /*!< GPDMA C1CONTROL: PROT3 Mask */\r
-#define GPDMA_C1CONTROL_I_Pos 31 /*!< GPDMA C1CONTROL: I Position */\r
-#define GPDMA_C1CONTROL_I_Msk (0x01UL << GPDMA_C1CONTROL_I_Pos) /*!< GPDMA C1CONTROL: I Mask */\r
-\r
-// ------------------------------------- GPDMA_C1CONFIG -----------------------------------------\r
-#define GPDMA_C1CONFIG_E_Pos 0 /*!< GPDMA C1CONFIG: E Position */\r
-#define GPDMA_C1CONFIG_E_Msk (0x01UL << GPDMA_C1CONFIG_E_Pos) /*!< GPDMA C1CONFIG: E Mask */\r
-#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */\r
-#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask */\r
-#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */\r
-#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */\r
-#define GPDMA_C1CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C1CONFIG: FLOWCNTRL Position */\r
-#define GPDMA_C1CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C1CONFIG: FLOWCNTRL Mask */\r
-#define GPDMA_C1CONFIG_IE_Pos 14 /*!< GPDMA C1CONFIG: IE Position */\r
-#define GPDMA_C1CONFIG_IE_Msk (0x01UL << GPDMA_C1CONFIG_IE_Pos) /*!< GPDMA C1CONFIG: IE Mask */\r
-#define GPDMA_C1CONFIG_ITC_Pos 15 /*!< GPDMA C1CONFIG: ITC Position */\r
-#define GPDMA_C1CONFIG_ITC_Msk (0x01UL << GPDMA_C1CONFIG_ITC_Pos) /*!< GPDMA C1CONFIG: ITC Mask */\r
-#define GPDMA_C1CONFIG_L_Pos 16 /*!< GPDMA C1CONFIG: L Position */\r
-#define GPDMA_C1CONFIG_L_Msk (0x01UL << GPDMA_C1CONFIG_L_Pos) /*!< GPDMA C1CONFIG: L Mask */\r
-#define GPDMA_C1CONFIG_A_Pos 17 /*!< GPDMA C1CONFIG: A Position */\r
-#define GPDMA_C1CONFIG_A_Msk (0x01UL << GPDMA_C1CONFIG_A_Pos) /*!< GPDMA C1CONFIG: A Mask */\r
-#define GPDMA_C1CONFIG_H_Pos 18 /*!< GPDMA C1CONFIG: H Position */\r
-#define GPDMA_C1CONFIG_H_Msk (0x01UL << GPDMA_C1CONFIG_H_Pos) /*!< GPDMA C1CONFIG: H Mask */\r
-\r
-// ------------------------------------- GPDMA_C2SRCADDR ----------------------------------------\r
-#define GPDMA_C2SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C2SRCADDR: SRCADDR Position */\r
-#define GPDMA_C2SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos) /*!< GPDMA C2SRCADDR: SRCADDR Mask */\r
-\r
-// ------------------------------------ GPDMA_C2DESTADDR ----------------------------------------\r
-#define GPDMA_C2DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C2DESTADDR: DESTADDR Position */\r
-#define GPDMA_C2DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos) /*!< GPDMA C2DESTADDR: DESTADDR Mask */\r
-\r
-// --------------------------------------- GPDMA_C2LLI ------------------------------------------\r
-#define GPDMA_C2LLI_LM_Pos 0 /*!< GPDMA C2LLI: LM Position */\r
-#define GPDMA_C2LLI_LM_Msk (0x01UL << GPDMA_C2LLI_LM_Pos) /*!< GPDMA C2LLI: LM Mask */\r
-#define GPDMA_C2LLI_R_Pos 1 /*!< GPDMA C2LLI: R Position */\r
-#define GPDMA_C2LLI_R_Msk (0x01UL << GPDMA_C2LLI_R_Pos) /*!< GPDMA C2LLI: R Mask */\r
-#define GPDMA_C2LLI_LLI_Pos 2 /*!< GPDMA C2LLI: LLI Position */\r
-#define GPDMA_C2LLI_LLI_Msk (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos) /*!< GPDMA C2LLI: LLI Mask */\r
-\r
-// ------------------------------------- GPDMA_C2CONTROL ----------------------------------------\r
-#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */\r
-#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask */\r
-#define GPDMA_C2CONTROL_SBSIZE_Pos 12 /*!< GPDMA C2CONTROL: SBSIZE Position */\r
-#define GPDMA_C2CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos) /*!< GPDMA C2CONTROL: SBSIZE Mask */\r
-#define GPDMA_C2CONTROL_DBSIZE_Pos 15 /*!< GPDMA C2CONTROL: DBSIZE Position */\r
-#define GPDMA_C2CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos) /*!< GPDMA C2CONTROL: DBSIZE Mask */\r
-#define GPDMA_C2CONTROL_SWIDTH_Pos 18 /*!< GPDMA C2CONTROL: SWIDTH Position */\r
-#define GPDMA_C2CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos) /*!< GPDMA C2CONTROL: SWIDTH Mask */\r
-#define GPDMA_C2CONTROL_DWIDTH_Pos 21 /*!< GPDMA C2CONTROL: DWIDTH Position */\r
-#define GPDMA_C2CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos) /*!< GPDMA C2CONTROL: DWIDTH Mask */\r
-#define GPDMA_C2CONTROL_S_Pos 24 /*!< GPDMA C2CONTROL: S Position */\r
-#define GPDMA_C2CONTROL_S_Msk (0x01UL << GPDMA_C2CONTROL_S_Pos) /*!< GPDMA C2CONTROL: S Mask */\r
-#define GPDMA_C2CONTROL_D_Pos 25 /*!< GPDMA C2CONTROL: D Position */\r
-#define GPDMA_C2CONTROL_D_Msk (0x01UL << GPDMA_C2CONTROL_D_Pos) /*!< GPDMA C2CONTROL: D Mask */\r
-#define GPDMA_C2CONTROL_SI_Pos 26 /*!< GPDMA C2CONTROL: SI Position */\r
-#define GPDMA_C2CONTROL_SI_Msk (0x01UL << GPDMA_C2CONTROL_SI_Pos) /*!< GPDMA C2CONTROL: SI Mask */\r
-#define GPDMA_C2CONTROL_DI_Pos 27 /*!< GPDMA C2CONTROL: DI Position */\r
-#define GPDMA_C2CONTROL_DI_Msk (0x01UL << GPDMA_C2CONTROL_DI_Pos) /*!< GPDMA C2CONTROL: DI Mask */\r
-#define GPDMA_C2CONTROL_PROT1_Pos 28 /*!< GPDMA C2CONTROL: PROT1 Position */\r
-#define GPDMA_C2CONTROL_PROT1_Msk (0x01UL << GPDMA_C2CONTROL_PROT1_Pos) /*!< GPDMA C2CONTROL: PROT1 Mask */\r
-#define GPDMA_C2CONTROL_PROT2_Pos 29 /*!< GPDMA C2CONTROL: PROT2 Position */\r
-#define GPDMA_C2CONTROL_PROT2_Msk (0x01UL << GPDMA_C2CONTROL_PROT2_Pos) /*!< GPDMA C2CONTROL: PROT2 Mask */\r
-#define GPDMA_C2CONTROL_PROT3_Pos 30 /*!< GPDMA C2CONTROL: PROT3 Position */\r
-#define GPDMA_C2CONTROL_PROT3_Msk (0x01UL << GPDMA_C2CONTROL_PROT3_Pos) /*!< GPDMA C2CONTROL: PROT3 Mask */\r
-#define GPDMA_C2CONTROL_I_Pos 31 /*!< GPDMA C2CONTROL: I Position */\r
-#define GPDMA_C2CONTROL_I_Msk (0x01UL << GPDMA_C2CONTROL_I_Pos) /*!< GPDMA C2CONTROL: I Mask */\r
-\r
-// ------------------------------------- GPDMA_C2CONFIG -----------------------------------------\r
-#define GPDMA_C2CONFIG_E_Pos 0 /*!< GPDMA C2CONFIG: E Position */\r
-#define GPDMA_C2CONFIG_E_Msk (0x01UL << GPDMA_C2CONFIG_E_Pos) /*!< GPDMA C2CONFIG: E Mask */\r
-#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */\r
-#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask */\r
-#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */\r
-#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */\r
-#define GPDMA_C2CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C2CONFIG: FLOWCNTRL Position */\r
-#define GPDMA_C2CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C2CONFIG: FLOWCNTRL Mask */\r
-#define GPDMA_C2CONFIG_IE_Pos 14 /*!< GPDMA C2CONFIG: IE Position */\r
-#define GPDMA_C2CONFIG_IE_Msk (0x01UL << GPDMA_C2CONFIG_IE_Pos) /*!< GPDMA C2CONFIG: IE Mask */\r
-#define GPDMA_C2CONFIG_ITC_Pos 15 /*!< GPDMA C2CONFIG: ITC Position */\r
-#define GPDMA_C2CONFIG_ITC_Msk (0x01UL << GPDMA_C2CONFIG_ITC_Pos) /*!< GPDMA C2CONFIG: ITC Mask */\r
-#define GPDMA_C2CONFIG_L_Pos 16 /*!< GPDMA C2CONFIG: L Position */\r
-#define GPDMA_C2CONFIG_L_Msk (0x01UL << GPDMA_C2CONFIG_L_Pos) /*!< GPDMA C2CONFIG: L Mask */\r
-#define GPDMA_C2CONFIG_A_Pos 17 /*!< GPDMA C2CONFIG: A Position */\r
-#define GPDMA_C2CONFIG_A_Msk (0x01UL << GPDMA_C2CONFIG_A_Pos) /*!< GPDMA C2CONFIG: A Mask */\r
-#define GPDMA_C2CONFIG_H_Pos 18 /*!< GPDMA C2CONFIG: H Position */\r
-#define GPDMA_C2CONFIG_H_Msk (0x01UL << GPDMA_C2CONFIG_H_Pos) /*!< GPDMA C2CONFIG: H Mask */\r
-\r
-// ------------------------------------- GPDMA_C3SRCADDR ----------------------------------------\r
-#define GPDMA_C3SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C3SRCADDR: SRCADDR Position */\r
-#define GPDMA_C3SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos) /*!< GPDMA C3SRCADDR: SRCADDR Mask */\r
-\r
-// ------------------------------------ GPDMA_C3DESTADDR ----------------------------------------\r
-#define GPDMA_C3DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C3DESTADDR: DESTADDR Position */\r
-#define GPDMA_C3DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos) /*!< GPDMA C3DESTADDR: DESTADDR Mask */\r
-\r
-// --------------------------------------- GPDMA_C3LLI ------------------------------------------\r
-#define GPDMA_C3LLI_LM_Pos 0 /*!< GPDMA C3LLI: LM Position */\r
-#define GPDMA_C3LLI_LM_Msk (0x01UL << GPDMA_C3LLI_LM_Pos) /*!< GPDMA C3LLI: LM Mask */\r
-#define GPDMA_C3LLI_R_Pos 1 /*!< GPDMA C3LLI: R Position */\r
-#define GPDMA_C3LLI_R_Msk (0x01UL << GPDMA_C3LLI_R_Pos) /*!< GPDMA C3LLI: R Mask */\r
-#define GPDMA_C3LLI_LLI_Pos 2 /*!< GPDMA C3LLI: LLI Position */\r
-#define GPDMA_C3LLI_LLI_Msk (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos) /*!< GPDMA C3LLI: LLI Mask */\r
-\r
-// ------------------------------------- GPDMA_C3CONTROL ----------------------------------------\r
-#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */\r
-#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask */\r
-#define GPDMA_C3CONTROL_SBSIZE_Pos 12 /*!< GPDMA C3CONTROL: SBSIZE Position */\r
-#define GPDMA_C3CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos) /*!< GPDMA C3CONTROL: SBSIZE Mask */\r
-#define GPDMA_C3CONTROL_DBSIZE_Pos 15 /*!< GPDMA C3CONTROL: DBSIZE Position */\r
-#define GPDMA_C3CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos) /*!< GPDMA C3CONTROL: DBSIZE Mask */\r
-#define GPDMA_C3CONTROL_SWIDTH_Pos 18 /*!< GPDMA C3CONTROL: SWIDTH Position */\r
-#define GPDMA_C3CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos) /*!< GPDMA C3CONTROL: SWIDTH Mask */\r
-#define GPDMA_C3CONTROL_DWIDTH_Pos 21 /*!< GPDMA C3CONTROL: DWIDTH Position */\r
-#define GPDMA_C3CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos) /*!< GPDMA C3CONTROL: DWIDTH Mask */\r
-#define GPDMA_C3CONTROL_S_Pos 24 /*!< GPDMA C3CONTROL: S Position */\r
-#define GPDMA_C3CONTROL_S_Msk (0x01UL << GPDMA_C3CONTROL_S_Pos) /*!< GPDMA C3CONTROL: S Mask */\r
-#define GPDMA_C3CONTROL_D_Pos 25 /*!< GPDMA C3CONTROL: D Position */\r
-#define GPDMA_C3CONTROL_D_Msk (0x01UL << GPDMA_C3CONTROL_D_Pos) /*!< GPDMA C3CONTROL: D Mask */\r
-#define GPDMA_C3CONTROL_SI_Pos 26 /*!< GPDMA C3CONTROL: SI Position */\r
-#define GPDMA_C3CONTROL_SI_Msk (0x01UL << GPDMA_C3CONTROL_SI_Pos) /*!< GPDMA C3CONTROL: SI Mask */\r
-#define GPDMA_C3CONTROL_DI_Pos 27 /*!< GPDMA C3CONTROL: DI Position */\r
-#define GPDMA_C3CONTROL_DI_Msk (0x01UL << GPDMA_C3CONTROL_DI_Pos) /*!< GPDMA C3CONTROL: DI Mask */\r
-#define GPDMA_C3CONTROL_PROT1_Pos 28 /*!< GPDMA C3CONTROL: PROT1 Position */\r
-#define GPDMA_C3CONTROL_PROT1_Msk (0x01UL << GPDMA_C3CONTROL_PROT1_Pos) /*!< GPDMA C3CONTROL: PROT1 Mask */\r
-#define GPDMA_C3CONTROL_PROT2_Pos 29 /*!< GPDMA C3CONTROL: PROT2 Position */\r
-#define GPDMA_C3CONTROL_PROT2_Msk (0x01UL << GPDMA_C3CONTROL_PROT2_Pos) /*!< GPDMA C3CONTROL: PROT2 Mask */\r
-#define GPDMA_C3CONTROL_PROT3_Pos 30 /*!< GPDMA C3CONTROL: PROT3 Position */\r
-#define GPDMA_C3CONTROL_PROT3_Msk (0x01UL << GPDMA_C3CONTROL_PROT3_Pos) /*!< GPDMA C3CONTROL: PROT3 Mask */\r
-#define GPDMA_C3CONTROL_I_Pos 31 /*!< GPDMA C3CONTROL: I Position */\r
-#define GPDMA_C3CONTROL_I_Msk (0x01UL << GPDMA_C3CONTROL_I_Pos) /*!< GPDMA C3CONTROL: I Mask */\r
-\r
-// ------------------------------------- GPDMA_C3CONFIG -----------------------------------------\r
-#define GPDMA_C3CONFIG_E_Pos 0 /*!< GPDMA C3CONFIG: E Position */\r
-#define GPDMA_C3CONFIG_E_Msk (0x01UL << GPDMA_C3CONFIG_E_Pos) /*!< GPDMA C3CONFIG: E Mask */\r
-#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */\r
-#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask */\r
-#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */\r
-#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */\r
-#define GPDMA_C3CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C3CONFIG: FLOWCNTRL Position */\r
-#define GPDMA_C3CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C3CONFIG: FLOWCNTRL Mask */\r
-#define GPDMA_C3CONFIG_IE_Pos 14 /*!< GPDMA C3CONFIG: IE Position */\r
-#define GPDMA_C3CONFIG_IE_Msk (0x01UL << GPDMA_C3CONFIG_IE_Pos) /*!< GPDMA C3CONFIG: IE Mask */\r
-#define GPDMA_C3CONFIG_ITC_Pos 15 /*!< GPDMA C3CONFIG: ITC Position */\r
-#define GPDMA_C3CONFIG_ITC_Msk (0x01UL << GPDMA_C3CONFIG_ITC_Pos) /*!< GPDMA C3CONFIG: ITC Mask */\r
-#define GPDMA_C3CONFIG_L_Pos 16 /*!< GPDMA C3CONFIG: L Position */\r
-#define GPDMA_C3CONFIG_L_Msk (0x01UL << GPDMA_C3CONFIG_L_Pos) /*!< GPDMA C3CONFIG: L Mask */\r
-#define GPDMA_C3CONFIG_A_Pos 17 /*!< GPDMA C3CONFIG: A Position */\r
-#define GPDMA_C3CONFIG_A_Msk (0x01UL << GPDMA_C3CONFIG_A_Pos) /*!< GPDMA C3CONFIG: A Mask */\r
-#define GPDMA_C3CONFIG_H_Pos 18 /*!< GPDMA C3CONFIG: H Position */\r
-#define GPDMA_C3CONFIG_H_Msk (0x01UL << GPDMA_C3CONFIG_H_Pos) /*!< GPDMA C3CONFIG: H Mask */\r
-\r
-// ------------------------------------- GPDMA_C4SRCADDR ----------------------------------------\r
-#define GPDMA_C4SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C4SRCADDR: SRCADDR Position */\r
-#define GPDMA_C4SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos) /*!< GPDMA C4SRCADDR: SRCADDR Mask */\r
-\r
-// ------------------------------------ GPDMA_C4DESTADDR ----------------------------------------\r
-#define GPDMA_C4DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C4DESTADDR: DESTADDR Position */\r
-#define GPDMA_C4DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos) /*!< GPDMA C4DESTADDR: DESTADDR Mask */\r
-\r
-// --------------------------------------- GPDMA_C4LLI ------------------------------------------\r
-#define GPDMA_C4LLI_LM_Pos 0 /*!< GPDMA C4LLI: LM Position */\r
-#define GPDMA_C4LLI_LM_Msk (0x01UL << GPDMA_C4LLI_LM_Pos) /*!< GPDMA C4LLI: LM Mask */\r
-#define GPDMA_C4LLI_R_Pos 1 /*!< GPDMA C4LLI: R Position */\r
-#define GPDMA_C4LLI_R_Msk (0x01UL << GPDMA_C4LLI_R_Pos) /*!< GPDMA C4LLI: R Mask */\r
-#define GPDMA_C4LLI_LLI_Pos 2 /*!< GPDMA C4LLI: LLI Position */\r
-#define GPDMA_C4LLI_LLI_Msk (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos) /*!< GPDMA C4LLI: LLI Mask */\r
-\r
-// ------------------------------------- GPDMA_C4CONTROL ----------------------------------------\r
-#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */\r
-#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask */\r
-#define GPDMA_C4CONTROL_SBSIZE_Pos 12 /*!< GPDMA C4CONTROL: SBSIZE Position */\r
-#define GPDMA_C4CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos) /*!< GPDMA C4CONTROL: SBSIZE Mask */\r
-#define GPDMA_C4CONTROL_DBSIZE_Pos 15 /*!< GPDMA C4CONTROL: DBSIZE Position */\r
-#define GPDMA_C4CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos) /*!< GPDMA C4CONTROL: DBSIZE Mask */\r
-#define GPDMA_C4CONTROL_SWIDTH_Pos 18 /*!< GPDMA C4CONTROL: SWIDTH Position */\r
-#define GPDMA_C4CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos) /*!< GPDMA C4CONTROL: SWIDTH Mask */\r
-#define GPDMA_C4CONTROL_DWIDTH_Pos 21 /*!< GPDMA C4CONTROL: DWIDTH Position */\r
-#define GPDMA_C4CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos) /*!< GPDMA C4CONTROL: DWIDTH Mask */\r
-#define GPDMA_C4CONTROL_S_Pos 24 /*!< GPDMA C4CONTROL: S Position */\r
-#define GPDMA_C4CONTROL_S_Msk (0x01UL << GPDMA_C4CONTROL_S_Pos) /*!< GPDMA C4CONTROL: S Mask */\r
-#define GPDMA_C4CONTROL_D_Pos 25 /*!< GPDMA C4CONTROL: D Position */\r
-#define GPDMA_C4CONTROL_D_Msk (0x01UL << GPDMA_C4CONTROL_D_Pos) /*!< GPDMA C4CONTROL: D Mask */\r
-#define GPDMA_C4CONTROL_SI_Pos 26 /*!< GPDMA C4CONTROL: SI Position */\r
-#define GPDMA_C4CONTROL_SI_Msk (0x01UL << GPDMA_C4CONTROL_SI_Pos) /*!< GPDMA C4CONTROL: SI Mask */\r
-#define GPDMA_C4CONTROL_DI_Pos 27 /*!< GPDMA C4CONTROL: DI Position */\r
-#define GPDMA_C4CONTROL_DI_Msk (0x01UL << GPDMA_C4CONTROL_DI_Pos) /*!< GPDMA C4CONTROL: DI Mask */\r
-#define GPDMA_C4CONTROL_PROT1_Pos 28 /*!< GPDMA C4CONTROL: PROT1 Position */\r
-#define GPDMA_C4CONTROL_PROT1_Msk (0x01UL << GPDMA_C4CONTROL_PROT1_Pos) /*!< GPDMA C4CONTROL: PROT1 Mask */\r
-#define GPDMA_C4CONTROL_PROT2_Pos 29 /*!< GPDMA C4CONTROL: PROT2 Position */\r
-#define GPDMA_C4CONTROL_PROT2_Msk (0x01UL << GPDMA_C4CONTROL_PROT2_Pos) /*!< GPDMA C4CONTROL: PROT2 Mask */\r
-#define GPDMA_C4CONTROL_PROT3_Pos 30 /*!< GPDMA C4CONTROL: PROT3 Position */\r
-#define GPDMA_C4CONTROL_PROT3_Msk (0x01UL << GPDMA_C4CONTROL_PROT3_Pos) /*!< GPDMA C4CONTROL: PROT3 Mask */\r
-#define GPDMA_C4CONTROL_I_Pos 31 /*!< GPDMA C4CONTROL: I Position */\r
-#define GPDMA_C4CONTROL_I_Msk (0x01UL << GPDMA_C4CONTROL_I_Pos) /*!< GPDMA C4CONTROL: I Mask */\r
-\r
-// ------------------------------------- GPDMA_C4CONFIG -----------------------------------------\r
-#define GPDMA_C4CONFIG_E_Pos 0 /*!< GPDMA C4CONFIG: E Position */\r
-#define GPDMA_C4CONFIG_E_Msk (0x01UL << GPDMA_C4CONFIG_E_Pos) /*!< GPDMA C4CONFIG: E Mask */\r
-#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */\r
-#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask */\r
-#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */\r
-#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */\r
-#define GPDMA_C4CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C4CONFIG: FLOWCNTRL Position */\r
-#define GPDMA_C4CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C4CONFIG: FLOWCNTRL Mask */\r
-#define GPDMA_C4CONFIG_IE_Pos 14 /*!< GPDMA C4CONFIG: IE Position */\r
-#define GPDMA_C4CONFIG_IE_Msk (0x01UL << GPDMA_C4CONFIG_IE_Pos) /*!< GPDMA C4CONFIG: IE Mask */\r
-#define GPDMA_C4CONFIG_ITC_Pos 15 /*!< GPDMA C4CONFIG: ITC Position */\r
-#define GPDMA_C4CONFIG_ITC_Msk (0x01UL << GPDMA_C4CONFIG_ITC_Pos) /*!< GPDMA C4CONFIG: ITC Mask */\r
-#define GPDMA_C4CONFIG_L_Pos 16 /*!< GPDMA C4CONFIG: L Position */\r
-#define GPDMA_C4CONFIG_L_Msk (0x01UL << GPDMA_C4CONFIG_L_Pos) /*!< GPDMA C4CONFIG: L Mask */\r
-#define GPDMA_C4CONFIG_A_Pos 17 /*!< GPDMA C4CONFIG: A Position */\r
-#define GPDMA_C4CONFIG_A_Msk (0x01UL << GPDMA_C4CONFIG_A_Pos) /*!< GPDMA C4CONFIG: A Mask */\r
-#define GPDMA_C4CONFIG_H_Pos 18 /*!< GPDMA C4CONFIG: H Position */\r
-#define GPDMA_C4CONFIG_H_Msk (0x01UL << GPDMA_C4CONFIG_H_Pos) /*!< GPDMA C4CONFIG: H Mask */\r
-\r
-// ------------------------------------- GPDMA_C5SRCADDR ----------------------------------------\r
-#define GPDMA_C5SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C5SRCADDR: SRCADDR Position */\r
-#define GPDMA_C5SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos) /*!< GPDMA C5SRCADDR: SRCADDR Mask */\r
-\r
-// ------------------------------------ GPDMA_C5DESTADDR ----------------------------------------\r
-#define GPDMA_C5DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C5DESTADDR: DESTADDR Position */\r
-#define GPDMA_C5DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos) /*!< GPDMA C5DESTADDR: DESTADDR Mask */\r
-\r
-// --------------------------------------- GPDMA_C5LLI ------------------------------------------\r
-#define GPDMA_C5LLI_LM_Pos 0 /*!< GPDMA C5LLI: LM Position */\r
-#define GPDMA_C5LLI_LM_Msk (0x01UL << GPDMA_C5LLI_LM_Pos) /*!< GPDMA C5LLI: LM Mask */\r
-#define GPDMA_C5LLI_R_Pos 1 /*!< GPDMA C5LLI: R Position */\r
-#define GPDMA_C5LLI_R_Msk (0x01UL << GPDMA_C5LLI_R_Pos) /*!< GPDMA C5LLI: R Mask */\r
-#define GPDMA_C5LLI_LLI_Pos 2 /*!< GPDMA C5LLI: LLI Position */\r
-#define GPDMA_C5LLI_LLI_Msk (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos) /*!< GPDMA C5LLI: LLI Mask */\r
-\r
-// ------------------------------------- GPDMA_C5CONTROL ----------------------------------------\r
-#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */\r
-#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask */\r
-#define GPDMA_C5CONTROL_SBSIZE_Pos 12 /*!< GPDMA C5CONTROL: SBSIZE Position */\r
-#define GPDMA_C5CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos) /*!< GPDMA C5CONTROL: SBSIZE Mask */\r
-#define GPDMA_C5CONTROL_DBSIZE_Pos 15 /*!< GPDMA C5CONTROL: DBSIZE Position */\r
-#define GPDMA_C5CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos) /*!< GPDMA C5CONTROL: DBSIZE Mask */\r
-#define GPDMA_C5CONTROL_SWIDTH_Pos 18 /*!< GPDMA C5CONTROL: SWIDTH Position */\r
-#define GPDMA_C5CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos) /*!< GPDMA C5CONTROL: SWIDTH Mask */\r
-#define GPDMA_C5CONTROL_DWIDTH_Pos 21 /*!< GPDMA C5CONTROL: DWIDTH Position */\r
-#define GPDMA_C5CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos) /*!< GPDMA C5CONTROL: DWIDTH Mask */\r
-#define GPDMA_C5CONTROL_S_Pos 24 /*!< GPDMA C5CONTROL: S Position */\r
-#define GPDMA_C5CONTROL_S_Msk (0x01UL << GPDMA_C5CONTROL_S_Pos) /*!< GPDMA C5CONTROL: S Mask */\r
-#define GPDMA_C5CONTROL_D_Pos 25 /*!< GPDMA C5CONTROL: D Position */\r
-#define GPDMA_C5CONTROL_D_Msk (0x01UL << GPDMA_C5CONTROL_D_Pos) /*!< GPDMA C5CONTROL: D Mask */\r
-#define GPDMA_C5CONTROL_SI_Pos 26 /*!< GPDMA C5CONTROL: SI Position */\r
-#define GPDMA_C5CONTROL_SI_Msk (0x01UL << GPDMA_C5CONTROL_SI_Pos) /*!< GPDMA C5CONTROL: SI Mask */\r
-#define GPDMA_C5CONTROL_DI_Pos 27 /*!< GPDMA C5CONTROL: DI Position */\r
-#define GPDMA_C5CONTROL_DI_Msk (0x01UL << GPDMA_C5CONTROL_DI_Pos) /*!< GPDMA C5CONTROL: DI Mask */\r
-#define GPDMA_C5CONTROL_PROT1_Pos 28 /*!< GPDMA C5CONTROL: PROT1 Position */\r
-#define GPDMA_C5CONTROL_PROT1_Msk (0x01UL << GPDMA_C5CONTROL_PROT1_Pos) /*!< GPDMA C5CONTROL: PROT1 Mask */\r
-#define GPDMA_C5CONTROL_PROT2_Pos 29 /*!< GPDMA C5CONTROL: PROT2 Position */\r
-#define GPDMA_C5CONTROL_PROT2_Msk (0x01UL << GPDMA_C5CONTROL_PROT2_Pos) /*!< GPDMA C5CONTROL: PROT2 Mask */\r
-#define GPDMA_C5CONTROL_PROT3_Pos 30 /*!< GPDMA C5CONTROL: PROT3 Position */\r
-#define GPDMA_C5CONTROL_PROT3_Msk (0x01UL << GPDMA_C5CONTROL_PROT3_Pos) /*!< GPDMA C5CONTROL: PROT3 Mask */\r
-#define GPDMA_C5CONTROL_I_Pos 31 /*!< GPDMA C5CONTROL: I Position */\r
-#define GPDMA_C5CONTROL_I_Msk (0x01UL << GPDMA_C5CONTROL_I_Pos) /*!< GPDMA C5CONTROL: I Mask */\r
-\r
-// ------------------------------------- GPDMA_C5CONFIG -----------------------------------------\r
-#define GPDMA_C5CONFIG_E_Pos 0 /*!< GPDMA C5CONFIG: E Position */\r
-#define GPDMA_C5CONFIG_E_Msk (0x01UL << GPDMA_C5CONFIG_E_Pos) /*!< GPDMA C5CONFIG: E Mask */\r
-#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */\r
-#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask */\r
-#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */\r
-#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */\r
-#define GPDMA_C5CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C5CONFIG: FLOWCNTRL Position */\r
-#define GPDMA_C5CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C5CONFIG: FLOWCNTRL Mask */\r
-#define GPDMA_C5CONFIG_IE_Pos 14 /*!< GPDMA C5CONFIG: IE Position */\r
-#define GPDMA_C5CONFIG_IE_Msk (0x01UL << GPDMA_C5CONFIG_IE_Pos) /*!< GPDMA C5CONFIG: IE Mask */\r
-#define GPDMA_C5CONFIG_ITC_Pos 15 /*!< GPDMA C5CONFIG: ITC Position */\r
-#define GPDMA_C5CONFIG_ITC_Msk (0x01UL << GPDMA_C5CONFIG_ITC_Pos) /*!< GPDMA C5CONFIG: ITC Mask */\r
-#define GPDMA_C5CONFIG_L_Pos 16 /*!< GPDMA C5CONFIG: L Position */\r
-#define GPDMA_C5CONFIG_L_Msk (0x01UL << GPDMA_C5CONFIG_L_Pos) /*!< GPDMA C5CONFIG: L Mask */\r
-#define GPDMA_C5CONFIG_A_Pos 17 /*!< GPDMA C5CONFIG: A Position */\r
-#define GPDMA_C5CONFIG_A_Msk (0x01UL << GPDMA_C5CONFIG_A_Pos) /*!< GPDMA C5CONFIG: A Mask */\r
-#define GPDMA_C5CONFIG_H_Pos 18 /*!< GPDMA C5CONFIG: H Position */\r
-#define GPDMA_C5CONFIG_H_Msk (0x01UL << GPDMA_C5CONFIG_H_Pos) /*!< GPDMA C5CONFIG: H Mask */\r
-\r
-// ------------------------------------- GPDMA_C6SRCADDR ----------------------------------------\r
-#define GPDMA_C6SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C6SRCADDR: SRCADDR Position */\r
-#define GPDMA_C6SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos) /*!< GPDMA C6SRCADDR: SRCADDR Mask */\r
-\r
-// ------------------------------------ GPDMA_C6DESTADDR ----------------------------------------\r
-#define GPDMA_C6DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C6DESTADDR: DESTADDR Position */\r
-#define GPDMA_C6DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos) /*!< GPDMA C6DESTADDR: DESTADDR Mask */\r
-\r
-// --------------------------------------- GPDMA_C6LLI ------------------------------------------\r
-#define GPDMA_C6LLI_LM_Pos 0 /*!< GPDMA C6LLI: LM Position */\r
-#define GPDMA_C6LLI_LM_Msk (0x01UL << GPDMA_C6LLI_LM_Pos) /*!< GPDMA C6LLI: LM Mask */\r
-#define GPDMA_C6LLI_R_Pos 1 /*!< GPDMA C6LLI: R Position */\r
-#define GPDMA_C6LLI_R_Msk (0x01UL << GPDMA_C6LLI_R_Pos) /*!< GPDMA C6LLI: R Mask */\r
-#define GPDMA_C6LLI_LLI_Pos 2 /*!< GPDMA C6LLI: LLI Position */\r
-#define GPDMA_C6LLI_LLI_Msk (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos) /*!< GPDMA C6LLI: LLI Mask */\r
-\r
-// ------------------------------------- GPDMA_C6CONTROL ----------------------------------------\r
-#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */\r
-#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask */\r
-#define GPDMA_C6CONTROL_SBSIZE_Pos 12 /*!< GPDMA C6CONTROL: SBSIZE Position */\r
-#define GPDMA_C6CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos) /*!< GPDMA C6CONTROL: SBSIZE Mask */\r
-#define GPDMA_C6CONTROL_DBSIZE_Pos 15 /*!< GPDMA C6CONTROL: DBSIZE Position */\r
-#define GPDMA_C6CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos) /*!< GPDMA C6CONTROL: DBSIZE Mask */\r
-#define GPDMA_C6CONTROL_SWIDTH_Pos 18 /*!< GPDMA C6CONTROL: SWIDTH Position */\r
-#define GPDMA_C6CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos) /*!< GPDMA C6CONTROL: SWIDTH Mask */\r
-#define GPDMA_C6CONTROL_DWIDTH_Pos 21 /*!< GPDMA C6CONTROL: DWIDTH Position */\r
-#define GPDMA_C6CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos) /*!< GPDMA C6CONTROL: DWIDTH Mask */\r
-#define GPDMA_C6CONTROL_S_Pos 24 /*!< GPDMA C6CONTROL: S Position */\r
-#define GPDMA_C6CONTROL_S_Msk (0x01UL << GPDMA_C6CONTROL_S_Pos) /*!< GPDMA C6CONTROL: S Mask */\r
-#define GPDMA_C6CONTROL_D_Pos 25 /*!< GPDMA C6CONTROL: D Position */\r
-#define GPDMA_C6CONTROL_D_Msk (0x01UL << GPDMA_C6CONTROL_D_Pos) /*!< GPDMA C6CONTROL: D Mask */\r
-#define GPDMA_C6CONTROL_SI_Pos 26 /*!< GPDMA C6CONTROL: SI Position */\r
-#define GPDMA_C6CONTROL_SI_Msk (0x01UL << GPDMA_C6CONTROL_SI_Pos) /*!< GPDMA C6CONTROL: SI Mask */\r
-#define GPDMA_C6CONTROL_DI_Pos 27 /*!< GPDMA C6CONTROL: DI Position */\r
-#define GPDMA_C6CONTROL_DI_Msk (0x01UL << GPDMA_C6CONTROL_DI_Pos) /*!< GPDMA C6CONTROL: DI Mask */\r
-#define GPDMA_C6CONTROL_PROT1_Pos 28 /*!< GPDMA C6CONTROL: PROT1 Position */\r
-#define GPDMA_C6CONTROL_PROT1_Msk (0x01UL << GPDMA_C6CONTROL_PROT1_Pos) /*!< GPDMA C6CONTROL: PROT1 Mask */\r
-#define GPDMA_C6CONTROL_PROT2_Pos 29 /*!< GPDMA C6CONTROL: PROT2 Position */\r
-#define GPDMA_C6CONTROL_PROT2_Msk (0x01UL << GPDMA_C6CONTROL_PROT2_Pos) /*!< GPDMA C6CONTROL: PROT2 Mask */\r
-#define GPDMA_C6CONTROL_PROT3_Pos 30 /*!< GPDMA C6CONTROL: PROT3 Position */\r
-#define GPDMA_C6CONTROL_PROT3_Msk (0x01UL << GPDMA_C6CONTROL_PROT3_Pos) /*!< GPDMA C6CONTROL: PROT3 Mask */\r
-#define GPDMA_C6CONTROL_I_Pos 31 /*!< GPDMA C6CONTROL: I Position */\r
-#define GPDMA_C6CONTROL_I_Msk (0x01UL << GPDMA_C6CONTROL_I_Pos) /*!< GPDMA C6CONTROL: I Mask */\r
-\r
-// ------------------------------------- GPDMA_C6CONFIG -----------------------------------------\r
-#define GPDMA_C6CONFIG_E_Pos 0 /*!< GPDMA C6CONFIG: E Position */\r
-#define GPDMA_C6CONFIG_E_Msk (0x01UL << GPDMA_C6CONFIG_E_Pos) /*!< GPDMA C6CONFIG: E Mask */\r
-#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */\r
-#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask */\r
-#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */\r
-#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */\r
-#define GPDMA_C6CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C6CONFIG: FLOWCNTRL Position */\r
-#define GPDMA_C6CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C6CONFIG: FLOWCNTRL Mask */\r
-#define GPDMA_C6CONFIG_IE_Pos 14 /*!< GPDMA C6CONFIG: IE Position */\r
-#define GPDMA_C6CONFIG_IE_Msk (0x01UL << GPDMA_C6CONFIG_IE_Pos) /*!< GPDMA C6CONFIG: IE Mask */\r
-#define GPDMA_C6CONFIG_ITC_Pos 15 /*!< GPDMA C6CONFIG: ITC Position */\r
-#define GPDMA_C6CONFIG_ITC_Msk (0x01UL << GPDMA_C6CONFIG_ITC_Pos) /*!< GPDMA C6CONFIG: ITC Mask */\r
-#define GPDMA_C6CONFIG_L_Pos 16 /*!< GPDMA C6CONFIG: L Position */\r
-#define GPDMA_C6CONFIG_L_Msk (0x01UL << GPDMA_C6CONFIG_L_Pos) /*!< GPDMA C6CONFIG: L Mask */\r
-#define GPDMA_C6CONFIG_A_Pos 17 /*!< GPDMA C6CONFIG: A Position */\r
-#define GPDMA_C6CONFIG_A_Msk (0x01UL << GPDMA_C6CONFIG_A_Pos) /*!< GPDMA C6CONFIG: A Mask */\r
-#define GPDMA_C6CONFIG_H_Pos 18 /*!< GPDMA C6CONFIG: H Position */\r
-#define GPDMA_C6CONFIG_H_Msk (0x01UL << GPDMA_C6CONFIG_H_Pos) /*!< GPDMA C6CONFIG: H Mask */\r
-\r
-// ------------------------------------- GPDMA_C7SRCADDR ----------------------------------------\r
-#define GPDMA_C7SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C7SRCADDR: SRCADDR Position */\r
-#define GPDMA_C7SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos) /*!< GPDMA C7SRCADDR: SRCADDR Mask */\r
-\r
-// ------------------------------------ GPDMA_C7DESTADDR ----------------------------------------\r
-#define GPDMA_C7DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C7DESTADDR: DESTADDR Position */\r
-#define GPDMA_C7DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos) /*!< GPDMA C7DESTADDR: DESTADDR Mask */\r
-\r
-// --------------------------------------- GPDMA_C7LLI ------------------------------------------\r
-#define GPDMA_C7LLI_LM_Pos 0 /*!< GPDMA C7LLI: LM Position */\r
-#define GPDMA_C7LLI_LM_Msk (0x01UL << GPDMA_C7LLI_LM_Pos) /*!< GPDMA C7LLI: LM Mask */\r
-#define GPDMA_C7LLI_R_Pos 1 /*!< GPDMA C7LLI: R Position */\r
-#define GPDMA_C7LLI_R_Msk (0x01UL << GPDMA_C7LLI_R_Pos) /*!< GPDMA C7LLI: R Mask */\r
-#define GPDMA_C7LLI_LLI_Pos 2 /*!< GPDMA C7LLI: LLI Position */\r
-#define GPDMA_C7LLI_LLI_Msk (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos) /*!< GPDMA C7LLI: LLI Mask */\r
-\r
-// ------------------------------------- GPDMA_C7CONTROL ----------------------------------------\r
-#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */\r
-#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask */\r
-#define GPDMA_C7CONTROL_SBSIZE_Pos 12 /*!< GPDMA C7CONTROL: SBSIZE Position */\r
-#define GPDMA_C7CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos) /*!< GPDMA C7CONTROL: SBSIZE Mask */\r
-#define GPDMA_C7CONTROL_DBSIZE_Pos 15 /*!< GPDMA C7CONTROL: DBSIZE Position */\r
-#define GPDMA_C7CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos) /*!< GPDMA C7CONTROL: DBSIZE Mask */\r
-#define GPDMA_C7CONTROL_SWIDTH_Pos 18 /*!< GPDMA C7CONTROL: SWIDTH Position */\r
-#define GPDMA_C7CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos) /*!< GPDMA C7CONTROL: SWIDTH Mask */\r
-#define GPDMA_C7CONTROL_DWIDTH_Pos 21 /*!< GPDMA C7CONTROL: DWIDTH Position */\r
-#define GPDMA_C7CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos) /*!< GPDMA C7CONTROL: DWIDTH Mask */\r
-#define GPDMA_C7CONTROL_S_Pos 24 /*!< GPDMA C7CONTROL: S Position */\r
-#define GPDMA_C7CONTROL_S_Msk (0x01UL << GPDMA_C7CONTROL_S_Pos) /*!< GPDMA C7CONTROL: S Mask */\r
-#define GPDMA_C7CONTROL_D_Pos 25 /*!< GPDMA C7CONTROL: D Position */\r
-#define GPDMA_C7CONTROL_D_Msk (0x01UL << GPDMA_C7CONTROL_D_Pos) /*!< GPDMA C7CONTROL: D Mask */\r
-#define GPDMA_C7CONTROL_SI_Pos 26 /*!< GPDMA C7CONTROL: SI Position */\r
-#define GPDMA_C7CONTROL_SI_Msk (0x01UL << GPDMA_C7CONTROL_SI_Pos) /*!< GPDMA C7CONTROL: SI Mask */\r
-#define GPDMA_C7CONTROL_DI_Pos 27 /*!< GPDMA C7CONTROL: DI Position */\r
-#define GPDMA_C7CONTROL_DI_Msk (0x01UL << GPDMA_C7CONTROL_DI_Pos) /*!< GPDMA C7CONTROL: DI Mask */\r
-#define GPDMA_C7CONTROL_PROT1_Pos 28 /*!< GPDMA C7CONTROL: PROT1 Position */\r
-#define GPDMA_C7CONTROL_PROT1_Msk (0x01UL << GPDMA_C7CONTROL_PROT1_Pos) /*!< GPDMA C7CONTROL: PROT1 Mask */\r
-#define GPDMA_C7CONTROL_PROT2_Pos 29 /*!< GPDMA C7CONTROL: PROT2 Position */\r
-#define GPDMA_C7CONTROL_PROT2_Msk (0x01UL << GPDMA_C7CONTROL_PROT2_Pos) /*!< GPDMA C7CONTROL: PROT2 Mask */\r
-#define GPDMA_C7CONTROL_PROT3_Pos 30 /*!< GPDMA C7CONTROL: PROT3 Position */\r
-#define GPDMA_C7CONTROL_PROT3_Msk (0x01UL << GPDMA_C7CONTROL_PROT3_Pos) /*!< GPDMA C7CONTROL: PROT3 Mask */\r
-#define GPDMA_C7CONTROL_I_Pos 31 /*!< GPDMA C7CONTROL: I Position */\r
-#define GPDMA_C7CONTROL_I_Msk (0x01UL << GPDMA_C7CONTROL_I_Pos) /*!< GPDMA C7CONTROL: I Mask */\r
-\r
-// ------------------------------------- GPDMA_C7CONFIG -----------------------------------------\r
-#define GPDMA_C7CONFIG_E_Pos 0 /*!< GPDMA C7CONFIG: E Position */\r
-#define GPDMA_C7CONFIG_E_Msk (0x01UL << GPDMA_C7CONFIG_E_Pos) /*!< GPDMA C7CONFIG: E Mask */\r
-#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */\r
-#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask */\r
-#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */\r
-#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */\r
-#define GPDMA_C7CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C7CONFIG: FLOWCNTRL Position */\r
-#define GPDMA_C7CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C7CONFIG: FLOWCNTRL Mask */\r
-#define GPDMA_C7CONFIG_IE_Pos 14 /*!< GPDMA C7CONFIG: IE Position */\r
-#define GPDMA_C7CONFIG_IE_Msk (0x01UL << GPDMA_C7CONFIG_IE_Pos) /*!< GPDMA C7CONFIG: IE Mask */\r
-#define GPDMA_C7CONFIG_ITC_Pos 15 /*!< GPDMA C7CONFIG: ITC Position */\r
-#define GPDMA_C7CONFIG_ITC_Msk (0x01UL << GPDMA_C7CONFIG_ITC_Pos) /*!< GPDMA C7CONFIG: ITC Mask */\r
-#define GPDMA_C7CONFIG_L_Pos 16 /*!< GPDMA C7CONFIG: L Position */\r
-#define GPDMA_C7CONFIG_L_Msk (0x01UL << GPDMA_C7CONFIG_L_Pos) /*!< GPDMA C7CONFIG: L Mask */\r
-#define GPDMA_C7CONFIG_A_Pos 17 /*!< GPDMA C7CONFIG: A Position */\r
-#define GPDMA_C7CONFIG_A_Msk (0x01UL << GPDMA_C7CONFIG_A_Pos) /*!< GPDMA C7CONFIG: A Mask */\r
-#define GPDMA_C7CONFIG_H_Pos 18 /*!< GPDMA C7CONFIG: H Position */\r
-#define GPDMA_C7CONFIG_H_Msk (0x01UL << GPDMA_C7CONFIG_H_Pos) /*!< GPDMA C7CONFIG: H Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- SDMMC Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- SDMMC_CTRL -------------------------------------------\r
-#define SDMMC_CTRL_CONTROLLER_RESET_Pos 0 /*!< SDMMC CTRL: CONTROLLER_RESET Position */\r
-#define SDMMC_CTRL_CONTROLLER_RESET_Msk (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos) /*!< SDMMC CTRL: CONTROLLER_RESET Mask */\r
-#define SDMMC_CTRL_FIFO_RESET_Pos 1 /*!< SDMMC CTRL: FIFO_RESET Position */\r
-#define SDMMC_CTRL_FIFO_RESET_Msk (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos) /*!< SDMMC CTRL: FIFO_RESET Mask */\r
-#define SDMMC_CTRL_DMA_RESET_Pos 2 /*!< SDMMC CTRL: DMA_RESET Position */\r
-#define SDMMC_CTRL_DMA_RESET_Msk (0x01UL << SDMMC_CTRL_DMA_RESET_Pos) /*!< SDMMC CTRL: DMA_RESET Mask */\r
-#define SDMMC_CTRL_INT_ENABLE_Pos 4 /*!< SDMMC CTRL: INT_ENABLE Position */\r
-#define SDMMC_CTRL_INT_ENABLE_Msk (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos) /*!< SDMMC CTRL: INT_ENABLE Mask */\r
-#define SDMMC_CTRL_DMA_ENABLE_Pos 5 /*!< SDMMC CTRL: DMA_ENABLE Position */\r
-#define SDMMC_CTRL_DMA_ENABLE_Msk (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos) /*!< SDMMC CTRL: DMA_ENABLE Mask */\r
-#define SDMMC_CTRL_READ_WAIT_Pos 6 /*!< SDMMC CTRL: READ_WAIT Position */\r
-#define SDMMC_CTRL_READ_WAIT_Msk (0x01UL << SDMMC_CTRL_READ_WAIT_Pos) /*!< SDMMC CTRL: READ_WAIT Mask */\r
-#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos 7 /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */\r
-#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos) /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask */\r
-#define SDMMC_CTRL_ABORT_READ_DATA_Pos 8 /*!< SDMMC CTRL: ABORT_READ_DATA Position */\r
-#define SDMMC_CTRL_ABORT_READ_DATA_Msk (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos) /*!< SDMMC CTRL: ABORT_READ_DATA Mask */\r
-#define SDMMC_CTRL_SEND_CCSD_Pos 9 /*!< SDMMC CTRL: SEND_CCSD Position */\r
-#define SDMMC_CTRL_SEND_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos) /*!< SDMMC CTRL: SEND_CCSD Mask */\r
-#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos 10 /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Position */\r
-#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos) /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Mask */\r
-#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos 11 /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */\r
-#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos) /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */\r
-#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos 16 /*!< SDMMC CTRL: CARD_VOLTAGE_A Position */\r
-#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A Mask */\r
-#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos 20 /*!< SDMMC CTRL: CARD_VOLTAGE_B Position */\r
-#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_B Mask */\r
-#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos 24 /*!< SDMMC CTRL: ENABLE_OD_PULLUP Position */\r
-#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos) /*!< SDMMC CTRL: ENABLE_OD_PULLUP Mask */\r
-#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos 25 /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */\r
-#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos) /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask */\r
-\r
-// --------------------------------------- SDMMC_PWREN ------------------------------------------\r
-#define SDMMC_PWREN_POWER_ENABLE_Pos 0 /*!< SDMMC PWREN: POWER_ENABLE Position */\r
-#define SDMMC_PWREN_POWER_ENABLE_Msk (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos) /*!< SDMMC PWREN: POWER_ENABLE Mask */\r
-\r
-// -------------------------------------- SDMMC_CLKDIV ------------------------------------------\r
-#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos 0 /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */\r
-#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask */\r
-#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos 8 /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */\r
-#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask */\r
-#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos 16 /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */\r
-#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask */\r
-#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos 24 /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */\r
-#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask */\r
-\r
-// -------------------------------------- SDMMC_CLKSRC ------------------------------------------\r
-#define SDMMC_CLKSRC_CLK_SOURCE_Pos 0 /*!< SDMMC CLKSRC: CLK_SOURCE Position */\r
-#define SDMMC_CLKSRC_CLK_SOURCE_Msk (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos) /*!< SDMMC CLKSRC: CLK_SOURCE Mask */\r
-\r
-// -------------------------------------- SDMMC_CLKENA ------------------------------------------\r
-#define SDMMC_CLKENA_CCLK_ENABLE_Pos 0 /*!< SDMMC CLKENA: CCLK_ENABLE Position */\r
-#define SDMMC_CLKENA_CCLK_ENABLE_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos) /*!< SDMMC CLKENA: CCLK_ENABLE Mask */\r
-#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos 16 /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */\r
-#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos) /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask */\r
-\r
-// --------------------------------------- SDMMC_TMOUT ------------------------------------------\r
-#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos 0 /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */\r
-#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos) /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask */\r
-#define SDMMC_TMOUT_DATA_TIMEOUT_Pos 8 /*!< SDMMC TMOUT: DATA_TIMEOUT Position */\r
-#define SDMMC_TMOUT_DATA_TIMEOUT_Msk (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos) /*!< SDMMC TMOUT: DATA_TIMEOUT Mask */\r
-\r
-// --------------------------------------- SDMMC_CTYPE ------------------------------------------\r
-#define SDMMC_CTYPE_CARD_WIDTH0_Pos 0 /*!< SDMMC CTYPE: CARD_WIDTH0 Position */\r
-#define SDMMC_CTYPE_CARD_WIDTH0_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos) /*!< SDMMC CTYPE: CARD_WIDTH0 Mask */\r
-#define SDMMC_CTYPE_CARD_WIDTH1_Pos 16 /*!< SDMMC CTYPE: CARD_WIDTH1 Position */\r
-#define SDMMC_CTYPE_CARD_WIDTH1_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos) /*!< SDMMC CTYPE: CARD_WIDTH1 Mask */\r
-\r
-// -------------------------------------- SDMMC_BLKSIZ ------------------------------------------\r
-#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos 0 /*!< SDMMC BLKSIZ: BLOCK_SIZE Position */\r
-#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos) /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask */\r
-\r
-// -------------------------------------- SDMMC_BYTCNT ------------------------------------------\r
-#define SDMMC_BYTCNT_BYTE_COUNT_Pos 0 /*!< SDMMC BYTCNT: BYTE_COUNT Position */\r
-#define SDMMC_BYTCNT_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos) /*!< SDMMC BYTCNT: BYTE_COUNT Mask */\r
-\r
-// -------------------------------------- SDMMC_INTMASK -----------------------------------------\r
-#define SDMMC_INTMASK_CDET_Pos 0 /*!< SDMMC INTMASK: CDET Position */\r
-#define SDMMC_INTMASK_CDET_Msk (0x01UL << SDMMC_INTMASK_CDET_Pos) /*!< SDMMC INTMASK: CDET Mask */\r
-#define SDMMC_INTMASK_RE_Pos 1 /*!< SDMMC INTMASK: RE Position */\r
-#define SDMMC_INTMASK_RE_Msk (0x01UL << SDMMC_INTMASK_RE_Pos) /*!< SDMMC INTMASK: RE Mask */\r
-#define SDMMC_INTMASK_CDONE_Pos 2 /*!< SDMMC INTMASK: CDONE Position */\r
-#define SDMMC_INTMASK_CDONE_Msk (0x01UL << SDMMC_INTMASK_CDONE_Pos) /*!< SDMMC INTMASK: CDONE Mask */\r
-#define SDMMC_INTMASK_DTO_Pos 3 /*!< SDMMC INTMASK: DTO Position */\r
-#define SDMMC_INTMASK_DTO_Msk (0x01UL << SDMMC_INTMASK_DTO_Pos) /*!< SDMMC INTMASK: DTO Mask */\r
-#define SDMMC_INTMASK_TXDR_Pos 4 /*!< SDMMC INTMASK: TXDR Position */\r
-#define SDMMC_INTMASK_TXDR_Msk (0x01UL << SDMMC_INTMASK_TXDR_Pos) /*!< SDMMC INTMASK: TXDR Mask */\r
-#define SDMMC_INTMASK_RXDR_Pos 5 /*!< SDMMC INTMASK: RXDR Position */\r
-#define SDMMC_INTMASK_RXDR_Msk (0x01UL << SDMMC_INTMASK_RXDR_Pos) /*!< SDMMC INTMASK: RXDR Mask */\r
-#define SDMMC_INTMASK_RCRC_Pos 6 /*!< SDMMC INTMASK: RCRC Position */\r
-#define SDMMC_INTMASK_RCRC_Msk (0x01UL << SDMMC_INTMASK_RCRC_Pos) /*!< SDMMC INTMASK: RCRC Mask */\r
-#define SDMMC_INTMASK_DCRC_Pos 7 /*!< SDMMC INTMASK: DCRC Position */\r
-#define SDMMC_INTMASK_DCRC_Msk (0x01UL << SDMMC_INTMASK_DCRC_Pos) /*!< SDMMC INTMASK: DCRC Mask */\r
-#define SDMMC_INTMASK_RTO_Pos 8 /*!< SDMMC INTMASK: RTO Position */\r
-#define SDMMC_INTMASK_RTO_Msk (0x01UL << SDMMC_INTMASK_RTO_Pos) /*!< SDMMC INTMASK: RTO Mask */\r
-#define SDMMC_INTMASK_DRTO_Pos 9 /*!< SDMMC INTMASK: DRTO Position */\r
-#define SDMMC_INTMASK_DRTO_Msk (0x01UL << SDMMC_INTMASK_DRTO_Pos) /*!< SDMMC INTMASK: DRTO Mask */\r
-#define SDMMC_INTMASK_HTO_Pos 10 /*!< SDMMC INTMASK: HTO Position */\r
-#define SDMMC_INTMASK_HTO_Msk (0x01UL << SDMMC_INTMASK_HTO_Pos) /*!< SDMMC INTMASK: HTO Mask */\r
-#define SDMMC_INTMASK_FRUN_Pos 11 /*!< SDMMC INTMASK: FRUN Position */\r
-#define SDMMC_INTMASK_FRUN_Msk (0x01UL << SDMMC_INTMASK_FRUN_Pos) /*!< SDMMC INTMASK: FRUN Mask */\r
-#define SDMMC_INTMASK_HLE_Pos 12 /*!< SDMMC INTMASK: HLE Position */\r
-#define SDMMC_INTMASK_HLE_Msk (0x01UL << SDMMC_INTMASK_HLE_Pos) /*!< SDMMC INTMASK: HLE Mask */\r
-#define SDMMC_INTMASK_SBE_Pos 13 /*!< SDMMC INTMASK: SBE Position */\r
-#define SDMMC_INTMASK_SBE_Msk (0x01UL << SDMMC_INTMASK_SBE_Pos) /*!< SDMMC INTMASK: SBE Mask */\r
-#define SDMMC_INTMASK_ACD_Pos 14 /*!< SDMMC INTMASK: ACD Position */\r
-#define SDMMC_INTMASK_ACD_Msk (0x01UL << SDMMC_INTMASK_ACD_Pos) /*!< SDMMC INTMASK: ACD Mask */\r
-#define SDMMC_INTMASK_EBE_Pos 15 /*!< SDMMC INTMASK: EBE Position */\r
-#define SDMMC_INTMASK_EBE_Msk (0x01UL << SDMMC_INTMASK_EBE_Pos) /*!< SDMMC INTMASK: EBE Mask */\r
-#define SDMMC_INTMASK_SDIO_INT_MASK_Pos 16 /*!< SDMMC INTMASK: SDIO_INT_MASK Position */\r
-#define SDMMC_INTMASK_SDIO_INT_MASK_Msk (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos) /*!< SDMMC INTMASK: SDIO_INT_MASK Mask */\r
-\r
-// -------------------------------------- SDMMC_CMDARG ------------------------------------------\r
-#define SDMMC_CMDARG_CMD_ARG_Pos 0 /*!< SDMMC CMDARG: CMD_ARG Position */\r
-#define SDMMC_CMDARG_CMD_ARG_Msk (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos) /*!< SDMMC CMDARG: CMD_ARG Mask */\r
-\r
-// ---------------------------------------- SDMMC_CMD -------------------------------------------\r
-#define SDMMC_CMD_CMD_INDEX_Pos 0 /*!< SDMMC CMD: CMD_INDEX Position */\r
-#define SDMMC_CMD_CMD_INDEX_Msk (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos) /*!< SDMMC CMD: CMD_INDEX Mask */\r
-#define SDMMC_CMD_RESPONSE_EXPECT_Pos 6 /*!< SDMMC CMD: RESPONSE_EXPECT Position */\r
-#define SDMMC_CMD_RESPONSE_EXPECT_Msk (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos) /*!< SDMMC CMD: RESPONSE_EXPECT Mask */\r
-#define SDMMC_CMD_RESPONSE_LENGTH_Pos 7 /*!< SDMMC CMD: RESPONSE_LENGTH Position */\r
-#define SDMMC_CMD_RESPONSE_LENGTH_Msk (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos) /*!< SDMMC CMD: RESPONSE_LENGTH Mask */\r
-#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos 8 /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */\r
-#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos) /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask */\r
-#define SDMMC_CMD_DATA_EXPECTED_Pos 9 /*!< SDMMC CMD: DATA_EXPECTED Position */\r
-#define SDMMC_CMD_DATA_EXPECTED_Msk (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos) /*!< SDMMC CMD: DATA_EXPECTED Mask */\r
-#define SDMMC_CMD_READ_WRITE_Pos 10 /*!< SDMMC CMD: READ_WRITE Position */\r
-#define SDMMC_CMD_READ_WRITE_Msk (0x01UL << SDMMC_CMD_READ_WRITE_Pos) /*!< SDMMC CMD: READ_WRITE Mask */\r
-#define SDMMC_CMD_TRANSFER_MODE_Pos 11 /*!< SDMMC CMD: TRANSFER_MODE Position */\r
-#define SDMMC_CMD_TRANSFER_MODE_Msk (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos) /*!< SDMMC CMD: TRANSFER_MODE Mask */\r
-#define SDMMC_CMD_SEND_AUTO_STOP_Pos 12 /*!< SDMMC CMD: SEND_AUTO_STOP Position */\r
-#define SDMMC_CMD_SEND_AUTO_STOP_Msk (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos) /*!< SDMMC CMD: SEND_AUTO_STOP Mask */\r
-#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos 13 /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */\r
-#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos) /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */\r
-#define SDMMC_CMD_STOP_ABORT_CMd_Pos 14 /*!< SDMMC CMD: STOP_ABORT_CMd Position */\r
-#define SDMMC_CMD_STOP_ABORT_CMd_Msk (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos) /*!< SDMMC CMD: STOP_ABORT_CMd Mask */\r
-#define SDMMC_CMD_SEND_INITIALIZATION_Pos 15 /*!< SDMMC CMD: SEND_INITIALIZATION Position */\r
-#define SDMMC_CMD_SEND_INITIALIZATION_Msk (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos) /*!< SDMMC CMD: SEND_INITIALIZATION Mask */\r
-#define SDMMC_CMD_CARD_NUMBER_Pos 16 /*!< SDMMC CMD: CARD_NUMBER Position */\r
-#define SDMMC_CMD_CARD_NUMBER_Msk (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos) /*!< SDMMC CMD: CARD_NUMBER Mask */\r
-#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos 21 /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */\r
-#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos) /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */\r
-#define SDMMC_CMD_READ_CEATA_DEVICE_Pos 22 /*!< SDMMC CMD: READ_CEATA_DEVICE Position */\r
-#define SDMMC_CMD_READ_CEATA_DEVICE_Msk (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos) /*!< SDMMC CMD: READ_CEATA_DEVICE Mask */\r
-#define SDMMC_CMD_CCS_EXPECTED_Pos 23 /*!< SDMMC CMD: CCS_EXPECTED Position */\r
-#define SDMMC_CMD_CCS_EXPECTED_Msk (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos) /*!< SDMMC CMD: CCS_EXPECTED Mask */\r
-#define SDMMC_CMD_ENABLE_BOOT_Pos 24 /*!< SDMMC CMD: ENABLE_BOOT Position */\r
-#define SDMMC_CMD_ENABLE_BOOT_Msk (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos) /*!< SDMMC CMD: ENABLE_BOOT Mask */\r
-#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos 25 /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */\r
-#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos) /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask */\r
-#define SDMMC_CMD_DISABLE_BOOT_Pos 26 /*!< SDMMC CMD: DISABLE_BOOT Position */\r
-#define SDMMC_CMD_DISABLE_BOOT_Msk (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos) /*!< SDMMC CMD: DISABLE_BOOT Mask */\r
-#define SDMMC_CMD_BOOT_MODE_Pos 27 /*!< SDMMC CMD: BOOT_MODE Position */\r
-#define SDMMC_CMD_BOOT_MODE_Msk (0x01UL << SDMMC_CMD_BOOT_MODE_Pos) /*!< SDMMC CMD: BOOT_MODE Mask */\r
-#define SDMMC_CMD_VOLT_SWITCH_Pos 28 /*!< SDMMC CMD: VOLT_SWITCH Position */\r
-#define SDMMC_CMD_VOLT_SWITCH_Msk (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos) /*!< SDMMC CMD: VOLT_SWITCH Mask */\r
-#define SDMMC_CMD_START_CMD_Pos 31 /*!< SDMMC CMD: START_CMD Position */\r
-#define SDMMC_CMD_START_CMD_Msk (0x01UL << SDMMC_CMD_START_CMD_Pos) /*!< SDMMC CMD: START_CMD Mask */\r
-\r
-// --------------------------------------- SDMMC_RESP0 ------------------------------------------\r
-#define SDMMC_RESP0_RESPONSE0_Pos 0 /*!< SDMMC RESP0: RESPONSE0 Position */\r
-#define SDMMC_RESP0_RESPONSE0_Msk (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos) /*!< SDMMC RESP0: RESPONSE0 Mask */\r
-\r
-// --------------------------------------- SDMMC_RESP1 ------------------------------------------\r
-#define SDMMC_RESP1_RESPONSE1_Pos 0 /*!< SDMMC RESP1: RESPONSE1 Position */\r
-#define SDMMC_RESP1_RESPONSE1_Msk (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos) /*!< SDMMC RESP1: RESPONSE1 Mask */\r
-\r
-// --------------------------------------- SDMMC_RESP2 ------------------------------------------\r
-#define SDMMC_RESP2_RESPONSE2_Pos 0 /*!< SDMMC RESP2: RESPONSE2 Position */\r
-#define SDMMC_RESP2_RESPONSE2_Msk (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos) /*!< SDMMC RESP2: RESPONSE2 Mask */\r
-\r
-// --------------------------------------- SDMMC_RESP3 ------------------------------------------\r
-#define SDMMC_RESP3_RESPONSE3_Pos 0 /*!< SDMMC RESP3: RESPONSE3 Position */\r
-#define SDMMC_RESP3_RESPONSE3_Msk (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos) /*!< SDMMC RESP3: RESPONSE3 Mask */\r
-\r
-// -------------------------------------- SDMMC_MINTSTS -----------------------------------------\r
-#define SDMMC_MINTSTS_CDET_Pos 0 /*!< SDMMC MINTSTS: CDET Position */\r
-#define SDMMC_MINTSTS_CDET_Msk (0x01UL << SDMMC_MINTSTS_CDET_Pos) /*!< SDMMC MINTSTS: CDET Mask */\r
-#define SDMMC_MINTSTS_RE_Pos 1 /*!< SDMMC MINTSTS: RE Position */\r
-#define SDMMC_MINTSTS_RE_Msk (0x01UL << SDMMC_MINTSTS_RE_Pos) /*!< SDMMC MINTSTS: RE Mask */\r
-#define SDMMC_MINTSTS_CDONE_Pos 2 /*!< SDMMC MINTSTS: CDONE Position */\r
-#define SDMMC_MINTSTS_CDONE_Msk (0x01UL << SDMMC_MINTSTS_CDONE_Pos) /*!< SDMMC MINTSTS: CDONE Mask */\r
-#define SDMMC_MINTSTS_DTO_Pos 3 /*!< SDMMC MINTSTS: DTO Position */\r
-#define SDMMC_MINTSTS_DTO_Msk (0x01UL << SDMMC_MINTSTS_DTO_Pos) /*!< SDMMC MINTSTS: DTO Mask */\r
-#define SDMMC_MINTSTS_TXDR_Pos 4 /*!< SDMMC MINTSTS: TXDR Position */\r
-#define SDMMC_MINTSTS_TXDR_Msk (0x01UL << SDMMC_MINTSTS_TXDR_Pos) /*!< SDMMC MINTSTS: TXDR Mask */\r
-#define SDMMC_MINTSTS_RXDR_Pos 5 /*!< SDMMC MINTSTS: RXDR Position */\r
-#define SDMMC_MINTSTS_RXDR_Msk (0x01UL << SDMMC_MINTSTS_RXDR_Pos) /*!< SDMMC MINTSTS: RXDR Mask */\r
-#define SDMMC_MINTSTS_RCRC_Pos 6 /*!< SDMMC MINTSTS: RCRC Position */\r
-#define SDMMC_MINTSTS_RCRC_Msk (0x01UL << SDMMC_MINTSTS_RCRC_Pos) /*!< SDMMC MINTSTS: RCRC Mask */\r
-#define SDMMC_MINTSTS_DCRC_Pos 7 /*!< SDMMC MINTSTS: DCRC Position */\r
-#define SDMMC_MINTSTS_DCRC_Msk (0x01UL << SDMMC_MINTSTS_DCRC_Pos) /*!< SDMMC MINTSTS: DCRC Mask */\r
-#define SDMMC_MINTSTS_RTO_Pos 8 /*!< SDMMC MINTSTS: RTO Position */\r
-#define SDMMC_MINTSTS_RTO_Msk (0x01UL << SDMMC_MINTSTS_RTO_Pos) /*!< SDMMC MINTSTS: RTO Mask */\r
-#define SDMMC_MINTSTS_DRTO_Pos 9 /*!< SDMMC MINTSTS: DRTO Position */\r
-#define SDMMC_MINTSTS_DRTO_Msk (0x01UL << SDMMC_MINTSTS_DRTO_Pos) /*!< SDMMC MINTSTS: DRTO Mask */\r
-#define SDMMC_MINTSTS_HTO_Pos 10 /*!< SDMMC MINTSTS: HTO Position */\r
-#define SDMMC_MINTSTS_HTO_Msk (0x01UL << SDMMC_MINTSTS_HTO_Pos) /*!< SDMMC MINTSTS: HTO Mask */\r
-#define SDMMC_MINTSTS_FRUN_Pos 11 /*!< SDMMC MINTSTS: FRUN Position */\r
-#define SDMMC_MINTSTS_FRUN_Msk (0x01UL << SDMMC_MINTSTS_FRUN_Pos) /*!< SDMMC MINTSTS: FRUN Mask */\r
-#define SDMMC_MINTSTS_HLE_Pos 12 /*!< SDMMC MINTSTS: HLE Position */\r
-#define SDMMC_MINTSTS_HLE_Msk (0x01UL << SDMMC_MINTSTS_HLE_Pos) /*!< SDMMC MINTSTS: HLE Mask */\r
-#define SDMMC_MINTSTS_SBE_Pos 13 /*!< SDMMC MINTSTS: SBE Position */\r
-#define SDMMC_MINTSTS_SBE_Msk (0x01UL << SDMMC_MINTSTS_SBE_Pos) /*!< SDMMC MINTSTS: SBE Mask */\r
-#define SDMMC_MINTSTS_ACD_Pos 14 /*!< SDMMC MINTSTS: ACD Position */\r
-#define SDMMC_MINTSTS_ACD_Msk (0x01UL << SDMMC_MINTSTS_ACD_Pos) /*!< SDMMC MINTSTS: ACD Mask */\r
-#define SDMMC_MINTSTS_EBE_Pos 15 /*!< SDMMC MINTSTS: EBE Position */\r
-#define SDMMC_MINTSTS_EBE_Msk (0x01UL << SDMMC_MINTSTS_EBE_Pos) /*!< SDMMC MINTSTS: EBE Mask */\r
-#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */\r
-#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask */\r
-\r
-// -------------------------------------- SDMMC_RINTSTS -----------------------------------------\r
-#define SDMMC_RINTSTS_CDET_Pos 0 /*!< SDMMC RINTSTS: CDET Position */\r
-#define SDMMC_RINTSTS_CDET_Msk (0x01UL << SDMMC_RINTSTS_CDET_Pos) /*!< SDMMC RINTSTS: CDET Mask */\r
-#define SDMMC_RINTSTS_RE_Pos 1 /*!< SDMMC RINTSTS: RE Position */\r
-#define SDMMC_RINTSTS_RE_Msk (0x01UL << SDMMC_RINTSTS_RE_Pos) /*!< SDMMC RINTSTS: RE Mask */\r
-#define SDMMC_RINTSTS_CDONE_Pos 2 /*!< SDMMC RINTSTS: CDONE Position */\r
-#define SDMMC_RINTSTS_CDONE_Msk (0x01UL << SDMMC_RINTSTS_CDONE_Pos) /*!< SDMMC RINTSTS: CDONE Mask */\r
-#define SDMMC_RINTSTS_DTO_Pos 3 /*!< SDMMC RINTSTS: DTO Position */\r
-#define SDMMC_RINTSTS_DTO_Msk (0x01UL << SDMMC_RINTSTS_DTO_Pos) /*!< SDMMC RINTSTS: DTO Mask */\r
-#define SDMMC_RINTSTS_TXDR_Pos 4 /*!< SDMMC RINTSTS: TXDR Position */\r
-#define SDMMC_RINTSTS_TXDR_Msk (0x01UL << SDMMC_RINTSTS_TXDR_Pos) /*!< SDMMC RINTSTS: TXDR Mask */\r
-#define SDMMC_RINTSTS_RXDR_Pos 5 /*!< SDMMC RINTSTS: RXDR Position */\r
-#define SDMMC_RINTSTS_RXDR_Msk (0x01UL << SDMMC_RINTSTS_RXDR_Pos) /*!< SDMMC RINTSTS: RXDR Mask */\r
-#define SDMMC_RINTSTS_RCRC_Pos 6 /*!< SDMMC RINTSTS: RCRC Position */\r
-#define SDMMC_RINTSTS_RCRC_Msk (0x01UL << SDMMC_RINTSTS_RCRC_Pos) /*!< SDMMC RINTSTS: RCRC Mask */\r
-#define SDMMC_RINTSTS_DCRC_Pos 7 /*!< SDMMC RINTSTS: DCRC Position */\r
-#define SDMMC_RINTSTS_DCRC_Msk (0x01UL << SDMMC_RINTSTS_DCRC_Pos) /*!< SDMMC RINTSTS: DCRC Mask */\r
-#define SDMMC_RINTSTS_RTO_BAR_Pos 8 /*!< SDMMC RINTSTS: RTO_BAR Position */\r
-#define SDMMC_RINTSTS_RTO_BAR_Msk (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos) /*!< SDMMC RINTSTS: RTO_BAR Mask */\r
-#define SDMMC_RINTSTS_DRTO_BDS_Pos 9 /*!< SDMMC RINTSTS: DRTO_BDS Position */\r
-#define SDMMC_RINTSTS_DRTO_BDS_Msk (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos) /*!< SDMMC RINTSTS: DRTO_BDS Mask */\r
-#define SDMMC_RINTSTS_HTO_Pos 10 /*!< SDMMC RINTSTS: HTO Position */\r
-#define SDMMC_RINTSTS_HTO_Msk (0x01UL << SDMMC_RINTSTS_HTO_Pos) /*!< SDMMC RINTSTS: HTO Mask */\r
-#define SDMMC_RINTSTS_FRUN_Pos 11 /*!< SDMMC RINTSTS: FRUN Position */\r
-#define SDMMC_RINTSTS_FRUN_Msk (0x01UL << SDMMC_RINTSTS_FRUN_Pos) /*!< SDMMC RINTSTS: FRUN Mask */\r
-#define SDMMC_RINTSTS_HLE_Pos 12 /*!< SDMMC RINTSTS: HLE Position */\r
-#define SDMMC_RINTSTS_HLE_Msk (0x01UL << SDMMC_RINTSTS_HLE_Pos) /*!< SDMMC RINTSTS: HLE Mask */\r
-#define SDMMC_RINTSTS_SBE_Pos 13 /*!< SDMMC RINTSTS: SBE Position */\r
-#define SDMMC_RINTSTS_SBE_Msk (0x01UL << SDMMC_RINTSTS_SBE_Pos) /*!< SDMMC RINTSTS: SBE Mask */\r
-#define SDMMC_RINTSTS_ACD_Pos 14 /*!< SDMMC RINTSTS: ACD Position */\r
-#define SDMMC_RINTSTS_ACD_Msk (0x01UL << SDMMC_RINTSTS_ACD_Pos) /*!< SDMMC RINTSTS: ACD Mask */\r
-#define SDMMC_RINTSTS_EBE_Pos 15 /*!< SDMMC RINTSTS: EBE Position */\r
-#define SDMMC_RINTSTS_EBE_Msk (0x01UL << SDMMC_RINTSTS_EBE_Pos) /*!< SDMMC RINTSTS: EBE Mask */\r
-#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */\r
-#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask */\r
-\r
-// -------------------------------------- SDMMC_STATUS ------------------------------------------\r
-#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos 0 /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */\r
-#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */\r
-#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos 1 /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */\r
-#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */\r
-#define SDMMC_STATUS_FIFO_EMPTY_Pos 2 /*!< SDMMC STATUS: FIFO_EMPTY Position */\r
-#define SDMMC_STATUS_FIFO_EMPTY_Msk (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos) /*!< SDMMC STATUS: FIFO_EMPTY Mask */\r
-#define SDMMC_STATUS_FIFO_FULL_Pos 3 /*!< SDMMC STATUS: FIFO_FULL Position */\r
-#define SDMMC_STATUS_FIFO_FULL_Msk (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos) /*!< SDMMC STATUS: FIFO_FULL Mask */\r
-#define SDMMC_STATUS_CMDFSMSTATES_Pos 4 /*!< SDMMC STATUS: CMDFSMSTATES Position */\r
-#define SDMMC_STATUS_CMDFSMSTATES_Msk (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos) /*!< SDMMC STATUS: CMDFSMSTATES Mask */\r
-#define SDMMC_STATUS_DATA_3_STATUS_Pos 8 /*!< SDMMC STATUS: DATA_3_STATUS Position */\r
-#define SDMMC_STATUS_DATA_3_STATUS_Msk (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos) /*!< SDMMC STATUS: DATA_3_STATUS Mask */\r
-#define SDMMC_STATUS_DATA_BUSY_Pos 9 /*!< SDMMC STATUS: DATA_BUSY Position */\r
-#define SDMMC_STATUS_DATA_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos) /*!< SDMMC STATUS: DATA_BUSY Mask */\r
-#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos 10 /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */\r
-#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos) /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */\r
-#define SDMMC_STATUS_RESPONSE_INDEX_Pos 11 /*!< SDMMC STATUS: RESPONSE_INDEX Position */\r
-#define SDMMC_STATUS_RESPONSE_INDEX_Msk (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos) /*!< SDMMC STATUS: RESPONSE_INDEX Mask */\r
-#define SDMMC_STATUS_FIFO_COUNT_Pos 17 /*!< SDMMC STATUS: FIFO_COUNT Position */\r
-#define SDMMC_STATUS_FIFO_COUNT_Msk (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos) /*!< SDMMC STATUS: FIFO_COUNT Mask */\r
-#define SDMMC_STATUS_DMA_ACK_Pos 30 /*!< SDMMC STATUS: DMA_ACK Position */\r
-#define SDMMC_STATUS_DMA_ACK_Msk (0x01UL << SDMMC_STATUS_DMA_ACK_Pos) /*!< SDMMC STATUS: DMA_ACK Mask */\r
-#define SDMMC_STATUS_DMA_REQ_Pos 31 /*!< SDMMC STATUS: DMA_REQ Position */\r
-#define SDMMC_STATUS_DMA_REQ_Msk (0x01UL << SDMMC_STATUS_DMA_REQ_Pos) /*!< SDMMC STATUS: DMA_REQ Mask */\r
-\r
-// -------------------------------------- SDMMC_FIFOTH ------------------------------------------\r
-#define SDMMC_FIFOTH_TX_WMARK_Pos 0 /*!< SDMMC FIFOTH: TX_WMARK Position */\r
-#define SDMMC_FIFOTH_TX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos) /*!< SDMMC FIFOTH: TX_WMARK Mask */\r
-#define SDMMC_FIFOTH_RX_WMARK_Pos 16 /*!< SDMMC FIFOTH: RX_WMARK Position */\r
-#define SDMMC_FIFOTH_RX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos) /*!< SDMMC FIFOTH: RX_WMARK Mask */\r
-#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos 28 /*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Position */\r
-#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */\r
-\r
-// -------------------------------------- SDMMC_CDETECT -----------------------------------------\r
-#define SDMMC_CDETECT_CARD_DETECT_N_Pos 0 /*!< SDMMC CDETECT: CARD_DETECT_N Position */\r
-#define SDMMC_CDETECT_CARD_DETECT_N_Msk (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos) /*!< SDMMC CDETECT: CARD_DETECT_N Mask */\r
-\r
-// -------------------------------------- SDMMC_WRTPRT ------------------------------------------\r
-#define SDMMC_WRTPRT_WRITE_PROTECT_Pos 0 /*!< SDMMC WRTPRT: WRITE_PROTECT Position */\r
-#define SDMMC_WRTPRT_WRITE_PROTECT_Msk (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos) /*!< SDMMC WRTPRT: WRITE_PROTECT Mask */\r
-\r
-// --------------------------------------- SDMMC_GPIO -------------------------------------------\r
-#define SDMMC_GPIO_GPI_Pos 0 /*!< SDMMC GPIO: GPI Position */\r
-#define SDMMC_GPIO_GPI_Msk (0x000000ffUL << SDMMC_GPIO_GPI_Pos) /*!< SDMMC GPIO: GPI Mask */\r
-#define SDMMC_GPIO_GPO_Pos 8 /*!< SDMMC GPIO: GPO Position */\r
-#define SDMMC_GPIO_GPO_Msk (0x0000ffffUL << SDMMC_GPIO_GPO_Pos) /*!< SDMMC GPIO: GPO Mask */\r
-\r
-// -------------------------------------- SDMMC_TCBCNT ------------------------------------------\r
-#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos 0 /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */\r
-#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos) /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */\r
-\r
-// -------------------------------------- SDMMC_TBBCNT ------------------------------------------\r
-#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos 0 /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */\r
-#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos) /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */\r
-\r
-// -------------------------------------- SDMMC_DEBNCE ------------------------------------------\r
-#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos 0 /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */\r
-#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos) /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask */\r
-\r
-// --------------------------------------- SDMMC_USRID ------------------------------------------\r
-#define SDMMC_USRID_USRID_Pos 0 /*!< SDMMC USRID: USRID Position */\r
-#define SDMMC_USRID_USRID_Msk (0xffffffffUL << SDMMC_USRID_USRID_Pos) /*!< SDMMC USRID: USRID Mask */\r
-\r
-// --------------------------------------- SDMMC_VERID ------------------------------------------\r
-#define SDMMC_VERID_VERID_Pos 0 /*!< SDMMC VERID: VERID Position */\r
-#define SDMMC_VERID_VERID_Msk (0xffffffffUL << SDMMC_VERID_VERID_Pos) /*!< SDMMC VERID: VERID Mask */\r
-\r
-// -------------------------------------- SDMMC_UHS_REG -----------------------------------------\r
-#define SDMMC_UHS_REG_VOLT_REG_Pos 0 /*!< SDMMC UHS_REG: VOLT_REG Position */\r
-#define SDMMC_UHS_REG_VOLT_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos) /*!< SDMMC UHS_REG: VOLT_REG Mask */\r
-#define SDMMC_UHS_REG_DDR_REG_Pos 16 /*!< SDMMC UHS_REG: DDR_REG Position */\r
-#define SDMMC_UHS_REG_DDR_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos) /*!< SDMMC UHS_REG: DDR_REG Mask */\r
-\r
-// --------------------------------------- SDMMC_RST_N ------------------------------------------\r
-#define SDMMC_RST_N_CARD_RESET_Pos 0 /*!< SDMMC RST_N: CARD_RESET Position */\r
-#define SDMMC_RST_N_CARD_RESET_Msk (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos) /*!< SDMMC RST_N: CARD_RESET Mask */\r
-\r
-// --------------------------------------- SDMMC_BMOD -------------------------------------------\r
-#define SDMMC_BMOD_SWR_Pos 0 /*!< SDMMC BMOD: SWR Position */\r
-#define SDMMC_BMOD_SWR_Msk (0x01UL << SDMMC_BMOD_SWR_Pos) /*!< SDMMC BMOD: SWR Mask */\r
-#define SDMMC_BMOD_FB_Pos 1 /*!< SDMMC BMOD: FB Position */\r
-#define SDMMC_BMOD_FB_Msk (0x01UL << SDMMC_BMOD_FB_Pos) /*!< SDMMC BMOD: FB Mask */\r
-#define SDMMC_BMOD_DSL_Pos 2 /*!< SDMMC BMOD: DSL Position */\r
-#define SDMMC_BMOD_DSL_Msk (0x1fUL << SDMMC_BMOD_DSL_Pos) /*!< SDMMC BMOD: DSL Mask */\r
-#define SDMMC_BMOD_DE_Pos 7 /*!< SDMMC BMOD: DE Position */\r
-#define SDMMC_BMOD_DE_Msk (0x01UL << SDMMC_BMOD_DE_Pos) /*!< SDMMC BMOD: DE Mask */\r
-#define SDMMC_BMOD_PBL_Pos 8 /*!< SDMMC BMOD: PBL Position */\r
-#define SDMMC_BMOD_PBL_Msk (0x07UL << SDMMC_BMOD_PBL_Pos) /*!< SDMMC BMOD: PBL Mask */\r
-\r
-// -------------------------------------- SDMMC_PLDMND ------------------------------------------\r
-#define SDMMC_PLDMND_PD_Pos 0 /*!< SDMMC PLDMND: PD Position */\r
-#define SDMMC_PLDMND_PD_Msk (0xffffffffUL << SDMMC_PLDMND_PD_Pos) /*!< SDMMC PLDMND: PD Mask */\r
-\r
-// -------------------------------------- SDMMC_DBADDR ------------------------------------------\r
-#define SDMMC_DBADDR_SDL_Pos 0 /*!< SDMMC DBADDR: SDL Position */\r
-#define SDMMC_DBADDR_SDL_Msk (0xffffffffUL << SDMMC_DBADDR_SDL_Pos) /*!< SDMMC DBADDR: SDL Mask */\r
-\r
-// --------------------------------------- SDMMC_IDSTS ------------------------------------------\r
-#define SDMMC_IDSTS_TI_Pos 0 /*!< SDMMC IDSTS: TI Position */\r
-#define SDMMC_IDSTS_TI_Msk (0x01UL << SDMMC_IDSTS_TI_Pos) /*!< SDMMC IDSTS: TI Mask */\r
-#define SDMMC_IDSTS_RI_Pos 1 /*!< SDMMC IDSTS: RI Position */\r
-#define SDMMC_IDSTS_RI_Msk (0x01UL << SDMMC_IDSTS_RI_Pos) /*!< SDMMC IDSTS: RI Mask */\r
-#define SDMMC_IDSTS_FBE_Pos 2 /*!< SDMMC IDSTS: FBE Position */\r
-#define SDMMC_IDSTS_FBE_Msk (0x01UL << SDMMC_IDSTS_FBE_Pos) /*!< SDMMC IDSTS: FBE Mask */\r
-#define SDMMC_IDSTS_DU_Pos 4 /*!< SDMMC IDSTS: DU Position */\r
-#define SDMMC_IDSTS_DU_Msk (0x01UL << SDMMC_IDSTS_DU_Pos) /*!< SDMMC IDSTS: DU Mask */\r
-#define SDMMC_IDSTS_CES_Pos 5 /*!< SDMMC IDSTS: CES Position */\r
-#define SDMMC_IDSTS_CES_Msk (0x01UL << SDMMC_IDSTS_CES_Pos) /*!< SDMMC IDSTS: CES Mask */\r
-#define SDMMC_IDSTS_NIS_Pos 8 /*!< SDMMC IDSTS: NIS Position */\r
-#define SDMMC_IDSTS_NIS_Msk (0x01UL << SDMMC_IDSTS_NIS_Pos) /*!< SDMMC IDSTS: NIS Mask */\r
-#define SDMMC_IDSTS_AIS_Pos 9 /*!< SDMMC IDSTS: AIS Position */\r
-#define SDMMC_IDSTS_AIS_Msk (0x01UL << SDMMC_IDSTS_AIS_Pos) /*!< SDMMC IDSTS: AIS Mask */\r
-#define SDMMC_IDSTS_EB_Pos 10 /*!< SDMMC IDSTS: EB Position */\r
-#define SDMMC_IDSTS_EB_Msk (0x07UL << SDMMC_IDSTS_EB_Pos) /*!< SDMMC IDSTS: EB Mask */\r
-#define SDMMC_IDSTS_FSM_Pos 13 /*!< SDMMC IDSTS: FSM Position */\r
-#define SDMMC_IDSTS_FSM_Msk (0x0fUL << SDMMC_IDSTS_FSM_Pos) /*!< SDMMC IDSTS: FSM Mask */\r
-\r
-// -------------------------------------- SDMMC_IDINTEN -----------------------------------------\r
-#define SDMMC_IDINTEN_TI_Pos 0 /*!< SDMMC IDINTEN: TI Position */\r
-#define SDMMC_IDINTEN_TI_Msk (0x01UL << SDMMC_IDINTEN_TI_Pos) /*!< SDMMC IDINTEN: TI Mask */\r
-#define SDMMC_IDINTEN_RI_Pos 1 /*!< SDMMC IDINTEN: RI Position */\r
-#define SDMMC_IDINTEN_RI_Msk (0x01UL << SDMMC_IDINTEN_RI_Pos) /*!< SDMMC IDINTEN: RI Mask */\r
-#define SDMMC_IDINTEN_FBE_Pos 2 /*!< SDMMC IDINTEN: FBE Position */\r
-#define SDMMC_IDINTEN_FBE_Msk (0x01UL << SDMMC_IDINTEN_FBE_Pos) /*!< SDMMC IDINTEN: FBE Mask */\r
-#define SDMMC_IDINTEN_DU_Pos 4 /*!< SDMMC IDINTEN: DU Position */\r
-#define SDMMC_IDINTEN_DU_Msk (0x01UL << SDMMC_IDINTEN_DU_Pos) /*!< SDMMC IDINTEN: DU Mask */\r
-#define SDMMC_IDINTEN_CES_Pos 5 /*!< SDMMC IDINTEN: CES Position */\r
-#define SDMMC_IDINTEN_CES_Msk (0x01UL << SDMMC_IDINTEN_CES_Pos) /*!< SDMMC IDINTEN: CES Mask */\r
-#define SDMMC_IDINTEN_NIS_Pos 8 /*!< SDMMC IDINTEN: NIS Position */\r
-#define SDMMC_IDINTEN_NIS_Msk (0x01UL << SDMMC_IDINTEN_NIS_Pos) /*!< SDMMC IDINTEN: NIS Mask */\r
-#define SDMMC_IDINTEN_AIS_Pos 9 /*!< SDMMC IDINTEN: AIS Position */\r
-#define SDMMC_IDINTEN_AIS_Msk (0x01UL << SDMMC_IDINTEN_AIS_Pos) /*!< SDMMC IDINTEN: AIS Mask */\r
-\r
-// -------------------------------------- SDMMC_DSCADDR -----------------------------------------\r
-#define SDMMC_DSCADDR_HDA_Pos 0 /*!< SDMMC DSCADDR: HDA Position */\r
-#define SDMMC_DSCADDR_HDA_Msk (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos) /*!< SDMMC DSCADDR: HDA Mask */\r
-\r
-// -------------------------------------- SDMMC_BUFADDR -----------------------------------------\r
-#define SDMMC_BUFADDR_HBA_Pos 0 /*!< SDMMC BUFADDR: HBA Position */\r
-#define SDMMC_BUFADDR_HBA_Msk (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos) /*!< SDMMC BUFADDR: HBA Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- EMC Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- EMC_CONTROL ------------------------------------------\r
-#define EMC_CONTROL_E_Pos 0 /*!< EMC CONTROL: E Position */\r
-#define EMC_CONTROL_E_Msk (0x01UL << EMC_CONTROL_E_Pos) /*!< EMC CONTROL: E Mask */\r
-#define EMC_CONTROL_M_Pos 1 /*!< EMC CONTROL: M Position */\r
-#define EMC_CONTROL_M_Msk (0x01UL << EMC_CONTROL_M_Pos) /*!< EMC CONTROL: M Mask */\r
-#define EMC_CONTROL_L_Pos 2 /*!< EMC CONTROL: L Position */\r
-#define EMC_CONTROL_L_Msk (0x01UL << EMC_CONTROL_L_Pos) /*!< EMC CONTROL: L Mask */\r
-\r
-// --------------------------------------- EMC_STATUS -------------------------------------------\r
-#define EMC_STATUS_B_Pos 0 /*!< EMC STATUS: B Position */\r
-#define EMC_STATUS_B_Msk (0x01UL << EMC_STATUS_B_Pos) /*!< EMC STATUS: B Mask */\r
-#define EMC_STATUS_S_Pos 1 /*!< EMC STATUS: S Position */\r
-#define EMC_STATUS_S_Msk (0x01UL << EMC_STATUS_S_Pos) /*!< EMC STATUS: S Mask */\r
-#define EMC_STATUS_SA_Pos 2 /*!< EMC STATUS: SA Position */\r
-#define EMC_STATUS_SA_Msk (0x01UL << EMC_STATUS_SA_Pos) /*!< EMC STATUS: SA Mask */\r
-\r
-// --------------------------------------- EMC_CONFIG -------------------------------------------\r
-#define EMC_CONFIG_EM_Pos 0 /*!< EMC CONFIG: EM Position */\r
-#define EMC_CONFIG_EM_Msk (0x01UL << EMC_CONFIG_EM_Pos) /*!< EMC CONFIG: EM Mask */\r
-#define EMC_CONFIG_CR_Pos 8 /*!< EMC CONFIG: CR Position */\r
-#define EMC_CONFIG_CR_Msk (0x01UL << EMC_CONFIG_CR_Pos) /*!< EMC CONFIG: CR Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICCONTROL ---------------------------------------\r
-#define EMC_DYNAMICCONTROL_CE_Pos 0 /*!< EMC DYNAMICCONTROL: CE Position */\r
-#define EMC_DYNAMICCONTROL_CE_Msk (0x01UL << EMC_DYNAMICCONTROL_CE_Pos) /*!< EMC DYNAMICCONTROL: CE Mask */\r
-#define EMC_DYNAMICCONTROL_CS_Pos 1 /*!< EMC DYNAMICCONTROL: CS Position */\r
-#define EMC_DYNAMICCONTROL_CS_Msk (0x01UL << EMC_DYNAMICCONTROL_CS_Pos) /*!< EMC DYNAMICCONTROL: CS Mask */\r
-#define EMC_DYNAMICCONTROL_SR_Pos 2 /*!< EMC DYNAMICCONTROL: SR Position */\r
-#define EMC_DYNAMICCONTROL_SR_Msk (0x01UL << EMC_DYNAMICCONTROL_SR_Pos) /*!< EMC DYNAMICCONTROL: SR Mask */\r
-#define EMC_DYNAMICCONTROL_MMC_Pos 5 /*!< EMC DYNAMICCONTROL: MMC Position */\r
-#define EMC_DYNAMICCONTROL_MMC_Msk (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos) /*!< EMC DYNAMICCONTROL: MMC Mask */\r
-#define EMC_DYNAMICCONTROL_I_Pos 7 /*!< EMC DYNAMICCONTROL: I Position */\r
-#define EMC_DYNAMICCONTROL_I_Msk (0x03UL << EMC_DYNAMICCONTROL_I_Pos) /*!< EMC DYNAMICCONTROL: I Mask */\r
-#define EMC_DYNAMICCONTROL_DP_Pos 13 /*!< EMC DYNAMICCONTROL: DP Position */\r
-#define EMC_DYNAMICCONTROL_DP_Msk (0x01UL << EMC_DYNAMICCONTROL_DP_Pos) /*!< EMC DYNAMICCONTROL: DP Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICREFRESH ---------------------------------------\r
-#define EMC_DYNAMICREFRESH_REFRESH_Pos 0 /*!< EMC DYNAMICREFRESH: REFRESH Position */\r
-#define EMC_DYNAMICREFRESH_REFRESH_Msk (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos) /*!< EMC DYNAMICREFRESH: REFRESH Mask */\r
-\r
-// ---------------------------------- EMC_DYNAMICREADCONFIG -------------------------------------\r
-#define EMC_DYNAMICREADCONFIG_RD_Pos 0 /*!< EMC DYNAMICREADCONFIG: RD Position */\r
-#define EMC_DYNAMICREADCONFIG_RD_Msk (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos) /*!< EMC DYNAMICREADCONFIG: RD Mask */\r
-\r
-// -------------------------------------- EMC_DYNAMICRP -----------------------------------------\r
-#define EMC_DYNAMICRP_tRP_Pos 0 /*!< EMC DYNAMICRP: tRP Position */\r
-#define EMC_DYNAMICRP_tRP_Msk (0x0fUL << EMC_DYNAMICRP_tRP_Pos) /*!< EMC DYNAMICRP: tRP Mask */\r
-\r
-// ------------------------------------- EMC_DYNAMICRAS -----------------------------------------\r
-#define EMC_DYNAMICRAS_tRAS_Pos 0 /*!< EMC DYNAMICRAS: tRAS Position */\r
-#define EMC_DYNAMICRAS_tRAS_Msk (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos) /*!< EMC DYNAMICRAS: tRAS Mask */\r
-\r
-// ------------------------------------- EMC_DYNAMICSREX ----------------------------------------\r
-#define EMC_DYNAMICSREX_tSREX_Pos 0 /*!< EMC DYNAMICSREX: tSREX Position */\r
-#define EMC_DYNAMICSREX_tSREX_Msk (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos) /*!< EMC DYNAMICSREX: tSREX Mask */\r
-\r
-// ------------------------------------- EMC_DYNAMICAPR -----------------------------------------\r
-#define EMC_DYNAMICAPR_tAPR_Pos 0 /*!< EMC DYNAMICAPR: tAPR Position */\r
-#define EMC_DYNAMICAPR_tAPR_Msk (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos) /*!< EMC DYNAMICAPR: tAPR Mask */\r
-\r
-// ------------------------------------- EMC_DYNAMICDAL -----------------------------------------\r
-#define EMC_DYNAMICDAL_tDAL_Pos 0 /*!< EMC DYNAMICDAL: tDAL Position */\r
-#define EMC_DYNAMICDAL_tDAL_Msk (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos) /*!< EMC DYNAMICDAL: tDAL Mask */\r
-\r
-// -------------------------------------- EMC_DYNAMICWR -----------------------------------------\r
-#define EMC_DYNAMICWR_tWR_Pos 0 /*!< EMC DYNAMICWR: tWR Position */\r
-#define EMC_DYNAMICWR_tWR_Msk (0x0fUL << EMC_DYNAMICWR_tWR_Pos) /*!< EMC DYNAMICWR: tWR Mask */\r
-\r
-// -------------------------------------- EMC_DYNAMICRC -----------------------------------------\r
-#define EMC_DYNAMICRC_tRC_Pos 0 /*!< EMC DYNAMICRC: tRC Position */\r
-#define EMC_DYNAMICRC_tRC_Msk (0x1fUL << EMC_DYNAMICRC_tRC_Pos) /*!< EMC DYNAMICRC: tRC Mask */\r
-\r
-// ------------------------------------- EMC_DYNAMICRFC -----------------------------------------\r
-#define EMC_DYNAMICRFC_tRFC_Pos 0 /*!< EMC DYNAMICRFC: tRFC Position */\r
-#define EMC_DYNAMICRFC_tRFC_Msk (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos) /*!< EMC DYNAMICRFC: tRFC Mask */\r
-\r
-// ------------------------------------- EMC_DYNAMICXSR -----------------------------------------\r
-#define EMC_DYNAMICXSR_tXSR_Pos 0 /*!< EMC DYNAMICXSR: tXSR Position */\r
-#define EMC_DYNAMICXSR_tXSR_Msk (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos) /*!< EMC DYNAMICXSR: tXSR Mask */\r
-\r
-// ------------------------------------- EMC_DYNAMICRRD -----------------------------------------\r
-#define EMC_DYNAMICRRD_tRRD_Pos 0 /*!< EMC DYNAMICRRD: tRRD Position */\r
-#define EMC_DYNAMICRRD_tRRD_Msk (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos) /*!< EMC DYNAMICRRD: tRRD Mask */\r
-\r
-// ------------------------------------- EMC_DYNAMICMRD -----------------------------------------\r
-#define EMC_DYNAMICMRD_tMRD_Pos 0 /*!< EMC DYNAMICMRD: tMRD Position */\r
-#define EMC_DYNAMICMRD_tMRD_Msk (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos) /*!< EMC DYNAMICMRD: tMRD Mask */\r
-\r
-// --------------------------------- EMC_STATICEXTENDEDWAIT -------------------------------------\r
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos 0 /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */\r
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos) /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICCONFIG0 ---------------------------------------\r
-#define EMC_DYNAMICCONFIG0_MD_Pos 3 /*!< EMC DYNAMICCONFIG0: MD Position */\r
-#define EMC_DYNAMICCONFIG0_MD_Msk (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos) /*!< EMC DYNAMICCONFIG0: MD Mask */\r
-#define EMC_DYNAMICCONFIG0_AM0_Pos 7 /*!< EMC DYNAMICCONFIG0: AM0 Position */\r
-#define EMC_DYNAMICCONFIG0_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos) /*!< EMC DYNAMICCONFIG0: AM0 Mask */\r
-#define EMC_DYNAMICCONFIG0_AM1_Pos 14 /*!< EMC DYNAMICCONFIG0: AM1 Position */\r
-#define EMC_DYNAMICCONFIG0_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos) /*!< EMC DYNAMICCONFIG0: AM1 Mask */\r
-#define EMC_DYNAMICCONFIG0_B_Pos 19 /*!< EMC DYNAMICCONFIG0: B Position */\r
-#define EMC_DYNAMICCONFIG0_B_Msk (0x01UL << EMC_DYNAMICCONFIG0_B_Pos) /*!< EMC DYNAMICCONFIG0: B Mask */\r
-#define EMC_DYNAMICCONFIG0_P_Pos 20 /*!< EMC DYNAMICCONFIG0: P Position */\r
-#define EMC_DYNAMICCONFIG0_P_Msk (0x01UL << EMC_DYNAMICCONFIG0_P_Pos) /*!< EMC DYNAMICCONFIG0: P Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICRASCAS0 ---------------------------------------\r
-#define EMC_DYNAMICRASCAS0_RAS_Pos 0 /*!< EMC DYNAMICRASCAS0: RAS Position */\r
-#define EMC_DYNAMICRASCAS0_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos) /*!< EMC DYNAMICRASCAS0: RAS Mask */\r
-#define EMC_DYNAMICRASCAS0_CAS_Pos 8 /*!< EMC DYNAMICRASCAS0: CAS Position */\r
-#define EMC_DYNAMICRASCAS0_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos) /*!< EMC DYNAMICRASCAS0: CAS Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICCONFIG1 ---------------------------------------\r
-#define EMC_DYNAMICCONFIG1_MD_Pos 3 /*!< EMC DYNAMICCONFIG1: MD Position */\r
-#define EMC_DYNAMICCONFIG1_MD_Msk (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos) /*!< EMC DYNAMICCONFIG1: MD Mask */\r
-#define EMC_DYNAMICCONFIG1_AM0_Pos 7 /*!< EMC DYNAMICCONFIG1: AM0 Position */\r
-#define EMC_DYNAMICCONFIG1_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos) /*!< EMC DYNAMICCONFIG1: AM0 Mask */\r
-#define EMC_DYNAMICCONFIG1_AM1_Pos 14 /*!< EMC DYNAMICCONFIG1: AM1 Position */\r
-#define EMC_DYNAMICCONFIG1_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos) /*!< EMC DYNAMICCONFIG1: AM1 Mask */\r
-#define EMC_DYNAMICCONFIG1_B_Pos 19 /*!< EMC DYNAMICCONFIG1: B Position */\r
-#define EMC_DYNAMICCONFIG1_B_Msk (0x01UL << EMC_DYNAMICCONFIG1_B_Pos) /*!< EMC DYNAMICCONFIG1: B Mask */\r
-#define EMC_DYNAMICCONFIG1_P_Pos 20 /*!< EMC DYNAMICCONFIG1: P Position */\r
-#define EMC_DYNAMICCONFIG1_P_Msk (0x01UL << EMC_DYNAMICCONFIG1_P_Pos) /*!< EMC DYNAMICCONFIG1: P Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICRASCAS1 ---------------------------------------\r
-#define EMC_DYNAMICRASCAS1_RAS_Pos 0 /*!< EMC DYNAMICRASCAS1: RAS Position */\r
-#define EMC_DYNAMICRASCAS1_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos) /*!< EMC DYNAMICRASCAS1: RAS Mask */\r
-#define EMC_DYNAMICRASCAS1_CAS_Pos 8 /*!< EMC DYNAMICRASCAS1: CAS Position */\r
-#define EMC_DYNAMICRASCAS1_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos) /*!< EMC DYNAMICRASCAS1: CAS Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICCONFIG2 ---------------------------------------\r
-#define EMC_DYNAMICCONFIG2_MD_Pos 3 /*!< EMC DYNAMICCONFIG2: MD Position */\r
-#define EMC_DYNAMICCONFIG2_MD_Msk (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos) /*!< EMC DYNAMICCONFIG2: MD Mask */\r
-#define EMC_DYNAMICCONFIG2_AM0_Pos 7 /*!< EMC DYNAMICCONFIG2: AM0 Position */\r
-#define EMC_DYNAMICCONFIG2_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos) /*!< EMC DYNAMICCONFIG2: AM0 Mask */\r
-#define EMC_DYNAMICCONFIG2_AM1_Pos 14 /*!< EMC DYNAMICCONFIG2: AM1 Position */\r
-#define EMC_DYNAMICCONFIG2_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos) /*!< EMC DYNAMICCONFIG2: AM1 Mask */\r
-#define EMC_DYNAMICCONFIG2_B_Pos 19 /*!< EMC DYNAMICCONFIG2: B Position */\r
-#define EMC_DYNAMICCONFIG2_B_Msk (0x01UL << EMC_DYNAMICCONFIG2_B_Pos) /*!< EMC DYNAMICCONFIG2: B Mask */\r
-#define EMC_DYNAMICCONFIG2_P_Pos 20 /*!< EMC DYNAMICCONFIG2: P Position */\r
-#define EMC_DYNAMICCONFIG2_P_Msk (0x01UL << EMC_DYNAMICCONFIG2_P_Pos) /*!< EMC DYNAMICCONFIG2: P Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICRASCAS2 ---------------------------------------\r
-#define EMC_DYNAMICRASCAS2_RAS_Pos 0 /*!< EMC DYNAMICRASCAS2: RAS Position */\r
-#define EMC_DYNAMICRASCAS2_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos) /*!< EMC DYNAMICRASCAS2: RAS Mask */\r
-#define EMC_DYNAMICRASCAS2_CAS_Pos 8 /*!< EMC DYNAMICRASCAS2: CAS Position */\r
-#define EMC_DYNAMICRASCAS2_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos) /*!< EMC DYNAMICRASCAS2: CAS Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICCONFIG3 ---------------------------------------\r
-#define EMC_DYNAMICCONFIG3_MD_Pos 3 /*!< EMC DYNAMICCONFIG3: MD Position */\r
-#define EMC_DYNAMICCONFIG3_MD_Msk (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos) /*!< EMC DYNAMICCONFIG3: MD Mask */\r
-#define EMC_DYNAMICCONFIG3_AM0_Pos 7 /*!< EMC DYNAMICCONFIG3: AM0 Position */\r
-#define EMC_DYNAMICCONFIG3_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos) /*!< EMC DYNAMICCONFIG3: AM0 Mask */\r
-#define EMC_DYNAMICCONFIG3_AM1_Pos 14 /*!< EMC DYNAMICCONFIG3: AM1 Position */\r
-#define EMC_DYNAMICCONFIG3_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos) /*!< EMC DYNAMICCONFIG3: AM1 Mask */\r
-#define EMC_DYNAMICCONFIG3_B_Pos 19 /*!< EMC DYNAMICCONFIG3: B Position */\r
-#define EMC_DYNAMICCONFIG3_B_Msk (0x01UL << EMC_DYNAMICCONFIG3_B_Pos) /*!< EMC DYNAMICCONFIG3: B Mask */\r
-#define EMC_DYNAMICCONFIG3_P_Pos 20 /*!< EMC DYNAMICCONFIG3: P Position */\r
-#define EMC_DYNAMICCONFIG3_P_Msk (0x01UL << EMC_DYNAMICCONFIG3_P_Pos) /*!< EMC DYNAMICCONFIG3: P Mask */\r
-\r
-// ----------------------------------- EMC_DYNAMICRASCAS3 ---------------------------------------\r
-#define EMC_DYNAMICRASCAS3_RAS_Pos 0 /*!< EMC DYNAMICRASCAS3: RAS Position */\r
-#define EMC_DYNAMICRASCAS3_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos) /*!< EMC DYNAMICRASCAS3: RAS Mask */\r
-#define EMC_DYNAMICRASCAS3_CAS_Pos 8 /*!< EMC DYNAMICRASCAS3: CAS Position */\r
-#define EMC_DYNAMICRASCAS3_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos) /*!< EMC DYNAMICRASCAS3: CAS Mask */\r
-\r
-// ------------------------------------ EMC_STATICCONFIG0 ---------------------------------------\r
-#define EMC_STATICCONFIG0_MW_Pos 0 /*!< EMC STATICCONFIG0: MW Position */\r
-#define EMC_STATICCONFIG0_MW_Msk (0x03UL << EMC_STATICCONFIG0_MW_Pos) /*!< EMC STATICCONFIG0: MW Mask */\r
-#define EMC_STATICCONFIG0_PM_Pos 3 /*!< EMC STATICCONFIG0: PM Position */\r
-#define EMC_STATICCONFIG0_PM_Msk (0x01UL << EMC_STATICCONFIG0_PM_Pos) /*!< EMC STATICCONFIG0: PM Mask */\r
-#define EMC_STATICCONFIG0_PC_Pos 6 /*!< EMC STATICCONFIG0: PC Position */\r
-#define EMC_STATICCONFIG0_PC_Msk (0x01UL << EMC_STATICCONFIG0_PC_Pos) /*!< EMC STATICCONFIG0: PC Mask */\r
-#define EMC_STATICCONFIG0_PB_Pos 7 /*!< EMC STATICCONFIG0: PB Position */\r
-#define EMC_STATICCONFIG0_PB_Msk (0x01UL << EMC_STATICCONFIG0_PB_Pos) /*!< EMC STATICCONFIG0: PB Mask */\r
-#define EMC_STATICCONFIG0_EW_Pos 8 /*!< EMC STATICCONFIG0: EW Position */\r
-#define EMC_STATICCONFIG0_EW_Msk (0x01UL << EMC_STATICCONFIG0_EW_Pos) /*!< EMC STATICCONFIG0: EW Mask */\r
-#define EMC_STATICCONFIG0_B_Pos 19 /*!< EMC STATICCONFIG0: B Position */\r
-#define EMC_STATICCONFIG0_B_Msk (0x01UL << EMC_STATICCONFIG0_B_Pos) /*!< EMC STATICCONFIG0: B Mask */\r
-#define EMC_STATICCONFIG0_P_Pos 20 /*!< EMC STATICCONFIG0: P Position */\r
-#define EMC_STATICCONFIG0_P_Msk (0x01UL << EMC_STATICCONFIG0_P_Pos) /*!< EMC STATICCONFIG0: P Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITWEN0 ---------------------------------------\r
-#define EMC_STATICWAITWEN0_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN0: WAITWEN Position */\r
-#define EMC_STATICWAITWEN0_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos) /*!< EMC STATICWAITWEN0: WAITWEN Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITOEN0 ---------------------------------------\r
-#define EMC_STATICWAITOEN0_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN0: WAITOEN Position */\r
-#define EMC_STATICWAITOEN0_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos) /*!< EMC STATICWAITOEN0: WAITOEN Mask */\r
-\r
-// ------------------------------------ EMC_STATICWAITRD0 ---------------------------------------\r
-#define EMC_STATICWAITRD0_WAITRD_Pos 0 /*!< EMC STATICWAITRD0: WAITRD Position */\r
-#define EMC_STATICWAITRD0_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos) /*!< EMC STATICWAITRD0: WAITRD Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITPAG0 ---------------------------------------\r
-#define EMC_STATICWAITPAG0_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG0: WAITPAGE Position */\r
-#define EMC_STATICWAITPAG0_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos) /*!< EMC STATICWAITPAG0: WAITPAGE Mask */\r
-\r
-// ------------------------------------ EMC_STATICWAITWR0 ---------------------------------------\r
-#define EMC_STATICWAITWR0_WAITWR_Pos 0 /*!< EMC STATICWAITWR0: WAITWR Position */\r
-#define EMC_STATICWAITWR0_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos) /*!< EMC STATICWAITWR0: WAITWR Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITTURN0 --------------------------------------\r
-#define EMC_STATICWAITTURN0_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN0: WAITTURN Position */\r
-#define EMC_STATICWAITTURN0_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos) /*!< EMC STATICWAITTURN0: WAITTURN Mask */\r
-\r
-// ------------------------------------ EMC_STATICCONFIG1 ---------------------------------------\r
-#define EMC_STATICCONFIG1_MW_Pos 0 /*!< EMC STATICCONFIG1: MW Position */\r
-#define EMC_STATICCONFIG1_MW_Msk (0x03UL << EMC_STATICCONFIG1_MW_Pos) /*!< EMC STATICCONFIG1: MW Mask */\r
-#define EMC_STATICCONFIG1_PM_Pos 3 /*!< EMC STATICCONFIG1: PM Position */\r
-#define EMC_STATICCONFIG1_PM_Msk (0x01UL << EMC_STATICCONFIG1_PM_Pos) /*!< EMC STATICCONFIG1: PM Mask */\r
-#define EMC_STATICCONFIG1_PC_Pos 6 /*!< EMC STATICCONFIG1: PC Position */\r
-#define EMC_STATICCONFIG1_PC_Msk (0x01UL << EMC_STATICCONFIG1_PC_Pos) /*!< EMC STATICCONFIG1: PC Mask */\r
-#define EMC_STATICCONFIG1_PB_Pos 7 /*!< EMC STATICCONFIG1: PB Position */\r
-#define EMC_STATICCONFIG1_PB_Msk (0x01UL << EMC_STATICCONFIG1_PB_Pos) /*!< EMC STATICCONFIG1: PB Mask */\r
-#define EMC_STATICCONFIG1_EW_Pos 8 /*!< EMC STATICCONFIG1: EW Position */\r
-#define EMC_STATICCONFIG1_EW_Msk (0x01UL << EMC_STATICCONFIG1_EW_Pos) /*!< EMC STATICCONFIG1: EW Mask */\r
-#define EMC_STATICCONFIG1_B_Pos 19 /*!< EMC STATICCONFIG1: B Position */\r
-#define EMC_STATICCONFIG1_B_Msk (0x01UL << EMC_STATICCONFIG1_B_Pos) /*!< EMC STATICCONFIG1: B Mask */\r
-#define EMC_STATICCONFIG1_P_Pos 20 /*!< EMC STATICCONFIG1: P Position */\r
-#define EMC_STATICCONFIG1_P_Msk (0x01UL << EMC_STATICCONFIG1_P_Pos) /*!< EMC STATICCONFIG1: P Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITWEN1 ---------------------------------------\r
-#define EMC_STATICWAITWEN1_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN1: WAITWEN Position */\r
-#define EMC_STATICWAITWEN1_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos) /*!< EMC STATICWAITWEN1: WAITWEN Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITOEN1 ---------------------------------------\r
-#define EMC_STATICWAITOEN1_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN1: WAITOEN Position */\r
-#define EMC_STATICWAITOEN1_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos) /*!< EMC STATICWAITOEN1: WAITOEN Mask */\r
-\r
-// ------------------------------------ EMC_STATICWAITRD1 ---------------------------------------\r
-#define EMC_STATICWAITRD1_WAITRD_Pos 0 /*!< EMC STATICWAITRD1: WAITRD Position */\r
-#define EMC_STATICWAITRD1_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos) /*!< EMC STATICWAITRD1: WAITRD Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITPAG1 ---------------------------------------\r
-#define EMC_STATICWAITPAG1_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG1: WAITPAGE Position */\r
-#define EMC_STATICWAITPAG1_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos) /*!< EMC STATICWAITPAG1: WAITPAGE Mask */\r
-\r
-// ------------------------------------ EMC_STATICWAITWR1 ---------------------------------------\r
-#define EMC_STATICWAITWR1_WAITWR_Pos 0 /*!< EMC STATICWAITWR1: WAITWR Position */\r
-#define EMC_STATICWAITWR1_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos) /*!< EMC STATICWAITWR1: WAITWR Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITTURN1 --------------------------------------\r
-#define EMC_STATICWAITTURN1_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN1: WAITTURN Position */\r
-#define EMC_STATICWAITTURN1_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos) /*!< EMC STATICWAITTURN1: WAITTURN Mask */\r
-\r
-// ------------------------------------ EMC_STATICCONFIG2 ---------------------------------------\r
-#define EMC_STATICCONFIG2_MW_Pos 0 /*!< EMC STATICCONFIG2: MW Position */\r
-#define EMC_STATICCONFIG2_MW_Msk (0x03UL << EMC_STATICCONFIG2_MW_Pos) /*!< EMC STATICCONFIG2: MW Mask */\r
-#define EMC_STATICCONFIG2_PM_Pos 3 /*!< EMC STATICCONFIG2: PM Position */\r
-#define EMC_STATICCONFIG2_PM_Msk (0x01UL << EMC_STATICCONFIG2_PM_Pos) /*!< EMC STATICCONFIG2: PM Mask */\r
-#define EMC_STATICCONFIG2_PC_Pos 6 /*!< EMC STATICCONFIG2: PC Position */\r
-#define EMC_STATICCONFIG2_PC_Msk (0x01UL << EMC_STATICCONFIG2_PC_Pos) /*!< EMC STATICCONFIG2: PC Mask */\r
-#define EMC_STATICCONFIG2_PB_Pos 7 /*!< EMC STATICCONFIG2: PB Position */\r
-#define EMC_STATICCONFIG2_PB_Msk (0x01UL << EMC_STATICCONFIG2_PB_Pos) /*!< EMC STATICCONFIG2: PB Mask */\r
-#define EMC_STATICCONFIG2_EW_Pos 8 /*!< EMC STATICCONFIG2: EW Position */\r
-#define EMC_STATICCONFIG2_EW_Msk (0x01UL << EMC_STATICCONFIG2_EW_Pos) /*!< EMC STATICCONFIG2: EW Mask */\r
-#define EMC_STATICCONFIG2_B_Pos 19 /*!< EMC STATICCONFIG2: B Position */\r
-#define EMC_STATICCONFIG2_B_Msk (0x01UL << EMC_STATICCONFIG2_B_Pos) /*!< EMC STATICCONFIG2: B Mask */\r
-#define EMC_STATICCONFIG2_P_Pos 20 /*!< EMC STATICCONFIG2: P Position */\r
-#define EMC_STATICCONFIG2_P_Msk (0x01UL << EMC_STATICCONFIG2_P_Pos) /*!< EMC STATICCONFIG2: P Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITWEN2 ---------------------------------------\r
-#define EMC_STATICWAITWEN2_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN2: WAITWEN Position */\r
-#define EMC_STATICWAITWEN2_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos) /*!< EMC STATICWAITWEN2: WAITWEN Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITOEN2 ---------------------------------------\r
-#define EMC_STATICWAITOEN2_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN2: WAITOEN Position */\r
-#define EMC_STATICWAITOEN2_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos) /*!< EMC STATICWAITOEN2: WAITOEN Mask */\r
-\r
-// ------------------------------------ EMC_STATICWAITRD2 ---------------------------------------\r
-#define EMC_STATICWAITRD2_WAITRD_Pos 0 /*!< EMC STATICWAITRD2: WAITRD Position */\r
-#define EMC_STATICWAITRD2_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos) /*!< EMC STATICWAITRD2: WAITRD Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITPAG2 ---------------------------------------\r
-#define EMC_STATICWAITPAG2_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG2: WAITPAGE Position */\r
-#define EMC_STATICWAITPAG2_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos) /*!< EMC STATICWAITPAG2: WAITPAGE Mask */\r
-\r
-// ------------------------------------ EMC_STATICWAITWR2 ---------------------------------------\r
-#define EMC_STATICWAITWR2_WAITWR_Pos 0 /*!< EMC STATICWAITWR2: WAITWR Position */\r
-#define EMC_STATICWAITWR2_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos) /*!< EMC STATICWAITWR2: WAITWR Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITTURN2 --------------------------------------\r
-#define EMC_STATICWAITTURN2_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN2: WAITTURN Position */\r
-#define EMC_STATICWAITTURN2_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos) /*!< EMC STATICWAITTURN2: WAITTURN Mask */\r
-\r
-// ------------------------------------ EMC_STATICCONFIG3 ---------------------------------------\r
-#define EMC_STATICCONFIG3_MW_Pos 0 /*!< EMC STATICCONFIG3: MW Position */\r
-#define EMC_STATICCONFIG3_MW_Msk (0x03UL << EMC_STATICCONFIG3_MW_Pos) /*!< EMC STATICCONFIG3: MW Mask */\r
-#define EMC_STATICCONFIG3_PM_Pos 3 /*!< EMC STATICCONFIG3: PM Position */\r
-#define EMC_STATICCONFIG3_PM_Msk (0x01UL << EMC_STATICCONFIG3_PM_Pos) /*!< EMC STATICCONFIG3: PM Mask */\r
-#define EMC_STATICCONFIG3_PC_Pos 6 /*!< EMC STATICCONFIG3: PC Position */\r
-#define EMC_STATICCONFIG3_PC_Msk (0x01UL << EMC_STATICCONFIG3_PC_Pos) /*!< EMC STATICCONFIG3: PC Mask */\r
-#define EMC_STATICCONFIG3_PB_Pos 7 /*!< EMC STATICCONFIG3: PB Position */\r
-#define EMC_STATICCONFIG3_PB_Msk (0x01UL << EMC_STATICCONFIG3_PB_Pos) /*!< EMC STATICCONFIG3: PB Mask */\r
-#define EMC_STATICCONFIG3_EW_Pos 8 /*!< EMC STATICCONFIG3: EW Position */\r
-#define EMC_STATICCONFIG3_EW_Msk (0x01UL << EMC_STATICCONFIG3_EW_Pos) /*!< EMC STATICCONFIG3: EW Mask */\r
-#define EMC_STATICCONFIG3_B_Pos 19 /*!< EMC STATICCONFIG3: B Position */\r
-#define EMC_STATICCONFIG3_B_Msk (0x01UL << EMC_STATICCONFIG3_B_Pos) /*!< EMC STATICCONFIG3: B Mask */\r
-#define EMC_STATICCONFIG3_P_Pos 20 /*!< EMC STATICCONFIG3: P Position */\r
-#define EMC_STATICCONFIG3_P_Msk (0x01UL << EMC_STATICCONFIG3_P_Pos) /*!< EMC STATICCONFIG3: P Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITWEN3 ---------------------------------------\r
-#define EMC_STATICWAITWEN3_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN3: WAITWEN Position */\r
-#define EMC_STATICWAITWEN3_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos) /*!< EMC STATICWAITWEN3: WAITWEN Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITOEN3 ---------------------------------------\r
-#define EMC_STATICWAITOEN3_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN3: WAITOEN Position */\r
-#define EMC_STATICWAITOEN3_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos) /*!< EMC STATICWAITOEN3: WAITOEN Mask */\r
-\r
-// ------------------------------------ EMC_STATICWAITRD3 ---------------------------------------\r
-#define EMC_STATICWAITRD3_WAITRD_Pos 0 /*!< EMC STATICWAITRD3: WAITRD Position */\r
-#define EMC_STATICWAITRD3_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos) /*!< EMC STATICWAITRD3: WAITRD Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITPAG3 ---------------------------------------\r
-#define EMC_STATICWAITPAG3_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG3: WAITPAGE Position */\r
-#define EMC_STATICWAITPAG3_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos) /*!< EMC STATICWAITPAG3: WAITPAGE Mask */\r
-\r
-// ------------------------------------ EMC_STATICWAITWR3 ---------------------------------------\r
-#define EMC_STATICWAITWR3_WAITWR_Pos 0 /*!< EMC STATICWAITWR3: WAITWR Position */\r
-#define EMC_STATICWAITWR3_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos) /*!< EMC STATICWAITWR3: WAITWR Mask */\r
-\r
-// ----------------------------------- EMC_STATICWAITTURN3 --------------------------------------\r
-#define EMC_STATICWAITTURN3_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN3: WAITTURN Position */\r
-#define EMC_STATICWAITTURN3_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos) /*!< EMC STATICWAITTURN3: WAITTURN Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- USB0 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ------------------------------------- USB0_CAPLENGTH -----------------------------------------\r
-#define USB0_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB0 CAPLENGTH: CAPLENGTH Position */\r
-#define USB0_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos) /*!< USB0 CAPLENGTH: CAPLENGTH Mask */\r
-#define USB0_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB0 CAPLENGTH: HCIVERSION Position */\r
-#define USB0_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos) /*!< USB0 CAPLENGTH: HCIVERSION Mask */\r
-\r
-// ------------------------------------- USB0_HCSPARAMS -----------------------------------------\r
-#define USB0_HCSPARAMS_N_PORTS_Pos 0 /*!< USB0 HCSPARAMS: N_PORTS Position */\r
-#define USB0_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos) /*!< USB0 HCSPARAMS: N_PORTS Mask */\r
-#define USB0_HCSPARAMS_PPC_Pos 4 /*!< USB0 HCSPARAMS: PPC Position */\r
-#define USB0_HCSPARAMS_PPC_Msk (0x01UL << USB0_HCSPARAMS_PPC_Pos) /*!< USB0 HCSPARAMS: PPC Mask */\r
-#define USB0_HCSPARAMS_N_PCC_Pos 8 /*!< USB0 HCSPARAMS: N_PCC Position */\r
-#define USB0_HCSPARAMS_N_PCC_Msk (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos) /*!< USB0 HCSPARAMS: N_PCC Mask */\r
-#define USB0_HCSPARAMS_N_CC_Pos 12 /*!< USB0 HCSPARAMS: N_CC Position */\r
-#define USB0_HCSPARAMS_N_CC_Msk (0x0fUL << USB0_HCSPARAMS_N_CC_Pos) /*!< USB0 HCSPARAMS: N_CC Mask */\r
-#define USB0_HCSPARAMS_PI_Pos 16 /*!< USB0 HCSPARAMS: PI Position */\r
-#define USB0_HCSPARAMS_PI_Msk (0x01UL << USB0_HCSPARAMS_PI_Pos) /*!< USB0 HCSPARAMS: PI Mask */\r
-#define USB0_HCSPARAMS_N_PTT_Pos 20 /*!< USB0 HCSPARAMS: N_PTT Position */\r
-#define USB0_HCSPARAMS_N_PTT_Msk (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos) /*!< USB0 HCSPARAMS: N_PTT Mask */\r
-#define USB0_HCSPARAMS_N_TT_Pos 24 /*!< USB0 HCSPARAMS: N_TT Position */\r
-#define USB0_HCSPARAMS_N_TT_Msk (0x0fUL << USB0_HCSPARAMS_N_TT_Pos) /*!< USB0 HCSPARAMS: N_TT Mask */\r
-\r
-// ------------------------------------- USB0_HCCPARAMS -----------------------------------------\r
-#define USB0_HCCPARAMS_ADC_Pos 0 /*!< USB0 HCCPARAMS: ADC Position */\r
-#define USB0_HCCPARAMS_ADC_Msk (0x01UL << USB0_HCCPARAMS_ADC_Pos) /*!< USB0 HCCPARAMS: ADC Mask */\r
-#define USB0_HCCPARAMS_PFL_Pos 1 /*!< USB0 HCCPARAMS: PFL Position */\r
-#define USB0_HCCPARAMS_PFL_Msk (0x01UL << USB0_HCCPARAMS_PFL_Pos) /*!< USB0 HCCPARAMS: PFL Mask */\r
-#define USB0_HCCPARAMS_ASP_Pos 2 /*!< USB0 HCCPARAMS: ASP Position */\r
-#define USB0_HCCPARAMS_ASP_Msk (0x01UL << USB0_HCCPARAMS_ASP_Pos) /*!< USB0 HCCPARAMS: ASP Mask */\r
-#define USB0_HCCPARAMS_IST_Pos 4 /*!< USB0 HCCPARAMS: IST Position */\r
-#define USB0_HCCPARAMS_IST_Msk (0x0fUL << USB0_HCCPARAMS_IST_Pos) /*!< USB0 HCCPARAMS: IST Mask */\r
-#define USB0_HCCPARAMS_EECP_Pos 8 /*!< USB0 HCCPARAMS: EECP Position */\r
-#define USB0_HCCPARAMS_EECP_Msk (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos) /*!< USB0 HCCPARAMS: EECP Mask */\r
-\r
-// ------------------------------------- USB0_DCIVERSION ----------------------------------------\r
-#define USB0_DCIVERSION_DCIVERSION_Pos 0 /*!< USB0 DCIVERSION: DCIVERSION Position */\r
-#define USB0_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos) /*!< USB0 DCIVERSION: DCIVERSION Mask */\r
-\r
-// -------------------------------------- USB0_USBCMD_D -----------------------------------------\r
-#define USB0_USBCMD_D_RS_Pos 0 /*!< USB0 USBCMD_D: RS Position */\r
-#define USB0_USBCMD_D_RS_Msk (0x01UL << USB0_USBCMD_D_RS_Pos) /*!< USB0 USBCMD_D: RS Mask */\r
-#define USB0_USBCMD_D_RST_Pos 1 /*!< USB0 USBCMD_D: RST Position */\r
-#define USB0_USBCMD_D_RST_Msk (0x01UL << USB0_USBCMD_D_RST_Pos) /*!< USB0 USBCMD_D: RST Mask */\r
-#define USB0_USBCMD_D_SUTW_Pos 13 /*!< USB0 USBCMD_D: SUTW Position */\r
-#define USB0_USBCMD_D_SUTW_Msk (0x01UL << USB0_USBCMD_D_SUTW_Pos) /*!< USB0 USBCMD_D: SUTW Mask */\r
-#define USB0_USBCMD_D_ATDTW_Pos 14 /*!< USB0 USBCMD_D: ATDTW Position */\r
-#define USB0_USBCMD_D_ATDTW_Msk (0x01UL << USB0_USBCMD_D_ATDTW_Pos) /*!< USB0 USBCMD_D: ATDTW Mask */\r
-#define USB0_USBCMD_D_ITC_Pos 16 /*!< USB0 USBCMD_D: ITC Position */\r
-#define USB0_USBCMD_D_ITC_Msk (0x000000ffUL << USB0_USBCMD_D_ITC_Pos) /*!< USB0 USBCMD_D: ITC Mask */\r
-\r
-// -------------------------------------- USB0_USBCMD_H -----------------------------------------\r
-#define USB0_USBCMD_H_RS_Pos 0 /*!< USB0 USBCMD_H: RS Position */\r
-#define USB0_USBCMD_H_RS_Msk (0x01UL << USB0_USBCMD_H_RS_Pos) /*!< USB0 USBCMD_H: RS Mask */\r
-#define USB0_USBCMD_H_RST_Pos 1 /*!< USB0 USBCMD_H: RST Position */\r
-#define USB0_USBCMD_H_RST_Msk (0x01UL << USB0_USBCMD_H_RST_Pos) /*!< USB0 USBCMD_H: RST Mask */\r
-#define USB0_USBCMD_H_FS0_Pos 2 /*!< USB0 USBCMD_H: FS0 Position */\r
-#define USB0_USBCMD_H_FS0_Msk (0x01UL << USB0_USBCMD_H_FS0_Pos) /*!< USB0 USBCMD_H: FS0 Mask */\r
-#define USB0_USBCMD_H_FS1_Pos 3 /*!< USB0 USBCMD_H: FS1 Position */\r
-#define USB0_USBCMD_H_FS1_Msk (0x01UL << USB0_USBCMD_H_FS1_Pos) /*!< USB0 USBCMD_H: FS1 Mask */\r
-#define USB0_USBCMD_H_PSE_Pos 4 /*!< USB0 USBCMD_H: PSE Position */\r
-#define USB0_USBCMD_H_PSE_Msk (0x01UL << USB0_USBCMD_H_PSE_Pos) /*!< USB0 USBCMD_H: PSE Mask */\r
-#define USB0_USBCMD_H_ASE_Pos 5 /*!< USB0 USBCMD_H: ASE Position */\r
-#define USB0_USBCMD_H_ASE_Msk (0x01UL << USB0_USBCMD_H_ASE_Pos) /*!< USB0 USBCMD_H: ASE Mask */\r
-#define USB0_USBCMD_H_IAA_Pos 6 /*!< USB0 USBCMD_H: IAA Position */\r
-#define USB0_USBCMD_H_IAA_Msk (0x01UL << USB0_USBCMD_H_IAA_Pos) /*!< USB0 USBCMD_H: IAA Mask */\r
-#define USB0_USBCMD_H_ASP1_0_Pos 8 /*!< USB0 USBCMD_H: ASP1_0 Position */\r
-#define USB0_USBCMD_H_ASP1_0_Msk (0x03UL << USB0_USBCMD_H_ASP1_0_Pos) /*!< USB0 USBCMD_H: ASP1_0 Mask */\r
-#define USB0_USBCMD_H_ASPE_Pos 11 /*!< USB0 USBCMD_H: ASPE Position */\r
-#define USB0_USBCMD_H_ASPE_Msk (0x01UL << USB0_USBCMD_H_ASPE_Pos) /*!< USB0 USBCMD_H: ASPE Mask */\r
-#define USB0_USBCMD_H_FS2_Pos 15 /*!< USB0 USBCMD_H: FS2 Position */\r
-#define USB0_USBCMD_H_FS2_Msk (0x01UL << USB0_USBCMD_H_FS2_Pos) /*!< USB0 USBCMD_H: FS2 Mask */\r
-#define USB0_USBCMD_H_ITC_Pos 16 /*!< USB0 USBCMD_H: ITC Position */\r
-#define USB0_USBCMD_H_ITC_Msk (0x000000ffUL << USB0_USBCMD_H_ITC_Pos) /*!< USB0 USBCMD_H: ITC Mask */\r
-\r
-// -------------------------------------- USB0_USBSTS_D -----------------------------------------\r
-#define USB0_USBSTS_D_UI_Pos 0 /*!< USB0 USBSTS_D: UI Position */\r
-#define USB0_USBSTS_D_UI_Msk (0x01UL << USB0_USBSTS_D_UI_Pos) /*!< USB0 USBSTS_D: UI Mask */\r
-#define USB0_USBSTS_D_UEI_Pos 1 /*!< USB0 USBSTS_D: UEI Position */\r
-#define USB0_USBSTS_D_UEI_Msk (0x01UL << USB0_USBSTS_D_UEI_Pos) /*!< USB0 USBSTS_D: UEI Mask */\r
-#define USB0_USBSTS_D_PCI_Pos 2 /*!< USB0 USBSTS_D: PCI Position */\r
-#define USB0_USBSTS_D_PCI_Msk (0x01UL << USB0_USBSTS_D_PCI_Pos) /*!< USB0 USBSTS_D: PCI Mask */\r
-#define USB0_USBSTS_D_AAI_Pos 5 /*!< USB0 USBSTS_D: AAI Position */\r
-#define USB0_USBSTS_D_AAI_Msk (0x01UL << USB0_USBSTS_D_AAI_Pos) /*!< USB0 USBSTS_D: AAI Mask */\r
-#define USB0_USBSTS_D_URI_Pos 6 /*!< USB0 USBSTS_D: URI Position */\r
-#define USB0_USBSTS_D_URI_Msk (0x01UL << USB0_USBSTS_D_URI_Pos) /*!< USB0 USBSTS_D: URI Mask */\r
-#define USB0_USBSTS_D_SRI_Pos 7 /*!< USB0 USBSTS_D: SRI Position */\r
-#define USB0_USBSTS_D_SRI_Msk (0x01UL << USB0_USBSTS_D_SRI_Pos) /*!< USB0 USBSTS_D: SRI Mask */\r
-#define USB0_USBSTS_D_SLI_Pos 8 /*!< USB0 USBSTS_D: SLI Position */\r
-#define USB0_USBSTS_D_SLI_Msk (0x01UL << USB0_USBSTS_D_SLI_Pos) /*!< USB0 USBSTS_D: SLI Mask */\r
-#define USB0_USBSTS_D_NAKI_Pos 16 /*!< USB0 USBSTS_D: NAKI Position */\r
-#define USB0_USBSTS_D_NAKI_Msk (0x01UL << USB0_USBSTS_D_NAKI_Pos) /*!< USB0 USBSTS_D: NAKI Mask */\r
-\r
-// -------------------------------------- USB0_USBSTS_H -----------------------------------------\r
-#define USB0_USBSTS_H_UI_Pos 0 /*!< USB0 USBSTS_H: UI Position */\r
-#define USB0_USBSTS_H_UI_Msk (0x01UL << USB0_USBSTS_H_UI_Pos) /*!< USB0 USBSTS_H: UI Mask */\r
-#define USB0_USBSTS_H_UEI_Pos 1 /*!< USB0 USBSTS_H: UEI Position */\r
-#define USB0_USBSTS_H_UEI_Msk (0x01UL << USB0_USBSTS_H_UEI_Pos) /*!< USB0 USBSTS_H: UEI Mask */\r
-#define USB0_USBSTS_H_PCI_Pos 2 /*!< USB0 USBSTS_H: PCI Position */\r
-#define USB0_USBSTS_H_PCI_Msk (0x01UL << USB0_USBSTS_H_PCI_Pos) /*!< USB0 USBSTS_H: PCI Mask */\r
-#define USB0_USBSTS_H_FRI_Pos 3 /*!< USB0 USBSTS_H: FRI Position */\r
-#define USB0_USBSTS_H_FRI_Msk (0x01UL << USB0_USBSTS_H_FRI_Pos) /*!< USB0 USBSTS_H: FRI Mask */\r
-#define USB0_USBSTS_H_AAI_Pos 5 /*!< USB0 USBSTS_H: AAI Position */\r
-#define USB0_USBSTS_H_AAI_Msk (0x01UL << USB0_USBSTS_H_AAI_Pos) /*!< USB0 USBSTS_H: AAI Mask */\r
-#define USB0_USBSTS_H_SRI_Pos 7 /*!< USB0 USBSTS_H: SRI Position */\r
-#define USB0_USBSTS_H_SRI_Msk (0x01UL << USB0_USBSTS_H_SRI_Pos) /*!< USB0 USBSTS_H: SRI Mask */\r
-#define USB0_USBSTS_H_HCH_Pos 12 /*!< USB0 USBSTS_H: HCH Position */\r
-#define USB0_USBSTS_H_HCH_Msk (0x01UL << USB0_USBSTS_H_HCH_Pos) /*!< USB0 USBSTS_H: HCH Mask */\r
-#define USB0_USBSTS_H_RCL_Pos 13 /*!< USB0 USBSTS_H: RCL Position */\r
-#define USB0_USBSTS_H_RCL_Msk (0x01UL << USB0_USBSTS_H_RCL_Pos) /*!< USB0 USBSTS_H: RCL Mask */\r
-#define USB0_USBSTS_H_PS_Pos 14 /*!< USB0 USBSTS_H: PS Position */\r
-#define USB0_USBSTS_H_PS_Msk (0x01UL << USB0_USBSTS_H_PS_Pos) /*!< USB0 USBSTS_H: PS Mask */\r
-#define USB0_USBSTS_H_AS_Pos 15 /*!< USB0 USBSTS_H: AS Position */\r
-#define USB0_USBSTS_H_AS_Msk (0x01UL << USB0_USBSTS_H_AS_Pos) /*!< USB0 USBSTS_H: AS Mask */\r
-#define USB0_USBSTS_H_UAI_Pos 18 /*!< USB0 USBSTS_H: UAI Position */\r
-#define USB0_USBSTS_H_UAI_Msk (0x01UL << USB0_USBSTS_H_UAI_Pos) /*!< USB0 USBSTS_H: UAI Mask */\r
-#define USB0_USBSTS_H_UPI_Pos 19 /*!< USB0 USBSTS_H: UPI Position */\r
-#define USB0_USBSTS_H_UPI_Msk (0x01UL << USB0_USBSTS_H_UPI_Pos) /*!< USB0 USBSTS_H: UPI Mask */\r
-\r
-// ------------------------------------- USB0_USBINTR_D -----------------------------------------\r
-#define USB0_USBINTR_D_UE_Pos 0 /*!< USB0 USBINTR_D: UE Position */\r
-#define USB0_USBINTR_D_UE_Msk (0x01UL << USB0_USBINTR_D_UE_Pos) /*!< USB0 USBINTR_D: UE Mask */\r
-#define USB0_USBINTR_D_UEE_Pos 1 /*!< USB0 USBINTR_D: UEE Position */\r
-#define USB0_USBINTR_D_UEE_Msk (0x01UL << USB0_USBINTR_D_UEE_Pos) /*!< USB0 USBINTR_D: UEE Mask */\r
-#define USB0_USBINTR_D_PCE_Pos 2 /*!< USB0 USBINTR_D: PCE Position */\r
-#define USB0_USBINTR_D_PCE_Msk (0x01UL << USB0_USBINTR_D_PCE_Pos) /*!< USB0 USBINTR_D: PCE Mask */\r
-#define USB0_USBINTR_D_URE_Pos 6 /*!< USB0 USBINTR_D: URE Position */\r
-#define USB0_USBINTR_D_URE_Msk (0x01UL << USB0_USBINTR_D_URE_Pos) /*!< USB0 USBINTR_D: URE Mask */\r
-#define USB0_USBINTR_D_SRE_Pos 7 /*!< USB0 USBINTR_D: SRE Position */\r
-#define USB0_USBINTR_D_SRE_Msk (0x01UL << USB0_USBINTR_D_SRE_Pos) /*!< USB0 USBINTR_D: SRE Mask */\r
-#define USB0_USBINTR_D_SLE_Pos 8 /*!< USB0 USBINTR_D: SLE Position */\r
-#define USB0_USBINTR_D_SLE_Msk (0x01UL << USB0_USBINTR_D_SLE_Pos) /*!< USB0 USBINTR_D: SLE Mask */\r
-#define USB0_USBINTR_D_NAKE_Pos 16 /*!< USB0 USBINTR_D: NAKE Position */\r
-#define USB0_USBINTR_D_NAKE_Msk (0x01UL << USB0_USBINTR_D_NAKE_Pos) /*!< USB0 USBINTR_D: NAKE Mask */\r
-\r
-// ------------------------------------- USB0_USBINTR_H -----------------------------------------\r
-#define USB0_USBINTR_H_UE_Pos 0 /*!< USB0 USBINTR_H: UE Position */\r
-#define USB0_USBINTR_H_UE_Msk (0x01UL << USB0_USBINTR_H_UE_Pos) /*!< USB0 USBINTR_H: UE Mask */\r
-#define USB0_USBINTR_H_UEE_Pos 1 /*!< USB0 USBINTR_H: UEE Position */\r
-#define USB0_USBINTR_H_UEE_Msk (0x01UL << USB0_USBINTR_H_UEE_Pos) /*!< USB0 USBINTR_H: UEE Mask */\r
-#define USB0_USBINTR_H_PCE_Pos 2 /*!< USB0 USBINTR_H: PCE Position */\r
-#define USB0_USBINTR_H_PCE_Msk (0x01UL << USB0_USBINTR_H_PCE_Pos) /*!< USB0 USBINTR_H: PCE Mask */\r
-#define USB0_USBINTR_H_FRE_Pos 3 /*!< USB0 USBINTR_H: FRE Position */\r
-#define USB0_USBINTR_H_FRE_Msk (0x01UL << USB0_USBINTR_H_FRE_Pos) /*!< USB0 USBINTR_H: FRE Mask */\r
-#define USB0_USBINTR_H_AAE_Pos 5 /*!< USB0 USBINTR_H: AAE Position */\r
-#define USB0_USBINTR_H_AAE_Msk (0x01UL << USB0_USBINTR_H_AAE_Pos) /*!< USB0 USBINTR_H: AAE Mask */\r
-#define USB0_USBINTR_H_SRE_Pos 7 /*!< USB0 USBINTR_H: SRE Position */\r
-#define USB0_USBINTR_H_SRE_Msk (0x01UL << USB0_USBINTR_H_SRE_Pos) /*!< USB0 USBINTR_H: SRE Mask */\r
-#define USB0_USBINTR_H_UAIE_Pos 18 /*!< USB0 USBINTR_H: UAIE Position */\r
-#define USB0_USBINTR_H_UAIE_Msk (0x01UL << USB0_USBINTR_H_UAIE_Pos) /*!< USB0 USBINTR_H: UAIE Mask */\r
-#define USB0_USBINTR_H_UPIA_Pos 19 /*!< USB0 USBINTR_H: UPIA Position */\r
-#define USB0_USBINTR_H_UPIA_Msk (0x01UL << USB0_USBINTR_H_UPIA_Pos) /*!< USB0 USBINTR_H: UPIA Mask */\r
-\r
-// ------------------------------------- USB0_FRINDEX_D -----------------------------------------\r
-#define USB0_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */\r
-#define USB0_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask */\r
-#define USB0_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */\r
-#define USB0_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask */\r
-\r
-// ------------------------------------- USB0_FRINDEX_H -----------------------------------------\r
-#define USB0_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */\r
-#define USB0_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask */\r
-#define USB0_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */\r
-#define USB0_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask */\r
-\r
-// ------------------------------------- USB0_DEVICEADDR ----------------------------------------\r
-#define USB0_DEVICEADDR_USBADRA_Pos 24 /*!< USB0 DEVICEADDR: USBADRA Position */\r
-#define USB0_DEVICEADDR_USBADRA_Msk (0x01UL << USB0_DEVICEADDR_USBADRA_Pos) /*!< USB0 DEVICEADDR: USBADRA Mask */\r
-#define USB0_DEVICEADDR_USBADR_Pos 25 /*!< USB0 DEVICEADDR: USBADR Position */\r
-#define USB0_DEVICEADDR_USBADR_Msk (0x7fUL << USB0_DEVICEADDR_USBADR_Pos) /*!< USB0 DEVICEADDR: USBADR Mask */\r
-\r
-// ---------------------------------- USB0_PERIODICLISTBASE -------------------------------------\r
-#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */\r
-#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */\r
-\r
-// ---------------------------------- USB0_ENDPOINTLISTADDR -------------------------------------\r
-#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */\r
-#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */\r
-\r
-// ----------------------------------- USB0_ASYNCLISTADDR ---------------------------------------\r
-#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */\r
-#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */\r
-\r
-// --------------------------------------- USB0_TTCTRL ------------------------------------------\r
-#define USB0_TTCTRL_TTHA_Pos 24 /*!< USB0 TTCTRL: TTHA Position */\r
-#define USB0_TTCTRL_TTHA_Msk (0x7fUL << USB0_TTCTRL_TTHA_Pos) /*!< USB0 TTCTRL: TTHA Mask */\r
-\r
-// ------------------------------------- USB0_BURSTSIZE -----------------------------------------\r
-#define USB0_BURSTSIZE_RXPBURST_Pos 0 /*!< USB0 BURSTSIZE: RXPBURST Position */\r
-#define USB0_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos) /*!< USB0 BURSTSIZE: RXPBURST Mask */\r
-#define USB0_BURSTSIZE_TXPBURST_Pos 8 /*!< USB0 BURSTSIZE: TXPBURST Position */\r
-#define USB0_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos) /*!< USB0 BURSTSIZE: TXPBURST Mask */\r
-\r
-// ------------------------------------ USB0_TXFILLTUNING ---------------------------------------\r
-#define USB0_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB0 TXFILLTUNING: TXSCHOH Position */\r
-#define USB0_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos) /*!< USB0 TXFILLTUNING: TXSCHOH Mask */\r
-#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */\r
-#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */\r
-#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */\r
-#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */\r
-\r
-// ------------------------------------- USB0_BINTERVAL -----------------------------------------\r
-#define USB0_BINTERVAL_BINT_Pos 0 /*!< USB0 BINTERVAL: BINT Position */\r
-#define USB0_BINTERVAL_BINT_Msk (0x0fUL << USB0_BINTERVAL_BINT_Pos) /*!< USB0 BINTERVAL: BINT Mask */\r
-\r
-// -------------------------------------- USB0_ENDPTNAK -----------------------------------------\r
-#define USB0_ENDPTNAK_EPRN0_Pos 0 /*!< USB0 ENDPTNAK: EPRN0 Position */\r
-#define USB0_ENDPTNAK_EPRN0_Msk (0x01UL << USB0_ENDPTNAK_EPRN0_Pos) /*!< USB0 ENDPTNAK: EPRN0 Mask */\r
-#define USB0_ENDPTNAK_EPRN1_Pos 1 /*!< USB0 ENDPTNAK: EPRN1 Position */\r
-#define USB0_ENDPTNAK_EPRN1_Msk (0x01UL << USB0_ENDPTNAK_EPRN1_Pos) /*!< USB0 ENDPTNAK: EPRN1 Mask */\r
-#define USB0_ENDPTNAK_EPRN2_Pos 2 /*!< USB0 ENDPTNAK: EPRN2 Position */\r
-#define USB0_ENDPTNAK_EPRN2_Msk (0x01UL << USB0_ENDPTNAK_EPRN2_Pos) /*!< USB0 ENDPTNAK: EPRN2 Mask */\r
-#define USB0_ENDPTNAK_EPRN3_Pos 3 /*!< USB0 ENDPTNAK: EPRN3 Position */\r
-#define USB0_ENDPTNAK_EPRN3_Msk (0x01UL << USB0_ENDPTNAK_EPRN3_Pos) /*!< USB0 ENDPTNAK: EPRN3 Mask */\r
-#define USB0_ENDPTNAK_EPRN4_Pos 4 /*!< USB0 ENDPTNAK: EPRN4 Position */\r
-#define USB0_ENDPTNAK_EPRN4_Msk (0x01UL << USB0_ENDPTNAK_EPRN4_Pos) /*!< USB0 ENDPTNAK: EPRN4 Mask */\r
-#define USB0_ENDPTNAK_EPRN5_Pos 5 /*!< USB0 ENDPTNAK: EPRN5 Position */\r
-#define USB0_ENDPTNAK_EPRN5_Msk (0x01UL << USB0_ENDPTNAK_EPRN5_Pos) /*!< USB0 ENDPTNAK: EPRN5 Mask */\r
-#define USB0_ENDPTNAK_EPTN0_Pos 16 /*!< USB0 ENDPTNAK: EPTN0 Position */\r
-#define USB0_ENDPTNAK_EPTN0_Msk (0x01UL << USB0_ENDPTNAK_EPTN0_Pos) /*!< USB0 ENDPTNAK: EPTN0 Mask */\r
-#define USB0_ENDPTNAK_EPTN1_Pos 17 /*!< USB0 ENDPTNAK: EPTN1 Position */\r
-#define USB0_ENDPTNAK_EPTN1_Msk (0x01UL << USB0_ENDPTNAK_EPTN1_Pos) /*!< USB0 ENDPTNAK: EPTN1 Mask */\r
-#define USB0_ENDPTNAK_EPTN2_Pos 18 /*!< USB0 ENDPTNAK: EPTN2 Position */\r
-#define USB0_ENDPTNAK_EPTN2_Msk (0x01UL << USB0_ENDPTNAK_EPTN2_Pos) /*!< USB0 ENDPTNAK: EPTN2 Mask */\r
-#define USB0_ENDPTNAK_EPTN3_Pos 19 /*!< USB0 ENDPTNAK: EPTN3 Position */\r
-#define USB0_ENDPTNAK_EPTN3_Msk (0x01UL << USB0_ENDPTNAK_EPTN3_Pos) /*!< USB0 ENDPTNAK: EPTN3 Mask */\r
-#define USB0_ENDPTNAK_EPTN4_Pos 20 /*!< USB0 ENDPTNAK: EPTN4 Position */\r
-#define USB0_ENDPTNAK_EPTN4_Msk (0x01UL << USB0_ENDPTNAK_EPTN4_Pos) /*!< USB0 ENDPTNAK: EPTN4 Mask */\r
-#define USB0_ENDPTNAK_EPTN5_Pos 21 /*!< USB0 ENDPTNAK: EPTN5 Position */\r
-#define USB0_ENDPTNAK_EPTN5_Msk (0x01UL << USB0_ENDPTNAK_EPTN5_Pos) /*!< USB0 ENDPTNAK: EPTN5 Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTNAKEN ----------------------------------------\r
-#define USB0_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB0 ENDPTNAKEN: EPRNE0 Position */\r
-#define USB0_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos) /*!< USB0 ENDPTNAKEN: EPRNE0 Mask */\r
-#define USB0_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB0 ENDPTNAKEN: EPRNE1 Position */\r
-#define USB0_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos) /*!< USB0 ENDPTNAKEN: EPRNE1 Mask */\r
-#define USB0_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB0 ENDPTNAKEN: EPRNE2 Position */\r
-#define USB0_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos) /*!< USB0 ENDPTNAKEN: EPRNE2 Mask */\r
-#define USB0_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB0 ENDPTNAKEN: EPRNE3 Position */\r
-#define USB0_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos) /*!< USB0 ENDPTNAKEN: EPRNE3 Mask */\r
-#define USB0_ENDPTNAKEN_EPRNE4_Pos 4 /*!< USB0 ENDPTNAKEN: EPRNE4 Position */\r
-#define USB0_ENDPTNAKEN_EPRNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos) /*!< USB0 ENDPTNAKEN: EPRNE4 Mask */\r
-#define USB0_ENDPTNAKEN_EPRNE5_Pos 5 /*!< USB0 ENDPTNAKEN: EPRNE5 Position */\r
-#define USB0_ENDPTNAKEN_EPRNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos) /*!< USB0 ENDPTNAKEN: EPRNE5 Mask */\r
-#define USB0_ENDPTNAKEN_EPTNE0_Pos 16 /*!< USB0 ENDPTNAKEN: EPTNE0 Position */\r
-#define USB0_ENDPTNAKEN_EPTNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos) /*!< USB0 ENDPTNAKEN: EPTNE0 Mask */\r
-#define USB0_ENDPTNAKEN_EPTNE1_Pos 17 /*!< USB0 ENDPTNAKEN: EPTNE1 Position */\r
-#define USB0_ENDPTNAKEN_EPTNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos) /*!< USB0 ENDPTNAKEN: EPTNE1 Mask */\r
-#define USB0_ENDPTNAKEN_EPTNE2_Pos 18 /*!< USB0 ENDPTNAKEN: EPTNE2 Position */\r
-#define USB0_ENDPTNAKEN_EPTNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos) /*!< USB0 ENDPTNAKEN: EPTNE2 Mask */\r
-#define USB0_ENDPTNAKEN_EPTNE3_Pos 19 /*!< USB0 ENDPTNAKEN: EPTNE3 Position */\r
-#define USB0_ENDPTNAKEN_EPTNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos) /*!< USB0 ENDPTNAKEN: EPTNE3 Mask */\r
-#define USB0_ENDPTNAKEN_EPTNE4_Pos 20 /*!< USB0 ENDPTNAKEN: EPTNE4 Position */\r
-#define USB0_ENDPTNAKEN_EPTNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos) /*!< USB0 ENDPTNAKEN: EPTNE4 Mask */\r
-#define USB0_ENDPTNAKEN_EPTNE5_Pos 21 /*!< USB0 ENDPTNAKEN: EPTNE5 Position */\r
-#define USB0_ENDPTNAKEN_EPTNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos) /*!< USB0 ENDPTNAKEN: EPTNE5 Mask */\r
-\r
-// ------------------------------------- USB0_PORTSC1_D -----------------------------------------\r
-#define USB0_PORTSC1_D_CCS_Pos 0 /*!< USB0 PORTSC1_D: CCS Position */\r
-#define USB0_PORTSC1_D_CCS_Msk (0x01UL << USB0_PORTSC1_D_CCS_Pos) /*!< USB0 PORTSC1_D: CCS Mask */\r
-#define USB0_PORTSC1_D_PE_Pos 2 /*!< USB0 PORTSC1_D: PE Position */\r
-#define USB0_PORTSC1_D_PE_Msk (0x01UL << USB0_PORTSC1_D_PE_Pos) /*!< USB0 PORTSC1_D: PE Mask */\r
-#define USB0_PORTSC1_D_PEC_Pos 3 /*!< USB0 PORTSC1_D: PEC Position */\r
-#define USB0_PORTSC1_D_PEC_Msk (0x01UL << USB0_PORTSC1_D_PEC_Pos) /*!< USB0 PORTSC1_D: PEC Mask */\r
-#define USB0_PORTSC1_D_FPR_Pos 6 /*!< USB0 PORTSC1_D: FPR Position */\r
-#define USB0_PORTSC1_D_FPR_Msk (0x01UL << USB0_PORTSC1_D_FPR_Pos) /*!< USB0 PORTSC1_D: FPR Mask */\r
-#define USB0_PORTSC1_D_SUSP_Pos 7 /*!< USB0 PORTSC1_D: SUSP Position */\r
-#define USB0_PORTSC1_D_SUSP_Msk (0x01UL << USB0_PORTSC1_D_SUSP_Pos) /*!< USB0 PORTSC1_D: SUSP Mask */\r
-#define USB0_PORTSC1_D_PR_Pos 8 /*!< USB0 PORTSC1_D: PR Position */\r
-#define USB0_PORTSC1_D_PR_Msk (0x01UL << USB0_PORTSC1_D_PR_Pos) /*!< USB0 PORTSC1_D: PR Mask */\r
-#define USB0_PORTSC1_D_HSP_Pos 9 /*!< USB0 PORTSC1_D: HSP Position */\r
-#define USB0_PORTSC1_D_HSP_Msk (0x01UL << USB0_PORTSC1_D_HSP_Pos) /*!< USB0 PORTSC1_D: HSP Mask */\r
-#define USB0_PORTSC1_D_PIC1_0_Pos 14 /*!< USB0 PORTSC1_D: PIC1_0 Position */\r
-#define USB0_PORTSC1_D_PIC1_0_Msk (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos) /*!< USB0 PORTSC1_D: PIC1_0 Mask */\r
-#define USB0_PORTSC1_D_PTC3_0_Pos 16 /*!< USB0 PORTSC1_D: PTC3_0 Position */\r
-#define USB0_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos) /*!< USB0 PORTSC1_D: PTC3_0 Mask */\r
-#define USB0_PORTSC1_D_PHCD_Pos 23 /*!< USB0 PORTSC1_D: PHCD Position */\r
-#define USB0_PORTSC1_D_PHCD_Msk (0x01UL << USB0_PORTSC1_D_PHCD_Pos) /*!< USB0 PORTSC1_D: PHCD Mask */\r
-#define USB0_PORTSC1_D_PFSC_Pos 24 /*!< USB0 PORTSC1_D: PFSC Position */\r
-#define USB0_PORTSC1_D_PFSC_Msk (0x01UL << USB0_PORTSC1_D_PFSC_Pos) /*!< USB0 PORTSC1_D: PFSC Mask */\r
-#define USB0_PORTSC1_D_PSPD_Pos 26 /*!< USB0 PORTSC1_D: PSPD Position */\r
-#define USB0_PORTSC1_D_PSPD_Msk (0x03UL << USB0_PORTSC1_D_PSPD_Pos) /*!< USB0 PORTSC1_D: PSPD Mask */\r
-\r
-// ------------------------------------- USB0_PORTSC1_H -----------------------------------------\r
-#define USB0_PORTSC1_H_CCS_Pos 0 /*!< USB0 PORTSC1_H: CCS Position */\r
-#define USB0_PORTSC1_H_CCS_Msk (0x01UL << USB0_PORTSC1_H_CCS_Pos) /*!< USB0 PORTSC1_H: CCS Mask */\r
-#define USB0_PORTSC1_H_CSC_Pos 1 /*!< USB0 PORTSC1_H: CSC Position */\r
-#define USB0_PORTSC1_H_CSC_Msk (0x01UL << USB0_PORTSC1_H_CSC_Pos) /*!< USB0 PORTSC1_H: CSC Mask */\r
-#define USB0_PORTSC1_H_PE_Pos 2 /*!< USB0 PORTSC1_H: PE Position */\r
-#define USB0_PORTSC1_H_PE_Msk (0x01UL << USB0_PORTSC1_H_PE_Pos) /*!< USB0 PORTSC1_H: PE Mask */\r
-#define USB0_PORTSC1_H_PEC_Pos 3 /*!< USB0 PORTSC1_H: PEC Position */\r
-#define USB0_PORTSC1_H_PEC_Msk (0x01UL << USB0_PORTSC1_H_PEC_Pos) /*!< USB0 PORTSC1_H: PEC Mask */\r
-#define USB0_PORTSC1_H_OCA_Pos 4 /*!< USB0 PORTSC1_H: OCA Position */\r
-#define USB0_PORTSC1_H_OCA_Msk (0x01UL << USB0_PORTSC1_H_OCA_Pos) /*!< USB0 PORTSC1_H: OCA Mask */\r
-#define USB0_PORTSC1_H_OCC_Pos 5 /*!< USB0 PORTSC1_H: OCC Position */\r
-#define USB0_PORTSC1_H_OCC_Msk (0x01UL << USB0_PORTSC1_H_OCC_Pos) /*!< USB0 PORTSC1_H: OCC Mask */\r
-#define USB0_PORTSC1_H_FPR_Pos 6 /*!< USB0 PORTSC1_H: FPR Position */\r
-#define USB0_PORTSC1_H_FPR_Msk (0x01UL << USB0_PORTSC1_H_FPR_Pos) /*!< USB0 PORTSC1_H: FPR Mask */\r
-#define USB0_PORTSC1_H_SUSP_Pos 7 /*!< USB0 PORTSC1_H: SUSP Position */\r
-#define USB0_PORTSC1_H_SUSP_Msk (0x01UL << USB0_PORTSC1_H_SUSP_Pos) /*!< USB0 PORTSC1_H: SUSP Mask */\r
-#define USB0_PORTSC1_H_PR_Pos 8 /*!< USB0 PORTSC1_H: PR Position */\r
-#define USB0_PORTSC1_H_PR_Msk (0x01UL << USB0_PORTSC1_H_PR_Pos) /*!< USB0 PORTSC1_H: PR Mask */\r
-#define USB0_PORTSC1_H_HSP_Pos 9 /*!< USB0 PORTSC1_H: HSP Position */\r
-#define USB0_PORTSC1_H_HSP_Msk (0x01UL << USB0_PORTSC1_H_HSP_Pos) /*!< USB0 PORTSC1_H: HSP Mask */\r
-#define USB0_PORTSC1_H_LS_Pos 10 /*!< USB0 PORTSC1_H: LS Position */\r
-#define USB0_PORTSC1_H_LS_Msk (0x03UL << USB0_PORTSC1_H_LS_Pos) /*!< USB0 PORTSC1_H: LS Mask */\r
-#define USB0_PORTSC1_H_PP_Pos 12 /*!< USB0 PORTSC1_H: PP Position */\r
-#define USB0_PORTSC1_H_PP_Msk (0x01UL << USB0_PORTSC1_H_PP_Pos) /*!< USB0 PORTSC1_H: PP Mask */\r
-#define USB0_PORTSC1_H_PIC1_0_Pos 14 /*!< USB0 PORTSC1_H: PIC1_0 Position */\r
-#define USB0_PORTSC1_H_PIC1_0_Msk (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos) /*!< USB0 PORTSC1_H: PIC1_0 Mask */\r
-#define USB0_PORTSC1_H_PTC3_0_Pos 16 /*!< USB0 PORTSC1_H: PTC3_0 Position */\r
-#define USB0_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos) /*!< USB0 PORTSC1_H: PTC3_0 Mask */\r
-#define USB0_PORTSC1_H_WKCN_Pos 20 /*!< USB0 PORTSC1_H: WKCN Position */\r
-#define USB0_PORTSC1_H_WKCN_Msk (0x01UL << USB0_PORTSC1_H_WKCN_Pos) /*!< USB0 PORTSC1_H: WKCN Mask */\r
-#define USB0_PORTSC1_H_WKDC_Pos 21 /*!< USB0 PORTSC1_H: WKDC Position */\r
-#define USB0_PORTSC1_H_WKDC_Msk (0x01UL << USB0_PORTSC1_H_WKDC_Pos) /*!< USB0 PORTSC1_H: WKDC Mask */\r
-#define USB0_PORTSC1_H_WKOC_Pos 22 /*!< USB0 PORTSC1_H: WKOC Position */\r
-#define USB0_PORTSC1_H_WKOC_Msk (0x01UL << USB0_PORTSC1_H_WKOC_Pos) /*!< USB0 PORTSC1_H: WKOC Mask */\r
-#define USB0_PORTSC1_H_PHCD_Pos 23 /*!< USB0 PORTSC1_H: PHCD Position */\r
-#define USB0_PORTSC1_H_PHCD_Msk (0x01UL << USB0_PORTSC1_H_PHCD_Pos) /*!< USB0 PORTSC1_H: PHCD Mask */\r
-#define USB0_PORTSC1_H_PFSC_Pos 24 /*!< USB0 PORTSC1_H: PFSC Position */\r
-#define USB0_PORTSC1_H_PFSC_Msk (0x01UL << USB0_PORTSC1_H_PFSC_Pos) /*!< USB0 PORTSC1_H: PFSC Mask */\r
-#define USB0_PORTSC1_H_PSPD_Pos 26 /*!< USB0 PORTSC1_H: PSPD Position */\r
-#define USB0_PORTSC1_H_PSPD_Msk (0x03UL << USB0_PORTSC1_H_PSPD_Pos) /*!< USB0 PORTSC1_H: PSPD Mask */\r
-\r
-// --------------------------------------- USB0_OTGSC -------------------------------------------\r
-#define USB0_OTGSC_VD_Pos 0 /*!< USB0 OTGSC: VD Position */\r
-#define USB0_OTGSC_VD_Msk (0x01UL << USB0_OTGSC_VD_Pos) /*!< USB0 OTGSC: VD Mask */\r
-#define USB0_OTGSC_VC_Pos 1 /*!< USB0 OTGSC: VC Position */\r
-#define USB0_OTGSC_VC_Msk (0x01UL << USB0_OTGSC_VC_Pos) /*!< USB0 OTGSC: VC Mask */\r
-#define USB0_OTGSC_HAAR_Pos 2 /*!< USB0 OTGSC: HAAR Position */\r
-#define USB0_OTGSC_HAAR_Msk (0x01UL << USB0_OTGSC_HAAR_Pos) /*!< USB0 OTGSC: HAAR Mask */\r
-#define USB0_OTGSC_OT_Pos 3 /*!< USB0 OTGSC: OT Position */\r
-#define USB0_OTGSC_OT_Msk (0x01UL << USB0_OTGSC_OT_Pos) /*!< USB0 OTGSC: OT Mask */\r
-#define USB0_OTGSC_DP_Pos 4 /*!< USB0 OTGSC: DP Position */\r
-#define USB0_OTGSC_DP_Msk (0x01UL << USB0_OTGSC_DP_Pos) /*!< USB0 OTGSC: DP Mask */\r
-#define USB0_OTGSC_IDPU_Pos 5 /*!< USB0 OTGSC: IDPU Position */\r
-#define USB0_OTGSC_IDPU_Msk (0x01UL << USB0_OTGSC_IDPU_Pos) /*!< USB0 OTGSC: IDPU Mask */\r
-#define USB0_OTGSC_HADP_Pos 6 /*!< USB0 OTGSC: HADP Position */\r
-#define USB0_OTGSC_HADP_Msk (0x01UL << USB0_OTGSC_HADP_Pos) /*!< USB0 OTGSC: HADP Mask */\r
-#define USB0_OTGSC_HABA_Pos 7 /*!< USB0 OTGSC: HABA Position */\r
-#define USB0_OTGSC_HABA_Msk (0x01UL << USB0_OTGSC_HABA_Pos) /*!< USB0 OTGSC: HABA Mask */\r
-#define USB0_OTGSC_ID_Pos 8 /*!< USB0 OTGSC: ID Position */\r
-#define USB0_OTGSC_ID_Msk (0x01UL << USB0_OTGSC_ID_Pos) /*!< USB0 OTGSC: ID Mask */\r
-#define USB0_OTGSC_AVV_Pos 9 /*!< USB0 OTGSC: AVV Position */\r
-#define USB0_OTGSC_AVV_Msk (0x01UL << USB0_OTGSC_AVV_Pos) /*!< USB0 OTGSC: AVV Mask */\r
-#define USB0_OTGSC_ASV_Pos 10 /*!< USB0 OTGSC: ASV Position */\r
-#define USB0_OTGSC_ASV_Msk (0x01UL << USB0_OTGSC_ASV_Pos) /*!< USB0 OTGSC: ASV Mask */\r
-#define USB0_OTGSC_BSV_Pos 11 /*!< USB0 OTGSC: BSV Position */\r
-#define USB0_OTGSC_BSV_Msk (0x01UL << USB0_OTGSC_BSV_Pos) /*!< USB0 OTGSC: BSV Mask */\r
-#define USB0_OTGSC_BSE_Pos 12 /*!< USB0 OTGSC: BSE Position */\r
-#define USB0_OTGSC_BSE_Msk (0x01UL << USB0_OTGSC_BSE_Pos) /*!< USB0 OTGSC: BSE Mask */\r
-#define USB0_OTGSC_MS1T_Pos 13 /*!< USB0 OTGSC: MS1T Position */\r
-#define USB0_OTGSC_MS1T_Msk (0x01UL << USB0_OTGSC_MS1T_Pos) /*!< USB0 OTGSC: MS1T Mask */\r
-#define USB0_OTGSC_DPS_Pos 14 /*!< USB0 OTGSC: DPS Position */\r
-#define USB0_OTGSC_DPS_Msk (0x01UL << USB0_OTGSC_DPS_Pos) /*!< USB0 OTGSC: DPS Mask */\r
-#define USB0_OTGSC_IDIS_Pos 16 /*!< USB0 OTGSC: IDIS Position */\r
-#define USB0_OTGSC_IDIS_Msk (0x01UL << USB0_OTGSC_IDIS_Pos) /*!< USB0 OTGSC: IDIS Mask */\r
-#define USB0_OTGSC_AVVIS_Pos 17 /*!< USB0 OTGSC: AVVIS Position */\r
-#define USB0_OTGSC_AVVIS_Msk (0x01UL << USB0_OTGSC_AVVIS_Pos) /*!< USB0 OTGSC: AVVIS Mask */\r
-#define USB0_OTGSC_ASVIS_Pos 18 /*!< USB0 OTGSC: ASVIS Position */\r
-#define USB0_OTGSC_ASVIS_Msk (0x01UL << USB0_OTGSC_ASVIS_Pos) /*!< USB0 OTGSC: ASVIS Mask */\r
-#define USB0_OTGSC_BSVIS_Pos 19 /*!< USB0 OTGSC: BSVIS Position */\r
-#define USB0_OTGSC_BSVIS_Msk (0x01UL << USB0_OTGSC_BSVIS_Pos) /*!< USB0 OTGSC: BSVIS Mask */\r
-#define USB0_OTGSC_BSEIS_Pos 20 /*!< USB0 OTGSC: BSEIS Position */\r
-#define USB0_OTGSC_BSEIS_Msk (0x01UL << USB0_OTGSC_BSEIS_Pos) /*!< USB0 OTGSC: BSEIS Mask */\r
-#define USB0_OTGSC_ms1S_Pos 21 /*!< USB0 OTGSC: ms1S Position */\r
-#define USB0_OTGSC_ms1S_Msk (0x01UL << USB0_OTGSC_ms1S_Pos) /*!< USB0 OTGSC: ms1S Mask */\r
-#define USB0_OTGSC_DPIS_Pos 22 /*!< USB0 OTGSC: DPIS Position */\r
-#define USB0_OTGSC_DPIS_Msk (0x01UL << USB0_OTGSC_DPIS_Pos) /*!< USB0 OTGSC: DPIS Mask */\r
-#define USB0_OTGSC_IDIE_Pos 24 /*!< USB0 OTGSC: IDIE Position */\r
-#define USB0_OTGSC_IDIE_Msk (0x01UL << USB0_OTGSC_IDIE_Pos) /*!< USB0 OTGSC: IDIE Mask */\r
-#define USB0_OTGSC_AVVIE_Pos 25 /*!< USB0 OTGSC: AVVIE Position */\r
-#define USB0_OTGSC_AVVIE_Msk (0x01UL << USB0_OTGSC_AVVIE_Pos) /*!< USB0 OTGSC: AVVIE Mask */\r
-#define USB0_OTGSC_ASVIE_Pos 26 /*!< USB0 OTGSC: ASVIE Position */\r
-#define USB0_OTGSC_ASVIE_Msk (0x01UL << USB0_OTGSC_ASVIE_Pos) /*!< USB0 OTGSC: ASVIE Mask */\r
-#define USB0_OTGSC_BSVIE_Pos 27 /*!< USB0 OTGSC: BSVIE Position */\r
-#define USB0_OTGSC_BSVIE_Msk (0x01UL << USB0_OTGSC_BSVIE_Pos) /*!< USB0 OTGSC: BSVIE Mask */\r
-#define USB0_OTGSC_BSEIE_Pos 28 /*!< USB0 OTGSC: BSEIE Position */\r
-#define USB0_OTGSC_BSEIE_Msk (0x01UL << USB0_OTGSC_BSEIE_Pos) /*!< USB0 OTGSC: BSEIE Mask */\r
-#define USB0_OTGSC_MS1E_Pos 29 /*!< USB0 OTGSC: MS1E Position */\r
-#define USB0_OTGSC_MS1E_Msk (0x01UL << USB0_OTGSC_MS1E_Pos) /*!< USB0 OTGSC: MS1E Mask */\r
-#define USB0_OTGSC_DPIE_Pos 30 /*!< USB0 OTGSC: DPIE Position */\r
-#define USB0_OTGSC_DPIE_Msk (0x01UL << USB0_OTGSC_DPIE_Pos) /*!< USB0 OTGSC: DPIE Mask */\r
-\r
-// ------------------------------------- USB0_USBMODE_D -----------------------------------------\r
-#define USB0_USBMODE_D_CM1_0_Pos 0 /*!< USB0 USBMODE_D: CM1_0 Position */\r
-#define USB0_USBMODE_D_CM1_0_Msk (0x03UL << USB0_USBMODE_D_CM1_0_Pos) /*!< USB0 USBMODE_D: CM1_0 Mask */\r
-#define USB0_USBMODE_D_ES_Pos 2 /*!< USB0 USBMODE_D: ES Position */\r
-#define USB0_USBMODE_D_ES_Msk (0x01UL << USB0_USBMODE_D_ES_Pos) /*!< USB0 USBMODE_D: ES Mask */\r
-#define USB0_USBMODE_D_SLOM_Pos 3 /*!< USB0 USBMODE_D: SLOM Position */\r
-#define USB0_USBMODE_D_SLOM_Msk (0x01UL << USB0_USBMODE_D_SLOM_Pos) /*!< USB0 USBMODE_D: SLOM Mask */\r
-#define USB0_USBMODE_D_SDIS_Pos 4 /*!< USB0 USBMODE_D: SDIS Position */\r
-#define USB0_USBMODE_D_SDIS_Msk (0x01UL << USB0_USBMODE_D_SDIS_Pos) /*!< USB0 USBMODE_D: SDIS Mask */\r
-\r
-// ------------------------------------- USB0_USBMODE_H -----------------------------------------\r
-#define USB0_USBMODE_H_CM_Pos 0 /*!< USB0 USBMODE_H: CM Position */\r
-#define USB0_USBMODE_H_CM_Msk (0x03UL << USB0_USBMODE_H_CM_Pos) /*!< USB0 USBMODE_H: CM Mask */\r
-#define USB0_USBMODE_H_ES_Pos 2 /*!< USB0 USBMODE_H: ES Position */\r
-#define USB0_USBMODE_H_ES_Msk (0x01UL << USB0_USBMODE_H_ES_Pos) /*!< USB0 USBMODE_H: ES Mask */\r
-#define USB0_USBMODE_H_SDIS_Pos 4 /*!< USB0 USBMODE_H: SDIS Position */\r
-#define USB0_USBMODE_H_SDIS_Msk (0x01UL << USB0_USBMODE_H_SDIS_Pos) /*!< USB0 USBMODE_H: SDIS Mask */\r
-#define USB0_USBMODE_H_VBPS_Pos 5 /*!< USB0 USBMODE_H: VBPS Position */\r
-#define USB0_USBMODE_H_VBPS_Msk (0x01UL << USB0_USBMODE_H_VBPS_Pos) /*!< USB0 USBMODE_H: VBPS Mask */\r
-\r
-// ----------------------------------- USB0_ENDPTSETUPSTAT --------------------------------------\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos 4 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos 5 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */\r
-#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTPRIME ----------------------------------------\r
-#define USB0_ENDPTPRIME_PERB0_Pos 0 /*!< USB0 ENDPTPRIME: PERB0 Position */\r
-#define USB0_ENDPTPRIME_PERB0_Msk (0x01UL << USB0_ENDPTPRIME_PERB0_Pos) /*!< USB0 ENDPTPRIME: PERB0 Mask */\r
-#define USB0_ENDPTPRIME_PERB1_Pos 1 /*!< USB0 ENDPTPRIME: PERB1 Position */\r
-#define USB0_ENDPTPRIME_PERB1_Msk (0x01UL << USB0_ENDPTPRIME_PERB1_Pos) /*!< USB0 ENDPTPRIME: PERB1 Mask */\r
-#define USB0_ENDPTPRIME_PERB2_Pos 2 /*!< USB0 ENDPTPRIME: PERB2 Position */\r
-#define USB0_ENDPTPRIME_PERB2_Msk (0x01UL << USB0_ENDPTPRIME_PERB2_Pos) /*!< USB0 ENDPTPRIME: PERB2 Mask */\r
-#define USB0_ENDPTPRIME_PERB3_Pos 3 /*!< USB0 ENDPTPRIME: PERB3 Position */\r
-#define USB0_ENDPTPRIME_PERB3_Msk (0x01UL << USB0_ENDPTPRIME_PERB3_Pos) /*!< USB0 ENDPTPRIME: PERB3 Mask */\r
-#define USB0_ENDPTPRIME_PERB4_Pos 4 /*!< USB0 ENDPTPRIME: PERB4 Position */\r
-#define USB0_ENDPTPRIME_PERB4_Msk (0x01UL << USB0_ENDPTPRIME_PERB4_Pos) /*!< USB0 ENDPTPRIME: PERB4 Mask */\r
-#define USB0_ENDPTPRIME_PERB5_Pos 5 /*!< USB0 ENDPTPRIME: PERB5 Position */\r
-#define USB0_ENDPTPRIME_PERB5_Msk (0x01UL << USB0_ENDPTPRIME_PERB5_Pos) /*!< USB0 ENDPTPRIME: PERB5 Mask */\r
-#define USB0_ENDPTPRIME_PETB0_Pos 16 /*!< USB0 ENDPTPRIME: PETB0 Position */\r
-#define USB0_ENDPTPRIME_PETB0_Msk (0x01UL << USB0_ENDPTPRIME_PETB0_Pos) /*!< USB0 ENDPTPRIME: PETB0 Mask */\r
-#define USB0_ENDPTPRIME_PETB1_Pos 17 /*!< USB0 ENDPTPRIME: PETB1 Position */\r
-#define USB0_ENDPTPRIME_PETB1_Msk (0x01UL << USB0_ENDPTPRIME_PETB1_Pos) /*!< USB0 ENDPTPRIME: PETB1 Mask */\r
-#define USB0_ENDPTPRIME_PETB2_Pos 18 /*!< USB0 ENDPTPRIME: PETB2 Position */\r
-#define USB0_ENDPTPRIME_PETB2_Msk (0x01UL << USB0_ENDPTPRIME_PETB2_Pos) /*!< USB0 ENDPTPRIME: PETB2 Mask */\r
-#define USB0_ENDPTPRIME_PETB3_Pos 19 /*!< USB0 ENDPTPRIME: PETB3 Position */\r
-#define USB0_ENDPTPRIME_PETB3_Msk (0x01UL << USB0_ENDPTPRIME_PETB3_Pos) /*!< USB0 ENDPTPRIME: PETB3 Mask */\r
-#define USB0_ENDPTPRIME_PETB4_Pos 20 /*!< USB0 ENDPTPRIME: PETB4 Position */\r
-#define USB0_ENDPTPRIME_PETB4_Msk (0x01UL << USB0_ENDPTPRIME_PETB4_Pos) /*!< USB0 ENDPTPRIME: PETB4 Mask */\r
-#define USB0_ENDPTPRIME_PETB5_Pos 21 /*!< USB0 ENDPTPRIME: PETB5 Position */\r
-#define USB0_ENDPTPRIME_PETB5_Msk (0x01UL << USB0_ENDPTPRIME_PETB5_Pos) /*!< USB0 ENDPTPRIME: PETB5 Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTFLUSH ----------------------------------------\r
-#define USB0_ENDPTFLUSH_FERB0_Pos 0 /*!< USB0 ENDPTFLUSH: FERB0 Position */\r
-#define USB0_ENDPTFLUSH_FERB0_Msk (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos) /*!< USB0 ENDPTFLUSH: FERB0 Mask */\r
-#define USB0_ENDPTFLUSH_FERB1_Pos 1 /*!< USB0 ENDPTFLUSH: FERB1 Position */\r
-#define USB0_ENDPTFLUSH_FERB1_Msk (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos) /*!< USB0 ENDPTFLUSH: FERB1 Mask */\r
-#define USB0_ENDPTFLUSH_FERB2_Pos 2 /*!< USB0 ENDPTFLUSH: FERB2 Position */\r
-#define USB0_ENDPTFLUSH_FERB2_Msk (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos) /*!< USB0 ENDPTFLUSH: FERB2 Mask */\r
-#define USB0_ENDPTFLUSH_FERB3_Pos 3 /*!< USB0 ENDPTFLUSH: FERB3 Position */\r
-#define USB0_ENDPTFLUSH_FERB3_Msk (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos) /*!< USB0 ENDPTFLUSH: FERB3 Mask */\r
-#define USB0_ENDPTFLUSH_FERB4_Pos 4 /*!< USB0 ENDPTFLUSH: FERB4 Position */\r
-#define USB0_ENDPTFLUSH_FERB4_Msk (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos) /*!< USB0 ENDPTFLUSH: FERB4 Mask */\r
-#define USB0_ENDPTFLUSH_FERB5_Pos 5 /*!< USB0 ENDPTFLUSH: FERB5 Position */\r
-#define USB0_ENDPTFLUSH_FERB5_Msk (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos) /*!< USB0 ENDPTFLUSH: FERB5 Mask */\r
-#define USB0_ENDPTFLUSH_FETB0_Pos 16 /*!< USB0 ENDPTFLUSH: FETB0 Position */\r
-#define USB0_ENDPTFLUSH_FETB0_Msk (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos) /*!< USB0 ENDPTFLUSH: FETB0 Mask */\r
-#define USB0_ENDPTFLUSH_FETB1_Pos 17 /*!< USB0 ENDPTFLUSH: FETB1 Position */\r
-#define USB0_ENDPTFLUSH_FETB1_Msk (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos) /*!< USB0 ENDPTFLUSH: FETB1 Mask */\r
-#define USB0_ENDPTFLUSH_FETB2_Pos 18 /*!< USB0 ENDPTFLUSH: FETB2 Position */\r
-#define USB0_ENDPTFLUSH_FETB2_Msk (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos) /*!< USB0 ENDPTFLUSH: FETB2 Mask */\r
-#define USB0_ENDPTFLUSH_FETB3_Pos 19 /*!< USB0 ENDPTFLUSH: FETB3 Position */\r
-#define USB0_ENDPTFLUSH_FETB3_Msk (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos) /*!< USB0 ENDPTFLUSH: FETB3 Mask */\r
-#define USB0_ENDPTFLUSH_FETB4_Pos 20 /*!< USB0 ENDPTFLUSH: FETB4 Position */\r
-#define USB0_ENDPTFLUSH_FETB4_Msk (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos) /*!< USB0 ENDPTFLUSH: FETB4 Mask */\r
-#define USB0_ENDPTFLUSH_FETB5_Pos 21 /*!< USB0 ENDPTFLUSH: FETB5 Position */\r
-#define USB0_ENDPTFLUSH_FETB5_Msk (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos) /*!< USB0 ENDPTFLUSH: FETB5 Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTSTAT -----------------------------------------\r
-#define USB0_ENDPTSTAT_ERBR0_Pos 0 /*!< USB0 ENDPTSTAT: ERBR0 Position */\r
-#define USB0_ENDPTSTAT_ERBR0_Msk (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos) /*!< USB0 ENDPTSTAT: ERBR0 Mask */\r
-#define USB0_ENDPTSTAT_ERBR1_Pos 1 /*!< USB0 ENDPTSTAT: ERBR1 Position */\r
-#define USB0_ENDPTSTAT_ERBR1_Msk (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos) /*!< USB0 ENDPTSTAT: ERBR1 Mask */\r
-#define USB0_ENDPTSTAT_ERBR2_Pos 2 /*!< USB0 ENDPTSTAT: ERBR2 Position */\r
-#define USB0_ENDPTSTAT_ERBR2_Msk (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos) /*!< USB0 ENDPTSTAT: ERBR2 Mask */\r
-#define USB0_ENDPTSTAT_ERBR3_Pos 3 /*!< USB0 ENDPTSTAT: ERBR3 Position */\r
-#define USB0_ENDPTSTAT_ERBR3_Msk (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos) /*!< USB0 ENDPTSTAT: ERBR3 Mask */\r
-#define USB0_ENDPTSTAT_ERBR4_Pos 4 /*!< USB0 ENDPTSTAT: ERBR4 Position */\r
-#define USB0_ENDPTSTAT_ERBR4_Msk (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos) /*!< USB0 ENDPTSTAT: ERBR4 Mask */\r
-#define USB0_ENDPTSTAT_ERBR5_Pos 5 /*!< USB0 ENDPTSTAT: ERBR5 Position */\r
-#define USB0_ENDPTSTAT_ERBR5_Msk (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos) /*!< USB0 ENDPTSTAT: ERBR5 Mask */\r
-#define USB0_ENDPTSTAT_ETBR0_Pos 16 /*!< USB0 ENDPTSTAT: ETBR0 Position */\r
-#define USB0_ENDPTSTAT_ETBR0_Msk (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos) /*!< USB0 ENDPTSTAT: ETBR0 Mask */\r
-#define USB0_ENDPTSTAT_ETBR1_Pos 17 /*!< USB0 ENDPTSTAT: ETBR1 Position */\r
-#define USB0_ENDPTSTAT_ETBR1_Msk (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos) /*!< USB0 ENDPTSTAT: ETBR1 Mask */\r
-#define USB0_ENDPTSTAT_ETBR2_Pos 18 /*!< USB0 ENDPTSTAT: ETBR2 Position */\r
-#define USB0_ENDPTSTAT_ETBR2_Msk (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos) /*!< USB0 ENDPTSTAT: ETBR2 Mask */\r
-#define USB0_ENDPTSTAT_ETBR3_Pos 19 /*!< USB0 ENDPTSTAT: ETBR3 Position */\r
-#define USB0_ENDPTSTAT_ETBR3_Msk (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos) /*!< USB0 ENDPTSTAT: ETBR3 Mask */\r
-#define USB0_ENDPTSTAT_ETBR4_Pos 20 /*!< USB0 ENDPTSTAT: ETBR4 Position */\r
-#define USB0_ENDPTSTAT_ETBR4_Msk (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos) /*!< USB0 ENDPTSTAT: ETBR4 Mask */\r
-#define USB0_ENDPTSTAT_ETBR5_Pos 21 /*!< USB0 ENDPTSTAT: ETBR5 Position */\r
-#define USB0_ENDPTSTAT_ETBR5_Msk (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos) /*!< USB0 ENDPTSTAT: ETBR5 Mask */\r
-\r
-// ----------------------------------- USB0_ENDPTCOMPLETE ---------------------------------------\r
-#define USB0_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB0 ENDPTCOMPLETE: ERCE0 Position */\r
-#define USB0_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask */\r
-#define USB0_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB0 ENDPTCOMPLETE: ERCE1 Position */\r
-#define USB0_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask */\r
-#define USB0_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB0 ENDPTCOMPLETE: ERCE2 Position */\r
-#define USB0_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask */\r
-#define USB0_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB0 ENDPTCOMPLETE: ERCE3 Position */\r
-#define USB0_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask */\r
-#define USB0_ENDPTCOMPLETE_ERCE4_Pos 4 /*!< USB0 ENDPTCOMPLETE: ERCE4 Position */\r
-#define USB0_ENDPTCOMPLETE_ERCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask */\r
-#define USB0_ENDPTCOMPLETE_ERCE5_Pos 5 /*!< USB0 ENDPTCOMPLETE: ERCE5 Position */\r
-#define USB0_ENDPTCOMPLETE_ERCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask */\r
-#define USB0_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB0 ENDPTCOMPLETE: ETCE0 Position */\r
-#define USB0_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask */\r
-#define USB0_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB0 ENDPTCOMPLETE: ETCE1 Position */\r
-#define USB0_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask */\r
-#define USB0_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB0 ENDPTCOMPLETE: ETCE2 Position */\r
-#define USB0_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask */\r
-#define USB0_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB0 ENDPTCOMPLETE: ETCE3 Position */\r
-#define USB0_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask */\r
-#define USB0_ENDPTCOMPLETE_ETCE4_Pos 20 /*!< USB0 ENDPTCOMPLETE: ETCE4 Position */\r
-#define USB0_ENDPTCOMPLETE_ETCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask */\r
-#define USB0_ENDPTCOMPLETE_ETCE5_Pos 21 /*!< USB0 ENDPTCOMPLETE: ETCE5 Position */\r
-#define USB0_ENDPTCOMPLETE_ETCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTCTRL0 ----------------------------------------\r
-#define USB0_ENDPTCTRL0_RXS_Pos 0 /*!< USB0 ENDPTCTRL0: RXS Position */\r
-#define USB0_ENDPTCTRL0_RXS_Msk (0x01UL << USB0_ENDPTCTRL0_RXS_Pos) /*!< USB0 ENDPTCTRL0: RXS Mask */\r
-#define USB0_ENDPTCTRL0_RXT1_0_Pos 2 /*!< USB0 ENDPTCTRL0: RXT1_0 Position */\r
-#define USB0_ENDPTCTRL0_RXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos) /*!< USB0 ENDPTCTRL0: RXT1_0 Mask */\r
-#define USB0_ENDPTCTRL0_RXE_Pos 7 /*!< USB0 ENDPTCTRL0: RXE Position */\r
-#define USB0_ENDPTCTRL0_RXE_Msk (0x01UL << USB0_ENDPTCTRL0_RXE_Pos) /*!< USB0 ENDPTCTRL0: RXE Mask */\r
-#define USB0_ENDPTCTRL0_TXS_Pos 16 /*!< USB0 ENDPTCTRL0: TXS Position */\r
-#define USB0_ENDPTCTRL0_TXS_Msk (0x01UL << USB0_ENDPTCTRL0_TXS_Pos) /*!< USB0 ENDPTCTRL0: TXS Mask */\r
-#define USB0_ENDPTCTRL0_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL0: TXT1_0 Position */\r
-#define USB0_ENDPTCTRL0_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos) /*!< USB0 ENDPTCTRL0: TXT1_0 Mask */\r
-#define USB0_ENDPTCTRL0_TXE_Pos 23 /*!< USB0 ENDPTCTRL0: TXE Position */\r
-#define USB0_ENDPTCTRL0_TXE_Msk (0x01UL << USB0_ENDPTCTRL0_TXE_Pos) /*!< USB0 ENDPTCTRL0: TXE Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTCTRL1 ----------------------------------------\r
-#define USB0_ENDPTCTRL1_RXS_Pos 0 /*!< USB0 ENDPTCTRL1: RXS Position */\r
-#define USB0_ENDPTCTRL1_RXS_Msk (0x01UL << USB0_ENDPTCTRL1_RXS_Pos) /*!< USB0 ENDPTCTRL1: RXS Mask */\r
-#define USB0_ENDPTCTRL1_RXT_Pos 2 /*!< USB0 ENDPTCTRL1: RXT Position */\r
-#define USB0_ENDPTCTRL1_RXT_Msk (0x03UL << USB0_ENDPTCTRL1_RXT_Pos) /*!< USB0 ENDPTCTRL1: RXT Mask */\r
-#define USB0_ENDPTCTRL1_RXI_Pos 5 /*!< USB0 ENDPTCTRL1: RXI Position */\r
-#define USB0_ENDPTCTRL1_RXI_Msk (0x01UL << USB0_ENDPTCTRL1_RXI_Pos) /*!< USB0 ENDPTCTRL1: RXI Mask */\r
-#define USB0_ENDPTCTRL1_RXR_Pos 6 /*!< USB0 ENDPTCTRL1: RXR Position */\r
-#define USB0_ENDPTCTRL1_RXR_Msk (0x01UL << USB0_ENDPTCTRL1_RXR_Pos) /*!< USB0 ENDPTCTRL1: RXR Mask */\r
-#define USB0_ENDPTCTRL1_RXE_Pos 7 /*!< USB0 ENDPTCTRL1: RXE Position */\r
-#define USB0_ENDPTCTRL1_RXE_Msk (0x01UL << USB0_ENDPTCTRL1_RXE_Pos) /*!< USB0 ENDPTCTRL1: RXE Mask */\r
-#define USB0_ENDPTCTRL1_TXS_Pos 16 /*!< USB0 ENDPTCTRL1: TXS Position */\r
-#define USB0_ENDPTCTRL1_TXS_Msk (0x01UL << USB0_ENDPTCTRL1_TXS_Pos) /*!< USB0 ENDPTCTRL1: TXS Mask */\r
-#define USB0_ENDPTCTRL1_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL1: TXT1_0 Position */\r
-#define USB0_ENDPTCTRL1_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos) /*!< USB0 ENDPTCTRL1: TXT1_0 Mask */\r
-#define USB0_ENDPTCTRL1_TXI_Pos 21 /*!< USB0 ENDPTCTRL1: TXI Position */\r
-#define USB0_ENDPTCTRL1_TXI_Msk (0x01UL << USB0_ENDPTCTRL1_TXI_Pos) /*!< USB0 ENDPTCTRL1: TXI Mask */\r
-#define USB0_ENDPTCTRL1_TXR_Pos 22 /*!< USB0 ENDPTCTRL1: TXR Position */\r
-#define USB0_ENDPTCTRL1_TXR_Msk (0x01UL << USB0_ENDPTCTRL1_TXR_Pos) /*!< USB0 ENDPTCTRL1: TXR Mask */\r
-#define USB0_ENDPTCTRL1_TXE_Pos 23 /*!< USB0 ENDPTCTRL1: TXE Position */\r
-#define USB0_ENDPTCTRL1_TXE_Msk (0x01UL << USB0_ENDPTCTRL1_TXE_Pos) /*!< USB0 ENDPTCTRL1: TXE Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTCTRL2 ----------------------------------------\r
-#define USB0_ENDPTCTRL2_RXS_Pos 0 /*!< USB0 ENDPTCTRL2: RXS Position */\r
-#define USB0_ENDPTCTRL2_RXS_Msk (0x01UL << USB0_ENDPTCTRL2_RXS_Pos) /*!< USB0 ENDPTCTRL2: RXS Mask */\r
-#define USB0_ENDPTCTRL2_RXT_Pos 2 /*!< USB0 ENDPTCTRL2: RXT Position */\r
-#define USB0_ENDPTCTRL2_RXT_Msk (0x03UL << USB0_ENDPTCTRL2_RXT_Pos) /*!< USB0 ENDPTCTRL2: RXT Mask */\r
-#define USB0_ENDPTCTRL2_RXI_Pos 5 /*!< USB0 ENDPTCTRL2: RXI Position */\r
-#define USB0_ENDPTCTRL2_RXI_Msk (0x01UL << USB0_ENDPTCTRL2_RXI_Pos) /*!< USB0 ENDPTCTRL2: RXI Mask */\r
-#define USB0_ENDPTCTRL2_RXR_Pos 6 /*!< USB0 ENDPTCTRL2: RXR Position */\r
-#define USB0_ENDPTCTRL2_RXR_Msk (0x01UL << USB0_ENDPTCTRL2_RXR_Pos) /*!< USB0 ENDPTCTRL2: RXR Mask */\r
-#define USB0_ENDPTCTRL2_RXE_Pos 7 /*!< USB0 ENDPTCTRL2: RXE Position */\r
-#define USB0_ENDPTCTRL2_RXE_Msk (0x01UL << USB0_ENDPTCTRL2_RXE_Pos) /*!< USB0 ENDPTCTRL2: RXE Mask */\r
-#define USB0_ENDPTCTRL2_TXS_Pos 16 /*!< USB0 ENDPTCTRL2: TXS Position */\r
-#define USB0_ENDPTCTRL2_TXS_Msk (0x01UL << USB0_ENDPTCTRL2_TXS_Pos) /*!< USB0 ENDPTCTRL2: TXS Mask */\r
-#define USB0_ENDPTCTRL2_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL2: TXT1_0 Position */\r
-#define USB0_ENDPTCTRL2_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos) /*!< USB0 ENDPTCTRL2: TXT1_0 Mask */\r
-#define USB0_ENDPTCTRL2_TXI_Pos 21 /*!< USB0 ENDPTCTRL2: TXI Position */\r
-#define USB0_ENDPTCTRL2_TXI_Msk (0x01UL << USB0_ENDPTCTRL2_TXI_Pos) /*!< USB0 ENDPTCTRL2: TXI Mask */\r
-#define USB0_ENDPTCTRL2_TXR_Pos 22 /*!< USB0 ENDPTCTRL2: TXR Position */\r
-#define USB0_ENDPTCTRL2_TXR_Msk (0x01UL << USB0_ENDPTCTRL2_TXR_Pos) /*!< USB0 ENDPTCTRL2: TXR Mask */\r
-#define USB0_ENDPTCTRL2_TXE_Pos 23 /*!< USB0 ENDPTCTRL2: TXE Position */\r
-#define USB0_ENDPTCTRL2_TXE_Msk (0x01UL << USB0_ENDPTCTRL2_TXE_Pos) /*!< USB0 ENDPTCTRL2: TXE Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTCTRL3 ----------------------------------------\r
-#define USB0_ENDPTCTRL3_RXS_Pos 0 /*!< USB0 ENDPTCTRL3: RXS Position */\r
-#define USB0_ENDPTCTRL3_RXS_Msk (0x01UL << USB0_ENDPTCTRL3_RXS_Pos) /*!< USB0 ENDPTCTRL3: RXS Mask */\r
-#define USB0_ENDPTCTRL3_RXT_Pos 2 /*!< USB0 ENDPTCTRL3: RXT Position */\r
-#define USB0_ENDPTCTRL3_RXT_Msk (0x03UL << USB0_ENDPTCTRL3_RXT_Pos) /*!< USB0 ENDPTCTRL3: RXT Mask */\r
-#define USB0_ENDPTCTRL3_RXI_Pos 5 /*!< USB0 ENDPTCTRL3: RXI Position */\r
-#define USB0_ENDPTCTRL3_RXI_Msk (0x01UL << USB0_ENDPTCTRL3_RXI_Pos) /*!< USB0 ENDPTCTRL3: RXI Mask */\r
-#define USB0_ENDPTCTRL3_RXR_Pos 6 /*!< USB0 ENDPTCTRL3: RXR Position */\r
-#define USB0_ENDPTCTRL3_RXR_Msk (0x01UL << USB0_ENDPTCTRL3_RXR_Pos) /*!< USB0 ENDPTCTRL3: RXR Mask */\r
-#define USB0_ENDPTCTRL3_RXE_Pos 7 /*!< USB0 ENDPTCTRL3: RXE Position */\r
-#define USB0_ENDPTCTRL3_RXE_Msk (0x01UL << USB0_ENDPTCTRL3_RXE_Pos) /*!< USB0 ENDPTCTRL3: RXE Mask */\r
-#define USB0_ENDPTCTRL3_TXS_Pos 16 /*!< USB0 ENDPTCTRL3: TXS Position */\r
-#define USB0_ENDPTCTRL3_TXS_Msk (0x01UL << USB0_ENDPTCTRL3_TXS_Pos) /*!< USB0 ENDPTCTRL3: TXS Mask */\r
-#define USB0_ENDPTCTRL3_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL3: TXT1_0 Position */\r
-#define USB0_ENDPTCTRL3_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos) /*!< USB0 ENDPTCTRL3: TXT1_0 Mask */\r
-#define USB0_ENDPTCTRL3_TXI_Pos 21 /*!< USB0 ENDPTCTRL3: TXI Position */\r
-#define USB0_ENDPTCTRL3_TXI_Msk (0x01UL << USB0_ENDPTCTRL3_TXI_Pos) /*!< USB0 ENDPTCTRL3: TXI Mask */\r
-#define USB0_ENDPTCTRL3_TXR_Pos 22 /*!< USB0 ENDPTCTRL3: TXR Position */\r
-#define USB0_ENDPTCTRL3_TXR_Msk (0x01UL << USB0_ENDPTCTRL3_TXR_Pos) /*!< USB0 ENDPTCTRL3: TXR Mask */\r
-#define USB0_ENDPTCTRL3_TXE_Pos 23 /*!< USB0 ENDPTCTRL3: TXE Position */\r
-#define USB0_ENDPTCTRL3_TXE_Msk (0x01UL << USB0_ENDPTCTRL3_TXE_Pos) /*!< USB0 ENDPTCTRL3: TXE Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTCTRL4 ----------------------------------------\r
-#define USB0_ENDPTCTRL4_RXS_Pos 0 /*!< USB0 ENDPTCTRL4: RXS Position */\r
-#define USB0_ENDPTCTRL4_RXS_Msk (0x01UL << USB0_ENDPTCTRL4_RXS_Pos) /*!< USB0 ENDPTCTRL4: RXS Mask */\r
-#define USB0_ENDPTCTRL4_RXT_Pos 2 /*!< USB0 ENDPTCTRL4: RXT Position */\r
-#define USB0_ENDPTCTRL4_RXT_Msk (0x03UL << USB0_ENDPTCTRL4_RXT_Pos) /*!< USB0 ENDPTCTRL4: RXT Mask */\r
-#define USB0_ENDPTCTRL4_RXI_Pos 5 /*!< USB0 ENDPTCTRL4: RXI Position */\r
-#define USB0_ENDPTCTRL4_RXI_Msk (0x01UL << USB0_ENDPTCTRL4_RXI_Pos) /*!< USB0 ENDPTCTRL4: RXI Mask */\r
-#define USB0_ENDPTCTRL4_RXR_Pos 6 /*!< USB0 ENDPTCTRL4: RXR Position */\r
-#define USB0_ENDPTCTRL4_RXR_Msk (0x01UL << USB0_ENDPTCTRL4_RXR_Pos) /*!< USB0 ENDPTCTRL4: RXR Mask */\r
-#define USB0_ENDPTCTRL4_RXE_Pos 7 /*!< USB0 ENDPTCTRL4: RXE Position */\r
-#define USB0_ENDPTCTRL4_RXE_Msk (0x01UL << USB0_ENDPTCTRL4_RXE_Pos) /*!< USB0 ENDPTCTRL4: RXE Mask */\r
-#define USB0_ENDPTCTRL4_TXS_Pos 16 /*!< USB0 ENDPTCTRL4: TXS Position */\r
-#define USB0_ENDPTCTRL4_TXS_Msk (0x01UL << USB0_ENDPTCTRL4_TXS_Pos) /*!< USB0 ENDPTCTRL4: TXS Mask */\r
-#define USB0_ENDPTCTRL4_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL4: TXT1_0 Position */\r
-#define USB0_ENDPTCTRL4_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos) /*!< USB0 ENDPTCTRL4: TXT1_0 Mask */\r
-#define USB0_ENDPTCTRL4_TXI_Pos 21 /*!< USB0 ENDPTCTRL4: TXI Position */\r
-#define USB0_ENDPTCTRL4_TXI_Msk (0x01UL << USB0_ENDPTCTRL4_TXI_Pos) /*!< USB0 ENDPTCTRL4: TXI Mask */\r
-#define USB0_ENDPTCTRL4_TXR_Pos 22 /*!< USB0 ENDPTCTRL4: TXR Position */\r
-#define USB0_ENDPTCTRL4_TXR_Msk (0x01UL << USB0_ENDPTCTRL4_TXR_Pos) /*!< USB0 ENDPTCTRL4: TXR Mask */\r
-#define USB0_ENDPTCTRL4_TXE_Pos 23 /*!< USB0 ENDPTCTRL4: TXE Position */\r
-#define USB0_ENDPTCTRL4_TXE_Msk (0x01UL << USB0_ENDPTCTRL4_TXE_Pos) /*!< USB0 ENDPTCTRL4: TXE Mask */\r
-\r
-// ------------------------------------- USB0_ENDPTCTRL5 ----------------------------------------\r
-#define USB0_ENDPTCTRL5_RXS_Pos 0 /*!< USB0 ENDPTCTRL5: RXS Position */\r
-#define USB0_ENDPTCTRL5_RXS_Msk (0x01UL << USB0_ENDPTCTRL5_RXS_Pos) /*!< USB0 ENDPTCTRL5: RXS Mask */\r
-#define USB0_ENDPTCTRL5_RXT_Pos 2 /*!< USB0 ENDPTCTRL5: RXT Position */\r
-#define USB0_ENDPTCTRL5_RXT_Msk (0x03UL << USB0_ENDPTCTRL5_RXT_Pos) /*!< USB0 ENDPTCTRL5: RXT Mask */\r
-#define USB0_ENDPTCTRL5_RXI_Pos 5 /*!< USB0 ENDPTCTRL5: RXI Position */\r
-#define USB0_ENDPTCTRL5_RXI_Msk (0x01UL << USB0_ENDPTCTRL5_RXI_Pos) /*!< USB0 ENDPTCTRL5: RXI Mask */\r
-#define USB0_ENDPTCTRL5_RXR_Pos 6 /*!< USB0 ENDPTCTRL5: RXR Position */\r
-#define USB0_ENDPTCTRL5_RXR_Msk (0x01UL << USB0_ENDPTCTRL5_RXR_Pos) /*!< USB0 ENDPTCTRL5: RXR Mask */\r
-#define USB0_ENDPTCTRL5_RXE_Pos 7 /*!< USB0 ENDPTCTRL5: RXE Position */\r
-#define USB0_ENDPTCTRL5_RXE_Msk (0x01UL << USB0_ENDPTCTRL5_RXE_Pos) /*!< USB0 ENDPTCTRL5: RXE Mask */\r
-#define USB0_ENDPTCTRL5_TXS_Pos 16 /*!< USB0 ENDPTCTRL5: TXS Position */\r
-#define USB0_ENDPTCTRL5_TXS_Msk (0x01UL << USB0_ENDPTCTRL5_TXS_Pos) /*!< USB0 ENDPTCTRL5: TXS Mask */\r
-#define USB0_ENDPTCTRL5_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL5: TXT1_0 Position */\r
-#define USB0_ENDPTCTRL5_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos) /*!< USB0 ENDPTCTRL5: TXT1_0 Mask */\r
-#define USB0_ENDPTCTRL5_TXI_Pos 21 /*!< USB0 ENDPTCTRL5: TXI Position */\r
-#define USB0_ENDPTCTRL5_TXI_Msk (0x01UL << USB0_ENDPTCTRL5_TXI_Pos) /*!< USB0 ENDPTCTRL5: TXI Mask */\r
-#define USB0_ENDPTCTRL5_TXR_Pos 22 /*!< USB0 ENDPTCTRL5: TXR Position */\r
-#define USB0_ENDPTCTRL5_TXR_Msk (0x01UL << USB0_ENDPTCTRL5_TXR_Pos) /*!< USB0 ENDPTCTRL5: TXR Mask */\r
-#define USB0_ENDPTCTRL5_TXE_Pos 23 /*!< USB0 ENDPTCTRL5: TXE Position */\r
-#define USB0_ENDPTCTRL5_TXE_Msk (0x01UL << USB0_ENDPTCTRL5_TXE_Pos) /*!< USB0 ENDPTCTRL5: TXE Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- USB1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ------------------------------------- USB1_CAPLENGTH -----------------------------------------\r
-#define USB1_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB1 CAPLENGTH: CAPLENGTH Position */\r
-#define USB1_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos) /*!< USB1 CAPLENGTH: CAPLENGTH Mask */\r
-#define USB1_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB1 CAPLENGTH: HCIVERSION Position */\r
-#define USB1_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos) /*!< USB1 CAPLENGTH: HCIVERSION Mask */\r
-\r
-// ------------------------------------- USB1_HCSPARAMS -----------------------------------------\r
-#define USB1_HCSPARAMS_N_PORTS_Pos 0 /*!< USB1 HCSPARAMS: N_PORTS Position */\r
-#define USB1_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos) /*!< USB1 HCSPARAMS: N_PORTS Mask */\r
-#define USB1_HCSPARAMS_PPC_Pos 4 /*!< USB1 HCSPARAMS: PPC Position */\r
-#define USB1_HCSPARAMS_PPC_Msk (0x01UL << USB1_HCSPARAMS_PPC_Pos) /*!< USB1 HCSPARAMS: PPC Mask */\r
-#define USB1_HCSPARAMS_N_PCC_Pos 8 /*!< USB1 HCSPARAMS: N_PCC Position */\r
-#define USB1_HCSPARAMS_N_PCC_Msk (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos) /*!< USB1 HCSPARAMS: N_PCC Mask */\r
-#define USB1_HCSPARAMS_N_CC_Pos 12 /*!< USB1 HCSPARAMS: N_CC Position */\r
-#define USB1_HCSPARAMS_N_CC_Msk (0x0fUL << USB1_HCSPARAMS_N_CC_Pos) /*!< USB1 HCSPARAMS: N_CC Mask */\r
-#define USB1_HCSPARAMS_PI_Pos 16 /*!< USB1 HCSPARAMS: PI Position */\r
-#define USB1_HCSPARAMS_PI_Msk (0x01UL << USB1_HCSPARAMS_PI_Pos) /*!< USB1 HCSPARAMS: PI Mask */\r
-#define USB1_HCSPARAMS_N_PTT_Pos 20 /*!< USB1 HCSPARAMS: N_PTT Position */\r
-#define USB1_HCSPARAMS_N_PTT_Msk (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos) /*!< USB1 HCSPARAMS: N_PTT Mask */\r
-#define USB1_HCSPARAMS_N_TT_Pos 24 /*!< USB1 HCSPARAMS: N_TT Position */\r
-#define USB1_HCSPARAMS_N_TT_Msk (0x0fUL << USB1_HCSPARAMS_N_TT_Pos) /*!< USB1 HCSPARAMS: N_TT Mask */\r
-\r
-// ------------------------------------- USB1_HCCPARAMS -----------------------------------------\r
-#define USB1_HCCPARAMS_ADC_Pos 0 /*!< USB1 HCCPARAMS: ADC Position */\r
-#define USB1_HCCPARAMS_ADC_Msk (0x01UL << USB1_HCCPARAMS_ADC_Pos) /*!< USB1 HCCPARAMS: ADC Mask */\r
-#define USB1_HCCPARAMS_PFL_Pos 1 /*!< USB1 HCCPARAMS: PFL Position */\r
-#define USB1_HCCPARAMS_PFL_Msk (0x01UL << USB1_HCCPARAMS_PFL_Pos) /*!< USB1 HCCPARAMS: PFL Mask */\r
-#define USB1_HCCPARAMS_ASP_Pos 2 /*!< USB1 HCCPARAMS: ASP Position */\r
-#define USB1_HCCPARAMS_ASP_Msk (0x01UL << USB1_HCCPARAMS_ASP_Pos) /*!< USB1 HCCPARAMS: ASP Mask */\r
-#define USB1_HCCPARAMS_IST_Pos 4 /*!< USB1 HCCPARAMS: IST Position */\r
-#define USB1_HCCPARAMS_IST_Msk (0x0fUL << USB1_HCCPARAMS_IST_Pos) /*!< USB1 HCCPARAMS: IST Mask */\r
-#define USB1_HCCPARAMS_EECP_Pos 8 /*!< USB1 HCCPARAMS: EECP Position */\r
-#define USB1_HCCPARAMS_EECP_Msk (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos) /*!< USB1 HCCPARAMS: EECP Mask */\r
-\r
-// ------------------------------------- USB1_DCIVERSION ----------------------------------------\r
-#define USB1_DCIVERSION_DCIVERSION_Pos 0 /*!< USB1 DCIVERSION: DCIVERSION Position */\r
-#define USB1_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos) /*!< USB1 DCIVERSION: DCIVERSION Mask */\r
-\r
-// -------------------------------------- USB1_USBCMD_D -----------------------------------------\r
-#define USB1_USBCMD_D_RS_Pos 0 /*!< USB1 USBCMD_D: RS Position */\r
-#define USB1_USBCMD_D_RS_Msk (0x01UL << USB1_USBCMD_D_RS_Pos) /*!< USB1 USBCMD_D: RS Mask */\r
-#define USB1_USBCMD_D_RST_Pos 1 /*!< USB1 USBCMD_D: RST Position */\r
-#define USB1_USBCMD_D_RST_Msk (0x01UL << USB1_USBCMD_D_RST_Pos) /*!< USB1 USBCMD_D: RST Mask */\r
-#define USB1_USBCMD_D_SUTW_Pos 13 /*!< USB1 USBCMD_D: SUTW Position */\r
-#define USB1_USBCMD_D_SUTW_Msk (0x01UL << USB1_USBCMD_D_SUTW_Pos) /*!< USB1 USBCMD_D: SUTW Mask */\r
-#define USB1_USBCMD_D_ATDTW_Pos 14 /*!< USB1 USBCMD_D: ATDTW Position */\r
-#define USB1_USBCMD_D_ATDTW_Msk (0x01UL << USB1_USBCMD_D_ATDTW_Pos) /*!< USB1 USBCMD_D: ATDTW Mask */\r
-#define USB1_USBCMD_D_FS2_Pos 15 /*!< USB1 USBCMD_D: FS2 Position */\r
-#define USB1_USBCMD_D_FS2_Msk (0x01UL << USB1_USBCMD_D_FS2_Pos) /*!< USB1 USBCMD_D: FS2 Mask */\r
-#define USB1_USBCMD_D_ITC_Pos 16 /*!< USB1 USBCMD_D: ITC Position */\r
-#define USB1_USBCMD_D_ITC_Msk (0x000000ffUL << USB1_USBCMD_D_ITC_Pos) /*!< USB1 USBCMD_D: ITC Mask */\r
-\r
-// -------------------------------------- USB1_USBCMD_H -----------------------------------------\r
-#define USB1_USBCMD_H_RS_Pos 0 /*!< USB1 USBCMD_H: RS Position */\r
-#define USB1_USBCMD_H_RS_Msk (0x01UL << USB1_USBCMD_H_RS_Pos) /*!< USB1 USBCMD_H: RS Mask */\r
-#define USB1_USBCMD_H_RST_Pos 1 /*!< USB1 USBCMD_H: RST Position */\r
-#define USB1_USBCMD_H_RST_Msk (0x01UL << USB1_USBCMD_H_RST_Pos) /*!< USB1 USBCMD_H: RST Mask */\r
-#define USB1_USBCMD_H_FS0_Pos 2 /*!< USB1 USBCMD_H: FS0 Position */\r
-#define USB1_USBCMD_H_FS0_Msk (0x01UL << USB1_USBCMD_H_FS0_Pos) /*!< USB1 USBCMD_H: FS0 Mask */\r
-#define USB1_USBCMD_H_FS1_Pos 3 /*!< USB1 USBCMD_H: FS1 Position */\r
-#define USB1_USBCMD_H_FS1_Msk (0x01UL << USB1_USBCMD_H_FS1_Pos) /*!< USB1 USBCMD_H: FS1 Mask */\r
-#define USB1_USBCMD_H_PSE_Pos 4 /*!< USB1 USBCMD_H: PSE Position */\r
-#define USB1_USBCMD_H_PSE_Msk (0x01UL << USB1_USBCMD_H_PSE_Pos) /*!< USB1 USBCMD_H: PSE Mask */\r
-#define USB1_USBCMD_H_ASE_Pos 5 /*!< USB1 USBCMD_H: ASE Position */\r
-#define USB1_USBCMD_H_ASE_Msk (0x01UL << USB1_USBCMD_H_ASE_Pos) /*!< USB1 USBCMD_H: ASE Mask */\r
-#define USB1_USBCMD_H_IAA_Pos 6 /*!< USB1 USBCMD_H: IAA Position */\r
-#define USB1_USBCMD_H_IAA_Msk (0x01UL << USB1_USBCMD_H_IAA_Pos) /*!< USB1 USBCMD_H: IAA Mask */\r
-#define USB1_USBCMD_H_ASP1_0_Pos 8 /*!< USB1 USBCMD_H: ASP1_0 Position */\r
-#define USB1_USBCMD_H_ASP1_0_Msk (0x03UL << USB1_USBCMD_H_ASP1_0_Pos) /*!< USB1 USBCMD_H: ASP1_0 Mask */\r
-#define USB1_USBCMD_H_ASPE_Pos 11 /*!< USB1 USBCMD_H: ASPE Position */\r
-#define USB1_USBCMD_H_ASPE_Msk (0x01UL << USB1_USBCMD_H_ASPE_Pos) /*!< USB1 USBCMD_H: ASPE Mask */\r
-#define USB1_USBCMD_H_FS2_Pos 15 /*!< USB1 USBCMD_H: FS2 Position */\r
-#define USB1_USBCMD_H_FS2_Msk (0x01UL << USB1_USBCMD_H_FS2_Pos) /*!< USB1 USBCMD_H: FS2 Mask */\r
-#define USB1_USBCMD_H_ITC_Pos 16 /*!< USB1 USBCMD_H: ITC Position */\r
-#define USB1_USBCMD_H_ITC_Msk (0x000000ffUL << USB1_USBCMD_H_ITC_Pos) /*!< USB1 USBCMD_H: ITC Mask */\r
-\r
-// -------------------------------------- USB1_USBSTS_D -----------------------------------------\r
-#define USB1_USBSTS_D_UI_Pos 0 /*!< USB1 USBSTS_D: UI Position */\r
-#define USB1_USBSTS_D_UI_Msk (0x01UL << USB1_USBSTS_D_UI_Pos) /*!< USB1 USBSTS_D: UI Mask */\r
-#define USB1_USBSTS_D_UEI_Pos 1 /*!< USB1 USBSTS_D: UEI Position */\r
-#define USB1_USBSTS_D_UEI_Msk (0x01UL << USB1_USBSTS_D_UEI_Pos) /*!< USB1 USBSTS_D: UEI Mask */\r
-#define USB1_USBSTS_D_PCI_Pos 2 /*!< USB1 USBSTS_D: PCI Position */\r
-#define USB1_USBSTS_D_PCI_Msk (0x01UL << USB1_USBSTS_D_PCI_Pos) /*!< USB1 USBSTS_D: PCI Mask */\r
-#define USB1_USBSTS_D_URI_Pos 6 /*!< USB1 USBSTS_D: URI Position */\r
-#define USB1_USBSTS_D_URI_Msk (0x01UL << USB1_USBSTS_D_URI_Pos) /*!< USB1 USBSTS_D: URI Mask */\r
-#define USB1_USBSTS_D_SRI_Pos 7 /*!< USB1 USBSTS_D: SRI Position */\r
-#define USB1_USBSTS_D_SRI_Msk (0x01UL << USB1_USBSTS_D_SRI_Pos) /*!< USB1 USBSTS_D: SRI Mask */\r
-#define USB1_USBSTS_D_SLI_Pos 8 /*!< USB1 USBSTS_D: SLI Position */\r
-#define USB1_USBSTS_D_SLI_Msk (0x01UL << USB1_USBSTS_D_SLI_Pos) /*!< USB1 USBSTS_D: SLI Mask */\r
-#define USB1_USBSTS_D_NAKI_Pos 16 /*!< USB1 USBSTS_D: NAKI Position */\r
-#define USB1_USBSTS_D_NAKI_Msk (0x01UL << USB1_USBSTS_D_NAKI_Pos) /*!< USB1 USBSTS_D: NAKI Mask */\r
-\r
-// -------------------------------------- USB1_USBSTS_H -----------------------------------------\r
-#define USB1_USBSTS_H_UI_Pos 0 /*!< USB1 USBSTS_H: UI Position */\r
-#define USB1_USBSTS_H_UI_Msk (0x01UL << USB1_USBSTS_H_UI_Pos) /*!< USB1 USBSTS_H: UI Mask */\r
-#define USB1_USBSTS_H_UEI_Pos 1 /*!< USB1 USBSTS_H: UEI Position */\r
-#define USB1_USBSTS_H_UEI_Msk (0x01UL << USB1_USBSTS_H_UEI_Pos) /*!< USB1 USBSTS_H: UEI Mask */\r
-#define USB1_USBSTS_H_PCI_Pos 2 /*!< USB1 USBSTS_H: PCI Position */\r
-#define USB1_USBSTS_H_PCI_Msk (0x01UL << USB1_USBSTS_H_PCI_Pos) /*!< USB1 USBSTS_H: PCI Mask */\r
-#define USB1_USBSTS_H_FRI_Pos 3 /*!< USB1 USBSTS_H: FRI Position */\r
-#define USB1_USBSTS_H_FRI_Msk (0x01UL << USB1_USBSTS_H_FRI_Pos) /*!< USB1 USBSTS_H: FRI Mask */\r
-#define USB1_USBSTS_H_AAI_Pos 5 /*!< USB1 USBSTS_H: AAI Position */\r
-#define USB1_USBSTS_H_AAI_Msk (0x01UL << USB1_USBSTS_H_AAI_Pos) /*!< USB1 USBSTS_H: AAI Mask */\r
-#define USB1_USBSTS_H_SRI_Pos 7 /*!< USB1 USBSTS_H: SRI Position */\r
-#define USB1_USBSTS_H_SRI_Msk (0x01UL << USB1_USBSTS_H_SRI_Pos) /*!< USB1 USBSTS_H: SRI Mask */\r
-#define USB1_USBSTS_H_SLI_Pos 8 /*!< USB1 USBSTS_H: SLI Position */\r
-#define USB1_USBSTS_H_SLI_Msk (0x01UL << USB1_USBSTS_H_SLI_Pos) /*!< USB1 USBSTS_H: SLI Mask */\r
-#define USB1_USBSTS_H_HCH_Pos 12 /*!< USB1 USBSTS_H: HCH Position */\r
-#define USB1_USBSTS_H_HCH_Msk (0x01UL << USB1_USBSTS_H_HCH_Pos) /*!< USB1 USBSTS_H: HCH Mask */\r
-#define USB1_USBSTS_H_RCL_Pos 13 /*!< USB1 USBSTS_H: RCL Position */\r
-#define USB1_USBSTS_H_RCL_Msk (0x01UL << USB1_USBSTS_H_RCL_Pos) /*!< USB1 USBSTS_H: RCL Mask */\r
-#define USB1_USBSTS_H_PS_Pos 14 /*!< USB1 USBSTS_H: PS Position */\r
-#define USB1_USBSTS_H_PS_Msk (0x01UL << USB1_USBSTS_H_PS_Pos) /*!< USB1 USBSTS_H: PS Mask */\r
-#define USB1_USBSTS_H_AS_Pos 15 /*!< USB1 USBSTS_H: AS Position */\r
-#define USB1_USBSTS_H_AS_Msk (0x01UL << USB1_USBSTS_H_AS_Pos) /*!< USB1 USBSTS_H: AS Mask */\r
-#define USB1_USBSTS_H_UAI_Pos 18 /*!< USB1 USBSTS_H: UAI Position */\r
-#define USB1_USBSTS_H_UAI_Msk (0x01UL << USB1_USBSTS_H_UAI_Pos) /*!< USB1 USBSTS_H: UAI Mask */\r
-#define USB1_USBSTS_H_UPI_Pos 19 /*!< USB1 USBSTS_H: UPI Position */\r
-#define USB1_USBSTS_H_UPI_Msk (0x01UL << USB1_USBSTS_H_UPI_Pos) /*!< USB1 USBSTS_H: UPI Mask */\r
-\r
-// ------------------------------------- USB1_USBINTR_D -----------------------------------------\r
-#define USB1_USBINTR_D_UE_Pos 0 /*!< USB1 USBINTR_D: UE Position */\r
-#define USB1_USBINTR_D_UE_Msk (0x01UL << USB1_USBINTR_D_UE_Pos) /*!< USB1 USBINTR_D: UE Mask */\r
-#define USB1_USBINTR_D_UEE_Pos 1 /*!< USB1 USBINTR_D: UEE Position */\r
-#define USB1_USBINTR_D_UEE_Msk (0x01UL << USB1_USBINTR_D_UEE_Pos) /*!< USB1 USBINTR_D: UEE Mask */\r
-#define USB1_USBINTR_D_PCE_Pos 2 /*!< USB1 USBINTR_D: PCE Position */\r
-#define USB1_USBINTR_D_PCE_Msk (0x01UL << USB1_USBINTR_D_PCE_Pos) /*!< USB1 USBINTR_D: PCE Mask */\r
-#define USB1_USBINTR_D_URE_Pos 6 /*!< USB1 USBINTR_D: URE Position */\r
-#define USB1_USBINTR_D_URE_Msk (0x01UL << USB1_USBINTR_D_URE_Pos) /*!< USB1 USBINTR_D: URE Mask */\r
-#define USB1_USBINTR_D_SRE_Pos 7 /*!< USB1 USBINTR_D: SRE Position */\r
-#define USB1_USBINTR_D_SRE_Msk (0x01UL << USB1_USBINTR_D_SRE_Pos) /*!< USB1 USBINTR_D: SRE Mask */\r
-#define USB1_USBINTR_D_SLE_Pos 8 /*!< USB1 USBINTR_D: SLE Position */\r
-#define USB1_USBINTR_D_SLE_Msk (0x01UL << USB1_USBINTR_D_SLE_Pos) /*!< USB1 USBINTR_D: SLE Mask */\r
-#define USB1_USBINTR_D_NAKE_Pos 16 /*!< USB1 USBINTR_D: NAKE Position */\r
-#define USB1_USBINTR_D_NAKE_Msk (0x01UL << USB1_USBINTR_D_NAKE_Pos) /*!< USB1 USBINTR_D: NAKE Mask */\r
-#define USB1_USBINTR_D_UAIE_Pos 18 /*!< USB1 USBINTR_D: UAIE Position */\r
-#define USB1_USBINTR_D_UAIE_Msk (0x01UL << USB1_USBINTR_D_UAIE_Pos) /*!< USB1 USBINTR_D: UAIE Mask */\r
-#define USB1_USBINTR_D_UPIA_Pos 19 /*!< USB1 USBINTR_D: UPIA Position */\r
-#define USB1_USBINTR_D_UPIA_Msk (0x01UL << USB1_USBINTR_D_UPIA_Pos) /*!< USB1 USBINTR_D: UPIA Mask */\r
-\r
-// ------------------------------------- USB1_USBINTR_H -----------------------------------------\r
-#define USB1_USBINTR_H_UE_Pos 0 /*!< USB1 USBINTR_H: UE Position */\r
-#define USB1_USBINTR_H_UE_Msk (0x01UL << USB1_USBINTR_H_UE_Pos) /*!< USB1 USBINTR_H: UE Mask */\r
-#define USB1_USBINTR_H_UEE_Pos 1 /*!< USB1 USBINTR_H: UEE Position */\r
-#define USB1_USBINTR_H_UEE_Msk (0x01UL << USB1_USBINTR_H_UEE_Pos) /*!< USB1 USBINTR_H: UEE Mask */\r
-#define USB1_USBINTR_H_PCE_Pos 2 /*!< USB1 USBINTR_H: PCE Position */\r
-#define USB1_USBINTR_H_PCE_Msk (0x01UL << USB1_USBINTR_H_PCE_Pos) /*!< USB1 USBINTR_H: PCE Mask */\r
-#define USB1_USBINTR_H_FRE_Pos 3 /*!< USB1 USBINTR_H: FRE Position */\r
-#define USB1_USBINTR_H_FRE_Msk (0x01UL << USB1_USBINTR_H_FRE_Pos) /*!< USB1 USBINTR_H: FRE Mask */\r
-#define USB1_USBINTR_H_AAE_Pos 5 /*!< USB1 USBINTR_H: AAE Position */\r
-#define USB1_USBINTR_H_AAE_Msk (0x01UL << USB1_USBINTR_H_AAE_Pos) /*!< USB1 USBINTR_H: AAE Mask */\r
-#define USB1_USBINTR_H_SRE_Pos 7 /*!< USB1 USBINTR_H: SRE Position */\r
-#define USB1_USBINTR_H_SRE_Msk (0x01UL << USB1_USBINTR_H_SRE_Pos) /*!< USB1 USBINTR_H: SRE Mask */\r
-#define USB1_USBINTR_H_UAIE_Pos 18 /*!< USB1 USBINTR_H: UAIE Position */\r
-#define USB1_USBINTR_H_UAIE_Msk (0x01UL << USB1_USBINTR_H_UAIE_Pos) /*!< USB1 USBINTR_H: UAIE Mask */\r
-#define USB1_USBINTR_H_UPIA_Pos 19 /*!< USB1 USBINTR_H: UPIA Position */\r
-#define USB1_USBINTR_H_UPIA_Msk (0x01UL << USB1_USBINTR_H_UPIA_Pos) /*!< USB1 USBINTR_H: UPIA Mask */\r
-\r
-// ------------------------------------- USB1_FRINDEX_D -----------------------------------------\r
-#define USB1_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */\r
-#define USB1_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask */\r
-#define USB1_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */\r
-#define USB1_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask */\r
-\r
-// ------------------------------------- USB1_FRINDEX_H -----------------------------------------\r
-#define USB1_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */\r
-#define USB1_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask */\r
-#define USB1_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */\r
-#define USB1_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask */\r
-\r
-// ------------------------------------- USB1_DEVICEADDR ----------------------------------------\r
-#define USB1_DEVICEADDR_USBADRA_Pos 24 /*!< USB1 DEVICEADDR: USBADRA Position */\r
-#define USB1_DEVICEADDR_USBADRA_Msk (0x01UL << USB1_DEVICEADDR_USBADRA_Pos) /*!< USB1 DEVICEADDR: USBADRA Mask */\r
-#define USB1_DEVICEADDR_USBADR_Pos 25 /*!< USB1 DEVICEADDR: USBADR Position */\r
-#define USB1_DEVICEADDR_USBADR_Msk (0x7fUL << USB1_DEVICEADDR_USBADR_Pos) /*!< USB1 DEVICEADDR: USBADR Mask */\r
-\r
-// ---------------------------------- USB1_PERIODICLISTBASE -------------------------------------\r
-#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */\r
-#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */\r
-\r
-// ---------------------------------- USB1_ENDPOINTLISTADDR -------------------------------------\r
-#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */\r
-#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */\r
-\r
-// ----------------------------------- USB1_ASYNCLISTADDR ---------------------------------------\r
-#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */\r
-#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */\r
-\r
-// --------------------------------------- USB1_TTCTRL ------------------------------------------\r
-#define USB1_TTCTRL_TTHA_Pos 24 /*!< USB1 TTCTRL: TTHA Position */\r
-#define USB1_TTCTRL_TTHA_Msk (0x7fUL << USB1_TTCTRL_TTHA_Pos) /*!< USB1 TTCTRL: TTHA Mask */\r
-\r
-// ------------------------------------- USB1_BURSTSIZE -----------------------------------------\r
-#define USB1_BURSTSIZE_RXPBURST_Pos 0 /*!< USB1 BURSTSIZE: RXPBURST Position */\r
-#define USB1_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos) /*!< USB1 BURSTSIZE: RXPBURST Mask */\r
-#define USB1_BURSTSIZE_TXPBURST_Pos 8 /*!< USB1 BURSTSIZE: TXPBURST Position */\r
-#define USB1_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos) /*!< USB1 BURSTSIZE: TXPBURST Mask */\r
-\r
-// ------------------------------------ USB1_TXFILLTUNING ---------------------------------------\r
-#define USB1_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB1 TXFILLTUNING: TXSCHOH Position */\r
-#define USB1_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos) /*!< USB1 TXFILLTUNING: TXSCHOH Mask */\r
-#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */\r
-#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */\r
-#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */\r
-#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */\r
-\r
-// ------------------------------------ USB1_ULPIVIEWPORT ---------------------------------------\r
-#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos 0 /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */\r
-#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask */\r
-#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos 8 /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */\r
-#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask */\r
-#define USB1_ULPIVIEWPORT_ULPIADDR_Pos 16 /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */\r
-#define USB1_ULPIVIEWPORT_ULPIADDR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask */\r
-#define USB1_ULPIVIEWPORT_ULPIPORT_Pos 24 /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */\r
-#define USB1_ULPIVIEWPORT_ULPIPORT_Msk (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos) /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask */\r
-#define USB1_ULPIVIEWPORT_ULPISS_Pos 27 /*!< USB1 ULPIVIEWPORT: ULPISS Position */\r
-#define USB1_ULPIVIEWPORT_ULPISS_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos) /*!< USB1 ULPIVIEWPORT: ULPISS Mask */\r
-#define USB1_ULPIVIEWPORT_ULPIRW_Pos 29 /*!< USB1 ULPIVIEWPORT: ULPIRW Position */\r
-#define USB1_ULPIVIEWPORT_ULPIRW_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRW Mask */\r
-#define USB1_ULPIVIEWPORT_ULPIRUN_Pos 30 /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */\r
-#define USB1_ULPIVIEWPORT_ULPIRUN_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask */\r
-#define USB1_ULPIVIEWPORT_ULPIWU_Pos 31 /*!< USB1 ULPIVIEWPORT: ULPIWU Position */\r
-#define USB1_ULPIVIEWPORT_ULPIWU_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos) /*!< USB1 ULPIVIEWPORT: ULPIWU Mask */\r
-\r
-// ------------------------------------- USB1_BINTERVAL -----------------------------------------\r
-#define USB1_BINTERVAL_BINT_Pos 0 /*!< USB1 BINTERVAL: BINT Position */\r
-#define USB1_BINTERVAL_BINT_Msk (0x0fUL << USB1_BINTERVAL_BINT_Pos) /*!< USB1 BINTERVAL: BINT Mask */\r
-\r
-// -------------------------------------- USB1_ENDPTNAK -----------------------------------------\r
-#define USB1_ENDPTNAK_EPRN0_Pos 0 /*!< USB1 ENDPTNAK: EPRN0 Position */\r
-#define USB1_ENDPTNAK_EPRN0_Msk (0x01UL << USB1_ENDPTNAK_EPRN0_Pos) /*!< USB1 ENDPTNAK: EPRN0 Mask */\r
-#define USB1_ENDPTNAK_EPRN1_Pos 1 /*!< USB1 ENDPTNAK: EPRN1 Position */\r
-#define USB1_ENDPTNAK_EPRN1_Msk (0x01UL << USB1_ENDPTNAK_EPRN1_Pos) /*!< USB1 ENDPTNAK: EPRN1 Mask */\r
-#define USB1_ENDPTNAK_EPRN2_Pos 2 /*!< USB1 ENDPTNAK: EPRN2 Position */\r
-#define USB1_ENDPTNAK_EPRN2_Msk (0x01UL << USB1_ENDPTNAK_EPRN2_Pos) /*!< USB1 ENDPTNAK: EPRN2 Mask */\r
-#define USB1_ENDPTNAK_EPRN3_Pos 3 /*!< USB1 ENDPTNAK: EPRN3 Position */\r
-#define USB1_ENDPTNAK_EPRN3_Msk (0x01UL << USB1_ENDPTNAK_EPRN3_Pos) /*!< USB1 ENDPTNAK: EPRN3 Mask */\r
-#define USB1_ENDPTNAK_EPTN16_Pos 16 /*!< USB1 ENDPTNAK: EPTN16 Position */\r
-#define USB1_ENDPTNAK_EPTN16_Msk (0x01UL << USB1_ENDPTNAK_EPTN16_Pos) /*!< USB1 ENDPTNAK: EPTN16 Mask */\r
-#define USB1_ENDPTNAK_EPTN17_Pos 17 /*!< USB1 ENDPTNAK: EPTN17 Position */\r
-#define USB1_ENDPTNAK_EPTN17_Msk (0x01UL << USB1_ENDPTNAK_EPTN17_Pos) /*!< USB1 ENDPTNAK: EPTN17 Mask */\r
-#define USB1_ENDPTNAK_EPTN18_Pos 18 /*!< USB1 ENDPTNAK: EPTN18 Position */\r
-#define USB1_ENDPTNAK_EPTN18_Msk (0x01UL << USB1_ENDPTNAK_EPTN18_Pos) /*!< USB1 ENDPTNAK: EPTN18 Mask */\r
-#define USB1_ENDPTNAK_EPTN19_Pos 19 /*!< USB1 ENDPTNAK: EPTN19 Position */\r
-#define USB1_ENDPTNAK_EPTN19_Msk (0x01UL << USB1_ENDPTNAK_EPTN19_Pos) /*!< USB1 ENDPTNAK: EPTN19 Mask */\r
-\r
-// ------------------------------------- USB1_ENDPTNAKEN ----------------------------------------\r
-#define USB1_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB1 ENDPTNAKEN: EPRNE0 Position */\r
-#define USB1_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos) /*!< USB1 ENDPTNAKEN: EPRNE0 Mask */\r
-#define USB1_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB1 ENDPTNAKEN: EPRNE1 Position */\r
-#define USB1_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos) /*!< USB1 ENDPTNAKEN: EPRNE1 Mask */\r
-#define USB1_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB1 ENDPTNAKEN: EPRNE2 Position */\r
-#define USB1_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos) /*!< USB1 ENDPTNAKEN: EPRNE2 Mask */\r
-#define USB1_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB1 ENDPTNAKEN: EPRNE3 Position */\r
-#define USB1_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos) /*!< USB1 ENDPTNAKEN: EPRNE3 Mask */\r
-#define USB1_ENDPTNAKEN_EPTNE16_Pos 16 /*!< USB1 ENDPTNAKEN: EPTNE16 Position */\r
-#define USB1_ENDPTNAKEN_EPTNE16_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos) /*!< USB1 ENDPTNAKEN: EPTNE16 Mask */\r
-#define USB1_ENDPTNAKEN_EPTNE17_Pos 17 /*!< USB1 ENDPTNAKEN: EPTNE17 Position */\r
-#define USB1_ENDPTNAKEN_EPTNE17_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos) /*!< USB1 ENDPTNAKEN: EPTNE17 Mask */\r
-#define USB1_ENDPTNAKEN_EPTNE18_Pos 18 /*!< USB1 ENDPTNAKEN: EPTNE18 Position */\r
-#define USB1_ENDPTNAKEN_EPTNE18_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos) /*!< USB1 ENDPTNAKEN: EPTNE18 Mask */\r
-#define USB1_ENDPTNAKEN_EPTNE19_Pos 19 /*!< USB1 ENDPTNAKEN: EPTNE19 Position */\r
-#define USB1_ENDPTNAKEN_EPTNE19_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos) /*!< USB1 ENDPTNAKEN: EPTNE19 Mask */\r
-\r
-// ------------------------------------- USB1_PORTSC1_D -----------------------------------------\r
-#define USB1_PORTSC1_D_CCS_Pos 0 /*!< USB1 PORTSC1_D: CCS Position */\r
-#define USB1_PORTSC1_D_CCS_Msk (0x01UL << USB1_PORTSC1_D_CCS_Pos) /*!< USB1 PORTSC1_D: CCS Mask */\r
-#define USB1_PORTSC1_D_CSC_Pos 1 /*!< USB1 PORTSC1_D: CSC Position */\r
-#define USB1_PORTSC1_D_CSC_Msk (0x01UL << USB1_PORTSC1_D_CSC_Pos) /*!< USB1 PORTSC1_D: CSC Mask */\r
-#define USB1_PORTSC1_D_PE_Pos 2 /*!< USB1 PORTSC1_D: PE Position */\r
-#define USB1_PORTSC1_D_PE_Msk (0x01UL << USB1_PORTSC1_D_PE_Pos) /*!< USB1 PORTSC1_D: PE Mask */\r
-#define USB1_PORTSC1_D_PEC_Pos 3 /*!< USB1 PORTSC1_D: PEC Position */\r
-#define USB1_PORTSC1_D_PEC_Msk (0x01UL << USB1_PORTSC1_D_PEC_Pos) /*!< USB1 PORTSC1_D: PEC Mask */\r
-#define USB1_PORTSC1_D_FPR_Pos 6 /*!< USB1 PORTSC1_D: FPR Position */\r
-#define USB1_PORTSC1_D_FPR_Msk (0x01UL << USB1_PORTSC1_D_FPR_Pos) /*!< USB1 PORTSC1_D: FPR Mask */\r
-#define USB1_PORTSC1_D_SUSP_Pos 7 /*!< USB1 PORTSC1_D: SUSP Position */\r
-#define USB1_PORTSC1_D_SUSP_Msk (0x01UL << USB1_PORTSC1_D_SUSP_Pos) /*!< USB1 PORTSC1_D: SUSP Mask */\r
-#define USB1_PORTSC1_D_PR_Pos 8 /*!< USB1 PORTSC1_D: PR Position */\r
-#define USB1_PORTSC1_D_PR_Msk (0x01UL << USB1_PORTSC1_D_PR_Pos) /*!< USB1 PORTSC1_D: PR Mask */\r
-#define USB1_PORTSC1_D_HSP_Pos 9 /*!< USB1 PORTSC1_D: HSP Position */\r
-#define USB1_PORTSC1_D_HSP_Msk (0x01UL << USB1_PORTSC1_D_HSP_Pos) /*!< USB1 PORTSC1_D: HSP Mask */\r
-#define USB1_PORTSC1_D_LS_Pos 10 /*!< USB1 PORTSC1_D: LS Position */\r
-#define USB1_PORTSC1_D_LS_Msk (0x03UL << USB1_PORTSC1_D_LS_Pos) /*!< USB1 PORTSC1_D: LS Mask */\r
-#define USB1_PORTSC1_D_PP_Pos 12 /*!< USB1 PORTSC1_D: PP Position */\r
-#define USB1_PORTSC1_D_PP_Msk (0x01UL << USB1_PORTSC1_D_PP_Pos) /*!< USB1 PORTSC1_D: PP Mask */\r
-#define USB1_PORTSC1_D_PIC1_0_Pos 14 /*!< USB1 PORTSC1_D: PIC1_0 Position */\r
-#define USB1_PORTSC1_D_PIC1_0_Msk (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos) /*!< USB1 PORTSC1_D: PIC1_0 Mask */\r
-#define USB1_PORTSC1_D_PTC3_0_Pos 16 /*!< USB1 PORTSC1_D: PTC3_0 Position */\r
-#define USB1_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos) /*!< USB1 PORTSC1_D: PTC3_0 Mask */\r
-#define USB1_PORTSC1_D_PHCD_Pos 23 /*!< USB1 PORTSC1_D: PHCD Position */\r
-#define USB1_PORTSC1_D_PHCD_Msk (0x01UL << USB1_PORTSC1_D_PHCD_Pos) /*!< USB1 PORTSC1_D: PHCD Mask */\r
-#define USB1_PORTSC1_D_PFSC_Pos 24 /*!< USB1 PORTSC1_D: PFSC Position */\r
-#define USB1_PORTSC1_D_PFSC_Msk (0x01UL << USB1_PORTSC1_D_PFSC_Pos) /*!< USB1 PORTSC1_D: PFSC Mask */\r
-#define USB1_PORTSC1_D_PSPD_Pos 26 /*!< USB1 PORTSC1_D: PSPD Position */\r
-#define USB1_PORTSC1_D_PSPD_Msk (0x03UL << USB1_PORTSC1_D_PSPD_Pos) /*!< USB1 PORTSC1_D: PSPD Mask */\r
-#define USB1_PORTSC1_D_PTS_Pos 30 /*!< USB1 PORTSC1_D: PTS Position */\r
-#define USB1_PORTSC1_D_PTS_Msk (0x03UL << USB1_PORTSC1_D_PTS_Pos) /*!< USB1 PORTSC1_D: PTS Mask */\r
-\r
-// ------------------------------------- USB1_PORTSC1_H -----------------------------------------\r
-#define USB1_PORTSC1_H_CCS_Pos 0 /*!< USB1 PORTSC1_H: CCS Position */\r
-#define USB1_PORTSC1_H_CCS_Msk (0x01UL << USB1_PORTSC1_H_CCS_Pos) /*!< USB1 PORTSC1_H: CCS Mask */\r
-#define USB1_PORTSC1_H_CSC_Pos 1 /*!< USB1 PORTSC1_H: CSC Position */\r
-#define USB1_PORTSC1_H_CSC_Msk (0x01UL << USB1_PORTSC1_H_CSC_Pos) /*!< USB1 PORTSC1_H: CSC Mask */\r
-#define USB1_PORTSC1_H_PE_Pos 2 /*!< USB1 PORTSC1_H: PE Position */\r
-#define USB1_PORTSC1_H_PE_Msk (0x01UL << USB1_PORTSC1_H_PE_Pos) /*!< USB1 PORTSC1_H: PE Mask */\r
-#define USB1_PORTSC1_H_PEC_Pos 3 /*!< USB1 PORTSC1_H: PEC Position */\r
-#define USB1_PORTSC1_H_PEC_Msk (0x01UL << USB1_PORTSC1_H_PEC_Pos) /*!< USB1 PORTSC1_H: PEC Mask */\r
-#define USB1_PORTSC1_H_OCA_Pos 4 /*!< USB1 PORTSC1_H: OCA Position */\r
-#define USB1_PORTSC1_H_OCA_Msk (0x01UL << USB1_PORTSC1_H_OCA_Pos) /*!< USB1 PORTSC1_H: OCA Mask */\r
-#define USB1_PORTSC1_H_OCC_Pos 5 /*!< USB1 PORTSC1_H: OCC Position */\r
-#define USB1_PORTSC1_H_OCC_Msk (0x01UL << USB1_PORTSC1_H_OCC_Pos) /*!< USB1 PORTSC1_H: OCC Mask */\r
-#define USB1_PORTSC1_H_FPR_Pos 6 /*!< USB1 PORTSC1_H: FPR Position */\r
-#define USB1_PORTSC1_H_FPR_Msk (0x01UL << USB1_PORTSC1_H_FPR_Pos) /*!< USB1 PORTSC1_H: FPR Mask */\r
-#define USB1_PORTSC1_H_SUSP_Pos 7 /*!< USB1 PORTSC1_H: SUSP Position */\r
-#define USB1_PORTSC1_H_SUSP_Msk (0x01UL << USB1_PORTSC1_H_SUSP_Pos) /*!< USB1 PORTSC1_H: SUSP Mask */\r
-#define USB1_PORTSC1_H_PR_Pos 8 /*!< USB1 PORTSC1_H: PR Position */\r
-#define USB1_PORTSC1_H_PR_Msk (0x01UL << USB1_PORTSC1_H_PR_Pos) /*!< USB1 PORTSC1_H: PR Mask */\r
-#define USB1_PORTSC1_H_HSP_Pos 9 /*!< USB1 PORTSC1_H: HSP Position */\r
-#define USB1_PORTSC1_H_HSP_Msk (0x01UL << USB1_PORTSC1_H_HSP_Pos) /*!< USB1 PORTSC1_H: HSP Mask */\r
-#define USB1_PORTSC1_H_LS_Pos 10 /*!< USB1 PORTSC1_H: LS Position */\r
-#define USB1_PORTSC1_H_LS_Msk (0x03UL << USB1_PORTSC1_H_LS_Pos) /*!< USB1 PORTSC1_H: LS Mask */\r
-#define USB1_PORTSC1_H_PP_Pos 12 /*!< USB1 PORTSC1_H: PP Position */\r
-#define USB1_PORTSC1_H_PP_Msk (0x01UL << USB1_PORTSC1_H_PP_Pos) /*!< USB1 PORTSC1_H: PP Mask */\r
-#define USB1_PORTSC1_H_PIC1_0_Pos 14 /*!< USB1 PORTSC1_H: PIC1_0 Position */\r
-#define USB1_PORTSC1_H_PIC1_0_Msk (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos) /*!< USB1 PORTSC1_H: PIC1_0 Mask */\r
-#define USB1_PORTSC1_H_PTC3_0_Pos 16 /*!< USB1 PORTSC1_H: PTC3_0 Position */\r
-#define USB1_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos) /*!< USB1 PORTSC1_H: PTC3_0 Mask */\r
-#define USB1_PORTSC1_H_WKCN_Pos 20 /*!< USB1 PORTSC1_H: WKCN Position */\r
-#define USB1_PORTSC1_H_WKCN_Msk (0x01UL << USB1_PORTSC1_H_WKCN_Pos) /*!< USB1 PORTSC1_H: WKCN Mask */\r
-#define USB1_PORTSC1_H_WKDC_Pos 21 /*!< USB1 PORTSC1_H: WKDC Position */\r
-#define USB1_PORTSC1_H_WKDC_Msk (0x01UL << USB1_PORTSC1_H_WKDC_Pos) /*!< USB1 PORTSC1_H: WKDC Mask */\r
-#define USB1_PORTSC1_H_WKOC_Pos 22 /*!< USB1 PORTSC1_H: WKOC Position */\r
-#define USB1_PORTSC1_H_WKOC_Msk (0x01UL << USB1_PORTSC1_H_WKOC_Pos) /*!< USB1 PORTSC1_H: WKOC Mask */\r
-#define USB1_PORTSC1_H_PHCD_Pos 23 /*!< USB1 PORTSC1_H: PHCD Position */\r
-#define USB1_PORTSC1_H_PHCD_Msk (0x01UL << USB1_PORTSC1_H_PHCD_Pos) /*!< USB1 PORTSC1_H: PHCD Mask */\r
-#define USB1_PORTSC1_H_PFSC_Pos 24 /*!< USB1 PORTSC1_H: PFSC Position */\r
-#define USB1_PORTSC1_H_PFSC_Msk (0x01UL << USB1_PORTSC1_H_PFSC_Pos) /*!< USB1 PORTSC1_H: PFSC Mask */\r
-#define USB1_PORTSC1_H_PSPD_Pos 26 /*!< USB1 PORTSC1_H: PSPD Position */\r
-#define USB1_PORTSC1_H_PSPD_Msk (0x03UL << USB1_PORTSC1_H_PSPD_Pos) /*!< USB1 PORTSC1_H: PSPD Mask */\r
-#define USB1_PORTSC1_H_PTS_Pos 30 /*!< USB1 PORTSC1_H: PTS Position */\r
-#define USB1_PORTSC1_H_PTS_Msk (0x03UL << USB1_PORTSC1_H_PTS_Pos) /*!< USB1 PORTSC1_H: PTS Mask */\r
-\r
-// ------------------------------------- USB1_USBMODE_D -----------------------------------------\r
-#define USB1_USBMODE_D_CM1_0_Pos 0 /*!< USB1 USBMODE_D: CM1_0 Position */\r
-#define USB1_USBMODE_D_CM1_0_Msk (0x03UL << USB1_USBMODE_D_CM1_0_Pos) /*!< USB1 USBMODE_D: CM1_0 Mask */\r
-#define USB1_USBMODE_D_ES_Pos 2 /*!< USB1 USBMODE_D: ES Position */\r
-#define USB1_USBMODE_D_ES_Msk (0x01UL << USB1_USBMODE_D_ES_Pos) /*!< USB1 USBMODE_D: ES Mask */\r
-#define USB1_USBMODE_D_SLOM_Pos 3 /*!< USB1 USBMODE_D: SLOM Position */\r
-#define USB1_USBMODE_D_SLOM_Msk (0x01UL << USB1_USBMODE_D_SLOM_Pos) /*!< USB1 USBMODE_D: SLOM Mask */\r
-#define USB1_USBMODE_D_SDIS_Pos 4 /*!< USB1 USBMODE_D: SDIS Position */\r
-#define USB1_USBMODE_D_SDIS_Msk (0x01UL << USB1_USBMODE_D_SDIS_Pos) /*!< USB1 USBMODE_D: SDIS Mask */\r
-\r
-// ------------------------------------- USB1_USBMODE_H -----------------------------------------\r
-#define USB1_USBMODE_H_CM1_0_Pos 0 /*!< USB1 USBMODE_H: CM1_0 Position */\r
-#define USB1_USBMODE_H_CM1_0_Msk (0x03UL << USB1_USBMODE_H_CM1_0_Pos) /*!< USB1 USBMODE_H: CM1_0 Mask */\r
-#define USB1_USBMODE_H_ES_Pos 2 /*!< USB1 USBMODE_H: ES Position */\r
-#define USB1_USBMODE_H_ES_Msk (0x01UL << USB1_USBMODE_H_ES_Pos) /*!< USB1 USBMODE_H: ES Mask */\r
-#define USB1_USBMODE_H_SDIS_Pos 4 /*!< USB1 USBMODE_H: SDIS Position */\r
-#define USB1_USBMODE_H_SDIS_Msk (0x01UL << USB1_USBMODE_H_SDIS_Pos) /*!< USB1 USBMODE_H: SDIS Mask */\r
-#define USB1_USBMODE_H_VBPS_Pos 5 /*!< USB1 USBMODE_H: VBPS Position */\r
-#define USB1_USBMODE_H_VBPS_Msk (0x01UL << USB1_USBMODE_H_VBPS_Pos) /*!< USB1 USBMODE_H: VBPS Mask */\r
-\r
-// ----------------------------------- USB1_ENDPTSETUPSTAT --------------------------------------\r
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */\r
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */\r
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */\r
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */\r
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */\r
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */\r
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */\r
-#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */\r
-\r
-// ------------------------------------- USB1_ENDPTPRIME ----------------------------------------\r
-#define USB1_ENDPTPRIME_PERB0_Pos 0 /*!< USB1 ENDPTPRIME: PERB0 Position */\r
-#define USB1_ENDPTPRIME_PERB0_Msk (0x01UL << USB1_ENDPTPRIME_PERB0_Pos) /*!< USB1 ENDPTPRIME: PERB0 Mask */\r
-#define USB1_ENDPTPRIME_PERB1_Pos 1 /*!< USB1 ENDPTPRIME: PERB1 Position */\r
-#define USB1_ENDPTPRIME_PERB1_Msk (0x01UL << USB1_ENDPTPRIME_PERB1_Pos) /*!< USB1 ENDPTPRIME: PERB1 Mask */\r
-#define USB1_ENDPTPRIME_PERB2_Pos 2 /*!< USB1 ENDPTPRIME: PERB2 Position */\r
-#define USB1_ENDPTPRIME_PERB2_Msk (0x01UL << USB1_ENDPTPRIME_PERB2_Pos) /*!< USB1 ENDPTPRIME: PERB2 Mask */\r
-#define USB1_ENDPTPRIME_PERB3_Pos 3 /*!< USB1 ENDPTPRIME: PERB3 Position */\r
-#define USB1_ENDPTPRIME_PERB3_Msk (0x01UL << USB1_ENDPTPRIME_PERB3_Pos) /*!< USB1 ENDPTPRIME: PERB3 Mask */\r
-#define USB1_ENDPTPRIME_PETB0_Pos 16 /*!< USB1 ENDPTPRIME: PETB0 Position */\r
-#define USB1_ENDPTPRIME_PETB0_Msk (0x01UL << USB1_ENDPTPRIME_PETB0_Pos) /*!< USB1 ENDPTPRIME: PETB0 Mask */\r
-#define USB1_ENDPTPRIME_PETB1_Pos 17 /*!< USB1 ENDPTPRIME: PETB1 Position */\r
-#define USB1_ENDPTPRIME_PETB1_Msk (0x01UL << USB1_ENDPTPRIME_PETB1_Pos) /*!< USB1 ENDPTPRIME: PETB1 Mask */\r
-#define USB1_ENDPTPRIME_PETB2_Pos 18 /*!< USB1 ENDPTPRIME: PETB2 Position */\r
-#define USB1_ENDPTPRIME_PETB2_Msk (0x01UL << USB1_ENDPTPRIME_PETB2_Pos) /*!< USB1 ENDPTPRIME: PETB2 Mask */\r
-#define USB1_ENDPTPRIME_PETB3_Pos 19 /*!< USB1 ENDPTPRIME: PETB3 Position */\r
-#define USB1_ENDPTPRIME_PETB3_Msk (0x01UL << USB1_ENDPTPRIME_PETB3_Pos) /*!< USB1 ENDPTPRIME: PETB3 Mask */\r
-\r
-// ------------------------------------- USB1_ENDPTFLUSH ----------------------------------------\r
-#define USB1_ENDPTFLUSH_FERB0_Pos 0 /*!< USB1 ENDPTFLUSH: FERB0 Position */\r
-#define USB1_ENDPTFLUSH_FERB0_Msk (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos) /*!< USB1 ENDPTFLUSH: FERB0 Mask */\r
-#define USB1_ENDPTFLUSH_FERB1_Pos 1 /*!< USB1 ENDPTFLUSH: FERB1 Position */\r
-#define USB1_ENDPTFLUSH_FERB1_Msk (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos) /*!< USB1 ENDPTFLUSH: FERB1 Mask */\r
-#define USB1_ENDPTFLUSH_FERB2_Pos 2 /*!< USB1 ENDPTFLUSH: FERB2 Position */\r
-#define USB1_ENDPTFLUSH_FERB2_Msk (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos) /*!< USB1 ENDPTFLUSH: FERB2 Mask */\r
-#define USB1_ENDPTFLUSH_FERB3_Pos 3 /*!< USB1 ENDPTFLUSH: FERB3 Position */\r
-#define USB1_ENDPTFLUSH_FERB3_Msk (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos) /*!< USB1 ENDPTFLUSH: FERB3 Mask */\r
-#define USB1_ENDPTFLUSH_FETB0_Pos 16 /*!< USB1 ENDPTFLUSH: FETB0 Position */\r
-#define USB1_ENDPTFLUSH_FETB0_Msk (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos) /*!< USB1 ENDPTFLUSH: FETB0 Mask */\r
-#define USB1_ENDPTFLUSH_FETB1_Pos 17 /*!< USB1 ENDPTFLUSH: FETB1 Position */\r
-#define USB1_ENDPTFLUSH_FETB1_Msk (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos) /*!< USB1 ENDPTFLUSH: FETB1 Mask */\r
-#define USB1_ENDPTFLUSH_FETB2_Pos 18 /*!< USB1 ENDPTFLUSH: FETB2 Position */\r
-#define USB1_ENDPTFLUSH_FETB2_Msk (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos) /*!< USB1 ENDPTFLUSH: FETB2 Mask */\r
-#define USB1_ENDPTFLUSH_FETB3_Pos 19 /*!< USB1 ENDPTFLUSH: FETB3 Position */\r
-#define USB1_ENDPTFLUSH_FETB3_Msk (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos) /*!< USB1 ENDPTFLUSH: FETB3 Mask */\r
-\r
-// ------------------------------------- USB1_ENDPTSTAT -----------------------------------------\r
-#define USB1_ENDPTSTAT_ERBR0_Pos 0 /*!< USB1 ENDPTSTAT: ERBR0 Position */\r
-#define USB1_ENDPTSTAT_ERBR0_Msk (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos) /*!< USB1 ENDPTSTAT: ERBR0 Mask */\r
-#define USB1_ENDPTSTAT_ERBR1_Pos 1 /*!< USB1 ENDPTSTAT: ERBR1 Position */\r
-#define USB1_ENDPTSTAT_ERBR1_Msk (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos) /*!< USB1 ENDPTSTAT: ERBR1 Mask */\r
-#define USB1_ENDPTSTAT_ERBR2_Pos 2 /*!< USB1 ENDPTSTAT: ERBR2 Position */\r
-#define USB1_ENDPTSTAT_ERBR2_Msk (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos) /*!< USB1 ENDPTSTAT: ERBR2 Mask */\r
-#define USB1_ENDPTSTAT_ERBR3_Pos 3 /*!< USB1 ENDPTSTAT: ERBR3 Position */\r
-#define USB1_ENDPTSTAT_ERBR3_Msk (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos) /*!< USB1 ENDPTSTAT: ERBR3 Mask */\r
-#define USB1_ENDPTSTAT_ETBR0_Pos 16 /*!< USB1 ENDPTSTAT: ETBR0 Position */\r
-#define USB1_ENDPTSTAT_ETBR0_Msk (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos) /*!< USB1 ENDPTSTAT: ETBR0 Mask */\r
-#define USB1_ENDPTSTAT_ETBR1_Pos 17 /*!< USB1 ENDPTSTAT: ETBR1 Position */\r
-#define USB1_ENDPTSTAT_ETBR1_Msk (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos) /*!< USB1 ENDPTSTAT: ETBR1 Mask */\r
-#define USB1_ENDPTSTAT_ETBR2_Pos 18 /*!< USB1 ENDPTSTAT: ETBR2 Position */\r
-#define USB1_ENDPTSTAT_ETBR2_Msk (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos) /*!< USB1 ENDPTSTAT: ETBR2 Mask */\r
-#define USB1_ENDPTSTAT_ETBR3_Pos 19 /*!< USB1 ENDPTSTAT: ETBR3 Position */\r
-#define USB1_ENDPTSTAT_ETBR3_Msk (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos) /*!< USB1 ENDPTSTAT: ETBR3 Mask */\r
-\r
-// ----------------------------------- USB1_ENDPTCOMPLETE ---------------------------------------\r
-#define USB1_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB1 ENDPTCOMPLETE: ERCE0 Position */\r
-#define USB1_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask */\r
-#define USB1_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB1 ENDPTCOMPLETE: ERCE1 Position */\r
-#define USB1_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask */\r
-#define USB1_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB1 ENDPTCOMPLETE: ERCE2 Position */\r
-#define USB1_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask */\r
-#define USB1_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB1 ENDPTCOMPLETE: ERCE3 Position */\r
-#define USB1_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask */\r
-#define USB1_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB1 ENDPTCOMPLETE: ETCE0 Position */\r
-#define USB1_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask */\r
-#define USB1_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB1 ENDPTCOMPLETE: ETCE1 Position */\r
-#define USB1_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask */\r
-#define USB1_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB1 ENDPTCOMPLETE: ETCE2 Position */\r
-#define USB1_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask */\r
-#define USB1_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB1 ENDPTCOMPLETE: ETCE3 Position */\r
-#define USB1_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask */\r
-\r
-// ------------------------------------- USB1_ENDPTCTRL0 ----------------------------------------\r
-#define USB1_ENDPTCTRL0_RXS_Pos 0 /*!< USB1 ENDPTCTRL0: RXS Position */\r
-#define USB1_ENDPTCTRL0_RXS_Msk (0x01UL << USB1_ENDPTCTRL0_RXS_Pos) /*!< USB1 ENDPTCTRL0: RXS Mask */\r
-#define USB1_ENDPTCTRL0_RXT_Pos 2 /*!< USB1 ENDPTCTRL0: RXT Position */\r
-#define USB1_ENDPTCTRL0_RXT_Msk (0x03UL << USB1_ENDPTCTRL0_RXT_Pos) /*!< USB1 ENDPTCTRL0: RXT Mask */\r
-#define USB1_ENDPTCTRL0_RXE_Pos 7 /*!< USB1 ENDPTCTRL0: RXE Position */\r
-#define USB1_ENDPTCTRL0_RXE_Msk (0x01UL << USB1_ENDPTCTRL0_RXE_Pos) /*!< USB1 ENDPTCTRL0: RXE Mask */\r
-#define USB1_ENDPTCTRL0_TXS_Pos 16 /*!< USB1 ENDPTCTRL0: TXS Position */\r
-#define USB1_ENDPTCTRL0_TXS_Msk (0x01UL << USB1_ENDPTCTRL0_TXS_Pos) /*!< USB1 ENDPTCTRL0: TXS Mask */\r
-#define USB1_ENDPTCTRL0_TXT_Pos 18 /*!< USB1 ENDPTCTRL0: TXT Position */\r
-#define USB1_ENDPTCTRL0_TXT_Msk (0x03UL << USB1_ENDPTCTRL0_TXT_Pos) /*!< USB1 ENDPTCTRL0: TXT Mask */\r
-#define USB1_ENDPTCTRL0_TXE_Pos 23 /*!< USB1 ENDPTCTRL0: TXE Position */\r
-#define USB1_ENDPTCTRL0_TXE_Msk (0x01UL << USB1_ENDPTCTRL0_TXE_Pos) /*!< USB1 ENDPTCTRL0: TXE Mask */\r
-\r
-// ------------------------------------- USB1_ENDPTCTRL1 ----------------------------------------\r
-#define USB1_ENDPTCTRL1_RXS_Pos 0 /*!< USB1 ENDPTCTRL1: RXS Position */\r
-#define USB1_ENDPTCTRL1_RXS_Msk (0x01UL << USB1_ENDPTCTRL1_RXS_Pos) /*!< USB1 ENDPTCTRL1: RXS Mask */\r
-#define USB1_ENDPTCTRL1_RXT_Pos 2 /*!< USB1 ENDPTCTRL1: RXT Position */\r
-#define USB1_ENDPTCTRL1_RXT_Msk (0x03UL << USB1_ENDPTCTRL1_RXT_Pos) /*!< USB1 ENDPTCTRL1: RXT Mask */\r
-#define USB1_ENDPTCTRL1_RXI_Pos 5 /*!< USB1 ENDPTCTRL1: RXI Position */\r
-#define USB1_ENDPTCTRL1_RXI_Msk (0x01UL << USB1_ENDPTCTRL1_RXI_Pos) /*!< USB1 ENDPTCTRL1: RXI Mask */\r
-#define USB1_ENDPTCTRL1_RXR_Pos 6 /*!< USB1 ENDPTCTRL1: RXR Position */\r
-#define USB1_ENDPTCTRL1_RXR_Msk (0x01UL << USB1_ENDPTCTRL1_RXR_Pos) /*!< USB1 ENDPTCTRL1: RXR Mask */\r
-#define USB1_ENDPTCTRL1_RXE_Pos 7 /*!< USB1 ENDPTCTRL1: RXE Position */\r
-#define USB1_ENDPTCTRL1_RXE_Msk (0x01UL << USB1_ENDPTCTRL1_RXE_Pos) /*!< USB1 ENDPTCTRL1: RXE Mask */\r
-#define USB1_ENDPTCTRL1_TXS_Pos 16 /*!< USB1 ENDPTCTRL1: TXS Position */\r
-#define USB1_ENDPTCTRL1_TXS_Msk (0x01UL << USB1_ENDPTCTRL1_TXS_Pos) /*!< USB1 ENDPTCTRL1: TXS Mask */\r
-#define USB1_ENDPTCTRL1_TXT_Pos 18 /*!< USB1 ENDPTCTRL1: TXT Position */\r
-#define USB1_ENDPTCTRL1_TXT_Msk (0x03UL << USB1_ENDPTCTRL1_TXT_Pos) /*!< USB1 ENDPTCTRL1: TXT Mask */\r
-#define USB1_ENDPTCTRL1_TXI_Pos 21 /*!< USB1 ENDPTCTRL1: TXI Position */\r
-#define USB1_ENDPTCTRL1_TXI_Msk (0x01UL << USB1_ENDPTCTRL1_TXI_Pos) /*!< USB1 ENDPTCTRL1: TXI Mask */\r
-#define USB1_ENDPTCTRL1_TXR_Pos 22 /*!< USB1 ENDPTCTRL1: TXR Position */\r
-#define USB1_ENDPTCTRL1_TXR_Msk (0x01UL << USB1_ENDPTCTRL1_TXR_Pos) /*!< USB1 ENDPTCTRL1: TXR Mask */\r
-#define USB1_ENDPTCTRL1_TXE_Pos 23 /*!< USB1 ENDPTCTRL1: TXE Position */\r
-#define USB1_ENDPTCTRL1_TXE_Msk (0x01UL << USB1_ENDPTCTRL1_TXE_Pos) /*!< USB1 ENDPTCTRL1: TXE Mask */\r
-\r
-// ------------------------------------- USB1_ENDPTCTRL2 ----------------------------------------\r
-#define USB1_ENDPTCTRL2_RXS_Pos 0 /*!< USB1 ENDPTCTRL2: RXS Position */\r
-#define USB1_ENDPTCTRL2_RXS_Msk (0x01UL << USB1_ENDPTCTRL2_RXS_Pos) /*!< USB1 ENDPTCTRL2: RXS Mask */\r
-#define USB1_ENDPTCTRL2_RXT_Pos 2 /*!< USB1 ENDPTCTRL2: RXT Position */\r
-#define USB1_ENDPTCTRL2_RXT_Msk (0x03UL << USB1_ENDPTCTRL2_RXT_Pos) /*!< USB1 ENDPTCTRL2: RXT Mask */\r
-#define USB1_ENDPTCTRL2_RXI_Pos 5 /*!< USB1 ENDPTCTRL2: RXI Position */\r
-#define USB1_ENDPTCTRL2_RXI_Msk (0x01UL << USB1_ENDPTCTRL2_RXI_Pos) /*!< USB1 ENDPTCTRL2: RXI Mask */\r
-#define USB1_ENDPTCTRL2_RXR_Pos 6 /*!< USB1 ENDPTCTRL2: RXR Position */\r
-#define USB1_ENDPTCTRL2_RXR_Msk (0x01UL << USB1_ENDPTCTRL2_RXR_Pos) /*!< USB1 ENDPTCTRL2: RXR Mask */\r
-#define USB1_ENDPTCTRL2_RXE_Pos 7 /*!< USB1 ENDPTCTRL2: RXE Position */\r
-#define USB1_ENDPTCTRL2_RXE_Msk (0x01UL << USB1_ENDPTCTRL2_RXE_Pos) /*!< USB1 ENDPTCTRL2: RXE Mask */\r
-#define USB1_ENDPTCTRL2_TXS_Pos 16 /*!< USB1 ENDPTCTRL2: TXS Position */\r
-#define USB1_ENDPTCTRL2_TXS_Msk (0x01UL << USB1_ENDPTCTRL2_TXS_Pos) /*!< USB1 ENDPTCTRL2: TXS Mask */\r
-#define USB1_ENDPTCTRL2_TXT_Pos 18 /*!< USB1 ENDPTCTRL2: TXT Position */\r
-#define USB1_ENDPTCTRL2_TXT_Msk (0x03UL << USB1_ENDPTCTRL2_TXT_Pos) /*!< USB1 ENDPTCTRL2: TXT Mask */\r
-#define USB1_ENDPTCTRL2_TXI_Pos 21 /*!< USB1 ENDPTCTRL2: TXI Position */\r
-#define USB1_ENDPTCTRL2_TXI_Msk (0x01UL << USB1_ENDPTCTRL2_TXI_Pos) /*!< USB1 ENDPTCTRL2: TXI Mask */\r
-#define USB1_ENDPTCTRL2_TXR_Pos 22 /*!< USB1 ENDPTCTRL2: TXR Position */\r
-#define USB1_ENDPTCTRL2_TXR_Msk (0x01UL << USB1_ENDPTCTRL2_TXR_Pos) /*!< USB1 ENDPTCTRL2: TXR Mask */\r
-#define USB1_ENDPTCTRL2_TXE_Pos 23 /*!< USB1 ENDPTCTRL2: TXE Position */\r
-#define USB1_ENDPTCTRL2_TXE_Msk (0x01UL << USB1_ENDPTCTRL2_TXE_Pos) /*!< USB1 ENDPTCTRL2: TXE Mask */\r
-\r
-// ------------------------------------- USB1_ENDPTCTRL3 ----------------------------------------\r
-#define USB1_ENDPTCTRL3_RXS_Pos 0 /*!< USB1 ENDPTCTRL3: RXS Position */\r
-#define USB1_ENDPTCTRL3_RXS_Msk (0x01UL << USB1_ENDPTCTRL3_RXS_Pos) /*!< USB1 ENDPTCTRL3: RXS Mask */\r
-#define USB1_ENDPTCTRL3_RXT_Pos 2 /*!< USB1 ENDPTCTRL3: RXT Position */\r
-#define USB1_ENDPTCTRL3_RXT_Msk (0x03UL << USB1_ENDPTCTRL3_RXT_Pos) /*!< USB1 ENDPTCTRL3: RXT Mask */\r
-#define USB1_ENDPTCTRL3_RXI_Pos 5 /*!< USB1 ENDPTCTRL3: RXI Position */\r
-#define USB1_ENDPTCTRL3_RXI_Msk (0x01UL << USB1_ENDPTCTRL3_RXI_Pos) /*!< USB1 ENDPTCTRL3: RXI Mask */\r
-#define USB1_ENDPTCTRL3_RXR_Pos 6 /*!< USB1 ENDPTCTRL3: RXR Position */\r
-#define USB1_ENDPTCTRL3_RXR_Msk (0x01UL << USB1_ENDPTCTRL3_RXR_Pos) /*!< USB1 ENDPTCTRL3: RXR Mask */\r
-#define USB1_ENDPTCTRL3_RXE_Pos 7 /*!< USB1 ENDPTCTRL3: RXE Position */\r
-#define USB1_ENDPTCTRL3_RXE_Msk (0x01UL << USB1_ENDPTCTRL3_RXE_Pos) /*!< USB1 ENDPTCTRL3: RXE Mask */\r
-#define USB1_ENDPTCTRL3_TXS_Pos 16 /*!< USB1 ENDPTCTRL3: TXS Position */\r
-#define USB1_ENDPTCTRL3_TXS_Msk (0x01UL << USB1_ENDPTCTRL3_TXS_Pos) /*!< USB1 ENDPTCTRL3: TXS Mask */\r
-#define USB1_ENDPTCTRL3_TXT_Pos 18 /*!< USB1 ENDPTCTRL3: TXT Position */\r
-#define USB1_ENDPTCTRL3_TXT_Msk (0x03UL << USB1_ENDPTCTRL3_TXT_Pos) /*!< USB1 ENDPTCTRL3: TXT Mask */\r
-#define USB1_ENDPTCTRL3_TXI_Pos 21 /*!< USB1 ENDPTCTRL3: TXI Position */\r
-#define USB1_ENDPTCTRL3_TXI_Msk (0x01UL << USB1_ENDPTCTRL3_TXI_Pos) /*!< USB1 ENDPTCTRL3: TXI Mask */\r
-#define USB1_ENDPTCTRL3_TXR_Pos 22 /*!< USB1 ENDPTCTRL3: TXR Position */\r
-#define USB1_ENDPTCTRL3_TXR_Msk (0x01UL << USB1_ENDPTCTRL3_TXR_Pos) /*!< USB1 ENDPTCTRL3: TXR Mask */\r
-#define USB1_ENDPTCTRL3_TXE_Pos 23 /*!< USB1 ENDPTCTRL3: TXE Position */\r
-#define USB1_ENDPTCTRL3_TXE_Msk (0x01UL << USB1_ENDPTCTRL3_TXE_Pos) /*!< USB1 ENDPTCTRL3: TXE Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- LCD Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- LCD_TIMH --------------------------------------------\r
-#define LCD_TIMH_PPL_Pos 2 /*!< LCD TIMH: PPL Position */\r
-#define LCD_TIMH_PPL_Msk (0x3fUL << LCD_TIMH_PPL_Pos) /*!< LCD TIMH: PPL Mask */\r
-#define LCD_TIMH_HSW_Pos 8 /*!< LCD TIMH: HSW Position */\r
-#define LCD_TIMH_HSW_Msk (0x000000ffUL << LCD_TIMH_HSW_Pos) /*!< LCD TIMH: HSW Mask */\r
-#define LCD_TIMH_HFP_Pos 16 /*!< LCD TIMH: HFP Position */\r
-#define LCD_TIMH_HFP_Msk (0x000000ffUL << LCD_TIMH_HFP_Pos) /*!< LCD TIMH: HFP Mask */\r
-#define LCD_TIMH_HBP_Pos 24 /*!< LCD TIMH: HBP Position */\r
-#define LCD_TIMH_HBP_Msk (0x000000ffUL << LCD_TIMH_HBP_Pos) /*!< LCD TIMH: HBP Mask */\r
-\r
-// ---------------------------------------- LCD_TIMV --------------------------------------------\r
-#define LCD_TIMV_LPP_Pos 0 /*!< LCD TIMV: LPP Position */\r
-#define LCD_TIMV_LPP_Msk (0x000003ffUL << LCD_TIMV_LPP_Pos) /*!< LCD TIMV: LPP Mask */\r
-#define LCD_TIMV_VSW_Pos 10 /*!< LCD TIMV: VSW Position */\r
-#define LCD_TIMV_VSW_Msk (0x3fUL << LCD_TIMV_VSW_Pos) /*!< LCD TIMV: VSW Mask */\r
-#define LCD_TIMV_VFP_Pos 16 /*!< LCD TIMV: VFP Position */\r
-#define LCD_TIMV_VFP_Msk (0x000000ffUL << LCD_TIMV_VFP_Pos) /*!< LCD TIMV: VFP Mask */\r
-#define LCD_TIMV_VBP_Pos 24 /*!< LCD TIMV: VBP Position */\r
-#define LCD_TIMV_VBP_Msk (0x000000ffUL << LCD_TIMV_VBP_Pos) /*!< LCD TIMV: VBP Mask */\r
-\r
-// ----------------------------------------- LCD_POL --------------------------------------------\r
-#define LCD_POL_PCD_LO_Pos 0 /*!< LCD POL: PCD_LO Position */\r
-#define LCD_POL_PCD_LO_Msk (0x1fUL << LCD_POL_PCD_LO_Pos) /*!< LCD POL: PCD_LO Mask */\r
-#define LCD_POL_CLKSEL_Pos 5 /*!< LCD POL: CLKSEL Position */\r
-#define LCD_POL_CLKSEL_Msk (0x01UL << LCD_POL_CLKSEL_Pos) /*!< LCD POL: CLKSEL Mask */\r
-#define LCD_POL_ACB_Pos 6 /*!< LCD POL: ACB Position */\r
-#define LCD_POL_ACB_Msk (0x1fUL << LCD_POL_ACB_Pos) /*!< LCD POL: ACB Mask */\r
-#define LCD_POL_IVS_Pos 11 /*!< LCD POL: IVS Position */\r
-#define LCD_POL_IVS_Msk (0x01UL << LCD_POL_IVS_Pos) /*!< LCD POL: IVS Mask */\r
-#define LCD_POL_IHS_Pos 12 /*!< LCD POL: IHS Position */\r
-#define LCD_POL_IHS_Msk (0x01UL << LCD_POL_IHS_Pos) /*!< LCD POL: IHS Mask */\r
-#define LCD_POL_IPC_Pos 13 /*!< LCD POL: IPC Position */\r
-#define LCD_POL_IPC_Msk (0x01UL << LCD_POL_IPC_Pos) /*!< LCD POL: IPC Mask */\r
-#define LCD_POL_IOE_Pos 14 /*!< LCD POL: IOE Position */\r
-#define LCD_POL_IOE_Msk (0x01UL << LCD_POL_IOE_Pos) /*!< LCD POL: IOE Mask */\r
-#define LCD_POL_CPL_Pos 16 /*!< LCD POL: CPL Position */\r
-#define LCD_POL_CPL_Msk (0x000003ffUL << LCD_POL_CPL_Pos) /*!< LCD POL: CPL Mask */\r
-#define LCD_POL_BCD_Pos 26 /*!< LCD POL: BCD Position */\r
-#define LCD_POL_BCD_Msk (0x01UL << LCD_POL_BCD_Pos) /*!< LCD POL: BCD Mask */\r
-#define LCD_POL_PCD_HI_Pos 27 /*!< LCD POL: PCD_HI Position */\r
-#define LCD_POL_PCD_HI_Msk (0x1fUL << LCD_POL_PCD_HI_Pos) /*!< LCD POL: PCD_HI Mask */\r
-\r
-// ----------------------------------------- LCD_LE ---------------------------------------------\r
-#define LCD_LE_LED_Pos 0 /*!< LCD LE: LED Position */\r
-#define LCD_LE_LED_Msk (0x7fUL << LCD_LE_LED_Pos) /*!< LCD LE: LED Mask */\r
-#define LCD_LE_LEE_Pos 16 /*!< LCD LE: LEE Position */\r
-#define LCD_LE_LEE_Msk (0x01UL << LCD_LE_LEE_Pos) /*!< LCD LE: LEE Mask */\r
-\r
-// --------------------------------------- LCD_UPBASE -------------------------------------------\r
-#define LCD_UPBASE_LCDUPBASE_Pos 3 /*!< LCD UPBASE: LCDUPBASE Position */\r
-#define LCD_UPBASE_LCDUPBASE_Msk (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos) /*!< LCD UPBASE: LCDUPBASE Mask */\r
-\r
-// --------------------------------------- LCD_LPBASE -------------------------------------------\r
-#define LCD_LPBASE_LCDLPBASE_Pos 3 /*!< LCD LPBASE: LCDLPBASE Position */\r
-#define LCD_LPBASE_LCDLPBASE_Msk (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos) /*!< LCD LPBASE: LCDLPBASE Mask */\r
-\r
-// ---------------------------------------- LCD_CTRL --------------------------------------------\r
-#define LCD_CTRL_LCDEN_Pos 0 /*!< LCD CTRL: LCDEN Position */\r
-#define LCD_CTRL_LCDEN_Msk (0x01UL << LCD_CTRL_LCDEN_Pos) /*!< LCD CTRL: LCDEN Mask */\r
-#define LCD_CTRL_LCDBPP_Pos 1 /*!< LCD CTRL: LCDBPP Position */\r
-#define LCD_CTRL_LCDBPP_Msk (0x07UL << LCD_CTRL_LCDBPP_Pos) /*!< LCD CTRL: LCDBPP Mask */\r
-#define LCD_CTRL_LCDBW_Pos 4 /*!< LCD CTRL: LCDBW Position */\r
-#define LCD_CTRL_LCDBW_Msk (0x01UL << LCD_CTRL_LCDBW_Pos) /*!< LCD CTRL: LCDBW Mask */\r
-#define LCD_CTRL_LCDTFT_Pos 5 /*!< LCD CTRL: LCDTFT Position */\r
-#define LCD_CTRL_LCDTFT_Msk (0x01UL << LCD_CTRL_LCDTFT_Pos) /*!< LCD CTRL: LCDTFT Mask */\r
-#define LCD_CTRL_LCDMONO8_Pos 6 /*!< LCD CTRL: LCDMONO8 Position */\r
-#define LCD_CTRL_LCDMONO8_Msk (0x01UL << LCD_CTRL_LCDMONO8_Pos) /*!< LCD CTRL: LCDMONO8 Mask */\r
-#define LCD_CTRL_LCDDUAL_Pos 7 /*!< LCD CTRL: LCDDUAL Position */\r
-#define LCD_CTRL_LCDDUAL_Msk (0x01UL << LCD_CTRL_LCDDUAL_Pos) /*!< LCD CTRL: LCDDUAL Mask */\r
-#define LCD_CTRL_BGR_Pos 8 /*!< LCD CTRL: BGR Position */\r
-#define LCD_CTRL_BGR_Msk (0x01UL << LCD_CTRL_BGR_Pos) /*!< LCD CTRL: BGR Mask */\r
-#define LCD_CTRL_BEBO_Pos 9 /*!< LCD CTRL: BEBO Position */\r
-#define LCD_CTRL_BEBO_Msk (0x01UL << LCD_CTRL_BEBO_Pos) /*!< LCD CTRL: BEBO Mask */\r
-#define LCD_CTRL_BEPO_Pos 10 /*!< LCD CTRL: BEPO Position */\r
-#define LCD_CTRL_BEPO_Msk (0x01UL << LCD_CTRL_BEPO_Pos) /*!< LCD CTRL: BEPO Mask */\r
-#define LCD_CTRL_LCDPWR_Pos 11 /*!< LCD CTRL: LCDPWR Position */\r
-#define LCD_CTRL_LCDPWR_Msk (0x01UL << LCD_CTRL_LCDPWR_Pos) /*!< LCD CTRL: LCDPWR Mask */\r
-#define LCD_CTRL_LCDVCOMP_Pos 12 /*!< LCD CTRL: LCDVCOMP Position */\r
-#define LCD_CTRL_LCDVCOMP_Msk (0x03UL << LCD_CTRL_LCDVCOMP_Pos) /*!< LCD CTRL: LCDVCOMP Mask */\r
-#define LCD_CTRL_WATERMARK_Pos 16 /*!< LCD CTRL: WATERMARK Position */\r
-#define LCD_CTRL_WATERMARK_Msk (0x01UL << LCD_CTRL_WATERMARK_Pos) /*!< LCD CTRL: WATERMARK Mask */\r
-\r
-// --------------------------------------- LCD_INTMSK -------------------------------------------\r
-#define LCD_INTMSK_FUFIM_Pos 1 /*!< LCD INTMSK: FUFIM Position */\r
-#define LCD_INTMSK_FUFIM_Msk (0x01UL << LCD_INTMSK_FUFIM_Pos) /*!< LCD INTMSK: FUFIM Mask */\r
-#define LCD_INTMSK_LNBUIM_Pos 2 /*!< LCD INTMSK: LNBUIM Position */\r
-#define LCD_INTMSK_LNBUIM_Msk (0x01UL << LCD_INTMSK_LNBUIM_Pos) /*!< LCD INTMSK: LNBUIM Mask */\r
-#define LCD_INTMSK_VCOMPIM_Pos 3 /*!< LCD INTMSK: VCOMPIM Position */\r
-#define LCD_INTMSK_VCOMPIM_Msk (0x01UL << LCD_INTMSK_VCOMPIM_Pos) /*!< LCD INTMSK: VCOMPIM Mask */\r
-#define LCD_INTMSK_BERIM_Pos 4 /*!< LCD INTMSK: BERIM Position */\r
-#define LCD_INTMSK_BERIM_Msk (0x01UL << LCD_INTMSK_BERIM_Pos) /*!< LCD INTMSK: BERIM Mask */\r
-\r
-// --------------------------------------- LCD_INTRAW -------------------------------------------\r
-#define LCD_INTRAW_FUFRIS_Pos 1 /*!< LCD INTRAW: FUFRIS Position */\r
-#define LCD_INTRAW_FUFRIS_Msk (0x01UL << LCD_INTRAW_FUFRIS_Pos) /*!< LCD INTRAW: FUFRIS Mask */\r
-#define LCD_INTRAW_LNBURIS_Pos 2 /*!< LCD INTRAW: LNBURIS Position */\r
-#define LCD_INTRAW_LNBURIS_Msk (0x01UL << LCD_INTRAW_LNBURIS_Pos) /*!< LCD INTRAW: LNBURIS Mask */\r
-#define LCD_INTRAW_VCOMPRIS_Pos 3 /*!< LCD INTRAW: VCOMPRIS Position */\r
-#define LCD_INTRAW_VCOMPRIS_Msk (0x01UL << LCD_INTRAW_VCOMPRIS_Pos) /*!< LCD INTRAW: VCOMPRIS Mask */\r
-#define LCD_INTRAW_BERRAW_Pos 4 /*!< LCD INTRAW: BERRAW Position */\r
-#define LCD_INTRAW_BERRAW_Msk (0x01UL << LCD_INTRAW_BERRAW_Pos) /*!< LCD INTRAW: BERRAW Mask */\r
-\r
-// --------------------------------------- LCD_INTSTAT ------------------------------------------\r
-#define LCD_INTSTAT_FUFMIS_Pos 1 /*!< LCD INTSTAT: FUFMIS Position */\r
-#define LCD_INTSTAT_FUFMIS_Msk (0x01UL << LCD_INTSTAT_FUFMIS_Pos) /*!< LCD INTSTAT: FUFMIS Mask */\r
-#define LCD_INTSTAT_LNBUMIS_Pos 2 /*!< LCD INTSTAT: LNBUMIS Position */\r
-#define LCD_INTSTAT_LNBUMIS_Msk (0x01UL << LCD_INTSTAT_LNBUMIS_Pos) /*!< LCD INTSTAT: LNBUMIS Mask */\r
-#define LCD_INTSTAT_VCOMPMIS_Pos 3 /*!< LCD INTSTAT: VCOMPMIS Position */\r
-#define LCD_INTSTAT_VCOMPMIS_Msk (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos) /*!< LCD INTSTAT: VCOMPMIS Mask */\r
-#define LCD_INTSTAT_BERMIS_Pos 4 /*!< LCD INTSTAT: BERMIS Position */\r
-#define LCD_INTSTAT_BERMIS_Msk (0x01UL << LCD_INTSTAT_BERMIS_Pos) /*!< LCD INTSTAT: BERMIS Mask */\r
-\r
-// --------------------------------------- LCD_INTCLR -------------------------------------------\r
-#define LCD_INTCLR_FUFIC_Pos 1 /*!< LCD INTCLR: FUFIC Position */\r
-#define LCD_INTCLR_FUFIC_Msk (0x01UL << LCD_INTCLR_FUFIC_Pos) /*!< LCD INTCLR: FUFIC Mask */\r
-#define LCD_INTCLR_LNBUIC_Pos 2 /*!< LCD INTCLR: LNBUIC Position */\r
-#define LCD_INTCLR_LNBUIC_Msk (0x01UL << LCD_INTCLR_LNBUIC_Pos) /*!< LCD INTCLR: LNBUIC Mask */\r
-#define LCD_INTCLR_VCOMPIC_Pos 3 /*!< LCD INTCLR: VCOMPIC Position */\r
-#define LCD_INTCLR_VCOMPIC_Msk (0x01UL << LCD_INTCLR_VCOMPIC_Pos) /*!< LCD INTCLR: VCOMPIC Mask */\r
-#define LCD_INTCLR_BERIC_Pos 4 /*!< LCD INTCLR: BERIC Position */\r
-#define LCD_INTCLR_BERIC_Msk (0x01UL << LCD_INTCLR_BERIC_Pos) /*!< LCD INTCLR: BERIC Mask */\r
-\r
-// --------------------------------------- LCD_UPCURR -------------------------------------------\r
-#define LCD_UPCURR_LCDUPCURR_Pos 0 /*!< LCD UPCURR: LCDUPCURR Position */\r
-#define LCD_UPCURR_LCDUPCURR_Msk (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos) /*!< LCD UPCURR: LCDUPCURR Mask */\r
-\r
-// --------------------------------------- LCD_LPCURR -------------------------------------------\r
-#define LCD_LPCURR_LCDLPCURR_Pos 0 /*!< LCD LPCURR: LCDLPCURR Position */\r
-#define LCD_LPCURR_LCDLPCURR_Msk (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos) /*!< LCD LPCURR: LCDLPCURR Mask */\r
-\r
-// ---------------------------------------- LCD_PAL0 --------------------------------------------\r
-#define LCD_PAL0_R04_0_Pos 0 /*!< LCD PAL0: R04_0 Position */\r
-#define LCD_PAL0_R04_0_Msk (0x1fUL << LCD_PAL0_R04_0_Pos) /*!< LCD PAL0: R04_0 Mask */\r
-#define LCD_PAL0_G04_0_Pos 5 /*!< LCD PAL0: G04_0 Position */\r
-#define LCD_PAL0_G04_0_Msk (0x1fUL << LCD_PAL0_G04_0_Pos) /*!< LCD PAL0: G04_0 Mask */\r
-#define LCD_PAL0_B04_0_Pos 10 /*!< LCD PAL0: B04_0 Position */\r
-#define LCD_PAL0_B04_0_Msk (0x1fUL << LCD_PAL0_B04_0_Pos) /*!< LCD PAL0: B04_0 Mask */\r
-#define LCD_PAL0_I0_Pos 15 /*!< LCD PAL0: I0 Position */\r
-#define LCD_PAL0_I0_Msk (0x01UL << LCD_PAL0_I0_Pos) /*!< LCD PAL0: I0 Mask */\r
-#define LCD_PAL0_R14_0_Pos 16 /*!< LCD PAL0: R14_0 Position */\r
-#define LCD_PAL0_R14_0_Msk (0x1fUL << LCD_PAL0_R14_0_Pos) /*!< LCD PAL0: R14_0 Mask */\r
-#define LCD_PAL0_G14_0_Pos 21 /*!< LCD PAL0: G14_0 Position */\r
-#define LCD_PAL0_G14_0_Msk (0x1fUL << LCD_PAL0_G14_0_Pos) /*!< LCD PAL0: G14_0 Mask */\r
-#define LCD_PAL0_B14_0_Pos 26 /*!< LCD PAL0: B14_0 Position */\r
-#define LCD_PAL0_B14_0_Msk (0x1fUL << LCD_PAL0_B14_0_Pos) /*!< LCD PAL0: B14_0 Mask */\r
-#define LCD_PAL0_I1_Pos 31 /*!< LCD PAL0: I1 Position */\r
-#define LCD_PAL0_I1_Msk (0x01UL << LCD_PAL0_I1_Pos) /*!< LCD PAL0: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL1 --------------------------------------------\r
-#define LCD_PAL1_R04_0_Pos 0 /*!< LCD PAL1: R04_0 Position */\r
-#define LCD_PAL1_R04_0_Msk (0x1fUL << LCD_PAL1_R04_0_Pos) /*!< LCD PAL1: R04_0 Mask */\r
-#define LCD_PAL1_G04_0_Pos 5 /*!< LCD PAL1: G04_0 Position */\r
-#define LCD_PAL1_G04_0_Msk (0x1fUL << LCD_PAL1_G04_0_Pos) /*!< LCD PAL1: G04_0 Mask */\r
-#define LCD_PAL1_B04_0_Pos 10 /*!< LCD PAL1: B04_0 Position */\r
-#define LCD_PAL1_B04_0_Msk (0x1fUL << LCD_PAL1_B04_0_Pos) /*!< LCD PAL1: B04_0 Mask */\r
-#define LCD_PAL1_I0_Pos 15 /*!< LCD PAL1: I0 Position */\r
-#define LCD_PAL1_I0_Msk (0x01UL << LCD_PAL1_I0_Pos) /*!< LCD PAL1: I0 Mask */\r
-#define LCD_PAL1_R14_0_Pos 16 /*!< LCD PAL1: R14_0 Position */\r
-#define LCD_PAL1_R14_0_Msk (0x1fUL << LCD_PAL1_R14_0_Pos) /*!< LCD PAL1: R14_0 Mask */\r
-#define LCD_PAL1_G14_0_Pos 21 /*!< LCD PAL1: G14_0 Position */\r
-#define LCD_PAL1_G14_0_Msk (0x1fUL << LCD_PAL1_G14_0_Pos) /*!< LCD PAL1: G14_0 Mask */\r
-#define LCD_PAL1_B14_0_Pos 26 /*!< LCD PAL1: B14_0 Position */\r
-#define LCD_PAL1_B14_0_Msk (0x1fUL << LCD_PAL1_B14_0_Pos) /*!< LCD PAL1: B14_0 Mask */\r
-#define LCD_PAL1_I1_Pos 31 /*!< LCD PAL1: I1 Position */\r
-#define LCD_PAL1_I1_Msk (0x01UL << LCD_PAL1_I1_Pos) /*!< LCD PAL1: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL2 --------------------------------------------\r
-#define LCD_PAL2_R04_0_Pos 0 /*!< LCD PAL2: R04_0 Position */\r
-#define LCD_PAL2_R04_0_Msk (0x1fUL << LCD_PAL2_R04_0_Pos) /*!< LCD PAL2: R04_0 Mask */\r
-#define LCD_PAL2_G04_0_Pos 5 /*!< LCD PAL2: G04_0 Position */\r
-#define LCD_PAL2_G04_0_Msk (0x1fUL << LCD_PAL2_G04_0_Pos) /*!< LCD PAL2: G04_0 Mask */\r
-#define LCD_PAL2_B04_0_Pos 10 /*!< LCD PAL2: B04_0 Position */\r
-#define LCD_PAL2_B04_0_Msk (0x1fUL << LCD_PAL2_B04_0_Pos) /*!< LCD PAL2: B04_0 Mask */\r
-#define LCD_PAL2_I0_Pos 15 /*!< LCD PAL2: I0 Position */\r
-#define LCD_PAL2_I0_Msk (0x01UL << LCD_PAL2_I0_Pos) /*!< LCD PAL2: I0 Mask */\r
-#define LCD_PAL2_R14_0_Pos 16 /*!< LCD PAL2: R14_0 Position */\r
-#define LCD_PAL2_R14_0_Msk (0x1fUL << LCD_PAL2_R14_0_Pos) /*!< LCD PAL2: R14_0 Mask */\r
-#define LCD_PAL2_G14_0_Pos 21 /*!< LCD PAL2: G14_0 Position */\r
-#define LCD_PAL2_G14_0_Msk (0x1fUL << LCD_PAL2_G14_0_Pos) /*!< LCD PAL2: G14_0 Mask */\r
-#define LCD_PAL2_B14_0_Pos 26 /*!< LCD PAL2: B14_0 Position */\r
-#define LCD_PAL2_B14_0_Msk (0x1fUL << LCD_PAL2_B14_0_Pos) /*!< LCD PAL2: B14_0 Mask */\r
-#define LCD_PAL2_I1_Pos 31 /*!< LCD PAL2: I1 Position */\r
-#define LCD_PAL2_I1_Msk (0x01UL << LCD_PAL2_I1_Pos) /*!< LCD PAL2: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL3 --------------------------------------------\r
-#define LCD_PAL3_R04_0_Pos 0 /*!< LCD PAL3: R04_0 Position */\r
-#define LCD_PAL3_R04_0_Msk (0x1fUL << LCD_PAL3_R04_0_Pos) /*!< LCD PAL3: R04_0 Mask */\r
-#define LCD_PAL3_G04_0_Pos 5 /*!< LCD PAL3: G04_0 Position */\r
-#define LCD_PAL3_G04_0_Msk (0x1fUL << LCD_PAL3_G04_0_Pos) /*!< LCD PAL3: G04_0 Mask */\r
-#define LCD_PAL3_B04_0_Pos 10 /*!< LCD PAL3: B04_0 Position */\r
-#define LCD_PAL3_B04_0_Msk (0x1fUL << LCD_PAL3_B04_0_Pos) /*!< LCD PAL3: B04_0 Mask */\r
-#define LCD_PAL3_I0_Pos 15 /*!< LCD PAL3: I0 Position */\r
-#define LCD_PAL3_I0_Msk (0x01UL << LCD_PAL3_I0_Pos) /*!< LCD PAL3: I0 Mask */\r
-#define LCD_PAL3_R14_0_Pos 16 /*!< LCD PAL3: R14_0 Position */\r
-#define LCD_PAL3_R14_0_Msk (0x1fUL << LCD_PAL3_R14_0_Pos) /*!< LCD PAL3: R14_0 Mask */\r
-#define LCD_PAL3_G14_0_Pos 21 /*!< LCD PAL3: G14_0 Position */\r
-#define LCD_PAL3_G14_0_Msk (0x1fUL << LCD_PAL3_G14_0_Pos) /*!< LCD PAL3: G14_0 Mask */\r
-#define LCD_PAL3_B14_0_Pos 26 /*!< LCD PAL3: B14_0 Position */\r
-#define LCD_PAL3_B14_0_Msk (0x1fUL << LCD_PAL3_B14_0_Pos) /*!< LCD PAL3: B14_0 Mask */\r
-#define LCD_PAL3_I1_Pos 31 /*!< LCD PAL3: I1 Position */\r
-#define LCD_PAL3_I1_Msk (0x01UL << LCD_PAL3_I1_Pos) /*!< LCD PAL3: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL4 --------------------------------------------\r
-#define LCD_PAL4_R04_0_Pos 0 /*!< LCD PAL4: R04_0 Position */\r
-#define LCD_PAL4_R04_0_Msk (0x1fUL << LCD_PAL4_R04_0_Pos) /*!< LCD PAL4: R04_0 Mask */\r
-#define LCD_PAL4_G04_0_Pos 5 /*!< LCD PAL4: G04_0 Position */\r
-#define LCD_PAL4_G04_0_Msk (0x1fUL << LCD_PAL4_G04_0_Pos) /*!< LCD PAL4: G04_0 Mask */\r
-#define LCD_PAL4_B04_0_Pos 10 /*!< LCD PAL4: B04_0 Position */\r
-#define LCD_PAL4_B04_0_Msk (0x1fUL << LCD_PAL4_B04_0_Pos) /*!< LCD PAL4: B04_0 Mask */\r
-#define LCD_PAL4_I0_Pos 15 /*!< LCD PAL4: I0 Position */\r
-#define LCD_PAL4_I0_Msk (0x01UL << LCD_PAL4_I0_Pos) /*!< LCD PAL4: I0 Mask */\r
-#define LCD_PAL4_R14_0_Pos 16 /*!< LCD PAL4: R14_0 Position */\r
-#define LCD_PAL4_R14_0_Msk (0x1fUL << LCD_PAL4_R14_0_Pos) /*!< LCD PAL4: R14_0 Mask */\r
-#define LCD_PAL4_G14_0_Pos 21 /*!< LCD PAL4: G14_0 Position */\r
-#define LCD_PAL4_G14_0_Msk (0x1fUL << LCD_PAL4_G14_0_Pos) /*!< LCD PAL4: G14_0 Mask */\r
-#define LCD_PAL4_B14_0_Pos 26 /*!< LCD PAL4: B14_0 Position */\r
-#define LCD_PAL4_B14_0_Msk (0x1fUL << LCD_PAL4_B14_0_Pos) /*!< LCD PAL4: B14_0 Mask */\r
-#define LCD_PAL4_I1_Pos 31 /*!< LCD PAL4: I1 Position */\r
-#define LCD_PAL4_I1_Msk (0x01UL << LCD_PAL4_I1_Pos) /*!< LCD PAL4: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL5 --------------------------------------------\r
-#define LCD_PAL5_R04_0_Pos 0 /*!< LCD PAL5: R04_0 Position */\r
-#define LCD_PAL5_R04_0_Msk (0x1fUL << LCD_PAL5_R04_0_Pos) /*!< LCD PAL5: R04_0 Mask */\r
-#define LCD_PAL5_G04_0_Pos 5 /*!< LCD PAL5: G04_0 Position */\r
-#define LCD_PAL5_G04_0_Msk (0x1fUL << LCD_PAL5_G04_0_Pos) /*!< LCD PAL5: G04_0 Mask */\r
-#define LCD_PAL5_B04_0_Pos 10 /*!< LCD PAL5: B04_0 Position */\r
-#define LCD_PAL5_B04_0_Msk (0x1fUL << LCD_PAL5_B04_0_Pos) /*!< LCD PAL5: B04_0 Mask */\r
-#define LCD_PAL5_I0_Pos 15 /*!< LCD PAL5: I0 Position */\r
-#define LCD_PAL5_I0_Msk (0x01UL << LCD_PAL5_I0_Pos) /*!< LCD PAL5: I0 Mask */\r
-#define LCD_PAL5_R14_0_Pos 16 /*!< LCD PAL5: R14_0 Position */\r
-#define LCD_PAL5_R14_0_Msk (0x1fUL << LCD_PAL5_R14_0_Pos) /*!< LCD PAL5: R14_0 Mask */\r
-#define LCD_PAL5_G14_0_Pos 21 /*!< LCD PAL5: G14_0 Position */\r
-#define LCD_PAL5_G14_0_Msk (0x1fUL << LCD_PAL5_G14_0_Pos) /*!< LCD PAL5: G14_0 Mask */\r
-#define LCD_PAL5_B14_0_Pos 26 /*!< LCD PAL5: B14_0 Position */\r
-#define LCD_PAL5_B14_0_Msk (0x1fUL << LCD_PAL5_B14_0_Pos) /*!< LCD PAL5: B14_0 Mask */\r
-#define LCD_PAL5_I1_Pos 31 /*!< LCD PAL5: I1 Position */\r
-#define LCD_PAL5_I1_Msk (0x01UL << LCD_PAL5_I1_Pos) /*!< LCD PAL5: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL6 --------------------------------------------\r
-#define LCD_PAL6_R04_0_Pos 0 /*!< LCD PAL6: R04_0 Position */\r
-#define LCD_PAL6_R04_0_Msk (0x1fUL << LCD_PAL6_R04_0_Pos) /*!< LCD PAL6: R04_0 Mask */\r
-#define LCD_PAL6_G04_0_Pos 5 /*!< LCD PAL6: G04_0 Position */\r
-#define LCD_PAL6_G04_0_Msk (0x1fUL << LCD_PAL6_G04_0_Pos) /*!< LCD PAL6: G04_0 Mask */\r
-#define LCD_PAL6_B04_0_Pos 10 /*!< LCD PAL6: B04_0 Position */\r
-#define LCD_PAL6_B04_0_Msk (0x1fUL << LCD_PAL6_B04_0_Pos) /*!< LCD PAL6: B04_0 Mask */\r
-#define LCD_PAL6_I0_Pos 15 /*!< LCD PAL6: I0 Position */\r
-#define LCD_PAL6_I0_Msk (0x01UL << LCD_PAL6_I0_Pos) /*!< LCD PAL6: I0 Mask */\r
-#define LCD_PAL6_R14_0_Pos 16 /*!< LCD PAL6: R14_0 Position */\r
-#define LCD_PAL6_R14_0_Msk (0x1fUL << LCD_PAL6_R14_0_Pos) /*!< LCD PAL6: R14_0 Mask */\r
-#define LCD_PAL6_G14_0_Pos 21 /*!< LCD PAL6: G14_0 Position */\r
-#define LCD_PAL6_G14_0_Msk (0x1fUL << LCD_PAL6_G14_0_Pos) /*!< LCD PAL6: G14_0 Mask */\r
-#define LCD_PAL6_B14_0_Pos 26 /*!< LCD PAL6: B14_0 Position */\r
-#define LCD_PAL6_B14_0_Msk (0x1fUL << LCD_PAL6_B14_0_Pos) /*!< LCD PAL6: B14_0 Mask */\r
-#define LCD_PAL6_I1_Pos 31 /*!< LCD PAL6: I1 Position */\r
-#define LCD_PAL6_I1_Msk (0x01UL << LCD_PAL6_I1_Pos) /*!< LCD PAL6: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL7 --------------------------------------------\r
-#define LCD_PAL7_R04_0_Pos 0 /*!< LCD PAL7: R04_0 Position */\r
-#define LCD_PAL7_R04_0_Msk (0x1fUL << LCD_PAL7_R04_0_Pos) /*!< LCD PAL7: R04_0 Mask */\r
-#define LCD_PAL7_G04_0_Pos 5 /*!< LCD PAL7: G04_0 Position */\r
-#define LCD_PAL7_G04_0_Msk (0x1fUL << LCD_PAL7_G04_0_Pos) /*!< LCD PAL7: G04_0 Mask */\r
-#define LCD_PAL7_B04_0_Pos 10 /*!< LCD PAL7: B04_0 Position */\r
-#define LCD_PAL7_B04_0_Msk (0x1fUL << LCD_PAL7_B04_0_Pos) /*!< LCD PAL7: B04_0 Mask */\r
-#define LCD_PAL7_I0_Pos 15 /*!< LCD PAL7: I0 Position */\r
-#define LCD_PAL7_I0_Msk (0x01UL << LCD_PAL7_I0_Pos) /*!< LCD PAL7: I0 Mask */\r
-#define LCD_PAL7_R14_0_Pos 16 /*!< LCD PAL7: R14_0 Position */\r
-#define LCD_PAL7_R14_0_Msk (0x1fUL << LCD_PAL7_R14_0_Pos) /*!< LCD PAL7: R14_0 Mask */\r
-#define LCD_PAL7_G14_0_Pos 21 /*!< LCD PAL7: G14_0 Position */\r
-#define LCD_PAL7_G14_0_Msk (0x1fUL << LCD_PAL7_G14_0_Pos) /*!< LCD PAL7: G14_0 Mask */\r
-#define LCD_PAL7_B14_0_Pos 26 /*!< LCD PAL7: B14_0 Position */\r
-#define LCD_PAL7_B14_0_Msk (0x1fUL << LCD_PAL7_B14_0_Pos) /*!< LCD PAL7: B14_0 Mask */\r
-#define LCD_PAL7_I1_Pos 31 /*!< LCD PAL7: I1 Position */\r
-#define LCD_PAL7_I1_Msk (0x01UL << LCD_PAL7_I1_Pos) /*!< LCD PAL7: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL8 --------------------------------------------\r
-#define LCD_PAL8_R04_0_Pos 0 /*!< LCD PAL8: R04_0 Position */\r
-#define LCD_PAL8_R04_0_Msk (0x1fUL << LCD_PAL8_R04_0_Pos) /*!< LCD PAL8: R04_0 Mask */\r
-#define LCD_PAL8_G04_0_Pos 5 /*!< LCD PAL8: G04_0 Position */\r
-#define LCD_PAL8_G04_0_Msk (0x1fUL << LCD_PAL8_G04_0_Pos) /*!< LCD PAL8: G04_0 Mask */\r
-#define LCD_PAL8_B04_0_Pos 10 /*!< LCD PAL8: B04_0 Position */\r
-#define LCD_PAL8_B04_0_Msk (0x1fUL << LCD_PAL8_B04_0_Pos) /*!< LCD PAL8: B04_0 Mask */\r
-#define LCD_PAL8_I0_Pos 15 /*!< LCD PAL8: I0 Position */\r
-#define LCD_PAL8_I0_Msk (0x01UL << LCD_PAL8_I0_Pos) /*!< LCD PAL8: I0 Mask */\r
-#define LCD_PAL8_R14_0_Pos 16 /*!< LCD PAL8: R14_0 Position */\r
-#define LCD_PAL8_R14_0_Msk (0x1fUL << LCD_PAL8_R14_0_Pos) /*!< LCD PAL8: R14_0 Mask */\r
-#define LCD_PAL8_G14_0_Pos 21 /*!< LCD PAL8: G14_0 Position */\r
-#define LCD_PAL8_G14_0_Msk (0x1fUL << LCD_PAL8_G14_0_Pos) /*!< LCD PAL8: G14_0 Mask */\r
-#define LCD_PAL8_B14_0_Pos 26 /*!< LCD PAL8: B14_0 Position */\r
-#define LCD_PAL8_B14_0_Msk (0x1fUL << LCD_PAL8_B14_0_Pos) /*!< LCD PAL8: B14_0 Mask */\r
-#define LCD_PAL8_I1_Pos 31 /*!< LCD PAL8: I1 Position */\r
-#define LCD_PAL8_I1_Msk (0x01UL << LCD_PAL8_I1_Pos) /*!< LCD PAL8: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL9 --------------------------------------------\r
-#define LCD_PAL9_R04_0_Pos 0 /*!< LCD PAL9: R04_0 Position */\r
-#define LCD_PAL9_R04_0_Msk (0x1fUL << LCD_PAL9_R04_0_Pos) /*!< LCD PAL9: R04_0 Mask */\r
-#define LCD_PAL9_G04_0_Pos 5 /*!< LCD PAL9: G04_0 Position */\r
-#define LCD_PAL9_G04_0_Msk (0x1fUL << LCD_PAL9_G04_0_Pos) /*!< LCD PAL9: G04_0 Mask */\r
-#define LCD_PAL9_B04_0_Pos 10 /*!< LCD PAL9: B04_0 Position */\r
-#define LCD_PAL9_B04_0_Msk (0x1fUL << LCD_PAL9_B04_0_Pos) /*!< LCD PAL9: B04_0 Mask */\r
-#define LCD_PAL9_I0_Pos 15 /*!< LCD PAL9: I0 Position */\r
-#define LCD_PAL9_I0_Msk (0x01UL << LCD_PAL9_I0_Pos) /*!< LCD PAL9: I0 Mask */\r
-#define LCD_PAL9_R14_0_Pos 16 /*!< LCD PAL9: R14_0 Position */\r
-#define LCD_PAL9_R14_0_Msk (0x1fUL << LCD_PAL9_R14_0_Pos) /*!< LCD PAL9: R14_0 Mask */\r
-#define LCD_PAL9_G14_0_Pos 21 /*!< LCD PAL9: G14_0 Position */\r
-#define LCD_PAL9_G14_0_Msk (0x1fUL << LCD_PAL9_G14_0_Pos) /*!< LCD PAL9: G14_0 Mask */\r
-#define LCD_PAL9_B14_0_Pos 26 /*!< LCD PAL9: B14_0 Position */\r
-#define LCD_PAL9_B14_0_Msk (0x1fUL << LCD_PAL9_B14_0_Pos) /*!< LCD PAL9: B14_0 Mask */\r
-#define LCD_PAL9_I1_Pos 31 /*!< LCD PAL9: I1 Position */\r
-#define LCD_PAL9_I1_Msk (0x01UL << LCD_PAL9_I1_Pos) /*!< LCD PAL9: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL10 -------------------------------------------\r
-#define LCD_PAL10_R04_0_Pos 0 /*!< LCD PAL10: R04_0 Position */\r
-#define LCD_PAL10_R04_0_Msk (0x1fUL << LCD_PAL10_R04_0_Pos) /*!< LCD PAL10: R04_0 Mask */\r
-#define LCD_PAL10_G04_0_Pos 5 /*!< LCD PAL10: G04_0 Position */\r
-#define LCD_PAL10_G04_0_Msk (0x1fUL << LCD_PAL10_G04_0_Pos) /*!< LCD PAL10: G04_0 Mask */\r
-#define LCD_PAL10_B04_0_Pos 10 /*!< LCD PAL10: B04_0 Position */\r
-#define LCD_PAL10_B04_0_Msk (0x1fUL << LCD_PAL10_B04_0_Pos) /*!< LCD PAL10: B04_0 Mask */\r
-#define LCD_PAL10_I0_Pos 15 /*!< LCD PAL10: I0 Position */\r
-#define LCD_PAL10_I0_Msk (0x01UL << LCD_PAL10_I0_Pos) /*!< LCD PAL10: I0 Mask */\r
-#define LCD_PAL10_R14_0_Pos 16 /*!< LCD PAL10: R14_0 Position */\r
-#define LCD_PAL10_R14_0_Msk (0x1fUL << LCD_PAL10_R14_0_Pos) /*!< LCD PAL10: R14_0 Mask */\r
-#define LCD_PAL10_G14_0_Pos 21 /*!< LCD PAL10: G14_0 Position */\r
-#define LCD_PAL10_G14_0_Msk (0x1fUL << LCD_PAL10_G14_0_Pos) /*!< LCD PAL10: G14_0 Mask */\r
-#define LCD_PAL10_B14_0_Pos 26 /*!< LCD PAL10: B14_0 Position */\r
-#define LCD_PAL10_B14_0_Msk (0x1fUL << LCD_PAL10_B14_0_Pos) /*!< LCD PAL10: B14_0 Mask */\r
-#define LCD_PAL10_I1_Pos 31 /*!< LCD PAL10: I1 Position */\r
-#define LCD_PAL10_I1_Msk (0x01UL << LCD_PAL10_I1_Pos) /*!< LCD PAL10: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL11 -------------------------------------------\r
-#define LCD_PAL11_R04_0_Pos 0 /*!< LCD PAL11: R04_0 Position */\r
-#define LCD_PAL11_R04_0_Msk (0x1fUL << LCD_PAL11_R04_0_Pos) /*!< LCD PAL11: R04_0 Mask */\r
-#define LCD_PAL11_G04_0_Pos 5 /*!< LCD PAL11: G04_0 Position */\r
-#define LCD_PAL11_G04_0_Msk (0x1fUL << LCD_PAL11_G04_0_Pos) /*!< LCD PAL11: G04_0 Mask */\r
-#define LCD_PAL11_B04_0_Pos 10 /*!< LCD PAL11: B04_0 Position */\r
-#define LCD_PAL11_B04_0_Msk (0x1fUL << LCD_PAL11_B04_0_Pos) /*!< LCD PAL11: B04_0 Mask */\r
-#define LCD_PAL11_I0_Pos 15 /*!< LCD PAL11: I0 Position */\r
-#define LCD_PAL11_I0_Msk (0x01UL << LCD_PAL11_I0_Pos) /*!< LCD PAL11: I0 Mask */\r
-#define LCD_PAL11_R14_0_Pos 16 /*!< LCD PAL11: R14_0 Position */\r
-#define LCD_PAL11_R14_0_Msk (0x1fUL << LCD_PAL11_R14_0_Pos) /*!< LCD PAL11: R14_0 Mask */\r
-#define LCD_PAL11_G14_0_Pos 21 /*!< LCD PAL11: G14_0 Position */\r
-#define LCD_PAL11_G14_0_Msk (0x1fUL << LCD_PAL11_G14_0_Pos) /*!< LCD PAL11: G14_0 Mask */\r
-#define LCD_PAL11_B14_0_Pos 26 /*!< LCD PAL11: B14_0 Position */\r
-#define LCD_PAL11_B14_0_Msk (0x1fUL << LCD_PAL11_B14_0_Pos) /*!< LCD PAL11: B14_0 Mask */\r
-#define LCD_PAL11_I1_Pos 31 /*!< LCD PAL11: I1 Position */\r
-#define LCD_PAL11_I1_Msk (0x01UL << LCD_PAL11_I1_Pos) /*!< LCD PAL11: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL12 -------------------------------------------\r
-#define LCD_PAL12_R04_0_Pos 0 /*!< LCD PAL12: R04_0 Position */\r
-#define LCD_PAL12_R04_0_Msk (0x1fUL << LCD_PAL12_R04_0_Pos) /*!< LCD PAL12: R04_0 Mask */\r
-#define LCD_PAL12_G04_0_Pos 5 /*!< LCD PAL12: G04_0 Position */\r
-#define LCD_PAL12_G04_0_Msk (0x1fUL << LCD_PAL12_G04_0_Pos) /*!< LCD PAL12: G04_0 Mask */\r
-#define LCD_PAL12_B04_0_Pos 10 /*!< LCD PAL12: B04_0 Position */\r
-#define LCD_PAL12_B04_0_Msk (0x1fUL << LCD_PAL12_B04_0_Pos) /*!< LCD PAL12: B04_0 Mask */\r
-#define LCD_PAL12_I0_Pos 15 /*!< LCD PAL12: I0 Position */\r
-#define LCD_PAL12_I0_Msk (0x01UL << LCD_PAL12_I0_Pos) /*!< LCD PAL12: I0 Mask */\r
-#define LCD_PAL12_R14_0_Pos 16 /*!< LCD PAL12: R14_0 Position */\r
-#define LCD_PAL12_R14_0_Msk (0x1fUL << LCD_PAL12_R14_0_Pos) /*!< LCD PAL12: R14_0 Mask */\r
-#define LCD_PAL12_G14_0_Pos 21 /*!< LCD PAL12: G14_0 Position */\r
-#define LCD_PAL12_G14_0_Msk (0x1fUL << LCD_PAL12_G14_0_Pos) /*!< LCD PAL12: G14_0 Mask */\r
-#define LCD_PAL12_B14_0_Pos 26 /*!< LCD PAL12: B14_0 Position */\r
-#define LCD_PAL12_B14_0_Msk (0x1fUL << LCD_PAL12_B14_0_Pos) /*!< LCD PAL12: B14_0 Mask */\r
-#define LCD_PAL12_I1_Pos 31 /*!< LCD PAL12: I1 Position */\r
-#define LCD_PAL12_I1_Msk (0x01UL << LCD_PAL12_I1_Pos) /*!< LCD PAL12: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL13 -------------------------------------------\r
-#define LCD_PAL13_R04_0_Pos 0 /*!< LCD PAL13: R04_0 Position */\r
-#define LCD_PAL13_R04_0_Msk (0x1fUL << LCD_PAL13_R04_0_Pos) /*!< LCD PAL13: R04_0 Mask */\r
-#define LCD_PAL13_G04_0_Pos 5 /*!< LCD PAL13: G04_0 Position */\r
-#define LCD_PAL13_G04_0_Msk (0x1fUL << LCD_PAL13_G04_0_Pos) /*!< LCD PAL13: G04_0 Mask */\r
-#define LCD_PAL13_B04_0_Pos 10 /*!< LCD PAL13: B04_0 Position */\r
-#define LCD_PAL13_B04_0_Msk (0x1fUL << LCD_PAL13_B04_0_Pos) /*!< LCD PAL13: B04_0 Mask */\r
-#define LCD_PAL13_I0_Pos 15 /*!< LCD PAL13: I0 Position */\r
-#define LCD_PAL13_I0_Msk (0x01UL << LCD_PAL13_I0_Pos) /*!< LCD PAL13: I0 Mask */\r
-#define LCD_PAL13_R14_0_Pos 16 /*!< LCD PAL13: R14_0 Position */\r
-#define LCD_PAL13_R14_0_Msk (0x1fUL << LCD_PAL13_R14_0_Pos) /*!< LCD PAL13: R14_0 Mask */\r
-#define LCD_PAL13_G14_0_Pos 21 /*!< LCD PAL13: G14_0 Position */\r
-#define LCD_PAL13_G14_0_Msk (0x1fUL << LCD_PAL13_G14_0_Pos) /*!< LCD PAL13: G14_0 Mask */\r
-#define LCD_PAL13_B14_0_Pos 26 /*!< LCD PAL13: B14_0 Position */\r
-#define LCD_PAL13_B14_0_Msk (0x1fUL << LCD_PAL13_B14_0_Pos) /*!< LCD PAL13: B14_0 Mask */\r
-#define LCD_PAL13_I1_Pos 31 /*!< LCD PAL13: I1 Position */\r
-#define LCD_PAL13_I1_Msk (0x01UL << LCD_PAL13_I1_Pos) /*!< LCD PAL13: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL14 -------------------------------------------\r
-#define LCD_PAL14_R04_0_Pos 0 /*!< LCD PAL14: R04_0 Position */\r
-#define LCD_PAL14_R04_0_Msk (0x1fUL << LCD_PAL14_R04_0_Pos) /*!< LCD PAL14: R04_0 Mask */\r
-#define LCD_PAL14_G04_0_Pos 5 /*!< LCD PAL14: G04_0 Position */\r
-#define LCD_PAL14_G04_0_Msk (0x1fUL << LCD_PAL14_G04_0_Pos) /*!< LCD PAL14: G04_0 Mask */\r
-#define LCD_PAL14_B04_0_Pos 10 /*!< LCD PAL14: B04_0 Position */\r
-#define LCD_PAL14_B04_0_Msk (0x1fUL << LCD_PAL14_B04_0_Pos) /*!< LCD PAL14: B04_0 Mask */\r
-#define LCD_PAL14_I0_Pos 15 /*!< LCD PAL14: I0 Position */\r
-#define LCD_PAL14_I0_Msk (0x01UL << LCD_PAL14_I0_Pos) /*!< LCD PAL14: I0 Mask */\r
-#define LCD_PAL14_R14_0_Pos 16 /*!< LCD PAL14: R14_0 Position */\r
-#define LCD_PAL14_R14_0_Msk (0x1fUL << LCD_PAL14_R14_0_Pos) /*!< LCD PAL14: R14_0 Mask */\r
-#define LCD_PAL14_G14_0_Pos 21 /*!< LCD PAL14: G14_0 Position */\r
-#define LCD_PAL14_G14_0_Msk (0x1fUL << LCD_PAL14_G14_0_Pos) /*!< LCD PAL14: G14_0 Mask */\r
-#define LCD_PAL14_B14_0_Pos 26 /*!< LCD PAL14: B14_0 Position */\r
-#define LCD_PAL14_B14_0_Msk (0x1fUL << LCD_PAL14_B14_0_Pos) /*!< LCD PAL14: B14_0 Mask */\r
-#define LCD_PAL14_I1_Pos 31 /*!< LCD PAL14: I1 Position */\r
-#define LCD_PAL14_I1_Msk (0x01UL << LCD_PAL14_I1_Pos) /*!< LCD PAL14: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL15 -------------------------------------------\r
-#define LCD_PAL15_R04_0_Pos 0 /*!< LCD PAL15: R04_0 Position */\r
-#define LCD_PAL15_R04_0_Msk (0x1fUL << LCD_PAL15_R04_0_Pos) /*!< LCD PAL15: R04_0 Mask */\r
-#define LCD_PAL15_G04_0_Pos 5 /*!< LCD PAL15: G04_0 Position */\r
-#define LCD_PAL15_G04_0_Msk (0x1fUL << LCD_PAL15_G04_0_Pos) /*!< LCD PAL15: G04_0 Mask */\r
-#define LCD_PAL15_B04_0_Pos 10 /*!< LCD PAL15: B04_0 Position */\r
-#define LCD_PAL15_B04_0_Msk (0x1fUL << LCD_PAL15_B04_0_Pos) /*!< LCD PAL15: B04_0 Mask */\r
-#define LCD_PAL15_I0_Pos 15 /*!< LCD PAL15: I0 Position */\r
-#define LCD_PAL15_I0_Msk (0x01UL << LCD_PAL15_I0_Pos) /*!< LCD PAL15: I0 Mask */\r
-#define LCD_PAL15_R14_0_Pos 16 /*!< LCD PAL15: R14_0 Position */\r
-#define LCD_PAL15_R14_0_Msk (0x1fUL << LCD_PAL15_R14_0_Pos) /*!< LCD PAL15: R14_0 Mask */\r
-#define LCD_PAL15_G14_0_Pos 21 /*!< LCD PAL15: G14_0 Position */\r
-#define LCD_PAL15_G14_0_Msk (0x1fUL << LCD_PAL15_G14_0_Pos) /*!< LCD PAL15: G14_0 Mask */\r
-#define LCD_PAL15_B14_0_Pos 26 /*!< LCD PAL15: B14_0 Position */\r
-#define LCD_PAL15_B14_0_Msk (0x1fUL << LCD_PAL15_B14_0_Pos) /*!< LCD PAL15: B14_0 Mask */\r
-#define LCD_PAL15_I1_Pos 31 /*!< LCD PAL15: I1 Position */\r
-#define LCD_PAL15_I1_Msk (0x01UL << LCD_PAL15_I1_Pos) /*!< LCD PAL15: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL16 -------------------------------------------\r
-#define LCD_PAL16_R04_0_Pos 0 /*!< LCD PAL16: R04_0 Position */\r
-#define LCD_PAL16_R04_0_Msk (0x1fUL << LCD_PAL16_R04_0_Pos) /*!< LCD PAL16: R04_0 Mask */\r
-#define LCD_PAL16_G04_0_Pos 5 /*!< LCD PAL16: G04_0 Position */\r
-#define LCD_PAL16_G04_0_Msk (0x1fUL << LCD_PAL16_G04_0_Pos) /*!< LCD PAL16: G04_0 Mask */\r
-#define LCD_PAL16_B04_0_Pos 10 /*!< LCD PAL16: B04_0 Position */\r
-#define LCD_PAL16_B04_0_Msk (0x1fUL << LCD_PAL16_B04_0_Pos) /*!< LCD PAL16: B04_0 Mask */\r
-#define LCD_PAL16_I0_Pos 15 /*!< LCD PAL16: I0 Position */\r
-#define LCD_PAL16_I0_Msk (0x01UL << LCD_PAL16_I0_Pos) /*!< LCD PAL16: I0 Mask */\r
-#define LCD_PAL16_R14_0_Pos 16 /*!< LCD PAL16: R14_0 Position */\r
-#define LCD_PAL16_R14_0_Msk (0x1fUL << LCD_PAL16_R14_0_Pos) /*!< LCD PAL16: R14_0 Mask */\r
-#define LCD_PAL16_G14_0_Pos 21 /*!< LCD PAL16: G14_0 Position */\r
-#define LCD_PAL16_G14_0_Msk (0x1fUL << LCD_PAL16_G14_0_Pos) /*!< LCD PAL16: G14_0 Mask */\r
-#define LCD_PAL16_B14_0_Pos 26 /*!< LCD PAL16: B14_0 Position */\r
-#define LCD_PAL16_B14_0_Msk (0x1fUL << LCD_PAL16_B14_0_Pos) /*!< LCD PAL16: B14_0 Mask */\r
-#define LCD_PAL16_I1_Pos 31 /*!< LCD PAL16: I1 Position */\r
-#define LCD_PAL16_I1_Msk (0x01UL << LCD_PAL16_I1_Pos) /*!< LCD PAL16: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL17 -------------------------------------------\r
-#define LCD_PAL17_R04_0_Pos 0 /*!< LCD PAL17: R04_0 Position */\r
-#define LCD_PAL17_R04_0_Msk (0x1fUL << LCD_PAL17_R04_0_Pos) /*!< LCD PAL17: R04_0 Mask */\r
-#define LCD_PAL17_G04_0_Pos 5 /*!< LCD PAL17: G04_0 Position */\r
-#define LCD_PAL17_G04_0_Msk (0x1fUL << LCD_PAL17_G04_0_Pos) /*!< LCD PAL17: G04_0 Mask */\r
-#define LCD_PAL17_B04_0_Pos 10 /*!< LCD PAL17: B04_0 Position */\r
-#define LCD_PAL17_B04_0_Msk (0x1fUL << LCD_PAL17_B04_0_Pos) /*!< LCD PAL17: B04_0 Mask */\r
-#define LCD_PAL17_I0_Pos 15 /*!< LCD PAL17: I0 Position */\r
-#define LCD_PAL17_I0_Msk (0x01UL << LCD_PAL17_I0_Pos) /*!< LCD PAL17: I0 Mask */\r
-#define LCD_PAL17_R14_0_Pos 16 /*!< LCD PAL17: R14_0 Position */\r
-#define LCD_PAL17_R14_0_Msk (0x1fUL << LCD_PAL17_R14_0_Pos) /*!< LCD PAL17: R14_0 Mask */\r
-#define LCD_PAL17_G14_0_Pos 21 /*!< LCD PAL17: G14_0 Position */\r
-#define LCD_PAL17_G14_0_Msk (0x1fUL << LCD_PAL17_G14_0_Pos) /*!< LCD PAL17: G14_0 Mask */\r
-#define LCD_PAL17_B14_0_Pos 26 /*!< LCD PAL17: B14_0 Position */\r
-#define LCD_PAL17_B14_0_Msk (0x1fUL << LCD_PAL17_B14_0_Pos) /*!< LCD PAL17: B14_0 Mask */\r
-#define LCD_PAL17_I1_Pos 31 /*!< LCD PAL17: I1 Position */\r
-#define LCD_PAL17_I1_Msk (0x01UL << LCD_PAL17_I1_Pos) /*!< LCD PAL17: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL18 -------------------------------------------\r
-#define LCD_PAL18_R04_0_Pos 0 /*!< LCD PAL18: R04_0 Position */\r
-#define LCD_PAL18_R04_0_Msk (0x1fUL << LCD_PAL18_R04_0_Pos) /*!< LCD PAL18: R04_0 Mask */\r
-#define LCD_PAL18_G04_0_Pos 5 /*!< LCD PAL18: G04_0 Position */\r
-#define LCD_PAL18_G04_0_Msk (0x1fUL << LCD_PAL18_G04_0_Pos) /*!< LCD PAL18: G04_0 Mask */\r
-#define LCD_PAL18_B04_0_Pos 10 /*!< LCD PAL18: B04_0 Position */\r
-#define LCD_PAL18_B04_0_Msk (0x1fUL << LCD_PAL18_B04_0_Pos) /*!< LCD PAL18: B04_0 Mask */\r
-#define LCD_PAL18_I0_Pos 15 /*!< LCD PAL18: I0 Position */\r
-#define LCD_PAL18_I0_Msk (0x01UL << LCD_PAL18_I0_Pos) /*!< LCD PAL18: I0 Mask */\r
-#define LCD_PAL18_R14_0_Pos 16 /*!< LCD PAL18: R14_0 Position */\r
-#define LCD_PAL18_R14_0_Msk (0x1fUL << LCD_PAL18_R14_0_Pos) /*!< LCD PAL18: R14_0 Mask */\r
-#define LCD_PAL18_G14_0_Pos 21 /*!< LCD PAL18: G14_0 Position */\r
-#define LCD_PAL18_G14_0_Msk (0x1fUL << LCD_PAL18_G14_0_Pos) /*!< LCD PAL18: G14_0 Mask */\r
-#define LCD_PAL18_B14_0_Pos 26 /*!< LCD PAL18: B14_0 Position */\r
-#define LCD_PAL18_B14_0_Msk (0x1fUL << LCD_PAL18_B14_0_Pos) /*!< LCD PAL18: B14_0 Mask */\r
-#define LCD_PAL18_I1_Pos 31 /*!< LCD PAL18: I1 Position */\r
-#define LCD_PAL18_I1_Msk (0x01UL << LCD_PAL18_I1_Pos) /*!< LCD PAL18: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL19 -------------------------------------------\r
-#define LCD_PAL19_R04_0_Pos 0 /*!< LCD PAL19: R04_0 Position */\r
-#define LCD_PAL19_R04_0_Msk (0x1fUL << LCD_PAL19_R04_0_Pos) /*!< LCD PAL19: R04_0 Mask */\r
-#define LCD_PAL19_G04_0_Pos 5 /*!< LCD PAL19: G04_0 Position */\r
-#define LCD_PAL19_G04_0_Msk (0x1fUL << LCD_PAL19_G04_0_Pos) /*!< LCD PAL19: G04_0 Mask */\r
-#define LCD_PAL19_B04_0_Pos 10 /*!< LCD PAL19: B04_0 Position */\r
-#define LCD_PAL19_B04_0_Msk (0x1fUL << LCD_PAL19_B04_0_Pos) /*!< LCD PAL19: B04_0 Mask */\r
-#define LCD_PAL19_I0_Pos 15 /*!< LCD PAL19: I0 Position */\r
-#define LCD_PAL19_I0_Msk (0x01UL << LCD_PAL19_I0_Pos) /*!< LCD PAL19: I0 Mask */\r
-#define LCD_PAL19_R14_0_Pos 16 /*!< LCD PAL19: R14_0 Position */\r
-#define LCD_PAL19_R14_0_Msk (0x1fUL << LCD_PAL19_R14_0_Pos) /*!< LCD PAL19: R14_0 Mask */\r
-#define LCD_PAL19_G14_0_Pos 21 /*!< LCD PAL19: G14_0 Position */\r
-#define LCD_PAL19_G14_0_Msk (0x1fUL << LCD_PAL19_G14_0_Pos) /*!< LCD PAL19: G14_0 Mask */\r
-#define LCD_PAL19_B14_0_Pos 26 /*!< LCD PAL19: B14_0 Position */\r
-#define LCD_PAL19_B14_0_Msk (0x1fUL << LCD_PAL19_B14_0_Pos) /*!< LCD PAL19: B14_0 Mask */\r
-#define LCD_PAL19_I1_Pos 31 /*!< LCD PAL19: I1 Position */\r
-#define LCD_PAL19_I1_Msk (0x01UL << LCD_PAL19_I1_Pos) /*!< LCD PAL19: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL20 -------------------------------------------\r
-#define LCD_PAL20_R04_0_Pos 0 /*!< LCD PAL20: R04_0 Position */\r
-#define LCD_PAL20_R04_0_Msk (0x1fUL << LCD_PAL20_R04_0_Pos) /*!< LCD PAL20: R04_0 Mask */\r
-#define LCD_PAL20_G04_0_Pos 5 /*!< LCD PAL20: G04_0 Position */\r
-#define LCD_PAL20_G04_0_Msk (0x1fUL << LCD_PAL20_G04_0_Pos) /*!< LCD PAL20: G04_0 Mask */\r
-#define LCD_PAL20_B04_0_Pos 10 /*!< LCD PAL20: B04_0 Position */\r
-#define LCD_PAL20_B04_0_Msk (0x1fUL << LCD_PAL20_B04_0_Pos) /*!< LCD PAL20: B04_0 Mask */\r
-#define LCD_PAL20_I0_Pos 15 /*!< LCD PAL20: I0 Position */\r
-#define LCD_PAL20_I0_Msk (0x01UL << LCD_PAL20_I0_Pos) /*!< LCD PAL20: I0 Mask */\r
-#define LCD_PAL20_R14_0_Pos 16 /*!< LCD PAL20: R14_0 Position */\r
-#define LCD_PAL20_R14_0_Msk (0x1fUL << LCD_PAL20_R14_0_Pos) /*!< LCD PAL20: R14_0 Mask */\r
-#define LCD_PAL20_G14_0_Pos 21 /*!< LCD PAL20: G14_0 Position */\r
-#define LCD_PAL20_G14_0_Msk (0x1fUL << LCD_PAL20_G14_0_Pos) /*!< LCD PAL20: G14_0 Mask */\r
-#define LCD_PAL20_B14_0_Pos 26 /*!< LCD PAL20: B14_0 Position */\r
-#define LCD_PAL20_B14_0_Msk (0x1fUL << LCD_PAL20_B14_0_Pos) /*!< LCD PAL20: B14_0 Mask */\r
-#define LCD_PAL20_I1_Pos 31 /*!< LCD PAL20: I1 Position */\r
-#define LCD_PAL20_I1_Msk (0x01UL << LCD_PAL20_I1_Pos) /*!< LCD PAL20: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL21 -------------------------------------------\r
-#define LCD_PAL21_R04_0_Pos 0 /*!< LCD PAL21: R04_0 Position */\r
-#define LCD_PAL21_R04_0_Msk (0x1fUL << LCD_PAL21_R04_0_Pos) /*!< LCD PAL21: R04_0 Mask */\r
-#define LCD_PAL21_G04_0_Pos 5 /*!< LCD PAL21: G04_0 Position */\r
-#define LCD_PAL21_G04_0_Msk (0x1fUL << LCD_PAL21_G04_0_Pos) /*!< LCD PAL21: G04_0 Mask */\r
-#define LCD_PAL21_B04_0_Pos 10 /*!< LCD PAL21: B04_0 Position */\r
-#define LCD_PAL21_B04_0_Msk (0x1fUL << LCD_PAL21_B04_0_Pos) /*!< LCD PAL21: B04_0 Mask */\r
-#define LCD_PAL21_I0_Pos 15 /*!< LCD PAL21: I0 Position */\r
-#define LCD_PAL21_I0_Msk (0x01UL << LCD_PAL21_I0_Pos) /*!< LCD PAL21: I0 Mask */\r
-#define LCD_PAL21_R14_0_Pos 16 /*!< LCD PAL21: R14_0 Position */\r
-#define LCD_PAL21_R14_0_Msk (0x1fUL << LCD_PAL21_R14_0_Pos) /*!< LCD PAL21: R14_0 Mask */\r
-#define LCD_PAL21_G14_0_Pos 21 /*!< LCD PAL21: G14_0 Position */\r
-#define LCD_PAL21_G14_0_Msk (0x1fUL << LCD_PAL21_G14_0_Pos) /*!< LCD PAL21: G14_0 Mask */\r
-#define LCD_PAL21_B14_0_Pos 26 /*!< LCD PAL21: B14_0 Position */\r
-#define LCD_PAL21_B14_0_Msk (0x1fUL << LCD_PAL21_B14_0_Pos) /*!< LCD PAL21: B14_0 Mask */\r
-#define LCD_PAL21_I1_Pos 31 /*!< LCD PAL21: I1 Position */\r
-#define LCD_PAL21_I1_Msk (0x01UL << LCD_PAL21_I1_Pos) /*!< LCD PAL21: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL22 -------------------------------------------\r
-#define LCD_PAL22_R04_0_Pos 0 /*!< LCD PAL22: R04_0 Position */\r
-#define LCD_PAL22_R04_0_Msk (0x1fUL << LCD_PAL22_R04_0_Pos) /*!< LCD PAL22: R04_0 Mask */\r
-#define LCD_PAL22_G04_0_Pos 5 /*!< LCD PAL22: G04_0 Position */\r
-#define LCD_PAL22_G04_0_Msk (0x1fUL << LCD_PAL22_G04_0_Pos) /*!< LCD PAL22: G04_0 Mask */\r
-#define LCD_PAL22_B04_0_Pos 10 /*!< LCD PAL22: B04_0 Position */\r
-#define LCD_PAL22_B04_0_Msk (0x1fUL << LCD_PAL22_B04_0_Pos) /*!< LCD PAL22: B04_0 Mask */\r
-#define LCD_PAL22_I0_Pos 15 /*!< LCD PAL22: I0 Position */\r
-#define LCD_PAL22_I0_Msk (0x01UL << LCD_PAL22_I0_Pos) /*!< LCD PAL22: I0 Mask */\r
-#define LCD_PAL22_R14_0_Pos 16 /*!< LCD PAL22: R14_0 Position */\r
-#define LCD_PAL22_R14_0_Msk (0x1fUL << LCD_PAL22_R14_0_Pos) /*!< LCD PAL22: R14_0 Mask */\r
-#define LCD_PAL22_G14_0_Pos 21 /*!< LCD PAL22: G14_0 Position */\r
-#define LCD_PAL22_G14_0_Msk (0x1fUL << LCD_PAL22_G14_0_Pos) /*!< LCD PAL22: G14_0 Mask */\r
-#define LCD_PAL22_B14_0_Pos 26 /*!< LCD PAL22: B14_0 Position */\r
-#define LCD_PAL22_B14_0_Msk (0x1fUL << LCD_PAL22_B14_0_Pos) /*!< LCD PAL22: B14_0 Mask */\r
-#define LCD_PAL22_I1_Pos 31 /*!< LCD PAL22: I1 Position */\r
-#define LCD_PAL22_I1_Msk (0x01UL << LCD_PAL22_I1_Pos) /*!< LCD PAL22: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL23 -------------------------------------------\r
-#define LCD_PAL23_R04_0_Pos 0 /*!< LCD PAL23: R04_0 Position */\r
-#define LCD_PAL23_R04_0_Msk (0x1fUL << LCD_PAL23_R04_0_Pos) /*!< LCD PAL23: R04_0 Mask */\r
-#define LCD_PAL23_G04_0_Pos 5 /*!< LCD PAL23: G04_0 Position */\r
-#define LCD_PAL23_G04_0_Msk (0x1fUL << LCD_PAL23_G04_0_Pos) /*!< LCD PAL23: G04_0 Mask */\r
-#define LCD_PAL23_B04_0_Pos 10 /*!< LCD PAL23: B04_0 Position */\r
-#define LCD_PAL23_B04_0_Msk (0x1fUL << LCD_PAL23_B04_0_Pos) /*!< LCD PAL23: B04_0 Mask */\r
-#define LCD_PAL23_I0_Pos 15 /*!< LCD PAL23: I0 Position */\r
-#define LCD_PAL23_I0_Msk (0x01UL << LCD_PAL23_I0_Pos) /*!< LCD PAL23: I0 Mask */\r
-#define LCD_PAL23_R14_0_Pos 16 /*!< LCD PAL23: R14_0 Position */\r
-#define LCD_PAL23_R14_0_Msk (0x1fUL << LCD_PAL23_R14_0_Pos) /*!< LCD PAL23: R14_0 Mask */\r
-#define LCD_PAL23_G14_0_Pos 21 /*!< LCD PAL23: G14_0 Position */\r
-#define LCD_PAL23_G14_0_Msk (0x1fUL << LCD_PAL23_G14_0_Pos) /*!< LCD PAL23: G14_0 Mask */\r
-#define LCD_PAL23_B14_0_Pos 26 /*!< LCD PAL23: B14_0 Position */\r
-#define LCD_PAL23_B14_0_Msk (0x1fUL << LCD_PAL23_B14_0_Pos) /*!< LCD PAL23: B14_0 Mask */\r
-#define LCD_PAL23_I1_Pos 31 /*!< LCD PAL23: I1 Position */\r
-#define LCD_PAL23_I1_Msk (0x01UL << LCD_PAL23_I1_Pos) /*!< LCD PAL23: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL24 -------------------------------------------\r
-#define LCD_PAL24_R04_0_Pos 0 /*!< LCD PAL24: R04_0 Position */\r
-#define LCD_PAL24_R04_0_Msk (0x1fUL << LCD_PAL24_R04_0_Pos) /*!< LCD PAL24: R04_0 Mask */\r
-#define LCD_PAL24_G04_0_Pos 5 /*!< LCD PAL24: G04_0 Position */\r
-#define LCD_PAL24_G04_0_Msk (0x1fUL << LCD_PAL24_G04_0_Pos) /*!< LCD PAL24: G04_0 Mask */\r
-#define LCD_PAL24_B04_0_Pos 10 /*!< LCD PAL24: B04_0 Position */\r
-#define LCD_PAL24_B04_0_Msk (0x1fUL << LCD_PAL24_B04_0_Pos) /*!< LCD PAL24: B04_0 Mask */\r
-#define LCD_PAL24_I0_Pos 15 /*!< LCD PAL24: I0 Position */\r
-#define LCD_PAL24_I0_Msk (0x01UL << LCD_PAL24_I0_Pos) /*!< LCD PAL24: I0 Mask */\r
-#define LCD_PAL24_R14_0_Pos 16 /*!< LCD PAL24: R14_0 Position */\r
-#define LCD_PAL24_R14_0_Msk (0x1fUL << LCD_PAL24_R14_0_Pos) /*!< LCD PAL24: R14_0 Mask */\r
-#define LCD_PAL24_G14_0_Pos 21 /*!< LCD PAL24: G14_0 Position */\r
-#define LCD_PAL24_G14_0_Msk (0x1fUL << LCD_PAL24_G14_0_Pos) /*!< LCD PAL24: G14_0 Mask */\r
-#define LCD_PAL24_B14_0_Pos 26 /*!< LCD PAL24: B14_0 Position */\r
-#define LCD_PAL24_B14_0_Msk (0x1fUL << LCD_PAL24_B14_0_Pos) /*!< LCD PAL24: B14_0 Mask */\r
-#define LCD_PAL24_I1_Pos 31 /*!< LCD PAL24: I1 Position */\r
-#define LCD_PAL24_I1_Msk (0x01UL << LCD_PAL24_I1_Pos) /*!< LCD PAL24: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL25 -------------------------------------------\r
-#define LCD_PAL25_R04_0_Pos 0 /*!< LCD PAL25: R04_0 Position */\r
-#define LCD_PAL25_R04_0_Msk (0x1fUL << LCD_PAL25_R04_0_Pos) /*!< LCD PAL25: R04_0 Mask */\r
-#define LCD_PAL25_G04_0_Pos 5 /*!< LCD PAL25: G04_0 Position */\r
-#define LCD_PAL25_G04_0_Msk (0x1fUL << LCD_PAL25_G04_0_Pos) /*!< LCD PAL25: G04_0 Mask */\r
-#define LCD_PAL25_B04_0_Pos 10 /*!< LCD PAL25: B04_0 Position */\r
-#define LCD_PAL25_B04_0_Msk (0x1fUL << LCD_PAL25_B04_0_Pos) /*!< LCD PAL25: B04_0 Mask */\r
-#define LCD_PAL25_I0_Pos 15 /*!< LCD PAL25: I0 Position */\r
-#define LCD_PAL25_I0_Msk (0x01UL << LCD_PAL25_I0_Pos) /*!< LCD PAL25: I0 Mask */\r
-#define LCD_PAL25_R14_0_Pos 16 /*!< LCD PAL25: R14_0 Position */\r
-#define LCD_PAL25_R14_0_Msk (0x1fUL << LCD_PAL25_R14_0_Pos) /*!< LCD PAL25: R14_0 Mask */\r
-#define LCD_PAL25_G14_0_Pos 21 /*!< LCD PAL25: G14_0 Position */\r
-#define LCD_PAL25_G14_0_Msk (0x1fUL << LCD_PAL25_G14_0_Pos) /*!< LCD PAL25: G14_0 Mask */\r
-#define LCD_PAL25_B14_0_Pos 26 /*!< LCD PAL25: B14_0 Position */\r
-#define LCD_PAL25_B14_0_Msk (0x1fUL << LCD_PAL25_B14_0_Pos) /*!< LCD PAL25: B14_0 Mask */\r
-#define LCD_PAL25_I1_Pos 31 /*!< LCD PAL25: I1 Position */\r
-#define LCD_PAL25_I1_Msk (0x01UL << LCD_PAL25_I1_Pos) /*!< LCD PAL25: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL26 -------------------------------------------\r
-#define LCD_PAL26_R04_0_Pos 0 /*!< LCD PAL26: R04_0 Position */\r
-#define LCD_PAL26_R04_0_Msk (0x1fUL << LCD_PAL26_R04_0_Pos) /*!< LCD PAL26: R04_0 Mask */\r
-#define LCD_PAL26_G04_0_Pos 5 /*!< LCD PAL26: G04_0 Position */\r
-#define LCD_PAL26_G04_0_Msk (0x1fUL << LCD_PAL26_G04_0_Pos) /*!< LCD PAL26: G04_0 Mask */\r
-#define LCD_PAL26_B04_0_Pos 10 /*!< LCD PAL26: B04_0 Position */\r
-#define LCD_PAL26_B04_0_Msk (0x1fUL << LCD_PAL26_B04_0_Pos) /*!< LCD PAL26: B04_0 Mask */\r
-#define LCD_PAL26_I0_Pos 15 /*!< LCD PAL26: I0 Position */\r
-#define LCD_PAL26_I0_Msk (0x01UL << LCD_PAL26_I0_Pos) /*!< LCD PAL26: I0 Mask */\r
-#define LCD_PAL26_R14_0_Pos 16 /*!< LCD PAL26: R14_0 Position */\r
-#define LCD_PAL26_R14_0_Msk (0x1fUL << LCD_PAL26_R14_0_Pos) /*!< LCD PAL26: R14_0 Mask */\r
-#define LCD_PAL26_G14_0_Pos 21 /*!< LCD PAL26: G14_0 Position */\r
-#define LCD_PAL26_G14_0_Msk (0x1fUL << LCD_PAL26_G14_0_Pos) /*!< LCD PAL26: G14_0 Mask */\r
-#define LCD_PAL26_B14_0_Pos 26 /*!< LCD PAL26: B14_0 Position */\r
-#define LCD_PAL26_B14_0_Msk (0x1fUL << LCD_PAL26_B14_0_Pos) /*!< LCD PAL26: B14_0 Mask */\r
-#define LCD_PAL26_I1_Pos 31 /*!< LCD PAL26: I1 Position */\r
-#define LCD_PAL26_I1_Msk (0x01UL << LCD_PAL26_I1_Pos) /*!< LCD PAL26: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL27 -------------------------------------------\r
-#define LCD_PAL27_R04_0_Pos 0 /*!< LCD PAL27: R04_0 Position */\r
-#define LCD_PAL27_R04_0_Msk (0x1fUL << LCD_PAL27_R04_0_Pos) /*!< LCD PAL27: R04_0 Mask */\r
-#define LCD_PAL27_G04_0_Pos 5 /*!< LCD PAL27: G04_0 Position */\r
-#define LCD_PAL27_G04_0_Msk (0x1fUL << LCD_PAL27_G04_0_Pos) /*!< LCD PAL27: G04_0 Mask */\r
-#define LCD_PAL27_B04_0_Pos 10 /*!< LCD PAL27: B04_0 Position */\r
-#define LCD_PAL27_B04_0_Msk (0x1fUL << LCD_PAL27_B04_0_Pos) /*!< LCD PAL27: B04_0 Mask */\r
-#define LCD_PAL27_I0_Pos 15 /*!< LCD PAL27: I0 Position */\r
-#define LCD_PAL27_I0_Msk (0x01UL << LCD_PAL27_I0_Pos) /*!< LCD PAL27: I0 Mask */\r
-#define LCD_PAL27_R14_0_Pos 16 /*!< LCD PAL27: R14_0 Position */\r
-#define LCD_PAL27_R14_0_Msk (0x1fUL << LCD_PAL27_R14_0_Pos) /*!< LCD PAL27: R14_0 Mask */\r
-#define LCD_PAL27_G14_0_Pos 21 /*!< LCD PAL27: G14_0 Position */\r
-#define LCD_PAL27_G14_0_Msk (0x1fUL << LCD_PAL27_G14_0_Pos) /*!< LCD PAL27: G14_0 Mask */\r
-#define LCD_PAL27_B14_0_Pos 26 /*!< LCD PAL27: B14_0 Position */\r
-#define LCD_PAL27_B14_0_Msk (0x1fUL << LCD_PAL27_B14_0_Pos) /*!< LCD PAL27: B14_0 Mask */\r
-#define LCD_PAL27_I1_Pos 31 /*!< LCD PAL27: I1 Position */\r
-#define LCD_PAL27_I1_Msk (0x01UL << LCD_PAL27_I1_Pos) /*!< LCD PAL27: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL28 -------------------------------------------\r
-#define LCD_PAL28_R04_0_Pos 0 /*!< LCD PAL28: R04_0 Position */\r
-#define LCD_PAL28_R04_0_Msk (0x1fUL << LCD_PAL28_R04_0_Pos) /*!< LCD PAL28: R04_0 Mask */\r
-#define LCD_PAL28_G04_0_Pos 5 /*!< LCD PAL28: G04_0 Position */\r
-#define LCD_PAL28_G04_0_Msk (0x1fUL << LCD_PAL28_G04_0_Pos) /*!< LCD PAL28: G04_0 Mask */\r
-#define LCD_PAL28_B04_0_Pos 10 /*!< LCD PAL28: B04_0 Position */\r
-#define LCD_PAL28_B04_0_Msk (0x1fUL << LCD_PAL28_B04_0_Pos) /*!< LCD PAL28: B04_0 Mask */\r
-#define LCD_PAL28_I0_Pos 15 /*!< LCD PAL28: I0 Position */\r
-#define LCD_PAL28_I0_Msk (0x01UL << LCD_PAL28_I0_Pos) /*!< LCD PAL28: I0 Mask */\r
-#define LCD_PAL28_R14_0_Pos 16 /*!< LCD PAL28: R14_0 Position */\r
-#define LCD_PAL28_R14_0_Msk (0x1fUL << LCD_PAL28_R14_0_Pos) /*!< LCD PAL28: R14_0 Mask */\r
-#define LCD_PAL28_G14_0_Pos 21 /*!< LCD PAL28: G14_0 Position */\r
-#define LCD_PAL28_G14_0_Msk (0x1fUL << LCD_PAL28_G14_0_Pos) /*!< LCD PAL28: G14_0 Mask */\r
-#define LCD_PAL28_B14_0_Pos 26 /*!< LCD PAL28: B14_0 Position */\r
-#define LCD_PAL28_B14_0_Msk (0x1fUL << LCD_PAL28_B14_0_Pos) /*!< LCD PAL28: B14_0 Mask */\r
-#define LCD_PAL28_I1_Pos 31 /*!< LCD PAL28: I1 Position */\r
-#define LCD_PAL28_I1_Msk (0x01UL << LCD_PAL28_I1_Pos) /*!< LCD PAL28: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL29 -------------------------------------------\r
-#define LCD_PAL29_R04_0_Pos 0 /*!< LCD PAL29: R04_0 Position */\r
-#define LCD_PAL29_R04_0_Msk (0x1fUL << LCD_PAL29_R04_0_Pos) /*!< LCD PAL29: R04_0 Mask */\r
-#define LCD_PAL29_G04_0_Pos 5 /*!< LCD PAL29: G04_0 Position */\r
-#define LCD_PAL29_G04_0_Msk (0x1fUL << LCD_PAL29_G04_0_Pos) /*!< LCD PAL29: G04_0 Mask */\r
-#define LCD_PAL29_B04_0_Pos 10 /*!< LCD PAL29: B04_0 Position */\r
-#define LCD_PAL29_B04_0_Msk (0x1fUL << LCD_PAL29_B04_0_Pos) /*!< LCD PAL29: B04_0 Mask */\r
-#define LCD_PAL29_I0_Pos 15 /*!< LCD PAL29: I0 Position */\r
-#define LCD_PAL29_I0_Msk (0x01UL << LCD_PAL29_I0_Pos) /*!< LCD PAL29: I0 Mask */\r
-#define LCD_PAL29_R14_0_Pos 16 /*!< LCD PAL29: R14_0 Position */\r
-#define LCD_PAL29_R14_0_Msk (0x1fUL << LCD_PAL29_R14_0_Pos) /*!< LCD PAL29: R14_0 Mask */\r
-#define LCD_PAL29_G14_0_Pos 21 /*!< LCD PAL29: G14_0 Position */\r
-#define LCD_PAL29_G14_0_Msk (0x1fUL << LCD_PAL29_G14_0_Pos) /*!< LCD PAL29: G14_0 Mask */\r
-#define LCD_PAL29_B14_0_Pos 26 /*!< LCD PAL29: B14_0 Position */\r
-#define LCD_PAL29_B14_0_Msk (0x1fUL << LCD_PAL29_B14_0_Pos) /*!< LCD PAL29: B14_0 Mask */\r
-#define LCD_PAL29_I1_Pos 31 /*!< LCD PAL29: I1 Position */\r
-#define LCD_PAL29_I1_Msk (0x01UL << LCD_PAL29_I1_Pos) /*!< LCD PAL29: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL30 -------------------------------------------\r
-#define LCD_PAL30_R04_0_Pos 0 /*!< LCD PAL30: R04_0 Position */\r
-#define LCD_PAL30_R04_0_Msk (0x1fUL << LCD_PAL30_R04_0_Pos) /*!< LCD PAL30: R04_0 Mask */\r
-#define LCD_PAL30_G04_0_Pos 5 /*!< LCD PAL30: G04_0 Position */\r
-#define LCD_PAL30_G04_0_Msk (0x1fUL << LCD_PAL30_G04_0_Pos) /*!< LCD PAL30: G04_0 Mask */\r
-#define LCD_PAL30_B04_0_Pos 10 /*!< LCD PAL30: B04_0 Position */\r
-#define LCD_PAL30_B04_0_Msk (0x1fUL << LCD_PAL30_B04_0_Pos) /*!< LCD PAL30: B04_0 Mask */\r
-#define LCD_PAL30_I0_Pos 15 /*!< LCD PAL30: I0 Position */\r
-#define LCD_PAL30_I0_Msk (0x01UL << LCD_PAL30_I0_Pos) /*!< LCD PAL30: I0 Mask */\r
-#define LCD_PAL30_R14_0_Pos 16 /*!< LCD PAL30: R14_0 Position */\r
-#define LCD_PAL30_R14_0_Msk (0x1fUL << LCD_PAL30_R14_0_Pos) /*!< LCD PAL30: R14_0 Mask */\r
-#define LCD_PAL30_G14_0_Pos 21 /*!< LCD PAL30: G14_0 Position */\r
-#define LCD_PAL30_G14_0_Msk (0x1fUL << LCD_PAL30_G14_0_Pos) /*!< LCD PAL30: G14_0 Mask */\r
-#define LCD_PAL30_B14_0_Pos 26 /*!< LCD PAL30: B14_0 Position */\r
-#define LCD_PAL30_B14_0_Msk (0x1fUL << LCD_PAL30_B14_0_Pos) /*!< LCD PAL30: B14_0 Mask */\r
-#define LCD_PAL30_I1_Pos 31 /*!< LCD PAL30: I1 Position */\r
-#define LCD_PAL30_I1_Msk (0x01UL << LCD_PAL30_I1_Pos) /*!< LCD PAL30: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL31 -------------------------------------------\r
-#define LCD_PAL31_R04_0_Pos 0 /*!< LCD PAL31: R04_0 Position */\r
-#define LCD_PAL31_R04_0_Msk (0x1fUL << LCD_PAL31_R04_0_Pos) /*!< LCD PAL31: R04_0 Mask */\r
-#define LCD_PAL31_G04_0_Pos 5 /*!< LCD PAL31: G04_0 Position */\r
-#define LCD_PAL31_G04_0_Msk (0x1fUL << LCD_PAL31_G04_0_Pos) /*!< LCD PAL31: G04_0 Mask */\r
-#define LCD_PAL31_B04_0_Pos 10 /*!< LCD PAL31: B04_0 Position */\r
-#define LCD_PAL31_B04_0_Msk (0x1fUL << LCD_PAL31_B04_0_Pos) /*!< LCD PAL31: B04_0 Mask */\r
-#define LCD_PAL31_I0_Pos 15 /*!< LCD PAL31: I0 Position */\r
-#define LCD_PAL31_I0_Msk (0x01UL << LCD_PAL31_I0_Pos) /*!< LCD PAL31: I0 Mask */\r
-#define LCD_PAL31_R14_0_Pos 16 /*!< LCD PAL31: R14_0 Position */\r
-#define LCD_PAL31_R14_0_Msk (0x1fUL << LCD_PAL31_R14_0_Pos) /*!< LCD PAL31: R14_0 Mask */\r
-#define LCD_PAL31_G14_0_Pos 21 /*!< LCD PAL31: G14_0 Position */\r
-#define LCD_PAL31_G14_0_Msk (0x1fUL << LCD_PAL31_G14_0_Pos) /*!< LCD PAL31: G14_0 Mask */\r
-#define LCD_PAL31_B14_0_Pos 26 /*!< LCD PAL31: B14_0 Position */\r
-#define LCD_PAL31_B14_0_Msk (0x1fUL << LCD_PAL31_B14_0_Pos) /*!< LCD PAL31: B14_0 Mask */\r
-#define LCD_PAL31_I1_Pos 31 /*!< LCD PAL31: I1 Position */\r
-#define LCD_PAL31_I1_Msk (0x01UL << LCD_PAL31_I1_Pos) /*!< LCD PAL31: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL32 -------------------------------------------\r
-#define LCD_PAL32_R04_0_Pos 0 /*!< LCD PAL32: R04_0 Position */\r
-#define LCD_PAL32_R04_0_Msk (0x1fUL << LCD_PAL32_R04_0_Pos) /*!< LCD PAL32: R04_0 Mask */\r
-#define LCD_PAL32_G04_0_Pos 5 /*!< LCD PAL32: G04_0 Position */\r
-#define LCD_PAL32_G04_0_Msk (0x1fUL << LCD_PAL32_G04_0_Pos) /*!< LCD PAL32: G04_0 Mask */\r
-#define LCD_PAL32_B04_0_Pos 10 /*!< LCD PAL32: B04_0 Position */\r
-#define LCD_PAL32_B04_0_Msk (0x1fUL << LCD_PAL32_B04_0_Pos) /*!< LCD PAL32: B04_0 Mask */\r
-#define LCD_PAL32_I0_Pos 15 /*!< LCD PAL32: I0 Position */\r
-#define LCD_PAL32_I0_Msk (0x01UL << LCD_PAL32_I0_Pos) /*!< LCD PAL32: I0 Mask */\r
-#define LCD_PAL32_R14_0_Pos 16 /*!< LCD PAL32: R14_0 Position */\r
-#define LCD_PAL32_R14_0_Msk (0x1fUL << LCD_PAL32_R14_0_Pos) /*!< LCD PAL32: R14_0 Mask */\r
-#define LCD_PAL32_G14_0_Pos 21 /*!< LCD PAL32: G14_0 Position */\r
-#define LCD_PAL32_G14_0_Msk (0x1fUL << LCD_PAL32_G14_0_Pos) /*!< LCD PAL32: G14_0 Mask */\r
-#define LCD_PAL32_B14_0_Pos 26 /*!< LCD PAL32: B14_0 Position */\r
-#define LCD_PAL32_B14_0_Msk (0x1fUL << LCD_PAL32_B14_0_Pos) /*!< LCD PAL32: B14_0 Mask */\r
-#define LCD_PAL32_I1_Pos 31 /*!< LCD PAL32: I1 Position */\r
-#define LCD_PAL32_I1_Msk (0x01UL << LCD_PAL32_I1_Pos) /*!< LCD PAL32: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL33 -------------------------------------------\r
-#define LCD_PAL33_R04_0_Pos 0 /*!< LCD PAL33: R04_0 Position */\r
-#define LCD_PAL33_R04_0_Msk (0x1fUL << LCD_PAL33_R04_0_Pos) /*!< LCD PAL33: R04_0 Mask */\r
-#define LCD_PAL33_G04_0_Pos 5 /*!< LCD PAL33: G04_0 Position */\r
-#define LCD_PAL33_G04_0_Msk (0x1fUL << LCD_PAL33_G04_0_Pos) /*!< LCD PAL33: G04_0 Mask */\r
-#define LCD_PAL33_B04_0_Pos 10 /*!< LCD PAL33: B04_0 Position */\r
-#define LCD_PAL33_B04_0_Msk (0x1fUL << LCD_PAL33_B04_0_Pos) /*!< LCD PAL33: B04_0 Mask */\r
-#define LCD_PAL33_I0_Pos 15 /*!< LCD PAL33: I0 Position */\r
-#define LCD_PAL33_I0_Msk (0x01UL << LCD_PAL33_I0_Pos) /*!< LCD PAL33: I0 Mask */\r
-#define LCD_PAL33_R14_0_Pos 16 /*!< LCD PAL33: R14_0 Position */\r
-#define LCD_PAL33_R14_0_Msk (0x1fUL << LCD_PAL33_R14_0_Pos) /*!< LCD PAL33: R14_0 Mask */\r
-#define LCD_PAL33_G14_0_Pos 21 /*!< LCD PAL33: G14_0 Position */\r
-#define LCD_PAL33_G14_0_Msk (0x1fUL << LCD_PAL33_G14_0_Pos) /*!< LCD PAL33: G14_0 Mask */\r
-#define LCD_PAL33_B14_0_Pos 26 /*!< LCD PAL33: B14_0 Position */\r
-#define LCD_PAL33_B14_0_Msk (0x1fUL << LCD_PAL33_B14_0_Pos) /*!< LCD PAL33: B14_0 Mask */\r
-#define LCD_PAL33_I1_Pos 31 /*!< LCD PAL33: I1 Position */\r
-#define LCD_PAL33_I1_Msk (0x01UL << LCD_PAL33_I1_Pos) /*!< LCD PAL33: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL34 -------------------------------------------\r
-#define LCD_PAL34_R04_0_Pos 0 /*!< LCD PAL34: R04_0 Position */\r
-#define LCD_PAL34_R04_0_Msk (0x1fUL << LCD_PAL34_R04_0_Pos) /*!< LCD PAL34: R04_0 Mask */\r
-#define LCD_PAL34_G04_0_Pos 5 /*!< LCD PAL34: G04_0 Position */\r
-#define LCD_PAL34_G04_0_Msk (0x1fUL << LCD_PAL34_G04_0_Pos) /*!< LCD PAL34: G04_0 Mask */\r
-#define LCD_PAL34_B04_0_Pos 10 /*!< LCD PAL34: B04_0 Position */\r
-#define LCD_PAL34_B04_0_Msk (0x1fUL << LCD_PAL34_B04_0_Pos) /*!< LCD PAL34: B04_0 Mask */\r
-#define LCD_PAL34_I0_Pos 15 /*!< LCD PAL34: I0 Position */\r
-#define LCD_PAL34_I0_Msk (0x01UL << LCD_PAL34_I0_Pos) /*!< LCD PAL34: I0 Mask */\r
-#define LCD_PAL34_R14_0_Pos 16 /*!< LCD PAL34: R14_0 Position */\r
-#define LCD_PAL34_R14_0_Msk (0x1fUL << LCD_PAL34_R14_0_Pos) /*!< LCD PAL34: R14_0 Mask */\r
-#define LCD_PAL34_G14_0_Pos 21 /*!< LCD PAL34: G14_0 Position */\r
-#define LCD_PAL34_G14_0_Msk (0x1fUL << LCD_PAL34_G14_0_Pos) /*!< LCD PAL34: G14_0 Mask */\r
-#define LCD_PAL34_B14_0_Pos 26 /*!< LCD PAL34: B14_0 Position */\r
-#define LCD_PAL34_B14_0_Msk (0x1fUL << LCD_PAL34_B14_0_Pos) /*!< LCD PAL34: B14_0 Mask */\r
-#define LCD_PAL34_I1_Pos 31 /*!< LCD PAL34: I1 Position */\r
-#define LCD_PAL34_I1_Msk (0x01UL << LCD_PAL34_I1_Pos) /*!< LCD PAL34: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL35 -------------------------------------------\r
-#define LCD_PAL35_R04_0_Pos 0 /*!< LCD PAL35: R04_0 Position */\r
-#define LCD_PAL35_R04_0_Msk (0x1fUL << LCD_PAL35_R04_0_Pos) /*!< LCD PAL35: R04_0 Mask */\r
-#define LCD_PAL35_G04_0_Pos 5 /*!< LCD PAL35: G04_0 Position */\r
-#define LCD_PAL35_G04_0_Msk (0x1fUL << LCD_PAL35_G04_0_Pos) /*!< LCD PAL35: G04_0 Mask */\r
-#define LCD_PAL35_B04_0_Pos 10 /*!< LCD PAL35: B04_0 Position */\r
-#define LCD_PAL35_B04_0_Msk (0x1fUL << LCD_PAL35_B04_0_Pos) /*!< LCD PAL35: B04_0 Mask */\r
-#define LCD_PAL35_I0_Pos 15 /*!< LCD PAL35: I0 Position */\r
-#define LCD_PAL35_I0_Msk (0x01UL << LCD_PAL35_I0_Pos) /*!< LCD PAL35: I0 Mask */\r
-#define LCD_PAL35_R14_0_Pos 16 /*!< LCD PAL35: R14_0 Position */\r
-#define LCD_PAL35_R14_0_Msk (0x1fUL << LCD_PAL35_R14_0_Pos) /*!< LCD PAL35: R14_0 Mask */\r
-#define LCD_PAL35_G14_0_Pos 21 /*!< LCD PAL35: G14_0 Position */\r
-#define LCD_PAL35_G14_0_Msk (0x1fUL << LCD_PAL35_G14_0_Pos) /*!< LCD PAL35: G14_0 Mask */\r
-#define LCD_PAL35_B14_0_Pos 26 /*!< LCD PAL35: B14_0 Position */\r
-#define LCD_PAL35_B14_0_Msk (0x1fUL << LCD_PAL35_B14_0_Pos) /*!< LCD PAL35: B14_0 Mask */\r
-#define LCD_PAL35_I1_Pos 31 /*!< LCD PAL35: I1 Position */\r
-#define LCD_PAL35_I1_Msk (0x01UL << LCD_PAL35_I1_Pos) /*!< LCD PAL35: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL36 -------------------------------------------\r
-#define LCD_PAL36_R04_0_Pos 0 /*!< LCD PAL36: R04_0 Position */\r
-#define LCD_PAL36_R04_0_Msk (0x1fUL << LCD_PAL36_R04_0_Pos) /*!< LCD PAL36: R04_0 Mask */\r
-#define LCD_PAL36_G04_0_Pos 5 /*!< LCD PAL36: G04_0 Position */\r
-#define LCD_PAL36_G04_0_Msk (0x1fUL << LCD_PAL36_G04_0_Pos) /*!< LCD PAL36: G04_0 Mask */\r
-#define LCD_PAL36_B04_0_Pos 10 /*!< LCD PAL36: B04_0 Position */\r
-#define LCD_PAL36_B04_0_Msk (0x1fUL << LCD_PAL36_B04_0_Pos) /*!< LCD PAL36: B04_0 Mask */\r
-#define LCD_PAL36_I0_Pos 15 /*!< LCD PAL36: I0 Position */\r
-#define LCD_PAL36_I0_Msk (0x01UL << LCD_PAL36_I0_Pos) /*!< LCD PAL36: I0 Mask */\r
-#define LCD_PAL36_R14_0_Pos 16 /*!< LCD PAL36: R14_0 Position */\r
-#define LCD_PAL36_R14_0_Msk (0x1fUL << LCD_PAL36_R14_0_Pos) /*!< LCD PAL36: R14_0 Mask */\r
-#define LCD_PAL36_G14_0_Pos 21 /*!< LCD PAL36: G14_0 Position */\r
-#define LCD_PAL36_G14_0_Msk (0x1fUL << LCD_PAL36_G14_0_Pos) /*!< LCD PAL36: G14_0 Mask */\r
-#define LCD_PAL36_B14_0_Pos 26 /*!< LCD PAL36: B14_0 Position */\r
-#define LCD_PAL36_B14_0_Msk (0x1fUL << LCD_PAL36_B14_0_Pos) /*!< LCD PAL36: B14_0 Mask */\r
-#define LCD_PAL36_I1_Pos 31 /*!< LCD PAL36: I1 Position */\r
-#define LCD_PAL36_I1_Msk (0x01UL << LCD_PAL36_I1_Pos) /*!< LCD PAL36: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL37 -------------------------------------------\r
-#define LCD_PAL37_R04_0_Pos 0 /*!< LCD PAL37: R04_0 Position */\r
-#define LCD_PAL37_R04_0_Msk (0x1fUL << LCD_PAL37_R04_0_Pos) /*!< LCD PAL37: R04_0 Mask */\r
-#define LCD_PAL37_G04_0_Pos 5 /*!< LCD PAL37: G04_0 Position */\r
-#define LCD_PAL37_G04_0_Msk (0x1fUL << LCD_PAL37_G04_0_Pos) /*!< LCD PAL37: G04_0 Mask */\r
-#define LCD_PAL37_B04_0_Pos 10 /*!< LCD PAL37: B04_0 Position */\r
-#define LCD_PAL37_B04_0_Msk (0x1fUL << LCD_PAL37_B04_0_Pos) /*!< LCD PAL37: B04_0 Mask */\r
-#define LCD_PAL37_I0_Pos 15 /*!< LCD PAL37: I0 Position */\r
-#define LCD_PAL37_I0_Msk (0x01UL << LCD_PAL37_I0_Pos) /*!< LCD PAL37: I0 Mask */\r
-#define LCD_PAL37_R14_0_Pos 16 /*!< LCD PAL37: R14_0 Position */\r
-#define LCD_PAL37_R14_0_Msk (0x1fUL << LCD_PAL37_R14_0_Pos) /*!< LCD PAL37: R14_0 Mask */\r
-#define LCD_PAL37_G14_0_Pos 21 /*!< LCD PAL37: G14_0 Position */\r
-#define LCD_PAL37_G14_0_Msk (0x1fUL << LCD_PAL37_G14_0_Pos) /*!< LCD PAL37: G14_0 Mask */\r
-#define LCD_PAL37_B14_0_Pos 26 /*!< LCD PAL37: B14_0 Position */\r
-#define LCD_PAL37_B14_0_Msk (0x1fUL << LCD_PAL37_B14_0_Pos) /*!< LCD PAL37: B14_0 Mask */\r
-#define LCD_PAL37_I1_Pos 31 /*!< LCD PAL37: I1 Position */\r
-#define LCD_PAL37_I1_Msk (0x01UL << LCD_PAL37_I1_Pos) /*!< LCD PAL37: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL38 -------------------------------------------\r
-#define LCD_PAL38_R04_0_Pos 0 /*!< LCD PAL38: R04_0 Position */\r
-#define LCD_PAL38_R04_0_Msk (0x1fUL << LCD_PAL38_R04_0_Pos) /*!< LCD PAL38: R04_0 Mask */\r
-#define LCD_PAL38_G04_0_Pos 5 /*!< LCD PAL38: G04_0 Position */\r
-#define LCD_PAL38_G04_0_Msk (0x1fUL << LCD_PAL38_G04_0_Pos) /*!< LCD PAL38: G04_0 Mask */\r
-#define LCD_PAL38_B04_0_Pos 10 /*!< LCD PAL38: B04_0 Position */\r
-#define LCD_PAL38_B04_0_Msk (0x1fUL << LCD_PAL38_B04_0_Pos) /*!< LCD PAL38: B04_0 Mask */\r
-#define LCD_PAL38_I0_Pos 15 /*!< LCD PAL38: I0 Position */\r
-#define LCD_PAL38_I0_Msk (0x01UL << LCD_PAL38_I0_Pos) /*!< LCD PAL38: I0 Mask */\r
-#define LCD_PAL38_R14_0_Pos 16 /*!< LCD PAL38: R14_0 Position */\r
-#define LCD_PAL38_R14_0_Msk (0x1fUL << LCD_PAL38_R14_0_Pos) /*!< LCD PAL38: R14_0 Mask */\r
-#define LCD_PAL38_G14_0_Pos 21 /*!< LCD PAL38: G14_0 Position */\r
-#define LCD_PAL38_G14_0_Msk (0x1fUL << LCD_PAL38_G14_0_Pos) /*!< LCD PAL38: G14_0 Mask */\r
-#define LCD_PAL38_B14_0_Pos 26 /*!< LCD PAL38: B14_0 Position */\r
-#define LCD_PAL38_B14_0_Msk (0x1fUL << LCD_PAL38_B14_0_Pos) /*!< LCD PAL38: B14_0 Mask */\r
-#define LCD_PAL38_I1_Pos 31 /*!< LCD PAL38: I1 Position */\r
-#define LCD_PAL38_I1_Msk (0x01UL << LCD_PAL38_I1_Pos) /*!< LCD PAL38: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL39 -------------------------------------------\r
-#define LCD_PAL39_R04_0_Pos 0 /*!< LCD PAL39: R04_0 Position */\r
-#define LCD_PAL39_R04_0_Msk (0x1fUL << LCD_PAL39_R04_0_Pos) /*!< LCD PAL39: R04_0 Mask */\r
-#define LCD_PAL39_G04_0_Pos 5 /*!< LCD PAL39: G04_0 Position */\r
-#define LCD_PAL39_G04_0_Msk (0x1fUL << LCD_PAL39_G04_0_Pos) /*!< LCD PAL39: G04_0 Mask */\r
-#define LCD_PAL39_B04_0_Pos 10 /*!< LCD PAL39: B04_0 Position */\r
-#define LCD_PAL39_B04_0_Msk (0x1fUL << LCD_PAL39_B04_0_Pos) /*!< LCD PAL39: B04_0 Mask */\r
-#define LCD_PAL39_I0_Pos 15 /*!< LCD PAL39: I0 Position */\r
-#define LCD_PAL39_I0_Msk (0x01UL << LCD_PAL39_I0_Pos) /*!< LCD PAL39: I0 Mask */\r
-#define LCD_PAL39_R14_0_Pos 16 /*!< LCD PAL39: R14_0 Position */\r
-#define LCD_PAL39_R14_0_Msk (0x1fUL << LCD_PAL39_R14_0_Pos) /*!< LCD PAL39: R14_0 Mask */\r
-#define LCD_PAL39_G14_0_Pos 21 /*!< LCD PAL39: G14_0 Position */\r
-#define LCD_PAL39_G14_0_Msk (0x1fUL << LCD_PAL39_G14_0_Pos) /*!< LCD PAL39: G14_0 Mask */\r
-#define LCD_PAL39_B14_0_Pos 26 /*!< LCD PAL39: B14_0 Position */\r
-#define LCD_PAL39_B14_0_Msk (0x1fUL << LCD_PAL39_B14_0_Pos) /*!< LCD PAL39: B14_0 Mask */\r
-#define LCD_PAL39_I1_Pos 31 /*!< LCD PAL39: I1 Position */\r
-#define LCD_PAL39_I1_Msk (0x01UL << LCD_PAL39_I1_Pos) /*!< LCD PAL39: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL40 -------------------------------------------\r
-#define LCD_PAL40_R04_0_Pos 0 /*!< LCD PAL40: R04_0 Position */\r
-#define LCD_PAL40_R04_0_Msk (0x1fUL << LCD_PAL40_R04_0_Pos) /*!< LCD PAL40: R04_0 Mask */\r
-#define LCD_PAL40_G04_0_Pos 5 /*!< LCD PAL40: G04_0 Position */\r
-#define LCD_PAL40_G04_0_Msk (0x1fUL << LCD_PAL40_G04_0_Pos) /*!< LCD PAL40: G04_0 Mask */\r
-#define LCD_PAL40_B04_0_Pos 10 /*!< LCD PAL40: B04_0 Position */\r
-#define LCD_PAL40_B04_0_Msk (0x1fUL << LCD_PAL40_B04_0_Pos) /*!< LCD PAL40: B04_0 Mask */\r
-#define LCD_PAL40_I0_Pos 15 /*!< LCD PAL40: I0 Position */\r
-#define LCD_PAL40_I0_Msk (0x01UL << LCD_PAL40_I0_Pos) /*!< LCD PAL40: I0 Mask */\r
-#define LCD_PAL40_R14_0_Pos 16 /*!< LCD PAL40: R14_0 Position */\r
-#define LCD_PAL40_R14_0_Msk (0x1fUL << LCD_PAL40_R14_0_Pos) /*!< LCD PAL40: R14_0 Mask */\r
-#define LCD_PAL40_G14_0_Pos 21 /*!< LCD PAL40: G14_0 Position */\r
-#define LCD_PAL40_G14_0_Msk (0x1fUL << LCD_PAL40_G14_0_Pos) /*!< LCD PAL40: G14_0 Mask */\r
-#define LCD_PAL40_B14_0_Pos 26 /*!< LCD PAL40: B14_0 Position */\r
-#define LCD_PAL40_B14_0_Msk (0x1fUL << LCD_PAL40_B14_0_Pos) /*!< LCD PAL40: B14_0 Mask */\r
-#define LCD_PAL40_I1_Pos 31 /*!< LCD PAL40: I1 Position */\r
-#define LCD_PAL40_I1_Msk (0x01UL << LCD_PAL40_I1_Pos) /*!< LCD PAL40: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL41 -------------------------------------------\r
-#define LCD_PAL41_R04_0_Pos 0 /*!< LCD PAL41: R04_0 Position */\r
-#define LCD_PAL41_R04_0_Msk (0x1fUL << LCD_PAL41_R04_0_Pos) /*!< LCD PAL41: R04_0 Mask */\r
-#define LCD_PAL41_G04_0_Pos 5 /*!< LCD PAL41: G04_0 Position */\r
-#define LCD_PAL41_G04_0_Msk (0x1fUL << LCD_PAL41_G04_0_Pos) /*!< LCD PAL41: G04_0 Mask */\r
-#define LCD_PAL41_B04_0_Pos 10 /*!< LCD PAL41: B04_0 Position */\r
-#define LCD_PAL41_B04_0_Msk (0x1fUL << LCD_PAL41_B04_0_Pos) /*!< LCD PAL41: B04_0 Mask */\r
-#define LCD_PAL41_I0_Pos 15 /*!< LCD PAL41: I0 Position */\r
-#define LCD_PAL41_I0_Msk (0x01UL << LCD_PAL41_I0_Pos) /*!< LCD PAL41: I0 Mask */\r
-#define LCD_PAL41_R14_0_Pos 16 /*!< LCD PAL41: R14_0 Position */\r
-#define LCD_PAL41_R14_0_Msk (0x1fUL << LCD_PAL41_R14_0_Pos) /*!< LCD PAL41: R14_0 Mask */\r
-#define LCD_PAL41_G14_0_Pos 21 /*!< LCD PAL41: G14_0 Position */\r
-#define LCD_PAL41_G14_0_Msk (0x1fUL << LCD_PAL41_G14_0_Pos) /*!< LCD PAL41: G14_0 Mask */\r
-#define LCD_PAL41_B14_0_Pos 26 /*!< LCD PAL41: B14_0 Position */\r
-#define LCD_PAL41_B14_0_Msk (0x1fUL << LCD_PAL41_B14_0_Pos) /*!< LCD PAL41: B14_0 Mask */\r
-#define LCD_PAL41_I1_Pos 31 /*!< LCD PAL41: I1 Position */\r
-#define LCD_PAL41_I1_Msk (0x01UL << LCD_PAL41_I1_Pos) /*!< LCD PAL41: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL42 -------------------------------------------\r
-#define LCD_PAL42_R04_0_Pos 0 /*!< LCD PAL42: R04_0 Position */\r
-#define LCD_PAL42_R04_0_Msk (0x1fUL << LCD_PAL42_R04_0_Pos) /*!< LCD PAL42: R04_0 Mask */\r
-#define LCD_PAL42_G04_0_Pos 5 /*!< LCD PAL42: G04_0 Position */\r
-#define LCD_PAL42_G04_0_Msk (0x1fUL << LCD_PAL42_G04_0_Pos) /*!< LCD PAL42: G04_0 Mask */\r
-#define LCD_PAL42_B04_0_Pos 10 /*!< LCD PAL42: B04_0 Position */\r
-#define LCD_PAL42_B04_0_Msk (0x1fUL << LCD_PAL42_B04_0_Pos) /*!< LCD PAL42: B04_0 Mask */\r
-#define LCD_PAL42_I0_Pos 15 /*!< LCD PAL42: I0 Position */\r
-#define LCD_PAL42_I0_Msk (0x01UL << LCD_PAL42_I0_Pos) /*!< LCD PAL42: I0 Mask */\r
-#define LCD_PAL42_R14_0_Pos 16 /*!< LCD PAL42: R14_0 Position */\r
-#define LCD_PAL42_R14_0_Msk (0x1fUL << LCD_PAL42_R14_0_Pos) /*!< LCD PAL42: R14_0 Mask */\r
-#define LCD_PAL42_G14_0_Pos 21 /*!< LCD PAL42: G14_0 Position */\r
-#define LCD_PAL42_G14_0_Msk (0x1fUL << LCD_PAL42_G14_0_Pos) /*!< LCD PAL42: G14_0 Mask */\r
-#define LCD_PAL42_B14_0_Pos 26 /*!< LCD PAL42: B14_0 Position */\r
-#define LCD_PAL42_B14_0_Msk (0x1fUL << LCD_PAL42_B14_0_Pos) /*!< LCD PAL42: B14_0 Mask */\r
-#define LCD_PAL42_I1_Pos 31 /*!< LCD PAL42: I1 Position */\r
-#define LCD_PAL42_I1_Msk (0x01UL << LCD_PAL42_I1_Pos) /*!< LCD PAL42: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL43 -------------------------------------------\r
-#define LCD_PAL43_R04_0_Pos 0 /*!< LCD PAL43: R04_0 Position */\r
-#define LCD_PAL43_R04_0_Msk (0x1fUL << LCD_PAL43_R04_0_Pos) /*!< LCD PAL43: R04_0 Mask */\r
-#define LCD_PAL43_G04_0_Pos 5 /*!< LCD PAL43: G04_0 Position */\r
-#define LCD_PAL43_G04_0_Msk (0x1fUL << LCD_PAL43_G04_0_Pos) /*!< LCD PAL43: G04_0 Mask */\r
-#define LCD_PAL43_B04_0_Pos 10 /*!< LCD PAL43: B04_0 Position */\r
-#define LCD_PAL43_B04_0_Msk (0x1fUL << LCD_PAL43_B04_0_Pos) /*!< LCD PAL43: B04_0 Mask */\r
-#define LCD_PAL43_I0_Pos 15 /*!< LCD PAL43: I0 Position */\r
-#define LCD_PAL43_I0_Msk (0x01UL << LCD_PAL43_I0_Pos) /*!< LCD PAL43: I0 Mask */\r
-#define LCD_PAL43_R14_0_Pos 16 /*!< LCD PAL43: R14_0 Position */\r
-#define LCD_PAL43_R14_0_Msk (0x1fUL << LCD_PAL43_R14_0_Pos) /*!< LCD PAL43: R14_0 Mask */\r
-#define LCD_PAL43_G14_0_Pos 21 /*!< LCD PAL43: G14_0 Position */\r
-#define LCD_PAL43_G14_0_Msk (0x1fUL << LCD_PAL43_G14_0_Pos) /*!< LCD PAL43: G14_0 Mask */\r
-#define LCD_PAL43_B14_0_Pos 26 /*!< LCD PAL43: B14_0 Position */\r
-#define LCD_PAL43_B14_0_Msk (0x1fUL << LCD_PAL43_B14_0_Pos) /*!< LCD PAL43: B14_0 Mask */\r
-#define LCD_PAL43_I1_Pos 31 /*!< LCD PAL43: I1 Position */\r
-#define LCD_PAL43_I1_Msk (0x01UL << LCD_PAL43_I1_Pos) /*!< LCD PAL43: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL44 -------------------------------------------\r
-#define LCD_PAL44_R04_0_Pos 0 /*!< LCD PAL44: R04_0 Position */\r
-#define LCD_PAL44_R04_0_Msk (0x1fUL << LCD_PAL44_R04_0_Pos) /*!< LCD PAL44: R04_0 Mask */\r
-#define LCD_PAL44_G04_0_Pos 5 /*!< LCD PAL44: G04_0 Position */\r
-#define LCD_PAL44_G04_0_Msk (0x1fUL << LCD_PAL44_G04_0_Pos) /*!< LCD PAL44: G04_0 Mask */\r
-#define LCD_PAL44_B04_0_Pos 10 /*!< LCD PAL44: B04_0 Position */\r
-#define LCD_PAL44_B04_0_Msk (0x1fUL << LCD_PAL44_B04_0_Pos) /*!< LCD PAL44: B04_0 Mask */\r
-#define LCD_PAL44_I0_Pos 15 /*!< LCD PAL44: I0 Position */\r
-#define LCD_PAL44_I0_Msk (0x01UL << LCD_PAL44_I0_Pos) /*!< LCD PAL44: I0 Mask */\r
-#define LCD_PAL44_R14_0_Pos 16 /*!< LCD PAL44: R14_0 Position */\r
-#define LCD_PAL44_R14_0_Msk (0x1fUL << LCD_PAL44_R14_0_Pos) /*!< LCD PAL44: R14_0 Mask */\r
-#define LCD_PAL44_G14_0_Pos 21 /*!< LCD PAL44: G14_0 Position */\r
-#define LCD_PAL44_G14_0_Msk (0x1fUL << LCD_PAL44_G14_0_Pos) /*!< LCD PAL44: G14_0 Mask */\r
-#define LCD_PAL44_B14_0_Pos 26 /*!< LCD PAL44: B14_0 Position */\r
-#define LCD_PAL44_B14_0_Msk (0x1fUL << LCD_PAL44_B14_0_Pos) /*!< LCD PAL44: B14_0 Mask */\r
-#define LCD_PAL44_I1_Pos 31 /*!< LCD PAL44: I1 Position */\r
-#define LCD_PAL44_I1_Msk (0x01UL << LCD_PAL44_I1_Pos) /*!< LCD PAL44: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL45 -------------------------------------------\r
-#define LCD_PAL45_R04_0_Pos 0 /*!< LCD PAL45: R04_0 Position */\r
-#define LCD_PAL45_R04_0_Msk (0x1fUL << LCD_PAL45_R04_0_Pos) /*!< LCD PAL45: R04_0 Mask */\r
-#define LCD_PAL45_G04_0_Pos 5 /*!< LCD PAL45: G04_0 Position */\r
-#define LCD_PAL45_G04_0_Msk (0x1fUL << LCD_PAL45_G04_0_Pos) /*!< LCD PAL45: G04_0 Mask */\r
-#define LCD_PAL45_B04_0_Pos 10 /*!< LCD PAL45: B04_0 Position */\r
-#define LCD_PAL45_B04_0_Msk (0x1fUL << LCD_PAL45_B04_0_Pos) /*!< LCD PAL45: B04_0 Mask */\r
-#define LCD_PAL45_I0_Pos 15 /*!< LCD PAL45: I0 Position */\r
-#define LCD_PAL45_I0_Msk (0x01UL << LCD_PAL45_I0_Pos) /*!< LCD PAL45: I0 Mask */\r
-#define LCD_PAL45_R14_0_Pos 16 /*!< LCD PAL45: R14_0 Position */\r
-#define LCD_PAL45_R14_0_Msk (0x1fUL << LCD_PAL45_R14_0_Pos) /*!< LCD PAL45: R14_0 Mask */\r
-#define LCD_PAL45_G14_0_Pos 21 /*!< LCD PAL45: G14_0 Position */\r
-#define LCD_PAL45_G14_0_Msk (0x1fUL << LCD_PAL45_G14_0_Pos) /*!< LCD PAL45: G14_0 Mask */\r
-#define LCD_PAL45_B14_0_Pos 26 /*!< LCD PAL45: B14_0 Position */\r
-#define LCD_PAL45_B14_0_Msk (0x1fUL << LCD_PAL45_B14_0_Pos) /*!< LCD PAL45: B14_0 Mask */\r
-#define LCD_PAL45_I1_Pos 31 /*!< LCD PAL45: I1 Position */\r
-#define LCD_PAL45_I1_Msk (0x01UL << LCD_PAL45_I1_Pos) /*!< LCD PAL45: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL46 -------------------------------------------\r
-#define LCD_PAL46_R04_0_Pos 0 /*!< LCD PAL46: R04_0 Position */\r
-#define LCD_PAL46_R04_0_Msk (0x1fUL << LCD_PAL46_R04_0_Pos) /*!< LCD PAL46: R04_0 Mask */\r
-#define LCD_PAL46_G04_0_Pos 5 /*!< LCD PAL46: G04_0 Position */\r
-#define LCD_PAL46_G04_0_Msk (0x1fUL << LCD_PAL46_G04_0_Pos) /*!< LCD PAL46: G04_0 Mask */\r
-#define LCD_PAL46_B04_0_Pos 10 /*!< LCD PAL46: B04_0 Position */\r
-#define LCD_PAL46_B04_0_Msk (0x1fUL << LCD_PAL46_B04_0_Pos) /*!< LCD PAL46: B04_0 Mask */\r
-#define LCD_PAL46_I0_Pos 15 /*!< LCD PAL46: I0 Position */\r
-#define LCD_PAL46_I0_Msk (0x01UL << LCD_PAL46_I0_Pos) /*!< LCD PAL46: I0 Mask */\r
-#define LCD_PAL46_R14_0_Pos 16 /*!< LCD PAL46: R14_0 Position */\r
-#define LCD_PAL46_R14_0_Msk (0x1fUL << LCD_PAL46_R14_0_Pos) /*!< LCD PAL46: R14_0 Mask */\r
-#define LCD_PAL46_G14_0_Pos 21 /*!< LCD PAL46: G14_0 Position */\r
-#define LCD_PAL46_G14_0_Msk (0x1fUL << LCD_PAL46_G14_0_Pos) /*!< LCD PAL46: G14_0 Mask */\r
-#define LCD_PAL46_B14_0_Pos 26 /*!< LCD PAL46: B14_0 Position */\r
-#define LCD_PAL46_B14_0_Msk (0x1fUL << LCD_PAL46_B14_0_Pos) /*!< LCD PAL46: B14_0 Mask */\r
-#define LCD_PAL46_I1_Pos 31 /*!< LCD PAL46: I1 Position */\r
-#define LCD_PAL46_I1_Msk (0x01UL << LCD_PAL46_I1_Pos) /*!< LCD PAL46: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL47 -------------------------------------------\r
-#define LCD_PAL47_R04_0_Pos 0 /*!< LCD PAL47: R04_0 Position */\r
-#define LCD_PAL47_R04_0_Msk (0x1fUL << LCD_PAL47_R04_0_Pos) /*!< LCD PAL47: R04_0 Mask */\r
-#define LCD_PAL47_G04_0_Pos 5 /*!< LCD PAL47: G04_0 Position */\r
-#define LCD_PAL47_G04_0_Msk (0x1fUL << LCD_PAL47_G04_0_Pos) /*!< LCD PAL47: G04_0 Mask */\r
-#define LCD_PAL47_B04_0_Pos 10 /*!< LCD PAL47: B04_0 Position */\r
-#define LCD_PAL47_B04_0_Msk (0x1fUL << LCD_PAL47_B04_0_Pos) /*!< LCD PAL47: B04_0 Mask */\r
-#define LCD_PAL47_I0_Pos 15 /*!< LCD PAL47: I0 Position */\r
-#define LCD_PAL47_I0_Msk (0x01UL << LCD_PAL47_I0_Pos) /*!< LCD PAL47: I0 Mask */\r
-#define LCD_PAL47_R14_0_Pos 16 /*!< LCD PAL47: R14_0 Position */\r
-#define LCD_PAL47_R14_0_Msk (0x1fUL << LCD_PAL47_R14_0_Pos) /*!< LCD PAL47: R14_0 Mask */\r
-#define LCD_PAL47_G14_0_Pos 21 /*!< LCD PAL47: G14_0 Position */\r
-#define LCD_PAL47_G14_0_Msk (0x1fUL << LCD_PAL47_G14_0_Pos) /*!< LCD PAL47: G14_0 Mask */\r
-#define LCD_PAL47_B14_0_Pos 26 /*!< LCD PAL47: B14_0 Position */\r
-#define LCD_PAL47_B14_0_Msk (0x1fUL << LCD_PAL47_B14_0_Pos) /*!< LCD PAL47: B14_0 Mask */\r
-#define LCD_PAL47_I1_Pos 31 /*!< LCD PAL47: I1 Position */\r
-#define LCD_PAL47_I1_Msk (0x01UL << LCD_PAL47_I1_Pos) /*!< LCD PAL47: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL48 -------------------------------------------\r
-#define LCD_PAL48_R04_0_Pos 0 /*!< LCD PAL48: R04_0 Position */\r
-#define LCD_PAL48_R04_0_Msk (0x1fUL << LCD_PAL48_R04_0_Pos) /*!< LCD PAL48: R04_0 Mask */\r
-#define LCD_PAL48_G04_0_Pos 5 /*!< LCD PAL48: G04_0 Position */\r
-#define LCD_PAL48_G04_0_Msk (0x1fUL << LCD_PAL48_G04_0_Pos) /*!< LCD PAL48: G04_0 Mask */\r
-#define LCD_PAL48_B04_0_Pos 10 /*!< LCD PAL48: B04_0 Position */\r
-#define LCD_PAL48_B04_0_Msk (0x1fUL << LCD_PAL48_B04_0_Pos) /*!< LCD PAL48: B04_0 Mask */\r
-#define LCD_PAL48_I0_Pos 15 /*!< LCD PAL48: I0 Position */\r
-#define LCD_PAL48_I0_Msk (0x01UL << LCD_PAL48_I0_Pos) /*!< LCD PAL48: I0 Mask */\r
-#define LCD_PAL48_R14_0_Pos 16 /*!< LCD PAL48: R14_0 Position */\r
-#define LCD_PAL48_R14_0_Msk (0x1fUL << LCD_PAL48_R14_0_Pos) /*!< LCD PAL48: R14_0 Mask */\r
-#define LCD_PAL48_G14_0_Pos 21 /*!< LCD PAL48: G14_0 Position */\r
-#define LCD_PAL48_G14_0_Msk (0x1fUL << LCD_PAL48_G14_0_Pos) /*!< LCD PAL48: G14_0 Mask */\r
-#define LCD_PAL48_B14_0_Pos 26 /*!< LCD PAL48: B14_0 Position */\r
-#define LCD_PAL48_B14_0_Msk (0x1fUL << LCD_PAL48_B14_0_Pos) /*!< LCD PAL48: B14_0 Mask */\r
-#define LCD_PAL48_I1_Pos 31 /*!< LCD PAL48: I1 Position */\r
-#define LCD_PAL48_I1_Msk (0x01UL << LCD_PAL48_I1_Pos) /*!< LCD PAL48: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL49 -------------------------------------------\r
-#define LCD_PAL49_R04_0_Pos 0 /*!< LCD PAL49: R04_0 Position */\r
-#define LCD_PAL49_R04_0_Msk (0x1fUL << LCD_PAL49_R04_0_Pos) /*!< LCD PAL49: R04_0 Mask */\r
-#define LCD_PAL49_G04_0_Pos 5 /*!< LCD PAL49: G04_0 Position */\r
-#define LCD_PAL49_G04_0_Msk (0x1fUL << LCD_PAL49_G04_0_Pos) /*!< LCD PAL49: G04_0 Mask */\r
-#define LCD_PAL49_B04_0_Pos 10 /*!< LCD PAL49: B04_0 Position */\r
-#define LCD_PAL49_B04_0_Msk (0x1fUL << LCD_PAL49_B04_0_Pos) /*!< LCD PAL49: B04_0 Mask */\r
-#define LCD_PAL49_I0_Pos 15 /*!< LCD PAL49: I0 Position */\r
-#define LCD_PAL49_I0_Msk (0x01UL << LCD_PAL49_I0_Pos) /*!< LCD PAL49: I0 Mask */\r
-#define LCD_PAL49_R14_0_Pos 16 /*!< LCD PAL49: R14_0 Position */\r
-#define LCD_PAL49_R14_0_Msk (0x1fUL << LCD_PAL49_R14_0_Pos) /*!< LCD PAL49: R14_0 Mask */\r
-#define LCD_PAL49_G14_0_Pos 21 /*!< LCD PAL49: G14_0 Position */\r
-#define LCD_PAL49_G14_0_Msk (0x1fUL << LCD_PAL49_G14_0_Pos) /*!< LCD PAL49: G14_0 Mask */\r
-#define LCD_PAL49_B14_0_Pos 26 /*!< LCD PAL49: B14_0 Position */\r
-#define LCD_PAL49_B14_0_Msk (0x1fUL << LCD_PAL49_B14_0_Pos) /*!< LCD PAL49: B14_0 Mask */\r
-#define LCD_PAL49_I1_Pos 31 /*!< LCD PAL49: I1 Position */\r
-#define LCD_PAL49_I1_Msk (0x01UL << LCD_PAL49_I1_Pos) /*!< LCD PAL49: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL50 -------------------------------------------\r
-#define LCD_PAL50_R04_0_Pos 0 /*!< LCD PAL50: R04_0 Position */\r
-#define LCD_PAL50_R04_0_Msk (0x1fUL << LCD_PAL50_R04_0_Pos) /*!< LCD PAL50: R04_0 Mask */\r
-#define LCD_PAL50_G04_0_Pos 5 /*!< LCD PAL50: G04_0 Position */\r
-#define LCD_PAL50_G04_0_Msk (0x1fUL << LCD_PAL50_G04_0_Pos) /*!< LCD PAL50: G04_0 Mask */\r
-#define LCD_PAL50_B04_0_Pos 10 /*!< LCD PAL50: B04_0 Position */\r
-#define LCD_PAL50_B04_0_Msk (0x1fUL << LCD_PAL50_B04_0_Pos) /*!< LCD PAL50: B04_0 Mask */\r
-#define LCD_PAL50_I0_Pos 15 /*!< LCD PAL50: I0 Position */\r
-#define LCD_PAL50_I0_Msk (0x01UL << LCD_PAL50_I0_Pos) /*!< LCD PAL50: I0 Mask */\r
-#define LCD_PAL50_R14_0_Pos 16 /*!< LCD PAL50: R14_0 Position */\r
-#define LCD_PAL50_R14_0_Msk (0x1fUL << LCD_PAL50_R14_0_Pos) /*!< LCD PAL50: R14_0 Mask */\r
-#define LCD_PAL50_G14_0_Pos 21 /*!< LCD PAL50: G14_0 Position */\r
-#define LCD_PAL50_G14_0_Msk (0x1fUL << LCD_PAL50_G14_0_Pos) /*!< LCD PAL50: G14_0 Mask */\r
-#define LCD_PAL50_B14_0_Pos 26 /*!< LCD PAL50: B14_0 Position */\r
-#define LCD_PAL50_B14_0_Msk (0x1fUL << LCD_PAL50_B14_0_Pos) /*!< LCD PAL50: B14_0 Mask */\r
-#define LCD_PAL50_I1_Pos 31 /*!< LCD PAL50: I1 Position */\r
-#define LCD_PAL50_I1_Msk (0x01UL << LCD_PAL50_I1_Pos) /*!< LCD PAL50: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL51 -------------------------------------------\r
-#define LCD_PAL51_R04_0_Pos 0 /*!< LCD PAL51: R04_0 Position */\r
-#define LCD_PAL51_R04_0_Msk (0x1fUL << LCD_PAL51_R04_0_Pos) /*!< LCD PAL51: R04_0 Mask */\r
-#define LCD_PAL51_G04_0_Pos 5 /*!< LCD PAL51: G04_0 Position */\r
-#define LCD_PAL51_G04_0_Msk (0x1fUL << LCD_PAL51_G04_0_Pos) /*!< LCD PAL51: G04_0 Mask */\r
-#define LCD_PAL51_B04_0_Pos 10 /*!< LCD PAL51: B04_0 Position */\r
-#define LCD_PAL51_B04_0_Msk (0x1fUL << LCD_PAL51_B04_0_Pos) /*!< LCD PAL51: B04_0 Mask */\r
-#define LCD_PAL51_I0_Pos 15 /*!< LCD PAL51: I0 Position */\r
-#define LCD_PAL51_I0_Msk (0x01UL << LCD_PAL51_I0_Pos) /*!< LCD PAL51: I0 Mask */\r
-#define LCD_PAL51_R14_0_Pos 16 /*!< LCD PAL51: R14_0 Position */\r
-#define LCD_PAL51_R14_0_Msk (0x1fUL << LCD_PAL51_R14_0_Pos) /*!< LCD PAL51: R14_0 Mask */\r
-#define LCD_PAL51_G14_0_Pos 21 /*!< LCD PAL51: G14_0 Position */\r
-#define LCD_PAL51_G14_0_Msk (0x1fUL << LCD_PAL51_G14_0_Pos) /*!< LCD PAL51: G14_0 Mask */\r
-#define LCD_PAL51_B14_0_Pos 26 /*!< LCD PAL51: B14_0 Position */\r
-#define LCD_PAL51_B14_0_Msk (0x1fUL << LCD_PAL51_B14_0_Pos) /*!< LCD PAL51: B14_0 Mask */\r
-#define LCD_PAL51_I1_Pos 31 /*!< LCD PAL51: I1 Position */\r
-#define LCD_PAL51_I1_Msk (0x01UL << LCD_PAL51_I1_Pos) /*!< LCD PAL51: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL52 -------------------------------------------\r
-#define LCD_PAL52_R04_0_Pos 0 /*!< LCD PAL52: R04_0 Position */\r
-#define LCD_PAL52_R04_0_Msk (0x1fUL << LCD_PAL52_R04_0_Pos) /*!< LCD PAL52: R04_0 Mask */\r
-#define LCD_PAL52_G04_0_Pos 5 /*!< LCD PAL52: G04_0 Position */\r
-#define LCD_PAL52_G04_0_Msk (0x1fUL << LCD_PAL52_G04_0_Pos) /*!< LCD PAL52: G04_0 Mask */\r
-#define LCD_PAL52_B04_0_Pos 10 /*!< LCD PAL52: B04_0 Position */\r
-#define LCD_PAL52_B04_0_Msk (0x1fUL << LCD_PAL52_B04_0_Pos) /*!< LCD PAL52: B04_0 Mask */\r
-#define LCD_PAL52_I0_Pos 15 /*!< LCD PAL52: I0 Position */\r
-#define LCD_PAL52_I0_Msk (0x01UL << LCD_PAL52_I0_Pos) /*!< LCD PAL52: I0 Mask */\r
-#define LCD_PAL52_R14_0_Pos 16 /*!< LCD PAL52: R14_0 Position */\r
-#define LCD_PAL52_R14_0_Msk (0x1fUL << LCD_PAL52_R14_0_Pos) /*!< LCD PAL52: R14_0 Mask */\r
-#define LCD_PAL52_G14_0_Pos 21 /*!< LCD PAL52: G14_0 Position */\r
-#define LCD_PAL52_G14_0_Msk (0x1fUL << LCD_PAL52_G14_0_Pos) /*!< LCD PAL52: G14_0 Mask */\r
-#define LCD_PAL52_B14_0_Pos 26 /*!< LCD PAL52: B14_0 Position */\r
-#define LCD_PAL52_B14_0_Msk (0x1fUL << LCD_PAL52_B14_0_Pos) /*!< LCD PAL52: B14_0 Mask */\r
-#define LCD_PAL52_I1_Pos 31 /*!< LCD PAL52: I1 Position */\r
-#define LCD_PAL52_I1_Msk (0x01UL << LCD_PAL52_I1_Pos) /*!< LCD PAL52: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL53 -------------------------------------------\r
-#define LCD_PAL53_R04_0_Pos 0 /*!< LCD PAL53: R04_0 Position */\r
-#define LCD_PAL53_R04_0_Msk (0x1fUL << LCD_PAL53_R04_0_Pos) /*!< LCD PAL53: R04_0 Mask */\r
-#define LCD_PAL53_G04_0_Pos 5 /*!< LCD PAL53: G04_0 Position */\r
-#define LCD_PAL53_G04_0_Msk (0x1fUL << LCD_PAL53_G04_0_Pos) /*!< LCD PAL53: G04_0 Mask */\r
-#define LCD_PAL53_B04_0_Pos 10 /*!< LCD PAL53: B04_0 Position */\r
-#define LCD_PAL53_B04_0_Msk (0x1fUL << LCD_PAL53_B04_0_Pos) /*!< LCD PAL53: B04_0 Mask */\r
-#define LCD_PAL53_I0_Pos 15 /*!< LCD PAL53: I0 Position */\r
-#define LCD_PAL53_I0_Msk (0x01UL << LCD_PAL53_I0_Pos) /*!< LCD PAL53: I0 Mask */\r
-#define LCD_PAL53_R14_0_Pos 16 /*!< LCD PAL53: R14_0 Position */\r
-#define LCD_PAL53_R14_0_Msk (0x1fUL << LCD_PAL53_R14_0_Pos) /*!< LCD PAL53: R14_0 Mask */\r
-#define LCD_PAL53_G14_0_Pos 21 /*!< LCD PAL53: G14_0 Position */\r
-#define LCD_PAL53_G14_0_Msk (0x1fUL << LCD_PAL53_G14_0_Pos) /*!< LCD PAL53: G14_0 Mask */\r
-#define LCD_PAL53_B14_0_Pos 26 /*!< LCD PAL53: B14_0 Position */\r
-#define LCD_PAL53_B14_0_Msk (0x1fUL << LCD_PAL53_B14_0_Pos) /*!< LCD PAL53: B14_0 Mask */\r
-#define LCD_PAL53_I1_Pos 31 /*!< LCD PAL53: I1 Position */\r
-#define LCD_PAL53_I1_Msk (0x01UL << LCD_PAL53_I1_Pos) /*!< LCD PAL53: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL54 -------------------------------------------\r
-#define LCD_PAL54_R04_0_Pos 0 /*!< LCD PAL54: R04_0 Position */\r
-#define LCD_PAL54_R04_0_Msk (0x1fUL << LCD_PAL54_R04_0_Pos) /*!< LCD PAL54: R04_0 Mask */\r
-#define LCD_PAL54_G04_0_Pos 5 /*!< LCD PAL54: G04_0 Position */\r
-#define LCD_PAL54_G04_0_Msk (0x1fUL << LCD_PAL54_G04_0_Pos) /*!< LCD PAL54: G04_0 Mask */\r
-#define LCD_PAL54_B04_0_Pos 10 /*!< LCD PAL54: B04_0 Position */\r
-#define LCD_PAL54_B04_0_Msk (0x1fUL << LCD_PAL54_B04_0_Pos) /*!< LCD PAL54: B04_0 Mask */\r
-#define LCD_PAL54_I0_Pos 15 /*!< LCD PAL54: I0 Position */\r
-#define LCD_PAL54_I0_Msk (0x01UL << LCD_PAL54_I0_Pos) /*!< LCD PAL54: I0 Mask */\r
-#define LCD_PAL54_R14_0_Pos 16 /*!< LCD PAL54: R14_0 Position */\r
-#define LCD_PAL54_R14_0_Msk (0x1fUL << LCD_PAL54_R14_0_Pos) /*!< LCD PAL54: R14_0 Mask */\r
-#define LCD_PAL54_G14_0_Pos 21 /*!< LCD PAL54: G14_0 Position */\r
-#define LCD_PAL54_G14_0_Msk (0x1fUL << LCD_PAL54_G14_0_Pos) /*!< LCD PAL54: G14_0 Mask */\r
-#define LCD_PAL54_B14_0_Pos 26 /*!< LCD PAL54: B14_0 Position */\r
-#define LCD_PAL54_B14_0_Msk (0x1fUL << LCD_PAL54_B14_0_Pos) /*!< LCD PAL54: B14_0 Mask */\r
-#define LCD_PAL54_I1_Pos 31 /*!< LCD PAL54: I1 Position */\r
-#define LCD_PAL54_I1_Msk (0x01UL << LCD_PAL54_I1_Pos) /*!< LCD PAL54: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL55 -------------------------------------------\r
-#define LCD_PAL55_R04_0_Pos 0 /*!< LCD PAL55: R04_0 Position */\r
-#define LCD_PAL55_R04_0_Msk (0x1fUL << LCD_PAL55_R04_0_Pos) /*!< LCD PAL55: R04_0 Mask */\r
-#define LCD_PAL55_G04_0_Pos 5 /*!< LCD PAL55: G04_0 Position */\r
-#define LCD_PAL55_G04_0_Msk (0x1fUL << LCD_PAL55_G04_0_Pos) /*!< LCD PAL55: G04_0 Mask */\r
-#define LCD_PAL55_B04_0_Pos 10 /*!< LCD PAL55: B04_0 Position */\r
-#define LCD_PAL55_B04_0_Msk (0x1fUL << LCD_PAL55_B04_0_Pos) /*!< LCD PAL55: B04_0 Mask */\r
-#define LCD_PAL55_I0_Pos 15 /*!< LCD PAL55: I0 Position */\r
-#define LCD_PAL55_I0_Msk (0x01UL << LCD_PAL55_I0_Pos) /*!< LCD PAL55: I0 Mask */\r
-#define LCD_PAL55_R14_0_Pos 16 /*!< LCD PAL55: R14_0 Position */\r
-#define LCD_PAL55_R14_0_Msk (0x1fUL << LCD_PAL55_R14_0_Pos) /*!< LCD PAL55: R14_0 Mask */\r
-#define LCD_PAL55_G14_0_Pos 21 /*!< LCD PAL55: G14_0 Position */\r
-#define LCD_PAL55_G14_0_Msk (0x1fUL << LCD_PAL55_G14_0_Pos) /*!< LCD PAL55: G14_0 Mask */\r
-#define LCD_PAL55_B14_0_Pos 26 /*!< LCD PAL55: B14_0 Position */\r
-#define LCD_PAL55_B14_0_Msk (0x1fUL << LCD_PAL55_B14_0_Pos) /*!< LCD PAL55: B14_0 Mask */\r
-#define LCD_PAL55_I1_Pos 31 /*!< LCD PAL55: I1 Position */\r
-#define LCD_PAL55_I1_Msk (0x01UL << LCD_PAL55_I1_Pos) /*!< LCD PAL55: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL56 -------------------------------------------\r
-#define LCD_PAL56_R04_0_Pos 0 /*!< LCD PAL56: R04_0 Position */\r
-#define LCD_PAL56_R04_0_Msk (0x1fUL << LCD_PAL56_R04_0_Pos) /*!< LCD PAL56: R04_0 Mask */\r
-#define LCD_PAL56_G04_0_Pos 5 /*!< LCD PAL56: G04_0 Position */\r
-#define LCD_PAL56_G04_0_Msk (0x1fUL << LCD_PAL56_G04_0_Pos) /*!< LCD PAL56: G04_0 Mask */\r
-#define LCD_PAL56_B04_0_Pos 10 /*!< LCD PAL56: B04_0 Position */\r
-#define LCD_PAL56_B04_0_Msk (0x1fUL << LCD_PAL56_B04_0_Pos) /*!< LCD PAL56: B04_0 Mask */\r
-#define LCD_PAL56_I0_Pos 15 /*!< LCD PAL56: I0 Position */\r
-#define LCD_PAL56_I0_Msk (0x01UL << LCD_PAL56_I0_Pos) /*!< LCD PAL56: I0 Mask */\r
-#define LCD_PAL56_R14_0_Pos 16 /*!< LCD PAL56: R14_0 Position */\r
-#define LCD_PAL56_R14_0_Msk (0x1fUL << LCD_PAL56_R14_0_Pos) /*!< LCD PAL56: R14_0 Mask */\r
-#define LCD_PAL56_G14_0_Pos 21 /*!< LCD PAL56: G14_0 Position */\r
-#define LCD_PAL56_G14_0_Msk (0x1fUL << LCD_PAL56_G14_0_Pos) /*!< LCD PAL56: G14_0 Mask */\r
-#define LCD_PAL56_B14_0_Pos 26 /*!< LCD PAL56: B14_0 Position */\r
-#define LCD_PAL56_B14_0_Msk (0x1fUL << LCD_PAL56_B14_0_Pos) /*!< LCD PAL56: B14_0 Mask */\r
-#define LCD_PAL56_I1_Pos 31 /*!< LCD PAL56: I1 Position */\r
-#define LCD_PAL56_I1_Msk (0x01UL << LCD_PAL56_I1_Pos) /*!< LCD PAL56: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL57 -------------------------------------------\r
-#define LCD_PAL57_R04_0_Pos 0 /*!< LCD PAL57: R04_0 Position */\r
-#define LCD_PAL57_R04_0_Msk (0x1fUL << LCD_PAL57_R04_0_Pos) /*!< LCD PAL57: R04_0 Mask */\r
-#define LCD_PAL57_G04_0_Pos 5 /*!< LCD PAL57: G04_0 Position */\r
-#define LCD_PAL57_G04_0_Msk (0x1fUL << LCD_PAL57_G04_0_Pos) /*!< LCD PAL57: G04_0 Mask */\r
-#define LCD_PAL57_B04_0_Pos 10 /*!< LCD PAL57: B04_0 Position */\r
-#define LCD_PAL57_B04_0_Msk (0x1fUL << LCD_PAL57_B04_0_Pos) /*!< LCD PAL57: B04_0 Mask */\r
-#define LCD_PAL57_I0_Pos 15 /*!< LCD PAL57: I0 Position */\r
-#define LCD_PAL57_I0_Msk (0x01UL << LCD_PAL57_I0_Pos) /*!< LCD PAL57: I0 Mask */\r
-#define LCD_PAL57_R14_0_Pos 16 /*!< LCD PAL57: R14_0 Position */\r
-#define LCD_PAL57_R14_0_Msk (0x1fUL << LCD_PAL57_R14_0_Pos) /*!< LCD PAL57: R14_0 Mask */\r
-#define LCD_PAL57_G14_0_Pos 21 /*!< LCD PAL57: G14_0 Position */\r
-#define LCD_PAL57_G14_0_Msk (0x1fUL << LCD_PAL57_G14_0_Pos) /*!< LCD PAL57: G14_0 Mask */\r
-#define LCD_PAL57_B14_0_Pos 26 /*!< LCD PAL57: B14_0 Position */\r
-#define LCD_PAL57_B14_0_Msk (0x1fUL << LCD_PAL57_B14_0_Pos) /*!< LCD PAL57: B14_0 Mask */\r
-#define LCD_PAL57_I1_Pos 31 /*!< LCD PAL57: I1 Position */\r
-#define LCD_PAL57_I1_Msk (0x01UL << LCD_PAL57_I1_Pos) /*!< LCD PAL57: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL58 -------------------------------------------\r
-#define LCD_PAL58_R04_0_Pos 0 /*!< LCD PAL58: R04_0 Position */\r
-#define LCD_PAL58_R04_0_Msk (0x1fUL << LCD_PAL58_R04_0_Pos) /*!< LCD PAL58: R04_0 Mask */\r
-#define LCD_PAL58_G04_0_Pos 5 /*!< LCD PAL58: G04_0 Position */\r
-#define LCD_PAL58_G04_0_Msk (0x1fUL << LCD_PAL58_G04_0_Pos) /*!< LCD PAL58: G04_0 Mask */\r
-#define LCD_PAL58_B04_0_Pos 10 /*!< LCD PAL58: B04_0 Position */\r
-#define LCD_PAL58_B04_0_Msk (0x1fUL << LCD_PAL58_B04_0_Pos) /*!< LCD PAL58: B04_0 Mask */\r
-#define LCD_PAL58_I0_Pos 15 /*!< LCD PAL58: I0 Position */\r
-#define LCD_PAL58_I0_Msk (0x01UL << LCD_PAL58_I0_Pos) /*!< LCD PAL58: I0 Mask */\r
-#define LCD_PAL58_R14_0_Pos 16 /*!< LCD PAL58: R14_0 Position */\r
-#define LCD_PAL58_R14_0_Msk (0x1fUL << LCD_PAL58_R14_0_Pos) /*!< LCD PAL58: R14_0 Mask */\r
-#define LCD_PAL58_G14_0_Pos 21 /*!< LCD PAL58: G14_0 Position */\r
-#define LCD_PAL58_G14_0_Msk (0x1fUL << LCD_PAL58_G14_0_Pos) /*!< LCD PAL58: G14_0 Mask */\r
-#define LCD_PAL58_B14_0_Pos 26 /*!< LCD PAL58: B14_0 Position */\r
-#define LCD_PAL58_B14_0_Msk (0x1fUL << LCD_PAL58_B14_0_Pos) /*!< LCD PAL58: B14_0 Mask */\r
-#define LCD_PAL58_I1_Pos 31 /*!< LCD PAL58: I1 Position */\r
-#define LCD_PAL58_I1_Msk (0x01UL << LCD_PAL58_I1_Pos) /*!< LCD PAL58: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL59 -------------------------------------------\r
-#define LCD_PAL59_R04_0_Pos 0 /*!< LCD PAL59: R04_0 Position */\r
-#define LCD_PAL59_R04_0_Msk (0x1fUL << LCD_PAL59_R04_0_Pos) /*!< LCD PAL59: R04_0 Mask */\r
-#define LCD_PAL59_G04_0_Pos 5 /*!< LCD PAL59: G04_0 Position */\r
-#define LCD_PAL59_G04_0_Msk (0x1fUL << LCD_PAL59_G04_0_Pos) /*!< LCD PAL59: G04_0 Mask */\r
-#define LCD_PAL59_B04_0_Pos 10 /*!< LCD PAL59: B04_0 Position */\r
-#define LCD_PAL59_B04_0_Msk (0x1fUL << LCD_PAL59_B04_0_Pos) /*!< LCD PAL59: B04_0 Mask */\r
-#define LCD_PAL59_I0_Pos 15 /*!< LCD PAL59: I0 Position */\r
-#define LCD_PAL59_I0_Msk (0x01UL << LCD_PAL59_I0_Pos) /*!< LCD PAL59: I0 Mask */\r
-#define LCD_PAL59_R14_0_Pos 16 /*!< LCD PAL59: R14_0 Position */\r
-#define LCD_PAL59_R14_0_Msk (0x1fUL << LCD_PAL59_R14_0_Pos) /*!< LCD PAL59: R14_0 Mask */\r
-#define LCD_PAL59_G14_0_Pos 21 /*!< LCD PAL59: G14_0 Position */\r
-#define LCD_PAL59_G14_0_Msk (0x1fUL << LCD_PAL59_G14_0_Pos) /*!< LCD PAL59: G14_0 Mask */\r
-#define LCD_PAL59_B14_0_Pos 26 /*!< LCD PAL59: B14_0 Position */\r
-#define LCD_PAL59_B14_0_Msk (0x1fUL << LCD_PAL59_B14_0_Pos) /*!< LCD PAL59: B14_0 Mask */\r
-#define LCD_PAL59_I1_Pos 31 /*!< LCD PAL59: I1 Position */\r
-#define LCD_PAL59_I1_Msk (0x01UL << LCD_PAL59_I1_Pos) /*!< LCD PAL59: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL60 -------------------------------------------\r
-#define LCD_PAL60_R04_0_Pos 0 /*!< LCD PAL60: R04_0 Position */\r
-#define LCD_PAL60_R04_0_Msk (0x1fUL << LCD_PAL60_R04_0_Pos) /*!< LCD PAL60: R04_0 Mask */\r
-#define LCD_PAL60_G04_0_Pos 5 /*!< LCD PAL60: G04_0 Position */\r
-#define LCD_PAL60_G04_0_Msk (0x1fUL << LCD_PAL60_G04_0_Pos) /*!< LCD PAL60: G04_0 Mask */\r
-#define LCD_PAL60_B04_0_Pos 10 /*!< LCD PAL60: B04_0 Position */\r
-#define LCD_PAL60_B04_0_Msk (0x1fUL << LCD_PAL60_B04_0_Pos) /*!< LCD PAL60: B04_0 Mask */\r
-#define LCD_PAL60_I0_Pos 15 /*!< LCD PAL60: I0 Position */\r
-#define LCD_PAL60_I0_Msk (0x01UL << LCD_PAL60_I0_Pos) /*!< LCD PAL60: I0 Mask */\r
-#define LCD_PAL60_R14_0_Pos 16 /*!< LCD PAL60: R14_0 Position */\r
-#define LCD_PAL60_R14_0_Msk (0x1fUL << LCD_PAL60_R14_0_Pos) /*!< LCD PAL60: R14_0 Mask */\r
-#define LCD_PAL60_G14_0_Pos 21 /*!< LCD PAL60: G14_0 Position */\r
-#define LCD_PAL60_G14_0_Msk (0x1fUL << LCD_PAL60_G14_0_Pos) /*!< LCD PAL60: G14_0 Mask */\r
-#define LCD_PAL60_B14_0_Pos 26 /*!< LCD PAL60: B14_0 Position */\r
-#define LCD_PAL60_B14_0_Msk (0x1fUL << LCD_PAL60_B14_0_Pos) /*!< LCD PAL60: B14_0 Mask */\r
-#define LCD_PAL60_I1_Pos 31 /*!< LCD PAL60: I1 Position */\r
-#define LCD_PAL60_I1_Msk (0x01UL << LCD_PAL60_I1_Pos) /*!< LCD PAL60: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL61 -------------------------------------------\r
-#define LCD_PAL61_R04_0_Pos 0 /*!< LCD PAL61: R04_0 Position */\r
-#define LCD_PAL61_R04_0_Msk (0x1fUL << LCD_PAL61_R04_0_Pos) /*!< LCD PAL61: R04_0 Mask */\r
-#define LCD_PAL61_G04_0_Pos 5 /*!< LCD PAL61: G04_0 Position */\r
-#define LCD_PAL61_G04_0_Msk (0x1fUL << LCD_PAL61_G04_0_Pos) /*!< LCD PAL61: G04_0 Mask */\r
-#define LCD_PAL61_B04_0_Pos 10 /*!< LCD PAL61: B04_0 Position */\r
-#define LCD_PAL61_B04_0_Msk (0x1fUL << LCD_PAL61_B04_0_Pos) /*!< LCD PAL61: B04_0 Mask */\r
-#define LCD_PAL61_I0_Pos 15 /*!< LCD PAL61: I0 Position */\r
-#define LCD_PAL61_I0_Msk (0x01UL << LCD_PAL61_I0_Pos) /*!< LCD PAL61: I0 Mask */\r
-#define LCD_PAL61_R14_0_Pos 16 /*!< LCD PAL61: R14_0 Position */\r
-#define LCD_PAL61_R14_0_Msk (0x1fUL << LCD_PAL61_R14_0_Pos) /*!< LCD PAL61: R14_0 Mask */\r
-#define LCD_PAL61_G14_0_Pos 21 /*!< LCD PAL61: G14_0 Position */\r
-#define LCD_PAL61_G14_0_Msk (0x1fUL << LCD_PAL61_G14_0_Pos) /*!< LCD PAL61: G14_0 Mask */\r
-#define LCD_PAL61_B14_0_Pos 26 /*!< LCD PAL61: B14_0 Position */\r
-#define LCD_PAL61_B14_0_Msk (0x1fUL << LCD_PAL61_B14_0_Pos) /*!< LCD PAL61: B14_0 Mask */\r
-#define LCD_PAL61_I1_Pos 31 /*!< LCD PAL61: I1 Position */\r
-#define LCD_PAL61_I1_Msk (0x01UL << LCD_PAL61_I1_Pos) /*!< LCD PAL61: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL62 -------------------------------------------\r
-#define LCD_PAL62_R04_0_Pos 0 /*!< LCD PAL62: R04_0 Position */\r
-#define LCD_PAL62_R04_0_Msk (0x1fUL << LCD_PAL62_R04_0_Pos) /*!< LCD PAL62: R04_0 Mask */\r
-#define LCD_PAL62_G04_0_Pos 5 /*!< LCD PAL62: G04_0 Position */\r
-#define LCD_PAL62_G04_0_Msk (0x1fUL << LCD_PAL62_G04_0_Pos) /*!< LCD PAL62: G04_0 Mask */\r
-#define LCD_PAL62_B04_0_Pos 10 /*!< LCD PAL62: B04_0 Position */\r
-#define LCD_PAL62_B04_0_Msk (0x1fUL << LCD_PAL62_B04_0_Pos) /*!< LCD PAL62: B04_0 Mask */\r
-#define LCD_PAL62_I0_Pos 15 /*!< LCD PAL62: I0 Position */\r
-#define LCD_PAL62_I0_Msk (0x01UL << LCD_PAL62_I0_Pos) /*!< LCD PAL62: I0 Mask */\r
-#define LCD_PAL62_R14_0_Pos 16 /*!< LCD PAL62: R14_0 Position */\r
-#define LCD_PAL62_R14_0_Msk (0x1fUL << LCD_PAL62_R14_0_Pos) /*!< LCD PAL62: R14_0 Mask */\r
-#define LCD_PAL62_G14_0_Pos 21 /*!< LCD PAL62: G14_0 Position */\r
-#define LCD_PAL62_G14_0_Msk (0x1fUL << LCD_PAL62_G14_0_Pos) /*!< LCD PAL62: G14_0 Mask */\r
-#define LCD_PAL62_B14_0_Pos 26 /*!< LCD PAL62: B14_0 Position */\r
-#define LCD_PAL62_B14_0_Msk (0x1fUL << LCD_PAL62_B14_0_Pos) /*!< LCD PAL62: B14_0 Mask */\r
-#define LCD_PAL62_I1_Pos 31 /*!< LCD PAL62: I1 Position */\r
-#define LCD_PAL62_I1_Msk (0x01UL << LCD_PAL62_I1_Pos) /*!< LCD PAL62: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL63 -------------------------------------------\r
-#define LCD_PAL63_R04_0_Pos 0 /*!< LCD PAL63: R04_0 Position */\r
-#define LCD_PAL63_R04_0_Msk (0x1fUL << LCD_PAL63_R04_0_Pos) /*!< LCD PAL63: R04_0 Mask */\r
-#define LCD_PAL63_G04_0_Pos 5 /*!< LCD PAL63: G04_0 Position */\r
-#define LCD_PAL63_G04_0_Msk (0x1fUL << LCD_PAL63_G04_0_Pos) /*!< LCD PAL63: G04_0 Mask */\r
-#define LCD_PAL63_B04_0_Pos 10 /*!< LCD PAL63: B04_0 Position */\r
-#define LCD_PAL63_B04_0_Msk (0x1fUL << LCD_PAL63_B04_0_Pos) /*!< LCD PAL63: B04_0 Mask */\r
-#define LCD_PAL63_I0_Pos 15 /*!< LCD PAL63: I0 Position */\r
-#define LCD_PAL63_I0_Msk (0x01UL << LCD_PAL63_I0_Pos) /*!< LCD PAL63: I0 Mask */\r
-#define LCD_PAL63_R14_0_Pos 16 /*!< LCD PAL63: R14_0 Position */\r
-#define LCD_PAL63_R14_0_Msk (0x1fUL << LCD_PAL63_R14_0_Pos) /*!< LCD PAL63: R14_0 Mask */\r
-#define LCD_PAL63_G14_0_Pos 21 /*!< LCD PAL63: G14_0 Position */\r
-#define LCD_PAL63_G14_0_Msk (0x1fUL << LCD_PAL63_G14_0_Pos) /*!< LCD PAL63: G14_0 Mask */\r
-#define LCD_PAL63_B14_0_Pos 26 /*!< LCD PAL63: B14_0 Position */\r
-#define LCD_PAL63_B14_0_Msk (0x1fUL << LCD_PAL63_B14_0_Pos) /*!< LCD PAL63: B14_0 Mask */\r
-#define LCD_PAL63_I1_Pos 31 /*!< LCD PAL63: I1 Position */\r
-#define LCD_PAL63_I1_Msk (0x01UL << LCD_PAL63_I1_Pos) /*!< LCD PAL63: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL64 -------------------------------------------\r
-#define LCD_PAL64_R04_0_Pos 0 /*!< LCD PAL64: R04_0 Position */\r
-#define LCD_PAL64_R04_0_Msk (0x1fUL << LCD_PAL64_R04_0_Pos) /*!< LCD PAL64: R04_0 Mask */\r
-#define LCD_PAL64_G04_0_Pos 5 /*!< LCD PAL64: G04_0 Position */\r
-#define LCD_PAL64_G04_0_Msk (0x1fUL << LCD_PAL64_G04_0_Pos) /*!< LCD PAL64: G04_0 Mask */\r
-#define LCD_PAL64_B04_0_Pos 10 /*!< LCD PAL64: B04_0 Position */\r
-#define LCD_PAL64_B04_0_Msk (0x1fUL << LCD_PAL64_B04_0_Pos) /*!< LCD PAL64: B04_0 Mask */\r
-#define LCD_PAL64_I0_Pos 15 /*!< LCD PAL64: I0 Position */\r
-#define LCD_PAL64_I0_Msk (0x01UL << LCD_PAL64_I0_Pos) /*!< LCD PAL64: I0 Mask */\r
-#define LCD_PAL64_R14_0_Pos 16 /*!< LCD PAL64: R14_0 Position */\r
-#define LCD_PAL64_R14_0_Msk (0x1fUL << LCD_PAL64_R14_0_Pos) /*!< LCD PAL64: R14_0 Mask */\r
-#define LCD_PAL64_G14_0_Pos 21 /*!< LCD PAL64: G14_0 Position */\r
-#define LCD_PAL64_G14_0_Msk (0x1fUL << LCD_PAL64_G14_0_Pos) /*!< LCD PAL64: G14_0 Mask */\r
-#define LCD_PAL64_B14_0_Pos 26 /*!< LCD PAL64: B14_0 Position */\r
-#define LCD_PAL64_B14_0_Msk (0x1fUL << LCD_PAL64_B14_0_Pos) /*!< LCD PAL64: B14_0 Mask */\r
-#define LCD_PAL64_I1_Pos 31 /*!< LCD PAL64: I1 Position */\r
-#define LCD_PAL64_I1_Msk (0x01UL << LCD_PAL64_I1_Pos) /*!< LCD PAL64: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL65 -------------------------------------------\r
-#define LCD_PAL65_R04_0_Pos 0 /*!< LCD PAL65: R04_0 Position */\r
-#define LCD_PAL65_R04_0_Msk (0x1fUL << LCD_PAL65_R04_0_Pos) /*!< LCD PAL65: R04_0 Mask */\r
-#define LCD_PAL65_G04_0_Pos 5 /*!< LCD PAL65: G04_0 Position */\r
-#define LCD_PAL65_G04_0_Msk (0x1fUL << LCD_PAL65_G04_0_Pos) /*!< LCD PAL65: G04_0 Mask */\r
-#define LCD_PAL65_B04_0_Pos 10 /*!< LCD PAL65: B04_0 Position */\r
-#define LCD_PAL65_B04_0_Msk (0x1fUL << LCD_PAL65_B04_0_Pos) /*!< LCD PAL65: B04_0 Mask */\r
-#define LCD_PAL65_I0_Pos 15 /*!< LCD PAL65: I0 Position */\r
-#define LCD_PAL65_I0_Msk (0x01UL << LCD_PAL65_I0_Pos) /*!< LCD PAL65: I0 Mask */\r
-#define LCD_PAL65_R14_0_Pos 16 /*!< LCD PAL65: R14_0 Position */\r
-#define LCD_PAL65_R14_0_Msk (0x1fUL << LCD_PAL65_R14_0_Pos) /*!< LCD PAL65: R14_0 Mask */\r
-#define LCD_PAL65_G14_0_Pos 21 /*!< LCD PAL65: G14_0 Position */\r
-#define LCD_PAL65_G14_0_Msk (0x1fUL << LCD_PAL65_G14_0_Pos) /*!< LCD PAL65: G14_0 Mask */\r
-#define LCD_PAL65_B14_0_Pos 26 /*!< LCD PAL65: B14_0 Position */\r
-#define LCD_PAL65_B14_0_Msk (0x1fUL << LCD_PAL65_B14_0_Pos) /*!< LCD PAL65: B14_0 Mask */\r
-#define LCD_PAL65_I1_Pos 31 /*!< LCD PAL65: I1 Position */\r
-#define LCD_PAL65_I1_Msk (0x01UL << LCD_PAL65_I1_Pos) /*!< LCD PAL65: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL66 -------------------------------------------\r
-#define LCD_PAL66_R04_0_Pos 0 /*!< LCD PAL66: R04_0 Position */\r
-#define LCD_PAL66_R04_0_Msk (0x1fUL << LCD_PAL66_R04_0_Pos) /*!< LCD PAL66: R04_0 Mask */\r
-#define LCD_PAL66_G04_0_Pos 5 /*!< LCD PAL66: G04_0 Position */\r
-#define LCD_PAL66_G04_0_Msk (0x1fUL << LCD_PAL66_G04_0_Pos) /*!< LCD PAL66: G04_0 Mask */\r
-#define LCD_PAL66_B04_0_Pos 10 /*!< LCD PAL66: B04_0 Position */\r
-#define LCD_PAL66_B04_0_Msk (0x1fUL << LCD_PAL66_B04_0_Pos) /*!< LCD PAL66: B04_0 Mask */\r
-#define LCD_PAL66_I0_Pos 15 /*!< LCD PAL66: I0 Position */\r
-#define LCD_PAL66_I0_Msk (0x01UL << LCD_PAL66_I0_Pos) /*!< LCD PAL66: I0 Mask */\r
-#define LCD_PAL66_R14_0_Pos 16 /*!< LCD PAL66: R14_0 Position */\r
-#define LCD_PAL66_R14_0_Msk (0x1fUL << LCD_PAL66_R14_0_Pos) /*!< LCD PAL66: R14_0 Mask */\r
-#define LCD_PAL66_G14_0_Pos 21 /*!< LCD PAL66: G14_0 Position */\r
-#define LCD_PAL66_G14_0_Msk (0x1fUL << LCD_PAL66_G14_0_Pos) /*!< LCD PAL66: G14_0 Mask */\r
-#define LCD_PAL66_B14_0_Pos 26 /*!< LCD PAL66: B14_0 Position */\r
-#define LCD_PAL66_B14_0_Msk (0x1fUL << LCD_PAL66_B14_0_Pos) /*!< LCD PAL66: B14_0 Mask */\r
-#define LCD_PAL66_I1_Pos 31 /*!< LCD PAL66: I1 Position */\r
-#define LCD_PAL66_I1_Msk (0x01UL << LCD_PAL66_I1_Pos) /*!< LCD PAL66: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL67 -------------------------------------------\r
-#define LCD_PAL67_R04_0_Pos 0 /*!< LCD PAL67: R04_0 Position */\r
-#define LCD_PAL67_R04_0_Msk (0x1fUL << LCD_PAL67_R04_0_Pos) /*!< LCD PAL67: R04_0 Mask */\r
-#define LCD_PAL67_G04_0_Pos 5 /*!< LCD PAL67: G04_0 Position */\r
-#define LCD_PAL67_G04_0_Msk (0x1fUL << LCD_PAL67_G04_0_Pos) /*!< LCD PAL67: G04_0 Mask */\r
-#define LCD_PAL67_B04_0_Pos 10 /*!< LCD PAL67: B04_0 Position */\r
-#define LCD_PAL67_B04_0_Msk (0x1fUL << LCD_PAL67_B04_0_Pos) /*!< LCD PAL67: B04_0 Mask */\r
-#define LCD_PAL67_I0_Pos 15 /*!< LCD PAL67: I0 Position */\r
-#define LCD_PAL67_I0_Msk (0x01UL << LCD_PAL67_I0_Pos) /*!< LCD PAL67: I0 Mask */\r
-#define LCD_PAL67_R14_0_Pos 16 /*!< LCD PAL67: R14_0 Position */\r
-#define LCD_PAL67_R14_0_Msk (0x1fUL << LCD_PAL67_R14_0_Pos) /*!< LCD PAL67: R14_0 Mask */\r
-#define LCD_PAL67_G14_0_Pos 21 /*!< LCD PAL67: G14_0 Position */\r
-#define LCD_PAL67_G14_0_Msk (0x1fUL << LCD_PAL67_G14_0_Pos) /*!< LCD PAL67: G14_0 Mask */\r
-#define LCD_PAL67_B14_0_Pos 26 /*!< LCD PAL67: B14_0 Position */\r
-#define LCD_PAL67_B14_0_Msk (0x1fUL << LCD_PAL67_B14_0_Pos) /*!< LCD PAL67: B14_0 Mask */\r
-#define LCD_PAL67_I1_Pos 31 /*!< LCD PAL67: I1 Position */\r
-#define LCD_PAL67_I1_Msk (0x01UL << LCD_PAL67_I1_Pos) /*!< LCD PAL67: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL68 -------------------------------------------\r
-#define LCD_PAL68_R04_0_Pos 0 /*!< LCD PAL68: R04_0 Position */\r
-#define LCD_PAL68_R04_0_Msk (0x1fUL << LCD_PAL68_R04_0_Pos) /*!< LCD PAL68: R04_0 Mask */\r
-#define LCD_PAL68_G04_0_Pos 5 /*!< LCD PAL68: G04_0 Position */\r
-#define LCD_PAL68_G04_0_Msk (0x1fUL << LCD_PAL68_G04_0_Pos) /*!< LCD PAL68: G04_0 Mask */\r
-#define LCD_PAL68_B04_0_Pos 10 /*!< LCD PAL68: B04_0 Position */\r
-#define LCD_PAL68_B04_0_Msk (0x1fUL << LCD_PAL68_B04_0_Pos) /*!< LCD PAL68: B04_0 Mask */\r
-#define LCD_PAL68_I0_Pos 15 /*!< LCD PAL68: I0 Position */\r
-#define LCD_PAL68_I0_Msk (0x01UL << LCD_PAL68_I0_Pos) /*!< LCD PAL68: I0 Mask */\r
-#define LCD_PAL68_R14_0_Pos 16 /*!< LCD PAL68: R14_0 Position */\r
-#define LCD_PAL68_R14_0_Msk (0x1fUL << LCD_PAL68_R14_0_Pos) /*!< LCD PAL68: R14_0 Mask */\r
-#define LCD_PAL68_G14_0_Pos 21 /*!< LCD PAL68: G14_0 Position */\r
-#define LCD_PAL68_G14_0_Msk (0x1fUL << LCD_PAL68_G14_0_Pos) /*!< LCD PAL68: G14_0 Mask */\r
-#define LCD_PAL68_B14_0_Pos 26 /*!< LCD PAL68: B14_0 Position */\r
-#define LCD_PAL68_B14_0_Msk (0x1fUL << LCD_PAL68_B14_0_Pos) /*!< LCD PAL68: B14_0 Mask */\r
-#define LCD_PAL68_I1_Pos 31 /*!< LCD PAL68: I1 Position */\r
-#define LCD_PAL68_I1_Msk (0x01UL << LCD_PAL68_I1_Pos) /*!< LCD PAL68: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL69 -------------------------------------------\r
-#define LCD_PAL69_R04_0_Pos 0 /*!< LCD PAL69: R04_0 Position */\r
-#define LCD_PAL69_R04_0_Msk (0x1fUL << LCD_PAL69_R04_0_Pos) /*!< LCD PAL69: R04_0 Mask */\r
-#define LCD_PAL69_G04_0_Pos 5 /*!< LCD PAL69: G04_0 Position */\r
-#define LCD_PAL69_G04_0_Msk (0x1fUL << LCD_PAL69_G04_0_Pos) /*!< LCD PAL69: G04_0 Mask */\r
-#define LCD_PAL69_B04_0_Pos 10 /*!< LCD PAL69: B04_0 Position */\r
-#define LCD_PAL69_B04_0_Msk (0x1fUL << LCD_PAL69_B04_0_Pos) /*!< LCD PAL69: B04_0 Mask */\r
-#define LCD_PAL69_I0_Pos 15 /*!< LCD PAL69: I0 Position */\r
-#define LCD_PAL69_I0_Msk (0x01UL << LCD_PAL69_I0_Pos) /*!< LCD PAL69: I0 Mask */\r
-#define LCD_PAL69_R14_0_Pos 16 /*!< LCD PAL69: R14_0 Position */\r
-#define LCD_PAL69_R14_0_Msk (0x1fUL << LCD_PAL69_R14_0_Pos) /*!< LCD PAL69: R14_0 Mask */\r
-#define LCD_PAL69_G14_0_Pos 21 /*!< LCD PAL69: G14_0 Position */\r
-#define LCD_PAL69_G14_0_Msk (0x1fUL << LCD_PAL69_G14_0_Pos) /*!< LCD PAL69: G14_0 Mask */\r
-#define LCD_PAL69_B14_0_Pos 26 /*!< LCD PAL69: B14_0 Position */\r
-#define LCD_PAL69_B14_0_Msk (0x1fUL << LCD_PAL69_B14_0_Pos) /*!< LCD PAL69: B14_0 Mask */\r
-#define LCD_PAL69_I1_Pos 31 /*!< LCD PAL69: I1 Position */\r
-#define LCD_PAL69_I1_Msk (0x01UL << LCD_PAL69_I1_Pos) /*!< LCD PAL69: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL70 -------------------------------------------\r
-#define LCD_PAL70_R04_0_Pos 0 /*!< LCD PAL70: R04_0 Position */\r
-#define LCD_PAL70_R04_0_Msk (0x1fUL << LCD_PAL70_R04_0_Pos) /*!< LCD PAL70: R04_0 Mask */\r
-#define LCD_PAL70_G04_0_Pos 5 /*!< LCD PAL70: G04_0 Position */\r
-#define LCD_PAL70_G04_0_Msk (0x1fUL << LCD_PAL70_G04_0_Pos) /*!< LCD PAL70: G04_0 Mask */\r
-#define LCD_PAL70_B04_0_Pos 10 /*!< LCD PAL70: B04_0 Position */\r
-#define LCD_PAL70_B04_0_Msk (0x1fUL << LCD_PAL70_B04_0_Pos) /*!< LCD PAL70: B04_0 Mask */\r
-#define LCD_PAL70_I0_Pos 15 /*!< LCD PAL70: I0 Position */\r
-#define LCD_PAL70_I0_Msk (0x01UL << LCD_PAL70_I0_Pos) /*!< LCD PAL70: I0 Mask */\r
-#define LCD_PAL70_R14_0_Pos 16 /*!< LCD PAL70: R14_0 Position */\r
-#define LCD_PAL70_R14_0_Msk (0x1fUL << LCD_PAL70_R14_0_Pos) /*!< LCD PAL70: R14_0 Mask */\r
-#define LCD_PAL70_G14_0_Pos 21 /*!< LCD PAL70: G14_0 Position */\r
-#define LCD_PAL70_G14_0_Msk (0x1fUL << LCD_PAL70_G14_0_Pos) /*!< LCD PAL70: G14_0 Mask */\r
-#define LCD_PAL70_B14_0_Pos 26 /*!< LCD PAL70: B14_0 Position */\r
-#define LCD_PAL70_B14_0_Msk (0x1fUL << LCD_PAL70_B14_0_Pos) /*!< LCD PAL70: B14_0 Mask */\r
-#define LCD_PAL70_I1_Pos 31 /*!< LCD PAL70: I1 Position */\r
-#define LCD_PAL70_I1_Msk (0x01UL << LCD_PAL70_I1_Pos) /*!< LCD PAL70: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL71 -------------------------------------------\r
-#define LCD_PAL71_R04_0_Pos 0 /*!< LCD PAL71: R04_0 Position */\r
-#define LCD_PAL71_R04_0_Msk (0x1fUL << LCD_PAL71_R04_0_Pos) /*!< LCD PAL71: R04_0 Mask */\r
-#define LCD_PAL71_G04_0_Pos 5 /*!< LCD PAL71: G04_0 Position */\r
-#define LCD_PAL71_G04_0_Msk (0x1fUL << LCD_PAL71_G04_0_Pos) /*!< LCD PAL71: G04_0 Mask */\r
-#define LCD_PAL71_B04_0_Pos 10 /*!< LCD PAL71: B04_0 Position */\r
-#define LCD_PAL71_B04_0_Msk (0x1fUL << LCD_PAL71_B04_0_Pos) /*!< LCD PAL71: B04_0 Mask */\r
-#define LCD_PAL71_I0_Pos 15 /*!< LCD PAL71: I0 Position */\r
-#define LCD_PAL71_I0_Msk (0x01UL << LCD_PAL71_I0_Pos) /*!< LCD PAL71: I0 Mask */\r
-#define LCD_PAL71_R14_0_Pos 16 /*!< LCD PAL71: R14_0 Position */\r
-#define LCD_PAL71_R14_0_Msk (0x1fUL << LCD_PAL71_R14_0_Pos) /*!< LCD PAL71: R14_0 Mask */\r
-#define LCD_PAL71_G14_0_Pos 21 /*!< LCD PAL71: G14_0 Position */\r
-#define LCD_PAL71_G14_0_Msk (0x1fUL << LCD_PAL71_G14_0_Pos) /*!< LCD PAL71: G14_0 Mask */\r
-#define LCD_PAL71_B14_0_Pos 26 /*!< LCD PAL71: B14_0 Position */\r
-#define LCD_PAL71_B14_0_Msk (0x1fUL << LCD_PAL71_B14_0_Pos) /*!< LCD PAL71: B14_0 Mask */\r
-#define LCD_PAL71_I1_Pos 31 /*!< LCD PAL71: I1 Position */\r
-#define LCD_PAL71_I1_Msk (0x01UL << LCD_PAL71_I1_Pos) /*!< LCD PAL71: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL72 -------------------------------------------\r
-#define LCD_PAL72_R04_0_Pos 0 /*!< LCD PAL72: R04_0 Position */\r
-#define LCD_PAL72_R04_0_Msk (0x1fUL << LCD_PAL72_R04_0_Pos) /*!< LCD PAL72: R04_0 Mask */\r
-#define LCD_PAL72_G04_0_Pos 5 /*!< LCD PAL72: G04_0 Position */\r
-#define LCD_PAL72_G04_0_Msk (0x1fUL << LCD_PAL72_G04_0_Pos) /*!< LCD PAL72: G04_0 Mask */\r
-#define LCD_PAL72_B04_0_Pos 10 /*!< LCD PAL72: B04_0 Position */\r
-#define LCD_PAL72_B04_0_Msk (0x1fUL << LCD_PAL72_B04_0_Pos) /*!< LCD PAL72: B04_0 Mask */\r
-#define LCD_PAL72_I0_Pos 15 /*!< LCD PAL72: I0 Position */\r
-#define LCD_PAL72_I0_Msk (0x01UL << LCD_PAL72_I0_Pos) /*!< LCD PAL72: I0 Mask */\r
-#define LCD_PAL72_R14_0_Pos 16 /*!< LCD PAL72: R14_0 Position */\r
-#define LCD_PAL72_R14_0_Msk (0x1fUL << LCD_PAL72_R14_0_Pos) /*!< LCD PAL72: R14_0 Mask */\r
-#define LCD_PAL72_G14_0_Pos 21 /*!< LCD PAL72: G14_0 Position */\r
-#define LCD_PAL72_G14_0_Msk (0x1fUL << LCD_PAL72_G14_0_Pos) /*!< LCD PAL72: G14_0 Mask */\r
-#define LCD_PAL72_B14_0_Pos 26 /*!< LCD PAL72: B14_0 Position */\r
-#define LCD_PAL72_B14_0_Msk (0x1fUL << LCD_PAL72_B14_0_Pos) /*!< LCD PAL72: B14_0 Mask */\r
-#define LCD_PAL72_I1_Pos 31 /*!< LCD PAL72: I1 Position */\r
-#define LCD_PAL72_I1_Msk (0x01UL << LCD_PAL72_I1_Pos) /*!< LCD PAL72: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL73 -------------------------------------------\r
-#define LCD_PAL73_R04_0_Pos 0 /*!< LCD PAL73: R04_0 Position */\r
-#define LCD_PAL73_R04_0_Msk (0x1fUL << LCD_PAL73_R04_0_Pos) /*!< LCD PAL73: R04_0 Mask */\r
-#define LCD_PAL73_G04_0_Pos 5 /*!< LCD PAL73: G04_0 Position */\r
-#define LCD_PAL73_G04_0_Msk (0x1fUL << LCD_PAL73_G04_0_Pos) /*!< LCD PAL73: G04_0 Mask */\r
-#define LCD_PAL73_B04_0_Pos 10 /*!< LCD PAL73: B04_0 Position */\r
-#define LCD_PAL73_B04_0_Msk (0x1fUL << LCD_PAL73_B04_0_Pos) /*!< LCD PAL73: B04_0 Mask */\r
-#define LCD_PAL73_I0_Pos 15 /*!< LCD PAL73: I0 Position */\r
-#define LCD_PAL73_I0_Msk (0x01UL << LCD_PAL73_I0_Pos) /*!< LCD PAL73: I0 Mask */\r
-#define LCD_PAL73_R14_0_Pos 16 /*!< LCD PAL73: R14_0 Position */\r
-#define LCD_PAL73_R14_0_Msk (0x1fUL << LCD_PAL73_R14_0_Pos) /*!< LCD PAL73: R14_0 Mask */\r
-#define LCD_PAL73_G14_0_Pos 21 /*!< LCD PAL73: G14_0 Position */\r
-#define LCD_PAL73_G14_0_Msk (0x1fUL << LCD_PAL73_G14_0_Pos) /*!< LCD PAL73: G14_0 Mask */\r
-#define LCD_PAL73_B14_0_Pos 26 /*!< LCD PAL73: B14_0 Position */\r
-#define LCD_PAL73_B14_0_Msk (0x1fUL << LCD_PAL73_B14_0_Pos) /*!< LCD PAL73: B14_0 Mask */\r
-#define LCD_PAL73_I1_Pos 31 /*!< LCD PAL73: I1 Position */\r
-#define LCD_PAL73_I1_Msk (0x01UL << LCD_PAL73_I1_Pos) /*!< LCD PAL73: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL74 -------------------------------------------\r
-#define LCD_PAL74_R04_0_Pos 0 /*!< LCD PAL74: R04_0 Position */\r
-#define LCD_PAL74_R04_0_Msk (0x1fUL << LCD_PAL74_R04_0_Pos) /*!< LCD PAL74: R04_0 Mask */\r
-#define LCD_PAL74_G04_0_Pos 5 /*!< LCD PAL74: G04_0 Position */\r
-#define LCD_PAL74_G04_0_Msk (0x1fUL << LCD_PAL74_G04_0_Pos) /*!< LCD PAL74: G04_0 Mask */\r
-#define LCD_PAL74_B04_0_Pos 10 /*!< LCD PAL74: B04_0 Position */\r
-#define LCD_PAL74_B04_0_Msk (0x1fUL << LCD_PAL74_B04_0_Pos) /*!< LCD PAL74: B04_0 Mask */\r
-#define LCD_PAL74_I0_Pos 15 /*!< LCD PAL74: I0 Position */\r
-#define LCD_PAL74_I0_Msk (0x01UL << LCD_PAL74_I0_Pos) /*!< LCD PAL74: I0 Mask */\r
-#define LCD_PAL74_R14_0_Pos 16 /*!< LCD PAL74: R14_0 Position */\r
-#define LCD_PAL74_R14_0_Msk (0x1fUL << LCD_PAL74_R14_0_Pos) /*!< LCD PAL74: R14_0 Mask */\r
-#define LCD_PAL74_G14_0_Pos 21 /*!< LCD PAL74: G14_0 Position */\r
-#define LCD_PAL74_G14_0_Msk (0x1fUL << LCD_PAL74_G14_0_Pos) /*!< LCD PAL74: G14_0 Mask */\r
-#define LCD_PAL74_B14_0_Pos 26 /*!< LCD PAL74: B14_0 Position */\r
-#define LCD_PAL74_B14_0_Msk (0x1fUL << LCD_PAL74_B14_0_Pos) /*!< LCD PAL74: B14_0 Mask */\r
-#define LCD_PAL74_I1_Pos 31 /*!< LCD PAL74: I1 Position */\r
-#define LCD_PAL74_I1_Msk (0x01UL << LCD_PAL74_I1_Pos) /*!< LCD PAL74: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL75 -------------------------------------------\r
-#define LCD_PAL75_R04_0_Pos 0 /*!< LCD PAL75: R04_0 Position */\r
-#define LCD_PAL75_R04_0_Msk (0x1fUL << LCD_PAL75_R04_0_Pos) /*!< LCD PAL75: R04_0 Mask */\r
-#define LCD_PAL75_G04_0_Pos 5 /*!< LCD PAL75: G04_0 Position */\r
-#define LCD_PAL75_G04_0_Msk (0x1fUL << LCD_PAL75_G04_0_Pos) /*!< LCD PAL75: G04_0 Mask */\r
-#define LCD_PAL75_B04_0_Pos 10 /*!< LCD PAL75: B04_0 Position */\r
-#define LCD_PAL75_B04_0_Msk (0x1fUL << LCD_PAL75_B04_0_Pos) /*!< LCD PAL75: B04_0 Mask */\r
-#define LCD_PAL75_I0_Pos 15 /*!< LCD PAL75: I0 Position */\r
-#define LCD_PAL75_I0_Msk (0x01UL << LCD_PAL75_I0_Pos) /*!< LCD PAL75: I0 Mask */\r
-#define LCD_PAL75_R14_0_Pos 16 /*!< LCD PAL75: R14_0 Position */\r
-#define LCD_PAL75_R14_0_Msk (0x1fUL << LCD_PAL75_R14_0_Pos) /*!< LCD PAL75: R14_0 Mask */\r
-#define LCD_PAL75_G14_0_Pos 21 /*!< LCD PAL75: G14_0 Position */\r
-#define LCD_PAL75_G14_0_Msk (0x1fUL << LCD_PAL75_G14_0_Pos) /*!< LCD PAL75: G14_0 Mask */\r
-#define LCD_PAL75_B14_0_Pos 26 /*!< LCD PAL75: B14_0 Position */\r
-#define LCD_PAL75_B14_0_Msk (0x1fUL << LCD_PAL75_B14_0_Pos) /*!< LCD PAL75: B14_0 Mask */\r
-#define LCD_PAL75_I1_Pos 31 /*!< LCD PAL75: I1 Position */\r
-#define LCD_PAL75_I1_Msk (0x01UL << LCD_PAL75_I1_Pos) /*!< LCD PAL75: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL76 -------------------------------------------\r
-#define LCD_PAL76_R04_0_Pos 0 /*!< LCD PAL76: R04_0 Position */\r
-#define LCD_PAL76_R04_0_Msk (0x1fUL << LCD_PAL76_R04_0_Pos) /*!< LCD PAL76: R04_0 Mask */\r
-#define LCD_PAL76_G04_0_Pos 5 /*!< LCD PAL76: G04_0 Position */\r
-#define LCD_PAL76_G04_0_Msk (0x1fUL << LCD_PAL76_G04_0_Pos) /*!< LCD PAL76: G04_0 Mask */\r
-#define LCD_PAL76_B04_0_Pos 10 /*!< LCD PAL76: B04_0 Position */\r
-#define LCD_PAL76_B04_0_Msk (0x1fUL << LCD_PAL76_B04_0_Pos) /*!< LCD PAL76: B04_0 Mask */\r
-#define LCD_PAL76_I0_Pos 15 /*!< LCD PAL76: I0 Position */\r
-#define LCD_PAL76_I0_Msk (0x01UL << LCD_PAL76_I0_Pos) /*!< LCD PAL76: I0 Mask */\r
-#define LCD_PAL76_R14_0_Pos 16 /*!< LCD PAL76: R14_0 Position */\r
-#define LCD_PAL76_R14_0_Msk (0x1fUL << LCD_PAL76_R14_0_Pos) /*!< LCD PAL76: R14_0 Mask */\r
-#define LCD_PAL76_G14_0_Pos 21 /*!< LCD PAL76: G14_0 Position */\r
-#define LCD_PAL76_G14_0_Msk (0x1fUL << LCD_PAL76_G14_0_Pos) /*!< LCD PAL76: G14_0 Mask */\r
-#define LCD_PAL76_B14_0_Pos 26 /*!< LCD PAL76: B14_0 Position */\r
-#define LCD_PAL76_B14_0_Msk (0x1fUL << LCD_PAL76_B14_0_Pos) /*!< LCD PAL76: B14_0 Mask */\r
-#define LCD_PAL76_I1_Pos 31 /*!< LCD PAL76: I1 Position */\r
-#define LCD_PAL76_I1_Msk (0x01UL << LCD_PAL76_I1_Pos) /*!< LCD PAL76: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL77 -------------------------------------------\r
-#define LCD_PAL77_R04_0_Pos 0 /*!< LCD PAL77: R04_0 Position */\r
-#define LCD_PAL77_R04_0_Msk (0x1fUL << LCD_PAL77_R04_0_Pos) /*!< LCD PAL77: R04_0 Mask */\r
-#define LCD_PAL77_G04_0_Pos 5 /*!< LCD PAL77: G04_0 Position */\r
-#define LCD_PAL77_G04_0_Msk (0x1fUL << LCD_PAL77_G04_0_Pos) /*!< LCD PAL77: G04_0 Mask */\r
-#define LCD_PAL77_B04_0_Pos 10 /*!< LCD PAL77: B04_0 Position */\r
-#define LCD_PAL77_B04_0_Msk (0x1fUL << LCD_PAL77_B04_0_Pos) /*!< LCD PAL77: B04_0 Mask */\r
-#define LCD_PAL77_I0_Pos 15 /*!< LCD PAL77: I0 Position */\r
-#define LCD_PAL77_I0_Msk (0x01UL << LCD_PAL77_I0_Pos) /*!< LCD PAL77: I0 Mask */\r
-#define LCD_PAL77_R14_0_Pos 16 /*!< LCD PAL77: R14_0 Position */\r
-#define LCD_PAL77_R14_0_Msk (0x1fUL << LCD_PAL77_R14_0_Pos) /*!< LCD PAL77: R14_0 Mask */\r
-#define LCD_PAL77_G14_0_Pos 21 /*!< LCD PAL77: G14_0 Position */\r
-#define LCD_PAL77_G14_0_Msk (0x1fUL << LCD_PAL77_G14_0_Pos) /*!< LCD PAL77: G14_0 Mask */\r
-#define LCD_PAL77_B14_0_Pos 26 /*!< LCD PAL77: B14_0 Position */\r
-#define LCD_PAL77_B14_0_Msk (0x1fUL << LCD_PAL77_B14_0_Pos) /*!< LCD PAL77: B14_0 Mask */\r
-#define LCD_PAL77_I1_Pos 31 /*!< LCD PAL77: I1 Position */\r
-#define LCD_PAL77_I1_Msk (0x01UL << LCD_PAL77_I1_Pos) /*!< LCD PAL77: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL78 -------------------------------------------\r
-#define LCD_PAL78_R04_0_Pos 0 /*!< LCD PAL78: R04_0 Position */\r
-#define LCD_PAL78_R04_0_Msk (0x1fUL << LCD_PAL78_R04_0_Pos) /*!< LCD PAL78: R04_0 Mask */\r
-#define LCD_PAL78_G04_0_Pos 5 /*!< LCD PAL78: G04_0 Position */\r
-#define LCD_PAL78_G04_0_Msk (0x1fUL << LCD_PAL78_G04_0_Pos) /*!< LCD PAL78: G04_0 Mask */\r
-#define LCD_PAL78_B04_0_Pos 10 /*!< LCD PAL78: B04_0 Position */\r
-#define LCD_PAL78_B04_0_Msk (0x1fUL << LCD_PAL78_B04_0_Pos) /*!< LCD PAL78: B04_0 Mask */\r
-#define LCD_PAL78_I0_Pos 15 /*!< LCD PAL78: I0 Position */\r
-#define LCD_PAL78_I0_Msk (0x01UL << LCD_PAL78_I0_Pos) /*!< LCD PAL78: I0 Mask */\r
-#define LCD_PAL78_R14_0_Pos 16 /*!< LCD PAL78: R14_0 Position */\r
-#define LCD_PAL78_R14_0_Msk (0x1fUL << LCD_PAL78_R14_0_Pos) /*!< LCD PAL78: R14_0 Mask */\r
-#define LCD_PAL78_G14_0_Pos 21 /*!< LCD PAL78: G14_0 Position */\r
-#define LCD_PAL78_G14_0_Msk (0x1fUL << LCD_PAL78_G14_0_Pos) /*!< LCD PAL78: G14_0 Mask */\r
-#define LCD_PAL78_B14_0_Pos 26 /*!< LCD PAL78: B14_0 Position */\r
-#define LCD_PAL78_B14_0_Msk (0x1fUL << LCD_PAL78_B14_0_Pos) /*!< LCD PAL78: B14_0 Mask */\r
-#define LCD_PAL78_I1_Pos 31 /*!< LCD PAL78: I1 Position */\r
-#define LCD_PAL78_I1_Msk (0x01UL << LCD_PAL78_I1_Pos) /*!< LCD PAL78: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL79 -------------------------------------------\r
-#define LCD_PAL79_R04_0_Pos 0 /*!< LCD PAL79: R04_0 Position */\r
-#define LCD_PAL79_R04_0_Msk (0x1fUL << LCD_PAL79_R04_0_Pos) /*!< LCD PAL79: R04_0 Mask */\r
-#define LCD_PAL79_G04_0_Pos 5 /*!< LCD PAL79: G04_0 Position */\r
-#define LCD_PAL79_G04_0_Msk (0x1fUL << LCD_PAL79_G04_0_Pos) /*!< LCD PAL79: G04_0 Mask */\r
-#define LCD_PAL79_B04_0_Pos 10 /*!< LCD PAL79: B04_0 Position */\r
-#define LCD_PAL79_B04_0_Msk (0x1fUL << LCD_PAL79_B04_0_Pos) /*!< LCD PAL79: B04_0 Mask */\r
-#define LCD_PAL79_I0_Pos 15 /*!< LCD PAL79: I0 Position */\r
-#define LCD_PAL79_I0_Msk (0x01UL << LCD_PAL79_I0_Pos) /*!< LCD PAL79: I0 Mask */\r
-#define LCD_PAL79_R14_0_Pos 16 /*!< LCD PAL79: R14_0 Position */\r
-#define LCD_PAL79_R14_0_Msk (0x1fUL << LCD_PAL79_R14_0_Pos) /*!< LCD PAL79: R14_0 Mask */\r
-#define LCD_PAL79_G14_0_Pos 21 /*!< LCD PAL79: G14_0 Position */\r
-#define LCD_PAL79_G14_0_Msk (0x1fUL << LCD_PAL79_G14_0_Pos) /*!< LCD PAL79: G14_0 Mask */\r
-#define LCD_PAL79_B14_0_Pos 26 /*!< LCD PAL79: B14_0 Position */\r
-#define LCD_PAL79_B14_0_Msk (0x1fUL << LCD_PAL79_B14_0_Pos) /*!< LCD PAL79: B14_0 Mask */\r
-#define LCD_PAL79_I1_Pos 31 /*!< LCD PAL79: I1 Position */\r
-#define LCD_PAL79_I1_Msk (0x01UL << LCD_PAL79_I1_Pos) /*!< LCD PAL79: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL80 -------------------------------------------\r
-#define LCD_PAL80_R04_0_Pos 0 /*!< LCD PAL80: R04_0 Position */\r
-#define LCD_PAL80_R04_0_Msk (0x1fUL << LCD_PAL80_R04_0_Pos) /*!< LCD PAL80: R04_0 Mask */\r
-#define LCD_PAL80_G04_0_Pos 5 /*!< LCD PAL80: G04_0 Position */\r
-#define LCD_PAL80_G04_0_Msk (0x1fUL << LCD_PAL80_G04_0_Pos) /*!< LCD PAL80: G04_0 Mask */\r
-#define LCD_PAL80_B04_0_Pos 10 /*!< LCD PAL80: B04_0 Position */\r
-#define LCD_PAL80_B04_0_Msk (0x1fUL << LCD_PAL80_B04_0_Pos) /*!< LCD PAL80: B04_0 Mask */\r
-#define LCD_PAL80_I0_Pos 15 /*!< LCD PAL80: I0 Position */\r
-#define LCD_PAL80_I0_Msk (0x01UL << LCD_PAL80_I0_Pos) /*!< LCD PAL80: I0 Mask */\r
-#define LCD_PAL80_R14_0_Pos 16 /*!< LCD PAL80: R14_0 Position */\r
-#define LCD_PAL80_R14_0_Msk (0x1fUL << LCD_PAL80_R14_0_Pos) /*!< LCD PAL80: R14_0 Mask */\r
-#define LCD_PAL80_G14_0_Pos 21 /*!< LCD PAL80: G14_0 Position */\r
-#define LCD_PAL80_G14_0_Msk (0x1fUL << LCD_PAL80_G14_0_Pos) /*!< LCD PAL80: G14_0 Mask */\r
-#define LCD_PAL80_B14_0_Pos 26 /*!< LCD PAL80: B14_0 Position */\r
-#define LCD_PAL80_B14_0_Msk (0x1fUL << LCD_PAL80_B14_0_Pos) /*!< LCD PAL80: B14_0 Mask */\r
-#define LCD_PAL80_I1_Pos 31 /*!< LCD PAL80: I1 Position */\r
-#define LCD_PAL80_I1_Msk (0x01UL << LCD_PAL80_I1_Pos) /*!< LCD PAL80: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL81 -------------------------------------------\r
-#define LCD_PAL81_R04_0_Pos 0 /*!< LCD PAL81: R04_0 Position */\r
-#define LCD_PAL81_R04_0_Msk (0x1fUL << LCD_PAL81_R04_0_Pos) /*!< LCD PAL81: R04_0 Mask */\r
-#define LCD_PAL81_G04_0_Pos 5 /*!< LCD PAL81: G04_0 Position */\r
-#define LCD_PAL81_G04_0_Msk (0x1fUL << LCD_PAL81_G04_0_Pos) /*!< LCD PAL81: G04_0 Mask */\r
-#define LCD_PAL81_B04_0_Pos 10 /*!< LCD PAL81: B04_0 Position */\r
-#define LCD_PAL81_B04_0_Msk (0x1fUL << LCD_PAL81_B04_0_Pos) /*!< LCD PAL81: B04_0 Mask */\r
-#define LCD_PAL81_I0_Pos 15 /*!< LCD PAL81: I0 Position */\r
-#define LCD_PAL81_I0_Msk (0x01UL << LCD_PAL81_I0_Pos) /*!< LCD PAL81: I0 Mask */\r
-#define LCD_PAL81_R14_0_Pos 16 /*!< LCD PAL81: R14_0 Position */\r
-#define LCD_PAL81_R14_0_Msk (0x1fUL << LCD_PAL81_R14_0_Pos) /*!< LCD PAL81: R14_0 Mask */\r
-#define LCD_PAL81_G14_0_Pos 21 /*!< LCD PAL81: G14_0 Position */\r
-#define LCD_PAL81_G14_0_Msk (0x1fUL << LCD_PAL81_G14_0_Pos) /*!< LCD PAL81: G14_0 Mask */\r
-#define LCD_PAL81_B14_0_Pos 26 /*!< LCD PAL81: B14_0 Position */\r
-#define LCD_PAL81_B14_0_Msk (0x1fUL << LCD_PAL81_B14_0_Pos) /*!< LCD PAL81: B14_0 Mask */\r
-#define LCD_PAL81_I1_Pos 31 /*!< LCD PAL81: I1 Position */\r
-#define LCD_PAL81_I1_Msk (0x01UL << LCD_PAL81_I1_Pos) /*!< LCD PAL81: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL82 -------------------------------------------\r
-#define LCD_PAL82_R04_0_Pos 0 /*!< LCD PAL82: R04_0 Position */\r
-#define LCD_PAL82_R04_0_Msk (0x1fUL << LCD_PAL82_R04_0_Pos) /*!< LCD PAL82: R04_0 Mask */\r
-#define LCD_PAL82_G04_0_Pos 5 /*!< LCD PAL82: G04_0 Position */\r
-#define LCD_PAL82_G04_0_Msk (0x1fUL << LCD_PAL82_G04_0_Pos) /*!< LCD PAL82: G04_0 Mask */\r
-#define LCD_PAL82_B04_0_Pos 10 /*!< LCD PAL82: B04_0 Position */\r
-#define LCD_PAL82_B04_0_Msk (0x1fUL << LCD_PAL82_B04_0_Pos) /*!< LCD PAL82: B04_0 Mask */\r
-#define LCD_PAL82_I0_Pos 15 /*!< LCD PAL82: I0 Position */\r
-#define LCD_PAL82_I0_Msk (0x01UL << LCD_PAL82_I0_Pos) /*!< LCD PAL82: I0 Mask */\r
-#define LCD_PAL82_R14_0_Pos 16 /*!< LCD PAL82: R14_0 Position */\r
-#define LCD_PAL82_R14_0_Msk (0x1fUL << LCD_PAL82_R14_0_Pos) /*!< LCD PAL82: R14_0 Mask */\r
-#define LCD_PAL82_G14_0_Pos 21 /*!< LCD PAL82: G14_0 Position */\r
-#define LCD_PAL82_G14_0_Msk (0x1fUL << LCD_PAL82_G14_0_Pos) /*!< LCD PAL82: G14_0 Mask */\r
-#define LCD_PAL82_B14_0_Pos 26 /*!< LCD PAL82: B14_0 Position */\r
-#define LCD_PAL82_B14_0_Msk (0x1fUL << LCD_PAL82_B14_0_Pos) /*!< LCD PAL82: B14_0 Mask */\r
-#define LCD_PAL82_I1_Pos 31 /*!< LCD PAL82: I1 Position */\r
-#define LCD_PAL82_I1_Msk (0x01UL << LCD_PAL82_I1_Pos) /*!< LCD PAL82: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL83 -------------------------------------------\r
-#define LCD_PAL83_R04_0_Pos 0 /*!< LCD PAL83: R04_0 Position */\r
-#define LCD_PAL83_R04_0_Msk (0x1fUL << LCD_PAL83_R04_0_Pos) /*!< LCD PAL83: R04_0 Mask */\r
-#define LCD_PAL83_G04_0_Pos 5 /*!< LCD PAL83: G04_0 Position */\r
-#define LCD_PAL83_G04_0_Msk (0x1fUL << LCD_PAL83_G04_0_Pos) /*!< LCD PAL83: G04_0 Mask */\r
-#define LCD_PAL83_B04_0_Pos 10 /*!< LCD PAL83: B04_0 Position */\r
-#define LCD_PAL83_B04_0_Msk (0x1fUL << LCD_PAL83_B04_0_Pos) /*!< LCD PAL83: B04_0 Mask */\r
-#define LCD_PAL83_I0_Pos 15 /*!< LCD PAL83: I0 Position */\r
-#define LCD_PAL83_I0_Msk (0x01UL << LCD_PAL83_I0_Pos) /*!< LCD PAL83: I0 Mask */\r
-#define LCD_PAL83_R14_0_Pos 16 /*!< LCD PAL83: R14_0 Position */\r
-#define LCD_PAL83_R14_0_Msk (0x1fUL << LCD_PAL83_R14_0_Pos) /*!< LCD PAL83: R14_0 Mask */\r
-#define LCD_PAL83_G14_0_Pos 21 /*!< LCD PAL83: G14_0 Position */\r
-#define LCD_PAL83_G14_0_Msk (0x1fUL << LCD_PAL83_G14_0_Pos) /*!< LCD PAL83: G14_0 Mask */\r
-#define LCD_PAL83_B14_0_Pos 26 /*!< LCD PAL83: B14_0 Position */\r
-#define LCD_PAL83_B14_0_Msk (0x1fUL << LCD_PAL83_B14_0_Pos) /*!< LCD PAL83: B14_0 Mask */\r
-#define LCD_PAL83_I1_Pos 31 /*!< LCD PAL83: I1 Position */\r
-#define LCD_PAL83_I1_Msk (0x01UL << LCD_PAL83_I1_Pos) /*!< LCD PAL83: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL84 -------------------------------------------\r
-#define LCD_PAL84_R04_0_Pos 0 /*!< LCD PAL84: R04_0 Position */\r
-#define LCD_PAL84_R04_0_Msk (0x1fUL << LCD_PAL84_R04_0_Pos) /*!< LCD PAL84: R04_0 Mask */\r
-#define LCD_PAL84_G04_0_Pos 5 /*!< LCD PAL84: G04_0 Position */\r
-#define LCD_PAL84_G04_0_Msk (0x1fUL << LCD_PAL84_G04_0_Pos) /*!< LCD PAL84: G04_0 Mask */\r
-#define LCD_PAL84_B04_0_Pos 10 /*!< LCD PAL84: B04_0 Position */\r
-#define LCD_PAL84_B04_0_Msk (0x1fUL << LCD_PAL84_B04_0_Pos) /*!< LCD PAL84: B04_0 Mask */\r
-#define LCD_PAL84_I0_Pos 15 /*!< LCD PAL84: I0 Position */\r
-#define LCD_PAL84_I0_Msk (0x01UL << LCD_PAL84_I0_Pos) /*!< LCD PAL84: I0 Mask */\r
-#define LCD_PAL84_R14_0_Pos 16 /*!< LCD PAL84: R14_0 Position */\r
-#define LCD_PAL84_R14_0_Msk (0x1fUL << LCD_PAL84_R14_0_Pos) /*!< LCD PAL84: R14_0 Mask */\r
-#define LCD_PAL84_G14_0_Pos 21 /*!< LCD PAL84: G14_0 Position */\r
-#define LCD_PAL84_G14_0_Msk (0x1fUL << LCD_PAL84_G14_0_Pos) /*!< LCD PAL84: G14_0 Mask */\r
-#define LCD_PAL84_B14_0_Pos 26 /*!< LCD PAL84: B14_0 Position */\r
-#define LCD_PAL84_B14_0_Msk (0x1fUL << LCD_PAL84_B14_0_Pos) /*!< LCD PAL84: B14_0 Mask */\r
-#define LCD_PAL84_I1_Pos 31 /*!< LCD PAL84: I1 Position */\r
-#define LCD_PAL84_I1_Msk (0x01UL << LCD_PAL84_I1_Pos) /*!< LCD PAL84: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL85 -------------------------------------------\r
-#define LCD_PAL85_R04_0_Pos 0 /*!< LCD PAL85: R04_0 Position */\r
-#define LCD_PAL85_R04_0_Msk (0x1fUL << LCD_PAL85_R04_0_Pos) /*!< LCD PAL85: R04_0 Mask */\r
-#define LCD_PAL85_G04_0_Pos 5 /*!< LCD PAL85: G04_0 Position */\r
-#define LCD_PAL85_G04_0_Msk (0x1fUL << LCD_PAL85_G04_0_Pos) /*!< LCD PAL85: G04_0 Mask */\r
-#define LCD_PAL85_B04_0_Pos 10 /*!< LCD PAL85: B04_0 Position */\r
-#define LCD_PAL85_B04_0_Msk (0x1fUL << LCD_PAL85_B04_0_Pos) /*!< LCD PAL85: B04_0 Mask */\r
-#define LCD_PAL85_I0_Pos 15 /*!< LCD PAL85: I0 Position */\r
-#define LCD_PAL85_I0_Msk (0x01UL << LCD_PAL85_I0_Pos) /*!< LCD PAL85: I0 Mask */\r
-#define LCD_PAL85_R14_0_Pos 16 /*!< LCD PAL85: R14_0 Position */\r
-#define LCD_PAL85_R14_0_Msk (0x1fUL << LCD_PAL85_R14_0_Pos) /*!< LCD PAL85: R14_0 Mask */\r
-#define LCD_PAL85_G14_0_Pos 21 /*!< LCD PAL85: G14_0 Position */\r
-#define LCD_PAL85_G14_0_Msk (0x1fUL << LCD_PAL85_G14_0_Pos) /*!< LCD PAL85: G14_0 Mask */\r
-#define LCD_PAL85_B14_0_Pos 26 /*!< LCD PAL85: B14_0 Position */\r
-#define LCD_PAL85_B14_0_Msk (0x1fUL << LCD_PAL85_B14_0_Pos) /*!< LCD PAL85: B14_0 Mask */\r
-#define LCD_PAL85_I1_Pos 31 /*!< LCD PAL85: I1 Position */\r
-#define LCD_PAL85_I1_Msk (0x01UL << LCD_PAL85_I1_Pos) /*!< LCD PAL85: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL86 -------------------------------------------\r
-#define LCD_PAL86_R04_0_Pos 0 /*!< LCD PAL86: R04_0 Position */\r
-#define LCD_PAL86_R04_0_Msk (0x1fUL << LCD_PAL86_R04_0_Pos) /*!< LCD PAL86: R04_0 Mask */\r
-#define LCD_PAL86_G04_0_Pos 5 /*!< LCD PAL86: G04_0 Position */\r
-#define LCD_PAL86_G04_0_Msk (0x1fUL << LCD_PAL86_G04_0_Pos) /*!< LCD PAL86: G04_0 Mask */\r
-#define LCD_PAL86_B04_0_Pos 10 /*!< LCD PAL86: B04_0 Position */\r
-#define LCD_PAL86_B04_0_Msk (0x1fUL << LCD_PAL86_B04_0_Pos) /*!< LCD PAL86: B04_0 Mask */\r
-#define LCD_PAL86_I0_Pos 15 /*!< LCD PAL86: I0 Position */\r
-#define LCD_PAL86_I0_Msk (0x01UL << LCD_PAL86_I0_Pos) /*!< LCD PAL86: I0 Mask */\r
-#define LCD_PAL86_R14_0_Pos 16 /*!< LCD PAL86: R14_0 Position */\r
-#define LCD_PAL86_R14_0_Msk (0x1fUL << LCD_PAL86_R14_0_Pos) /*!< LCD PAL86: R14_0 Mask */\r
-#define LCD_PAL86_G14_0_Pos 21 /*!< LCD PAL86: G14_0 Position */\r
-#define LCD_PAL86_G14_0_Msk (0x1fUL << LCD_PAL86_G14_0_Pos) /*!< LCD PAL86: G14_0 Mask */\r
-#define LCD_PAL86_B14_0_Pos 26 /*!< LCD PAL86: B14_0 Position */\r
-#define LCD_PAL86_B14_0_Msk (0x1fUL << LCD_PAL86_B14_0_Pos) /*!< LCD PAL86: B14_0 Mask */\r
-#define LCD_PAL86_I1_Pos 31 /*!< LCD PAL86: I1 Position */\r
-#define LCD_PAL86_I1_Msk (0x01UL << LCD_PAL86_I1_Pos) /*!< LCD PAL86: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL87 -------------------------------------------\r
-#define LCD_PAL87_R04_0_Pos 0 /*!< LCD PAL87: R04_0 Position */\r
-#define LCD_PAL87_R04_0_Msk (0x1fUL << LCD_PAL87_R04_0_Pos) /*!< LCD PAL87: R04_0 Mask */\r
-#define LCD_PAL87_G04_0_Pos 5 /*!< LCD PAL87: G04_0 Position */\r
-#define LCD_PAL87_G04_0_Msk (0x1fUL << LCD_PAL87_G04_0_Pos) /*!< LCD PAL87: G04_0 Mask */\r
-#define LCD_PAL87_B04_0_Pos 10 /*!< LCD PAL87: B04_0 Position */\r
-#define LCD_PAL87_B04_0_Msk (0x1fUL << LCD_PAL87_B04_0_Pos) /*!< LCD PAL87: B04_0 Mask */\r
-#define LCD_PAL87_I0_Pos 15 /*!< LCD PAL87: I0 Position */\r
-#define LCD_PAL87_I0_Msk (0x01UL << LCD_PAL87_I0_Pos) /*!< LCD PAL87: I0 Mask */\r
-#define LCD_PAL87_R14_0_Pos 16 /*!< LCD PAL87: R14_0 Position */\r
-#define LCD_PAL87_R14_0_Msk (0x1fUL << LCD_PAL87_R14_0_Pos) /*!< LCD PAL87: R14_0 Mask */\r
-#define LCD_PAL87_G14_0_Pos 21 /*!< LCD PAL87: G14_0 Position */\r
-#define LCD_PAL87_G14_0_Msk (0x1fUL << LCD_PAL87_G14_0_Pos) /*!< LCD PAL87: G14_0 Mask */\r
-#define LCD_PAL87_B14_0_Pos 26 /*!< LCD PAL87: B14_0 Position */\r
-#define LCD_PAL87_B14_0_Msk (0x1fUL << LCD_PAL87_B14_0_Pos) /*!< LCD PAL87: B14_0 Mask */\r
-#define LCD_PAL87_I1_Pos 31 /*!< LCD PAL87: I1 Position */\r
-#define LCD_PAL87_I1_Msk (0x01UL << LCD_PAL87_I1_Pos) /*!< LCD PAL87: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL88 -------------------------------------------\r
-#define LCD_PAL88_R04_0_Pos 0 /*!< LCD PAL88: R04_0 Position */\r
-#define LCD_PAL88_R04_0_Msk (0x1fUL << LCD_PAL88_R04_0_Pos) /*!< LCD PAL88: R04_0 Mask */\r
-#define LCD_PAL88_G04_0_Pos 5 /*!< LCD PAL88: G04_0 Position */\r
-#define LCD_PAL88_G04_0_Msk (0x1fUL << LCD_PAL88_G04_0_Pos) /*!< LCD PAL88: G04_0 Mask */\r
-#define LCD_PAL88_B04_0_Pos 10 /*!< LCD PAL88: B04_0 Position */\r
-#define LCD_PAL88_B04_0_Msk (0x1fUL << LCD_PAL88_B04_0_Pos) /*!< LCD PAL88: B04_0 Mask */\r
-#define LCD_PAL88_I0_Pos 15 /*!< LCD PAL88: I0 Position */\r
-#define LCD_PAL88_I0_Msk (0x01UL << LCD_PAL88_I0_Pos) /*!< LCD PAL88: I0 Mask */\r
-#define LCD_PAL88_R14_0_Pos 16 /*!< LCD PAL88: R14_0 Position */\r
-#define LCD_PAL88_R14_0_Msk (0x1fUL << LCD_PAL88_R14_0_Pos) /*!< LCD PAL88: R14_0 Mask */\r
-#define LCD_PAL88_G14_0_Pos 21 /*!< LCD PAL88: G14_0 Position */\r
-#define LCD_PAL88_G14_0_Msk (0x1fUL << LCD_PAL88_G14_0_Pos) /*!< LCD PAL88: G14_0 Mask */\r
-#define LCD_PAL88_B14_0_Pos 26 /*!< LCD PAL88: B14_0 Position */\r
-#define LCD_PAL88_B14_0_Msk (0x1fUL << LCD_PAL88_B14_0_Pos) /*!< LCD PAL88: B14_0 Mask */\r
-#define LCD_PAL88_I1_Pos 31 /*!< LCD PAL88: I1 Position */\r
-#define LCD_PAL88_I1_Msk (0x01UL << LCD_PAL88_I1_Pos) /*!< LCD PAL88: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL89 -------------------------------------------\r
-#define LCD_PAL89_R04_0_Pos 0 /*!< LCD PAL89: R04_0 Position */\r
-#define LCD_PAL89_R04_0_Msk (0x1fUL << LCD_PAL89_R04_0_Pos) /*!< LCD PAL89: R04_0 Mask */\r
-#define LCD_PAL89_G04_0_Pos 5 /*!< LCD PAL89: G04_0 Position */\r
-#define LCD_PAL89_G04_0_Msk (0x1fUL << LCD_PAL89_G04_0_Pos) /*!< LCD PAL89: G04_0 Mask */\r
-#define LCD_PAL89_B04_0_Pos 10 /*!< LCD PAL89: B04_0 Position */\r
-#define LCD_PAL89_B04_0_Msk (0x1fUL << LCD_PAL89_B04_0_Pos) /*!< LCD PAL89: B04_0 Mask */\r
-#define LCD_PAL89_I0_Pos 15 /*!< LCD PAL89: I0 Position */\r
-#define LCD_PAL89_I0_Msk (0x01UL << LCD_PAL89_I0_Pos) /*!< LCD PAL89: I0 Mask */\r
-#define LCD_PAL89_R14_0_Pos 16 /*!< LCD PAL89: R14_0 Position */\r
-#define LCD_PAL89_R14_0_Msk (0x1fUL << LCD_PAL89_R14_0_Pos) /*!< LCD PAL89: R14_0 Mask */\r
-#define LCD_PAL89_G14_0_Pos 21 /*!< LCD PAL89: G14_0 Position */\r
-#define LCD_PAL89_G14_0_Msk (0x1fUL << LCD_PAL89_G14_0_Pos) /*!< LCD PAL89: G14_0 Mask */\r
-#define LCD_PAL89_B14_0_Pos 26 /*!< LCD PAL89: B14_0 Position */\r
-#define LCD_PAL89_B14_0_Msk (0x1fUL << LCD_PAL89_B14_0_Pos) /*!< LCD PAL89: B14_0 Mask */\r
-#define LCD_PAL89_I1_Pos 31 /*!< LCD PAL89: I1 Position */\r
-#define LCD_PAL89_I1_Msk (0x01UL << LCD_PAL89_I1_Pos) /*!< LCD PAL89: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL90 -------------------------------------------\r
-#define LCD_PAL90_R04_0_Pos 0 /*!< LCD PAL90: R04_0 Position */\r
-#define LCD_PAL90_R04_0_Msk (0x1fUL << LCD_PAL90_R04_0_Pos) /*!< LCD PAL90: R04_0 Mask */\r
-#define LCD_PAL90_G04_0_Pos 5 /*!< LCD PAL90: G04_0 Position */\r
-#define LCD_PAL90_G04_0_Msk (0x1fUL << LCD_PAL90_G04_0_Pos) /*!< LCD PAL90: G04_0 Mask */\r
-#define LCD_PAL90_B04_0_Pos 10 /*!< LCD PAL90: B04_0 Position */\r
-#define LCD_PAL90_B04_0_Msk (0x1fUL << LCD_PAL90_B04_0_Pos) /*!< LCD PAL90: B04_0 Mask */\r
-#define LCD_PAL90_I0_Pos 15 /*!< LCD PAL90: I0 Position */\r
-#define LCD_PAL90_I0_Msk (0x01UL << LCD_PAL90_I0_Pos) /*!< LCD PAL90: I0 Mask */\r
-#define LCD_PAL90_R14_0_Pos 16 /*!< LCD PAL90: R14_0 Position */\r
-#define LCD_PAL90_R14_0_Msk (0x1fUL << LCD_PAL90_R14_0_Pos) /*!< LCD PAL90: R14_0 Mask */\r
-#define LCD_PAL90_G14_0_Pos 21 /*!< LCD PAL90: G14_0 Position */\r
-#define LCD_PAL90_G14_0_Msk (0x1fUL << LCD_PAL90_G14_0_Pos) /*!< LCD PAL90: G14_0 Mask */\r
-#define LCD_PAL90_B14_0_Pos 26 /*!< LCD PAL90: B14_0 Position */\r
-#define LCD_PAL90_B14_0_Msk (0x1fUL << LCD_PAL90_B14_0_Pos) /*!< LCD PAL90: B14_0 Mask */\r
-#define LCD_PAL90_I1_Pos 31 /*!< LCD PAL90: I1 Position */\r
-#define LCD_PAL90_I1_Msk (0x01UL << LCD_PAL90_I1_Pos) /*!< LCD PAL90: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL91 -------------------------------------------\r
-#define LCD_PAL91_R04_0_Pos 0 /*!< LCD PAL91: R04_0 Position */\r
-#define LCD_PAL91_R04_0_Msk (0x1fUL << LCD_PAL91_R04_0_Pos) /*!< LCD PAL91: R04_0 Mask */\r
-#define LCD_PAL91_G04_0_Pos 5 /*!< LCD PAL91: G04_0 Position */\r
-#define LCD_PAL91_G04_0_Msk (0x1fUL << LCD_PAL91_G04_0_Pos) /*!< LCD PAL91: G04_0 Mask */\r
-#define LCD_PAL91_B04_0_Pos 10 /*!< LCD PAL91: B04_0 Position */\r
-#define LCD_PAL91_B04_0_Msk (0x1fUL << LCD_PAL91_B04_0_Pos) /*!< LCD PAL91: B04_0 Mask */\r
-#define LCD_PAL91_I0_Pos 15 /*!< LCD PAL91: I0 Position */\r
-#define LCD_PAL91_I0_Msk (0x01UL << LCD_PAL91_I0_Pos) /*!< LCD PAL91: I0 Mask */\r
-#define LCD_PAL91_R14_0_Pos 16 /*!< LCD PAL91: R14_0 Position */\r
-#define LCD_PAL91_R14_0_Msk (0x1fUL << LCD_PAL91_R14_0_Pos) /*!< LCD PAL91: R14_0 Mask */\r
-#define LCD_PAL91_G14_0_Pos 21 /*!< LCD PAL91: G14_0 Position */\r
-#define LCD_PAL91_G14_0_Msk (0x1fUL << LCD_PAL91_G14_0_Pos) /*!< LCD PAL91: G14_0 Mask */\r
-#define LCD_PAL91_B14_0_Pos 26 /*!< LCD PAL91: B14_0 Position */\r
-#define LCD_PAL91_B14_0_Msk (0x1fUL << LCD_PAL91_B14_0_Pos) /*!< LCD PAL91: B14_0 Mask */\r
-#define LCD_PAL91_I1_Pos 31 /*!< LCD PAL91: I1 Position */\r
-#define LCD_PAL91_I1_Msk (0x01UL << LCD_PAL91_I1_Pos) /*!< LCD PAL91: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL92 -------------------------------------------\r
-#define LCD_PAL92_R04_0_Pos 0 /*!< LCD PAL92: R04_0 Position */\r
-#define LCD_PAL92_R04_0_Msk (0x1fUL << LCD_PAL92_R04_0_Pos) /*!< LCD PAL92: R04_0 Mask */\r
-#define LCD_PAL92_G04_0_Pos 5 /*!< LCD PAL92: G04_0 Position */\r
-#define LCD_PAL92_G04_0_Msk (0x1fUL << LCD_PAL92_G04_0_Pos) /*!< LCD PAL92: G04_0 Mask */\r
-#define LCD_PAL92_B04_0_Pos 10 /*!< LCD PAL92: B04_0 Position */\r
-#define LCD_PAL92_B04_0_Msk (0x1fUL << LCD_PAL92_B04_0_Pos) /*!< LCD PAL92: B04_0 Mask */\r
-#define LCD_PAL92_I0_Pos 15 /*!< LCD PAL92: I0 Position */\r
-#define LCD_PAL92_I0_Msk (0x01UL << LCD_PAL92_I0_Pos) /*!< LCD PAL92: I0 Mask */\r
-#define LCD_PAL92_R14_0_Pos 16 /*!< LCD PAL92: R14_0 Position */\r
-#define LCD_PAL92_R14_0_Msk (0x1fUL << LCD_PAL92_R14_0_Pos) /*!< LCD PAL92: R14_0 Mask */\r
-#define LCD_PAL92_G14_0_Pos 21 /*!< LCD PAL92: G14_0 Position */\r
-#define LCD_PAL92_G14_0_Msk (0x1fUL << LCD_PAL92_G14_0_Pos) /*!< LCD PAL92: G14_0 Mask */\r
-#define LCD_PAL92_B14_0_Pos 26 /*!< LCD PAL92: B14_0 Position */\r
-#define LCD_PAL92_B14_0_Msk (0x1fUL << LCD_PAL92_B14_0_Pos) /*!< LCD PAL92: B14_0 Mask */\r
-#define LCD_PAL92_I1_Pos 31 /*!< LCD PAL92: I1 Position */\r
-#define LCD_PAL92_I1_Msk (0x01UL << LCD_PAL92_I1_Pos) /*!< LCD PAL92: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL93 -------------------------------------------\r
-#define LCD_PAL93_R04_0_Pos 0 /*!< LCD PAL93: R04_0 Position */\r
-#define LCD_PAL93_R04_0_Msk (0x1fUL << LCD_PAL93_R04_0_Pos) /*!< LCD PAL93: R04_0 Mask */\r
-#define LCD_PAL93_G04_0_Pos 5 /*!< LCD PAL93: G04_0 Position */\r
-#define LCD_PAL93_G04_0_Msk (0x1fUL << LCD_PAL93_G04_0_Pos) /*!< LCD PAL93: G04_0 Mask */\r
-#define LCD_PAL93_B04_0_Pos 10 /*!< LCD PAL93: B04_0 Position */\r
-#define LCD_PAL93_B04_0_Msk (0x1fUL << LCD_PAL93_B04_0_Pos) /*!< LCD PAL93: B04_0 Mask */\r
-#define LCD_PAL93_I0_Pos 15 /*!< LCD PAL93: I0 Position */\r
-#define LCD_PAL93_I0_Msk (0x01UL << LCD_PAL93_I0_Pos) /*!< LCD PAL93: I0 Mask */\r
-#define LCD_PAL93_R14_0_Pos 16 /*!< LCD PAL93: R14_0 Position */\r
-#define LCD_PAL93_R14_0_Msk (0x1fUL << LCD_PAL93_R14_0_Pos) /*!< LCD PAL93: R14_0 Mask */\r
-#define LCD_PAL93_G14_0_Pos 21 /*!< LCD PAL93: G14_0 Position */\r
-#define LCD_PAL93_G14_0_Msk (0x1fUL << LCD_PAL93_G14_0_Pos) /*!< LCD PAL93: G14_0 Mask */\r
-#define LCD_PAL93_B14_0_Pos 26 /*!< LCD PAL93: B14_0 Position */\r
-#define LCD_PAL93_B14_0_Msk (0x1fUL << LCD_PAL93_B14_0_Pos) /*!< LCD PAL93: B14_0 Mask */\r
-#define LCD_PAL93_I1_Pos 31 /*!< LCD PAL93: I1 Position */\r
-#define LCD_PAL93_I1_Msk (0x01UL << LCD_PAL93_I1_Pos) /*!< LCD PAL93: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL94 -------------------------------------------\r
-#define LCD_PAL94_R04_0_Pos 0 /*!< LCD PAL94: R04_0 Position */\r
-#define LCD_PAL94_R04_0_Msk (0x1fUL << LCD_PAL94_R04_0_Pos) /*!< LCD PAL94: R04_0 Mask */\r
-#define LCD_PAL94_G04_0_Pos 5 /*!< LCD PAL94: G04_0 Position */\r
-#define LCD_PAL94_G04_0_Msk (0x1fUL << LCD_PAL94_G04_0_Pos) /*!< LCD PAL94: G04_0 Mask */\r
-#define LCD_PAL94_B04_0_Pos 10 /*!< LCD PAL94: B04_0 Position */\r
-#define LCD_PAL94_B04_0_Msk (0x1fUL << LCD_PAL94_B04_0_Pos) /*!< LCD PAL94: B04_0 Mask */\r
-#define LCD_PAL94_I0_Pos 15 /*!< LCD PAL94: I0 Position */\r
-#define LCD_PAL94_I0_Msk (0x01UL << LCD_PAL94_I0_Pos) /*!< LCD PAL94: I0 Mask */\r
-#define LCD_PAL94_R14_0_Pos 16 /*!< LCD PAL94: R14_0 Position */\r
-#define LCD_PAL94_R14_0_Msk (0x1fUL << LCD_PAL94_R14_0_Pos) /*!< LCD PAL94: R14_0 Mask */\r
-#define LCD_PAL94_G14_0_Pos 21 /*!< LCD PAL94: G14_0 Position */\r
-#define LCD_PAL94_G14_0_Msk (0x1fUL << LCD_PAL94_G14_0_Pos) /*!< LCD PAL94: G14_0 Mask */\r
-#define LCD_PAL94_B14_0_Pos 26 /*!< LCD PAL94: B14_0 Position */\r
-#define LCD_PAL94_B14_0_Msk (0x1fUL << LCD_PAL94_B14_0_Pos) /*!< LCD PAL94: B14_0 Mask */\r
-#define LCD_PAL94_I1_Pos 31 /*!< LCD PAL94: I1 Position */\r
-#define LCD_PAL94_I1_Msk (0x01UL << LCD_PAL94_I1_Pos) /*!< LCD PAL94: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL95 -------------------------------------------\r
-#define LCD_PAL95_R04_0_Pos 0 /*!< LCD PAL95: R04_0 Position */\r
-#define LCD_PAL95_R04_0_Msk (0x1fUL << LCD_PAL95_R04_0_Pos) /*!< LCD PAL95: R04_0 Mask */\r
-#define LCD_PAL95_G04_0_Pos 5 /*!< LCD PAL95: G04_0 Position */\r
-#define LCD_PAL95_G04_0_Msk (0x1fUL << LCD_PAL95_G04_0_Pos) /*!< LCD PAL95: G04_0 Mask */\r
-#define LCD_PAL95_B04_0_Pos 10 /*!< LCD PAL95: B04_0 Position */\r
-#define LCD_PAL95_B04_0_Msk (0x1fUL << LCD_PAL95_B04_0_Pos) /*!< LCD PAL95: B04_0 Mask */\r
-#define LCD_PAL95_I0_Pos 15 /*!< LCD PAL95: I0 Position */\r
-#define LCD_PAL95_I0_Msk (0x01UL << LCD_PAL95_I0_Pos) /*!< LCD PAL95: I0 Mask */\r
-#define LCD_PAL95_R14_0_Pos 16 /*!< LCD PAL95: R14_0 Position */\r
-#define LCD_PAL95_R14_0_Msk (0x1fUL << LCD_PAL95_R14_0_Pos) /*!< LCD PAL95: R14_0 Mask */\r
-#define LCD_PAL95_G14_0_Pos 21 /*!< LCD PAL95: G14_0 Position */\r
-#define LCD_PAL95_G14_0_Msk (0x1fUL << LCD_PAL95_G14_0_Pos) /*!< LCD PAL95: G14_0 Mask */\r
-#define LCD_PAL95_B14_0_Pos 26 /*!< LCD PAL95: B14_0 Position */\r
-#define LCD_PAL95_B14_0_Msk (0x1fUL << LCD_PAL95_B14_0_Pos) /*!< LCD PAL95: B14_0 Mask */\r
-#define LCD_PAL95_I1_Pos 31 /*!< LCD PAL95: I1 Position */\r
-#define LCD_PAL95_I1_Msk (0x01UL << LCD_PAL95_I1_Pos) /*!< LCD PAL95: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL96 -------------------------------------------\r
-#define LCD_PAL96_R04_0_Pos 0 /*!< LCD PAL96: R04_0 Position */\r
-#define LCD_PAL96_R04_0_Msk (0x1fUL << LCD_PAL96_R04_0_Pos) /*!< LCD PAL96: R04_0 Mask */\r
-#define LCD_PAL96_G04_0_Pos 5 /*!< LCD PAL96: G04_0 Position */\r
-#define LCD_PAL96_G04_0_Msk (0x1fUL << LCD_PAL96_G04_0_Pos) /*!< LCD PAL96: G04_0 Mask */\r
-#define LCD_PAL96_B04_0_Pos 10 /*!< LCD PAL96: B04_0 Position */\r
-#define LCD_PAL96_B04_0_Msk (0x1fUL << LCD_PAL96_B04_0_Pos) /*!< LCD PAL96: B04_0 Mask */\r
-#define LCD_PAL96_I0_Pos 15 /*!< LCD PAL96: I0 Position */\r
-#define LCD_PAL96_I0_Msk (0x01UL << LCD_PAL96_I0_Pos) /*!< LCD PAL96: I0 Mask */\r
-#define LCD_PAL96_R14_0_Pos 16 /*!< LCD PAL96: R14_0 Position */\r
-#define LCD_PAL96_R14_0_Msk (0x1fUL << LCD_PAL96_R14_0_Pos) /*!< LCD PAL96: R14_0 Mask */\r
-#define LCD_PAL96_G14_0_Pos 21 /*!< LCD PAL96: G14_0 Position */\r
-#define LCD_PAL96_G14_0_Msk (0x1fUL << LCD_PAL96_G14_0_Pos) /*!< LCD PAL96: G14_0 Mask */\r
-#define LCD_PAL96_B14_0_Pos 26 /*!< LCD PAL96: B14_0 Position */\r
-#define LCD_PAL96_B14_0_Msk (0x1fUL << LCD_PAL96_B14_0_Pos) /*!< LCD PAL96: B14_0 Mask */\r
-#define LCD_PAL96_I1_Pos 31 /*!< LCD PAL96: I1 Position */\r
-#define LCD_PAL96_I1_Msk (0x01UL << LCD_PAL96_I1_Pos) /*!< LCD PAL96: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL97 -------------------------------------------\r
-#define LCD_PAL97_R04_0_Pos 0 /*!< LCD PAL97: R04_0 Position */\r
-#define LCD_PAL97_R04_0_Msk (0x1fUL << LCD_PAL97_R04_0_Pos) /*!< LCD PAL97: R04_0 Mask */\r
-#define LCD_PAL97_G04_0_Pos 5 /*!< LCD PAL97: G04_0 Position */\r
-#define LCD_PAL97_G04_0_Msk (0x1fUL << LCD_PAL97_G04_0_Pos) /*!< LCD PAL97: G04_0 Mask */\r
-#define LCD_PAL97_B04_0_Pos 10 /*!< LCD PAL97: B04_0 Position */\r
-#define LCD_PAL97_B04_0_Msk (0x1fUL << LCD_PAL97_B04_0_Pos) /*!< LCD PAL97: B04_0 Mask */\r
-#define LCD_PAL97_I0_Pos 15 /*!< LCD PAL97: I0 Position */\r
-#define LCD_PAL97_I0_Msk (0x01UL << LCD_PAL97_I0_Pos) /*!< LCD PAL97: I0 Mask */\r
-#define LCD_PAL97_R14_0_Pos 16 /*!< LCD PAL97: R14_0 Position */\r
-#define LCD_PAL97_R14_0_Msk (0x1fUL << LCD_PAL97_R14_0_Pos) /*!< LCD PAL97: R14_0 Mask */\r
-#define LCD_PAL97_G14_0_Pos 21 /*!< LCD PAL97: G14_0 Position */\r
-#define LCD_PAL97_G14_0_Msk (0x1fUL << LCD_PAL97_G14_0_Pos) /*!< LCD PAL97: G14_0 Mask */\r
-#define LCD_PAL97_B14_0_Pos 26 /*!< LCD PAL97: B14_0 Position */\r
-#define LCD_PAL97_B14_0_Msk (0x1fUL << LCD_PAL97_B14_0_Pos) /*!< LCD PAL97: B14_0 Mask */\r
-#define LCD_PAL97_I1_Pos 31 /*!< LCD PAL97: I1 Position */\r
-#define LCD_PAL97_I1_Msk (0x01UL << LCD_PAL97_I1_Pos) /*!< LCD PAL97: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL98 -------------------------------------------\r
-#define LCD_PAL98_R04_0_Pos 0 /*!< LCD PAL98: R04_0 Position */\r
-#define LCD_PAL98_R04_0_Msk (0x1fUL << LCD_PAL98_R04_0_Pos) /*!< LCD PAL98: R04_0 Mask */\r
-#define LCD_PAL98_G04_0_Pos 5 /*!< LCD PAL98: G04_0 Position */\r
-#define LCD_PAL98_G04_0_Msk (0x1fUL << LCD_PAL98_G04_0_Pos) /*!< LCD PAL98: G04_0 Mask */\r
-#define LCD_PAL98_B04_0_Pos 10 /*!< LCD PAL98: B04_0 Position */\r
-#define LCD_PAL98_B04_0_Msk (0x1fUL << LCD_PAL98_B04_0_Pos) /*!< LCD PAL98: B04_0 Mask */\r
-#define LCD_PAL98_I0_Pos 15 /*!< LCD PAL98: I0 Position */\r
-#define LCD_PAL98_I0_Msk (0x01UL << LCD_PAL98_I0_Pos) /*!< LCD PAL98: I0 Mask */\r
-#define LCD_PAL98_R14_0_Pos 16 /*!< LCD PAL98: R14_0 Position */\r
-#define LCD_PAL98_R14_0_Msk (0x1fUL << LCD_PAL98_R14_0_Pos) /*!< LCD PAL98: R14_0 Mask */\r
-#define LCD_PAL98_G14_0_Pos 21 /*!< LCD PAL98: G14_0 Position */\r
-#define LCD_PAL98_G14_0_Msk (0x1fUL << LCD_PAL98_G14_0_Pos) /*!< LCD PAL98: G14_0 Mask */\r
-#define LCD_PAL98_B14_0_Pos 26 /*!< LCD PAL98: B14_0 Position */\r
-#define LCD_PAL98_B14_0_Msk (0x1fUL << LCD_PAL98_B14_0_Pos) /*!< LCD PAL98: B14_0 Mask */\r
-#define LCD_PAL98_I1_Pos 31 /*!< LCD PAL98: I1 Position */\r
-#define LCD_PAL98_I1_Msk (0x01UL << LCD_PAL98_I1_Pos) /*!< LCD PAL98: I1 Mask */\r
-\r
-// ---------------------------------------- LCD_PAL99 -------------------------------------------\r
-#define LCD_PAL99_R04_0_Pos 0 /*!< LCD PAL99: R04_0 Position */\r
-#define LCD_PAL99_R04_0_Msk (0x1fUL << LCD_PAL99_R04_0_Pos) /*!< LCD PAL99: R04_0 Mask */\r
-#define LCD_PAL99_G04_0_Pos 5 /*!< LCD PAL99: G04_0 Position */\r
-#define LCD_PAL99_G04_0_Msk (0x1fUL << LCD_PAL99_G04_0_Pos) /*!< LCD PAL99: G04_0 Mask */\r
-#define LCD_PAL99_B04_0_Pos 10 /*!< LCD PAL99: B04_0 Position */\r
-#define LCD_PAL99_B04_0_Msk (0x1fUL << LCD_PAL99_B04_0_Pos) /*!< LCD PAL99: B04_0 Mask */\r
-#define LCD_PAL99_I0_Pos 15 /*!< LCD PAL99: I0 Position */\r
-#define LCD_PAL99_I0_Msk (0x01UL << LCD_PAL99_I0_Pos) /*!< LCD PAL99: I0 Mask */\r
-#define LCD_PAL99_R14_0_Pos 16 /*!< LCD PAL99: R14_0 Position */\r
-#define LCD_PAL99_R14_0_Msk (0x1fUL << LCD_PAL99_R14_0_Pos) /*!< LCD PAL99: R14_0 Mask */\r
-#define LCD_PAL99_G14_0_Pos 21 /*!< LCD PAL99: G14_0 Position */\r
-#define LCD_PAL99_G14_0_Msk (0x1fUL << LCD_PAL99_G14_0_Pos) /*!< LCD PAL99: G14_0 Mask */\r
-#define LCD_PAL99_B14_0_Pos 26 /*!< LCD PAL99: B14_0 Position */\r
-#define LCD_PAL99_B14_0_Msk (0x1fUL << LCD_PAL99_B14_0_Pos) /*!< LCD PAL99: B14_0 Mask */\r
-#define LCD_PAL99_I1_Pos 31 /*!< LCD PAL99: I1 Position */\r
-#define LCD_PAL99_I1_Msk (0x01UL << LCD_PAL99_I1_Pos) /*!< LCD PAL99: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL100 -------------------------------------------\r
-#define LCD_PAL100_R04_0_Pos 0 /*!< LCD PAL100: R04_0 Position */\r
-#define LCD_PAL100_R04_0_Msk (0x1fUL << LCD_PAL100_R04_0_Pos) /*!< LCD PAL100: R04_0 Mask */\r
-#define LCD_PAL100_G04_0_Pos 5 /*!< LCD PAL100: G04_0 Position */\r
-#define LCD_PAL100_G04_0_Msk (0x1fUL << LCD_PAL100_G04_0_Pos) /*!< LCD PAL100: G04_0 Mask */\r
-#define LCD_PAL100_B04_0_Pos 10 /*!< LCD PAL100: B04_0 Position */\r
-#define LCD_PAL100_B04_0_Msk (0x1fUL << LCD_PAL100_B04_0_Pos) /*!< LCD PAL100: B04_0 Mask */\r
-#define LCD_PAL100_I0_Pos 15 /*!< LCD PAL100: I0 Position */\r
-#define LCD_PAL100_I0_Msk (0x01UL << LCD_PAL100_I0_Pos) /*!< LCD PAL100: I0 Mask */\r
-#define LCD_PAL100_R14_0_Pos 16 /*!< LCD PAL100: R14_0 Position */\r
-#define LCD_PAL100_R14_0_Msk (0x1fUL << LCD_PAL100_R14_0_Pos) /*!< LCD PAL100: R14_0 Mask */\r
-#define LCD_PAL100_G14_0_Pos 21 /*!< LCD PAL100: G14_0 Position */\r
-#define LCD_PAL100_G14_0_Msk (0x1fUL << LCD_PAL100_G14_0_Pos) /*!< LCD PAL100: G14_0 Mask */\r
-#define LCD_PAL100_B14_0_Pos 26 /*!< LCD PAL100: B14_0 Position */\r
-#define LCD_PAL100_B14_0_Msk (0x1fUL << LCD_PAL100_B14_0_Pos) /*!< LCD PAL100: B14_0 Mask */\r
-#define LCD_PAL100_I1_Pos 31 /*!< LCD PAL100: I1 Position */\r
-#define LCD_PAL100_I1_Msk (0x01UL << LCD_PAL100_I1_Pos) /*!< LCD PAL100: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL101 -------------------------------------------\r
-#define LCD_PAL101_R04_0_Pos 0 /*!< LCD PAL101: R04_0 Position */\r
-#define LCD_PAL101_R04_0_Msk (0x1fUL << LCD_PAL101_R04_0_Pos) /*!< LCD PAL101: R04_0 Mask */\r
-#define LCD_PAL101_G04_0_Pos 5 /*!< LCD PAL101: G04_0 Position */\r
-#define LCD_PAL101_G04_0_Msk (0x1fUL << LCD_PAL101_G04_0_Pos) /*!< LCD PAL101: G04_0 Mask */\r
-#define LCD_PAL101_B04_0_Pos 10 /*!< LCD PAL101: B04_0 Position */\r
-#define LCD_PAL101_B04_0_Msk (0x1fUL << LCD_PAL101_B04_0_Pos) /*!< LCD PAL101: B04_0 Mask */\r
-#define LCD_PAL101_I0_Pos 15 /*!< LCD PAL101: I0 Position */\r
-#define LCD_PAL101_I0_Msk (0x01UL << LCD_PAL101_I0_Pos) /*!< LCD PAL101: I0 Mask */\r
-#define LCD_PAL101_R14_0_Pos 16 /*!< LCD PAL101: R14_0 Position */\r
-#define LCD_PAL101_R14_0_Msk (0x1fUL << LCD_PAL101_R14_0_Pos) /*!< LCD PAL101: R14_0 Mask */\r
-#define LCD_PAL101_G14_0_Pos 21 /*!< LCD PAL101: G14_0 Position */\r
-#define LCD_PAL101_G14_0_Msk (0x1fUL << LCD_PAL101_G14_0_Pos) /*!< LCD PAL101: G14_0 Mask */\r
-#define LCD_PAL101_B14_0_Pos 26 /*!< LCD PAL101: B14_0 Position */\r
-#define LCD_PAL101_B14_0_Msk (0x1fUL << LCD_PAL101_B14_0_Pos) /*!< LCD PAL101: B14_0 Mask */\r
-#define LCD_PAL101_I1_Pos 31 /*!< LCD PAL101: I1 Position */\r
-#define LCD_PAL101_I1_Msk (0x01UL << LCD_PAL101_I1_Pos) /*!< LCD PAL101: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL102 -------------------------------------------\r
-#define LCD_PAL102_R04_0_Pos 0 /*!< LCD PAL102: R04_0 Position */\r
-#define LCD_PAL102_R04_0_Msk (0x1fUL << LCD_PAL102_R04_0_Pos) /*!< LCD PAL102: R04_0 Mask */\r
-#define LCD_PAL102_G04_0_Pos 5 /*!< LCD PAL102: G04_0 Position */\r
-#define LCD_PAL102_G04_0_Msk (0x1fUL << LCD_PAL102_G04_0_Pos) /*!< LCD PAL102: G04_0 Mask */\r
-#define LCD_PAL102_B04_0_Pos 10 /*!< LCD PAL102: B04_0 Position */\r
-#define LCD_PAL102_B04_0_Msk (0x1fUL << LCD_PAL102_B04_0_Pos) /*!< LCD PAL102: B04_0 Mask */\r
-#define LCD_PAL102_I0_Pos 15 /*!< LCD PAL102: I0 Position */\r
-#define LCD_PAL102_I0_Msk (0x01UL << LCD_PAL102_I0_Pos) /*!< LCD PAL102: I0 Mask */\r
-#define LCD_PAL102_R14_0_Pos 16 /*!< LCD PAL102: R14_0 Position */\r
-#define LCD_PAL102_R14_0_Msk (0x1fUL << LCD_PAL102_R14_0_Pos) /*!< LCD PAL102: R14_0 Mask */\r
-#define LCD_PAL102_G14_0_Pos 21 /*!< LCD PAL102: G14_0 Position */\r
-#define LCD_PAL102_G14_0_Msk (0x1fUL << LCD_PAL102_G14_0_Pos) /*!< LCD PAL102: G14_0 Mask */\r
-#define LCD_PAL102_B14_0_Pos 26 /*!< LCD PAL102: B14_0 Position */\r
-#define LCD_PAL102_B14_0_Msk (0x1fUL << LCD_PAL102_B14_0_Pos) /*!< LCD PAL102: B14_0 Mask */\r
-#define LCD_PAL102_I1_Pos 31 /*!< LCD PAL102: I1 Position */\r
-#define LCD_PAL102_I1_Msk (0x01UL << LCD_PAL102_I1_Pos) /*!< LCD PAL102: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL103 -------------------------------------------\r
-#define LCD_PAL103_R04_0_Pos 0 /*!< LCD PAL103: R04_0 Position */\r
-#define LCD_PAL103_R04_0_Msk (0x1fUL << LCD_PAL103_R04_0_Pos) /*!< LCD PAL103: R04_0 Mask */\r
-#define LCD_PAL103_G04_0_Pos 5 /*!< LCD PAL103: G04_0 Position */\r
-#define LCD_PAL103_G04_0_Msk (0x1fUL << LCD_PAL103_G04_0_Pos) /*!< LCD PAL103: G04_0 Mask */\r
-#define LCD_PAL103_B04_0_Pos 10 /*!< LCD PAL103: B04_0 Position */\r
-#define LCD_PAL103_B04_0_Msk (0x1fUL << LCD_PAL103_B04_0_Pos) /*!< LCD PAL103: B04_0 Mask */\r
-#define LCD_PAL103_I0_Pos 15 /*!< LCD PAL103: I0 Position */\r
-#define LCD_PAL103_I0_Msk (0x01UL << LCD_PAL103_I0_Pos) /*!< LCD PAL103: I0 Mask */\r
-#define LCD_PAL103_R14_0_Pos 16 /*!< LCD PAL103: R14_0 Position */\r
-#define LCD_PAL103_R14_0_Msk (0x1fUL << LCD_PAL103_R14_0_Pos) /*!< LCD PAL103: R14_0 Mask */\r
-#define LCD_PAL103_G14_0_Pos 21 /*!< LCD PAL103: G14_0 Position */\r
-#define LCD_PAL103_G14_0_Msk (0x1fUL << LCD_PAL103_G14_0_Pos) /*!< LCD PAL103: G14_0 Mask */\r
-#define LCD_PAL103_B14_0_Pos 26 /*!< LCD PAL103: B14_0 Position */\r
-#define LCD_PAL103_B14_0_Msk (0x1fUL << LCD_PAL103_B14_0_Pos) /*!< LCD PAL103: B14_0 Mask */\r
-#define LCD_PAL103_I1_Pos 31 /*!< LCD PAL103: I1 Position */\r
-#define LCD_PAL103_I1_Msk (0x01UL << LCD_PAL103_I1_Pos) /*!< LCD PAL103: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL104 -------------------------------------------\r
-#define LCD_PAL104_R04_0_Pos 0 /*!< LCD PAL104: R04_0 Position */\r
-#define LCD_PAL104_R04_0_Msk (0x1fUL << LCD_PAL104_R04_0_Pos) /*!< LCD PAL104: R04_0 Mask */\r
-#define LCD_PAL104_G04_0_Pos 5 /*!< LCD PAL104: G04_0 Position */\r
-#define LCD_PAL104_G04_0_Msk (0x1fUL << LCD_PAL104_G04_0_Pos) /*!< LCD PAL104: G04_0 Mask */\r
-#define LCD_PAL104_B04_0_Pos 10 /*!< LCD PAL104: B04_0 Position */\r
-#define LCD_PAL104_B04_0_Msk (0x1fUL << LCD_PAL104_B04_0_Pos) /*!< LCD PAL104: B04_0 Mask */\r
-#define LCD_PAL104_I0_Pos 15 /*!< LCD PAL104: I0 Position */\r
-#define LCD_PAL104_I0_Msk (0x01UL << LCD_PAL104_I0_Pos) /*!< LCD PAL104: I0 Mask */\r
-#define LCD_PAL104_R14_0_Pos 16 /*!< LCD PAL104: R14_0 Position */\r
-#define LCD_PAL104_R14_0_Msk (0x1fUL << LCD_PAL104_R14_0_Pos) /*!< LCD PAL104: R14_0 Mask */\r
-#define LCD_PAL104_G14_0_Pos 21 /*!< LCD PAL104: G14_0 Position */\r
-#define LCD_PAL104_G14_0_Msk (0x1fUL << LCD_PAL104_G14_0_Pos) /*!< LCD PAL104: G14_0 Mask */\r
-#define LCD_PAL104_B14_0_Pos 26 /*!< LCD PAL104: B14_0 Position */\r
-#define LCD_PAL104_B14_0_Msk (0x1fUL << LCD_PAL104_B14_0_Pos) /*!< LCD PAL104: B14_0 Mask */\r
-#define LCD_PAL104_I1_Pos 31 /*!< LCD PAL104: I1 Position */\r
-#define LCD_PAL104_I1_Msk (0x01UL << LCD_PAL104_I1_Pos) /*!< LCD PAL104: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL105 -------------------------------------------\r
-#define LCD_PAL105_R04_0_Pos 0 /*!< LCD PAL105: R04_0 Position */\r
-#define LCD_PAL105_R04_0_Msk (0x1fUL << LCD_PAL105_R04_0_Pos) /*!< LCD PAL105: R04_0 Mask */\r
-#define LCD_PAL105_G04_0_Pos 5 /*!< LCD PAL105: G04_0 Position */\r
-#define LCD_PAL105_G04_0_Msk (0x1fUL << LCD_PAL105_G04_0_Pos) /*!< LCD PAL105: G04_0 Mask */\r
-#define LCD_PAL105_B04_0_Pos 10 /*!< LCD PAL105: B04_0 Position */\r
-#define LCD_PAL105_B04_0_Msk (0x1fUL << LCD_PAL105_B04_0_Pos) /*!< LCD PAL105: B04_0 Mask */\r
-#define LCD_PAL105_I0_Pos 15 /*!< LCD PAL105: I0 Position */\r
-#define LCD_PAL105_I0_Msk (0x01UL << LCD_PAL105_I0_Pos) /*!< LCD PAL105: I0 Mask */\r
-#define LCD_PAL105_R14_0_Pos 16 /*!< LCD PAL105: R14_0 Position */\r
-#define LCD_PAL105_R14_0_Msk (0x1fUL << LCD_PAL105_R14_0_Pos) /*!< LCD PAL105: R14_0 Mask */\r
-#define LCD_PAL105_G14_0_Pos 21 /*!< LCD PAL105: G14_0 Position */\r
-#define LCD_PAL105_G14_0_Msk (0x1fUL << LCD_PAL105_G14_0_Pos) /*!< LCD PAL105: G14_0 Mask */\r
-#define LCD_PAL105_B14_0_Pos 26 /*!< LCD PAL105: B14_0 Position */\r
-#define LCD_PAL105_B14_0_Msk (0x1fUL << LCD_PAL105_B14_0_Pos) /*!< LCD PAL105: B14_0 Mask */\r
-#define LCD_PAL105_I1_Pos 31 /*!< LCD PAL105: I1 Position */\r
-#define LCD_PAL105_I1_Msk (0x01UL << LCD_PAL105_I1_Pos) /*!< LCD PAL105: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL106 -------------------------------------------\r
-#define LCD_PAL106_R04_0_Pos 0 /*!< LCD PAL106: R04_0 Position */\r
-#define LCD_PAL106_R04_0_Msk (0x1fUL << LCD_PAL106_R04_0_Pos) /*!< LCD PAL106: R04_0 Mask */\r
-#define LCD_PAL106_G04_0_Pos 5 /*!< LCD PAL106: G04_0 Position */\r
-#define LCD_PAL106_G04_0_Msk (0x1fUL << LCD_PAL106_G04_0_Pos) /*!< LCD PAL106: G04_0 Mask */\r
-#define LCD_PAL106_B04_0_Pos 10 /*!< LCD PAL106: B04_0 Position */\r
-#define LCD_PAL106_B04_0_Msk (0x1fUL << LCD_PAL106_B04_0_Pos) /*!< LCD PAL106: B04_0 Mask */\r
-#define LCD_PAL106_I0_Pos 15 /*!< LCD PAL106: I0 Position */\r
-#define LCD_PAL106_I0_Msk (0x01UL << LCD_PAL106_I0_Pos) /*!< LCD PAL106: I0 Mask */\r
-#define LCD_PAL106_R14_0_Pos 16 /*!< LCD PAL106: R14_0 Position */\r
-#define LCD_PAL106_R14_0_Msk (0x1fUL << LCD_PAL106_R14_0_Pos) /*!< LCD PAL106: R14_0 Mask */\r
-#define LCD_PAL106_G14_0_Pos 21 /*!< LCD PAL106: G14_0 Position */\r
-#define LCD_PAL106_G14_0_Msk (0x1fUL << LCD_PAL106_G14_0_Pos) /*!< LCD PAL106: G14_0 Mask */\r
-#define LCD_PAL106_B14_0_Pos 26 /*!< LCD PAL106: B14_0 Position */\r
-#define LCD_PAL106_B14_0_Msk (0x1fUL << LCD_PAL106_B14_0_Pos) /*!< LCD PAL106: B14_0 Mask */\r
-#define LCD_PAL106_I1_Pos 31 /*!< LCD PAL106: I1 Position */\r
-#define LCD_PAL106_I1_Msk (0x01UL << LCD_PAL106_I1_Pos) /*!< LCD PAL106: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL107 -------------------------------------------\r
-#define LCD_PAL107_R04_0_Pos 0 /*!< LCD PAL107: R04_0 Position */\r
-#define LCD_PAL107_R04_0_Msk (0x1fUL << LCD_PAL107_R04_0_Pos) /*!< LCD PAL107: R04_0 Mask */\r
-#define LCD_PAL107_G04_0_Pos 5 /*!< LCD PAL107: G04_0 Position */\r
-#define LCD_PAL107_G04_0_Msk (0x1fUL << LCD_PAL107_G04_0_Pos) /*!< LCD PAL107: G04_0 Mask */\r
-#define LCD_PAL107_B04_0_Pos 10 /*!< LCD PAL107: B04_0 Position */\r
-#define LCD_PAL107_B04_0_Msk (0x1fUL << LCD_PAL107_B04_0_Pos) /*!< LCD PAL107: B04_0 Mask */\r
-#define LCD_PAL107_I0_Pos 15 /*!< LCD PAL107: I0 Position */\r
-#define LCD_PAL107_I0_Msk (0x01UL << LCD_PAL107_I0_Pos) /*!< LCD PAL107: I0 Mask */\r
-#define LCD_PAL107_R14_0_Pos 16 /*!< LCD PAL107: R14_0 Position */\r
-#define LCD_PAL107_R14_0_Msk (0x1fUL << LCD_PAL107_R14_0_Pos) /*!< LCD PAL107: R14_0 Mask */\r
-#define LCD_PAL107_G14_0_Pos 21 /*!< LCD PAL107: G14_0 Position */\r
-#define LCD_PAL107_G14_0_Msk (0x1fUL << LCD_PAL107_G14_0_Pos) /*!< LCD PAL107: G14_0 Mask */\r
-#define LCD_PAL107_B14_0_Pos 26 /*!< LCD PAL107: B14_0 Position */\r
-#define LCD_PAL107_B14_0_Msk (0x1fUL << LCD_PAL107_B14_0_Pos) /*!< LCD PAL107: B14_0 Mask */\r
-#define LCD_PAL107_I1_Pos 31 /*!< LCD PAL107: I1 Position */\r
-#define LCD_PAL107_I1_Msk (0x01UL << LCD_PAL107_I1_Pos) /*!< LCD PAL107: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL108 -------------------------------------------\r
-#define LCD_PAL108_R04_0_Pos 0 /*!< LCD PAL108: R04_0 Position */\r
-#define LCD_PAL108_R04_0_Msk (0x1fUL << LCD_PAL108_R04_0_Pos) /*!< LCD PAL108: R04_0 Mask */\r
-#define LCD_PAL108_G04_0_Pos 5 /*!< LCD PAL108: G04_0 Position */\r
-#define LCD_PAL108_G04_0_Msk (0x1fUL << LCD_PAL108_G04_0_Pos) /*!< LCD PAL108: G04_0 Mask */\r
-#define LCD_PAL108_B04_0_Pos 10 /*!< LCD PAL108: B04_0 Position */\r
-#define LCD_PAL108_B04_0_Msk (0x1fUL << LCD_PAL108_B04_0_Pos) /*!< LCD PAL108: B04_0 Mask */\r
-#define LCD_PAL108_I0_Pos 15 /*!< LCD PAL108: I0 Position */\r
-#define LCD_PAL108_I0_Msk (0x01UL << LCD_PAL108_I0_Pos) /*!< LCD PAL108: I0 Mask */\r
-#define LCD_PAL108_R14_0_Pos 16 /*!< LCD PAL108: R14_0 Position */\r
-#define LCD_PAL108_R14_0_Msk (0x1fUL << LCD_PAL108_R14_0_Pos) /*!< LCD PAL108: R14_0 Mask */\r
-#define LCD_PAL108_G14_0_Pos 21 /*!< LCD PAL108: G14_0 Position */\r
-#define LCD_PAL108_G14_0_Msk (0x1fUL << LCD_PAL108_G14_0_Pos) /*!< LCD PAL108: G14_0 Mask */\r
-#define LCD_PAL108_B14_0_Pos 26 /*!< LCD PAL108: B14_0 Position */\r
-#define LCD_PAL108_B14_0_Msk (0x1fUL << LCD_PAL108_B14_0_Pos) /*!< LCD PAL108: B14_0 Mask */\r
-#define LCD_PAL108_I1_Pos 31 /*!< LCD PAL108: I1 Position */\r
-#define LCD_PAL108_I1_Msk (0x01UL << LCD_PAL108_I1_Pos) /*!< LCD PAL108: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL109 -------------------------------------------\r
-#define LCD_PAL109_R04_0_Pos 0 /*!< LCD PAL109: R04_0 Position */\r
-#define LCD_PAL109_R04_0_Msk (0x1fUL << LCD_PAL109_R04_0_Pos) /*!< LCD PAL109: R04_0 Mask */\r
-#define LCD_PAL109_G04_0_Pos 5 /*!< LCD PAL109: G04_0 Position */\r
-#define LCD_PAL109_G04_0_Msk (0x1fUL << LCD_PAL109_G04_0_Pos) /*!< LCD PAL109: G04_0 Mask */\r
-#define LCD_PAL109_B04_0_Pos 10 /*!< LCD PAL109: B04_0 Position */\r
-#define LCD_PAL109_B04_0_Msk (0x1fUL << LCD_PAL109_B04_0_Pos) /*!< LCD PAL109: B04_0 Mask */\r
-#define LCD_PAL109_I0_Pos 15 /*!< LCD PAL109: I0 Position */\r
-#define LCD_PAL109_I0_Msk (0x01UL << LCD_PAL109_I0_Pos) /*!< LCD PAL109: I0 Mask */\r
-#define LCD_PAL109_R14_0_Pos 16 /*!< LCD PAL109: R14_0 Position */\r
-#define LCD_PAL109_R14_0_Msk (0x1fUL << LCD_PAL109_R14_0_Pos) /*!< LCD PAL109: R14_0 Mask */\r
-#define LCD_PAL109_G14_0_Pos 21 /*!< LCD PAL109: G14_0 Position */\r
-#define LCD_PAL109_G14_0_Msk (0x1fUL << LCD_PAL109_G14_0_Pos) /*!< LCD PAL109: G14_0 Mask */\r
-#define LCD_PAL109_B14_0_Pos 26 /*!< LCD PAL109: B14_0 Position */\r
-#define LCD_PAL109_B14_0_Msk (0x1fUL << LCD_PAL109_B14_0_Pos) /*!< LCD PAL109: B14_0 Mask */\r
-#define LCD_PAL109_I1_Pos 31 /*!< LCD PAL109: I1 Position */\r
-#define LCD_PAL109_I1_Msk (0x01UL << LCD_PAL109_I1_Pos) /*!< LCD PAL109: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL110 -------------------------------------------\r
-#define LCD_PAL110_R04_0_Pos 0 /*!< LCD PAL110: R04_0 Position */\r
-#define LCD_PAL110_R04_0_Msk (0x1fUL << LCD_PAL110_R04_0_Pos) /*!< LCD PAL110: R04_0 Mask */\r
-#define LCD_PAL110_G04_0_Pos 5 /*!< LCD PAL110: G04_0 Position */\r
-#define LCD_PAL110_G04_0_Msk (0x1fUL << LCD_PAL110_G04_0_Pos) /*!< LCD PAL110: G04_0 Mask */\r
-#define LCD_PAL110_B04_0_Pos 10 /*!< LCD PAL110: B04_0 Position */\r
-#define LCD_PAL110_B04_0_Msk (0x1fUL << LCD_PAL110_B04_0_Pos) /*!< LCD PAL110: B04_0 Mask */\r
-#define LCD_PAL110_I0_Pos 15 /*!< LCD PAL110: I0 Position */\r
-#define LCD_PAL110_I0_Msk (0x01UL << LCD_PAL110_I0_Pos) /*!< LCD PAL110: I0 Mask */\r
-#define LCD_PAL110_R14_0_Pos 16 /*!< LCD PAL110: R14_0 Position */\r
-#define LCD_PAL110_R14_0_Msk (0x1fUL << LCD_PAL110_R14_0_Pos) /*!< LCD PAL110: R14_0 Mask */\r
-#define LCD_PAL110_G14_0_Pos 21 /*!< LCD PAL110: G14_0 Position */\r
-#define LCD_PAL110_G14_0_Msk (0x1fUL << LCD_PAL110_G14_0_Pos) /*!< LCD PAL110: G14_0 Mask */\r
-#define LCD_PAL110_B14_0_Pos 26 /*!< LCD PAL110: B14_0 Position */\r
-#define LCD_PAL110_B14_0_Msk (0x1fUL << LCD_PAL110_B14_0_Pos) /*!< LCD PAL110: B14_0 Mask */\r
-#define LCD_PAL110_I1_Pos 31 /*!< LCD PAL110: I1 Position */\r
-#define LCD_PAL110_I1_Msk (0x01UL << LCD_PAL110_I1_Pos) /*!< LCD PAL110: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL111 -------------------------------------------\r
-#define LCD_PAL111_R04_0_Pos 0 /*!< LCD PAL111: R04_0 Position */\r
-#define LCD_PAL111_R04_0_Msk (0x1fUL << LCD_PAL111_R04_0_Pos) /*!< LCD PAL111: R04_0 Mask */\r
-#define LCD_PAL111_G04_0_Pos 5 /*!< LCD PAL111: G04_0 Position */\r
-#define LCD_PAL111_G04_0_Msk (0x1fUL << LCD_PAL111_G04_0_Pos) /*!< LCD PAL111: G04_0 Mask */\r
-#define LCD_PAL111_B04_0_Pos 10 /*!< LCD PAL111: B04_0 Position */\r
-#define LCD_PAL111_B04_0_Msk (0x1fUL << LCD_PAL111_B04_0_Pos) /*!< LCD PAL111: B04_0 Mask */\r
-#define LCD_PAL111_I0_Pos 15 /*!< LCD PAL111: I0 Position */\r
-#define LCD_PAL111_I0_Msk (0x01UL << LCD_PAL111_I0_Pos) /*!< LCD PAL111: I0 Mask */\r
-#define LCD_PAL111_R14_0_Pos 16 /*!< LCD PAL111: R14_0 Position */\r
-#define LCD_PAL111_R14_0_Msk (0x1fUL << LCD_PAL111_R14_0_Pos) /*!< LCD PAL111: R14_0 Mask */\r
-#define LCD_PAL111_G14_0_Pos 21 /*!< LCD PAL111: G14_0 Position */\r
-#define LCD_PAL111_G14_0_Msk (0x1fUL << LCD_PAL111_G14_0_Pos) /*!< LCD PAL111: G14_0 Mask */\r
-#define LCD_PAL111_B14_0_Pos 26 /*!< LCD PAL111: B14_0 Position */\r
-#define LCD_PAL111_B14_0_Msk (0x1fUL << LCD_PAL111_B14_0_Pos) /*!< LCD PAL111: B14_0 Mask */\r
-#define LCD_PAL111_I1_Pos 31 /*!< LCD PAL111: I1 Position */\r
-#define LCD_PAL111_I1_Msk (0x01UL << LCD_PAL111_I1_Pos) /*!< LCD PAL111: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL112 -------------------------------------------\r
-#define LCD_PAL112_R04_0_Pos 0 /*!< LCD PAL112: R04_0 Position */\r
-#define LCD_PAL112_R04_0_Msk (0x1fUL << LCD_PAL112_R04_0_Pos) /*!< LCD PAL112: R04_0 Mask */\r
-#define LCD_PAL112_G04_0_Pos 5 /*!< LCD PAL112: G04_0 Position */\r
-#define LCD_PAL112_G04_0_Msk (0x1fUL << LCD_PAL112_G04_0_Pos) /*!< LCD PAL112: G04_0 Mask */\r
-#define LCD_PAL112_B04_0_Pos 10 /*!< LCD PAL112: B04_0 Position */\r
-#define LCD_PAL112_B04_0_Msk (0x1fUL << LCD_PAL112_B04_0_Pos) /*!< LCD PAL112: B04_0 Mask */\r
-#define LCD_PAL112_I0_Pos 15 /*!< LCD PAL112: I0 Position */\r
-#define LCD_PAL112_I0_Msk (0x01UL << LCD_PAL112_I0_Pos) /*!< LCD PAL112: I0 Mask */\r
-#define LCD_PAL112_R14_0_Pos 16 /*!< LCD PAL112: R14_0 Position */\r
-#define LCD_PAL112_R14_0_Msk (0x1fUL << LCD_PAL112_R14_0_Pos) /*!< LCD PAL112: R14_0 Mask */\r
-#define LCD_PAL112_G14_0_Pos 21 /*!< LCD PAL112: G14_0 Position */\r
-#define LCD_PAL112_G14_0_Msk (0x1fUL << LCD_PAL112_G14_0_Pos) /*!< LCD PAL112: G14_0 Mask */\r
-#define LCD_PAL112_B14_0_Pos 26 /*!< LCD PAL112: B14_0 Position */\r
-#define LCD_PAL112_B14_0_Msk (0x1fUL << LCD_PAL112_B14_0_Pos) /*!< LCD PAL112: B14_0 Mask */\r
-#define LCD_PAL112_I1_Pos 31 /*!< LCD PAL112: I1 Position */\r
-#define LCD_PAL112_I1_Msk (0x01UL << LCD_PAL112_I1_Pos) /*!< LCD PAL112: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL113 -------------------------------------------\r
-#define LCD_PAL113_R04_0_Pos 0 /*!< LCD PAL113: R04_0 Position */\r
-#define LCD_PAL113_R04_0_Msk (0x1fUL << LCD_PAL113_R04_0_Pos) /*!< LCD PAL113: R04_0 Mask */\r
-#define LCD_PAL113_G04_0_Pos 5 /*!< LCD PAL113: G04_0 Position */\r
-#define LCD_PAL113_G04_0_Msk (0x1fUL << LCD_PAL113_G04_0_Pos) /*!< LCD PAL113: G04_0 Mask */\r
-#define LCD_PAL113_B04_0_Pos 10 /*!< LCD PAL113: B04_0 Position */\r
-#define LCD_PAL113_B04_0_Msk (0x1fUL << LCD_PAL113_B04_0_Pos) /*!< LCD PAL113: B04_0 Mask */\r
-#define LCD_PAL113_I0_Pos 15 /*!< LCD PAL113: I0 Position */\r
-#define LCD_PAL113_I0_Msk (0x01UL << LCD_PAL113_I0_Pos) /*!< LCD PAL113: I0 Mask */\r
-#define LCD_PAL113_R14_0_Pos 16 /*!< LCD PAL113: R14_0 Position */\r
-#define LCD_PAL113_R14_0_Msk (0x1fUL << LCD_PAL113_R14_0_Pos) /*!< LCD PAL113: R14_0 Mask */\r
-#define LCD_PAL113_G14_0_Pos 21 /*!< LCD PAL113: G14_0 Position */\r
-#define LCD_PAL113_G14_0_Msk (0x1fUL << LCD_PAL113_G14_0_Pos) /*!< LCD PAL113: G14_0 Mask */\r
-#define LCD_PAL113_B14_0_Pos 26 /*!< LCD PAL113: B14_0 Position */\r
-#define LCD_PAL113_B14_0_Msk (0x1fUL << LCD_PAL113_B14_0_Pos) /*!< LCD PAL113: B14_0 Mask */\r
-#define LCD_PAL113_I1_Pos 31 /*!< LCD PAL113: I1 Position */\r
-#define LCD_PAL113_I1_Msk (0x01UL << LCD_PAL113_I1_Pos) /*!< LCD PAL113: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL114 -------------------------------------------\r
-#define LCD_PAL114_R04_0_Pos 0 /*!< LCD PAL114: R04_0 Position */\r
-#define LCD_PAL114_R04_0_Msk (0x1fUL << LCD_PAL114_R04_0_Pos) /*!< LCD PAL114: R04_0 Mask */\r
-#define LCD_PAL114_G04_0_Pos 5 /*!< LCD PAL114: G04_0 Position */\r
-#define LCD_PAL114_G04_0_Msk (0x1fUL << LCD_PAL114_G04_0_Pos) /*!< LCD PAL114: G04_0 Mask */\r
-#define LCD_PAL114_B04_0_Pos 10 /*!< LCD PAL114: B04_0 Position */\r
-#define LCD_PAL114_B04_0_Msk (0x1fUL << LCD_PAL114_B04_0_Pos) /*!< LCD PAL114: B04_0 Mask */\r
-#define LCD_PAL114_I0_Pos 15 /*!< LCD PAL114: I0 Position */\r
-#define LCD_PAL114_I0_Msk (0x01UL << LCD_PAL114_I0_Pos) /*!< LCD PAL114: I0 Mask */\r
-#define LCD_PAL114_R14_0_Pos 16 /*!< LCD PAL114: R14_0 Position */\r
-#define LCD_PAL114_R14_0_Msk (0x1fUL << LCD_PAL114_R14_0_Pos) /*!< LCD PAL114: R14_0 Mask */\r
-#define LCD_PAL114_G14_0_Pos 21 /*!< LCD PAL114: G14_0 Position */\r
-#define LCD_PAL114_G14_0_Msk (0x1fUL << LCD_PAL114_G14_0_Pos) /*!< LCD PAL114: G14_0 Mask */\r
-#define LCD_PAL114_B14_0_Pos 26 /*!< LCD PAL114: B14_0 Position */\r
-#define LCD_PAL114_B14_0_Msk (0x1fUL << LCD_PAL114_B14_0_Pos) /*!< LCD PAL114: B14_0 Mask */\r
-#define LCD_PAL114_I1_Pos 31 /*!< LCD PAL114: I1 Position */\r
-#define LCD_PAL114_I1_Msk (0x01UL << LCD_PAL114_I1_Pos) /*!< LCD PAL114: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL115 -------------------------------------------\r
-#define LCD_PAL115_R04_0_Pos 0 /*!< LCD PAL115: R04_0 Position */\r
-#define LCD_PAL115_R04_0_Msk (0x1fUL << LCD_PAL115_R04_0_Pos) /*!< LCD PAL115: R04_0 Mask */\r
-#define LCD_PAL115_G04_0_Pos 5 /*!< LCD PAL115: G04_0 Position */\r
-#define LCD_PAL115_G04_0_Msk (0x1fUL << LCD_PAL115_G04_0_Pos) /*!< LCD PAL115: G04_0 Mask */\r
-#define LCD_PAL115_B04_0_Pos 10 /*!< LCD PAL115: B04_0 Position */\r
-#define LCD_PAL115_B04_0_Msk (0x1fUL << LCD_PAL115_B04_0_Pos) /*!< LCD PAL115: B04_0 Mask */\r
-#define LCD_PAL115_I0_Pos 15 /*!< LCD PAL115: I0 Position */\r
-#define LCD_PAL115_I0_Msk (0x01UL << LCD_PAL115_I0_Pos) /*!< LCD PAL115: I0 Mask */\r
-#define LCD_PAL115_R14_0_Pos 16 /*!< LCD PAL115: R14_0 Position */\r
-#define LCD_PAL115_R14_0_Msk (0x1fUL << LCD_PAL115_R14_0_Pos) /*!< LCD PAL115: R14_0 Mask */\r
-#define LCD_PAL115_G14_0_Pos 21 /*!< LCD PAL115: G14_0 Position */\r
-#define LCD_PAL115_G14_0_Msk (0x1fUL << LCD_PAL115_G14_0_Pos) /*!< LCD PAL115: G14_0 Mask */\r
-#define LCD_PAL115_B14_0_Pos 26 /*!< LCD PAL115: B14_0 Position */\r
-#define LCD_PAL115_B14_0_Msk (0x1fUL << LCD_PAL115_B14_0_Pos) /*!< LCD PAL115: B14_0 Mask */\r
-#define LCD_PAL115_I1_Pos 31 /*!< LCD PAL115: I1 Position */\r
-#define LCD_PAL115_I1_Msk (0x01UL << LCD_PAL115_I1_Pos) /*!< LCD PAL115: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL116 -------------------------------------------\r
-#define LCD_PAL116_R04_0_Pos 0 /*!< LCD PAL116: R04_0 Position */\r
-#define LCD_PAL116_R04_0_Msk (0x1fUL << LCD_PAL116_R04_0_Pos) /*!< LCD PAL116: R04_0 Mask */\r
-#define LCD_PAL116_G04_0_Pos 5 /*!< LCD PAL116: G04_0 Position */\r
-#define LCD_PAL116_G04_0_Msk (0x1fUL << LCD_PAL116_G04_0_Pos) /*!< LCD PAL116: G04_0 Mask */\r
-#define LCD_PAL116_B04_0_Pos 10 /*!< LCD PAL116: B04_0 Position */\r
-#define LCD_PAL116_B04_0_Msk (0x1fUL << LCD_PAL116_B04_0_Pos) /*!< LCD PAL116: B04_0 Mask */\r
-#define LCD_PAL116_I0_Pos 15 /*!< LCD PAL116: I0 Position */\r
-#define LCD_PAL116_I0_Msk (0x01UL << LCD_PAL116_I0_Pos) /*!< LCD PAL116: I0 Mask */\r
-#define LCD_PAL116_R14_0_Pos 16 /*!< LCD PAL116: R14_0 Position */\r
-#define LCD_PAL116_R14_0_Msk (0x1fUL << LCD_PAL116_R14_0_Pos) /*!< LCD PAL116: R14_0 Mask */\r
-#define LCD_PAL116_G14_0_Pos 21 /*!< LCD PAL116: G14_0 Position */\r
-#define LCD_PAL116_G14_0_Msk (0x1fUL << LCD_PAL116_G14_0_Pos) /*!< LCD PAL116: G14_0 Mask */\r
-#define LCD_PAL116_B14_0_Pos 26 /*!< LCD PAL116: B14_0 Position */\r
-#define LCD_PAL116_B14_0_Msk (0x1fUL << LCD_PAL116_B14_0_Pos) /*!< LCD PAL116: B14_0 Mask */\r
-#define LCD_PAL116_I1_Pos 31 /*!< LCD PAL116: I1 Position */\r
-#define LCD_PAL116_I1_Msk (0x01UL << LCD_PAL116_I1_Pos) /*!< LCD PAL116: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL117 -------------------------------------------\r
-#define LCD_PAL117_R04_0_Pos 0 /*!< LCD PAL117: R04_0 Position */\r
-#define LCD_PAL117_R04_0_Msk (0x1fUL << LCD_PAL117_R04_0_Pos) /*!< LCD PAL117: R04_0 Mask */\r
-#define LCD_PAL117_G04_0_Pos 5 /*!< LCD PAL117: G04_0 Position */\r
-#define LCD_PAL117_G04_0_Msk (0x1fUL << LCD_PAL117_G04_0_Pos) /*!< LCD PAL117: G04_0 Mask */\r
-#define LCD_PAL117_B04_0_Pos 10 /*!< LCD PAL117: B04_0 Position */\r
-#define LCD_PAL117_B04_0_Msk (0x1fUL << LCD_PAL117_B04_0_Pos) /*!< LCD PAL117: B04_0 Mask */\r
-#define LCD_PAL117_I0_Pos 15 /*!< LCD PAL117: I0 Position */\r
-#define LCD_PAL117_I0_Msk (0x01UL << LCD_PAL117_I0_Pos) /*!< LCD PAL117: I0 Mask */\r
-#define LCD_PAL117_R14_0_Pos 16 /*!< LCD PAL117: R14_0 Position */\r
-#define LCD_PAL117_R14_0_Msk (0x1fUL << LCD_PAL117_R14_0_Pos) /*!< LCD PAL117: R14_0 Mask */\r
-#define LCD_PAL117_G14_0_Pos 21 /*!< LCD PAL117: G14_0 Position */\r
-#define LCD_PAL117_G14_0_Msk (0x1fUL << LCD_PAL117_G14_0_Pos) /*!< LCD PAL117: G14_0 Mask */\r
-#define LCD_PAL117_B14_0_Pos 26 /*!< LCD PAL117: B14_0 Position */\r
-#define LCD_PAL117_B14_0_Msk (0x1fUL << LCD_PAL117_B14_0_Pos) /*!< LCD PAL117: B14_0 Mask */\r
-#define LCD_PAL117_I1_Pos 31 /*!< LCD PAL117: I1 Position */\r
-#define LCD_PAL117_I1_Msk (0x01UL << LCD_PAL117_I1_Pos) /*!< LCD PAL117: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL118 -------------------------------------------\r
-#define LCD_PAL118_R04_0_Pos 0 /*!< LCD PAL118: R04_0 Position */\r
-#define LCD_PAL118_R04_0_Msk (0x1fUL << LCD_PAL118_R04_0_Pos) /*!< LCD PAL118: R04_0 Mask */\r
-#define LCD_PAL118_G04_0_Pos 5 /*!< LCD PAL118: G04_0 Position */\r
-#define LCD_PAL118_G04_0_Msk (0x1fUL << LCD_PAL118_G04_0_Pos) /*!< LCD PAL118: G04_0 Mask */\r
-#define LCD_PAL118_B04_0_Pos 10 /*!< LCD PAL118: B04_0 Position */\r
-#define LCD_PAL118_B04_0_Msk (0x1fUL << LCD_PAL118_B04_0_Pos) /*!< LCD PAL118: B04_0 Mask */\r
-#define LCD_PAL118_I0_Pos 15 /*!< LCD PAL118: I0 Position */\r
-#define LCD_PAL118_I0_Msk (0x01UL << LCD_PAL118_I0_Pos) /*!< LCD PAL118: I0 Mask */\r
-#define LCD_PAL118_R14_0_Pos 16 /*!< LCD PAL118: R14_0 Position */\r
-#define LCD_PAL118_R14_0_Msk (0x1fUL << LCD_PAL118_R14_0_Pos) /*!< LCD PAL118: R14_0 Mask */\r
-#define LCD_PAL118_G14_0_Pos 21 /*!< LCD PAL118: G14_0 Position */\r
-#define LCD_PAL118_G14_0_Msk (0x1fUL << LCD_PAL118_G14_0_Pos) /*!< LCD PAL118: G14_0 Mask */\r
-#define LCD_PAL118_B14_0_Pos 26 /*!< LCD PAL118: B14_0 Position */\r
-#define LCD_PAL118_B14_0_Msk (0x1fUL << LCD_PAL118_B14_0_Pos) /*!< LCD PAL118: B14_0 Mask */\r
-#define LCD_PAL118_I1_Pos 31 /*!< LCD PAL118: I1 Position */\r
-#define LCD_PAL118_I1_Msk (0x01UL << LCD_PAL118_I1_Pos) /*!< LCD PAL118: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL119 -------------------------------------------\r
-#define LCD_PAL119_R04_0_Pos 0 /*!< LCD PAL119: R04_0 Position */\r
-#define LCD_PAL119_R04_0_Msk (0x1fUL << LCD_PAL119_R04_0_Pos) /*!< LCD PAL119: R04_0 Mask */\r
-#define LCD_PAL119_G04_0_Pos 5 /*!< LCD PAL119: G04_0 Position */\r
-#define LCD_PAL119_G04_0_Msk (0x1fUL << LCD_PAL119_G04_0_Pos) /*!< LCD PAL119: G04_0 Mask */\r
-#define LCD_PAL119_B04_0_Pos 10 /*!< LCD PAL119: B04_0 Position */\r
-#define LCD_PAL119_B04_0_Msk (0x1fUL << LCD_PAL119_B04_0_Pos) /*!< LCD PAL119: B04_0 Mask */\r
-#define LCD_PAL119_I0_Pos 15 /*!< LCD PAL119: I0 Position */\r
-#define LCD_PAL119_I0_Msk (0x01UL << LCD_PAL119_I0_Pos) /*!< LCD PAL119: I0 Mask */\r
-#define LCD_PAL119_R14_0_Pos 16 /*!< LCD PAL119: R14_0 Position */\r
-#define LCD_PAL119_R14_0_Msk (0x1fUL << LCD_PAL119_R14_0_Pos) /*!< LCD PAL119: R14_0 Mask */\r
-#define LCD_PAL119_G14_0_Pos 21 /*!< LCD PAL119: G14_0 Position */\r
-#define LCD_PAL119_G14_0_Msk (0x1fUL << LCD_PAL119_G14_0_Pos) /*!< LCD PAL119: G14_0 Mask */\r
-#define LCD_PAL119_B14_0_Pos 26 /*!< LCD PAL119: B14_0 Position */\r
-#define LCD_PAL119_B14_0_Msk (0x1fUL << LCD_PAL119_B14_0_Pos) /*!< LCD PAL119: B14_0 Mask */\r
-#define LCD_PAL119_I1_Pos 31 /*!< LCD PAL119: I1 Position */\r
-#define LCD_PAL119_I1_Msk (0x01UL << LCD_PAL119_I1_Pos) /*!< LCD PAL119: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL120 -------------------------------------------\r
-#define LCD_PAL120_R04_0_Pos 0 /*!< LCD PAL120: R04_0 Position */\r
-#define LCD_PAL120_R04_0_Msk (0x1fUL << LCD_PAL120_R04_0_Pos) /*!< LCD PAL120: R04_0 Mask */\r
-#define LCD_PAL120_G04_0_Pos 5 /*!< LCD PAL120: G04_0 Position */\r
-#define LCD_PAL120_G04_0_Msk (0x1fUL << LCD_PAL120_G04_0_Pos) /*!< LCD PAL120: G04_0 Mask */\r
-#define LCD_PAL120_B04_0_Pos 10 /*!< LCD PAL120: B04_0 Position */\r
-#define LCD_PAL120_B04_0_Msk (0x1fUL << LCD_PAL120_B04_0_Pos) /*!< LCD PAL120: B04_0 Mask */\r
-#define LCD_PAL120_I0_Pos 15 /*!< LCD PAL120: I0 Position */\r
-#define LCD_PAL120_I0_Msk (0x01UL << LCD_PAL120_I0_Pos) /*!< LCD PAL120: I0 Mask */\r
-#define LCD_PAL120_R14_0_Pos 16 /*!< LCD PAL120: R14_0 Position */\r
-#define LCD_PAL120_R14_0_Msk (0x1fUL << LCD_PAL120_R14_0_Pos) /*!< LCD PAL120: R14_0 Mask */\r
-#define LCD_PAL120_G14_0_Pos 21 /*!< LCD PAL120: G14_0 Position */\r
-#define LCD_PAL120_G14_0_Msk (0x1fUL << LCD_PAL120_G14_0_Pos) /*!< LCD PAL120: G14_0 Mask */\r
-#define LCD_PAL120_B14_0_Pos 26 /*!< LCD PAL120: B14_0 Position */\r
-#define LCD_PAL120_B14_0_Msk (0x1fUL << LCD_PAL120_B14_0_Pos) /*!< LCD PAL120: B14_0 Mask */\r
-#define LCD_PAL120_I1_Pos 31 /*!< LCD PAL120: I1 Position */\r
-#define LCD_PAL120_I1_Msk (0x01UL << LCD_PAL120_I1_Pos) /*!< LCD PAL120: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL121 -------------------------------------------\r
-#define LCD_PAL121_R04_0_Pos 0 /*!< LCD PAL121: R04_0 Position */\r
-#define LCD_PAL121_R04_0_Msk (0x1fUL << LCD_PAL121_R04_0_Pos) /*!< LCD PAL121: R04_0 Mask */\r
-#define LCD_PAL121_G04_0_Pos 5 /*!< LCD PAL121: G04_0 Position */\r
-#define LCD_PAL121_G04_0_Msk (0x1fUL << LCD_PAL121_G04_0_Pos) /*!< LCD PAL121: G04_0 Mask */\r
-#define LCD_PAL121_B04_0_Pos 10 /*!< LCD PAL121: B04_0 Position */\r
-#define LCD_PAL121_B04_0_Msk (0x1fUL << LCD_PAL121_B04_0_Pos) /*!< LCD PAL121: B04_0 Mask */\r
-#define LCD_PAL121_I0_Pos 15 /*!< LCD PAL121: I0 Position */\r
-#define LCD_PAL121_I0_Msk (0x01UL << LCD_PAL121_I0_Pos) /*!< LCD PAL121: I0 Mask */\r
-#define LCD_PAL121_R14_0_Pos 16 /*!< LCD PAL121: R14_0 Position */\r
-#define LCD_PAL121_R14_0_Msk (0x1fUL << LCD_PAL121_R14_0_Pos) /*!< LCD PAL121: R14_0 Mask */\r
-#define LCD_PAL121_G14_0_Pos 21 /*!< LCD PAL121: G14_0 Position */\r
-#define LCD_PAL121_G14_0_Msk (0x1fUL << LCD_PAL121_G14_0_Pos) /*!< LCD PAL121: G14_0 Mask */\r
-#define LCD_PAL121_B14_0_Pos 26 /*!< LCD PAL121: B14_0 Position */\r
-#define LCD_PAL121_B14_0_Msk (0x1fUL << LCD_PAL121_B14_0_Pos) /*!< LCD PAL121: B14_0 Mask */\r
-#define LCD_PAL121_I1_Pos 31 /*!< LCD PAL121: I1 Position */\r
-#define LCD_PAL121_I1_Msk (0x01UL << LCD_PAL121_I1_Pos) /*!< LCD PAL121: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL122 -------------------------------------------\r
-#define LCD_PAL122_R04_0_Pos 0 /*!< LCD PAL122: R04_0 Position */\r
-#define LCD_PAL122_R04_0_Msk (0x1fUL << LCD_PAL122_R04_0_Pos) /*!< LCD PAL122: R04_0 Mask */\r
-#define LCD_PAL122_G04_0_Pos 5 /*!< LCD PAL122: G04_0 Position */\r
-#define LCD_PAL122_G04_0_Msk (0x1fUL << LCD_PAL122_G04_0_Pos) /*!< LCD PAL122: G04_0 Mask */\r
-#define LCD_PAL122_B04_0_Pos 10 /*!< LCD PAL122: B04_0 Position */\r
-#define LCD_PAL122_B04_0_Msk (0x1fUL << LCD_PAL122_B04_0_Pos) /*!< LCD PAL122: B04_0 Mask */\r
-#define LCD_PAL122_I0_Pos 15 /*!< LCD PAL122: I0 Position */\r
-#define LCD_PAL122_I0_Msk (0x01UL << LCD_PAL122_I0_Pos) /*!< LCD PAL122: I0 Mask */\r
-#define LCD_PAL122_R14_0_Pos 16 /*!< LCD PAL122: R14_0 Position */\r
-#define LCD_PAL122_R14_0_Msk (0x1fUL << LCD_PAL122_R14_0_Pos) /*!< LCD PAL122: R14_0 Mask */\r
-#define LCD_PAL122_G14_0_Pos 21 /*!< LCD PAL122: G14_0 Position */\r
-#define LCD_PAL122_G14_0_Msk (0x1fUL << LCD_PAL122_G14_0_Pos) /*!< LCD PAL122: G14_0 Mask */\r
-#define LCD_PAL122_B14_0_Pos 26 /*!< LCD PAL122: B14_0 Position */\r
-#define LCD_PAL122_B14_0_Msk (0x1fUL << LCD_PAL122_B14_0_Pos) /*!< LCD PAL122: B14_0 Mask */\r
-#define LCD_PAL122_I1_Pos 31 /*!< LCD PAL122: I1 Position */\r
-#define LCD_PAL122_I1_Msk (0x01UL << LCD_PAL122_I1_Pos) /*!< LCD PAL122: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL123 -------------------------------------------\r
-#define LCD_PAL123_R04_0_Pos 0 /*!< LCD PAL123: R04_0 Position */\r
-#define LCD_PAL123_R04_0_Msk (0x1fUL << LCD_PAL123_R04_0_Pos) /*!< LCD PAL123: R04_0 Mask */\r
-#define LCD_PAL123_G04_0_Pos 5 /*!< LCD PAL123: G04_0 Position */\r
-#define LCD_PAL123_G04_0_Msk (0x1fUL << LCD_PAL123_G04_0_Pos) /*!< LCD PAL123: G04_0 Mask */\r
-#define LCD_PAL123_B04_0_Pos 10 /*!< LCD PAL123: B04_0 Position */\r
-#define LCD_PAL123_B04_0_Msk (0x1fUL << LCD_PAL123_B04_0_Pos) /*!< LCD PAL123: B04_0 Mask */\r
-#define LCD_PAL123_I0_Pos 15 /*!< LCD PAL123: I0 Position */\r
-#define LCD_PAL123_I0_Msk (0x01UL << LCD_PAL123_I0_Pos) /*!< LCD PAL123: I0 Mask */\r
-#define LCD_PAL123_R14_0_Pos 16 /*!< LCD PAL123: R14_0 Position */\r
-#define LCD_PAL123_R14_0_Msk (0x1fUL << LCD_PAL123_R14_0_Pos) /*!< LCD PAL123: R14_0 Mask */\r
-#define LCD_PAL123_G14_0_Pos 21 /*!< LCD PAL123: G14_0 Position */\r
-#define LCD_PAL123_G14_0_Msk (0x1fUL << LCD_PAL123_G14_0_Pos) /*!< LCD PAL123: G14_0 Mask */\r
-#define LCD_PAL123_B14_0_Pos 26 /*!< LCD PAL123: B14_0 Position */\r
-#define LCD_PAL123_B14_0_Msk (0x1fUL << LCD_PAL123_B14_0_Pos) /*!< LCD PAL123: B14_0 Mask */\r
-#define LCD_PAL123_I1_Pos 31 /*!< LCD PAL123: I1 Position */\r
-#define LCD_PAL123_I1_Msk (0x01UL << LCD_PAL123_I1_Pos) /*!< LCD PAL123: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL124 -------------------------------------------\r
-#define LCD_PAL124_R04_0_Pos 0 /*!< LCD PAL124: R04_0 Position */\r
-#define LCD_PAL124_R04_0_Msk (0x1fUL << LCD_PAL124_R04_0_Pos) /*!< LCD PAL124: R04_0 Mask */\r
-#define LCD_PAL124_G04_0_Pos 5 /*!< LCD PAL124: G04_0 Position */\r
-#define LCD_PAL124_G04_0_Msk (0x1fUL << LCD_PAL124_G04_0_Pos) /*!< LCD PAL124: G04_0 Mask */\r
-#define LCD_PAL124_B04_0_Pos 10 /*!< LCD PAL124: B04_0 Position */\r
-#define LCD_PAL124_B04_0_Msk (0x1fUL << LCD_PAL124_B04_0_Pos) /*!< LCD PAL124: B04_0 Mask */\r
-#define LCD_PAL124_I0_Pos 15 /*!< LCD PAL124: I0 Position */\r
-#define LCD_PAL124_I0_Msk (0x01UL << LCD_PAL124_I0_Pos) /*!< LCD PAL124: I0 Mask */\r
-#define LCD_PAL124_R14_0_Pos 16 /*!< LCD PAL124: R14_0 Position */\r
-#define LCD_PAL124_R14_0_Msk (0x1fUL << LCD_PAL124_R14_0_Pos) /*!< LCD PAL124: R14_0 Mask */\r
-#define LCD_PAL124_G14_0_Pos 21 /*!< LCD PAL124: G14_0 Position */\r
-#define LCD_PAL124_G14_0_Msk (0x1fUL << LCD_PAL124_G14_0_Pos) /*!< LCD PAL124: G14_0 Mask */\r
-#define LCD_PAL124_B14_0_Pos 26 /*!< LCD PAL124: B14_0 Position */\r
-#define LCD_PAL124_B14_0_Msk (0x1fUL << LCD_PAL124_B14_0_Pos) /*!< LCD PAL124: B14_0 Mask */\r
-#define LCD_PAL124_I1_Pos 31 /*!< LCD PAL124: I1 Position */\r
-#define LCD_PAL124_I1_Msk (0x01UL << LCD_PAL124_I1_Pos) /*!< LCD PAL124: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL125 -------------------------------------------\r
-#define LCD_PAL125_R04_0_Pos 0 /*!< LCD PAL125: R04_0 Position */\r
-#define LCD_PAL125_R04_0_Msk (0x1fUL << LCD_PAL125_R04_0_Pos) /*!< LCD PAL125: R04_0 Mask */\r
-#define LCD_PAL125_G04_0_Pos 5 /*!< LCD PAL125: G04_0 Position */\r
-#define LCD_PAL125_G04_0_Msk (0x1fUL << LCD_PAL125_G04_0_Pos) /*!< LCD PAL125: G04_0 Mask */\r
-#define LCD_PAL125_B04_0_Pos 10 /*!< LCD PAL125: B04_0 Position */\r
-#define LCD_PAL125_B04_0_Msk (0x1fUL << LCD_PAL125_B04_0_Pos) /*!< LCD PAL125: B04_0 Mask */\r
-#define LCD_PAL125_I0_Pos 15 /*!< LCD PAL125: I0 Position */\r
-#define LCD_PAL125_I0_Msk (0x01UL << LCD_PAL125_I0_Pos) /*!< LCD PAL125: I0 Mask */\r
-#define LCD_PAL125_R14_0_Pos 16 /*!< LCD PAL125: R14_0 Position */\r
-#define LCD_PAL125_R14_0_Msk (0x1fUL << LCD_PAL125_R14_0_Pos) /*!< LCD PAL125: R14_0 Mask */\r
-#define LCD_PAL125_G14_0_Pos 21 /*!< LCD PAL125: G14_0 Position */\r
-#define LCD_PAL125_G14_0_Msk (0x1fUL << LCD_PAL125_G14_0_Pos) /*!< LCD PAL125: G14_0 Mask */\r
-#define LCD_PAL125_B14_0_Pos 26 /*!< LCD PAL125: B14_0 Position */\r
-#define LCD_PAL125_B14_0_Msk (0x1fUL << LCD_PAL125_B14_0_Pos) /*!< LCD PAL125: B14_0 Mask */\r
-#define LCD_PAL125_I1_Pos 31 /*!< LCD PAL125: I1 Position */\r
-#define LCD_PAL125_I1_Msk (0x01UL << LCD_PAL125_I1_Pos) /*!< LCD PAL125: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL126 -------------------------------------------\r
-#define LCD_PAL126_R04_0_Pos 0 /*!< LCD PAL126: R04_0 Position */\r
-#define LCD_PAL126_R04_0_Msk (0x1fUL << LCD_PAL126_R04_0_Pos) /*!< LCD PAL126: R04_0 Mask */\r
-#define LCD_PAL126_G04_0_Pos 5 /*!< LCD PAL126: G04_0 Position */\r
-#define LCD_PAL126_G04_0_Msk (0x1fUL << LCD_PAL126_G04_0_Pos) /*!< LCD PAL126: G04_0 Mask */\r
-#define LCD_PAL126_B04_0_Pos 10 /*!< LCD PAL126: B04_0 Position */\r
-#define LCD_PAL126_B04_0_Msk (0x1fUL << LCD_PAL126_B04_0_Pos) /*!< LCD PAL126: B04_0 Mask */\r
-#define LCD_PAL126_I0_Pos 15 /*!< LCD PAL126: I0 Position */\r
-#define LCD_PAL126_I0_Msk (0x01UL << LCD_PAL126_I0_Pos) /*!< LCD PAL126: I0 Mask */\r
-#define LCD_PAL126_R14_0_Pos 16 /*!< LCD PAL126: R14_0 Position */\r
-#define LCD_PAL126_R14_0_Msk (0x1fUL << LCD_PAL126_R14_0_Pos) /*!< LCD PAL126: R14_0 Mask */\r
-#define LCD_PAL126_G14_0_Pos 21 /*!< LCD PAL126: G14_0 Position */\r
-#define LCD_PAL126_G14_0_Msk (0x1fUL << LCD_PAL126_G14_0_Pos) /*!< LCD PAL126: G14_0 Mask */\r
-#define LCD_PAL126_B14_0_Pos 26 /*!< LCD PAL126: B14_0 Position */\r
-#define LCD_PAL126_B14_0_Msk (0x1fUL << LCD_PAL126_B14_0_Pos) /*!< LCD PAL126: B14_0 Mask */\r
-#define LCD_PAL126_I1_Pos 31 /*!< LCD PAL126: I1 Position */\r
-#define LCD_PAL126_I1_Msk (0x01UL << LCD_PAL126_I1_Pos) /*!< LCD PAL126: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL127 -------------------------------------------\r
-#define LCD_PAL127_R04_0_Pos 0 /*!< LCD PAL127: R04_0 Position */\r
-#define LCD_PAL127_R04_0_Msk (0x1fUL << LCD_PAL127_R04_0_Pos) /*!< LCD PAL127: R04_0 Mask */\r
-#define LCD_PAL127_G04_0_Pos 5 /*!< LCD PAL127: G04_0 Position */\r
-#define LCD_PAL127_G04_0_Msk (0x1fUL << LCD_PAL127_G04_0_Pos) /*!< LCD PAL127: G04_0 Mask */\r
-#define LCD_PAL127_B04_0_Pos 10 /*!< LCD PAL127: B04_0 Position */\r
-#define LCD_PAL127_B04_0_Msk (0x1fUL << LCD_PAL127_B04_0_Pos) /*!< LCD PAL127: B04_0 Mask */\r
-#define LCD_PAL127_I0_Pos 15 /*!< LCD PAL127: I0 Position */\r
-#define LCD_PAL127_I0_Msk (0x01UL << LCD_PAL127_I0_Pos) /*!< LCD PAL127: I0 Mask */\r
-#define LCD_PAL127_R14_0_Pos 16 /*!< LCD PAL127: R14_0 Position */\r
-#define LCD_PAL127_R14_0_Msk (0x1fUL << LCD_PAL127_R14_0_Pos) /*!< LCD PAL127: R14_0 Mask */\r
-#define LCD_PAL127_G14_0_Pos 21 /*!< LCD PAL127: G14_0 Position */\r
-#define LCD_PAL127_G14_0_Msk (0x1fUL << LCD_PAL127_G14_0_Pos) /*!< LCD PAL127: G14_0 Mask */\r
-#define LCD_PAL127_B14_0_Pos 26 /*!< LCD PAL127: B14_0 Position */\r
-#define LCD_PAL127_B14_0_Msk (0x1fUL << LCD_PAL127_B14_0_Pos) /*!< LCD PAL127: B14_0 Mask */\r
-#define LCD_PAL127_I1_Pos 31 /*!< LCD PAL127: I1 Position */\r
-#define LCD_PAL127_I1_Msk (0x01UL << LCD_PAL127_I1_Pos) /*!< LCD PAL127: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL128 -------------------------------------------\r
-#define LCD_PAL128_R04_0_Pos 0 /*!< LCD PAL128: R04_0 Position */\r
-#define LCD_PAL128_R04_0_Msk (0x1fUL << LCD_PAL128_R04_0_Pos) /*!< LCD PAL128: R04_0 Mask */\r
-#define LCD_PAL128_G04_0_Pos 5 /*!< LCD PAL128: G04_0 Position */\r
-#define LCD_PAL128_G04_0_Msk (0x1fUL << LCD_PAL128_G04_0_Pos) /*!< LCD PAL128: G04_0 Mask */\r
-#define LCD_PAL128_B04_0_Pos 10 /*!< LCD PAL128: B04_0 Position */\r
-#define LCD_PAL128_B04_0_Msk (0x1fUL << LCD_PAL128_B04_0_Pos) /*!< LCD PAL128: B04_0 Mask */\r
-#define LCD_PAL128_I0_Pos 15 /*!< LCD PAL128: I0 Position */\r
-#define LCD_PAL128_I0_Msk (0x01UL << LCD_PAL128_I0_Pos) /*!< LCD PAL128: I0 Mask */\r
-#define LCD_PAL128_R14_0_Pos 16 /*!< LCD PAL128: R14_0 Position */\r
-#define LCD_PAL128_R14_0_Msk (0x1fUL << LCD_PAL128_R14_0_Pos) /*!< LCD PAL128: R14_0 Mask */\r
-#define LCD_PAL128_G14_0_Pos 21 /*!< LCD PAL128: G14_0 Position */\r
-#define LCD_PAL128_G14_0_Msk (0x1fUL << LCD_PAL128_G14_0_Pos) /*!< LCD PAL128: G14_0 Mask */\r
-#define LCD_PAL128_B14_0_Pos 26 /*!< LCD PAL128: B14_0 Position */\r
-#define LCD_PAL128_B14_0_Msk (0x1fUL << LCD_PAL128_B14_0_Pos) /*!< LCD PAL128: B14_0 Mask */\r
-#define LCD_PAL128_I1_Pos 31 /*!< LCD PAL128: I1 Position */\r
-#define LCD_PAL128_I1_Msk (0x01UL << LCD_PAL128_I1_Pos) /*!< LCD PAL128: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL129 -------------------------------------------\r
-#define LCD_PAL129_R04_0_Pos 0 /*!< LCD PAL129: R04_0 Position */\r
-#define LCD_PAL129_R04_0_Msk (0x1fUL << LCD_PAL129_R04_0_Pos) /*!< LCD PAL129: R04_0 Mask */\r
-#define LCD_PAL129_G04_0_Pos 5 /*!< LCD PAL129: G04_0 Position */\r
-#define LCD_PAL129_G04_0_Msk (0x1fUL << LCD_PAL129_G04_0_Pos) /*!< LCD PAL129: G04_0 Mask */\r
-#define LCD_PAL129_B04_0_Pos 10 /*!< LCD PAL129: B04_0 Position */\r
-#define LCD_PAL129_B04_0_Msk (0x1fUL << LCD_PAL129_B04_0_Pos) /*!< LCD PAL129: B04_0 Mask */\r
-#define LCD_PAL129_I0_Pos 15 /*!< LCD PAL129: I0 Position */\r
-#define LCD_PAL129_I0_Msk (0x01UL << LCD_PAL129_I0_Pos) /*!< LCD PAL129: I0 Mask */\r
-#define LCD_PAL129_R14_0_Pos 16 /*!< LCD PAL129: R14_0 Position */\r
-#define LCD_PAL129_R14_0_Msk (0x1fUL << LCD_PAL129_R14_0_Pos) /*!< LCD PAL129: R14_0 Mask */\r
-#define LCD_PAL129_G14_0_Pos 21 /*!< LCD PAL129: G14_0 Position */\r
-#define LCD_PAL129_G14_0_Msk (0x1fUL << LCD_PAL129_G14_0_Pos) /*!< LCD PAL129: G14_0 Mask */\r
-#define LCD_PAL129_B14_0_Pos 26 /*!< LCD PAL129: B14_0 Position */\r
-#define LCD_PAL129_B14_0_Msk (0x1fUL << LCD_PAL129_B14_0_Pos) /*!< LCD PAL129: B14_0 Mask */\r
-#define LCD_PAL129_I1_Pos 31 /*!< LCD PAL129: I1 Position */\r
-#define LCD_PAL129_I1_Msk (0x01UL << LCD_PAL129_I1_Pos) /*!< LCD PAL129: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL130 -------------------------------------------\r
-#define LCD_PAL130_R04_0_Pos 0 /*!< LCD PAL130: R04_0 Position */\r
-#define LCD_PAL130_R04_0_Msk (0x1fUL << LCD_PAL130_R04_0_Pos) /*!< LCD PAL130: R04_0 Mask */\r
-#define LCD_PAL130_G04_0_Pos 5 /*!< LCD PAL130: G04_0 Position */\r
-#define LCD_PAL130_G04_0_Msk (0x1fUL << LCD_PAL130_G04_0_Pos) /*!< LCD PAL130: G04_0 Mask */\r
-#define LCD_PAL130_B04_0_Pos 10 /*!< LCD PAL130: B04_0 Position */\r
-#define LCD_PAL130_B04_0_Msk (0x1fUL << LCD_PAL130_B04_0_Pos) /*!< LCD PAL130: B04_0 Mask */\r
-#define LCD_PAL130_I0_Pos 15 /*!< LCD PAL130: I0 Position */\r
-#define LCD_PAL130_I0_Msk (0x01UL << LCD_PAL130_I0_Pos) /*!< LCD PAL130: I0 Mask */\r
-#define LCD_PAL130_R14_0_Pos 16 /*!< LCD PAL130: R14_0 Position */\r
-#define LCD_PAL130_R14_0_Msk (0x1fUL << LCD_PAL130_R14_0_Pos) /*!< LCD PAL130: R14_0 Mask */\r
-#define LCD_PAL130_G14_0_Pos 21 /*!< LCD PAL130: G14_0 Position */\r
-#define LCD_PAL130_G14_0_Msk (0x1fUL << LCD_PAL130_G14_0_Pos) /*!< LCD PAL130: G14_0 Mask */\r
-#define LCD_PAL130_B14_0_Pos 26 /*!< LCD PAL130: B14_0 Position */\r
-#define LCD_PAL130_B14_0_Msk (0x1fUL << LCD_PAL130_B14_0_Pos) /*!< LCD PAL130: B14_0 Mask */\r
-#define LCD_PAL130_I1_Pos 31 /*!< LCD PAL130: I1 Position */\r
-#define LCD_PAL130_I1_Msk (0x01UL << LCD_PAL130_I1_Pos) /*!< LCD PAL130: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL131 -------------------------------------------\r
-#define LCD_PAL131_R04_0_Pos 0 /*!< LCD PAL131: R04_0 Position */\r
-#define LCD_PAL131_R04_0_Msk (0x1fUL << LCD_PAL131_R04_0_Pos) /*!< LCD PAL131: R04_0 Mask */\r
-#define LCD_PAL131_G04_0_Pos 5 /*!< LCD PAL131: G04_0 Position */\r
-#define LCD_PAL131_G04_0_Msk (0x1fUL << LCD_PAL131_G04_0_Pos) /*!< LCD PAL131: G04_0 Mask */\r
-#define LCD_PAL131_B04_0_Pos 10 /*!< LCD PAL131: B04_0 Position */\r
-#define LCD_PAL131_B04_0_Msk (0x1fUL << LCD_PAL131_B04_0_Pos) /*!< LCD PAL131: B04_0 Mask */\r
-#define LCD_PAL131_I0_Pos 15 /*!< LCD PAL131: I0 Position */\r
-#define LCD_PAL131_I0_Msk (0x01UL << LCD_PAL131_I0_Pos) /*!< LCD PAL131: I0 Mask */\r
-#define LCD_PAL131_R14_0_Pos 16 /*!< LCD PAL131: R14_0 Position */\r
-#define LCD_PAL131_R14_0_Msk (0x1fUL << LCD_PAL131_R14_0_Pos) /*!< LCD PAL131: R14_0 Mask */\r
-#define LCD_PAL131_G14_0_Pos 21 /*!< LCD PAL131: G14_0 Position */\r
-#define LCD_PAL131_G14_0_Msk (0x1fUL << LCD_PAL131_G14_0_Pos) /*!< LCD PAL131: G14_0 Mask */\r
-#define LCD_PAL131_B14_0_Pos 26 /*!< LCD PAL131: B14_0 Position */\r
-#define LCD_PAL131_B14_0_Msk (0x1fUL << LCD_PAL131_B14_0_Pos) /*!< LCD PAL131: B14_0 Mask */\r
-#define LCD_PAL131_I1_Pos 31 /*!< LCD PAL131: I1 Position */\r
-#define LCD_PAL131_I1_Msk (0x01UL << LCD_PAL131_I1_Pos) /*!< LCD PAL131: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL132 -------------------------------------------\r
-#define LCD_PAL132_R04_0_Pos 0 /*!< LCD PAL132: R04_0 Position */\r
-#define LCD_PAL132_R04_0_Msk (0x1fUL << LCD_PAL132_R04_0_Pos) /*!< LCD PAL132: R04_0 Mask */\r
-#define LCD_PAL132_G04_0_Pos 5 /*!< LCD PAL132: G04_0 Position */\r
-#define LCD_PAL132_G04_0_Msk (0x1fUL << LCD_PAL132_G04_0_Pos) /*!< LCD PAL132: G04_0 Mask */\r
-#define LCD_PAL132_B04_0_Pos 10 /*!< LCD PAL132: B04_0 Position */\r
-#define LCD_PAL132_B04_0_Msk (0x1fUL << LCD_PAL132_B04_0_Pos) /*!< LCD PAL132: B04_0 Mask */\r
-#define LCD_PAL132_I0_Pos 15 /*!< LCD PAL132: I0 Position */\r
-#define LCD_PAL132_I0_Msk (0x01UL << LCD_PAL132_I0_Pos) /*!< LCD PAL132: I0 Mask */\r
-#define LCD_PAL132_R14_0_Pos 16 /*!< LCD PAL132: R14_0 Position */\r
-#define LCD_PAL132_R14_0_Msk (0x1fUL << LCD_PAL132_R14_0_Pos) /*!< LCD PAL132: R14_0 Mask */\r
-#define LCD_PAL132_G14_0_Pos 21 /*!< LCD PAL132: G14_0 Position */\r
-#define LCD_PAL132_G14_0_Msk (0x1fUL << LCD_PAL132_G14_0_Pos) /*!< LCD PAL132: G14_0 Mask */\r
-#define LCD_PAL132_B14_0_Pos 26 /*!< LCD PAL132: B14_0 Position */\r
-#define LCD_PAL132_B14_0_Msk (0x1fUL << LCD_PAL132_B14_0_Pos) /*!< LCD PAL132: B14_0 Mask */\r
-#define LCD_PAL132_I1_Pos 31 /*!< LCD PAL132: I1 Position */\r
-#define LCD_PAL132_I1_Msk (0x01UL << LCD_PAL132_I1_Pos) /*!< LCD PAL132: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL133 -------------------------------------------\r
-#define LCD_PAL133_R04_0_Pos 0 /*!< LCD PAL133: R04_0 Position */\r
-#define LCD_PAL133_R04_0_Msk (0x1fUL << LCD_PAL133_R04_0_Pos) /*!< LCD PAL133: R04_0 Mask */\r
-#define LCD_PAL133_G04_0_Pos 5 /*!< LCD PAL133: G04_0 Position */\r
-#define LCD_PAL133_G04_0_Msk (0x1fUL << LCD_PAL133_G04_0_Pos) /*!< LCD PAL133: G04_0 Mask */\r
-#define LCD_PAL133_B04_0_Pos 10 /*!< LCD PAL133: B04_0 Position */\r
-#define LCD_PAL133_B04_0_Msk (0x1fUL << LCD_PAL133_B04_0_Pos) /*!< LCD PAL133: B04_0 Mask */\r
-#define LCD_PAL133_I0_Pos 15 /*!< LCD PAL133: I0 Position */\r
-#define LCD_PAL133_I0_Msk (0x01UL << LCD_PAL133_I0_Pos) /*!< LCD PAL133: I0 Mask */\r
-#define LCD_PAL133_R14_0_Pos 16 /*!< LCD PAL133: R14_0 Position */\r
-#define LCD_PAL133_R14_0_Msk (0x1fUL << LCD_PAL133_R14_0_Pos) /*!< LCD PAL133: R14_0 Mask */\r
-#define LCD_PAL133_G14_0_Pos 21 /*!< LCD PAL133: G14_0 Position */\r
-#define LCD_PAL133_G14_0_Msk (0x1fUL << LCD_PAL133_G14_0_Pos) /*!< LCD PAL133: G14_0 Mask */\r
-#define LCD_PAL133_B14_0_Pos 26 /*!< LCD PAL133: B14_0 Position */\r
-#define LCD_PAL133_B14_0_Msk (0x1fUL << LCD_PAL133_B14_0_Pos) /*!< LCD PAL133: B14_0 Mask */\r
-#define LCD_PAL133_I1_Pos 31 /*!< LCD PAL133: I1 Position */\r
-#define LCD_PAL133_I1_Msk (0x01UL << LCD_PAL133_I1_Pos) /*!< LCD PAL133: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL134 -------------------------------------------\r
-#define LCD_PAL134_R04_0_Pos 0 /*!< LCD PAL134: R04_0 Position */\r
-#define LCD_PAL134_R04_0_Msk (0x1fUL << LCD_PAL134_R04_0_Pos) /*!< LCD PAL134: R04_0 Mask */\r
-#define LCD_PAL134_G04_0_Pos 5 /*!< LCD PAL134: G04_0 Position */\r
-#define LCD_PAL134_G04_0_Msk (0x1fUL << LCD_PAL134_G04_0_Pos) /*!< LCD PAL134: G04_0 Mask */\r
-#define LCD_PAL134_B04_0_Pos 10 /*!< LCD PAL134: B04_0 Position */\r
-#define LCD_PAL134_B04_0_Msk (0x1fUL << LCD_PAL134_B04_0_Pos) /*!< LCD PAL134: B04_0 Mask */\r
-#define LCD_PAL134_I0_Pos 15 /*!< LCD PAL134: I0 Position */\r
-#define LCD_PAL134_I0_Msk (0x01UL << LCD_PAL134_I0_Pos) /*!< LCD PAL134: I0 Mask */\r
-#define LCD_PAL134_R14_0_Pos 16 /*!< LCD PAL134: R14_0 Position */\r
-#define LCD_PAL134_R14_0_Msk (0x1fUL << LCD_PAL134_R14_0_Pos) /*!< LCD PAL134: R14_0 Mask */\r
-#define LCD_PAL134_G14_0_Pos 21 /*!< LCD PAL134: G14_0 Position */\r
-#define LCD_PAL134_G14_0_Msk (0x1fUL << LCD_PAL134_G14_0_Pos) /*!< LCD PAL134: G14_0 Mask */\r
-#define LCD_PAL134_B14_0_Pos 26 /*!< LCD PAL134: B14_0 Position */\r
-#define LCD_PAL134_B14_0_Msk (0x1fUL << LCD_PAL134_B14_0_Pos) /*!< LCD PAL134: B14_0 Mask */\r
-#define LCD_PAL134_I1_Pos 31 /*!< LCD PAL134: I1 Position */\r
-#define LCD_PAL134_I1_Msk (0x01UL << LCD_PAL134_I1_Pos) /*!< LCD PAL134: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL135 -------------------------------------------\r
-#define LCD_PAL135_R04_0_Pos 0 /*!< LCD PAL135: R04_0 Position */\r
-#define LCD_PAL135_R04_0_Msk (0x1fUL << LCD_PAL135_R04_0_Pos) /*!< LCD PAL135: R04_0 Mask */\r
-#define LCD_PAL135_G04_0_Pos 5 /*!< LCD PAL135: G04_0 Position */\r
-#define LCD_PAL135_G04_0_Msk (0x1fUL << LCD_PAL135_G04_0_Pos) /*!< LCD PAL135: G04_0 Mask */\r
-#define LCD_PAL135_B04_0_Pos 10 /*!< LCD PAL135: B04_0 Position */\r
-#define LCD_PAL135_B04_0_Msk (0x1fUL << LCD_PAL135_B04_0_Pos) /*!< LCD PAL135: B04_0 Mask */\r
-#define LCD_PAL135_I0_Pos 15 /*!< LCD PAL135: I0 Position */\r
-#define LCD_PAL135_I0_Msk (0x01UL << LCD_PAL135_I0_Pos) /*!< LCD PAL135: I0 Mask */\r
-#define LCD_PAL135_R14_0_Pos 16 /*!< LCD PAL135: R14_0 Position */\r
-#define LCD_PAL135_R14_0_Msk (0x1fUL << LCD_PAL135_R14_0_Pos) /*!< LCD PAL135: R14_0 Mask */\r
-#define LCD_PAL135_G14_0_Pos 21 /*!< LCD PAL135: G14_0 Position */\r
-#define LCD_PAL135_G14_0_Msk (0x1fUL << LCD_PAL135_G14_0_Pos) /*!< LCD PAL135: G14_0 Mask */\r
-#define LCD_PAL135_B14_0_Pos 26 /*!< LCD PAL135: B14_0 Position */\r
-#define LCD_PAL135_B14_0_Msk (0x1fUL << LCD_PAL135_B14_0_Pos) /*!< LCD PAL135: B14_0 Mask */\r
-#define LCD_PAL135_I1_Pos 31 /*!< LCD PAL135: I1 Position */\r
-#define LCD_PAL135_I1_Msk (0x01UL << LCD_PAL135_I1_Pos) /*!< LCD PAL135: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL136 -------------------------------------------\r
-#define LCD_PAL136_R04_0_Pos 0 /*!< LCD PAL136: R04_0 Position */\r
-#define LCD_PAL136_R04_0_Msk (0x1fUL << LCD_PAL136_R04_0_Pos) /*!< LCD PAL136: R04_0 Mask */\r
-#define LCD_PAL136_G04_0_Pos 5 /*!< LCD PAL136: G04_0 Position */\r
-#define LCD_PAL136_G04_0_Msk (0x1fUL << LCD_PAL136_G04_0_Pos) /*!< LCD PAL136: G04_0 Mask */\r
-#define LCD_PAL136_B04_0_Pos 10 /*!< LCD PAL136: B04_0 Position */\r
-#define LCD_PAL136_B04_0_Msk (0x1fUL << LCD_PAL136_B04_0_Pos) /*!< LCD PAL136: B04_0 Mask */\r
-#define LCD_PAL136_I0_Pos 15 /*!< LCD PAL136: I0 Position */\r
-#define LCD_PAL136_I0_Msk (0x01UL << LCD_PAL136_I0_Pos) /*!< LCD PAL136: I0 Mask */\r
-#define LCD_PAL136_R14_0_Pos 16 /*!< LCD PAL136: R14_0 Position */\r
-#define LCD_PAL136_R14_0_Msk (0x1fUL << LCD_PAL136_R14_0_Pos) /*!< LCD PAL136: R14_0 Mask */\r
-#define LCD_PAL136_G14_0_Pos 21 /*!< LCD PAL136: G14_0 Position */\r
-#define LCD_PAL136_G14_0_Msk (0x1fUL << LCD_PAL136_G14_0_Pos) /*!< LCD PAL136: G14_0 Mask */\r
-#define LCD_PAL136_B14_0_Pos 26 /*!< LCD PAL136: B14_0 Position */\r
-#define LCD_PAL136_B14_0_Msk (0x1fUL << LCD_PAL136_B14_0_Pos) /*!< LCD PAL136: B14_0 Mask */\r
-#define LCD_PAL136_I1_Pos 31 /*!< LCD PAL136: I1 Position */\r
-#define LCD_PAL136_I1_Msk (0x01UL << LCD_PAL136_I1_Pos) /*!< LCD PAL136: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL137 -------------------------------------------\r
-#define LCD_PAL137_R04_0_Pos 0 /*!< LCD PAL137: R04_0 Position */\r
-#define LCD_PAL137_R04_0_Msk (0x1fUL << LCD_PAL137_R04_0_Pos) /*!< LCD PAL137: R04_0 Mask */\r
-#define LCD_PAL137_G04_0_Pos 5 /*!< LCD PAL137: G04_0 Position */\r
-#define LCD_PAL137_G04_0_Msk (0x1fUL << LCD_PAL137_G04_0_Pos) /*!< LCD PAL137: G04_0 Mask */\r
-#define LCD_PAL137_B04_0_Pos 10 /*!< LCD PAL137: B04_0 Position */\r
-#define LCD_PAL137_B04_0_Msk (0x1fUL << LCD_PAL137_B04_0_Pos) /*!< LCD PAL137: B04_0 Mask */\r
-#define LCD_PAL137_I0_Pos 15 /*!< LCD PAL137: I0 Position */\r
-#define LCD_PAL137_I0_Msk (0x01UL << LCD_PAL137_I0_Pos) /*!< LCD PAL137: I0 Mask */\r
-#define LCD_PAL137_R14_0_Pos 16 /*!< LCD PAL137: R14_0 Position */\r
-#define LCD_PAL137_R14_0_Msk (0x1fUL << LCD_PAL137_R14_0_Pos) /*!< LCD PAL137: R14_0 Mask */\r
-#define LCD_PAL137_G14_0_Pos 21 /*!< LCD PAL137: G14_0 Position */\r
-#define LCD_PAL137_G14_0_Msk (0x1fUL << LCD_PAL137_G14_0_Pos) /*!< LCD PAL137: G14_0 Mask */\r
-#define LCD_PAL137_B14_0_Pos 26 /*!< LCD PAL137: B14_0 Position */\r
-#define LCD_PAL137_B14_0_Msk (0x1fUL << LCD_PAL137_B14_0_Pos) /*!< LCD PAL137: B14_0 Mask */\r
-#define LCD_PAL137_I1_Pos 31 /*!< LCD PAL137: I1 Position */\r
-#define LCD_PAL137_I1_Msk (0x01UL << LCD_PAL137_I1_Pos) /*!< LCD PAL137: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL138 -------------------------------------------\r
-#define LCD_PAL138_R04_0_Pos 0 /*!< LCD PAL138: R04_0 Position */\r
-#define LCD_PAL138_R04_0_Msk (0x1fUL << LCD_PAL138_R04_0_Pos) /*!< LCD PAL138: R04_0 Mask */\r
-#define LCD_PAL138_G04_0_Pos 5 /*!< LCD PAL138: G04_0 Position */\r
-#define LCD_PAL138_G04_0_Msk (0x1fUL << LCD_PAL138_G04_0_Pos) /*!< LCD PAL138: G04_0 Mask */\r
-#define LCD_PAL138_B04_0_Pos 10 /*!< LCD PAL138: B04_0 Position */\r
-#define LCD_PAL138_B04_0_Msk (0x1fUL << LCD_PAL138_B04_0_Pos) /*!< LCD PAL138: B04_0 Mask */\r
-#define LCD_PAL138_I0_Pos 15 /*!< LCD PAL138: I0 Position */\r
-#define LCD_PAL138_I0_Msk (0x01UL << LCD_PAL138_I0_Pos) /*!< LCD PAL138: I0 Mask */\r
-#define LCD_PAL138_R14_0_Pos 16 /*!< LCD PAL138: R14_0 Position */\r
-#define LCD_PAL138_R14_0_Msk (0x1fUL << LCD_PAL138_R14_0_Pos) /*!< LCD PAL138: R14_0 Mask */\r
-#define LCD_PAL138_G14_0_Pos 21 /*!< LCD PAL138: G14_0 Position */\r
-#define LCD_PAL138_G14_0_Msk (0x1fUL << LCD_PAL138_G14_0_Pos) /*!< LCD PAL138: G14_0 Mask */\r
-#define LCD_PAL138_B14_0_Pos 26 /*!< LCD PAL138: B14_0 Position */\r
-#define LCD_PAL138_B14_0_Msk (0x1fUL << LCD_PAL138_B14_0_Pos) /*!< LCD PAL138: B14_0 Mask */\r
-#define LCD_PAL138_I1_Pos 31 /*!< LCD PAL138: I1 Position */\r
-#define LCD_PAL138_I1_Msk (0x01UL << LCD_PAL138_I1_Pos) /*!< LCD PAL138: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL139 -------------------------------------------\r
-#define LCD_PAL139_R04_0_Pos 0 /*!< LCD PAL139: R04_0 Position */\r
-#define LCD_PAL139_R04_0_Msk (0x1fUL << LCD_PAL139_R04_0_Pos) /*!< LCD PAL139: R04_0 Mask */\r
-#define LCD_PAL139_G04_0_Pos 5 /*!< LCD PAL139: G04_0 Position */\r
-#define LCD_PAL139_G04_0_Msk (0x1fUL << LCD_PAL139_G04_0_Pos) /*!< LCD PAL139: G04_0 Mask */\r
-#define LCD_PAL139_B04_0_Pos 10 /*!< LCD PAL139: B04_0 Position */\r
-#define LCD_PAL139_B04_0_Msk (0x1fUL << LCD_PAL139_B04_0_Pos) /*!< LCD PAL139: B04_0 Mask */\r
-#define LCD_PAL139_I0_Pos 15 /*!< LCD PAL139: I0 Position */\r
-#define LCD_PAL139_I0_Msk (0x01UL << LCD_PAL139_I0_Pos) /*!< LCD PAL139: I0 Mask */\r
-#define LCD_PAL139_R14_0_Pos 16 /*!< LCD PAL139: R14_0 Position */\r
-#define LCD_PAL139_R14_0_Msk (0x1fUL << LCD_PAL139_R14_0_Pos) /*!< LCD PAL139: R14_0 Mask */\r
-#define LCD_PAL139_G14_0_Pos 21 /*!< LCD PAL139: G14_0 Position */\r
-#define LCD_PAL139_G14_0_Msk (0x1fUL << LCD_PAL139_G14_0_Pos) /*!< LCD PAL139: G14_0 Mask */\r
-#define LCD_PAL139_B14_0_Pos 26 /*!< LCD PAL139: B14_0 Position */\r
-#define LCD_PAL139_B14_0_Msk (0x1fUL << LCD_PAL139_B14_0_Pos) /*!< LCD PAL139: B14_0 Mask */\r
-#define LCD_PAL139_I1_Pos 31 /*!< LCD PAL139: I1 Position */\r
-#define LCD_PAL139_I1_Msk (0x01UL << LCD_PAL139_I1_Pos) /*!< LCD PAL139: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL140 -------------------------------------------\r
-#define LCD_PAL140_R04_0_Pos 0 /*!< LCD PAL140: R04_0 Position */\r
-#define LCD_PAL140_R04_0_Msk (0x1fUL << LCD_PAL140_R04_0_Pos) /*!< LCD PAL140: R04_0 Mask */\r
-#define LCD_PAL140_G04_0_Pos 5 /*!< LCD PAL140: G04_0 Position */\r
-#define LCD_PAL140_G04_0_Msk (0x1fUL << LCD_PAL140_G04_0_Pos) /*!< LCD PAL140: G04_0 Mask */\r
-#define LCD_PAL140_B04_0_Pos 10 /*!< LCD PAL140: B04_0 Position */\r
-#define LCD_PAL140_B04_0_Msk (0x1fUL << LCD_PAL140_B04_0_Pos) /*!< LCD PAL140: B04_0 Mask */\r
-#define LCD_PAL140_I0_Pos 15 /*!< LCD PAL140: I0 Position */\r
-#define LCD_PAL140_I0_Msk (0x01UL << LCD_PAL140_I0_Pos) /*!< LCD PAL140: I0 Mask */\r
-#define LCD_PAL140_R14_0_Pos 16 /*!< LCD PAL140: R14_0 Position */\r
-#define LCD_PAL140_R14_0_Msk (0x1fUL << LCD_PAL140_R14_0_Pos) /*!< LCD PAL140: R14_0 Mask */\r
-#define LCD_PAL140_G14_0_Pos 21 /*!< LCD PAL140: G14_0 Position */\r
-#define LCD_PAL140_G14_0_Msk (0x1fUL << LCD_PAL140_G14_0_Pos) /*!< LCD PAL140: G14_0 Mask */\r
-#define LCD_PAL140_B14_0_Pos 26 /*!< LCD PAL140: B14_0 Position */\r
-#define LCD_PAL140_B14_0_Msk (0x1fUL << LCD_PAL140_B14_0_Pos) /*!< LCD PAL140: B14_0 Mask */\r
-#define LCD_PAL140_I1_Pos 31 /*!< LCD PAL140: I1 Position */\r
-#define LCD_PAL140_I1_Msk (0x01UL << LCD_PAL140_I1_Pos) /*!< LCD PAL140: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL141 -------------------------------------------\r
-#define LCD_PAL141_R04_0_Pos 0 /*!< LCD PAL141: R04_0 Position */\r
-#define LCD_PAL141_R04_0_Msk (0x1fUL << LCD_PAL141_R04_0_Pos) /*!< LCD PAL141: R04_0 Mask */\r
-#define LCD_PAL141_G04_0_Pos 5 /*!< LCD PAL141: G04_0 Position */\r
-#define LCD_PAL141_G04_0_Msk (0x1fUL << LCD_PAL141_G04_0_Pos) /*!< LCD PAL141: G04_0 Mask */\r
-#define LCD_PAL141_B04_0_Pos 10 /*!< LCD PAL141: B04_0 Position */\r
-#define LCD_PAL141_B04_0_Msk (0x1fUL << LCD_PAL141_B04_0_Pos) /*!< LCD PAL141: B04_0 Mask */\r
-#define LCD_PAL141_I0_Pos 15 /*!< LCD PAL141: I0 Position */\r
-#define LCD_PAL141_I0_Msk (0x01UL << LCD_PAL141_I0_Pos) /*!< LCD PAL141: I0 Mask */\r
-#define LCD_PAL141_R14_0_Pos 16 /*!< LCD PAL141: R14_0 Position */\r
-#define LCD_PAL141_R14_0_Msk (0x1fUL << LCD_PAL141_R14_0_Pos) /*!< LCD PAL141: R14_0 Mask */\r
-#define LCD_PAL141_G14_0_Pos 21 /*!< LCD PAL141: G14_0 Position */\r
-#define LCD_PAL141_G14_0_Msk (0x1fUL << LCD_PAL141_G14_0_Pos) /*!< LCD PAL141: G14_0 Mask */\r
-#define LCD_PAL141_B14_0_Pos 26 /*!< LCD PAL141: B14_0 Position */\r
-#define LCD_PAL141_B14_0_Msk (0x1fUL << LCD_PAL141_B14_0_Pos) /*!< LCD PAL141: B14_0 Mask */\r
-#define LCD_PAL141_I1_Pos 31 /*!< LCD PAL141: I1 Position */\r
-#define LCD_PAL141_I1_Msk (0x01UL << LCD_PAL141_I1_Pos) /*!< LCD PAL141: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL142 -------------------------------------------\r
-#define LCD_PAL142_R04_0_Pos 0 /*!< LCD PAL142: R04_0 Position */\r
-#define LCD_PAL142_R04_0_Msk (0x1fUL << LCD_PAL142_R04_0_Pos) /*!< LCD PAL142: R04_0 Mask */\r
-#define LCD_PAL142_G04_0_Pos 5 /*!< LCD PAL142: G04_0 Position */\r
-#define LCD_PAL142_G04_0_Msk (0x1fUL << LCD_PAL142_G04_0_Pos) /*!< LCD PAL142: G04_0 Mask */\r
-#define LCD_PAL142_B04_0_Pos 10 /*!< LCD PAL142: B04_0 Position */\r
-#define LCD_PAL142_B04_0_Msk (0x1fUL << LCD_PAL142_B04_0_Pos) /*!< LCD PAL142: B04_0 Mask */\r
-#define LCD_PAL142_I0_Pos 15 /*!< LCD PAL142: I0 Position */\r
-#define LCD_PAL142_I0_Msk (0x01UL << LCD_PAL142_I0_Pos) /*!< LCD PAL142: I0 Mask */\r
-#define LCD_PAL142_R14_0_Pos 16 /*!< LCD PAL142: R14_0 Position */\r
-#define LCD_PAL142_R14_0_Msk (0x1fUL << LCD_PAL142_R14_0_Pos) /*!< LCD PAL142: R14_0 Mask */\r
-#define LCD_PAL142_G14_0_Pos 21 /*!< LCD PAL142: G14_0 Position */\r
-#define LCD_PAL142_G14_0_Msk (0x1fUL << LCD_PAL142_G14_0_Pos) /*!< LCD PAL142: G14_0 Mask */\r
-#define LCD_PAL142_B14_0_Pos 26 /*!< LCD PAL142: B14_0 Position */\r
-#define LCD_PAL142_B14_0_Msk (0x1fUL << LCD_PAL142_B14_0_Pos) /*!< LCD PAL142: B14_0 Mask */\r
-#define LCD_PAL142_I1_Pos 31 /*!< LCD PAL142: I1 Position */\r
-#define LCD_PAL142_I1_Msk (0x01UL << LCD_PAL142_I1_Pos) /*!< LCD PAL142: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL143 -------------------------------------------\r
-#define LCD_PAL143_R04_0_Pos 0 /*!< LCD PAL143: R04_0 Position */\r
-#define LCD_PAL143_R04_0_Msk (0x1fUL << LCD_PAL143_R04_0_Pos) /*!< LCD PAL143: R04_0 Mask */\r
-#define LCD_PAL143_G04_0_Pos 5 /*!< LCD PAL143: G04_0 Position */\r
-#define LCD_PAL143_G04_0_Msk (0x1fUL << LCD_PAL143_G04_0_Pos) /*!< LCD PAL143: G04_0 Mask */\r
-#define LCD_PAL143_B04_0_Pos 10 /*!< LCD PAL143: B04_0 Position */\r
-#define LCD_PAL143_B04_0_Msk (0x1fUL << LCD_PAL143_B04_0_Pos) /*!< LCD PAL143: B04_0 Mask */\r
-#define LCD_PAL143_I0_Pos 15 /*!< LCD PAL143: I0 Position */\r
-#define LCD_PAL143_I0_Msk (0x01UL << LCD_PAL143_I0_Pos) /*!< LCD PAL143: I0 Mask */\r
-#define LCD_PAL143_R14_0_Pos 16 /*!< LCD PAL143: R14_0 Position */\r
-#define LCD_PAL143_R14_0_Msk (0x1fUL << LCD_PAL143_R14_0_Pos) /*!< LCD PAL143: R14_0 Mask */\r
-#define LCD_PAL143_G14_0_Pos 21 /*!< LCD PAL143: G14_0 Position */\r
-#define LCD_PAL143_G14_0_Msk (0x1fUL << LCD_PAL143_G14_0_Pos) /*!< LCD PAL143: G14_0 Mask */\r
-#define LCD_PAL143_B14_0_Pos 26 /*!< LCD PAL143: B14_0 Position */\r
-#define LCD_PAL143_B14_0_Msk (0x1fUL << LCD_PAL143_B14_0_Pos) /*!< LCD PAL143: B14_0 Mask */\r
-#define LCD_PAL143_I1_Pos 31 /*!< LCD PAL143: I1 Position */\r
-#define LCD_PAL143_I1_Msk (0x01UL << LCD_PAL143_I1_Pos) /*!< LCD PAL143: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL144 -------------------------------------------\r
-#define LCD_PAL144_R04_0_Pos 0 /*!< LCD PAL144: R04_0 Position */\r
-#define LCD_PAL144_R04_0_Msk (0x1fUL << LCD_PAL144_R04_0_Pos) /*!< LCD PAL144: R04_0 Mask */\r
-#define LCD_PAL144_G04_0_Pos 5 /*!< LCD PAL144: G04_0 Position */\r
-#define LCD_PAL144_G04_0_Msk (0x1fUL << LCD_PAL144_G04_0_Pos) /*!< LCD PAL144: G04_0 Mask */\r
-#define LCD_PAL144_B04_0_Pos 10 /*!< LCD PAL144: B04_0 Position */\r
-#define LCD_PAL144_B04_0_Msk (0x1fUL << LCD_PAL144_B04_0_Pos) /*!< LCD PAL144: B04_0 Mask */\r
-#define LCD_PAL144_I0_Pos 15 /*!< LCD PAL144: I0 Position */\r
-#define LCD_PAL144_I0_Msk (0x01UL << LCD_PAL144_I0_Pos) /*!< LCD PAL144: I0 Mask */\r
-#define LCD_PAL144_R14_0_Pos 16 /*!< LCD PAL144: R14_0 Position */\r
-#define LCD_PAL144_R14_0_Msk (0x1fUL << LCD_PAL144_R14_0_Pos) /*!< LCD PAL144: R14_0 Mask */\r
-#define LCD_PAL144_G14_0_Pos 21 /*!< LCD PAL144: G14_0 Position */\r
-#define LCD_PAL144_G14_0_Msk (0x1fUL << LCD_PAL144_G14_0_Pos) /*!< LCD PAL144: G14_0 Mask */\r
-#define LCD_PAL144_B14_0_Pos 26 /*!< LCD PAL144: B14_0 Position */\r
-#define LCD_PAL144_B14_0_Msk (0x1fUL << LCD_PAL144_B14_0_Pos) /*!< LCD PAL144: B14_0 Mask */\r
-#define LCD_PAL144_I1_Pos 31 /*!< LCD PAL144: I1 Position */\r
-#define LCD_PAL144_I1_Msk (0x01UL << LCD_PAL144_I1_Pos) /*!< LCD PAL144: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL145 -------------------------------------------\r
-#define LCD_PAL145_R04_0_Pos 0 /*!< LCD PAL145: R04_0 Position */\r
-#define LCD_PAL145_R04_0_Msk (0x1fUL << LCD_PAL145_R04_0_Pos) /*!< LCD PAL145: R04_0 Mask */\r
-#define LCD_PAL145_G04_0_Pos 5 /*!< LCD PAL145: G04_0 Position */\r
-#define LCD_PAL145_G04_0_Msk (0x1fUL << LCD_PAL145_G04_0_Pos) /*!< LCD PAL145: G04_0 Mask */\r
-#define LCD_PAL145_B04_0_Pos 10 /*!< LCD PAL145: B04_0 Position */\r
-#define LCD_PAL145_B04_0_Msk (0x1fUL << LCD_PAL145_B04_0_Pos) /*!< LCD PAL145: B04_0 Mask */\r
-#define LCD_PAL145_I0_Pos 15 /*!< LCD PAL145: I0 Position */\r
-#define LCD_PAL145_I0_Msk (0x01UL << LCD_PAL145_I0_Pos) /*!< LCD PAL145: I0 Mask */\r
-#define LCD_PAL145_R14_0_Pos 16 /*!< LCD PAL145: R14_0 Position */\r
-#define LCD_PAL145_R14_0_Msk (0x1fUL << LCD_PAL145_R14_0_Pos) /*!< LCD PAL145: R14_0 Mask */\r
-#define LCD_PAL145_G14_0_Pos 21 /*!< LCD PAL145: G14_0 Position */\r
-#define LCD_PAL145_G14_0_Msk (0x1fUL << LCD_PAL145_G14_0_Pos) /*!< LCD PAL145: G14_0 Mask */\r
-#define LCD_PAL145_B14_0_Pos 26 /*!< LCD PAL145: B14_0 Position */\r
-#define LCD_PAL145_B14_0_Msk (0x1fUL << LCD_PAL145_B14_0_Pos) /*!< LCD PAL145: B14_0 Mask */\r
-#define LCD_PAL145_I1_Pos 31 /*!< LCD PAL145: I1 Position */\r
-#define LCD_PAL145_I1_Msk (0x01UL << LCD_PAL145_I1_Pos) /*!< LCD PAL145: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL146 -------------------------------------------\r
-#define LCD_PAL146_R04_0_Pos 0 /*!< LCD PAL146: R04_0 Position */\r
-#define LCD_PAL146_R04_0_Msk (0x1fUL << LCD_PAL146_R04_0_Pos) /*!< LCD PAL146: R04_0 Mask */\r
-#define LCD_PAL146_G04_0_Pos 5 /*!< LCD PAL146: G04_0 Position */\r
-#define LCD_PAL146_G04_0_Msk (0x1fUL << LCD_PAL146_G04_0_Pos) /*!< LCD PAL146: G04_0 Mask */\r
-#define LCD_PAL146_B04_0_Pos 10 /*!< LCD PAL146: B04_0 Position */\r
-#define LCD_PAL146_B04_0_Msk (0x1fUL << LCD_PAL146_B04_0_Pos) /*!< LCD PAL146: B04_0 Mask */\r
-#define LCD_PAL146_I0_Pos 15 /*!< LCD PAL146: I0 Position */\r
-#define LCD_PAL146_I0_Msk (0x01UL << LCD_PAL146_I0_Pos) /*!< LCD PAL146: I0 Mask */\r
-#define LCD_PAL146_R14_0_Pos 16 /*!< LCD PAL146: R14_0 Position */\r
-#define LCD_PAL146_R14_0_Msk (0x1fUL << LCD_PAL146_R14_0_Pos) /*!< LCD PAL146: R14_0 Mask */\r
-#define LCD_PAL146_G14_0_Pos 21 /*!< LCD PAL146: G14_0 Position */\r
-#define LCD_PAL146_G14_0_Msk (0x1fUL << LCD_PAL146_G14_0_Pos) /*!< LCD PAL146: G14_0 Mask */\r
-#define LCD_PAL146_B14_0_Pos 26 /*!< LCD PAL146: B14_0 Position */\r
-#define LCD_PAL146_B14_0_Msk (0x1fUL << LCD_PAL146_B14_0_Pos) /*!< LCD PAL146: B14_0 Mask */\r
-#define LCD_PAL146_I1_Pos 31 /*!< LCD PAL146: I1 Position */\r
-#define LCD_PAL146_I1_Msk (0x01UL << LCD_PAL146_I1_Pos) /*!< LCD PAL146: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL147 -------------------------------------------\r
-#define LCD_PAL147_R04_0_Pos 0 /*!< LCD PAL147: R04_0 Position */\r
-#define LCD_PAL147_R04_0_Msk (0x1fUL << LCD_PAL147_R04_0_Pos) /*!< LCD PAL147: R04_0 Mask */\r
-#define LCD_PAL147_G04_0_Pos 5 /*!< LCD PAL147: G04_0 Position */\r
-#define LCD_PAL147_G04_0_Msk (0x1fUL << LCD_PAL147_G04_0_Pos) /*!< LCD PAL147: G04_0 Mask */\r
-#define LCD_PAL147_B04_0_Pos 10 /*!< LCD PAL147: B04_0 Position */\r
-#define LCD_PAL147_B04_0_Msk (0x1fUL << LCD_PAL147_B04_0_Pos) /*!< LCD PAL147: B04_0 Mask */\r
-#define LCD_PAL147_I0_Pos 15 /*!< LCD PAL147: I0 Position */\r
-#define LCD_PAL147_I0_Msk (0x01UL << LCD_PAL147_I0_Pos) /*!< LCD PAL147: I0 Mask */\r
-#define LCD_PAL147_R14_0_Pos 16 /*!< LCD PAL147: R14_0 Position */\r
-#define LCD_PAL147_R14_0_Msk (0x1fUL << LCD_PAL147_R14_0_Pos) /*!< LCD PAL147: R14_0 Mask */\r
-#define LCD_PAL147_G14_0_Pos 21 /*!< LCD PAL147: G14_0 Position */\r
-#define LCD_PAL147_G14_0_Msk (0x1fUL << LCD_PAL147_G14_0_Pos) /*!< LCD PAL147: G14_0 Mask */\r
-#define LCD_PAL147_B14_0_Pos 26 /*!< LCD PAL147: B14_0 Position */\r
-#define LCD_PAL147_B14_0_Msk (0x1fUL << LCD_PAL147_B14_0_Pos) /*!< LCD PAL147: B14_0 Mask */\r
-#define LCD_PAL147_I1_Pos 31 /*!< LCD PAL147: I1 Position */\r
-#define LCD_PAL147_I1_Msk (0x01UL << LCD_PAL147_I1_Pos) /*!< LCD PAL147: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL148 -------------------------------------------\r
-#define LCD_PAL148_R04_0_Pos 0 /*!< LCD PAL148: R04_0 Position */\r
-#define LCD_PAL148_R04_0_Msk (0x1fUL << LCD_PAL148_R04_0_Pos) /*!< LCD PAL148: R04_0 Mask */\r
-#define LCD_PAL148_G04_0_Pos 5 /*!< LCD PAL148: G04_0 Position */\r
-#define LCD_PAL148_G04_0_Msk (0x1fUL << LCD_PAL148_G04_0_Pos) /*!< LCD PAL148: G04_0 Mask */\r
-#define LCD_PAL148_B04_0_Pos 10 /*!< LCD PAL148: B04_0 Position */\r
-#define LCD_PAL148_B04_0_Msk (0x1fUL << LCD_PAL148_B04_0_Pos) /*!< LCD PAL148: B04_0 Mask */\r
-#define LCD_PAL148_I0_Pos 15 /*!< LCD PAL148: I0 Position */\r
-#define LCD_PAL148_I0_Msk (0x01UL << LCD_PAL148_I0_Pos) /*!< LCD PAL148: I0 Mask */\r
-#define LCD_PAL148_R14_0_Pos 16 /*!< LCD PAL148: R14_0 Position */\r
-#define LCD_PAL148_R14_0_Msk (0x1fUL << LCD_PAL148_R14_0_Pos) /*!< LCD PAL148: R14_0 Mask */\r
-#define LCD_PAL148_G14_0_Pos 21 /*!< LCD PAL148: G14_0 Position */\r
-#define LCD_PAL148_G14_0_Msk (0x1fUL << LCD_PAL148_G14_0_Pos) /*!< LCD PAL148: G14_0 Mask */\r
-#define LCD_PAL148_B14_0_Pos 26 /*!< LCD PAL148: B14_0 Position */\r
-#define LCD_PAL148_B14_0_Msk (0x1fUL << LCD_PAL148_B14_0_Pos) /*!< LCD PAL148: B14_0 Mask */\r
-#define LCD_PAL148_I1_Pos 31 /*!< LCD PAL148: I1 Position */\r
-#define LCD_PAL148_I1_Msk (0x01UL << LCD_PAL148_I1_Pos) /*!< LCD PAL148: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL149 -------------------------------------------\r
-#define LCD_PAL149_R04_0_Pos 0 /*!< LCD PAL149: R04_0 Position */\r
-#define LCD_PAL149_R04_0_Msk (0x1fUL << LCD_PAL149_R04_0_Pos) /*!< LCD PAL149: R04_0 Mask */\r
-#define LCD_PAL149_G04_0_Pos 5 /*!< LCD PAL149: G04_0 Position */\r
-#define LCD_PAL149_G04_0_Msk (0x1fUL << LCD_PAL149_G04_0_Pos) /*!< LCD PAL149: G04_0 Mask */\r
-#define LCD_PAL149_B04_0_Pos 10 /*!< LCD PAL149: B04_0 Position */\r
-#define LCD_PAL149_B04_0_Msk (0x1fUL << LCD_PAL149_B04_0_Pos) /*!< LCD PAL149: B04_0 Mask */\r
-#define LCD_PAL149_I0_Pos 15 /*!< LCD PAL149: I0 Position */\r
-#define LCD_PAL149_I0_Msk (0x01UL << LCD_PAL149_I0_Pos) /*!< LCD PAL149: I0 Mask */\r
-#define LCD_PAL149_R14_0_Pos 16 /*!< LCD PAL149: R14_0 Position */\r
-#define LCD_PAL149_R14_0_Msk (0x1fUL << LCD_PAL149_R14_0_Pos) /*!< LCD PAL149: R14_0 Mask */\r
-#define LCD_PAL149_G14_0_Pos 21 /*!< LCD PAL149: G14_0 Position */\r
-#define LCD_PAL149_G14_0_Msk (0x1fUL << LCD_PAL149_G14_0_Pos) /*!< LCD PAL149: G14_0 Mask */\r
-#define LCD_PAL149_B14_0_Pos 26 /*!< LCD PAL149: B14_0 Position */\r
-#define LCD_PAL149_B14_0_Msk (0x1fUL << LCD_PAL149_B14_0_Pos) /*!< LCD PAL149: B14_0 Mask */\r
-#define LCD_PAL149_I1_Pos 31 /*!< LCD PAL149: I1 Position */\r
-#define LCD_PAL149_I1_Msk (0x01UL << LCD_PAL149_I1_Pos) /*!< LCD PAL149: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL150 -------------------------------------------\r
-#define LCD_PAL150_R04_0_Pos 0 /*!< LCD PAL150: R04_0 Position */\r
-#define LCD_PAL150_R04_0_Msk (0x1fUL << LCD_PAL150_R04_0_Pos) /*!< LCD PAL150: R04_0 Mask */\r
-#define LCD_PAL150_G04_0_Pos 5 /*!< LCD PAL150: G04_0 Position */\r
-#define LCD_PAL150_G04_0_Msk (0x1fUL << LCD_PAL150_G04_0_Pos) /*!< LCD PAL150: G04_0 Mask */\r
-#define LCD_PAL150_B04_0_Pos 10 /*!< LCD PAL150: B04_0 Position */\r
-#define LCD_PAL150_B04_0_Msk (0x1fUL << LCD_PAL150_B04_0_Pos) /*!< LCD PAL150: B04_0 Mask */\r
-#define LCD_PAL150_I0_Pos 15 /*!< LCD PAL150: I0 Position */\r
-#define LCD_PAL150_I0_Msk (0x01UL << LCD_PAL150_I0_Pos) /*!< LCD PAL150: I0 Mask */\r
-#define LCD_PAL150_R14_0_Pos 16 /*!< LCD PAL150: R14_0 Position */\r
-#define LCD_PAL150_R14_0_Msk (0x1fUL << LCD_PAL150_R14_0_Pos) /*!< LCD PAL150: R14_0 Mask */\r
-#define LCD_PAL150_G14_0_Pos 21 /*!< LCD PAL150: G14_0 Position */\r
-#define LCD_PAL150_G14_0_Msk (0x1fUL << LCD_PAL150_G14_0_Pos) /*!< LCD PAL150: G14_0 Mask */\r
-#define LCD_PAL150_B14_0_Pos 26 /*!< LCD PAL150: B14_0 Position */\r
-#define LCD_PAL150_B14_0_Msk (0x1fUL << LCD_PAL150_B14_0_Pos) /*!< LCD PAL150: B14_0 Mask */\r
-#define LCD_PAL150_I1_Pos 31 /*!< LCD PAL150: I1 Position */\r
-#define LCD_PAL150_I1_Msk (0x01UL << LCD_PAL150_I1_Pos) /*!< LCD PAL150: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL151 -------------------------------------------\r
-#define LCD_PAL151_R04_0_Pos 0 /*!< LCD PAL151: R04_0 Position */\r
-#define LCD_PAL151_R04_0_Msk (0x1fUL << LCD_PAL151_R04_0_Pos) /*!< LCD PAL151: R04_0 Mask */\r
-#define LCD_PAL151_G04_0_Pos 5 /*!< LCD PAL151: G04_0 Position */\r
-#define LCD_PAL151_G04_0_Msk (0x1fUL << LCD_PAL151_G04_0_Pos) /*!< LCD PAL151: G04_0 Mask */\r
-#define LCD_PAL151_B04_0_Pos 10 /*!< LCD PAL151: B04_0 Position */\r
-#define LCD_PAL151_B04_0_Msk (0x1fUL << LCD_PAL151_B04_0_Pos) /*!< LCD PAL151: B04_0 Mask */\r
-#define LCD_PAL151_I0_Pos 15 /*!< LCD PAL151: I0 Position */\r
-#define LCD_PAL151_I0_Msk (0x01UL << LCD_PAL151_I0_Pos) /*!< LCD PAL151: I0 Mask */\r
-#define LCD_PAL151_R14_0_Pos 16 /*!< LCD PAL151: R14_0 Position */\r
-#define LCD_PAL151_R14_0_Msk (0x1fUL << LCD_PAL151_R14_0_Pos) /*!< LCD PAL151: R14_0 Mask */\r
-#define LCD_PAL151_G14_0_Pos 21 /*!< LCD PAL151: G14_0 Position */\r
-#define LCD_PAL151_G14_0_Msk (0x1fUL << LCD_PAL151_G14_0_Pos) /*!< LCD PAL151: G14_0 Mask */\r
-#define LCD_PAL151_B14_0_Pos 26 /*!< LCD PAL151: B14_0 Position */\r
-#define LCD_PAL151_B14_0_Msk (0x1fUL << LCD_PAL151_B14_0_Pos) /*!< LCD PAL151: B14_0 Mask */\r
-#define LCD_PAL151_I1_Pos 31 /*!< LCD PAL151: I1 Position */\r
-#define LCD_PAL151_I1_Msk (0x01UL << LCD_PAL151_I1_Pos) /*!< LCD PAL151: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL152 -------------------------------------------\r
-#define LCD_PAL152_R04_0_Pos 0 /*!< LCD PAL152: R04_0 Position */\r
-#define LCD_PAL152_R04_0_Msk (0x1fUL << LCD_PAL152_R04_0_Pos) /*!< LCD PAL152: R04_0 Mask */\r
-#define LCD_PAL152_G04_0_Pos 5 /*!< LCD PAL152: G04_0 Position */\r
-#define LCD_PAL152_G04_0_Msk (0x1fUL << LCD_PAL152_G04_0_Pos) /*!< LCD PAL152: G04_0 Mask */\r
-#define LCD_PAL152_B04_0_Pos 10 /*!< LCD PAL152: B04_0 Position */\r
-#define LCD_PAL152_B04_0_Msk (0x1fUL << LCD_PAL152_B04_0_Pos) /*!< LCD PAL152: B04_0 Mask */\r
-#define LCD_PAL152_I0_Pos 15 /*!< LCD PAL152: I0 Position */\r
-#define LCD_PAL152_I0_Msk (0x01UL << LCD_PAL152_I0_Pos) /*!< LCD PAL152: I0 Mask */\r
-#define LCD_PAL152_R14_0_Pos 16 /*!< LCD PAL152: R14_0 Position */\r
-#define LCD_PAL152_R14_0_Msk (0x1fUL << LCD_PAL152_R14_0_Pos) /*!< LCD PAL152: R14_0 Mask */\r
-#define LCD_PAL152_G14_0_Pos 21 /*!< LCD PAL152: G14_0 Position */\r
-#define LCD_PAL152_G14_0_Msk (0x1fUL << LCD_PAL152_G14_0_Pos) /*!< LCD PAL152: G14_0 Mask */\r
-#define LCD_PAL152_B14_0_Pos 26 /*!< LCD PAL152: B14_0 Position */\r
-#define LCD_PAL152_B14_0_Msk (0x1fUL << LCD_PAL152_B14_0_Pos) /*!< LCD PAL152: B14_0 Mask */\r
-#define LCD_PAL152_I1_Pos 31 /*!< LCD PAL152: I1 Position */\r
-#define LCD_PAL152_I1_Msk (0x01UL << LCD_PAL152_I1_Pos) /*!< LCD PAL152: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL153 -------------------------------------------\r
-#define LCD_PAL153_R04_0_Pos 0 /*!< LCD PAL153: R04_0 Position */\r
-#define LCD_PAL153_R04_0_Msk (0x1fUL << LCD_PAL153_R04_0_Pos) /*!< LCD PAL153: R04_0 Mask */\r
-#define LCD_PAL153_G04_0_Pos 5 /*!< LCD PAL153: G04_0 Position */\r
-#define LCD_PAL153_G04_0_Msk (0x1fUL << LCD_PAL153_G04_0_Pos) /*!< LCD PAL153: G04_0 Mask */\r
-#define LCD_PAL153_B04_0_Pos 10 /*!< LCD PAL153: B04_0 Position */\r
-#define LCD_PAL153_B04_0_Msk (0x1fUL << LCD_PAL153_B04_0_Pos) /*!< LCD PAL153: B04_0 Mask */\r
-#define LCD_PAL153_I0_Pos 15 /*!< LCD PAL153: I0 Position */\r
-#define LCD_PAL153_I0_Msk (0x01UL << LCD_PAL153_I0_Pos) /*!< LCD PAL153: I0 Mask */\r
-#define LCD_PAL153_R14_0_Pos 16 /*!< LCD PAL153: R14_0 Position */\r
-#define LCD_PAL153_R14_0_Msk (0x1fUL << LCD_PAL153_R14_0_Pos) /*!< LCD PAL153: R14_0 Mask */\r
-#define LCD_PAL153_G14_0_Pos 21 /*!< LCD PAL153: G14_0 Position */\r
-#define LCD_PAL153_G14_0_Msk (0x1fUL << LCD_PAL153_G14_0_Pos) /*!< LCD PAL153: G14_0 Mask */\r
-#define LCD_PAL153_B14_0_Pos 26 /*!< LCD PAL153: B14_0 Position */\r
-#define LCD_PAL153_B14_0_Msk (0x1fUL << LCD_PAL153_B14_0_Pos) /*!< LCD PAL153: B14_0 Mask */\r
-#define LCD_PAL153_I1_Pos 31 /*!< LCD PAL153: I1 Position */\r
-#define LCD_PAL153_I1_Msk (0x01UL << LCD_PAL153_I1_Pos) /*!< LCD PAL153: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL154 -------------------------------------------\r
-#define LCD_PAL154_R04_0_Pos 0 /*!< LCD PAL154: R04_0 Position */\r
-#define LCD_PAL154_R04_0_Msk (0x1fUL << LCD_PAL154_R04_0_Pos) /*!< LCD PAL154: R04_0 Mask */\r
-#define LCD_PAL154_G04_0_Pos 5 /*!< LCD PAL154: G04_0 Position */\r
-#define LCD_PAL154_G04_0_Msk (0x1fUL << LCD_PAL154_G04_0_Pos) /*!< LCD PAL154: G04_0 Mask */\r
-#define LCD_PAL154_B04_0_Pos 10 /*!< LCD PAL154: B04_0 Position */\r
-#define LCD_PAL154_B04_0_Msk (0x1fUL << LCD_PAL154_B04_0_Pos) /*!< LCD PAL154: B04_0 Mask */\r
-#define LCD_PAL154_I0_Pos 15 /*!< LCD PAL154: I0 Position */\r
-#define LCD_PAL154_I0_Msk (0x01UL << LCD_PAL154_I0_Pos) /*!< LCD PAL154: I0 Mask */\r
-#define LCD_PAL154_R14_0_Pos 16 /*!< LCD PAL154: R14_0 Position */\r
-#define LCD_PAL154_R14_0_Msk (0x1fUL << LCD_PAL154_R14_0_Pos) /*!< LCD PAL154: R14_0 Mask */\r
-#define LCD_PAL154_G14_0_Pos 21 /*!< LCD PAL154: G14_0 Position */\r
-#define LCD_PAL154_G14_0_Msk (0x1fUL << LCD_PAL154_G14_0_Pos) /*!< LCD PAL154: G14_0 Mask */\r
-#define LCD_PAL154_B14_0_Pos 26 /*!< LCD PAL154: B14_0 Position */\r
-#define LCD_PAL154_B14_0_Msk (0x1fUL << LCD_PAL154_B14_0_Pos) /*!< LCD PAL154: B14_0 Mask */\r
-#define LCD_PAL154_I1_Pos 31 /*!< LCD PAL154: I1 Position */\r
-#define LCD_PAL154_I1_Msk (0x01UL << LCD_PAL154_I1_Pos) /*!< LCD PAL154: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL155 -------------------------------------------\r
-#define LCD_PAL155_R04_0_Pos 0 /*!< LCD PAL155: R04_0 Position */\r
-#define LCD_PAL155_R04_0_Msk (0x1fUL << LCD_PAL155_R04_0_Pos) /*!< LCD PAL155: R04_0 Mask */\r
-#define LCD_PAL155_G04_0_Pos 5 /*!< LCD PAL155: G04_0 Position */\r
-#define LCD_PAL155_G04_0_Msk (0x1fUL << LCD_PAL155_G04_0_Pos) /*!< LCD PAL155: G04_0 Mask */\r
-#define LCD_PAL155_B04_0_Pos 10 /*!< LCD PAL155: B04_0 Position */\r
-#define LCD_PAL155_B04_0_Msk (0x1fUL << LCD_PAL155_B04_0_Pos) /*!< LCD PAL155: B04_0 Mask */\r
-#define LCD_PAL155_I0_Pos 15 /*!< LCD PAL155: I0 Position */\r
-#define LCD_PAL155_I0_Msk (0x01UL << LCD_PAL155_I0_Pos) /*!< LCD PAL155: I0 Mask */\r
-#define LCD_PAL155_R14_0_Pos 16 /*!< LCD PAL155: R14_0 Position */\r
-#define LCD_PAL155_R14_0_Msk (0x1fUL << LCD_PAL155_R14_0_Pos) /*!< LCD PAL155: R14_0 Mask */\r
-#define LCD_PAL155_G14_0_Pos 21 /*!< LCD PAL155: G14_0 Position */\r
-#define LCD_PAL155_G14_0_Msk (0x1fUL << LCD_PAL155_G14_0_Pos) /*!< LCD PAL155: G14_0 Mask */\r
-#define LCD_PAL155_B14_0_Pos 26 /*!< LCD PAL155: B14_0 Position */\r
-#define LCD_PAL155_B14_0_Msk (0x1fUL << LCD_PAL155_B14_0_Pos) /*!< LCD PAL155: B14_0 Mask */\r
-#define LCD_PAL155_I1_Pos 31 /*!< LCD PAL155: I1 Position */\r
-#define LCD_PAL155_I1_Msk (0x01UL << LCD_PAL155_I1_Pos) /*!< LCD PAL155: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL156 -------------------------------------------\r
-#define LCD_PAL156_R04_0_Pos 0 /*!< LCD PAL156: R04_0 Position */\r
-#define LCD_PAL156_R04_0_Msk (0x1fUL << LCD_PAL156_R04_0_Pos) /*!< LCD PAL156: R04_0 Mask */\r
-#define LCD_PAL156_G04_0_Pos 5 /*!< LCD PAL156: G04_0 Position */\r
-#define LCD_PAL156_G04_0_Msk (0x1fUL << LCD_PAL156_G04_0_Pos) /*!< LCD PAL156: G04_0 Mask */\r
-#define LCD_PAL156_B04_0_Pos 10 /*!< LCD PAL156: B04_0 Position */\r
-#define LCD_PAL156_B04_0_Msk (0x1fUL << LCD_PAL156_B04_0_Pos) /*!< LCD PAL156: B04_0 Mask */\r
-#define LCD_PAL156_I0_Pos 15 /*!< LCD PAL156: I0 Position */\r
-#define LCD_PAL156_I0_Msk (0x01UL << LCD_PAL156_I0_Pos) /*!< LCD PAL156: I0 Mask */\r
-#define LCD_PAL156_R14_0_Pos 16 /*!< LCD PAL156: R14_0 Position */\r
-#define LCD_PAL156_R14_0_Msk (0x1fUL << LCD_PAL156_R14_0_Pos) /*!< LCD PAL156: R14_0 Mask */\r
-#define LCD_PAL156_G14_0_Pos 21 /*!< LCD PAL156: G14_0 Position */\r
-#define LCD_PAL156_G14_0_Msk (0x1fUL << LCD_PAL156_G14_0_Pos) /*!< LCD PAL156: G14_0 Mask */\r
-#define LCD_PAL156_B14_0_Pos 26 /*!< LCD PAL156: B14_0 Position */\r
-#define LCD_PAL156_B14_0_Msk (0x1fUL << LCD_PAL156_B14_0_Pos) /*!< LCD PAL156: B14_0 Mask */\r
-#define LCD_PAL156_I1_Pos 31 /*!< LCD PAL156: I1 Position */\r
-#define LCD_PAL156_I1_Msk (0x01UL << LCD_PAL156_I1_Pos) /*!< LCD PAL156: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL157 -------------------------------------------\r
-#define LCD_PAL157_R04_0_Pos 0 /*!< LCD PAL157: R04_0 Position */\r
-#define LCD_PAL157_R04_0_Msk (0x1fUL << LCD_PAL157_R04_0_Pos) /*!< LCD PAL157: R04_0 Mask */\r
-#define LCD_PAL157_G04_0_Pos 5 /*!< LCD PAL157: G04_0 Position */\r
-#define LCD_PAL157_G04_0_Msk (0x1fUL << LCD_PAL157_G04_0_Pos) /*!< LCD PAL157: G04_0 Mask */\r
-#define LCD_PAL157_B04_0_Pos 10 /*!< LCD PAL157: B04_0 Position */\r
-#define LCD_PAL157_B04_0_Msk (0x1fUL << LCD_PAL157_B04_0_Pos) /*!< LCD PAL157: B04_0 Mask */\r
-#define LCD_PAL157_I0_Pos 15 /*!< LCD PAL157: I0 Position */\r
-#define LCD_PAL157_I0_Msk (0x01UL << LCD_PAL157_I0_Pos) /*!< LCD PAL157: I0 Mask */\r
-#define LCD_PAL157_R14_0_Pos 16 /*!< LCD PAL157: R14_0 Position */\r
-#define LCD_PAL157_R14_0_Msk (0x1fUL << LCD_PAL157_R14_0_Pos) /*!< LCD PAL157: R14_0 Mask */\r
-#define LCD_PAL157_G14_0_Pos 21 /*!< LCD PAL157: G14_0 Position */\r
-#define LCD_PAL157_G14_0_Msk (0x1fUL << LCD_PAL157_G14_0_Pos) /*!< LCD PAL157: G14_0 Mask */\r
-#define LCD_PAL157_B14_0_Pos 26 /*!< LCD PAL157: B14_0 Position */\r
-#define LCD_PAL157_B14_0_Msk (0x1fUL << LCD_PAL157_B14_0_Pos) /*!< LCD PAL157: B14_0 Mask */\r
-#define LCD_PAL157_I1_Pos 31 /*!< LCD PAL157: I1 Position */\r
-#define LCD_PAL157_I1_Msk (0x01UL << LCD_PAL157_I1_Pos) /*!< LCD PAL157: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL158 -------------------------------------------\r
-#define LCD_PAL158_R04_0_Pos 0 /*!< LCD PAL158: R04_0 Position */\r
-#define LCD_PAL158_R04_0_Msk (0x1fUL << LCD_PAL158_R04_0_Pos) /*!< LCD PAL158: R04_0 Mask */\r
-#define LCD_PAL158_G04_0_Pos 5 /*!< LCD PAL158: G04_0 Position */\r
-#define LCD_PAL158_G04_0_Msk (0x1fUL << LCD_PAL158_G04_0_Pos) /*!< LCD PAL158: G04_0 Mask */\r
-#define LCD_PAL158_B04_0_Pos 10 /*!< LCD PAL158: B04_0 Position */\r
-#define LCD_PAL158_B04_0_Msk (0x1fUL << LCD_PAL158_B04_0_Pos) /*!< LCD PAL158: B04_0 Mask */\r
-#define LCD_PAL158_I0_Pos 15 /*!< LCD PAL158: I0 Position */\r
-#define LCD_PAL158_I0_Msk (0x01UL << LCD_PAL158_I0_Pos) /*!< LCD PAL158: I0 Mask */\r
-#define LCD_PAL158_R14_0_Pos 16 /*!< LCD PAL158: R14_0 Position */\r
-#define LCD_PAL158_R14_0_Msk (0x1fUL << LCD_PAL158_R14_0_Pos) /*!< LCD PAL158: R14_0 Mask */\r
-#define LCD_PAL158_G14_0_Pos 21 /*!< LCD PAL158: G14_0 Position */\r
-#define LCD_PAL158_G14_0_Msk (0x1fUL << LCD_PAL158_G14_0_Pos) /*!< LCD PAL158: G14_0 Mask */\r
-#define LCD_PAL158_B14_0_Pos 26 /*!< LCD PAL158: B14_0 Position */\r
-#define LCD_PAL158_B14_0_Msk (0x1fUL << LCD_PAL158_B14_0_Pos) /*!< LCD PAL158: B14_0 Mask */\r
-#define LCD_PAL158_I1_Pos 31 /*!< LCD PAL158: I1 Position */\r
-#define LCD_PAL158_I1_Msk (0x01UL << LCD_PAL158_I1_Pos) /*!< LCD PAL158: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL159 -------------------------------------------\r
-#define LCD_PAL159_R04_0_Pos 0 /*!< LCD PAL159: R04_0 Position */\r
-#define LCD_PAL159_R04_0_Msk (0x1fUL << LCD_PAL159_R04_0_Pos) /*!< LCD PAL159: R04_0 Mask */\r
-#define LCD_PAL159_G04_0_Pos 5 /*!< LCD PAL159: G04_0 Position */\r
-#define LCD_PAL159_G04_0_Msk (0x1fUL << LCD_PAL159_G04_0_Pos) /*!< LCD PAL159: G04_0 Mask */\r
-#define LCD_PAL159_B04_0_Pos 10 /*!< LCD PAL159: B04_0 Position */\r
-#define LCD_PAL159_B04_0_Msk (0x1fUL << LCD_PAL159_B04_0_Pos) /*!< LCD PAL159: B04_0 Mask */\r
-#define LCD_PAL159_I0_Pos 15 /*!< LCD PAL159: I0 Position */\r
-#define LCD_PAL159_I0_Msk (0x01UL << LCD_PAL159_I0_Pos) /*!< LCD PAL159: I0 Mask */\r
-#define LCD_PAL159_R14_0_Pos 16 /*!< LCD PAL159: R14_0 Position */\r
-#define LCD_PAL159_R14_0_Msk (0x1fUL << LCD_PAL159_R14_0_Pos) /*!< LCD PAL159: R14_0 Mask */\r
-#define LCD_PAL159_G14_0_Pos 21 /*!< LCD PAL159: G14_0 Position */\r
-#define LCD_PAL159_G14_0_Msk (0x1fUL << LCD_PAL159_G14_0_Pos) /*!< LCD PAL159: G14_0 Mask */\r
-#define LCD_PAL159_B14_0_Pos 26 /*!< LCD PAL159: B14_0 Position */\r
-#define LCD_PAL159_B14_0_Msk (0x1fUL << LCD_PAL159_B14_0_Pos) /*!< LCD PAL159: B14_0 Mask */\r
-#define LCD_PAL159_I1_Pos 31 /*!< LCD PAL159: I1 Position */\r
-#define LCD_PAL159_I1_Msk (0x01UL << LCD_PAL159_I1_Pos) /*!< LCD PAL159: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL160 -------------------------------------------\r
-#define LCD_PAL160_R04_0_Pos 0 /*!< LCD PAL160: R04_0 Position */\r
-#define LCD_PAL160_R04_0_Msk (0x1fUL << LCD_PAL160_R04_0_Pos) /*!< LCD PAL160: R04_0 Mask */\r
-#define LCD_PAL160_G04_0_Pos 5 /*!< LCD PAL160: G04_0 Position */\r
-#define LCD_PAL160_G04_0_Msk (0x1fUL << LCD_PAL160_G04_0_Pos) /*!< LCD PAL160: G04_0 Mask */\r
-#define LCD_PAL160_B04_0_Pos 10 /*!< LCD PAL160: B04_0 Position */\r
-#define LCD_PAL160_B04_0_Msk (0x1fUL << LCD_PAL160_B04_0_Pos) /*!< LCD PAL160: B04_0 Mask */\r
-#define LCD_PAL160_I0_Pos 15 /*!< LCD PAL160: I0 Position */\r
-#define LCD_PAL160_I0_Msk (0x01UL << LCD_PAL160_I0_Pos) /*!< LCD PAL160: I0 Mask */\r
-#define LCD_PAL160_R14_0_Pos 16 /*!< LCD PAL160: R14_0 Position */\r
-#define LCD_PAL160_R14_0_Msk (0x1fUL << LCD_PAL160_R14_0_Pos) /*!< LCD PAL160: R14_0 Mask */\r
-#define LCD_PAL160_G14_0_Pos 21 /*!< LCD PAL160: G14_0 Position */\r
-#define LCD_PAL160_G14_0_Msk (0x1fUL << LCD_PAL160_G14_0_Pos) /*!< LCD PAL160: G14_0 Mask */\r
-#define LCD_PAL160_B14_0_Pos 26 /*!< LCD PAL160: B14_0 Position */\r
-#define LCD_PAL160_B14_0_Msk (0x1fUL << LCD_PAL160_B14_0_Pos) /*!< LCD PAL160: B14_0 Mask */\r
-#define LCD_PAL160_I1_Pos 31 /*!< LCD PAL160: I1 Position */\r
-#define LCD_PAL160_I1_Msk (0x01UL << LCD_PAL160_I1_Pos) /*!< LCD PAL160: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL161 -------------------------------------------\r
-#define LCD_PAL161_R04_0_Pos 0 /*!< LCD PAL161: R04_0 Position */\r
-#define LCD_PAL161_R04_0_Msk (0x1fUL << LCD_PAL161_R04_0_Pos) /*!< LCD PAL161: R04_0 Mask */\r
-#define LCD_PAL161_G04_0_Pos 5 /*!< LCD PAL161: G04_0 Position */\r
-#define LCD_PAL161_G04_0_Msk (0x1fUL << LCD_PAL161_G04_0_Pos) /*!< LCD PAL161: G04_0 Mask */\r
-#define LCD_PAL161_B04_0_Pos 10 /*!< LCD PAL161: B04_0 Position */\r
-#define LCD_PAL161_B04_0_Msk (0x1fUL << LCD_PAL161_B04_0_Pos) /*!< LCD PAL161: B04_0 Mask */\r
-#define LCD_PAL161_I0_Pos 15 /*!< LCD PAL161: I0 Position */\r
-#define LCD_PAL161_I0_Msk (0x01UL << LCD_PAL161_I0_Pos) /*!< LCD PAL161: I0 Mask */\r
-#define LCD_PAL161_R14_0_Pos 16 /*!< LCD PAL161: R14_0 Position */\r
-#define LCD_PAL161_R14_0_Msk (0x1fUL << LCD_PAL161_R14_0_Pos) /*!< LCD PAL161: R14_0 Mask */\r
-#define LCD_PAL161_G14_0_Pos 21 /*!< LCD PAL161: G14_0 Position */\r
-#define LCD_PAL161_G14_0_Msk (0x1fUL << LCD_PAL161_G14_0_Pos) /*!< LCD PAL161: G14_0 Mask */\r
-#define LCD_PAL161_B14_0_Pos 26 /*!< LCD PAL161: B14_0 Position */\r
-#define LCD_PAL161_B14_0_Msk (0x1fUL << LCD_PAL161_B14_0_Pos) /*!< LCD PAL161: B14_0 Mask */\r
-#define LCD_PAL161_I1_Pos 31 /*!< LCD PAL161: I1 Position */\r
-#define LCD_PAL161_I1_Msk (0x01UL << LCD_PAL161_I1_Pos) /*!< LCD PAL161: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL162 -------------------------------------------\r
-#define LCD_PAL162_R04_0_Pos 0 /*!< LCD PAL162: R04_0 Position */\r
-#define LCD_PAL162_R04_0_Msk (0x1fUL << LCD_PAL162_R04_0_Pos) /*!< LCD PAL162: R04_0 Mask */\r
-#define LCD_PAL162_G04_0_Pos 5 /*!< LCD PAL162: G04_0 Position */\r
-#define LCD_PAL162_G04_0_Msk (0x1fUL << LCD_PAL162_G04_0_Pos) /*!< LCD PAL162: G04_0 Mask */\r
-#define LCD_PAL162_B04_0_Pos 10 /*!< LCD PAL162: B04_0 Position */\r
-#define LCD_PAL162_B04_0_Msk (0x1fUL << LCD_PAL162_B04_0_Pos) /*!< LCD PAL162: B04_0 Mask */\r
-#define LCD_PAL162_I0_Pos 15 /*!< LCD PAL162: I0 Position */\r
-#define LCD_PAL162_I0_Msk (0x01UL << LCD_PAL162_I0_Pos) /*!< LCD PAL162: I0 Mask */\r
-#define LCD_PAL162_R14_0_Pos 16 /*!< LCD PAL162: R14_0 Position */\r
-#define LCD_PAL162_R14_0_Msk (0x1fUL << LCD_PAL162_R14_0_Pos) /*!< LCD PAL162: R14_0 Mask */\r
-#define LCD_PAL162_G14_0_Pos 21 /*!< LCD PAL162: G14_0 Position */\r
-#define LCD_PAL162_G14_0_Msk (0x1fUL << LCD_PAL162_G14_0_Pos) /*!< LCD PAL162: G14_0 Mask */\r
-#define LCD_PAL162_B14_0_Pos 26 /*!< LCD PAL162: B14_0 Position */\r
-#define LCD_PAL162_B14_0_Msk (0x1fUL << LCD_PAL162_B14_0_Pos) /*!< LCD PAL162: B14_0 Mask */\r
-#define LCD_PAL162_I1_Pos 31 /*!< LCD PAL162: I1 Position */\r
-#define LCD_PAL162_I1_Msk (0x01UL << LCD_PAL162_I1_Pos) /*!< LCD PAL162: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL163 -------------------------------------------\r
-#define LCD_PAL163_R04_0_Pos 0 /*!< LCD PAL163: R04_0 Position */\r
-#define LCD_PAL163_R04_0_Msk (0x1fUL << LCD_PAL163_R04_0_Pos) /*!< LCD PAL163: R04_0 Mask */\r
-#define LCD_PAL163_G04_0_Pos 5 /*!< LCD PAL163: G04_0 Position */\r
-#define LCD_PAL163_G04_0_Msk (0x1fUL << LCD_PAL163_G04_0_Pos) /*!< LCD PAL163: G04_0 Mask */\r
-#define LCD_PAL163_B04_0_Pos 10 /*!< LCD PAL163: B04_0 Position */\r
-#define LCD_PAL163_B04_0_Msk (0x1fUL << LCD_PAL163_B04_0_Pos) /*!< LCD PAL163: B04_0 Mask */\r
-#define LCD_PAL163_I0_Pos 15 /*!< LCD PAL163: I0 Position */\r
-#define LCD_PAL163_I0_Msk (0x01UL << LCD_PAL163_I0_Pos) /*!< LCD PAL163: I0 Mask */\r
-#define LCD_PAL163_R14_0_Pos 16 /*!< LCD PAL163: R14_0 Position */\r
-#define LCD_PAL163_R14_0_Msk (0x1fUL << LCD_PAL163_R14_0_Pos) /*!< LCD PAL163: R14_0 Mask */\r
-#define LCD_PAL163_G14_0_Pos 21 /*!< LCD PAL163: G14_0 Position */\r
-#define LCD_PAL163_G14_0_Msk (0x1fUL << LCD_PAL163_G14_0_Pos) /*!< LCD PAL163: G14_0 Mask */\r
-#define LCD_PAL163_B14_0_Pos 26 /*!< LCD PAL163: B14_0 Position */\r
-#define LCD_PAL163_B14_0_Msk (0x1fUL << LCD_PAL163_B14_0_Pos) /*!< LCD PAL163: B14_0 Mask */\r
-#define LCD_PAL163_I1_Pos 31 /*!< LCD PAL163: I1 Position */\r
-#define LCD_PAL163_I1_Msk (0x01UL << LCD_PAL163_I1_Pos) /*!< LCD PAL163: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL164 -------------------------------------------\r
-#define LCD_PAL164_R04_0_Pos 0 /*!< LCD PAL164: R04_0 Position */\r
-#define LCD_PAL164_R04_0_Msk (0x1fUL << LCD_PAL164_R04_0_Pos) /*!< LCD PAL164: R04_0 Mask */\r
-#define LCD_PAL164_G04_0_Pos 5 /*!< LCD PAL164: G04_0 Position */\r
-#define LCD_PAL164_G04_0_Msk (0x1fUL << LCD_PAL164_G04_0_Pos) /*!< LCD PAL164: G04_0 Mask */\r
-#define LCD_PAL164_B04_0_Pos 10 /*!< LCD PAL164: B04_0 Position */\r
-#define LCD_PAL164_B04_0_Msk (0x1fUL << LCD_PAL164_B04_0_Pos) /*!< LCD PAL164: B04_0 Mask */\r
-#define LCD_PAL164_I0_Pos 15 /*!< LCD PAL164: I0 Position */\r
-#define LCD_PAL164_I0_Msk (0x01UL << LCD_PAL164_I0_Pos) /*!< LCD PAL164: I0 Mask */\r
-#define LCD_PAL164_R14_0_Pos 16 /*!< LCD PAL164: R14_0 Position */\r
-#define LCD_PAL164_R14_0_Msk (0x1fUL << LCD_PAL164_R14_0_Pos) /*!< LCD PAL164: R14_0 Mask */\r
-#define LCD_PAL164_G14_0_Pos 21 /*!< LCD PAL164: G14_0 Position */\r
-#define LCD_PAL164_G14_0_Msk (0x1fUL << LCD_PAL164_G14_0_Pos) /*!< LCD PAL164: G14_0 Mask */\r
-#define LCD_PAL164_B14_0_Pos 26 /*!< LCD PAL164: B14_0 Position */\r
-#define LCD_PAL164_B14_0_Msk (0x1fUL << LCD_PAL164_B14_0_Pos) /*!< LCD PAL164: B14_0 Mask */\r
-#define LCD_PAL164_I1_Pos 31 /*!< LCD PAL164: I1 Position */\r
-#define LCD_PAL164_I1_Msk (0x01UL << LCD_PAL164_I1_Pos) /*!< LCD PAL164: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL165 -------------------------------------------\r
-#define LCD_PAL165_R04_0_Pos 0 /*!< LCD PAL165: R04_0 Position */\r
-#define LCD_PAL165_R04_0_Msk (0x1fUL << LCD_PAL165_R04_0_Pos) /*!< LCD PAL165: R04_0 Mask */\r
-#define LCD_PAL165_G04_0_Pos 5 /*!< LCD PAL165: G04_0 Position */\r
-#define LCD_PAL165_G04_0_Msk (0x1fUL << LCD_PAL165_G04_0_Pos) /*!< LCD PAL165: G04_0 Mask */\r
-#define LCD_PAL165_B04_0_Pos 10 /*!< LCD PAL165: B04_0 Position */\r
-#define LCD_PAL165_B04_0_Msk (0x1fUL << LCD_PAL165_B04_0_Pos) /*!< LCD PAL165: B04_0 Mask */\r
-#define LCD_PAL165_I0_Pos 15 /*!< LCD PAL165: I0 Position */\r
-#define LCD_PAL165_I0_Msk (0x01UL << LCD_PAL165_I0_Pos) /*!< LCD PAL165: I0 Mask */\r
-#define LCD_PAL165_R14_0_Pos 16 /*!< LCD PAL165: R14_0 Position */\r
-#define LCD_PAL165_R14_0_Msk (0x1fUL << LCD_PAL165_R14_0_Pos) /*!< LCD PAL165: R14_0 Mask */\r
-#define LCD_PAL165_G14_0_Pos 21 /*!< LCD PAL165: G14_0 Position */\r
-#define LCD_PAL165_G14_0_Msk (0x1fUL << LCD_PAL165_G14_0_Pos) /*!< LCD PAL165: G14_0 Mask */\r
-#define LCD_PAL165_B14_0_Pos 26 /*!< LCD PAL165: B14_0 Position */\r
-#define LCD_PAL165_B14_0_Msk (0x1fUL << LCD_PAL165_B14_0_Pos) /*!< LCD PAL165: B14_0 Mask */\r
-#define LCD_PAL165_I1_Pos 31 /*!< LCD PAL165: I1 Position */\r
-#define LCD_PAL165_I1_Msk (0x01UL << LCD_PAL165_I1_Pos) /*!< LCD PAL165: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL166 -------------------------------------------\r
-#define LCD_PAL166_R04_0_Pos 0 /*!< LCD PAL166: R04_0 Position */\r
-#define LCD_PAL166_R04_0_Msk (0x1fUL << LCD_PAL166_R04_0_Pos) /*!< LCD PAL166: R04_0 Mask */\r
-#define LCD_PAL166_G04_0_Pos 5 /*!< LCD PAL166: G04_0 Position */\r
-#define LCD_PAL166_G04_0_Msk (0x1fUL << LCD_PAL166_G04_0_Pos) /*!< LCD PAL166: G04_0 Mask */\r
-#define LCD_PAL166_B04_0_Pos 10 /*!< LCD PAL166: B04_0 Position */\r
-#define LCD_PAL166_B04_0_Msk (0x1fUL << LCD_PAL166_B04_0_Pos) /*!< LCD PAL166: B04_0 Mask */\r
-#define LCD_PAL166_I0_Pos 15 /*!< LCD PAL166: I0 Position */\r
-#define LCD_PAL166_I0_Msk (0x01UL << LCD_PAL166_I0_Pos) /*!< LCD PAL166: I0 Mask */\r
-#define LCD_PAL166_R14_0_Pos 16 /*!< LCD PAL166: R14_0 Position */\r
-#define LCD_PAL166_R14_0_Msk (0x1fUL << LCD_PAL166_R14_0_Pos) /*!< LCD PAL166: R14_0 Mask */\r
-#define LCD_PAL166_G14_0_Pos 21 /*!< LCD PAL166: G14_0 Position */\r
-#define LCD_PAL166_G14_0_Msk (0x1fUL << LCD_PAL166_G14_0_Pos) /*!< LCD PAL166: G14_0 Mask */\r
-#define LCD_PAL166_B14_0_Pos 26 /*!< LCD PAL166: B14_0 Position */\r
-#define LCD_PAL166_B14_0_Msk (0x1fUL << LCD_PAL166_B14_0_Pos) /*!< LCD PAL166: B14_0 Mask */\r
-#define LCD_PAL166_I1_Pos 31 /*!< LCD PAL166: I1 Position */\r
-#define LCD_PAL166_I1_Msk (0x01UL << LCD_PAL166_I1_Pos) /*!< LCD PAL166: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL167 -------------------------------------------\r
-#define LCD_PAL167_R04_0_Pos 0 /*!< LCD PAL167: R04_0 Position */\r
-#define LCD_PAL167_R04_0_Msk (0x1fUL << LCD_PAL167_R04_0_Pos) /*!< LCD PAL167: R04_0 Mask */\r
-#define LCD_PAL167_G04_0_Pos 5 /*!< LCD PAL167: G04_0 Position */\r
-#define LCD_PAL167_G04_0_Msk (0x1fUL << LCD_PAL167_G04_0_Pos) /*!< LCD PAL167: G04_0 Mask */\r
-#define LCD_PAL167_B04_0_Pos 10 /*!< LCD PAL167: B04_0 Position */\r
-#define LCD_PAL167_B04_0_Msk (0x1fUL << LCD_PAL167_B04_0_Pos) /*!< LCD PAL167: B04_0 Mask */\r
-#define LCD_PAL167_I0_Pos 15 /*!< LCD PAL167: I0 Position */\r
-#define LCD_PAL167_I0_Msk (0x01UL << LCD_PAL167_I0_Pos) /*!< LCD PAL167: I0 Mask */\r
-#define LCD_PAL167_R14_0_Pos 16 /*!< LCD PAL167: R14_0 Position */\r
-#define LCD_PAL167_R14_0_Msk (0x1fUL << LCD_PAL167_R14_0_Pos) /*!< LCD PAL167: R14_0 Mask */\r
-#define LCD_PAL167_G14_0_Pos 21 /*!< LCD PAL167: G14_0 Position */\r
-#define LCD_PAL167_G14_0_Msk (0x1fUL << LCD_PAL167_G14_0_Pos) /*!< LCD PAL167: G14_0 Mask */\r
-#define LCD_PAL167_B14_0_Pos 26 /*!< LCD PAL167: B14_0 Position */\r
-#define LCD_PAL167_B14_0_Msk (0x1fUL << LCD_PAL167_B14_0_Pos) /*!< LCD PAL167: B14_0 Mask */\r
-#define LCD_PAL167_I1_Pos 31 /*!< LCD PAL167: I1 Position */\r
-#define LCD_PAL167_I1_Msk (0x01UL << LCD_PAL167_I1_Pos) /*!< LCD PAL167: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL168 -------------------------------------------\r
-#define LCD_PAL168_R04_0_Pos 0 /*!< LCD PAL168: R04_0 Position */\r
-#define LCD_PAL168_R04_0_Msk (0x1fUL << LCD_PAL168_R04_0_Pos) /*!< LCD PAL168: R04_0 Mask */\r
-#define LCD_PAL168_G04_0_Pos 5 /*!< LCD PAL168: G04_0 Position */\r
-#define LCD_PAL168_G04_0_Msk (0x1fUL << LCD_PAL168_G04_0_Pos) /*!< LCD PAL168: G04_0 Mask */\r
-#define LCD_PAL168_B04_0_Pos 10 /*!< LCD PAL168: B04_0 Position */\r
-#define LCD_PAL168_B04_0_Msk (0x1fUL << LCD_PAL168_B04_0_Pos) /*!< LCD PAL168: B04_0 Mask */\r
-#define LCD_PAL168_I0_Pos 15 /*!< LCD PAL168: I0 Position */\r
-#define LCD_PAL168_I0_Msk (0x01UL << LCD_PAL168_I0_Pos) /*!< LCD PAL168: I0 Mask */\r
-#define LCD_PAL168_R14_0_Pos 16 /*!< LCD PAL168: R14_0 Position */\r
-#define LCD_PAL168_R14_0_Msk (0x1fUL << LCD_PAL168_R14_0_Pos) /*!< LCD PAL168: R14_0 Mask */\r
-#define LCD_PAL168_G14_0_Pos 21 /*!< LCD PAL168: G14_0 Position */\r
-#define LCD_PAL168_G14_0_Msk (0x1fUL << LCD_PAL168_G14_0_Pos) /*!< LCD PAL168: G14_0 Mask */\r
-#define LCD_PAL168_B14_0_Pos 26 /*!< LCD PAL168: B14_0 Position */\r
-#define LCD_PAL168_B14_0_Msk (0x1fUL << LCD_PAL168_B14_0_Pos) /*!< LCD PAL168: B14_0 Mask */\r
-#define LCD_PAL168_I1_Pos 31 /*!< LCD PAL168: I1 Position */\r
-#define LCD_PAL168_I1_Msk (0x01UL << LCD_PAL168_I1_Pos) /*!< LCD PAL168: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL169 -------------------------------------------\r
-#define LCD_PAL169_R04_0_Pos 0 /*!< LCD PAL169: R04_0 Position */\r
-#define LCD_PAL169_R04_0_Msk (0x1fUL << LCD_PAL169_R04_0_Pos) /*!< LCD PAL169: R04_0 Mask */\r
-#define LCD_PAL169_G04_0_Pos 5 /*!< LCD PAL169: G04_0 Position */\r
-#define LCD_PAL169_G04_0_Msk (0x1fUL << LCD_PAL169_G04_0_Pos) /*!< LCD PAL169: G04_0 Mask */\r
-#define LCD_PAL169_B04_0_Pos 10 /*!< LCD PAL169: B04_0 Position */\r
-#define LCD_PAL169_B04_0_Msk (0x1fUL << LCD_PAL169_B04_0_Pos) /*!< LCD PAL169: B04_0 Mask */\r
-#define LCD_PAL169_I0_Pos 15 /*!< LCD PAL169: I0 Position */\r
-#define LCD_PAL169_I0_Msk (0x01UL << LCD_PAL169_I0_Pos) /*!< LCD PAL169: I0 Mask */\r
-#define LCD_PAL169_R14_0_Pos 16 /*!< LCD PAL169: R14_0 Position */\r
-#define LCD_PAL169_R14_0_Msk (0x1fUL << LCD_PAL169_R14_0_Pos) /*!< LCD PAL169: R14_0 Mask */\r
-#define LCD_PAL169_G14_0_Pos 21 /*!< LCD PAL169: G14_0 Position */\r
-#define LCD_PAL169_G14_0_Msk (0x1fUL << LCD_PAL169_G14_0_Pos) /*!< LCD PAL169: G14_0 Mask */\r
-#define LCD_PAL169_B14_0_Pos 26 /*!< LCD PAL169: B14_0 Position */\r
-#define LCD_PAL169_B14_0_Msk (0x1fUL << LCD_PAL169_B14_0_Pos) /*!< LCD PAL169: B14_0 Mask */\r
-#define LCD_PAL169_I1_Pos 31 /*!< LCD PAL169: I1 Position */\r
-#define LCD_PAL169_I1_Msk (0x01UL << LCD_PAL169_I1_Pos) /*!< LCD PAL169: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL170 -------------------------------------------\r
-#define LCD_PAL170_R04_0_Pos 0 /*!< LCD PAL170: R04_0 Position */\r
-#define LCD_PAL170_R04_0_Msk (0x1fUL << LCD_PAL170_R04_0_Pos) /*!< LCD PAL170: R04_0 Mask */\r
-#define LCD_PAL170_G04_0_Pos 5 /*!< LCD PAL170: G04_0 Position */\r
-#define LCD_PAL170_G04_0_Msk (0x1fUL << LCD_PAL170_G04_0_Pos) /*!< LCD PAL170: G04_0 Mask */\r
-#define LCD_PAL170_B04_0_Pos 10 /*!< LCD PAL170: B04_0 Position */\r
-#define LCD_PAL170_B04_0_Msk (0x1fUL << LCD_PAL170_B04_0_Pos) /*!< LCD PAL170: B04_0 Mask */\r
-#define LCD_PAL170_I0_Pos 15 /*!< LCD PAL170: I0 Position */\r
-#define LCD_PAL170_I0_Msk (0x01UL << LCD_PAL170_I0_Pos) /*!< LCD PAL170: I0 Mask */\r
-#define LCD_PAL170_R14_0_Pos 16 /*!< LCD PAL170: R14_0 Position */\r
-#define LCD_PAL170_R14_0_Msk (0x1fUL << LCD_PAL170_R14_0_Pos) /*!< LCD PAL170: R14_0 Mask */\r
-#define LCD_PAL170_G14_0_Pos 21 /*!< LCD PAL170: G14_0 Position */\r
-#define LCD_PAL170_G14_0_Msk (0x1fUL << LCD_PAL170_G14_0_Pos) /*!< LCD PAL170: G14_0 Mask */\r
-#define LCD_PAL170_B14_0_Pos 26 /*!< LCD PAL170: B14_0 Position */\r
-#define LCD_PAL170_B14_0_Msk (0x1fUL << LCD_PAL170_B14_0_Pos) /*!< LCD PAL170: B14_0 Mask */\r
-#define LCD_PAL170_I1_Pos 31 /*!< LCD PAL170: I1 Position */\r
-#define LCD_PAL170_I1_Msk (0x01UL << LCD_PAL170_I1_Pos) /*!< LCD PAL170: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL171 -------------------------------------------\r
-#define LCD_PAL171_R04_0_Pos 0 /*!< LCD PAL171: R04_0 Position */\r
-#define LCD_PAL171_R04_0_Msk (0x1fUL << LCD_PAL171_R04_0_Pos) /*!< LCD PAL171: R04_0 Mask */\r
-#define LCD_PAL171_G04_0_Pos 5 /*!< LCD PAL171: G04_0 Position */\r
-#define LCD_PAL171_G04_0_Msk (0x1fUL << LCD_PAL171_G04_0_Pos) /*!< LCD PAL171: G04_0 Mask */\r
-#define LCD_PAL171_B04_0_Pos 10 /*!< LCD PAL171: B04_0 Position */\r
-#define LCD_PAL171_B04_0_Msk (0x1fUL << LCD_PAL171_B04_0_Pos) /*!< LCD PAL171: B04_0 Mask */\r
-#define LCD_PAL171_I0_Pos 15 /*!< LCD PAL171: I0 Position */\r
-#define LCD_PAL171_I0_Msk (0x01UL << LCD_PAL171_I0_Pos) /*!< LCD PAL171: I0 Mask */\r
-#define LCD_PAL171_R14_0_Pos 16 /*!< LCD PAL171: R14_0 Position */\r
-#define LCD_PAL171_R14_0_Msk (0x1fUL << LCD_PAL171_R14_0_Pos) /*!< LCD PAL171: R14_0 Mask */\r
-#define LCD_PAL171_G14_0_Pos 21 /*!< LCD PAL171: G14_0 Position */\r
-#define LCD_PAL171_G14_0_Msk (0x1fUL << LCD_PAL171_G14_0_Pos) /*!< LCD PAL171: G14_0 Mask */\r
-#define LCD_PAL171_B14_0_Pos 26 /*!< LCD PAL171: B14_0 Position */\r
-#define LCD_PAL171_B14_0_Msk (0x1fUL << LCD_PAL171_B14_0_Pos) /*!< LCD PAL171: B14_0 Mask */\r
-#define LCD_PAL171_I1_Pos 31 /*!< LCD PAL171: I1 Position */\r
-#define LCD_PAL171_I1_Msk (0x01UL << LCD_PAL171_I1_Pos) /*!< LCD PAL171: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL172 -------------------------------------------\r
-#define LCD_PAL172_R04_0_Pos 0 /*!< LCD PAL172: R04_0 Position */\r
-#define LCD_PAL172_R04_0_Msk (0x1fUL << LCD_PAL172_R04_0_Pos) /*!< LCD PAL172: R04_0 Mask */\r
-#define LCD_PAL172_G04_0_Pos 5 /*!< LCD PAL172: G04_0 Position */\r
-#define LCD_PAL172_G04_0_Msk (0x1fUL << LCD_PAL172_G04_0_Pos) /*!< LCD PAL172: G04_0 Mask */\r
-#define LCD_PAL172_B04_0_Pos 10 /*!< LCD PAL172: B04_0 Position */\r
-#define LCD_PAL172_B04_0_Msk (0x1fUL << LCD_PAL172_B04_0_Pos) /*!< LCD PAL172: B04_0 Mask */\r
-#define LCD_PAL172_I0_Pos 15 /*!< LCD PAL172: I0 Position */\r
-#define LCD_PAL172_I0_Msk (0x01UL << LCD_PAL172_I0_Pos) /*!< LCD PAL172: I0 Mask */\r
-#define LCD_PAL172_R14_0_Pos 16 /*!< LCD PAL172: R14_0 Position */\r
-#define LCD_PAL172_R14_0_Msk (0x1fUL << LCD_PAL172_R14_0_Pos) /*!< LCD PAL172: R14_0 Mask */\r
-#define LCD_PAL172_G14_0_Pos 21 /*!< LCD PAL172: G14_0 Position */\r
-#define LCD_PAL172_G14_0_Msk (0x1fUL << LCD_PAL172_G14_0_Pos) /*!< LCD PAL172: G14_0 Mask */\r
-#define LCD_PAL172_B14_0_Pos 26 /*!< LCD PAL172: B14_0 Position */\r
-#define LCD_PAL172_B14_0_Msk (0x1fUL << LCD_PAL172_B14_0_Pos) /*!< LCD PAL172: B14_0 Mask */\r
-#define LCD_PAL172_I1_Pos 31 /*!< LCD PAL172: I1 Position */\r
-#define LCD_PAL172_I1_Msk (0x01UL << LCD_PAL172_I1_Pos) /*!< LCD PAL172: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL173 -------------------------------------------\r
-#define LCD_PAL173_R04_0_Pos 0 /*!< LCD PAL173: R04_0 Position */\r
-#define LCD_PAL173_R04_0_Msk (0x1fUL << LCD_PAL173_R04_0_Pos) /*!< LCD PAL173: R04_0 Mask */\r
-#define LCD_PAL173_G04_0_Pos 5 /*!< LCD PAL173: G04_0 Position */\r
-#define LCD_PAL173_G04_0_Msk (0x1fUL << LCD_PAL173_G04_0_Pos) /*!< LCD PAL173: G04_0 Mask */\r
-#define LCD_PAL173_B04_0_Pos 10 /*!< LCD PAL173: B04_0 Position */\r
-#define LCD_PAL173_B04_0_Msk (0x1fUL << LCD_PAL173_B04_0_Pos) /*!< LCD PAL173: B04_0 Mask */\r
-#define LCD_PAL173_I0_Pos 15 /*!< LCD PAL173: I0 Position */\r
-#define LCD_PAL173_I0_Msk (0x01UL << LCD_PAL173_I0_Pos) /*!< LCD PAL173: I0 Mask */\r
-#define LCD_PAL173_R14_0_Pos 16 /*!< LCD PAL173: R14_0 Position */\r
-#define LCD_PAL173_R14_0_Msk (0x1fUL << LCD_PAL173_R14_0_Pos) /*!< LCD PAL173: R14_0 Mask */\r
-#define LCD_PAL173_G14_0_Pos 21 /*!< LCD PAL173: G14_0 Position */\r
-#define LCD_PAL173_G14_0_Msk (0x1fUL << LCD_PAL173_G14_0_Pos) /*!< LCD PAL173: G14_0 Mask */\r
-#define LCD_PAL173_B14_0_Pos 26 /*!< LCD PAL173: B14_0 Position */\r
-#define LCD_PAL173_B14_0_Msk (0x1fUL << LCD_PAL173_B14_0_Pos) /*!< LCD PAL173: B14_0 Mask */\r
-#define LCD_PAL173_I1_Pos 31 /*!< LCD PAL173: I1 Position */\r
-#define LCD_PAL173_I1_Msk (0x01UL << LCD_PAL173_I1_Pos) /*!< LCD PAL173: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL174 -------------------------------------------\r
-#define LCD_PAL174_R04_0_Pos 0 /*!< LCD PAL174: R04_0 Position */\r
-#define LCD_PAL174_R04_0_Msk (0x1fUL << LCD_PAL174_R04_0_Pos) /*!< LCD PAL174: R04_0 Mask */\r
-#define LCD_PAL174_G04_0_Pos 5 /*!< LCD PAL174: G04_0 Position */\r
-#define LCD_PAL174_G04_0_Msk (0x1fUL << LCD_PAL174_G04_0_Pos) /*!< LCD PAL174: G04_0 Mask */\r
-#define LCD_PAL174_B04_0_Pos 10 /*!< LCD PAL174: B04_0 Position */\r
-#define LCD_PAL174_B04_0_Msk (0x1fUL << LCD_PAL174_B04_0_Pos) /*!< LCD PAL174: B04_0 Mask */\r
-#define LCD_PAL174_I0_Pos 15 /*!< LCD PAL174: I0 Position */\r
-#define LCD_PAL174_I0_Msk (0x01UL << LCD_PAL174_I0_Pos) /*!< LCD PAL174: I0 Mask */\r
-#define LCD_PAL174_R14_0_Pos 16 /*!< LCD PAL174: R14_0 Position */\r
-#define LCD_PAL174_R14_0_Msk (0x1fUL << LCD_PAL174_R14_0_Pos) /*!< LCD PAL174: R14_0 Mask */\r
-#define LCD_PAL174_G14_0_Pos 21 /*!< LCD PAL174: G14_0 Position */\r
-#define LCD_PAL174_G14_0_Msk (0x1fUL << LCD_PAL174_G14_0_Pos) /*!< LCD PAL174: G14_0 Mask */\r
-#define LCD_PAL174_B14_0_Pos 26 /*!< LCD PAL174: B14_0 Position */\r
-#define LCD_PAL174_B14_0_Msk (0x1fUL << LCD_PAL174_B14_0_Pos) /*!< LCD PAL174: B14_0 Mask */\r
-#define LCD_PAL174_I1_Pos 31 /*!< LCD PAL174: I1 Position */\r
-#define LCD_PAL174_I1_Msk (0x01UL << LCD_PAL174_I1_Pos) /*!< LCD PAL174: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL175 -------------------------------------------\r
-#define LCD_PAL175_R04_0_Pos 0 /*!< LCD PAL175: R04_0 Position */\r
-#define LCD_PAL175_R04_0_Msk (0x1fUL << LCD_PAL175_R04_0_Pos) /*!< LCD PAL175: R04_0 Mask */\r
-#define LCD_PAL175_G04_0_Pos 5 /*!< LCD PAL175: G04_0 Position */\r
-#define LCD_PAL175_G04_0_Msk (0x1fUL << LCD_PAL175_G04_0_Pos) /*!< LCD PAL175: G04_0 Mask */\r
-#define LCD_PAL175_B04_0_Pos 10 /*!< LCD PAL175: B04_0 Position */\r
-#define LCD_PAL175_B04_0_Msk (0x1fUL << LCD_PAL175_B04_0_Pos) /*!< LCD PAL175: B04_0 Mask */\r
-#define LCD_PAL175_I0_Pos 15 /*!< LCD PAL175: I0 Position */\r
-#define LCD_PAL175_I0_Msk (0x01UL << LCD_PAL175_I0_Pos) /*!< LCD PAL175: I0 Mask */\r
-#define LCD_PAL175_R14_0_Pos 16 /*!< LCD PAL175: R14_0 Position */\r
-#define LCD_PAL175_R14_0_Msk (0x1fUL << LCD_PAL175_R14_0_Pos) /*!< LCD PAL175: R14_0 Mask */\r
-#define LCD_PAL175_G14_0_Pos 21 /*!< LCD PAL175: G14_0 Position */\r
-#define LCD_PAL175_G14_0_Msk (0x1fUL << LCD_PAL175_G14_0_Pos) /*!< LCD PAL175: G14_0 Mask */\r
-#define LCD_PAL175_B14_0_Pos 26 /*!< LCD PAL175: B14_0 Position */\r
-#define LCD_PAL175_B14_0_Msk (0x1fUL << LCD_PAL175_B14_0_Pos) /*!< LCD PAL175: B14_0 Mask */\r
-#define LCD_PAL175_I1_Pos 31 /*!< LCD PAL175: I1 Position */\r
-#define LCD_PAL175_I1_Msk (0x01UL << LCD_PAL175_I1_Pos) /*!< LCD PAL175: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL176 -------------------------------------------\r
-#define LCD_PAL176_R04_0_Pos 0 /*!< LCD PAL176: R04_0 Position */\r
-#define LCD_PAL176_R04_0_Msk (0x1fUL << LCD_PAL176_R04_0_Pos) /*!< LCD PAL176: R04_0 Mask */\r
-#define LCD_PAL176_G04_0_Pos 5 /*!< LCD PAL176: G04_0 Position */\r
-#define LCD_PAL176_G04_0_Msk (0x1fUL << LCD_PAL176_G04_0_Pos) /*!< LCD PAL176: G04_0 Mask */\r
-#define LCD_PAL176_B04_0_Pos 10 /*!< LCD PAL176: B04_0 Position */\r
-#define LCD_PAL176_B04_0_Msk (0x1fUL << LCD_PAL176_B04_0_Pos) /*!< LCD PAL176: B04_0 Mask */\r
-#define LCD_PAL176_I0_Pos 15 /*!< LCD PAL176: I0 Position */\r
-#define LCD_PAL176_I0_Msk (0x01UL << LCD_PAL176_I0_Pos) /*!< LCD PAL176: I0 Mask */\r
-#define LCD_PAL176_R14_0_Pos 16 /*!< LCD PAL176: R14_0 Position */\r
-#define LCD_PAL176_R14_0_Msk (0x1fUL << LCD_PAL176_R14_0_Pos) /*!< LCD PAL176: R14_0 Mask */\r
-#define LCD_PAL176_G14_0_Pos 21 /*!< LCD PAL176: G14_0 Position */\r
-#define LCD_PAL176_G14_0_Msk (0x1fUL << LCD_PAL176_G14_0_Pos) /*!< LCD PAL176: G14_0 Mask */\r
-#define LCD_PAL176_B14_0_Pos 26 /*!< LCD PAL176: B14_0 Position */\r
-#define LCD_PAL176_B14_0_Msk (0x1fUL << LCD_PAL176_B14_0_Pos) /*!< LCD PAL176: B14_0 Mask */\r
-#define LCD_PAL176_I1_Pos 31 /*!< LCD PAL176: I1 Position */\r
-#define LCD_PAL176_I1_Msk (0x01UL << LCD_PAL176_I1_Pos) /*!< LCD PAL176: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL177 -------------------------------------------\r
-#define LCD_PAL177_R04_0_Pos 0 /*!< LCD PAL177: R04_0 Position */\r
-#define LCD_PAL177_R04_0_Msk (0x1fUL << LCD_PAL177_R04_0_Pos) /*!< LCD PAL177: R04_0 Mask */\r
-#define LCD_PAL177_G04_0_Pos 5 /*!< LCD PAL177: G04_0 Position */\r
-#define LCD_PAL177_G04_0_Msk (0x1fUL << LCD_PAL177_G04_0_Pos) /*!< LCD PAL177: G04_0 Mask */\r
-#define LCD_PAL177_B04_0_Pos 10 /*!< LCD PAL177: B04_0 Position */\r
-#define LCD_PAL177_B04_0_Msk (0x1fUL << LCD_PAL177_B04_0_Pos) /*!< LCD PAL177: B04_0 Mask */\r
-#define LCD_PAL177_I0_Pos 15 /*!< LCD PAL177: I0 Position */\r
-#define LCD_PAL177_I0_Msk (0x01UL << LCD_PAL177_I0_Pos) /*!< LCD PAL177: I0 Mask */\r
-#define LCD_PAL177_R14_0_Pos 16 /*!< LCD PAL177: R14_0 Position */\r
-#define LCD_PAL177_R14_0_Msk (0x1fUL << LCD_PAL177_R14_0_Pos) /*!< LCD PAL177: R14_0 Mask */\r
-#define LCD_PAL177_G14_0_Pos 21 /*!< LCD PAL177: G14_0 Position */\r
-#define LCD_PAL177_G14_0_Msk (0x1fUL << LCD_PAL177_G14_0_Pos) /*!< LCD PAL177: G14_0 Mask */\r
-#define LCD_PAL177_B14_0_Pos 26 /*!< LCD PAL177: B14_0 Position */\r
-#define LCD_PAL177_B14_0_Msk (0x1fUL << LCD_PAL177_B14_0_Pos) /*!< LCD PAL177: B14_0 Mask */\r
-#define LCD_PAL177_I1_Pos 31 /*!< LCD PAL177: I1 Position */\r
-#define LCD_PAL177_I1_Msk (0x01UL << LCD_PAL177_I1_Pos) /*!< LCD PAL177: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL178 -------------------------------------------\r
-#define LCD_PAL178_R04_0_Pos 0 /*!< LCD PAL178: R04_0 Position */\r
-#define LCD_PAL178_R04_0_Msk (0x1fUL << LCD_PAL178_R04_0_Pos) /*!< LCD PAL178: R04_0 Mask */\r
-#define LCD_PAL178_G04_0_Pos 5 /*!< LCD PAL178: G04_0 Position */\r
-#define LCD_PAL178_G04_0_Msk (0x1fUL << LCD_PAL178_G04_0_Pos) /*!< LCD PAL178: G04_0 Mask */\r
-#define LCD_PAL178_B04_0_Pos 10 /*!< LCD PAL178: B04_0 Position */\r
-#define LCD_PAL178_B04_0_Msk (0x1fUL << LCD_PAL178_B04_0_Pos) /*!< LCD PAL178: B04_0 Mask */\r
-#define LCD_PAL178_I0_Pos 15 /*!< LCD PAL178: I0 Position */\r
-#define LCD_PAL178_I0_Msk (0x01UL << LCD_PAL178_I0_Pos) /*!< LCD PAL178: I0 Mask */\r
-#define LCD_PAL178_R14_0_Pos 16 /*!< LCD PAL178: R14_0 Position */\r
-#define LCD_PAL178_R14_0_Msk (0x1fUL << LCD_PAL178_R14_0_Pos) /*!< LCD PAL178: R14_0 Mask */\r
-#define LCD_PAL178_G14_0_Pos 21 /*!< LCD PAL178: G14_0 Position */\r
-#define LCD_PAL178_G14_0_Msk (0x1fUL << LCD_PAL178_G14_0_Pos) /*!< LCD PAL178: G14_0 Mask */\r
-#define LCD_PAL178_B14_0_Pos 26 /*!< LCD PAL178: B14_0 Position */\r
-#define LCD_PAL178_B14_0_Msk (0x1fUL << LCD_PAL178_B14_0_Pos) /*!< LCD PAL178: B14_0 Mask */\r
-#define LCD_PAL178_I1_Pos 31 /*!< LCD PAL178: I1 Position */\r
-#define LCD_PAL178_I1_Msk (0x01UL << LCD_PAL178_I1_Pos) /*!< LCD PAL178: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL179 -------------------------------------------\r
-#define LCD_PAL179_R04_0_Pos 0 /*!< LCD PAL179: R04_0 Position */\r
-#define LCD_PAL179_R04_0_Msk (0x1fUL << LCD_PAL179_R04_0_Pos) /*!< LCD PAL179: R04_0 Mask */\r
-#define LCD_PAL179_G04_0_Pos 5 /*!< LCD PAL179: G04_0 Position */\r
-#define LCD_PAL179_G04_0_Msk (0x1fUL << LCD_PAL179_G04_0_Pos) /*!< LCD PAL179: G04_0 Mask */\r
-#define LCD_PAL179_B04_0_Pos 10 /*!< LCD PAL179: B04_0 Position */\r
-#define LCD_PAL179_B04_0_Msk (0x1fUL << LCD_PAL179_B04_0_Pos) /*!< LCD PAL179: B04_0 Mask */\r
-#define LCD_PAL179_I0_Pos 15 /*!< LCD PAL179: I0 Position */\r
-#define LCD_PAL179_I0_Msk (0x01UL << LCD_PAL179_I0_Pos) /*!< LCD PAL179: I0 Mask */\r
-#define LCD_PAL179_R14_0_Pos 16 /*!< LCD PAL179: R14_0 Position */\r
-#define LCD_PAL179_R14_0_Msk (0x1fUL << LCD_PAL179_R14_0_Pos) /*!< LCD PAL179: R14_0 Mask */\r
-#define LCD_PAL179_G14_0_Pos 21 /*!< LCD PAL179: G14_0 Position */\r
-#define LCD_PAL179_G14_0_Msk (0x1fUL << LCD_PAL179_G14_0_Pos) /*!< LCD PAL179: G14_0 Mask */\r
-#define LCD_PAL179_B14_0_Pos 26 /*!< LCD PAL179: B14_0 Position */\r
-#define LCD_PAL179_B14_0_Msk (0x1fUL << LCD_PAL179_B14_0_Pos) /*!< LCD PAL179: B14_0 Mask */\r
-#define LCD_PAL179_I1_Pos 31 /*!< LCD PAL179: I1 Position */\r
-#define LCD_PAL179_I1_Msk (0x01UL << LCD_PAL179_I1_Pos) /*!< LCD PAL179: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL180 -------------------------------------------\r
-#define LCD_PAL180_R04_0_Pos 0 /*!< LCD PAL180: R04_0 Position */\r
-#define LCD_PAL180_R04_0_Msk (0x1fUL << LCD_PAL180_R04_0_Pos) /*!< LCD PAL180: R04_0 Mask */\r
-#define LCD_PAL180_G04_0_Pos 5 /*!< LCD PAL180: G04_0 Position */\r
-#define LCD_PAL180_G04_0_Msk (0x1fUL << LCD_PAL180_G04_0_Pos) /*!< LCD PAL180: G04_0 Mask */\r
-#define LCD_PAL180_B04_0_Pos 10 /*!< LCD PAL180: B04_0 Position */\r
-#define LCD_PAL180_B04_0_Msk (0x1fUL << LCD_PAL180_B04_0_Pos) /*!< LCD PAL180: B04_0 Mask */\r
-#define LCD_PAL180_I0_Pos 15 /*!< LCD PAL180: I0 Position */\r
-#define LCD_PAL180_I0_Msk (0x01UL << LCD_PAL180_I0_Pos) /*!< LCD PAL180: I0 Mask */\r
-#define LCD_PAL180_R14_0_Pos 16 /*!< LCD PAL180: R14_0 Position */\r
-#define LCD_PAL180_R14_0_Msk (0x1fUL << LCD_PAL180_R14_0_Pos) /*!< LCD PAL180: R14_0 Mask */\r
-#define LCD_PAL180_G14_0_Pos 21 /*!< LCD PAL180: G14_0 Position */\r
-#define LCD_PAL180_G14_0_Msk (0x1fUL << LCD_PAL180_G14_0_Pos) /*!< LCD PAL180: G14_0 Mask */\r
-#define LCD_PAL180_B14_0_Pos 26 /*!< LCD PAL180: B14_0 Position */\r
-#define LCD_PAL180_B14_0_Msk (0x1fUL << LCD_PAL180_B14_0_Pos) /*!< LCD PAL180: B14_0 Mask */\r
-#define LCD_PAL180_I1_Pos 31 /*!< LCD PAL180: I1 Position */\r
-#define LCD_PAL180_I1_Msk (0x01UL << LCD_PAL180_I1_Pos) /*!< LCD PAL180: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL181 -------------------------------------------\r
-#define LCD_PAL181_R04_0_Pos 0 /*!< LCD PAL181: R04_0 Position */\r
-#define LCD_PAL181_R04_0_Msk (0x1fUL << LCD_PAL181_R04_0_Pos) /*!< LCD PAL181: R04_0 Mask */\r
-#define LCD_PAL181_G04_0_Pos 5 /*!< LCD PAL181: G04_0 Position */\r
-#define LCD_PAL181_G04_0_Msk (0x1fUL << LCD_PAL181_G04_0_Pos) /*!< LCD PAL181: G04_0 Mask */\r
-#define LCD_PAL181_B04_0_Pos 10 /*!< LCD PAL181: B04_0 Position */\r
-#define LCD_PAL181_B04_0_Msk (0x1fUL << LCD_PAL181_B04_0_Pos) /*!< LCD PAL181: B04_0 Mask */\r
-#define LCD_PAL181_I0_Pos 15 /*!< LCD PAL181: I0 Position */\r
-#define LCD_PAL181_I0_Msk (0x01UL << LCD_PAL181_I0_Pos) /*!< LCD PAL181: I0 Mask */\r
-#define LCD_PAL181_R14_0_Pos 16 /*!< LCD PAL181: R14_0 Position */\r
-#define LCD_PAL181_R14_0_Msk (0x1fUL << LCD_PAL181_R14_0_Pos) /*!< LCD PAL181: R14_0 Mask */\r
-#define LCD_PAL181_G14_0_Pos 21 /*!< LCD PAL181: G14_0 Position */\r
-#define LCD_PAL181_G14_0_Msk (0x1fUL << LCD_PAL181_G14_0_Pos) /*!< LCD PAL181: G14_0 Mask */\r
-#define LCD_PAL181_B14_0_Pos 26 /*!< LCD PAL181: B14_0 Position */\r
-#define LCD_PAL181_B14_0_Msk (0x1fUL << LCD_PAL181_B14_0_Pos) /*!< LCD PAL181: B14_0 Mask */\r
-#define LCD_PAL181_I1_Pos 31 /*!< LCD PAL181: I1 Position */\r
-#define LCD_PAL181_I1_Msk (0x01UL << LCD_PAL181_I1_Pos) /*!< LCD PAL181: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL182 -------------------------------------------\r
-#define LCD_PAL182_R04_0_Pos 0 /*!< LCD PAL182: R04_0 Position */\r
-#define LCD_PAL182_R04_0_Msk (0x1fUL << LCD_PAL182_R04_0_Pos) /*!< LCD PAL182: R04_0 Mask */\r
-#define LCD_PAL182_G04_0_Pos 5 /*!< LCD PAL182: G04_0 Position */\r
-#define LCD_PAL182_G04_0_Msk (0x1fUL << LCD_PAL182_G04_0_Pos) /*!< LCD PAL182: G04_0 Mask */\r
-#define LCD_PAL182_B04_0_Pos 10 /*!< LCD PAL182: B04_0 Position */\r
-#define LCD_PAL182_B04_0_Msk (0x1fUL << LCD_PAL182_B04_0_Pos) /*!< LCD PAL182: B04_0 Mask */\r
-#define LCD_PAL182_I0_Pos 15 /*!< LCD PAL182: I0 Position */\r
-#define LCD_PAL182_I0_Msk (0x01UL << LCD_PAL182_I0_Pos) /*!< LCD PAL182: I0 Mask */\r
-#define LCD_PAL182_R14_0_Pos 16 /*!< LCD PAL182: R14_0 Position */\r
-#define LCD_PAL182_R14_0_Msk (0x1fUL << LCD_PAL182_R14_0_Pos) /*!< LCD PAL182: R14_0 Mask */\r
-#define LCD_PAL182_G14_0_Pos 21 /*!< LCD PAL182: G14_0 Position */\r
-#define LCD_PAL182_G14_0_Msk (0x1fUL << LCD_PAL182_G14_0_Pos) /*!< LCD PAL182: G14_0 Mask */\r
-#define LCD_PAL182_B14_0_Pos 26 /*!< LCD PAL182: B14_0 Position */\r
-#define LCD_PAL182_B14_0_Msk (0x1fUL << LCD_PAL182_B14_0_Pos) /*!< LCD PAL182: B14_0 Mask */\r
-#define LCD_PAL182_I1_Pos 31 /*!< LCD PAL182: I1 Position */\r
-#define LCD_PAL182_I1_Msk (0x01UL << LCD_PAL182_I1_Pos) /*!< LCD PAL182: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL183 -------------------------------------------\r
-#define LCD_PAL183_R04_0_Pos 0 /*!< LCD PAL183: R04_0 Position */\r
-#define LCD_PAL183_R04_0_Msk (0x1fUL << LCD_PAL183_R04_0_Pos) /*!< LCD PAL183: R04_0 Mask */\r
-#define LCD_PAL183_G04_0_Pos 5 /*!< LCD PAL183: G04_0 Position */\r
-#define LCD_PAL183_G04_0_Msk (0x1fUL << LCD_PAL183_G04_0_Pos) /*!< LCD PAL183: G04_0 Mask */\r
-#define LCD_PAL183_B04_0_Pos 10 /*!< LCD PAL183: B04_0 Position */\r
-#define LCD_PAL183_B04_0_Msk (0x1fUL << LCD_PAL183_B04_0_Pos) /*!< LCD PAL183: B04_0 Mask */\r
-#define LCD_PAL183_I0_Pos 15 /*!< LCD PAL183: I0 Position */\r
-#define LCD_PAL183_I0_Msk (0x01UL << LCD_PAL183_I0_Pos) /*!< LCD PAL183: I0 Mask */\r
-#define LCD_PAL183_R14_0_Pos 16 /*!< LCD PAL183: R14_0 Position */\r
-#define LCD_PAL183_R14_0_Msk (0x1fUL << LCD_PAL183_R14_0_Pos) /*!< LCD PAL183: R14_0 Mask */\r
-#define LCD_PAL183_G14_0_Pos 21 /*!< LCD PAL183: G14_0 Position */\r
-#define LCD_PAL183_G14_0_Msk (0x1fUL << LCD_PAL183_G14_0_Pos) /*!< LCD PAL183: G14_0 Mask */\r
-#define LCD_PAL183_B14_0_Pos 26 /*!< LCD PAL183: B14_0 Position */\r
-#define LCD_PAL183_B14_0_Msk (0x1fUL << LCD_PAL183_B14_0_Pos) /*!< LCD PAL183: B14_0 Mask */\r
-#define LCD_PAL183_I1_Pos 31 /*!< LCD PAL183: I1 Position */\r
-#define LCD_PAL183_I1_Msk (0x01UL << LCD_PAL183_I1_Pos) /*!< LCD PAL183: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL184 -------------------------------------------\r
-#define LCD_PAL184_R04_0_Pos 0 /*!< LCD PAL184: R04_0 Position */\r
-#define LCD_PAL184_R04_0_Msk (0x1fUL << LCD_PAL184_R04_0_Pos) /*!< LCD PAL184: R04_0 Mask */\r
-#define LCD_PAL184_G04_0_Pos 5 /*!< LCD PAL184: G04_0 Position */\r
-#define LCD_PAL184_G04_0_Msk (0x1fUL << LCD_PAL184_G04_0_Pos) /*!< LCD PAL184: G04_0 Mask */\r
-#define LCD_PAL184_B04_0_Pos 10 /*!< LCD PAL184: B04_0 Position */\r
-#define LCD_PAL184_B04_0_Msk (0x1fUL << LCD_PAL184_B04_0_Pos) /*!< LCD PAL184: B04_0 Mask */\r
-#define LCD_PAL184_I0_Pos 15 /*!< LCD PAL184: I0 Position */\r
-#define LCD_PAL184_I0_Msk (0x01UL << LCD_PAL184_I0_Pos) /*!< LCD PAL184: I0 Mask */\r
-#define LCD_PAL184_R14_0_Pos 16 /*!< LCD PAL184: R14_0 Position */\r
-#define LCD_PAL184_R14_0_Msk (0x1fUL << LCD_PAL184_R14_0_Pos) /*!< LCD PAL184: R14_0 Mask */\r
-#define LCD_PAL184_G14_0_Pos 21 /*!< LCD PAL184: G14_0 Position */\r
-#define LCD_PAL184_G14_0_Msk (0x1fUL << LCD_PAL184_G14_0_Pos) /*!< LCD PAL184: G14_0 Mask */\r
-#define LCD_PAL184_B14_0_Pos 26 /*!< LCD PAL184: B14_0 Position */\r
-#define LCD_PAL184_B14_0_Msk (0x1fUL << LCD_PAL184_B14_0_Pos) /*!< LCD PAL184: B14_0 Mask */\r
-#define LCD_PAL184_I1_Pos 31 /*!< LCD PAL184: I1 Position */\r
-#define LCD_PAL184_I1_Msk (0x01UL << LCD_PAL184_I1_Pos) /*!< LCD PAL184: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL185 -------------------------------------------\r
-#define LCD_PAL185_R04_0_Pos 0 /*!< LCD PAL185: R04_0 Position */\r
-#define LCD_PAL185_R04_0_Msk (0x1fUL << LCD_PAL185_R04_0_Pos) /*!< LCD PAL185: R04_0 Mask */\r
-#define LCD_PAL185_G04_0_Pos 5 /*!< LCD PAL185: G04_0 Position */\r
-#define LCD_PAL185_G04_0_Msk (0x1fUL << LCD_PAL185_G04_0_Pos) /*!< LCD PAL185: G04_0 Mask */\r
-#define LCD_PAL185_B04_0_Pos 10 /*!< LCD PAL185: B04_0 Position */\r
-#define LCD_PAL185_B04_0_Msk (0x1fUL << LCD_PAL185_B04_0_Pos) /*!< LCD PAL185: B04_0 Mask */\r
-#define LCD_PAL185_I0_Pos 15 /*!< LCD PAL185: I0 Position */\r
-#define LCD_PAL185_I0_Msk (0x01UL << LCD_PAL185_I0_Pos) /*!< LCD PAL185: I0 Mask */\r
-#define LCD_PAL185_R14_0_Pos 16 /*!< LCD PAL185: R14_0 Position */\r
-#define LCD_PAL185_R14_0_Msk (0x1fUL << LCD_PAL185_R14_0_Pos) /*!< LCD PAL185: R14_0 Mask */\r
-#define LCD_PAL185_G14_0_Pos 21 /*!< LCD PAL185: G14_0 Position */\r
-#define LCD_PAL185_G14_0_Msk (0x1fUL << LCD_PAL185_G14_0_Pos) /*!< LCD PAL185: G14_0 Mask */\r
-#define LCD_PAL185_B14_0_Pos 26 /*!< LCD PAL185: B14_0 Position */\r
-#define LCD_PAL185_B14_0_Msk (0x1fUL << LCD_PAL185_B14_0_Pos) /*!< LCD PAL185: B14_0 Mask */\r
-#define LCD_PAL185_I1_Pos 31 /*!< LCD PAL185: I1 Position */\r
-#define LCD_PAL185_I1_Msk (0x01UL << LCD_PAL185_I1_Pos) /*!< LCD PAL185: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL186 -------------------------------------------\r
-#define LCD_PAL186_R04_0_Pos 0 /*!< LCD PAL186: R04_0 Position */\r
-#define LCD_PAL186_R04_0_Msk (0x1fUL << LCD_PAL186_R04_0_Pos) /*!< LCD PAL186: R04_0 Mask */\r
-#define LCD_PAL186_G04_0_Pos 5 /*!< LCD PAL186: G04_0 Position */\r
-#define LCD_PAL186_G04_0_Msk (0x1fUL << LCD_PAL186_G04_0_Pos) /*!< LCD PAL186: G04_0 Mask */\r
-#define LCD_PAL186_B04_0_Pos 10 /*!< LCD PAL186: B04_0 Position */\r
-#define LCD_PAL186_B04_0_Msk (0x1fUL << LCD_PAL186_B04_0_Pos) /*!< LCD PAL186: B04_0 Mask */\r
-#define LCD_PAL186_I0_Pos 15 /*!< LCD PAL186: I0 Position */\r
-#define LCD_PAL186_I0_Msk (0x01UL << LCD_PAL186_I0_Pos) /*!< LCD PAL186: I0 Mask */\r
-#define LCD_PAL186_R14_0_Pos 16 /*!< LCD PAL186: R14_0 Position */\r
-#define LCD_PAL186_R14_0_Msk (0x1fUL << LCD_PAL186_R14_0_Pos) /*!< LCD PAL186: R14_0 Mask */\r
-#define LCD_PAL186_G14_0_Pos 21 /*!< LCD PAL186: G14_0 Position */\r
-#define LCD_PAL186_G14_0_Msk (0x1fUL << LCD_PAL186_G14_0_Pos) /*!< LCD PAL186: G14_0 Mask */\r
-#define LCD_PAL186_B14_0_Pos 26 /*!< LCD PAL186: B14_0 Position */\r
-#define LCD_PAL186_B14_0_Msk (0x1fUL << LCD_PAL186_B14_0_Pos) /*!< LCD PAL186: B14_0 Mask */\r
-#define LCD_PAL186_I1_Pos 31 /*!< LCD PAL186: I1 Position */\r
-#define LCD_PAL186_I1_Msk (0x01UL << LCD_PAL186_I1_Pos) /*!< LCD PAL186: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL187 -------------------------------------------\r
-#define LCD_PAL187_R04_0_Pos 0 /*!< LCD PAL187: R04_0 Position */\r
-#define LCD_PAL187_R04_0_Msk (0x1fUL << LCD_PAL187_R04_0_Pos) /*!< LCD PAL187: R04_0 Mask */\r
-#define LCD_PAL187_G04_0_Pos 5 /*!< LCD PAL187: G04_0 Position */\r
-#define LCD_PAL187_G04_0_Msk (0x1fUL << LCD_PAL187_G04_0_Pos) /*!< LCD PAL187: G04_0 Mask */\r
-#define LCD_PAL187_B04_0_Pos 10 /*!< LCD PAL187: B04_0 Position */\r
-#define LCD_PAL187_B04_0_Msk (0x1fUL << LCD_PAL187_B04_0_Pos) /*!< LCD PAL187: B04_0 Mask */\r
-#define LCD_PAL187_I0_Pos 15 /*!< LCD PAL187: I0 Position */\r
-#define LCD_PAL187_I0_Msk (0x01UL << LCD_PAL187_I0_Pos) /*!< LCD PAL187: I0 Mask */\r
-#define LCD_PAL187_R14_0_Pos 16 /*!< LCD PAL187: R14_0 Position */\r
-#define LCD_PAL187_R14_0_Msk (0x1fUL << LCD_PAL187_R14_0_Pos) /*!< LCD PAL187: R14_0 Mask */\r
-#define LCD_PAL187_G14_0_Pos 21 /*!< LCD PAL187: G14_0 Position */\r
-#define LCD_PAL187_G14_0_Msk (0x1fUL << LCD_PAL187_G14_0_Pos) /*!< LCD PAL187: G14_0 Mask */\r
-#define LCD_PAL187_B14_0_Pos 26 /*!< LCD PAL187: B14_0 Position */\r
-#define LCD_PAL187_B14_0_Msk (0x1fUL << LCD_PAL187_B14_0_Pos) /*!< LCD PAL187: B14_0 Mask */\r
-#define LCD_PAL187_I1_Pos 31 /*!< LCD PAL187: I1 Position */\r
-#define LCD_PAL187_I1_Msk (0x01UL << LCD_PAL187_I1_Pos) /*!< LCD PAL187: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL188 -------------------------------------------\r
-#define LCD_PAL188_R04_0_Pos 0 /*!< LCD PAL188: R04_0 Position */\r
-#define LCD_PAL188_R04_0_Msk (0x1fUL << LCD_PAL188_R04_0_Pos) /*!< LCD PAL188: R04_0 Mask */\r
-#define LCD_PAL188_G04_0_Pos 5 /*!< LCD PAL188: G04_0 Position */\r
-#define LCD_PAL188_G04_0_Msk (0x1fUL << LCD_PAL188_G04_0_Pos) /*!< LCD PAL188: G04_0 Mask */\r
-#define LCD_PAL188_B04_0_Pos 10 /*!< LCD PAL188: B04_0 Position */\r
-#define LCD_PAL188_B04_0_Msk (0x1fUL << LCD_PAL188_B04_0_Pos) /*!< LCD PAL188: B04_0 Mask */\r
-#define LCD_PAL188_I0_Pos 15 /*!< LCD PAL188: I0 Position */\r
-#define LCD_PAL188_I0_Msk (0x01UL << LCD_PAL188_I0_Pos) /*!< LCD PAL188: I0 Mask */\r
-#define LCD_PAL188_R14_0_Pos 16 /*!< LCD PAL188: R14_0 Position */\r
-#define LCD_PAL188_R14_0_Msk (0x1fUL << LCD_PAL188_R14_0_Pos) /*!< LCD PAL188: R14_0 Mask */\r
-#define LCD_PAL188_G14_0_Pos 21 /*!< LCD PAL188: G14_0 Position */\r
-#define LCD_PAL188_G14_0_Msk (0x1fUL << LCD_PAL188_G14_0_Pos) /*!< LCD PAL188: G14_0 Mask */\r
-#define LCD_PAL188_B14_0_Pos 26 /*!< LCD PAL188: B14_0 Position */\r
-#define LCD_PAL188_B14_0_Msk (0x1fUL << LCD_PAL188_B14_0_Pos) /*!< LCD PAL188: B14_0 Mask */\r
-#define LCD_PAL188_I1_Pos 31 /*!< LCD PAL188: I1 Position */\r
-#define LCD_PAL188_I1_Msk (0x01UL << LCD_PAL188_I1_Pos) /*!< LCD PAL188: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL189 -------------------------------------------\r
-#define LCD_PAL189_R04_0_Pos 0 /*!< LCD PAL189: R04_0 Position */\r
-#define LCD_PAL189_R04_0_Msk (0x1fUL << LCD_PAL189_R04_0_Pos) /*!< LCD PAL189: R04_0 Mask */\r
-#define LCD_PAL189_G04_0_Pos 5 /*!< LCD PAL189: G04_0 Position */\r
-#define LCD_PAL189_G04_0_Msk (0x1fUL << LCD_PAL189_G04_0_Pos) /*!< LCD PAL189: G04_0 Mask */\r
-#define LCD_PAL189_B04_0_Pos 10 /*!< LCD PAL189: B04_0 Position */\r
-#define LCD_PAL189_B04_0_Msk (0x1fUL << LCD_PAL189_B04_0_Pos) /*!< LCD PAL189: B04_0 Mask */\r
-#define LCD_PAL189_I0_Pos 15 /*!< LCD PAL189: I0 Position */\r
-#define LCD_PAL189_I0_Msk (0x01UL << LCD_PAL189_I0_Pos) /*!< LCD PAL189: I0 Mask */\r
-#define LCD_PAL189_R14_0_Pos 16 /*!< LCD PAL189: R14_0 Position */\r
-#define LCD_PAL189_R14_0_Msk (0x1fUL << LCD_PAL189_R14_0_Pos) /*!< LCD PAL189: R14_0 Mask */\r
-#define LCD_PAL189_G14_0_Pos 21 /*!< LCD PAL189: G14_0 Position */\r
-#define LCD_PAL189_G14_0_Msk (0x1fUL << LCD_PAL189_G14_0_Pos) /*!< LCD PAL189: G14_0 Mask */\r
-#define LCD_PAL189_B14_0_Pos 26 /*!< LCD PAL189: B14_0 Position */\r
-#define LCD_PAL189_B14_0_Msk (0x1fUL << LCD_PAL189_B14_0_Pos) /*!< LCD PAL189: B14_0 Mask */\r
-#define LCD_PAL189_I1_Pos 31 /*!< LCD PAL189: I1 Position */\r
-#define LCD_PAL189_I1_Msk (0x01UL << LCD_PAL189_I1_Pos) /*!< LCD PAL189: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL190 -------------------------------------------\r
-#define LCD_PAL190_R04_0_Pos 0 /*!< LCD PAL190: R04_0 Position */\r
-#define LCD_PAL190_R04_0_Msk (0x1fUL << LCD_PAL190_R04_0_Pos) /*!< LCD PAL190: R04_0 Mask */\r
-#define LCD_PAL190_G04_0_Pos 5 /*!< LCD PAL190: G04_0 Position */\r
-#define LCD_PAL190_G04_0_Msk (0x1fUL << LCD_PAL190_G04_0_Pos) /*!< LCD PAL190: G04_0 Mask */\r
-#define LCD_PAL190_B04_0_Pos 10 /*!< LCD PAL190: B04_0 Position */\r
-#define LCD_PAL190_B04_0_Msk (0x1fUL << LCD_PAL190_B04_0_Pos) /*!< LCD PAL190: B04_0 Mask */\r
-#define LCD_PAL190_I0_Pos 15 /*!< LCD PAL190: I0 Position */\r
-#define LCD_PAL190_I0_Msk (0x01UL << LCD_PAL190_I0_Pos) /*!< LCD PAL190: I0 Mask */\r
-#define LCD_PAL190_R14_0_Pos 16 /*!< LCD PAL190: R14_0 Position */\r
-#define LCD_PAL190_R14_0_Msk (0x1fUL << LCD_PAL190_R14_0_Pos) /*!< LCD PAL190: R14_0 Mask */\r
-#define LCD_PAL190_G14_0_Pos 21 /*!< LCD PAL190: G14_0 Position */\r
-#define LCD_PAL190_G14_0_Msk (0x1fUL << LCD_PAL190_G14_0_Pos) /*!< LCD PAL190: G14_0 Mask */\r
-#define LCD_PAL190_B14_0_Pos 26 /*!< LCD PAL190: B14_0 Position */\r
-#define LCD_PAL190_B14_0_Msk (0x1fUL << LCD_PAL190_B14_0_Pos) /*!< LCD PAL190: B14_0 Mask */\r
-#define LCD_PAL190_I1_Pos 31 /*!< LCD PAL190: I1 Position */\r
-#define LCD_PAL190_I1_Msk (0x01UL << LCD_PAL190_I1_Pos) /*!< LCD PAL190: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL191 -------------------------------------------\r
-#define LCD_PAL191_R04_0_Pos 0 /*!< LCD PAL191: R04_0 Position */\r
-#define LCD_PAL191_R04_0_Msk (0x1fUL << LCD_PAL191_R04_0_Pos) /*!< LCD PAL191: R04_0 Mask */\r
-#define LCD_PAL191_G04_0_Pos 5 /*!< LCD PAL191: G04_0 Position */\r
-#define LCD_PAL191_G04_0_Msk (0x1fUL << LCD_PAL191_G04_0_Pos) /*!< LCD PAL191: G04_0 Mask */\r
-#define LCD_PAL191_B04_0_Pos 10 /*!< LCD PAL191: B04_0 Position */\r
-#define LCD_PAL191_B04_0_Msk (0x1fUL << LCD_PAL191_B04_0_Pos) /*!< LCD PAL191: B04_0 Mask */\r
-#define LCD_PAL191_I0_Pos 15 /*!< LCD PAL191: I0 Position */\r
-#define LCD_PAL191_I0_Msk (0x01UL << LCD_PAL191_I0_Pos) /*!< LCD PAL191: I0 Mask */\r
-#define LCD_PAL191_R14_0_Pos 16 /*!< LCD PAL191: R14_0 Position */\r
-#define LCD_PAL191_R14_0_Msk (0x1fUL << LCD_PAL191_R14_0_Pos) /*!< LCD PAL191: R14_0 Mask */\r
-#define LCD_PAL191_G14_0_Pos 21 /*!< LCD PAL191: G14_0 Position */\r
-#define LCD_PAL191_G14_0_Msk (0x1fUL << LCD_PAL191_G14_0_Pos) /*!< LCD PAL191: G14_0 Mask */\r
-#define LCD_PAL191_B14_0_Pos 26 /*!< LCD PAL191: B14_0 Position */\r
-#define LCD_PAL191_B14_0_Msk (0x1fUL << LCD_PAL191_B14_0_Pos) /*!< LCD PAL191: B14_0 Mask */\r
-#define LCD_PAL191_I1_Pos 31 /*!< LCD PAL191: I1 Position */\r
-#define LCD_PAL191_I1_Msk (0x01UL << LCD_PAL191_I1_Pos) /*!< LCD PAL191: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL192 -------------------------------------------\r
-#define LCD_PAL192_R04_0_Pos 0 /*!< LCD PAL192: R04_0 Position */\r
-#define LCD_PAL192_R04_0_Msk (0x1fUL << LCD_PAL192_R04_0_Pos) /*!< LCD PAL192: R04_0 Mask */\r
-#define LCD_PAL192_G04_0_Pos 5 /*!< LCD PAL192: G04_0 Position */\r
-#define LCD_PAL192_G04_0_Msk (0x1fUL << LCD_PAL192_G04_0_Pos) /*!< LCD PAL192: G04_0 Mask */\r
-#define LCD_PAL192_B04_0_Pos 10 /*!< LCD PAL192: B04_0 Position */\r
-#define LCD_PAL192_B04_0_Msk (0x1fUL << LCD_PAL192_B04_0_Pos) /*!< LCD PAL192: B04_0 Mask */\r
-#define LCD_PAL192_I0_Pos 15 /*!< LCD PAL192: I0 Position */\r
-#define LCD_PAL192_I0_Msk (0x01UL << LCD_PAL192_I0_Pos) /*!< LCD PAL192: I0 Mask */\r
-#define LCD_PAL192_R14_0_Pos 16 /*!< LCD PAL192: R14_0 Position */\r
-#define LCD_PAL192_R14_0_Msk (0x1fUL << LCD_PAL192_R14_0_Pos) /*!< LCD PAL192: R14_0 Mask */\r
-#define LCD_PAL192_G14_0_Pos 21 /*!< LCD PAL192: G14_0 Position */\r
-#define LCD_PAL192_G14_0_Msk (0x1fUL << LCD_PAL192_G14_0_Pos) /*!< LCD PAL192: G14_0 Mask */\r
-#define LCD_PAL192_B14_0_Pos 26 /*!< LCD PAL192: B14_0 Position */\r
-#define LCD_PAL192_B14_0_Msk (0x1fUL << LCD_PAL192_B14_0_Pos) /*!< LCD PAL192: B14_0 Mask */\r
-#define LCD_PAL192_I1_Pos 31 /*!< LCD PAL192: I1 Position */\r
-#define LCD_PAL192_I1_Msk (0x01UL << LCD_PAL192_I1_Pos) /*!< LCD PAL192: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL193 -------------------------------------------\r
-#define LCD_PAL193_R04_0_Pos 0 /*!< LCD PAL193: R04_0 Position */\r
-#define LCD_PAL193_R04_0_Msk (0x1fUL << LCD_PAL193_R04_0_Pos) /*!< LCD PAL193: R04_0 Mask */\r
-#define LCD_PAL193_G04_0_Pos 5 /*!< LCD PAL193: G04_0 Position */\r
-#define LCD_PAL193_G04_0_Msk (0x1fUL << LCD_PAL193_G04_0_Pos) /*!< LCD PAL193: G04_0 Mask */\r
-#define LCD_PAL193_B04_0_Pos 10 /*!< LCD PAL193: B04_0 Position */\r
-#define LCD_PAL193_B04_0_Msk (0x1fUL << LCD_PAL193_B04_0_Pos) /*!< LCD PAL193: B04_0 Mask */\r
-#define LCD_PAL193_I0_Pos 15 /*!< LCD PAL193: I0 Position */\r
-#define LCD_PAL193_I0_Msk (0x01UL << LCD_PAL193_I0_Pos) /*!< LCD PAL193: I0 Mask */\r
-#define LCD_PAL193_R14_0_Pos 16 /*!< LCD PAL193: R14_0 Position */\r
-#define LCD_PAL193_R14_0_Msk (0x1fUL << LCD_PAL193_R14_0_Pos) /*!< LCD PAL193: R14_0 Mask */\r
-#define LCD_PAL193_G14_0_Pos 21 /*!< LCD PAL193: G14_0 Position */\r
-#define LCD_PAL193_G14_0_Msk (0x1fUL << LCD_PAL193_G14_0_Pos) /*!< LCD PAL193: G14_0 Mask */\r
-#define LCD_PAL193_B14_0_Pos 26 /*!< LCD PAL193: B14_0 Position */\r
-#define LCD_PAL193_B14_0_Msk (0x1fUL << LCD_PAL193_B14_0_Pos) /*!< LCD PAL193: B14_0 Mask */\r
-#define LCD_PAL193_I1_Pos 31 /*!< LCD PAL193: I1 Position */\r
-#define LCD_PAL193_I1_Msk (0x01UL << LCD_PAL193_I1_Pos) /*!< LCD PAL193: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL194 -------------------------------------------\r
-#define LCD_PAL194_R04_0_Pos 0 /*!< LCD PAL194: R04_0 Position */\r
-#define LCD_PAL194_R04_0_Msk (0x1fUL << LCD_PAL194_R04_0_Pos) /*!< LCD PAL194: R04_0 Mask */\r
-#define LCD_PAL194_G04_0_Pos 5 /*!< LCD PAL194: G04_0 Position */\r
-#define LCD_PAL194_G04_0_Msk (0x1fUL << LCD_PAL194_G04_0_Pos) /*!< LCD PAL194: G04_0 Mask */\r
-#define LCD_PAL194_B04_0_Pos 10 /*!< LCD PAL194: B04_0 Position */\r
-#define LCD_PAL194_B04_0_Msk (0x1fUL << LCD_PAL194_B04_0_Pos) /*!< LCD PAL194: B04_0 Mask */\r
-#define LCD_PAL194_I0_Pos 15 /*!< LCD PAL194: I0 Position */\r
-#define LCD_PAL194_I0_Msk (0x01UL << LCD_PAL194_I0_Pos) /*!< LCD PAL194: I0 Mask */\r
-#define LCD_PAL194_R14_0_Pos 16 /*!< LCD PAL194: R14_0 Position */\r
-#define LCD_PAL194_R14_0_Msk (0x1fUL << LCD_PAL194_R14_0_Pos) /*!< LCD PAL194: R14_0 Mask */\r
-#define LCD_PAL194_G14_0_Pos 21 /*!< LCD PAL194: G14_0 Position */\r
-#define LCD_PAL194_G14_0_Msk (0x1fUL << LCD_PAL194_G14_0_Pos) /*!< LCD PAL194: G14_0 Mask */\r
-#define LCD_PAL194_B14_0_Pos 26 /*!< LCD PAL194: B14_0 Position */\r
-#define LCD_PAL194_B14_0_Msk (0x1fUL << LCD_PAL194_B14_0_Pos) /*!< LCD PAL194: B14_0 Mask */\r
-#define LCD_PAL194_I1_Pos 31 /*!< LCD PAL194: I1 Position */\r
-#define LCD_PAL194_I1_Msk (0x01UL << LCD_PAL194_I1_Pos) /*!< LCD PAL194: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL195 -------------------------------------------\r
-#define LCD_PAL195_R04_0_Pos 0 /*!< LCD PAL195: R04_0 Position */\r
-#define LCD_PAL195_R04_0_Msk (0x1fUL << LCD_PAL195_R04_0_Pos) /*!< LCD PAL195: R04_0 Mask */\r
-#define LCD_PAL195_G04_0_Pos 5 /*!< LCD PAL195: G04_0 Position */\r
-#define LCD_PAL195_G04_0_Msk (0x1fUL << LCD_PAL195_G04_0_Pos) /*!< LCD PAL195: G04_0 Mask */\r
-#define LCD_PAL195_B04_0_Pos 10 /*!< LCD PAL195: B04_0 Position */\r
-#define LCD_PAL195_B04_0_Msk (0x1fUL << LCD_PAL195_B04_0_Pos) /*!< LCD PAL195: B04_0 Mask */\r
-#define LCD_PAL195_I0_Pos 15 /*!< LCD PAL195: I0 Position */\r
-#define LCD_PAL195_I0_Msk (0x01UL << LCD_PAL195_I0_Pos) /*!< LCD PAL195: I0 Mask */\r
-#define LCD_PAL195_R14_0_Pos 16 /*!< LCD PAL195: R14_0 Position */\r
-#define LCD_PAL195_R14_0_Msk (0x1fUL << LCD_PAL195_R14_0_Pos) /*!< LCD PAL195: R14_0 Mask */\r
-#define LCD_PAL195_G14_0_Pos 21 /*!< LCD PAL195: G14_0 Position */\r
-#define LCD_PAL195_G14_0_Msk (0x1fUL << LCD_PAL195_G14_0_Pos) /*!< LCD PAL195: G14_0 Mask */\r
-#define LCD_PAL195_B14_0_Pos 26 /*!< LCD PAL195: B14_0 Position */\r
-#define LCD_PAL195_B14_0_Msk (0x1fUL << LCD_PAL195_B14_0_Pos) /*!< LCD PAL195: B14_0 Mask */\r
-#define LCD_PAL195_I1_Pos 31 /*!< LCD PAL195: I1 Position */\r
-#define LCD_PAL195_I1_Msk (0x01UL << LCD_PAL195_I1_Pos) /*!< LCD PAL195: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL196 -------------------------------------------\r
-#define LCD_PAL196_R04_0_Pos 0 /*!< LCD PAL196: R04_0 Position */\r
-#define LCD_PAL196_R04_0_Msk (0x1fUL << LCD_PAL196_R04_0_Pos) /*!< LCD PAL196: R04_0 Mask */\r
-#define LCD_PAL196_G04_0_Pos 5 /*!< LCD PAL196: G04_0 Position */\r
-#define LCD_PAL196_G04_0_Msk (0x1fUL << LCD_PAL196_G04_0_Pos) /*!< LCD PAL196: G04_0 Mask */\r
-#define LCD_PAL196_B04_0_Pos 10 /*!< LCD PAL196: B04_0 Position */\r
-#define LCD_PAL196_B04_0_Msk (0x1fUL << LCD_PAL196_B04_0_Pos) /*!< LCD PAL196: B04_0 Mask */\r
-#define LCD_PAL196_I0_Pos 15 /*!< LCD PAL196: I0 Position */\r
-#define LCD_PAL196_I0_Msk (0x01UL << LCD_PAL196_I0_Pos) /*!< LCD PAL196: I0 Mask */\r
-#define LCD_PAL196_R14_0_Pos 16 /*!< LCD PAL196: R14_0 Position */\r
-#define LCD_PAL196_R14_0_Msk (0x1fUL << LCD_PAL196_R14_0_Pos) /*!< LCD PAL196: R14_0 Mask */\r
-#define LCD_PAL196_G14_0_Pos 21 /*!< LCD PAL196: G14_0 Position */\r
-#define LCD_PAL196_G14_0_Msk (0x1fUL << LCD_PAL196_G14_0_Pos) /*!< LCD PAL196: G14_0 Mask */\r
-#define LCD_PAL196_B14_0_Pos 26 /*!< LCD PAL196: B14_0 Position */\r
-#define LCD_PAL196_B14_0_Msk (0x1fUL << LCD_PAL196_B14_0_Pos) /*!< LCD PAL196: B14_0 Mask */\r
-#define LCD_PAL196_I1_Pos 31 /*!< LCD PAL196: I1 Position */\r
-#define LCD_PAL196_I1_Msk (0x01UL << LCD_PAL196_I1_Pos) /*!< LCD PAL196: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL197 -------------------------------------------\r
-#define LCD_PAL197_R04_0_Pos 0 /*!< LCD PAL197: R04_0 Position */\r
-#define LCD_PAL197_R04_0_Msk (0x1fUL << LCD_PAL197_R04_0_Pos) /*!< LCD PAL197: R04_0 Mask */\r
-#define LCD_PAL197_G04_0_Pos 5 /*!< LCD PAL197: G04_0 Position */\r
-#define LCD_PAL197_G04_0_Msk (0x1fUL << LCD_PAL197_G04_0_Pos) /*!< LCD PAL197: G04_0 Mask */\r
-#define LCD_PAL197_B04_0_Pos 10 /*!< LCD PAL197: B04_0 Position */\r
-#define LCD_PAL197_B04_0_Msk (0x1fUL << LCD_PAL197_B04_0_Pos) /*!< LCD PAL197: B04_0 Mask */\r
-#define LCD_PAL197_I0_Pos 15 /*!< LCD PAL197: I0 Position */\r
-#define LCD_PAL197_I0_Msk (0x01UL << LCD_PAL197_I0_Pos) /*!< LCD PAL197: I0 Mask */\r
-#define LCD_PAL197_R14_0_Pos 16 /*!< LCD PAL197: R14_0 Position */\r
-#define LCD_PAL197_R14_0_Msk (0x1fUL << LCD_PAL197_R14_0_Pos) /*!< LCD PAL197: R14_0 Mask */\r
-#define LCD_PAL197_G14_0_Pos 21 /*!< LCD PAL197: G14_0 Position */\r
-#define LCD_PAL197_G14_0_Msk (0x1fUL << LCD_PAL197_G14_0_Pos) /*!< LCD PAL197: G14_0 Mask */\r
-#define LCD_PAL197_B14_0_Pos 26 /*!< LCD PAL197: B14_0 Position */\r
-#define LCD_PAL197_B14_0_Msk (0x1fUL << LCD_PAL197_B14_0_Pos) /*!< LCD PAL197: B14_0 Mask */\r
-#define LCD_PAL197_I1_Pos 31 /*!< LCD PAL197: I1 Position */\r
-#define LCD_PAL197_I1_Msk (0x01UL << LCD_PAL197_I1_Pos) /*!< LCD PAL197: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL198 -------------------------------------------\r
-#define LCD_PAL198_R04_0_Pos 0 /*!< LCD PAL198: R04_0 Position */\r
-#define LCD_PAL198_R04_0_Msk (0x1fUL << LCD_PAL198_R04_0_Pos) /*!< LCD PAL198: R04_0 Mask */\r
-#define LCD_PAL198_G04_0_Pos 5 /*!< LCD PAL198: G04_0 Position */\r
-#define LCD_PAL198_G04_0_Msk (0x1fUL << LCD_PAL198_G04_0_Pos) /*!< LCD PAL198: G04_0 Mask */\r
-#define LCD_PAL198_B04_0_Pos 10 /*!< LCD PAL198: B04_0 Position */\r
-#define LCD_PAL198_B04_0_Msk (0x1fUL << LCD_PAL198_B04_0_Pos) /*!< LCD PAL198: B04_0 Mask */\r
-#define LCD_PAL198_I0_Pos 15 /*!< LCD PAL198: I0 Position */\r
-#define LCD_PAL198_I0_Msk (0x01UL << LCD_PAL198_I0_Pos) /*!< LCD PAL198: I0 Mask */\r
-#define LCD_PAL198_R14_0_Pos 16 /*!< LCD PAL198: R14_0 Position */\r
-#define LCD_PAL198_R14_0_Msk (0x1fUL << LCD_PAL198_R14_0_Pos) /*!< LCD PAL198: R14_0 Mask */\r
-#define LCD_PAL198_G14_0_Pos 21 /*!< LCD PAL198: G14_0 Position */\r
-#define LCD_PAL198_G14_0_Msk (0x1fUL << LCD_PAL198_G14_0_Pos) /*!< LCD PAL198: G14_0 Mask */\r
-#define LCD_PAL198_B14_0_Pos 26 /*!< LCD PAL198: B14_0 Position */\r
-#define LCD_PAL198_B14_0_Msk (0x1fUL << LCD_PAL198_B14_0_Pos) /*!< LCD PAL198: B14_0 Mask */\r
-#define LCD_PAL198_I1_Pos 31 /*!< LCD PAL198: I1 Position */\r
-#define LCD_PAL198_I1_Msk (0x01UL << LCD_PAL198_I1_Pos) /*!< LCD PAL198: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL199 -------------------------------------------\r
-#define LCD_PAL199_R04_0_Pos 0 /*!< LCD PAL199: R04_0 Position */\r
-#define LCD_PAL199_R04_0_Msk (0x1fUL << LCD_PAL199_R04_0_Pos) /*!< LCD PAL199: R04_0 Mask */\r
-#define LCD_PAL199_G04_0_Pos 5 /*!< LCD PAL199: G04_0 Position */\r
-#define LCD_PAL199_G04_0_Msk (0x1fUL << LCD_PAL199_G04_0_Pos) /*!< LCD PAL199: G04_0 Mask */\r
-#define LCD_PAL199_B04_0_Pos 10 /*!< LCD PAL199: B04_0 Position */\r
-#define LCD_PAL199_B04_0_Msk (0x1fUL << LCD_PAL199_B04_0_Pos) /*!< LCD PAL199: B04_0 Mask */\r
-#define LCD_PAL199_I0_Pos 15 /*!< LCD PAL199: I0 Position */\r
-#define LCD_PAL199_I0_Msk (0x01UL << LCD_PAL199_I0_Pos) /*!< LCD PAL199: I0 Mask */\r
-#define LCD_PAL199_R14_0_Pos 16 /*!< LCD PAL199: R14_0 Position */\r
-#define LCD_PAL199_R14_0_Msk (0x1fUL << LCD_PAL199_R14_0_Pos) /*!< LCD PAL199: R14_0 Mask */\r
-#define LCD_PAL199_G14_0_Pos 21 /*!< LCD PAL199: G14_0 Position */\r
-#define LCD_PAL199_G14_0_Msk (0x1fUL << LCD_PAL199_G14_0_Pos) /*!< LCD PAL199: G14_0 Mask */\r
-#define LCD_PAL199_B14_0_Pos 26 /*!< LCD PAL199: B14_0 Position */\r
-#define LCD_PAL199_B14_0_Msk (0x1fUL << LCD_PAL199_B14_0_Pos) /*!< LCD PAL199: B14_0 Mask */\r
-#define LCD_PAL199_I1_Pos 31 /*!< LCD PAL199: I1 Position */\r
-#define LCD_PAL199_I1_Msk (0x01UL << LCD_PAL199_I1_Pos) /*!< LCD PAL199: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL200 -------------------------------------------\r
-#define LCD_PAL200_R04_0_Pos 0 /*!< LCD PAL200: R04_0 Position */\r
-#define LCD_PAL200_R04_0_Msk (0x1fUL << LCD_PAL200_R04_0_Pos) /*!< LCD PAL200: R04_0 Mask */\r
-#define LCD_PAL200_G04_0_Pos 5 /*!< LCD PAL200: G04_0 Position */\r
-#define LCD_PAL200_G04_0_Msk (0x1fUL << LCD_PAL200_G04_0_Pos) /*!< LCD PAL200: G04_0 Mask */\r
-#define LCD_PAL200_B04_0_Pos 10 /*!< LCD PAL200: B04_0 Position */\r
-#define LCD_PAL200_B04_0_Msk (0x1fUL << LCD_PAL200_B04_0_Pos) /*!< LCD PAL200: B04_0 Mask */\r
-#define LCD_PAL200_I0_Pos 15 /*!< LCD PAL200: I0 Position */\r
-#define LCD_PAL200_I0_Msk (0x01UL << LCD_PAL200_I0_Pos) /*!< LCD PAL200: I0 Mask */\r
-#define LCD_PAL200_R14_0_Pos 16 /*!< LCD PAL200: R14_0 Position */\r
-#define LCD_PAL200_R14_0_Msk (0x1fUL << LCD_PAL200_R14_0_Pos) /*!< LCD PAL200: R14_0 Mask */\r
-#define LCD_PAL200_G14_0_Pos 21 /*!< LCD PAL200: G14_0 Position */\r
-#define LCD_PAL200_G14_0_Msk (0x1fUL << LCD_PAL200_G14_0_Pos) /*!< LCD PAL200: G14_0 Mask */\r
-#define LCD_PAL200_B14_0_Pos 26 /*!< LCD PAL200: B14_0 Position */\r
-#define LCD_PAL200_B14_0_Msk (0x1fUL << LCD_PAL200_B14_0_Pos) /*!< LCD PAL200: B14_0 Mask */\r
-#define LCD_PAL200_I1_Pos 31 /*!< LCD PAL200: I1 Position */\r
-#define LCD_PAL200_I1_Msk (0x01UL << LCD_PAL200_I1_Pos) /*!< LCD PAL200: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL201 -------------------------------------------\r
-#define LCD_PAL201_R04_0_Pos 0 /*!< LCD PAL201: R04_0 Position */\r
-#define LCD_PAL201_R04_0_Msk (0x1fUL << LCD_PAL201_R04_0_Pos) /*!< LCD PAL201: R04_0 Mask */\r
-#define LCD_PAL201_G04_0_Pos 5 /*!< LCD PAL201: G04_0 Position */\r
-#define LCD_PAL201_G04_0_Msk (0x1fUL << LCD_PAL201_G04_0_Pos) /*!< LCD PAL201: G04_0 Mask */\r
-#define LCD_PAL201_B04_0_Pos 10 /*!< LCD PAL201: B04_0 Position */\r
-#define LCD_PAL201_B04_0_Msk (0x1fUL << LCD_PAL201_B04_0_Pos) /*!< LCD PAL201: B04_0 Mask */\r
-#define LCD_PAL201_I0_Pos 15 /*!< LCD PAL201: I0 Position */\r
-#define LCD_PAL201_I0_Msk (0x01UL << LCD_PAL201_I0_Pos) /*!< LCD PAL201: I0 Mask */\r
-#define LCD_PAL201_R14_0_Pos 16 /*!< LCD PAL201: R14_0 Position */\r
-#define LCD_PAL201_R14_0_Msk (0x1fUL << LCD_PAL201_R14_0_Pos) /*!< LCD PAL201: R14_0 Mask */\r
-#define LCD_PAL201_G14_0_Pos 21 /*!< LCD PAL201: G14_0 Position */\r
-#define LCD_PAL201_G14_0_Msk (0x1fUL << LCD_PAL201_G14_0_Pos) /*!< LCD PAL201: G14_0 Mask */\r
-#define LCD_PAL201_B14_0_Pos 26 /*!< LCD PAL201: B14_0 Position */\r
-#define LCD_PAL201_B14_0_Msk (0x1fUL << LCD_PAL201_B14_0_Pos) /*!< LCD PAL201: B14_0 Mask */\r
-#define LCD_PAL201_I1_Pos 31 /*!< LCD PAL201: I1 Position */\r
-#define LCD_PAL201_I1_Msk (0x01UL << LCD_PAL201_I1_Pos) /*!< LCD PAL201: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL202 -------------------------------------------\r
-#define LCD_PAL202_R04_0_Pos 0 /*!< LCD PAL202: R04_0 Position */\r
-#define LCD_PAL202_R04_0_Msk (0x1fUL << LCD_PAL202_R04_0_Pos) /*!< LCD PAL202: R04_0 Mask */\r
-#define LCD_PAL202_G04_0_Pos 5 /*!< LCD PAL202: G04_0 Position */\r
-#define LCD_PAL202_G04_0_Msk (0x1fUL << LCD_PAL202_G04_0_Pos) /*!< LCD PAL202: G04_0 Mask */\r
-#define LCD_PAL202_B04_0_Pos 10 /*!< LCD PAL202: B04_0 Position */\r
-#define LCD_PAL202_B04_0_Msk (0x1fUL << LCD_PAL202_B04_0_Pos) /*!< LCD PAL202: B04_0 Mask */\r
-#define LCD_PAL202_I0_Pos 15 /*!< LCD PAL202: I0 Position */\r
-#define LCD_PAL202_I0_Msk (0x01UL << LCD_PAL202_I0_Pos) /*!< LCD PAL202: I0 Mask */\r
-#define LCD_PAL202_R14_0_Pos 16 /*!< LCD PAL202: R14_0 Position */\r
-#define LCD_PAL202_R14_0_Msk (0x1fUL << LCD_PAL202_R14_0_Pos) /*!< LCD PAL202: R14_0 Mask */\r
-#define LCD_PAL202_G14_0_Pos 21 /*!< LCD PAL202: G14_0 Position */\r
-#define LCD_PAL202_G14_0_Msk (0x1fUL << LCD_PAL202_G14_0_Pos) /*!< LCD PAL202: G14_0 Mask */\r
-#define LCD_PAL202_B14_0_Pos 26 /*!< LCD PAL202: B14_0 Position */\r
-#define LCD_PAL202_B14_0_Msk (0x1fUL << LCD_PAL202_B14_0_Pos) /*!< LCD PAL202: B14_0 Mask */\r
-#define LCD_PAL202_I1_Pos 31 /*!< LCD PAL202: I1 Position */\r
-#define LCD_PAL202_I1_Msk (0x01UL << LCD_PAL202_I1_Pos) /*!< LCD PAL202: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL203 -------------------------------------------\r
-#define LCD_PAL203_R04_0_Pos 0 /*!< LCD PAL203: R04_0 Position */\r
-#define LCD_PAL203_R04_0_Msk (0x1fUL << LCD_PAL203_R04_0_Pos) /*!< LCD PAL203: R04_0 Mask */\r
-#define LCD_PAL203_G04_0_Pos 5 /*!< LCD PAL203: G04_0 Position */\r
-#define LCD_PAL203_G04_0_Msk (0x1fUL << LCD_PAL203_G04_0_Pos) /*!< LCD PAL203: G04_0 Mask */\r
-#define LCD_PAL203_B04_0_Pos 10 /*!< LCD PAL203: B04_0 Position */\r
-#define LCD_PAL203_B04_0_Msk (0x1fUL << LCD_PAL203_B04_0_Pos) /*!< LCD PAL203: B04_0 Mask */\r
-#define LCD_PAL203_I0_Pos 15 /*!< LCD PAL203: I0 Position */\r
-#define LCD_PAL203_I0_Msk (0x01UL << LCD_PAL203_I0_Pos) /*!< LCD PAL203: I0 Mask */\r
-#define LCD_PAL203_R14_0_Pos 16 /*!< LCD PAL203: R14_0 Position */\r
-#define LCD_PAL203_R14_0_Msk (0x1fUL << LCD_PAL203_R14_0_Pos) /*!< LCD PAL203: R14_0 Mask */\r
-#define LCD_PAL203_G14_0_Pos 21 /*!< LCD PAL203: G14_0 Position */\r
-#define LCD_PAL203_G14_0_Msk (0x1fUL << LCD_PAL203_G14_0_Pos) /*!< LCD PAL203: G14_0 Mask */\r
-#define LCD_PAL203_B14_0_Pos 26 /*!< LCD PAL203: B14_0 Position */\r
-#define LCD_PAL203_B14_0_Msk (0x1fUL << LCD_PAL203_B14_0_Pos) /*!< LCD PAL203: B14_0 Mask */\r
-#define LCD_PAL203_I1_Pos 31 /*!< LCD PAL203: I1 Position */\r
-#define LCD_PAL203_I1_Msk (0x01UL << LCD_PAL203_I1_Pos) /*!< LCD PAL203: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL204 -------------------------------------------\r
-#define LCD_PAL204_R04_0_Pos 0 /*!< LCD PAL204: R04_0 Position */\r
-#define LCD_PAL204_R04_0_Msk (0x1fUL << LCD_PAL204_R04_0_Pos) /*!< LCD PAL204: R04_0 Mask */\r
-#define LCD_PAL204_G04_0_Pos 5 /*!< LCD PAL204: G04_0 Position */\r
-#define LCD_PAL204_G04_0_Msk (0x1fUL << LCD_PAL204_G04_0_Pos) /*!< LCD PAL204: G04_0 Mask */\r
-#define LCD_PAL204_B04_0_Pos 10 /*!< LCD PAL204: B04_0 Position */\r
-#define LCD_PAL204_B04_0_Msk (0x1fUL << LCD_PAL204_B04_0_Pos) /*!< LCD PAL204: B04_0 Mask */\r
-#define LCD_PAL204_I0_Pos 15 /*!< LCD PAL204: I0 Position */\r
-#define LCD_PAL204_I0_Msk (0x01UL << LCD_PAL204_I0_Pos) /*!< LCD PAL204: I0 Mask */\r
-#define LCD_PAL204_R14_0_Pos 16 /*!< LCD PAL204: R14_0 Position */\r
-#define LCD_PAL204_R14_0_Msk (0x1fUL << LCD_PAL204_R14_0_Pos) /*!< LCD PAL204: R14_0 Mask */\r
-#define LCD_PAL204_G14_0_Pos 21 /*!< LCD PAL204: G14_0 Position */\r
-#define LCD_PAL204_G14_0_Msk (0x1fUL << LCD_PAL204_G14_0_Pos) /*!< LCD PAL204: G14_0 Mask */\r
-#define LCD_PAL204_B14_0_Pos 26 /*!< LCD PAL204: B14_0 Position */\r
-#define LCD_PAL204_B14_0_Msk (0x1fUL << LCD_PAL204_B14_0_Pos) /*!< LCD PAL204: B14_0 Mask */\r
-#define LCD_PAL204_I1_Pos 31 /*!< LCD PAL204: I1 Position */\r
-#define LCD_PAL204_I1_Msk (0x01UL << LCD_PAL204_I1_Pos) /*!< LCD PAL204: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL205 -------------------------------------------\r
-#define LCD_PAL205_R04_0_Pos 0 /*!< LCD PAL205: R04_0 Position */\r
-#define LCD_PAL205_R04_0_Msk (0x1fUL << LCD_PAL205_R04_0_Pos) /*!< LCD PAL205: R04_0 Mask */\r
-#define LCD_PAL205_G04_0_Pos 5 /*!< LCD PAL205: G04_0 Position */\r
-#define LCD_PAL205_G04_0_Msk (0x1fUL << LCD_PAL205_G04_0_Pos) /*!< LCD PAL205: G04_0 Mask */\r
-#define LCD_PAL205_B04_0_Pos 10 /*!< LCD PAL205: B04_0 Position */\r
-#define LCD_PAL205_B04_0_Msk (0x1fUL << LCD_PAL205_B04_0_Pos) /*!< LCD PAL205: B04_0 Mask */\r
-#define LCD_PAL205_I0_Pos 15 /*!< LCD PAL205: I0 Position */\r
-#define LCD_PAL205_I0_Msk (0x01UL << LCD_PAL205_I0_Pos) /*!< LCD PAL205: I0 Mask */\r
-#define LCD_PAL205_R14_0_Pos 16 /*!< LCD PAL205: R14_0 Position */\r
-#define LCD_PAL205_R14_0_Msk (0x1fUL << LCD_PAL205_R14_0_Pos) /*!< LCD PAL205: R14_0 Mask */\r
-#define LCD_PAL205_G14_0_Pos 21 /*!< LCD PAL205: G14_0 Position */\r
-#define LCD_PAL205_G14_0_Msk (0x1fUL << LCD_PAL205_G14_0_Pos) /*!< LCD PAL205: G14_0 Mask */\r
-#define LCD_PAL205_B14_0_Pos 26 /*!< LCD PAL205: B14_0 Position */\r
-#define LCD_PAL205_B14_0_Msk (0x1fUL << LCD_PAL205_B14_0_Pos) /*!< LCD PAL205: B14_0 Mask */\r
-#define LCD_PAL205_I1_Pos 31 /*!< LCD PAL205: I1 Position */\r
-#define LCD_PAL205_I1_Msk (0x01UL << LCD_PAL205_I1_Pos) /*!< LCD PAL205: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL206 -------------------------------------------\r
-#define LCD_PAL206_R04_0_Pos 0 /*!< LCD PAL206: R04_0 Position */\r
-#define LCD_PAL206_R04_0_Msk (0x1fUL << LCD_PAL206_R04_0_Pos) /*!< LCD PAL206: R04_0 Mask */\r
-#define LCD_PAL206_G04_0_Pos 5 /*!< LCD PAL206: G04_0 Position */\r
-#define LCD_PAL206_G04_0_Msk (0x1fUL << LCD_PAL206_G04_0_Pos) /*!< LCD PAL206: G04_0 Mask */\r
-#define LCD_PAL206_B04_0_Pos 10 /*!< LCD PAL206: B04_0 Position */\r
-#define LCD_PAL206_B04_0_Msk (0x1fUL << LCD_PAL206_B04_0_Pos) /*!< LCD PAL206: B04_0 Mask */\r
-#define LCD_PAL206_I0_Pos 15 /*!< LCD PAL206: I0 Position */\r
-#define LCD_PAL206_I0_Msk (0x01UL << LCD_PAL206_I0_Pos) /*!< LCD PAL206: I0 Mask */\r
-#define LCD_PAL206_R14_0_Pos 16 /*!< LCD PAL206: R14_0 Position */\r
-#define LCD_PAL206_R14_0_Msk (0x1fUL << LCD_PAL206_R14_0_Pos) /*!< LCD PAL206: R14_0 Mask */\r
-#define LCD_PAL206_G14_0_Pos 21 /*!< LCD PAL206: G14_0 Position */\r
-#define LCD_PAL206_G14_0_Msk (0x1fUL << LCD_PAL206_G14_0_Pos) /*!< LCD PAL206: G14_0 Mask */\r
-#define LCD_PAL206_B14_0_Pos 26 /*!< LCD PAL206: B14_0 Position */\r
-#define LCD_PAL206_B14_0_Msk (0x1fUL << LCD_PAL206_B14_0_Pos) /*!< LCD PAL206: B14_0 Mask */\r
-#define LCD_PAL206_I1_Pos 31 /*!< LCD PAL206: I1 Position */\r
-#define LCD_PAL206_I1_Msk (0x01UL << LCD_PAL206_I1_Pos) /*!< LCD PAL206: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL207 -------------------------------------------\r
-#define LCD_PAL207_R04_0_Pos 0 /*!< LCD PAL207: R04_0 Position */\r
-#define LCD_PAL207_R04_0_Msk (0x1fUL << LCD_PAL207_R04_0_Pos) /*!< LCD PAL207: R04_0 Mask */\r
-#define LCD_PAL207_G04_0_Pos 5 /*!< LCD PAL207: G04_0 Position */\r
-#define LCD_PAL207_G04_0_Msk (0x1fUL << LCD_PAL207_G04_0_Pos) /*!< LCD PAL207: G04_0 Mask */\r
-#define LCD_PAL207_B04_0_Pos 10 /*!< LCD PAL207: B04_0 Position */\r
-#define LCD_PAL207_B04_0_Msk (0x1fUL << LCD_PAL207_B04_0_Pos) /*!< LCD PAL207: B04_0 Mask */\r
-#define LCD_PAL207_I0_Pos 15 /*!< LCD PAL207: I0 Position */\r
-#define LCD_PAL207_I0_Msk (0x01UL << LCD_PAL207_I0_Pos) /*!< LCD PAL207: I0 Mask */\r
-#define LCD_PAL207_R14_0_Pos 16 /*!< LCD PAL207: R14_0 Position */\r
-#define LCD_PAL207_R14_0_Msk (0x1fUL << LCD_PAL207_R14_0_Pos) /*!< LCD PAL207: R14_0 Mask */\r
-#define LCD_PAL207_G14_0_Pos 21 /*!< LCD PAL207: G14_0 Position */\r
-#define LCD_PAL207_G14_0_Msk (0x1fUL << LCD_PAL207_G14_0_Pos) /*!< LCD PAL207: G14_0 Mask */\r
-#define LCD_PAL207_B14_0_Pos 26 /*!< LCD PAL207: B14_0 Position */\r
-#define LCD_PAL207_B14_0_Msk (0x1fUL << LCD_PAL207_B14_0_Pos) /*!< LCD PAL207: B14_0 Mask */\r
-#define LCD_PAL207_I1_Pos 31 /*!< LCD PAL207: I1 Position */\r
-#define LCD_PAL207_I1_Msk (0x01UL << LCD_PAL207_I1_Pos) /*!< LCD PAL207: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL208 -------------------------------------------\r
-#define LCD_PAL208_R04_0_Pos 0 /*!< LCD PAL208: R04_0 Position */\r
-#define LCD_PAL208_R04_0_Msk (0x1fUL << LCD_PAL208_R04_0_Pos) /*!< LCD PAL208: R04_0 Mask */\r
-#define LCD_PAL208_G04_0_Pos 5 /*!< LCD PAL208: G04_0 Position */\r
-#define LCD_PAL208_G04_0_Msk (0x1fUL << LCD_PAL208_G04_0_Pos) /*!< LCD PAL208: G04_0 Mask */\r
-#define LCD_PAL208_B04_0_Pos 10 /*!< LCD PAL208: B04_0 Position */\r
-#define LCD_PAL208_B04_0_Msk (0x1fUL << LCD_PAL208_B04_0_Pos) /*!< LCD PAL208: B04_0 Mask */\r
-#define LCD_PAL208_I0_Pos 15 /*!< LCD PAL208: I0 Position */\r
-#define LCD_PAL208_I0_Msk (0x01UL << LCD_PAL208_I0_Pos) /*!< LCD PAL208: I0 Mask */\r
-#define LCD_PAL208_R14_0_Pos 16 /*!< LCD PAL208: R14_0 Position */\r
-#define LCD_PAL208_R14_0_Msk (0x1fUL << LCD_PAL208_R14_0_Pos) /*!< LCD PAL208: R14_0 Mask */\r
-#define LCD_PAL208_G14_0_Pos 21 /*!< LCD PAL208: G14_0 Position */\r
-#define LCD_PAL208_G14_0_Msk (0x1fUL << LCD_PAL208_G14_0_Pos) /*!< LCD PAL208: G14_0 Mask */\r
-#define LCD_PAL208_B14_0_Pos 26 /*!< LCD PAL208: B14_0 Position */\r
-#define LCD_PAL208_B14_0_Msk (0x1fUL << LCD_PAL208_B14_0_Pos) /*!< LCD PAL208: B14_0 Mask */\r
-#define LCD_PAL208_I1_Pos 31 /*!< LCD PAL208: I1 Position */\r
-#define LCD_PAL208_I1_Msk (0x01UL << LCD_PAL208_I1_Pos) /*!< LCD PAL208: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL209 -------------------------------------------\r
-#define LCD_PAL209_R04_0_Pos 0 /*!< LCD PAL209: R04_0 Position */\r
-#define LCD_PAL209_R04_0_Msk (0x1fUL << LCD_PAL209_R04_0_Pos) /*!< LCD PAL209: R04_0 Mask */\r
-#define LCD_PAL209_G04_0_Pos 5 /*!< LCD PAL209: G04_0 Position */\r
-#define LCD_PAL209_G04_0_Msk (0x1fUL << LCD_PAL209_G04_0_Pos) /*!< LCD PAL209: G04_0 Mask */\r
-#define LCD_PAL209_B04_0_Pos 10 /*!< LCD PAL209: B04_0 Position */\r
-#define LCD_PAL209_B04_0_Msk (0x1fUL << LCD_PAL209_B04_0_Pos) /*!< LCD PAL209: B04_0 Mask */\r
-#define LCD_PAL209_I0_Pos 15 /*!< LCD PAL209: I0 Position */\r
-#define LCD_PAL209_I0_Msk (0x01UL << LCD_PAL209_I0_Pos) /*!< LCD PAL209: I0 Mask */\r
-#define LCD_PAL209_R14_0_Pos 16 /*!< LCD PAL209: R14_0 Position */\r
-#define LCD_PAL209_R14_0_Msk (0x1fUL << LCD_PAL209_R14_0_Pos) /*!< LCD PAL209: R14_0 Mask */\r
-#define LCD_PAL209_G14_0_Pos 21 /*!< LCD PAL209: G14_0 Position */\r
-#define LCD_PAL209_G14_0_Msk (0x1fUL << LCD_PAL209_G14_0_Pos) /*!< LCD PAL209: G14_0 Mask */\r
-#define LCD_PAL209_B14_0_Pos 26 /*!< LCD PAL209: B14_0 Position */\r
-#define LCD_PAL209_B14_0_Msk (0x1fUL << LCD_PAL209_B14_0_Pos) /*!< LCD PAL209: B14_0 Mask */\r
-#define LCD_PAL209_I1_Pos 31 /*!< LCD PAL209: I1 Position */\r
-#define LCD_PAL209_I1_Msk (0x01UL << LCD_PAL209_I1_Pos) /*!< LCD PAL209: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL210 -------------------------------------------\r
-#define LCD_PAL210_R04_0_Pos 0 /*!< LCD PAL210: R04_0 Position */\r
-#define LCD_PAL210_R04_0_Msk (0x1fUL << LCD_PAL210_R04_0_Pos) /*!< LCD PAL210: R04_0 Mask */\r
-#define LCD_PAL210_G04_0_Pos 5 /*!< LCD PAL210: G04_0 Position */\r
-#define LCD_PAL210_G04_0_Msk (0x1fUL << LCD_PAL210_G04_0_Pos) /*!< LCD PAL210: G04_0 Mask */\r
-#define LCD_PAL210_B04_0_Pos 10 /*!< LCD PAL210: B04_0 Position */\r
-#define LCD_PAL210_B04_0_Msk (0x1fUL << LCD_PAL210_B04_0_Pos) /*!< LCD PAL210: B04_0 Mask */\r
-#define LCD_PAL210_I0_Pos 15 /*!< LCD PAL210: I0 Position */\r
-#define LCD_PAL210_I0_Msk (0x01UL << LCD_PAL210_I0_Pos) /*!< LCD PAL210: I0 Mask */\r
-#define LCD_PAL210_R14_0_Pos 16 /*!< LCD PAL210: R14_0 Position */\r
-#define LCD_PAL210_R14_0_Msk (0x1fUL << LCD_PAL210_R14_0_Pos) /*!< LCD PAL210: R14_0 Mask */\r
-#define LCD_PAL210_G14_0_Pos 21 /*!< LCD PAL210: G14_0 Position */\r
-#define LCD_PAL210_G14_0_Msk (0x1fUL << LCD_PAL210_G14_0_Pos) /*!< LCD PAL210: G14_0 Mask */\r
-#define LCD_PAL210_B14_0_Pos 26 /*!< LCD PAL210: B14_0 Position */\r
-#define LCD_PAL210_B14_0_Msk (0x1fUL << LCD_PAL210_B14_0_Pos) /*!< LCD PAL210: B14_0 Mask */\r
-#define LCD_PAL210_I1_Pos 31 /*!< LCD PAL210: I1 Position */\r
-#define LCD_PAL210_I1_Msk (0x01UL << LCD_PAL210_I1_Pos) /*!< LCD PAL210: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL211 -------------------------------------------\r
-#define LCD_PAL211_R04_0_Pos 0 /*!< LCD PAL211: R04_0 Position */\r
-#define LCD_PAL211_R04_0_Msk (0x1fUL << LCD_PAL211_R04_0_Pos) /*!< LCD PAL211: R04_0 Mask */\r
-#define LCD_PAL211_G04_0_Pos 5 /*!< LCD PAL211: G04_0 Position */\r
-#define LCD_PAL211_G04_0_Msk (0x1fUL << LCD_PAL211_G04_0_Pos) /*!< LCD PAL211: G04_0 Mask */\r
-#define LCD_PAL211_B04_0_Pos 10 /*!< LCD PAL211: B04_0 Position */\r
-#define LCD_PAL211_B04_0_Msk (0x1fUL << LCD_PAL211_B04_0_Pos) /*!< LCD PAL211: B04_0 Mask */\r
-#define LCD_PAL211_I0_Pos 15 /*!< LCD PAL211: I0 Position */\r
-#define LCD_PAL211_I0_Msk (0x01UL << LCD_PAL211_I0_Pos) /*!< LCD PAL211: I0 Mask */\r
-#define LCD_PAL211_R14_0_Pos 16 /*!< LCD PAL211: R14_0 Position */\r
-#define LCD_PAL211_R14_0_Msk (0x1fUL << LCD_PAL211_R14_0_Pos) /*!< LCD PAL211: R14_0 Mask */\r
-#define LCD_PAL211_G14_0_Pos 21 /*!< LCD PAL211: G14_0 Position */\r
-#define LCD_PAL211_G14_0_Msk (0x1fUL << LCD_PAL211_G14_0_Pos) /*!< LCD PAL211: G14_0 Mask */\r
-#define LCD_PAL211_B14_0_Pos 26 /*!< LCD PAL211: B14_0 Position */\r
-#define LCD_PAL211_B14_0_Msk (0x1fUL << LCD_PAL211_B14_0_Pos) /*!< LCD PAL211: B14_0 Mask */\r
-#define LCD_PAL211_I1_Pos 31 /*!< LCD PAL211: I1 Position */\r
-#define LCD_PAL211_I1_Msk (0x01UL << LCD_PAL211_I1_Pos) /*!< LCD PAL211: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL212 -------------------------------------------\r
-#define LCD_PAL212_R04_0_Pos 0 /*!< LCD PAL212: R04_0 Position */\r
-#define LCD_PAL212_R04_0_Msk (0x1fUL << LCD_PAL212_R04_0_Pos) /*!< LCD PAL212: R04_0 Mask */\r
-#define LCD_PAL212_G04_0_Pos 5 /*!< LCD PAL212: G04_0 Position */\r
-#define LCD_PAL212_G04_0_Msk (0x1fUL << LCD_PAL212_G04_0_Pos) /*!< LCD PAL212: G04_0 Mask */\r
-#define LCD_PAL212_B04_0_Pos 10 /*!< LCD PAL212: B04_0 Position */\r
-#define LCD_PAL212_B04_0_Msk (0x1fUL << LCD_PAL212_B04_0_Pos) /*!< LCD PAL212: B04_0 Mask */\r
-#define LCD_PAL212_I0_Pos 15 /*!< LCD PAL212: I0 Position */\r
-#define LCD_PAL212_I0_Msk (0x01UL << LCD_PAL212_I0_Pos) /*!< LCD PAL212: I0 Mask */\r
-#define LCD_PAL212_R14_0_Pos 16 /*!< LCD PAL212: R14_0 Position */\r
-#define LCD_PAL212_R14_0_Msk (0x1fUL << LCD_PAL212_R14_0_Pos) /*!< LCD PAL212: R14_0 Mask */\r
-#define LCD_PAL212_G14_0_Pos 21 /*!< LCD PAL212: G14_0 Position */\r
-#define LCD_PAL212_G14_0_Msk (0x1fUL << LCD_PAL212_G14_0_Pos) /*!< LCD PAL212: G14_0 Mask */\r
-#define LCD_PAL212_B14_0_Pos 26 /*!< LCD PAL212: B14_0 Position */\r
-#define LCD_PAL212_B14_0_Msk (0x1fUL << LCD_PAL212_B14_0_Pos) /*!< LCD PAL212: B14_0 Mask */\r
-#define LCD_PAL212_I1_Pos 31 /*!< LCD PAL212: I1 Position */\r
-#define LCD_PAL212_I1_Msk (0x01UL << LCD_PAL212_I1_Pos) /*!< LCD PAL212: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL213 -------------------------------------------\r
-#define LCD_PAL213_R04_0_Pos 0 /*!< LCD PAL213: R04_0 Position */\r
-#define LCD_PAL213_R04_0_Msk (0x1fUL << LCD_PAL213_R04_0_Pos) /*!< LCD PAL213: R04_0 Mask */\r
-#define LCD_PAL213_G04_0_Pos 5 /*!< LCD PAL213: G04_0 Position */\r
-#define LCD_PAL213_G04_0_Msk (0x1fUL << LCD_PAL213_G04_0_Pos) /*!< LCD PAL213: G04_0 Mask */\r
-#define LCD_PAL213_B04_0_Pos 10 /*!< LCD PAL213: B04_0 Position */\r
-#define LCD_PAL213_B04_0_Msk (0x1fUL << LCD_PAL213_B04_0_Pos) /*!< LCD PAL213: B04_0 Mask */\r
-#define LCD_PAL213_I0_Pos 15 /*!< LCD PAL213: I0 Position */\r
-#define LCD_PAL213_I0_Msk (0x01UL << LCD_PAL213_I0_Pos) /*!< LCD PAL213: I0 Mask */\r
-#define LCD_PAL213_R14_0_Pos 16 /*!< LCD PAL213: R14_0 Position */\r
-#define LCD_PAL213_R14_0_Msk (0x1fUL << LCD_PAL213_R14_0_Pos) /*!< LCD PAL213: R14_0 Mask */\r
-#define LCD_PAL213_G14_0_Pos 21 /*!< LCD PAL213: G14_0 Position */\r
-#define LCD_PAL213_G14_0_Msk (0x1fUL << LCD_PAL213_G14_0_Pos) /*!< LCD PAL213: G14_0 Mask */\r
-#define LCD_PAL213_B14_0_Pos 26 /*!< LCD PAL213: B14_0 Position */\r
-#define LCD_PAL213_B14_0_Msk (0x1fUL << LCD_PAL213_B14_0_Pos) /*!< LCD PAL213: B14_0 Mask */\r
-#define LCD_PAL213_I1_Pos 31 /*!< LCD PAL213: I1 Position */\r
-#define LCD_PAL213_I1_Msk (0x01UL << LCD_PAL213_I1_Pos) /*!< LCD PAL213: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL214 -------------------------------------------\r
-#define LCD_PAL214_R04_0_Pos 0 /*!< LCD PAL214: R04_0 Position */\r
-#define LCD_PAL214_R04_0_Msk (0x1fUL << LCD_PAL214_R04_0_Pos) /*!< LCD PAL214: R04_0 Mask */\r
-#define LCD_PAL214_G04_0_Pos 5 /*!< LCD PAL214: G04_0 Position */\r
-#define LCD_PAL214_G04_0_Msk (0x1fUL << LCD_PAL214_G04_0_Pos) /*!< LCD PAL214: G04_0 Mask */\r
-#define LCD_PAL214_B04_0_Pos 10 /*!< LCD PAL214: B04_0 Position */\r
-#define LCD_PAL214_B04_0_Msk (0x1fUL << LCD_PAL214_B04_0_Pos) /*!< LCD PAL214: B04_0 Mask */\r
-#define LCD_PAL214_I0_Pos 15 /*!< LCD PAL214: I0 Position */\r
-#define LCD_PAL214_I0_Msk (0x01UL << LCD_PAL214_I0_Pos) /*!< LCD PAL214: I0 Mask */\r
-#define LCD_PAL214_R14_0_Pos 16 /*!< LCD PAL214: R14_0 Position */\r
-#define LCD_PAL214_R14_0_Msk (0x1fUL << LCD_PAL214_R14_0_Pos) /*!< LCD PAL214: R14_0 Mask */\r
-#define LCD_PAL214_G14_0_Pos 21 /*!< LCD PAL214: G14_0 Position */\r
-#define LCD_PAL214_G14_0_Msk (0x1fUL << LCD_PAL214_G14_0_Pos) /*!< LCD PAL214: G14_0 Mask */\r
-#define LCD_PAL214_B14_0_Pos 26 /*!< LCD PAL214: B14_0 Position */\r
-#define LCD_PAL214_B14_0_Msk (0x1fUL << LCD_PAL214_B14_0_Pos) /*!< LCD PAL214: B14_0 Mask */\r
-#define LCD_PAL214_I1_Pos 31 /*!< LCD PAL214: I1 Position */\r
-#define LCD_PAL214_I1_Msk (0x01UL << LCD_PAL214_I1_Pos) /*!< LCD PAL214: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL215 -------------------------------------------\r
-#define LCD_PAL215_R04_0_Pos 0 /*!< LCD PAL215: R04_0 Position */\r
-#define LCD_PAL215_R04_0_Msk (0x1fUL << LCD_PAL215_R04_0_Pos) /*!< LCD PAL215: R04_0 Mask */\r
-#define LCD_PAL215_G04_0_Pos 5 /*!< LCD PAL215: G04_0 Position */\r
-#define LCD_PAL215_G04_0_Msk (0x1fUL << LCD_PAL215_G04_0_Pos) /*!< LCD PAL215: G04_0 Mask */\r
-#define LCD_PAL215_B04_0_Pos 10 /*!< LCD PAL215: B04_0 Position */\r
-#define LCD_PAL215_B04_0_Msk (0x1fUL << LCD_PAL215_B04_0_Pos) /*!< LCD PAL215: B04_0 Mask */\r
-#define LCD_PAL215_I0_Pos 15 /*!< LCD PAL215: I0 Position */\r
-#define LCD_PAL215_I0_Msk (0x01UL << LCD_PAL215_I0_Pos) /*!< LCD PAL215: I0 Mask */\r
-#define LCD_PAL215_R14_0_Pos 16 /*!< LCD PAL215: R14_0 Position */\r
-#define LCD_PAL215_R14_0_Msk (0x1fUL << LCD_PAL215_R14_0_Pos) /*!< LCD PAL215: R14_0 Mask */\r
-#define LCD_PAL215_G14_0_Pos 21 /*!< LCD PAL215: G14_0 Position */\r
-#define LCD_PAL215_G14_0_Msk (0x1fUL << LCD_PAL215_G14_0_Pos) /*!< LCD PAL215: G14_0 Mask */\r
-#define LCD_PAL215_B14_0_Pos 26 /*!< LCD PAL215: B14_0 Position */\r
-#define LCD_PAL215_B14_0_Msk (0x1fUL << LCD_PAL215_B14_0_Pos) /*!< LCD PAL215: B14_0 Mask */\r
-#define LCD_PAL215_I1_Pos 31 /*!< LCD PAL215: I1 Position */\r
-#define LCD_PAL215_I1_Msk (0x01UL << LCD_PAL215_I1_Pos) /*!< LCD PAL215: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL216 -------------------------------------------\r
-#define LCD_PAL216_R04_0_Pos 0 /*!< LCD PAL216: R04_0 Position */\r
-#define LCD_PAL216_R04_0_Msk (0x1fUL << LCD_PAL216_R04_0_Pos) /*!< LCD PAL216: R04_0 Mask */\r
-#define LCD_PAL216_G04_0_Pos 5 /*!< LCD PAL216: G04_0 Position */\r
-#define LCD_PAL216_G04_0_Msk (0x1fUL << LCD_PAL216_G04_0_Pos) /*!< LCD PAL216: G04_0 Mask */\r
-#define LCD_PAL216_B04_0_Pos 10 /*!< LCD PAL216: B04_0 Position */\r
-#define LCD_PAL216_B04_0_Msk (0x1fUL << LCD_PAL216_B04_0_Pos) /*!< LCD PAL216: B04_0 Mask */\r
-#define LCD_PAL216_I0_Pos 15 /*!< LCD PAL216: I0 Position */\r
-#define LCD_PAL216_I0_Msk (0x01UL << LCD_PAL216_I0_Pos) /*!< LCD PAL216: I0 Mask */\r
-#define LCD_PAL216_R14_0_Pos 16 /*!< LCD PAL216: R14_0 Position */\r
-#define LCD_PAL216_R14_0_Msk (0x1fUL << LCD_PAL216_R14_0_Pos) /*!< LCD PAL216: R14_0 Mask */\r
-#define LCD_PAL216_G14_0_Pos 21 /*!< LCD PAL216: G14_0 Position */\r
-#define LCD_PAL216_G14_0_Msk (0x1fUL << LCD_PAL216_G14_0_Pos) /*!< LCD PAL216: G14_0 Mask */\r
-#define LCD_PAL216_B14_0_Pos 26 /*!< LCD PAL216: B14_0 Position */\r
-#define LCD_PAL216_B14_0_Msk (0x1fUL << LCD_PAL216_B14_0_Pos) /*!< LCD PAL216: B14_0 Mask */\r
-#define LCD_PAL216_I1_Pos 31 /*!< LCD PAL216: I1 Position */\r
-#define LCD_PAL216_I1_Msk (0x01UL << LCD_PAL216_I1_Pos) /*!< LCD PAL216: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL217 -------------------------------------------\r
-#define LCD_PAL217_R04_0_Pos 0 /*!< LCD PAL217: R04_0 Position */\r
-#define LCD_PAL217_R04_0_Msk (0x1fUL << LCD_PAL217_R04_0_Pos) /*!< LCD PAL217: R04_0 Mask */\r
-#define LCD_PAL217_G04_0_Pos 5 /*!< LCD PAL217: G04_0 Position */\r
-#define LCD_PAL217_G04_0_Msk (0x1fUL << LCD_PAL217_G04_0_Pos) /*!< LCD PAL217: G04_0 Mask */\r
-#define LCD_PAL217_B04_0_Pos 10 /*!< LCD PAL217: B04_0 Position */\r
-#define LCD_PAL217_B04_0_Msk (0x1fUL << LCD_PAL217_B04_0_Pos) /*!< LCD PAL217: B04_0 Mask */\r
-#define LCD_PAL217_I0_Pos 15 /*!< LCD PAL217: I0 Position */\r
-#define LCD_PAL217_I0_Msk (0x01UL << LCD_PAL217_I0_Pos) /*!< LCD PAL217: I0 Mask */\r
-#define LCD_PAL217_R14_0_Pos 16 /*!< LCD PAL217: R14_0 Position */\r
-#define LCD_PAL217_R14_0_Msk (0x1fUL << LCD_PAL217_R14_0_Pos) /*!< LCD PAL217: R14_0 Mask */\r
-#define LCD_PAL217_G14_0_Pos 21 /*!< LCD PAL217: G14_0 Position */\r
-#define LCD_PAL217_G14_0_Msk (0x1fUL << LCD_PAL217_G14_0_Pos) /*!< LCD PAL217: G14_0 Mask */\r
-#define LCD_PAL217_B14_0_Pos 26 /*!< LCD PAL217: B14_0 Position */\r
-#define LCD_PAL217_B14_0_Msk (0x1fUL << LCD_PAL217_B14_0_Pos) /*!< LCD PAL217: B14_0 Mask */\r
-#define LCD_PAL217_I1_Pos 31 /*!< LCD PAL217: I1 Position */\r
-#define LCD_PAL217_I1_Msk (0x01UL << LCD_PAL217_I1_Pos) /*!< LCD PAL217: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL218 -------------------------------------------\r
-#define LCD_PAL218_R04_0_Pos 0 /*!< LCD PAL218: R04_0 Position */\r
-#define LCD_PAL218_R04_0_Msk (0x1fUL << LCD_PAL218_R04_0_Pos) /*!< LCD PAL218: R04_0 Mask */\r
-#define LCD_PAL218_G04_0_Pos 5 /*!< LCD PAL218: G04_0 Position */\r
-#define LCD_PAL218_G04_0_Msk (0x1fUL << LCD_PAL218_G04_0_Pos) /*!< LCD PAL218: G04_0 Mask */\r
-#define LCD_PAL218_B04_0_Pos 10 /*!< LCD PAL218: B04_0 Position */\r
-#define LCD_PAL218_B04_0_Msk (0x1fUL << LCD_PAL218_B04_0_Pos) /*!< LCD PAL218: B04_0 Mask */\r
-#define LCD_PAL218_I0_Pos 15 /*!< LCD PAL218: I0 Position */\r
-#define LCD_PAL218_I0_Msk (0x01UL << LCD_PAL218_I0_Pos) /*!< LCD PAL218: I0 Mask */\r
-#define LCD_PAL218_R14_0_Pos 16 /*!< LCD PAL218: R14_0 Position */\r
-#define LCD_PAL218_R14_0_Msk (0x1fUL << LCD_PAL218_R14_0_Pos) /*!< LCD PAL218: R14_0 Mask */\r
-#define LCD_PAL218_G14_0_Pos 21 /*!< LCD PAL218: G14_0 Position */\r
-#define LCD_PAL218_G14_0_Msk (0x1fUL << LCD_PAL218_G14_0_Pos) /*!< LCD PAL218: G14_0 Mask */\r
-#define LCD_PAL218_B14_0_Pos 26 /*!< LCD PAL218: B14_0 Position */\r
-#define LCD_PAL218_B14_0_Msk (0x1fUL << LCD_PAL218_B14_0_Pos) /*!< LCD PAL218: B14_0 Mask */\r
-#define LCD_PAL218_I1_Pos 31 /*!< LCD PAL218: I1 Position */\r
-#define LCD_PAL218_I1_Msk (0x01UL << LCD_PAL218_I1_Pos) /*!< LCD PAL218: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL219 -------------------------------------------\r
-#define LCD_PAL219_R04_0_Pos 0 /*!< LCD PAL219: R04_0 Position */\r
-#define LCD_PAL219_R04_0_Msk (0x1fUL << LCD_PAL219_R04_0_Pos) /*!< LCD PAL219: R04_0 Mask */\r
-#define LCD_PAL219_G04_0_Pos 5 /*!< LCD PAL219: G04_0 Position */\r
-#define LCD_PAL219_G04_0_Msk (0x1fUL << LCD_PAL219_G04_0_Pos) /*!< LCD PAL219: G04_0 Mask */\r
-#define LCD_PAL219_B04_0_Pos 10 /*!< LCD PAL219: B04_0 Position */\r
-#define LCD_PAL219_B04_0_Msk (0x1fUL << LCD_PAL219_B04_0_Pos) /*!< LCD PAL219: B04_0 Mask */\r
-#define LCD_PAL219_I0_Pos 15 /*!< LCD PAL219: I0 Position */\r
-#define LCD_PAL219_I0_Msk (0x01UL << LCD_PAL219_I0_Pos) /*!< LCD PAL219: I0 Mask */\r
-#define LCD_PAL219_R14_0_Pos 16 /*!< LCD PAL219: R14_0 Position */\r
-#define LCD_PAL219_R14_0_Msk (0x1fUL << LCD_PAL219_R14_0_Pos) /*!< LCD PAL219: R14_0 Mask */\r
-#define LCD_PAL219_G14_0_Pos 21 /*!< LCD PAL219: G14_0 Position */\r
-#define LCD_PAL219_G14_0_Msk (0x1fUL << LCD_PAL219_G14_0_Pos) /*!< LCD PAL219: G14_0 Mask */\r
-#define LCD_PAL219_B14_0_Pos 26 /*!< LCD PAL219: B14_0 Position */\r
-#define LCD_PAL219_B14_0_Msk (0x1fUL << LCD_PAL219_B14_0_Pos) /*!< LCD PAL219: B14_0 Mask */\r
-#define LCD_PAL219_I1_Pos 31 /*!< LCD PAL219: I1 Position */\r
-#define LCD_PAL219_I1_Msk (0x01UL << LCD_PAL219_I1_Pos) /*!< LCD PAL219: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL220 -------------------------------------------\r
-#define LCD_PAL220_R04_0_Pos 0 /*!< LCD PAL220: R04_0 Position */\r
-#define LCD_PAL220_R04_0_Msk (0x1fUL << LCD_PAL220_R04_0_Pos) /*!< LCD PAL220: R04_0 Mask */\r
-#define LCD_PAL220_G04_0_Pos 5 /*!< LCD PAL220: G04_0 Position */\r
-#define LCD_PAL220_G04_0_Msk (0x1fUL << LCD_PAL220_G04_0_Pos) /*!< LCD PAL220: G04_0 Mask */\r
-#define LCD_PAL220_B04_0_Pos 10 /*!< LCD PAL220: B04_0 Position */\r
-#define LCD_PAL220_B04_0_Msk (0x1fUL << LCD_PAL220_B04_0_Pos) /*!< LCD PAL220: B04_0 Mask */\r
-#define LCD_PAL220_I0_Pos 15 /*!< LCD PAL220: I0 Position */\r
-#define LCD_PAL220_I0_Msk (0x01UL << LCD_PAL220_I0_Pos) /*!< LCD PAL220: I0 Mask */\r
-#define LCD_PAL220_R14_0_Pos 16 /*!< LCD PAL220: R14_0 Position */\r
-#define LCD_PAL220_R14_0_Msk (0x1fUL << LCD_PAL220_R14_0_Pos) /*!< LCD PAL220: R14_0 Mask */\r
-#define LCD_PAL220_G14_0_Pos 21 /*!< LCD PAL220: G14_0 Position */\r
-#define LCD_PAL220_G14_0_Msk (0x1fUL << LCD_PAL220_G14_0_Pos) /*!< LCD PAL220: G14_0 Mask */\r
-#define LCD_PAL220_B14_0_Pos 26 /*!< LCD PAL220: B14_0 Position */\r
-#define LCD_PAL220_B14_0_Msk (0x1fUL << LCD_PAL220_B14_0_Pos) /*!< LCD PAL220: B14_0 Mask */\r
-#define LCD_PAL220_I1_Pos 31 /*!< LCD PAL220: I1 Position */\r
-#define LCD_PAL220_I1_Msk (0x01UL << LCD_PAL220_I1_Pos) /*!< LCD PAL220: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL221 -------------------------------------------\r
-#define LCD_PAL221_R04_0_Pos 0 /*!< LCD PAL221: R04_0 Position */\r
-#define LCD_PAL221_R04_0_Msk (0x1fUL << LCD_PAL221_R04_0_Pos) /*!< LCD PAL221: R04_0 Mask */\r
-#define LCD_PAL221_G04_0_Pos 5 /*!< LCD PAL221: G04_0 Position */\r
-#define LCD_PAL221_G04_0_Msk (0x1fUL << LCD_PAL221_G04_0_Pos) /*!< LCD PAL221: G04_0 Mask */\r
-#define LCD_PAL221_B04_0_Pos 10 /*!< LCD PAL221: B04_0 Position */\r
-#define LCD_PAL221_B04_0_Msk (0x1fUL << LCD_PAL221_B04_0_Pos) /*!< LCD PAL221: B04_0 Mask */\r
-#define LCD_PAL221_I0_Pos 15 /*!< LCD PAL221: I0 Position */\r
-#define LCD_PAL221_I0_Msk (0x01UL << LCD_PAL221_I0_Pos) /*!< LCD PAL221: I0 Mask */\r
-#define LCD_PAL221_R14_0_Pos 16 /*!< LCD PAL221: R14_0 Position */\r
-#define LCD_PAL221_R14_0_Msk (0x1fUL << LCD_PAL221_R14_0_Pos) /*!< LCD PAL221: R14_0 Mask */\r
-#define LCD_PAL221_G14_0_Pos 21 /*!< LCD PAL221: G14_0 Position */\r
-#define LCD_PAL221_G14_0_Msk (0x1fUL << LCD_PAL221_G14_0_Pos) /*!< LCD PAL221: G14_0 Mask */\r
-#define LCD_PAL221_B14_0_Pos 26 /*!< LCD PAL221: B14_0 Position */\r
-#define LCD_PAL221_B14_0_Msk (0x1fUL << LCD_PAL221_B14_0_Pos) /*!< LCD PAL221: B14_0 Mask */\r
-#define LCD_PAL221_I1_Pos 31 /*!< LCD PAL221: I1 Position */\r
-#define LCD_PAL221_I1_Msk (0x01UL << LCD_PAL221_I1_Pos) /*!< LCD PAL221: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL222 -------------------------------------------\r
-#define LCD_PAL222_R04_0_Pos 0 /*!< LCD PAL222: R04_0 Position */\r
-#define LCD_PAL222_R04_0_Msk (0x1fUL << LCD_PAL222_R04_0_Pos) /*!< LCD PAL222: R04_0 Mask */\r
-#define LCD_PAL222_G04_0_Pos 5 /*!< LCD PAL222: G04_0 Position */\r
-#define LCD_PAL222_G04_0_Msk (0x1fUL << LCD_PAL222_G04_0_Pos) /*!< LCD PAL222: G04_0 Mask */\r
-#define LCD_PAL222_B04_0_Pos 10 /*!< LCD PAL222: B04_0 Position */\r
-#define LCD_PAL222_B04_0_Msk (0x1fUL << LCD_PAL222_B04_0_Pos) /*!< LCD PAL222: B04_0 Mask */\r
-#define LCD_PAL222_I0_Pos 15 /*!< LCD PAL222: I0 Position */\r
-#define LCD_PAL222_I0_Msk (0x01UL << LCD_PAL222_I0_Pos) /*!< LCD PAL222: I0 Mask */\r
-#define LCD_PAL222_R14_0_Pos 16 /*!< LCD PAL222: R14_0 Position */\r
-#define LCD_PAL222_R14_0_Msk (0x1fUL << LCD_PAL222_R14_0_Pos) /*!< LCD PAL222: R14_0 Mask */\r
-#define LCD_PAL222_G14_0_Pos 21 /*!< LCD PAL222: G14_0 Position */\r
-#define LCD_PAL222_G14_0_Msk (0x1fUL << LCD_PAL222_G14_0_Pos) /*!< LCD PAL222: G14_0 Mask */\r
-#define LCD_PAL222_B14_0_Pos 26 /*!< LCD PAL222: B14_0 Position */\r
-#define LCD_PAL222_B14_0_Msk (0x1fUL << LCD_PAL222_B14_0_Pos) /*!< LCD PAL222: B14_0 Mask */\r
-#define LCD_PAL222_I1_Pos 31 /*!< LCD PAL222: I1 Position */\r
-#define LCD_PAL222_I1_Msk (0x01UL << LCD_PAL222_I1_Pos) /*!< LCD PAL222: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL223 -------------------------------------------\r
-#define LCD_PAL223_R04_0_Pos 0 /*!< LCD PAL223: R04_0 Position */\r
-#define LCD_PAL223_R04_0_Msk (0x1fUL << LCD_PAL223_R04_0_Pos) /*!< LCD PAL223: R04_0 Mask */\r
-#define LCD_PAL223_G04_0_Pos 5 /*!< LCD PAL223: G04_0 Position */\r
-#define LCD_PAL223_G04_0_Msk (0x1fUL << LCD_PAL223_G04_0_Pos) /*!< LCD PAL223: G04_0 Mask */\r
-#define LCD_PAL223_B04_0_Pos 10 /*!< LCD PAL223: B04_0 Position */\r
-#define LCD_PAL223_B04_0_Msk (0x1fUL << LCD_PAL223_B04_0_Pos) /*!< LCD PAL223: B04_0 Mask */\r
-#define LCD_PAL223_I0_Pos 15 /*!< LCD PAL223: I0 Position */\r
-#define LCD_PAL223_I0_Msk (0x01UL << LCD_PAL223_I0_Pos) /*!< LCD PAL223: I0 Mask */\r
-#define LCD_PAL223_R14_0_Pos 16 /*!< LCD PAL223: R14_0 Position */\r
-#define LCD_PAL223_R14_0_Msk (0x1fUL << LCD_PAL223_R14_0_Pos) /*!< LCD PAL223: R14_0 Mask */\r
-#define LCD_PAL223_G14_0_Pos 21 /*!< LCD PAL223: G14_0 Position */\r
-#define LCD_PAL223_G14_0_Msk (0x1fUL << LCD_PAL223_G14_0_Pos) /*!< LCD PAL223: G14_0 Mask */\r
-#define LCD_PAL223_B14_0_Pos 26 /*!< LCD PAL223: B14_0 Position */\r
-#define LCD_PAL223_B14_0_Msk (0x1fUL << LCD_PAL223_B14_0_Pos) /*!< LCD PAL223: B14_0 Mask */\r
-#define LCD_PAL223_I1_Pos 31 /*!< LCD PAL223: I1 Position */\r
-#define LCD_PAL223_I1_Msk (0x01UL << LCD_PAL223_I1_Pos) /*!< LCD PAL223: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL224 -------------------------------------------\r
-#define LCD_PAL224_R04_0_Pos 0 /*!< LCD PAL224: R04_0 Position */\r
-#define LCD_PAL224_R04_0_Msk (0x1fUL << LCD_PAL224_R04_0_Pos) /*!< LCD PAL224: R04_0 Mask */\r
-#define LCD_PAL224_G04_0_Pos 5 /*!< LCD PAL224: G04_0 Position */\r
-#define LCD_PAL224_G04_0_Msk (0x1fUL << LCD_PAL224_G04_0_Pos) /*!< LCD PAL224: G04_0 Mask */\r
-#define LCD_PAL224_B04_0_Pos 10 /*!< LCD PAL224: B04_0 Position */\r
-#define LCD_PAL224_B04_0_Msk (0x1fUL << LCD_PAL224_B04_0_Pos) /*!< LCD PAL224: B04_0 Mask */\r
-#define LCD_PAL224_I0_Pos 15 /*!< LCD PAL224: I0 Position */\r
-#define LCD_PAL224_I0_Msk (0x01UL << LCD_PAL224_I0_Pos) /*!< LCD PAL224: I0 Mask */\r
-#define LCD_PAL224_R14_0_Pos 16 /*!< LCD PAL224: R14_0 Position */\r
-#define LCD_PAL224_R14_0_Msk (0x1fUL << LCD_PAL224_R14_0_Pos) /*!< LCD PAL224: R14_0 Mask */\r
-#define LCD_PAL224_G14_0_Pos 21 /*!< LCD PAL224: G14_0 Position */\r
-#define LCD_PAL224_G14_0_Msk (0x1fUL << LCD_PAL224_G14_0_Pos) /*!< LCD PAL224: G14_0 Mask */\r
-#define LCD_PAL224_B14_0_Pos 26 /*!< LCD PAL224: B14_0 Position */\r
-#define LCD_PAL224_B14_0_Msk (0x1fUL << LCD_PAL224_B14_0_Pos) /*!< LCD PAL224: B14_0 Mask */\r
-#define LCD_PAL224_I1_Pos 31 /*!< LCD PAL224: I1 Position */\r
-#define LCD_PAL224_I1_Msk (0x01UL << LCD_PAL224_I1_Pos) /*!< LCD PAL224: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL225 -------------------------------------------\r
-#define LCD_PAL225_R04_0_Pos 0 /*!< LCD PAL225: R04_0 Position */\r
-#define LCD_PAL225_R04_0_Msk (0x1fUL << LCD_PAL225_R04_0_Pos) /*!< LCD PAL225: R04_0 Mask */\r
-#define LCD_PAL225_G04_0_Pos 5 /*!< LCD PAL225: G04_0 Position */\r
-#define LCD_PAL225_G04_0_Msk (0x1fUL << LCD_PAL225_G04_0_Pos) /*!< LCD PAL225: G04_0 Mask */\r
-#define LCD_PAL225_B04_0_Pos 10 /*!< LCD PAL225: B04_0 Position */\r
-#define LCD_PAL225_B04_0_Msk (0x1fUL << LCD_PAL225_B04_0_Pos) /*!< LCD PAL225: B04_0 Mask */\r
-#define LCD_PAL225_I0_Pos 15 /*!< LCD PAL225: I0 Position */\r
-#define LCD_PAL225_I0_Msk (0x01UL << LCD_PAL225_I0_Pos) /*!< LCD PAL225: I0 Mask */\r
-#define LCD_PAL225_R14_0_Pos 16 /*!< LCD PAL225: R14_0 Position */\r
-#define LCD_PAL225_R14_0_Msk (0x1fUL << LCD_PAL225_R14_0_Pos) /*!< LCD PAL225: R14_0 Mask */\r
-#define LCD_PAL225_G14_0_Pos 21 /*!< LCD PAL225: G14_0 Position */\r
-#define LCD_PAL225_G14_0_Msk (0x1fUL << LCD_PAL225_G14_0_Pos) /*!< LCD PAL225: G14_0 Mask */\r
-#define LCD_PAL225_B14_0_Pos 26 /*!< LCD PAL225: B14_0 Position */\r
-#define LCD_PAL225_B14_0_Msk (0x1fUL << LCD_PAL225_B14_0_Pos) /*!< LCD PAL225: B14_0 Mask */\r
-#define LCD_PAL225_I1_Pos 31 /*!< LCD PAL225: I1 Position */\r
-#define LCD_PAL225_I1_Msk (0x01UL << LCD_PAL225_I1_Pos) /*!< LCD PAL225: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL226 -------------------------------------------\r
-#define LCD_PAL226_R04_0_Pos 0 /*!< LCD PAL226: R04_0 Position */\r
-#define LCD_PAL226_R04_0_Msk (0x1fUL << LCD_PAL226_R04_0_Pos) /*!< LCD PAL226: R04_0 Mask */\r
-#define LCD_PAL226_G04_0_Pos 5 /*!< LCD PAL226: G04_0 Position */\r
-#define LCD_PAL226_G04_0_Msk (0x1fUL << LCD_PAL226_G04_0_Pos) /*!< LCD PAL226: G04_0 Mask */\r
-#define LCD_PAL226_B04_0_Pos 10 /*!< LCD PAL226: B04_0 Position */\r
-#define LCD_PAL226_B04_0_Msk (0x1fUL << LCD_PAL226_B04_0_Pos) /*!< LCD PAL226: B04_0 Mask */\r
-#define LCD_PAL226_I0_Pos 15 /*!< LCD PAL226: I0 Position */\r
-#define LCD_PAL226_I0_Msk (0x01UL << LCD_PAL226_I0_Pos) /*!< LCD PAL226: I0 Mask */\r
-#define LCD_PAL226_R14_0_Pos 16 /*!< LCD PAL226: R14_0 Position */\r
-#define LCD_PAL226_R14_0_Msk (0x1fUL << LCD_PAL226_R14_0_Pos) /*!< LCD PAL226: R14_0 Mask */\r
-#define LCD_PAL226_G14_0_Pos 21 /*!< LCD PAL226: G14_0 Position */\r
-#define LCD_PAL226_G14_0_Msk (0x1fUL << LCD_PAL226_G14_0_Pos) /*!< LCD PAL226: G14_0 Mask */\r
-#define LCD_PAL226_B14_0_Pos 26 /*!< LCD PAL226: B14_0 Position */\r
-#define LCD_PAL226_B14_0_Msk (0x1fUL << LCD_PAL226_B14_0_Pos) /*!< LCD PAL226: B14_0 Mask */\r
-#define LCD_PAL226_I1_Pos 31 /*!< LCD PAL226: I1 Position */\r
-#define LCD_PAL226_I1_Msk (0x01UL << LCD_PAL226_I1_Pos) /*!< LCD PAL226: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL227 -------------------------------------------\r
-#define LCD_PAL227_R04_0_Pos 0 /*!< LCD PAL227: R04_0 Position */\r
-#define LCD_PAL227_R04_0_Msk (0x1fUL << LCD_PAL227_R04_0_Pos) /*!< LCD PAL227: R04_0 Mask */\r
-#define LCD_PAL227_G04_0_Pos 5 /*!< LCD PAL227: G04_0 Position */\r
-#define LCD_PAL227_G04_0_Msk (0x1fUL << LCD_PAL227_G04_0_Pos) /*!< LCD PAL227: G04_0 Mask */\r
-#define LCD_PAL227_B04_0_Pos 10 /*!< LCD PAL227: B04_0 Position */\r
-#define LCD_PAL227_B04_0_Msk (0x1fUL << LCD_PAL227_B04_0_Pos) /*!< LCD PAL227: B04_0 Mask */\r
-#define LCD_PAL227_I0_Pos 15 /*!< LCD PAL227: I0 Position */\r
-#define LCD_PAL227_I0_Msk (0x01UL << LCD_PAL227_I0_Pos) /*!< LCD PAL227: I0 Mask */\r
-#define LCD_PAL227_R14_0_Pos 16 /*!< LCD PAL227: R14_0 Position */\r
-#define LCD_PAL227_R14_0_Msk (0x1fUL << LCD_PAL227_R14_0_Pos) /*!< LCD PAL227: R14_0 Mask */\r
-#define LCD_PAL227_G14_0_Pos 21 /*!< LCD PAL227: G14_0 Position */\r
-#define LCD_PAL227_G14_0_Msk (0x1fUL << LCD_PAL227_G14_0_Pos) /*!< LCD PAL227: G14_0 Mask */\r
-#define LCD_PAL227_B14_0_Pos 26 /*!< LCD PAL227: B14_0 Position */\r
-#define LCD_PAL227_B14_0_Msk (0x1fUL << LCD_PAL227_B14_0_Pos) /*!< LCD PAL227: B14_0 Mask */\r
-#define LCD_PAL227_I1_Pos 31 /*!< LCD PAL227: I1 Position */\r
-#define LCD_PAL227_I1_Msk (0x01UL << LCD_PAL227_I1_Pos) /*!< LCD PAL227: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL228 -------------------------------------------\r
-#define LCD_PAL228_R04_0_Pos 0 /*!< LCD PAL228: R04_0 Position */\r
-#define LCD_PAL228_R04_0_Msk (0x1fUL << LCD_PAL228_R04_0_Pos) /*!< LCD PAL228: R04_0 Mask */\r
-#define LCD_PAL228_G04_0_Pos 5 /*!< LCD PAL228: G04_0 Position */\r
-#define LCD_PAL228_G04_0_Msk (0x1fUL << LCD_PAL228_G04_0_Pos) /*!< LCD PAL228: G04_0 Mask */\r
-#define LCD_PAL228_B04_0_Pos 10 /*!< LCD PAL228: B04_0 Position */\r
-#define LCD_PAL228_B04_0_Msk (0x1fUL << LCD_PAL228_B04_0_Pos) /*!< LCD PAL228: B04_0 Mask */\r
-#define LCD_PAL228_I0_Pos 15 /*!< LCD PAL228: I0 Position */\r
-#define LCD_PAL228_I0_Msk (0x01UL << LCD_PAL228_I0_Pos) /*!< LCD PAL228: I0 Mask */\r
-#define LCD_PAL228_R14_0_Pos 16 /*!< LCD PAL228: R14_0 Position */\r
-#define LCD_PAL228_R14_0_Msk (0x1fUL << LCD_PAL228_R14_0_Pos) /*!< LCD PAL228: R14_0 Mask */\r
-#define LCD_PAL228_G14_0_Pos 21 /*!< LCD PAL228: G14_0 Position */\r
-#define LCD_PAL228_G14_0_Msk (0x1fUL << LCD_PAL228_G14_0_Pos) /*!< LCD PAL228: G14_0 Mask */\r
-#define LCD_PAL228_B14_0_Pos 26 /*!< LCD PAL228: B14_0 Position */\r
-#define LCD_PAL228_B14_0_Msk (0x1fUL << LCD_PAL228_B14_0_Pos) /*!< LCD PAL228: B14_0 Mask */\r
-#define LCD_PAL228_I1_Pos 31 /*!< LCD PAL228: I1 Position */\r
-#define LCD_PAL228_I1_Msk (0x01UL << LCD_PAL228_I1_Pos) /*!< LCD PAL228: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL229 -------------------------------------------\r
-#define LCD_PAL229_R04_0_Pos 0 /*!< LCD PAL229: R04_0 Position */\r
-#define LCD_PAL229_R04_0_Msk (0x1fUL << LCD_PAL229_R04_0_Pos) /*!< LCD PAL229: R04_0 Mask */\r
-#define LCD_PAL229_G04_0_Pos 5 /*!< LCD PAL229: G04_0 Position */\r
-#define LCD_PAL229_G04_0_Msk (0x1fUL << LCD_PAL229_G04_0_Pos) /*!< LCD PAL229: G04_0 Mask */\r
-#define LCD_PAL229_B04_0_Pos 10 /*!< LCD PAL229: B04_0 Position */\r
-#define LCD_PAL229_B04_0_Msk (0x1fUL << LCD_PAL229_B04_0_Pos) /*!< LCD PAL229: B04_0 Mask */\r
-#define LCD_PAL229_I0_Pos 15 /*!< LCD PAL229: I0 Position */\r
-#define LCD_PAL229_I0_Msk (0x01UL << LCD_PAL229_I0_Pos) /*!< LCD PAL229: I0 Mask */\r
-#define LCD_PAL229_R14_0_Pos 16 /*!< LCD PAL229: R14_0 Position */\r
-#define LCD_PAL229_R14_0_Msk (0x1fUL << LCD_PAL229_R14_0_Pos) /*!< LCD PAL229: R14_0 Mask */\r
-#define LCD_PAL229_G14_0_Pos 21 /*!< LCD PAL229: G14_0 Position */\r
-#define LCD_PAL229_G14_0_Msk (0x1fUL << LCD_PAL229_G14_0_Pos) /*!< LCD PAL229: G14_0 Mask */\r
-#define LCD_PAL229_B14_0_Pos 26 /*!< LCD PAL229: B14_0 Position */\r
-#define LCD_PAL229_B14_0_Msk (0x1fUL << LCD_PAL229_B14_0_Pos) /*!< LCD PAL229: B14_0 Mask */\r
-#define LCD_PAL229_I1_Pos 31 /*!< LCD PAL229: I1 Position */\r
-#define LCD_PAL229_I1_Msk (0x01UL << LCD_PAL229_I1_Pos) /*!< LCD PAL229: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL230 -------------------------------------------\r
-#define LCD_PAL230_R04_0_Pos 0 /*!< LCD PAL230: R04_0 Position */\r
-#define LCD_PAL230_R04_0_Msk (0x1fUL << LCD_PAL230_R04_0_Pos) /*!< LCD PAL230: R04_0 Mask */\r
-#define LCD_PAL230_G04_0_Pos 5 /*!< LCD PAL230: G04_0 Position */\r
-#define LCD_PAL230_G04_0_Msk (0x1fUL << LCD_PAL230_G04_0_Pos) /*!< LCD PAL230: G04_0 Mask */\r
-#define LCD_PAL230_B04_0_Pos 10 /*!< LCD PAL230: B04_0 Position */\r
-#define LCD_PAL230_B04_0_Msk (0x1fUL << LCD_PAL230_B04_0_Pos) /*!< LCD PAL230: B04_0 Mask */\r
-#define LCD_PAL230_I0_Pos 15 /*!< LCD PAL230: I0 Position */\r
-#define LCD_PAL230_I0_Msk (0x01UL << LCD_PAL230_I0_Pos) /*!< LCD PAL230: I0 Mask */\r
-#define LCD_PAL230_R14_0_Pos 16 /*!< LCD PAL230: R14_0 Position */\r
-#define LCD_PAL230_R14_0_Msk (0x1fUL << LCD_PAL230_R14_0_Pos) /*!< LCD PAL230: R14_0 Mask */\r
-#define LCD_PAL230_G14_0_Pos 21 /*!< LCD PAL230: G14_0 Position */\r
-#define LCD_PAL230_G14_0_Msk (0x1fUL << LCD_PAL230_G14_0_Pos) /*!< LCD PAL230: G14_0 Mask */\r
-#define LCD_PAL230_B14_0_Pos 26 /*!< LCD PAL230: B14_0 Position */\r
-#define LCD_PAL230_B14_0_Msk (0x1fUL << LCD_PAL230_B14_0_Pos) /*!< LCD PAL230: B14_0 Mask */\r
-#define LCD_PAL230_I1_Pos 31 /*!< LCD PAL230: I1 Position */\r
-#define LCD_PAL230_I1_Msk (0x01UL << LCD_PAL230_I1_Pos) /*!< LCD PAL230: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL231 -------------------------------------------\r
-#define LCD_PAL231_R04_0_Pos 0 /*!< LCD PAL231: R04_0 Position */\r
-#define LCD_PAL231_R04_0_Msk (0x1fUL << LCD_PAL231_R04_0_Pos) /*!< LCD PAL231: R04_0 Mask */\r
-#define LCD_PAL231_G04_0_Pos 5 /*!< LCD PAL231: G04_0 Position */\r
-#define LCD_PAL231_G04_0_Msk (0x1fUL << LCD_PAL231_G04_0_Pos) /*!< LCD PAL231: G04_0 Mask */\r
-#define LCD_PAL231_B04_0_Pos 10 /*!< LCD PAL231: B04_0 Position */\r
-#define LCD_PAL231_B04_0_Msk (0x1fUL << LCD_PAL231_B04_0_Pos) /*!< LCD PAL231: B04_0 Mask */\r
-#define LCD_PAL231_I0_Pos 15 /*!< LCD PAL231: I0 Position */\r
-#define LCD_PAL231_I0_Msk (0x01UL << LCD_PAL231_I0_Pos) /*!< LCD PAL231: I0 Mask */\r
-#define LCD_PAL231_R14_0_Pos 16 /*!< LCD PAL231: R14_0 Position */\r
-#define LCD_PAL231_R14_0_Msk (0x1fUL << LCD_PAL231_R14_0_Pos) /*!< LCD PAL231: R14_0 Mask */\r
-#define LCD_PAL231_G14_0_Pos 21 /*!< LCD PAL231: G14_0 Position */\r
-#define LCD_PAL231_G14_0_Msk (0x1fUL << LCD_PAL231_G14_0_Pos) /*!< LCD PAL231: G14_0 Mask */\r
-#define LCD_PAL231_B14_0_Pos 26 /*!< LCD PAL231: B14_0 Position */\r
-#define LCD_PAL231_B14_0_Msk (0x1fUL << LCD_PAL231_B14_0_Pos) /*!< LCD PAL231: B14_0 Mask */\r
-#define LCD_PAL231_I1_Pos 31 /*!< LCD PAL231: I1 Position */\r
-#define LCD_PAL231_I1_Msk (0x01UL << LCD_PAL231_I1_Pos) /*!< LCD PAL231: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL232 -------------------------------------------\r
-#define LCD_PAL232_R04_0_Pos 0 /*!< LCD PAL232: R04_0 Position */\r
-#define LCD_PAL232_R04_0_Msk (0x1fUL << LCD_PAL232_R04_0_Pos) /*!< LCD PAL232: R04_0 Mask */\r
-#define LCD_PAL232_G04_0_Pos 5 /*!< LCD PAL232: G04_0 Position */\r
-#define LCD_PAL232_G04_0_Msk (0x1fUL << LCD_PAL232_G04_0_Pos) /*!< LCD PAL232: G04_0 Mask */\r
-#define LCD_PAL232_B04_0_Pos 10 /*!< LCD PAL232: B04_0 Position */\r
-#define LCD_PAL232_B04_0_Msk (0x1fUL << LCD_PAL232_B04_0_Pos) /*!< LCD PAL232: B04_0 Mask */\r
-#define LCD_PAL232_I0_Pos 15 /*!< LCD PAL232: I0 Position */\r
-#define LCD_PAL232_I0_Msk (0x01UL << LCD_PAL232_I0_Pos) /*!< LCD PAL232: I0 Mask */\r
-#define LCD_PAL232_R14_0_Pos 16 /*!< LCD PAL232: R14_0 Position */\r
-#define LCD_PAL232_R14_0_Msk (0x1fUL << LCD_PAL232_R14_0_Pos) /*!< LCD PAL232: R14_0 Mask */\r
-#define LCD_PAL232_G14_0_Pos 21 /*!< LCD PAL232: G14_0 Position */\r
-#define LCD_PAL232_G14_0_Msk (0x1fUL << LCD_PAL232_G14_0_Pos) /*!< LCD PAL232: G14_0 Mask */\r
-#define LCD_PAL232_B14_0_Pos 26 /*!< LCD PAL232: B14_0 Position */\r
-#define LCD_PAL232_B14_0_Msk (0x1fUL << LCD_PAL232_B14_0_Pos) /*!< LCD PAL232: B14_0 Mask */\r
-#define LCD_PAL232_I1_Pos 31 /*!< LCD PAL232: I1 Position */\r
-#define LCD_PAL232_I1_Msk (0x01UL << LCD_PAL232_I1_Pos) /*!< LCD PAL232: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL233 -------------------------------------------\r
-#define LCD_PAL233_R04_0_Pos 0 /*!< LCD PAL233: R04_0 Position */\r
-#define LCD_PAL233_R04_0_Msk (0x1fUL << LCD_PAL233_R04_0_Pos) /*!< LCD PAL233: R04_0 Mask */\r
-#define LCD_PAL233_G04_0_Pos 5 /*!< LCD PAL233: G04_0 Position */\r
-#define LCD_PAL233_G04_0_Msk (0x1fUL << LCD_PAL233_G04_0_Pos) /*!< LCD PAL233: G04_0 Mask */\r
-#define LCD_PAL233_B04_0_Pos 10 /*!< LCD PAL233: B04_0 Position */\r
-#define LCD_PAL233_B04_0_Msk (0x1fUL << LCD_PAL233_B04_0_Pos) /*!< LCD PAL233: B04_0 Mask */\r
-#define LCD_PAL233_I0_Pos 15 /*!< LCD PAL233: I0 Position */\r
-#define LCD_PAL233_I0_Msk (0x01UL << LCD_PAL233_I0_Pos) /*!< LCD PAL233: I0 Mask */\r
-#define LCD_PAL233_R14_0_Pos 16 /*!< LCD PAL233: R14_0 Position */\r
-#define LCD_PAL233_R14_0_Msk (0x1fUL << LCD_PAL233_R14_0_Pos) /*!< LCD PAL233: R14_0 Mask */\r
-#define LCD_PAL233_G14_0_Pos 21 /*!< LCD PAL233: G14_0 Position */\r
-#define LCD_PAL233_G14_0_Msk (0x1fUL << LCD_PAL233_G14_0_Pos) /*!< LCD PAL233: G14_0 Mask */\r
-#define LCD_PAL233_B14_0_Pos 26 /*!< LCD PAL233: B14_0 Position */\r
-#define LCD_PAL233_B14_0_Msk (0x1fUL << LCD_PAL233_B14_0_Pos) /*!< LCD PAL233: B14_0 Mask */\r
-#define LCD_PAL233_I1_Pos 31 /*!< LCD PAL233: I1 Position */\r
-#define LCD_PAL233_I1_Msk (0x01UL << LCD_PAL233_I1_Pos) /*!< LCD PAL233: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL234 -------------------------------------------\r
-#define LCD_PAL234_R04_0_Pos 0 /*!< LCD PAL234: R04_0 Position */\r
-#define LCD_PAL234_R04_0_Msk (0x1fUL << LCD_PAL234_R04_0_Pos) /*!< LCD PAL234: R04_0 Mask */\r
-#define LCD_PAL234_G04_0_Pos 5 /*!< LCD PAL234: G04_0 Position */\r
-#define LCD_PAL234_G04_0_Msk (0x1fUL << LCD_PAL234_G04_0_Pos) /*!< LCD PAL234: G04_0 Mask */\r
-#define LCD_PAL234_B04_0_Pos 10 /*!< LCD PAL234: B04_0 Position */\r
-#define LCD_PAL234_B04_0_Msk (0x1fUL << LCD_PAL234_B04_0_Pos) /*!< LCD PAL234: B04_0 Mask */\r
-#define LCD_PAL234_I0_Pos 15 /*!< LCD PAL234: I0 Position */\r
-#define LCD_PAL234_I0_Msk (0x01UL << LCD_PAL234_I0_Pos) /*!< LCD PAL234: I0 Mask */\r
-#define LCD_PAL234_R14_0_Pos 16 /*!< LCD PAL234: R14_0 Position */\r
-#define LCD_PAL234_R14_0_Msk (0x1fUL << LCD_PAL234_R14_0_Pos) /*!< LCD PAL234: R14_0 Mask */\r
-#define LCD_PAL234_G14_0_Pos 21 /*!< LCD PAL234: G14_0 Position */\r
-#define LCD_PAL234_G14_0_Msk (0x1fUL << LCD_PAL234_G14_0_Pos) /*!< LCD PAL234: G14_0 Mask */\r
-#define LCD_PAL234_B14_0_Pos 26 /*!< LCD PAL234: B14_0 Position */\r
-#define LCD_PAL234_B14_0_Msk (0x1fUL << LCD_PAL234_B14_0_Pos) /*!< LCD PAL234: B14_0 Mask */\r
-#define LCD_PAL234_I1_Pos 31 /*!< LCD PAL234: I1 Position */\r
-#define LCD_PAL234_I1_Msk (0x01UL << LCD_PAL234_I1_Pos) /*!< LCD PAL234: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL235 -------------------------------------------\r
-#define LCD_PAL235_R04_0_Pos 0 /*!< LCD PAL235: R04_0 Position */\r
-#define LCD_PAL235_R04_0_Msk (0x1fUL << LCD_PAL235_R04_0_Pos) /*!< LCD PAL235: R04_0 Mask */\r
-#define LCD_PAL235_G04_0_Pos 5 /*!< LCD PAL235: G04_0 Position */\r
-#define LCD_PAL235_G04_0_Msk (0x1fUL << LCD_PAL235_G04_0_Pos) /*!< LCD PAL235: G04_0 Mask */\r
-#define LCD_PAL235_B04_0_Pos 10 /*!< LCD PAL235: B04_0 Position */\r
-#define LCD_PAL235_B04_0_Msk (0x1fUL << LCD_PAL235_B04_0_Pos) /*!< LCD PAL235: B04_0 Mask */\r
-#define LCD_PAL235_I0_Pos 15 /*!< LCD PAL235: I0 Position */\r
-#define LCD_PAL235_I0_Msk (0x01UL << LCD_PAL235_I0_Pos) /*!< LCD PAL235: I0 Mask */\r
-#define LCD_PAL235_R14_0_Pos 16 /*!< LCD PAL235: R14_0 Position */\r
-#define LCD_PAL235_R14_0_Msk (0x1fUL << LCD_PAL235_R14_0_Pos) /*!< LCD PAL235: R14_0 Mask */\r
-#define LCD_PAL235_G14_0_Pos 21 /*!< LCD PAL235: G14_0 Position */\r
-#define LCD_PAL235_G14_0_Msk (0x1fUL << LCD_PAL235_G14_0_Pos) /*!< LCD PAL235: G14_0 Mask */\r
-#define LCD_PAL235_B14_0_Pos 26 /*!< LCD PAL235: B14_0 Position */\r
-#define LCD_PAL235_B14_0_Msk (0x1fUL << LCD_PAL235_B14_0_Pos) /*!< LCD PAL235: B14_0 Mask */\r
-#define LCD_PAL235_I1_Pos 31 /*!< LCD PAL235: I1 Position */\r
-#define LCD_PAL235_I1_Msk (0x01UL << LCD_PAL235_I1_Pos) /*!< LCD PAL235: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL236 -------------------------------------------\r
-#define LCD_PAL236_R04_0_Pos 0 /*!< LCD PAL236: R04_0 Position */\r
-#define LCD_PAL236_R04_0_Msk (0x1fUL << LCD_PAL236_R04_0_Pos) /*!< LCD PAL236: R04_0 Mask */\r
-#define LCD_PAL236_G04_0_Pos 5 /*!< LCD PAL236: G04_0 Position */\r
-#define LCD_PAL236_G04_0_Msk (0x1fUL << LCD_PAL236_G04_0_Pos) /*!< LCD PAL236: G04_0 Mask */\r
-#define LCD_PAL236_B04_0_Pos 10 /*!< LCD PAL236: B04_0 Position */\r
-#define LCD_PAL236_B04_0_Msk (0x1fUL << LCD_PAL236_B04_0_Pos) /*!< LCD PAL236: B04_0 Mask */\r
-#define LCD_PAL236_I0_Pos 15 /*!< LCD PAL236: I0 Position */\r
-#define LCD_PAL236_I0_Msk (0x01UL << LCD_PAL236_I0_Pos) /*!< LCD PAL236: I0 Mask */\r
-#define LCD_PAL236_R14_0_Pos 16 /*!< LCD PAL236: R14_0 Position */\r
-#define LCD_PAL236_R14_0_Msk (0x1fUL << LCD_PAL236_R14_0_Pos) /*!< LCD PAL236: R14_0 Mask */\r
-#define LCD_PAL236_G14_0_Pos 21 /*!< LCD PAL236: G14_0 Position */\r
-#define LCD_PAL236_G14_0_Msk (0x1fUL << LCD_PAL236_G14_0_Pos) /*!< LCD PAL236: G14_0 Mask */\r
-#define LCD_PAL236_B14_0_Pos 26 /*!< LCD PAL236: B14_0 Position */\r
-#define LCD_PAL236_B14_0_Msk (0x1fUL << LCD_PAL236_B14_0_Pos) /*!< LCD PAL236: B14_0 Mask */\r
-#define LCD_PAL236_I1_Pos 31 /*!< LCD PAL236: I1 Position */\r
-#define LCD_PAL236_I1_Msk (0x01UL << LCD_PAL236_I1_Pos) /*!< LCD PAL236: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL237 -------------------------------------------\r
-#define LCD_PAL237_R04_0_Pos 0 /*!< LCD PAL237: R04_0 Position */\r
-#define LCD_PAL237_R04_0_Msk (0x1fUL << LCD_PAL237_R04_0_Pos) /*!< LCD PAL237: R04_0 Mask */\r
-#define LCD_PAL237_G04_0_Pos 5 /*!< LCD PAL237: G04_0 Position */\r
-#define LCD_PAL237_G04_0_Msk (0x1fUL << LCD_PAL237_G04_0_Pos) /*!< LCD PAL237: G04_0 Mask */\r
-#define LCD_PAL237_B04_0_Pos 10 /*!< LCD PAL237: B04_0 Position */\r
-#define LCD_PAL237_B04_0_Msk (0x1fUL << LCD_PAL237_B04_0_Pos) /*!< LCD PAL237: B04_0 Mask */\r
-#define LCD_PAL237_I0_Pos 15 /*!< LCD PAL237: I0 Position */\r
-#define LCD_PAL237_I0_Msk (0x01UL << LCD_PAL237_I0_Pos) /*!< LCD PAL237: I0 Mask */\r
-#define LCD_PAL237_R14_0_Pos 16 /*!< LCD PAL237: R14_0 Position */\r
-#define LCD_PAL237_R14_0_Msk (0x1fUL << LCD_PAL237_R14_0_Pos) /*!< LCD PAL237: R14_0 Mask */\r
-#define LCD_PAL237_G14_0_Pos 21 /*!< LCD PAL237: G14_0 Position */\r
-#define LCD_PAL237_G14_0_Msk (0x1fUL << LCD_PAL237_G14_0_Pos) /*!< LCD PAL237: G14_0 Mask */\r
-#define LCD_PAL237_B14_0_Pos 26 /*!< LCD PAL237: B14_0 Position */\r
-#define LCD_PAL237_B14_0_Msk (0x1fUL << LCD_PAL237_B14_0_Pos) /*!< LCD PAL237: B14_0 Mask */\r
-#define LCD_PAL237_I1_Pos 31 /*!< LCD PAL237: I1 Position */\r
-#define LCD_PAL237_I1_Msk (0x01UL << LCD_PAL237_I1_Pos) /*!< LCD PAL237: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL238 -------------------------------------------\r
-#define LCD_PAL238_R04_0_Pos 0 /*!< LCD PAL238: R04_0 Position */\r
-#define LCD_PAL238_R04_0_Msk (0x1fUL << LCD_PAL238_R04_0_Pos) /*!< LCD PAL238: R04_0 Mask */\r
-#define LCD_PAL238_G04_0_Pos 5 /*!< LCD PAL238: G04_0 Position */\r
-#define LCD_PAL238_G04_0_Msk (0x1fUL << LCD_PAL238_G04_0_Pos) /*!< LCD PAL238: G04_0 Mask */\r
-#define LCD_PAL238_B04_0_Pos 10 /*!< LCD PAL238: B04_0 Position */\r
-#define LCD_PAL238_B04_0_Msk (0x1fUL << LCD_PAL238_B04_0_Pos) /*!< LCD PAL238: B04_0 Mask */\r
-#define LCD_PAL238_I0_Pos 15 /*!< LCD PAL238: I0 Position */\r
-#define LCD_PAL238_I0_Msk (0x01UL << LCD_PAL238_I0_Pos) /*!< LCD PAL238: I0 Mask */\r
-#define LCD_PAL238_R14_0_Pos 16 /*!< LCD PAL238: R14_0 Position */\r
-#define LCD_PAL238_R14_0_Msk (0x1fUL << LCD_PAL238_R14_0_Pos) /*!< LCD PAL238: R14_0 Mask */\r
-#define LCD_PAL238_G14_0_Pos 21 /*!< LCD PAL238: G14_0 Position */\r
-#define LCD_PAL238_G14_0_Msk (0x1fUL << LCD_PAL238_G14_0_Pos) /*!< LCD PAL238: G14_0 Mask */\r
-#define LCD_PAL238_B14_0_Pos 26 /*!< LCD PAL238: B14_0 Position */\r
-#define LCD_PAL238_B14_0_Msk (0x1fUL << LCD_PAL238_B14_0_Pos) /*!< LCD PAL238: B14_0 Mask */\r
-#define LCD_PAL238_I1_Pos 31 /*!< LCD PAL238: I1 Position */\r
-#define LCD_PAL238_I1_Msk (0x01UL << LCD_PAL238_I1_Pos) /*!< LCD PAL238: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL239 -------------------------------------------\r
-#define LCD_PAL239_R04_0_Pos 0 /*!< LCD PAL239: R04_0 Position */\r
-#define LCD_PAL239_R04_0_Msk (0x1fUL << LCD_PAL239_R04_0_Pos) /*!< LCD PAL239: R04_0 Mask */\r
-#define LCD_PAL239_G04_0_Pos 5 /*!< LCD PAL239: G04_0 Position */\r
-#define LCD_PAL239_G04_0_Msk (0x1fUL << LCD_PAL239_G04_0_Pos) /*!< LCD PAL239: G04_0 Mask */\r
-#define LCD_PAL239_B04_0_Pos 10 /*!< LCD PAL239: B04_0 Position */\r
-#define LCD_PAL239_B04_0_Msk (0x1fUL << LCD_PAL239_B04_0_Pos) /*!< LCD PAL239: B04_0 Mask */\r
-#define LCD_PAL239_I0_Pos 15 /*!< LCD PAL239: I0 Position */\r
-#define LCD_PAL239_I0_Msk (0x01UL << LCD_PAL239_I0_Pos) /*!< LCD PAL239: I0 Mask */\r
-#define LCD_PAL239_R14_0_Pos 16 /*!< LCD PAL239: R14_0 Position */\r
-#define LCD_PAL239_R14_0_Msk (0x1fUL << LCD_PAL239_R14_0_Pos) /*!< LCD PAL239: R14_0 Mask */\r
-#define LCD_PAL239_G14_0_Pos 21 /*!< LCD PAL239: G14_0 Position */\r
-#define LCD_PAL239_G14_0_Msk (0x1fUL << LCD_PAL239_G14_0_Pos) /*!< LCD PAL239: G14_0 Mask */\r
-#define LCD_PAL239_B14_0_Pos 26 /*!< LCD PAL239: B14_0 Position */\r
-#define LCD_PAL239_B14_0_Msk (0x1fUL << LCD_PAL239_B14_0_Pos) /*!< LCD PAL239: B14_0 Mask */\r
-#define LCD_PAL239_I1_Pos 31 /*!< LCD PAL239: I1 Position */\r
-#define LCD_PAL239_I1_Msk (0x01UL << LCD_PAL239_I1_Pos) /*!< LCD PAL239: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL240 -------------------------------------------\r
-#define LCD_PAL240_R04_0_Pos 0 /*!< LCD PAL240: R04_0 Position */\r
-#define LCD_PAL240_R04_0_Msk (0x1fUL << LCD_PAL240_R04_0_Pos) /*!< LCD PAL240: R04_0 Mask */\r
-#define LCD_PAL240_G04_0_Pos 5 /*!< LCD PAL240: G04_0 Position */\r
-#define LCD_PAL240_G04_0_Msk (0x1fUL << LCD_PAL240_G04_0_Pos) /*!< LCD PAL240: G04_0 Mask */\r
-#define LCD_PAL240_B04_0_Pos 10 /*!< LCD PAL240: B04_0 Position */\r
-#define LCD_PAL240_B04_0_Msk (0x1fUL << LCD_PAL240_B04_0_Pos) /*!< LCD PAL240: B04_0 Mask */\r
-#define LCD_PAL240_I0_Pos 15 /*!< LCD PAL240: I0 Position */\r
-#define LCD_PAL240_I0_Msk (0x01UL << LCD_PAL240_I0_Pos) /*!< LCD PAL240: I0 Mask */\r
-#define LCD_PAL240_R14_0_Pos 16 /*!< LCD PAL240: R14_0 Position */\r
-#define LCD_PAL240_R14_0_Msk (0x1fUL << LCD_PAL240_R14_0_Pos) /*!< LCD PAL240: R14_0 Mask */\r
-#define LCD_PAL240_G14_0_Pos 21 /*!< LCD PAL240: G14_0 Position */\r
-#define LCD_PAL240_G14_0_Msk (0x1fUL << LCD_PAL240_G14_0_Pos) /*!< LCD PAL240: G14_0 Mask */\r
-#define LCD_PAL240_B14_0_Pos 26 /*!< LCD PAL240: B14_0 Position */\r
-#define LCD_PAL240_B14_0_Msk (0x1fUL << LCD_PAL240_B14_0_Pos) /*!< LCD PAL240: B14_0 Mask */\r
-#define LCD_PAL240_I1_Pos 31 /*!< LCD PAL240: I1 Position */\r
-#define LCD_PAL240_I1_Msk (0x01UL << LCD_PAL240_I1_Pos) /*!< LCD PAL240: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL241 -------------------------------------------\r
-#define LCD_PAL241_R04_0_Pos 0 /*!< LCD PAL241: R04_0 Position */\r
-#define LCD_PAL241_R04_0_Msk (0x1fUL << LCD_PAL241_R04_0_Pos) /*!< LCD PAL241: R04_0 Mask */\r
-#define LCD_PAL241_G04_0_Pos 5 /*!< LCD PAL241: G04_0 Position */\r
-#define LCD_PAL241_G04_0_Msk (0x1fUL << LCD_PAL241_G04_0_Pos) /*!< LCD PAL241: G04_0 Mask */\r
-#define LCD_PAL241_B04_0_Pos 10 /*!< LCD PAL241: B04_0 Position */\r
-#define LCD_PAL241_B04_0_Msk (0x1fUL << LCD_PAL241_B04_0_Pos) /*!< LCD PAL241: B04_0 Mask */\r
-#define LCD_PAL241_I0_Pos 15 /*!< LCD PAL241: I0 Position */\r
-#define LCD_PAL241_I0_Msk (0x01UL << LCD_PAL241_I0_Pos) /*!< LCD PAL241: I0 Mask */\r
-#define LCD_PAL241_R14_0_Pos 16 /*!< LCD PAL241: R14_0 Position */\r
-#define LCD_PAL241_R14_0_Msk (0x1fUL << LCD_PAL241_R14_0_Pos) /*!< LCD PAL241: R14_0 Mask */\r
-#define LCD_PAL241_G14_0_Pos 21 /*!< LCD PAL241: G14_0 Position */\r
-#define LCD_PAL241_G14_0_Msk (0x1fUL << LCD_PAL241_G14_0_Pos) /*!< LCD PAL241: G14_0 Mask */\r
-#define LCD_PAL241_B14_0_Pos 26 /*!< LCD PAL241: B14_0 Position */\r
-#define LCD_PAL241_B14_0_Msk (0x1fUL << LCD_PAL241_B14_0_Pos) /*!< LCD PAL241: B14_0 Mask */\r
-#define LCD_PAL241_I1_Pos 31 /*!< LCD PAL241: I1 Position */\r
-#define LCD_PAL241_I1_Msk (0x01UL << LCD_PAL241_I1_Pos) /*!< LCD PAL241: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL242 -------------------------------------------\r
-#define LCD_PAL242_R04_0_Pos 0 /*!< LCD PAL242: R04_0 Position */\r
-#define LCD_PAL242_R04_0_Msk (0x1fUL << LCD_PAL242_R04_0_Pos) /*!< LCD PAL242: R04_0 Mask */\r
-#define LCD_PAL242_G04_0_Pos 5 /*!< LCD PAL242: G04_0 Position */\r
-#define LCD_PAL242_G04_0_Msk (0x1fUL << LCD_PAL242_G04_0_Pos) /*!< LCD PAL242: G04_0 Mask */\r
-#define LCD_PAL242_B04_0_Pos 10 /*!< LCD PAL242: B04_0 Position */\r
-#define LCD_PAL242_B04_0_Msk (0x1fUL << LCD_PAL242_B04_0_Pos) /*!< LCD PAL242: B04_0 Mask */\r
-#define LCD_PAL242_I0_Pos 15 /*!< LCD PAL242: I0 Position */\r
-#define LCD_PAL242_I0_Msk (0x01UL << LCD_PAL242_I0_Pos) /*!< LCD PAL242: I0 Mask */\r
-#define LCD_PAL242_R14_0_Pos 16 /*!< LCD PAL242: R14_0 Position */\r
-#define LCD_PAL242_R14_0_Msk (0x1fUL << LCD_PAL242_R14_0_Pos) /*!< LCD PAL242: R14_0 Mask */\r
-#define LCD_PAL242_G14_0_Pos 21 /*!< LCD PAL242: G14_0 Position */\r
-#define LCD_PAL242_G14_0_Msk (0x1fUL << LCD_PAL242_G14_0_Pos) /*!< LCD PAL242: G14_0 Mask */\r
-#define LCD_PAL242_B14_0_Pos 26 /*!< LCD PAL242: B14_0 Position */\r
-#define LCD_PAL242_B14_0_Msk (0x1fUL << LCD_PAL242_B14_0_Pos) /*!< LCD PAL242: B14_0 Mask */\r
-#define LCD_PAL242_I1_Pos 31 /*!< LCD PAL242: I1 Position */\r
-#define LCD_PAL242_I1_Msk (0x01UL << LCD_PAL242_I1_Pos) /*!< LCD PAL242: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL243 -------------------------------------------\r
-#define LCD_PAL243_R04_0_Pos 0 /*!< LCD PAL243: R04_0 Position */\r
-#define LCD_PAL243_R04_0_Msk (0x1fUL << LCD_PAL243_R04_0_Pos) /*!< LCD PAL243: R04_0 Mask */\r
-#define LCD_PAL243_G04_0_Pos 5 /*!< LCD PAL243: G04_0 Position */\r
-#define LCD_PAL243_G04_0_Msk (0x1fUL << LCD_PAL243_G04_0_Pos) /*!< LCD PAL243: G04_0 Mask */\r
-#define LCD_PAL243_B04_0_Pos 10 /*!< LCD PAL243: B04_0 Position */\r
-#define LCD_PAL243_B04_0_Msk (0x1fUL << LCD_PAL243_B04_0_Pos) /*!< LCD PAL243: B04_0 Mask */\r
-#define LCD_PAL243_I0_Pos 15 /*!< LCD PAL243: I0 Position */\r
-#define LCD_PAL243_I0_Msk (0x01UL << LCD_PAL243_I0_Pos) /*!< LCD PAL243: I0 Mask */\r
-#define LCD_PAL243_R14_0_Pos 16 /*!< LCD PAL243: R14_0 Position */\r
-#define LCD_PAL243_R14_0_Msk (0x1fUL << LCD_PAL243_R14_0_Pos) /*!< LCD PAL243: R14_0 Mask */\r
-#define LCD_PAL243_G14_0_Pos 21 /*!< LCD PAL243: G14_0 Position */\r
-#define LCD_PAL243_G14_0_Msk (0x1fUL << LCD_PAL243_G14_0_Pos) /*!< LCD PAL243: G14_0 Mask */\r
-#define LCD_PAL243_B14_0_Pos 26 /*!< LCD PAL243: B14_0 Position */\r
-#define LCD_PAL243_B14_0_Msk (0x1fUL << LCD_PAL243_B14_0_Pos) /*!< LCD PAL243: B14_0 Mask */\r
-#define LCD_PAL243_I1_Pos 31 /*!< LCD PAL243: I1 Position */\r
-#define LCD_PAL243_I1_Msk (0x01UL << LCD_PAL243_I1_Pos) /*!< LCD PAL243: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL244 -------------------------------------------\r
-#define LCD_PAL244_R04_0_Pos 0 /*!< LCD PAL244: R04_0 Position */\r
-#define LCD_PAL244_R04_0_Msk (0x1fUL << LCD_PAL244_R04_0_Pos) /*!< LCD PAL244: R04_0 Mask */\r
-#define LCD_PAL244_G04_0_Pos 5 /*!< LCD PAL244: G04_0 Position */\r
-#define LCD_PAL244_G04_0_Msk (0x1fUL << LCD_PAL244_G04_0_Pos) /*!< LCD PAL244: G04_0 Mask */\r
-#define LCD_PAL244_B04_0_Pos 10 /*!< LCD PAL244: B04_0 Position */\r
-#define LCD_PAL244_B04_0_Msk (0x1fUL << LCD_PAL244_B04_0_Pos) /*!< LCD PAL244: B04_0 Mask */\r
-#define LCD_PAL244_I0_Pos 15 /*!< LCD PAL244: I0 Position */\r
-#define LCD_PAL244_I0_Msk (0x01UL << LCD_PAL244_I0_Pos) /*!< LCD PAL244: I0 Mask */\r
-#define LCD_PAL244_R14_0_Pos 16 /*!< LCD PAL244: R14_0 Position */\r
-#define LCD_PAL244_R14_0_Msk (0x1fUL << LCD_PAL244_R14_0_Pos) /*!< LCD PAL244: R14_0 Mask */\r
-#define LCD_PAL244_G14_0_Pos 21 /*!< LCD PAL244: G14_0 Position */\r
-#define LCD_PAL244_G14_0_Msk (0x1fUL << LCD_PAL244_G14_0_Pos) /*!< LCD PAL244: G14_0 Mask */\r
-#define LCD_PAL244_B14_0_Pos 26 /*!< LCD PAL244: B14_0 Position */\r
-#define LCD_PAL244_B14_0_Msk (0x1fUL << LCD_PAL244_B14_0_Pos) /*!< LCD PAL244: B14_0 Mask */\r
-#define LCD_PAL244_I1_Pos 31 /*!< LCD PAL244: I1 Position */\r
-#define LCD_PAL244_I1_Msk (0x01UL << LCD_PAL244_I1_Pos) /*!< LCD PAL244: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL245 -------------------------------------------\r
-#define LCD_PAL245_R04_0_Pos 0 /*!< LCD PAL245: R04_0 Position */\r
-#define LCD_PAL245_R04_0_Msk (0x1fUL << LCD_PAL245_R04_0_Pos) /*!< LCD PAL245: R04_0 Mask */\r
-#define LCD_PAL245_G04_0_Pos 5 /*!< LCD PAL245: G04_0 Position */\r
-#define LCD_PAL245_G04_0_Msk (0x1fUL << LCD_PAL245_G04_0_Pos) /*!< LCD PAL245: G04_0 Mask */\r
-#define LCD_PAL245_B04_0_Pos 10 /*!< LCD PAL245: B04_0 Position */\r
-#define LCD_PAL245_B04_0_Msk (0x1fUL << LCD_PAL245_B04_0_Pos) /*!< LCD PAL245: B04_0 Mask */\r
-#define LCD_PAL245_I0_Pos 15 /*!< LCD PAL245: I0 Position */\r
-#define LCD_PAL245_I0_Msk (0x01UL << LCD_PAL245_I0_Pos) /*!< LCD PAL245: I0 Mask */\r
-#define LCD_PAL245_R14_0_Pos 16 /*!< LCD PAL245: R14_0 Position */\r
-#define LCD_PAL245_R14_0_Msk (0x1fUL << LCD_PAL245_R14_0_Pos) /*!< LCD PAL245: R14_0 Mask */\r
-#define LCD_PAL245_G14_0_Pos 21 /*!< LCD PAL245: G14_0 Position */\r
-#define LCD_PAL245_G14_0_Msk (0x1fUL << LCD_PAL245_G14_0_Pos) /*!< LCD PAL245: G14_0 Mask */\r
-#define LCD_PAL245_B14_0_Pos 26 /*!< LCD PAL245: B14_0 Position */\r
-#define LCD_PAL245_B14_0_Msk (0x1fUL << LCD_PAL245_B14_0_Pos) /*!< LCD PAL245: B14_0 Mask */\r
-#define LCD_PAL245_I1_Pos 31 /*!< LCD PAL245: I1 Position */\r
-#define LCD_PAL245_I1_Msk (0x01UL << LCD_PAL245_I1_Pos) /*!< LCD PAL245: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL246 -------------------------------------------\r
-#define LCD_PAL246_R04_0_Pos 0 /*!< LCD PAL246: R04_0 Position */\r
-#define LCD_PAL246_R04_0_Msk (0x1fUL << LCD_PAL246_R04_0_Pos) /*!< LCD PAL246: R04_0 Mask */\r
-#define LCD_PAL246_G04_0_Pos 5 /*!< LCD PAL246: G04_0 Position */\r
-#define LCD_PAL246_G04_0_Msk (0x1fUL << LCD_PAL246_G04_0_Pos) /*!< LCD PAL246: G04_0 Mask */\r
-#define LCD_PAL246_B04_0_Pos 10 /*!< LCD PAL246: B04_0 Position */\r
-#define LCD_PAL246_B04_0_Msk (0x1fUL << LCD_PAL246_B04_0_Pos) /*!< LCD PAL246: B04_0 Mask */\r
-#define LCD_PAL246_I0_Pos 15 /*!< LCD PAL246: I0 Position */\r
-#define LCD_PAL246_I0_Msk (0x01UL << LCD_PAL246_I0_Pos) /*!< LCD PAL246: I0 Mask */\r
-#define LCD_PAL246_R14_0_Pos 16 /*!< LCD PAL246: R14_0 Position */\r
-#define LCD_PAL246_R14_0_Msk (0x1fUL << LCD_PAL246_R14_0_Pos) /*!< LCD PAL246: R14_0 Mask */\r
-#define LCD_PAL246_G14_0_Pos 21 /*!< LCD PAL246: G14_0 Position */\r
-#define LCD_PAL246_G14_0_Msk (0x1fUL << LCD_PAL246_G14_0_Pos) /*!< LCD PAL246: G14_0 Mask */\r
-#define LCD_PAL246_B14_0_Pos 26 /*!< LCD PAL246: B14_0 Position */\r
-#define LCD_PAL246_B14_0_Msk (0x1fUL << LCD_PAL246_B14_0_Pos) /*!< LCD PAL246: B14_0 Mask */\r
-#define LCD_PAL246_I1_Pos 31 /*!< LCD PAL246: I1 Position */\r
-#define LCD_PAL246_I1_Msk (0x01UL << LCD_PAL246_I1_Pos) /*!< LCD PAL246: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL247 -------------------------------------------\r
-#define LCD_PAL247_R04_0_Pos 0 /*!< LCD PAL247: R04_0 Position */\r
-#define LCD_PAL247_R04_0_Msk (0x1fUL << LCD_PAL247_R04_0_Pos) /*!< LCD PAL247: R04_0 Mask */\r
-#define LCD_PAL247_G04_0_Pos 5 /*!< LCD PAL247: G04_0 Position */\r
-#define LCD_PAL247_G04_0_Msk (0x1fUL << LCD_PAL247_G04_0_Pos) /*!< LCD PAL247: G04_0 Mask */\r
-#define LCD_PAL247_B04_0_Pos 10 /*!< LCD PAL247: B04_0 Position */\r
-#define LCD_PAL247_B04_0_Msk (0x1fUL << LCD_PAL247_B04_0_Pos) /*!< LCD PAL247: B04_0 Mask */\r
-#define LCD_PAL247_I0_Pos 15 /*!< LCD PAL247: I0 Position */\r
-#define LCD_PAL247_I0_Msk (0x01UL << LCD_PAL247_I0_Pos) /*!< LCD PAL247: I0 Mask */\r
-#define LCD_PAL247_R14_0_Pos 16 /*!< LCD PAL247: R14_0 Position */\r
-#define LCD_PAL247_R14_0_Msk (0x1fUL << LCD_PAL247_R14_0_Pos) /*!< LCD PAL247: R14_0 Mask */\r
-#define LCD_PAL247_G14_0_Pos 21 /*!< LCD PAL247: G14_0 Position */\r
-#define LCD_PAL247_G14_0_Msk (0x1fUL << LCD_PAL247_G14_0_Pos) /*!< LCD PAL247: G14_0 Mask */\r
-#define LCD_PAL247_B14_0_Pos 26 /*!< LCD PAL247: B14_0 Position */\r
-#define LCD_PAL247_B14_0_Msk (0x1fUL << LCD_PAL247_B14_0_Pos) /*!< LCD PAL247: B14_0 Mask */\r
-#define LCD_PAL247_I1_Pos 31 /*!< LCD PAL247: I1 Position */\r
-#define LCD_PAL247_I1_Msk (0x01UL << LCD_PAL247_I1_Pos) /*!< LCD PAL247: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL248 -------------------------------------------\r
-#define LCD_PAL248_R04_0_Pos 0 /*!< LCD PAL248: R04_0 Position */\r
-#define LCD_PAL248_R04_0_Msk (0x1fUL << LCD_PAL248_R04_0_Pos) /*!< LCD PAL248: R04_0 Mask */\r
-#define LCD_PAL248_G04_0_Pos 5 /*!< LCD PAL248: G04_0 Position */\r
-#define LCD_PAL248_G04_0_Msk (0x1fUL << LCD_PAL248_G04_0_Pos) /*!< LCD PAL248: G04_0 Mask */\r
-#define LCD_PAL248_B04_0_Pos 10 /*!< LCD PAL248: B04_0 Position */\r
-#define LCD_PAL248_B04_0_Msk (0x1fUL << LCD_PAL248_B04_0_Pos) /*!< LCD PAL248: B04_0 Mask */\r
-#define LCD_PAL248_I0_Pos 15 /*!< LCD PAL248: I0 Position */\r
-#define LCD_PAL248_I0_Msk (0x01UL << LCD_PAL248_I0_Pos) /*!< LCD PAL248: I0 Mask */\r
-#define LCD_PAL248_R14_0_Pos 16 /*!< LCD PAL248: R14_0 Position */\r
-#define LCD_PAL248_R14_0_Msk (0x1fUL << LCD_PAL248_R14_0_Pos) /*!< LCD PAL248: R14_0 Mask */\r
-#define LCD_PAL248_G14_0_Pos 21 /*!< LCD PAL248: G14_0 Position */\r
-#define LCD_PAL248_G14_0_Msk (0x1fUL << LCD_PAL248_G14_0_Pos) /*!< LCD PAL248: G14_0 Mask */\r
-#define LCD_PAL248_B14_0_Pos 26 /*!< LCD PAL248: B14_0 Position */\r
-#define LCD_PAL248_B14_0_Msk (0x1fUL << LCD_PAL248_B14_0_Pos) /*!< LCD PAL248: B14_0 Mask */\r
-#define LCD_PAL248_I1_Pos 31 /*!< LCD PAL248: I1 Position */\r
-#define LCD_PAL248_I1_Msk (0x01UL << LCD_PAL248_I1_Pos) /*!< LCD PAL248: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL249 -------------------------------------------\r
-#define LCD_PAL249_R04_0_Pos 0 /*!< LCD PAL249: R04_0 Position */\r
-#define LCD_PAL249_R04_0_Msk (0x1fUL << LCD_PAL249_R04_0_Pos) /*!< LCD PAL249: R04_0 Mask */\r
-#define LCD_PAL249_G04_0_Pos 5 /*!< LCD PAL249: G04_0 Position */\r
-#define LCD_PAL249_G04_0_Msk (0x1fUL << LCD_PAL249_G04_0_Pos) /*!< LCD PAL249: G04_0 Mask */\r
-#define LCD_PAL249_B04_0_Pos 10 /*!< LCD PAL249: B04_0 Position */\r
-#define LCD_PAL249_B04_0_Msk (0x1fUL << LCD_PAL249_B04_0_Pos) /*!< LCD PAL249: B04_0 Mask */\r
-#define LCD_PAL249_I0_Pos 15 /*!< LCD PAL249: I0 Position */\r
-#define LCD_PAL249_I0_Msk (0x01UL << LCD_PAL249_I0_Pos) /*!< LCD PAL249: I0 Mask */\r
-#define LCD_PAL249_R14_0_Pos 16 /*!< LCD PAL249: R14_0 Position */\r
-#define LCD_PAL249_R14_0_Msk (0x1fUL << LCD_PAL249_R14_0_Pos) /*!< LCD PAL249: R14_0 Mask */\r
-#define LCD_PAL249_G14_0_Pos 21 /*!< LCD PAL249: G14_0 Position */\r
-#define LCD_PAL249_G14_0_Msk (0x1fUL << LCD_PAL249_G14_0_Pos) /*!< LCD PAL249: G14_0 Mask */\r
-#define LCD_PAL249_B14_0_Pos 26 /*!< LCD PAL249: B14_0 Position */\r
-#define LCD_PAL249_B14_0_Msk (0x1fUL << LCD_PAL249_B14_0_Pos) /*!< LCD PAL249: B14_0 Mask */\r
-#define LCD_PAL249_I1_Pos 31 /*!< LCD PAL249: I1 Position */\r
-#define LCD_PAL249_I1_Msk (0x01UL << LCD_PAL249_I1_Pos) /*!< LCD PAL249: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL250 -------------------------------------------\r
-#define LCD_PAL250_R04_0_Pos 0 /*!< LCD PAL250: R04_0 Position */\r
-#define LCD_PAL250_R04_0_Msk (0x1fUL << LCD_PAL250_R04_0_Pos) /*!< LCD PAL250: R04_0 Mask */\r
-#define LCD_PAL250_G04_0_Pos 5 /*!< LCD PAL250: G04_0 Position */\r
-#define LCD_PAL250_G04_0_Msk (0x1fUL << LCD_PAL250_G04_0_Pos) /*!< LCD PAL250: G04_0 Mask */\r
-#define LCD_PAL250_B04_0_Pos 10 /*!< LCD PAL250: B04_0 Position */\r
-#define LCD_PAL250_B04_0_Msk (0x1fUL << LCD_PAL250_B04_0_Pos) /*!< LCD PAL250: B04_0 Mask */\r
-#define LCD_PAL250_I0_Pos 15 /*!< LCD PAL250: I0 Position */\r
-#define LCD_PAL250_I0_Msk (0x01UL << LCD_PAL250_I0_Pos) /*!< LCD PAL250: I0 Mask */\r
-#define LCD_PAL250_R14_0_Pos 16 /*!< LCD PAL250: R14_0 Position */\r
-#define LCD_PAL250_R14_0_Msk (0x1fUL << LCD_PAL250_R14_0_Pos) /*!< LCD PAL250: R14_0 Mask */\r
-#define LCD_PAL250_G14_0_Pos 21 /*!< LCD PAL250: G14_0 Position */\r
-#define LCD_PAL250_G14_0_Msk (0x1fUL << LCD_PAL250_G14_0_Pos) /*!< LCD PAL250: G14_0 Mask */\r
-#define LCD_PAL250_B14_0_Pos 26 /*!< LCD PAL250: B14_0 Position */\r
-#define LCD_PAL250_B14_0_Msk (0x1fUL << LCD_PAL250_B14_0_Pos) /*!< LCD PAL250: B14_0 Mask */\r
-#define LCD_PAL250_I1_Pos 31 /*!< LCD PAL250: I1 Position */\r
-#define LCD_PAL250_I1_Msk (0x01UL << LCD_PAL250_I1_Pos) /*!< LCD PAL250: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL251 -------------------------------------------\r
-#define LCD_PAL251_R04_0_Pos 0 /*!< LCD PAL251: R04_0 Position */\r
-#define LCD_PAL251_R04_0_Msk (0x1fUL << LCD_PAL251_R04_0_Pos) /*!< LCD PAL251: R04_0 Mask */\r
-#define LCD_PAL251_G04_0_Pos 5 /*!< LCD PAL251: G04_0 Position */\r
-#define LCD_PAL251_G04_0_Msk (0x1fUL << LCD_PAL251_G04_0_Pos) /*!< LCD PAL251: G04_0 Mask */\r
-#define LCD_PAL251_B04_0_Pos 10 /*!< LCD PAL251: B04_0 Position */\r
-#define LCD_PAL251_B04_0_Msk (0x1fUL << LCD_PAL251_B04_0_Pos) /*!< LCD PAL251: B04_0 Mask */\r
-#define LCD_PAL251_I0_Pos 15 /*!< LCD PAL251: I0 Position */\r
-#define LCD_PAL251_I0_Msk (0x01UL << LCD_PAL251_I0_Pos) /*!< LCD PAL251: I0 Mask */\r
-#define LCD_PAL251_R14_0_Pos 16 /*!< LCD PAL251: R14_0 Position */\r
-#define LCD_PAL251_R14_0_Msk (0x1fUL << LCD_PAL251_R14_0_Pos) /*!< LCD PAL251: R14_0 Mask */\r
-#define LCD_PAL251_G14_0_Pos 21 /*!< LCD PAL251: G14_0 Position */\r
-#define LCD_PAL251_G14_0_Msk (0x1fUL << LCD_PAL251_G14_0_Pos) /*!< LCD PAL251: G14_0 Mask */\r
-#define LCD_PAL251_B14_0_Pos 26 /*!< LCD PAL251: B14_0 Position */\r
-#define LCD_PAL251_B14_0_Msk (0x1fUL << LCD_PAL251_B14_0_Pos) /*!< LCD PAL251: B14_0 Mask */\r
-#define LCD_PAL251_I1_Pos 31 /*!< LCD PAL251: I1 Position */\r
-#define LCD_PAL251_I1_Msk (0x01UL << LCD_PAL251_I1_Pos) /*!< LCD PAL251: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL252 -------------------------------------------\r
-#define LCD_PAL252_R04_0_Pos 0 /*!< LCD PAL252: R04_0 Position */\r
-#define LCD_PAL252_R04_0_Msk (0x1fUL << LCD_PAL252_R04_0_Pos) /*!< LCD PAL252: R04_0 Mask */\r
-#define LCD_PAL252_G04_0_Pos 5 /*!< LCD PAL252: G04_0 Position */\r
-#define LCD_PAL252_G04_0_Msk (0x1fUL << LCD_PAL252_G04_0_Pos) /*!< LCD PAL252: G04_0 Mask */\r
-#define LCD_PAL252_B04_0_Pos 10 /*!< LCD PAL252: B04_0 Position */\r
-#define LCD_PAL252_B04_0_Msk (0x1fUL << LCD_PAL252_B04_0_Pos) /*!< LCD PAL252: B04_0 Mask */\r
-#define LCD_PAL252_I0_Pos 15 /*!< LCD PAL252: I0 Position */\r
-#define LCD_PAL252_I0_Msk (0x01UL << LCD_PAL252_I0_Pos) /*!< LCD PAL252: I0 Mask */\r
-#define LCD_PAL252_R14_0_Pos 16 /*!< LCD PAL252: R14_0 Position */\r
-#define LCD_PAL252_R14_0_Msk (0x1fUL << LCD_PAL252_R14_0_Pos) /*!< LCD PAL252: R14_0 Mask */\r
-#define LCD_PAL252_G14_0_Pos 21 /*!< LCD PAL252: G14_0 Position */\r
-#define LCD_PAL252_G14_0_Msk (0x1fUL << LCD_PAL252_G14_0_Pos) /*!< LCD PAL252: G14_0 Mask */\r
-#define LCD_PAL252_B14_0_Pos 26 /*!< LCD PAL252: B14_0 Position */\r
-#define LCD_PAL252_B14_0_Msk (0x1fUL << LCD_PAL252_B14_0_Pos) /*!< LCD PAL252: B14_0 Mask */\r
-#define LCD_PAL252_I1_Pos 31 /*!< LCD PAL252: I1 Position */\r
-#define LCD_PAL252_I1_Msk (0x01UL << LCD_PAL252_I1_Pos) /*!< LCD PAL252: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL253 -------------------------------------------\r
-#define LCD_PAL253_R04_0_Pos 0 /*!< LCD PAL253: R04_0 Position */\r
-#define LCD_PAL253_R04_0_Msk (0x1fUL << LCD_PAL253_R04_0_Pos) /*!< LCD PAL253: R04_0 Mask */\r
-#define LCD_PAL253_G04_0_Pos 5 /*!< LCD PAL253: G04_0 Position */\r
-#define LCD_PAL253_G04_0_Msk (0x1fUL << LCD_PAL253_G04_0_Pos) /*!< LCD PAL253: G04_0 Mask */\r
-#define LCD_PAL253_B04_0_Pos 10 /*!< LCD PAL253: B04_0 Position */\r
-#define LCD_PAL253_B04_0_Msk (0x1fUL << LCD_PAL253_B04_0_Pos) /*!< LCD PAL253: B04_0 Mask */\r
-#define LCD_PAL253_I0_Pos 15 /*!< LCD PAL253: I0 Position */\r
-#define LCD_PAL253_I0_Msk (0x01UL << LCD_PAL253_I0_Pos) /*!< LCD PAL253: I0 Mask */\r
-#define LCD_PAL253_R14_0_Pos 16 /*!< LCD PAL253: R14_0 Position */\r
-#define LCD_PAL253_R14_0_Msk (0x1fUL << LCD_PAL253_R14_0_Pos) /*!< LCD PAL253: R14_0 Mask */\r
-#define LCD_PAL253_G14_0_Pos 21 /*!< LCD PAL253: G14_0 Position */\r
-#define LCD_PAL253_G14_0_Msk (0x1fUL << LCD_PAL253_G14_0_Pos) /*!< LCD PAL253: G14_0 Mask */\r
-#define LCD_PAL253_B14_0_Pos 26 /*!< LCD PAL253: B14_0 Position */\r
-#define LCD_PAL253_B14_0_Msk (0x1fUL << LCD_PAL253_B14_0_Pos) /*!< LCD PAL253: B14_0 Mask */\r
-#define LCD_PAL253_I1_Pos 31 /*!< LCD PAL253: I1 Position */\r
-#define LCD_PAL253_I1_Msk (0x01UL << LCD_PAL253_I1_Pos) /*!< LCD PAL253: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL254 -------------------------------------------\r
-#define LCD_PAL254_R04_0_Pos 0 /*!< LCD PAL254: R04_0 Position */\r
-#define LCD_PAL254_R04_0_Msk (0x1fUL << LCD_PAL254_R04_0_Pos) /*!< LCD PAL254: R04_0 Mask */\r
-#define LCD_PAL254_G04_0_Pos 5 /*!< LCD PAL254: G04_0 Position */\r
-#define LCD_PAL254_G04_0_Msk (0x1fUL << LCD_PAL254_G04_0_Pos) /*!< LCD PAL254: G04_0 Mask */\r
-#define LCD_PAL254_B04_0_Pos 10 /*!< LCD PAL254: B04_0 Position */\r
-#define LCD_PAL254_B04_0_Msk (0x1fUL << LCD_PAL254_B04_0_Pos) /*!< LCD PAL254: B04_0 Mask */\r
-#define LCD_PAL254_I0_Pos 15 /*!< LCD PAL254: I0 Position */\r
-#define LCD_PAL254_I0_Msk (0x01UL << LCD_PAL254_I0_Pos) /*!< LCD PAL254: I0 Mask */\r
-#define LCD_PAL254_R14_0_Pos 16 /*!< LCD PAL254: R14_0 Position */\r
-#define LCD_PAL254_R14_0_Msk (0x1fUL << LCD_PAL254_R14_0_Pos) /*!< LCD PAL254: R14_0 Mask */\r
-#define LCD_PAL254_G14_0_Pos 21 /*!< LCD PAL254: G14_0 Position */\r
-#define LCD_PAL254_G14_0_Msk (0x1fUL << LCD_PAL254_G14_0_Pos) /*!< LCD PAL254: G14_0 Mask */\r
-#define LCD_PAL254_B14_0_Pos 26 /*!< LCD PAL254: B14_0 Position */\r
-#define LCD_PAL254_B14_0_Msk (0x1fUL << LCD_PAL254_B14_0_Pos) /*!< LCD PAL254: B14_0 Mask */\r
-#define LCD_PAL254_I1_Pos 31 /*!< LCD PAL254: I1 Position */\r
-#define LCD_PAL254_I1_Msk (0x01UL << LCD_PAL254_I1_Pos) /*!< LCD PAL254: I1 Mask */\r
-\r
-// --------------------------------------- LCD_PAL255 -------------------------------------------\r
-#define LCD_PAL255_R04_0_Pos 0 /*!< LCD PAL255: R04_0 Position */\r
-#define LCD_PAL255_R04_0_Msk (0x1fUL << LCD_PAL255_R04_0_Pos) /*!< LCD PAL255: R04_0 Mask */\r
-#define LCD_PAL255_G04_0_Pos 5 /*!< LCD PAL255: G04_0 Position */\r
-#define LCD_PAL255_G04_0_Msk (0x1fUL << LCD_PAL255_G04_0_Pos) /*!< LCD PAL255: G04_0 Mask */\r
-#define LCD_PAL255_B04_0_Pos 10 /*!< LCD PAL255: B04_0 Position */\r
-#define LCD_PAL255_B04_0_Msk (0x1fUL << LCD_PAL255_B04_0_Pos) /*!< LCD PAL255: B04_0 Mask */\r
-#define LCD_PAL255_I0_Pos 15 /*!< LCD PAL255: I0 Position */\r
-#define LCD_PAL255_I0_Msk (0x01UL << LCD_PAL255_I0_Pos) /*!< LCD PAL255: I0 Mask */\r
-#define LCD_PAL255_R14_0_Pos 16 /*!< LCD PAL255: R14_0 Position */\r
-#define LCD_PAL255_R14_0_Msk (0x1fUL << LCD_PAL255_R14_0_Pos) /*!< LCD PAL255: R14_0 Mask */\r
-#define LCD_PAL255_G14_0_Pos 21 /*!< LCD PAL255: G14_0 Position */\r
-#define LCD_PAL255_G14_0_Msk (0x1fUL << LCD_PAL255_G14_0_Pos) /*!< LCD PAL255: G14_0 Mask */\r
-#define LCD_PAL255_B14_0_Pos 26 /*!< LCD PAL255: B14_0 Position */\r
-#define LCD_PAL255_B14_0_Msk (0x1fUL << LCD_PAL255_B14_0_Pos) /*!< LCD PAL255: B14_0 Mask */\r
-#define LCD_PAL255_I1_Pos 31 /*!< LCD PAL255: I1 Position */\r
-#define LCD_PAL255_I1_Msk (0x01UL << LCD_PAL255_I1_Pos) /*!< LCD PAL255: I1 Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG0 -----------------------------------------\r
-#define LCD_CRSR_IMG0_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG0: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG0_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos) /*!< LCD CRSR_IMG0: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG1 -----------------------------------------\r
-#define LCD_CRSR_IMG1_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG1: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG1_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos) /*!< LCD CRSR_IMG1: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG2 -----------------------------------------\r
-#define LCD_CRSR_IMG2_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG2: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG2_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos) /*!< LCD CRSR_IMG2: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG3 -----------------------------------------\r
-#define LCD_CRSR_IMG3_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG3: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG3_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos) /*!< LCD CRSR_IMG3: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG4 -----------------------------------------\r
-#define LCD_CRSR_IMG4_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG4: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG4_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos) /*!< LCD CRSR_IMG4: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG5 -----------------------------------------\r
-#define LCD_CRSR_IMG5_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG5: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG5_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos) /*!< LCD CRSR_IMG5: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG6 -----------------------------------------\r
-#define LCD_CRSR_IMG6_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG6: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG6_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos) /*!< LCD CRSR_IMG6: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG7 -----------------------------------------\r
-#define LCD_CRSR_IMG7_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG7: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG7_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos) /*!< LCD CRSR_IMG7: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG8 -----------------------------------------\r
-#define LCD_CRSR_IMG8_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG8: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG8_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos) /*!< LCD CRSR_IMG8: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_IMG9 -----------------------------------------\r
-#define LCD_CRSR_IMG9_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG9: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG9_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos) /*!< LCD CRSR_IMG9: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG10 -----------------------------------------\r
-#define LCD_CRSR_IMG10_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG10: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG10_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos) /*!< LCD CRSR_IMG10: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG11 -----------------------------------------\r
-#define LCD_CRSR_IMG11_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG11: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG11_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos) /*!< LCD CRSR_IMG11: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG12 -----------------------------------------\r
-#define LCD_CRSR_IMG12_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG12: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG12_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos) /*!< LCD CRSR_IMG12: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG13 -----------------------------------------\r
-#define LCD_CRSR_IMG13_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG13: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG13_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos) /*!< LCD CRSR_IMG13: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG14 -----------------------------------------\r
-#define LCD_CRSR_IMG14_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG14: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG14_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos) /*!< LCD CRSR_IMG14: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG15 -----------------------------------------\r
-#define LCD_CRSR_IMG15_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG15: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG15_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos) /*!< LCD CRSR_IMG15: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG16 -----------------------------------------\r
-#define LCD_CRSR_IMG16_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG16: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG16_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos) /*!< LCD CRSR_IMG16: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG17 -----------------------------------------\r
-#define LCD_CRSR_IMG17_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG17: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG17_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos) /*!< LCD CRSR_IMG17: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG18 -----------------------------------------\r
-#define LCD_CRSR_IMG18_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG18: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG18_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos) /*!< LCD CRSR_IMG18: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG19 -----------------------------------------\r
-#define LCD_CRSR_IMG19_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG19: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG19_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos) /*!< LCD CRSR_IMG19: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG20 -----------------------------------------\r
-#define LCD_CRSR_IMG20_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG20: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG20_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos) /*!< LCD CRSR_IMG20: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG21 -----------------------------------------\r
-#define LCD_CRSR_IMG21_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG21: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG21_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos) /*!< LCD CRSR_IMG21: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG22 -----------------------------------------\r
-#define LCD_CRSR_IMG22_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG22: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG22_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos) /*!< LCD CRSR_IMG22: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG23 -----------------------------------------\r
-#define LCD_CRSR_IMG23_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG23: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG23_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos) /*!< LCD CRSR_IMG23: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG24 -----------------------------------------\r
-#define LCD_CRSR_IMG24_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG24: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG24_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos) /*!< LCD CRSR_IMG24: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG25 -----------------------------------------\r
-#define LCD_CRSR_IMG25_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG25: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG25_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos) /*!< LCD CRSR_IMG25: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG26 -----------------------------------------\r
-#define LCD_CRSR_IMG26_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG26: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG26_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos) /*!< LCD CRSR_IMG26: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG27 -----------------------------------------\r
-#define LCD_CRSR_IMG27_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG27: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG27_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos) /*!< LCD CRSR_IMG27: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG28 -----------------------------------------\r
-#define LCD_CRSR_IMG28_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG28: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG28_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos) /*!< LCD CRSR_IMG28: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG29 -----------------------------------------\r
-#define LCD_CRSR_IMG29_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG29: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG29_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos) /*!< LCD CRSR_IMG29: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG30 -----------------------------------------\r
-#define LCD_CRSR_IMG30_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG30: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG30_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos) /*!< LCD CRSR_IMG30: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG31 -----------------------------------------\r
-#define LCD_CRSR_IMG31_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG31: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG31_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos) /*!< LCD CRSR_IMG31: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG32 -----------------------------------------\r
-#define LCD_CRSR_IMG32_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG32: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG32_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos) /*!< LCD CRSR_IMG32: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG33 -----------------------------------------\r
-#define LCD_CRSR_IMG33_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG33: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG33_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos) /*!< LCD CRSR_IMG33: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG34 -----------------------------------------\r
-#define LCD_CRSR_IMG34_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG34: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG34_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos) /*!< LCD CRSR_IMG34: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG35 -----------------------------------------\r
-#define LCD_CRSR_IMG35_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG35: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG35_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos) /*!< LCD CRSR_IMG35: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG36 -----------------------------------------\r
-#define LCD_CRSR_IMG36_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG36: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG36_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos) /*!< LCD CRSR_IMG36: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG37 -----------------------------------------\r
-#define LCD_CRSR_IMG37_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG37: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG37_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos) /*!< LCD CRSR_IMG37: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG38 -----------------------------------------\r
-#define LCD_CRSR_IMG38_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG38: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG38_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos) /*!< LCD CRSR_IMG38: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG39 -----------------------------------------\r
-#define LCD_CRSR_IMG39_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG39: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG39_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos) /*!< LCD CRSR_IMG39: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG40 -----------------------------------------\r
-#define LCD_CRSR_IMG40_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG40: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG40_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos) /*!< LCD CRSR_IMG40: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG41 -----------------------------------------\r
-#define LCD_CRSR_IMG41_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG41: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG41_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos) /*!< LCD CRSR_IMG41: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG42 -----------------------------------------\r
-#define LCD_CRSR_IMG42_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG42: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG42_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos) /*!< LCD CRSR_IMG42: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG43 -----------------------------------------\r
-#define LCD_CRSR_IMG43_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG43: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG43_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos) /*!< LCD CRSR_IMG43: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG44 -----------------------------------------\r
-#define LCD_CRSR_IMG44_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG44: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG44_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos) /*!< LCD CRSR_IMG44: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG45 -----------------------------------------\r
-#define LCD_CRSR_IMG45_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG45: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG45_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos) /*!< LCD CRSR_IMG45: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG46 -----------------------------------------\r
-#define LCD_CRSR_IMG46_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG46: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG46_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos) /*!< LCD CRSR_IMG46: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG47 -----------------------------------------\r
-#define LCD_CRSR_IMG47_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG47: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG47_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos) /*!< LCD CRSR_IMG47: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG48 -----------------------------------------\r
-#define LCD_CRSR_IMG48_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG48: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG48_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos) /*!< LCD CRSR_IMG48: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG49 -----------------------------------------\r
-#define LCD_CRSR_IMG49_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG49: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG49_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos) /*!< LCD CRSR_IMG49: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG50 -----------------------------------------\r
-#define LCD_CRSR_IMG50_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG50: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG50_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos) /*!< LCD CRSR_IMG50: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG51 -----------------------------------------\r
-#define LCD_CRSR_IMG51_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG51: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG51_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos) /*!< LCD CRSR_IMG51: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG52 -----------------------------------------\r
-#define LCD_CRSR_IMG52_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG52: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG52_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos) /*!< LCD CRSR_IMG52: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG53 -----------------------------------------\r
-#define LCD_CRSR_IMG53_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG53: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG53_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos) /*!< LCD CRSR_IMG53: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG54 -----------------------------------------\r
-#define LCD_CRSR_IMG54_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG54: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG54_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos) /*!< LCD CRSR_IMG54: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG55 -----------------------------------------\r
-#define LCD_CRSR_IMG55_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG55: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG55_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos) /*!< LCD CRSR_IMG55: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG56 -----------------------------------------\r
-#define LCD_CRSR_IMG56_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG56: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG56_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos) /*!< LCD CRSR_IMG56: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG57 -----------------------------------------\r
-#define LCD_CRSR_IMG57_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG57: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG57_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos) /*!< LCD CRSR_IMG57: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG58 -----------------------------------------\r
-#define LCD_CRSR_IMG58_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG58: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG58_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos) /*!< LCD CRSR_IMG58: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG59 -----------------------------------------\r
-#define LCD_CRSR_IMG59_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG59: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG59_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos) /*!< LCD CRSR_IMG59: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG60 -----------------------------------------\r
-#define LCD_CRSR_IMG60_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG60: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG60_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos) /*!< LCD CRSR_IMG60: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG61 -----------------------------------------\r
-#define LCD_CRSR_IMG61_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG61: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG61_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos) /*!< LCD CRSR_IMG61: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG62 -----------------------------------------\r
-#define LCD_CRSR_IMG62_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG62: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG62_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos) /*!< LCD CRSR_IMG62: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG63 -----------------------------------------\r
-#define LCD_CRSR_IMG63_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG63: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG63_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos) /*!< LCD CRSR_IMG63: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG64 -----------------------------------------\r
-#define LCD_CRSR_IMG64_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG64: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG64_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos) /*!< LCD CRSR_IMG64: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG65 -----------------------------------------\r
-#define LCD_CRSR_IMG65_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG65: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG65_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos) /*!< LCD CRSR_IMG65: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG66 -----------------------------------------\r
-#define LCD_CRSR_IMG66_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG66: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG66_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos) /*!< LCD CRSR_IMG66: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG67 -----------------------------------------\r
-#define LCD_CRSR_IMG67_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG67: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG67_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos) /*!< LCD CRSR_IMG67: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG68 -----------------------------------------\r
-#define LCD_CRSR_IMG68_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG68: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG68_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos) /*!< LCD CRSR_IMG68: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG69 -----------------------------------------\r
-#define LCD_CRSR_IMG69_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG69: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG69_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos) /*!< LCD CRSR_IMG69: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG70 -----------------------------------------\r
-#define LCD_CRSR_IMG70_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG70: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG70_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos) /*!< LCD CRSR_IMG70: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG71 -----------------------------------------\r
-#define LCD_CRSR_IMG71_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG71: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG71_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos) /*!< LCD CRSR_IMG71: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG72 -----------------------------------------\r
-#define LCD_CRSR_IMG72_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG72: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG72_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos) /*!< LCD CRSR_IMG72: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG73 -----------------------------------------\r
-#define LCD_CRSR_IMG73_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG73: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG73_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos) /*!< LCD CRSR_IMG73: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG74 -----------------------------------------\r
-#define LCD_CRSR_IMG74_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG74: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG74_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos) /*!< LCD CRSR_IMG74: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG75 -----------------------------------------\r
-#define LCD_CRSR_IMG75_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG75: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG75_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos) /*!< LCD CRSR_IMG75: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG76 -----------------------------------------\r
-#define LCD_CRSR_IMG76_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG76: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG76_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos) /*!< LCD CRSR_IMG76: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG77 -----------------------------------------\r
-#define LCD_CRSR_IMG77_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG77: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG77_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos) /*!< LCD CRSR_IMG77: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG78 -----------------------------------------\r
-#define LCD_CRSR_IMG78_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG78: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG78_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos) /*!< LCD CRSR_IMG78: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG79 -----------------------------------------\r
-#define LCD_CRSR_IMG79_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG79: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG79_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos) /*!< LCD CRSR_IMG79: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG80 -----------------------------------------\r
-#define LCD_CRSR_IMG80_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG80: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG80_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos) /*!< LCD CRSR_IMG80: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG81 -----------------------------------------\r
-#define LCD_CRSR_IMG81_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG81: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG81_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos) /*!< LCD CRSR_IMG81: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG82 -----------------------------------------\r
-#define LCD_CRSR_IMG82_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG82: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG82_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos) /*!< LCD CRSR_IMG82: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG83 -----------------------------------------\r
-#define LCD_CRSR_IMG83_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG83: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG83_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos) /*!< LCD CRSR_IMG83: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG84 -----------------------------------------\r
-#define LCD_CRSR_IMG84_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG84: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG84_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos) /*!< LCD CRSR_IMG84: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG85 -----------------------------------------\r
-#define LCD_CRSR_IMG85_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG85: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG85_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos) /*!< LCD CRSR_IMG85: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG86 -----------------------------------------\r
-#define LCD_CRSR_IMG86_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG86: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG86_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos) /*!< LCD CRSR_IMG86: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG87 -----------------------------------------\r
-#define LCD_CRSR_IMG87_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG87: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG87_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos) /*!< LCD CRSR_IMG87: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG88 -----------------------------------------\r
-#define LCD_CRSR_IMG88_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG88: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG88_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos) /*!< LCD CRSR_IMG88: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG89 -----------------------------------------\r
-#define LCD_CRSR_IMG89_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG89: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG89_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos) /*!< LCD CRSR_IMG89: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG90 -----------------------------------------\r
-#define LCD_CRSR_IMG90_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG90: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG90_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos) /*!< LCD CRSR_IMG90: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG91 -----------------------------------------\r
-#define LCD_CRSR_IMG91_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG91: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG91_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos) /*!< LCD CRSR_IMG91: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG92 -----------------------------------------\r
-#define LCD_CRSR_IMG92_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG92: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG92_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos) /*!< LCD CRSR_IMG92: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG93 -----------------------------------------\r
-#define LCD_CRSR_IMG93_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG93: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG93_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos) /*!< LCD CRSR_IMG93: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG94 -----------------------------------------\r
-#define LCD_CRSR_IMG94_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG94: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG94_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos) /*!< LCD CRSR_IMG94: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG95 -----------------------------------------\r
-#define LCD_CRSR_IMG95_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG95: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG95_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos) /*!< LCD CRSR_IMG95: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG96 -----------------------------------------\r
-#define LCD_CRSR_IMG96_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG96: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG96_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos) /*!< LCD CRSR_IMG96: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG97 -----------------------------------------\r
-#define LCD_CRSR_IMG97_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG97: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG97_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos) /*!< LCD CRSR_IMG97: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG98 -----------------------------------------\r
-#define LCD_CRSR_IMG98_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG98: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG98_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos) /*!< LCD CRSR_IMG98: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG99 -----------------------------------------\r
-#define LCD_CRSR_IMG99_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG99: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG99_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos) /*!< LCD CRSR_IMG99: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG100 ----------------------------------------\r
-#define LCD_CRSR_IMG100_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG100: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG100_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos) /*!< LCD CRSR_IMG100: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG101 ----------------------------------------\r
-#define LCD_CRSR_IMG101_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG101: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG101_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos) /*!< LCD CRSR_IMG101: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG102 ----------------------------------------\r
-#define LCD_CRSR_IMG102_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG102: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG102_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos) /*!< LCD CRSR_IMG102: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG103 ----------------------------------------\r
-#define LCD_CRSR_IMG103_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG103: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG103_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos) /*!< LCD CRSR_IMG103: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG104 ----------------------------------------\r
-#define LCD_CRSR_IMG104_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG104: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG104_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos) /*!< LCD CRSR_IMG104: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG105 ----------------------------------------\r
-#define LCD_CRSR_IMG105_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG105: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG105_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos) /*!< LCD CRSR_IMG105: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG106 ----------------------------------------\r
-#define LCD_CRSR_IMG106_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG106: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG106_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos) /*!< LCD CRSR_IMG106: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG107 ----------------------------------------\r
-#define LCD_CRSR_IMG107_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG107: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG107_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos) /*!< LCD CRSR_IMG107: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG108 ----------------------------------------\r
-#define LCD_CRSR_IMG108_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG108: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG108_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos) /*!< LCD CRSR_IMG108: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG109 ----------------------------------------\r
-#define LCD_CRSR_IMG109_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG109: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG109_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos) /*!< LCD CRSR_IMG109: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG110 ----------------------------------------\r
-#define LCD_CRSR_IMG110_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG110: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG110_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos) /*!< LCD CRSR_IMG110: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG111 ----------------------------------------\r
-#define LCD_CRSR_IMG111_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG111: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG111_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos) /*!< LCD CRSR_IMG111: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG112 ----------------------------------------\r
-#define LCD_CRSR_IMG112_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG112: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG112_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos) /*!< LCD CRSR_IMG112: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG113 ----------------------------------------\r
-#define LCD_CRSR_IMG113_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG113: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG113_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos) /*!< LCD CRSR_IMG113: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG114 ----------------------------------------\r
-#define LCD_CRSR_IMG114_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG114: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG114_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos) /*!< LCD CRSR_IMG114: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG115 ----------------------------------------\r
-#define LCD_CRSR_IMG115_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG115: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG115_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos) /*!< LCD CRSR_IMG115: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG116 ----------------------------------------\r
-#define LCD_CRSR_IMG116_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG116: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG116_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos) /*!< LCD CRSR_IMG116: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG117 ----------------------------------------\r
-#define LCD_CRSR_IMG117_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG117: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG117_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos) /*!< LCD CRSR_IMG117: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG118 ----------------------------------------\r
-#define LCD_CRSR_IMG118_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG118: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG118_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos) /*!< LCD CRSR_IMG118: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG119 ----------------------------------------\r
-#define LCD_CRSR_IMG119_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG119: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG119_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos) /*!< LCD CRSR_IMG119: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG120 ----------------------------------------\r
-#define LCD_CRSR_IMG120_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG120: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG120_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos) /*!< LCD CRSR_IMG120: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG121 ----------------------------------------\r
-#define LCD_CRSR_IMG121_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG121: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG121_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos) /*!< LCD CRSR_IMG121: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG122 ----------------------------------------\r
-#define LCD_CRSR_IMG122_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG122: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG122_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos) /*!< LCD CRSR_IMG122: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG123 ----------------------------------------\r
-#define LCD_CRSR_IMG123_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG123: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG123_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos) /*!< LCD CRSR_IMG123: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG124 ----------------------------------------\r
-#define LCD_CRSR_IMG124_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG124: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG124_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos) /*!< LCD CRSR_IMG124: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG125 ----------------------------------------\r
-#define LCD_CRSR_IMG125_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG125: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG125_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos) /*!< LCD CRSR_IMG125: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG126 ----------------------------------------\r
-#define LCD_CRSR_IMG126_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG126: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG126_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos) /*!< LCD CRSR_IMG126: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG127 ----------------------------------------\r
-#define LCD_CRSR_IMG127_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG127: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG127_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos) /*!< LCD CRSR_IMG127: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG128 ----------------------------------------\r
-#define LCD_CRSR_IMG128_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG128: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG128_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos) /*!< LCD CRSR_IMG128: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG129 ----------------------------------------\r
-#define LCD_CRSR_IMG129_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG129: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG129_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos) /*!< LCD CRSR_IMG129: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG130 ----------------------------------------\r
-#define LCD_CRSR_IMG130_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG130: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG130_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos) /*!< LCD CRSR_IMG130: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG131 ----------------------------------------\r
-#define LCD_CRSR_IMG131_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG131: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG131_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos) /*!< LCD CRSR_IMG131: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG132 ----------------------------------------\r
-#define LCD_CRSR_IMG132_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG132: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG132_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos) /*!< LCD CRSR_IMG132: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG133 ----------------------------------------\r
-#define LCD_CRSR_IMG133_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG133: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG133_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos) /*!< LCD CRSR_IMG133: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG134 ----------------------------------------\r
-#define LCD_CRSR_IMG134_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG134: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG134_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos) /*!< LCD CRSR_IMG134: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG135 ----------------------------------------\r
-#define LCD_CRSR_IMG135_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG135: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG135_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos) /*!< LCD CRSR_IMG135: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG136 ----------------------------------------\r
-#define LCD_CRSR_IMG136_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG136: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG136_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos) /*!< LCD CRSR_IMG136: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG137 ----------------------------------------\r
-#define LCD_CRSR_IMG137_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG137: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG137_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos) /*!< LCD CRSR_IMG137: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG138 ----------------------------------------\r
-#define LCD_CRSR_IMG138_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG138: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG138_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos) /*!< LCD CRSR_IMG138: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG139 ----------------------------------------\r
-#define LCD_CRSR_IMG139_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG139: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG139_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos) /*!< LCD CRSR_IMG139: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG140 ----------------------------------------\r
-#define LCD_CRSR_IMG140_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG140: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG140_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos) /*!< LCD CRSR_IMG140: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG141 ----------------------------------------\r
-#define LCD_CRSR_IMG141_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG141: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG141_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos) /*!< LCD CRSR_IMG141: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG142 ----------------------------------------\r
-#define LCD_CRSR_IMG142_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG142: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG142_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos) /*!< LCD CRSR_IMG142: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG143 ----------------------------------------\r
-#define LCD_CRSR_IMG143_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG143: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG143_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos) /*!< LCD CRSR_IMG143: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG144 ----------------------------------------\r
-#define LCD_CRSR_IMG144_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG144: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG144_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos) /*!< LCD CRSR_IMG144: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG145 ----------------------------------------\r
-#define LCD_CRSR_IMG145_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG145: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG145_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos) /*!< LCD CRSR_IMG145: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG146 ----------------------------------------\r
-#define LCD_CRSR_IMG146_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG146: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG146_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos) /*!< LCD CRSR_IMG146: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG147 ----------------------------------------\r
-#define LCD_CRSR_IMG147_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG147: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG147_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos) /*!< LCD CRSR_IMG147: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG148 ----------------------------------------\r
-#define LCD_CRSR_IMG148_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG148: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG148_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos) /*!< LCD CRSR_IMG148: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG149 ----------------------------------------\r
-#define LCD_CRSR_IMG149_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG149: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG149_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos) /*!< LCD CRSR_IMG149: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG150 ----------------------------------------\r
-#define LCD_CRSR_IMG150_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG150: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG150_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos) /*!< LCD CRSR_IMG150: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG151 ----------------------------------------\r
-#define LCD_CRSR_IMG151_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG151: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG151_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos) /*!< LCD CRSR_IMG151: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG152 ----------------------------------------\r
-#define LCD_CRSR_IMG152_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG152: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG152_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos) /*!< LCD CRSR_IMG152: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG153 ----------------------------------------\r
-#define LCD_CRSR_IMG153_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG153: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG153_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos) /*!< LCD CRSR_IMG153: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG154 ----------------------------------------\r
-#define LCD_CRSR_IMG154_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG154: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG154_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos) /*!< LCD CRSR_IMG154: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG155 ----------------------------------------\r
-#define LCD_CRSR_IMG155_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG155: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG155_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos) /*!< LCD CRSR_IMG155: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG156 ----------------------------------------\r
-#define LCD_CRSR_IMG156_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG156: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG156_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos) /*!< LCD CRSR_IMG156: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG157 ----------------------------------------\r
-#define LCD_CRSR_IMG157_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG157: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG157_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos) /*!< LCD CRSR_IMG157: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG158 ----------------------------------------\r
-#define LCD_CRSR_IMG158_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG158: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG158_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos) /*!< LCD CRSR_IMG158: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG159 ----------------------------------------\r
-#define LCD_CRSR_IMG159_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG159: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG159_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos) /*!< LCD CRSR_IMG159: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG160 ----------------------------------------\r
-#define LCD_CRSR_IMG160_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG160: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG160_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos) /*!< LCD CRSR_IMG160: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG161 ----------------------------------------\r
-#define LCD_CRSR_IMG161_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG161: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG161_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos) /*!< LCD CRSR_IMG161: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG162 ----------------------------------------\r
-#define LCD_CRSR_IMG162_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG162: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG162_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos) /*!< LCD CRSR_IMG162: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG163 ----------------------------------------\r
-#define LCD_CRSR_IMG163_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG163: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG163_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos) /*!< LCD CRSR_IMG163: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG164 ----------------------------------------\r
-#define LCD_CRSR_IMG164_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG164: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG164_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos) /*!< LCD CRSR_IMG164: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG165 ----------------------------------------\r
-#define LCD_CRSR_IMG165_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG165: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG165_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos) /*!< LCD CRSR_IMG165: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG166 ----------------------------------------\r
-#define LCD_CRSR_IMG166_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG166: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG166_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos) /*!< LCD CRSR_IMG166: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG167 ----------------------------------------\r
-#define LCD_CRSR_IMG167_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG167: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG167_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos) /*!< LCD CRSR_IMG167: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG168 ----------------------------------------\r
-#define LCD_CRSR_IMG168_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG168: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG168_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos) /*!< LCD CRSR_IMG168: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG169 ----------------------------------------\r
-#define LCD_CRSR_IMG169_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG169: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG169_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos) /*!< LCD CRSR_IMG169: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG170 ----------------------------------------\r
-#define LCD_CRSR_IMG170_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG170: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG170_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos) /*!< LCD CRSR_IMG170: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG171 ----------------------------------------\r
-#define LCD_CRSR_IMG171_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG171: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG171_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos) /*!< LCD CRSR_IMG171: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG172 ----------------------------------------\r
-#define LCD_CRSR_IMG172_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG172: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG172_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos) /*!< LCD CRSR_IMG172: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG173 ----------------------------------------\r
-#define LCD_CRSR_IMG173_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG173: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG173_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos) /*!< LCD CRSR_IMG173: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG174 ----------------------------------------\r
-#define LCD_CRSR_IMG174_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG174: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG174_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos) /*!< LCD CRSR_IMG174: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG175 ----------------------------------------\r
-#define LCD_CRSR_IMG175_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG175: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG175_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos) /*!< LCD CRSR_IMG175: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG176 ----------------------------------------\r
-#define LCD_CRSR_IMG176_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG176: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG176_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos) /*!< LCD CRSR_IMG176: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG177 ----------------------------------------\r
-#define LCD_CRSR_IMG177_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG177: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG177_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos) /*!< LCD CRSR_IMG177: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG178 ----------------------------------------\r
-#define LCD_CRSR_IMG178_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG178: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG178_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos) /*!< LCD CRSR_IMG178: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG179 ----------------------------------------\r
-#define LCD_CRSR_IMG179_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG179: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG179_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos) /*!< LCD CRSR_IMG179: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG180 ----------------------------------------\r
-#define LCD_CRSR_IMG180_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG180: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG180_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos) /*!< LCD CRSR_IMG180: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG181 ----------------------------------------\r
-#define LCD_CRSR_IMG181_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG181: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG181_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos) /*!< LCD CRSR_IMG181: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG182 ----------------------------------------\r
-#define LCD_CRSR_IMG182_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG182: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG182_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos) /*!< LCD CRSR_IMG182: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG183 ----------------------------------------\r
-#define LCD_CRSR_IMG183_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG183: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG183_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos) /*!< LCD CRSR_IMG183: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG184 ----------------------------------------\r
-#define LCD_CRSR_IMG184_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG184: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG184_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos) /*!< LCD CRSR_IMG184: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG185 ----------------------------------------\r
-#define LCD_CRSR_IMG185_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG185: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG185_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos) /*!< LCD CRSR_IMG185: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG186 ----------------------------------------\r
-#define LCD_CRSR_IMG186_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG186: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG186_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos) /*!< LCD CRSR_IMG186: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG187 ----------------------------------------\r
-#define LCD_CRSR_IMG187_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG187: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG187_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos) /*!< LCD CRSR_IMG187: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG188 ----------------------------------------\r
-#define LCD_CRSR_IMG188_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG188: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG188_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos) /*!< LCD CRSR_IMG188: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG189 ----------------------------------------\r
-#define LCD_CRSR_IMG189_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG189: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG189_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos) /*!< LCD CRSR_IMG189: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG190 ----------------------------------------\r
-#define LCD_CRSR_IMG190_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG190: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG190_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos) /*!< LCD CRSR_IMG190: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG191 ----------------------------------------\r
-#define LCD_CRSR_IMG191_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG191: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG191_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos) /*!< LCD CRSR_IMG191: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG192 ----------------------------------------\r
-#define LCD_CRSR_IMG192_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG192: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG192_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos) /*!< LCD CRSR_IMG192: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG193 ----------------------------------------\r
-#define LCD_CRSR_IMG193_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG193: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG193_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos) /*!< LCD CRSR_IMG193: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG194 ----------------------------------------\r
-#define LCD_CRSR_IMG194_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG194: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG194_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos) /*!< LCD CRSR_IMG194: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG195 ----------------------------------------\r
-#define LCD_CRSR_IMG195_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG195: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG195_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos) /*!< LCD CRSR_IMG195: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG196 ----------------------------------------\r
-#define LCD_CRSR_IMG196_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG196: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG196_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos) /*!< LCD CRSR_IMG196: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG197 ----------------------------------------\r
-#define LCD_CRSR_IMG197_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG197: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG197_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos) /*!< LCD CRSR_IMG197: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG198 ----------------------------------------\r
-#define LCD_CRSR_IMG198_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG198: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG198_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos) /*!< LCD CRSR_IMG198: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG199 ----------------------------------------\r
-#define LCD_CRSR_IMG199_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG199: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG199_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos) /*!< LCD CRSR_IMG199: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG200 ----------------------------------------\r
-#define LCD_CRSR_IMG200_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG200: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG200_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos) /*!< LCD CRSR_IMG200: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG201 ----------------------------------------\r
-#define LCD_CRSR_IMG201_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG201: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG201_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos) /*!< LCD CRSR_IMG201: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG202 ----------------------------------------\r
-#define LCD_CRSR_IMG202_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG202: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG202_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos) /*!< LCD CRSR_IMG202: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG203 ----------------------------------------\r
-#define LCD_CRSR_IMG203_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG203: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG203_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos) /*!< LCD CRSR_IMG203: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG204 ----------------------------------------\r
-#define LCD_CRSR_IMG204_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG204: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG204_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos) /*!< LCD CRSR_IMG204: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG205 ----------------------------------------\r
-#define LCD_CRSR_IMG205_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG205: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG205_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos) /*!< LCD CRSR_IMG205: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG206 ----------------------------------------\r
-#define LCD_CRSR_IMG206_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG206: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG206_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos) /*!< LCD CRSR_IMG206: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG207 ----------------------------------------\r
-#define LCD_CRSR_IMG207_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG207: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG207_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos) /*!< LCD CRSR_IMG207: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG208 ----------------------------------------\r
-#define LCD_CRSR_IMG208_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG208: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG208_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos) /*!< LCD CRSR_IMG208: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG209 ----------------------------------------\r
-#define LCD_CRSR_IMG209_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG209: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG209_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos) /*!< LCD CRSR_IMG209: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG210 ----------------------------------------\r
-#define LCD_CRSR_IMG210_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG210: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG210_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos) /*!< LCD CRSR_IMG210: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG211 ----------------------------------------\r
-#define LCD_CRSR_IMG211_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG211: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG211_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos) /*!< LCD CRSR_IMG211: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG212 ----------------------------------------\r
-#define LCD_CRSR_IMG212_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG212: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG212_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos) /*!< LCD CRSR_IMG212: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG213 ----------------------------------------\r
-#define LCD_CRSR_IMG213_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG213: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG213_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos) /*!< LCD CRSR_IMG213: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG214 ----------------------------------------\r
-#define LCD_CRSR_IMG214_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG214: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG214_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos) /*!< LCD CRSR_IMG214: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG215 ----------------------------------------\r
-#define LCD_CRSR_IMG215_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG215: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG215_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos) /*!< LCD CRSR_IMG215: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG216 ----------------------------------------\r
-#define LCD_CRSR_IMG216_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG216: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG216_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos) /*!< LCD CRSR_IMG216: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG217 ----------------------------------------\r
-#define LCD_CRSR_IMG217_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG217: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG217_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos) /*!< LCD CRSR_IMG217: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG218 ----------------------------------------\r
-#define LCD_CRSR_IMG218_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG218: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG218_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos) /*!< LCD CRSR_IMG218: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG219 ----------------------------------------\r
-#define LCD_CRSR_IMG219_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG219: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG219_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos) /*!< LCD CRSR_IMG219: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG220 ----------------------------------------\r
-#define LCD_CRSR_IMG220_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG220: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG220_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos) /*!< LCD CRSR_IMG220: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG221 ----------------------------------------\r
-#define LCD_CRSR_IMG221_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG221: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG221_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos) /*!< LCD CRSR_IMG221: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG222 ----------------------------------------\r
-#define LCD_CRSR_IMG222_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG222: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG222_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos) /*!< LCD CRSR_IMG222: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG223 ----------------------------------------\r
-#define LCD_CRSR_IMG223_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG223: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG223_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos) /*!< LCD CRSR_IMG223: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG224 ----------------------------------------\r
-#define LCD_CRSR_IMG224_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG224: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG224_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos) /*!< LCD CRSR_IMG224: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG225 ----------------------------------------\r
-#define LCD_CRSR_IMG225_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG225: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG225_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos) /*!< LCD CRSR_IMG225: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG226 ----------------------------------------\r
-#define LCD_CRSR_IMG226_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG226: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG226_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos) /*!< LCD CRSR_IMG226: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG227 ----------------------------------------\r
-#define LCD_CRSR_IMG227_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG227: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG227_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos) /*!< LCD CRSR_IMG227: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG228 ----------------------------------------\r
-#define LCD_CRSR_IMG228_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG228: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG228_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos) /*!< LCD CRSR_IMG228: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG229 ----------------------------------------\r
-#define LCD_CRSR_IMG229_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG229: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG229_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos) /*!< LCD CRSR_IMG229: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG230 ----------------------------------------\r
-#define LCD_CRSR_IMG230_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG230: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG230_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos) /*!< LCD CRSR_IMG230: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG231 ----------------------------------------\r
-#define LCD_CRSR_IMG231_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG231: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG231_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos) /*!< LCD CRSR_IMG231: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG232 ----------------------------------------\r
-#define LCD_CRSR_IMG232_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG232: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG232_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos) /*!< LCD CRSR_IMG232: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG233 ----------------------------------------\r
-#define LCD_CRSR_IMG233_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG233: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG233_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos) /*!< LCD CRSR_IMG233: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG234 ----------------------------------------\r
-#define LCD_CRSR_IMG234_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG234: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG234_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos) /*!< LCD CRSR_IMG234: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG235 ----------------------------------------\r
-#define LCD_CRSR_IMG235_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG235: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG235_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos) /*!< LCD CRSR_IMG235: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG236 ----------------------------------------\r
-#define LCD_CRSR_IMG236_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG236: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG236_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos) /*!< LCD CRSR_IMG236: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG237 ----------------------------------------\r
-#define LCD_CRSR_IMG237_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG237: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG237_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos) /*!< LCD CRSR_IMG237: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG238 ----------------------------------------\r
-#define LCD_CRSR_IMG238_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG238: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG238_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos) /*!< LCD CRSR_IMG238: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG239 ----------------------------------------\r
-#define LCD_CRSR_IMG239_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG239: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG239_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos) /*!< LCD CRSR_IMG239: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG240 ----------------------------------------\r
-#define LCD_CRSR_IMG240_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG240: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG240_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos) /*!< LCD CRSR_IMG240: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG241 ----------------------------------------\r
-#define LCD_CRSR_IMG241_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG241: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG241_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos) /*!< LCD CRSR_IMG241: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG242 ----------------------------------------\r
-#define LCD_CRSR_IMG242_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG242: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG242_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos) /*!< LCD CRSR_IMG242: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG243 ----------------------------------------\r
-#define LCD_CRSR_IMG243_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG243: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG243_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos) /*!< LCD CRSR_IMG243: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG244 ----------------------------------------\r
-#define LCD_CRSR_IMG244_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG244: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG244_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos) /*!< LCD CRSR_IMG244: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG245 ----------------------------------------\r
-#define LCD_CRSR_IMG245_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG245: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG245_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos) /*!< LCD CRSR_IMG245: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG246 ----------------------------------------\r
-#define LCD_CRSR_IMG246_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG246: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG246_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos) /*!< LCD CRSR_IMG246: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG247 ----------------------------------------\r
-#define LCD_CRSR_IMG247_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG247: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG247_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos) /*!< LCD CRSR_IMG247: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG248 ----------------------------------------\r
-#define LCD_CRSR_IMG248_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG248: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG248_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos) /*!< LCD CRSR_IMG248: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG249 ----------------------------------------\r
-#define LCD_CRSR_IMG249_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG249: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG249_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos) /*!< LCD CRSR_IMG249: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG250 ----------------------------------------\r
-#define LCD_CRSR_IMG250_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG250: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG250_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos) /*!< LCD CRSR_IMG250: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG251 ----------------------------------------\r
-#define LCD_CRSR_IMG251_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG251: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG251_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos) /*!< LCD CRSR_IMG251: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG252 ----------------------------------------\r
-#define LCD_CRSR_IMG252_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG252: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG252_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos) /*!< LCD CRSR_IMG252: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG253 ----------------------------------------\r
-#define LCD_CRSR_IMG253_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG253: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG253_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos) /*!< LCD CRSR_IMG253: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG254 ----------------------------------------\r
-#define LCD_CRSR_IMG254_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG254: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG254_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos) /*!< LCD CRSR_IMG254: CRSR_IMG Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_IMG255 ----------------------------------------\r
-#define LCD_CRSR_IMG255_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG255: CRSR_IMG Position */\r
-#define LCD_CRSR_IMG255_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos) /*!< LCD CRSR_IMG255: CRSR_IMG Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_CTRL -----------------------------------------\r
-#define LCD_CRSR_CTRL_CrsrOn_Pos 0 /*!< LCD CRSR_CTRL: CrsrOn Position */\r
-#define LCD_CRSR_CTRL_CrsrOn_Msk (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos) /*!< LCD CRSR_CTRL: CrsrOn Mask */\r
-#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos 4 /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position */\r
-#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos) /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_CFG ------------------------------------------\r
-#define LCD_CRSR_CFG_CrsrSize_Pos 0 /*!< LCD CRSR_CFG: CrsrSize Position */\r
-#define LCD_CRSR_CFG_CrsrSize_Msk (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos) /*!< LCD CRSR_CFG: CrsrSize Mask */\r
-#define LCD_CRSR_CFG_FRAMESYNC_Pos 1 /*!< LCD CRSR_CFG: FRAMESYNC Position */\r
-#define LCD_CRSR_CFG_FRAMESYNC_Msk (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos) /*!< LCD CRSR_CFG: FRAMESYNC Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_PAL0 -----------------------------------------\r
-#define LCD_CRSR_PAL0_RED_Pos 0 /*!< LCD CRSR_PAL0: RED Position */\r
-#define LCD_CRSR_PAL0_RED_Msk (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos) /*!< LCD CRSR_PAL0: RED Mask */\r
-#define LCD_CRSR_PAL0_GREEN_Pos 8 /*!< LCD CRSR_PAL0: GREEN Position */\r
-#define LCD_CRSR_PAL0_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos) /*!< LCD CRSR_PAL0: GREEN Mask */\r
-#define LCD_CRSR_PAL0_BLUE_Pos 16 /*!< LCD CRSR_PAL0: BLUE Position */\r
-#define LCD_CRSR_PAL0_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos) /*!< LCD CRSR_PAL0: BLUE Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_PAL1 -----------------------------------------\r
-#define LCD_CRSR_PAL1_RED_Pos 0 /*!< LCD CRSR_PAL1: RED Position */\r
-#define LCD_CRSR_PAL1_RED_Msk (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos) /*!< LCD CRSR_PAL1: RED Mask */\r
-#define LCD_CRSR_PAL1_GREEN_Pos 8 /*!< LCD CRSR_PAL1: GREEN Position */\r
-#define LCD_CRSR_PAL1_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos) /*!< LCD CRSR_PAL1: GREEN Mask */\r
-#define LCD_CRSR_PAL1_BLUE_Pos 16 /*!< LCD CRSR_PAL1: BLUE Position */\r
-#define LCD_CRSR_PAL1_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos) /*!< LCD CRSR_PAL1: BLUE Mask */\r
-\r
-// --------------------------------------- LCD_CRSR_XY ------------------------------------------\r
-#define LCD_CRSR_XY_CRSRX_Pos 0 /*!< LCD CRSR_XY: CRSRX Position */\r
-#define LCD_CRSR_XY_CRSRX_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos) /*!< LCD CRSR_XY: CRSRX Mask */\r
-#define LCD_CRSR_XY_CRSRY_Pos 16 /*!< LCD CRSR_XY: CRSRY Position */\r
-#define LCD_CRSR_XY_CRSRY_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos) /*!< LCD CRSR_XY: CRSRY Mask */\r
-\r
-// -------------------------------------- LCD_CRSR_CLIP -----------------------------------------\r
-#define LCD_CRSR_CLIP_CRSRCLIPX_Pos 0 /*!< LCD CRSR_CLIP: CRSRCLIPX Position */\r
-#define LCD_CRSR_CLIP_CRSRCLIPX_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPX Mask */\r
-#define LCD_CRSR_CLIP_CRSRCLIPY_Pos 8 /*!< LCD CRSR_CLIP: CRSRCLIPY Position */\r
-#define LCD_CRSR_CLIP_CRSRCLIPY_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPY Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_INTMSK ----------------------------------------\r
-#define LCD_CRSR_INTMSK_CRSRIM_Pos 0 /*!< LCD CRSR_INTMSK: CRSRIM Position */\r
-#define LCD_CRSR_INTMSK_CRSRIM_Msk (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos) /*!< LCD CRSR_INTMSK: CRSRIM Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_INTCLR ----------------------------------------\r
-#define LCD_CRSR_INTCLR_CRSRIC_Pos 0 /*!< LCD CRSR_INTCLR: CRSRIC Position */\r
-#define LCD_CRSR_INTCLR_CRSRIC_Msk (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos) /*!< LCD CRSR_INTCLR: CRSRIC Mask */\r
-\r
-// ------------------------------------- LCD_CRSR_INTRAW ----------------------------------------\r
-#define LCD_CRSR_INTRAW_CRSRRIS_Pos 0 /*!< LCD CRSR_INTRAW: CRSRRIS Position */\r
-#define LCD_CRSR_INTRAW_CRSRRIS_Msk (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos) /*!< LCD CRSR_INTRAW: CRSRRIS Mask */\r
-\r
-// ------------------------------------ LCD_CRSR_INTSTAT ----------------------------------------\r
-#define LCD_CRSR_INTSTAT_CRSRMIS_Pos 0 /*!< LCD CRSR_INTSTAT: CRSRMIS Position */\r
-#define LCD_CRSR_INTSTAT_CRSRMIS_Msk (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos) /*!< LCD CRSR_INTSTAT: CRSRMIS Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- ETHERNET Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------- ETHERNET_MAC_CONFIG --------------------------------------\r
-#define ETHERNET_MAC_CONFIG_RE_Pos 2 /*!< ETHERNET MAC_CONFIG: RE Position */\r
-#define ETHERNET_MAC_CONFIG_RE_Msk (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos) /*!< ETHERNET MAC_CONFIG: RE Mask */\r
-#define ETHERNET_MAC_CONFIG_TE_Pos 3 /*!< ETHERNET MAC_CONFIG: TE Position */\r
-#define ETHERNET_MAC_CONFIG_TE_Msk (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos) /*!< ETHERNET MAC_CONFIG: TE Mask */\r
-#define ETHERNET_MAC_CONFIG_DF_Pos 4 /*!< ETHERNET MAC_CONFIG: DF Position */\r
-#define ETHERNET_MAC_CONFIG_DF_Msk (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos) /*!< ETHERNET MAC_CONFIG: DF Mask */\r
-#define ETHERNET_MAC_CONFIG_BL_Pos 5 /*!< ETHERNET MAC_CONFIG: BL Position */\r
-#define ETHERNET_MAC_CONFIG_BL_Msk (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos) /*!< ETHERNET MAC_CONFIG: BL Mask */\r
-#define ETHERNET_MAC_CONFIG_ACS_Pos 7 /*!< ETHERNET MAC_CONFIG: ACS Position */\r
-#define ETHERNET_MAC_CONFIG_ACS_Msk (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos) /*!< ETHERNET MAC_CONFIG: ACS Mask */\r
-#define ETHERNET_MAC_CONFIG_DR_Pos 9 /*!< ETHERNET MAC_CONFIG: DR Position */\r
-#define ETHERNET_MAC_CONFIG_DR_Msk (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos) /*!< ETHERNET MAC_CONFIG: DR Mask */\r
-#define ETHERNET_MAC_CONFIG_IPC_Pos 10 /*!< ETHERNET MAC_CONFIG: IPC Position */\r
-#define ETHERNET_MAC_CONFIG_IPC_Msk (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos) /*!< ETHERNET MAC_CONFIG: IPC Mask */\r
-#define ETHERNET_MAC_CONFIG_DM_Pos 11 /*!< ETHERNET MAC_CONFIG: DM Position */\r
-#define ETHERNET_MAC_CONFIG_DM_Msk (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos) /*!< ETHERNET MAC_CONFIG: DM Mask */\r
-#define ETHERNET_MAC_CONFIG_LM_Pos 12 /*!< ETHERNET MAC_CONFIG: LM Position */\r
-#define ETHERNET_MAC_CONFIG_LM_Msk (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos) /*!< ETHERNET MAC_CONFIG: LM Mask */\r
-#define ETHERNET_MAC_CONFIG_DO_Pos 13 /*!< ETHERNET MAC_CONFIG: DO Position */\r
-#define ETHERNET_MAC_CONFIG_DO_Msk (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos) /*!< ETHERNET MAC_CONFIG: DO Mask */\r
-#define ETHERNET_MAC_CONFIG_FES_Pos 14 /*!< ETHERNET MAC_CONFIG: FES Position */\r
-#define ETHERNET_MAC_CONFIG_FES_Msk (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos) /*!< ETHERNET MAC_CONFIG: FES Mask */\r
-#define ETHERNET_MAC_CONFIG_PS_Pos 15 /*!< ETHERNET MAC_CONFIG: PS Position */\r
-#define ETHERNET_MAC_CONFIG_PS_Msk (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos) /*!< ETHERNET MAC_CONFIG: PS Mask */\r
-#define ETHERNET_MAC_CONFIG_DCRS_Pos 16 /*!< ETHERNET MAC_CONFIG: DCRS Position */\r
-#define ETHERNET_MAC_CONFIG_DCRS_Msk (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos) /*!< ETHERNET MAC_CONFIG: DCRS Mask */\r
-#define ETHERNET_MAC_CONFIG_IFG_Pos 17 /*!< ETHERNET MAC_CONFIG: IFG Position */\r
-#define ETHERNET_MAC_CONFIG_IFG_Msk (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos) /*!< ETHERNET MAC_CONFIG: IFG Mask */\r
-#define ETHERNET_MAC_CONFIG_JE_Pos 20 /*!< ETHERNET MAC_CONFIG: JE Position */\r
-#define ETHERNET_MAC_CONFIG_JE_Msk (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos) /*!< ETHERNET MAC_CONFIG: JE Mask */\r
-#define ETHERNET_MAC_CONFIG_JD_Pos 22 /*!< ETHERNET MAC_CONFIG: JD Position */\r
-#define ETHERNET_MAC_CONFIG_JD_Msk (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos) /*!< ETHERNET MAC_CONFIG: JD Mask */\r
-#define ETHERNET_MAC_CONFIG_WD_Pos 23 /*!< ETHERNET MAC_CONFIG: WD Position */\r
-#define ETHERNET_MAC_CONFIG_WD_Msk (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos) /*!< ETHERNET MAC_CONFIG: WD Mask */\r
-\r
-// -------------------------------- ETHERNET_MAC_FRAME_FILTER -----------------------------------\r
-#define ETHERNET_MAC_FRAME_FILTER_PR_Pos 0 /*!< ETHERNET MAC_FRAME_FILTER: PR Position */\r
-#define ETHERNET_MAC_FRAME_FILTER_PR_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PR Mask */\r
-#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos 3 /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */\r
-#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */\r
-#define ETHERNET_MAC_FRAME_FILTER_PM_Pos 4 /*!< ETHERNET MAC_FRAME_FILTER: PM Position */\r
-#define ETHERNET_MAC_FRAME_FILTER_PM_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PM Mask */\r
-#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos 5 /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */\r
-#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */\r
-#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos 6 /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */\r
-#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */\r
-#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos 8 /*!< ETHERNET MAC_FRAME_FILTER: SAIF Position */\r
-#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAIF Mask */\r
-#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos 9 /*!< ETHERNET MAC_FRAME_FILTER: SAF Position */\r
-#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAF Mask */\r
-#define ETHERNET_MAC_FRAME_FILTER_RA_Pos 31 /*!< ETHERNET MAC_FRAME_FILTER: RA Position */\r
-#define ETHERNET_MAC_FRAME_FILTER_RA_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos) /*!< ETHERNET MAC_FRAME_FILTER: RA Mask */\r
-\r
-// ------------------------------- ETHERNET_MAC_HASHTABLE_HIGH ----------------------------------\r
-#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos 0 /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */\r
-#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos) /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */\r
-\r
-// ------------------------------- ETHERNET_MAC_HASHTABLE_LOW -----------------------------------\r
-#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos 0 /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */\r
-#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos) /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */\r
-\r
-// ---------------------------------- ETHERNET_MAC_MII_ADDR -------------------------------------\r
-#define ETHERNET_MAC_MII_ADDR_GB_Pos 0 /*!< ETHERNET MAC_MII_ADDR: GB Position */\r
-#define ETHERNET_MAC_MII_ADDR_GB_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos) /*!< ETHERNET MAC_MII_ADDR: GB Mask */\r
-#define ETHERNET_MAC_MII_ADDR_W_Pos 1 /*!< ETHERNET MAC_MII_ADDR: W Position */\r
-#define ETHERNET_MAC_MII_ADDR_W_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos) /*!< ETHERNET MAC_MII_ADDR: W Mask */\r
-#define ETHERNET_MAC_MII_ADDR_CR_Pos 2 /*!< ETHERNET MAC_MII_ADDR: CR Position */\r
-#define ETHERNET_MAC_MII_ADDR_CR_Msk (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos) /*!< ETHERNET MAC_MII_ADDR: CR Mask */\r
-#define ETHERNET_MAC_MII_ADDR_GR_Pos 6 /*!< ETHERNET MAC_MII_ADDR: GR Position */\r
-#define ETHERNET_MAC_MII_ADDR_GR_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos) /*!< ETHERNET MAC_MII_ADDR: GR Mask */\r
-#define ETHERNET_MAC_MII_ADDR_PA_Pos 11 /*!< ETHERNET MAC_MII_ADDR: PA Position */\r
-#define ETHERNET_MAC_MII_ADDR_PA_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos) /*!< ETHERNET MAC_MII_ADDR: PA Mask */\r
-\r
-// ---------------------------------- ETHERNET_MAC_MII_DATA -------------------------------------\r
-#define ETHERNET_MAC_MII_DATA_GD_Pos 0 /*!< ETHERNET MAC_MII_DATA: GD Position */\r
-#define ETHERNET_MAC_MII_DATA_GD_Msk (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos) /*!< ETHERNET MAC_MII_DATA: GD Mask */\r
-\r
-// --------------------------------- ETHERNET_MAC_FLOW_CTRL -------------------------------------\r
-#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos 0 /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */\r
-#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos) /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask */\r
-#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos 1 /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */\r
-#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask */\r
-#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos 2 /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */\r
-#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask */\r
-#define ETHERNET_MAC_FLOW_CTRL_UP_Pos 3 /*!< ETHERNET MAC_FLOW_CTRL: UP Position */\r
-#define ETHERNET_MAC_FLOW_CTRL_UP_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos) /*!< ETHERNET MAC_FLOW_CTRL: UP Mask */\r
-#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos 4 /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */\r
-#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask */\r
-#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos 7 /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */\r
-#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos) /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask */\r
-#define ETHERNET_MAC_FLOW_CTRL_PT_Pos 16 /*!< ETHERNET MAC_FLOW_CTRL: PT Position */\r
-#define ETHERNET_MAC_FLOW_CTRL_PT_Msk (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PT Mask */\r
-\r
-// ---------------------------------- ETHERNET_MAC_VLAN_TAG -------------------------------------\r
-#define ETHERNET_MAC_VLAN_TAG_VL_Pos 0 /*!< ETHERNET MAC_VLAN_TAG: VL Position */\r
-#define ETHERNET_MAC_VLAN_TAG_VL_Msk (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos) /*!< ETHERNET MAC_VLAN_TAG: VL Mask */\r
-#define ETHERNET_MAC_VLAN_TAG_ETV_Pos 16 /*!< ETHERNET MAC_VLAN_TAG: ETV Position */\r
-#define ETHERNET_MAC_VLAN_TAG_ETV_Msk (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos) /*!< ETHERNET MAC_VLAN_TAG: ETV Mask */\r
-\r
-// ----------------------------------- ETHERNET_MAC_DEBUG ---------------------------------------\r
-#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos 0 /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */\r
-#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */\r
-#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos 1 /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */\r
-#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos) /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask */\r
-#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos 4 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */\r
-#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */\r
-#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos 5 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */\r
-#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */\r
-#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos 8 /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */\r
-#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask */\r
-#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos 16 /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */\r
-#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */\r
-#define ETHERNET_MAC_DEBUG_TXSTAT_Pos 17 /*!< ETHERNET MAC_DEBUG: TXSTAT Position */\r
-#define ETHERNET_MAC_DEBUG_TXSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXSTAT Mask */\r
-#define ETHERNET_MAC_DEBUG_PAUSE_Pos 19 /*!< ETHERNET MAC_DEBUG: PAUSE Position */\r
-#define ETHERNET_MAC_DEBUG_PAUSE_Msk (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos) /*!< ETHERNET MAC_DEBUG: PAUSE Mask */\r
-#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos 20 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */\r
-#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */\r
-#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos 22 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */\r
-#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */\r
-#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos 24 /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */\r
-#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask */\r
-#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos 25 /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */\r
-#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */\r
-\r
-// -------------------------------- ETHERNET_MAC_RWAKE_FRFLT ------------------------------------\r
-#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos 0 /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */\r
-#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos) /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */\r
-\r
-// ------------------------------- ETHERNET_MAC_PMT_CTRL_STAT -----------------------------------\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos 0 /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos 1 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos 2 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos 5 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos 6 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos 9 /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos 31 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */\r
-#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */\r
-\r
-// --------------------------------- ETHERNET_MAC_INTR_MASK -------------------------------------\r
-#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos 3 /*!< ETHERNET MAC_INTR_MASK: PMTMSK Position */\r
-#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos) /*!< ETHERNET MAC_INTR_MASK: PMTMSK Mask */\r
-\r
-// --------------------------------- ETHERNET_MAC_ADDR0_HIGH ------------------------------------\r
-#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos 0 /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */\r
-#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */\r
-#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos 31 /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */\r
-#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask */\r
-\r
-// --------------------------------- ETHERNET_MAC_ADDR0_LOW -------------------------------------\r
-#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos 0 /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */\r
-#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos) /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask */\r
-\r
-// -------------------------------- ETHERNET_MAC_TIMESTP_CTRL -----------------------------------\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos 0 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos 1 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos 2 /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos 3 /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos 4 /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos 5 /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos 8 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos 9 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos 10 /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos 11 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos 12 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos 13 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos 14 /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos 15 /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos 16 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos 18 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */\r
-#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */\r
-\r
-// ---------------------------------- ETHERNET_DMA_BUS_MODE -------------------------------------\r
-#define ETHERNET_DMA_BUS_MODE_SWR_Pos 0 /*!< ETHERNET DMA_BUS_MODE: SWR Position */\r
-#define ETHERNET_DMA_BUS_MODE_SWR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos) /*!< ETHERNET DMA_BUS_MODE: SWR Mask */\r
-#define ETHERNET_DMA_BUS_MODE_DA_Pos 1 /*!< ETHERNET DMA_BUS_MODE: DA Position */\r
-#define ETHERNET_DMA_BUS_MODE_DA_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos) /*!< ETHERNET DMA_BUS_MODE: DA Mask */\r
-#define ETHERNET_DMA_BUS_MODE_DSL_Pos 2 /*!< ETHERNET DMA_BUS_MODE: DSL Position */\r
-#define ETHERNET_DMA_BUS_MODE_DSL_Msk (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos) /*!< ETHERNET DMA_BUS_MODE: DSL Mask */\r
-#define ETHERNET_DMA_BUS_MODE_ATDS_Pos 7 /*!< ETHERNET DMA_BUS_MODE: ATDS Position */\r
-#define ETHERNET_DMA_BUS_MODE_ATDS_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos) /*!< ETHERNET DMA_BUS_MODE: ATDS Mask */\r
-#define ETHERNET_DMA_BUS_MODE_PBL_Pos 8 /*!< ETHERNET DMA_BUS_MODE: PBL Position */\r
-#define ETHERNET_DMA_BUS_MODE_PBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL Mask */\r
-#define ETHERNET_DMA_BUS_MODE_PR_Pos 14 /*!< ETHERNET DMA_BUS_MODE: PR Position */\r
-#define ETHERNET_DMA_BUS_MODE_PR_Msk (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos) /*!< ETHERNET DMA_BUS_MODE: PR Mask */\r
-#define ETHERNET_DMA_BUS_MODE_FB_Pos 16 /*!< ETHERNET DMA_BUS_MODE: FB Position */\r
-#define ETHERNET_DMA_BUS_MODE_FB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos) /*!< ETHERNET DMA_BUS_MODE: FB Mask */\r
-#define ETHERNET_DMA_BUS_MODE_RPBL_Pos 17 /*!< ETHERNET DMA_BUS_MODE: RPBL Position */\r
-#define ETHERNET_DMA_BUS_MODE_RPBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos) /*!< ETHERNET DMA_BUS_MODE: RPBL Mask */\r
-#define ETHERNET_DMA_BUS_MODE_USP_Pos 23 /*!< ETHERNET DMA_BUS_MODE: USP Position */\r
-#define ETHERNET_DMA_BUS_MODE_USP_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos) /*!< ETHERNET DMA_BUS_MODE: USP Mask */\r
-#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos 24 /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */\r
-#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask */\r
-#define ETHERNET_DMA_BUS_MODE_AAL_Pos 25 /*!< ETHERNET DMA_BUS_MODE: AAL Position */\r
-#define ETHERNET_DMA_BUS_MODE_AAL_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos) /*!< ETHERNET DMA_BUS_MODE: AAL Mask */\r
-#define ETHERNET_DMA_BUS_MODE_MB_Pos 26 /*!< ETHERNET DMA_BUS_MODE: MB Position */\r
-#define ETHERNET_DMA_BUS_MODE_MB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos) /*!< ETHERNET DMA_BUS_MODE: MB Mask */\r
-#define ETHERNET_DMA_BUS_MODE_TXPR_Pos 27 /*!< ETHERNET DMA_BUS_MODE: TXPR Position */\r
-#define ETHERNET_DMA_BUS_MODE_TXPR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos) /*!< ETHERNET DMA_BUS_MODE: TXPR Mask */\r
-\r
-// ----------------------------- ETHERNET_DMA_TRANS_POLL_DEMAND ---------------------------------\r
-#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos 0 /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */\r
-#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos) /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */\r
-\r
-// ------------------------------ ETHERNET_DMA_REC_POLL_DEMAND ----------------------------------\r
-#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos 0 /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */\r
-#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos) /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */\r
-\r
-// -------------------------------- ETHERNET_DMA_REC_DES_ADDR -----------------------------------\r
-#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */\r
-#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */\r
-\r
-// ------------------------------- ETHERNET_DMA_TRANS_DES_ADDR ----------------------------------\r
-#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */\r
-#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */\r
-\r
-// ------------------------------------ ETHERNET_DMA_STAT ---------------------------------------\r
-#define ETHERNET_DMA_STAT_TI_Pos 0 /*!< ETHERNET DMA_STAT: TI Position */\r
-#define ETHERNET_DMA_STAT_TI_Msk (0x01UL << ETHERNET_DMA_STAT_TI_Pos) /*!< ETHERNET DMA_STAT: TI Mask */\r
-#define ETHERNET_DMA_STAT_TPS_Pos 1 /*!< ETHERNET DMA_STAT: TPS Position */\r
-#define ETHERNET_DMA_STAT_TPS_Msk (0x01UL << ETHERNET_DMA_STAT_TPS_Pos) /*!< ETHERNET DMA_STAT: TPS Mask */\r
-#define ETHERNET_DMA_STAT_TU_Pos 2 /*!< ETHERNET DMA_STAT: TU Position */\r
-#define ETHERNET_DMA_STAT_TU_Msk (0x01UL << ETHERNET_DMA_STAT_TU_Pos) /*!< ETHERNET DMA_STAT: TU Mask */\r
-#define ETHERNET_DMA_STAT_TJT_Pos 3 /*!< ETHERNET DMA_STAT: TJT Position */\r
-#define ETHERNET_DMA_STAT_TJT_Msk (0x01UL << ETHERNET_DMA_STAT_TJT_Pos) /*!< ETHERNET DMA_STAT: TJT Mask */\r
-#define ETHERNET_DMA_STAT_OVF_Pos 4 /*!< ETHERNET DMA_STAT: OVF Position */\r
-#define ETHERNET_DMA_STAT_OVF_Msk (0x01UL << ETHERNET_DMA_STAT_OVF_Pos) /*!< ETHERNET DMA_STAT: OVF Mask */\r
-#define ETHERNET_DMA_STAT_UNF_Pos 5 /*!< ETHERNET DMA_STAT: UNF Position */\r
-#define ETHERNET_DMA_STAT_UNF_Msk (0x01UL << ETHERNET_DMA_STAT_UNF_Pos) /*!< ETHERNET DMA_STAT: UNF Mask */\r
-#define ETHERNET_DMA_STAT_RI_Pos 6 /*!< ETHERNET DMA_STAT: RI Position */\r
-#define ETHERNET_DMA_STAT_RI_Msk (0x01UL << ETHERNET_DMA_STAT_RI_Pos) /*!< ETHERNET DMA_STAT: RI Mask */\r
-#define ETHERNET_DMA_STAT_RU_Pos 7 /*!< ETHERNET DMA_STAT: RU Position */\r
-#define ETHERNET_DMA_STAT_RU_Msk (0x01UL << ETHERNET_DMA_STAT_RU_Pos) /*!< ETHERNET DMA_STAT: RU Mask */\r
-#define ETHERNET_DMA_STAT_RPS_Pos 8 /*!< ETHERNET DMA_STAT: RPS Position */\r
-#define ETHERNET_DMA_STAT_RPS_Msk (0x01UL << ETHERNET_DMA_STAT_RPS_Pos) /*!< ETHERNET DMA_STAT: RPS Mask */\r
-#define ETHERNET_DMA_STAT_RWT_Pos 9 /*!< ETHERNET DMA_STAT: RWT Position */\r
-#define ETHERNET_DMA_STAT_RWT_Msk (0x01UL << ETHERNET_DMA_STAT_RWT_Pos) /*!< ETHERNET DMA_STAT: RWT Mask */\r
-#define ETHERNET_DMA_STAT_ETI_Pos 10 /*!< ETHERNET DMA_STAT: ETI Position */\r
-#define ETHERNET_DMA_STAT_ETI_Msk (0x01UL << ETHERNET_DMA_STAT_ETI_Pos) /*!< ETHERNET DMA_STAT: ETI Mask */\r
-#define ETHERNET_DMA_STAT_FBI_Pos 13 /*!< ETHERNET DMA_STAT: FBI Position */\r
-#define ETHERNET_DMA_STAT_FBI_Msk (0x01UL << ETHERNET_DMA_STAT_FBI_Pos) /*!< ETHERNET DMA_STAT: FBI Mask */\r
-#define ETHERNET_DMA_STAT_ERI_Pos 14 /*!< ETHERNET DMA_STAT: ERI Position */\r
-#define ETHERNET_DMA_STAT_ERI_Msk (0x01UL << ETHERNET_DMA_STAT_ERI_Pos) /*!< ETHERNET DMA_STAT: ERI Mask */\r
-#define ETHERNET_DMA_STAT_AIE_Pos 15 /*!< ETHERNET DMA_STAT: AIE Position */\r
-#define ETHERNET_DMA_STAT_AIE_Msk (0x01UL << ETHERNET_DMA_STAT_AIE_Pos) /*!< ETHERNET DMA_STAT: AIE Mask */\r
-#define ETHERNET_DMA_STAT_NIS_Pos 16 /*!< ETHERNET DMA_STAT: NIS Position */\r
-#define ETHERNET_DMA_STAT_NIS_Msk (0x01UL << ETHERNET_DMA_STAT_NIS_Pos) /*!< ETHERNET DMA_STAT: NIS Mask */\r
-\r
-// ---------------------------------- ETHERNET_DMA_OP_MODE --------------------------------------\r
-#define ETHERNET_DMA_OP_MODE_SR_Pos 1 /*!< ETHERNET DMA_OP_MODE: SR Position */\r
-#define ETHERNET_DMA_OP_MODE_SR_Msk (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos) /*!< ETHERNET DMA_OP_MODE: SR Mask */\r
-#define ETHERNET_DMA_OP_MODE_OSF_Pos 2 /*!< ETHERNET DMA_OP_MODE: OSF Position */\r
-#define ETHERNET_DMA_OP_MODE_OSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos) /*!< ETHERNET DMA_OP_MODE: OSF Mask */\r
-#define ETHERNET_DMA_OP_MODE_RTC_Pos 3 /*!< ETHERNET DMA_OP_MODE: RTC Position */\r
-#define ETHERNET_DMA_OP_MODE_RTC_Msk (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos) /*!< ETHERNET DMA_OP_MODE: RTC Mask */\r
-#define ETHERNET_DMA_OP_MODE_FUF_Pos 6 /*!< ETHERNET DMA_OP_MODE: FUF Position */\r
-#define ETHERNET_DMA_OP_MODE_FUF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos) /*!< ETHERNET DMA_OP_MODE: FUF Mask */\r
-#define ETHERNET_DMA_OP_MODE_FEF_Pos 7 /*!< ETHERNET DMA_OP_MODE: FEF Position */\r
-#define ETHERNET_DMA_OP_MODE_FEF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos) /*!< ETHERNET DMA_OP_MODE: FEF Mask */\r
-#define ETHERNET_DMA_OP_MODE_ST_Pos 13 /*!< ETHERNET DMA_OP_MODE: ST Position */\r
-#define ETHERNET_DMA_OP_MODE_ST_Msk (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos) /*!< ETHERNET DMA_OP_MODE: ST Mask */\r
-#define ETHERNET_DMA_OP_MODE_TTC_Pos 14 /*!< ETHERNET DMA_OP_MODE: TTC Position */\r
-#define ETHERNET_DMA_OP_MODE_TTC_Msk (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos) /*!< ETHERNET DMA_OP_MODE: TTC Mask */\r
-#define ETHERNET_DMA_OP_MODE_FTF_Pos 20 /*!< ETHERNET DMA_OP_MODE: FTF Position */\r
-#define ETHERNET_DMA_OP_MODE_FTF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos) /*!< ETHERNET DMA_OP_MODE: FTF Mask */\r
-#define ETHERNET_DMA_OP_MODE_TSF_Pos 21 /*!< ETHERNET DMA_OP_MODE: TSF Position */\r
-#define ETHERNET_DMA_OP_MODE_TSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos) /*!< ETHERNET DMA_OP_MODE: TSF Mask */\r
-#define ETHERNET_DMA_OP_MODE_DFF_Pos 24 /*!< ETHERNET DMA_OP_MODE: DFF Position */\r
-#define ETHERNET_DMA_OP_MODE_DFF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos) /*!< ETHERNET DMA_OP_MODE: DFF Mask */\r
-#define ETHERNET_DMA_OP_MODE_RSF_Pos 25 /*!< ETHERNET DMA_OP_MODE: RSF Position */\r
-#define ETHERNET_DMA_OP_MODE_RSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos) /*!< ETHERNET DMA_OP_MODE: RSF Mask */\r
-#define ETHERNET_DMA_OP_MODE_DT_Pos 26 /*!< ETHERNET DMA_OP_MODE: DT Position */\r
-#define ETHERNET_DMA_OP_MODE_DT_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos) /*!< ETHERNET DMA_OP_MODE: DT Mask */\r
-\r
-// ----------------------------------- ETHERNET_DMA_INT_EN --------------------------------------\r
-#define ETHERNET_DMA_INT_EN_TIE_Pos 0 /*!< ETHERNET DMA_INT_EN: TIE Position */\r
-#define ETHERNET_DMA_INT_EN_TIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos) /*!< ETHERNET DMA_INT_EN: TIE Mask */\r
-#define ETHERNET_DMA_INT_EN_TSE_Pos 1 /*!< ETHERNET DMA_INT_EN: TSE Position */\r
-#define ETHERNET_DMA_INT_EN_TSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos) /*!< ETHERNET DMA_INT_EN: TSE Mask */\r
-#define ETHERNET_DMA_INT_EN_TUE_Pos 2 /*!< ETHERNET DMA_INT_EN: TUE Position */\r
-#define ETHERNET_DMA_INT_EN_TUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos) /*!< ETHERNET DMA_INT_EN: TUE Mask */\r
-#define ETHERNET_DMA_INT_EN_TJE_Pos 3 /*!< ETHERNET DMA_INT_EN: TJE Position */\r
-#define ETHERNET_DMA_INT_EN_TJE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos) /*!< ETHERNET DMA_INT_EN: TJE Mask */\r
-#define ETHERNET_DMA_INT_EN_OVE_Pos 4 /*!< ETHERNET DMA_INT_EN: OVE Position */\r
-#define ETHERNET_DMA_INT_EN_OVE_Msk (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos) /*!< ETHERNET DMA_INT_EN: OVE Mask */\r
-#define ETHERNET_DMA_INT_EN_UNE_Pos 5 /*!< ETHERNET DMA_INT_EN: UNE Position */\r
-#define ETHERNET_DMA_INT_EN_UNE_Msk (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos) /*!< ETHERNET DMA_INT_EN: UNE Mask */\r
-#define ETHERNET_DMA_INT_EN_RIE_Pos 6 /*!< ETHERNET DMA_INT_EN: RIE Position */\r
-#define ETHERNET_DMA_INT_EN_RIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos) /*!< ETHERNET DMA_INT_EN: RIE Mask */\r
-#define ETHERNET_DMA_INT_EN_RUE_Pos 7 /*!< ETHERNET DMA_INT_EN: RUE Position */\r
-#define ETHERNET_DMA_INT_EN_RUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos) /*!< ETHERNET DMA_INT_EN: RUE Mask */\r
-#define ETHERNET_DMA_INT_EN_RSE_Pos 8 /*!< ETHERNET DMA_INT_EN: RSE Position */\r
-#define ETHERNET_DMA_INT_EN_RSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos) /*!< ETHERNET DMA_INT_EN: RSE Mask */\r
-#define ETHERNET_DMA_INT_EN_RWE_Pos 9 /*!< ETHERNET DMA_INT_EN: RWE Position */\r
-#define ETHERNET_DMA_INT_EN_RWE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos) /*!< ETHERNET DMA_INT_EN: RWE Mask */\r
-#define ETHERNET_DMA_INT_EN_ETE_Pos 10 /*!< ETHERNET DMA_INT_EN: ETE Position */\r
-#define ETHERNET_DMA_INT_EN_ETE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos) /*!< ETHERNET DMA_INT_EN: ETE Mask */\r
-#define ETHERNET_DMA_INT_EN_FBE_Pos 13 /*!< ETHERNET DMA_INT_EN: FBE Position */\r
-#define ETHERNET_DMA_INT_EN_FBE_Msk (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos) /*!< ETHERNET DMA_INT_EN: FBE Mask */\r
-#define ETHERNET_DMA_INT_EN_ERE_Pos 14 /*!< ETHERNET DMA_INT_EN: ERE Position */\r
-#define ETHERNET_DMA_INT_EN_ERE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos) /*!< ETHERNET DMA_INT_EN: ERE Mask */\r
-#define ETHERNET_DMA_INT_EN_AIE_Pos 15 /*!< ETHERNET DMA_INT_EN: AIE Position */\r
-#define ETHERNET_DMA_INT_EN_AIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos) /*!< ETHERNET DMA_INT_EN: AIE Mask */\r
-#define ETHERNET_DMA_INT_EN_NIE_Pos 16 /*!< ETHERNET DMA_INT_EN: NIE Position */\r
-#define ETHERNET_DMA_INT_EN_NIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos) /*!< ETHERNET DMA_INT_EN: NIE Mask */\r
-\r
-// --------------------------------- ETHERNET_DMA_MFRM_BUFOF ------------------------------------\r
-#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos 0 /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */\r
-#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask */\r
-#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos 16 /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */\r
-#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask */\r
-#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos 17 /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */\r
-#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask */\r
-#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos 28 /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */\r
-#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask */\r
-\r
-// -------------------------------- ETHERNET_DMA_REC_INT_WDT ------------------------------------\r
-#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos 0 /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */\r
-#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos) /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */\r
-\r
-// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_DES ---------------------------------\r
-#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */\r
-#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */\r
-\r
-// ------------------------------ ETHERNET_DMA_CURHOST_REC_DES ----------------------------------\r
-#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */\r
-#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos) /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */\r
-\r
-// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_BUF ---------------------------------\r
-#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */\r
-#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */\r
-\r
-// ------------------------------ ETHERNET_DMA_CURHOST_REC_BUF ----------------------------------\r
-#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */\r
-#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos) /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- ATIMER Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------- ATIMER_DOWNCOUNTER ---------------------------------------\r
-#define ATIMER_DOWNCOUNTER_CVAL_Pos 0 /*!< ATIMER DOWNCOUNTER: CVAL Position */\r
-#define ATIMER_DOWNCOUNTER_CVAL_Msk (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos) /*!< ATIMER DOWNCOUNTER: CVAL Mask */\r
-\r
-// -------------------------------------- ATIMER_PRESET -----------------------------------------\r
-#define ATIMER_PRESET_PRESETVAL_Pos 0 /*!< ATIMER PRESET: PRESETVAL Position */\r
-#define ATIMER_PRESET_PRESETVAL_Msk (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos) /*!< ATIMER PRESET: PRESETVAL Mask */\r
-\r
-// -------------------------------------- ATIMER_CLR_EN -----------------------------------------\r
-#define ATIMER_CLR_EN_CLR_EN_Pos 0 /*!< ATIMER CLR_EN: CLR_EN Position */\r
-#define ATIMER_CLR_EN_CLR_EN_Msk (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos) /*!< ATIMER CLR_EN: CLR_EN Mask */\r
-\r
-// -------------------------------------- ATIMER_SET_EN -----------------------------------------\r
-#define ATIMER_SET_EN_SET_EN_Pos 0 /*!< ATIMER SET_EN: SET_EN Position */\r
-#define ATIMER_SET_EN_SET_EN_Msk (0x01UL << ATIMER_SET_EN_SET_EN_Pos) /*!< ATIMER SET_EN: SET_EN Mask */\r
-\r
-// -------------------------------------- ATIMER_STATUS -----------------------------------------\r
-#define ATIMER_STATUS_STAT_Pos 0 /*!< ATIMER STATUS: STAT Position */\r
-#define ATIMER_STATUS_STAT_Msk (0x01UL << ATIMER_STATUS_STAT_Pos) /*!< ATIMER STATUS: STAT Mask */\r
-\r
-// -------------------------------------- ATIMER_ENABLE -----------------------------------------\r
-#define ATIMER_ENABLE_EN_Pos 0 /*!< ATIMER ENABLE: EN Position */\r
-#define ATIMER_ENABLE_EN_Msk (0x01UL << ATIMER_ENABLE_EN_Pos) /*!< ATIMER ENABLE: EN Mask */\r
-\r
-// ------------------------------------- ATIMER_CLR_STAT ----------------------------------------\r
-#define ATIMER_CLR_STAT_CSTAT_Pos 0 /*!< ATIMER CLR_STAT: CSTAT Position */\r
-#define ATIMER_CLR_STAT_CSTAT_Msk (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos) /*!< ATIMER CLR_STAT: CSTAT Mask */\r
-\r
-// ------------------------------------- ATIMER_SET_STAT ----------------------------------------\r
-#define ATIMER_SET_STAT_SSTAT_Pos 0 /*!< ATIMER SET_STAT: SSTAT Position */\r
-#define ATIMER_SET_STAT_SSTAT_Msk (0x01UL << ATIMER_SET_STAT_SSTAT_Pos) /*!< ATIMER SET_STAT: SSTAT Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- REGFILE Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ------------------------------------ REGFILE_REGFILE0 ----------------------------------------\r
-#define REGFILE_REGFILE0_REGVAL_Pos 0 /*!< REGFILE REGFILE0: REGVAL Position */\r
-#define REGFILE_REGFILE0_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos) /*!< REGFILE REGFILE0: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE1 ----------------------------------------\r
-#define REGFILE_REGFILE1_REGVAL_Pos 0 /*!< REGFILE REGFILE1: REGVAL Position */\r
-#define REGFILE_REGFILE1_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos) /*!< REGFILE REGFILE1: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE2 ----------------------------------------\r
-#define REGFILE_REGFILE2_REGVAL_Pos 0 /*!< REGFILE REGFILE2: REGVAL Position */\r
-#define REGFILE_REGFILE2_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos) /*!< REGFILE REGFILE2: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE3 ----------------------------------------\r
-#define REGFILE_REGFILE3_REGVAL_Pos 0 /*!< REGFILE REGFILE3: REGVAL Position */\r
-#define REGFILE_REGFILE3_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos) /*!< REGFILE REGFILE3: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE4 ----------------------------------------\r
-#define REGFILE_REGFILE4_REGVAL_Pos 0 /*!< REGFILE REGFILE4: REGVAL Position */\r
-#define REGFILE_REGFILE4_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos) /*!< REGFILE REGFILE4: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE5 ----------------------------------------\r
-#define REGFILE_REGFILE5_REGVAL_Pos 0 /*!< REGFILE REGFILE5: REGVAL Position */\r
-#define REGFILE_REGFILE5_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos) /*!< REGFILE REGFILE5: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE6 ----------------------------------------\r
-#define REGFILE_REGFILE6_REGVAL_Pos 0 /*!< REGFILE REGFILE6: REGVAL Position */\r
-#define REGFILE_REGFILE6_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos) /*!< REGFILE REGFILE6: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE7 ----------------------------------------\r
-#define REGFILE_REGFILE7_REGVAL_Pos 0 /*!< REGFILE REGFILE7: REGVAL Position */\r
-#define REGFILE_REGFILE7_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos) /*!< REGFILE REGFILE7: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE8 ----------------------------------------\r
-#define REGFILE_REGFILE8_REGVAL_Pos 0 /*!< REGFILE REGFILE8: REGVAL Position */\r
-#define REGFILE_REGFILE8_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos) /*!< REGFILE REGFILE8: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE9 ----------------------------------------\r
-#define REGFILE_REGFILE9_REGVAL_Pos 0 /*!< REGFILE REGFILE9: REGVAL Position */\r
-#define REGFILE_REGFILE9_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos) /*!< REGFILE REGFILE9: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE10 ---------------------------------------\r
-#define REGFILE_REGFILE10_REGVAL_Pos 0 /*!< REGFILE REGFILE10: REGVAL Position */\r
-#define REGFILE_REGFILE10_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos) /*!< REGFILE REGFILE10: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE11 ---------------------------------------\r
-#define REGFILE_REGFILE11_REGVAL_Pos 0 /*!< REGFILE REGFILE11: REGVAL Position */\r
-#define REGFILE_REGFILE11_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos) /*!< REGFILE REGFILE11: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE12 ---------------------------------------\r
-#define REGFILE_REGFILE12_REGVAL_Pos 0 /*!< REGFILE REGFILE12: REGVAL Position */\r
-#define REGFILE_REGFILE12_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos) /*!< REGFILE REGFILE12: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE13 ---------------------------------------\r
-#define REGFILE_REGFILE13_REGVAL_Pos 0 /*!< REGFILE REGFILE13: REGVAL Position */\r
-#define REGFILE_REGFILE13_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos) /*!< REGFILE REGFILE13: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE14 ---------------------------------------\r
-#define REGFILE_REGFILE14_REGVAL_Pos 0 /*!< REGFILE REGFILE14: REGVAL Position */\r
-#define REGFILE_REGFILE14_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos) /*!< REGFILE REGFILE14: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE15 ---------------------------------------\r
-#define REGFILE_REGFILE15_REGVAL_Pos 0 /*!< REGFILE REGFILE15: REGVAL Position */\r
-#define REGFILE_REGFILE15_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos) /*!< REGFILE REGFILE15: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE16 ---------------------------------------\r
-#define REGFILE_REGFILE16_REGVAL_Pos 0 /*!< REGFILE REGFILE16: REGVAL Position */\r
-#define REGFILE_REGFILE16_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos) /*!< REGFILE REGFILE16: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE17 ---------------------------------------\r
-#define REGFILE_REGFILE17_REGVAL_Pos 0 /*!< REGFILE REGFILE17: REGVAL Position */\r
-#define REGFILE_REGFILE17_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos) /*!< REGFILE REGFILE17: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE18 ---------------------------------------\r
-#define REGFILE_REGFILE18_REGVAL_Pos 0 /*!< REGFILE REGFILE18: REGVAL Position */\r
-#define REGFILE_REGFILE18_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos) /*!< REGFILE REGFILE18: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE19 ---------------------------------------\r
-#define REGFILE_REGFILE19_REGVAL_Pos 0 /*!< REGFILE REGFILE19: REGVAL Position */\r
-#define REGFILE_REGFILE19_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos) /*!< REGFILE REGFILE19: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE20 ---------------------------------------\r
-#define REGFILE_REGFILE20_REGVAL_Pos 0 /*!< REGFILE REGFILE20: REGVAL Position */\r
-#define REGFILE_REGFILE20_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos) /*!< REGFILE REGFILE20: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE21 ---------------------------------------\r
-#define REGFILE_REGFILE21_REGVAL_Pos 0 /*!< REGFILE REGFILE21: REGVAL Position */\r
-#define REGFILE_REGFILE21_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos) /*!< REGFILE REGFILE21: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE22 ---------------------------------------\r
-#define REGFILE_REGFILE22_REGVAL_Pos 0 /*!< REGFILE REGFILE22: REGVAL Position */\r
-#define REGFILE_REGFILE22_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos) /*!< REGFILE REGFILE22: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE23 ---------------------------------------\r
-#define REGFILE_REGFILE23_REGVAL_Pos 0 /*!< REGFILE REGFILE23: REGVAL Position */\r
-#define REGFILE_REGFILE23_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos) /*!< REGFILE REGFILE23: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE24 ---------------------------------------\r
-#define REGFILE_REGFILE24_REGVAL_Pos 0 /*!< REGFILE REGFILE24: REGVAL Position */\r
-#define REGFILE_REGFILE24_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos) /*!< REGFILE REGFILE24: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE25 ---------------------------------------\r
-#define REGFILE_REGFILE25_REGVAL_Pos 0 /*!< REGFILE REGFILE25: REGVAL Position */\r
-#define REGFILE_REGFILE25_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos) /*!< REGFILE REGFILE25: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE26 ---------------------------------------\r
-#define REGFILE_REGFILE26_REGVAL_Pos 0 /*!< REGFILE REGFILE26: REGVAL Position */\r
-#define REGFILE_REGFILE26_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos) /*!< REGFILE REGFILE26: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE27 ---------------------------------------\r
-#define REGFILE_REGFILE27_REGVAL_Pos 0 /*!< REGFILE REGFILE27: REGVAL Position */\r
-#define REGFILE_REGFILE27_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos) /*!< REGFILE REGFILE27: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE28 ---------------------------------------\r
-#define REGFILE_REGFILE28_REGVAL_Pos 0 /*!< REGFILE REGFILE28: REGVAL Position */\r
-#define REGFILE_REGFILE28_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos) /*!< REGFILE REGFILE28: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE29 ---------------------------------------\r
-#define REGFILE_REGFILE29_REGVAL_Pos 0 /*!< REGFILE REGFILE29: REGVAL Position */\r
-#define REGFILE_REGFILE29_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos) /*!< REGFILE REGFILE29: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE30 ---------------------------------------\r
-#define REGFILE_REGFILE30_REGVAL_Pos 0 /*!< REGFILE REGFILE30: REGVAL Position */\r
-#define REGFILE_REGFILE30_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos) /*!< REGFILE REGFILE30: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE31 ---------------------------------------\r
-#define REGFILE_REGFILE31_REGVAL_Pos 0 /*!< REGFILE REGFILE31: REGVAL Position */\r
-#define REGFILE_REGFILE31_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos) /*!< REGFILE REGFILE31: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE32 ---------------------------------------\r
-#define REGFILE_REGFILE32_REGVAL_Pos 0 /*!< REGFILE REGFILE32: REGVAL Position */\r
-#define REGFILE_REGFILE32_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos) /*!< REGFILE REGFILE32: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE33 ---------------------------------------\r
-#define REGFILE_REGFILE33_REGVAL_Pos 0 /*!< REGFILE REGFILE33: REGVAL Position */\r
-#define REGFILE_REGFILE33_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos) /*!< REGFILE REGFILE33: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE34 ---------------------------------------\r
-#define REGFILE_REGFILE34_REGVAL_Pos 0 /*!< REGFILE REGFILE34: REGVAL Position */\r
-#define REGFILE_REGFILE34_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos) /*!< REGFILE REGFILE34: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE35 ---------------------------------------\r
-#define REGFILE_REGFILE35_REGVAL_Pos 0 /*!< REGFILE REGFILE35: REGVAL Position */\r
-#define REGFILE_REGFILE35_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos) /*!< REGFILE REGFILE35: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE36 ---------------------------------------\r
-#define REGFILE_REGFILE36_REGVAL_Pos 0 /*!< REGFILE REGFILE36: REGVAL Position */\r
-#define REGFILE_REGFILE36_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos) /*!< REGFILE REGFILE36: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE37 ---------------------------------------\r
-#define REGFILE_REGFILE37_REGVAL_Pos 0 /*!< REGFILE REGFILE37: REGVAL Position */\r
-#define REGFILE_REGFILE37_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos) /*!< REGFILE REGFILE37: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE38 ---------------------------------------\r
-#define REGFILE_REGFILE38_REGVAL_Pos 0 /*!< REGFILE REGFILE38: REGVAL Position */\r
-#define REGFILE_REGFILE38_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos) /*!< REGFILE REGFILE38: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE39 ---------------------------------------\r
-#define REGFILE_REGFILE39_REGVAL_Pos 0 /*!< REGFILE REGFILE39: REGVAL Position */\r
-#define REGFILE_REGFILE39_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos) /*!< REGFILE REGFILE39: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE40 ---------------------------------------\r
-#define REGFILE_REGFILE40_REGVAL_Pos 0 /*!< REGFILE REGFILE40: REGVAL Position */\r
-#define REGFILE_REGFILE40_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos) /*!< REGFILE REGFILE40: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE41 ---------------------------------------\r
-#define REGFILE_REGFILE41_REGVAL_Pos 0 /*!< REGFILE REGFILE41: REGVAL Position */\r
-#define REGFILE_REGFILE41_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos) /*!< REGFILE REGFILE41: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE42 ---------------------------------------\r
-#define REGFILE_REGFILE42_REGVAL_Pos 0 /*!< REGFILE REGFILE42: REGVAL Position */\r
-#define REGFILE_REGFILE42_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos) /*!< REGFILE REGFILE42: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE43 ---------------------------------------\r
-#define REGFILE_REGFILE43_REGVAL_Pos 0 /*!< REGFILE REGFILE43: REGVAL Position */\r
-#define REGFILE_REGFILE43_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos) /*!< REGFILE REGFILE43: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE44 ---------------------------------------\r
-#define REGFILE_REGFILE44_REGVAL_Pos 0 /*!< REGFILE REGFILE44: REGVAL Position */\r
-#define REGFILE_REGFILE44_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos) /*!< REGFILE REGFILE44: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE45 ---------------------------------------\r
-#define REGFILE_REGFILE45_REGVAL_Pos 0 /*!< REGFILE REGFILE45: REGVAL Position */\r
-#define REGFILE_REGFILE45_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos) /*!< REGFILE REGFILE45: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE46 ---------------------------------------\r
-#define REGFILE_REGFILE46_REGVAL_Pos 0 /*!< REGFILE REGFILE46: REGVAL Position */\r
-#define REGFILE_REGFILE46_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos) /*!< REGFILE REGFILE46: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE47 ---------------------------------------\r
-#define REGFILE_REGFILE47_REGVAL_Pos 0 /*!< REGFILE REGFILE47: REGVAL Position */\r
-#define REGFILE_REGFILE47_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos) /*!< REGFILE REGFILE47: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE48 ---------------------------------------\r
-#define REGFILE_REGFILE48_REGVAL_Pos 0 /*!< REGFILE REGFILE48: REGVAL Position */\r
-#define REGFILE_REGFILE48_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos) /*!< REGFILE REGFILE48: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE49 ---------------------------------------\r
-#define REGFILE_REGFILE49_REGVAL_Pos 0 /*!< REGFILE REGFILE49: REGVAL Position */\r
-#define REGFILE_REGFILE49_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos) /*!< REGFILE REGFILE49: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE50 ---------------------------------------\r
-#define REGFILE_REGFILE50_REGVAL_Pos 0 /*!< REGFILE REGFILE50: REGVAL Position */\r
-#define REGFILE_REGFILE50_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos) /*!< REGFILE REGFILE50: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE51 ---------------------------------------\r
-#define REGFILE_REGFILE51_REGVAL_Pos 0 /*!< REGFILE REGFILE51: REGVAL Position */\r
-#define REGFILE_REGFILE51_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos) /*!< REGFILE REGFILE51: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE52 ---------------------------------------\r
-#define REGFILE_REGFILE52_REGVAL_Pos 0 /*!< REGFILE REGFILE52: REGVAL Position */\r
-#define REGFILE_REGFILE52_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos) /*!< REGFILE REGFILE52: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE53 ---------------------------------------\r
-#define REGFILE_REGFILE53_REGVAL_Pos 0 /*!< REGFILE REGFILE53: REGVAL Position */\r
-#define REGFILE_REGFILE53_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos) /*!< REGFILE REGFILE53: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE54 ---------------------------------------\r
-#define REGFILE_REGFILE54_REGVAL_Pos 0 /*!< REGFILE REGFILE54: REGVAL Position */\r
-#define REGFILE_REGFILE54_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos) /*!< REGFILE REGFILE54: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE55 ---------------------------------------\r
-#define REGFILE_REGFILE55_REGVAL_Pos 0 /*!< REGFILE REGFILE55: REGVAL Position */\r
-#define REGFILE_REGFILE55_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos) /*!< REGFILE REGFILE55: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE56 ---------------------------------------\r
-#define REGFILE_REGFILE56_REGVAL_Pos 0 /*!< REGFILE REGFILE56: REGVAL Position */\r
-#define REGFILE_REGFILE56_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos) /*!< REGFILE REGFILE56: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE57 ---------------------------------------\r
-#define REGFILE_REGFILE57_REGVAL_Pos 0 /*!< REGFILE REGFILE57: REGVAL Position */\r
-#define REGFILE_REGFILE57_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos) /*!< REGFILE REGFILE57: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE58 ---------------------------------------\r
-#define REGFILE_REGFILE58_REGVAL_Pos 0 /*!< REGFILE REGFILE58: REGVAL Position */\r
-#define REGFILE_REGFILE58_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos) /*!< REGFILE REGFILE58: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE59 ---------------------------------------\r
-#define REGFILE_REGFILE59_REGVAL_Pos 0 /*!< REGFILE REGFILE59: REGVAL Position */\r
-#define REGFILE_REGFILE59_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos) /*!< REGFILE REGFILE59: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE60 ---------------------------------------\r
-#define REGFILE_REGFILE60_REGVAL_Pos 0 /*!< REGFILE REGFILE60: REGVAL Position */\r
-#define REGFILE_REGFILE60_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos) /*!< REGFILE REGFILE60: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE61 ---------------------------------------\r
-#define REGFILE_REGFILE61_REGVAL_Pos 0 /*!< REGFILE REGFILE61: REGVAL Position */\r
-#define REGFILE_REGFILE61_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos) /*!< REGFILE REGFILE61: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE62 ---------------------------------------\r
-#define REGFILE_REGFILE62_REGVAL_Pos 0 /*!< REGFILE REGFILE62: REGVAL Position */\r
-#define REGFILE_REGFILE62_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos) /*!< REGFILE REGFILE62: REGVAL Mask */\r
-\r
-// ------------------------------------ REGFILE_REGFILE63 ---------------------------------------\r
-#define REGFILE_REGFILE63_REGVAL_Pos 0 /*!< REGFILE REGFILE63: REGVAL Position */\r
-#define REGFILE_REGFILE63_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos) /*!< REGFILE REGFILE63: REGVAL Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- PMC Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------- PMC_PD0_SLEEP0_HW_ENA -------------------------------------\r
-#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos 0 /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */\r
-#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos) /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */\r
-\r
-// ----------------------------------- PMC_PD0_SLEEP0_MODE --------------------------------------\r
-#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos 0 /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */\r
-#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos) /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- CREG Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- CREG_IRCTRM ------------------------------------------\r
-#define CREG_IRCTRM_TRM_Pos 0 /*!< CREG IRCTRM: TRM Position */\r
-#define CREG_IRCTRM_TRM_Msk (0x00000fffUL << CREG_IRCTRM_TRM_Pos) /*!< CREG IRCTRM: TRM Mask */\r
-\r
-// --------------------------------------- CREG_CREG0 -------------------------------------------\r
-#define CREG_CREG0_EN1KHZ_Pos 0 /*!< CREG CREG0: EN1KHZ Position */\r
-#define CREG_CREG0_EN1KHZ_Msk (0x01UL << CREG_CREG0_EN1KHZ_Pos) /*!< CREG CREG0: EN1KHZ Mask */\r
-#define CREG_CREG0_EN32KHZ_Pos 1 /*!< CREG CREG0: EN32KHZ Position */\r
-#define CREG_CREG0_EN32KHZ_Msk (0x01UL << CREG_CREG0_EN32KHZ_Pos) /*!< CREG CREG0: EN32KHZ Mask */\r
-#define CREG_CREG0_RESET32KHZ_Pos 2 /*!< CREG CREG0: RESET32KHZ Position */\r
-#define CREG_CREG0_RESET32KHZ_Msk (0x01UL << CREG_CREG0_RESET32KHZ_Pos) /*!< CREG CREG0: RESET32KHZ Mask */\r
-#define CREG_CREG0_32KHZPD_Pos 3 /*!< CREG CREG0: 32KHZPD Position */\r
-#define CREG_CREG0_32KHZPD_Msk (0x01UL << CREG_CREG0_32KHZPD_Pos) /*!< CREG CREG0: 32KHZPD Mask */\r
-#define CREG_CREG0_USB0PHY_Pos 5 /*!< CREG CREG0: USB0PHY Position */\r
-#define CREG_CREG0_USB0PHY_Msk (0x01UL << CREG_CREG0_USB0PHY_Pos) /*!< CREG CREG0: USB0PHY Mask */\r
-#define CREG_CREG0_ALARMCTRL_Pos 6 /*!< CREG CREG0: ALARMCTRL Position */\r
-#define CREG_CREG0_ALARMCTRL_Msk (0x03UL << CREG_CREG0_ALARMCTRL_Pos) /*!< CREG CREG0: ALARMCTRL Mask */\r
-#define CREG_CREG0_BODLVL1_Pos 8 /*!< CREG CREG0: BODLVL1 Position */\r
-#define CREG_CREG0_BODLVL1_Msk (0x03UL << CREG_CREG0_BODLVL1_Pos) /*!< CREG CREG0: BODLVL1 Mask */\r
-#define CREG_CREG0_BODLVL2_Pos 10 /*!< CREG CREG0: BODLVL2 Position */\r
-#define CREG_CREG0_BODLVL2_Msk (0x03UL << CREG_CREG0_BODLVL2_Pos) /*!< CREG CREG0: BODLVL2 Mask */\r
-#define CREG_CREG0_WAKEUP0CTRL_Pos 14 /*!< CREG CREG0: WAKEUP0CTRL Position */\r
-#define CREG_CREG0_WAKEUP0CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos) /*!< CREG CREG0: WAKEUP0CTRL Mask */\r
-#define CREG_CREG0_WAKEUP1CTRL_Pos 16 /*!< CREG CREG0: WAKEUP1CTRL Position */\r
-#define CREG_CREG0_WAKEUP1CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos) /*!< CREG CREG0: WAKEUP1CTRL Mask */\r
-\r
-// --------------------------------------- CREG_PMUCON ------------------------------------------\r
-#define CREG_PMUCON_PWRCTRL_Pos 0 /*!< CREG PMUCON: PWRCTRL Position */\r
-#define CREG_PMUCON_PWRCTRL_Msk (0x000001ffUL << CREG_PMUCON_PWRCTRL_Pos) /*!< CREG PMUCON: PWRCTRL Mask */\r
-#define CREG_PMUCON_DYNAMICPWRCTRL_Pos 15 /*!< CREG PMUCON: DYNAMICPWRCTRL Position */\r
-#define CREG_PMUCON_DYNAMICPWRCTRL_Msk (0x01UL << CREG_PMUCON_DYNAMICPWRCTRL_Pos) /*!< CREG PMUCON: DYNAMICPWRCTRL Mask */\r
-\r
-// -------------------------------------- CREG_M3MEMMAP -----------------------------------------\r
-#define CREG_M3MEMMAP_M3MAP_Pos 12 /*!< CREG M3MEMMAP: M3MAP Position */\r
-#define CREG_M3MEMMAP_M3MAP_Msk (0x000fffffUL << CREG_M3MEMMAP_M3MAP_Pos) /*!< CREG M3MEMMAP: M3MAP Mask */\r
-\r
-// --------------------------------------- CREG_CREG5 -------------------------------------------\r
-#define CREG_CREG5_M3TAPSEL_Pos 6 /*!< CREG CREG5: M3TAPSEL Position */\r
-#define CREG_CREG5_M3TAPSEL_Msk (0x01UL << CREG_CREG5_M3TAPSEL_Pos) /*!< CREG CREG5: M3TAPSEL Mask */\r
-\r
-// --------------------------------------- CREG_DMAMUX ------------------------------------------\r
-#define CREG_DMAMUX_DMAMUXCH0_Pos 0 /*!< CREG DMAMUX: DMAMUXCH0 Position */\r
-#define CREG_DMAMUX_DMAMUXCH0_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos) /*!< CREG DMAMUX: DMAMUXCH0 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH1_Pos 2 /*!< CREG DMAMUX: DMAMUXCH1 Position */\r
-#define CREG_DMAMUX_DMAMUXCH1_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos) /*!< CREG DMAMUX: DMAMUXCH1 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH2_Pos 4 /*!< CREG DMAMUX: DMAMUXCH2 Position */\r
-#define CREG_DMAMUX_DMAMUXCH2_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos) /*!< CREG DMAMUX: DMAMUXCH2 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH3_Pos 6 /*!< CREG DMAMUX: DMAMUXCH3 Position */\r
-#define CREG_DMAMUX_DMAMUXCH3_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos) /*!< CREG DMAMUX: DMAMUXCH3 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH4_Pos 8 /*!< CREG DMAMUX: DMAMUXCH4 Position */\r
-#define CREG_DMAMUX_DMAMUXCH4_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos) /*!< CREG DMAMUX: DMAMUXCH4 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH5_Pos 10 /*!< CREG DMAMUX: DMAMUXCH5 Position */\r
-#define CREG_DMAMUX_DMAMUXCH5_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos) /*!< CREG DMAMUX: DMAMUXCH5 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH6_Pos 12 /*!< CREG DMAMUX: DMAMUXCH6 Position */\r
-#define CREG_DMAMUX_DMAMUXCH6_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos) /*!< CREG DMAMUX: DMAMUXCH6 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH7_Pos 14 /*!< CREG DMAMUX: DMAMUXCH7 Position */\r
-#define CREG_DMAMUX_DMAMUXCH7_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos) /*!< CREG DMAMUX: DMAMUXCH7 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH8_Pos 16 /*!< CREG DMAMUX: DMAMUXCH8 Position */\r
-#define CREG_DMAMUX_DMAMUXCH8_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos) /*!< CREG DMAMUX: DMAMUXCH8 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH9_Pos 18 /*!< CREG DMAMUX: DMAMUXCH9 Position */\r
-#define CREG_DMAMUX_DMAMUXCH9_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos) /*!< CREG DMAMUX: DMAMUXCH9 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH10_Pos 20 /*!< CREG DMAMUX: DMAMUXCH10 Position */\r
-#define CREG_DMAMUX_DMAMUXCH10_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos) /*!< CREG DMAMUX: DMAMUXCH10 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH11_Pos 22 /*!< CREG DMAMUX: DMAMUXCH11 Position */\r
-#define CREG_DMAMUX_DMAMUXCH11_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos) /*!< CREG DMAMUX: DMAMUXCH11 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH12_Pos 24 /*!< CREG DMAMUX: DMAMUXCH12 Position */\r
-#define CREG_DMAMUX_DMAMUXCH12_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos) /*!< CREG DMAMUX: DMAMUXCH12 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH13_Pos 26 /*!< CREG DMAMUX: DMAMUXCH13 Position */\r
-#define CREG_DMAMUX_DMAMUXCH13_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos) /*!< CREG DMAMUX: DMAMUXCH13 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH14_Pos 28 /*!< CREG DMAMUX: DMAMUXCH14 Position */\r
-#define CREG_DMAMUX_DMAMUXCH14_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos) /*!< CREG DMAMUX: DMAMUXCH14 Mask */\r
-#define CREG_DMAMUX_DMAMUXCH15_Pos 30 /*!< CREG DMAMUX: DMAMUXCH15 Position */\r
-#define CREG_DMAMUX_DMAMUXCH15_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos) /*!< CREG DMAMUX: DMAMUXCH15 Mask */\r
-\r
-// --------------------------------------- CREG_ETBCFG ------------------------------------------\r
-#define CREG_ETBCFG_ETB_Pos 0 /*!< CREG ETBCFG: ETB Position */\r
-#define CREG_ETBCFG_ETB_Msk (0x01UL << CREG_ETBCFG_ETB_Pos) /*!< CREG ETBCFG: ETB Mask */\r
-\r
-// --------------------------------------- CREG_CREG6 -------------------------------------------\r
-#define CREG_CREG6_ETHMODE_Pos 0 /*!< CREG CREG6: ETHMODE Position */\r
-#define CREG_CREG6_ETHMODE_Msk (0x07UL << CREG_CREG6_ETHMODE_Pos) /*!< CREG CREG6: ETHMODE Mask */\r
-#define CREG_CREG6_TIMCTRL_Pos 4 /*!< CREG CREG6: TIMCTRL Position */\r
-#define CREG_CREG6_TIMCTRL_Msk (0x01UL << CREG_CREG6_TIMCTRL_Pos) /*!< CREG CREG6: TIMCTRL Mask */\r
-#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos 12 /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */\r
-#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */\r
-#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos 13 /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */\r
-#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */\r
-#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos 14 /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */\r
-#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */\r
-#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos 15 /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */\r
-#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */\r
-#define CREG_CREG6_EMC_CLK_SEL_Pos 16 /*!< CREG CREG6: EMC_CLK_SEL Position */\r
-#define CREG_CREG6_EMC_CLK_SEL_Msk (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos) /*!< CREG CREG6: EMC_CLK_SEL Mask */\r
-\r
-// --------------------------------------- CREG_CHIPID ------------------------------------------\r
-#define CREG_CHIPID_ID_Pos 0 /*!< CREG CHIPID: ID Position */\r
-#define CREG_CHIPID_ID_Msk (0xffffffffUL << CREG_CHIPID_ID_Pos) /*!< CREG CHIPID: ID Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- EVENTROUTER Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ------------------------------------ EVENTROUTER_HILO ----------------------------------------\r
-#define EVENTROUTER_HILO_WAKEUP0_L_Pos 0 /*!< EVENTROUTER HILO: WAKEUP0_L Position */\r
-#define EVENTROUTER_HILO_WAKEUP0_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos) /*!< EVENTROUTER HILO: WAKEUP0_L Mask */\r
-#define EVENTROUTER_HILO_WAKEUP1_L_Pos 1 /*!< EVENTROUTER HILO: WAKEUP1_L Position */\r
-#define EVENTROUTER_HILO_WAKEUP1_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos) /*!< EVENTROUTER HILO: WAKEUP1_L Mask */\r
-#define EVENTROUTER_HILO_WAKEUP2_L_Pos 2 /*!< EVENTROUTER HILO: WAKEUP2_L Position */\r
-#define EVENTROUTER_HILO_WAKEUP2_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos) /*!< EVENTROUTER HILO: WAKEUP2_L Mask */\r
-#define EVENTROUTER_HILO_WAKEUP3_L_Pos 3 /*!< EVENTROUTER HILO: WAKEUP3_L Position */\r
-#define EVENTROUTER_HILO_WAKEUP3_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos) /*!< EVENTROUTER HILO: WAKEUP3_L Mask */\r
-#define EVENTROUTER_HILO_ATIMER_L_Pos 4 /*!< EVENTROUTER HILO: ATIMER_L Position */\r
-#define EVENTROUTER_HILO_ATIMER_L_Msk (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos) /*!< EVENTROUTER HILO: ATIMER_L Mask */\r
-#define EVENTROUTER_HILO_RTC_L_Pos 5 /*!< EVENTROUTER HILO: RTC_L Position */\r
-#define EVENTROUTER_HILO_RTC_L_Msk (0x01UL << EVENTROUTER_HILO_RTC_L_Pos) /*!< EVENTROUTER HILO: RTC_L Mask */\r
-#define EVENTROUTER_HILO_BOD_L_Pos 6 /*!< EVENTROUTER HILO: BOD_L Position */\r
-#define EVENTROUTER_HILO_BOD_L_Msk (0x01UL << EVENTROUTER_HILO_BOD_L_Pos) /*!< EVENTROUTER HILO: BOD_L Mask */\r
-#define EVENTROUTER_HILO_WWDT_L_Pos 7 /*!< EVENTROUTER HILO: WWDT_L Position */\r
-#define EVENTROUTER_HILO_WWDT_L_Msk (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos) /*!< EVENTROUTER HILO: WWDT_L Mask */\r
-#define EVENTROUTER_HILO_ETH_L_Pos 8 /*!< EVENTROUTER HILO: ETH_L Position */\r
-#define EVENTROUTER_HILO_ETH_L_Msk (0x01UL << EVENTROUTER_HILO_ETH_L_Pos) /*!< EVENTROUTER HILO: ETH_L Mask */\r
-#define EVENTROUTER_HILO_USB0_L_Pos 9 /*!< EVENTROUTER HILO: USB0_L Position */\r
-#define EVENTROUTER_HILO_USB0_L_Msk (0x01UL << EVENTROUTER_HILO_USB0_L_Pos) /*!< EVENTROUTER HILO: USB0_L Mask */\r
-#define EVENTROUTER_HILO_USB1_L_Pos 10 /*!< EVENTROUTER HILO: USB1_L Position */\r
-#define EVENTROUTER_HILO_USB1_L_Msk (0x01UL << EVENTROUTER_HILO_USB1_L_Pos) /*!< EVENTROUTER HILO: USB1_L Mask */\r
-#define EVENTROUTER_HILO_SDMMC_L_Pos 11 /*!< EVENTROUTER HILO: SDMMC_L Position */\r
-#define EVENTROUTER_HILO_SDMMC_L_Msk (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos) /*!< EVENTROUTER HILO: SDMMC_L Mask */\r
-#define EVENTROUTER_HILO_CAN_L_Pos 12 /*!< EVENTROUTER HILO: CAN_L Position */\r
-#define EVENTROUTER_HILO_CAN_L_Msk (0x01UL << EVENTROUTER_HILO_CAN_L_Pos) /*!< EVENTROUTER HILO: CAN_L Mask */\r
-#define EVENTROUTER_HILO_TIM2_L_Pos 13 /*!< EVENTROUTER HILO: TIM2_L Position */\r
-#define EVENTROUTER_HILO_TIM2_L_Msk (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos) /*!< EVENTROUTER HILO: TIM2_L Mask */\r
-#define EVENTROUTER_HILO_TIM6_L_Pos 14 /*!< EVENTROUTER HILO: TIM6_L Position */\r
-#define EVENTROUTER_HILO_TIM6_L_Msk (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos) /*!< EVENTROUTER HILO: TIM6_L Mask */\r
-#define EVENTROUTER_HILO_QEI_L_Pos 15 /*!< EVENTROUTER HILO: QEI_L Position */\r
-#define EVENTROUTER_HILO_QEI_L_Msk (0x01UL << EVENTROUTER_HILO_QEI_L_Pos) /*!< EVENTROUTER HILO: QEI_L Mask */\r
-#define EVENTROUTER_HILO_TIM14_L_Pos 16 /*!< EVENTROUTER HILO: TIM14_L Position */\r
-#define EVENTROUTER_HILO_TIM14_L_Msk (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos) /*!< EVENTROUTER HILO: TIM14_L Mask */\r
-#define EVENTROUTER_HILO_RESET_L_Pos 19 /*!< EVENTROUTER HILO: RESET_L Position */\r
-#define EVENTROUTER_HILO_RESET_L_Msk (0x01UL << EVENTROUTER_HILO_RESET_L_Pos) /*!< EVENTROUTER HILO: RESET_L Mask */\r
-\r
-// ------------------------------------ EVENTROUTER_EDGE ----------------------------------------\r
-#define EVENTROUTER_EDGE_WAKEUP0_E_Pos 0 /*!< EVENTROUTER EDGE: WAKEUP0_E Position */\r
-#define EVENTROUTER_EDGE_WAKEUP0_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP0_E Mask */\r
-#define EVENTROUTER_EDGE_WAKEUP1_E_Pos 1 /*!< EVENTROUTER EDGE: WAKEUP1_E Position */\r
-#define EVENTROUTER_EDGE_WAKEUP1_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP1_E Mask */\r
-#define EVENTROUTER_EDGE_WAKEUP2_E_Pos 2 /*!< EVENTROUTER EDGE: WAKEUP2_E Position */\r
-#define EVENTROUTER_EDGE_WAKEUP2_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP2_E Mask */\r
-#define EVENTROUTER_EDGE_WAKEUP3_E_Pos 3 /*!< EVENTROUTER EDGE: WAKEUP3_E Position */\r
-#define EVENTROUTER_EDGE_WAKEUP3_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP3_E Mask */\r
-#define EVENTROUTER_EDGE_ATIMER_E_Pos 4 /*!< EVENTROUTER EDGE: ATIMER_E Position */\r
-#define EVENTROUTER_EDGE_ATIMER_E_Msk (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos) /*!< EVENTROUTER EDGE: ATIMER_E Mask */\r
-#define EVENTROUTER_EDGE_RTC_E_Pos 5 /*!< EVENTROUTER EDGE: RTC_E Position */\r
-#define EVENTROUTER_EDGE_RTC_E_Msk (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos) /*!< EVENTROUTER EDGE: RTC_E Mask */\r
-#define EVENTROUTER_EDGE_BOD_E_Pos 6 /*!< EVENTROUTER EDGE: BOD_E Position */\r
-#define EVENTROUTER_EDGE_BOD_E_Msk (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos) /*!< EVENTROUTER EDGE: BOD_E Mask */\r
-#define EVENTROUTER_EDGE_WWDT_E_Pos 7 /*!< EVENTROUTER EDGE: WWDT_E Position */\r
-#define EVENTROUTER_EDGE_WWDT_E_Msk (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos) /*!< EVENTROUTER EDGE: WWDT_E Mask */\r
-#define EVENTROUTER_EDGE_ETH_E_Pos 8 /*!< EVENTROUTER EDGE: ETH_E Position */\r
-#define EVENTROUTER_EDGE_ETH_E_Msk (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos) /*!< EVENTROUTER EDGE: ETH_E Mask */\r
-#define EVENTROUTER_EDGE_USB0_E_Pos 9 /*!< EVENTROUTER EDGE: USB0_E Position */\r
-#define EVENTROUTER_EDGE_USB0_E_Msk (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos) /*!< EVENTROUTER EDGE: USB0_E Mask */\r
-#define EVENTROUTER_EDGE_USB1_E_Pos 10 /*!< EVENTROUTER EDGE: USB1_E Position */\r
-#define EVENTROUTER_EDGE_USB1_E_Msk (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos) /*!< EVENTROUTER EDGE: USB1_E Mask */\r
-#define EVENTROUTER_EDGE_SDMMC_E_Pos 11 /*!< EVENTROUTER EDGE: SDMMC_E Position */\r
-#define EVENTROUTER_EDGE_SDMMC_E_Msk (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos) /*!< EVENTROUTER EDGE: SDMMC_E Mask */\r
-#define EVENTROUTER_EDGE_CAN_E_Pos 12 /*!< EVENTROUTER EDGE: CAN_E Position */\r
-#define EVENTROUTER_EDGE_CAN_E_Msk (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos) /*!< EVENTROUTER EDGE: CAN_E Mask */\r
-#define EVENTROUTER_EDGE_TIM2_E_Pos 13 /*!< EVENTROUTER EDGE: TIM2_E Position */\r
-#define EVENTROUTER_EDGE_TIM2_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos) /*!< EVENTROUTER EDGE: TIM2_E Mask */\r
-#define EVENTROUTER_EDGE_TIM6_E_Pos 14 /*!< EVENTROUTER EDGE: TIM6_E Position */\r
-#define EVENTROUTER_EDGE_TIM6_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos) /*!< EVENTROUTER EDGE: TIM6_E Mask */\r
-#define EVENTROUTER_EDGE_QEI_E_Pos 15 /*!< EVENTROUTER EDGE: QEI_E Position */\r
-#define EVENTROUTER_EDGE_QEI_E_Msk (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos) /*!< EVENTROUTER EDGE: QEI_E Mask */\r
-#define EVENTROUTER_EDGE_TIM14_E_Pos 16 /*!< EVENTROUTER EDGE: TIM14_E Position */\r
-#define EVENTROUTER_EDGE_TIM14_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos) /*!< EVENTROUTER EDGE: TIM14_E Mask */\r
-#define EVENTROUTER_EDGE_RESET_E_Pos 19 /*!< EVENTROUTER EDGE: RESET_E Position */\r
-#define EVENTROUTER_EDGE_RESET_E_Msk (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos) /*!< EVENTROUTER EDGE: RESET_E Mask */\r
-\r
-// ----------------------------------- EVENTROUTER_CLR_EN ---------------------------------------\r
-#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos 0 /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos 1 /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos 2 /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos 3 /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos 4 /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos 5 /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos 6 /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos) /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos 7 /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos 8 /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos 9 /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos 10 /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos 11 /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos 12 /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos) /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos 13 /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos 14 /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos 15 /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos) /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos 16 /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */\r
-#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos 19 /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */\r
-#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */\r
-\r
-// ----------------------------------- EVENTROUTER_SET_EN ---------------------------------------\r
-#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos 0 /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */\r
-#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos 1 /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */\r
-#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos 2 /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */\r
-#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos 3 /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */\r
-#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos 4 /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */\r
-#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos) /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_RTC_SETEN_Pos 5 /*!< EVENTROUTER SET_EN: RTC_SETEN Position */\r
-#define EVENTROUTER_SET_EN_RTC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos) /*!< EVENTROUTER SET_EN: RTC_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_BOD_SETEN_Pos 6 /*!< EVENTROUTER SET_EN: BOD_SETEN Position */\r
-#define EVENTROUTER_SET_EN_BOD_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos) /*!< EVENTROUTER SET_EN: BOD_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos 7 /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */\r
-#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos) /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_ETH_SETEN_Pos 8 /*!< EVENTROUTER SET_EN: ETH_SETEN Position */\r
-#define EVENTROUTER_SET_EN_ETH_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos) /*!< EVENTROUTER SET_EN: ETH_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_USB0_SETEN_Pos 9 /*!< EVENTROUTER SET_EN: USB0_SETEN Position */\r
-#define EVENTROUTER_SET_EN_USB0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_USB1_SETEN_Pos 10 /*!< EVENTROUTER SET_EN: USB1_SETEN Position */\r
-#define EVENTROUTER_SET_EN_USB1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos 11 /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */\r
-#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos) /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_CAN_SETEN_Pos 12 /*!< EVENTROUTER SET_EN: CAN_SETEN Position */\r
-#define EVENTROUTER_SET_EN_CAN_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos) /*!< EVENTROUTER SET_EN: CAN_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos 13 /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */\r
-#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos 14 /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */\r
-#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_QEI_SETEN_Pos 15 /*!< EVENTROUTER SET_EN: QEI_SETEN Position */\r
-#define EVENTROUTER_SET_EN_QEI_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos) /*!< EVENTROUTER SET_EN: QEI_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos 16 /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */\r
-#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */\r
-#define EVENTROUTER_SET_EN_RESET_SETEN_Pos 19 /*!< EVENTROUTER SET_EN: RESET_SETEN Position */\r
-#define EVENTROUTER_SET_EN_RESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */\r
-\r
-// ----------------------------------- EVENTROUTER_STATUS ---------------------------------------\r
-#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos 0 /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */\r
-#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */\r
-#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos 1 /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */\r
-#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */\r
-#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos 2 /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */\r
-#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */\r
-#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos 3 /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */\r
-#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */\r
-#define EVENTROUTER_STATUS_ATIMER_ST_Pos 4 /*!< EVENTROUTER STATUS: ATIMER_ST Position */\r
-#define EVENTROUTER_STATUS_ATIMER_ST_Msk (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos) /*!< EVENTROUTER STATUS: ATIMER_ST Mask */\r
-#define EVENTROUTER_STATUS_RTC_ST_Pos 5 /*!< EVENTROUTER STATUS: RTC_ST Position */\r
-#define EVENTROUTER_STATUS_RTC_ST_Msk (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos) /*!< EVENTROUTER STATUS: RTC_ST Mask */\r
-#define EVENTROUTER_STATUS_BOD_ST_Pos 6 /*!< EVENTROUTER STATUS: BOD_ST Position */\r
-#define EVENTROUTER_STATUS_BOD_ST_Msk (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos) /*!< EVENTROUTER STATUS: BOD_ST Mask */\r
-#define EVENTROUTER_STATUS_WWDT_ST_Pos 7 /*!< EVENTROUTER STATUS: WWDT_ST Position */\r
-#define EVENTROUTER_STATUS_WWDT_ST_Msk (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos) /*!< EVENTROUTER STATUS: WWDT_ST Mask */\r
-#define EVENTROUTER_STATUS_ETH_ST_Pos 8 /*!< EVENTROUTER STATUS: ETH_ST Position */\r
-#define EVENTROUTER_STATUS_ETH_ST_Msk (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos) /*!< EVENTROUTER STATUS: ETH_ST Mask */\r
-#define EVENTROUTER_STATUS_USB0_ST_Pos 9 /*!< EVENTROUTER STATUS: USB0_ST Position */\r
-#define EVENTROUTER_STATUS_USB0_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos) /*!< EVENTROUTER STATUS: USB0_ST Mask */\r
-#define EVENTROUTER_STATUS_USB1_ST_Pos 10 /*!< EVENTROUTER STATUS: USB1_ST Position */\r
-#define EVENTROUTER_STATUS_USB1_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos) /*!< EVENTROUTER STATUS: USB1_ST Mask */\r
-#define EVENTROUTER_STATUS_SDMMC_ST_Pos 11 /*!< EVENTROUTER STATUS: SDMMC_ST Position */\r
-#define EVENTROUTER_STATUS_SDMMC_ST_Msk (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos) /*!< EVENTROUTER STATUS: SDMMC_ST Mask */\r
-#define EVENTROUTER_STATUS_CAN_ST_Pos 12 /*!< EVENTROUTER STATUS: CAN_ST Position */\r
-#define EVENTROUTER_STATUS_CAN_ST_Msk (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos) /*!< EVENTROUTER STATUS: CAN_ST Mask */\r
-#define EVENTROUTER_STATUS_TIM2_ST_Pos 13 /*!< EVENTROUTER STATUS: TIM2_ST Position */\r
-#define EVENTROUTER_STATUS_TIM2_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos) /*!< EVENTROUTER STATUS: TIM2_ST Mask */\r
-#define EVENTROUTER_STATUS_TIM6_ST_Pos 14 /*!< EVENTROUTER STATUS: TIM6_ST Position */\r
-#define EVENTROUTER_STATUS_TIM6_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos) /*!< EVENTROUTER STATUS: TIM6_ST Mask */\r
-#define EVENTROUTER_STATUS_QEI_ST_Pos 15 /*!< EVENTROUTER STATUS: QEI_ST Position */\r
-#define EVENTROUTER_STATUS_QEI_ST_Msk (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos) /*!< EVENTROUTER STATUS: QEI_ST Mask */\r
-#define EVENTROUTER_STATUS_TIM14_ST_Pos 16 /*!< EVENTROUTER STATUS: TIM14_ST Position */\r
-#define EVENTROUTER_STATUS_TIM14_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos) /*!< EVENTROUTER STATUS: TIM14_ST Mask */\r
-#define EVENTROUTER_STATUS_RESET_ST_Pos 19 /*!< EVENTROUTER STATUS: RESET_ST Position */\r
-#define EVENTROUTER_STATUS_RESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos) /*!< EVENTROUTER STATUS: RESET_ST Mask */\r
-\r
-// ----------------------------------- EVENTROUTER_ENABLE ---------------------------------------\r
-#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos 0 /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */\r
-#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */\r
-#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos 1 /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */\r
-#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */\r
-#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos 2 /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */\r
-#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */\r
-#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos 3 /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */\r
-#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */\r
-#define EVENTROUTER_ENABLE_ATIMER_EN_Pos 4 /*!< EVENTROUTER ENABLE: ATIMER_EN Position */\r
-#define EVENTROUTER_ENABLE_ATIMER_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos) /*!< EVENTROUTER ENABLE: ATIMER_EN Mask */\r
-#define EVENTROUTER_ENABLE_RTC_EN_Pos 5 /*!< EVENTROUTER ENABLE: RTC_EN Position */\r
-#define EVENTROUTER_ENABLE_RTC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos) /*!< EVENTROUTER ENABLE: RTC_EN Mask */\r
-#define EVENTROUTER_ENABLE_BOD_EN_Pos 6 /*!< EVENTROUTER ENABLE: BOD_EN Position */\r
-#define EVENTROUTER_ENABLE_BOD_EN_Msk (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos) /*!< EVENTROUTER ENABLE: BOD_EN Mask */\r
-#define EVENTROUTER_ENABLE_WWDT_EN_Pos 7 /*!< EVENTROUTER ENABLE: WWDT_EN Position */\r
-#define EVENTROUTER_ENABLE_WWDT_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos) /*!< EVENTROUTER ENABLE: WWDT_EN Mask */\r
-#define EVENTROUTER_ENABLE_ETH_EN_Pos 8 /*!< EVENTROUTER ENABLE: ETH_EN Position */\r
-#define EVENTROUTER_ENABLE_ETH_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos) /*!< EVENTROUTER ENABLE: ETH_EN Mask */\r
-#define EVENTROUTER_ENABLE_USB0_EN_Pos 9 /*!< EVENTROUTER ENABLE: USB0_EN Position */\r
-#define EVENTROUTER_ENABLE_USB0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos) /*!< EVENTROUTER ENABLE: USB0_EN Mask */\r
-#define EVENTROUTER_ENABLE_USB1_EN_Pos 10 /*!< EVENTROUTER ENABLE: USB1_EN Position */\r
-#define EVENTROUTER_ENABLE_USB1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos) /*!< EVENTROUTER ENABLE: USB1_EN Mask */\r
-#define EVENTROUTER_ENABLE_SDMMC_EN_Pos 11 /*!< EVENTROUTER ENABLE: SDMMC_EN Position */\r
-#define EVENTROUTER_ENABLE_SDMMC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos) /*!< EVENTROUTER ENABLE: SDMMC_EN Mask */\r
-#define EVENTROUTER_ENABLE_CAN_EN_Pos 12 /*!< EVENTROUTER ENABLE: CAN_EN Position */\r
-#define EVENTROUTER_ENABLE_CAN_EN_Msk (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos) /*!< EVENTROUTER ENABLE: CAN_EN Mask */\r
-#define EVENTROUTER_ENABLE_TIM2_EN_Pos 13 /*!< EVENTROUTER ENABLE: TIM2_EN Position */\r
-#define EVENTROUTER_ENABLE_TIM2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos) /*!< EVENTROUTER ENABLE: TIM2_EN Mask */\r
-#define EVENTROUTER_ENABLE_TIM6_EN_Pos 14 /*!< EVENTROUTER ENABLE: TIM6_EN Position */\r
-#define EVENTROUTER_ENABLE_TIM6_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos) /*!< EVENTROUTER ENABLE: TIM6_EN Mask */\r
-#define EVENTROUTER_ENABLE_QEI_EN_Pos 15 /*!< EVENTROUTER ENABLE: QEI_EN Position */\r
-#define EVENTROUTER_ENABLE_QEI_EN_Msk (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos) /*!< EVENTROUTER ENABLE: QEI_EN Mask */\r
-#define EVENTROUTER_ENABLE_TIM14_EN_Pos 16 /*!< EVENTROUTER ENABLE: TIM14_EN Position */\r
-#define EVENTROUTER_ENABLE_TIM14_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos) /*!< EVENTROUTER ENABLE: TIM14_EN Mask */\r
-#define EVENTROUTER_ENABLE_RESET_EN_Pos 19 /*!< EVENTROUTER ENABLE: RESET_EN Position */\r
-#define EVENTROUTER_ENABLE_RESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos) /*!< EVENTROUTER ENABLE: RESET_EN Mask */\r
-\r
-// ---------------------------------- EVENTROUTER_CLR_STAT --------------------------------------\r
-#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos 0 /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos 1 /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos 2 /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos 3 /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos 4 /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos 5 /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos 6 /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos 7 /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos 8 /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos 9 /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos 10 /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos 11 /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos 12 /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos 13 /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos 14 /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos 15 /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos 16 /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */\r
-#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos 19 /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */\r
-#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */\r
-\r
-// ---------------------------------- EVENTROUTER_SET_STAT --------------------------------------\r
-#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos 0 /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */\r
-#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos 1 /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */\r
-#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos 2 /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */\r
-#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos 3 /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */\r
-#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos 4 /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */\r
-#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos) /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_RTC_SETST_Pos 5 /*!< EVENTROUTER SET_STAT: RTC_SETST Position */\r
-#define EVENTROUTER_SET_STAT_RTC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos) /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_BOD_SETST_Pos 6 /*!< EVENTROUTER SET_STAT: BOD_SETST Position */\r
-#define EVENTROUTER_SET_STAT_BOD_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos) /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos 7 /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */\r
-#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos) /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_ETH_SETST_Pos 8 /*!< EVENTROUTER SET_STAT: ETH_SETST Position */\r
-#define EVENTROUTER_SET_STAT_ETH_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos) /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_USB0_SETST_Pos 9 /*!< EVENTROUTER SET_STAT: USB0_SETST Position */\r
-#define EVENTROUTER_SET_STAT_USB0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_USB1_SETST_Pos 10 /*!< EVENTROUTER SET_STAT: USB1_SETST Position */\r
-#define EVENTROUTER_SET_STAT_USB1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos 11 /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */\r
-#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos) /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_CAN_SETST_Pos 12 /*!< EVENTROUTER SET_STAT: CAN_SETST Position */\r
-#define EVENTROUTER_SET_STAT_CAN_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos) /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos 13 /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */\r
-#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos 14 /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */\r
-#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_QEI_SETST_Pos 15 /*!< EVENTROUTER SET_STAT: QEI_SETST Position */\r
-#define EVENTROUTER_SET_STAT_QEI_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos) /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos 16 /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */\r
-#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */\r
-#define EVENTROUTER_SET_STAT_RESET_SETST_Pos 19 /*!< EVENTROUTER SET_STAT: RESET_SETST Position */\r
-#define EVENTROUTER_SET_STAT_RESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- RTC Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------- RTC_ILR --------------------------------------------\r
-#define RTC_ILR_RTCCIF_Pos 0 /*!< RTC ILR: RTCCIF Position */\r
-#define RTC_ILR_RTCCIF_Msk (0x01UL << RTC_ILR_RTCCIF_Pos) /*!< RTC ILR: RTCCIF Mask */\r
-#define RTC_ILR_RTCALF_Pos 1 /*!< RTC ILR: RTCALF Position */\r
-#define RTC_ILR_RTCALF_Msk (0x01UL << RTC_ILR_RTCALF_Pos) /*!< RTC ILR: RTCALF Mask */\r
-\r
-// ----------------------------------------- RTC_CCR --------------------------------------------\r
-#define RTC_CCR_CLKEN_Pos 0 /*!< RTC CCR: CLKEN Position */\r
-#define RTC_CCR_CLKEN_Msk (0x01UL << RTC_CCR_CLKEN_Pos) /*!< RTC CCR: CLKEN Mask */\r
-#define RTC_CCR_CTCRST_Pos 1 /*!< RTC CCR: CTCRST Position */\r
-#define RTC_CCR_CTCRST_Msk (0x01UL << RTC_CCR_CTCRST_Pos) /*!< RTC CCR: CTCRST Mask */\r
-#define RTC_CCR_CCALEN_Pos 4 /*!< RTC CCR: CCALEN Position */\r
-#define RTC_CCR_CCALEN_Msk (0x01UL << RTC_CCR_CCALEN_Pos) /*!< RTC CCR: CCALEN Mask */\r
-\r
-// ---------------------------------------- RTC_CIIR --------------------------------------------\r
-#define RTC_CIIR_IMSEC_Pos 0 /*!< RTC CIIR: IMSEC Position */\r
-#define RTC_CIIR_IMSEC_Msk (0x01UL << RTC_CIIR_IMSEC_Pos) /*!< RTC CIIR: IMSEC Mask */\r
-#define RTC_CIIR_IMMIN_Pos 1 /*!< RTC CIIR: IMMIN Position */\r
-#define RTC_CIIR_IMMIN_Msk (0x01UL << RTC_CIIR_IMMIN_Pos) /*!< RTC CIIR: IMMIN Mask */\r
-#define RTC_CIIR_IMHOUR_Pos 2 /*!< RTC CIIR: IMHOUR Position */\r
-#define RTC_CIIR_IMHOUR_Msk (0x01UL << RTC_CIIR_IMHOUR_Pos) /*!< RTC CIIR: IMHOUR Mask */\r
-#define RTC_CIIR_IMDOM_Pos 3 /*!< RTC CIIR: IMDOM Position */\r
-#define RTC_CIIR_IMDOM_Msk (0x01UL << RTC_CIIR_IMDOM_Pos) /*!< RTC CIIR: IMDOM Mask */\r
-#define RTC_CIIR_IMDOW_Pos 4 /*!< RTC CIIR: IMDOW Position */\r
-#define RTC_CIIR_IMDOW_Msk (0x01UL << RTC_CIIR_IMDOW_Pos) /*!< RTC CIIR: IMDOW Mask */\r
-#define RTC_CIIR_IMDOY_Pos 5 /*!< RTC CIIR: IMDOY Position */\r
-#define RTC_CIIR_IMDOY_Msk (0x01UL << RTC_CIIR_IMDOY_Pos) /*!< RTC CIIR: IMDOY Mask */\r
-#define RTC_CIIR_IMMON_Pos 6 /*!< RTC CIIR: IMMON Position */\r
-#define RTC_CIIR_IMMON_Msk (0x01UL << RTC_CIIR_IMMON_Pos) /*!< RTC CIIR: IMMON Mask */\r
-#define RTC_CIIR_IMYEAR_Pos 7 /*!< RTC CIIR: IMYEAR Position */\r
-#define RTC_CIIR_IMYEAR_Msk (0x01UL << RTC_CIIR_IMYEAR_Pos) /*!< RTC CIIR: IMYEAR Mask */\r
-\r
-// ----------------------------------------- RTC_AMR --------------------------------------------\r
-#define RTC_AMR_AMRSEC_Pos 0 /*!< RTC AMR: AMRSEC Position */\r
-#define RTC_AMR_AMRSEC_Msk (0x01UL << RTC_AMR_AMRSEC_Pos) /*!< RTC AMR: AMRSEC Mask */\r
-#define RTC_AMR_AMRMIN_Pos 1 /*!< RTC AMR: AMRMIN Position */\r
-#define RTC_AMR_AMRMIN_Msk (0x01UL << RTC_AMR_AMRMIN_Pos) /*!< RTC AMR: AMRMIN Mask */\r
-#define RTC_AMR_AMRHOUR_Pos 2 /*!< RTC AMR: AMRHOUR Position */\r
-#define RTC_AMR_AMRHOUR_Msk (0x01UL << RTC_AMR_AMRHOUR_Pos) /*!< RTC AMR: AMRHOUR Mask */\r
-#define RTC_AMR_AMRDOM_Pos 3 /*!< RTC AMR: AMRDOM Position */\r
-#define RTC_AMR_AMRDOM_Msk (0x01UL << RTC_AMR_AMRDOM_Pos) /*!< RTC AMR: AMRDOM Mask */\r
-#define RTC_AMR_AMRDOW_Pos 4 /*!< RTC AMR: AMRDOW Position */\r
-#define RTC_AMR_AMRDOW_Msk (0x01UL << RTC_AMR_AMRDOW_Pos) /*!< RTC AMR: AMRDOW Mask */\r
-#define RTC_AMR_AMRDOY_Pos 5 /*!< RTC AMR: AMRDOY Position */\r
-#define RTC_AMR_AMRDOY_Msk (0x01UL << RTC_AMR_AMRDOY_Pos) /*!< RTC AMR: AMRDOY Mask */\r
-#define RTC_AMR_AMRMON_Pos 6 /*!< RTC AMR: AMRMON Position */\r
-#define RTC_AMR_AMRMON_Msk (0x01UL << RTC_AMR_AMRMON_Pos) /*!< RTC AMR: AMRMON Mask */\r
-#define RTC_AMR_AMRYEAR_Pos 7 /*!< RTC AMR: AMRYEAR Position */\r
-#define RTC_AMR_AMRYEAR_Msk (0x01UL << RTC_AMR_AMRYEAR_Pos) /*!< RTC AMR: AMRYEAR Mask */\r
-\r
-// --------------------------------------- RTC_CTIME0 -------------------------------------------\r
-#define RTC_CTIME0_SECONDS_Pos 0 /*!< RTC CTIME0: SECONDS Position */\r
-#define RTC_CTIME0_SECONDS_Msk (0x3fUL << RTC_CTIME0_SECONDS_Pos) /*!< RTC CTIME0: SECONDS Mask */\r
-#define RTC_CTIME0_MINUTES_Pos 8 /*!< RTC CTIME0: MINUTES Position */\r
-#define RTC_CTIME0_MINUTES_Msk (0x3fUL << RTC_CTIME0_MINUTES_Pos) /*!< RTC CTIME0: MINUTES Mask */\r
-#define RTC_CTIME0_HOURS_Pos 16 /*!< RTC CTIME0: HOURS Position */\r
-#define RTC_CTIME0_HOURS_Msk (0x1fUL << RTC_CTIME0_HOURS_Pos) /*!< RTC CTIME0: HOURS Mask */\r
-#define RTC_CTIME0_DOW_Pos 24 /*!< RTC CTIME0: DOW Position */\r
-#define RTC_CTIME0_DOW_Msk (0x07UL << RTC_CTIME0_DOW_Pos) /*!< RTC CTIME0: DOW Mask */\r
-\r
-// --------------------------------------- RTC_CTIME1 -------------------------------------------\r
-#define RTC_CTIME1_DOM_Pos 0 /*!< RTC CTIME1: DOM Position */\r
-#define RTC_CTIME1_DOM_Msk (0x1fUL << RTC_CTIME1_DOM_Pos) /*!< RTC CTIME1: DOM Mask */\r
-#define RTC_CTIME1_MONTH_Pos 8 /*!< RTC CTIME1: MONTH Position */\r
-#define RTC_CTIME1_MONTH_Msk (0x0fUL << RTC_CTIME1_MONTH_Pos) /*!< RTC CTIME1: MONTH Mask */\r
-#define RTC_CTIME1_YEAR_Pos 16 /*!< RTC CTIME1: YEAR Position */\r
-#define RTC_CTIME1_YEAR_Msk (0x00000fffUL << RTC_CTIME1_YEAR_Pos) /*!< RTC CTIME1: YEAR Mask */\r
-\r
-// --------------------------------------- RTC_CTIME2 -------------------------------------------\r
-#define RTC_CTIME2_DOY_Pos 0 /*!< RTC CTIME2: DOY Position */\r
-#define RTC_CTIME2_DOY_Msk (0x00000fffUL << RTC_CTIME2_DOY_Pos) /*!< RTC CTIME2: DOY Mask */\r
-\r
-// ----------------------------------------- RTC_SEC --------------------------------------------\r
-#define RTC_SEC_SECONDS_Pos 0 /*!< RTC SEC: SECONDS Position */\r
-#define RTC_SEC_SECONDS_Msk (0x3fUL << RTC_SEC_SECONDS_Pos) /*!< RTC SEC: SECONDS Mask */\r
-\r
-// ----------------------------------------- RTC_MIN --------------------------------------------\r
-#define RTC_MIN_MINUTES_Pos 0 /*!< RTC MIN: MINUTES Position */\r
-#define RTC_MIN_MINUTES_Msk (0x3fUL << RTC_MIN_MINUTES_Pos) /*!< RTC MIN: MINUTES Mask */\r
-\r
-// ----------------------------------------- RTC_HRS --------------------------------------------\r
-#define RTC_HRS_HOURS_Pos 0 /*!< RTC HRS: HOURS Position */\r
-#define RTC_HRS_HOURS_Msk (0x1fUL << RTC_HRS_HOURS_Pos) /*!< RTC HRS: HOURS Mask */\r
-\r
-// ----------------------------------------- RTC_DOM --------------------------------------------\r
-#define RTC_DOM_DOM_Pos 0 /*!< RTC DOM: DOM Position */\r
-#define RTC_DOM_DOM_Msk (0x1fUL << RTC_DOM_DOM_Pos) /*!< RTC DOM: DOM Mask */\r
-\r
-// ----------------------------------------- RTC_DOW --------------------------------------------\r
-#define RTC_DOW_DOW_Pos 0 /*!< RTC DOW: DOW Position */\r
-#define RTC_DOW_DOW_Msk (0x07UL << RTC_DOW_DOW_Pos) /*!< RTC DOW: DOW Mask */\r
-\r
-// ----------------------------------------- RTC_DOY --------------------------------------------\r
-#define RTC_DOY_DOY_Pos 0 /*!< RTC DOY: DOY Position */\r
-#define RTC_DOY_DOY_Msk (0x000001ffUL << RTC_DOY_DOY_Pos) /*!< RTC DOY: DOY Mask */\r
-\r
-// ---------------------------------------- RTC_MONTH -------------------------------------------\r
-#define RTC_MONTH_MONTH_Pos 0 /*!< RTC MONTH: MONTH Position */\r
-#define RTC_MONTH_MONTH_Msk (0x0fUL << RTC_MONTH_MONTH_Pos) /*!< RTC MONTH: MONTH Mask */\r
-\r
-// ---------------------------------------- RTC_YEAR --------------------------------------------\r
-#define RTC_YEAR_YEAR_Pos 0 /*!< RTC YEAR: YEAR Position */\r
-#define RTC_YEAR_YEAR_Msk (0x00000fffUL << RTC_YEAR_YEAR_Pos) /*!< RTC YEAR: YEAR Mask */\r
-\r
-// ------------------------------------- RTC_CALIBRATION ----------------------------------------\r
-#define RTC_CALIBRATION_CALVAL_Pos 0 /*!< RTC CALIBRATION: CALVAL Position */\r
-#define RTC_CALIBRATION_CALVAL_Msk (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos) /*!< RTC CALIBRATION: CALVAL Mask */\r
-#define RTC_CALIBRATION_CALDIR_Pos 17 /*!< RTC CALIBRATION: CALDIR Position */\r
-#define RTC_CALIBRATION_CALDIR_Msk (0x01UL << RTC_CALIBRATION_CALDIR_Pos) /*!< RTC CALIBRATION: CALDIR Mask */\r
-\r
-// ---------------------------------------- RTC_ASEC --------------------------------------------\r
-#define RTC_ASEC_SECONDS_Pos 0 /*!< RTC ASEC: SECONDS Position */\r
-#define RTC_ASEC_SECONDS_Msk (0x3fUL << RTC_ASEC_SECONDS_Pos) /*!< RTC ASEC: SECONDS Mask */\r
-\r
-// ---------------------------------------- RTC_AMIN --------------------------------------------\r
-#define RTC_AMIN_MINUTES_Pos 0 /*!< RTC AMIN: MINUTES Position */\r
-#define RTC_AMIN_MINUTES_Msk (0x3fUL << RTC_AMIN_MINUTES_Pos) /*!< RTC AMIN: MINUTES Mask */\r
-\r
-// ---------------------------------------- RTC_AHRS --------------------------------------------\r
-#define RTC_AHRS_HOURS_Pos 0 /*!< RTC AHRS: HOURS Position */\r
-#define RTC_AHRS_HOURS_Msk (0x1fUL << RTC_AHRS_HOURS_Pos) /*!< RTC AHRS: HOURS Mask */\r
-\r
-// ---------------------------------------- RTC_ADOM --------------------------------------------\r
-#define RTC_ADOM_DOM_Pos 0 /*!< RTC ADOM: DOM Position */\r
-#define RTC_ADOM_DOM_Msk (0x1fUL << RTC_ADOM_DOM_Pos) /*!< RTC ADOM: DOM Mask */\r
-\r
-// ---------------------------------------- RTC_ADOW --------------------------------------------\r
-#define RTC_ADOW_DOW_Pos 0 /*!< RTC ADOW: DOW Position */\r
-#define RTC_ADOW_DOW_Msk (0x07UL << RTC_ADOW_DOW_Pos) /*!< RTC ADOW: DOW Mask */\r
-\r
-// ---------------------------------------- RTC_ADOY --------------------------------------------\r
-#define RTC_ADOY_DOY_Pos 0 /*!< RTC ADOY: DOY Position */\r
-#define RTC_ADOY_DOY_Msk (0x000001ffUL << RTC_ADOY_DOY_Pos) /*!< RTC ADOY: DOY Mask */\r
-\r
-// ---------------------------------------- RTC_AMON --------------------------------------------\r
-#define RTC_AMON_MONTH_Pos 0 /*!< RTC AMON: MONTH Position */\r
-#define RTC_AMON_MONTH_Msk (0x0fUL << RTC_AMON_MONTH_Pos) /*!< RTC AMON: MONTH Mask */\r
-\r
-// ---------------------------------------- RTC_AYRS --------------------------------------------\r
-#define RTC_AYRS_YEAR_Pos 0 /*!< RTC AYRS: YEAR Position */\r
-#define RTC_AYRS_YEAR_Msk (0x00000fffUL << RTC_AYRS_YEAR_Pos) /*!< RTC AYRS: YEAR Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- CGU Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// -------------------------------------- CGU_FREQ_MON ------------------------------------------\r
-#define CGU_FREQ_MON_RCNT_Pos 0 /*!< CGU FREQ_MON: RCNT Position */\r
-#define CGU_FREQ_MON_RCNT_Msk (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos) /*!< CGU FREQ_MON: RCNT Mask */\r
-#define CGU_FREQ_MON_FCNT_Pos 9 /*!< CGU FREQ_MON: FCNT Position */\r
-#define CGU_FREQ_MON_FCNT_Msk (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos) /*!< CGU FREQ_MON: FCNT Mask */\r
-#define CGU_FREQ_MON_MEAS_Pos 23 /*!< CGU FREQ_MON: MEAS Position */\r
-#define CGU_FREQ_MON_MEAS_Msk (0x01UL << CGU_FREQ_MON_MEAS_Pos) /*!< CGU FREQ_MON: MEAS Mask */\r
-#define CGU_FREQ_MON_CLK_SEL_Pos 24 /*!< CGU FREQ_MON: CLK_SEL Position */\r
-#define CGU_FREQ_MON_CLK_SEL_Msk (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos) /*!< CGU FREQ_MON: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_XTAL_OSC_CTRL ---------------------------------------\r
-#define CGU_XTAL_OSC_CTRL_ENABLE_Pos 0 /*!< CGU XTAL_OSC_CTRL: ENABLE Position */\r
-#define CGU_XTAL_OSC_CTRL_ENABLE_Msk (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos) /*!< CGU XTAL_OSC_CTRL: ENABLE Mask */\r
-#define CGU_XTAL_OSC_CTRL_BYPASS_Pos 1 /*!< CGU XTAL_OSC_CTRL: BYPASS Position */\r
-#define CGU_XTAL_OSC_CTRL_BYPASS_Msk (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos) /*!< CGU XTAL_OSC_CTRL: BYPASS Mask */\r
-#define CGU_XTAL_OSC_CTRL_HF_Pos 2 /*!< CGU XTAL_OSC_CTRL: HF Position */\r
-#define CGU_XTAL_OSC_CTRL_HF_Msk (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos) /*!< CGU XTAL_OSC_CTRL: HF Mask */\r
-\r
-// ------------------------------------ CGU_PLL0USB_STAT ----------------------------------------\r
-#define CGU_PLL0USB_STAT_LOCK_Pos 0 /*!< CGU PLL0USB_STAT: LOCK Position */\r
-#define CGU_PLL0USB_STAT_LOCK_Msk (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos) /*!< CGU PLL0USB_STAT: LOCK Mask */\r
-#define CGU_PLL0USB_STAT_FR_Pos 1 /*!< CGU PLL0USB_STAT: FR Position */\r
-#define CGU_PLL0USB_STAT_FR_Msk (0x01UL << CGU_PLL0USB_STAT_FR_Pos) /*!< CGU PLL0USB_STAT: FR Mask */\r
-\r
-// ------------------------------------ CGU_PLL0USB_CTRL ----------------------------------------\r
-#define CGU_PLL0USB_CTRL_PD_Pos 0 /*!< CGU PLL0USB_CTRL: PD Position */\r
-#define CGU_PLL0USB_CTRL_PD_Msk (0x01UL << CGU_PLL0USB_CTRL_PD_Pos) /*!< CGU PLL0USB_CTRL: PD Mask */\r
-#define CGU_PLL0USB_CTRL_BYPASS_Pos 1 /*!< CGU PLL0USB_CTRL: BYPASS Position */\r
-#define CGU_PLL0USB_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos) /*!< CGU PLL0USB_CTRL: BYPASS Mask */\r
-#define CGU_PLL0USB_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0USB_CTRL: DIRECTI Position */\r
-#define CGU_PLL0USB_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos) /*!< CGU PLL0USB_CTRL: DIRECTI Mask */\r
-#define CGU_PLL0USB_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0USB_CTRL: DIRECTO Position */\r
-#define CGU_PLL0USB_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos) /*!< CGU PLL0USB_CTRL: DIRECTO Mask */\r
-#define CGU_PLL0USB_CTRL_CLKEN_Pos 4 /*!< CGU PLL0USB_CTRL: CLKEN Position */\r
-#define CGU_PLL0USB_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos) /*!< CGU PLL0USB_CTRL: CLKEN Mask */\r
-#define CGU_PLL0USB_CTRL_FRM_Pos 6 /*!< CGU PLL0USB_CTRL: FRM Position */\r
-#define CGU_PLL0USB_CTRL_FRM_Msk (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos) /*!< CGU PLL0USB_CTRL: FRM Mask */\r
-#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */\r
-#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask */\r
-#define CGU_PLL0USB_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0USB_CTRL: CLK_SEL Position */\r
-#define CGU_PLL0USB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos) /*!< CGU PLL0USB_CTRL: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_PLL0USB_MDIV ----------------------------------------\r
-#define CGU_PLL0USB_MDIV_MDEC_Pos 0 /*!< CGU PLL0USB_MDIV: MDEC Position */\r
-#define CGU_PLL0USB_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos) /*!< CGU PLL0USB_MDIV: MDEC Mask */\r
-#define CGU_PLL0USB_MDIV_SELP_Pos 17 /*!< CGU PLL0USB_MDIV: SELP Position */\r
-#define CGU_PLL0USB_MDIV_SELP_Msk (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos) /*!< CGU PLL0USB_MDIV: SELP Mask */\r
-#define CGU_PLL0USB_MDIV_SELI_Pos 22 /*!< CGU PLL0USB_MDIV: SELI Position */\r
-#define CGU_PLL0USB_MDIV_SELI_Msk (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos) /*!< CGU PLL0USB_MDIV: SELI Mask */\r
-#define CGU_PLL0USB_MDIV_SELR_Pos 28 /*!< CGU PLL0USB_MDIV: SELR Position */\r
-#define CGU_PLL0USB_MDIV_SELR_Msk (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos) /*!< CGU PLL0USB_MDIV: SELR Mask */\r
-\r
-// ----------------------------------- CGU_PLL0USB_NP_DIV ---------------------------------------\r
-#define CGU_PLL0USB_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0USB_NP_DIV: PDEC Position */\r
-#define CGU_PLL0USB_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos) /*!< CGU PLL0USB_NP_DIV: PDEC Mask */\r
-#define CGU_PLL0USB_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0USB_NP_DIV: NDEC Position */\r
-#define CGU_PLL0USB_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos) /*!< CGU PLL0USB_NP_DIV: NDEC Mask */\r
-\r
-// ----------------------------------- CGU_PLL0AUDIO_STAT ---------------------------------------\r
-#define CGU_PLL0AUDIO_STAT_LOCK_Pos 0 /*!< CGU PLL0AUDIO_STAT: LOCK Position */\r
-#define CGU_PLL0AUDIO_STAT_LOCK_Msk (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos) /*!< CGU PLL0AUDIO_STAT: LOCK Mask */\r
-#define CGU_PLL0AUDIO_STAT_FR_Pos 1 /*!< CGU PLL0AUDIO_STAT: FR Position */\r
-#define CGU_PLL0AUDIO_STAT_FR_Msk (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos) /*!< CGU PLL0AUDIO_STAT: FR Mask */\r
-\r
-// ----------------------------------- CGU_PLL0AUDIO_CTRL ---------------------------------------\r
-#define CGU_PLL0AUDIO_CTRL_PD_Pos 0 /*!< CGU PLL0AUDIO_CTRL: PD Position */\r
-#define CGU_PLL0AUDIO_CTRL_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: PD Mask */\r
-#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos 1 /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */\r
-#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos) /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask */\r
-#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */\r
-#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask */\r
-#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */\r
-#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask */\r
-#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos 4 /*!< CGU PLL0AUDIO_CTRL: CLKEN Position */\r
-#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos) /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask */\r
-#define CGU_PLL0AUDIO_CTRL_FRM_Pos 6 /*!< CGU PLL0AUDIO_CTRL: FRM Position */\r
-#define CGU_PLL0AUDIO_CTRL_FRM_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos) /*!< CGU PLL0AUDIO_CTRL: FRM Mask */\r
-#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */\r
-#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask */\r
-#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos 12 /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Position */\r
-#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos) /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Mask */\r
-#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos 13 /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */\r
-#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos) /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask */\r
-#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos 14 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */\r
-#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask */\r
-#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */\r
-#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos) /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask */\r
-\r
-// ----------------------------------- CGU_PLL0AUDIO_MDIV ---------------------------------------\r
-#define CGU_PLL0AUDIO_MDIV_MDEC_Pos 0 /*!< CGU PLL0AUDIO_MDIV: MDEC Position */\r
-#define CGU_PLL0AUDIO_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos) /*!< CGU PLL0AUDIO_MDIV: MDEC Mask */\r
-\r
-// ---------------------------------- CGU_PLL0AUDIO_NP_DIV --------------------------------------\r
-#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */\r
-#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask */\r
-#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */\r
-#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask */\r
-\r
-// ----------------------------------- CGU_PLL0AUDIO_FRAC ---------------------------------------\r
-#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos 0 /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */\r
-#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos) /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */\r
-\r
-// -------------------------------------- CGU_PLL1_STAT -----------------------------------------\r
-#define CGU_PLL1_STAT_LOCK_Pos 0 /*!< CGU PLL1_STAT: LOCK Position */\r
-#define CGU_PLL1_STAT_LOCK_Msk (0x01UL << CGU_PLL1_STAT_LOCK_Pos) /*!< CGU PLL1_STAT: LOCK Mask */\r
-\r
-// -------------------------------------- CGU_PLL1_CTRL -----------------------------------------\r
-#define CGU_PLL1_CTRL_PD_Pos 0 /*!< CGU PLL1_CTRL: PD Position */\r
-#define CGU_PLL1_CTRL_PD_Msk (0x01UL << CGU_PLL1_CTRL_PD_Pos) /*!< CGU PLL1_CTRL: PD Mask */\r
-#define CGU_PLL1_CTRL_BYPASS_Pos 1 /*!< CGU PLL1_CTRL: BYPASS Position */\r
-#define CGU_PLL1_CTRL_BYPASS_Msk (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos) /*!< CGU PLL1_CTRL: BYPASS Mask */\r
-#define CGU_PLL1_CTRL_FBSEL_Pos 6 /*!< CGU PLL1_CTRL: FBSEL Position */\r
-#define CGU_PLL1_CTRL_FBSEL_Msk (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos) /*!< CGU PLL1_CTRL: FBSEL Mask */\r
-#define CGU_PLL1_CTRL_DIRECT_Pos 7 /*!< CGU PLL1_CTRL: DIRECT Position */\r
-#define CGU_PLL1_CTRL_DIRECT_Msk (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos) /*!< CGU PLL1_CTRL: DIRECT Mask */\r
-#define CGU_PLL1_CTRL_PSEL_Pos 8 /*!< CGU PLL1_CTRL: PSEL Position */\r
-#define CGU_PLL1_CTRL_PSEL_Msk (0x03UL << CGU_PLL1_CTRL_PSEL_Pos) /*!< CGU PLL1_CTRL: PSEL Mask */\r
-#define CGU_PLL1_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL1_CTRL: AUTOBLOCK Position */\r
-#define CGU_PLL1_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL1_CTRL: AUTOBLOCK Mask */\r
-#define CGU_PLL1_CTRL_NSEL_Pos 12 /*!< CGU PLL1_CTRL: NSEL Position */\r
-#define CGU_PLL1_CTRL_NSEL_Msk (0x03UL << CGU_PLL1_CTRL_NSEL_Pos) /*!< CGU PLL1_CTRL: NSEL Mask */\r
-#define CGU_PLL1_CTRL_MSEL_Pos 16 /*!< CGU PLL1_CTRL: MSEL Position */\r
-#define CGU_PLL1_CTRL_MSEL_Msk (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos) /*!< CGU PLL1_CTRL: MSEL Mask */\r
-#define CGU_PLL1_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL1_CTRL: CLK_SEL Position */\r
-#define CGU_PLL1_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos) /*!< CGU PLL1_CTRL: CLK_SEL Mask */\r
-\r
-// ------------------------------------- CGU_IDIVA_CTRL -----------------------------------------\r
-#define CGU_IDIVA_CTRL_PD_Pos 0 /*!< CGU IDIVA_CTRL: PD Position */\r
-#define CGU_IDIVA_CTRL_PD_Msk (0x01UL << CGU_IDIVA_CTRL_PD_Pos) /*!< CGU IDIVA_CTRL: PD Mask */\r
-#define CGU_IDIVA_CTRL_IDIV_Pos 2 /*!< CGU IDIVA_CTRL: IDIV Position */\r
-#define CGU_IDIVA_CTRL_IDIV_Msk (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos) /*!< CGU IDIVA_CTRL: IDIV Mask */\r
-#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVA_CTRL: AUTOBLOCK Position */\r
-#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask */\r
-#define CGU_IDIVA_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVA_CTRL: CLK_SEL Position */\r
-#define CGU_IDIVA_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos) /*!< CGU IDIVA_CTRL: CLK_SEL Mask */\r
-\r
-// ------------------------------------- CGU_IDIVB_CTRL -----------------------------------------\r
-#define CGU_IDIVB_CTRL_PD_Pos 0 /*!< CGU IDIVB_CTRL: PD Position */\r
-#define CGU_IDIVB_CTRL_PD_Msk (0x01UL << CGU_IDIVB_CTRL_PD_Pos) /*!< CGU IDIVB_CTRL: PD Mask */\r
-#define CGU_IDIVB_CTRL_IDIV_Pos 2 /*!< CGU IDIVB_CTRL: IDIV Position */\r
-#define CGU_IDIVB_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos) /*!< CGU IDIVB_CTRL: IDIV Mask */\r
-#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVB_CTRL: AUTOBLOCK Position */\r
-#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask */\r
-#define CGU_IDIVB_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVB_CTRL: CLK_SEL Position */\r
-#define CGU_IDIVB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos) /*!< CGU IDIVB_CTRL: CLK_SEL Mask */\r
-\r
-// ------------------------------------- CGU_IDIVE_CTRL -----------------------------------------\r
-#define CGU_IDIVE_CTRL_PD_Pos 0 /*!< CGU IDIVE_CTRL: PD Position */\r
-#define CGU_IDIVE_CTRL_PD_Msk (0x01UL << CGU_IDIVE_CTRL_PD_Pos) /*!< CGU IDIVE_CTRL: PD Mask */\r
-#define CGU_IDIVE_CTRL_IDIV_Pos 2 /*!< CGU IDIVE_CTRL: IDIV Position */\r
-#define CGU_IDIVE_CTRL_IDIV_Msk (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos) /*!< CGU IDIVE_CTRL: IDIV Mask */\r
-#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVE_CTRL: AUTOBLOCK Position */\r
-#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask */\r
-#define CGU_IDIVE_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVE_CTRL: CLK_SEL Position */\r
-#define CGU_IDIVE_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos) /*!< CGU IDIVE_CTRL: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_SAFE_CLK ---------------------------------------\r
-#define CGU_BASE_SAFE_CLK_PD_Pos 0 /*!< CGU BASE_SAFE_CLK: PD Position */\r
-#define CGU_BASE_SAFE_CLK_PD_Msk (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos) /*!< CGU BASE_SAFE_CLK: PD Mask */\r
-#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */\r
-#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos) /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_USB0_CLK ---------------------------------------\r
-#define CGU_BASE_USB0_CLK_PD_Pos 0 /*!< CGU BASE_USB0_CLK: PD Position */\r
-#define CGU_BASE_USB0_CLK_PD_Msk (0x01UL << CGU_BASE_USB0_CLK_PD_Pos) /*!< CGU BASE_USB0_CLK: PD Mask */\r
-#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_USB0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB0_CLK: CLK_SEL Position */\r
-#define CGU_BASE_USB0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB0_CLK: CLK_SEL Mask */\r
-\r
-// ----------------------------------- CGU_BASE_PERIPH_CLK --------------------------------------\r
-#define CGU_BASE_PERIPH_CLK_PD_Pos 0 /*!< CGU BASE_PERIPH_CLK: PD Position */\r
-#define CGU_BASE_PERIPH_CLK_PD_Msk (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos) /*!< CGU BASE_PERIPH_CLK: PD Mask */\r
-#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */\r
-#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos) /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_USB1_CLK ---------------------------------------\r
-#define CGU_BASE_USB1_CLK_PD_Pos 0 /*!< CGU BASE_USB1_CLK: PD Position */\r
-#define CGU_BASE_USB1_CLK_PD_Msk (0x01UL << CGU_BASE_USB1_CLK_PD_Pos) /*!< CGU BASE_USB1_CLK: PD Mask */\r
-#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_USB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB1_CLK: CLK_SEL Position */\r
-#define CGU_BASE_USB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB1_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------- CGU_BASE_M4_CLK ----------------------------------------\r
-#define CGU_BASE_M4_CLK_PD_Pos 0 /*!< CGU BASE_M4_CLK: PD Position */\r
-#define CGU_BASE_M4_CLK_PD_Msk (0x01UL << CGU_BASE_M4_CLK_PD_Pos) /*!< CGU BASE_M4_CLK: PD Mask */\r
-#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_M4_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_M4_CLK: CLK_SEL Position */\r
-#define CGU_BASE_M4_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos) /*!< CGU BASE_M4_CLK: CLK_SEL Mask */\r
-\r
-// ----------------------------------- CGU_BASE_SPIFI_CLK ---------------------------------------\r
-#define CGU_BASE_SPIFI_CLK_PD_Pos 0 /*!< CGU BASE_SPIFI_CLK: PD Position */\r
-#define CGU_BASE_SPIFI_CLK_PD_Msk (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos) /*!< CGU BASE_SPIFI_CLK: PD Mask */\r
-#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */\r
-#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_SPI_CLK ----------------------------------------\r
-#define CGU_BASE_SPI_CLK_PD_Pos 0 /*!< CGU BASE_SPI_CLK: PD Position */\r
-#define CGU_BASE_SPI_CLK_PD_Msk (0x01UL << CGU_BASE_SPI_CLK_PD_Pos) /*!< CGU BASE_SPI_CLK: PD Mask */\r
-#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_SPI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPI_CLK: CLK_SEL Position */\r
-#define CGU_BASE_SPI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPI_CLK: CLK_SEL Mask */\r
-\r
-// ----------------------------------- CGU_BASE_PHY_RX_CLK --------------------------------------\r
-#define CGU_BASE_PHY_RX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_RX_CLK: PD Position */\r
-#define CGU_BASE_PHY_RX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos) /*!< CGU BASE_PHY_RX_CLK: PD Mask */\r
-#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */\r
-#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask */\r
-\r
-// ----------------------------------- CGU_BASE_PHY_TX_CLK --------------------------------------\r
-#define CGU_BASE_PHY_TX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_TX_CLK: PD Position */\r
-#define CGU_BASE_PHY_TX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos) /*!< CGU BASE_PHY_TX_CLK: PD Mask */\r
-#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */\r
-#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_APB1_CLK ---------------------------------------\r
-#define CGU_BASE_APB1_CLK_PD_Pos 0 /*!< CGU BASE_APB1_CLK: PD Position */\r
-#define CGU_BASE_APB1_CLK_PD_Msk (0x01UL << CGU_BASE_APB1_CLK_PD_Pos) /*!< CGU BASE_APB1_CLK: PD Mask */\r
-#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_APB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB1_CLK: CLK_SEL Position */\r
-#define CGU_BASE_APB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB1_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_APB3_CLK ---------------------------------------\r
-#define CGU_BASE_APB3_CLK_PD_Pos 0 /*!< CGU BASE_APB3_CLK: PD Position */\r
-#define CGU_BASE_APB3_CLK_PD_Msk (0x01UL << CGU_BASE_APB3_CLK_PD_Pos) /*!< CGU BASE_APB3_CLK: PD Mask */\r
-#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_APB3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB3_CLK: CLK_SEL Position */\r
-#define CGU_BASE_APB3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB3_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_LCD_CLK ----------------------------------------\r
-#define CGU_BASE_LCD_CLK_PD_Pos 0 /*!< CGU BASE_LCD_CLK: PD Position */\r
-#define CGU_BASE_LCD_CLK_PD_Msk (0x01UL << CGU_BASE_LCD_CLK_PD_Pos) /*!< CGU BASE_LCD_CLK: PD Mask */\r
-#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_LCD_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_LCD_CLK: CLK_SEL Position */\r
-#define CGU_BASE_LCD_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos) /*!< CGU BASE_LCD_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_SDIO_CLK ---------------------------------------\r
-#define CGU_BASE_SDIO_CLK_PD_Pos 0 /*!< CGU BASE_SDIO_CLK: PD Position */\r
-#define CGU_BASE_SDIO_CLK_PD_Msk (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos) /*!< CGU BASE_SDIO_CLK: PD Mask */\r
-#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */\r
-#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos) /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_SSP0_CLK ---------------------------------------\r
-#define CGU_BASE_SSP0_CLK_PD_Pos 0 /*!< CGU BASE_SSP0_CLK: PD Position */\r
-#define CGU_BASE_SSP0_CLK_PD_Msk (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos) /*!< CGU BASE_SSP0_CLK: PD Mask */\r
-#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */\r
-#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_SSP1_CLK ---------------------------------------\r
-#define CGU_BASE_SSP1_CLK_PD_Pos 0 /*!< CGU BASE_SSP1_CLK: PD Position */\r
-#define CGU_BASE_SSP1_CLK_PD_Msk (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos) /*!< CGU BASE_SSP1_CLK: PD Mask */\r
-#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */\r
-#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask */\r
-\r
-// ----------------------------------- CGU_BASE_UART0_CLK ---------------------------------------\r
-#define CGU_BASE_UART0_CLK_PD_Pos 0 /*!< CGU BASE_UART0_CLK: PD Position */\r
-#define CGU_BASE_UART0_CLK_PD_Msk (0x01UL << CGU_BASE_UART0_CLK_PD_Pos) /*!< CGU BASE_UART0_CLK: PD Mask */\r
-#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_UART0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART0_CLK: CLK_SEL Position */\r
-#define CGU_BASE_UART0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART0_CLK: CLK_SEL Mask */\r
-\r
-// ----------------------------------- CGU_BASE_UART1_CLK ---------------------------------------\r
-#define CGU_BASE_UART1_CLK_PD_Pos 0 /*!< CGU BASE_UART1_CLK: PD Position */\r
-#define CGU_BASE_UART1_CLK_PD_Msk (0x01UL << CGU_BASE_UART1_CLK_PD_Pos) /*!< CGU BASE_UART1_CLK: PD Mask */\r
-#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_UART1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART1_CLK: CLK_SEL Position */\r
-#define CGU_BASE_UART1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART1_CLK: CLK_SEL Mask */\r
-\r
-// ----------------------------------- CGU_BASE_UART2_CLK ---------------------------------------\r
-#define CGU_BASE_UART2_CLK_PD_Pos 0 /*!< CGU BASE_UART2_CLK: PD Position */\r
-#define CGU_BASE_UART2_CLK_PD_Msk (0x01UL << CGU_BASE_UART2_CLK_PD_Pos) /*!< CGU BASE_UART2_CLK: PD Mask */\r
-#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_UART2_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART2_CLK: CLK_SEL Position */\r
-#define CGU_BASE_UART2_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART2_CLK: CLK_SEL Mask */\r
-\r
-// ----------------------------------- CGU_BASE_UART3_CLK ---------------------------------------\r
-#define CGU_BASE_UART3_CLK_PD_Pos 0 /*!< CGU BASE_UART3_CLK: PD Position */\r
-#define CGU_BASE_UART3_CLK_PD_Msk (0x01UL << CGU_BASE_UART3_CLK_PD_Pos) /*!< CGU BASE_UART3_CLK: PD Mask */\r
-#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_UART3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART3_CLK: CLK_SEL Position */\r
-#define CGU_BASE_UART3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART3_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_OUT_CLK ----------------------------------------\r
-#define CGU_BASE_OUT_CLK_PD_Pos 0 /*!< CGU BASE_OUT_CLK: PD Position */\r
-#define CGU_BASE_OUT_CLK_PD_Msk (0x01UL << CGU_BASE_OUT_CLK_PD_Pos) /*!< CGU BASE_OUT_CLK: PD Mask */\r
-#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_OUT_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_OUT_CLK: CLK_SEL Position */\r
-#define CGU_BASE_OUT_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos) /*!< CGU BASE_OUT_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------ CGU_BASE_APLL_CLK ---------------------------------------\r
-#define CGU_BASE_APLL_CLK_PD_Pos 0 /*!< CGU BASE_APLL_CLK: PD Position */\r
-#define CGU_BASE_APLL_CLK_PD_Msk (0x01UL << CGU_BASE_APLL_CLK_PD_Pos) /*!< CGU BASE_APLL_CLK: PD Mask */\r
-#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_APLL_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APLL_CLK: CLK_SEL Position */\r
-#define CGU_BASE_APLL_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos) /*!< CGU BASE_APLL_CLK: CLK_SEL Mask */\r
-\r
-// ---------------------------------- CGU_BASE_CGU_OUT0_CLK -------------------------------------\r
-#define CGU_BASE_CGU_OUT0_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT0_CLK: PD Position */\r
-#define CGU_BASE_CGU_OUT0_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT0_CLK: PD Mask */\r
-#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */\r
-#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */\r
-\r
-// ---------------------------------- CGU_BASE_CGU_OUT1_CLK -------------------------------------\r
-#define CGU_BASE_CGU_OUT1_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT1_CLK: PD Position */\r
-#define CGU_BASE_CGU_OUT1_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT1_CLK: PD Mask */\r
-#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */\r
-#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */\r
-#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */\r
-#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */\r
-\r
-// ------------------------------------- CGU_IDIVC_CTRL -----------------------------------------\r
-#define CGU_IDIVC_CTRL_PD_Pos 0 /*!< CGU IDIVC_CTRL: PD Position */\r
-#define CGU_IDIVC_CTRL_PD_Msk (0x01UL << CGU_IDIVC_CTRL_PD_Pos) /*!< CGU IDIVC_CTRL: PD Mask */\r
-#define CGU_IDIVC_CTRL_IDIV_Pos 2 /*!< CGU IDIVC_CTRL: IDIV Position */\r
-#define CGU_IDIVC_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos) /*!< CGU IDIVC_CTRL: IDIV Mask */\r
-#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVC_CTRL: AUTOBLOCK Position */\r
-#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask */\r
-#define CGU_IDIVC_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVC_CTRL: CLK_SEL Position */\r
-#define CGU_IDIVC_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos) /*!< CGU IDIVC_CTRL: CLK_SEL Mask */\r
-\r
-// ------------------------------------- CGU_IDIVD_CTRL -----------------------------------------\r
-#define CGU_IDIVD_CTRL_PD_Pos 0 /*!< CGU IDIVD_CTRL: PD Position */\r
-#define CGU_IDIVD_CTRL_PD_Msk (0x01UL << CGU_IDIVD_CTRL_PD_Pos) /*!< CGU IDIVD_CTRL: PD Mask */\r
-#define CGU_IDIVD_CTRL_IDIV_Pos 2 /*!< CGU IDIVD_CTRL: IDIV Position */\r
-#define CGU_IDIVD_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos) /*!< CGU IDIVD_CTRL: IDIV Mask */\r
-#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVD_CTRL: AUTOBLOCK Position */\r
-#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask */\r
-#define CGU_IDIVD_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVD_CTRL: CLK_SEL Position */\r
-#define CGU_IDIVD_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos) /*!< CGU IDIVD_CTRL: CLK_SEL Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- CCU1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------- CCU1_PM --------------------------------------------\r
-#define CCU1_PM_PD_Pos 0 /*!< CCU1 PM: PD Position */\r
-#define CCU1_PM_PD_Msk (0x01UL << CCU1_PM_PD_Pos) /*!< CCU1 PM: PD Mask */\r
-\r
-// ------------------------------------- CCU1_BASE_STAT -----------------------------------------\r
-#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos 0 /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */\r
-#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */\r
-#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos 1 /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */\r
-#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */\r
-#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos 2 /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */\r
-#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */\r
-#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos 3 /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */\r
-#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */\r
-#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos 7 /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */\r
-#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */\r
-#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos 8 /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */\r
-#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_APB3_BUS_CFG -------------------------------------\r
-#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */\r
-#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask */\r
-#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */\r
-#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_BUS_STAT -------------------------------------\r
-#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */\r
-#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask */\r
-#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */\r
-#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_I2C1_CFG -------------------------------------\r
-#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */\r
-#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask */\r
-#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */\r
-#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_I2C1_STAT ------------------------------------\r
-#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */\r
-#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask */\r
-#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */\r
-#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_APB3_DAC_CFG -------------------------------------\r
-#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */\r
-#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask */\r
-#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */\r
-#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_DAC_STAT -------------------------------------\r
-#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */\r
-#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask */\r
-#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */\r
-#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_ADC0_CFG -------------------------------------\r
-#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */\r
-#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask */\r
-#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */\r
-#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_ADC0_STAT ------------------------------------\r
-#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */\r
-#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask */\r
-#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */\r
-#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_ADC1_CFG -------------------------------------\r
-#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */\r
-#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask */\r
-#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */\r
-#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_ADC1_STAT ------------------------------------\r
-#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */\r
-#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask */\r
-#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */\r
-#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_CAN0_CFG -------------------------------------\r
-#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */\r
-#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask */\r
-#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */\r
-#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB3_CAN0_STAT ------------------------------------\r
-#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */\r
-#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask */\r
-#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */\r
-#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_APB1_BUS_CFG -------------------------------------\r
-#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */\r
-#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask */\r
-#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */\r
-#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB1_BUS_STAT -------------------------------------\r
-#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */\r
-#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask */\r
-#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */\r
-#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */\r
-\r
-// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_CFG ----------------------------------\r
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */\r
-\r
-// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_STAT ---------------------------------\r
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_ABP1_I2C0_CFG -------------------------------------\r
-#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos 0 /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Position */\r
-#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Mask */\r
-#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Position */\r
-#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Mask */\r
-#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Position */\r
-#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB1_I2C0_STAT ------------------------------------\r
-#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */\r
-#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask */\r
-#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */\r
-#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_APB1_I2S_CFG -------------------------------------\r
-#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */\r
-#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask */\r
-#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */\r
-#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB1_I2S_STAT -------------------------------------\r
-#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */\r
-#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask */\r
-#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */\r
-#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB1_CAN1_CFG -------------------------------------\r
-#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */\r
-#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask */\r
-#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */\r
-#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask */\r
-#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */\r
-#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_APB1_CAN1_STAT ------------------------------------\r
-#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */\r
-#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask */\r
-#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */\r
-#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask */\r
-#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */\r
-#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_SPIFI_CFG ---------------------------------------\r
-#define CCU1_CLK_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_CFG: RUN Position */\r
-#define CCU1_CLK_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_SPIFI_CFG: RUN Mask */\r
-#define CCU1_CLK_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_CFG: AUTO Position */\r
-#define CCU1_CLK_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask */\r
-#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */\r
-#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_SPIFI_STAT --------------------------------------\r
-#define CCU1_CLK_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_STAT: RUN Position */\r
-#define CCU1_CLK_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_SPIFI_STAT: RUN Mask */\r
-#define CCU1_CLK_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_STAT: AUTO Position */\r
-#define CCU1_CLK_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask */\r
-#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */\r
-#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_M3_BUS_CFG --------------------------------------\r
-#define CCU1_CLK_M3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_BUS_CFG: RUN Position */\r
-#define CCU1_CLK_M3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_M3_BUS_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_BUS_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_BUS_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_BUS_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_BUS_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_BUS_STAT --------------------------------------\r
-#define CCU1_CLK_M3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_BUS_STAT: RUN Position */\r
-#define CCU1_CLK_M3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_M3_BUS_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_BUS_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_BUS_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_BUS_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_BUS_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_SPIFI_CFG -------------------------------------\r
-#define CCU1_CLK_M3_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SPIFI_CFG: RUN Position */\r
-#define CCU1_CLK_M3_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SPIFI_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SPIFI_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SPIFI_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SPIFI_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SPIFI_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_SPIFI_STAT -------------------------------------\r
-#define CCU1_CLK_M3_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SPIFI_STAT: RUN Position */\r
-#define CCU1_CLK_M3_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SPIFI_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SPIFI_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SPIFI_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SPIFI_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SPIFI_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_GPIO_CFG --------------------------------------\r
-#define CCU1_CLK_M3_GPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_GPIO_CFG: RUN Position */\r
-#define CCU1_CLK_M3_GPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_GPIO_CFG_RUN_Pos) /*!< CCU1 CLK_M3_GPIO_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_GPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_GPIO_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_GPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_GPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_GPIO_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_GPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_GPIO_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_GPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_GPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_GPIO_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_GPIO_STAT -------------------------------------\r
-#define CCU1_CLK_M3_GPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_GPIO_STAT: RUN Position */\r
-#define CCU1_CLK_M3_GPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_GPIO_STAT_RUN_Pos) /*!< CCU1 CLK_M3_GPIO_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_GPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_GPIO_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_GPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_GPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_GPIO_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_GPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_GPIO_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_GPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_GPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_GPIO_STAT: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_M3_LCD_CFG --------------------------------------\r
-#define CCU1_CLK_M3_LCD_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_LCD_CFG: RUN Position */\r
-#define CCU1_CLK_M3_LCD_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_LCD_CFG_RUN_Pos) /*!< CCU1 CLK_M3_LCD_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_LCD_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_LCD_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_LCD_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_LCD_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_LCD_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_LCD_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_LCD_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_LCD_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_LCD_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_LCD_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_LCD_STAT --------------------------------------\r
-#define CCU1_CLK_M3_LCD_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_LCD_STAT: RUN Position */\r
-#define CCU1_CLK_M3_LCD_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_LCD_STAT_RUN_Pos) /*!< CCU1 CLK_M3_LCD_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_LCD_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_LCD_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_LCD_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_LCD_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_LCD_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_LCD_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_LCD_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_LCD_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_LCD_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_LCD_STAT: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU1_CLK_M3_ETHERNET_CFG ------------------------------------\r
-#define CCU1_CLK_M3_ETHERNET_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_ETHERNET_CFG: RUN Position */\r
-#define CCU1_CLK_M3_ETHERNET_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_CFG_RUN_Pos) /*!< CCU1 CLK_M3_ETHERNET_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_ETHERNET_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_ETHERNET_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_ETHERNET_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_ETHERNET_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_ETHERNET_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_ETHERNET_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_ETHERNET_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_ETHERNET_CFG: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU1_CLK_M3_ETHERNET_STAT -----------------------------------\r
-#define CCU1_CLK_M3_ETHERNET_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_ETHERNET_STAT: RUN Position */\r
-#define CCU1_CLK_M3_ETHERNET_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_STAT_RUN_Pos) /*!< CCU1 CLK_M3_ETHERNET_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_ETHERNET_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_ETHERNET_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_ETHERNET_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_ETHERNET_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_ETHERNET_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_ETHERNET_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_ETHERNET_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_ETHERNET_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_ETHERNET_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_USB0_CFG --------------------------------------\r
-#define CCU1_CLK_M3_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USB0_CFG: RUN Position */\r
-#define CCU1_CLK_M3_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USB0_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB0_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USB0_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB0_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB0_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_USB0_STAT -------------------------------------\r
-#define CCU1_CLK_M3_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USB0_STAT: RUN Position */\r
-#define CCU1_CLK_M3_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USB0_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB0_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USB0_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB0_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB0_STAT: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_M3_EMC_CFG --------------------------------------\r
-#define CCU1_CLK_M3_EMC_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_EMC_CFG: RUN Position */\r
-#define CCU1_CLK_M3_EMC_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_EMC_CFG_RUN_Pos) /*!< CCU1 CLK_M3_EMC_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_EMC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMC_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_EMC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMC_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_EMC_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_EMC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMC_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_EMC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMC_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_EMC_STAT --------------------------------------\r
-#define CCU1_CLK_M3_EMC_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_EMC_STAT: RUN Position */\r
-#define CCU1_CLK_M3_EMC_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_EMC_STAT_RUN_Pos) /*!< CCU1 CLK_M3_EMC_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_EMC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMC_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_EMC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMC_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_EMC_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_EMC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMC_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_EMC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMC_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_SDIO_CFG --------------------------------------\r
-#define CCU1_CLK_M3_SDIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SDIO_CFG: RUN Position */\r
-#define CCU1_CLK_M3_SDIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SDIO_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SDIO_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_SDIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SDIO_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_SDIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SDIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SDIO_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SDIO_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SDIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SDIO_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_SDIO_STAT -------------------------------------\r
-#define CCU1_CLK_M3_SDIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SDIO_STAT: RUN Position */\r
-#define CCU1_CLK_M3_SDIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SDIO_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SDIO_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_SDIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SDIO_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_SDIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SDIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SDIO_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SDIO_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SDIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SDIO_STAT: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_M3_DMA_CFG --------------------------------------\r
-#define CCU1_CLK_M3_DMA_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_DMA_CFG: RUN Position */\r
-#define CCU1_CLK_M3_DMA_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_DMA_CFG_RUN_Pos) /*!< CCU1 CLK_M3_DMA_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_DMA_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_DMA_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_DMA_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_DMA_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_DMA_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_DMA_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_DMA_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_DMA_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_DMA_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_DMA_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_DMA_STAT --------------------------------------\r
-#define CCU1_CLK_M3_DMA_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_DMA_STAT: RUN Position */\r
-#define CCU1_CLK_M3_DMA_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_DMA_STAT_RUN_Pos) /*!< CCU1 CLK_M3_DMA_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_DMA_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_DMA_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_DMA_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_DMA_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_DMA_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_DMA_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_DMA_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_DMA_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_DMA_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_DMA_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_M3CORE_CFG -------------------------------------\r
-#define CCU1_CLK_M3_M3CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_M3CORE_CFG: RUN Position */\r
-#define CCU1_CLK_M3_M3CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_M3CORE_CFG_RUN_Pos) /*!< CCU1 CLK_M3_M3CORE_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_M3CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_M3CORE_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_M3CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_M3CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_M3CORE_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_M3CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_M3CORE_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_M3CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_M3CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_M3CORE_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_M3CORE_STAT ------------------------------------\r
-#define CCU1_CLK_M3_M3CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_M3CORE_STAT: RUN Position */\r
-#define CCU1_CLK_M3_M3CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_M3CORE_STAT_RUN_Pos) /*!< CCU1 CLK_M3_M3CORE_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_M3CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_M3CORE_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_M3CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_M3CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_M3CORE_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_M3CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_M3CORE_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_M3CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_M3CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_M3CORE_STAT: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_M3_SCT_CFG --------------------------------------\r
-#define CCU1_CLK_M3_SCT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SCT_CFG: RUN Position */\r
-#define CCU1_CLK_M3_SCT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SCT_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SCT_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_SCT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCT_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_SCT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCT_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SCT_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_SCT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCT_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_SCT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCT_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_SCT_STAT --------------------------------------\r
-#define CCU1_CLK_M3_SCT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SCT_STAT: RUN Position */\r
-#define CCU1_CLK_M3_SCT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SCT_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SCT_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_SCT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCT_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_SCT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCT_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SCT_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_SCT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCT_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_SCT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCT_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_USB1_CFG --------------------------------------\r
-#define CCU1_CLK_M3_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USB1_CFG: RUN Position */\r
-#define CCU1_CLK_M3_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USB1_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB1_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USB1_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB1_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB1_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_USB1_STAT -------------------------------------\r
-#define CCU1_CLK_M3_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USB1_STAT: RUN Position */\r
-#define CCU1_CLK_M3_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USB1_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USB1_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USB1_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USB1_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USB1_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_EMCDIV_CFG -------------------------------------\r
-#define CCU1_CLK_M3_EMCDIV_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_EMCDIV_CFG: RUN Position */\r
-#define CCU1_CLK_M3_EMCDIV_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_CFG_RUN_Pos) /*!< CCU1 CLK_M3_EMCDIV_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_EMCDIV_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMCDIV_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_EMCDIV_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_EMCDIV_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_EMCDIV_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMCDIV_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_EMCDIV_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMCDIV_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_EMCDIV_STAT ------------------------------------\r
-#define CCU1_CLK_M3_EMCDIV_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_EMCDIV_STAT: RUN Position */\r
-#define CCU1_CLK_M3_EMCDIV_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_STAT_RUN_Pos) /*!< CCU1 CLK_M3_EMCDIV_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_EMCDIV_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_EMCDIV_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_EMCDIV_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_EMCDIV_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_EMCDIV_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_EMCDIV_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_EMCDIV_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_EMCDIV_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_EMCDIV_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_WWDT_CFG --------------------------------------\r
-#define CCU1_CLK_M3_WWDT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_WWDT_CFG: RUN Position */\r
-#define CCU1_CLK_M3_WWDT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_WWDT_CFG_RUN_Pos) /*!< CCU1 CLK_M3_WWDT_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_WWDT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_WWDT_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_WWDT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_WWDT_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_WWDT_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_WWDT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_WWDT_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_WWDT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_WWDT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_WWDT_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_WWDT_STAT -------------------------------------\r
-#define CCU1_CLK_M3_WWDT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_WWDT_STAT: RUN Position */\r
-#define CCU1_CLK_M3_WWDT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_WWDT_STAT_RUN_Pos) /*!< CCU1 CLK_M3_WWDT_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_WWDT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_WWDT_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_WWDT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_WWDT_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_WWDT_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_WWDT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_WWDT_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_WWDT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_WWDT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_WWDT_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_USART0_CFG -------------------------------------\r
-#define CCU1_CLK_M3_USART0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USART0_CFG: RUN Position */\r
-#define CCU1_CLK_M3_USART0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USART0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USART0_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_USART0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART0_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_USART0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USART0_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_USART0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART0_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_USART0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART0_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_USART0_STAT ------------------------------------\r
-#define CCU1_CLK_M3_USART0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USART0_STAT: RUN Position */\r
-#define CCU1_CLK_M3_USART0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USART0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USART0_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_USART0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART0_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_USART0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USART0_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_USART0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART0_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_USART0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART0_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_UART1_CFG -------------------------------------\r
-#define CCU1_CLK_M3_UART1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_UART1_CFG: RUN Position */\r
-#define CCU1_CLK_M3_UART1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_UART1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_UART1_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_UART1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_UART1_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_UART1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_UART1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_UART1_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_UART1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_UART1_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_UART1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_UART1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_UART1_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_UART1_STAT -------------------------------------\r
-#define CCU1_CLK_M3_UART1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_UART1_STAT: RUN Position */\r
-#define CCU1_CLK_M3_UART1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_UART1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_UART1_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_UART1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_UART1_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_UART1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_UART1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_UART1_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_UART1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_UART1_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_UART1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_UART1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_UART1_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_SSP0_CFG --------------------------------------\r
-#define CCU1_CLK_M3_SSP0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP0_CFG: RUN Position */\r
-#define CCU1_CLK_M3_SSP0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SSP0_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_SSP0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP0_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_SSP0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SSP0_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP0_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP0_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_SSP0_STAT -------------------------------------\r
-#define CCU1_CLK_M3_SSP0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP0_STAT: RUN Position */\r
-#define CCU1_CLK_M3_SSP0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SSP0_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_SSP0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP0_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_SSP0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SSP0_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP0_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP0_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_TIMER0_CFG -------------------------------------\r
-#define CCU1_CLK_M3_TIMER0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER0_CFG: RUN Position */\r
-#define CCU1_CLK_M3_TIMER0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER0_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER0_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_TIMER0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER0_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_TIMER0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER0_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER0_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_TIMER0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER0_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_TIMER0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER0_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_TIMER0_STAT ------------------------------------\r
-#define CCU1_CLK_M3_TIMER0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER0_STAT: RUN Position */\r
-#define CCU1_CLK_M3_TIMER0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER0_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER0_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_TIMER0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER0_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_TIMER0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER0_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER0_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_TIMER0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER0_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_TIMER0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER0_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_TIMER1_CFG -------------------------------------\r
-#define CCU1_CLK_M3_TIMER1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER1_CFG: RUN Position */\r
-#define CCU1_CLK_M3_TIMER1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER1_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_TIMER1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER1_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_TIMER1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER1_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_TIMER1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER1_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_TIMER1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER1_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_TIMER1_STAT ------------------------------------\r
-#define CCU1_CLK_M3_TIMER1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER1_STAT: RUN Position */\r
-#define CCU1_CLK_M3_TIMER1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER1_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_TIMER1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER1_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_TIMER1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER1_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_TIMER1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER1_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_TIMER1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER1_STAT: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_M3_SCU_CFG --------------------------------------\r
-#define CCU1_CLK_M3_SCU_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SCU_CFG: RUN Position */\r
-#define CCU1_CLK_M3_SCU_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SCU_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SCU_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_SCU_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCU_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_SCU_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCU_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SCU_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_SCU_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCU_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_SCU_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCU_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCU_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_SCU_STAT --------------------------------------\r
-#define CCU1_CLK_M3_SCU_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SCU_STAT: RUN Position */\r
-#define CCU1_CLK_M3_SCU_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SCU_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SCU_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_SCU_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SCU_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_SCU_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SCU_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SCU_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_SCU_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SCU_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_SCU_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SCU_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SCU_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_CREG_CFG --------------------------------------\r
-#define CCU1_CLK_M3_CREG_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_CREG_CFG: RUN Position */\r
-#define CCU1_CLK_M3_CREG_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_CREG_CFG_RUN_Pos) /*!< CCU1 CLK_M3_CREG_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_CREG_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_CREG_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_CREG_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_CREG_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_CREG_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_CREG_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_CREG_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_CREG_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_CREG_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_CREG_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_CREG_STAT -------------------------------------\r
-#define CCU1_CLK_M3_CREG_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_CREG_STAT: RUN Position */\r
-#define CCU1_CLK_M3_CREG_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_CREG_STAT_RUN_Pos) /*!< CCU1 CLK_M3_CREG_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_CREG_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_CREG_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_CREG_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_CREG_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_CREG_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_CREG_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_CREG_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_CREG_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_CREG_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_CREG_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_RITIMER_CFG ------------------------------------\r
-#define CCU1_CLK_M3_RITIMER_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_RITIMER_CFG: RUN Position */\r
-#define CCU1_CLK_M3_RITIMER_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_RITIMER_CFG_RUN_Pos) /*!< CCU1 CLK_M3_RITIMER_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_RITIMER_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_RITIMER_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_RITIMER_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_RITIMER_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_RITIMER_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_RITIMER_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_RITIMER_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_RITIMER_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_RITIMER_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_RITIMER_CFG: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU1_CLK_M3_RITIMER_STAT ------------------------------------\r
-#define CCU1_CLK_M3_RITIMER_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_RITIMER_STAT: RUN Position */\r
-#define CCU1_CLK_M3_RITIMER_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_RITIMER_STAT_RUN_Pos) /*!< CCU1 CLK_M3_RITIMER_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_RITIMER_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_RITIMER_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_RITIMER_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_RITIMER_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_RITIMER_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_RITIMER_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_RITIMER_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_RITIMER_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_RITIMER_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_RITIMER_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_USART2_CFG -------------------------------------\r
-#define CCU1_CLK_M3_USART2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USART2_CFG: RUN Position */\r
-#define CCU1_CLK_M3_USART2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USART2_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USART2_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_USART2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART2_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_USART2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART2_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USART2_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_USART2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART2_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_USART2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART2_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_USART2_STAT ------------------------------------\r
-#define CCU1_CLK_M3_USART2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USART2_STAT: RUN Position */\r
-#define CCU1_CLK_M3_USART2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USART2_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USART2_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_USART2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART2_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_USART2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART2_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USART2_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_USART2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART2_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_USART2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART2_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_USART3_CFG -------------------------------------\r
-#define CCU1_CLK_M3_USART3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_USART3_CFG: RUN Position */\r
-#define CCU1_CLK_M3_USART3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_USART3_CFG_RUN_Pos) /*!< CCU1 CLK_M3_USART3_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_USART3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART3_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_USART3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART3_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_USART3_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_USART3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART3_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_USART3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART3_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_USART3_STAT ------------------------------------\r
-#define CCU1_CLK_M3_USART3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_USART3_STAT: RUN Position */\r
-#define CCU1_CLK_M3_USART3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_USART3_STAT_RUN_Pos) /*!< CCU1 CLK_M3_USART3_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_USART3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_USART3_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_USART3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_USART3_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_USART3_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_USART3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_USART3_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_USART3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_USART3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_USART3_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_TIMER2_CFG -------------------------------------\r
-#define CCU1_CLK_M3_TIMER2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER2_CFG: RUN Position */\r
-#define CCU1_CLK_M3_TIMER2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER2_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER2_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_TIMER2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER2_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_TIMER2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER2_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER2_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_TIMER2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER2_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_TIMER2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER2_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_TIMER2_STAT ------------------------------------\r
-#define CCU1_CLK_M3_TIMER2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER2_STAT: RUN Position */\r
-#define CCU1_CLK_M3_TIMER2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER2_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER2_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_TIMER2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER2_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_TIMER2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER2_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER2_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_TIMER2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER2_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_TIMER2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER2_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_TIMER3_CFG -------------------------------------\r
-#define CCU1_CLK_M3_TIMER3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER3_CFG: RUN Position */\r
-#define CCU1_CLK_M3_TIMER3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER3_CFG_RUN_Pos) /*!< CCU1 CLK_M3_TIMER3_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_TIMER3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER3_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_TIMER3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER3_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER3_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_TIMER3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER3_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_TIMER3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER3_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_M3_TIMER3_STAT ------------------------------------\r
-#define CCU1_CLK_M3_TIMER3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_TIMER3_STAT: RUN Position */\r
-#define CCU1_CLK_M3_TIMER3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_TIMER3_STAT_RUN_Pos) /*!< CCU1 CLK_M3_TIMER3_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_TIMER3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_TIMER3_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_TIMER3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_TIMER3_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_TIMER3_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_TIMER3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_TIMER3_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_TIMER3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_TIMER3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_TIMER3_STAT: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_SSP1_CFG --------------------------------------\r
-#define CCU1_CLK_M3_SSP1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP1_CFG: RUN Position */\r
-#define CCU1_CLK_M3_SSP1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP1_CFG_RUN_Pos) /*!< CCU1 CLK_M3_SSP1_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_SSP1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP1_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_SSP1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP1_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_SSP1_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP1_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP1_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_SSP1_STAT -------------------------------------\r
-#define CCU1_CLK_M3_SSP1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_SSP1_STAT: RUN Position */\r
-#define CCU1_CLK_M3_SSP1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_SSP1_STAT_RUN_Pos) /*!< CCU1 CLK_M3_SSP1_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_SSP1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_SSP1_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_SSP1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_SSP1_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_SSP1_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_SSP1_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_SSP1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_SSP1_STAT: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_M3_QEI_CFG --------------------------------------\r
-#define CCU1_CLK_M3_QEI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M3_QEI_CFG: RUN Position */\r
-#define CCU1_CLK_M3_QEI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M3_QEI_CFG_RUN_Pos) /*!< CCU1 CLK_M3_QEI_CFG: RUN Mask */\r
-#define CCU1_CLK_M3_QEI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M3_QEI_CFG: AUTO Position */\r
-#define CCU1_CLK_M3_QEI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M3_QEI_CFG_AUTO_Pos) /*!< CCU1 CLK_M3_QEI_CFG: AUTO Mask */\r
-#define CCU1_CLK_M3_QEI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_QEI_CFG: WAKEUP Position */\r
-#define CCU1_CLK_M3_QEI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_QEI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M3_QEI_CFG: WAKEUP Mask */\r
-\r
-// ---------------------------------- CCU1_CLK_M3_QEI_STAT --------------------------------------\r
-#define CCU1_CLK_M3_QEI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M3_QEI_STAT: RUN Position */\r
-#define CCU1_CLK_M3_QEI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M3_QEI_STAT_RUN_Pos) /*!< CCU1 CLK_M3_QEI_STAT: RUN Mask */\r
-#define CCU1_CLK_M3_QEI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M3_QEI_STAT: AUTO Position */\r
-#define CCU1_CLK_M3_QEI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M3_QEI_STAT_AUTO_Pos) /*!< CCU1 CLK_M3_QEI_STAT: AUTO Mask */\r
-#define CCU1_CLK_M3_QEI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M3_QEI_STAT: WAKEUP Position */\r
-#define CCU1_CLK_M3_QEI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M3_QEI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M3_QEI_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU1_CLK_PERIPH_BUS_CFG ------------------------------------\r
-#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */\r
-#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask */\r
-#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */\r
-#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask */\r
-#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */\r
-#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU1_CLK_PERIPH_BUS_STAT ------------------------------------\r
-#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */\r
-#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask */\r
-#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */\r
-#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */\r
-#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */\r
-#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU1_CLK_PERIPH_CORE_CFG ------------------------------------\r
-#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */\r
-#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask */\r
-#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */\r
-#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */\r
-#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */\r
-#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU1_CLK_PERIPH_CORE_STAT -----------------------------------\r
-#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */\r
-#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */\r
-#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */\r
-#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */\r
-#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */\r
-#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */\r
-\r
-\r
-// ------------------------------------ CCU1_CLK_USB0_CFG ---------------------------------------\r
-#define CCU1_CLK_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB0_CFG: RUN Position */\r
-#define CCU1_CLK_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_USB0_CFG: RUN Mask */\r
-#define CCU1_CLK_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB0_CFG: AUTO Position */\r
-#define CCU1_CLK_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_USB0_CFG: AUTO Mask */\r
-#define CCU1_CLK_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_CFG: WAKEUP Position */\r
-#define CCU1_CLK_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_USB0_STAT ---------------------------------------\r
-#define CCU1_CLK_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB0_STAT: RUN Position */\r
-#define CCU1_CLK_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_USB0_STAT: RUN Mask */\r
-#define CCU1_CLK_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB0_STAT: AUTO Position */\r
-#define CCU1_CLK_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_USB0_STAT: AUTO Mask */\r
-#define CCU1_CLK_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */\r
-#define CCU1_CLK_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask */\r
-\r
-// ------------------------------------ CCU1_CLK_USB1_CFG ---------------------------------------\r
-#define CCU1_CLK_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB1_CFG: RUN Position */\r
-#define CCU1_CLK_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_USB1_CFG: RUN Mask */\r
-#define CCU1_CLK_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB1_CFG: AUTO Position */\r
-#define CCU1_CLK_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_USB1_CFG: AUTO Mask */\r
-#define CCU1_CLK_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_CFG: WAKEUP Position */\r
-#define CCU1_CLK_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_USB1_STAT ---------------------------------------\r
-#define CCU1_CLK_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB1_STAT: RUN Position */\r
-#define CCU1_CLK_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_USB1_STAT: RUN Mask */\r
-#define CCU1_CLK_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB1_STAT: AUTO Position */\r
-#define CCU1_CLK_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_USB1_STAT: AUTO Mask */\r
-#define CCU1_CLK_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */\r
-#define CCU1_CLK_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask */\r
-\r
-// ------------------------------------ CCU1_CLK_VADC_CFG ---------------------------------------\r
-#define CCU1_CLK_VADC_CFG_RUN_Pos 0 /*!< CCU1 CLK_VADC_CFG: RUN Position */\r
-#define CCU1_CLK_VADC_CFG_RUN_Msk (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos) /*!< CCU1 CLK_VADC_CFG: RUN Mask */\r
-#define CCU1_CLK_VADC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_VADC_CFG: AUTO Position */\r
-#define CCU1_CLK_VADC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos) /*!< CCU1 CLK_VADC_CFG: AUTO Mask */\r
-#define CCU1_CLK_VADC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_CFG: WAKEUP Position */\r
-#define CCU1_CLK_VADC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_VADC_CFG: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU1_CLK_VADC_STAT ---------------------------------------\r
-#define CCU1_CLK_VADC_STAT_RUN_Pos 0 /*!< CCU1 CLK_VADC_STAT: RUN Position */\r
-#define CCU1_CLK_VADC_STAT_RUN_Msk (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos) /*!< CCU1 CLK_VADC_STAT: RUN Mask */\r
-#define CCU1_CLK_VADC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_VADC_STAT: AUTO Position */\r
-#define CCU1_CLK_VADC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos) /*!< CCU1 CLK_VADC_STAT: AUTO Mask */\r
-#define CCU1_CLK_VADC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_STAT: WAKEUP Position */\r
-#define CCU1_CLK_VADC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_VADC_STAT: WAKEUP Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- CCU2 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------- CCU2_PM --------------------------------------------\r
-#define CCU2_PM_PD_Pos 0 /*!< CCU2 PM: PD Position */\r
-#define CCU2_PM_PD_Msk (0x01UL << CCU2_PM_PD_Pos) /*!< CCU2 PM: PD Mask */\r
-\r
-// ------------------------------------- CCU2_BASE_STAT -----------------------------------------\r
-#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos 1 /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */\r
-#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */\r
-#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos 2 /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */\r
-#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */\r
-#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos 3 /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */\r
-#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */\r
-#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos 4 /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */\r
-#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */\r
-#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos 5 /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */\r
-#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask */\r
-#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos 6 /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */\r
-#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask */\r
-\r
-// ----------------------------------- CCU2_CLK_APLL3_CFG ---------------------------------------\r
-#define CCU2_CLK_APLL3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APLL3_CFG: RUN Position */\r
-#define CCU2_CLK_APLL3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APLL3_CFG_RUN_Pos) /*!< CCU2 CLK_APLL3_CFG: RUN Mask */\r
-#define CCU2_CLK_APLL3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APLL3_CFG: AUTO Position */\r
-#define CCU2_CLK_APLL3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APLL3_CFG_AUTO_Pos) /*!< CCU2 CLK_APLL3_CFG: AUTO Mask */\r
-#define CCU2_CLK_APLL3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL3_CFG: WAKEUP Position */\r
-#define CCU2_CLK_APLL3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APLL3_CFG: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU2_CLK_APLL_STAT ---------------------------------------\r
-#define CCU2_CLK_APLL_STAT_RUN_Pos 0 /*!< CCU2 CLK_APLL_STAT: RUN Position */\r
-#define CCU2_CLK_APLL_STAT_RUN_Msk (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos) /*!< CCU2 CLK_APLL_STAT: RUN Mask */\r
-#define CCU2_CLK_APLL_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APLL_STAT: AUTO Position */\r
-#define CCU2_CLK_APLL_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos) /*!< CCU2 CLK_APLL_STAT: AUTO Mask */\r
-#define CCU2_CLK_APLL_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL_STAT: WAKEUP Position */\r
-#define CCU2_CLK_APLL_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APLL_STAT: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU2_CLK_APB2_USART3_CFG ------------------------------------\r
-#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */\r
-#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask */\r
-#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */\r
-#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */\r
-#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */\r
-#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU2_CLK_APB2_USART3_STAT -----------------------------------\r
-#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */\r
-#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */\r
-#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */\r
-#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */\r
-#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */\r
-#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU2_CLK_APB2_USART2_CFG ------------------------------------\r
-#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */\r
-#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask */\r
-#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */\r
-#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */\r
-#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */\r
-#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU2_CLK_APB2_USART2_STAT -----------------------------------\r
-#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */\r
-#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */\r
-#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */\r
-#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */\r
-#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */\r
-#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */\r
-\r
-// ------------------------------- CCU2_CLK_APB0_UART1_BUS_CFG ----------------------------------\r
-#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */\r
-#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */\r
-#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */\r
-#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */\r
-#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */\r
-#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU2_CLK_APB0_UART1_STAT ------------------------------------\r
-#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */\r
-#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask */\r
-#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */\r
-#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */\r
-#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */\r
-#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU2_CLK_APB0_USART0_CFG ------------------------------------\r
-#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */\r
-#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask */\r
-#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */\r
-#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */\r
-#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */\r
-#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */\r
-\r
-// -------------------------------- CCU2_CLK_APB0_USART0_STAT -----------------------------------\r
-#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */\r
-#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */\r
-#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */\r
-#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */\r
-#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */\r
-#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU2_CLK_APB2_SSP1_CFG -------------------------------------\r
-#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */\r
-#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask */\r
-#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */\r
-#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask */\r
-#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */\r
-#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU2_CLK_APB2_SSP1_STAT ------------------------------------\r
-#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */\r
-#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask */\r
-#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */\r
-#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask */\r
-#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */\r
-#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU2_CLK_APB0_SSP0_CFG -------------------------------------\r
-#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */\r
-#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask */\r
-#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */\r
-#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask */\r
-#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */\r
-#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */\r
-\r
-// --------------------------------- CCU2_CLK_APB0_SSP0_STAT ------------------------------------\r
-#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */\r
-#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask */\r
-#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */\r
-#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask */\r
-#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */\r
-#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */\r
-\r
-// ------------------------------------ CCU2_CLK_SDIO_CFG ---------------------------------------\r
-#define CCU2_CLK_SDIO_CFG_RUN_Pos 0 /*!< CCU2 CLK_SDIO_CFG: RUN Position */\r
-#define CCU2_CLK_SDIO_CFG_RUN_Msk (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos) /*!< CCU2 CLK_SDIO_CFG: RUN Mask */\r
-#define CCU2_CLK_SDIO_CFG_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_CFG: AUTO Position */\r
-#define CCU2_CLK_SDIO_CFG_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos) /*!< CCU2 CLK_SDIO_CFG: AUTO Mask */\r
-#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position */\r
-#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask */\r
-\r
-// ----------------------------------- CCU2_CLK_SDIO_STAT ---------------------------------------\r
-#define CCU2_CLK_SDIO_STAT_RUN_Pos 0 /*!< CCU2 CLK_SDIO_STAT: RUN Position */\r
-#define CCU2_CLK_SDIO_STAT_RUN_Msk (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos) /*!< CCU2 CLK_SDIO_STAT: RUN Mask */\r
-#define CCU2_CLK_SDIO_STAT_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_STAT: AUTO Position */\r
-#define CCU2_CLK_SDIO_STAT_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos) /*!< CCU2 CLK_SDIO_STAT: AUTO Mask */\r
-#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */\r
-#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- RGU Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ------------------------------------- RGU_RESET_CTRL0 ----------------------------------------\r
-#define RGU_RESET_CTRL0_CORE_RST_Pos 0 /*!< RGU RESET_CTRL0: CORE_RST Position */\r
-#define RGU_RESET_CTRL0_CORE_RST_Msk (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos) /*!< RGU RESET_CTRL0: CORE_RST Mask */\r
-#define RGU_RESET_CTRL0_PERIPH_RST_Pos 1 /*!< RGU RESET_CTRL0: PERIPH_RST Position */\r
-#define RGU_RESET_CTRL0_PERIPH_RST_Msk (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos) /*!< RGU RESET_CTRL0: PERIPH_RST Mask */\r
-#define RGU_RESET_CTRL0_MASTER_RST_Pos 2 /*!< RGU RESET_CTRL0: MASTER_RST Position */\r
-#define RGU_RESET_CTRL0_MASTER_RST_Msk (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos) /*!< RGU RESET_CTRL0: MASTER_RST Mask */\r
-#define RGU_RESET_CTRL0_WWDT_RST_Pos 4 /*!< RGU RESET_CTRL0: WWDT_RST Position */\r
-#define RGU_RESET_CTRL0_WWDT_RST_Msk (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos) /*!< RGU RESET_CTRL0: WWDT_RST Mask */\r
-#define RGU_RESET_CTRL0_CREG_RST_Pos 5 /*!< RGU RESET_CTRL0: CREG_RST Position */\r
-#define RGU_RESET_CTRL0_CREG_RST_Msk (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos) /*!< RGU RESET_CTRL0: CREG_RST Mask */\r
-#define RGU_RESET_CTRL0_BUS_RST_Pos 8 /*!< RGU RESET_CTRL0: BUS_RST Position */\r
-#define RGU_RESET_CTRL0_BUS_RST_Msk (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos) /*!< RGU RESET_CTRL0: BUS_RST Mask */\r
-#define RGU_RESET_CTRL0_SCU_RST_Pos 9 /*!< RGU RESET_CTRL0: SCU_RST Position */\r
-#define RGU_RESET_CTRL0_SCU_RST_Msk (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos) /*!< RGU RESET_CTRL0: SCU_RST Mask */\r
-#define RGU_RESET_CTRL0_PINMUX_RST_Pos 10 /*!< RGU RESET_CTRL0: PINMUX_RST Position */\r
-#define RGU_RESET_CTRL0_PINMUX_RST_Msk (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos) /*!< RGU RESET_CTRL0: PINMUX_RST Mask */\r
-#define RGU_RESET_CTRL0_M3_RST_Pos 13 /*!< RGU RESET_CTRL0: M3_RST Position */\r
-#define RGU_RESET_CTRL0_M3_RST_Msk (0x01UL << RGU_RESET_CTRL0_M3_RST_Pos) /*!< RGU RESET_CTRL0: M3_RST Mask */\r
-#define RGU_RESET_CTRL0_LCD_RST_Pos 16 /*!< RGU RESET_CTRL0: LCD_RST Position */\r
-#define RGU_RESET_CTRL0_LCD_RST_Msk (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos) /*!< RGU RESET_CTRL0: LCD_RST Mask */\r
-#define RGU_RESET_CTRL0_USB0_RST_Pos 17 /*!< RGU RESET_CTRL0: USB0_RST Position */\r
-#define RGU_RESET_CTRL0_USB0_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos) /*!< RGU RESET_CTRL0: USB0_RST Mask */\r
-#define RGU_RESET_CTRL0_USB1_RST_Pos 18 /*!< RGU RESET_CTRL0: USB1_RST Position */\r
-#define RGU_RESET_CTRL0_USB1_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos) /*!< RGU RESET_CTRL0: USB1_RST Mask */\r
-#define RGU_RESET_CTRL0_DMA_RST_Pos 19 /*!< RGU RESET_CTRL0: DMA_RST Position */\r
-#define RGU_RESET_CTRL0_DMA_RST_Msk (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos) /*!< RGU RESET_CTRL0: DMA_RST Mask */\r
-#define RGU_RESET_CTRL0_SDIO_RST_Pos 20 /*!< RGU RESET_CTRL0: SDIO_RST Position */\r
-#define RGU_RESET_CTRL0_SDIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos) /*!< RGU RESET_CTRL0: SDIO_RST Mask */\r
-#define RGU_RESET_CTRL0_EMC_RST_Pos 21 /*!< RGU RESET_CTRL0: EMC_RST Position */\r
-#define RGU_RESET_CTRL0_EMC_RST_Msk (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos) /*!< RGU RESET_CTRL0: EMC_RST Mask */\r
-#define RGU_RESET_CTRL0_ETHERNET_RST_Pos 22 /*!< RGU RESET_CTRL0: ETHERNET_RST Position */\r
-#define RGU_RESET_CTRL0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos) /*!< RGU RESET_CTRL0: ETHERNET_RST Mask */\r
-#define RGU_RESET_CTRL0_GPIO_RST_Pos 28 /*!< RGU RESET_CTRL0: GPIO_RST Position */\r
-#define RGU_RESET_CTRL0_GPIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos) /*!< RGU RESET_CTRL0: GPIO_RST Mask */\r
-\r
-// ------------------------------------- RGU_RESET_CTRL1 ----------------------------------------\r
-#define RGU_RESET_CTRL1_TIMER0_RST_Pos 0 /*!< RGU RESET_CTRL1: TIMER0_RST Position */\r
-#define RGU_RESET_CTRL1_TIMER0_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos) /*!< RGU RESET_CTRL1: TIMER0_RST Mask */\r
-#define RGU_RESET_CTRL1_TIMER1_RST_Pos 1 /*!< RGU RESET_CTRL1: TIMER1_RST Position */\r
-#define RGU_RESET_CTRL1_TIMER1_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos) /*!< RGU RESET_CTRL1: TIMER1_RST Mask */\r
-#define RGU_RESET_CTRL1_TIMER2_RST_Pos 2 /*!< RGU RESET_CTRL1: TIMER2_RST Position */\r
-#define RGU_RESET_CTRL1_TIMER2_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos) /*!< RGU RESET_CTRL1: TIMER2_RST Mask */\r
-#define RGU_RESET_CTRL1_TIMER3_RST_Pos 3 /*!< RGU RESET_CTRL1: TIMER3_RST Position */\r
-#define RGU_RESET_CTRL1_TIMER3_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos) /*!< RGU RESET_CTRL1: TIMER3_RST Mask */\r
-#define RGU_RESET_CTRL1_RITIMER_RST_Pos 4 /*!< RGU RESET_CTRL1: RITIMER_RST Position */\r
-#define RGU_RESET_CTRL1_RITIMER_RST_Msk (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos) /*!< RGU RESET_CTRL1: RITIMER_RST Mask */\r
-#define RGU_RESET_CTRL1_SCT_RST_Pos 5 /*!< RGU RESET_CTRL1: SCT_RST Position */\r
-#define RGU_RESET_CTRL1_SCT_RST_Msk (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos) /*!< RGU RESET_CTRL1: SCT_RST Mask */\r
-#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */\r
-#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */\r
-#define RGU_RESET_CTRL1_QEI_RST_Pos 7 /*!< RGU RESET_CTRL1: QEI_RST Position */\r
-#define RGU_RESET_CTRL1_QEI_RST_Msk (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos) /*!< RGU RESET_CTRL1: QEI_RST Mask */\r
-#define RGU_RESET_CTRL1_ADC0_RST_Pos 8 /*!< RGU RESET_CTRL1: ADC0_RST Position */\r
-#define RGU_RESET_CTRL1_ADC0_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos) /*!< RGU RESET_CTRL1: ADC0_RST Mask */\r
-#define RGU_RESET_CTRL1_ADC1_RST_Pos 9 /*!< RGU RESET_CTRL1: ADC1_RST Position */\r
-#define RGU_RESET_CTRL1_ADC1_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos) /*!< RGU RESET_CTRL1: ADC1_RST Mask */\r
-#define RGU_RESET_CTRL1_DAC_RST_Pos 10 /*!< RGU RESET_CTRL1: DAC_RST Position */\r
-#define RGU_RESET_CTRL1_DAC_RST_Msk (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos) /*!< RGU RESET_CTRL1: DAC_RST Mask */\r
-#define RGU_RESET_CTRL1_UART0_RST_Pos 12 /*!< RGU RESET_CTRL1: UART0_RST Position */\r
-#define RGU_RESET_CTRL1_UART0_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos) /*!< RGU RESET_CTRL1: UART0_RST Mask */\r
-#define RGU_RESET_CTRL1_UART1_RST_Pos 13 /*!< RGU RESET_CTRL1: UART1_RST Position */\r
-#define RGU_RESET_CTRL1_UART1_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos) /*!< RGU RESET_CTRL1: UART1_RST Mask */\r
-#define RGU_RESET_CTRL1_UART2_RST_Pos 14 /*!< RGU RESET_CTRL1: UART2_RST Position */\r
-#define RGU_RESET_CTRL1_UART2_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos) /*!< RGU RESET_CTRL1: UART2_RST Mask */\r
-#define RGU_RESET_CTRL1_UART3_RST_Pos 15 /*!< RGU RESET_CTRL1: UART3_RST Position */\r
-#define RGU_RESET_CTRL1_UART3_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos) /*!< RGU RESET_CTRL1: UART3_RST Mask */\r
-#define RGU_RESET_CTRL1_I2C0_RST_Pos 16 /*!< RGU RESET_CTRL1: I2C0_RST Position */\r
-#define RGU_RESET_CTRL1_I2C0_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos) /*!< RGU RESET_CTRL1: I2C0_RST Mask */\r
-#define RGU_RESET_CTRL1_I2C1_RST_Pos 17 /*!< RGU RESET_CTRL1: I2C1_RST Position */\r
-#define RGU_RESET_CTRL1_I2C1_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos) /*!< RGU RESET_CTRL1: I2C1_RST Mask */\r
-#define RGU_RESET_CTRL1_SSP0_RST_Pos 18 /*!< RGU RESET_CTRL1: SSP0_RST Position */\r
-#define RGU_RESET_CTRL1_SSP0_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos) /*!< RGU RESET_CTRL1: SSP0_RST Mask */\r
-#define RGU_RESET_CTRL1_SSP1_RST_Pos 19 /*!< RGU RESET_CTRL1: SSP1_RST Position */\r
-#define RGU_RESET_CTRL1_SSP1_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos) /*!< RGU RESET_CTRL1: SSP1_RST Mask */\r
-#define RGU_RESET_CTRL1_I2S_RST_Pos 20 /*!< RGU RESET_CTRL1: I2S_RST Position */\r
-#define RGU_RESET_CTRL1_I2S_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos) /*!< RGU RESET_CTRL1: I2S_RST Mask */\r
-#define RGU_RESET_CTRL1_SPIFI_RST_Pos 21 /*!< RGU RESET_CTRL1: SPIFI_RST Position */\r
-#define RGU_RESET_CTRL1_SPIFI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos) /*!< RGU RESET_CTRL1: SPIFI_RST Mask */\r
-#define RGU_RESET_CTRL1_CAN1_RST_Pos 22 /*!< RGU RESET_CTRL1: CAN1_RST Position */\r
-#define RGU_RESET_CTRL1_CAN1_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos) /*!< RGU RESET_CTRL1: CAN1_RST Mask */\r
-#define RGU_RESET_CTRL1_CAN0_RST_Pos 23 /*!< RGU RESET_CTRL1: CAN0_RST Position */\r
-#define RGU_RESET_CTRL1_CAN0_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos) /*!< RGU RESET_CTRL1: CAN0_RST Mask */\r
-\r
-// ------------------------------------ RGU_RESET_STATUS0 ---------------------------------------\r
-#define RGU_RESET_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_STATUS0: CORE_RST Position */\r
-#define RGU_RESET_STATUS0_CORE_RST_Msk (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos) /*!< RGU RESET_STATUS0: CORE_RST Mask */\r
-#define RGU_RESET_STATUS0_PERIPH_RST_Pos 2 /*!< RGU RESET_STATUS0: PERIPH_RST Position */\r
-#define RGU_RESET_STATUS0_PERIPH_RST_Msk (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_STATUS0: PERIPH_RST Mask */\r
-#define RGU_RESET_STATUS0_MASTER_RST_Pos 4 /*!< RGU RESET_STATUS0: MASTER_RST Position */\r
-#define RGU_RESET_STATUS0_MASTER_RST_Msk (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_STATUS0: MASTER_RST Mask */\r
-#define RGU_RESET_STATUS0_WWDT_RST_Pos 8 /*!< RGU RESET_STATUS0: WWDT_RST Position */\r
-#define RGU_RESET_STATUS0_WWDT_RST_Msk (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_STATUS0: WWDT_RST Mask */\r
-#define RGU_RESET_STATUS0_CREG_RST_Pos 10 /*!< RGU RESET_STATUS0: CREG_RST Position */\r
-#define RGU_RESET_STATUS0_CREG_RST_Msk (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos) /*!< RGU RESET_STATUS0: CREG_RST Mask */\r
-#define RGU_RESET_STATUS0_BUS_RST_Pos 16 /*!< RGU RESET_STATUS0: BUS_RST Position */\r
-#define RGU_RESET_STATUS0_BUS_RST_Msk (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos) /*!< RGU RESET_STATUS0: BUS_RST Mask */\r
-#define RGU_RESET_STATUS0_SCU_RST_Pos 18 /*!< RGU RESET_STATUS0: SCU_RST Position */\r
-#define RGU_RESET_STATUS0_SCU_RST_Msk (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos) /*!< RGU RESET_STATUS0: SCU_RST Mask */\r
-#define RGU_RESET_STATUS0_M3_RST_Pos 26 /*!< RGU RESET_STATUS0: M3_RST Position */\r
-#define RGU_RESET_STATUS0_M3_RST_Msk (0x03UL << RGU_RESET_STATUS0_M3_RST_Pos) /*!< RGU RESET_STATUS0: M3_RST Mask */\r
-\r
-// ------------------------------------ RGU_RESET_STATUS1 ---------------------------------------\r
-#define RGU_RESET_STATUS1_LCD_RST_Pos 0 /*!< RGU RESET_STATUS1: LCD_RST Position */\r
-#define RGU_RESET_STATUS1_LCD_RST_Msk (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos) /*!< RGU RESET_STATUS1: LCD_RST Mask */\r
-#define RGU_RESET_STATUS1_USB0_RST_Pos 2 /*!< RGU RESET_STATUS1: USB0_RST Position */\r
-#define RGU_RESET_STATUS1_USB0_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos) /*!< RGU RESET_STATUS1: USB0_RST Mask */\r
-#define RGU_RESET_STATUS1_USB1_RST_Pos 4 /*!< RGU RESET_STATUS1: USB1_RST Position */\r
-#define RGU_RESET_STATUS1_USB1_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos) /*!< RGU RESET_STATUS1: USB1_RST Mask */\r
-#define RGU_RESET_STATUS1_DMA_RST_Pos 6 /*!< RGU RESET_STATUS1: DMA_RST Position */\r
-#define RGU_RESET_STATUS1_DMA_RST_Msk (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos) /*!< RGU RESET_STATUS1: DMA_RST Mask */\r
-#define RGU_RESET_STATUS1_SDIO_RST_Pos 8 /*!< RGU RESET_STATUS1: SDIO_RST Position */\r
-#define RGU_RESET_STATUS1_SDIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos) /*!< RGU RESET_STATUS1: SDIO_RST Mask */\r
-#define RGU_RESET_STATUS1_EMC_RST_Pos 10 /*!< RGU RESET_STATUS1: EMC_RST Position */\r
-#define RGU_RESET_STATUS1_EMC_RST_Msk (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos) /*!< RGU RESET_STATUS1: EMC_RST Mask */\r
-#define RGU_RESET_STATUS1_ETHERNET_RST_Pos 12 /*!< RGU RESET_STATUS1: ETHERNET_RST Position */\r
-#define RGU_RESET_STATUS1_ETHERNET_RST_Msk (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos) /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */\r
-#define RGU_RESET_STATUS1_GPIO_RST_Pos 24 /*!< RGU RESET_STATUS1: GPIO_RST Position */\r
-#define RGU_RESET_STATUS1_GPIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos) /*!< RGU RESET_STATUS1: GPIO_RST Mask */\r
-\r
-// ------------------------------------ RGU_RESET_STATUS2 ---------------------------------------\r
-#define RGU_RESET_STATUS2_TIMER0_RST_Pos 0 /*!< RGU RESET_STATUS2: TIMER0_RST Position */\r
-#define RGU_RESET_STATUS2_TIMER0_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos) /*!< RGU RESET_STATUS2: TIMER0_RST Mask */\r
-#define RGU_RESET_STATUS2_TIMER1_RST_Pos 2 /*!< RGU RESET_STATUS2: TIMER1_RST Position */\r
-#define RGU_RESET_STATUS2_TIMER1_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos) /*!< RGU RESET_STATUS2: TIMER1_RST Mask */\r
-#define RGU_RESET_STATUS2_TIMER2_RST_Pos 4 /*!< RGU RESET_STATUS2: TIMER2_RST Position */\r
-#define RGU_RESET_STATUS2_TIMER2_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos) /*!< RGU RESET_STATUS2: TIMER2_RST Mask */\r
-#define RGU_RESET_STATUS2_TIMER3_RST_Pos 6 /*!< RGU RESET_STATUS2: TIMER3_RST Position */\r
-#define RGU_RESET_STATUS2_TIMER3_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos) /*!< RGU RESET_STATUS2: TIMER3_RST Mask */\r
-#define RGU_RESET_STATUS2_RITIMER_RST_Pos 8 /*!< RGU RESET_STATUS2: RITIMER_RST Position */\r
-#define RGU_RESET_STATUS2_RITIMER_RST_Msk (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos) /*!< RGU RESET_STATUS2: RITIMER_RST Mask */\r
-#define RGU_RESET_STATUS2_SCT_RST_Pos 10 /*!< RGU RESET_STATUS2: SCT_RST Position */\r
-#define RGU_RESET_STATUS2_SCT_RST_Msk (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos) /*!< RGU RESET_STATUS2: SCT_RST Mask */\r
-#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos 12 /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */\r
-#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos) /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */\r
-#define RGU_RESET_STATUS2_QEI_RST_Pos 14 /*!< RGU RESET_STATUS2: QEI_RST Position */\r
-#define RGU_RESET_STATUS2_QEI_RST_Msk (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos) /*!< RGU RESET_STATUS2: QEI_RST Mask */\r
-#define RGU_RESET_STATUS2_ADC0_RST_Pos 16 /*!< RGU RESET_STATUS2: ADC0_RST Position */\r
-#define RGU_RESET_STATUS2_ADC0_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos) /*!< RGU RESET_STATUS2: ADC0_RST Mask */\r
-#define RGU_RESET_STATUS2_ADC1_RST_Pos 18 /*!< RGU RESET_STATUS2: ADC1_RST Position */\r
-#define RGU_RESET_STATUS2_ADC1_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos) /*!< RGU RESET_STATUS2: ADC1_RST Mask */\r
-#define RGU_RESET_STATUS2_DAC_RST_Pos 20 /*!< RGU RESET_STATUS2: DAC_RST Position */\r
-#define RGU_RESET_STATUS2_DAC_RST_Msk (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos) /*!< RGU RESET_STATUS2: DAC_RST Mask */\r
-#define RGU_RESET_STATUS2_UART0_RST_Pos 24 /*!< RGU RESET_STATUS2: UART0_RST Position */\r
-#define RGU_RESET_STATUS2_UART0_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos) /*!< RGU RESET_STATUS2: UART0_RST Mask */\r
-#define RGU_RESET_STATUS2_UART1_RST_Pos 26 /*!< RGU RESET_STATUS2: UART1_RST Position */\r
-#define RGU_RESET_STATUS2_UART1_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos) /*!< RGU RESET_STATUS2: UART1_RST Mask */\r
-#define RGU_RESET_STATUS2_UART2_RST_Pos 28 /*!< RGU RESET_STATUS2: UART2_RST Position */\r
-#define RGU_RESET_STATUS2_UART2_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos) /*!< RGU RESET_STATUS2: UART2_RST Mask */\r
-#define RGU_RESET_STATUS2_UART3_RST_Pos 30 /*!< RGU RESET_STATUS2: UART3_RST Position */\r
-#define RGU_RESET_STATUS2_UART3_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos) /*!< RGU RESET_STATUS2: UART3_RST Mask */\r
-\r
-// ------------------------------------ RGU_RESET_STATUS3 ---------------------------------------\r
-#define RGU_RESET_STATUS3_I2C0_RST_Pos 0 /*!< RGU RESET_STATUS3: I2C0_RST Position */\r
-#define RGU_RESET_STATUS3_I2C0_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos) /*!< RGU RESET_STATUS3: I2C0_RST Mask */\r
-#define RGU_RESET_STATUS3_I2C1_RST_Pos 2 /*!< RGU RESET_STATUS3: I2C1_RST Position */\r
-#define RGU_RESET_STATUS3_I2C1_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos) /*!< RGU RESET_STATUS3: I2C1_RST Mask */\r
-#define RGU_RESET_STATUS3_SSP0_RST_Pos 4 /*!< RGU RESET_STATUS3: SSP0_RST Position */\r
-#define RGU_RESET_STATUS3_SSP0_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos) /*!< RGU RESET_STATUS3: SSP0_RST Mask */\r
-#define RGU_RESET_STATUS3_SSP1_RST_Pos 6 /*!< RGU RESET_STATUS3: SSP1_RST Position */\r
-#define RGU_RESET_STATUS3_SSP1_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos) /*!< RGU RESET_STATUS3: SSP1_RST Mask */\r
-#define RGU_RESET_STATUS3_I2S_RST_Pos 8 /*!< RGU RESET_STATUS3: I2S_RST Position */\r
-#define RGU_RESET_STATUS3_I2S_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos) /*!< RGU RESET_STATUS3: I2S_RST Mask */\r
-#define RGU_RESET_STATUS3_SPIFI_RST_Pos 10 /*!< RGU RESET_STATUS3: SPIFI_RST Position */\r
-#define RGU_RESET_STATUS3_SPIFI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos) /*!< RGU RESET_STATUS3: SPIFI_RST Mask */\r
-#define RGU_RESET_STATUS3_CAN1_RST_Pos 12 /*!< RGU RESET_STATUS3: CAN1_RST Position */\r
-#define RGU_RESET_STATUS3_CAN1_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos) /*!< RGU RESET_STATUS3: CAN1_RST Mask */\r
-#define RGU_RESET_STATUS3_CAN0_RST_Pos 14 /*!< RGU RESET_STATUS3: CAN0_RST Position */\r
-#define RGU_RESET_STATUS3_CAN0_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos) /*!< RGU RESET_STATUS3: CAN0_RST Mask */\r
-\r
-// -------------------------------- RGU_RESET_ACTIVE_STATUS0 ------------------------------------\r
-#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos 28 /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */\r
-\r
-// -------------------------------- RGU_RESET_ACTIVE_STATUS1 ------------------------------------\r
-#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos 3 /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos 7 /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos 12 /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos 14 /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos 15 /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */\r
-#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos 23 /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */\r
-#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */\r
-\r
-// ----------------------------------- RGU_RESET_EXT_STAT0 --------------------------------------\r
-#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos 0 /*!< RGU RESET_EXT_STAT0: EXT_RESET Position */\r
-#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: EXT_RESET Mask */\r
-#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos 4 /*!< RGU RESET_EXT_STAT0: BOD_RESET Position */\r
-#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos) /*!< RGU RESET_EXT_STAT0: BOD_RESET Mask */\r
-#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos 5 /*!< RGU RESET_EXT_STAT0: WWDT_RESET Position */\r
-#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: WWDT_RESET Mask */\r
-\r
-// ----------------------------------- RGU_RESET_EXT_STAT1 --------------------------------------\r
-#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */\r
-#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */\r
-\r
-// ----------------------------------- RGU_RESET_EXT_STAT2 --------------------------------------\r
-#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */\r
-\r
-// ----------------------------------- RGU_RESET_EXT_STAT4 --------------------------------------\r
-#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT4: CORE_RESET Position */\r
-#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT4: CORE_RESET Mask */\r
-\r
-// ----------------------------------- RGU_RESET_EXT_STAT5 --------------------------------------\r
-#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */\r
-#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */\r
-\r
-// ----------------------------------- RGU_RESET_EXT_STAT8 --------------------------------------\r
-#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */\r
-\r
-// ----------------------------------- RGU_RESET_EXT_STAT9 --------------------------------------\r
-#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT13 --------------------------------------\r
-#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */\r
-#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT16 --------------------------------------\r
-#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */\r
-#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT17 --------------------------------------\r
-#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */\r
-#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT18 --------------------------------------\r
-#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */\r
-#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT19 --------------------------------------\r
-#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */\r
-#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT20 --------------------------------------\r
-#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */\r
-#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT21 --------------------------------------\r
-#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */\r
-#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT22 --------------------------------------\r
-#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */\r
-#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT23 --------------------------------------\r
-#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT23: MASTER_RESET Position */\r
-#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT23: MASTER_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT28 --------------------------------------\r
-#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT32 --------------------------------------\r
-#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT33 --------------------------------------\r
-#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT34 --------------------------------------\r
-#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT35 --------------------------------------\r
-#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT36 --------------------------------------\r
-#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT37 --------------------------------------\r
-#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT38 --------------------------------------\r
-#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT39 --------------------------------------\r
-#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT40 --------------------------------------\r
-#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT41 --------------------------------------\r
-#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT42 --------------------------------------\r
-#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT44 --------------------------------------\r
-#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT45 --------------------------------------\r
-#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT46 --------------------------------------\r
-#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT47 --------------------------------------\r
-#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT48 --------------------------------------\r
-#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT49 --------------------------------------\r
-#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT50 --------------------------------------\r
-#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT51 --------------------------------------\r
-#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT52 --------------------------------------\r
-#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT53 --------------------------------------\r
-#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT54 --------------------------------------\r
-#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */\r
-\r
-// ---------------------------------- RGU_RESET_EXT_STAT55 --------------------------------------\r
-#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */\r
-#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- WWDT Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- WWDT_MOD --------------------------------------------\r
-#define WWDT_MOD_WDEN_Pos 0 /*!< WWDT MOD: WDEN Position */\r
-#define WWDT_MOD_WDEN_Msk (0x01UL << WWDT_MOD_WDEN_Pos) /*!< WWDT MOD: WDEN Mask */\r
-#define WWDT_MOD_WDRESET_Pos 1 /*!< WWDT MOD: WDRESET Position */\r
-#define WWDT_MOD_WDRESET_Msk (0x01UL << WWDT_MOD_WDRESET_Pos) /*!< WWDT MOD: WDRESET Mask */\r
-#define WWDT_MOD_WDTOF_Pos 2 /*!< WWDT MOD: WDTOF Position */\r
-#define WWDT_MOD_WDTOF_Msk (0x01UL << WWDT_MOD_WDTOF_Pos) /*!< WWDT MOD: WDTOF Mask */\r
-#define WWDT_MOD_WDINT_Pos 3 /*!< WWDT MOD: WDINT Position */\r
-#define WWDT_MOD_WDINT_Msk (0x01UL << WWDT_MOD_WDINT_Pos) /*!< WWDT MOD: WDINT Mask */\r
-#define WWDT_MOD_WDPROTECT_Pos 4 /*!< WWDT MOD: WDPROTECT Position */\r
-#define WWDT_MOD_WDPROTECT_Msk (0x01UL << WWDT_MOD_WDPROTECT_Pos) /*!< WWDT MOD: WDPROTECT Mask */\r
-\r
-// ----------------------------------------- WWDT_TC --------------------------------------------\r
-#define WWDT_TC_WDTC_Pos 0 /*!< WWDT TC: WDTC Position */\r
-#define WWDT_TC_WDTC_Msk (0x00ffffffUL << WWDT_TC_WDTC_Pos) /*!< WWDT TC: WDTC Mask */\r
-\r
-// ---------------------------------------- WWDT_FEED -------------------------------------------\r
-#define WWDT_FEED_Feed_Pos 0 /*!< WWDT FEED: Feed Position */\r
-#define WWDT_FEED_Feed_Msk (0x000000ffUL << WWDT_FEED_Feed_Pos) /*!< WWDT FEED: Feed Mask */\r
-\r
-// ----------------------------------------- WWDT_TV --------------------------------------------\r
-#define WWDT_TV_Count_Pos 0 /*!< WWDT TV: Count Position */\r
-#define WWDT_TV_Count_Msk (0x00ffffffUL << WWDT_TV_Count_Pos) /*!< WWDT TV: Count Mask */\r
-\r
-// -------------------------------------- WWDT_WARNINT ------------------------------------------\r
-#define WWDT_WARNINT_WDWARNINT_Pos 0 /*!< WWDT WARNINT: WDWARNINT Position */\r
-#define WWDT_WARNINT_WDWARNINT_Msk (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos) /*!< WWDT WARNINT: WDWARNINT Mask */\r
-\r
-// --------------------------------------- WWDT_WINDOW ------------------------------------------\r
-#define WWDT_WINDOW_WDWINDOW_Pos 0 /*!< WWDT WINDOW: WDWINDOW Position */\r
-#define WWDT_WINDOW_WDWINDOW_Msk (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos) /*!< WWDT WINDOW: WDWINDOW Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- USART0 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- USART0_RBR -------------------------------------------\r
-#define USART0_RBR_RBR_Pos 0 /*!< USART0 RBR: RBR Position */\r
-#define USART0_RBR_RBR_Msk (0x000000ffUL << USART0_RBR_RBR_Pos) /*!< USART0 RBR: RBR Mask */\r
-\r
-// --------------------------------------- USART0_THR -------------------------------------------\r
-#define USART0_THR_THR_Pos 0 /*!< USART0 THR: THR Position */\r
-#define USART0_THR_THR_Msk (0x000000ffUL << USART0_THR_THR_Pos) /*!< USART0 THR: THR Mask */\r
-\r
-// --------------------------------------- USART0_DLL -------------------------------------------\r
-#define USART0_DLL_DLLSB_Pos 0 /*!< USART0 DLL: DLLSB Position */\r
-#define USART0_DLL_DLLSB_Msk (0x000000ffUL << USART0_DLL_DLLSB_Pos) /*!< USART0 DLL: DLLSB Mask */\r
-\r
-// --------------------------------------- USART0_DLM -------------------------------------------\r
-#define USART0_DLM_DLMSB_Pos 0 /*!< USART0 DLM: DLMSB Position */\r
-#define USART0_DLM_DLMSB_Msk (0x000000ffUL << USART0_DLM_DLMSB_Pos) /*!< USART0 DLM: DLMSB Mask */\r
-\r
-// --------------------------------------- USART0_IER -------------------------------------------\r
-#define USART0_IER_RBRIE_Pos 0 /*!< USART0 IER: RBRIE Position */\r
-#define USART0_IER_RBRIE_Msk (0x01UL << USART0_IER_RBRIE_Pos) /*!< USART0 IER: RBRIE Mask */\r
-#define USART0_IER_THREIE_Pos 1 /*!< USART0 IER: THREIE Position */\r
-#define USART0_IER_THREIE_Msk (0x01UL << USART0_IER_THREIE_Pos) /*!< USART0 IER: THREIE Mask */\r
-#define USART0_IER_RXIE_Pos 2 /*!< USART0 IER: RXIE Position */\r
-#define USART0_IER_RXIE_Msk (0x01UL << USART0_IER_RXIE_Pos) /*!< USART0 IER: RXIE Mask */\r
-#define USART0_IER_ABEOINTEN_Pos 8 /*!< USART0 IER: ABEOINTEN Position */\r
-#define USART0_IER_ABEOINTEN_Msk (0x01UL << USART0_IER_ABEOINTEN_Pos) /*!< USART0 IER: ABEOINTEN Mask */\r
-#define USART0_IER_ABTOINTEN_Pos 9 /*!< USART0 IER: ABTOINTEN Position */\r
-#define USART0_IER_ABTOINTEN_Msk (0x01UL << USART0_IER_ABTOINTEN_Pos) /*!< USART0 IER: ABTOINTEN Mask */\r
-\r
-// --------------------------------------- USART0_IIR -------------------------------------------\r
-#define USART0_IIR_INTSTATUS_Pos 0 /*!< USART0 IIR: INTSTATUS Position */\r
-#define USART0_IIR_INTSTATUS_Msk (0x01UL << USART0_IIR_INTSTATUS_Pos) /*!< USART0 IIR: INTSTATUS Mask */\r
-#define USART0_IIR_INTID_Pos 1 /*!< USART0 IIR: INTID Position */\r
-#define USART0_IIR_INTID_Msk (0x07UL << USART0_IIR_INTID_Pos) /*!< USART0 IIR: INTID Mask */\r
-#define USART0_IIR_FIFOENABLE_Pos 6 /*!< USART0 IIR: FIFOENABLE Position */\r
-#define USART0_IIR_FIFOENABLE_Msk (0x03UL << USART0_IIR_FIFOENABLE_Pos) /*!< USART0 IIR: FIFOENABLE Mask */\r
-#define USART0_IIR_ABEOINT_Pos 8 /*!< USART0 IIR: ABEOINT Position */\r
-#define USART0_IIR_ABEOINT_Msk (0x01UL << USART0_IIR_ABEOINT_Pos) /*!< USART0 IIR: ABEOINT Mask */\r
-#define USART0_IIR_ABTOINT_Pos 9 /*!< USART0 IIR: ABTOINT Position */\r
-#define USART0_IIR_ABTOINT_Msk (0x01UL << USART0_IIR_ABTOINT_Pos) /*!< USART0 IIR: ABTOINT Mask */\r
-\r
-// --------------------------------------- USART0_FCR -------------------------------------------\r
-#define USART0_FCR_FIFOEN_Pos 0 /*!< USART0 FCR: FIFOEN Position */\r
-#define USART0_FCR_FIFOEN_Msk (0x01UL << USART0_FCR_FIFOEN_Pos) /*!< USART0 FCR: FIFOEN Mask */\r
-#define USART0_FCR_RXFIFORES_Pos 1 /*!< USART0 FCR: RXFIFORES Position */\r
-#define USART0_FCR_RXFIFORES_Msk (0x01UL << USART0_FCR_RXFIFORES_Pos) /*!< USART0 FCR: RXFIFORES Mask */\r
-#define USART0_FCR_TXFIFORES_Pos 2 /*!< USART0 FCR: TXFIFORES Position */\r
-#define USART0_FCR_TXFIFORES_Msk (0x01UL << USART0_FCR_TXFIFORES_Pos) /*!< USART0 FCR: TXFIFORES Mask */\r
-#define USART0_FCR_DMAMODE_Pos 3 /*!< USART0 FCR: DMAMODE Position */\r
-#define USART0_FCR_DMAMODE_Msk (0x01UL << USART0_FCR_DMAMODE_Pos) /*!< USART0 FCR: DMAMODE Mask */\r
-#define USART0_FCR_RXTRIGLVL_Pos 6 /*!< USART0 FCR: RXTRIGLVL Position */\r
-#define USART0_FCR_RXTRIGLVL_Msk (0x03UL << USART0_FCR_RXTRIGLVL_Pos) /*!< USART0 FCR: RXTRIGLVL Mask */\r
-\r
-// --------------------------------------- USART0_LCR -------------------------------------------\r
-#define USART0_LCR_WLS_Pos 0 /*!< USART0 LCR: WLS Position */\r
-#define USART0_LCR_WLS_Msk (0x03UL << USART0_LCR_WLS_Pos) /*!< USART0 LCR: WLS Mask */\r
-#define USART0_LCR_SBS_Pos 2 /*!< USART0 LCR: SBS Position */\r
-#define USART0_LCR_SBS_Msk (0x01UL << USART0_LCR_SBS_Pos) /*!< USART0 LCR: SBS Mask */\r
-#define USART0_LCR_PE_Pos 3 /*!< USART0 LCR: PE Position */\r
-#define USART0_LCR_PE_Msk (0x01UL << USART0_LCR_PE_Pos) /*!< USART0 LCR: PE Mask */\r
-#define USART0_LCR_PS_Pos 4 /*!< USART0 LCR: PS Position */\r
-#define USART0_LCR_PS_Msk (0x03UL << USART0_LCR_PS_Pos) /*!< USART0 LCR: PS Mask */\r
-#define USART0_LCR_BC_Pos 6 /*!< USART0 LCR: BC Position */\r
-#define USART0_LCR_BC_Msk (0x01UL << USART0_LCR_BC_Pos) /*!< USART0 LCR: BC Mask */\r
-#define USART0_LCR_DLAB_Pos 7 /*!< USART0 LCR: DLAB Position */\r
-#define USART0_LCR_DLAB_Msk (0x01UL << USART0_LCR_DLAB_Pos) /*!< USART0 LCR: DLAB Mask */\r
-\r
-// --------------------------------------- USART0_LSR -------------------------------------------\r
-#define USART0_LSR_RDR_Pos 0 /*!< USART0 LSR: RDR Position */\r
-#define USART0_LSR_RDR_Msk (0x01UL << USART0_LSR_RDR_Pos) /*!< USART0 LSR: RDR Mask */\r
-#define USART0_LSR_OE_Pos 1 /*!< USART0 LSR: OE Position */\r
-#define USART0_LSR_OE_Msk (0x01UL << USART0_LSR_OE_Pos) /*!< USART0 LSR: OE Mask */\r
-#define USART0_LSR_PE_Pos 2 /*!< USART0 LSR: PE Position */\r
-#define USART0_LSR_PE_Msk (0x01UL << USART0_LSR_PE_Pos) /*!< USART0 LSR: PE Mask */\r
-#define USART0_LSR_FE_Pos 3 /*!< USART0 LSR: FE Position */\r
-#define USART0_LSR_FE_Msk (0x01UL << USART0_LSR_FE_Pos) /*!< USART0 LSR: FE Mask */\r
-#define USART0_LSR_BI_Pos 4 /*!< USART0 LSR: BI Position */\r
-#define USART0_LSR_BI_Msk (0x01UL << USART0_LSR_BI_Pos) /*!< USART0 LSR: BI Mask */\r
-#define USART0_LSR_THRE_Pos 5 /*!< USART0 LSR: THRE Position */\r
-#define USART0_LSR_THRE_Msk (0x01UL << USART0_LSR_THRE_Pos) /*!< USART0 LSR: THRE Mask */\r
-#define USART0_LSR_TEMT_Pos 6 /*!< USART0 LSR: TEMT Position */\r
-#define USART0_LSR_TEMT_Msk (0x01UL << USART0_LSR_TEMT_Pos) /*!< USART0 LSR: TEMT Mask */\r
-#define USART0_LSR_RXFE_Pos 7 /*!< USART0 LSR: RXFE Position */\r
-#define USART0_LSR_RXFE_Msk (0x01UL << USART0_LSR_RXFE_Pos) /*!< USART0 LSR: RXFE Mask */\r
-#define USART0_LSR_TXERR_Pos 8 /*!< USART0 LSR: TXERR Position */\r
-#define USART0_LSR_TXERR_Msk (0x01UL << USART0_LSR_TXERR_Pos) /*!< USART0 LSR: TXERR Mask */\r
-\r
-// --------------------------------------- USART0_SCR -------------------------------------------\r
-#define USART0_SCR_PAD_Pos 0 /*!< USART0 SCR: PAD Position */\r
-#define USART0_SCR_PAD_Msk (0x000000ffUL << USART0_SCR_PAD_Pos) /*!< USART0 SCR: PAD Mask */\r
-\r
-// --------------------------------------- USART0_ACR -------------------------------------------\r
-#define USART0_ACR_START_Pos 0 /*!< USART0 ACR: START Position */\r
-#define USART0_ACR_START_Msk (0x01UL << USART0_ACR_START_Pos) /*!< USART0 ACR: START Mask */\r
-#define USART0_ACR_MODE_Pos 1 /*!< USART0 ACR: MODE Position */\r
-#define USART0_ACR_MODE_Msk (0x01UL << USART0_ACR_MODE_Pos) /*!< USART0 ACR: MODE Mask */\r
-#define USART0_ACR_AUTORESTART_Pos 2 /*!< USART0 ACR: AUTORESTART Position */\r
-#define USART0_ACR_AUTORESTART_Msk (0x01UL << USART0_ACR_AUTORESTART_Pos) /*!< USART0 ACR: AUTORESTART Mask */\r
-#define USART0_ACR_ABEOINTCLR_Pos 8 /*!< USART0 ACR: ABEOINTCLR Position */\r
-#define USART0_ACR_ABEOINTCLR_Msk (0x01UL << USART0_ACR_ABEOINTCLR_Pos) /*!< USART0 ACR: ABEOINTCLR Mask */\r
-#define USART0_ACR_ABTOINTCLR_Pos 9 /*!< USART0 ACR: ABTOINTCLR Position */\r
-#define USART0_ACR_ABTOINTCLR_Msk (0x01UL << USART0_ACR_ABTOINTCLR_Pos) /*!< USART0 ACR: ABTOINTCLR Mask */\r
-\r
-// --------------------------------------- USART0_ICR -------------------------------------------\r
-#define USART0_ICR_IRDAEN_Pos 0 /*!< USART0 ICR: IRDAEN Position */\r
-#define USART0_ICR_IRDAEN_Msk (0x01UL << USART0_ICR_IRDAEN_Pos) /*!< USART0 ICR: IRDAEN Mask */\r
-#define USART0_ICR_IRDAINV_Pos 1 /*!< USART0 ICR: IRDAINV Position */\r
-#define USART0_ICR_IRDAINV_Msk (0x01UL << USART0_ICR_IRDAINV_Pos) /*!< USART0 ICR: IRDAINV Mask */\r
-#define USART0_ICR_FIXPULSEEN_Pos 2 /*!< USART0 ICR: FIXPULSEEN Position */\r
-#define USART0_ICR_FIXPULSEEN_Msk (0x01UL << USART0_ICR_FIXPULSEEN_Pos) /*!< USART0 ICR: FIXPULSEEN Mask */\r
-#define USART0_ICR_PULSEDIV_Pos 3 /*!< USART0 ICR: PULSEDIV Position */\r
-#define USART0_ICR_PULSEDIV_Msk (0x07UL << USART0_ICR_PULSEDIV_Pos) /*!< USART0 ICR: PULSEDIV Mask */\r
-\r
-// --------------------------------------- USART0_FDR -------------------------------------------\r
-#define USART0_FDR_DIVADDVAL_Pos 0 /*!< USART0 FDR: DIVADDVAL Position */\r
-#define USART0_FDR_DIVADDVAL_Msk (0x0fUL << USART0_FDR_DIVADDVAL_Pos) /*!< USART0 FDR: DIVADDVAL Mask */\r
-#define USART0_FDR_MULVAL_Pos 4 /*!< USART0 FDR: MULVAL Position */\r
-#define USART0_FDR_MULVAL_Msk (0x0fUL << USART0_FDR_MULVAL_Pos) /*!< USART0 FDR: MULVAL Mask */\r
-\r
-// --------------------------------------- USART0_OSR -------------------------------------------\r
-#define USART0_OSR_OSFRAC_Pos 1 /*!< USART0 OSR: OSFRAC Position */\r
-#define USART0_OSR_OSFRAC_Msk (0x07UL << USART0_OSR_OSFRAC_Pos) /*!< USART0 OSR: OSFRAC Mask */\r
-#define USART0_OSR_OSINT_Pos 4 /*!< USART0 OSR: OSINT Position */\r
-#define USART0_OSR_OSINT_Msk (0x0fUL << USART0_OSR_OSINT_Pos) /*!< USART0 OSR: OSINT Mask */\r
-#define USART0_OSR_FDINT_Pos 8 /*!< USART0 OSR: FDINT Position */\r
-#define USART0_OSR_FDINT_Msk (0x7fUL << USART0_OSR_FDINT_Pos) /*!< USART0 OSR: FDINT Mask */\r
-\r
-// --------------------------------------- USART0_HDEN ------------------------------------------\r
-#define USART0_HDEN_HDEN_Pos 0 /*!< USART0 HDEN: HDEN Position */\r
-#define USART0_HDEN_HDEN_Msk (0x01UL << USART0_HDEN_HDEN_Pos) /*!< USART0 HDEN: HDEN Mask */\r
-\r
-// ------------------------------------- USART0_SCICTRL -----------------------------------------\r
-#define USART0_SCICTRL_SCIEN_Pos 0 /*!< USART0 SCICTRL: SCIEN Position */\r
-#define USART0_SCICTRL_SCIEN_Msk (0x01UL << USART0_SCICTRL_SCIEN_Pos) /*!< USART0 SCICTRL: SCIEN Mask */\r
-#define USART0_SCICTRL_NACKDIS_Pos 1 /*!< USART0 SCICTRL: NACKDIS Position */\r
-#define USART0_SCICTRL_NACKDIS_Msk (0x01UL << USART0_SCICTRL_NACKDIS_Pos) /*!< USART0 SCICTRL: NACKDIS Mask */\r
-#define USART0_SCICTRL_PROTSEL_Pos 2 /*!< USART0 SCICTRL: PROTSEL Position */\r
-#define USART0_SCICTRL_PROTSEL_Msk (0x01UL << USART0_SCICTRL_PROTSEL_Pos) /*!< USART0 SCICTRL: PROTSEL Mask */\r
-#define USART0_SCICTRL_TXRETRY_Pos 5 /*!< USART0 SCICTRL: TXRETRY Position */\r
-#define USART0_SCICTRL_TXRETRY_Msk (0x07UL << USART0_SCICTRL_TXRETRY_Pos) /*!< USART0 SCICTRL: TXRETRY Mask */\r
-#define USART0_SCICTRL_GUARDTIME_Pos 8 /*!< USART0 SCICTRL: GUARDTIME Position */\r
-#define USART0_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos) /*!< USART0 SCICTRL: GUARDTIME Mask */\r
-\r
-// ------------------------------------ USART0_RS485CTRL ----------------------------------------\r
-#define USART0_RS485CTRL_NMMEN_Pos 0 /*!< USART0 RS485CTRL: NMMEN Position */\r
-#define USART0_RS485CTRL_NMMEN_Msk (0x01UL << USART0_RS485CTRL_NMMEN_Pos) /*!< USART0 RS485CTRL: NMMEN Mask */\r
-#define USART0_RS485CTRL_RXDIS_Pos 1 /*!< USART0 RS485CTRL: RXDIS Position */\r
-#define USART0_RS485CTRL_RXDIS_Msk (0x01UL << USART0_RS485CTRL_RXDIS_Pos) /*!< USART0 RS485CTRL: RXDIS Mask */\r
-#define USART0_RS485CTRL_AADEN_Pos 2 /*!< USART0 RS485CTRL: AADEN Position */\r
-#define USART0_RS485CTRL_AADEN_Msk (0x01UL << USART0_RS485CTRL_AADEN_Pos) /*!< USART0 RS485CTRL: AADEN Mask */\r
-#define USART0_RS485CTRL_DCTRL_Pos 4 /*!< USART0 RS485CTRL: DCTRL Position */\r
-#define USART0_RS485CTRL_DCTRL_Msk (0x01UL << USART0_RS485CTRL_DCTRL_Pos) /*!< USART0 RS485CTRL: DCTRL Mask */\r
-#define USART0_RS485CTRL_OINV_Pos 5 /*!< USART0 RS485CTRL: OINV Position */\r
-#define USART0_RS485CTRL_OINV_Msk (0x01UL << USART0_RS485CTRL_OINV_Pos) /*!< USART0 RS485CTRL: OINV Mask */\r
-\r
-// ---------------------------------- USART0_RS485ADRMATCH --------------------------------------\r
-#define USART0_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART0 RS485ADRMATCH: ADRMATCH Position */\r
-#define USART0_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */\r
-\r
-// ------------------------------------- USART0_RS485DLY ----------------------------------------\r
-#define USART0_RS485DLY_DLY_Pos 0 /*!< USART0 RS485DLY: DLY Position */\r
-#define USART0_RS485DLY_DLY_Msk (0x000000ffUL << USART0_RS485DLY_DLY_Pos) /*!< USART0 RS485DLY: DLY Mask */\r
-\r
-// ------------------------------------- USART0_SYNCCTRL ----------------------------------------\r
-#define USART0_SYNCCTRL_SYNC_Pos 0 /*!< USART0 SYNCCTRL: SYNC Position */\r
-#define USART0_SYNCCTRL_SYNC_Msk (0x01UL << USART0_SYNCCTRL_SYNC_Pos) /*!< USART0 SYNCCTRL: SYNC Mask */\r
-#define USART0_SYNCCTRL_CSRC_Pos 1 /*!< USART0 SYNCCTRL: CSRC Position */\r
-#define USART0_SYNCCTRL_CSRC_Msk (0x01UL << USART0_SYNCCTRL_CSRC_Pos) /*!< USART0 SYNCCTRL: CSRC Mask */\r
-#define USART0_SYNCCTRL_FES_Pos 2 /*!< USART0 SYNCCTRL: FES Position */\r
-#define USART0_SYNCCTRL_FES_Msk (0x01UL << USART0_SYNCCTRL_FES_Pos) /*!< USART0 SYNCCTRL: FES Mask */\r
-#define USART0_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART0 SYNCCTRL: TSBYPASS Position */\r
-#define USART0_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos) /*!< USART0 SYNCCTRL: TSBYPASS Mask */\r
-#define USART0_SYNCCTRL_CSCEN_Pos 4 /*!< USART0 SYNCCTRL: CSCEN Position */\r
-#define USART0_SYNCCTRL_CSCEN_Msk (0x01UL << USART0_SYNCCTRL_CSCEN_Pos) /*!< USART0 SYNCCTRL: CSCEN Mask */\r
-#define USART0_SYNCCTRL_SSSDIS_Pos 5 /*!< USART0 SYNCCTRL: SSSDIS Position */\r
-#define USART0_SYNCCTRL_SSSDIS_Msk (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos) /*!< USART0 SYNCCTRL: SSSDIS Mask */\r
-#define USART0_SYNCCTRL_CCCLR_Pos 6 /*!< USART0 SYNCCTRL: CCCLR Position */\r
-#define USART0_SYNCCTRL_CCCLR_Msk (0x01UL << USART0_SYNCCTRL_CCCLR_Pos) /*!< USART0 SYNCCTRL: CCCLR Mask */\r
-\r
-// --------------------------------------- USART0_TER -------------------------------------------\r
-#define USART0_TER_TXEN_Pos 0 /*!< USART0 TER: TXEN Position */\r
-#define USART0_TER_TXEN_Msk (0x01UL << USART0_TER_TXEN_Pos) /*!< USART0 TER: TXEN Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- USART2 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- USART2_DLL -------------------------------------------\r
-#define USART2_DLL_DLLSB_Pos 0 /*!< USART2 DLL: DLLSB Position */\r
-#define USART2_DLL_DLLSB_Msk (0x000000ffUL << USART2_DLL_DLLSB_Pos) /*!< USART2 DLL: DLLSB Mask */\r
-\r
-// --------------------------------------- USART2_THR -------------------------------------------\r
-#define USART2_THR_THR_Pos 0 /*!< USART2 THR: THR Position */\r
-#define USART2_THR_THR_Msk (0x000000ffUL << USART2_THR_THR_Pos) /*!< USART2 THR: THR Mask */\r
-\r
-// --------------------------------------- USART2_RBR -------------------------------------------\r
-#define USART2_RBR_RBR_Pos 0 /*!< USART2 RBR: RBR Position */\r
-#define USART2_RBR_RBR_Msk (0x000000ffUL << USART2_RBR_RBR_Pos) /*!< USART2 RBR: RBR Mask */\r
-\r
-// --------------------------------------- USART2_IER -------------------------------------------\r
-#define USART2_IER_RBRIE_Pos 0 /*!< USART2 IER: RBRIE Position */\r
-#define USART2_IER_RBRIE_Msk (0x01UL << USART2_IER_RBRIE_Pos) /*!< USART2 IER: RBRIE Mask */\r
-#define USART2_IER_THREIE_Pos 1 /*!< USART2 IER: THREIE Position */\r
-#define USART2_IER_THREIE_Msk (0x01UL << USART2_IER_THREIE_Pos) /*!< USART2 IER: THREIE Mask */\r
-#define USART2_IER_RXIE_Pos 2 /*!< USART2 IER: RXIE Position */\r
-#define USART2_IER_RXIE_Msk (0x01UL << USART2_IER_RXIE_Pos) /*!< USART2 IER: RXIE Mask */\r
-#define USART2_IER_ABEOINTEN_Pos 8 /*!< USART2 IER: ABEOINTEN Position */\r
-#define USART2_IER_ABEOINTEN_Msk (0x01UL << USART2_IER_ABEOINTEN_Pos) /*!< USART2 IER: ABEOINTEN Mask */\r
-#define USART2_IER_ABTOINTEN_Pos 9 /*!< USART2 IER: ABTOINTEN Position */\r
-#define USART2_IER_ABTOINTEN_Msk (0x01UL << USART2_IER_ABTOINTEN_Pos) /*!< USART2 IER: ABTOINTEN Mask */\r
-\r
-// --------------------------------------- USART2_DLM -------------------------------------------\r
-#define USART2_DLM_DLMSB_Pos 0 /*!< USART2 DLM: DLMSB Position */\r
-#define USART2_DLM_DLMSB_Msk (0x000000ffUL << USART2_DLM_DLMSB_Pos) /*!< USART2 DLM: DLMSB Mask */\r
-\r
-// --------------------------------------- USART2_FCR -------------------------------------------\r
-#define USART2_FCR_FIFOEN_Pos 0 /*!< USART2 FCR: FIFOEN Position */\r
-#define USART2_FCR_FIFOEN_Msk (0x01UL << USART2_FCR_FIFOEN_Pos) /*!< USART2 FCR: FIFOEN Mask */\r
-#define USART2_FCR_RXFIFORES_Pos 1 /*!< USART2 FCR: RXFIFORES Position */\r
-#define USART2_FCR_RXFIFORES_Msk (0x01UL << USART2_FCR_RXFIFORES_Pos) /*!< USART2 FCR: RXFIFORES Mask */\r
-#define USART2_FCR_TXFIFORES_Pos 2 /*!< USART2 FCR: TXFIFORES Position */\r
-#define USART2_FCR_TXFIFORES_Msk (0x01UL << USART2_FCR_TXFIFORES_Pos) /*!< USART2 FCR: TXFIFORES Mask */\r
-#define USART2_FCR_DMAMODE_Pos 3 /*!< USART2 FCR: DMAMODE Position */\r
-#define USART2_FCR_DMAMODE_Msk (0x01UL << USART2_FCR_DMAMODE_Pos) /*!< USART2 FCR: DMAMODE Mask */\r
-#define USART2_FCR_RXTRIGLVL_Pos 6 /*!< USART2 FCR: RXTRIGLVL Position */\r
-#define USART2_FCR_RXTRIGLVL_Msk (0x03UL << USART2_FCR_RXTRIGLVL_Pos) /*!< USART2 FCR: RXTRIGLVL Mask */\r
-\r
-// --------------------------------------- USART2_IIR -------------------------------------------\r
-#define USART2_IIR_INTSTATUS_Pos 0 /*!< USART2 IIR: INTSTATUS Position */\r
-#define USART2_IIR_INTSTATUS_Msk (0x01UL << USART2_IIR_INTSTATUS_Pos) /*!< USART2 IIR: INTSTATUS Mask */\r
-#define USART2_IIR_INTID_Pos 1 /*!< USART2 IIR: INTID Position */\r
-#define USART2_IIR_INTID_Msk (0x07UL << USART2_IIR_INTID_Pos) /*!< USART2 IIR: INTID Mask */\r
-#define USART2_IIR_FIFOENABLE_Pos 6 /*!< USART2 IIR: FIFOENABLE Position */\r
-#define USART2_IIR_FIFOENABLE_Msk (0x03UL << USART2_IIR_FIFOENABLE_Pos) /*!< USART2 IIR: FIFOENABLE Mask */\r
-#define USART2_IIR_ABEOINT_Pos 8 /*!< USART2 IIR: ABEOINT Position */\r
-#define USART2_IIR_ABEOINT_Msk (0x01UL << USART2_IIR_ABEOINT_Pos) /*!< USART2 IIR: ABEOINT Mask */\r
-#define USART2_IIR_ABTOINT_Pos 9 /*!< USART2 IIR: ABTOINT Position */\r
-#define USART2_IIR_ABTOINT_Msk (0x01UL << USART2_IIR_ABTOINT_Pos) /*!< USART2 IIR: ABTOINT Mask */\r
-\r
-// --------------------------------------- USART2_LCR -------------------------------------------\r
-#define USART2_LCR_WLS_Pos 0 /*!< USART2 LCR: WLS Position */\r
-#define USART2_LCR_WLS_Msk (0x03UL << USART2_LCR_WLS_Pos) /*!< USART2 LCR: WLS Mask */\r
-#define USART2_LCR_SBS_Pos 2 /*!< USART2 LCR: SBS Position */\r
-#define USART2_LCR_SBS_Msk (0x01UL << USART2_LCR_SBS_Pos) /*!< USART2 LCR: SBS Mask */\r
-#define USART2_LCR_PE_Pos 3 /*!< USART2 LCR: PE Position */\r
-#define USART2_LCR_PE_Msk (0x01UL << USART2_LCR_PE_Pos) /*!< USART2 LCR: PE Mask */\r
-#define USART2_LCR_PS_Pos 4 /*!< USART2 LCR: PS Position */\r
-#define USART2_LCR_PS_Msk (0x03UL << USART2_LCR_PS_Pos) /*!< USART2 LCR: PS Mask */\r
-#define USART2_LCR_BC_Pos 6 /*!< USART2 LCR: BC Position */\r
-#define USART2_LCR_BC_Msk (0x01UL << USART2_LCR_BC_Pos) /*!< USART2 LCR: BC Mask */\r
-#define USART2_LCR_DLAB_Pos 7 /*!< USART2 LCR: DLAB Position */\r
-#define USART2_LCR_DLAB_Msk (0x01UL << USART2_LCR_DLAB_Pos) /*!< USART2 LCR: DLAB Mask */\r
-\r
-// --------------------------------------- USART2_LSR -------------------------------------------\r
-#define USART2_LSR_RDR_Pos 0 /*!< USART2 LSR: RDR Position */\r
-#define USART2_LSR_RDR_Msk (0x01UL << USART2_LSR_RDR_Pos) /*!< USART2 LSR: RDR Mask */\r
-#define USART2_LSR_OE_Pos 1 /*!< USART2 LSR: OE Position */\r
-#define USART2_LSR_OE_Msk (0x01UL << USART2_LSR_OE_Pos) /*!< USART2 LSR: OE Mask */\r
-#define USART2_LSR_PE_Pos 2 /*!< USART2 LSR: PE Position */\r
-#define USART2_LSR_PE_Msk (0x01UL << USART2_LSR_PE_Pos) /*!< USART2 LSR: PE Mask */\r
-#define USART2_LSR_FE_Pos 3 /*!< USART2 LSR: FE Position */\r
-#define USART2_LSR_FE_Msk (0x01UL << USART2_LSR_FE_Pos) /*!< USART2 LSR: FE Mask */\r
-#define USART2_LSR_BI_Pos 4 /*!< USART2 LSR: BI Position */\r
-#define USART2_LSR_BI_Msk (0x01UL << USART2_LSR_BI_Pos) /*!< USART2 LSR: BI Mask */\r
-#define USART2_LSR_THRE_Pos 5 /*!< USART2 LSR: THRE Position */\r
-#define USART2_LSR_THRE_Msk (0x01UL << USART2_LSR_THRE_Pos) /*!< USART2 LSR: THRE Mask */\r
-#define USART2_LSR_TEMT_Pos 6 /*!< USART2 LSR: TEMT Position */\r
-#define USART2_LSR_TEMT_Msk (0x01UL << USART2_LSR_TEMT_Pos) /*!< USART2 LSR: TEMT Mask */\r
-#define USART2_LSR_RXFE_Pos 7 /*!< USART2 LSR: RXFE Position */\r
-#define USART2_LSR_RXFE_Msk (0x01UL << USART2_LSR_RXFE_Pos) /*!< USART2 LSR: RXFE Mask */\r
-#define USART2_LSR_TXERR_Pos 8 /*!< USART2 LSR: TXERR Position */\r
-#define USART2_LSR_TXERR_Msk (0x01UL << USART2_LSR_TXERR_Pos) /*!< USART2 LSR: TXERR Mask */\r
-\r
-// --------------------------------------- USART2_SCR -------------------------------------------\r
-#define USART2_SCR_PAD_Pos 0 /*!< USART2 SCR: PAD Position */\r
-#define USART2_SCR_PAD_Msk (0x000000ffUL << USART2_SCR_PAD_Pos) /*!< USART2 SCR: PAD Mask */\r
-\r
-// --------------------------------------- USART2_ACR -------------------------------------------\r
-#define USART2_ACR_START_Pos 0 /*!< USART2 ACR: START Position */\r
-#define USART2_ACR_START_Msk (0x01UL << USART2_ACR_START_Pos) /*!< USART2 ACR: START Mask */\r
-#define USART2_ACR_MODE_Pos 1 /*!< USART2 ACR: MODE Position */\r
-#define USART2_ACR_MODE_Msk (0x01UL << USART2_ACR_MODE_Pos) /*!< USART2 ACR: MODE Mask */\r
-#define USART2_ACR_AUTORESTART_Pos 2 /*!< USART2 ACR: AUTORESTART Position */\r
-#define USART2_ACR_AUTORESTART_Msk (0x01UL << USART2_ACR_AUTORESTART_Pos) /*!< USART2 ACR: AUTORESTART Mask */\r
-#define USART2_ACR_ABEOINTCLR_Pos 8 /*!< USART2 ACR: ABEOINTCLR Position */\r
-#define USART2_ACR_ABEOINTCLR_Msk (0x01UL << USART2_ACR_ABEOINTCLR_Pos) /*!< USART2 ACR: ABEOINTCLR Mask */\r
-#define USART2_ACR_ABTOINTCLR_Pos 9 /*!< USART2 ACR: ABTOINTCLR Position */\r
-#define USART2_ACR_ABTOINTCLR_Msk (0x01UL << USART2_ACR_ABTOINTCLR_Pos) /*!< USART2 ACR: ABTOINTCLR Mask */\r
-\r
-// --------------------------------------- USART2_ICR -------------------------------------------\r
-#define USART2_ICR_IRDAEN_Pos 0 /*!< USART2 ICR: IRDAEN Position */\r
-#define USART2_ICR_IRDAEN_Msk (0x01UL << USART2_ICR_IRDAEN_Pos) /*!< USART2 ICR: IRDAEN Mask */\r
-#define USART2_ICR_IRDAINV_Pos 1 /*!< USART2 ICR: IRDAINV Position */\r
-#define USART2_ICR_IRDAINV_Msk (0x01UL << USART2_ICR_IRDAINV_Pos) /*!< USART2 ICR: IRDAINV Mask */\r
-#define USART2_ICR_FIXPULSEEN_Pos 2 /*!< USART2 ICR: FIXPULSEEN Position */\r
-#define USART2_ICR_FIXPULSEEN_Msk (0x01UL << USART2_ICR_FIXPULSEEN_Pos) /*!< USART2 ICR: FIXPULSEEN Mask */\r
-#define USART2_ICR_PULSEDIV_Pos 3 /*!< USART2 ICR: PULSEDIV Position */\r
-#define USART2_ICR_PULSEDIV_Msk (0x07UL << USART2_ICR_PULSEDIV_Pos) /*!< USART2 ICR: PULSEDIV Mask */\r
-\r
-// --------------------------------------- USART2_FDR -------------------------------------------\r
-#define USART2_FDR_DIVADDVAL_Pos 0 /*!< USART2 FDR: DIVADDVAL Position */\r
-#define USART2_FDR_DIVADDVAL_Msk (0x0fUL << USART2_FDR_DIVADDVAL_Pos) /*!< USART2 FDR: DIVADDVAL Mask */\r
-#define USART2_FDR_MULVAL_Pos 4 /*!< USART2 FDR: MULVAL Position */\r
-#define USART2_FDR_MULVAL_Msk (0x0fUL << USART2_FDR_MULVAL_Pos) /*!< USART2 FDR: MULVAL Mask */\r
-\r
-// --------------------------------------- USART2_OSR -------------------------------------------\r
-#define USART2_OSR_OSFRAC_Pos 1 /*!< USART2 OSR: OSFRAC Position */\r
-#define USART2_OSR_OSFRAC_Msk (0x07UL << USART2_OSR_OSFRAC_Pos) /*!< USART2 OSR: OSFRAC Mask */\r
-#define USART2_OSR_OSINT_Pos 4 /*!< USART2 OSR: OSINT Position */\r
-#define USART2_OSR_OSINT_Msk (0x0fUL << USART2_OSR_OSINT_Pos) /*!< USART2 OSR: OSINT Mask */\r
-#define USART2_OSR_FDINT_Pos 8 /*!< USART2 OSR: FDINT Position */\r
-#define USART2_OSR_FDINT_Msk (0x7fUL << USART2_OSR_FDINT_Pos) /*!< USART2 OSR: FDINT Mask */\r
-\r
-// --------------------------------------- USART2_HDEN ------------------------------------------\r
-#define USART2_HDEN_HDEN_Pos 0 /*!< USART2 HDEN: HDEN Position */\r
-#define USART2_HDEN_HDEN_Msk (0x01UL << USART2_HDEN_HDEN_Pos) /*!< USART2 HDEN: HDEN Mask */\r
-\r
-// ------------------------------------- USART2_SCICTRL -----------------------------------------\r
-#define USART2_SCICTRL_SCIEN_Pos 0 /*!< USART2 SCICTRL: SCIEN Position */\r
-#define USART2_SCICTRL_SCIEN_Msk (0x01UL << USART2_SCICTRL_SCIEN_Pos) /*!< USART2 SCICTRL: SCIEN Mask */\r
-#define USART2_SCICTRL_NACKDIS_Pos 1 /*!< USART2 SCICTRL: NACKDIS Position */\r
-#define USART2_SCICTRL_NACKDIS_Msk (0x01UL << USART2_SCICTRL_NACKDIS_Pos) /*!< USART2 SCICTRL: NACKDIS Mask */\r
-#define USART2_SCICTRL_PROTSEL_Pos 2 /*!< USART2 SCICTRL: PROTSEL Position */\r
-#define USART2_SCICTRL_PROTSEL_Msk (0x01UL << USART2_SCICTRL_PROTSEL_Pos) /*!< USART2 SCICTRL: PROTSEL Mask */\r
-#define USART2_SCICTRL_TXRETRY_Pos 5 /*!< USART2 SCICTRL: TXRETRY Position */\r
-#define USART2_SCICTRL_TXRETRY_Msk (0x07UL << USART2_SCICTRL_TXRETRY_Pos) /*!< USART2 SCICTRL: TXRETRY Mask */\r
-#define USART2_SCICTRL_GUARDTIME_Pos 8 /*!< USART2 SCICTRL: GUARDTIME Position */\r
-#define USART2_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos) /*!< USART2 SCICTRL: GUARDTIME Mask */\r
-\r
-// ------------------------------------ USART2_RS485CTRL ----------------------------------------\r
-#define USART2_RS485CTRL_NMMEN_Pos 0 /*!< USART2 RS485CTRL: NMMEN Position */\r
-#define USART2_RS485CTRL_NMMEN_Msk (0x01UL << USART2_RS485CTRL_NMMEN_Pos) /*!< USART2 RS485CTRL: NMMEN Mask */\r
-#define USART2_RS485CTRL_RXDIS_Pos 1 /*!< USART2 RS485CTRL: RXDIS Position */\r
-#define USART2_RS485CTRL_RXDIS_Msk (0x01UL << USART2_RS485CTRL_RXDIS_Pos) /*!< USART2 RS485CTRL: RXDIS Mask */\r
-#define USART2_RS485CTRL_AADEN_Pos 2 /*!< USART2 RS485CTRL: AADEN Position */\r
-#define USART2_RS485CTRL_AADEN_Msk (0x01UL << USART2_RS485CTRL_AADEN_Pos) /*!< USART2 RS485CTRL: AADEN Mask */\r
-#define USART2_RS485CTRL_DCTRL_Pos 4 /*!< USART2 RS485CTRL: DCTRL Position */\r
-#define USART2_RS485CTRL_DCTRL_Msk (0x01UL << USART2_RS485CTRL_DCTRL_Pos) /*!< USART2 RS485CTRL: DCTRL Mask */\r
-#define USART2_RS485CTRL_OINV_Pos 5 /*!< USART2 RS485CTRL: OINV Position */\r
-#define USART2_RS485CTRL_OINV_Msk (0x01UL << USART2_RS485CTRL_OINV_Pos) /*!< USART2 RS485CTRL: OINV Mask */\r
-\r
-// ---------------------------------- USART2_RS485ADRMATCH --------------------------------------\r
-#define USART2_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART2 RS485ADRMATCH: ADRMATCH Position */\r
-#define USART2_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */\r
-\r
-// ------------------------------------- USART2_RS485DLY ----------------------------------------\r
-#define USART2_RS485DLY_DLY_Pos 0 /*!< USART2 RS485DLY: DLY Position */\r
-#define USART2_RS485DLY_DLY_Msk (0x000000ffUL << USART2_RS485DLY_DLY_Pos) /*!< USART2 RS485DLY: DLY Mask */\r
-\r
-// ------------------------------------- USART2_SYNCCTRL ----------------------------------------\r
-#define USART2_SYNCCTRL_SYNC_Pos 0 /*!< USART2 SYNCCTRL: SYNC Position */\r
-#define USART2_SYNCCTRL_SYNC_Msk (0x01UL << USART2_SYNCCTRL_SYNC_Pos) /*!< USART2 SYNCCTRL: SYNC Mask */\r
-#define USART2_SYNCCTRL_CSRC_Pos 1 /*!< USART2 SYNCCTRL: CSRC Position */\r
-#define USART2_SYNCCTRL_CSRC_Msk (0x01UL << USART2_SYNCCTRL_CSRC_Pos) /*!< USART2 SYNCCTRL: CSRC Mask */\r
-#define USART2_SYNCCTRL_FES_Pos 2 /*!< USART2 SYNCCTRL: FES Position */\r
-#define USART2_SYNCCTRL_FES_Msk (0x01UL << USART2_SYNCCTRL_FES_Pos) /*!< USART2 SYNCCTRL: FES Mask */\r
-#define USART2_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART2 SYNCCTRL: TSBYPASS Position */\r
-#define USART2_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos) /*!< USART2 SYNCCTRL: TSBYPASS Mask */\r
-#define USART2_SYNCCTRL_CSCEN_Pos 4 /*!< USART2 SYNCCTRL: CSCEN Position */\r
-#define USART2_SYNCCTRL_CSCEN_Msk (0x01UL << USART2_SYNCCTRL_CSCEN_Pos) /*!< USART2 SYNCCTRL: CSCEN Mask */\r
-#define USART2_SYNCCTRL_SSSDIS_Pos 5 /*!< USART2 SYNCCTRL: SSSDIS Position */\r
-#define USART2_SYNCCTRL_SSSDIS_Msk (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos) /*!< USART2 SYNCCTRL: SSSDIS Mask */\r
-#define USART2_SYNCCTRL_CCCLR_Pos 6 /*!< USART2 SYNCCTRL: CCCLR Position */\r
-#define USART2_SYNCCTRL_CCCLR_Msk (0x01UL << USART2_SYNCCTRL_CCCLR_Pos) /*!< USART2 SYNCCTRL: CCCLR Mask */\r
-\r
-// --------------------------------------- USART2_TER -------------------------------------------\r
-#define USART2_TER_TXEN_Pos 0 /*!< USART2 TER: TXEN Position */\r
-#define USART2_TER_TXEN_Msk (0x01UL << USART2_TER_TXEN_Pos) /*!< USART2 TER: TXEN Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- USART3 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- USART3_DLL -------------------------------------------\r
-#define USART3_DLL_DLLSB_Pos 0 /*!< USART3 DLL: DLLSB Position */\r
-#define USART3_DLL_DLLSB_Msk (0x000000ffUL << USART3_DLL_DLLSB_Pos) /*!< USART3 DLL: DLLSB Mask */\r
-\r
-// --------------------------------------- USART3_THR -------------------------------------------\r
-#define USART3_THR_THR_Pos 0 /*!< USART3 THR: THR Position */\r
-#define USART3_THR_THR_Msk (0x000000ffUL << USART3_THR_THR_Pos) /*!< USART3 THR: THR Mask */\r
-\r
-// --------------------------------------- USART3_RBR -------------------------------------------\r
-#define USART3_RBR_RBR_Pos 0 /*!< USART3 RBR: RBR Position */\r
-#define USART3_RBR_RBR_Msk (0x000000ffUL << USART3_RBR_RBR_Pos) /*!< USART3 RBR: RBR Mask */\r
-\r
-// --------------------------------------- USART3_IER -------------------------------------------\r
-#define USART3_IER_RBRIE_Pos 0 /*!< USART3 IER: RBRIE Position */\r
-#define USART3_IER_RBRIE_Msk (0x01UL << USART3_IER_RBRIE_Pos) /*!< USART3 IER: RBRIE Mask */\r
-#define USART3_IER_THREIE_Pos 1 /*!< USART3 IER: THREIE Position */\r
-#define USART3_IER_THREIE_Msk (0x01UL << USART3_IER_THREIE_Pos) /*!< USART3 IER: THREIE Mask */\r
-#define USART3_IER_RXIE_Pos 2 /*!< USART3 IER: RXIE Position */\r
-#define USART3_IER_RXIE_Msk (0x01UL << USART3_IER_RXIE_Pos) /*!< USART3 IER: RXIE Mask */\r
-#define USART3_IER_ABEOINTEN_Pos 8 /*!< USART3 IER: ABEOINTEN Position */\r
-#define USART3_IER_ABEOINTEN_Msk (0x01UL << USART3_IER_ABEOINTEN_Pos) /*!< USART3 IER: ABEOINTEN Mask */\r
-#define USART3_IER_ABTOINTEN_Pos 9 /*!< USART3 IER: ABTOINTEN Position */\r
-#define USART3_IER_ABTOINTEN_Msk (0x01UL << USART3_IER_ABTOINTEN_Pos) /*!< USART3 IER: ABTOINTEN Mask */\r
-\r
-// --------------------------------------- USART3_DLM -------------------------------------------\r
-#define USART3_DLM_DLMSB_Pos 0 /*!< USART3 DLM: DLMSB Position */\r
-#define USART3_DLM_DLMSB_Msk (0x000000ffUL << USART3_DLM_DLMSB_Pos) /*!< USART3 DLM: DLMSB Mask */\r
-\r
-// --------------------------------------- USART3_FCR -------------------------------------------\r
-#define USART3_FCR_FIFOEN_Pos 0 /*!< USART3 FCR: FIFOEN Position */\r
-#define USART3_FCR_FIFOEN_Msk (0x01UL << USART3_FCR_FIFOEN_Pos) /*!< USART3 FCR: FIFOEN Mask */\r
-#define USART3_FCR_RXFIFORES_Pos 1 /*!< USART3 FCR: RXFIFORES Position */\r
-#define USART3_FCR_RXFIFORES_Msk (0x01UL << USART3_FCR_RXFIFORES_Pos) /*!< USART3 FCR: RXFIFORES Mask */\r
-#define USART3_FCR_TXFIFORES_Pos 2 /*!< USART3 FCR: TXFIFORES Position */\r
-#define USART3_FCR_TXFIFORES_Msk (0x01UL << USART3_FCR_TXFIFORES_Pos) /*!< USART3 FCR: TXFIFORES Mask */\r
-#define USART3_FCR_DMAMODE_Pos 3 /*!< USART3 FCR: DMAMODE Position */\r
-#define USART3_FCR_DMAMODE_Msk (0x01UL << USART3_FCR_DMAMODE_Pos) /*!< USART3 FCR: DMAMODE Mask */\r
-#define USART3_FCR_RXTRIGLVL_Pos 6 /*!< USART3 FCR: RXTRIGLVL Position */\r
-#define USART3_FCR_RXTRIGLVL_Msk (0x03UL << USART3_FCR_RXTRIGLVL_Pos) /*!< USART3 FCR: RXTRIGLVL Mask */\r
-\r
-// --------------------------------------- USART3_IIR -------------------------------------------\r
-#define USART3_IIR_INTSTATUS_Pos 0 /*!< USART3 IIR: INTSTATUS Position */\r
-#define USART3_IIR_INTSTATUS_Msk (0x01UL << USART3_IIR_INTSTATUS_Pos) /*!< USART3 IIR: INTSTATUS Mask */\r
-#define USART3_IIR_INTID_Pos 1 /*!< USART3 IIR: INTID Position */\r
-#define USART3_IIR_INTID_Msk (0x07UL << USART3_IIR_INTID_Pos) /*!< USART3 IIR: INTID Mask */\r
-#define USART3_IIR_FIFOENABLE_Pos 6 /*!< USART3 IIR: FIFOENABLE Position */\r
-#define USART3_IIR_FIFOENABLE_Msk (0x03UL << USART3_IIR_FIFOENABLE_Pos) /*!< USART3 IIR: FIFOENABLE Mask */\r
-#define USART3_IIR_ABEOINT_Pos 8 /*!< USART3 IIR: ABEOINT Position */\r
-#define USART3_IIR_ABEOINT_Msk (0x01UL << USART3_IIR_ABEOINT_Pos) /*!< USART3 IIR: ABEOINT Mask */\r
-#define USART3_IIR_ABTOINT_Pos 9 /*!< USART3 IIR: ABTOINT Position */\r
-#define USART3_IIR_ABTOINT_Msk (0x01UL << USART3_IIR_ABTOINT_Pos) /*!< USART3 IIR: ABTOINT Mask */\r
-\r
-// --------------------------------------- USART3_LCR -------------------------------------------\r
-#define USART3_LCR_WLS_Pos 0 /*!< USART3 LCR: WLS Position */\r
-#define USART3_LCR_WLS_Msk (0x03UL << USART3_LCR_WLS_Pos) /*!< USART3 LCR: WLS Mask */\r
-#define USART3_LCR_SBS_Pos 2 /*!< USART3 LCR: SBS Position */\r
-#define USART3_LCR_SBS_Msk (0x01UL << USART3_LCR_SBS_Pos) /*!< USART3 LCR: SBS Mask */\r
-#define USART3_LCR_PE_Pos 3 /*!< USART3 LCR: PE Position */\r
-#define USART3_LCR_PE_Msk (0x01UL << USART3_LCR_PE_Pos) /*!< USART3 LCR: PE Mask */\r
-#define USART3_LCR_PS_Pos 4 /*!< USART3 LCR: PS Position */\r
-#define USART3_LCR_PS_Msk (0x03UL << USART3_LCR_PS_Pos) /*!< USART3 LCR: PS Mask */\r
-#define USART3_LCR_BC_Pos 6 /*!< USART3 LCR: BC Position */\r
-#define USART3_LCR_BC_Msk (0x01UL << USART3_LCR_BC_Pos) /*!< USART3 LCR: BC Mask */\r
-#define USART3_LCR_DLAB_Pos 7 /*!< USART3 LCR: DLAB Position */\r
-#define USART3_LCR_DLAB_Msk (0x01UL << USART3_LCR_DLAB_Pos) /*!< USART3 LCR: DLAB Mask */\r
-\r
-// --------------------------------------- USART3_LSR -------------------------------------------\r
-#define USART3_LSR_RDR_Pos 0 /*!< USART3 LSR: RDR Position */\r
-#define USART3_LSR_RDR_Msk (0x01UL << USART3_LSR_RDR_Pos) /*!< USART3 LSR: RDR Mask */\r
-#define USART3_LSR_OE_Pos 1 /*!< USART3 LSR: OE Position */\r
-#define USART3_LSR_OE_Msk (0x01UL << USART3_LSR_OE_Pos) /*!< USART3 LSR: OE Mask */\r
-#define USART3_LSR_PE_Pos 2 /*!< USART3 LSR: PE Position */\r
-#define USART3_LSR_PE_Msk (0x01UL << USART3_LSR_PE_Pos) /*!< USART3 LSR: PE Mask */\r
-#define USART3_LSR_FE_Pos 3 /*!< USART3 LSR: FE Position */\r
-#define USART3_LSR_FE_Msk (0x01UL << USART3_LSR_FE_Pos) /*!< USART3 LSR: FE Mask */\r
-#define USART3_LSR_BI_Pos 4 /*!< USART3 LSR: BI Position */\r
-#define USART3_LSR_BI_Msk (0x01UL << USART3_LSR_BI_Pos) /*!< USART3 LSR: BI Mask */\r
-#define USART3_LSR_THRE_Pos 5 /*!< USART3 LSR: THRE Position */\r
-#define USART3_LSR_THRE_Msk (0x01UL << USART3_LSR_THRE_Pos) /*!< USART3 LSR: THRE Mask */\r
-#define USART3_LSR_TEMT_Pos 6 /*!< USART3 LSR: TEMT Position */\r
-#define USART3_LSR_TEMT_Msk (0x01UL << USART3_LSR_TEMT_Pos) /*!< USART3 LSR: TEMT Mask */\r
-#define USART3_LSR_RXFE_Pos 7 /*!< USART3 LSR: RXFE Position */\r
-#define USART3_LSR_RXFE_Msk (0x01UL << USART3_LSR_RXFE_Pos) /*!< USART3 LSR: RXFE Mask */\r
-#define USART3_LSR_TXERR_Pos 8 /*!< USART3 LSR: TXERR Position */\r
-#define USART3_LSR_TXERR_Msk (0x01UL << USART3_LSR_TXERR_Pos) /*!< USART3 LSR: TXERR Mask */\r
-\r
-// --------------------------------------- USART3_SCR -------------------------------------------\r
-#define USART3_SCR_PAD_Pos 0 /*!< USART3 SCR: PAD Position */\r
-#define USART3_SCR_PAD_Msk (0x000000ffUL << USART3_SCR_PAD_Pos) /*!< USART3 SCR: PAD Mask */\r
-\r
-// --------------------------------------- USART3_ACR -------------------------------------------\r
-#define USART3_ACR_START_Pos 0 /*!< USART3 ACR: START Position */\r
-#define USART3_ACR_START_Msk (0x01UL << USART3_ACR_START_Pos) /*!< USART3 ACR: START Mask */\r
-#define USART3_ACR_MODE_Pos 1 /*!< USART3 ACR: MODE Position */\r
-#define USART3_ACR_MODE_Msk (0x01UL << USART3_ACR_MODE_Pos) /*!< USART3 ACR: MODE Mask */\r
-#define USART3_ACR_AUTORESTART_Pos 2 /*!< USART3 ACR: AUTORESTART Position */\r
-#define USART3_ACR_AUTORESTART_Msk (0x01UL << USART3_ACR_AUTORESTART_Pos) /*!< USART3 ACR: AUTORESTART Mask */\r
-#define USART3_ACR_ABEOINTCLR_Pos 8 /*!< USART3 ACR: ABEOINTCLR Position */\r
-#define USART3_ACR_ABEOINTCLR_Msk (0x01UL << USART3_ACR_ABEOINTCLR_Pos) /*!< USART3 ACR: ABEOINTCLR Mask */\r
-#define USART3_ACR_ABTOINTCLR_Pos 9 /*!< USART3 ACR: ABTOINTCLR Position */\r
-#define USART3_ACR_ABTOINTCLR_Msk (0x01UL << USART3_ACR_ABTOINTCLR_Pos) /*!< USART3 ACR: ABTOINTCLR Mask */\r
-\r
-// --------------------------------------- USART3_ICR -------------------------------------------\r
-#define USART3_ICR_IRDAEN_Pos 0 /*!< USART3 ICR: IRDAEN Position */\r
-#define USART3_ICR_IRDAEN_Msk (0x01UL << USART3_ICR_IRDAEN_Pos) /*!< USART3 ICR: IRDAEN Mask */\r
-#define USART3_ICR_IRDAINV_Pos 1 /*!< USART3 ICR: IRDAINV Position */\r
-#define USART3_ICR_IRDAINV_Msk (0x01UL << USART3_ICR_IRDAINV_Pos) /*!< USART3 ICR: IRDAINV Mask */\r
-#define USART3_ICR_FIXPULSEEN_Pos 2 /*!< USART3 ICR: FIXPULSEEN Position */\r
-#define USART3_ICR_FIXPULSEEN_Msk (0x01UL << USART3_ICR_FIXPULSEEN_Pos) /*!< USART3 ICR: FIXPULSEEN Mask */\r
-#define USART3_ICR_PULSEDIV_Pos 3 /*!< USART3 ICR: PULSEDIV Position */\r
-#define USART3_ICR_PULSEDIV_Msk (0x07UL << USART3_ICR_PULSEDIV_Pos) /*!< USART3 ICR: PULSEDIV Mask */\r
-\r
-// --------------------------------------- USART3_FDR -------------------------------------------\r
-#define USART3_FDR_DIVADDVAL_Pos 0 /*!< USART3 FDR: DIVADDVAL Position */\r
-#define USART3_FDR_DIVADDVAL_Msk (0x0fUL << USART3_FDR_DIVADDVAL_Pos) /*!< USART3 FDR: DIVADDVAL Mask */\r
-#define USART3_FDR_MULVAL_Pos 4 /*!< USART3 FDR: MULVAL Position */\r
-#define USART3_FDR_MULVAL_Msk (0x0fUL << USART3_FDR_MULVAL_Pos) /*!< USART3 FDR: MULVAL Mask */\r
-\r
-// --------------------------------------- USART3_OSR -------------------------------------------\r
-#define USART3_OSR_OSFRAC_Pos 1 /*!< USART3 OSR: OSFRAC Position */\r
-#define USART3_OSR_OSFRAC_Msk (0x07UL << USART3_OSR_OSFRAC_Pos) /*!< USART3 OSR: OSFRAC Mask */\r
-#define USART3_OSR_OSINT_Pos 4 /*!< USART3 OSR: OSINT Position */\r
-#define USART3_OSR_OSINT_Msk (0x0fUL << USART3_OSR_OSINT_Pos) /*!< USART3 OSR: OSINT Mask */\r
-#define USART3_OSR_FDINT_Pos 8 /*!< USART3 OSR: FDINT Position */\r
-#define USART3_OSR_FDINT_Msk (0x7fUL << USART3_OSR_FDINT_Pos) /*!< USART3 OSR: FDINT Mask */\r
-\r
-// --------------------------------------- USART3_HDEN ------------------------------------------\r
-#define USART3_HDEN_HDEN_Pos 0 /*!< USART3 HDEN: HDEN Position */\r
-#define USART3_HDEN_HDEN_Msk (0x01UL << USART3_HDEN_HDEN_Pos) /*!< USART3 HDEN: HDEN Mask */\r
-\r
-// ------------------------------------- USART3_SCICTRL -----------------------------------------\r
-#define USART3_SCICTRL_SCIEN_Pos 0 /*!< USART3 SCICTRL: SCIEN Position */\r
-#define USART3_SCICTRL_SCIEN_Msk (0x01UL << USART3_SCICTRL_SCIEN_Pos) /*!< USART3 SCICTRL: SCIEN Mask */\r
-#define USART3_SCICTRL_NACKDIS_Pos 1 /*!< USART3 SCICTRL: NACKDIS Position */\r
-#define USART3_SCICTRL_NACKDIS_Msk (0x01UL << USART3_SCICTRL_NACKDIS_Pos) /*!< USART3 SCICTRL: NACKDIS Mask */\r
-#define USART3_SCICTRL_PROTSEL_Pos 2 /*!< USART3 SCICTRL: PROTSEL Position */\r
-#define USART3_SCICTRL_PROTSEL_Msk (0x01UL << USART3_SCICTRL_PROTSEL_Pos) /*!< USART3 SCICTRL: PROTSEL Mask */\r
-#define USART3_SCICTRL_TXRETRY_Pos 5 /*!< USART3 SCICTRL: TXRETRY Position */\r
-#define USART3_SCICTRL_TXRETRY_Msk (0x07UL << USART3_SCICTRL_TXRETRY_Pos) /*!< USART3 SCICTRL: TXRETRY Mask */\r
-#define USART3_SCICTRL_GUARDTIME_Pos 8 /*!< USART3 SCICTRL: GUARDTIME Position */\r
-#define USART3_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos) /*!< USART3 SCICTRL: GUARDTIME Mask */\r
-\r
-// ------------------------------------ USART3_RS485CTRL ----------------------------------------\r
-#define USART3_RS485CTRL_NMMEN_Pos 0 /*!< USART3 RS485CTRL: NMMEN Position */\r
-#define USART3_RS485CTRL_NMMEN_Msk (0x01UL << USART3_RS485CTRL_NMMEN_Pos) /*!< USART3 RS485CTRL: NMMEN Mask */\r
-#define USART3_RS485CTRL_RXDIS_Pos 1 /*!< USART3 RS485CTRL: RXDIS Position */\r
-#define USART3_RS485CTRL_RXDIS_Msk (0x01UL << USART3_RS485CTRL_RXDIS_Pos) /*!< USART3 RS485CTRL: RXDIS Mask */\r
-#define USART3_RS485CTRL_AADEN_Pos 2 /*!< USART3 RS485CTRL: AADEN Position */\r
-#define USART3_RS485CTRL_AADEN_Msk (0x01UL << USART3_RS485CTRL_AADEN_Pos) /*!< USART3 RS485CTRL: AADEN Mask */\r
-#define USART3_RS485CTRL_DCTRL_Pos 4 /*!< USART3 RS485CTRL: DCTRL Position */\r
-#define USART3_RS485CTRL_DCTRL_Msk (0x01UL << USART3_RS485CTRL_DCTRL_Pos) /*!< USART3 RS485CTRL: DCTRL Mask */\r
-#define USART3_RS485CTRL_OINV_Pos 5 /*!< USART3 RS485CTRL: OINV Position */\r
-#define USART3_RS485CTRL_OINV_Msk (0x01UL << USART3_RS485CTRL_OINV_Pos) /*!< USART3 RS485CTRL: OINV Mask */\r
-\r
-// ---------------------------------- USART3_RS485ADRMATCH --------------------------------------\r
-#define USART3_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART3 RS485ADRMATCH: ADRMATCH Position */\r
-#define USART3_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */\r
-\r
-// ------------------------------------- USART3_RS485DLY ----------------------------------------\r
-#define USART3_RS485DLY_DLY_Pos 0 /*!< USART3 RS485DLY: DLY Position */\r
-#define USART3_RS485DLY_DLY_Msk (0x000000ffUL << USART3_RS485DLY_DLY_Pos) /*!< USART3 RS485DLY: DLY Mask */\r
-\r
-// ------------------------------------- USART3_SYNCCTRL ----------------------------------------\r
-#define USART3_SYNCCTRL_SYNC_Pos 0 /*!< USART3 SYNCCTRL: SYNC Position */\r
-#define USART3_SYNCCTRL_SYNC_Msk (0x01UL << USART3_SYNCCTRL_SYNC_Pos) /*!< USART3 SYNCCTRL: SYNC Mask */\r
-#define USART3_SYNCCTRL_CSRC_Pos 1 /*!< USART3 SYNCCTRL: CSRC Position */\r
-#define USART3_SYNCCTRL_CSRC_Msk (0x01UL << USART3_SYNCCTRL_CSRC_Pos) /*!< USART3 SYNCCTRL: CSRC Mask */\r
-#define USART3_SYNCCTRL_FES_Pos 2 /*!< USART3 SYNCCTRL: FES Position */\r
-#define USART3_SYNCCTRL_FES_Msk (0x01UL << USART3_SYNCCTRL_FES_Pos) /*!< USART3 SYNCCTRL: FES Mask */\r
-#define USART3_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART3 SYNCCTRL: TSBYPASS Position */\r
-#define USART3_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos) /*!< USART3 SYNCCTRL: TSBYPASS Mask */\r
-#define USART3_SYNCCTRL_CSCEN_Pos 4 /*!< USART3 SYNCCTRL: CSCEN Position */\r
-#define USART3_SYNCCTRL_CSCEN_Msk (0x01UL << USART3_SYNCCTRL_CSCEN_Pos) /*!< USART3 SYNCCTRL: CSCEN Mask */\r
-#define USART3_SYNCCTRL_SSSDIS_Pos 5 /*!< USART3 SYNCCTRL: SSSDIS Position */\r
-#define USART3_SYNCCTRL_SSSDIS_Msk (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos) /*!< USART3 SYNCCTRL: SSSDIS Mask */\r
-#define USART3_SYNCCTRL_CCCLR_Pos 6 /*!< USART3 SYNCCTRL: CCCLR Position */\r
-#define USART3_SYNCCTRL_CCCLR_Msk (0x01UL << USART3_SYNCCTRL_CCCLR_Pos) /*!< USART3 SYNCCTRL: CCCLR Mask */\r
-\r
-// --------------------------------------- USART3_TER -------------------------------------------\r
-#define USART3_TER_TXEN_Pos 0 /*!< USART3 TER: TXEN Position */\r
-#define USART3_TER_TXEN_Msk (0x01UL << USART3_TER_TXEN_Pos) /*!< USART3 TER: TXEN Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- UART1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- UART1_RBR -------------------------------------------\r
-#define UART1_RBR_RBR_Pos 0 /*!< UART1 RBR: RBR Position */\r
-#define UART1_RBR_RBR_Msk (0x000000ffUL << UART1_RBR_RBR_Pos) /*!< UART1 RBR: RBR Mask */\r
-\r
-// ---------------------------------------- UART1_THR -------------------------------------------\r
-#define UART1_THR_THR_Pos 0 /*!< UART1 THR: THR Position */\r
-#define UART1_THR_THR_Msk (0x000000ffUL << UART1_THR_THR_Pos) /*!< UART1 THR: THR Mask */\r
-\r
-// ---------------------------------------- UART1_DLL -------------------------------------------\r
-#define UART1_DLL_DLLSB_Pos 0 /*!< UART1 DLL: DLLSB Position */\r
-#define UART1_DLL_DLLSB_Msk (0x000000ffUL << UART1_DLL_DLLSB_Pos) /*!< UART1 DLL: DLLSB Mask */\r
-\r
-// ---------------------------------------- UART1_DLM -------------------------------------------\r
-#define UART1_DLM_DLMSB_Pos 0 /*!< UART1 DLM: DLMSB Position */\r
-#define UART1_DLM_DLMSB_Msk (0x000000ffUL << UART1_DLM_DLMSB_Pos) /*!< UART1 DLM: DLMSB Mask */\r
-\r
-// ---------------------------------------- UART1_IER -------------------------------------------\r
-#define UART1_IER_RBRIE_Pos 0 /*!< UART1 IER: RBRIE Position */\r
-#define UART1_IER_RBRIE_Msk (0x01UL << UART1_IER_RBRIE_Pos) /*!< UART1 IER: RBRIE Mask */\r
-#define UART1_IER_THREIE_Pos 1 /*!< UART1 IER: THREIE Position */\r
-#define UART1_IER_THREIE_Msk (0x01UL << UART1_IER_THREIE_Pos) /*!< UART1 IER: THREIE Mask */\r
-#define UART1_IER_RXIE_Pos 2 /*!< UART1 IER: RXIE Position */\r
-#define UART1_IER_RXIE_Msk (0x01UL << UART1_IER_RXIE_Pos) /*!< UART1 IER: RXIE Mask */\r
-#define UART1_IER_MSIE_Pos 3 /*!< UART1 IER: MSIE Position */\r
-#define UART1_IER_MSIE_Msk (0x01UL << UART1_IER_MSIE_Pos) /*!< UART1 IER: MSIE Mask */\r
-#define UART1_IER_CTSIE_Pos 7 /*!< UART1 IER: CTSIE Position */\r
-#define UART1_IER_CTSIE_Msk (0x01UL << UART1_IER_CTSIE_Pos) /*!< UART1 IER: CTSIE Mask */\r
-#define UART1_IER_ABEOIE_Pos 8 /*!< UART1 IER: ABEOIE Position */\r
-#define UART1_IER_ABEOIE_Msk (0x01UL << UART1_IER_ABEOIE_Pos) /*!< UART1 IER: ABEOIE Mask */\r
-#define UART1_IER_ABTOIE_Pos 9 /*!< UART1 IER: ABTOIE Position */\r
-#define UART1_IER_ABTOIE_Msk (0x01UL << UART1_IER_ABTOIE_Pos) /*!< UART1 IER: ABTOIE Mask */\r
-\r
-// ---------------------------------------- UART1_IIR -------------------------------------------\r
-#define UART1_IIR_INTSTATUS_Pos 0 /*!< UART1 IIR: INTSTATUS Position */\r
-#define UART1_IIR_INTSTATUS_Msk (0x01UL << UART1_IIR_INTSTATUS_Pos) /*!< UART1 IIR: INTSTATUS Mask */\r
-#define UART1_IIR_INTID_Pos 1 /*!< UART1 IIR: INTID Position */\r
-#define UART1_IIR_INTID_Msk (0x07UL << UART1_IIR_INTID_Pos) /*!< UART1 IIR: INTID Mask */\r
-#define UART1_IIR_FIFOENABLE_Pos 6 /*!< UART1 IIR: FIFOENABLE Position */\r
-#define UART1_IIR_FIFOENABLE_Msk (0x03UL << UART1_IIR_FIFOENABLE_Pos) /*!< UART1 IIR: FIFOENABLE Mask */\r
-#define UART1_IIR_ABEOINT_Pos 8 /*!< UART1 IIR: ABEOINT Position */\r
-#define UART1_IIR_ABEOINT_Msk (0x01UL << UART1_IIR_ABEOINT_Pos) /*!< UART1 IIR: ABEOINT Mask */\r
-#define UART1_IIR_ABTOINT_Pos 9 /*!< UART1 IIR: ABTOINT Position */\r
-#define UART1_IIR_ABTOINT_Msk (0x01UL << UART1_IIR_ABTOINT_Pos) /*!< UART1 IIR: ABTOINT Mask */\r
-\r
-// ---------------------------------------- UART1_FCR -------------------------------------------\r
-#define UART1_FCR_FIFOEN_Pos 0 /*!< UART1 FCR: FIFOEN Position */\r
-#define UART1_FCR_FIFOEN_Msk (0x01UL << UART1_FCR_FIFOEN_Pos) /*!< UART1 FCR: FIFOEN Mask */\r
-#define UART1_FCR_RXFIFORES_Pos 1 /*!< UART1 FCR: RXFIFORES Position */\r
-#define UART1_FCR_RXFIFORES_Msk (0x01UL << UART1_FCR_RXFIFORES_Pos) /*!< UART1 FCR: RXFIFORES Mask */\r
-#define UART1_FCR_TXFIFORES_Pos 2 /*!< UART1 FCR: TXFIFORES Position */\r
-#define UART1_FCR_TXFIFORES_Msk (0x01UL << UART1_FCR_TXFIFORES_Pos) /*!< UART1 FCR: TXFIFORES Mask */\r
-#define UART1_FCR_DMAMODE_Pos 3 /*!< UART1 FCR: DMAMODE Position */\r
-#define UART1_FCR_DMAMODE_Msk (0x01UL << UART1_FCR_DMAMODE_Pos) /*!< UART1 FCR: DMAMODE Mask */\r
-#define UART1_FCR_RXTRIGLVL_Pos 6 /*!< UART1 FCR: RXTRIGLVL Position */\r
-#define UART1_FCR_RXTRIGLVL_Msk (0x03UL << UART1_FCR_RXTRIGLVL_Pos) /*!< UART1 FCR: RXTRIGLVL Mask */\r
-\r
-// ---------------------------------------- UART1_LCR -------------------------------------------\r
-#define UART1_LCR_WLS_Pos 0 /*!< UART1 LCR: WLS Position */\r
-#define UART1_LCR_WLS_Msk (0x03UL << UART1_LCR_WLS_Pos) /*!< UART1 LCR: WLS Mask */\r
-#define UART1_LCR_SBS_Pos 2 /*!< UART1 LCR: SBS Position */\r
-#define UART1_LCR_SBS_Msk (0x01UL << UART1_LCR_SBS_Pos) /*!< UART1 LCR: SBS Mask */\r
-#define UART1_LCR_PE_Pos 3 /*!< UART1 LCR: PE Position */\r
-#define UART1_LCR_PE_Msk (0x01UL << UART1_LCR_PE_Pos) /*!< UART1 LCR: PE Mask */\r
-#define UART1_LCR_PS_Pos 4 /*!< UART1 LCR: PS Position */\r
-#define UART1_LCR_PS_Msk (0x03UL << UART1_LCR_PS_Pos) /*!< UART1 LCR: PS Mask */\r
-#define UART1_LCR_BC_Pos 6 /*!< UART1 LCR: BC Position */\r
-#define UART1_LCR_BC_Msk (0x01UL << UART1_LCR_BC_Pos) /*!< UART1 LCR: BC Mask */\r
-#define UART1_LCR_DLAB_Pos 7 /*!< UART1 LCR: DLAB Position */\r
-#define UART1_LCR_DLAB_Msk (0x01UL << UART1_LCR_DLAB_Pos) /*!< UART1 LCR: DLAB Mask */\r
-\r
-// ---------------------------------------- UART1_MCR -------------------------------------------\r
-#define UART1_MCR_DTRCTRL_Pos 0 /*!< UART1 MCR: DTRCTRL Position */\r
-#define UART1_MCR_DTRCTRL_Msk (0x01UL << UART1_MCR_DTRCTRL_Pos) /*!< UART1 MCR: DTRCTRL Mask */\r
-#define UART1_MCR_RTSCTRL_Pos 1 /*!< UART1 MCR: RTSCTRL Position */\r
-#define UART1_MCR_RTSCTRL_Msk (0x01UL << UART1_MCR_RTSCTRL_Pos) /*!< UART1 MCR: RTSCTRL Mask */\r
-#define UART1_MCR_LMS_Pos 4 /*!< UART1 MCR: LMS Position */\r
-#define UART1_MCR_LMS_Msk (0x01UL << UART1_MCR_LMS_Pos) /*!< UART1 MCR: LMS Mask */\r
-#define UART1_MCR_RTSEN_Pos 6 /*!< UART1 MCR: RTSEN Position */\r
-#define UART1_MCR_RTSEN_Msk (0x01UL << UART1_MCR_RTSEN_Pos) /*!< UART1 MCR: RTSEN Mask */\r
-#define UART1_MCR_CTSEN_Pos 7 /*!< UART1 MCR: CTSEN Position */\r
-#define UART1_MCR_CTSEN_Msk (0x01UL << UART1_MCR_CTSEN_Pos) /*!< UART1 MCR: CTSEN Mask */\r
-\r
-// ---------------------------------------- UART1_LSR -------------------------------------------\r
-#define UART1_LSR_RDR_Pos 0 /*!< UART1 LSR: RDR Position */\r
-#define UART1_LSR_RDR_Msk (0x01UL << UART1_LSR_RDR_Pos) /*!< UART1 LSR: RDR Mask */\r
-#define UART1_LSR_OE_Pos 1 /*!< UART1 LSR: OE Position */\r
-#define UART1_LSR_OE_Msk (0x01UL << UART1_LSR_OE_Pos) /*!< UART1 LSR: OE Mask */\r
-#define UART1_LSR_PE_Pos 2 /*!< UART1 LSR: PE Position */\r
-#define UART1_LSR_PE_Msk (0x01UL << UART1_LSR_PE_Pos) /*!< UART1 LSR: PE Mask */\r
-#define UART1_LSR_FE_Pos 3 /*!< UART1 LSR: FE Position */\r
-#define UART1_LSR_FE_Msk (0x01UL << UART1_LSR_FE_Pos) /*!< UART1 LSR: FE Mask */\r
-#define UART1_LSR_BI_Pos 4 /*!< UART1 LSR: BI Position */\r
-#define UART1_LSR_BI_Msk (0x01UL << UART1_LSR_BI_Pos) /*!< UART1 LSR: BI Mask */\r
-#define UART1_LSR_THRE_Pos 5 /*!< UART1 LSR: THRE Position */\r
-#define UART1_LSR_THRE_Msk (0x01UL << UART1_LSR_THRE_Pos) /*!< UART1 LSR: THRE Mask */\r
-#define UART1_LSR_TEMT_Pos 6 /*!< UART1 LSR: TEMT Position */\r
-#define UART1_LSR_TEMT_Msk (0x01UL << UART1_LSR_TEMT_Pos) /*!< UART1 LSR: TEMT Mask */\r
-#define UART1_LSR_RXFE_Pos 7 /*!< UART1 LSR: RXFE Position */\r
-#define UART1_LSR_RXFE_Msk (0x01UL << UART1_LSR_RXFE_Pos) /*!< UART1 LSR: RXFE Mask */\r
-\r
-// ---------------------------------------- UART1_MSR -------------------------------------------\r
-#define UART1_MSR_DCTS_Pos 0 /*!< UART1 MSR: DCTS Position */\r
-#define UART1_MSR_DCTS_Msk (0x01UL << UART1_MSR_DCTS_Pos) /*!< UART1 MSR: DCTS Mask */\r
-#define UART1_MSR_DDSR_Pos 1 /*!< UART1 MSR: DDSR Position */\r
-#define UART1_MSR_DDSR_Msk (0x01UL << UART1_MSR_DDSR_Pos) /*!< UART1 MSR: DDSR Mask */\r
-#define UART1_MSR_TERI_Pos 2 /*!< UART1 MSR: TERI Position */\r
-#define UART1_MSR_TERI_Msk (0x01UL << UART1_MSR_TERI_Pos) /*!< UART1 MSR: TERI Mask */\r
-#define UART1_MSR_DDCD_Pos 3 /*!< UART1 MSR: DDCD Position */\r
-#define UART1_MSR_DDCD_Msk (0x01UL << UART1_MSR_DDCD_Pos) /*!< UART1 MSR: DDCD Mask */\r
-#define UART1_MSR_CTS_Pos 4 /*!< UART1 MSR: CTS Position */\r
-#define UART1_MSR_CTS_Msk (0x01UL << UART1_MSR_CTS_Pos) /*!< UART1 MSR: CTS Mask */\r
-#define UART1_MSR_DSR_Pos 5 /*!< UART1 MSR: DSR Position */\r
-#define UART1_MSR_DSR_Msk (0x01UL << UART1_MSR_DSR_Pos) /*!< UART1 MSR: DSR Mask */\r
-#define UART1_MSR_RI_Pos 6 /*!< UART1 MSR: RI Position */\r
-#define UART1_MSR_RI_Msk (0x01UL << UART1_MSR_RI_Pos) /*!< UART1 MSR: RI Mask */\r
-#define UART1_MSR_DCD_Pos 7 /*!< UART1 MSR: DCD Position */\r
-#define UART1_MSR_DCD_Msk (0x01UL << UART1_MSR_DCD_Pos) /*!< UART1 MSR: DCD Mask */\r
-\r
-// ---------------------------------------- UART1_SCR -------------------------------------------\r
-#define UART1_SCR_Pad_Pos 0 /*!< UART1 SCR: Pad Position */\r
-#define UART1_SCR_Pad_Msk (0x000000ffUL << UART1_SCR_Pad_Pos) /*!< UART1 SCR: Pad Mask */\r
-\r
-// ---------------------------------------- UART1_ACR -------------------------------------------\r
-#define UART1_ACR_START_Pos 0 /*!< UART1 ACR: START Position */\r
-#define UART1_ACR_START_Msk (0x01UL << UART1_ACR_START_Pos) /*!< UART1 ACR: START Mask */\r
-#define UART1_ACR_MODE_Pos 1 /*!< UART1 ACR: MODE Position */\r
-#define UART1_ACR_MODE_Msk (0x01UL << UART1_ACR_MODE_Pos) /*!< UART1 ACR: MODE Mask */\r
-#define UART1_ACR_AUTORESTART_Pos 2 /*!< UART1 ACR: AUTORESTART Position */\r
-#define UART1_ACR_AUTORESTART_Msk (0x01UL << UART1_ACR_AUTORESTART_Pos) /*!< UART1 ACR: AUTORESTART Mask */\r
-#define UART1_ACR_ABEOINTCLR_Pos 8 /*!< UART1 ACR: ABEOINTCLR Position */\r
-#define UART1_ACR_ABEOINTCLR_Msk (0x01UL << UART1_ACR_ABEOINTCLR_Pos) /*!< UART1 ACR: ABEOINTCLR Mask */\r
-#define UART1_ACR_ABTOINTCLR_Pos 9 /*!< UART1 ACR: ABTOINTCLR Position */\r
-#define UART1_ACR_ABTOINTCLR_Msk (0x01UL << UART1_ACR_ABTOINTCLR_Pos) /*!< UART1 ACR: ABTOINTCLR Mask */\r
-\r
-// ---------------------------------------- UART1_FDR -------------------------------------------\r
-#define UART1_FDR_DIVADDVAL_Pos 0 /*!< UART1 FDR: DIVADDVAL Position */\r
-#define UART1_FDR_DIVADDVAL_Msk (0x0fUL << UART1_FDR_DIVADDVAL_Pos) /*!< UART1 FDR: DIVADDVAL Mask */\r
-#define UART1_FDR_MULVAL_Pos 4 /*!< UART1 FDR: MULVAL Position */\r
-#define UART1_FDR_MULVAL_Msk (0x0fUL << UART1_FDR_MULVAL_Pos) /*!< UART1 FDR: MULVAL Mask */\r
-\r
-// ---------------------------------------- UART1_TER -------------------------------------------\r
-#define UART1_TER_TXEN_Pos 7 /*!< UART1 TER: TXEN Position */\r
-#define UART1_TER_TXEN_Msk (0x01UL << UART1_TER_TXEN_Pos) /*!< UART1 TER: TXEN Mask */\r
-\r
-// ------------------------------------- UART1_RS485CTRL ----------------------------------------\r
-#define UART1_RS485CTRL_NMMEN_Pos 0 /*!< UART1 RS485CTRL: NMMEN Position */\r
-#define UART1_RS485CTRL_NMMEN_Msk (0x01UL << UART1_RS485CTRL_NMMEN_Pos) /*!< UART1 RS485CTRL: NMMEN Mask */\r
-#define UART1_RS485CTRL_RXDIS_Pos 1 /*!< UART1 RS485CTRL: RXDIS Position */\r
-#define UART1_RS485CTRL_RXDIS_Msk (0x01UL << UART1_RS485CTRL_RXDIS_Pos) /*!< UART1 RS485CTRL: RXDIS Mask */\r
-#define UART1_RS485CTRL_AADEN_Pos 2 /*!< UART1 RS485CTRL: AADEN Position */\r
-#define UART1_RS485CTRL_AADEN_Msk (0x01UL << UART1_RS485CTRL_AADEN_Pos) /*!< UART1 RS485CTRL: AADEN Mask */\r
-#define UART1_RS485CTRL_SEL_Pos 3 /*!< UART1 RS485CTRL: SEL Position */\r
-#define UART1_RS485CTRL_SEL_Msk (0x01UL << UART1_RS485CTRL_SEL_Pos) /*!< UART1 RS485CTRL: SEL Mask */\r
-#define UART1_RS485CTRL_DCTRL_Pos 4 /*!< UART1 RS485CTRL: DCTRL Position */\r
-#define UART1_RS485CTRL_DCTRL_Msk (0x01UL << UART1_RS485CTRL_DCTRL_Pos) /*!< UART1 RS485CTRL: DCTRL Mask */\r
-#define UART1_RS485CTRL_OINV_Pos 5 /*!< UART1 RS485CTRL: OINV Position */\r
-#define UART1_RS485CTRL_OINV_Msk (0x01UL << UART1_RS485CTRL_OINV_Pos) /*!< UART1 RS485CTRL: OINV Mask */\r
-\r
-// ----------------------------------- UART1_RS485ADRMATCH --------------------------------------\r
-#define UART1_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< UART1 RS485ADRMATCH: ADRMATCH Position */\r
-#define UART1_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos) /*!< UART1 RS485ADRMATCH: ADRMATCH Mask */\r
-\r
-// ------------------------------------- UART1_RS485DLY -----------------------------------------\r
-#define UART1_RS485DLY_DLY_Pos 0 /*!< UART1 RS485DLY: DLY Position */\r
-#define UART1_RS485DLY_DLY_Msk (0x000000ffUL << UART1_RS485DLY_DLY_Pos) /*!< UART1 RS485DLY: DLY Mask */\r
-\r
-// -------------------------------------- UART1_FIFOLVL -----------------------------------------\r
-#define UART1_FIFOLVL_RXFIFILVL_Pos 0 /*!< UART1 FIFOLVL: RXFIFILVL Position */\r
-#define UART1_FIFOLVL_RXFIFILVL_Msk (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos) /*!< UART1 FIFOLVL: RXFIFILVL Mask */\r
-#define UART1_FIFOLVL_TXFIFOLVL_Pos 8 /*!< UART1 FIFOLVL: TXFIFOLVL Position */\r
-#define UART1_FIFOLVL_TXFIFOLVL_Msk (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos) /*!< UART1 FIFOLVL: TXFIFOLVL Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- SSP0 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- SSP0_CR0 --------------------------------------------\r
-#define SSP0_CR0_DSS_Pos 0 /*!< SSP0 CR0: DSS Position */\r
-#define SSP0_CR0_DSS_Msk (0x0fUL << SSP0_CR0_DSS_Pos) /*!< SSP0 CR0: DSS Mask */\r
-#define SSP0_CR0_FRF_Pos 4 /*!< SSP0 CR0: FRF Position */\r
-#define SSP0_CR0_FRF_Msk (0x03UL << SSP0_CR0_FRF_Pos) /*!< SSP0 CR0: FRF Mask */\r
-#define SSP0_CR0_CPOL_Pos 6 /*!< SSP0 CR0: CPOL Position */\r
-#define SSP0_CR0_CPOL_Msk (0x01UL << SSP0_CR0_CPOL_Pos) /*!< SSP0 CR0: CPOL Mask */\r
-#define SSP0_CR0_CPHA_Pos 7 /*!< SSP0 CR0: CPHA Position */\r
-#define SSP0_CR0_CPHA_Msk (0x01UL << SSP0_CR0_CPHA_Pos) /*!< SSP0 CR0: CPHA Mask */\r
-#define SSP0_CR0_SCR_Pos 8 /*!< SSP0 CR0: SCR Position */\r
-#define SSP0_CR0_SCR_Msk (0x000000ffUL << SSP0_CR0_SCR_Pos) /*!< SSP0 CR0: SCR Mask */\r
-\r
-// ---------------------------------------- SSP0_CR1 --------------------------------------------\r
-#define SSP0_CR1_LBM_Pos 0 /*!< SSP0 CR1: LBM Position */\r
-#define SSP0_CR1_LBM_Msk (0x01UL << SSP0_CR1_LBM_Pos) /*!< SSP0 CR1: LBM Mask */\r
-#define SSP0_CR1_SSE_Pos 1 /*!< SSP0 CR1: SSE Position */\r
-#define SSP0_CR1_SSE_Msk (0x01UL << SSP0_CR1_SSE_Pos) /*!< SSP0 CR1: SSE Mask */\r
-#define SSP0_CR1_MS_Pos 2 /*!< SSP0 CR1: MS Position */\r
-#define SSP0_CR1_MS_Msk (0x01UL << SSP0_CR1_MS_Pos) /*!< SSP0 CR1: MS Mask */\r
-#define SSP0_CR1_SOD_Pos 3 /*!< SSP0 CR1: SOD Position */\r
-#define SSP0_CR1_SOD_Msk (0x01UL << SSP0_CR1_SOD_Pos) /*!< SSP0 CR1: SOD Mask */\r
-\r
-// ----------------------------------------- SSP0_DR --------------------------------------------\r
-#define SSP0_DR_DATA_Pos 0 /*!< SSP0 DR: DATA Position */\r
-#define SSP0_DR_DATA_Msk (0x0000ffffUL << SSP0_DR_DATA_Pos) /*!< SSP0 DR: DATA Mask */\r
-\r
-// ----------------------------------------- SSP0_SR --------------------------------------------\r
-#define SSP0_SR_TFE_Pos 0 /*!< SSP0 SR: TFE Position */\r
-#define SSP0_SR_TFE_Msk (0x01UL << SSP0_SR_TFE_Pos) /*!< SSP0 SR: TFE Mask */\r
-#define SSP0_SR_TNF_Pos 1 /*!< SSP0 SR: TNF Position */\r
-#define SSP0_SR_TNF_Msk (0x01UL << SSP0_SR_TNF_Pos) /*!< SSP0 SR: TNF Mask */\r
-#define SSP0_SR_RNE_Pos 2 /*!< SSP0 SR: RNE Position */\r
-#define SSP0_SR_RNE_Msk (0x01UL << SSP0_SR_RNE_Pos) /*!< SSP0 SR: RNE Mask */\r
-#define SSP0_SR_RFF_Pos 3 /*!< SSP0 SR: RFF Position */\r
-#define SSP0_SR_RFF_Msk (0x01UL << SSP0_SR_RFF_Pos) /*!< SSP0 SR: RFF Mask */\r
-#define SSP0_SR_BSY_Pos 4 /*!< SSP0 SR: BSY Position */\r
-#define SSP0_SR_BSY_Msk (0x01UL << SSP0_SR_BSY_Pos) /*!< SSP0 SR: BSY Mask */\r
-\r
-// ---------------------------------------- SSP0_CPSR -------------------------------------------\r
-#define SSP0_CPSR_CPSDVSR_Pos 0 /*!< SSP0 CPSR: CPSDVSR Position */\r
-#define SSP0_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos) /*!< SSP0 CPSR: CPSDVSR Mask */\r
-\r
-// ---------------------------------------- SSP0_IMSC -------------------------------------------\r
-#define SSP0_IMSC_RORIM_Pos 0 /*!< SSP0 IMSC: RORIM Position */\r
-#define SSP0_IMSC_RORIM_Msk (0x01UL << SSP0_IMSC_RORIM_Pos) /*!< SSP0 IMSC: RORIM Mask */\r
-#define SSP0_IMSC_RTIM_Pos 1 /*!< SSP0 IMSC: RTIM Position */\r
-#define SSP0_IMSC_RTIM_Msk (0x01UL << SSP0_IMSC_RTIM_Pos) /*!< SSP0 IMSC: RTIM Mask */\r
-#define SSP0_IMSC_RXIM_Pos 2 /*!< SSP0 IMSC: RXIM Position */\r
-#define SSP0_IMSC_RXIM_Msk (0x01UL << SSP0_IMSC_RXIM_Pos) /*!< SSP0 IMSC: RXIM Mask */\r
-#define SSP0_IMSC_TXIM_Pos 3 /*!< SSP0 IMSC: TXIM Position */\r
-#define SSP0_IMSC_TXIM_Msk (0x01UL << SSP0_IMSC_TXIM_Pos) /*!< SSP0 IMSC: TXIM Mask */\r
-\r
-// ---------------------------------------- SSP0_RIS --------------------------------------------\r
-#define SSP0_RIS_RORRIS_Pos 0 /*!< SSP0 RIS: RORRIS Position */\r
-#define SSP0_RIS_RORRIS_Msk (0x01UL << SSP0_RIS_RORRIS_Pos) /*!< SSP0 RIS: RORRIS Mask */\r
-#define SSP0_RIS_RTRIS_Pos 1 /*!< SSP0 RIS: RTRIS Position */\r
-#define SSP0_RIS_RTRIS_Msk (0x01UL << SSP0_RIS_RTRIS_Pos) /*!< SSP0 RIS: RTRIS Mask */\r
-#define SSP0_RIS_RXRIS_Pos 2 /*!< SSP0 RIS: RXRIS Position */\r
-#define SSP0_RIS_RXRIS_Msk (0x01UL << SSP0_RIS_RXRIS_Pos) /*!< SSP0 RIS: RXRIS Mask */\r
-#define SSP0_RIS_TXRIS_Pos 3 /*!< SSP0 RIS: TXRIS Position */\r
-#define SSP0_RIS_TXRIS_Msk (0x01UL << SSP0_RIS_TXRIS_Pos) /*!< SSP0 RIS: TXRIS Mask */\r
-\r
-// ---------------------------------------- SSP0_MIS --------------------------------------------\r
-#define SSP0_MIS_RORMIS_Pos 0 /*!< SSP0 MIS: RORMIS Position */\r
-#define SSP0_MIS_RORMIS_Msk (0x01UL << SSP0_MIS_RORMIS_Pos) /*!< SSP0 MIS: RORMIS Mask */\r
-#define SSP0_MIS_RTMIS_Pos 1 /*!< SSP0 MIS: RTMIS Position */\r
-#define SSP0_MIS_RTMIS_Msk (0x01UL << SSP0_MIS_RTMIS_Pos) /*!< SSP0 MIS: RTMIS Mask */\r
-#define SSP0_MIS_RXMIS_Pos 2 /*!< SSP0 MIS: RXMIS Position */\r
-#define SSP0_MIS_RXMIS_Msk (0x01UL << SSP0_MIS_RXMIS_Pos) /*!< SSP0 MIS: RXMIS Mask */\r
-#define SSP0_MIS_TXMIS_Pos 3 /*!< SSP0 MIS: TXMIS Position */\r
-#define SSP0_MIS_TXMIS_Msk (0x01UL << SSP0_MIS_TXMIS_Pos) /*!< SSP0 MIS: TXMIS Mask */\r
-\r
-// ---------------------------------------- SSP0_ICR --------------------------------------------\r
-#define SSP0_ICR_RORIC_Pos 0 /*!< SSP0 ICR: RORIC Position */\r
-#define SSP0_ICR_RORIC_Msk (0x01UL << SSP0_ICR_RORIC_Pos) /*!< SSP0 ICR: RORIC Mask */\r
-#define SSP0_ICR_RTIC_Pos 1 /*!< SSP0 ICR: RTIC Position */\r
-#define SSP0_ICR_RTIC_Msk (0x01UL << SSP0_ICR_RTIC_Pos) /*!< SSP0 ICR: RTIC Mask */\r
-\r
-// --------------------------------------- SSP0_DMACR -------------------------------------------\r
-#define SSP0_DMACR_RXDMAE_Pos 0 /*!< SSP0 DMACR: RXDMAE Position */\r
-#define SSP0_DMACR_RXDMAE_Msk (0x01UL << SSP0_DMACR_RXDMAE_Pos) /*!< SSP0 DMACR: RXDMAE Mask */\r
-#define SSP0_DMACR_TXDMAE_Pos 1 /*!< SSP0 DMACR: TXDMAE Position */\r
-#define SSP0_DMACR_TXDMAE_Msk (0x01UL << SSP0_DMACR_TXDMAE_Pos) /*!< SSP0 DMACR: TXDMAE Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- SSP1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- SSP1_CR0 --------------------------------------------\r
-#define SSP1_CR0_DSS_Pos 0 /*!< SSP1 CR0: DSS Position */\r
-#define SSP1_CR0_DSS_Msk (0x0fUL << SSP1_CR0_DSS_Pos) /*!< SSP1 CR0: DSS Mask */\r
-#define SSP1_CR0_FRF_Pos 4 /*!< SSP1 CR0: FRF Position */\r
-#define SSP1_CR0_FRF_Msk (0x03UL << SSP1_CR0_FRF_Pos) /*!< SSP1 CR0: FRF Mask */\r
-#define SSP1_CR0_CPOL_Pos 6 /*!< SSP1 CR0: CPOL Position */\r
-#define SSP1_CR0_CPOL_Msk (0x01UL << SSP1_CR0_CPOL_Pos) /*!< SSP1 CR0: CPOL Mask */\r
-#define SSP1_CR0_CPHA_Pos 7 /*!< SSP1 CR0: CPHA Position */\r
-#define SSP1_CR0_CPHA_Msk (0x01UL << SSP1_CR0_CPHA_Pos) /*!< SSP1 CR0: CPHA Mask */\r
-#define SSP1_CR0_SCR_Pos 8 /*!< SSP1 CR0: SCR Position */\r
-#define SSP1_CR0_SCR_Msk (0x000000ffUL << SSP1_CR0_SCR_Pos) /*!< SSP1 CR0: SCR Mask */\r
-\r
-// ---------------------------------------- SSP1_CR1 --------------------------------------------\r
-#define SSP1_CR1_LBM_Pos 0 /*!< SSP1 CR1: LBM Position */\r
-#define SSP1_CR1_LBM_Msk (0x01UL << SSP1_CR1_LBM_Pos) /*!< SSP1 CR1: LBM Mask */\r
-#define SSP1_CR1_SSE_Pos 1 /*!< SSP1 CR1: SSE Position */\r
-#define SSP1_CR1_SSE_Msk (0x01UL << SSP1_CR1_SSE_Pos) /*!< SSP1 CR1: SSE Mask */\r
-#define SSP1_CR1_MS_Pos 2 /*!< SSP1 CR1: MS Position */\r
-#define SSP1_CR1_MS_Msk (0x01UL << SSP1_CR1_MS_Pos) /*!< SSP1 CR1: MS Mask */\r
-#define SSP1_CR1_SOD_Pos 3 /*!< SSP1 CR1: SOD Position */\r
-#define SSP1_CR1_SOD_Msk (0x01UL << SSP1_CR1_SOD_Pos) /*!< SSP1 CR1: SOD Mask */\r
-\r
-// ----------------------------------------- SSP1_DR --------------------------------------------\r
-#define SSP1_DR_DATA_Pos 0 /*!< SSP1 DR: DATA Position */\r
-#define SSP1_DR_DATA_Msk (0x0000ffffUL << SSP1_DR_DATA_Pos) /*!< SSP1 DR: DATA Mask */\r
-\r
-// ----------------------------------------- SSP1_SR --------------------------------------------\r
-#define SSP1_SR_TFE_Pos 0 /*!< SSP1 SR: TFE Position */\r
-#define SSP1_SR_TFE_Msk (0x01UL << SSP1_SR_TFE_Pos) /*!< SSP1 SR: TFE Mask */\r
-#define SSP1_SR_TNF_Pos 1 /*!< SSP1 SR: TNF Position */\r
-#define SSP1_SR_TNF_Msk (0x01UL << SSP1_SR_TNF_Pos) /*!< SSP1 SR: TNF Mask */\r
-#define SSP1_SR_RNE_Pos 2 /*!< SSP1 SR: RNE Position */\r
-#define SSP1_SR_RNE_Msk (0x01UL << SSP1_SR_RNE_Pos) /*!< SSP1 SR: RNE Mask */\r
-#define SSP1_SR_RFF_Pos 3 /*!< SSP1 SR: RFF Position */\r
-#define SSP1_SR_RFF_Msk (0x01UL << SSP1_SR_RFF_Pos) /*!< SSP1 SR: RFF Mask */\r
-#define SSP1_SR_BSY_Pos 4 /*!< SSP1 SR: BSY Position */\r
-#define SSP1_SR_BSY_Msk (0x01UL << SSP1_SR_BSY_Pos) /*!< SSP1 SR: BSY Mask */\r
-\r
-// ---------------------------------------- SSP1_CPSR -------------------------------------------\r
-#define SSP1_CPSR_CPSDVSR_Pos 0 /*!< SSP1 CPSR: CPSDVSR Position */\r
-#define SSP1_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos) /*!< SSP1 CPSR: CPSDVSR Mask */\r
-\r
-// ---------------------------------------- SSP1_IMSC -------------------------------------------\r
-#define SSP1_IMSC_RORIM_Pos 0 /*!< SSP1 IMSC: RORIM Position */\r
-#define SSP1_IMSC_RORIM_Msk (0x01UL << SSP1_IMSC_RORIM_Pos) /*!< SSP1 IMSC: RORIM Mask */\r
-#define SSP1_IMSC_RTIM_Pos 1 /*!< SSP1 IMSC: RTIM Position */\r
-#define SSP1_IMSC_RTIM_Msk (0x01UL << SSP1_IMSC_RTIM_Pos) /*!< SSP1 IMSC: RTIM Mask */\r
-#define SSP1_IMSC_RXIM_Pos 2 /*!< SSP1 IMSC: RXIM Position */\r
-#define SSP1_IMSC_RXIM_Msk (0x01UL << SSP1_IMSC_RXIM_Pos) /*!< SSP1 IMSC: RXIM Mask */\r
-#define SSP1_IMSC_TXIM_Pos 3 /*!< SSP1 IMSC: TXIM Position */\r
-#define SSP1_IMSC_TXIM_Msk (0x01UL << SSP1_IMSC_TXIM_Pos) /*!< SSP1 IMSC: TXIM Mask */\r
-\r
-// ---------------------------------------- SSP1_RIS --------------------------------------------\r
-#define SSP1_RIS_RORRIS_Pos 0 /*!< SSP1 RIS: RORRIS Position */\r
-#define SSP1_RIS_RORRIS_Msk (0x01UL << SSP1_RIS_RORRIS_Pos) /*!< SSP1 RIS: RORRIS Mask */\r
-#define SSP1_RIS_RTRIS_Pos 1 /*!< SSP1 RIS: RTRIS Position */\r
-#define SSP1_RIS_RTRIS_Msk (0x01UL << SSP1_RIS_RTRIS_Pos) /*!< SSP1 RIS: RTRIS Mask */\r
-#define SSP1_RIS_RXRIS_Pos 2 /*!< SSP1 RIS: RXRIS Position */\r
-#define SSP1_RIS_RXRIS_Msk (0x01UL << SSP1_RIS_RXRIS_Pos) /*!< SSP1 RIS: RXRIS Mask */\r
-#define SSP1_RIS_TXRIS_Pos 3 /*!< SSP1 RIS: TXRIS Position */\r
-#define SSP1_RIS_TXRIS_Msk (0x01UL << SSP1_RIS_TXRIS_Pos) /*!< SSP1 RIS: TXRIS Mask */\r
-\r
-// ---------------------------------------- SSP1_MIS --------------------------------------------\r
-#define SSP1_MIS_RORMIS_Pos 0 /*!< SSP1 MIS: RORMIS Position */\r
-#define SSP1_MIS_RORMIS_Msk (0x01UL << SSP1_MIS_RORMIS_Pos) /*!< SSP1 MIS: RORMIS Mask */\r
-#define SSP1_MIS_RTMIS_Pos 1 /*!< SSP1 MIS: RTMIS Position */\r
-#define SSP1_MIS_RTMIS_Msk (0x01UL << SSP1_MIS_RTMIS_Pos) /*!< SSP1 MIS: RTMIS Mask */\r
-#define SSP1_MIS_RXMIS_Pos 2 /*!< SSP1 MIS: RXMIS Position */\r
-#define SSP1_MIS_RXMIS_Msk (0x01UL << SSP1_MIS_RXMIS_Pos) /*!< SSP1 MIS: RXMIS Mask */\r
-#define SSP1_MIS_TXMIS_Pos 3 /*!< SSP1 MIS: TXMIS Position */\r
-#define SSP1_MIS_TXMIS_Msk (0x01UL << SSP1_MIS_TXMIS_Pos) /*!< SSP1 MIS: TXMIS Mask */\r
-\r
-// ---------------------------------------- SSP1_ICR --------------------------------------------\r
-#define SSP1_ICR_RORIC_Pos 0 /*!< SSP1 ICR: RORIC Position */\r
-#define SSP1_ICR_RORIC_Msk (0x01UL << SSP1_ICR_RORIC_Pos) /*!< SSP1 ICR: RORIC Mask */\r
-#define SSP1_ICR_RTIC_Pos 1 /*!< SSP1 ICR: RTIC Position */\r
-#define SSP1_ICR_RTIC_Msk (0x01UL << SSP1_ICR_RTIC_Pos) /*!< SSP1 ICR: RTIC Mask */\r
-\r
-// --------------------------------------- SSP1_DMACR -------------------------------------------\r
-#define SSP1_DMACR_RXDMAE_Pos 0 /*!< SSP1 DMACR: RXDMAE Position */\r
-#define SSP1_DMACR_RXDMAE_Msk (0x01UL << SSP1_DMACR_RXDMAE_Pos) /*!< SSP1 DMACR: RXDMAE Mask */\r
-#define SSP1_DMACR_TXDMAE_Pos 1 /*!< SSP1 DMACR: TXDMAE Position */\r
-#define SSP1_DMACR_TXDMAE_Msk (0x01UL << SSP1_DMACR_TXDMAE_Pos) /*!< SSP1 DMACR: TXDMAE Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- TIMER0 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- TIMER0_IR -------------------------------------------\r
-#define TIMER0_IR_MR0INT_Pos 0 /*!< TIMER0 IR: MR0INT Position */\r
-#define TIMER0_IR_MR0INT_Msk (0x01UL << TIMER0_IR_MR0INT_Pos) /*!< TIMER0 IR: MR0INT Mask */\r
-#define TIMER0_IR_MR1INT_Pos 1 /*!< TIMER0 IR: MR1INT Position */\r
-#define TIMER0_IR_MR1INT_Msk (0x01UL << TIMER0_IR_MR1INT_Pos) /*!< TIMER0 IR: MR1INT Mask */\r
-#define TIMER0_IR_MR2INT_Pos 2 /*!< TIMER0 IR: MR2INT Position */\r
-#define TIMER0_IR_MR2INT_Msk (0x01UL << TIMER0_IR_MR2INT_Pos) /*!< TIMER0 IR: MR2INT Mask */\r
-#define TIMER0_IR_MR3INT_Pos 3 /*!< TIMER0 IR: MR3INT Position */\r
-#define TIMER0_IR_MR3INT_Msk (0x01UL << TIMER0_IR_MR3INT_Pos) /*!< TIMER0 IR: MR3INT Mask */\r
-#define TIMER0_IR_CR0INT_Pos 4 /*!< TIMER0 IR: CR0INT Position */\r
-#define TIMER0_IR_CR0INT_Msk (0x01UL << TIMER0_IR_CR0INT_Pos) /*!< TIMER0 IR: CR0INT Mask */\r
-#define TIMER0_IR_CR1INT_Pos 5 /*!< TIMER0 IR: CR1INT Position */\r
-#define TIMER0_IR_CR1INT_Msk (0x01UL << TIMER0_IR_CR1INT_Pos) /*!< TIMER0 IR: CR1INT Mask */\r
-#define TIMER0_IR_CR2INT_Pos 6 /*!< TIMER0 IR: CR2INT Position */\r
-#define TIMER0_IR_CR2INT_Msk (0x01UL << TIMER0_IR_CR2INT_Pos) /*!< TIMER0 IR: CR2INT Mask */\r
-#define TIMER0_IR_CR3INT_Pos 7 /*!< TIMER0 IR: CR3INT Position */\r
-#define TIMER0_IR_CR3INT_Msk (0x01UL << TIMER0_IR_CR3INT_Pos) /*!< TIMER0 IR: CR3INT Mask */\r
-\r
-// --------------------------------------- TIMER0_TCR -------------------------------------------\r
-#define TIMER0_TCR_CEN_Pos 0 /*!< TIMER0 TCR: CEN Position */\r
-#define TIMER0_TCR_CEN_Msk (0x01UL << TIMER0_TCR_CEN_Pos) /*!< TIMER0 TCR: CEN Mask */\r
-#define TIMER0_TCR_CRST_Pos 1 /*!< TIMER0 TCR: CRST Position */\r
-#define TIMER0_TCR_CRST_Msk (0x01UL << TIMER0_TCR_CRST_Pos) /*!< TIMER0 TCR: CRST Mask */\r
-\r
-// ---------------------------------------- TIMER0_TC -------------------------------------------\r
-#define TIMER0_TC_TC_Pos 0 /*!< TIMER0 TC: TC Position */\r
-#define TIMER0_TC_TC_Msk (0xffffffffUL << TIMER0_TC_TC_Pos) /*!< TIMER0 TC: TC Mask */\r
-\r
-// ---------------------------------------- TIMER0_PR -------------------------------------------\r
-#define TIMER0_PR_PM_Pos 0 /*!< TIMER0 PR: PM Position */\r
-#define TIMER0_PR_PM_Msk (0xffffffffUL << TIMER0_PR_PM_Pos) /*!< TIMER0 PR: PM Mask */\r
-\r
-// ---------------------------------------- TIMER0_PC -------------------------------------------\r
-#define TIMER0_PC_PC_Pos 0 /*!< TIMER0 PC: PC Position */\r
-#define TIMER0_PC_PC_Msk (0xffffffffUL << TIMER0_PC_PC_Pos) /*!< TIMER0 PC: PC Mask */\r
-\r
-// --------------------------------------- TIMER0_MCR -------------------------------------------\r
-#define TIMER0_MCR_MR0I_Pos 0 /*!< TIMER0 MCR: MR0I Position */\r
-#define TIMER0_MCR_MR0I_Msk (0x01UL << TIMER0_MCR_MR0I_Pos) /*!< TIMER0 MCR: MR0I Mask */\r
-#define TIMER0_MCR_MR0R_Pos 1 /*!< TIMER0 MCR: MR0R Position */\r
-#define TIMER0_MCR_MR0R_Msk (0x01UL << TIMER0_MCR_MR0R_Pos) /*!< TIMER0 MCR: MR0R Mask */\r
-#define TIMER0_MCR_MR0S_Pos 2 /*!< TIMER0 MCR: MR0S Position */\r
-#define TIMER0_MCR_MR0S_Msk (0x01UL << TIMER0_MCR_MR0S_Pos) /*!< TIMER0 MCR: MR0S Mask */\r
-#define TIMER0_MCR_MR1I_Pos 3 /*!< TIMER0 MCR: MR1I Position */\r
-#define TIMER0_MCR_MR1I_Msk (0x01UL << TIMER0_MCR_MR1I_Pos) /*!< TIMER0 MCR: MR1I Mask */\r
-#define TIMER0_MCR_MR1R_Pos 4 /*!< TIMER0 MCR: MR1R Position */\r
-#define TIMER0_MCR_MR1R_Msk (0x01UL << TIMER0_MCR_MR1R_Pos) /*!< TIMER0 MCR: MR1R Mask */\r
-#define TIMER0_MCR_MR1S_Pos 5 /*!< TIMER0 MCR: MR1S Position */\r
-#define TIMER0_MCR_MR1S_Msk (0x01UL << TIMER0_MCR_MR1S_Pos) /*!< TIMER0 MCR: MR1S Mask */\r
-#define TIMER0_MCR_MR2I_Pos 6 /*!< TIMER0 MCR: MR2I Position */\r
-#define TIMER0_MCR_MR2I_Msk (0x01UL << TIMER0_MCR_MR2I_Pos) /*!< TIMER0 MCR: MR2I Mask */\r
-#define TIMER0_MCR_MR2R_Pos 7 /*!< TIMER0 MCR: MR2R Position */\r
-#define TIMER0_MCR_MR2R_Msk (0x01UL << TIMER0_MCR_MR2R_Pos) /*!< TIMER0 MCR: MR2R Mask */\r
-#define TIMER0_MCR_MR2S_Pos 8 /*!< TIMER0 MCR: MR2S Position */\r
-#define TIMER0_MCR_MR2S_Msk (0x01UL << TIMER0_MCR_MR2S_Pos) /*!< TIMER0 MCR: MR2S Mask */\r
-#define TIMER0_MCR_MR3I_Pos 9 /*!< TIMER0 MCR: MR3I Position */\r
-#define TIMER0_MCR_MR3I_Msk (0x01UL << TIMER0_MCR_MR3I_Pos) /*!< TIMER0 MCR: MR3I Mask */\r
-#define TIMER0_MCR_MR3R_Pos 10 /*!< TIMER0 MCR: MR3R Position */\r
-#define TIMER0_MCR_MR3R_Msk (0x01UL << TIMER0_MCR_MR3R_Pos) /*!< TIMER0 MCR: MR3R Mask */\r
-#define TIMER0_MCR_MR3S_Pos 11 /*!< TIMER0 MCR: MR3S Position */\r
-#define TIMER0_MCR_MR3S_Msk (0x01UL << TIMER0_MCR_MR3S_Pos) /*!< TIMER0 MCR: MR3S Mask */\r
-\r
-// --------------------------------------- TIMER0_MR0 -------------------------------------------\r
-#define TIMER0_MR0_MATCH_Pos 0 /*!< TIMER0 MR0: MATCH Position */\r
-#define TIMER0_MR0_MATCH_Msk (0xffffffffUL << TIMER0_MR0_MATCH_Pos) /*!< TIMER0 MR0: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER0_MR1 -------------------------------------------\r
-#define TIMER0_MR1_MATCH_Pos 0 /*!< TIMER0 MR1: MATCH Position */\r
-#define TIMER0_MR1_MATCH_Msk (0xffffffffUL << TIMER0_MR1_MATCH_Pos) /*!< TIMER0 MR1: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER0_MR2 -------------------------------------------\r
-#define TIMER0_MR2_MATCH_Pos 0 /*!< TIMER0 MR2: MATCH Position */\r
-#define TIMER0_MR2_MATCH_Msk (0xffffffffUL << TIMER0_MR2_MATCH_Pos) /*!< TIMER0 MR2: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER0_MR3 -------------------------------------------\r
-#define TIMER0_MR3_MATCH_Pos 0 /*!< TIMER0 MR3: MATCH Position */\r
-#define TIMER0_MR3_MATCH_Msk (0xffffffffUL << TIMER0_MR3_MATCH_Pos) /*!< TIMER0 MR3: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER0_CCR -------------------------------------------\r
-#define TIMER0_CCR_CAP0RE_Pos 0 /*!< TIMER0 CCR: CAP0RE Position */\r
-#define TIMER0_CCR_CAP0RE_Msk (0x01UL << TIMER0_CCR_CAP0RE_Pos) /*!< TIMER0 CCR: CAP0RE Mask */\r
-#define TIMER0_CCR_CAP0FE_Pos 1 /*!< TIMER0 CCR: CAP0FE Position */\r
-#define TIMER0_CCR_CAP0FE_Msk (0x01UL << TIMER0_CCR_CAP0FE_Pos) /*!< TIMER0 CCR: CAP0FE Mask */\r
-#define TIMER0_CCR_CAP0I_Pos 2 /*!< TIMER0 CCR: CAP0I Position */\r
-#define TIMER0_CCR_CAP0I_Msk (0x01UL << TIMER0_CCR_CAP0I_Pos) /*!< TIMER0 CCR: CAP0I Mask */\r
-#define TIMER0_CCR_CAP1RE_Pos 3 /*!< TIMER0 CCR: CAP1RE Position */\r
-#define TIMER0_CCR_CAP1RE_Msk (0x01UL << TIMER0_CCR_CAP1RE_Pos) /*!< TIMER0 CCR: CAP1RE Mask */\r
-#define TIMER0_CCR_CAP1FE_Pos 4 /*!< TIMER0 CCR: CAP1FE Position */\r
-#define TIMER0_CCR_CAP1FE_Msk (0x01UL << TIMER0_CCR_CAP1FE_Pos) /*!< TIMER0 CCR: CAP1FE Mask */\r
-#define TIMER0_CCR_CAP1I_Pos 5 /*!< TIMER0 CCR: CAP1I Position */\r
-#define TIMER0_CCR_CAP1I_Msk (0x01UL << TIMER0_CCR_CAP1I_Pos) /*!< TIMER0 CCR: CAP1I Mask */\r
-#define TIMER0_CCR_CAP2RE_Pos 6 /*!< TIMER0 CCR: CAP2RE Position */\r
-#define TIMER0_CCR_CAP2RE_Msk (0x01UL << TIMER0_CCR_CAP2RE_Pos) /*!< TIMER0 CCR: CAP2RE Mask */\r
-#define TIMER0_CCR_CAP2FE_Pos 7 /*!< TIMER0 CCR: CAP2FE Position */\r
-#define TIMER0_CCR_CAP2FE_Msk (0x01UL << TIMER0_CCR_CAP2FE_Pos) /*!< TIMER0 CCR: CAP2FE Mask */\r
-#define TIMER0_CCR_CAP2I_Pos 8 /*!< TIMER0 CCR: CAP2I Position */\r
-#define TIMER0_CCR_CAP2I_Msk (0x01UL << TIMER0_CCR_CAP2I_Pos) /*!< TIMER0 CCR: CAP2I Mask */\r
-#define TIMER0_CCR_CAP3RE_Pos 9 /*!< TIMER0 CCR: CAP3RE Position */\r
-#define TIMER0_CCR_CAP3RE_Msk (0x01UL << TIMER0_CCR_CAP3RE_Pos) /*!< TIMER0 CCR: CAP3RE Mask */\r
-#define TIMER0_CCR_CAP3FE_Pos 10 /*!< TIMER0 CCR: CAP3FE Position */\r
-#define TIMER0_CCR_CAP3FE_Msk (0x01UL << TIMER0_CCR_CAP3FE_Pos) /*!< TIMER0 CCR: CAP3FE Mask */\r
-#define TIMER0_CCR_CAP3I_Pos 11 /*!< TIMER0 CCR: CAP3I Position */\r
-#define TIMER0_CCR_CAP3I_Msk (0x01UL << TIMER0_CCR_CAP3I_Pos) /*!< TIMER0 CCR: CAP3I Mask */\r
-\r
-// --------------------------------------- TIMER0_CR0 -------------------------------------------\r
-#define TIMER0_CR0_CAP_Pos 0 /*!< TIMER0 CR0: CAP Position */\r
-#define TIMER0_CR0_CAP_Msk (0xffffffffUL << TIMER0_CR0_CAP_Pos) /*!< TIMER0 CR0: CAP Mask */\r
-\r
-// --------------------------------------- TIMER0_CR1 -------------------------------------------\r
-#define TIMER0_CR1_CAP_Pos 0 /*!< TIMER0 CR1: CAP Position */\r
-#define TIMER0_CR1_CAP_Msk (0xffffffffUL << TIMER0_CR1_CAP_Pos) /*!< TIMER0 CR1: CAP Mask */\r
-\r
-// --------------------------------------- TIMER0_CR2 -------------------------------------------\r
-#define TIMER0_CR2_CAP_Pos 0 /*!< TIMER0 CR2: CAP Position */\r
-#define TIMER0_CR2_CAP_Msk (0xffffffffUL << TIMER0_CR2_CAP_Pos) /*!< TIMER0 CR2: CAP Mask */\r
-\r
-// --------------------------------------- TIMER0_CR3 -------------------------------------------\r
-#define TIMER0_CR3_CAP_Pos 0 /*!< TIMER0 CR3: CAP Position */\r
-#define TIMER0_CR3_CAP_Msk (0xffffffffUL << TIMER0_CR3_CAP_Pos) /*!< TIMER0 CR3: CAP Mask */\r
-\r
-// --------------------------------------- TIMER0_EMR -------------------------------------------\r
-#define TIMER0_EMR_EM0_Pos 0 /*!< TIMER0 EMR: EM0 Position */\r
-#define TIMER0_EMR_EM0_Msk (0x01UL << TIMER0_EMR_EM0_Pos) /*!< TIMER0 EMR: EM0 Mask */\r
-#define TIMER0_EMR_EM1_Pos 1 /*!< TIMER0 EMR: EM1 Position */\r
-#define TIMER0_EMR_EM1_Msk (0x01UL << TIMER0_EMR_EM1_Pos) /*!< TIMER0 EMR: EM1 Mask */\r
-#define TIMER0_EMR_EM2_Pos 2 /*!< TIMER0 EMR: EM2 Position */\r
-#define TIMER0_EMR_EM2_Msk (0x01UL << TIMER0_EMR_EM2_Pos) /*!< TIMER0 EMR: EM2 Mask */\r
-#define TIMER0_EMR_EM3_Pos 3 /*!< TIMER0 EMR: EM3 Position */\r
-#define TIMER0_EMR_EM3_Msk (0x01UL << TIMER0_EMR_EM3_Pos) /*!< TIMER0 EMR: EM3 Mask */\r
-#define TIMER0_EMR_EMC0_Pos 4 /*!< TIMER0 EMR: EMC0 Position */\r
-#define TIMER0_EMR_EMC0_Msk (0x03UL << TIMER0_EMR_EMC0_Pos) /*!< TIMER0 EMR: EMC0 Mask */\r
-#define TIMER0_EMR_EMC1_Pos 6 /*!< TIMER0 EMR: EMC1 Position */\r
-#define TIMER0_EMR_EMC1_Msk (0x03UL << TIMER0_EMR_EMC1_Pos) /*!< TIMER0 EMR: EMC1 Mask */\r
-#define TIMER0_EMR_EMC2_Pos 8 /*!< TIMER0 EMR: EMC2 Position */\r
-#define TIMER0_EMR_EMC2_Msk (0x03UL << TIMER0_EMR_EMC2_Pos) /*!< TIMER0 EMR: EMC2 Mask */\r
-#define TIMER0_EMR_EMC3_Pos 10 /*!< TIMER0 EMR: EMC3 Position */\r
-#define TIMER0_EMR_EMC3_Msk (0x03UL << TIMER0_EMR_EMC3_Pos) /*!< TIMER0 EMR: EMC3 Mask */\r
-\r
-// --------------------------------------- TIMER0_CTCR ------------------------------------------\r
-#define TIMER0_CTCR_CTMODE_Pos 0 /*!< TIMER0 CTCR: CTMODE Position */\r
-#define TIMER0_CTCR_CTMODE_Msk (0x03UL << TIMER0_CTCR_CTMODE_Pos) /*!< TIMER0 CTCR: CTMODE Mask */\r
-#define TIMER0_CTCR_CINSEL_Pos 2 /*!< TIMER0 CTCR: CINSEL Position */\r
-#define TIMER0_CTCR_CINSEL_Msk (0x03UL << TIMER0_CTCR_CINSEL_Pos) /*!< TIMER0 CTCR: CINSEL Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- TIMER1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- TIMER1_IR -------------------------------------------\r
-#define TIMER1_IR_MR0INT_Pos 0 /*!< TIMER1 IR: MR0INT Position */\r
-#define TIMER1_IR_MR0INT_Msk (0x01UL << TIMER1_IR_MR0INT_Pos) /*!< TIMER1 IR: MR0INT Mask */\r
-#define TIMER1_IR_MR1INT_Pos 1 /*!< TIMER1 IR: MR1INT Position */\r
-#define TIMER1_IR_MR1INT_Msk (0x01UL << TIMER1_IR_MR1INT_Pos) /*!< TIMER1 IR: MR1INT Mask */\r
-#define TIMER1_IR_MR2INT_Pos 2 /*!< TIMER1 IR: MR2INT Position */\r
-#define TIMER1_IR_MR2INT_Msk (0x01UL << TIMER1_IR_MR2INT_Pos) /*!< TIMER1 IR: MR2INT Mask */\r
-#define TIMER1_IR_MR3INT_Pos 3 /*!< TIMER1 IR: MR3INT Position */\r
-#define TIMER1_IR_MR3INT_Msk (0x01UL << TIMER1_IR_MR3INT_Pos) /*!< TIMER1 IR: MR3INT Mask */\r
-#define TIMER1_IR_CR0INT_Pos 4 /*!< TIMER1 IR: CR0INT Position */\r
-#define TIMER1_IR_CR0INT_Msk (0x01UL << TIMER1_IR_CR0INT_Pos) /*!< TIMER1 IR: CR0INT Mask */\r
-#define TIMER1_IR_CR1INT_Pos 5 /*!< TIMER1 IR: CR1INT Position */\r
-#define TIMER1_IR_CR1INT_Msk (0x01UL << TIMER1_IR_CR1INT_Pos) /*!< TIMER1 IR: CR1INT Mask */\r
-#define TIMER1_IR_CR2INT_Pos 6 /*!< TIMER1 IR: CR2INT Position */\r
-#define TIMER1_IR_CR2INT_Msk (0x01UL << TIMER1_IR_CR2INT_Pos) /*!< TIMER1 IR: CR2INT Mask */\r
-#define TIMER1_IR_CR3INT_Pos 7 /*!< TIMER1 IR: CR3INT Position */\r
-#define TIMER1_IR_CR3INT_Msk (0x01UL << TIMER1_IR_CR3INT_Pos) /*!< TIMER1 IR: CR3INT Mask */\r
-\r
-// --------------------------------------- TIMER1_TCR -------------------------------------------\r
-#define TIMER1_TCR_CEN_Pos 0 /*!< TIMER1 TCR: CEN Position */\r
-#define TIMER1_TCR_CEN_Msk (0x01UL << TIMER1_TCR_CEN_Pos) /*!< TIMER1 TCR: CEN Mask */\r
-#define TIMER1_TCR_CRST_Pos 1 /*!< TIMER1 TCR: CRST Position */\r
-#define TIMER1_TCR_CRST_Msk (0x01UL << TIMER1_TCR_CRST_Pos) /*!< TIMER1 TCR: CRST Mask */\r
-\r
-// ---------------------------------------- TIMER1_TC -------------------------------------------\r
-#define TIMER1_TC_TC_Pos 0 /*!< TIMER1 TC: TC Position */\r
-#define TIMER1_TC_TC_Msk (0xffffffffUL << TIMER1_TC_TC_Pos) /*!< TIMER1 TC: TC Mask */\r
-\r
-// ---------------------------------------- TIMER1_PR -------------------------------------------\r
-#define TIMER1_PR_PM_Pos 0 /*!< TIMER1 PR: PM Position */\r
-#define TIMER1_PR_PM_Msk (0xffffffffUL << TIMER1_PR_PM_Pos) /*!< TIMER1 PR: PM Mask */\r
-\r
-// ---------------------------------------- TIMER1_PC -------------------------------------------\r
-#define TIMER1_PC_PC_Pos 0 /*!< TIMER1 PC: PC Position */\r
-#define TIMER1_PC_PC_Msk (0xffffffffUL << TIMER1_PC_PC_Pos) /*!< TIMER1 PC: PC Mask */\r
-\r
-// --------------------------------------- TIMER1_MCR -------------------------------------------\r
-#define TIMER1_MCR_MR0I_Pos 0 /*!< TIMER1 MCR: MR0I Position */\r
-#define TIMER1_MCR_MR0I_Msk (0x01UL << TIMER1_MCR_MR0I_Pos) /*!< TIMER1 MCR: MR0I Mask */\r
-#define TIMER1_MCR_MR0R_Pos 1 /*!< TIMER1 MCR: MR0R Position */\r
-#define TIMER1_MCR_MR0R_Msk (0x01UL << TIMER1_MCR_MR0R_Pos) /*!< TIMER1 MCR: MR0R Mask */\r
-#define TIMER1_MCR_MR0S_Pos 2 /*!< TIMER1 MCR: MR0S Position */\r
-#define TIMER1_MCR_MR0S_Msk (0x01UL << TIMER1_MCR_MR0S_Pos) /*!< TIMER1 MCR: MR0S Mask */\r
-#define TIMER1_MCR_MR1I_Pos 3 /*!< TIMER1 MCR: MR1I Position */\r
-#define TIMER1_MCR_MR1I_Msk (0x01UL << TIMER1_MCR_MR1I_Pos) /*!< TIMER1 MCR: MR1I Mask */\r
-#define TIMER1_MCR_MR1R_Pos 4 /*!< TIMER1 MCR: MR1R Position */\r
-#define TIMER1_MCR_MR1R_Msk (0x01UL << TIMER1_MCR_MR1R_Pos) /*!< TIMER1 MCR: MR1R Mask */\r
-#define TIMER1_MCR_MR1S_Pos 5 /*!< TIMER1 MCR: MR1S Position */\r
-#define TIMER1_MCR_MR1S_Msk (0x01UL << TIMER1_MCR_MR1S_Pos) /*!< TIMER1 MCR: MR1S Mask */\r
-#define TIMER1_MCR_MR2I_Pos 6 /*!< TIMER1 MCR: MR2I Position */\r
-#define TIMER1_MCR_MR2I_Msk (0x01UL << TIMER1_MCR_MR2I_Pos) /*!< TIMER1 MCR: MR2I Mask */\r
-#define TIMER1_MCR_MR2R_Pos 7 /*!< TIMER1 MCR: MR2R Position */\r
-#define TIMER1_MCR_MR2R_Msk (0x01UL << TIMER1_MCR_MR2R_Pos) /*!< TIMER1 MCR: MR2R Mask */\r
-#define TIMER1_MCR_MR2S_Pos 8 /*!< TIMER1 MCR: MR2S Position */\r
-#define TIMER1_MCR_MR2S_Msk (0x01UL << TIMER1_MCR_MR2S_Pos) /*!< TIMER1 MCR: MR2S Mask */\r
-#define TIMER1_MCR_MR3I_Pos 9 /*!< TIMER1 MCR: MR3I Position */\r
-#define TIMER1_MCR_MR3I_Msk (0x01UL << TIMER1_MCR_MR3I_Pos) /*!< TIMER1 MCR: MR3I Mask */\r
-#define TIMER1_MCR_MR3R_Pos 10 /*!< TIMER1 MCR: MR3R Position */\r
-#define TIMER1_MCR_MR3R_Msk (0x01UL << TIMER1_MCR_MR3R_Pos) /*!< TIMER1 MCR: MR3R Mask */\r
-#define TIMER1_MCR_MR3S_Pos 11 /*!< TIMER1 MCR: MR3S Position */\r
-#define TIMER1_MCR_MR3S_Msk (0x01UL << TIMER1_MCR_MR3S_Pos) /*!< TIMER1 MCR: MR3S Mask */\r
-\r
-// --------------------------------------- TIMER1_MR0 -------------------------------------------\r
-#define TIMER1_MR0_MATCH_Pos 0 /*!< TIMER1 MR0: MATCH Position */\r
-#define TIMER1_MR0_MATCH_Msk (0xffffffffUL << TIMER1_MR0_MATCH_Pos) /*!< TIMER1 MR0: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER1_MR1 -------------------------------------------\r
-#define TIMER1_MR1_MATCH_Pos 0 /*!< TIMER1 MR1: MATCH Position */\r
-#define TIMER1_MR1_MATCH_Msk (0xffffffffUL << TIMER1_MR1_MATCH_Pos) /*!< TIMER1 MR1: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER1_MR2 -------------------------------------------\r
-#define TIMER1_MR2_MATCH_Pos 0 /*!< TIMER1 MR2: MATCH Position */\r
-#define TIMER1_MR2_MATCH_Msk (0xffffffffUL << TIMER1_MR2_MATCH_Pos) /*!< TIMER1 MR2: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER1_MR3 -------------------------------------------\r
-#define TIMER1_MR3_MATCH_Pos 0 /*!< TIMER1 MR3: MATCH Position */\r
-#define TIMER1_MR3_MATCH_Msk (0xffffffffUL << TIMER1_MR3_MATCH_Pos) /*!< TIMER1 MR3: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER1_CCR -------------------------------------------\r
-#define TIMER1_CCR_CAP0RE_Pos 0 /*!< TIMER1 CCR: CAP0RE Position */\r
-#define TIMER1_CCR_CAP0RE_Msk (0x01UL << TIMER1_CCR_CAP0RE_Pos) /*!< TIMER1 CCR: CAP0RE Mask */\r
-#define TIMER1_CCR_CAP0FE_Pos 1 /*!< TIMER1 CCR: CAP0FE Position */\r
-#define TIMER1_CCR_CAP0FE_Msk (0x01UL << TIMER1_CCR_CAP0FE_Pos) /*!< TIMER1 CCR: CAP0FE Mask */\r
-#define TIMER1_CCR_CAP0I_Pos 2 /*!< TIMER1 CCR: CAP0I Position */\r
-#define TIMER1_CCR_CAP0I_Msk (0x01UL << TIMER1_CCR_CAP0I_Pos) /*!< TIMER1 CCR: CAP0I Mask */\r
-#define TIMER1_CCR_CAP1RE_Pos 3 /*!< TIMER1 CCR: CAP1RE Position */\r
-#define TIMER1_CCR_CAP1RE_Msk (0x01UL << TIMER1_CCR_CAP1RE_Pos) /*!< TIMER1 CCR: CAP1RE Mask */\r
-#define TIMER1_CCR_CAP1FE_Pos 4 /*!< TIMER1 CCR: CAP1FE Position */\r
-#define TIMER1_CCR_CAP1FE_Msk (0x01UL << TIMER1_CCR_CAP1FE_Pos) /*!< TIMER1 CCR: CAP1FE Mask */\r
-#define TIMER1_CCR_CAP1I_Pos 5 /*!< TIMER1 CCR: CAP1I Position */\r
-#define TIMER1_CCR_CAP1I_Msk (0x01UL << TIMER1_CCR_CAP1I_Pos) /*!< TIMER1 CCR: CAP1I Mask */\r
-#define TIMER1_CCR_CAP2RE_Pos 6 /*!< TIMER1 CCR: CAP2RE Position */\r
-#define TIMER1_CCR_CAP2RE_Msk (0x01UL << TIMER1_CCR_CAP2RE_Pos) /*!< TIMER1 CCR: CAP2RE Mask */\r
-#define TIMER1_CCR_CAP2FE_Pos 7 /*!< TIMER1 CCR: CAP2FE Position */\r
-#define TIMER1_CCR_CAP2FE_Msk (0x01UL << TIMER1_CCR_CAP2FE_Pos) /*!< TIMER1 CCR: CAP2FE Mask */\r
-#define TIMER1_CCR_CAP2I_Pos 8 /*!< TIMER1 CCR: CAP2I Position */\r
-#define TIMER1_CCR_CAP2I_Msk (0x01UL << TIMER1_CCR_CAP2I_Pos) /*!< TIMER1 CCR: CAP2I Mask */\r
-#define TIMER1_CCR_CAP3RE_Pos 9 /*!< TIMER1 CCR: CAP3RE Position */\r
-#define TIMER1_CCR_CAP3RE_Msk (0x01UL << TIMER1_CCR_CAP3RE_Pos) /*!< TIMER1 CCR: CAP3RE Mask */\r
-#define TIMER1_CCR_CAP3FE_Pos 10 /*!< TIMER1 CCR: CAP3FE Position */\r
-#define TIMER1_CCR_CAP3FE_Msk (0x01UL << TIMER1_CCR_CAP3FE_Pos) /*!< TIMER1 CCR: CAP3FE Mask */\r
-#define TIMER1_CCR_CAP3I_Pos 11 /*!< TIMER1 CCR: CAP3I Position */\r
-#define TIMER1_CCR_CAP3I_Msk (0x01UL << TIMER1_CCR_CAP3I_Pos) /*!< TIMER1 CCR: CAP3I Mask */\r
-\r
-// --------------------------------------- TIMER1_CR0 -------------------------------------------\r
-#define TIMER1_CR0_CAP_Pos 0 /*!< TIMER1 CR0: CAP Position */\r
-#define TIMER1_CR0_CAP_Msk (0xffffffffUL << TIMER1_CR0_CAP_Pos) /*!< TIMER1 CR0: CAP Mask */\r
-\r
-// --------------------------------------- TIMER1_CR1 -------------------------------------------\r
-#define TIMER1_CR1_CAP_Pos 0 /*!< TIMER1 CR1: CAP Position */\r
-#define TIMER1_CR1_CAP_Msk (0xffffffffUL << TIMER1_CR1_CAP_Pos) /*!< TIMER1 CR1: CAP Mask */\r
-\r
-// --------------------------------------- TIMER1_CR2 -------------------------------------------\r
-#define TIMER1_CR2_CAP_Pos 0 /*!< TIMER1 CR2: CAP Position */\r
-#define TIMER1_CR2_CAP_Msk (0xffffffffUL << TIMER1_CR2_CAP_Pos) /*!< TIMER1 CR2: CAP Mask */\r
-\r
-// --------------------------------------- TIMER1_CR3 -------------------------------------------\r
-#define TIMER1_CR3_CAP_Pos 0 /*!< TIMER1 CR3: CAP Position */\r
-#define TIMER1_CR3_CAP_Msk (0xffffffffUL << TIMER1_CR3_CAP_Pos) /*!< TIMER1 CR3: CAP Mask */\r
-\r
-// --------------------------------------- TIMER1_EMR -------------------------------------------\r
-#define TIMER1_EMR_EM0_Pos 0 /*!< TIMER1 EMR: EM0 Position */\r
-#define TIMER1_EMR_EM0_Msk (0x01UL << TIMER1_EMR_EM0_Pos) /*!< TIMER1 EMR: EM0 Mask */\r
-#define TIMER1_EMR_EM1_Pos 1 /*!< TIMER1 EMR: EM1 Position */\r
-#define TIMER1_EMR_EM1_Msk (0x01UL << TIMER1_EMR_EM1_Pos) /*!< TIMER1 EMR: EM1 Mask */\r
-#define TIMER1_EMR_EM2_Pos 2 /*!< TIMER1 EMR: EM2 Position */\r
-#define TIMER1_EMR_EM2_Msk (0x01UL << TIMER1_EMR_EM2_Pos) /*!< TIMER1 EMR: EM2 Mask */\r
-#define TIMER1_EMR_EM3_Pos 3 /*!< TIMER1 EMR: EM3 Position */\r
-#define TIMER1_EMR_EM3_Msk (0x01UL << TIMER1_EMR_EM3_Pos) /*!< TIMER1 EMR: EM3 Mask */\r
-#define TIMER1_EMR_EMC0_Pos 4 /*!< TIMER1 EMR: EMC0 Position */\r
-#define TIMER1_EMR_EMC0_Msk (0x03UL << TIMER1_EMR_EMC0_Pos) /*!< TIMER1 EMR: EMC0 Mask */\r
-#define TIMER1_EMR_EMC1_Pos 6 /*!< TIMER1 EMR: EMC1 Position */\r
-#define TIMER1_EMR_EMC1_Msk (0x03UL << TIMER1_EMR_EMC1_Pos) /*!< TIMER1 EMR: EMC1 Mask */\r
-#define TIMER1_EMR_EMC2_Pos 8 /*!< TIMER1 EMR: EMC2 Position */\r
-#define TIMER1_EMR_EMC2_Msk (0x03UL << TIMER1_EMR_EMC2_Pos) /*!< TIMER1 EMR: EMC2 Mask */\r
-#define TIMER1_EMR_EMC3_Pos 10 /*!< TIMER1 EMR: EMC3 Position */\r
-#define TIMER1_EMR_EMC3_Msk (0x03UL << TIMER1_EMR_EMC3_Pos) /*!< TIMER1 EMR: EMC3 Mask */\r
-\r
-// --------------------------------------- TIMER1_CTCR ------------------------------------------\r
-#define TIMER1_CTCR_CTMODE_Pos 0 /*!< TIMER1 CTCR: CTMODE Position */\r
-#define TIMER1_CTCR_CTMODE_Msk (0x03UL << TIMER1_CTCR_CTMODE_Pos) /*!< TIMER1 CTCR: CTMODE Mask */\r
-#define TIMER1_CTCR_CINSEL_Pos 2 /*!< TIMER1 CTCR: CINSEL Position */\r
-#define TIMER1_CTCR_CINSEL_Msk (0x03UL << TIMER1_CTCR_CINSEL_Pos) /*!< TIMER1 CTCR: CINSEL Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- TIMER2 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- TIMER2_IR -------------------------------------------\r
-#define TIMER2_IR_MR0INT_Pos 0 /*!< TIMER2 IR: MR0INT Position */\r
-#define TIMER2_IR_MR0INT_Msk (0x01UL << TIMER2_IR_MR0INT_Pos) /*!< TIMER2 IR: MR0INT Mask */\r
-#define TIMER2_IR_MR1INT_Pos 1 /*!< TIMER2 IR: MR1INT Position */\r
-#define TIMER2_IR_MR1INT_Msk (0x01UL << TIMER2_IR_MR1INT_Pos) /*!< TIMER2 IR: MR1INT Mask */\r
-#define TIMER2_IR_MR2INT_Pos 2 /*!< TIMER2 IR: MR2INT Position */\r
-#define TIMER2_IR_MR2INT_Msk (0x01UL << TIMER2_IR_MR2INT_Pos) /*!< TIMER2 IR: MR2INT Mask */\r
-#define TIMER2_IR_MR3INT_Pos 3 /*!< TIMER2 IR: MR3INT Position */\r
-#define TIMER2_IR_MR3INT_Msk (0x01UL << TIMER2_IR_MR3INT_Pos) /*!< TIMER2 IR: MR3INT Mask */\r
-#define TIMER2_IR_CR0INT_Pos 4 /*!< TIMER2 IR: CR0INT Position */\r
-#define TIMER2_IR_CR0INT_Msk (0x01UL << TIMER2_IR_CR0INT_Pos) /*!< TIMER2 IR: CR0INT Mask */\r
-#define TIMER2_IR_CR1INT_Pos 5 /*!< TIMER2 IR: CR1INT Position */\r
-#define TIMER2_IR_CR1INT_Msk (0x01UL << TIMER2_IR_CR1INT_Pos) /*!< TIMER2 IR: CR1INT Mask */\r
-#define TIMER2_IR_CR2INT_Pos 6 /*!< TIMER2 IR: CR2INT Position */\r
-#define TIMER2_IR_CR2INT_Msk (0x01UL << TIMER2_IR_CR2INT_Pos) /*!< TIMER2 IR: CR2INT Mask */\r
-#define TIMER2_IR_CR3INT_Pos 7 /*!< TIMER2 IR: CR3INT Position */\r
-#define TIMER2_IR_CR3INT_Msk (0x01UL << TIMER2_IR_CR3INT_Pos) /*!< TIMER2 IR: CR3INT Mask */\r
-\r
-// --------------------------------------- TIMER2_TCR -------------------------------------------\r
-#define TIMER2_TCR_CEN_Pos 0 /*!< TIMER2 TCR: CEN Position */\r
-#define TIMER2_TCR_CEN_Msk (0x01UL << TIMER2_TCR_CEN_Pos) /*!< TIMER2 TCR: CEN Mask */\r
-#define TIMER2_TCR_CRST_Pos 1 /*!< TIMER2 TCR: CRST Position */\r
-#define TIMER2_TCR_CRST_Msk (0x01UL << TIMER2_TCR_CRST_Pos) /*!< TIMER2 TCR: CRST Mask */\r
-\r
-// ---------------------------------------- TIMER2_TC -------------------------------------------\r
-#define TIMER2_TC_TC_Pos 0 /*!< TIMER2 TC: TC Position */\r
-#define TIMER2_TC_TC_Msk (0xffffffffUL << TIMER2_TC_TC_Pos) /*!< TIMER2 TC: TC Mask */\r
-\r
-// ---------------------------------------- TIMER2_PR -------------------------------------------\r
-#define TIMER2_PR_PM_Pos 0 /*!< TIMER2 PR: PM Position */\r
-#define TIMER2_PR_PM_Msk (0xffffffffUL << TIMER2_PR_PM_Pos) /*!< TIMER2 PR: PM Mask */\r
-\r
-// ---------------------------------------- TIMER2_PC -------------------------------------------\r
-#define TIMER2_PC_PC_Pos 0 /*!< TIMER2 PC: PC Position */\r
-#define TIMER2_PC_PC_Msk (0xffffffffUL << TIMER2_PC_PC_Pos) /*!< TIMER2 PC: PC Mask */\r
-\r
-// --------------------------------------- TIMER2_MCR -------------------------------------------\r
-#define TIMER2_MCR_MR0I_Pos 0 /*!< TIMER2 MCR: MR0I Position */\r
-#define TIMER2_MCR_MR0I_Msk (0x01UL << TIMER2_MCR_MR0I_Pos) /*!< TIMER2 MCR: MR0I Mask */\r
-#define TIMER2_MCR_MR0R_Pos 1 /*!< TIMER2 MCR: MR0R Position */\r
-#define TIMER2_MCR_MR0R_Msk (0x01UL << TIMER2_MCR_MR0R_Pos) /*!< TIMER2 MCR: MR0R Mask */\r
-#define TIMER2_MCR_MR0S_Pos 2 /*!< TIMER2 MCR: MR0S Position */\r
-#define TIMER2_MCR_MR0S_Msk (0x01UL << TIMER2_MCR_MR0S_Pos) /*!< TIMER2 MCR: MR0S Mask */\r
-#define TIMER2_MCR_MR1I_Pos 3 /*!< TIMER2 MCR: MR1I Position */\r
-#define TIMER2_MCR_MR1I_Msk (0x01UL << TIMER2_MCR_MR1I_Pos) /*!< TIMER2 MCR: MR1I Mask */\r
-#define TIMER2_MCR_MR1R_Pos 4 /*!< TIMER2 MCR: MR1R Position */\r
-#define TIMER2_MCR_MR1R_Msk (0x01UL << TIMER2_MCR_MR1R_Pos) /*!< TIMER2 MCR: MR1R Mask */\r
-#define TIMER2_MCR_MR1S_Pos 5 /*!< TIMER2 MCR: MR1S Position */\r
-#define TIMER2_MCR_MR1S_Msk (0x01UL << TIMER2_MCR_MR1S_Pos) /*!< TIMER2 MCR: MR1S Mask */\r
-#define TIMER2_MCR_MR2I_Pos 6 /*!< TIMER2 MCR: MR2I Position */\r
-#define TIMER2_MCR_MR2I_Msk (0x01UL << TIMER2_MCR_MR2I_Pos) /*!< TIMER2 MCR: MR2I Mask */\r
-#define TIMER2_MCR_MR2R_Pos 7 /*!< TIMER2 MCR: MR2R Position */\r
-#define TIMER2_MCR_MR2R_Msk (0x01UL << TIMER2_MCR_MR2R_Pos) /*!< TIMER2 MCR: MR2R Mask */\r
-#define TIMER2_MCR_MR2S_Pos 8 /*!< TIMER2 MCR: MR2S Position */\r
-#define TIMER2_MCR_MR2S_Msk (0x01UL << TIMER2_MCR_MR2S_Pos) /*!< TIMER2 MCR: MR2S Mask */\r
-#define TIMER2_MCR_MR3I_Pos 9 /*!< TIMER2 MCR: MR3I Position */\r
-#define TIMER2_MCR_MR3I_Msk (0x01UL << TIMER2_MCR_MR3I_Pos) /*!< TIMER2 MCR: MR3I Mask */\r
-#define TIMER2_MCR_MR3R_Pos 10 /*!< TIMER2 MCR: MR3R Position */\r
-#define TIMER2_MCR_MR3R_Msk (0x01UL << TIMER2_MCR_MR3R_Pos) /*!< TIMER2 MCR: MR3R Mask */\r
-#define TIMER2_MCR_MR3S_Pos 11 /*!< TIMER2 MCR: MR3S Position */\r
-#define TIMER2_MCR_MR3S_Msk (0x01UL << TIMER2_MCR_MR3S_Pos) /*!< TIMER2 MCR: MR3S Mask */\r
-\r
-// --------------------------------------- TIMER2_MR0 -------------------------------------------\r
-#define TIMER2_MR0_MATCH_Pos 0 /*!< TIMER2 MR0: MATCH Position */\r
-#define TIMER2_MR0_MATCH_Msk (0xffffffffUL << TIMER2_MR0_MATCH_Pos) /*!< TIMER2 MR0: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER2_MR1 -------------------------------------------\r
-#define TIMER2_MR1_MATCH_Pos 0 /*!< TIMER2 MR1: MATCH Position */\r
-#define TIMER2_MR1_MATCH_Msk (0xffffffffUL << TIMER2_MR1_MATCH_Pos) /*!< TIMER2 MR1: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER2_MR2 -------------------------------------------\r
-#define TIMER2_MR2_MATCH_Pos 0 /*!< TIMER2 MR2: MATCH Position */\r
-#define TIMER2_MR2_MATCH_Msk (0xffffffffUL << TIMER2_MR2_MATCH_Pos) /*!< TIMER2 MR2: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER2_MR3 -------------------------------------------\r
-#define TIMER2_MR3_MATCH_Pos 0 /*!< TIMER2 MR3: MATCH Position */\r
-#define TIMER2_MR3_MATCH_Msk (0xffffffffUL << TIMER2_MR3_MATCH_Pos) /*!< TIMER2 MR3: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER2_CCR -------------------------------------------\r
-#define TIMER2_CCR_CAP0RE_Pos 0 /*!< TIMER2 CCR: CAP0RE Position */\r
-#define TIMER2_CCR_CAP0RE_Msk (0x01UL << TIMER2_CCR_CAP0RE_Pos) /*!< TIMER2 CCR: CAP0RE Mask */\r
-#define TIMER2_CCR_CAP0FE_Pos 1 /*!< TIMER2 CCR: CAP0FE Position */\r
-#define TIMER2_CCR_CAP0FE_Msk (0x01UL << TIMER2_CCR_CAP0FE_Pos) /*!< TIMER2 CCR: CAP0FE Mask */\r
-#define TIMER2_CCR_CAP0I_Pos 2 /*!< TIMER2 CCR: CAP0I Position */\r
-#define TIMER2_CCR_CAP0I_Msk (0x01UL << TIMER2_CCR_CAP0I_Pos) /*!< TIMER2 CCR: CAP0I Mask */\r
-#define TIMER2_CCR_CAP1RE_Pos 3 /*!< TIMER2 CCR: CAP1RE Position */\r
-#define TIMER2_CCR_CAP1RE_Msk (0x01UL << TIMER2_CCR_CAP1RE_Pos) /*!< TIMER2 CCR: CAP1RE Mask */\r
-#define TIMER2_CCR_CAP1FE_Pos 4 /*!< TIMER2 CCR: CAP1FE Position */\r
-#define TIMER2_CCR_CAP1FE_Msk (0x01UL << TIMER2_CCR_CAP1FE_Pos) /*!< TIMER2 CCR: CAP1FE Mask */\r
-#define TIMER2_CCR_CAP1I_Pos 5 /*!< TIMER2 CCR: CAP1I Position */\r
-#define TIMER2_CCR_CAP1I_Msk (0x01UL << TIMER2_CCR_CAP1I_Pos) /*!< TIMER2 CCR: CAP1I Mask */\r
-#define TIMER2_CCR_CAP2RE_Pos 6 /*!< TIMER2 CCR: CAP2RE Position */\r
-#define TIMER2_CCR_CAP2RE_Msk (0x01UL << TIMER2_CCR_CAP2RE_Pos) /*!< TIMER2 CCR: CAP2RE Mask */\r
-#define TIMER2_CCR_CAP2FE_Pos 7 /*!< TIMER2 CCR: CAP2FE Position */\r
-#define TIMER2_CCR_CAP2FE_Msk (0x01UL << TIMER2_CCR_CAP2FE_Pos) /*!< TIMER2 CCR: CAP2FE Mask */\r
-#define TIMER2_CCR_CAP2I_Pos 8 /*!< TIMER2 CCR: CAP2I Position */\r
-#define TIMER2_CCR_CAP2I_Msk (0x01UL << TIMER2_CCR_CAP2I_Pos) /*!< TIMER2 CCR: CAP2I Mask */\r
-#define TIMER2_CCR_CAP3RE_Pos 9 /*!< TIMER2 CCR: CAP3RE Position */\r
-#define TIMER2_CCR_CAP3RE_Msk (0x01UL << TIMER2_CCR_CAP3RE_Pos) /*!< TIMER2 CCR: CAP3RE Mask */\r
-#define TIMER2_CCR_CAP3FE_Pos 10 /*!< TIMER2 CCR: CAP3FE Position */\r
-#define TIMER2_CCR_CAP3FE_Msk (0x01UL << TIMER2_CCR_CAP3FE_Pos) /*!< TIMER2 CCR: CAP3FE Mask */\r
-#define TIMER2_CCR_CAP3I_Pos 11 /*!< TIMER2 CCR: CAP3I Position */\r
-#define TIMER2_CCR_CAP3I_Msk (0x01UL << TIMER2_CCR_CAP3I_Pos) /*!< TIMER2 CCR: CAP3I Mask */\r
-\r
-// --------------------------------------- TIMER2_CR0 -------------------------------------------\r
-#define TIMER2_CR0_CAP_Pos 0 /*!< TIMER2 CR0: CAP Position */\r
-#define TIMER2_CR0_CAP_Msk (0xffffffffUL << TIMER2_CR0_CAP_Pos) /*!< TIMER2 CR0: CAP Mask */\r
-\r
-// --------------------------------------- TIMER2_CR1 -------------------------------------------\r
-#define TIMER2_CR1_CAP_Pos 0 /*!< TIMER2 CR1: CAP Position */\r
-#define TIMER2_CR1_CAP_Msk (0xffffffffUL << TIMER2_CR1_CAP_Pos) /*!< TIMER2 CR1: CAP Mask */\r
-\r
-// --------------------------------------- TIMER2_CR2 -------------------------------------------\r
-#define TIMER2_CR2_CAP_Pos 0 /*!< TIMER2 CR2: CAP Position */\r
-#define TIMER2_CR2_CAP_Msk (0xffffffffUL << TIMER2_CR2_CAP_Pos) /*!< TIMER2 CR2: CAP Mask */\r
-\r
-// --------------------------------------- TIMER2_CR3 -------------------------------------------\r
-#define TIMER2_CR3_CAP_Pos 0 /*!< TIMER2 CR3: CAP Position */\r
-#define TIMER2_CR3_CAP_Msk (0xffffffffUL << TIMER2_CR3_CAP_Pos) /*!< TIMER2 CR3: CAP Mask */\r
-\r
-// --------------------------------------- TIMER2_EMR -------------------------------------------\r
-#define TIMER2_EMR_EM0_Pos 0 /*!< TIMER2 EMR: EM0 Position */\r
-#define TIMER2_EMR_EM0_Msk (0x01UL << TIMER2_EMR_EM0_Pos) /*!< TIMER2 EMR: EM0 Mask */\r
-#define TIMER2_EMR_EM1_Pos 1 /*!< TIMER2 EMR: EM1 Position */\r
-#define TIMER2_EMR_EM1_Msk (0x01UL << TIMER2_EMR_EM1_Pos) /*!< TIMER2 EMR: EM1 Mask */\r
-#define TIMER2_EMR_EM2_Pos 2 /*!< TIMER2 EMR: EM2 Position */\r
-#define TIMER2_EMR_EM2_Msk (0x01UL << TIMER2_EMR_EM2_Pos) /*!< TIMER2 EMR: EM2 Mask */\r
-#define TIMER2_EMR_EM3_Pos 3 /*!< TIMER2 EMR: EM3 Position */\r
-#define TIMER2_EMR_EM3_Msk (0x01UL << TIMER2_EMR_EM3_Pos) /*!< TIMER2 EMR: EM3 Mask */\r
-#define TIMER2_EMR_EMC0_Pos 4 /*!< TIMER2 EMR: EMC0 Position */\r
-#define TIMER2_EMR_EMC0_Msk (0x03UL << TIMER2_EMR_EMC0_Pos) /*!< TIMER2 EMR: EMC0 Mask */\r
-#define TIMER2_EMR_EMC1_Pos 6 /*!< TIMER2 EMR: EMC1 Position */\r
-#define TIMER2_EMR_EMC1_Msk (0x03UL << TIMER2_EMR_EMC1_Pos) /*!< TIMER2 EMR: EMC1 Mask */\r
-#define TIMER2_EMR_EMC2_Pos 8 /*!< TIMER2 EMR: EMC2 Position */\r
-#define TIMER2_EMR_EMC2_Msk (0x03UL << TIMER2_EMR_EMC2_Pos) /*!< TIMER2 EMR: EMC2 Mask */\r
-#define TIMER2_EMR_EMC3_Pos 10 /*!< TIMER2 EMR: EMC3 Position */\r
-#define TIMER2_EMR_EMC3_Msk (0x03UL << TIMER2_EMR_EMC3_Pos) /*!< TIMER2 EMR: EMC3 Mask */\r
-\r
-// --------------------------------------- TIMER2_CTCR ------------------------------------------\r
-#define TIMER2_CTCR_CTMODE_Pos 0 /*!< TIMER2 CTCR: CTMODE Position */\r
-#define TIMER2_CTCR_CTMODE_Msk (0x03UL << TIMER2_CTCR_CTMODE_Pos) /*!< TIMER2 CTCR: CTMODE Mask */\r
-#define TIMER2_CTCR_CINSEL_Pos 2 /*!< TIMER2 CTCR: CINSEL Position */\r
-#define TIMER2_CTCR_CINSEL_Msk (0x03UL << TIMER2_CTCR_CINSEL_Pos) /*!< TIMER2 CTCR: CINSEL Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- TIMER3 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- TIMER3_IR -------------------------------------------\r
-#define TIMER3_IR_MR0INT_Pos 0 /*!< TIMER3 IR: MR0INT Position */\r
-#define TIMER3_IR_MR0INT_Msk (0x01UL << TIMER3_IR_MR0INT_Pos) /*!< TIMER3 IR: MR0INT Mask */\r
-#define TIMER3_IR_MR1INT_Pos 1 /*!< TIMER3 IR: MR1INT Position */\r
-#define TIMER3_IR_MR1INT_Msk (0x01UL << TIMER3_IR_MR1INT_Pos) /*!< TIMER3 IR: MR1INT Mask */\r
-#define TIMER3_IR_MR2INT_Pos 2 /*!< TIMER3 IR: MR2INT Position */\r
-#define TIMER3_IR_MR2INT_Msk (0x01UL << TIMER3_IR_MR2INT_Pos) /*!< TIMER3 IR: MR2INT Mask */\r
-#define TIMER3_IR_MR3INT_Pos 3 /*!< TIMER3 IR: MR3INT Position */\r
-#define TIMER3_IR_MR3INT_Msk (0x01UL << TIMER3_IR_MR3INT_Pos) /*!< TIMER3 IR: MR3INT Mask */\r
-#define TIMER3_IR_CR0INT_Pos 4 /*!< TIMER3 IR: CR0INT Position */\r
-#define TIMER3_IR_CR0INT_Msk (0x01UL << TIMER3_IR_CR0INT_Pos) /*!< TIMER3 IR: CR0INT Mask */\r
-#define TIMER3_IR_CR1INT_Pos 5 /*!< TIMER3 IR: CR1INT Position */\r
-#define TIMER3_IR_CR1INT_Msk (0x01UL << TIMER3_IR_CR1INT_Pos) /*!< TIMER3 IR: CR1INT Mask */\r
-#define TIMER3_IR_CR2INT_Pos 6 /*!< TIMER3 IR: CR2INT Position */\r
-#define TIMER3_IR_CR2INT_Msk (0x01UL << TIMER3_IR_CR2INT_Pos) /*!< TIMER3 IR: CR2INT Mask */\r
-#define TIMER3_IR_CR3INT_Pos 7 /*!< TIMER3 IR: CR3INT Position */\r
-#define TIMER3_IR_CR3INT_Msk (0x01UL << TIMER3_IR_CR3INT_Pos) /*!< TIMER3 IR: CR3INT Mask */\r
-\r
-// --------------------------------------- TIMER3_TCR -------------------------------------------\r
-#define TIMER3_TCR_CEN_Pos 0 /*!< TIMER3 TCR: CEN Position */\r
-#define TIMER3_TCR_CEN_Msk (0x01UL << TIMER3_TCR_CEN_Pos) /*!< TIMER3 TCR: CEN Mask */\r
-#define TIMER3_TCR_CRST_Pos 1 /*!< TIMER3 TCR: CRST Position */\r
-#define TIMER3_TCR_CRST_Msk (0x01UL << TIMER3_TCR_CRST_Pos) /*!< TIMER3 TCR: CRST Mask */\r
-\r
-// ---------------------------------------- TIMER3_TC -------------------------------------------\r
-#define TIMER3_TC_TC_Pos 0 /*!< TIMER3 TC: TC Position */\r
-#define TIMER3_TC_TC_Msk (0xffffffffUL << TIMER3_TC_TC_Pos) /*!< TIMER3 TC: TC Mask */\r
-\r
-// ---------------------------------------- TIMER3_PR -------------------------------------------\r
-#define TIMER3_PR_PM_Pos 0 /*!< TIMER3 PR: PM Position */\r
-#define TIMER3_PR_PM_Msk (0xffffffffUL << TIMER3_PR_PM_Pos) /*!< TIMER3 PR: PM Mask */\r
-\r
-// ---------------------------------------- TIMER3_PC -------------------------------------------\r
-#define TIMER3_PC_PC_Pos 0 /*!< TIMER3 PC: PC Position */\r
-#define TIMER3_PC_PC_Msk (0xffffffffUL << TIMER3_PC_PC_Pos) /*!< TIMER3 PC: PC Mask */\r
-\r
-// --------------------------------------- TIMER3_MCR -------------------------------------------\r
-#define TIMER3_MCR_MR0I_Pos 0 /*!< TIMER3 MCR: MR0I Position */\r
-#define TIMER3_MCR_MR0I_Msk (0x01UL << TIMER3_MCR_MR0I_Pos) /*!< TIMER3 MCR: MR0I Mask */\r
-#define TIMER3_MCR_MR0R_Pos 1 /*!< TIMER3 MCR: MR0R Position */\r
-#define TIMER3_MCR_MR0R_Msk (0x01UL << TIMER3_MCR_MR0R_Pos) /*!< TIMER3 MCR: MR0R Mask */\r
-#define TIMER3_MCR_MR0S_Pos 2 /*!< TIMER3 MCR: MR0S Position */\r
-#define TIMER3_MCR_MR0S_Msk (0x01UL << TIMER3_MCR_MR0S_Pos) /*!< TIMER3 MCR: MR0S Mask */\r
-#define TIMER3_MCR_MR1I_Pos 3 /*!< TIMER3 MCR: MR1I Position */\r
-#define TIMER3_MCR_MR1I_Msk (0x01UL << TIMER3_MCR_MR1I_Pos) /*!< TIMER3 MCR: MR1I Mask */\r
-#define TIMER3_MCR_MR1R_Pos 4 /*!< TIMER3 MCR: MR1R Position */\r
-#define TIMER3_MCR_MR1R_Msk (0x01UL << TIMER3_MCR_MR1R_Pos) /*!< TIMER3 MCR: MR1R Mask */\r
-#define TIMER3_MCR_MR1S_Pos 5 /*!< TIMER3 MCR: MR1S Position */\r
-#define TIMER3_MCR_MR1S_Msk (0x01UL << TIMER3_MCR_MR1S_Pos) /*!< TIMER3 MCR: MR1S Mask */\r
-#define TIMER3_MCR_MR2I_Pos 6 /*!< TIMER3 MCR: MR2I Position */\r
-#define TIMER3_MCR_MR2I_Msk (0x01UL << TIMER3_MCR_MR2I_Pos) /*!< TIMER3 MCR: MR2I Mask */\r
-#define TIMER3_MCR_MR2R_Pos 7 /*!< TIMER3 MCR: MR2R Position */\r
-#define TIMER3_MCR_MR2R_Msk (0x01UL << TIMER3_MCR_MR2R_Pos) /*!< TIMER3 MCR: MR2R Mask */\r
-#define TIMER3_MCR_MR2S_Pos 8 /*!< TIMER3 MCR: MR2S Position */\r
-#define TIMER3_MCR_MR2S_Msk (0x01UL << TIMER3_MCR_MR2S_Pos) /*!< TIMER3 MCR: MR2S Mask */\r
-#define TIMER3_MCR_MR3I_Pos 9 /*!< TIMER3 MCR: MR3I Position */\r
-#define TIMER3_MCR_MR3I_Msk (0x01UL << TIMER3_MCR_MR3I_Pos) /*!< TIMER3 MCR: MR3I Mask */\r
-#define TIMER3_MCR_MR3R_Pos 10 /*!< TIMER3 MCR: MR3R Position */\r
-#define TIMER3_MCR_MR3R_Msk (0x01UL << TIMER3_MCR_MR3R_Pos) /*!< TIMER3 MCR: MR3R Mask */\r
-#define TIMER3_MCR_MR3S_Pos 11 /*!< TIMER3 MCR: MR3S Position */\r
-#define TIMER3_MCR_MR3S_Msk (0x01UL << TIMER3_MCR_MR3S_Pos) /*!< TIMER3 MCR: MR3S Mask */\r
-\r
-// --------------------------------------- TIMER3_MR0 -------------------------------------------\r
-#define TIMER3_MR0_MATCH_Pos 0 /*!< TIMER3 MR0: MATCH Position */\r
-#define TIMER3_MR0_MATCH_Msk (0xffffffffUL << TIMER3_MR0_MATCH_Pos) /*!< TIMER3 MR0: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER3_MR1 -------------------------------------------\r
-#define TIMER3_MR1_MATCH_Pos 0 /*!< TIMER3 MR1: MATCH Position */\r
-#define TIMER3_MR1_MATCH_Msk (0xffffffffUL << TIMER3_MR1_MATCH_Pos) /*!< TIMER3 MR1: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER3_MR2 -------------------------------------------\r
-#define TIMER3_MR2_MATCH_Pos 0 /*!< TIMER3 MR2: MATCH Position */\r
-#define TIMER3_MR2_MATCH_Msk (0xffffffffUL << TIMER3_MR2_MATCH_Pos) /*!< TIMER3 MR2: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER3_MR3 -------------------------------------------\r
-#define TIMER3_MR3_MATCH_Pos 0 /*!< TIMER3 MR3: MATCH Position */\r
-#define TIMER3_MR3_MATCH_Msk (0xffffffffUL << TIMER3_MR3_MATCH_Pos) /*!< TIMER3 MR3: MATCH Mask */\r
-\r
-// --------------------------------------- TIMER3_CCR -------------------------------------------\r
-#define TIMER3_CCR_CAP0RE_Pos 0 /*!< TIMER3 CCR: CAP0RE Position */\r
-#define TIMER3_CCR_CAP0RE_Msk (0x01UL << TIMER3_CCR_CAP0RE_Pos) /*!< TIMER3 CCR: CAP0RE Mask */\r
-#define TIMER3_CCR_CAP0FE_Pos 1 /*!< TIMER3 CCR: CAP0FE Position */\r
-#define TIMER3_CCR_CAP0FE_Msk (0x01UL << TIMER3_CCR_CAP0FE_Pos) /*!< TIMER3 CCR: CAP0FE Mask */\r
-#define TIMER3_CCR_CAP0I_Pos 2 /*!< TIMER3 CCR: CAP0I Position */\r
-#define TIMER3_CCR_CAP0I_Msk (0x01UL << TIMER3_CCR_CAP0I_Pos) /*!< TIMER3 CCR: CAP0I Mask */\r
-#define TIMER3_CCR_CAP1RE_Pos 3 /*!< TIMER3 CCR: CAP1RE Position */\r
-#define TIMER3_CCR_CAP1RE_Msk (0x01UL << TIMER3_CCR_CAP1RE_Pos) /*!< TIMER3 CCR: CAP1RE Mask */\r
-#define TIMER3_CCR_CAP1FE_Pos 4 /*!< TIMER3 CCR: CAP1FE Position */\r
-#define TIMER3_CCR_CAP1FE_Msk (0x01UL << TIMER3_CCR_CAP1FE_Pos) /*!< TIMER3 CCR: CAP1FE Mask */\r
-#define TIMER3_CCR_CAP1I_Pos 5 /*!< TIMER3 CCR: CAP1I Position */\r
-#define TIMER3_CCR_CAP1I_Msk (0x01UL << TIMER3_CCR_CAP1I_Pos) /*!< TIMER3 CCR: CAP1I Mask */\r
-#define TIMER3_CCR_CAP2RE_Pos 6 /*!< TIMER3 CCR: CAP2RE Position */\r
-#define TIMER3_CCR_CAP2RE_Msk (0x01UL << TIMER3_CCR_CAP2RE_Pos) /*!< TIMER3 CCR: CAP2RE Mask */\r
-#define TIMER3_CCR_CAP2FE_Pos 7 /*!< TIMER3 CCR: CAP2FE Position */\r
-#define TIMER3_CCR_CAP2FE_Msk (0x01UL << TIMER3_CCR_CAP2FE_Pos) /*!< TIMER3 CCR: CAP2FE Mask */\r
-#define TIMER3_CCR_CAP2I_Pos 8 /*!< TIMER3 CCR: CAP2I Position */\r
-#define TIMER3_CCR_CAP2I_Msk (0x01UL << TIMER3_CCR_CAP2I_Pos) /*!< TIMER3 CCR: CAP2I Mask */\r
-#define TIMER3_CCR_CAP3RE_Pos 9 /*!< TIMER3 CCR: CAP3RE Position */\r
-#define TIMER3_CCR_CAP3RE_Msk (0x01UL << TIMER3_CCR_CAP3RE_Pos) /*!< TIMER3 CCR: CAP3RE Mask */\r
-#define TIMER3_CCR_CAP3FE_Pos 10 /*!< TIMER3 CCR: CAP3FE Position */\r
-#define TIMER3_CCR_CAP3FE_Msk (0x01UL << TIMER3_CCR_CAP3FE_Pos) /*!< TIMER3 CCR: CAP3FE Mask */\r
-#define TIMER3_CCR_CAP3I_Pos 11 /*!< TIMER3 CCR: CAP3I Position */\r
-#define TIMER3_CCR_CAP3I_Msk (0x01UL << TIMER3_CCR_CAP3I_Pos) /*!< TIMER3 CCR: CAP3I Mask */\r
-\r
-// --------------------------------------- TIMER3_CR0 -------------------------------------------\r
-#define TIMER3_CR0_CAP_Pos 0 /*!< TIMER3 CR0: CAP Position */\r
-#define TIMER3_CR0_CAP_Msk (0xffffffffUL << TIMER3_CR0_CAP_Pos) /*!< TIMER3 CR0: CAP Mask */\r
-\r
-// --------------------------------------- TIMER3_CR1 -------------------------------------------\r
-#define TIMER3_CR1_CAP_Pos 0 /*!< TIMER3 CR1: CAP Position */\r
-#define TIMER3_CR1_CAP_Msk (0xffffffffUL << TIMER3_CR1_CAP_Pos) /*!< TIMER3 CR1: CAP Mask */\r
-\r
-// --------------------------------------- TIMER3_CR2 -------------------------------------------\r
-#define TIMER3_CR2_CAP_Pos 0 /*!< TIMER3 CR2: CAP Position */\r
-#define TIMER3_CR2_CAP_Msk (0xffffffffUL << TIMER3_CR2_CAP_Pos) /*!< TIMER3 CR2: CAP Mask */\r
-\r
-// --------------------------------------- TIMER3_CR3 -------------------------------------------\r
-#define TIMER3_CR3_CAP_Pos 0 /*!< TIMER3 CR3: CAP Position */\r
-#define TIMER3_CR3_CAP_Msk (0xffffffffUL << TIMER3_CR3_CAP_Pos) /*!< TIMER3 CR3: CAP Mask */\r
-\r
-// --------------------------------------- TIMER3_EMR -------------------------------------------\r
-#define TIMER3_EMR_EM0_Pos 0 /*!< TIMER3 EMR: EM0 Position */\r
-#define TIMER3_EMR_EM0_Msk (0x01UL << TIMER3_EMR_EM0_Pos) /*!< TIMER3 EMR: EM0 Mask */\r
-#define TIMER3_EMR_EM1_Pos 1 /*!< TIMER3 EMR: EM1 Position */\r
-#define TIMER3_EMR_EM1_Msk (0x01UL << TIMER3_EMR_EM1_Pos) /*!< TIMER3 EMR: EM1 Mask */\r
-#define TIMER3_EMR_EM2_Pos 2 /*!< TIMER3 EMR: EM2 Position */\r
-#define TIMER3_EMR_EM2_Msk (0x01UL << TIMER3_EMR_EM2_Pos) /*!< TIMER3 EMR: EM2 Mask */\r
-#define TIMER3_EMR_EM3_Pos 3 /*!< TIMER3 EMR: EM3 Position */\r
-#define TIMER3_EMR_EM3_Msk (0x01UL << TIMER3_EMR_EM3_Pos) /*!< TIMER3 EMR: EM3 Mask */\r
-#define TIMER3_EMR_EMC0_Pos 4 /*!< TIMER3 EMR: EMC0 Position */\r
-#define TIMER3_EMR_EMC0_Msk (0x03UL << TIMER3_EMR_EMC0_Pos) /*!< TIMER3 EMR: EMC0 Mask */\r
-#define TIMER3_EMR_EMC1_Pos 6 /*!< TIMER3 EMR: EMC1 Position */\r
-#define TIMER3_EMR_EMC1_Msk (0x03UL << TIMER3_EMR_EMC1_Pos) /*!< TIMER3 EMR: EMC1 Mask */\r
-#define TIMER3_EMR_EMC2_Pos 8 /*!< TIMER3 EMR: EMC2 Position */\r
-#define TIMER3_EMR_EMC2_Msk (0x03UL << TIMER3_EMR_EMC2_Pos) /*!< TIMER3 EMR: EMC2 Mask */\r
-#define TIMER3_EMR_EMC3_Pos 10 /*!< TIMER3 EMR: EMC3 Position */\r
-#define TIMER3_EMR_EMC3_Msk (0x03UL << TIMER3_EMR_EMC3_Pos) /*!< TIMER3 EMR: EMC3 Mask */\r
-\r
-// --------------------------------------- TIMER3_CTCR ------------------------------------------\r
-#define TIMER3_CTCR_CTMODE_Pos 0 /*!< TIMER3 CTCR: CTMODE Position */\r
-#define TIMER3_CTCR_CTMODE_Msk (0x03UL << TIMER3_CTCR_CTMODE_Pos) /*!< TIMER3 CTCR: CTMODE Mask */\r
-#define TIMER3_CTCR_CINSEL_Pos 2 /*!< TIMER3 CTCR: CINSEL Position */\r
-#define TIMER3_CTCR_CINSEL_Msk (0x03UL << TIMER3_CTCR_CINSEL_Pos) /*!< TIMER3 CTCR: CINSEL Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- SCU Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- SCU_SFSP0_0 ------------------------------------------\r
-#define SCU_SFSP0_0_MODE_Pos 0 /*!< SCU SFSP0_0: MODE Position */\r
-#define SCU_SFSP0_0_MODE_Msk (0x07UL << SCU_SFSP0_0_MODE_Pos) /*!< SCU SFSP0_0: MODE Mask */\r
-#define SCU_SFSP0_0_EPD_Pos 3 /*!< SCU SFSP0_0: EPD Position */\r
-#define SCU_SFSP0_0_EPD_Msk (0x01UL << SCU_SFSP0_0_EPD_Pos) /*!< SCU SFSP0_0: EPD Mask */\r
-#define SCU_SFSP0_0_EPUN_Pos 4 /*!< SCU SFSP0_0: EPUN Position */\r
-#define SCU_SFSP0_0_EPUN_Msk (0x01UL << SCU_SFSP0_0_EPUN_Pos) /*!< SCU SFSP0_0: EPUN Mask */\r
-#define SCU_SFSP0_0_EHS_Pos 5 /*!< SCU SFSP0_0: EHS Position */\r
-#define SCU_SFSP0_0_EHS_Msk (0x01UL << SCU_SFSP0_0_EHS_Pos) /*!< SCU SFSP0_0: EHS Mask */\r
-#define SCU_SFSP0_0_EZI_Pos 6 /*!< SCU SFSP0_0: EZI Position */\r
-#define SCU_SFSP0_0_EZI_Msk (0x01UL << SCU_SFSP0_0_EZI_Pos) /*!< SCU SFSP0_0: EZI Mask */\r
-\r
-// --------------------------------------- SCU_SFSP0_1 ------------------------------------------\r
-#define SCU_SFSP0_1_MODE_Pos 0 /*!< SCU SFSP0_1: MODE Position */\r
-#define SCU_SFSP0_1_MODE_Msk (0x07UL << SCU_SFSP0_1_MODE_Pos) /*!< SCU SFSP0_1: MODE Mask */\r
-#define SCU_SFSP0_1_EPD_Pos 3 /*!< SCU SFSP0_1: EPD Position */\r
-#define SCU_SFSP0_1_EPD_Msk (0x01UL << SCU_SFSP0_1_EPD_Pos) /*!< SCU SFSP0_1: EPD Mask */\r
-#define SCU_SFSP0_1_EPUN_Pos 4 /*!< SCU SFSP0_1: EPUN Position */\r
-#define SCU_SFSP0_1_EPUN_Msk (0x01UL << SCU_SFSP0_1_EPUN_Pos) /*!< SCU SFSP0_1: EPUN Mask */\r
-#define SCU_SFSP0_1_EHS_Pos 5 /*!< SCU SFSP0_1: EHS Position */\r
-#define SCU_SFSP0_1_EHS_Msk (0x01UL << SCU_SFSP0_1_EHS_Pos) /*!< SCU SFSP0_1: EHS Mask */\r
-#define SCU_SFSP0_1_EZI_Pos 6 /*!< SCU SFSP0_1: EZI Position */\r
-#define SCU_SFSP0_1_EZI_Msk (0x01UL << SCU_SFSP0_1_EZI_Pos) /*!< SCU SFSP0_1: EZI Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_0 ------------------------------------------\r
-#define SCU_SFSP1_0_MODE_Pos 0 /*!< SCU SFSP1_0: MODE Position */\r
-#define SCU_SFSP1_0_MODE_Msk (0x07UL << SCU_SFSP1_0_MODE_Pos) /*!< SCU SFSP1_0: MODE Mask */\r
-#define SCU_SFSP1_0_EPD_Pos 3 /*!< SCU SFSP1_0: EPD Position */\r
-#define SCU_SFSP1_0_EPD_Msk (0x01UL << SCU_SFSP1_0_EPD_Pos) /*!< SCU SFSP1_0: EPD Mask */\r
-#define SCU_SFSP1_0_EPUN_Pos 4 /*!< SCU SFSP1_0: EPUN Position */\r
-#define SCU_SFSP1_0_EPUN_Msk (0x01UL << SCU_SFSP1_0_EPUN_Pos) /*!< SCU SFSP1_0: EPUN Mask */\r
-#define SCU_SFSP1_0_EHS_Pos 5 /*!< SCU SFSP1_0: EHS Position */\r
-#define SCU_SFSP1_0_EHS_Msk (0x01UL << SCU_SFSP1_0_EHS_Pos) /*!< SCU SFSP1_0: EHS Mask */\r
-#define SCU_SFSP1_0_EZI_Pos 6 /*!< SCU SFSP1_0: EZI Position */\r
-#define SCU_SFSP1_0_EZI_Msk (0x01UL << SCU_SFSP1_0_EZI_Pos) /*!< SCU SFSP1_0: EZI Mask */\r
-#define SCU_SFSP1_0_EHD_Pos 8 /*!< SCU SFSP1_0: EHD Position */\r
-#define SCU_SFSP1_0_EHD_Msk (0x03UL << SCU_SFSP1_0_EHD_Pos) /*!< SCU SFSP1_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_1 ------------------------------------------\r
-#define SCU_SFSP1_1_MODE_Pos 0 /*!< SCU SFSP1_1: MODE Position */\r
-#define SCU_SFSP1_1_MODE_Msk (0x07UL << SCU_SFSP1_1_MODE_Pos) /*!< SCU SFSP1_1: MODE Mask */\r
-#define SCU_SFSP1_1_EPD_Pos 3 /*!< SCU SFSP1_1: EPD Position */\r
-#define SCU_SFSP1_1_EPD_Msk (0x01UL << SCU_SFSP1_1_EPD_Pos) /*!< SCU SFSP1_1: EPD Mask */\r
-#define SCU_SFSP1_1_EPUN_Pos 4 /*!< SCU SFSP1_1: EPUN Position */\r
-#define SCU_SFSP1_1_EPUN_Msk (0x01UL << SCU_SFSP1_1_EPUN_Pos) /*!< SCU SFSP1_1: EPUN Mask */\r
-#define SCU_SFSP1_1_EHS_Pos 5 /*!< SCU SFSP1_1: EHS Position */\r
-#define SCU_SFSP1_1_EHS_Msk (0x01UL << SCU_SFSP1_1_EHS_Pos) /*!< SCU SFSP1_1: EHS Mask */\r
-#define SCU_SFSP1_1_EZI_Pos 6 /*!< SCU SFSP1_1: EZI Position */\r
-#define SCU_SFSP1_1_EZI_Msk (0x01UL << SCU_SFSP1_1_EZI_Pos) /*!< SCU SFSP1_1: EZI Mask */\r
-#define SCU_SFSP1_1_EHD_Pos 8 /*!< SCU SFSP1_1: EHD Position */\r
-#define SCU_SFSP1_1_EHD_Msk (0x03UL << SCU_SFSP1_1_EHD_Pos) /*!< SCU SFSP1_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_2 ------------------------------------------\r
-#define SCU_SFSP1_2_MODE_Pos 0 /*!< SCU SFSP1_2: MODE Position */\r
-#define SCU_SFSP1_2_MODE_Msk (0x07UL << SCU_SFSP1_2_MODE_Pos) /*!< SCU SFSP1_2: MODE Mask */\r
-#define SCU_SFSP1_2_EPD_Pos 3 /*!< SCU SFSP1_2: EPD Position */\r
-#define SCU_SFSP1_2_EPD_Msk (0x01UL << SCU_SFSP1_2_EPD_Pos) /*!< SCU SFSP1_2: EPD Mask */\r
-#define SCU_SFSP1_2_EPUN_Pos 4 /*!< SCU SFSP1_2: EPUN Position */\r
-#define SCU_SFSP1_2_EPUN_Msk (0x01UL << SCU_SFSP1_2_EPUN_Pos) /*!< SCU SFSP1_2: EPUN Mask */\r
-#define SCU_SFSP1_2_EHS_Pos 5 /*!< SCU SFSP1_2: EHS Position */\r
-#define SCU_SFSP1_2_EHS_Msk (0x01UL << SCU_SFSP1_2_EHS_Pos) /*!< SCU SFSP1_2: EHS Mask */\r
-#define SCU_SFSP1_2_EZI_Pos 6 /*!< SCU SFSP1_2: EZI Position */\r
-#define SCU_SFSP1_2_EZI_Msk (0x01UL << SCU_SFSP1_2_EZI_Pos) /*!< SCU SFSP1_2: EZI Mask */\r
-#define SCU_SFSP1_2_EHD_Pos 8 /*!< SCU SFSP1_2: EHD Position */\r
-#define SCU_SFSP1_2_EHD_Msk (0x03UL << SCU_SFSP1_2_EHD_Pos) /*!< SCU SFSP1_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_3 ------------------------------------------\r
-#define SCU_SFSP1_3_MODE_Pos 0 /*!< SCU SFSP1_3: MODE Position */\r
-#define SCU_SFSP1_3_MODE_Msk (0x07UL << SCU_SFSP1_3_MODE_Pos) /*!< SCU SFSP1_3: MODE Mask */\r
-#define SCU_SFSP1_3_EPD_Pos 3 /*!< SCU SFSP1_3: EPD Position */\r
-#define SCU_SFSP1_3_EPD_Msk (0x01UL << SCU_SFSP1_3_EPD_Pos) /*!< SCU SFSP1_3: EPD Mask */\r
-#define SCU_SFSP1_3_EPUN_Pos 4 /*!< SCU SFSP1_3: EPUN Position */\r
-#define SCU_SFSP1_3_EPUN_Msk (0x01UL << SCU_SFSP1_3_EPUN_Pos) /*!< SCU SFSP1_3: EPUN Mask */\r
-#define SCU_SFSP1_3_EHS_Pos 5 /*!< SCU SFSP1_3: EHS Position */\r
-#define SCU_SFSP1_3_EHS_Msk (0x01UL << SCU_SFSP1_3_EHS_Pos) /*!< SCU SFSP1_3: EHS Mask */\r
-#define SCU_SFSP1_3_EZI_Pos 6 /*!< SCU SFSP1_3: EZI Position */\r
-#define SCU_SFSP1_3_EZI_Msk (0x01UL << SCU_SFSP1_3_EZI_Pos) /*!< SCU SFSP1_3: EZI Mask */\r
-#define SCU_SFSP1_3_EHD_Pos 8 /*!< SCU SFSP1_3: EHD Position */\r
-#define SCU_SFSP1_3_EHD_Msk (0x03UL << SCU_SFSP1_3_EHD_Pos) /*!< SCU SFSP1_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_4 ------------------------------------------\r
-#define SCU_SFSP1_4_MODE_Pos 0 /*!< SCU SFSP1_4: MODE Position */\r
-#define SCU_SFSP1_4_MODE_Msk (0x07UL << SCU_SFSP1_4_MODE_Pos) /*!< SCU SFSP1_4: MODE Mask */\r
-#define SCU_SFSP1_4_EPD_Pos 3 /*!< SCU SFSP1_4: EPD Position */\r
-#define SCU_SFSP1_4_EPD_Msk (0x01UL << SCU_SFSP1_4_EPD_Pos) /*!< SCU SFSP1_4: EPD Mask */\r
-#define SCU_SFSP1_4_EPUN_Pos 4 /*!< SCU SFSP1_4: EPUN Position */\r
-#define SCU_SFSP1_4_EPUN_Msk (0x01UL << SCU_SFSP1_4_EPUN_Pos) /*!< SCU SFSP1_4: EPUN Mask */\r
-#define SCU_SFSP1_4_EHS_Pos 5 /*!< SCU SFSP1_4: EHS Position */\r
-#define SCU_SFSP1_4_EHS_Msk (0x01UL << SCU_SFSP1_4_EHS_Pos) /*!< SCU SFSP1_4: EHS Mask */\r
-#define SCU_SFSP1_4_EZI_Pos 6 /*!< SCU SFSP1_4: EZI Position */\r
-#define SCU_SFSP1_4_EZI_Msk (0x01UL << SCU_SFSP1_4_EZI_Pos) /*!< SCU SFSP1_4: EZI Mask */\r
-#define SCU_SFSP1_4_EHD_Pos 8 /*!< SCU SFSP1_4: EHD Position */\r
-#define SCU_SFSP1_4_EHD_Msk (0x03UL << SCU_SFSP1_4_EHD_Pos) /*!< SCU SFSP1_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_5 ------------------------------------------\r
-#define SCU_SFSP1_5_MODE_Pos 0 /*!< SCU SFSP1_5: MODE Position */\r
-#define SCU_SFSP1_5_MODE_Msk (0x07UL << SCU_SFSP1_5_MODE_Pos) /*!< SCU SFSP1_5: MODE Mask */\r
-#define SCU_SFSP1_5_EPD_Pos 3 /*!< SCU SFSP1_5: EPD Position */\r
-#define SCU_SFSP1_5_EPD_Msk (0x01UL << SCU_SFSP1_5_EPD_Pos) /*!< SCU SFSP1_5: EPD Mask */\r
-#define SCU_SFSP1_5_EPUN_Pos 4 /*!< SCU SFSP1_5: EPUN Position */\r
-#define SCU_SFSP1_5_EPUN_Msk (0x01UL << SCU_SFSP1_5_EPUN_Pos) /*!< SCU SFSP1_5: EPUN Mask */\r
-#define SCU_SFSP1_5_EHS_Pos 5 /*!< SCU SFSP1_5: EHS Position */\r
-#define SCU_SFSP1_5_EHS_Msk (0x01UL << SCU_SFSP1_5_EHS_Pos) /*!< SCU SFSP1_5: EHS Mask */\r
-#define SCU_SFSP1_5_EZI_Pos 6 /*!< SCU SFSP1_5: EZI Position */\r
-#define SCU_SFSP1_5_EZI_Msk (0x01UL << SCU_SFSP1_5_EZI_Pos) /*!< SCU SFSP1_5: EZI Mask */\r
-#define SCU_SFSP1_5_EHD_Pos 8 /*!< SCU SFSP1_5: EHD Position */\r
-#define SCU_SFSP1_5_EHD_Msk (0x03UL << SCU_SFSP1_5_EHD_Pos) /*!< SCU SFSP1_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_6 ------------------------------------------\r
-#define SCU_SFSP1_6_MODE_Pos 0 /*!< SCU SFSP1_6: MODE Position */\r
-#define SCU_SFSP1_6_MODE_Msk (0x07UL << SCU_SFSP1_6_MODE_Pos) /*!< SCU SFSP1_6: MODE Mask */\r
-#define SCU_SFSP1_6_EPD_Pos 3 /*!< SCU SFSP1_6: EPD Position */\r
-#define SCU_SFSP1_6_EPD_Msk (0x01UL << SCU_SFSP1_6_EPD_Pos) /*!< SCU SFSP1_6: EPD Mask */\r
-#define SCU_SFSP1_6_EPUN_Pos 4 /*!< SCU SFSP1_6: EPUN Position */\r
-#define SCU_SFSP1_6_EPUN_Msk (0x01UL << SCU_SFSP1_6_EPUN_Pos) /*!< SCU SFSP1_6: EPUN Mask */\r
-#define SCU_SFSP1_6_EHS_Pos 5 /*!< SCU SFSP1_6: EHS Position */\r
-#define SCU_SFSP1_6_EHS_Msk (0x01UL << SCU_SFSP1_6_EHS_Pos) /*!< SCU SFSP1_6: EHS Mask */\r
-#define SCU_SFSP1_6_EZI_Pos 6 /*!< SCU SFSP1_6: EZI Position */\r
-#define SCU_SFSP1_6_EZI_Msk (0x01UL << SCU_SFSP1_6_EZI_Pos) /*!< SCU SFSP1_6: EZI Mask */\r
-#define SCU_SFSP1_6_EHD_Pos 8 /*!< SCU SFSP1_6: EHD Position */\r
-#define SCU_SFSP1_6_EHD_Msk (0x03UL << SCU_SFSP1_6_EHD_Pos) /*!< SCU SFSP1_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_7 ------------------------------------------\r
-#define SCU_SFSP1_7_MODE_Pos 0 /*!< SCU SFSP1_7: MODE Position */\r
-#define SCU_SFSP1_7_MODE_Msk (0x07UL << SCU_SFSP1_7_MODE_Pos) /*!< SCU SFSP1_7: MODE Mask */\r
-#define SCU_SFSP1_7_EPD_Pos 3 /*!< SCU SFSP1_7: EPD Position */\r
-#define SCU_SFSP1_7_EPD_Msk (0x01UL << SCU_SFSP1_7_EPD_Pos) /*!< SCU SFSP1_7: EPD Mask */\r
-#define SCU_SFSP1_7_EPUN_Pos 4 /*!< SCU SFSP1_7: EPUN Position */\r
-#define SCU_SFSP1_7_EPUN_Msk (0x01UL << SCU_SFSP1_7_EPUN_Pos) /*!< SCU SFSP1_7: EPUN Mask */\r
-#define SCU_SFSP1_7_EHS_Pos 5 /*!< SCU SFSP1_7: EHS Position */\r
-#define SCU_SFSP1_7_EHS_Msk (0x01UL << SCU_SFSP1_7_EHS_Pos) /*!< SCU SFSP1_7: EHS Mask */\r
-#define SCU_SFSP1_7_EZI_Pos 6 /*!< SCU SFSP1_7: EZI Position */\r
-#define SCU_SFSP1_7_EZI_Msk (0x01UL << SCU_SFSP1_7_EZI_Pos) /*!< SCU SFSP1_7: EZI Mask */\r
-#define SCU_SFSP1_7_EHD_Pos 8 /*!< SCU SFSP1_7: EHD Position */\r
-#define SCU_SFSP1_7_EHD_Msk (0x03UL << SCU_SFSP1_7_EHD_Pos) /*!< SCU SFSP1_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_8 ------------------------------------------\r
-#define SCU_SFSP1_8_MODE_Pos 0 /*!< SCU SFSP1_8: MODE Position */\r
-#define SCU_SFSP1_8_MODE_Msk (0x07UL << SCU_SFSP1_8_MODE_Pos) /*!< SCU SFSP1_8: MODE Mask */\r
-#define SCU_SFSP1_8_EPD_Pos 3 /*!< SCU SFSP1_8: EPD Position */\r
-#define SCU_SFSP1_8_EPD_Msk (0x01UL << SCU_SFSP1_8_EPD_Pos) /*!< SCU SFSP1_8: EPD Mask */\r
-#define SCU_SFSP1_8_EPUN_Pos 4 /*!< SCU SFSP1_8: EPUN Position */\r
-#define SCU_SFSP1_8_EPUN_Msk (0x01UL << SCU_SFSP1_8_EPUN_Pos) /*!< SCU SFSP1_8: EPUN Mask */\r
-#define SCU_SFSP1_8_EHS_Pos 5 /*!< SCU SFSP1_8: EHS Position */\r
-#define SCU_SFSP1_8_EHS_Msk (0x01UL << SCU_SFSP1_8_EHS_Pos) /*!< SCU SFSP1_8: EHS Mask */\r
-#define SCU_SFSP1_8_EZI_Pos 6 /*!< SCU SFSP1_8: EZI Position */\r
-#define SCU_SFSP1_8_EZI_Msk (0x01UL << SCU_SFSP1_8_EZI_Pos) /*!< SCU SFSP1_8: EZI Mask */\r
-#define SCU_SFSP1_8_EHD_Pos 8 /*!< SCU SFSP1_8: EHD Position */\r
-#define SCU_SFSP1_8_EHD_Msk (0x03UL << SCU_SFSP1_8_EHD_Pos) /*!< SCU SFSP1_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP1_9 ------------------------------------------\r
-#define SCU_SFSP1_9_MODE_Pos 0 /*!< SCU SFSP1_9: MODE Position */\r
-#define SCU_SFSP1_9_MODE_Msk (0x07UL << SCU_SFSP1_9_MODE_Pos) /*!< SCU SFSP1_9: MODE Mask */\r
-#define SCU_SFSP1_9_EPD_Pos 3 /*!< SCU SFSP1_9: EPD Position */\r
-#define SCU_SFSP1_9_EPD_Msk (0x01UL << SCU_SFSP1_9_EPD_Pos) /*!< SCU SFSP1_9: EPD Mask */\r
-#define SCU_SFSP1_9_EPUN_Pos 4 /*!< SCU SFSP1_9: EPUN Position */\r
-#define SCU_SFSP1_9_EPUN_Msk (0x01UL << SCU_SFSP1_9_EPUN_Pos) /*!< SCU SFSP1_9: EPUN Mask */\r
-#define SCU_SFSP1_9_EHS_Pos 5 /*!< SCU SFSP1_9: EHS Position */\r
-#define SCU_SFSP1_9_EHS_Msk (0x01UL << SCU_SFSP1_9_EHS_Pos) /*!< SCU SFSP1_9: EHS Mask */\r
-#define SCU_SFSP1_9_EZI_Pos 6 /*!< SCU SFSP1_9: EZI Position */\r
-#define SCU_SFSP1_9_EZI_Msk (0x01UL << SCU_SFSP1_9_EZI_Pos) /*!< SCU SFSP1_9: EZI Mask */\r
-#define SCU_SFSP1_9_EHD_Pos 8 /*!< SCU SFSP1_9: EHD Position */\r
-#define SCU_SFSP1_9_EHD_Msk (0x03UL << SCU_SFSP1_9_EHD_Pos) /*!< SCU SFSP1_9: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_10 ------------------------------------------\r
-#define SCU_SFSP1_10_MODE_Pos 0 /*!< SCU SFSP1_10: MODE Position */\r
-#define SCU_SFSP1_10_MODE_Msk (0x07UL << SCU_SFSP1_10_MODE_Pos) /*!< SCU SFSP1_10: MODE Mask */\r
-#define SCU_SFSP1_10_EPD_Pos 3 /*!< SCU SFSP1_10: EPD Position */\r
-#define SCU_SFSP1_10_EPD_Msk (0x01UL << SCU_SFSP1_10_EPD_Pos) /*!< SCU SFSP1_10: EPD Mask */\r
-#define SCU_SFSP1_10_EPUN_Pos 4 /*!< SCU SFSP1_10: EPUN Position */\r
-#define SCU_SFSP1_10_EPUN_Msk (0x01UL << SCU_SFSP1_10_EPUN_Pos) /*!< SCU SFSP1_10: EPUN Mask */\r
-#define SCU_SFSP1_10_EHS_Pos 5 /*!< SCU SFSP1_10: EHS Position */\r
-#define SCU_SFSP1_10_EHS_Msk (0x01UL << SCU_SFSP1_10_EHS_Pos) /*!< SCU SFSP1_10: EHS Mask */\r
-#define SCU_SFSP1_10_EZI_Pos 6 /*!< SCU SFSP1_10: EZI Position */\r
-#define SCU_SFSP1_10_EZI_Msk (0x01UL << SCU_SFSP1_10_EZI_Pos) /*!< SCU SFSP1_10: EZI Mask */\r
-#define SCU_SFSP1_10_EHD_Pos 8 /*!< SCU SFSP1_10: EHD Position */\r
-#define SCU_SFSP1_10_EHD_Msk (0x03UL << SCU_SFSP1_10_EHD_Pos) /*!< SCU SFSP1_10: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_11 ------------------------------------------\r
-#define SCU_SFSP1_11_MODE_Pos 0 /*!< SCU SFSP1_11: MODE Position */\r
-#define SCU_SFSP1_11_MODE_Msk (0x07UL << SCU_SFSP1_11_MODE_Pos) /*!< SCU SFSP1_11: MODE Mask */\r
-#define SCU_SFSP1_11_EPD_Pos 3 /*!< SCU SFSP1_11: EPD Position */\r
-#define SCU_SFSP1_11_EPD_Msk (0x01UL << SCU_SFSP1_11_EPD_Pos) /*!< SCU SFSP1_11: EPD Mask */\r
-#define SCU_SFSP1_11_EPUN_Pos 4 /*!< SCU SFSP1_11: EPUN Position */\r
-#define SCU_SFSP1_11_EPUN_Msk (0x01UL << SCU_SFSP1_11_EPUN_Pos) /*!< SCU SFSP1_11: EPUN Mask */\r
-#define SCU_SFSP1_11_EHS_Pos 5 /*!< SCU SFSP1_11: EHS Position */\r
-#define SCU_SFSP1_11_EHS_Msk (0x01UL << SCU_SFSP1_11_EHS_Pos) /*!< SCU SFSP1_11: EHS Mask */\r
-#define SCU_SFSP1_11_EZI_Pos 6 /*!< SCU SFSP1_11: EZI Position */\r
-#define SCU_SFSP1_11_EZI_Msk (0x01UL << SCU_SFSP1_11_EZI_Pos) /*!< SCU SFSP1_11: EZI Mask */\r
-#define SCU_SFSP1_11_EHD_Pos 8 /*!< SCU SFSP1_11: EHD Position */\r
-#define SCU_SFSP1_11_EHD_Msk (0x03UL << SCU_SFSP1_11_EHD_Pos) /*!< SCU SFSP1_11: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_12 ------------------------------------------\r
-#define SCU_SFSP1_12_MODE_Pos 0 /*!< SCU SFSP1_12: MODE Position */\r
-#define SCU_SFSP1_12_MODE_Msk (0x07UL << SCU_SFSP1_12_MODE_Pos) /*!< SCU SFSP1_12: MODE Mask */\r
-#define SCU_SFSP1_12_EPD_Pos 3 /*!< SCU SFSP1_12: EPD Position */\r
-#define SCU_SFSP1_12_EPD_Msk (0x01UL << SCU_SFSP1_12_EPD_Pos) /*!< SCU SFSP1_12: EPD Mask */\r
-#define SCU_SFSP1_12_EPUN_Pos 4 /*!< SCU SFSP1_12: EPUN Position */\r
-#define SCU_SFSP1_12_EPUN_Msk (0x01UL << SCU_SFSP1_12_EPUN_Pos) /*!< SCU SFSP1_12: EPUN Mask */\r
-#define SCU_SFSP1_12_EHS_Pos 5 /*!< SCU SFSP1_12: EHS Position */\r
-#define SCU_SFSP1_12_EHS_Msk (0x01UL << SCU_SFSP1_12_EHS_Pos) /*!< SCU SFSP1_12: EHS Mask */\r
-#define SCU_SFSP1_12_EZI_Pos 6 /*!< SCU SFSP1_12: EZI Position */\r
-#define SCU_SFSP1_12_EZI_Msk (0x01UL << SCU_SFSP1_12_EZI_Pos) /*!< SCU SFSP1_12: EZI Mask */\r
-#define SCU_SFSP1_12_EHD_Pos 8 /*!< SCU SFSP1_12: EHD Position */\r
-#define SCU_SFSP1_12_EHD_Msk (0x03UL << SCU_SFSP1_12_EHD_Pos) /*!< SCU SFSP1_12: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_13 ------------------------------------------\r
-#define SCU_SFSP1_13_MODE_Pos 0 /*!< SCU SFSP1_13: MODE Position */\r
-#define SCU_SFSP1_13_MODE_Msk (0x07UL << SCU_SFSP1_13_MODE_Pos) /*!< SCU SFSP1_13: MODE Mask */\r
-#define SCU_SFSP1_13_EPD_Pos 3 /*!< SCU SFSP1_13: EPD Position */\r
-#define SCU_SFSP1_13_EPD_Msk (0x01UL << SCU_SFSP1_13_EPD_Pos) /*!< SCU SFSP1_13: EPD Mask */\r
-#define SCU_SFSP1_13_EPUN_Pos 4 /*!< SCU SFSP1_13: EPUN Position */\r
-#define SCU_SFSP1_13_EPUN_Msk (0x01UL << SCU_SFSP1_13_EPUN_Pos) /*!< SCU SFSP1_13: EPUN Mask */\r
-#define SCU_SFSP1_13_EHS_Pos 5 /*!< SCU SFSP1_13: EHS Position */\r
-#define SCU_SFSP1_13_EHS_Msk (0x01UL << SCU_SFSP1_13_EHS_Pos) /*!< SCU SFSP1_13: EHS Mask */\r
-#define SCU_SFSP1_13_EZI_Pos 6 /*!< SCU SFSP1_13: EZI Position */\r
-#define SCU_SFSP1_13_EZI_Msk (0x01UL << SCU_SFSP1_13_EZI_Pos) /*!< SCU SFSP1_13: EZI Mask */\r
-#define SCU_SFSP1_13_EHD_Pos 8 /*!< SCU SFSP1_13: EHD Position */\r
-#define SCU_SFSP1_13_EHD_Msk (0x03UL << SCU_SFSP1_13_EHD_Pos) /*!< SCU SFSP1_13: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_14 ------------------------------------------\r
-#define SCU_SFSP1_14_MODE_Pos 0 /*!< SCU SFSP1_14: MODE Position */\r
-#define SCU_SFSP1_14_MODE_Msk (0x07UL << SCU_SFSP1_14_MODE_Pos) /*!< SCU SFSP1_14: MODE Mask */\r
-#define SCU_SFSP1_14_EPD_Pos 3 /*!< SCU SFSP1_14: EPD Position */\r
-#define SCU_SFSP1_14_EPD_Msk (0x01UL << SCU_SFSP1_14_EPD_Pos) /*!< SCU SFSP1_14: EPD Mask */\r
-#define SCU_SFSP1_14_EPUN_Pos 4 /*!< SCU SFSP1_14: EPUN Position */\r
-#define SCU_SFSP1_14_EPUN_Msk (0x01UL << SCU_SFSP1_14_EPUN_Pos) /*!< SCU SFSP1_14: EPUN Mask */\r
-#define SCU_SFSP1_14_EHS_Pos 5 /*!< SCU SFSP1_14: EHS Position */\r
-#define SCU_SFSP1_14_EHS_Msk (0x01UL << SCU_SFSP1_14_EHS_Pos) /*!< SCU SFSP1_14: EHS Mask */\r
-#define SCU_SFSP1_14_EZI_Pos 6 /*!< SCU SFSP1_14: EZI Position */\r
-#define SCU_SFSP1_14_EZI_Msk (0x01UL << SCU_SFSP1_14_EZI_Pos) /*!< SCU SFSP1_14: EZI Mask */\r
-#define SCU_SFSP1_14_EHD_Pos 8 /*!< SCU SFSP1_14: EHD Position */\r
-#define SCU_SFSP1_14_EHD_Msk (0x03UL << SCU_SFSP1_14_EHD_Pos) /*!< SCU SFSP1_14: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_15 ------------------------------------------\r
-#define SCU_SFSP1_15_MODE_Pos 0 /*!< SCU SFSP1_15: MODE Position */\r
-#define SCU_SFSP1_15_MODE_Msk (0x07UL << SCU_SFSP1_15_MODE_Pos) /*!< SCU SFSP1_15: MODE Mask */\r
-#define SCU_SFSP1_15_EPD_Pos 3 /*!< SCU SFSP1_15: EPD Position */\r
-#define SCU_SFSP1_15_EPD_Msk (0x01UL << SCU_SFSP1_15_EPD_Pos) /*!< SCU SFSP1_15: EPD Mask */\r
-#define SCU_SFSP1_15_EPUN_Pos 4 /*!< SCU SFSP1_15: EPUN Position */\r
-#define SCU_SFSP1_15_EPUN_Msk (0x01UL << SCU_SFSP1_15_EPUN_Pos) /*!< SCU SFSP1_15: EPUN Mask */\r
-#define SCU_SFSP1_15_EHS_Pos 5 /*!< SCU SFSP1_15: EHS Position */\r
-#define SCU_SFSP1_15_EHS_Msk (0x01UL << SCU_SFSP1_15_EHS_Pos) /*!< SCU SFSP1_15: EHS Mask */\r
-#define SCU_SFSP1_15_EZI_Pos 6 /*!< SCU SFSP1_15: EZI Position */\r
-#define SCU_SFSP1_15_EZI_Msk (0x01UL << SCU_SFSP1_15_EZI_Pos) /*!< SCU SFSP1_15: EZI Mask */\r
-#define SCU_SFSP1_15_EHD_Pos 8 /*!< SCU SFSP1_15: EHD Position */\r
-#define SCU_SFSP1_15_EHD_Msk (0x03UL << SCU_SFSP1_15_EHD_Pos) /*!< SCU SFSP1_15: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_16 ------------------------------------------\r
-#define SCU_SFSP1_16_MODE_Pos 0 /*!< SCU SFSP1_16: MODE Position */\r
-#define SCU_SFSP1_16_MODE_Msk (0x07UL << SCU_SFSP1_16_MODE_Pos) /*!< SCU SFSP1_16: MODE Mask */\r
-#define SCU_SFSP1_16_EPD_Pos 3 /*!< SCU SFSP1_16: EPD Position */\r
-#define SCU_SFSP1_16_EPD_Msk (0x01UL << SCU_SFSP1_16_EPD_Pos) /*!< SCU SFSP1_16: EPD Mask */\r
-#define SCU_SFSP1_16_EPUN_Pos 4 /*!< SCU SFSP1_16: EPUN Position */\r
-#define SCU_SFSP1_16_EPUN_Msk (0x01UL << SCU_SFSP1_16_EPUN_Pos) /*!< SCU SFSP1_16: EPUN Mask */\r
-#define SCU_SFSP1_16_EHS_Pos 5 /*!< SCU SFSP1_16: EHS Position */\r
-#define SCU_SFSP1_16_EHS_Msk (0x01UL << SCU_SFSP1_16_EHS_Pos) /*!< SCU SFSP1_16: EHS Mask */\r
-#define SCU_SFSP1_16_EZI_Pos 6 /*!< SCU SFSP1_16: EZI Position */\r
-#define SCU_SFSP1_16_EZI_Msk (0x01UL << SCU_SFSP1_16_EZI_Pos) /*!< SCU SFSP1_16: EZI Mask */\r
-#define SCU_SFSP1_16_EHD_Pos 8 /*!< SCU SFSP1_16: EHD Position */\r
-#define SCU_SFSP1_16_EHD_Msk (0x03UL << SCU_SFSP1_16_EHD_Pos) /*!< SCU SFSP1_16: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_17 ------------------------------------------\r
-#define SCU_SFSP1_17_MODE_Pos 0 /*!< SCU SFSP1_17: MODE Position */\r
-#define SCU_SFSP1_17_MODE_Msk (0x07UL << SCU_SFSP1_17_MODE_Pos) /*!< SCU SFSP1_17: MODE Mask */\r
-#define SCU_SFSP1_17_EPD_Pos 3 /*!< SCU SFSP1_17: EPD Position */\r
-#define SCU_SFSP1_17_EPD_Msk (0x01UL << SCU_SFSP1_17_EPD_Pos) /*!< SCU SFSP1_17: EPD Mask */\r
-#define SCU_SFSP1_17_EPUN_Pos 4 /*!< SCU SFSP1_17: EPUN Position */\r
-#define SCU_SFSP1_17_EPUN_Msk (0x01UL << SCU_SFSP1_17_EPUN_Pos) /*!< SCU SFSP1_17: EPUN Mask */\r
-#define SCU_SFSP1_17_EHS_Pos 5 /*!< SCU SFSP1_17: EHS Position */\r
-#define SCU_SFSP1_17_EHS_Msk (0x01UL << SCU_SFSP1_17_EHS_Pos) /*!< SCU SFSP1_17: EHS Mask */\r
-#define SCU_SFSP1_17_EZI_Pos 6 /*!< SCU SFSP1_17: EZI Position */\r
-#define SCU_SFSP1_17_EZI_Msk (0x01UL << SCU_SFSP1_17_EZI_Pos) /*!< SCU SFSP1_17: EZI Mask */\r
-#define SCU_SFSP1_17_EHD_Pos 8 /*!< SCU SFSP1_17: EHD Position */\r
-#define SCU_SFSP1_17_EHD_Msk (0x03UL << SCU_SFSP1_17_EHD_Pos) /*!< SCU SFSP1_17: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_18 ------------------------------------------\r
-#define SCU_SFSP1_18_MODE_Pos 0 /*!< SCU SFSP1_18: MODE Position */\r
-#define SCU_SFSP1_18_MODE_Msk (0x07UL << SCU_SFSP1_18_MODE_Pos) /*!< SCU SFSP1_18: MODE Mask */\r
-#define SCU_SFSP1_18_EPD_Pos 3 /*!< SCU SFSP1_18: EPD Position */\r
-#define SCU_SFSP1_18_EPD_Msk (0x01UL << SCU_SFSP1_18_EPD_Pos) /*!< SCU SFSP1_18: EPD Mask */\r
-#define SCU_SFSP1_18_EPUN_Pos 4 /*!< SCU SFSP1_18: EPUN Position */\r
-#define SCU_SFSP1_18_EPUN_Msk (0x01UL << SCU_SFSP1_18_EPUN_Pos) /*!< SCU SFSP1_18: EPUN Mask */\r
-#define SCU_SFSP1_18_EHS_Pos 5 /*!< SCU SFSP1_18: EHS Position */\r
-#define SCU_SFSP1_18_EHS_Msk (0x01UL << SCU_SFSP1_18_EHS_Pos) /*!< SCU SFSP1_18: EHS Mask */\r
-#define SCU_SFSP1_18_EZI_Pos 6 /*!< SCU SFSP1_18: EZI Position */\r
-#define SCU_SFSP1_18_EZI_Msk (0x01UL << SCU_SFSP1_18_EZI_Pos) /*!< SCU SFSP1_18: EZI Mask */\r
-#define SCU_SFSP1_18_EHD_Pos 8 /*!< SCU SFSP1_18: EHD Position */\r
-#define SCU_SFSP1_18_EHD_Msk (0x03UL << SCU_SFSP1_18_EHD_Pos) /*!< SCU SFSP1_18: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_19 ------------------------------------------\r
-#define SCU_SFSP1_19_MODE_Pos 0 /*!< SCU SFSP1_19: MODE Position */\r
-#define SCU_SFSP1_19_MODE_Msk (0x07UL << SCU_SFSP1_19_MODE_Pos) /*!< SCU SFSP1_19: MODE Mask */\r
-#define SCU_SFSP1_19_EPD_Pos 3 /*!< SCU SFSP1_19: EPD Position */\r
-#define SCU_SFSP1_19_EPD_Msk (0x01UL << SCU_SFSP1_19_EPD_Pos) /*!< SCU SFSP1_19: EPD Mask */\r
-#define SCU_SFSP1_19_EPUN_Pos 4 /*!< SCU SFSP1_19: EPUN Position */\r
-#define SCU_SFSP1_19_EPUN_Msk (0x01UL << SCU_SFSP1_19_EPUN_Pos) /*!< SCU SFSP1_19: EPUN Mask */\r
-#define SCU_SFSP1_19_EHS_Pos 5 /*!< SCU SFSP1_19: EHS Position */\r
-#define SCU_SFSP1_19_EHS_Msk (0x01UL << SCU_SFSP1_19_EHS_Pos) /*!< SCU SFSP1_19: EHS Mask */\r
-#define SCU_SFSP1_19_EZI_Pos 6 /*!< SCU SFSP1_19: EZI Position */\r
-#define SCU_SFSP1_19_EZI_Msk (0x01UL << SCU_SFSP1_19_EZI_Pos) /*!< SCU SFSP1_19: EZI Mask */\r
-#define SCU_SFSP1_19_EHD_Pos 8 /*!< SCU SFSP1_19: EHD Position */\r
-#define SCU_SFSP1_19_EHD_Msk (0x03UL << SCU_SFSP1_19_EHD_Pos) /*!< SCU SFSP1_19: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP1_20 ------------------------------------------\r
-#define SCU_SFSP1_20_MODE_Pos 0 /*!< SCU SFSP1_20: MODE Position */\r
-#define SCU_SFSP1_20_MODE_Msk (0x07UL << SCU_SFSP1_20_MODE_Pos) /*!< SCU SFSP1_20: MODE Mask */\r
-#define SCU_SFSP1_20_EPD_Pos 3 /*!< SCU SFSP1_20: EPD Position */\r
-#define SCU_SFSP1_20_EPD_Msk (0x01UL << SCU_SFSP1_20_EPD_Pos) /*!< SCU SFSP1_20: EPD Mask */\r
-#define SCU_SFSP1_20_EPUN_Pos 4 /*!< SCU SFSP1_20: EPUN Position */\r
-#define SCU_SFSP1_20_EPUN_Msk (0x01UL << SCU_SFSP1_20_EPUN_Pos) /*!< SCU SFSP1_20: EPUN Mask */\r
-#define SCU_SFSP1_20_EHS_Pos 5 /*!< SCU SFSP1_20: EHS Position */\r
-#define SCU_SFSP1_20_EHS_Msk (0x01UL << SCU_SFSP1_20_EHS_Pos) /*!< SCU SFSP1_20: EHS Mask */\r
-#define SCU_SFSP1_20_EZI_Pos 6 /*!< SCU SFSP1_20: EZI Position */\r
-#define SCU_SFSP1_20_EZI_Msk (0x01UL << SCU_SFSP1_20_EZI_Pos) /*!< SCU SFSP1_20: EZI Mask */\r
-#define SCU_SFSP1_20_EHD_Pos 8 /*!< SCU SFSP1_20: EHD Position */\r
-#define SCU_SFSP1_20_EHD_Msk (0x03UL << SCU_SFSP1_20_EHD_Pos) /*!< SCU SFSP1_20: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_0 ------------------------------------------\r
-#define SCU_SFSP2_0_MODE_Pos 0 /*!< SCU SFSP2_0: MODE Position */\r
-#define SCU_SFSP2_0_MODE_Msk (0x07UL << SCU_SFSP2_0_MODE_Pos) /*!< SCU SFSP2_0: MODE Mask */\r
-#define SCU_SFSP2_0_EPD_Pos 3 /*!< SCU SFSP2_0: EPD Position */\r
-#define SCU_SFSP2_0_EPD_Msk (0x01UL << SCU_SFSP2_0_EPD_Pos) /*!< SCU SFSP2_0: EPD Mask */\r
-#define SCU_SFSP2_0_EPUN_Pos 4 /*!< SCU SFSP2_0: EPUN Position */\r
-#define SCU_SFSP2_0_EPUN_Msk (0x01UL << SCU_SFSP2_0_EPUN_Pos) /*!< SCU SFSP2_0: EPUN Mask */\r
-#define SCU_SFSP2_0_EHS_Pos 5 /*!< SCU SFSP2_0: EHS Position */\r
-#define SCU_SFSP2_0_EHS_Msk (0x01UL << SCU_SFSP2_0_EHS_Pos) /*!< SCU SFSP2_0: EHS Mask */\r
-#define SCU_SFSP2_0_EZI_Pos 6 /*!< SCU SFSP2_0: EZI Position */\r
-#define SCU_SFSP2_0_EZI_Msk (0x01UL << SCU_SFSP2_0_EZI_Pos) /*!< SCU SFSP2_0: EZI Mask */\r
-#define SCU_SFSP2_0_EHD_Pos 8 /*!< SCU SFSP2_0: EHD Position */\r
-#define SCU_SFSP2_0_EHD_Msk (0x03UL << SCU_SFSP2_0_EHD_Pos) /*!< SCU SFSP2_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_1 ------------------------------------------\r
-#define SCU_SFSP2_1_MODE_Pos 0 /*!< SCU SFSP2_1: MODE Position */\r
-#define SCU_SFSP2_1_MODE_Msk (0x07UL << SCU_SFSP2_1_MODE_Pos) /*!< SCU SFSP2_1: MODE Mask */\r
-#define SCU_SFSP2_1_EPD_Pos 3 /*!< SCU SFSP2_1: EPD Position */\r
-#define SCU_SFSP2_1_EPD_Msk (0x01UL << SCU_SFSP2_1_EPD_Pos) /*!< SCU SFSP2_1: EPD Mask */\r
-#define SCU_SFSP2_1_EPUN_Pos 4 /*!< SCU SFSP2_1: EPUN Position */\r
-#define SCU_SFSP2_1_EPUN_Msk (0x01UL << SCU_SFSP2_1_EPUN_Pos) /*!< SCU SFSP2_1: EPUN Mask */\r
-#define SCU_SFSP2_1_EHS_Pos 5 /*!< SCU SFSP2_1: EHS Position */\r
-#define SCU_SFSP2_1_EHS_Msk (0x01UL << SCU_SFSP2_1_EHS_Pos) /*!< SCU SFSP2_1: EHS Mask */\r
-#define SCU_SFSP2_1_EZI_Pos 6 /*!< SCU SFSP2_1: EZI Position */\r
-#define SCU_SFSP2_1_EZI_Msk (0x01UL << SCU_SFSP2_1_EZI_Pos) /*!< SCU SFSP2_1: EZI Mask */\r
-#define SCU_SFSP2_1_EHD_Pos 8 /*!< SCU SFSP2_1: EHD Position */\r
-#define SCU_SFSP2_1_EHD_Msk (0x03UL << SCU_SFSP2_1_EHD_Pos) /*!< SCU SFSP2_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_2 ------------------------------------------\r
-#define SCU_SFSP2_2_MODE_Pos 0 /*!< SCU SFSP2_2: MODE Position */\r
-#define SCU_SFSP2_2_MODE_Msk (0x07UL << SCU_SFSP2_2_MODE_Pos) /*!< SCU SFSP2_2: MODE Mask */\r
-#define SCU_SFSP2_2_EPD_Pos 3 /*!< SCU SFSP2_2: EPD Position */\r
-#define SCU_SFSP2_2_EPD_Msk (0x01UL << SCU_SFSP2_2_EPD_Pos) /*!< SCU SFSP2_2: EPD Mask */\r
-#define SCU_SFSP2_2_EPUN_Pos 4 /*!< SCU SFSP2_2: EPUN Position */\r
-#define SCU_SFSP2_2_EPUN_Msk (0x01UL << SCU_SFSP2_2_EPUN_Pos) /*!< SCU SFSP2_2: EPUN Mask */\r
-#define SCU_SFSP2_2_EHS_Pos 5 /*!< SCU SFSP2_2: EHS Position */\r
-#define SCU_SFSP2_2_EHS_Msk (0x01UL << SCU_SFSP2_2_EHS_Pos) /*!< SCU SFSP2_2: EHS Mask */\r
-#define SCU_SFSP2_2_EZI_Pos 6 /*!< SCU SFSP2_2: EZI Position */\r
-#define SCU_SFSP2_2_EZI_Msk (0x01UL << SCU_SFSP2_2_EZI_Pos) /*!< SCU SFSP2_2: EZI Mask */\r
-#define SCU_SFSP2_2_EHD_Pos 8 /*!< SCU SFSP2_2: EHD Position */\r
-#define SCU_SFSP2_2_EHD_Msk (0x03UL << SCU_SFSP2_2_EHD_Pos) /*!< SCU SFSP2_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_3 ------------------------------------------\r
-#define SCU_SFSP2_3_MODE_Pos 0 /*!< SCU SFSP2_3: MODE Position */\r
-#define SCU_SFSP2_3_MODE_Msk (0x07UL << SCU_SFSP2_3_MODE_Pos) /*!< SCU SFSP2_3: MODE Mask */\r
-#define SCU_SFSP2_3_EPD_Pos 3 /*!< SCU SFSP2_3: EPD Position */\r
-#define SCU_SFSP2_3_EPD_Msk (0x01UL << SCU_SFSP2_3_EPD_Pos) /*!< SCU SFSP2_3: EPD Mask */\r
-#define SCU_SFSP2_3_EPUN_Pos 4 /*!< SCU SFSP2_3: EPUN Position */\r
-#define SCU_SFSP2_3_EPUN_Msk (0x01UL << SCU_SFSP2_3_EPUN_Pos) /*!< SCU SFSP2_3: EPUN Mask */\r
-#define SCU_SFSP2_3_EHS_Pos 5 /*!< SCU SFSP2_3: EHS Position */\r
-#define SCU_SFSP2_3_EHS_Msk (0x01UL << SCU_SFSP2_3_EHS_Pos) /*!< SCU SFSP2_3: EHS Mask */\r
-#define SCU_SFSP2_3_EZI_Pos 6 /*!< SCU SFSP2_3: EZI Position */\r
-#define SCU_SFSP2_3_EZI_Msk (0x01UL << SCU_SFSP2_3_EZI_Pos) /*!< SCU SFSP2_3: EZI Mask */\r
-#define SCU_SFSP2_3_EHD_Pos 8 /*!< SCU SFSP2_3: EHD Position */\r
-#define SCU_SFSP2_3_EHD_Msk (0x03UL << SCU_SFSP2_3_EHD_Pos) /*!< SCU SFSP2_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_4 ------------------------------------------\r
-#define SCU_SFSP2_4_MODE_Pos 0 /*!< SCU SFSP2_4: MODE Position */\r
-#define SCU_SFSP2_4_MODE_Msk (0x07UL << SCU_SFSP2_4_MODE_Pos) /*!< SCU SFSP2_4: MODE Mask */\r
-#define SCU_SFSP2_4_EPD_Pos 3 /*!< SCU SFSP2_4: EPD Position */\r
-#define SCU_SFSP2_4_EPD_Msk (0x01UL << SCU_SFSP2_4_EPD_Pos) /*!< SCU SFSP2_4: EPD Mask */\r
-#define SCU_SFSP2_4_EPUN_Pos 4 /*!< SCU SFSP2_4: EPUN Position */\r
-#define SCU_SFSP2_4_EPUN_Msk (0x01UL << SCU_SFSP2_4_EPUN_Pos) /*!< SCU SFSP2_4: EPUN Mask */\r
-#define SCU_SFSP2_4_EHS_Pos 5 /*!< SCU SFSP2_4: EHS Position */\r
-#define SCU_SFSP2_4_EHS_Msk (0x01UL << SCU_SFSP2_4_EHS_Pos) /*!< SCU SFSP2_4: EHS Mask */\r
-#define SCU_SFSP2_4_EZI_Pos 6 /*!< SCU SFSP2_4: EZI Position */\r
-#define SCU_SFSP2_4_EZI_Msk (0x01UL << SCU_SFSP2_4_EZI_Pos) /*!< SCU SFSP2_4: EZI Mask */\r
-#define SCU_SFSP2_4_EHD_Pos 8 /*!< SCU SFSP2_4: EHD Position */\r
-#define SCU_SFSP2_4_EHD_Msk (0x03UL << SCU_SFSP2_4_EHD_Pos) /*!< SCU SFSP2_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_5 ------------------------------------------\r
-#define SCU_SFSP2_5_MODE_Pos 0 /*!< SCU SFSP2_5: MODE Position */\r
-#define SCU_SFSP2_5_MODE_Msk (0x07UL << SCU_SFSP2_5_MODE_Pos) /*!< SCU SFSP2_5: MODE Mask */\r
-#define SCU_SFSP2_5_EPD_Pos 3 /*!< SCU SFSP2_5: EPD Position */\r
-#define SCU_SFSP2_5_EPD_Msk (0x01UL << SCU_SFSP2_5_EPD_Pos) /*!< SCU SFSP2_5: EPD Mask */\r
-#define SCU_SFSP2_5_EPUN_Pos 4 /*!< SCU SFSP2_5: EPUN Position */\r
-#define SCU_SFSP2_5_EPUN_Msk (0x01UL << SCU_SFSP2_5_EPUN_Pos) /*!< SCU SFSP2_5: EPUN Mask */\r
-#define SCU_SFSP2_5_EHS_Pos 5 /*!< SCU SFSP2_5: EHS Position */\r
-#define SCU_SFSP2_5_EHS_Msk (0x01UL << SCU_SFSP2_5_EHS_Pos) /*!< SCU SFSP2_5: EHS Mask */\r
-#define SCU_SFSP2_5_EZI_Pos 6 /*!< SCU SFSP2_5: EZI Position */\r
-#define SCU_SFSP2_5_EZI_Msk (0x01UL << SCU_SFSP2_5_EZI_Pos) /*!< SCU SFSP2_5: EZI Mask */\r
-#define SCU_SFSP2_5_EHD_Pos 8 /*!< SCU SFSP2_5: EHD Position */\r
-#define SCU_SFSP2_5_EHD_Msk (0x03UL << SCU_SFSP2_5_EHD_Pos) /*!< SCU SFSP2_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_6 ------------------------------------------\r
-#define SCU_SFSP2_6_MODE_Pos 0 /*!< SCU SFSP2_6: MODE Position */\r
-#define SCU_SFSP2_6_MODE_Msk (0x07UL << SCU_SFSP2_6_MODE_Pos) /*!< SCU SFSP2_6: MODE Mask */\r
-#define SCU_SFSP2_6_EPD_Pos 3 /*!< SCU SFSP2_6: EPD Position */\r
-#define SCU_SFSP2_6_EPD_Msk (0x01UL << SCU_SFSP2_6_EPD_Pos) /*!< SCU SFSP2_6: EPD Mask */\r
-#define SCU_SFSP2_6_EPUN_Pos 4 /*!< SCU SFSP2_6: EPUN Position */\r
-#define SCU_SFSP2_6_EPUN_Msk (0x01UL << SCU_SFSP2_6_EPUN_Pos) /*!< SCU SFSP2_6: EPUN Mask */\r
-#define SCU_SFSP2_6_EHS_Pos 5 /*!< SCU SFSP2_6: EHS Position */\r
-#define SCU_SFSP2_6_EHS_Msk (0x01UL << SCU_SFSP2_6_EHS_Pos) /*!< SCU SFSP2_6: EHS Mask */\r
-#define SCU_SFSP2_6_EZI_Pos 6 /*!< SCU SFSP2_6: EZI Position */\r
-#define SCU_SFSP2_6_EZI_Msk (0x01UL << SCU_SFSP2_6_EZI_Pos) /*!< SCU SFSP2_6: EZI Mask */\r
-#define SCU_SFSP2_6_EHD_Pos 8 /*!< SCU SFSP2_6: EHD Position */\r
-#define SCU_SFSP2_6_EHD_Msk (0x03UL << SCU_SFSP2_6_EHD_Pos) /*!< SCU SFSP2_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_7 ------------------------------------------\r
-#define SCU_SFSP2_7_MODE_Pos 0 /*!< SCU SFSP2_7: MODE Position */\r
-#define SCU_SFSP2_7_MODE_Msk (0x07UL << SCU_SFSP2_7_MODE_Pos) /*!< SCU SFSP2_7: MODE Mask */\r
-#define SCU_SFSP2_7_EPD_Pos 3 /*!< SCU SFSP2_7: EPD Position */\r
-#define SCU_SFSP2_7_EPD_Msk (0x01UL << SCU_SFSP2_7_EPD_Pos) /*!< SCU SFSP2_7: EPD Mask */\r
-#define SCU_SFSP2_7_EPUN_Pos 4 /*!< SCU SFSP2_7: EPUN Position */\r
-#define SCU_SFSP2_7_EPUN_Msk (0x01UL << SCU_SFSP2_7_EPUN_Pos) /*!< SCU SFSP2_7: EPUN Mask */\r
-#define SCU_SFSP2_7_EHS_Pos 5 /*!< SCU SFSP2_7: EHS Position */\r
-#define SCU_SFSP2_7_EHS_Msk (0x01UL << SCU_SFSP2_7_EHS_Pos) /*!< SCU SFSP2_7: EHS Mask */\r
-#define SCU_SFSP2_7_EZI_Pos 6 /*!< SCU SFSP2_7: EZI Position */\r
-#define SCU_SFSP2_7_EZI_Msk (0x01UL << SCU_SFSP2_7_EZI_Pos) /*!< SCU SFSP2_7: EZI Mask */\r
-#define SCU_SFSP2_7_EHD_Pos 8 /*!< SCU SFSP2_7: EHD Position */\r
-#define SCU_SFSP2_7_EHD_Msk (0x03UL << SCU_SFSP2_7_EHD_Pos) /*!< SCU SFSP2_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_8 ------------------------------------------\r
-#define SCU_SFSP2_8_MODE_Pos 0 /*!< SCU SFSP2_8: MODE Position */\r
-#define SCU_SFSP2_8_MODE_Msk (0x07UL << SCU_SFSP2_8_MODE_Pos) /*!< SCU SFSP2_8: MODE Mask */\r
-#define SCU_SFSP2_8_EPD_Pos 3 /*!< SCU SFSP2_8: EPD Position */\r
-#define SCU_SFSP2_8_EPD_Msk (0x01UL << SCU_SFSP2_8_EPD_Pos) /*!< SCU SFSP2_8: EPD Mask */\r
-#define SCU_SFSP2_8_EPUN_Pos 4 /*!< SCU SFSP2_8: EPUN Position */\r
-#define SCU_SFSP2_8_EPUN_Msk (0x01UL << SCU_SFSP2_8_EPUN_Pos) /*!< SCU SFSP2_8: EPUN Mask */\r
-#define SCU_SFSP2_8_EHS_Pos 5 /*!< SCU SFSP2_8: EHS Position */\r
-#define SCU_SFSP2_8_EHS_Msk (0x01UL << SCU_SFSP2_8_EHS_Pos) /*!< SCU SFSP2_8: EHS Mask */\r
-#define SCU_SFSP2_8_EZI_Pos 6 /*!< SCU SFSP2_8: EZI Position */\r
-#define SCU_SFSP2_8_EZI_Msk (0x01UL << SCU_SFSP2_8_EZI_Pos) /*!< SCU SFSP2_8: EZI Mask */\r
-#define SCU_SFSP2_8_EHD_Pos 8 /*!< SCU SFSP2_8: EHD Position */\r
-#define SCU_SFSP2_8_EHD_Msk (0x03UL << SCU_SFSP2_8_EHD_Pos) /*!< SCU SFSP2_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP2_9 ------------------------------------------\r
-#define SCU_SFSP2_9_MODE_Pos 0 /*!< SCU SFSP2_9: MODE Position */\r
-#define SCU_SFSP2_9_MODE_Msk (0x07UL << SCU_SFSP2_9_MODE_Pos) /*!< SCU SFSP2_9: MODE Mask */\r
-#define SCU_SFSP2_9_EPD_Pos 3 /*!< SCU SFSP2_9: EPD Position */\r
-#define SCU_SFSP2_9_EPD_Msk (0x01UL << SCU_SFSP2_9_EPD_Pos) /*!< SCU SFSP2_9: EPD Mask */\r
-#define SCU_SFSP2_9_EPUN_Pos 4 /*!< SCU SFSP2_9: EPUN Position */\r
-#define SCU_SFSP2_9_EPUN_Msk (0x01UL << SCU_SFSP2_9_EPUN_Pos) /*!< SCU SFSP2_9: EPUN Mask */\r
-#define SCU_SFSP2_9_EHS_Pos 5 /*!< SCU SFSP2_9: EHS Position */\r
-#define SCU_SFSP2_9_EHS_Msk (0x01UL << SCU_SFSP2_9_EHS_Pos) /*!< SCU SFSP2_9: EHS Mask */\r
-#define SCU_SFSP2_9_EZI_Pos 6 /*!< SCU SFSP2_9: EZI Position */\r
-#define SCU_SFSP2_9_EZI_Msk (0x01UL << SCU_SFSP2_9_EZI_Pos) /*!< SCU SFSP2_9: EZI Mask */\r
-#define SCU_SFSP2_9_EHD_Pos 8 /*!< SCU SFSP2_9: EHD Position */\r
-#define SCU_SFSP2_9_EHD_Msk (0x03UL << SCU_SFSP2_9_EHD_Pos) /*!< SCU SFSP2_9: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP2_10 ------------------------------------------\r
-#define SCU_SFSP2_10_MODE_Pos 0 /*!< SCU SFSP2_10: MODE Position */\r
-#define SCU_SFSP2_10_MODE_Msk (0x07UL << SCU_SFSP2_10_MODE_Pos) /*!< SCU SFSP2_10: MODE Mask */\r
-#define SCU_SFSP2_10_EPD_Pos 3 /*!< SCU SFSP2_10: EPD Position */\r
-#define SCU_SFSP2_10_EPD_Msk (0x01UL << SCU_SFSP2_10_EPD_Pos) /*!< SCU SFSP2_10: EPD Mask */\r
-#define SCU_SFSP2_10_EPUN_Pos 4 /*!< SCU SFSP2_10: EPUN Position */\r
-#define SCU_SFSP2_10_EPUN_Msk (0x01UL << SCU_SFSP2_10_EPUN_Pos) /*!< SCU SFSP2_10: EPUN Mask */\r
-#define SCU_SFSP2_10_EHS_Pos 5 /*!< SCU SFSP2_10: EHS Position */\r
-#define SCU_SFSP2_10_EHS_Msk (0x01UL << SCU_SFSP2_10_EHS_Pos) /*!< SCU SFSP2_10: EHS Mask */\r
-#define SCU_SFSP2_10_EZI_Pos 6 /*!< SCU SFSP2_10: EZI Position */\r
-#define SCU_SFSP2_10_EZI_Msk (0x01UL << SCU_SFSP2_10_EZI_Pos) /*!< SCU SFSP2_10: EZI Mask */\r
-#define SCU_SFSP2_10_EHD_Pos 8 /*!< SCU SFSP2_10: EHD Position */\r
-#define SCU_SFSP2_10_EHD_Msk (0x03UL << SCU_SFSP2_10_EHD_Pos) /*!< SCU SFSP2_10: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP2_11 ------------------------------------------\r
-#define SCU_SFSP2_11_MODE_Pos 0 /*!< SCU SFSP2_11: MODE Position */\r
-#define SCU_SFSP2_11_MODE_Msk (0x07UL << SCU_SFSP2_11_MODE_Pos) /*!< SCU SFSP2_11: MODE Mask */\r
-#define SCU_SFSP2_11_EPD_Pos 3 /*!< SCU SFSP2_11: EPD Position */\r
-#define SCU_SFSP2_11_EPD_Msk (0x01UL << SCU_SFSP2_11_EPD_Pos) /*!< SCU SFSP2_11: EPD Mask */\r
-#define SCU_SFSP2_11_EPUN_Pos 4 /*!< SCU SFSP2_11: EPUN Position */\r
-#define SCU_SFSP2_11_EPUN_Msk (0x01UL << SCU_SFSP2_11_EPUN_Pos) /*!< SCU SFSP2_11: EPUN Mask */\r
-#define SCU_SFSP2_11_EHS_Pos 5 /*!< SCU SFSP2_11: EHS Position */\r
-#define SCU_SFSP2_11_EHS_Msk (0x01UL << SCU_SFSP2_11_EHS_Pos) /*!< SCU SFSP2_11: EHS Mask */\r
-#define SCU_SFSP2_11_EZI_Pos 6 /*!< SCU SFSP2_11: EZI Position */\r
-#define SCU_SFSP2_11_EZI_Msk (0x01UL << SCU_SFSP2_11_EZI_Pos) /*!< SCU SFSP2_11: EZI Mask */\r
-#define SCU_SFSP2_11_EHD_Pos 8 /*!< SCU SFSP2_11: EHD Position */\r
-#define SCU_SFSP2_11_EHD_Msk (0x03UL << SCU_SFSP2_11_EHD_Pos) /*!< SCU SFSP2_11: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP2_12 ------------------------------------------\r
-#define SCU_SFSP2_12_MODE_Pos 0 /*!< SCU SFSP2_12: MODE Position */\r
-#define SCU_SFSP2_12_MODE_Msk (0x07UL << SCU_SFSP2_12_MODE_Pos) /*!< SCU SFSP2_12: MODE Mask */\r
-#define SCU_SFSP2_12_EPD_Pos 3 /*!< SCU SFSP2_12: EPD Position */\r
-#define SCU_SFSP2_12_EPD_Msk (0x01UL << SCU_SFSP2_12_EPD_Pos) /*!< SCU SFSP2_12: EPD Mask */\r
-#define SCU_SFSP2_12_EPUN_Pos 4 /*!< SCU SFSP2_12: EPUN Position */\r
-#define SCU_SFSP2_12_EPUN_Msk (0x01UL << SCU_SFSP2_12_EPUN_Pos) /*!< SCU SFSP2_12: EPUN Mask */\r
-#define SCU_SFSP2_12_EHS_Pos 5 /*!< SCU SFSP2_12: EHS Position */\r
-#define SCU_SFSP2_12_EHS_Msk (0x01UL << SCU_SFSP2_12_EHS_Pos) /*!< SCU SFSP2_12: EHS Mask */\r
-#define SCU_SFSP2_12_EZI_Pos 6 /*!< SCU SFSP2_12: EZI Position */\r
-#define SCU_SFSP2_12_EZI_Msk (0x01UL << SCU_SFSP2_12_EZI_Pos) /*!< SCU SFSP2_12: EZI Mask */\r
-#define SCU_SFSP2_12_EHD_Pos 8 /*!< SCU SFSP2_12: EHD Position */\r
-#define SCU_SFSP2_12_EHD_Msk (0x03UL << SCU_SFSP2_12_EHD_Pos) /*!< SCU SFSP2_12: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP2_13 ------------------------------------------\r
-#define SCU_SFSP2_13_MODE_Pos 0 /*!< SCU SFSP2_13: MODE Position */\r
-#define SCU_SFSP2_13_MODE_Msk (0x07UL << SCU_SFSP2_13_MODE_Pos) /*!< SCU SFSP2_13: MODE Mask */\r
-#define SCU_SFSP2_13_EPD_Pos 3 /*!< SCU SFSP2_13: EPD Position */\r
-#define SCU_SFSP2_13_EPD_Msk (0x01UL << SCU_SFSP2_13_EPD_Pos) /*!< SCU SFSP2_13: EPD Mask */\r
-#define SCU_SFSP2_13_EPUN_Pos 4 /*!< SCU SFSP2_13: EPUN Position */\r
-#define SCU_SFSP2_13_EPUN_Msk (0x01UL << SCU_SFSP2_13_EPUN_Pos) /*!< SCU SFSP2_13: EPUN Mask */\r
-#define SCU_SFSP2_13_EHS_Pos 5 /*!< SCU SFSP2_13: EHS Position */\r
-#define SCU_SFSP2_13_EHS_Msk (0x01UL << SCU_SFSP2_13_EHS_Pos) /*!< SCU SFSP2_13: EHS Mask */\r
-#define SCU_SFSP2_13_EZI_Pos 6 /*!< SCU SFSP2_13: EZI Position */\r
-#define SCU_SFSP2_13_EZI_Msk (0x01UL << SCU_SFSP2_13_EZI_Pos) /*!< SCU SFSP2_13: EZI Mask */\r
-#define SCU_SFSP2_13_EHD_Pos 8 /*!< SCU SFSP2_13: EHD Position */\r
-#define SCU_SFSP2_13_EHD_Msk (0x03UL << SCU_SFSP2_13_EHD_Pos) /*!< SCU SFSP2_13: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP3_0 ------------------------------------------\r
-#define SCU_SFSP3_0_MODE_Pos 0 /*!< SCU SFSP3_0: MODE Position */\r
-#define SCU_SFSP3_0_MODE_Msk (0x07UL << SCU_SFSP3_0_MODE_Pos) /*!< SCU SFSP3_0: MODE Mask */\r
-#define SCU_SFSP3_0_EPD_Pos 3 /*!< SCU SFSP3_0: EPD Position */\r
-#define SCU_SFSP3_0_EPD_Msk (0x01UL << SCU_SFSP3_0_EPD_Pos) /*!< SCU SFSP3_0: EPD Mask */\r
-#define SCU_SFSP3_0_EPUN_Pos 4 /*!< SCU SFSP3_0: EPUN Position */\r
-#define SCU_SFSP3_0_EPUN_Msk (0x01UL << SCU_SFSP3_0_EPUN_Pos) /*!< SCU SFSP3_0: EPUN Mask */\r
-#define SCU_SFSP3_0_EHS_Pos 5 /*!< SCU SFSP3_0: EHS Position */\r
-#define SCU_SFSP3_0_EHS_Msk (0x01UL << SCU_SFSP3_0_EHS_Pos) /*!< SCU SFSP3_0: EHS Mask */\r
-#define SCU_SFSP3_0_EZI_Pos 6 /*!< SCU SFSP3_0: EZI Position */\r
-#define SCU_SFSP3_0_EZI_Msk (0x01UL << SCU_SFSP3_0_EZI_Pos) /*!< SCU SFSP3_0: EZI Mask */\r
-#define SCU_SFSP3_0_EHD_Pos 8 /*!< SCU SFSP3_0: EHD Position */\r
-#define SCU_SFSP3_0_EHD_Msk (0x03UL << SCU_SFSP3_0_EHD_Pos) /*!< SCU SFSP3_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP3_1 ------------------------------------------\r
-#define SCU_SFSP3_1_MODE_Pos 0 /*!< SCU SFSP3_1: MODE Position */\r
-#define SCU_SFSP3_1_MODE_Msk (0x07UL << SCU_SFSP3_1_MODE_Pos) /*!< SCU SFSP3_1: MODE Mask */\r
-#define SCU_SFSP3_1_EPD_Pos 3 /*!< SCU SFSP3_1: EPD Position */\r
-#define SCU_SFSP3_1_EPD_Msk (0x01UL << SCU_SFSP3_1_EPD_Pos) /*!< SCU SFSP3_1: EPD Mask */\r
-#define SCU_SFSP3_1_EPUN_Pos 4 /*!< SCU SFSP3_1: EPUN Position */\r
-#define SCU_SFSP3_1_EPUN_Msk (0x01UL << SCU_SFSP3_1_EPUN_Pos) /*!< SCU SFSP3_1: EPUN Mask */\r
-#define SCU_SFSP3_1_EHS_Pos 5 /*!< SCU SFSP3_1: EHS Position */\r
-#define SCU_SFSP3_1_EHS_Msk (0x01UL << SCU_SFSP3_1_EHS_Pos) /*!< SCU SFSP3_1: EHS Mask */\r
-#define SCU_SFSP3_1_EZI_Pos 6 /*!< SCU SFSP3_1: EZI Position */\r
-#define SCU_SFSP3_1_EZI_Msk (0x01UL << SCU_SFSP3_1_EZI_Pos) /*!< SCU SFSP3_1: EZI Mask */\r
-#define SCU_SFSP3_1_EHD_Pos 8 /*!< SCU SFSP3_1: EHD Position */\r
-#define SCU_SFSP3_1_EHD_Msk (0x03UL << SCU_SFSP3_1_EHD_Pos) /*!< SCU SFSP3_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP3_2 ------------------------------------------\r
-#define SCU_SFSP3_2_MODE_Pos 0 /*!< SCU SFSP3_2: MODE Position */\r
-#define SCU_SFSP3_2_MODE_Msk (0x07UL << SCU_SFSP3_2_MODE_Pos) /*!< SCU SFSP3_2: MODE Mask */\r
-#define SCU_SFSP3_2_EPD_Pos 3 /*!< SCU SFSP3_2: EPD Position */\r
-#define SCU_SFSP3_2_EPD_Msk (0x01UL << SCU_SFSP3_2_EPD_Pos) /*!< SCU SFSP3_2: EPD Mask */\r
-#define SCU_SFSP3_2_EPUN_Pos 4 /*!< SCU SFSP3_2: EPUN Position */\r
-#define SCU_SFSP3_2_EPUN_Msk (0x01UL << SCU_SFSP3_2_EPUN_Pos) /*!< SCU SFSP3_2: EPUN Mask */\r
-#define SCU_SFSP3_2_EHS_Pos 5 /*!< SCU SFSP3_2: EHS Position */\r
-#define SCU_SFSP3_2_EHS_Msk (0x01UL << SCU_SFSP3_2_EHS_Pos) /*!< SCU SFSP3_2: EHS Mask */\r
-#define SCU_SFSP3_2_EZI_Pos 6 /*!< SCU SFSP3_2: EZI Position */\r
-#define SCU_SFSP3_2_EZI_Msk (0x01UL << SCU_SFSP3_2_EZI_Pos) /*!< SCU SFSP3_2: EZI Mask */\r
-#define SCU_SFSP3_2_EHD_Pos 8 /*!< SCU SFSP3_2: EHD Position */\r
-#define SCU_SFSP3_2_EHD_Msk (0x03UL << SCU_SFSP3_2_EHD_Pos) /*!< SCU SFSP3_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP3_3 ------------------------------------------\r
-#define SCU_SFSP3_3_MODE_Pos 0 /*!< SCU SFSP3_3: MODE Position */\r
-#define SCU_SFSP3_3_MODE_Msk (0x07UL << SCU_SFSP3_3_MODE_Pos) /*!< SCU SFSP3_3: MODE Mask */\r
-#define SCU_SFSP3_3_EPD_Pos 3 /*!< SCU SFSP3_3: EPD Position */\r
-#define SCU_SFSP3_3_EPD_Msk (0x01UL << SCU_SFSP3_3_EPD_Pos) /*!< SCU SFSP3_3: EPD Mask */\r
-#define SCU_SFSP3_3_EPUN_Pos 4 /*!< SCU SFSP3_3: EPUN Position */\r
-#define SCU_SFSP3_3_EPUN_Msk (0x01UL << SCU_SFSP3_3_EPUN_Pos) /*!< SCU SFSP3_3: EPUN Mask */\r
-#define SCU_SFSP3_3_EHS_Pos 5 /*!< SCU SFSP3_3: EHS Position */\r
-#define SCU_SFSP3_3_EHS_Msk (0x01UL << SCU_SFSP3_3_EHS_Pos) /*!< SCU SFSP3_3: EHS Mask */\r
-#define SCU_SFSP3_3_EZI_Pos 6 /*!< SCU SFSP3_3: EZI Position */\r
-#define SCU_SFSP3_3_EZI_Msk (0x01UL << SCU_SFSP3_3_EZI_Pos) /*!< SCU SFSP3_3: EZI Mask */\r
-#define SCU_SFSP3_3_EHD_Pos 8 /*!< SCU SFSP3_3: EHD Position */\r
-#define SCU_SFSP3_3_EHD_Msk (0x03UL << SCU_SFSP3_3_EHD_Pos) /*!< SCU SFSP3_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP3_4 ------------------------------------------\r
-#define SCU_SFSP3_4_MODE_Pos 0 /*!< SCU SFSP3_4: MODE Position */\r
-#define SCU_SFSP3_4_MODE_Msk (0x07UL << SCU_SFSP3_4_MODE_Pos) /*!< SCU SFSP3_4: MODE Mask */\r
-#define SCU_SFSP3_4_EPD_Pos 3 /*!< SCU SFSP3_4: EPD Position */\r
-#define SCU_SFSP3_4_EPD_Msk (0x01UL << SCU_SFSP3_4_EPD_Pos) /*!< SCU SFSP3_4: EPD Mask */\r
-#define SCU_SFSP3_4_EPUN_Pos 4 /*!< SCU SFSP3_4: EPUN Position */\r
-#define SCU_SFSP3_4_EPUN_Msk (0x01UL << SCU_SFSP3_4_EPUN_Pos) /*!< SCU SFSP3_4: EPUN Mask */\r
-#define SCU_SFSP3_4_EHS_Pos 5 /*!< SCU SFSP3_4: EHS Position */\r
-#define SCU_SFSP3_4_EHS_Msk (0x01UL << SCU_SFSP3_4_EHS_Pos) /*!< SCU SFSP3_4: EHS Mask */\r
-#define SCU_SFSP3_4_EZI_Pos 6 /*!< SCU SFSP3_4: EZI Position */\r
-#define SCU_SFSP3_4_EZI_Msk (0x01UL << SCU_SFSP3_4_EZI_Pos) /*!< SCU SFSP3_4: EZI Mask */\r
-#define SCU_SFSP3_4_EHD_Pos 8 /*!< SCU SFSP3_4: EHD Position */\r
-#define SCU_SFSP3_4_EHD_Msk (0x03UL << SCU_SFSP3_4_EHD_Pos) /*!< SCU SFSP3_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP3_5 ------------------------------------------\r
-#define SCU_SFSP3_5_MODE_Pos 0 /*!< SCU SFSP3_5: MODE Position */\r
-#define SCU_SFSP3_5_MODE_Msk (0x07UL << SCU_SFSP3_5_MODE_Pos) /*!< SCU SFSP3_5: MODE Mask */\r
-#define SCU_SFSP3_5_EPD_Pos 3 /*!< SCU SFSP3_5: EPD Position */\r
-#define SCU_SFSP3_5_EPD_Msk (0x01UL << SCU_SFSP3_5_EPD_Pos) /*!< SCU SFSP3_5: EPD Mask */\r
-#define SCU_SFSP3_5_EPUN_Pos 4 /*!< SCU SFSP3_5: EPUN Position */\r
-#define SCU_SFSP3_5_EPUN_Msk (0x01UL << SCU_SFSP3_5_EPUN_Pos) /*!< SCU SFSP3_5: EPUN Mask */\r
-#define SCU_SFSP3_5_EHS_Pos 5 /*!< SCU SFSP3_5: EHS Position */\r
-#define SCU_SFSP3_5_EHS_Msk (0x01UL << SCU_SFSP3_5_EHS_Pos) /*!< SCU SFSP3_5: EHS Mask */\r
-#define SCU_SFSP3_5_EZI_Pos 6 /*!< SCU SFSP3_5: EZI Position */\r
-#define SCU_SFSP3_5_EZI_Msk (0x01UL << SCU_SFSP3_5_EZI_Pos) /*!< SCU SFSP3_5: EZI Mask */\r
-#define SCU_SFSP3_5_EHD_Pos 8 /*!< SCU SFSP3_5: EHD Position */\r
-#define SCU_SFSP3_5_EHD_Msk (0x03UL << SCU_SFSP3_5_EHD_Pos) /*!< SCU SFSP3_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP3_6 ------------------------------------------\r
-#define SCU_SFSP3_6_MODE_Pos 0 /*!< SCU SFSP3_6: MODE Position */\r
-#define SCU_SFSP3_6_MODE_Msk (0x07UL << SCU_SFSP3_6_MODE_Pos) /*!< SCU SFSP3_6: MODE Mask */\r
-#define SCU_SFSP3_6_EPD_Pos 3 /*!< SCU SFSP3_6: EPD Position */\r
-#define SCU_SFSP3_6_EPD_Msk (0x01UL << SCU_SFSP3_6_EPD_Pos) /*!< SCU SFSP3_6: EPD Mask */\r
-#define SCU_SFSP3_6_EPUN_Pos 4 /*!< SCU SFSP3_6: EPUN Position */\r
-#define SCU_SFSP3_6_EPUN_Msk (0x01UL << SCU_SFSP3_6_EPUN_Pos) /*!< SCU SFSP3_6: EPUN Mask */\r
-#define SCU_SFSP3_6_EHS_Pos 5 /*!< SCU SFSP3_6: EHS Position */\r
-#define SCU_SFSP3_6_EHS_Msk (0x01UL << SCU_SFSP3_6_EHS_Pos) /*!< SCU SFSP3_6: EHS Mask */\r
-#define SCU_SFSP3_6_EZI_Pos 6 /*!< SCU SFSP3_6: EZI Position */\r
-#define SCU_SFSP3_6_EZI_Msk (0x01UL << SCU_SFSP3_6_EZI_Pos) /*!< SCU SFSP3_6: EZI Mask */\r
-#define SCU_SFSP3_6_EHD_Pos 8 /*!< SCU SFSP3_6: EHD Position */\r
-#define SCU_SFSP3_6_EHD_Msk (0x03UL << SCU_SFSP3_6_EHD_Pos) /*!< SCU SFSP3_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP3_7 ------------------------------------------\r
-#define SCU_SFSP3_7_MODE_Pos 0 /*!< SCU SFSP3_7: MODE Position */\r
-#define SCU_SFSP3_7_MODE_Msk (0x07UL << SCU_SFSP3_7_MODE_Pos) /*!< SCU SFSP3_7: MODE Mask */\r
-#define SCU_SFSP3_7_EPD_Pos 3 /*!< SCU SFSP3_7: EPD Position */\r
-#define SCU_SFSP3_7_EPD_Msk (0x01UL << SCU_SFSP3_7_EPD_Pos) /*!< SCU SFSP3_7: EPD Mask */\r
-#define SCU_SFSP3_7_EPUN_Pos 4 /*!< SCU SFSP3_7: EPUN Position */\r
-#define SCU_SFSP3_7_EPUN_Msk (0x01UL << SCU_SFSP3_7_EPUN_Pos) /*!< SCU SFSP3_7: EPUN Mask */\r
-#define SCU_SFSP3_7_EHS_Pos 5 /*!< SCU SFSP3_7: EHS Position */\r
-#define SCU_SFSP3_7_EHS_Msk (0x01UL << SCU_SFSP3_7_EHS_Pos) /*!< SCU SFSP3_7: EHS Mask */\r
-#define SCU_SFSP3_7_EZI_Pos 6 /*!< SCU SFSP3_7: EZI Position */\r
-#define SCU_SFSP3_7_EZI_Msk (0x01UL << SCU_SFSP3_7_EZI_Pos) /*!< SCU SFSP3_7: EZI Mask */\r
-#define SCU_SFSP3_7_EHD_Pos 8 /*!< SCU SFSP3_7: EHD Position */\r
-#define SCU_SFSP3_7_EHD_Msk (0x03UL << SCU_SFSP3_7_EHD_Pos) /*!< SCU SFSP3_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP3_8 ------------------------------------------\r
-#define SCU_SFSP3_8_MODE_Pos 0 /*!< SCU SFSP3_8: MODE Position */\r
-#define SCU_SFSP3_8_MODE_Msk (0x07UL << SCU_SFSP3_8_MODE_Pos) /*!< SCU SFSP3_8: MODE Mask */\r
-#define SCU_SFSP3_8_EPD_Pos 3 /*!< SCU SFSP3_8: EPD Position */\r
-#define SCU_SFSP3_8_EPD_Msk (0x01UL << SCU_SFSP3_8_EPD_Pos) /*!< SCU SFSP3_8: EPD Mask */\r
-#define SCU_SFSP3_8_EPUN_Pos 4 /*!< SCU SFSP3_8: EPUN Position */\r
-#define SCU_SFSP3_8_EPUN_Msk (0x01UL << SCU_SFSP3_8_EPUN_Pos) /*!< SCU SFSP3_8: EPUN Mask */\r
-#define SCU_SFSP3_8_EHS_Pos 5 /*!< SCU SFSP3_8: EHS Position */\r
-#define SCU_SFSP3_8_EHS_Msk (0x01UL << SCU_SFSP3_8_EHS_Pos) /*!< SCU SFSP3_8: EHS Mask */\r
-#define SCU_SFSP3_8_EZI_Pos 6 /*!< SCU SFSP3_8: EZI Position */\r
-#define SCU_SFSP3_8_EZI_Msk (0x01UL << SCU_SFSP3_8_EZI_Pos) /*!< SCU SFSP3_8: EZI Mask */\r
-#define SCU_SFSP3_8_EHD_Pos 8 /*!< SCU SFSP3_8: EHD Position */\r
-#define SCU_SFSP3_8_EHD_Msk (0x03UL << SCU_SFSP3_8_EHD_Pos) /*!< SCU SFSP3_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_0 ------------------------------------------\r
-#define SCU_SFSP4_0_MODE_Pos 0 /*!< SCU SFSP4_0: MODE Position */\r
-#define SCU_SFSP4_0_MODE_Msk (0x07UL << SCU_SFSP4_0_MODE_Pos) /*!< SCU SFSP4_0: MODE Mask */\r
-#define SCU_SFSP4_0_EPD_Pos 3 /*!< SCU SFSP4_0: EPD Position */\r
-#define SCU_SFSP4_0_EPD_Msk (0x01UL << SCU_SFSP4_0_EPD_Pos) /*!< SCU SFSP4_0: EPD Mask */\r
-#define SCU_SFSP4_0_EPUN_Pos 4 /*!< SCU SFSP4_0: EPUN Position */\r
-#define SCU_SFSP4_0_EPUN_Msk (0x01UL << SCU_SFSP4_0_EPUN_Pos) /*!< SCU SFSP4_0: EPUN Mask */\r
-#define SCU_SFSP4_0_EHS_Pos 5 /*!< SCU SFSP4_0: EHS Position */\r
-#define SCU_SFSP4_0_EHS_Msk (0x01UL << SCU_SFSP4_0_EHS_Pos) /*!< SCU SFSP4_0: EHS Mask */\r
-#define SCU_SFSP4_0_EZI_Pos 6 /*!< SCU SFSP4_0: EZI Position */\r
-#define SCU_SFSP4_0_EZI_Msk (0x01UL << SCU_SFSP4_0_EZI_Pos) /*!< SCU SFSP4_0: EZI Mask */\r
-#define SCU_SFSP4_0_EHD_Pos 8 /*!< SCU SFSP4_0: EHD Position */\r
-#define SCU_SFSP4_0_EHD_Msk (0x03UL << SCU_SFSP4_0_EHD_Pos) /*!< SCU SFSP4_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_1 ------------------------------------------\r
-#define SCU_SFSP4_1_MODE_Pos 0 /*!< SCU SFSP4_1: MODE Position */\r
-#define SCU_SFSP4_1_MODE_Msk (0x07UL << SCU_SFSP4_1_MODE_Pos) /*!< SCU SFSP4_1: MODE Mask */\r
-#define SCU_SFSP4_1_EPD_Pos 3 /*!< SCU SFSP4_1: EPD Position */\r
-#define SCU_SFSP4_1_EPD_Msk (0x01UL << SCU_SFSP4_1_EPD_Pos) /*!< SCU SFSP4_1: EPD Mask */\r
-#define SCU_SFSP4_1_EPUN_Pos 4 /*!< SCU SFSP4_1: EPUN Position */\r
-#define SCU_SFSP4_1_EPUN_Msk (0x01UL << SCU_SFSP4_1_EPUN_Pos) /*!< SCU SFSP4_1: EPUN Mask */\r
-#define SCU_SFSP4_1_EHS_Pos 5 /*!< SCU SFSP4_1: EHS Position */\r
-#define SCU_SFSP4_1_EHS_Msk (0x01UL << SCU_SFSP4_1_EHS_Pos) /*!< SCU SFSP4_1: EHS Mask */\r
-#define SCU_SFSP4_1_EZI_Pos 6 /*!< SCU SFSP4_1: EZI Position */\r
-#define SCU_SFSP4_1_EZI_Msk (0x01UL << SCU_SFSP4_1_EZI_Pos) /*!< SCU SFSP4_1: EZI Mask */\r
-#define SCU_SFSP4_1_EHD_Pos 8 /*!< SCU SFSP4_1: EHD Position */\r
-#define SCU_SFSP4_1_EHD_Msk (0x03UL << SCU_SFSP4_1_EHD_Pos) /*!< SCU SFSP4_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_2 ------------------------------------------\r
-#define SCU_SFSP4_2_MODE_Pos 0 /*!< SCU SFSP4_2: MODE Position */\r
-#define SCU_SFSP4_2_MODE_Msk (0x07UL << SCU_SFSP4_2_MODE_Pos) /*!< SCU SFSP4_2: MODE Mask */\r
-#define SCU_SFSP4_2_EPD_Pos 3 /*!< SCU SFSP4_2: EPD Position */\r
-#define SCU_SFSP4_2_EPD_Msk (0x01UL << SCU_SFSP4_2_EPD_Pos) /*!< SCU SFSP4_2: EPD Mask */\r
-#define SCU_SFSP4_2_EPUN_Pos 4 /*!< SCU SFSP4_2: EPUN Position */\r
-#define SCU_SFSP4_2_EPUN_Msk (0x01UL << SCU_SFSP4_2_EPUN_Pos) /*!< SCU SFSP4_2: EPUN Mask */\r
-#define SCU_SFSP4_2_EHS_Pos 5 /*!< SCU SFSP4_2: EHS Position */\r
-#define SCU_SFSP4_2_EHS_Msk (0x01UL << SCU_SFSP4_2_EHS_Pos) /*!< SCU SFSP4_2: EHS Mask */\r
-#define SCU_SFSP4_2_EZI_Pos 6 /*!< SCU SFSP4_2: EZI Position */\r
-#define SCU_SFSP4_2_EZI_Msk (0x01UL << SCU_SFSP4_2_EZI_Pos) /*!< SCU SFSP4_2: EZI Mask */\r
-#define SCU_SFSP4_2_EHD_Pos 8 /*!< SCU SFSP4_2: EHD Position */\r
-#define SCU_SFSP4_2_EHD_Msk (0x03UL << SCU_SFSP4_2_EHD_Pos) /*!< SCU SFSP4_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_3 ------------------------------------------\r
-#define SCU_SFSP4_3_MODE_Pos 0 /*!< SCU SFSP4_3: MODE Position */\r
-#define SCU_SFSP4_3_MODE_Msk (0x07UL << SCU_SFSP4_3_MODE_Pos) /*!< SCU SFSP4_3: MODE Mask */\r
-#define SCU_SFSP4_3_EPD_Pos 3 /*!< SCU SFSP4_3: EPD Position */\r
-#define SCU_SFSP4_3_EPD_Msk (0x01UL << SCU_SFSP4_3_EPD_Pos) /*!< SCU SFSP4_3: EPD Mask */\r
-#define SCU_SFSP4_3_EPUN_Pos 4 /*!< SCU SFSP4_3: EPUN Position */\r
-#define SCU_SFSP4_3_EPUN_Msk (0x01UL << SCU_SFSP4_3_EPUN_Pos) /*!< SCU SFSP4_3: EPUN Mask */\r
-#define SCU_SFSP4_3_EHS_Pos 5 /*!< SCU SFSP4_3: EHS Position */\r
-#define SCU_SFSP4_3_EHS_Msk (0x01UL << SCU_SFSP4_3_EHS_Pos) /*!< SCU SFSP4_3: EHS Mask */\r
-#define SCU_SFSP4_3_EZI_Pos 6 /*!< SCU SFSP4_3: EZI Position */\r
-#define SCU_SFSP4_3_EZI_Msk (0x01UL << SCU_SFSP4_3_EZI_Pos) /*!< SCU SFSP4_3: EZI Mask */\r
-#define SCU_SFSP4_3_EHD_Pos 8 /*!< SCU SFSP4_3: EHD Position */\r
-#define SCU_SFSP4_3_EHD_Msk (0x03UL << SCU_SFSP4_3_EHD_Pos) /*!< SCU SFSP4_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_4 ------------------------------------------\r
-#define SCU_SFSP4_4_MODE_Pos 0 /*!< SCU SFSP4_4: MODE Position */\r
-#define SCU_SFSP4_4_MODE_Msk (0x07UL << SCU_SFSP4_4_MODE_Pos) /*!< SCU SFSP4_4: MODE Mask */\r
-#define SCU_SFSP4_4_EPD_Pos 3 /*!< SCU SFSP4_4: EPD Position */\r
-#define SCU_SFSP4_4_EPD_Msk (0x01UL << SCU_SFSP4_4_EPD_Pos) /*!< SCU SFSP4_4: EPD Mask */\r
-#define SCU_SFSP4_4_EPUN_Pos 4 /*!< SCU SFSP4_4: EPUN Position */\r
-#define SCU_SFSP4_4_EPUN_Msk (0x01UL << SCU_SFSP4_4_EPUN_Pos) /*!< SCU SFSP4_4: EPUN Mask */\r
-#define SCU_SFSP4_4_EHS_Pos 5 /*!< SCU SFSP4_4: EHS Position */\r
-#define SCU_SFSP4_4_EHS_Msk (0x01UL << SCU_SFSP4_4_EHS_Pos) /*!< SCU SFSP4_4: EHS Mask */\r
-#define SCU_SFSP4_4_EZI_Pos 6 /*!< SCU SFSP4_4: EZI Position */\r
-#define SCU_SFSP4_4_EZI_Msk (0x01UL << SCU_SFSP4_4_EZI_Pos) /*!< SCU SFSP4_4: EZI Mask */\r
-#define SCU_SFSP4_4_EHD_Pos 8 /*!< SCU SFSP4_4: EHD Position */\r
-#define SCU_SFSP4_4_EHD_Msk (0x03UL << SCU_SFSP4_4_EHD_Pos) /*!< SCU SFSP4_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_5 ------------------------------------------\r
-#define SCU_SFSP4_5_MODE_Pos 0 /*!< SCU SFSP4_5: MODE Position */\r
-#define SCU_SFSP4_5_MODE_Msk (0x07UL << SCU_SFSP4_5_MODE_Pos) /*!< SCU SFSP4_5: MODE Mask */\r
-#define SCU_SFSP4_5_EPD_Pos 3 /*!< SCU SFSP4_5: EPD Position */\r
-#define SCU_SFSP4_5_EPD_Msk (0x01UL << SCU_SFSP4_5_EPD_Pos) /*!< SCU SFSP4_5: EPD Mask */\r
-#define SCU_SFSP4_5_EPUN_Pos 4 /*!< SCU SFSP4_5: EPUN Position */\r
-#define SCU_SFSP4_5_EPUN_Msk (0x01UL << SCU_SFSP4_5_EPUN_Pos) /*!< SCU SFSP4_5: EPUN Mask */\r
-#define SCU_SFSP4_5_EHS_Pos 5 /*!< SCU SFSP4_5: EHS Position */\r
-#define SCU_SFSP4_5_EHS_Msk (0x01UL << SCU_SFSP4_5_EHS_Pos) /*!< SCU SFSP4_5: EHS Mask */\r
-#define SCU_SFSP4_5_EZI_Pos 6 /*!< SCU SFSP4_5: EZI Position */\r
-#define SCU_SFSP4_5_EZI_Msk (0x01UL << SCU_SFSP4_5_EZI_Pos) /*!< SCU SFSP4_5: EZI Mask */\r
-#define SCU_SFSP4_5_EHD_Pos 8 /*!< SCU SFSP4_5: EHD Position */\r
-#define SCU_SFSP4_5_EHD_Msk (0x03UL << SCU_SFSP4_5_EHD_Pos) /*!< SCU SFSP4_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_6 ------------------------------------------\r
-#define SCU_SFSP4_6_MODE_Pos 0 /*!< SCU SFSP4_6: MODE Position */\r
-#define SCU_SFSP4_6_MODE_Msk (0x07UL << SCU_SFSP4_6_MODE_Pos) /*!< SCU SFSP4_6: MODE Mask */\r
-#define SCU_SFSP4_6_EPD_Pos 3 /*!< SCU SFSP4_6: EPD Position */\r
-#define SCU_SFSP4_6_EPD_Msk (0x01UL << SCU_SFSP4_6_EPD_Pos) /*!< SCU SFSP4_6: EPD Mask */\r
-#define SCU_SFSP4_6_EPUN_Pos 4 /*!< SCU SFSP4_6: EPUN Position */\r
-#define SCU_SFSP4_6_EPUN_Msk (0x01UL << SCU_SFSP4_6_EPUN_Pos) /*!< SCU SFSP4_6: EPUN Mask */\r
-#define SCU_SFSP4_6_EHS_Pos 5 /*!< SCU SFSP4_6: EHS Position */\r
-#define SCU_SFSP4_6_EHS_Msk (0x01UL << SCU_SFSP4_6_EHS_Pos) /*!< SCU SFSP4_6: EHS Mask */\r
-#define SCU_SFSP4_6_EZI_Pos 6 /*!< SCU SFSP4_6: EZI Position */\r
-#define SCU_SFSP4_6_EZI_Msk (0x01UL << SCU_SFSP4_6_EZI_Pos) /*!< SCU SFSP4_6: EZI Mask */\r
-#define SCU_SFSP4_6_EHD_Pos 8 /*!< SCU SFSP4_6: EHD Position */\r
-#define SCU_SFSP4_6_EHD_Msk (0x03UL << SCU_SFSP4_6_EHD_Pos) /*!< SCU SFSP4_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_7 ------------------------------------------\r
-#define SCU_SFSP4_7_MODE_Pos 0 /*!< SCU SFSP4_7: MODE Position */\r
-#define SCU_SFSP4_7_MODE_Msk (0x07UL << SCU_SFSP4_7_MODE_Pos) /*!< SCU SFSP4_7: MODE Mask */\r
-#define SCU_SFSP4_7_EPD_Pos 3 /*!< SCU SFSP4_7: EPD Position */\r
-#define SCU_SFSP4_7_EPD_Msk (0x01UL << SCU_SFSP4_7_EPD_Pos) /*!< SCU SFSP4_7: EPD Mask */\r
-#define SCU_SFSP4_7_EPUN_Pos 4 /*!< SCU SFSP4_7: EPUN Position */\r
-#define SCU_SFSP4_7_EPUN_Msk (0x01UL << SCU_SFSP4_7_EPUN_Pos) /*!< SCU SFSP4_7: EPUN Mask */\r
-#define SCU_SFSP4_7_EHS_Pos 5 /*!< SCU SFSP4_7: EHS Position */\r
-#define SCU_SFSP4_7_EHS_Msk (0x01UL << SCU_SFSP4_7_EHS_Pos) /*!< SCU SFSP4_7: EHS Mask */\r
-#define SCU_SFSP4_7_EZI_Pos 6 /*!< SCU SFSP4_7: EZI Position */\r
-#define SCU_SFSP4_7_EZI_Msk (0x01UL << SCU_SFSP4_7_EZI_Pos) /*!< SCU SFSP4_7: EZI Mask */\r
-#define SCU_SFSP4_7_EHD_Pos 8 /*!< SCU SFSP4_7: EHD Position */\r
-#define SCU_SFSP4_7_EHD_Msk (0x03UL << SCU_SFSP4_7_EHD_Pos) /*!< SCU SFSP4_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_8 ------------------------------------------\r
-#define SCU_SFSP4_8_MODE_Pos 0 /*!< SCU SFSP4_8: MODE Position */\r
-#define SCU_SFSP4_8_MODE_Msk (0x07UL << SCU_SFSP4_8_MODE_Pos) /*!< SCU SFSP4_8: MODE Mask */\r
-#define SCU_SFSP4_8_EPD_Pos 3 /*!< SCU SFSP4_8: EPD Position */\r
-#define SCU_SFSP4_8_EPD_Msk (0x01UL << SCU_SFSP4_8_EPD_Pos) /*!< SCU SFSP4_8: EPD Mask */\r
-#define SCU_SFSP4_8_EPUN_Pos 4 /*!< SCU SFSP4_8: EPUN Position */\r
-#define SCU_SFSP4_8_EPUN_Msk (0x01UL << SCU_SFSP4_8_EPUN_Pos) /*!< SCU SFSP4_8: EPUN Mask */\r
-#define SCU_SFSP4_8_EHS_Pos 5 /*!< SCU SFSP4_8: EHS Position */\r
-#define SCU_SFSP4_8_EHS_Msk (0x01UL << SCU_SFSP4_8_EHS_Pos) /*!< SCU SFSP4_8: EHS Mask */\r
-#define SCU_SFSP4_8_EZI_Pos 6 /*!< SCU SFSP4_8: EZI Position */\r
-#define SCU_SFSP4_8_EZI_Msk (0x01UL << SCU_SFSP4_8_EZI_Pos) /*!< SCU SFSP4_8: EZI Mask */\r
-#define SCU_SFSP4_8_EHD_Pos 8 /*!< SCU SFSP4_8: EHD Position */\r
-#define SCU_SFSP4_8_EHD_Msk (0x03UL << SCU_SFSP4_8_EHD_Pos) /*!< SCU SFSP4_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP4_9 ------------------------------------------\r
-#define SCU_SFSP4_9_MODE_Pos 0 /*!< SCU SFSP4_9: MODE Position */\r
-#define SCU_SFSP4_9_MODE_Msk (0x07UL << SCU_SFSP4_9_MODE_Pos) /*!< SCU SFSP4_9: MODE Mask */\r
-#define SCU_SFSP4_9_EPD_Pos 3 /*!< SCU SFSP4_9: EPD Position */\r
-#define SCU_SFSP4_9_EPD_Msk (0x01UL << SCU_SFSP4_9_EPD_Pos) /*!< SCU SFSP4_9: EPD Mask */\r
-#define SCU_SFSP4_9_EPUN_Pos 4 /*!< SCU SFSP4_9: EPUN Position */\r
-#define SCU_SFSP4_9_EPUN_Msk (0x01UL << SCU_SFSP4_9_EPUN_Pos) /*!< SCU SFSP4_9: EPUN Mask */\r
-#define SCU_SFSP4_9_EHS_Pos 5 /*!< SCU SFSP4_9: EHS Position */\r
-#define SCU_SFSP4_9_EHS_Msk (0x01UL << SCU_SFSP4_9_EHS_Pos) /*!< SCU SFSP4_9: EHS Mask */\r
-#define SCU_SFSP4_9_EZI_Pos 6 /*!< SCU SFSP4_9: EZI Position */\r
-#define SCU_SFSP4_9_EZI_Msk (0x01UL << SCU_SFSP4_9_EZI_Pos) /*!< SCU SFSP4_9: EZI Mask */\r
-#define SCU_SFSP4_9_EHD_Pos 8 /*!< SCU SFSP4_9: EHD Position */\r
-#define SCU_SFSP4_9_EHD_Msk (0x03UL << SCU_SFSP4_9_EHD_Pos) /*!< SCU SFSP4_9: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP4_10 ------------------------------------------\r
-#define SCU_SFSP4_10_MODE_Pos 0 /*!< SCU SFSP4_10: MODE Position */\r
-#define SCU_SFSP4_10_MODE_Msk (0x07UL << SCU_SFSP4_10_MODE_Pos) /*!< SCU SFSP4_10: MODE Mask */\r
-#define SCU_SFSP4_10_EPD_Pos 3 /*!< SCU SFSP4_10: EPD Position */\r
-#define SCU_SFSP4_10_EPD_Msk (0x01UL << SCU_SFSP4_10_EPD_Pos) /*!< SCU SFSP4_10: EPD Mask */\r
-#define SCU_SFSP4_10_EPUN_Pos 4 /*!< SCU SFSP4_10: EPUN Position */\r
-#define SCU_SFSP4_10_EPUN_Msk (0x01UL << SCU_SFSP4_10_EPUN_Pos) /*!< SCU SFSP4_10: EPUN Mask */\r
-#define SCU_SFSP4_10_EHS_Pos 5 /*!< SCU SFSP4_10: EHS Position */\r
-#define SCU_SFSP4_10_EHS_Msk (0x01UL << SCU_SFSP4_10_EHS_Pos) /*!< SCU SFSP4_10: EHS Mask */\r
-#define SCU_SFSP4_10_EZI_Pos 6 /*!< SCU SFSP4_10: EZI Position */\r
-#define SCU_SFSP4_10_EZI_Msk (0x01UL << SCU_SFSP4_10_EZI_Pos) /*!< SCU SFSP4_10: EZI Mask */\r
-#define SCU_SFSP4_10_EHD_Pos 8 /*!< SCU SFSP4_10: EHD Position */\r
-#define SCU_SFSP4_10_EHD_Msk (0x03UL << SCU_SFSP4_10_EHD_Pos) /*!< SCU SFSP4_10: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP5_0 ------------------------------------------\r
-#define SCU_SFSP5_0_MODE_Pos 0 /*!< SCU SFSP5_0: MODE Position */\r
-#define SCU_SFSP5_0_MODE_Msk (0x07UL << SCU_SFSP5_0_MODE_Pos) /*!< SCU SFSP5_0: MODE Mask */\r
-#define SCU_SFSP5_0_EPD_Pos 3 /*!< SCU SFSP5_0: EPD Position */\r
-#define SCU_SFSP5_0_EPD_Msk (0x01UL << SCU_SFSP5_0_EPD_Pos) /*!< SCU SFSP5_0: EPD Mask */\r
-#define SCU_SFSP5_0_EPUN_Pos 4 /*!< SCU SFSP5_0: EPUN Position */\r
-#define SCU_SFSP5_0_EPUN_Msk (0x01UL << SCU_SFSP5_0_EPUN_Pos) /*!< SCU SFSP5_0: EPUN Mask */\r
-#define SCU_SFSP5_0_EHS_Pos 5 /*!< SCU SFSP5_0: EHS Position */\r
-#define SCU_SFSP5_0_EHS_Msk (0x01UL << SCU_SFSP5_0_EHS_Pos) /*!< SCU SFSP5_0: EHS Mask */\r
-#define SCU_SFSP5_0_EZI_Pos 6 /*!< SCU SFSP5_0: EZI Position */\r
-#define SCU_SFSP5_0_EZI_Msk (0x01UL << SCU_SFSP5_0_EZI_Pos) /*!< SCU SFSP5_0: EZI Mask */\r
-#define SCU_SFSP5_0_EHD_Pos 8 /*!< SCU SFSP5_0: EHD Position */\r
-#define SCU_SFSP5_0_EHD_Msk (0x03UL << SCU_SFSP5_0_EHD_Pos) /*!< SCU SFSP5_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP5_1 ------------------------------------------\r
-#define SCU_SFSP5_1_MODE_Pos 0 /*!< SCU SFSP5_1: MODE Position */\r
-#define SCU_SFSP5_1_MODE_Msk (0x07UL << SCU_SFSP5_1_MODE_Pos) /*!< SCU SFSP5_1: MODE Mask */\r
-#define SCU_SFSP5_1_EPD_Pos 3 /*!< SCU SFSP5_1: EPD Position */\r
-#define SCU_SFSP5_1_EPD_Msk (0x01UL << SCU_SFSP5_1_EPD_Pos) /*!< SCU SFSP5_1: EPD Mask */\r
-#define SCU_SFSP5_1_EPUN_Pos 4 /*!< SCU SFSP5_1: EPUN Position */\r
-#define SCU_SFSP5_1_EPUN_Msk (0x01UL << SCU_SFSP5_1_EPUN_Pos) /*!< SCU SFSP5_1: EPUN Mask */\r
-#define SCU_SFSP5_1_EHS_Pos 5 /*!< SCU SFSP5_1: EHS Position */\r
-#define SCU_SFSP5_1_EHS_Msk (0x01UL << SCU_SFSP5_1_EHS_Pos) /*!< SCU SFSP5_1: EHS Mask */\r
-#define SCU_SFSP5_1_EZI_Pos 6 /*!< SCU SFSP5_1: EZI Position */\r
-#define SCU_SFSP5_1_EZI_Msk (0x01UL << SCU_SFSP5_1_EZI_Pos) /*!< SCU SFSP5_1: EZI Mask */\r
-#define SCU_SFSP5_1_EHD_Pos 8 /*!< SCU SFSP5_1: EHD Position */\r
-#define SCU_SFSP5_1_EHD_Msk (0x03UL << SCU_SFSP5_1_EHD_Pos) /*!< SCU SFSP5_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP5_2 ------------------------------------------\r
-#define SCU_SFSP5_2_MODE_Pos 0 /*!< SCU SFSP5_2: MODE Position */\r
-#define SCU_SFSP5_2_MODE_Msk (0x07UL << SCU_SFSP5_2_MODE_Pos) /*!< SCU SFSP5_2: MODE Mask */\r
-#define SCU_SFSP5_2_EPD_Pos 3 /*!< SCU SFSP5_2: EPD Position */\r
-#define SCU_SFSP5_2_EPD_Msk (0x01UL << SCU_SFSP5_2_EPD_Pos) /*!< SCU SFSP5_2: EPD Mask */\r
-#define SCU_SFSP5_2_EPUN_Pos 4 /*!< SCU SFSP5_2: EPUN Position */\r
-#define SCU_SFSP5_2_EPUN_Msk (0x01UL << SCU_SFSP5_2_EPUN_Pos) /*!< SCU SFSP5_2: EPUN Mask */\r
-#define SCU_SFSP5_2_EHS_Pos 5 /*!< SCU SFSP5_2: EHS Position */\r
-#define SCU_SFSP5_2_EHS_Msk (0x01UL << SCU_SFSP5_2_EHS_Pos) /*!< SCU SFSP5_2: EHS Mask */\r
-#define SCU_SFSP5_2_EZI_Pos 6 /*!< SCU SFSP5_2: EZI Position */\r
-#define SCU_SFSP5_2_EZI_Msk (0x01UL << SCU_SFSP5_2_EZI_Pos) /*!< SCU SFSP5_2: EZI Mask */\r
-#define SCU_SFSP5_2_EHD_Pos 8 /*!< SCU SFSP5_2: EHD Position */\r
-#define SCU_SFSP5_2_EHD_Msk (0x03UL << SCU_SFSP5_2_EHD_Pos) /*!< SCU SFSP5_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP5_3 ------------------------------------------\r
-#define SCU_SFSP5_3_MODE_Pos 0 /*!< SCU SFSP5_3: MODE Position */\r
-#define SCU_SFSP5_3_MODE_Msk (0x07UL << SCU_SFSP5_3_MODE_Pos) /*!< SCU SFSP5_3: MODE Mask */\r
-#define SCU_SFSP5_3_EPD_Pos 3 /*!< SCU SFSP5_3: EPD Position */\r
-#define SCU_SFSP5_3_EPD_Msk (0x01UL << SCU_SFSP5_3_EPD_Pos) /*!< SCU SFSP5_3: EPD Mask */\r
-#define SCU_SFSP5_3_EPUN_Pos 4 /*!< SCU SFSP5_3: EPUN Position */\r
-#define SCU_SFSP5_3_EPUN_Msk (0x01UL << SCU_SFSP5_3_EPUN_Pos) /*!< SCU SFSP5_3: EPUN Mask */\r
-#define SCU_SFSP5_3_EHS_Pos 5 /*!< SCU SFSP5_3: EHS Position */\r
-#define SCU_SFSP5_3_EHS_Msk (0x01UL << SCU_SFSP5_3_EHS_Pos) /*!< SCU SFSP5_3: EHS Mask */\r
-#define SCU_SFSP5_3_EZI_Pos 6 /*!< SCU SFSP5_3: EZI Position */\r
-#define SCU_SFSP5_3_EZI_Msk (0x01UL << SCU_SFSP5_3_EZI_Pos) /*!< SCU SFSP5_3: EZI Mask */\r
-#define SCU_SFSP5_3_EHD_Pos 8 /*!< SCU SFSP5_3: EHD Position */\r
-#define SCU_SFSP5_3_EHD_Msk (0x03UL << SCU_SFSP5_3_EHD_Pos) /*!< SCU SFSP5_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP5_4 ------------------------------------------\r
-#define SCU_SFSP5_4_MODE_Pos 0 /*!< SCU SFSP5_4: MODE Position */\r
-#define SCU_SFSP5_4_MODE_Msk (0x07UL << SCU_SFSP5_4_MODE_Pos) /*!< SCU SFSP5_4: MODE Mask */\r
-#define SCU_SFSP5_4_EPD_Pos 3 /*!< SCU SFSP5_4: EPD Position */\r
-#define SCU_SFSP5_4_EPD_Msk (0x01UL << SCU_SFSP5_4_EPD_Pos) /*!< SCU SFSP5_4: EPD Mask */\r
-#define SCU_SFSP5_4_EPUN_Pos 4 /*!< SCU SFSP5_4: EPUN Position */\r
-#define SCU_SFSP5_4_EPUN_Msk (0x01UL << SCU_SFSP5_4_EPUN_Pos) /*!< SCU SFSP5_4: EPUN Mask */\r
-#define SCU_SFSP5_4_EHS_Pos 5 /*!< SCU SFSP5_4: EHS Position */\r
-#define SCU_SFSP5_4_EHS_Msk (0x01UL << SCU_SFSP5_4_EHS_Pos) /*!< SCU SFSP5_4: EHS Mask */\r
-#define SCU_SFSP5_4_EZI_Pos 6 /*!< SCU SFSP5_4: EZI Position */\r
-#define SCU_SFSP5_4_EZI_Msk (0x01UL << SCU_SFSP5_4_EZI_Pos) /*!< SCU SFSP5_4: EZI Mask */\r
-#define SCU_SFSP5_4_EHD_Pos 8 /*!< SCU SFSP5_4: EHD Position */\r
-#define SCU_SFSP5_4_EHD_Msk (0x03UL << SCU_SFSP5_4_EHD_Pos) /*!< SCU SFSP5_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP5_5 ------------------------------------------\r
-#define SCU_SFSP5_5_MODE_Pos 0 /*!< SCU SFSP5_5: MODE Position */\r
-#define SCU_SFSP5_5_MODE_Msk (0x07UL << SCU_SFSP5_5_MODE_Pos) /*!< SCU SFSP5_5: MODE Mask */\r
-#define SCU_SFSP5_5_EPD_Pos 3 /*!< SCU SFSP5_5: EPD Position */\r
-#define SCU_SFSP5_5_EPD_Msk (0x01UL << SCU_SFSP5_5_EPD_Pos) /*!< SCU SFSP5_5: EPD Mask */\r
-#define SCU_SFSP5_5_EPUN_Pos 4 /*!< SCU SFSP5_5: EPUN Position */\r
-#define SCU_SFSP5_5_EPUN_Msk (0x01UL << SCU_SFSP5_5_EPUN_Pos) /*!< SCU SFSP5_5: EPUN Mask */\r
-#define SCU_SFSP5_5_EHS_Pos 5 /*!< SCU SFSP5_5: EHS Position */\r
-#define SCU_SFSP5_5_EHS_Msk (0x01UL << SCU_SFSP5_5_EHS_Pos) /*!< SCU SFSP5_5: EHS Mask */\r
-#define SCU_SFSP5_5_EZI_Pos 6 /*!< SCU SFSP5_5: EZI Position */\r
-#define SCU_SFSP5_5_EZI_Msk (0x01UL << SCU_SFSP5_5_EZI_Pos) /*!< SCU SFSP5_5: EZI Mask */\r
-#define SCU_SFSP5_5_EHD_Pos 8 /*!< SCU SFSP5_5: EHD Position */\r
-#define SCU_SFSP5_5_EHD_Msk (0x03UL << SCU_SFSP5_5_EHD_Pos) /*!< SCU SFSP5_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP5_6 ------------------------------------------\r
-#define SCU_SFSP5_6_MODE_Pos 0 /*!< SCU SFSP5_6: MODE Position */\r
-#define SCU_SFSP5_6_MODE_Msk (0x07UL << SCU_SFSP5_6_MODE_Pos) /*!< SCU SFSP5_6: MODE Mask */\r
-#define SCU_SFSP5_6_EPD_Pos 3 /*!< SCU SFSP5_6: EPD Position */\r
-#define SCU_SFSP5_6_EPD_Msk (0x01UL << SCU_SFSP5_6_EPD_Pos) /*!< SCU SFSP5_6: EPD Mask */\r
-#define SCU_SFSP5_6_EPUN_Pos 4 /*!< SCU SFSP5_6: EPUN Position */\r
-#define SCU_SFSP5_6_EPUN_Msk (0x01UL << SCU_SFSP5_6_EPUN_Pos) /*!< SCU SFSP5_6: EPUN Mask */\r
-#define SCU_SFSP5_6_EHS_Pos 5 /*!< SCU SFSP5_6: EHS Position */\r
-#define SCU_SFSP5_6_EHS_Msk (0x01UL << SCU_SFSP5_6_EHS_Pos) /*!< SCU SFSP5_6: EHS Mask */\r
-#define SCU_SFSP5_6_EZI_Pos 6 /*!< SCU SFSP5_6: EZI Position */\r
-#define SCU_SFSP5_6_EZI_Msk (0x01UL << SCU_SFSP5_6_EZI_Pos) /*!< SCU SFSP5_6: EZI Mask */\r
-#define SCU_SFSP5_6_EHD_Pos 8 /*!< SCU SFSP5_6: EHD Position */\r
-#define SCU_SFSP5_6_EHD_Msk (0x03UL << SCU_SFSP5_6_EHD_Pos) /*!< SCU SFSP5_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP5_7 ------------------------------------------\r
-#define SCU_SFSP5_7_MODE_Pos 0 /*!< SCU SFSP5_7: MODE Position */\r
-#define SCU_SFSP5_7_MODE_Msk (0x07UL << SCU_SFSP5_7_MODE_Pos) /*!< SCU SFSP5_7: MODE Mask */\r
-#define SCU_SFSP5_7_EPD_Pos 3 /*!< SCU SFSP5_7: EPD Position */\r
-#define SCU_SFSP5_7_EPD_Msk (0x01UL << SCU_SFSP5_7_EPD_Pos) /*!< SCU SFSP5_7: EPD Mask */\r
-#define SCU_SFSP5_7_EPUN_Pos 4 /*!< SCU SFSP5_7: EPUN Position */\r
-#define SCU_SFSP5_7_EPUN_Msk (0x01UL << SCU_SFSP5_7_EPUN_Pos) /*!< SCU SFSP5_7: EPUN Mask */\r
-#define SCU_SFSP5_7_EHS_Pos 5 /*!< SCU SFSP5_7: EHS Position */\r
-#define SCU_SFSP5_7_EHS_Msk (0x01UL << SCU_SFSP5_7_EHS_Pos) /*!< SCU SFSP5_7: EHS Mask */\r
-#define SCU_SFSP5_7_EZI_Pos 6 /*!< SCU SFSP5_7: EZI Position */\r
-#define SCU_SFSP5_7_EZI_Msk (0x01UL << SCU_SFSP5_7_EZI_Pos) /*!< SCU SFSP5_7: EZI Mask */\r
-#define SCU_SFSP5_7_EHD_Pos 8 /*!< SCU SFSP5_7: EHD Position */\r
-#define SCU_SFSP5_7_EHD_Msk (0x03UL << SCU_SFSP5_7_EHD_Pos) /*!< SCU SFSP5_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_0 ------------------------------------------\r
-#define SCU_SFSP6_0_MODE_Pos 0 /*!< SCU SFSP6_0: MODE Position */\r
-#define SCU_SFSP6_0_MODE_Msk (0x07UL << SCU_SFSP6_0_MODE_Pos) /*!< SCU SFSP6_0: MODE Mask */\r
-#define SCU_SFSP6_0_EPD_Pos 3 /*!< SCU SFSP6_0: EPD Position */\r
-#define SCU_SFSP6_0_EPD_Msk (0x01UL << SCU_SFSP6_0_EPD_Pos) /*!< SCU SFSP6_0: EPD Mask */\r
-#define SCU_SFSP6_0_EPUN_Pos 4 /*!< SCU SFSP6_0: EPUN Position */\r
-#define SCU_SFSP6_0_EPUN_Msk (0x01UL << SCU_SFSP6_0_EPUN_Pos) /*!< SCU SFSP6_0: EPUN Mask */\r
-#define SCU_SFSP6_0_EHS_Pos 5 /*!< SCU SFSP6_0: EHS Position */\r
-#define SCU_SFSP6_0_EHS_Msk (0x01UL << SCU_SFSP6_0_EHS_Pos) /*!< SCU SFSP6_0: EHS Mask */\r
-#define SCU_SFSP6_0_EZI_Pos 6 /*!< SCU SFSP6_0: EZI Position */\r
-#define SCU_SFSP6_0_EZI_Msk (0x01UL << SCU_SFSP6_0_EZI_Pos) /*!< SCU SFSP6_0: EZI Mask */\r
-#define SCU_SFSP6_0_EHD_Pos 8 /*!< SCU SFSP6_0: EHD Position */\r
-#define SCU_SFSP6_0_EHD_Msk (0x03UL << SCU_SFSP6_0_EHD_Pos) /*!< SCU SFSP6_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_1 ------------------------------------------\r
-#define SCU_SFSP6_1_MODE_Pos 0 /*!< SCU SFSP6_1: MODE Position */\r
-#define SCU_SFSP6_1_MODE_Msk (0x07UL << SCU_SFSP6_1_MODE_Pos) /*!< SCU SFSP6_1: MODE Mask */\r
-#define SCU_SFSP6_1_EPD_Pos 3 /*!< SCU SFSP6_1: EPD Position */\r
-#define SCU_SFSP6_1_EPD_Msk (0x01UL << SCU_SFSP6_1_EPD_Pos) /*!< SCU SFSP6_1: EPD Mask */\r
-#define SCU_SFSP6_1_EPUN_Pos 4 /*!< SCU SFSP6_1: EPUN Position */\r
-#define SCU_SFSP6_1_EPUN_Msk (0x01UL << SCU_SFSP6_1_EPUN_Pos) /*!< SCU SFSP6_1: EPUN Mask */\r
-#define SCU_SFSP6_1_EHS_Pos 5 /*!< SCU SFSP6_1: EHS Position */\r
-#define SCU_SFSP6_1_EHS_Msk (0x01UL << SCU_SFSP6_1_EHS_Pos) /*!< SCU SFSP6_1: EHS Mask */\r
-#define SCU_SFSP6_1_EZI_Pos 6 /*!< SCU SFSP6_1: EZI Position */\r
-#define SCU_SFSP6_1_EZI_Msk (0x01UL << SCU_SFSP6_1_EZI_Pos) /*!< SCU SFSP6_1: EZI Mask */\r
-#define SCU_SFSP6_1_EHD_Pos 8 /*!< SCU SFSP6_1: EHD Position */\r
-#define SCU_SFSP6_1_EHD_Msk (0x03UL << SCU_SFSP6_1_EHD_Pos) /*!< SCU SFSP6_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_2 ------------------------------------------\r
-#define SCU_SFSP6_2_MODE_Pos 0 /*!< SCU SFSP6_2: MODE Position */\r
-#define SCU_SFSP6_2_MODE_Msk (0x07UL << SCU_SFSP6_2_MODE_Pos) /*!< SCU SFSP6_2: MODE Mask */\r
-#define SCU_SFSP6_2_EPD_Pos 3 /*!< SCU SFSP6_2: EPD Position */\r
-#define SCU_SFSP6_2_EPD_Msk (0x01UL << SCU_SFSP6_2_EPD_Pos) /*!< SCU SFSP6_2: EPD Mask */\r
-#define SCU_SFSP6_2_EPUN_Pos 4 /*!< SCU SFSP6_2: EPUN Position */\r
-#define SCU_SFSP6_2_EPUN_Msk (0x01UL << SCU_SFSP6_2_EPUN_Pos) /*!< SCU SFSP6_2: EPUN Mask */\r
-#define SCU_SFSP6_2_EHS_Pos 5 /*!< SCU SFSP6_2: EHS Position */\r
-#define SCU_SFSP6_2_EHS_Msk (0x01UL << SCU_SFSP6_2_EHS_Pos) /*!< SCU SFSP6_2: EHS Mask */\r
-#define SCU_SFSP6_2_EZI_Pos 6 /*!< SCU SFSP6_2: EZI Position */\r
-#define SCU_SFSP6_2_EZI_Msk (0x01UL << SCU_SFSP6_2_EZI_Pos) /*!< SCU SFSP6_2: EZI Mask */\r
-#define SCU_SFSP6_2_EHD_Pos 8 /*!< SCU SFSP6_2: EHD Position */\r
-#define SCU_SFSP6_2_EHD_Msk (0x03UL << SCU_SFSP6_2_EHD_Pos) /*!< SCU SFSP6_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_3 ------------------------------------------\r
-#define SCU_SFSP6_3_MODE_Pos 0 /*!< SCU SFSP6_3: MODE Position */\r
-#define SCU_SFSP6_3_MODE_Msk (0x07UL << SCU_SFSP6_3_MODE_Pos) /*!< SCU SFSP6_3: MODE Mask */\r
-#define SCU_SFSP6_3_EPD_Pos 3 /*!< SCU SFSP6_3: EPD Position */\r
-#define SCU_SFSP6_3_EPD_Msk (0x01UL << SCU_SFSP6_3_EPD_Pos) /*!< SCU SFSP6_3: EPD Mask */\r
-#define SCU_SFSP6_3_EPUN_Pos 4 /*!< SCU SFSP6_3: EPUN Position */\r
-#define SCU_SFSP6_3_EPUN_Msk (0x01UL << SCU_SFSP6_3_EPUN_Pos) /*!< SCU SFSP6_3: EPUN Mask */\r
-#define SCU_SFSP6_3_EHS_Pos 5 /*!< SCU SFSP6_3: EHS Position */\r
-#define SCU_SFSP6_3_EHS_Msk (0x01UL << SCU_SFSP6_3_EHS_Pos) /*!< SCU SFSP6_3: EHS Mask */\r
-#define SCU_SFSP6_3_EZI_Pos 6 /*!< SCU SFSP6_3: EZI Position */\r
-#define SCU_SFSP6_3_EZI_Msk (0x01UL << SCU_SFSP6_3_EZI_Pos) /*!< SCU SFSP6_3: EZI Mask */\r
-#define SCU_SFSP6_3_EHD_Pos 8 /*!< SCU SFSP6_3: EHD Position */\r
-#define SCU_SFSP6_3_EHD_Msk (0x03UL << SCU_SFSP6_3_EHD_Pos) /*!< SCU SFSP6_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_4 ------------------------------------------\r
-#define SCU_SFSP6_4_MODE_Pos 0 /*!< SCU SFSP6_4: MODE Position */\r
-#define SCU_SFSP6_4_MODE_Msk (0x07UL << SCU_SFSP6_4_MODE_Pos) /*!< SCU SFSP6_4: MODE Mask */\r
-#define SCU_SFSP6_4_EPD_Pos 3 /*!< SCU SFSP6_4: EPD Position */\r
-#define SCU_SFSP6_4_EPD_Msk (0x01UL << SCU_SFSP6_4_EPD_Pos) /*!< SCU SFSP6_4: EPD Mask */\r
-#define SCU_SFSP6_4_EPUN_Pos 4 /*!< SCU SFSP6_4: EPUN Position */\r
-#define SCU_SFSP6_4_EPUN_Msk (0x01UL << SCU_SFSP6_4_EPUN_Pos) /*!< SCU SFSP6_4: EPUN Mask */\r
-#define SCU_SFSP6_4_EHS_Pos 5 /*!< SCU SFSP6_4: EHS Position */\r
-#define SCU_SFSP6_4_EHS_Msk (0x01UL << SCU_SFSP6_4_EHS_Pos) /*!< SCU SFSP6_4: EHS Mask */\r
-#define SCU_SFSP6_4_EZI_Pos 6 /*!< SCU SFSP6_4: EZI Position */\r
-#define SCU_SFSP6_4_EZI_Msk (0x01UL << SCU_SFSP6_4_EZI_Pos) /*!< SCU SFSP6_4: EZI Mask */\r
-#define SCU_SFSP6_4_EHD_Pos 8 /*!< SCU SFSP6_4: EHD Position */\r
-#define SCU_SFSP6_4_EHD_Msk (0x03UL << SCU_SFSP6_4_EHD_Pos) /*!< SCU SFSP6_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_5 ------------------------------------------\r
-#define SCU_SFSP6_5_MODE_Pos 0 /*!< SCU SFSP6_5: MODE Position */\r
-#define SCU_SFSP6_5_MODE_Msk (0x07UL << SCU_SFSP6_5_MODE_Pos) /*!< SCU SFSP6_5: MODE Mask */\r
-#define SCU_SFSP6_5_EPD_Pos 3 /*!< SCU SFSP6_5: EPD Position */\r
-#define SCU_SFSP6_5_EPD_Msk (0x01UL << SCU_SFSP6_5_EPD_Pos) /*!< SCU SFSP6_5: EPD Mask */\r
-#define SCU_SFSP6_5_EPUN_Pos 4 /*!< SCU SFSP6_5: EPUN Position */\r
-#define SCU_SFSP6_5_EPUN_Msk (0x01UL << SCU_SFSP6_5_EPUN_Pos) /*!< SCU SFSP6_5: EPUN Mask */\r
-#define SCU_SFSP6_5_EHS_Pos 5 /*!< SCU SFSP6_5: EHS Position */\r
-#define SCU_SFSP6_5_EHS_Msk (0x01UL << SCU_SFSP6_5_EHS_Pos) /*!< SCU SFSP6_5: EHS Mask */\r
-#define SCU_SFSP6_5_EZI_Pos 6 /*!< SCU SFSP6_5: EZI Position */\r
-#define SCU_SFSP6_5_EZI_Msk (0x01UL << SCU_SFSP6_5_EZI_Pos) /*!< SCU SFSP6_5: EZI Mask */\r
-#define SCU_SFSP6_5_EHD_Pos 8 /*!< SCU SFSP6_5: EHD Position */\r
-#define SCU_SFSP6_5_EHD_Msk (0x03UL << SCU_SFSP6_5_EHD_Pos) /*!< SCU SFSP6_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_6 ------------------------------------------\r
-#define SCU_SFSP6_6_MODE_Pos 0 /*!< SCU SFSP6_6: MODE Position */\r
-#define SCU_SFSP6_6_MODE_Msk (0x07UL << SCU_SFSP6_6_MODE_Pos) /*!< SCU SFSP6_6: MODE Mask */\r
-#define SCU_SFSP6_6_EPD_Pos 3 /*!< SCU SFSP6_6: EPD Position */\r
-#define SCU_SFSP6_6_EPD_Msk (0x01UL << SCU_SFSP6_6_EPD_Pos) /*!< SCU SFSP6_6: EPD Mask */\r
-#define SCU_SFSP6_6_EPUN_Pos 4 /*!< SCU SFSP6_6: EPUN Position */\r
-#define SCU_SFSP6_6_EPUN_Msk (0x01UL << SCU_SFSP6_6_EPUN_Pos) /*!< SCU SFSP6_6: EPUN Mask */\r
-#define SCU_SFSP6_6_EHS_Pos 5 /*!< SCU SFSP6_6: EHS Position */\r
-#define SCU_SFSP6_6_EHS_Msk (0x01UL << SCU_SFSP6_6_EHS_Pos) /*!< SCU SFSP6_6: EHS Mask */\r
-#define SCU_SFSP6_6_EZI_Pos 6 /*!< SCU SFSP6_6: EZI Position */\r
-#define SCU_SFSP6_6_EZI_Msk (0x01UL << SCU_SFSP6_6_EZI_Pos) /*!< SCU SFSP6_6: EZI Mask */\r
-#define SCU_SFSP6_6_EHD_Pos 8 /*!< SCU SFSP6_6: EHD Position */\r
-#define SCU_SFSP6_6_EHD_Msk (0x03UL << SCU_SFSP6_6_EHD_Pos) /*!< SCU SFSP6_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_7 ------------------------------------------\r
-#define SCU_SFSP6_7_MODE_Pos 0 /*!< SCU SFSP6_7: MODE Position */\r
-#define SCU_SFSP6_7_MODE_Msk (0x07UL << SCU_SFSP6_7_MODE_Pos) /*!< SCU SFSP6_7: MODE Mask */\r
-#define SCU_SFSP6_7_EPD_Pos 3 /*!< SCU SFSP6_7: EPD Position */\r
-#define SCU_SFSP6_7_EPD_Msk (0x01UL << SCU_SFSP6_7_EPD_Pos) /*!< SCU SFSP6_7: EPD Mask */\r
-#define SCU_SFSP6_7_EPUN_Pos 4 /*!< SCU SFSP6_7: EPUN Position */\r
-#define SCU_SFSP6_7_EPUN_Msk (0x01UL << SCU_SFSP6_7_EPUN_Pos) /*!< SCU SFSP6_7: EPUN Mask */\r
-#define SCU_SFSP6_7_EHS_Pos 5 /*!< SCU SFSP6_7: EHS Position */\r
-#define SCU_SFSP6_7_EHS_Msk (0x01UL << SCU_SFSP6_7_EHS_Pos) /*!< SCU SFSP6_7: EHS Mask */\r
-#define SCU_SFSP6_7_EZI_Pos 6 /*!< SCU SFSP6_7: EZI Position */\r
-#define SCU_SFSP6_7_EZI_Msk (0x01UL << SCU_SFSP6_7_EZI_Pos) /*!< SCU SFSP6_7: EZI Mask */\r
-#define SCU_SFSP6_7_EHD_Pos 8 /*!< SCU SFSP6_7: EHD Position */\r
-#define SCU_SFSP6_7_EHD_Msk (0x03UL << SCU_SFSP6_7_EHD_Pos) /*!< SCU SFSP6_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_8 ------------------------------------------\r
-#define SCU_SFSP6_8_MODE_Pos 0 /*!< SCU SFSP6_8: MODE Position */\r
-#define SCU_SFSP6_8_MODE_Msk (0x07UL << SCU_SFSP6_8_MODE_Pos) /*!< SCU SFSP6_8: MODE Mask */\r
-#define SCU_SFSP6_8_EPD_Pos 3 /*!< SCU SFSP6_8: EPD Position */\r
-#define SCU_SFSP6_8_EPD_Msk (0x01UL << SCU_SFSP6_8_EPD_Pos) /*!< SCU SFSP6_8: EPD Mask */\r
-#define SCU_SFSP6_8_EPUN_Pos 4 /*!< SCU SFSP6_8: EPUN Position */\r
-#define SCU_SFSP6_8_EPUN_Msk (0x01UL << SCU_SFSP6_8_EPUN_Pos) /*!< SCU SFSP6_8: EPUN Mask */\r
-#define SCU_SFSP6_8_EHS_Pos 5 /*!< SCU SFSP6_8: EHS Position */\r
-#define SCU_SFSP6_8_EHS_Msk (0x01UL << SCU_SFSP6_8_EHS_Pos) /*!< SCU SFSP6_8: EHS Mask */\r
-#define SCU_SFSP6_8_EZI_Pos 6 /*!< SCU SFSP6_8: EZI Position */\r
-#define SCU_SFSP6_8_EZI_Msk (0x01UL << SCU_SFSP6_8_EZI_Pos) /*!< SCU SFSP6_8: EZI Mask */\r
-#define SCU_SFSP6_8_EHD_Pos 8 /*!< SCU SFSP6_8: EHD Position */\r
-#define SCU_SFSP6_8_EHD_Msk (0x03UL << SCU_SFSP6_8_EHD_Pos) /*!< SCU SFSP6_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP6_9 ------------------------------------------\r
-#define SCU_SFSP6_9_MODE_Pos 0 /*!< SCU SFSP6_9: MODE Position */\r
-#define SCU_SFSP6_9_MODE_Msk (0x07UL << SCU_SFSP6_9_MODE_Pos) /*!< SCU SFSP6_9: MODE Mask */\r
-#define SCU_SFSP6_9_EPD_Pos 3 /*!< SCU SFSP6_9: EPD Position */\r
-#define SCU_SFSP6_9_EPD_Msk (0x01UL << SCU_SFSP6_9_EPD_Pos) /*!< SCU SFSP6_9: EPD Mask */\r
-#define SCU_SFSP6_9_EPUN_Pos 4 /*!< SCU SFSP6_9: EPUN Position */\r
-#define SCU_SFSP6_9_EPUN_Msk (0x01UL << SCU_SFSP6_9_EPUN_Pos) /*!< SCU SFSP6_9: EPUN Mask */\r
-#define SCU_SFSP6_9_EHS_Pos 5 /*!< SCU SFSP6_9: EHS Position */\r
-#define SCU_SFSP6_9_EHS_Msk (0x01UL << SCU_SFSP6_9_EHS_Pos) /*!< SCU SFSP6_9: EHS Mask */\r
-#define SCU_SFSP6_9_EZI_Pos 6 /*!< SCU SFSP6_9: EZI Position */\r
-#define SCU_SFSP6_9_EZI_Msk (0x01UL << SCU_SFSP6_9_EZI_Pos) /*!< SCU SFSP6_9: EZI Mask */\r
-#define SCU_SFSP6_9_EHD_Pos 8 /*!< SCU SFSP6_9: EHD Position */\r
-#define SCU_SFSP6_9_EHD_Msk (0x03UL << SCU_SFSP6_9_EHD_Pos) /*!< SCU SFSP6_9: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP6_10 ------------------------------------------\r
-#define SCU_SFSP6_10_MODE_Pos 0 /*!< SCU SFSP6_10: MODE Position */\r
-#define SCU_SFSP6_10_MODE_Msk (0x07UL << SCU_SFSP6_10_MODE_Pos) /*!< SCU SFSP6_10: MODE Mask */\r
-#define SCU_SFSP6_10_EPD_Pos 3 /*!< SCU SFSP6_10: EPD Position */\r
-#define SCU_SFSP6_10_EPD_Msk (0x01UL << SCU_SFSP6_10_EPD_Pos) /*!< SCU SFSP6_10: EPD Mask */\r
-#define SCU_SFSP6_10_EPUN_Pos 4 /*!< SCU SFSP6_10: EPUN Position */\r
-#define SCU_SFSP6_10_EPUN_Msk (0x01UL << SCU_SFSP6_10_EPUN_Pos) /*!< SCU SFSP6_10: EPUN Mask */\r
-#define SCU_SFSP6_10_EHS_Pos 5 /*!< SCU SFSP6_10: EHS Position */\r
-#define SCU_SFSP6_10_EHS_Msk (0x01UL << SCU_SFSP6_10_EHS_Pos) /*!< SCU SFSP6_10: EHS Mask */\r
-#define SCU_SFSP6_10_EZI_Pos 6 /*!< SCU SFSP6_10: EZI Position */\r
-#define SCU_SFSP6_10_EZI_Msk (0x01UL << SCU_SFSP6_10_EZI_Pos) /*!< SCU SFSP6_10: EZI Mask */\r
-#define SCU_SFSP6_10_EHD_Pos 8 /*!< SCU SFSP6_10: EHD Position */\r
-#define SCU_SFSP6_10_EHD_Msk (0x03UL << SCU_SFSP6_10_EHD_Pos) /*!< SCU SFSP6_10: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP6_11 ------------------------------------------\r
-#define SCU_SFSP6_11_MODE_Pos 0 /*!< SCU SFSP6_11: MODE Position */\r
-#define SCU_SFSP6_11_MODE_Msk (0x07UL << SCU_SFSP6_11_MODE_Pos) /*!< SCU SFSP6_11: MODE Mask */\r
-#define SCU_SFSP6_11_EPD_Pos 3 /*!< SCU SFSP6_11: EPD Position */\r
-#define SCU_SFSP6_11_EPD_Msk (0x01UL << SCU_SFSP6_11_EPD_Pos) /*!< SCU SFSP6_11: EPD Mask */\r
-#define SCU_SFSP6_11_EPUN_Pos 4 /*!< SCU SFSP6_11: EPUN Position */\r
-#define SCU_SFSP6_11_EPUN_Msk (0x01UL << SCU_SFSP6_11_EPUN_Pos) /*!< SCU SFSP6_11: EPUN Mask */\r
-#define SCU_SFSP6_11_EHS_Pos 5 /*!< SCU SFSP6_11: EHS Position */\r
-#define SCU_SFSP6_11_EHS_Msk (0x01UL << SCU_SFSP6_11_EHS_Pos) /*!< SCU SFSP6_11: EHS Mask */\r
-#define SCU_SFSP6_11_EZI_Pos 6 /*!< SCU SFSP6_11: EZI Position */\r
-#define SCU_SFSP6_11_EZI_Msk (0x01UL << SCU_SFSP6_11_EZI_Pos) /*!< SCU SFSP6_11: EZI Mask */\r
-#define SCU_SFSP6_11_EHD_Pos 8 /*!< SCU SFSP6_11: EHD Position */\r
-#define SCU_SFSP6_11_EHD_Msk (0x03UL << SCU_SFSP6_11_EHD_Pos) /*!< SCU SFSP6_11: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSP6_12 ------------------------------------------\r
-#define SCU_SFSP6_12_MODE_Pos 0 /*!< SCU SFSP6_12: MODE Position */\r
-#define SCU_SFSP6_12_MODE_Msk (0x07UL << SCU_SFSP6_12_MODE_Pos) /*!< SCU SFSP6_12: MODE Mask */\r
-#define SCU_SFSP6_12_EPD_Pos 3 /*!< SCU SFSP6_12: EPD Position */\r
-#define SCU_SFSP6_12_EPD_Msk (0x01UL << SCU_SFSP6_12_EPD_Pos) /*!< SCU SFSP6_12: EPD Mask */\r
-#define SCU_SFSP6_12_EPUN_Pos 4 /*!< SCU SFSP6_12: EPUN Position */\r
-#define SCU_SFSP6_12_EPUN_Msk (0x01UL << SCU_SFSP6_12_EPUN_Pos) /*!< SCU SFSP6_12: EPUN Mask */\r
-#define SCU_SFSP6_12_EHS_Pos 5 /*!< SCU SFSP6_12: EHS Position */\r
-#define SCU_SFSP6_12_EHS_Msk (0x01UL << SCU_SFSP6_12_EHS_Pos) /*!< SCU SFSP6_12: EHS Mask */\r
-#define SCU_SFSP6_12_EZI_Pos 6 /*!< SCU SFSP6_12: EZI Position */\r
-#define SCU_SFSP6_12_EZI_Msk (0x01UL << SCU_SFSP6_12_EZI_Pos) /*!< SCU SFSP6_12: EZI Mask */\r
-#define SCU_SFSP6_12_EHD_Pos 8 /*!< SCU SFSP6_12: EHD Position */\r
-#define SCU_SFSP6_12_EHD_Msk (0x03UL << SCU_SFSP6_12_EHD_Pos) /*!< SCU SFSP6_12: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP7_0 ------------------------------------------\r
-#define SCU_SFSP7_0_MODE_Pos 0 /*!< SCU SFSP7_0: MODE Position */\r
-#define SCU_SFSP7_0_MODE_Msk (0x07UL << SCU_SFSP7_0_MODE_Pos) /*!< SCU SFSP7_0: MODE Mask */\r
-#define SCU_SFSP7_0_EPD_Pos 3 /*!< SCU SFSP7_0: EPD Position */\r
-#define SCU_SFSP7_0_EPD_Msk (0x01UL << SCU_SFSP7_0_EPD_Pos) /*!< SCU SFSP7_0: EPD Mask */\r
-#define SCU_SFSP7_0_EPUN_Pos 4 /*!< SCU SFSP7_0: EPUN Position */\r
-#define SCU_SFSP7_0_EPUN_Msk (0x01UL << SCU_SFSP7_0_EPUN_Pos) /*!< SCU SFSP7_0: EPUN Mask */\r
-#define SCU_SFSP7_0_EHS_Pos 5 /*!< SCU SFSP7_0: EHS Position */\r
-#define SCU_SFSP7_0_EHS_Msk (0x01UL << SCU_SFSP7_0_EHS_Pos) /*!< SCU SFSP7_0: EHS Mask */\r
-#define SCU_SFSP7_0_EZI_Pos 6 /*!< SCU SFSP7_0: EZI Position */\r
-#define SCU_SFSP7_0_EZI_Msk (0x01UL << SCU_SFSP7_0_EZI_Pos) /*!< SCU SFSP7_0: EZI Mask */\r
-#define SCU_SFSP7_0_EHD_Pos 8 /*!< SCU SFSP7_0: EHD Position */\r
-#define SCU_SFSP7_0_EHD_Msk (0x03UL << SCU_SFSP7_0_EHD_Pos) /*!< SCU SFSP7_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP7_1 ------------------------------------------\r
-#define SCU_SFSP7_1_MODE_Pos 0 /*!< SCU SFSP7_1: MODE Position */\r
-#define SCU_SFSP7_1_MODE_Msk (0x07UL << SCU_SFSP7_1_MODE_Pos) /*!< SCU SFSP7_1: MODE Mask */\r
-#define SCU_SFSP7_1_EPD_Pos 3 /*!< SCU SFSP7_1: EPD Position */\r
-#define SCU_SFSP7_1_EPD_Msk (0x01UL << SCU_SFSP7_1_EPD_Pos) /*!< SCU SFSP7_1: EPD Mask */\r
-#define SCU_SFSP7_1_EPUN_Pos 4 /*!< SCU SFSP7_1: EPUN Position */\r
-#define SCU_SFSP7_1_EPUN_Msk (0x01UL << SCU_SFSP7_1_EPUN_Pos) /*!< SCU SFSP7_1: EPUN Mask */\r
-#define SCU_SFSP7_1_EHS_Pos 5 /*!< SCU SFSP7_1: EHS Position */\r
-#define SCU_SFSP7_1_EHS_Msk (0x01UL << SCU_SFSP7_1_EHS_Pos) /*!< SCU SFSP7_1: EHS Mask */\r
-#define SCU_SFSP7_1_EZI_Pos 6 /*!< SCU SFSP7_1: EZI Position */\r
-#define SCU_SFSP7_1_EZI_Msk (0x01UL << SCU_SFSP7_1_EZI_Pos) /*!< SCU SFSP7_1: EZI Mask */\r
-#define SCU_SFSP7_1_EHD_Pos 8 /*!< SCU SFSP7_1: EHD Position */\r
-#define SCU_SFSP7_1_EHD_Msk (0x03UL << SCU_SFSP7_1_EHD_Pos) /*!< SCU SFSP7_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP7_2 ------------------------------------------\r
-#define SCU_SFSP7_2_MODE_Pos 0 /*!< SCU SFSP7_2: MODE Position */\r
-#define SCU_SFSP7_2_MODE_Msk (0x07UL << SCU_SFSP7_2_MODE_Pos) /*!< SCU SFSP7_2: MODE Mask */\r
-#define SCU_SFSP7_2_EPD_Pos 3 /*!< SCU SFSP7_2: EPD Position */\r
-#define SCU_SFSP7_2_EPD_Msk (0x01UL << SCU_SFSP7_2_EPD_Pos) /*!< SCU SFSP7_2: EPD Mask */\r
-#define SCU_SFSP7_2_EPUN_Pos 4 /*!< SCU SFSP7_2: EPUN Position */\r
-#define SCU_SFSP7_2_EPUN_Msk (0x01UL << SCU_SFSP7_2_EPUN_Pos) /*!< SCU SFSP7_2: EPUN Mask */\r
-#define SCU_SFSP7_2_EHS_Pos 5 /*!< SCU SFSP7_2: EHS Position */\r
-#define SCU_SFSP7_2_EHS_Msk (0x01UL << SCU_SFSP7_2_EHS_Pos) /*!< SCU SFSP7_2: EHS Mask */\r
-#define SCU_SFSP7_2_EZI_Pos 6 /*!< SCU SFSP7_2: EZI Position */\r
-#define SCU_SFSP7_2_EZI_Msk (0x01UL << SCU_SFSP7_2_EZI_Pos) /*!< SCU SFSP7_2: EZI Mask */\r
-#define SCU_SFSP7_2_EHD_Pos 8 /*!< SCU SFSP7_2: EHD Position */\r
-#define SCU_SFSP7_2_EHD_Msk (0x03UL << SCU_SFSP7_2_EHD_Pos) /*!< SCU SFSP7_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP7_3 ------------------------------------------\r
-#define SCU_SFSP7_3_MODE_Pos 0 /*!< SCU SFSP7_3: MODE Position */\r
-#define SCU_SFSP7_3_MODE_Msk (0x07UL << SCU_SFSP7_3_MODE_Pos) /*!< SCU SFSP7_3: MODE Mask */\r
-#define SCU_SFSP7_3_EPD_Pos 3 /*!< SCU SFSP7_3: EPD Position */\r
-#define SCU_SFSP7_3_EPD_Msk (0x01UL << SCU_SFSP7_3_EPD_Pos) /*!< SCU SFSP7_3: EPD Mask */\r
-#define SCU_SFSP7_3_EPUN_Pos 4 /*!< SCU SFSP7_3: EPUN Position */\r
-#define SCU_SFSP7_3_EPUN_Msk (0x01UL << SCU_SFSP7_3_EPUN_Pos) /*!< SCU SFSP7_3: EPUN Mask */\r
-#define SCU_SFSP7_3_EHS_Pos 5 /*!< SCU SFSP7_3: EHS Position */\r
-#define SCU_SFSP7_3_EHS_Msk (0x01UL << SCU_SFSP7_3_EHS_Pos) /*!< SCU SFSP7_3: EHS Mask */\r
-#define SCU_SFSP7_3_EZI_Pos 6 /*!< SCU SFSP7_3: EZI Position */\r
-#define SCU_SFSP7_3_EZI_Msk (0x01UL << SCU_SFSP7_3_EZI_Pos) /*!< SCU SFSP7_3: EZI Mask */\r
-#define SCU_SFSP7_3_EHD_Pos 8 /*!< SCU SFSP7_3: EHD Position */\r
-#define SCU_SFSP7_3_EHD_Msk (0x03UL << SCU_SFSP7_3_EHD_Pos) /*!< SCU SFSP7_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP7_4 ------------------------------------------\r
-#define SCU_SFSP7_4_MODE_Pos 0 /*!< SCU SFSP7_4: MODE Position */\r
-#define SCU_SFSP7_4_MODE_Msk (0x07UL << SCU_SFSP7_4_MODE_Pos) /*!< SCU SFSP7_4: MODE Mask */\r
-#define SCU_SFSP7_4_EPD_Pos 3 /*!< SCU SFSP7_4: EPD Position */\r
-#define SCU_SFSP7_4_EPD_Msk (0x01UL << SCU_SFSP7_4_EPD_Pos) /*!< SCU SFSP7_4: EPD Mask */\r
-#define SCU_SFSP7_4_EPUN_Pos 4 /*!< SCU SFSP7_4: EPUN Position */\r
-#define SCU_SFSP7_4_EPUN_Msk (0x01UL << SCU_SFSP7_4_EPUN_Pos) /*!< SCU SFSP7_4: EPUN Mask */\r
-#define SCU_SFSP7_4_EHS_Pos 5 /*!< SCU SFSP7_4: EHS Position */\r
-#define SCU_SFSP7_4_EHS_Msk (0x01UL << SCU_SFSP7_4_EHS_Pos) /*!< SCU SFSP7_4: EHS Mask */\r
-#define SCU_SFSP7_4_EZI_Pos 6 /*!< SCU SFSP7_4: EZI Position */\r
-#define SCU_SFSP7_4_EZI_Msk (0x01UL << SCU_SFSP7_4_EZI_Pos) /*!< SCU SFSP7_4: EZI Mask */\r
-#define SCU_SFSP7_4_EHD_Pos 8 /*!< SCU SFSP7_4: EHD Position */\r
-#define SCU_SFSP7_4_EHD_Msk (0x03UL << SCU_SFSP7_4_EHD_Pos) /*!< SCU SFSP7_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP7_5 ------------------------------------------\r
-#define SCU_SFSP7_5_MODE_Pos 0 /*!< SCU SFSP7_5: MODE Position */\r
-#define SCU_SFSP7_5_MODE_Msk (0x07UL << SCU_SFSP7_5_MODE_Pos) /*!< SCU SFSP7_5: MODE Mask */\r
-#define SCU_SFSP7_5_EPD_Pos 3 /*!< SCU SFSP7_5: EPD Position */\r
-#define SCU_SFSP7_5_EPD_Msk (0x01UL << SCU_SFSP7_5_EPD_Pos) /*!< SCU SFSP7_5: EPD Mask */\r
-#define SCU_SFSP7_5_EPUN_Pos 4 /*!< SCU SFSP7_5: EPUN Position */\r
-#define SCU_SFSP7_5_EPUN_Msk (0x01UL << SCU_SFSP7_5_EPUN_Pos) /*!< SCU SFSP7_5: EPUN Mask */\r
-#define SCU_SFSP7_5_EHS_Pos 5 /*!< SCU SFSP7_5: EHS Position */\r
-#define SCU_SFSP7_5_EHS_Msk (0x01UL << SCU_SFSP7_5_EHS_Pos) /*!< SCU SFSP7_5: EHS Mask */\r
-#define SCU_SFSP7_5_EZI_Pos 6 /*!< SCU SFSP7_5: EZI Position */\r
-#define SCU_SFSP7_5_EZI_Msk (0x01UL << SCU_SFSP7_5_EZI_Pos) /*!< SCU SFSP7_5: EZI Mask */\r
-#define SCU_SFSP7_5_EHD_Pos 8 /*!< SCU SFSP7_5: EHD Position */\r
-#define SCU_SFSP7_5_EHD_Msk (0x03UL << SCU_SFSP7_5_EHD_Pos) /*!< SCU SFSP7_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP7_6 ------------------------------------------\r
-#define SCU_SFSP7_6_MODE_Pos 0 /*!< SCU SFSP7_6: MODE Position */\r
-#define SCU_SFSP7_6_MODE_Msk (0x07UL << SCU_SFSP7_6_MODE_Pos) /*!< SCU SFSP7_6: MODE Mask */\r
-#define SCU_SFSP7_6_EPD_Pos 3 /*!< SCU SFSP7_6: EPD Position */\r
-#define SCU_SFSP7_6_EPD_Msk (0x01UL << SCU_SFSP7_6_EPD_Pos) /*!< SCU SFSP7_6: EPD Mask */\r
-#define SCU_SFSP7_6_EPUN_Pos 4 /*!< SCU SFSP7_6: EPUN Position */\r
-#define SCU_SFSP7_6_EPUN_Msk (0x01UL << SCU_SFSP7_6_EPUN_Pos) /*!< SCU SFSP7_6: EPUN Mask */\r
-#define SCU_SFSP7_6_EHS_Pos 5 /*!< SCU SFSP7_6: EHS Position */\r
-#define SCU_SFSP7_6_EHS_Msk (0x01UL << SCU_SFSP7_6_EHS_Pos) /*!< SCU SFSP7_6: EHS Mask */\r
-#define SCU_SFSP7_6_EZI_Pos 6 /*!< SCU SFSP7_6: EZI Position */\r
-#define SCU_SFSP7_6_EZI_Msk (0x01UL << SCU_SFSP7_6_EZI_Pos) /*!< SCU SFSP7_6: EZI Mask */\r
-#define SCU_SFSP7_6_EHD_Pos 8 /*!< SCU SFSP7_6: EHD Position */\r
-#define SCU_SFSP7_6_EHD_Msk (0x03UL << SCU_SFSP7_6_EHD_Pos) /*!< SCU SFSP7_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP7_7 ------------------------------------------\r
-#define SCU_SFSP7_7_MODE_Pos 0 /*!< SCU SFSP7_7: MODE Position */\r
-#define SCU_SFSP7_7_MODE_Msk (0x07UL << SCU_SFSP7_7_MODE_Pos) /*!< SCU SFSP7_7: MODE Mask */\r
-#define SCU_SFSP7_7_EPD_Pos 3 /*!< SCU SFSP7_7: EPD Position */\r
-#define SCU_SFSP7_7_EPD_Msk (0x01UL << SCU_SFSP7_7_EPD_Pos) /*!< SCU SFSP7_7: EPD Mask */\r
-#define SCU_SFSP7_7_EPUN_Pos 4 /*!< SCU SFSP7_7: EPUN Position */\r
-#define SCU_SFSP7_7_EPUN_Msk (0x01UL << SCU_SFSP7_7_EPUN_Pos) /*!< SCU SFSP7_7: EPUN Mask */\r
-#define SCU_SFSP7_7_EHS_Pos 5 /*!< SCU SFSP7_7: EHS Position */\r
-#define SCU_SFSP7_7_EHS_Msk (0x01UL << SCU_SFSP7_7_EHS_Pos) /*!< SCU SFSP7_7: EHS Mask */\r
-#define SCU_SFSP7_7_EZI_Pos 6 /*!< SCU SFSP7_7: EZI Position */\r
-#define SCU_SFSP7_7_EZI_Msk (0x01UL << SCU_SFSP7_7_EZI_Pos) /*!< SCU SFSP7_7: EZI Mask */\r
-#define SCU_SFSP7_7_EHD_Pos 8 /*!< SCU SFSP7_7: EHD Position */\r
-#define SCU_SFSP7_7_EHD_Msk (0x03UL << SCU_SFSP7_7_EHD_Pos) /*!< SCU SFSP7_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP8_0 ------------------------------------------\r
-#define SCU_SFSP8_0_MODE_Pos 0 /*!< SCU SFSP8_0: MODE Position */\r
-#define SCU_SFSP8_0_MODE_Msk (0x07UL << SCU_SFSP8_0_MODE_Pos) /*!< SCU SFSP8_0: MODE Mask */\r
-#define SCU_SFSP8_0_EPD_Pos 3 /*!< SCU SFSP8_0: EPD Position */\r
-#define SCU_SFSP8_0_EPD_Msk (0x01UL << SCU_SFSP8_0_EPD_Pos) /*!< SCU SFSP8_0: EPD Mask */\r
-#define SCU_SFSP8_0_EPUN_Pos 4 /*!< SCU SFSP8_0: EPUN Position */\r
-#define SCU_SFSP8_0_EPUN_Msk (0x01UL << SCU_SFSP8_0_EPUN_Pos) /*!< SCU SFSP8_0: EPUN Mask */\r
-#define SCU_SFSP8_0_EHS_Pos 5 /*!< SCU SFSP8_0: EHS Position */\r
-#define SCU_SFSP8_0_EHS_Msk (0x01UL << SCU_SFSP8_0_EHS_Pos) /*!< SCU SFSP8_0: EHS Mask */\r
-#define SCU_SFSP8_0_EZI_Pos 6 /*!< SCU SFSP8_0: EZI Position */\r
-#define SCU_SFSP8_0_EZI_Msk (0x01UL << SCU_SFSP8_0_EZI_Pos) /*!< SCU SFSP8_0: EZI Mask */\r
-#define SCU_SFSP8_0_EHD_Pos 8 /*!< SCU SFSP8_0: EHD Position */\r
-#define SCU_SFSP8_0_EHD_Msk (0x03UL << SCU_SFSP8_0_EHD_Pos) /*!< SCU SFSP8_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP8_1 ------------------------------------------\r
-#define SCU_SFSP8_1_MODE_Pos 0 /*!< SCU SFSP8_1: MODE Position */\r
-#define SCU_SFSP8_1_MODE_Msk (0x07UL << SCU_SFSP8_1_MODE_Pos) /*!< SCU SFSP8_1: MODE Mask */\r
-#define SCU_SFSP8_1_EPD_Pos 3 /*!< SCU SFSP8_1: EPD Position */\r
-#define SCU_SFSP8_1_EPD_Msk (0x01UL << SCU_SFSP8_1_EPD_Pos) /*!< SCU SFSP8_1: EPD Mask */\r
-#define SCU_SFSP8_1_EPUN_Pos 4 /*!< SCU SFSP8_1: EPUN Position */\r
-#define SCU_SFSP8_1_EPUN_Msk (0x01UL << SCU_SFSP8_1_EPUN_Pos) /*!< SCU SFSP8_1: EPUN Mask */\r
-#define SCU_SFSP8_1_EHS_Pos 5 /*!< SCU SFSP8_1: EHS Position */\r
-#define SCU_SFSP8_1_EHS_Msk (0x01UL << SCU_SFSP8_1_EHS_Pos) /*!< SCU SFSP8_1: EHS Mask */\r
-#define SCU_SFSP8_1_EZI_Pos 6 /*!< SCU SFSP8_1: EZI Position */\r
-#define SCU_SFSP8_1_EZI_Msk (0x01UL << SCU_SFSP8_1_EZI_Pos) /*!< SCU SFSP8_1: EZI Mask */\r
-#define SCU_SFSP8_1_EHD_Pos 8 /*!< SCU SFSP8_1: EHD Position */\r
-#define SCU_SFSP8_1_EHD_Msk (0x03UL << SCU_SFSP8_1_EHD_Pos) /*!< SCU SFSP8_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP8_2 ------------------------------------------\r
-#define SCU_SFSP8_2_MODE_Pos 0 /*!< SCU SFSP8_2: MODE Position */\r
-#define SCU_SFSP8_2_MODE_Msk (0x07UL << SCU_SFSP8_2_MODE_Pos) /*!< SCU SFSP8_2: MODE Mask */\r
-#define SCU_SFSP8_2_EPD_Pos 3 /*!< SCU SFSP8_2: EPD Position */\r
-#define SCU_SFSP8_2_EPD_Msk (0x01UL << SCU_SFSP8_2_EPD_Pos) /*!< SCU SFSP8_2: EPD Mask */\r
-#define SCU_SFSP8_2_EPUN_Pos 4 /*!< SCU SFSP8_2: EPUN Position */\r
-#define SCU_SFSP8_2_EPUN_Msk (0x01UL << SCU_SFSP8_2_EPUN_Pos) /*!< SCU SFSP8_2: EPUN Mask */\r
-#define SCU_SFSP8_2_EHS_Pos 5 /*!< SCU SFSP8_2: EHS Position */\r
-#define SCU_SFSP8_2_EHS_Msk (0x01UL << SCU_SFSP8_2_EHS_Pos) /*!< SCU SFSP8_2: EHS Mask */\r
-#define SCU_SFSP8_2_EZI_Pos 6 /*!< SCU SFSP8_2: EZI Position */\r
-#define SCU_SFSP8_2_EZI_Msk (0x01UL << SCU_SFSP8_2_EZI_Pos) /*!< SCU SFSP8_2: EZI Mask */\r
-#define SCU_SFSP8_2_EHD_Pos 8 /*!< SCU SFSP8_2: EHD Position */\r
-#define SCU_SFSP8_2_EHD_Msk (0x03UL << SCU_SFSP8_2_EHD_Pos) /*!< SCU SFSP8_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP8_3 ------------------------------------------\r
-#define SCU_SFSP8_3_MODE_Pos 0 /*!< SCU SFSP8_3: MODE Position */\r
-#define SCU_SFSP8_3_MODE_Msk (0x07UL << SCU_SFSP8_3_MODE_Pos) /*!< SCU SFSP8_3: MODE Mask */\r
-#define SCU_SFSP8_3_EPD_Pos 3 /*!< SCU SFSP8_3: EPD Position */\r
-#define SCU_SFSP8_3_EPD_Msk (0x01UL << SCU_SFSP8_3_EPD_Pos) /*!< SCU SFSP8_3: EPD Mask */\r
-#define SCU_SFSP8_3_EPUN_Pos 4 /*!< SCU SFSP8_3: EPUN Position */\r
-#define SCU_SFSP8_3_EPUN_Msk (0x01UL << SCU_SFSP8_3_EPUN_Pos) /*!< SCU SFSP8_3: EPUN Mask */\r
-#define SCU_SFSP8_3_EHS_Pos 5 /*!< SCU SFSP8_3: EHS Position */\r
-#define SCU_SFSP8_3_EHS_Msk (0x01UL << SCU_SFSP8_3_EHS_Pos) /*!< SCU SFSP8_3: EHS Mask */\r
-#define SCU_SFSP8_3_EZI_Pos 6 /*!< SCU SFSP8_3: EZI Position */\r
-#define SCU_SFSP8_3_EZI_Msk (0x01UL << SCU_SFSP8_3_EZI_Pos) /*!< SCU SFSP8_3: EZI Mask */\r
-#define SCU_SFSP8_3_EHD_Pos 8 /*!< SCU SFSP8_3: EHD Position */\r
-#define SCU_SFSP8_3_EHD_Msk (0x03UL << SCU_SFSP8_3_EHD_Pos) /*!< SCU SFSP8_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP8_4 ------------------------------------------\r
-#define SCU_SFSP8_4_MODE_Pos 0 /*!< SCU SFSP8_4: MODE Position */\r
-#define SCU_SFSP8_4_MODE_Msk (0x07UL << SCU_SFSP8_4_MODE_Pos) /*!< SCU SFSP8_4: MODE Mask */\r
-#define SCU_SFSP8_4_EPD_Pos 3 /*!< SCU SFSP8_4: EPD Position */\r
-#define SCU_SFSP8_4_EPD_Msk (0x01UL << SCU_SFSP8_4_EPD_Pos) /*!< SCU SFSP8_4: EPD Mask */\r
-#define SCU_SFSP8_4_EPUN_Pos 4 /*!< SCU SFSP8_4: EPUN Position */\r
-#define SCU_SFSP8_4_EPUN_Msk (0x01UL << SCU_SFSP8_4_EPUN_Pos) /*!< SCU SFSP8_4: EPUN Mask */\r
-#define SCU_SFSP8_4_EHS_Pos 5 /*!< SCU SFSP8_4: EHS Position */\r
-#define SCU_SFSP8_4_EHS_Msk (0x01UL << SCU_SFSP8_4_EHS_Pos) /*!< SCU SFSP8_4: EHS Mask */\r
-#define SCU_SFSP8_4_EZI_Pos 6 /*!< SCU SFSP8_4: EZI Position */\r
-#define SCU_SFSP8_4_EZI_Msk (0x01UL << SCU_SFSP8_4_EZI_Pos) /*!< SCU SFSP8_4: EZI Mask */\r
-#define SCU_SFSP8_4_EHD_Pos 8 /*!< SCU SFSP8_4: EHD Position */\r
-#define SCU_SFSP8_4_EHD_Msk (0x03UL << SCU_SFSP8_4_EHD_Pos) /*!< SCU SFSP8_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP8_5 ------------------------------------------\r
-#define SCU_SFSP8_5_MODE_Pos 0 /*!< SCU SFSP8_5: MODE Position */\r
-#define SCU_SFSP8_5_MODE_Msk (0x07UL << SCU_SFSP8_5_MODE_Pos) /*!< SCU SFSP8_5: MODE Mask */\r
-#define SCU_SFSP8_5_EPD_Pos 3 /*!< SCU SFSP8_5: EPD Position */\r
-#define SCU_SFSP8_5_EPD_Msk (0x01UL << SCU_SFSP8_5_EPD_Pos) /*!< SCU SFSP8_5: EPD Mask */\r
-#define SCU_SFSP8_5_EPUN_Pos 4 /*!< SCU SFSP8_5: EPUN Position */\r
-#define SCU_SFSP8_5_EPUN_Msk (0x01UL << SCU_SFSP8_5_EPUN_Pos) /*!< SCU SFSP8_5: EPUN Mask */\r
-#define SCU_SFSP8_5_EHS_Pos 5 /*!< SCU SFSP8_5: EHS Position */\r
-#define SCU_SFSP8_5_EHS_Msk (0x01UL << SCU_SFSP8_5_EHS_Pos) /*!< SCU SFSP8_5: EHS Mask */\r
-#define SCU_SFSP8_5_EZI_Pos 6 /*!< SCU SFSP8_5: EZI Position */\r
-#define SCU_SFSP8_5_EZI_Msk (0x01UL << SCU_SFSP8_5_EZI_Pos) /*!< SCU SFSP8_5: EZI Mask */\r
-#define SCU_SFSP8_5_EHD_Pos 8 /*!< SCU SFSP8_5: EHD Position */\r
-#define SCU_SFSP8_5_EHD_Msk (0x03UL << SCU_SFSP8_5_EHD_Pos) /*!< SCU SFSP8_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP8_6 ------------------------------------------\r
-#define SCU_SFSP8_6_MODE_Pos 0 /*!< SCU SFSP8_6: MODE Position */\r
-#define SCU_SFSP8_6_MODE_Msk (0x07UL << SCU_SFSP8_6_MODE_Pos) /*!< SCU SFSP8_6: MODE Mask */\r
-#define SCU_SFSP8_6_EPD_Pos 3 /*!< SCU SFSP8_6: EPD Position */\r
-#define SCU_SFSP8_6_EPD_Msk (0x01UL << SCU_SFSP8_6_EPD_Pos) /*!< SCU SFSP8_6: EPD Mask */\r
-#define SCU_SFSP8_6_EPUN_Pos 4 /*!< SCU SFSP8_6: EPUN Position */\r
-#define SCU_SFSP8_6_EPUN_Msk (0x01UL << SCU_SFSP8_6_EPUN_Pos) /*!< SCU SFSP8_6: EPUN Mask */\r
-#define SCU_SFSP8_6_EHS_Pos 5 /*!< SCU SFSP8_6: EHS Position */\r
-#define SCU_SFSP8_6_EHS_Msk (0x01UL << SCU_SFSP8_6_EHS_Pos) /*!< SCU SFSP8_6: EHS Mask */\r
-#define SCU_SFSP8_6_EZI_Pos 6 /*!< SCU SFSP8_6: EZI Position */\r
-#define SCU_SFSP8_6_EZI_Msk (0x01UL << SCU_SFSP8_6_EZI_Pos) /*!< SCU SFSP8_6: EZI Mask */\r
-#define SCU_SFSP8_6_EHD_Pos 8 /*!< SCU SFSP8_6: EHD Position */\r
-#define SCU_SFSP8_6_EHD_Msk (0x03UL << SCU_SFSP8_6_EHD_Pos) /*!< SCU SFSP8_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP8_7 ------------------------------------------\r
-#define SCU_SFSP8_7_MODE_Pos 0 /*!< SCU SFSP8_7: MODE Position */\r
-#define SCU_SFSP8_7_MODE_Msk (0x07UL << SCU_SFSP8_7_MODE_Pos) /*!< SCU SFSP8_7: MODE Mask */\r
-#define SCU_SFSP8_7_EPD_Pos 3 /*!< SCU SFSP8_7: EPD Position */\r
-#define SCU_SFSP8_7_EPD_Msk (0x01UL << SCU_SFSP8_7_EPD_Pos) /*!< SCU SFSP8_7: EPD Mask */\r
-#define SCU_SFSP8_7_EPUN_Pos 4 /*!< SCU SFSP8_7: EPUN Position */\r
-#define SCU_SFSP8_7_EPUN_Msk (0x01UL << SCU_SFSP8_7_EPUN_Pos) /*!< SCU SFSP8_7: EPUN Mask */\r
-#define SCU_SFSP8_7_EHS_Pos 5 /*!< SCU SFSP8_7: EHS Position */\r
-#define SCU_SFSP8_7_EHS_Msk (0x01UL << SCU_SFSP8_7_EHS_Pos) /*!< SCU SFSP8_7: EHS Mask */\r
-#define SCU_SFSP8_7_EZI_Pos 6 /*!< SCU SFSP8_7: EZI Position */\r
-#define SCU_SFSP8_7_EZI_Msk (0x01UL << SCU_SFSP8_7_EZI_Pos) /*!< SCU SFSP8_7: EZI Mask */\r
-#define SCU_SFSP8_7_EHD_Pos 8 /*!< SCU SFSP8_7: EHD Position */\r
-#define SCU_SFSP8_7_EHD_Msk (0x03UL << SCU_SFSP8_7_EHD_Pos) /*!< SCU SFSP8_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP8_8 ------------------------------------------\r
-#define SCU_SFSP8_8_MODE_Pos 0 /*!< SCU SFSP8_8: MODE Position */\r
-#define SCU_SFSP8_8_MODE_Msk (0x07UL << SCU_SFSP8_8_MODE_Pos) /*!< SCU SFSP8_8: MODE Mask */\r
-#define SCU_SFSP8_8_EPD_Pos 3 /*!< SCU SFSP8_8: EPD Position */\r
-#define SCU_SFSP8_8_EPD_Msk (0x01UL << SCU_SFSP8_8_EPD_Pos) /*!< SCU SFSP8_8: EPD Mask */\r
-#define SCU_SFSP8_8_EPUN_Pos 4 /*!< SCU SFSP8_8: EPUN Position */\r
-#define SCU_SFSP8_8_EPUN_Msk (0x01UL << SCU_SFSP8_8_EPUN_Pos) /*!< SCU SFSP8_8: EPUN Mask */\r
-#define SCU_SFSP8_8_EHS_Pos 5 /*!< SCU SFSP8_8: EHS Position */\r
-#define SCU_SFSP8_8_EHS_Msk (0x01UL << SCU_SFSP8_8_EHS_Pos) /*!< SCU SFSP8_8: EHS Mask */\r
-#define SCU_SFSP8_8_EZI_Pos 6 /*!< SCU SFSP8_8: EZI Position */\r
-#define SCU_SFSP8_8_EZI_Msk (0x01UL << SCU_SFSP8_8_EZI_Pos) /*!< SCU SFSP8_8: EZI Mask */\r
-#define SCU_SFSP8_8_EHD_Pos 8 /*!< SCU SFSP8_8: EHD Position */\r
-#define SCU_SFSP8_8_EHD_Msk (0x03UL << SCU_SFSP8_8_EHD_Pos) /*!< SCU SFSP8_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP9_0 ------------------------------------------\r
-#define SCU_SFSP9_0_MODE_Pos 0 /*!< SCU SFSP9_0: MODE Position */\r
-#define SCU_SFSP9_0_MODE_Msk (0x07UL << SCU_SFSP9_0_MODE_Pos) /*!< SCU SFSP9_0: MODE Mask */\r
-#define SCU_SFSP9_0_EPD_Pos 3 /*!< SCU SFSP9_0: EPD Position */\r
-#define SCU_SFSP9_0_EPD_Msk (0x01UL << SCU_SFSP9_0_EPD_Pos) /*!< SCU SFSP9_0: EPD Mask */\r
-#define SCU_SFSP9_0_EPUN_Pos 4 /*!< SCU SFSP9_0: EPUN Position */\r
-#define SCU_SFSP9_0_EPUN_Msk (0x01UL << SCU_SFSP9_0_EPUN_Pos) /*!< SCU SFSP9_0: EPUN Mask */\r
-#define SCU_SFSP9_0_EHS_Pos 5 /*!< SCU SFSP9_0: EHS Position */\r
-#define SCU_SFSP9_0_EHS_Msk (0x01UL << SCU_SFSP9_0_EHS_Pos) /*!< SCU SFSP9_0: EHS Mask */\r
-#define SCU_SFSP9_0_EZI_Pos 6 /*!< SCU SFSP9_0: EZI Position */\r
-#define SCU_SFSP9_0_EZI_Msk (0x01UL << SCU_SFSP9_0_EZI_Pos) /*!< SCU SFSP9_0: EZI Mask */\r
-#define SCU_SFSP9_0_EHD_Pos 8 /*!< SCU SFSP9_0: EHD Position */\r
-#define SCU_SFSP9_0_EHD_Msk (0x03UL << SCU_SFSP9_0_EHD_Pos) /*!< SCU SFSP9_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP9_1 ------------------------------------------\r
-#define SCU_SFSP9_1_MODE_Pos 0 /*!< SCU SFSP9_1: MODE Position */\r
-#define SCU_SFSP9_1_MODE_Msk (0x07UL << SCU_SFSP9_1_MODE_Pos) /*!< SCU SFSP9_1: MODE Mask */\r
-#define SCU_SFSP9_1_EPD_Pos 3 /*!< SCU SFSP9_1: EPD Position */\r
-#define SCU_SFSP9_1_EPD_Msk (0x01UL << SCU_SFSP9_1_EPD_Pos) /*!< SCU SFSP9_1: EPD Mask */\r
-#define SCU_SFSP9_1_EPUN_Pos 4 /*!< SCU SFSP9_1: EPUN Position */\r
-#define SCU_SFSP9_1_EPUN_Msk (0x01UL << SCU_SFSP9_1_EPUN_Pos) /*!< SCU SFSP9_1: EPUN Mask */\r
-#define SCU_SFSP9_1_EHS_Pos 5 /*!< SCU SFSP9_1: EHS Position */\r
-#define SCU_SFSP9_1_EHS_Msk (0x01UL << SCU_SFSP9_1_EHS_Pos) /*!< SCU SFSP9_1: EHS Mask */\r
-#define SCU_SFSP9_1_EZI_Pos 6 /*!< SCU SFSP9_1: EZI Position */\r
-#define SCU_SFSP9_1_EZI_Msk (0x01UL << SCU_SFSP9_1_EZI_Pos) /*!< SCU SFSP9_1: EZI Mask */\r
-#define SCU_SFSP9_1_EHD_Pos 8 /*!< SCU SFSP9_1: EHD Position */\r
-#define SCU_SFSP9_1_EHD_Msk (0x03UL << SCU_SFSP9_1_EHD_Pos) /*!< SCU SFSP9_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP9_2 ------------------------------------------\r
-#define SCU_SFSP9_2_MODE_Pos 0 /*!< SCU SFSP9_2: MODE Position */\r
-#define SCU_SFSP9_2_MODE_Msk (0x07UL << SCU_SFSP9_2_MODE_Pos) /*!< SCU SFSP9_2: MODE Mask */\r
-#define SCU_SFSP9_2_EPD_Pos 3 /*!< SCU SFSP9_2: EPD Position */\r
-#define SCU_SFSP9_2_EPD_Msk (0x01UL << SCU_SFSP9_2_EPD_Pos) /*!< SCU SFSP9_2: EPD Mask */\r
-#define SCU_SFSP9_2_EPUN_Pos 4 /*!< SCU SFSP9_2: EPUN Position */\r
-#define SCU_SFSP9_2_EPUN_Msk (0x01UL << SCU_SFSP9_2_EPUN_Pos) /*!< SCU SFSP9_2: EPUN Mask */\r
-#define SCU_SFSP9_2_EHS_Pos 5 /*!< SCU SFSP9_2: EHS Position */\r
-#define SCU_SFSP9_2_EHS_Msk (0x01UL << SCU_SFSP9_2_EHS_Pos) /*!< SCU SFSP9_2: EHS Mask */\r
-#define SCU_SFSP9_2_EZI_Pos 6 /*!< SCU SFSP9_2: EZI Position */\r
-#define SCU_SFSP9_2_EZI_Msk (0x01UL << SCU_SFSP9_2_EZI_Pos) /*!< SCU SFSP9_2: EZI Mask */\r
-#define SCU_SFSP9_2_EHD_Pos 8 /*!< SCU SFSP9_2: EHD Position */\r
-#define SCU_SFSP9_2_EHD_Msk (0x03UL << SCU_SFSP9_2_EHD_Pos) /*!< SCU SFSP9_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP9_3 ------------------------------------------\r
-#define SCU_SFSP9_3_MODE_Pos 0 /*!< SCU SFSP9_3: MODE Position */\r
-#define SCU_SFSP9_3_MODE_Msk (0x07UL << SCU_SFSP9_3_MODE_Pos) /*!< SCU SFSP9_3: MODE Mask */\r
-#define SCU_SFSP9_3_EPD_Pos 3 /*!< SCU SFSP9_3: EPD Position */\r
-#define SCU_SFSP9_3_EPD_Msk (0x01UL << SCU_SFSP9_3_EPD_Pos) /*!< SCU SFSP9_3: EPD Mask */\r
-#define SCU_SFSP9_3_EPUN_Pos 4 /*!< SCU SFSP9_3: EPUN Position */\r
-#define SCU_SFSP9_3_EPUN_Msk (0x01UL << SCU_SFSP9_3_EPUN_Pos) /*!< SCU SFSP9_3: EPUN Mask */\r
-#define SCU_SFSP9_3_EHS_Pos 5 /*!< SCU SFSP9_3: EHS Position */\r
-#define SCU_SFSP9_3_EHS_Msk (0x01UL << SCU_SFSP9_3_EHS_Pos) /*!< SCU SFSP9_3: EHS Mask */\r
-#define SCU_SFSP9_3_EZI_Pos 6 /*!< SCU SFSP9_3: EZI Position */\r
-#define SCU_SFSP9_3_EZI_Msk (0x01UL << SCU_SFSP9_3_EZI_Pos) /*!< SCU SFSP9_3: EZI Mask */\r
-#define SCU_SFSP9_3_EHD_Pos 8 /*!< SCU SFSP9_3: EHD Position */\r
-#define SCU_SFSP9_3_EHD_Msk (0x03UL << SCU_SFSP9_3_EHD_Pos) /*!< SCU SFSP9_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP9_4 ------------------------------------------\r
-#define SCU_SFSP9_4_MODE_Pos 0 /*!< SCU SFSP9_4: MODE Position */\r
-#define SCU_SFSP9_4_MODE_Msk (0x07UL << SCU_SFSP9_4_MODE_Pos) /*!< SCU SFSP9_4: MODE Mask */\r
-#define SCU_SFSP9_4_EPD_Pos 3 /*!< SCU SFSP9_4: EPD Position */\r
-#define SCU_SFSP9_4_EPD_Msk (0x01UL << SCU_SFSP9_4_EPD_Pos) /*!< SCU SFSP9_4: EPD Mask */\r
-#define SCU_SFSP9_4_EPUN_Pos 4 /*!< SCU SFSP9_4: EPUN Position */\r
-#define SCU_SFSP9_4_EPUN_Msk (0x01UL << SCU_SFSP9_4_EPUN_Pos) /*!< SCU SFSP9_4: EPUN Mask */\r
-#define SCU_SFSP9_4_EHS_Pos 5 /*!< SCU SFSP9_4: EHS Position */\r
-#define SCU_SFSP9_4_EHS_Msk (0x01UL << SCU_SFSP9_4_EHS_Pos) /*!< SCU SFSP9_4: EHS Mask */\r
-#define SCU_SFSP9_4_EZI_Pos 6 /*!< SCU SFSP9_4: EZI Position */\r
-#define SCU_SFSP9_4_EZI_Msk (0x01UL << SCU_SFSP9_4_EZI_Pos) /*!< SCU SFSP9_4: EZI Mask */\r
-#define SCU_SFSP9_4_EHD_Pos 8 /*!< SCU SFSP9_4: EHD Position */\r
-#define SCU_SFSP9_4_EHD_Msk (0x03UL << SCU_SFSP9_4_EHD_Pos) /*!< SCU SFSP9_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP9_5 ------------------------------------------\r
-#define SCU_SFSP9_5_MODE_Pos 0 /*!< SCU SFSP9_5: MODE Position */\r
-#define SCU_SFSP9_5_MODE_Msk (0x07UL << SCU_SFSP9_5_MODE_Pos) /*!< SCU SFSP9_5: MODE Mask */\r
-#define SCU_SFSP9_5_EPD_Pos 3 /*!< SCU SFSP9_5: EPD Position */\r
-#define SCU_SFSP9_5_EPD_Msk (0x01UL << SCU_SFSP9_5_EPD_Pos) /*!< SCU SFSP9_5: EPD Mask */\r
-#define SCU_SFSP9_5_EPUN_Pos 4 /*!< SCU SFSP9_5: EPUN Position */\r
-#define SCU_SFSP9_5_EPUN_Msk (0x01UL << SCU_SFSP9_5_EPUN_Pos) /*!< SCU SFSP9_5: EPUN Mask */\r
-#define SCU_SFSP9_5_EHS_Pos 5 /*!< SCU SFSP9_5: EHS Position */\r
-#define SCU_SFSP9_5_EHS_Msk (0x01UL << SCU_SFSP9_5_EHS_Pos) /*!< SCU SFSP9_5: EHS Mask */\r
-#define SCU_SFSP9_5_EZI_Pos 6 /*!< SCU SFSP9_5: EZI Position */\r
-#define SCU_SFSP9_5_EZI_Msk (0x01UL << SCU_SFSP9_5_EZI_Pos) /*!< SCU SFSP9_5: EZI Mask */\r
-#define SCU_SFSP9_5_EHD_Pos 8 /*!< SCU SFSP9_5: EHD Position */\r
-#define SCU_SFSP9_5_EHD_Msk (0x03UL << SCU_SFSP9_5_EHD_Pos) /*!< SCU SFSP9_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSP9_6 ------------------------------------------\r
-#define SCU_SFSP9_6_MODE_Pos 0 /*!< SCU SFSP9_6: MODE Position */\r
-#define SCU_SFSP9_6_MODE_Msk (0x07UL << SCU_SFSP9_6_MODE_Pos) /*!< SCU SFSP9_6: MODE Mask */\r
-#define SCU_SFSP9_6_EPD_Pos 3 /*!< SCU SFSP9_6: EPD Position */\r
-#define SCU_SFSP9_6_EPD_Msk (0x01UL << SCU_SFSP9_6_EPD_Pos) /*!< SCU SFSP9_6: EPD Mask */\r
-#define SCU_SFSP9_6_EPUN_Pos 4 /*!< SCU SFSP9_6: EPUN Position */\r
-#define SCU_SFSP9_6_EPUN_Msk (0x01UL << SCU_SFSP9_6_EPUN_Pos) /*!< SCU SFSP9_6: EPUN Mask */\r
-#define SCU_SFSP9_6_EHS_Pos 5 /*!< SCU SFSP9_6: EHS Position */\r
-#define SCU_SFSP9_6_EHS_Msk (0x01UL << SCU_SFSP9_6_EHS_Pos) /*!< SCU SFSP9_6: EHS Mask */\r
-#define SCU_SFSP9_6_EZI_Pos 6 /*!< SCU SFSP9_6: EZI Position */\r
-#define SCU_SFSP9_6_EZI_Msk (0x01UL << SCU_SFSP9_6_EZI_Pos) /*!< SCU SFSP9_6: EZI Mask */\r
-#define SCU_SFSP9_6_EHD_Pos 8 /*!< SCU SFSP9_6: EHD Position */\r
-#define SCU_SFSP9_6_EHD_Msk (0x03UL << SCU_SFSP9_6_EHD_Pos) /*!< SCU SFSP9_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPA_0 ------------------------------------------\r
-#define SCU_SFSPA_0_MODE_Pos 0 /*!< SCU SFSPA_0: MODE Position */\r
-#define SCU_SFSPA_0_MODE_Msk (0x07UL << SCU_SFSPA_0_MODE_Pos) /*!< SCU SFSPA_0: MODE Mask */\r
-#define SCU_SFSPA_0_EPD_Pos 3 /*!< SCU SFSPA_0: EPD Position */\r
-#define SCU_SFSPA_0_EPD_Msk (0x01UL << SCU_SFSPA_0_EPD_Pos) /*!< SCU SFSPA_0: EPD Mask */\r
-#define SCU_SFSPA_0_EPUN_Pos 4 /*!< SCU SFSPA_0: EPUN Position */\r
-#define SCU_SFSPA_0_EPUN_Msk (0x01UL << SCU_SFSPA_0_EPUN_Pos) /*!< SCU SFSPA_0: EPUN Mask */\r
-#define SCU_SFSPA_0_EHS_Pos 5 /*!< SCU SFSPA_0: EHS Position */\r
-#define SCU_SFSPA_0_EHS_Msk (0x01UL << SCU_SFSPA_0_EHS_Pos) /*!< SCU SFSPA_0: EHS Mask */\r
-#define SCU_SFSPA_0_EZI_Pos 6 /*!< SCU SFSPA_0: EZI Position */\r
-#define SCU_SFSPA_0_EZI_Msk (0x01UL << SCU_SFSPA_0_EZI_Pos) /*!< SCU SFSPA_0: EZI Mask */\r
-#define SCU_SFSPA_0_EHD_Pos 8 /*!< SCU SFSPA_0: EHD Position */\r
-#define SCU_SFSPA_0_EHD_Msk (0x03UL << SCU_SFSPA_0_EHD_Pos) /*!< SCU SFSPA_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPA_1 ------------------------------------------\r
-#define SCU_SFSPA_1_MODE_Pos 0 /*!< SCU SFSPA_1: MODE Position */\r
-#define SCU_SFSPA_1_MODE_Msk (0x07UL << SCU_SFSPA_1_MODE_Pos) /*!< SCU SFSPA_1: MODE Mask */\r
-#define SCU_SFSPA_1_EPD_Pos 3 /*!< SCU SFSPA_1: EPD Position */\r
-#define SCU_SFSPA_1_EPD_Msk (0x01UL << SCU_SFSPA_1_EPD_Pos) /*!< SCU SFSPA_1: EPD Mask */\r
-#define SCU_SFSPA_1_EPUN_Pos 4 /*!< SCU SFSPA_1: EPUN Position */\r
-#define SCU_SFSPA_1_EPUN_Msk (0x01UL << SCU_SFSPA_1_EPUN_Pos) /*!< SCU SFSPA_1: EPUN Mask */\r
-#define SCU_SFSPA_1_EHS_Pos 5 /*!< SCU SFSPA_1: EHS Position */\r
-#define SCU_SFSPA_1_EHS_Msk (0x01UL << SCU_SFSPA_1_EHS_Pos) /*!< SCU SFSPA_1: EHS Mask */\r
-#define SCU_SFSPA_1_EZI_Pos 6 /*!< SCU SFSPA_1: EZI Position */\r
-#define SCU_SFSPA_1_EZI_Msk (0x01UL << SCU_SFSPA_1_EZI_Pos) /*!< SCU SFSPA_1: EZI Mask */\r
-#define SCU_SFSPA_1_EHD_Pos 8 /*!< SCU SFSPA_1: EHD Position */\r
-#define SCU_SFSPA_1_EHD_Msk (0x03UL << SCU_SFSPA_1_EHD_Pos) /*!< SCU SFSPA_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPA_2 ------------------------------------------\r
-#define SCU_SFSPA_2_MODE_Pos 0 /*!< SCU SFSPA_2: MODE Position */\r
-#define SCU_SFSPA_2_MODE_Msk (0x07UL << SCU_SFSPA_2_MODE_Pos) /*!< SCU SFSPA_2: MODE Mask */\r
-#define SCU_SFSPA_2_EPD_Pos 3 /*!< SCU SFSPA_2: EPD Position */\r
-#define SCU_SFSPA_2_EPD_Msk (0x01UL << SCU_SFSPA_2_EPD_Pos) /*!< SCU SFSPA_2: EPD Mask */\r
-#define SCU_SFSPA_2_EPUN_Pos 4 /*!< SCU SFSPA_2: EPUN Position */\r
-#define SCU_SFSPA_2_EPUN_Msk (0x01UL << SCU_SFSPA_2_EPUN_Pos) /*!< SCU SFSPA_2: EPUN Mask */\r
-#define SCU_SFSPA_2_EHS_Pos 5 /*!< SCU SFSPA_2: EHS Position */\r
-#define SCU_SFSPA_2_EHS_Msk (0x01UL << SCU_SFSPA_2_EHS_Pos) /*!< SCU SFSPA_2: EHS Mask */\r
-#define SCU_SFSPA_2_EZI_Pos 6 /*!< SCU SFSPA_2: EZI Position */\r
-#define SCU_SFSPA_2_EZI_Msk (0x01UL << SCU_SFSPA_2_EZI_Pos) /*!< SCU SFSPA_2: EZI Mask */\r
-#define SCU_SFSPA_2_EHD_Pos 8 /*!< SCU SFSPA_2: EHD Position */\r
-#define SCU_SFSPA_2_EHD_Msk (0x03UL << SCU_SFSPA_2_EHD_Pos) /*!< SCU SFSPA_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPA_3 ------------------------------------------\r
-#define SCU_SFSPA_3_MODE_Pos 0 /*!< SCU SFSPA_3: MODE Position */\r
-#define SCU_SFSPA_3_MODE_Msk (0x07UL << SCU_SFSPA_3_MODE_Pos) /*!< SCU SFSPA_3: MODE Mask */\r
-#define SCU_SFSPA_3_EPD_Pos 3 /*!< SCU SFSPA_3: EPD Position */\r
-#define SCU_SFSPA_3_EPD_Msk (0x01UL << SCU_SFSPA_3_EPD_Pos) /*!< SCU SFSPA_3: EPD Mask */\r
-#define SCU_SFSPA_3_EPUN_Pos 4 /*!< SCU SFSPA_3: EPUN Position */\r
-#define SCU_SFSPA_3_EPUN_Msk (0x01UL << SCU_SFSPA_3_EPUN_Pos) /*!< SCU SFSPA_3: EPUN Mask */\r
-#define SCU_SFSPA_3_EHS_Pos 5 /*!< SCU SFSPA_3: EHS Position */\r
-#define SCU_SFSPA_3_EHS_Msk (0x01UL << SCU_SFSPA_3_EHS_Pos) /*!< SCU SFSPA_3: EHS Mask */\r
-#define SCU_SFSPA_3_EZI_Pos 6 /*!< SCU SFSPA_3: EZI Position */\r
-#define SCU_SFSPA_3_EZI_Msk (0x01UL << SCU_SFSPA_3_EZI_Pos) /*!< SCU SFSPA_3: EZI Mask */\r
-#define SCU_SFSPA_3_EHD_Pos 8 /*!< SCU SFSPA_3: EHD Position */\r
-#define SCU_SFSPA_3_EHD_Msk (0x03UL << SCU_SFSPA_3_EHD_Pos) /*!< SCU SFSPA_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPA_4 ------------------------------------------\r
-#define SCU_SFSPA_4_MODE_Pos 0 /*!< SCU SFSPA_4: MODE Position */\r
-#define SCU_SFSPA_4_MODE_Msk (0x07UL << SCU_SFSPA_4_MODE_Pos) /*!< SCU SFSPA_4: MODE Mask */\r
-#define SCU_SFSPA_4_EPD_Pos 3 /*!< SCU SFSPA_4: EPD Position */\r
-#define SCU_SFSPA_4_EPD_Msk (0x01UL << SCU_SFSPA_4_EPD_Pos) /*!< SCU SFSPA_4: EPD Mask */\r
-#define SCU_SFSPA_4_EPUN_Pos 4 /*!< SCU SFSPA_4: EPUN Position */\r
-#define SCU_SFSPA_4_EPUN_Msk (0x01UL << SCU_SFSPA_4_EPUN_Pos) /*!< SCU SFSPA_4: EPUN Mask */\r
-#define SCU_SFSPA_4_EHS_Pos 5 /*!< SCU SFSPA_4: EHS Position */\r
-#define SCU_SFSPA_4_EHS_Msk (0x01UL << SCU_SFSPA_4_EHS_Pos) /*!< SCU SFSPA_4: EHS Mask */\r
-#define SCU_SFSPA_4_EZI_Pos 6 /*!< SCU SFSPA_4: EZI Position */\r
-#define SCU_SFSPA_4_EZI_Msk (0x01UL << SCU_SFSPA_4_EZI_Pos) /*!< SCU SFSPA_4: EZI Mask */\r
-#define SCU_SFSPA_4_EHD_Pos 8 /*!< SCU SFSPA_4: EHD Position */\r
-#define SCU_SFSPA_4_EHD_Msk (0x03UL << SCU_SFSPA_4_EHD_Pos) /*!< SCU SFSPA_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPB_0 ------------------------------------------\r
-#define SCU_SFSPB_0_MODE_Pos 0 /*!< SCU SFSPB_0: MODE Position */\r
-#define SCU_SFSPB_0_MODE_Msk (0x07UL << SCU_SFSPB_0_MODE_Pos) /*!< SCU SFSPB_0: MODE Mask */\r
-#define SCU_SFSPB_0_EPD_Pos 3 /*!< SCU SFSPB_0: EPD Position */\r
-#define SCU_SFSPB_0_EPD_Msk (0x01UL << SCU_SFSPB_0_EPD_Pos) /*!< SCU SFSPB_0: EPD Mask */\r
-#define SCU_SFSPB_0_EPUN_Pos 4 /*!< SCU SFSPB_0: EPUN Position */\r
-#define SCU_SFSPB_0_EPUN_Msk (0x01UL << SCU_SFSPB_0_EPUN_Pos) /*!< SCU SFSPB_0: EPUN Mask */\r
-#define SCU_SFSPB_0_EHS_Pos 5 /*!< SCU SFSPB_0: EHS Position */\r
-#define SCU_SFSPB_0_EHS_Msk (0x01UL << SCU_SFSPB_0_EHS_Pos) /*!< SCU SFSPB_0: EHS Mask */\r
-#define SCU_SFSPB_0_EZI_Pos 6 /*!< SCU SFSPB_0: EZI Position */\r
-#define SCU_SFSPB_0_EZI_Msk (0x01UL << SCU_SFSPB_0_EZI_Pos) /*!< SCU SFSPB_0: EZI Mask */\r
-#define SCU_SFSPB_0_EHD_Pos 8 /*!< SCU SFSPB_0: EHD Position */\r
-#define SCU_SFSPB_0_EHD_Msk (0x03UL << SCU_SFSPB_0_EHD_Pos) /*!< SCU SFSPB_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPB_1 ------------------------------------------\r
-#define SCU_SFSPB_1_MODE_Pos 0 /*!< SCU SFSPB_1: MODE Position */\r
-#define SCU_SFSPB_1_MODE_Msk (0x07UL << SCU_SFSPB_1_MODE_Pos) /*!< SCU SFSPB_1: MODE Mask */\r
-#define SCU_SFSPB_1_EPD_Pos 3 /*!< SCU SFSPB_1: EPD Position */\r
-#define SCU_SFSPB_1_EPD_Msk (0x01UL << SCU_SFSPB_1_EPD_Pos) /*!< SCU SFSPB_1: EPD Mask */\r
-#define SCU_SFSPB_1_EPUN_Pos 4 /*!< SCU SFSPB_1: EPUN Position */\r
-#define SCU_SFSPB_1_EPUN_Msk (0x01UL << SCU_SFSPB_1_EPUN_Pos) /*!< SCU SFSPB_1: EPUN Mask */\r
-#define SCU_SFSPB_1_EHS_Pos 5 /*!< SCU SFSPB_1: EHS Position */\r
-#define SCU_SFSPB_1_EHS_Msk (0x01UL << SCU_SFSPB_1_EHS_Pos) /*!< SCU SFSPB_1: EHS Mask */\r
-#define SCU_SFSPB_1_EZI_Pos 6 /*!< SCU SFSPB_1: EZI Position */\r
-#define SCU_SFSPB_1_EZI_Msk (0x01UL << SCU_SFSPB_1_EZI_Pos) /*!< SCU SFSPB_1: EZI Mask */\r
-#define SCU_SFSPB_1_EHD_Pos 8 /*!< SCU SFSPB_1: EHD Position */\r
-#define SCU_SFSPB_1_EHD_Msk (0x03UL << SCU_SFSPB_1_EHD_Pos) /*!< SCU SFSPB_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPB_2 ------------------------------------------\r
-#define SCU_SFSPB_2_MODE_Pos 0 /*!< SCU SFSPB_2: MODE Position */\r
-#define SCU_SFSPB_2_MODE_Msk (0x07UL << SCU_SFSPB_2_MODE_Pos) /*!< SCU SFSPB_2: MODE Mask */\r
-#define SCU_SFSPB_2_EPD_Pos 3 /*!< SCU SFSPB_2: EPD Position */\r
-#define SCU_SFSPB_2_EPD_Msk (0x01UL << SCU_SFSPB_2_EPD_Pos) /*!< SCU SFSPB_2: EPD Mask */\r
-#define SCU_SFSPB_2_EPUN_Pos 4 /*!< SCU SFSPB_2: EPUN Position */\r
-#define SCU_SFSPB_2_EPUN_Msk (0x01UL << SCU_SFSPB_2_EPUN_Pos) /*!< SCU SFSPB_2: EPUN Mask */\r
-#define SCU_SFSPB_2_EHS_Pos 5 /*!< SCU SFSPB_2: EHS Position */\r
-#define SCU_SFSPB_2_EHS_Msk (0x01UL << SCU_SFSPB_2_EHS_Pos) /*!< SCU SFSPB_2: EHS Mask */\r
-#define SCU_SFSPB_2_EZI_Pos 6 /*!< SCU SFSPB_2: EZI Position */\r
-#define SCU_SFSPB_2_EZI_Msk (0x01UL << SCU_SFSPB_2_EZI_Pos) /*!< SCU SFSPB_2: EZI Mask */\r
-#define SCU_SFSPB_2_EHD_Pos 8 /*!< SCU SFSPB_2: EHD Position */\r
-#define SCU_SFSPB_2_EHD_Msk (0x03UL << SCU_SFSPB_2_EHD_Pos) /*!< SCU SFSPB_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPB_3 ------------------------------------------\r
-#define SCU_SFSPB_3_MODE_Pos 0 /*!< SCU SFSPB_3: MODE Position */\r
-#define SCU_SFSPB_3_MODE_Msk (0x07UL << SCU_SFSPB_3_MODE_Pos) /*!< SCU SFSPB_3: MODE Mask */\r
-#define SCU_SFSPB_3_EPD_Pos 3 /*!< SCU SFSPB_3: EPD Position */\r
-#define SCU_SFSPB_3_EPD_Msk (0x01UL << SCU_SFSPB_3_EPD_Pos) /*!< SCU SFSPB_3: EPD Mask */\r
-#define SCU_SFSPB_3_EPUN_Pos 4 /*!< SCU SFSPB_3: EPUN Position */\r
-#define SCU_SFSPB_3_EPUN_Msk (0x01UL << SCU_SFSPB_3_EPUN_Pos) /*!< SCU SFSPB_3: EPUN Mask */\r
-#define SCU_SFSPB_3_EHS_Pos 5 /*!< SCU SFSPB_3: EHS Position */\r
-#define SCU_SFSPB_3_EHS_Msk (0x01UL << SCU_SFSPB_3_EHS_Pos) /*!< SCU SFSPB_3: EHS Mask */\r
-#define SCU_SFSPB_3_EZI_Pos 6 /*!< SCU SFSPB_3: EZI Position */\r
-#define SCU_SFSPB_3_EZI_Msk (0x01UL << SCU_SFSPB_3_EZI_Pos) /*!< SCU SFSPB_3: EZI Mask */\r
-#define SCU_SFSPB_3_EHD_Pos 8 /*!< SCU SFSPB_3: EHD Position */\r
-#define SCU_SFSPB_3_EHD_Msk (0x03UL << SCU_SFSPB_3_EHD_Pos) /*!< SCU SFSPB_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPB_4 ------------------------------------------\r
-#define SCU_SFSPB_4_MODE_Pos 0 /*!< SCU SFSPB_4: MODE Position */\r
-#define SCU_SFSPB_4_MODE_Msk (0x07UL << SCU_SFSPB_4_MODE_Pos) /*!< SCU SFSPB_4: MODE Mask */\r
-#define SCU_SFSPB_4_EPD_Pos 3 /*!< SCU SFSPB_4: EPD Position */\r
-#define SCU_SFSPB_4_EPD_Msk (0x01UL << SCU_SFSPB_4_EPD_Pos) /*!< SCU SFSPB_4: EPD Mask */\r
-#define SCU_SFSPB_4_EPUN_Pos 4 /*!< SCU SFSPB_4: EPUN Position */\r
-#define SCU_SFSPB_4_EPUN_Msk (0x01UL << SCU_SFSPB_4_EPUN_Pos) /*!< SCU SFSPB_4: EPUN Mask */\r
-#define SCU_SFSPB_4_EHS_Pos 5 /*!< SCU SFSPB_4: EHS Position */\r
-#define SCU_SFSPB_4_EHS_Msk (0x01UL << SCU_SFSPB_4_EHS_Pos) /*!< SCU SFSPB_4: EHS Mask */\r
-#define SCU_SFSPB_4_EZI_Pos 6 /*!< SCU SFSPB_4: EZI Position */\r
-#define SCU_SFSPB_4_EZI_Msk (0x01UL << SCU_SFSPB_4_EZI_Pos) /*!< SCU SFSPB_4: EZI Mask */\r
-#define SCU_SFSPB_4_EHD_Pos 8 /*!< SCU SFSPB_4: EHD Position */\r
-#define SCU_SFSPB_4_EHD_Msk (0x03UL << SCU_SFSPB_4_EHD_Pos) /*!< SCU SFSPB_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPB_5 ------------------------------------------\r
-#define SCU_SFSPB_5_MODE_Pos 0 /*!< SCU SFSPB_5: MODE Position */\r
-#define SCU_SFSPB_5_MODE_Msk (0x07UL << SCU_SFSPB_5_MODE_Pos) /*!< SCU SFSPB_5: MODE Mask */\r
-#define SCU_SFSPB_5_EPD_Pos 3 /*!< SCU SFSPB_5: EPD Position */\r
-#define SCU_SFSPB_5_EPD_Msk (0x01UL << SCU_SFSPB_5_EPD_Pos) /*!< SCU SFSPB_5: EPD Mask */\r
-#define SCU_SFSPB_5_EPUN_Pos 4 /*!< SCU SFSPB_5: EPUN Position */\r
-#define SCU_SFSPB_5_EPUN_Msk (0x01UL << SCU_SFSPB_5_EPUN_Pos) /*!< SCU SFSPB_5: EPUN Mask */\r
-#define SCU_SFSPB_5_EHS_Pos 5 /*!< SCU SFSPB_5: EHS Position */\r
-#define SCU_SFSPB_5_EHS_Msk (0x01UL << SCU_SFSPB_5_EHS_Pos) /*!< SCU SFSPB_5: EHS Mask */\r
-#define SCU_SFSPB_5_EZI_Pos 6 /*!< SCU SFSPB_5: EZI Position */\r
-#define SCU_SFSPB_5_EZI_Msk (0x01UL << SCU_SFSPB_5_EZI_Pos) /*!< SCU SFSPB_5: EZI Mask */\r
-#define SCU_SFSPB_5_EHD_Pos 8 /*!< SCU SFSPB_5: EHD Position */\r
-#define SCU_SFSPB_5_EHD_Msk (0x03UL << SCU_SFSPB_5_EHD_Pos) /*!< SCU SFSPB_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPB_6 ------------------------------------------\r
-#define SCU_SFSPB_6_MODE_Pos 0 /*!< SCU SFSPB_6: MODE Position */\r
-#define SCU_SFSPB_6_MODE_Msk (0x07UL << SCU_SFSPB_6_MODE_Pos) /*!< SCU SFSPB_6: MODE Mask */\r
-#define SCU_SFSPB_6_EPD_Pos 3 /*!< SCU SFSPB_6: EPD Position */\r
-#define SCU_SFSPB_6_EPD_Msk (0x01UL << SCU_SFSPB_6_EPD_Pos) /*!< SCU SFSPB_6: EPD Mask */\r
-#define SCU_SFSPB_6_EPUN_Pos 4 /*!< SCU SFSPB_6: EPUN Position */\r
-#define SCU_SFSPB_6_EPUN_Msk (0x01UL << SCU_SFSPB_6_EPUN_Pos) /*!< SCU SFSPB_6: EPUN Mask */\r
-#define SCU_SFSPB_6_EHS_Pos 5 /*!< SCU SFSPB_6: EHS Position */\r
-#define SCU_SFSPB_6_EHS_Msk (0x01UL << SCU_SFSPB_6_EHS_Pos) /*!< SCU SFSPB_6: EHS Mask */\r
-#define SCU_SFSPB_6_EZI_Pos 6 /*!< SCU SFSPB_6: EZI Position */\r
-#define SCU_SFSPB_6_EZI_Msk (0x01UL << SCU_SFSPB_6_EZI_Pos) /*!< SCU SFSPB_6: EZI Mask */\r
-#define SCU_SFSPB_6_EHD_Pos 8 /*!< SCU SFSPB_6: EHD Position */\r
-#define SCU_SFSPB_6_EHD_Msk (0x03UL << SCU_SFSPB_6_EHD_Pos) /*!< SCU SFSPB_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_0 ------------------------------------------\r
-#define SCU_SFSPC_0_MODE_Pos 0 /*!< SCU SFSPC_0: MODE Position */\r
-#define SCU_SFSPC_0_MODE_Msk (0x07UL << SCU_SFSPC_0_MODE_Pos) /*!< SCU SFSPC_0: MODE Mask */\r
-#define SCU_SFSPC_0_EPD_Pos 3 /*!< SCU SFSPC_0: EPD Position */\r
-#define SCU_SFSPC_0_EPD_Msk (0x01UL << SCU_SFSPC_0_EPD_Pos) /*!< SCU SFSPC_0: EPD Mask */\r
-#define SCU_SFSPC_0_EPUN_Pos 4 /*!< SCU SFSPC_0: EPUN Position */\r
-#define SCU_SFSPC_0_EPUN_Msk (0x01UL << SCU_SFSPC_0_EPUN_Pos) /*!< SCU SFSPC_0: EPUN Mask */\r
-#define SCU_SFSPC_0_EHS_Pos 5 /*!< SCU SFSPC_0: EHS Position */\r
-#define SCU_SFSPC_0_EHS_Msk (0x01UL << SCU_SFSPC_0_EHS_Pos) /*!< SCU SFSPC_0: EHS Mask */\r
-#define SCU_SFSPC_0_EZI_Pos 6 /*!< SCU SFSPC_0: EZI Position */\r
-#define SCU_SFSPC_0_EZI_Msk (0x01UL << SCU_SFSPC_0_EZI_Pos) /*!< SCU SFSPC_0: EZI Mask */\r
-#define SCU_SFSPC_0_EHD_Pos 8 /*!< SCU SFSPC_0: EHD Position */\r
-#define SCU_SFSPC_0_EHD_Msk (0x03UL << SCU_SFSPC_0_EHD_Pos) /*!< SCU SFSPC_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_1 ------------------------------------------\r
-#define SCU_SFSPC_1_MODE_Pos 0 /*!< SCU SFSPC_1: MODE Position */\r
-#define SCU_SFSPC_1_MODE_Msk (0x07UL << SCU_SFSPC_1_MODE_Pos) /*!< SCU SFSPC_1: MODE Mask */\r
-#define SCU_SFSPC_1_EPD_Pos 3 /*!< SCU SFSPC_1: EPD Position */\r
-#define SCU_SFSPC_1_EPD_Msk (0x01UL << SCU_SFSPC_1_EPD_Pos) /*!< SCU SFSPC_1: EPD Mask */\r
-#define SCU_SFSPC_1_EPUN_Pos 4 /*!< SCU SFSPC_1: EPUN Position */\r
-#define SCU_SFSPC_1_EPUN_Msk (0x01UL << SCU_SFSPC_1_EPUN_Pos) /*!< SCU SFSPC_1: EPUN Mask */\r
-#define SCU_SFSPC_1_EHS_Pos 5 /*!< SCU SFSPC_1: EHS Position */\r
-#define SCU_SFSPC_1_EHS_Msk (0x01UL << SCU_SFSPC_1_EHS_Pos) /*!< SCU SFSPC_1: EHS Mask */\r
-#define SCU_SFSPC_1_EZI_Pos 6 /*!< SCU SFSPC_1: EZI Position */\r
-#define SCU_SFSPC_1_EZI_Msk (0x01UL << SCU_SFSPC_1_EZI_Pos) /*!< SCU SFSPC_1: EZI Mask */\r
-#define SCU_SFSPC_1_EHD_Pos 8 /*!< SCU SFSPC_1: EHD Position */\r
-#define SCU_SFSPC_1_EHD_Msk (0x03UL << SCU_SFSPC_1_EHD_Pos) /*!< SCU SFSPC_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_2 ------------------------------------------\r
-#define SCU_SFSPC_2_MODE_Pos 0 /*!< SCU SFSPC_2: MODE Position */\r
-#define SCU_SFSPC_2_MODE_Msk (0x07UL << SCU_SFSPC_2_MODE_Pos) /*!< SCU SFSPC_2: MODE Mask */\r
-#define SCU_SFSPC_2_EPD_Pos 3 /*!< SCU SFSPC_2: EPD Position */\r
-#define SCU_SFSPC_2_EPD_Msk (0x01UL << SCU_SFSPC_2_EPD_Pos) /*!< SCU SFSPC_2: EPD Mask */\r
-#define SCU_SFSPC_2_EPUN_Pos 4 /*!< SCU SFSPC_2: EPUN Position */\r
-#define SCU_SFSPC_2_EPUN_Msk (0x01UL << SCU_SFSPC_2_EPUN_Pos) /*!< SCU SFSPC_2: EPUN Mask */\r
-#define SCU_SFSPC_2_EHS_Pos 5 /*!< SCU SFSPC_2: EHS Position */\r
-#define SCU_SFSPC_2_EHS_Msk (0x01UL << SCU_SFSPC_2_EHS_Pos) /*!< SCU SFSPC_2: EHS Mask */\r
-#define SCU_SFSPC_2_EZI_Pos 6 /*!< SCU SFSPC_2: EZI Position */\r
-#define SCU_SFSPC_2_EZI_Msk (0x01UL << SCU_SFSPC_2_EZI_Pos) /*!< SCU SFSPC_2: EZI Mask */\r
-#define SCU_SFSPC_2_EHD_Pos 8 /*!< SCU SFSPC_2: EHD Position */\r
-#define SCU_SFSPC_2_EHD_Msk (0x03UL << SCU_SFSPC_2_EHD_Pos) /*!< SCU SFSPC_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_3 ------------------------------------------\r
-#define SCU_SFSPC_3_MODE_Pos 0 /*!< SCU SFSPC_3: MODE Position */\r
-#define SCU_SFSPC_3_MODE_Msk (0x07UL << SCU_SFSPC_3_MODE_Pos) /*!< SCU SFSPC_3: MODE Mask */\r
-#define SCU_SFSPC_3_EPD_Pos 3 /*!< SCU SFSPC_3: EPD Position */\r
-#define SCU_SFSPC_3_EPD_Msk (0x01UL << SCU_SFSPC_3_EPD_Pos) /*!< SCU SFSPC_3: EPD Mask */\r
-#define SCU_SFSPC_3_EPUN_Pos 4 /*!< SCU SFSPC_3: EPUN Position */\r
-#define SCU_SFSPC_3_EPUN_Msk (0x01UL << SCU_SFSPC_3_EPUN_Pos) /*!< SCU SFSPC_3: EPUN Mask */\r
-#define SCU_SFSPC_3_EHS_Pos 5 /*!< SCU SFSPC_3: EHS Position */\r
-#define SCU_SFSPC_3_EHS_Msk (0x01UL << SCU_SFSPC_3_EHS_Pos) /*!< SCU SFSPC_3: EHS Mask */\r
-#define SCU_SFSPC_3_EZI_Pos 6 /*!< SCU SFSPC_3: EZI Position */\r
-#define SCU_SFSPC_3_EZI_Msk (0x01UL << SCU_SFSPC_3_EZI_Pos) /*!< SCU SFSPC_3: EZI Mask */\r
-#define SCU_SFSPC_3_EHD_Pos 8 /*!< SCU SFSPC_3: EHD Position */\r
-#define SCU_SFSPC_3_EHD_Msk (0x03UL << SCU_SFSPC_3_EHD_Pos) /*!< SCU SFSPC_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_4 ------------------------------------------\r
-#define SCU_SFSPC_4_MODE_Pos 0 /*!< SCU SFSPC_4: MODE Position */\r
-#define SCU_SFSPC_4_MODE_Msk (0x07UL << SCU_SFSPC_4_MODE_Pos) /*!< SCU SFSPC_4: MODE Mask */\r
-#define SCU_SFSPC_4_EPD_Pos 3 /*!< SCU SFSPC_4: EPD Position */\r
-#define SCU_SFSPC_4_EPD_Msk (0x01UL << SCU_SFSPC_4_EPD_Pos) /*!< SCU SFSPC_4: EPD Mask */\r
-#define SCU_SFSPC_4_EPUN_Pos 4 /*!< SCU SFSPC_4: EPUN Position */\r
-#define SCU_SFSPC_4_EPUN_Msk (0x01UL << SCU_SFSPC_4_EPUN_Pos) /*!< SCU SFSPC_4: EPUN Mask */\r
-#define SCU_SFSPC_4_EHS_Pos 5 /*!< SCU SFSPC_4: EHS Position */\r
-#define SCU_SFSPC_4_EHS_Msk (0x01UL << SCU_SFSPC_4_EHS_Pos) /*!< SCU SFSPC_4: EHS Mask */\r
-#define SCU_SFSPC_4_EZI_Pos 6 /*!< SCU SFSPC_4: EZI Position */\r
-#define SCU_SFSPC_4_EZI_Msk (0x01UL << SCU_SFSPC_4_EZI_Pos) /*!< SCU SFSPC_4: EZI Mask */\r
-#define SCU_SFSPC_4_EHD_Pos 8 /*!< SCU SFSPC_4: EHD Position */\r
-#define SCU_SFSPC_4_EHD_Msk (0x03UL << SCU_SFSPC_4_EHD_Pos) /*!< SCU SFSPC_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_5 ------------------------------------------\r
-#define SCU_SFSPC_5_MODE_Pos 0 /*!< SCU SFSPC_5: MODE Position */\r
-#define SCU_SFSPC_5_MODE_Msk (0x07UL << SCU_SFSPC_5_MODE_Pos) /*!< SCU SFSPC_5: MODE Mask */\r
-#define SCU_SFSPC_5_EPD_Pos 3 /*!< SCU SFSPC_5: EPD Position */\r
-#define SCU_SFSPC_5_EPD_Msk (0x01UL << SCU_SFSPC_5_EPD_Pos) /*!< SCU SFSPC_5: EPD Mask */\r
-#define SCU_SFSPC_5_EPUN_Pos 4 /*!< SCU SFSPC_5: EPUN Position */\r
-#define SCU_SFSPC_5_EPUN_Msk (0x01UL << SCU_SFSPC_5_EPUN_Pos) /*!< SCU SFSPC_5: EPUN Mask */\r
-#define SCU_SFSPC_5_EHS_Pos 5 /*!< SCU SFSPC_5: EHS Position */\r
-#define SCU_SFSPC_5_EHS_Msk (0x01UL << SCU_SFSPC_5_EHS_Pos) /*!< SCU SFSPC_5: EHS Mask */\r
-#define SCU_SFSPC_5_EZI_Pos 6 /*!< SCU SFSPC_5: EZI Position */\r
-#define SCU_SFSPC_5_EZI_Msk (0x01UL << SCU_SFSPC_5_EZI_Pos) /*!< SCU SFSPC_5: EZI Mask */\r
-#define SCU_SFSPC_5_EHD_Pos 8 /*!< SCU SFSPC_5: EHD Position */\r
-#define SCU_SFSPC_5_EHD_Msk (0x03UL << SCU_SFSPC_5_EHD_Pos) /*!< SCU SFSPC_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_6 ------------------------------------------\r
-#define SCU_SFSPC_6_MODE_Pos 0 /*!< SCU SFSPC_6: MODE Position */\r
-#define SCU_SFSPC_6_MODE_Msk (0x07UL << SCU_SFSPC_6_MODE_Pos) /*!< SCU SFSPC_6: MODE Mask */\r
-#define SCU_SFSPC_6_EPD_Pos 3 /*!< SCU SFSPC_6: EPD Position */\r
-#define SCU_SFSPC_6_EPD_Msk (0x01UL << SCU_SFSPC_6_EPD_Pos) /*!< SCU SFSPC_6: EPD Mask */\r
-#define SCU_SFSPC_6_EPUN_Pos 4 /*!< SCU SFSPC_6: EPUN Position */\r
-#define SCU_SFSPC_6_EPUN_Msk (0x01UL << SCU_SFSPC_6_EPUN_Pos) /*!< SCU SFSPC_6: EPUN Mask */\r
-#define SCU_SFSPC_6_EHS_Pos 5 /*!< SCU SFSPC_6: EHS Position */\r
-#define SCU_SFSPC_6_EHS_Msk (0x01UL << SCU_SFSPC_6_EHS_Pos) /*!< SCU SFSPC_6: EHS Mask */\r
-#define SCU_SFSPC_6_EZI_Pos 6 /*!< SCU SFSPC_6: EZI Position */\r
-#define SCU_SFSPC_6_EZI_Msk (0x01UL << SCU_SFSPC_6_EZI_Pos) /*!< SCU SFSPC_6: EZI Mask */\r
-#define SCU_SFSPC_6_EHD_Pos 8 /*!< SCU SFSPC_6: EHD Position */\r
-#define SCU_SFSPC_6_EHD_Msk (0x03UL << SCU_SFSPC_6_EHD_Pos) /*!< SCU SFSPC_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_7 ------------------------------------------\r
-#define SCU_SFSPC_7_MODE_Pos 0 /*!< SCU SFSPC_7: MODE Position */\r
-#define SCU_SFSPC_7_MODE_Msk (0x07UL << SCU_SFSPC_7_MODE_Pos) /*!< SCU SFSPC_7: MODE Mask */\r
-#define SCU_SFSPC_7_EPD_Pos 3 /*!< SCU SFSPC_7: EPD Position */\r
-#define SCU_SFSPC_7_EPD_Msk (0x01UL << SCU_SFSPC_7_EPD_Pos) /*!< SCU SFSPC_7: EPD Mask */\r
-#define SCU_SFSPC_7_EPUN_Pos 4 /*!< SCU SFSPC_7: EPUN Position */\r
-#define SCU_SFSPC_7_EPUN_Msk (0x01UL << SCU_SFSPC_7_EPUN_Pos) /*!< SCU SFSPC_7: EPUN Mask */\r
-#define SCU_SFSPC_7_EHS_Pos 5 /*!< SCU SFSPC_7: EHS Position */\r
-#define SCU_SFSPC_7_EHS_Msk (0x01UL << SCU_SFSPC_7_EHS_Pos) /*!< SCU SFSPC_7: EHS Mask */\r
-#define SCU_SFSPC_7_EZI_Pos 6 /*!< SCU SFSPC_7: EZI Position */\r
-#define SCU_SFSPC_7_EZI_Msk (0x01UL << SCU_SFSPC_7_EZI_Pos) /*!< SCU SFSPC_7: EZI Mask */\r
-#define SCU_SFSPC_7_EHD_Pos 8 /*!< SCU SFSPC_7: EHD Position */\r
-#define SCU_SFSPC_7_EHD_Msk (0x03UL << SCU_SFSPC_7_EHD_Pos) /*!< SCU SFSPC_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_8 ------------------------------------------\r
-#define SCU_SFSPC_8_MODE_Pos 0 /*!< SCU SFSPC_8: MODE Position */\r
-#define SCU_SFSPC_8_MODE_Msk (0x07UL << SCU_SFSPC_8_MODE_Pos) /*!< SCU SFSPC_8: MODE Mask */\r
-#define SCU_SFSPC_8_EPD_Pos 3 /*!< SCU SFSPC_8: EPD Position */\r
-#define SCU_SFSPC_8_EPD_Msk (0x01UL << SCU_SFSPC_8_EPD_Pos) /*!< SCU SFSPC_8: EPD Mask */\r
-#define SCU_SFSPC_8_EPUN_Pos 4 /*!< SCU SFSPC_8: EPUN Position */\r
-#define SCU_SFSPC_8_EPUN_Msk (0x01UL << SCU_SFSPC_8_EPUN_Pos) /*!< SCU SFSPC_8: EPUN Mask */\r
-#define SCU_SFSPC_8_EHS_Pos 5 /*!< SCU SFSPC_8: EHS Position */\r
-#define SCU_SFSPC_8_EHS_Msk (0x01UL << SCU_SFSPC_8_EHS_Pos) /*!< SCU SFSPC_8: EHS Mask */\r
-#define SCU_SFSPC_8_EZI_Pos 6 /*!< SCU SFSPC_8: EZI Position */\r
-#define SCU_SFSPC_8_EZI_Msk (0x01UL << SCU_SFSPC_8_EZI_Pos) /*!< SCU SFSPC_8: EZI Mask */\r
-#define SCU_SFSPC_8_EHD_Pos 8 /*!< SCU SFSPC_8: EHD Position */\r
-#define SCU_SFSPC_8_EHD_Msk (0x03UL << SCU_SFSPC_8_EHD_Pos) /*!< SCU SFSPC_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPC_9 ------------------------------------------\r
-#define SCU_SFSPC_9_MODE_Pos 0 /*!< SCU SFSPC_9: MODE Position */\r
-#define SCU_SFSPC_9_MODE_Msk (0x07UL << SCU_SFSPC_9_MODE_Pos) /*!< SCU SFSPC_9: MODE Mask */\r
-#define SCU_SFSPC_9_EPD_Pos 3 /*!< SCU SFSPC_9: EPD Position */\r
-#define SCU_SFSPC_9_EPD_Msk (0x01UL << SCU_SFSPC_9_EPD_Pos) /*!< SCU SFSPC_9: EPD Mask */\r
-#define SCU_SFSPC_9_EPUN_Pos 4 /*!< SCU SFSPC_9: EPUN Position */\r
-#define SCU_SFSPC_9_EPUN_Msk (0x01UL << SCU_SFSPC_9_EPUN_Pos) /*!< SCU SFSPC_9: EPUN Mask */\r
-#define SCU_SFSPC_9_EHS_Pos 5 /*!< SCU SFSPC_9: EHS Position */\r
-#define SCU_SFSPC_9_EHS_Msk (0x01UL << SCU_SFSPC_9_EHS_Pos) /*!< SCU SFSPC_9: EHS Mask */\r
-#define SCU_SFSPC_9_EZI_Pos 6 /*!< SCU SFSPC_9: EZI Position */\r
-#define SCU_SFSPC_9_EZI_Msk (0x01UL << SCU_SFSPC_9_EZI_Pos) /*!< SCU SFSPC_9: EZI Mask */\r
-#define SCU_SFSPC_9_EHD_Pos 8 /*!< SCU SFSPC_9: EHD Position */\r
-#define SCU_SFSPC_9_EHD_Msk (0x03UL << SCU_SFSPC_9_EHD_Pos) /*!< SCU SFSPC_9: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPC_10 ------------------------------------------\r
-#define SCU_SFSPC_10_MODE_Pos 0 /*!< SCU SFSPC_10: MODE Position */\r
-#define SCU_SFSPC_10_MODE_Msk (0x07UL << SCU_SFSPC_10_MODE_Pos) /*!< SCU SFSPC_10: MODE Mask */\r
-#define SCU_SFSPC_10_EPD_Pos 3 /*!< SCU SFSPC_10: EPD Position */\r
-#define SCU_SFSPC_10_EPD_Msk (0x01UL << SCU_SFSPC_10_EPD_Pos) /*!< SCU SFSPC_10: EPD Mask */\r
-#define SCU_SFSPC_10_EPUN_Pos 4 /*!< SCU SFSPC_10: EPUN Position */\r
-#define SCU_SFSPC_10_EPUN_Msk (0x01UL << SCU_SFSPC_10_EPUN_Pos) /*!< SCU SFSPC_10: EPUN Mask */\r
-#define SCU_SFSPC_10_EHS_Pos 5 /*!< SCU SFSPC_10: EHS Position */\r
-#define SCU_SFSPC_10_EHS_Msk (0x01UL << SCU_SFSPC_10_EHS_Pos) /*!< SCU SFSPC_10: EHS Mask */\r
-#define SCU_SFSPC_10_EZI_Pos 6 /*!< SCU SFSPC_10: EZI Position */\r
-#define SCU_SFSPC_10_EZI_Msk (0x01UL << SCU_SFSPC_10_EZI_Pos) /*!< SCU SFSPC_10: EZI Mask */\r
-#define SCU_SFSPC_10_EHD_Pos 8 /*!< SCU SFSPC_10: EHD Position */\r
-#define SCU_SFSPC_10_EHD_Msk (0x03UL << SCU_SFSPC_10_EHD_Pos) /*!< SCU SFSPC_10: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPC_11 ------------------------------------------\r
-#define SCU_SFSPC_11_MODE_Pos 0 /*!< SCU SFSPC_11: MODE Position */\r
-#define SCU_SFSPC_11_MODE_Msk (0x07UL << SCU_SFSPC_11_MODE_Pos) /*!< SCU SFSPC_11: MODE Mask */\r
-#define SCU_SFSPC_11_EPD_Pos 3 /*!< SCU SFSPC_11: EPD Position */\r
-#define SCU_SFSPC_11_EPD_Msk (0x01UL << SCU_SFSPC_11_EPD_Pos) /*!< SCU SFSPC_11: EPD Mask */\r
-#define SCU_SFSPC_11_EPUN_Pos 4 /*!< SCU SFSPC_11: EPUN Position */\r
-#define SCU_SFSPC_11_EPUN_Msk (0x01UL << SCU_SFSPC_11_EPUN_Pos) /*!< SCU SFSPC_11: EPUN Mask */\r
-#define SCU_SFSPC_11_EHS_Pos 5 /*!< SCU SFSPC_11: EHS Position */\r
-#define SCU_SFSPC_11_EHS_Msk (0x01UL << SCU_SFSPC_11_EHS_Pos) /*!< SCU SFSPC_11: EHS Mask */\r
-#define SCU_SFSPC_11_EZI_Pos 6 /*!< SCU SFSPC_11: EZI Position */\r
-#define SCU_SFSPC_11_EZI_Msk (0x01UL << SCU_SFSPC_11_EZI_Pos) /*!< SCU SFSPC_11: EZI Mask */\r
-#define SCU_SFSPC_11_EHD_Pos 8 /*!< SCU SFSPC_11: EHD Position */\r
-#define SCU_SFSPC_11_EHD_Msk (0x03UL << SCU_SFSPC_11_EHD_Pos) /*!< SCU SFSPC_11: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPC_12 ------------------------------------------\r
-#define SCU_SFSPC_12_MODE_Pos 0 /*!< SCU SFSPC_12: MODE Position */\r
-#define SCU_SFSPC_12_MODE_Msk (0x07UL << SCU_SFSPC_12_MODE_Pos) /*!< SCU SFSPC_12: MODE Mask */\r
-#define SCU_SFSPC_12_EPD_Pos 3 /*!< SCU SFSPC_12: EPD Position */\r
-#define SCU_SFSPC_12_EPD_Msk (0x01UL << SCU_SFSPC_12_EPD_Pos) /*!< SCU SFSPC_12: EPD Mask */\r
-#define SCU_SFSPC_12_EPUN_Pos 4 /*!< SCU SFSPC_12: EPUN Position */\r
-#define SCU_SFSPC_12_EPUN_Msk (0x01UL << SCU_SFSPC_12_EPUN_Pos) /*!< SCU SFSPC_12: EPUN Mask */\r
-#define SCU_SFSPC_12_EHS_Pos 5 /*!< SCU SFSPC_12: EHS Position */\r
-#define SCU_SFSPC_12_EHS_Msk (0x01UL << SCU_SFSPC_12_EHS_Pos) /*!< SCU SFSPC_12: EHS Mask */\r
-#define SCU_SFSPC_12_EZI_Pos 6 /*!< SCU SFSPC_12: EZI Position */\r
-#define SCU_SFSPC_12_EZI_Msk (0x01UL << SCU_SFSPC_12_EZI_Pos) /*!< SCU SFSPC_12: EZI Mask */\r
-#define SCU_SFSPC_12_EHD_Pos 8 /*!< SCU SFSPC_12: EHD Position */\r
-#define SCU_SFSPC_12_EHD_Msk (0x03UL << SCU_SFSPC_12_EHD_Pos) /*!< SCU SFSPC_12: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPC_13 ------------------------------------------\r
-#define SCU_SFSPC_13_MODE_Pos 0 /*!< SCU SFSPC_13: MODE Position */\r
-#define SCU_SFSPC_13_MODE_Msk (0x07UL << SCU_SFSPC_13_MODE_Pos) /*!< SCU SFSPC_13: MODE Mask */\r
-#define SCU_SFSPC_13_EPD_Pos 3 /*!< SCU SFSPC_13: EPD Position */\r
-#define SCU_SFSPC_13_EPD_Msk (0x01UL << SCU_SFSPC_13_EPD_Pos) /*!< SCU SFSPC_13: EPD Mask */\r
-#define SCU_SFSPC_13_EPUN_Pos 4 /*!< SCU SFSPC_13: EPUN Position */\r
-#define SCU_SFSPC_13_EPUN_Msk (0x01UL << SCU_SFSPC_13_EPUN_Pos) /*!< SCU SFSPC_13: EPUN Mask */\r
-#define SCU_SFSPC_13_EHS_Pos 5 /*!< SCU SFSPC_13: EHS Position */\r
-#define SCU_SFSPC_13_EHS_Msk (0x01UL << SCU_SFSPC_13_EHS_Pos) /*!< SCU SFSPC_13: EHS Mask */\r
-#define SCU_SFSPC_13_EZI_Pos 6 /*!< SCU SFSPC_13: EZI Position */\r
-#define SCU_SFSPC_13_EZI_Msk (0x01UL << SCU_SFSPC_13_EZI_Pos) /*!< SCU SFSPC_13: EZI Mask */\r
-#define SCU_SFSPC_13_EHD_Pos 8 /*!< SCU SFSPC_13: EHD Position */\r
-#define SCU_SFSPC_13_EHD_Msk (0x03UL << SCU_SFSPC_13_EHD_Pos) /*!< SCU SFSPC_13: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPC_14 ------------------------------------------\r
-#define SCU_SFSPC_14_MODE_Pos 0 /*!< SCU SFSPC_14: MODE Position */\r
-#define SCU_SFSPC_14_MODE_Msk (0x07UL << SCU_SFSPC_14_MODE_Pos) /*!< SCU SFSPC_14: MODE Mask */\r
-#define SCU_SFSPC_14_EPD_Pos 3 /*!< SCU SFSPC_14: EPD Position */\r
-#define SCU_SFSPC_14_EPD_Msk (0x01UL << SCU_SFSPC_14_EPD_Pos) /*!< SCU SFSPC_14: EPD Mask */\r
-#define SCU_SFSPC_14_EPUN_Pos 4 /*!< SCU SFSPC_14: EPUN Position */\r
-#define SCU_SFSPC_14_EPUN_Msk (0x01UL << SCU_SFSPC_14_EPUN_Pos) /*!< SCU SFSPC_14: EPUN Mask */\r
-#define SCU_SFSPC_14_EHS_Pos 5 /*!< SCU SFSPC_14: EHS Position */\r
-#define SCU_SFSPC_14_EHS_Msk (0x01UL << SCU_SFSPC_14_EHS_Pos) /*!< SCU SFSPC_14: EHS Mask */\r
-#define SCU_SFSPC_14_EZI_Pos 6 /*!< SCU SFSPC_14: EZI Position */\r
-#define SCU_SFSPC_14_EZI_Msk (0x01UL << SCU_SFSPC_14_EZI_Pos) /*!< SCU SFSPC_14: EZI Mask */\r
-#define SCU_SFSPC_14_EHD_Pos 8 /*!< SCU SFSPC_14: EHD Position */\r
-#define SCU_SFSPC_14_EHD_Msk (0x03UL << SCU_SFSPC_14_EHD_Pos) /*!< SCU SFSPC_14: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_0 ------------------------------------------\r
-#define SCU_SFSPD_0_MODE_Pos 0 /*!< SCU SFSPD_0: MODE Position */\r
-#define SCU_SFSPD_0_MODE_Msk (0x07UL << SCU_SFSPD_0_MODE_Pos) /*!< SCU SFSPD_0: MODE Mask */\r
-#define SCU_SFSPD_0_EPD_Pos 3 /*!< SCU SFSPD_0: EPD Position */\r
-#define SCU_SFSPD_0_EPD_Msk (0x01UL << SCU_SFSPD_0_EPD_Pos) /*!< SCU SFSPD_0: EPD Mask */\r
-#define SCU_SFSPD_0_EPUN_Pos 4 /*!< SCU SFSPD_0: EPUN Position */\r
-#define SCU_SFSPD_0_EPUN_Msk (0x01UL << SCU_SFSPD_0_EPUN_Pos) /*!< SCU SFSPD_0: EPUN Mask */\r
-#define SCU_SFSPD_0_EHS_Pos 5 /*!< SCU SFSPD_0: EHS Position */\r
-#define SCU_SFSPD_0_EHS_Msk (0x01UL << SCU_SFSPD_0_EHS_Pos) /*!< SCU SFSPD_0: EHS Mask */\r
-#define SCU_SFSPD_0_EZI_Pos 6 /*!< SCU SFSPD_0: EZI Position */\r
-#define SCU_SFSPD_0_EZI_Msk (0x01UL << SCU_SFSPD_0_EZI_Pos) /*!< SCU SFSPD_0: EZI Mask */\r
-#define SCU_SFSPD_0_EHD_Pos 8 /*!< SCU SFSPD_0: EHD Position */\r
-#define SCU_SFSPD_0_EHD_Msk (0x03UL << SCU_SFSPD_0_EHD_Pos) /*!< SCU SFSPD_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_1 ------------------------------------------\r
-#define SCU_SFSPD_1_MODE_Pos 0 /*!< SCU SFSPD_1: MODE Position */\r
-#define SCU_SFSPD_1_MODE_Msk (0x07UL << SCU_SFSPD_1_MODE_Pos) /*!< SCU SFSPD_1: MODE Mask */\r
-#define SCU_SFSPD_1_EPD_Pos 3 /*!< SCU SFSPD_1: EPD Position */\r
-#define SCU_SFSPD_1_EPD_Msk (0x01UL << SCU_SFSPD_1_EPD_Pos) /*!< SCU SFSPD_1: EPD Mask */\r
-#define SCU_SFSPD_1_EPUN_Pos 4 /*!< SCU SFSPD_1: EPUN Position */\r
-#define SCU_SFSPD_1_EPUN_Msk (0x01UL << SCU_SFSPD_1_EPUN_Pos) /*!< SCU SFSPD_1: EPUN Mask */\r
-#define SCU_SFSPD_1_EHS_Pos 5 /*!< SCU SFSPD_1: EHS Position */\r
-#define SCU_SFSPD_1_EHS_Msk (0x01UL << SCU_SFSPD_1_EHS_Pos) /*!< SCU SFSPD_1: EHS Mask */\r
-#define SCU_SFSPD_1_EZI_Pos 6 /*!< SCU SFSPD_1: EZI Position */\r
-#define SCU_SFSPD_1_EZI_Msk (0x01UL << SCU_SFSPD_1_EZI_Pos) /*!< SCU SFSPD_1: EZI Mask */\r
-#define SCU_SFSPD_1_EHD_Pos 8 /*!< SCU SFSPD_1: EHD Position */\r
-#define SCU_SFSPD_1_EHD_Msk (0x03UL << SCU_SFSPD_1_EHD_Pos) /*!< SCU SFSPD_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_2 ------------------------------------------\r
-#define SCU_SFSPD_2_MODE_Pos 0 /*!< SCU SFSPD_2: MODE Position */\r
-#define SCU_SFSPD_2_MODE_Msk (0x07UL << SCU_SFSPD_2_MODE_Pos) /*!< SCU SFSPD_2: MODE Mask */\r
-#define SCU_SFSPD_2_EPD_Pos 3 /*!< SCU SFSPD_2: EPD Position */\r
-#define SCU_SFSPD_2_EPD_Msk (0x01UL << SCU_SFSPD_2_EPD_Pos) /*!< SCU SFSPD_2: EPD Mask */\r
-#define SCU_SFSPD_2_EPUN_Pos 4 /*!< SCU SFSPD_2: EPUN Position */\r
-#define SCU_SFSPD_2_EPUN_Msk (0x01UL << SCU_SFSPD_2_EPUN_Pos) /*!< SCU SFSPD_2: EPUN Mask */\r
-#define SCU_SFSPD_2_EHS_Pos 5 /*!< SCU SFSPD_2: EHS Position */\r
-#define SCU_SFSPD_2_EHS_Msk (0x01UL << SCU_SFSPD_2_EHS_Pos) /*!< SCU SFSPD_2: EHS Mask */\r
-#define SCU_SFSPD_2_EZI_Pos 6 /*!< SCU SFSPD_2: EZI Position */\r
-#define SCU_SFSPD_2_EZI_Msk (0x01UL << SCU_SFSPD_2_EZI_Pos) /*!< SCU SFSPD_2: EZI Mask */\r
-#define SCU_SFSPD_2_EHD_Pos 8 /*!< SCU SFSPD_2: EHD Position */\r
-#define SCU_SFSPD_2_EHD_Msk (0x03UL << SCU_SFSPD_2_EHD_Pos) /*!< SCU SFSPD_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_3 ------------------------------------------\r
-#define SCU_SFSPD_3_MODE_Pos 0 /*!< SCU SFSPD_3: MODE Position */\r
-#define SCU_SFSPD_3_MODE_Msk (0x07UL << SCU_SFSPD_3_MODE_Pos) /*!< SCU SFSPD_3: MODE Mask */\r
-#define SCU_SFSPD_3_EPD_Pos 3 /*!< SCU SFSPD_3: EPD Position */\r
-#define SCU_SFSPD_3_EPD_Msk (0x01UL << SCU_SFSPD_3_EPD_Pos) /*!< SCU SFSPD_3: EPD Mask */\r
-#define SCU_SFSPD_3_EPUN_Pos 4 /*!< SCU SFSPD_3: EPUN Position */\r
-#define SCU_SFSPD_3_EPUN_Msk (0x01UL << SCU_SFSPD_3_EPUN_Pos) /*!< SCU SFSPD_3: EPUN Mask */\r
-#define SCU_SFSPD_3_EHS_Pos 5 /*!< SCU SFSPD_3: EHS Position */\r
-#define SCU_SFSPD_3_EHS_Msk (0x01UL << SCU_SFSPD_3_EHS_Pos) /*!< SCU SFSPD_3: EHS Mask */\r
-#define SCU_SFSPD_3_EZI_Pos 6 /*!< SCU SFSPD_3: EZI Position */\r
-#define SCU_SFSPD_3_EZI_Msk (0x01UL << SCU_SFSPD_3_EZI_Pos) /*!< SCU SFSPD_3: EZI Mask */\r
-#define SCU_SFSPD_3_EHD_Pos 8 /*!< SCU SFSPD_3: EHD Position */\r
-#define SCU_SFSPD_3_EHD_Msk (0x03UL << SCU_SFSPD_3_EHD_Pos) /*!< SCU SFSPD_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_4 ------------------------------------------\r
-#define SCU_SFSPD_4_MODE_Pos 0 /*!< SCU SFSPD_4: MODE Position */\r
-#define SCU_SFSPD_4_MODE_Msk (0x07UL << SCU_SFSPD_4_MODE_Pos) /*!< SCU SFSPD_4: MODE Mask */\r
-#define SCU_SFSPD_4_EPD_Pos 3 /*!< SCU SFSPD_4: EPD Position */\r
-#define SCU_SFSPD_4_EPD_Msk (0x01UL << SCU_SFSPD_4_EPD_Pos) /*!< SCU SFSPD_4: EPD Mask */\r
-#define SCU_SFSPD_4_EPUN_Pos 4 /*!< SCU SFSPD_4: EPUN Position */\r
-#define SCU_SFSPD_4_EPUN_Msk (0x01UL << SCU_SFSPD_4_EPUN_Pos) /*!< SCU SFSPD_4: EPUN Mask */\r
-#define SCU_SFSPD_4_EHS_Pos 5 /*!< SCU SFSPD_4: EHS Position */\r
-#define SCU_SFSPD_4_EHS_Msk (0x01UL << SCU_SFSPD_4_EHS_Pos) /*!< SCU SFSPD_4: EHS Mask */\r
-#define SCU_SFSPD_4_EZI_Pos 6 /*!< SCU SFSPD_4: EZI Position */\r
-#define SCU_SFSPD_4_EZI_Msk (0x01UL << SCU_SFSPD_4_EZI_Pos) /*!< SCU SFSPD_4: EZI Mask */\r
-#define SCU_SFSPD_4_EHD_Pos 8 /*!< SCU SFSPD_4: EHD Position */\r
-#define SCU_SFSPD_4_EHD_Msk (0x03UL << SCU_SFSPD_4_EHD_Pos) /*!< SCU SFSPD_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_5 ------------------------------------------\r
-#define SCU_SFSPD_5_MODE_Pos 0 /*!< SCU SFSPD_5: MODE Position */\r
-#define SCU_SFSPD_5_MODE_Msk (0x07UL << SCU_SFSPD_5_MODE_Pos) /*!< SCU SFSPD_5: MODE Mask */\r
-#define SCU_SFSPD_5_EPD_Pos 3 /*!< SCU SFSPD_5: EPD Position */\r
-#define SCU_SFSPD_5_EPD_Msk (0x01UL << SCU_SFSPD_5_EPD_Pos) /*!< SCU SFSPD_5: EPD Mask */\r
-#define SCU_SFSPD_5_EPUN_Pos 4 /*!< SCU SFSPD_5: EPUN Position */\r
-#define SCU_SFSPD_5_EPUN_Msk (0x01UL << SCU_SFSPD_5_EPUN_Pos) /*!< SCU SFSPD_5: EPUN Mask */\r
-#define SCU_SFSPD_5_EHS_Pos 5 /*!< SCU SFSPD_5: EHS Position */\r
-#define SCU_SFSPD_5_EHS_Msk (0x01UL << SCU_SFSPD_5_EHS_Pos) /*!< SCU SFSPD_5: EHS Mask */\r
-#define SCU_SFSPD_5_EZI_Pos 6 /*!< SCU SFSPD_5: EZI Position */\r
-#define SCU_SFSPD_5_EZI_Msk (0x01UL << SCU_SFSPD_5_EZI_Pos) /*!< SCU SFSPD_5: EZI Mask */\r
-#define SCU_SFSPD_5_EHD_Pos 8 /*!< SCU SFSPD_5: EHD Position */\r
-#define SCU_SFSPD_5_EHD_Msk (0x03UL << SCU_SFSPD_5_EHD_Pos) /*!< SCU SFSPD_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_6 ------------------------------------------\r
-#define SCU_SFSPD_6_MODE_Pos 0 /*!< SCU SFSPD_6: MODE Position */\r
-#define SCU_SFSPD_6_MODE_Msk (0x07UL << SCU_SFSPD_6_MODE_Pos) /*!< SCU SFSPD_6: MODE Mask */\r
-#define SCU_SFSPD_6_EPD_Pos 3 /*!< SCU SFSPD_6: EPD Position */\r
-#define SCU_SFSPD_6_EPD_Msk (0x01UL << SCU_SFSPD_6_EPD_Pos) /*!< SCU SFSPD_6: EPD Mask */\r
-#define SCU_SFSPD_6_EPUN_Pos 4 /*!< SCU SFSPD_6: EPUN Position */\r
-#define SCU_SFSPD_6_EPUN_Msk (0x01UL << SCU_SFSPD_6_EPUN_Pos) /*!< SCU SFSPD_6: EPUN Mask */\r
-#define SCU_SFSPD_6_EHS_Pos 5 /*!< SCU SFSPD_6: EHS Position */\r
-#define SCU_SFSPD_6_EHS_Msk (0x01UL << SCU_SFSPD_6_EHS_Pos) /*!< SCU SFSPD_6: EHS Mask */\r
-#define SCU_SFSPD_6_EZI_Pos 6 /*!< SCU SFSPD_6: EZI Position */\r
-#define SCU_SFSPD_6_EZI_Msk (0x01UL << SCU_SFSPD_6_EZI_Pos) /*!< SCU SFSPD_6: EZI Mask */\r
-#define SCU_SFSPD_6_EHD_Pos 8 /*!< SCU SFSPD_6: EHD Position */\r
-#define SCU_SFSPD_6_EHD_Msk (0x03UL << SCU_SFSPD_6_EHD_Pos) /*!< SCU SFSPD_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_7 ------------------------------------------\r
-#define SCU_SFSPD_7_MODE_Pos 0 /*!< SCU SFSPD_7: MODE Position */\r
-#define SCU_SFSPD_7_MODE_Msk (0x07UL << SCU_SFSPD_7_MODE_Pos) /*!< SCU SFSPD_7: MODE Mask */\r
-#define SCU_SFSPD_7_EPD_Pos 3 /*!< SCU SFSPD_7: EPD Position */\r
-#define SCU_SFSPD_7_EPD_Msk (0x01UL << SCU_SFSPD_7_EPD_Pos) /*!< SCU SFSPD_7: EPD Mask */\r
-#define SCU_SFSPD_7_EPUN_Pos 4 /*!< SCU SFSPD_7: EPUN Position */\r
-#define SCU_SFSPD_7_EPUN_Msk (0x01UL << SCU_SFSPD_7_EPUN_Pos) /*!< SCU SFSPD_7: EPUN Mask */\r
-#define SCU_SFSPD_7_EHS_Pos 5 /*!< SCU SFSPD_7: EHS Position */\r
-#define SCU_SFSPD_7_EHS_Msk (0x01UL << SCU_SFSPD_7_EHS_Pos) /*!< SCU SFSPD_7: EHS Mask */\r
-#define SCU_SFSPD_7_EZI_Pos 6 /*!< SCU SFSPD_7: EZI Position */\r
-#define SCU_SFSPD_7_EZI_Msk (0x01UL << SCU_SFSPD_7_EZI_Pos) /*!< SCU SFSPD_7: EZI Mask */\r
-#define SCU_SFSPD_7_EHD_Pos 8 /*!< SCU SFSPD_7: EHD Position */\r
-#define SCU_SFSPD_7_EHD_Msk (0x03UL << SCU_SFSPD_7_EHD_Pos) /*!< SCU SFSPD_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_8 ------------------------------------------\r
-#define SCU_SFSPD_8_MODE_Pos 0 /*!< SCU SFSPD_8: MODE Position */\r
-#define SCU_SFSPD_8_MODE_Msk (0x07UL << SCU_SFSPD_8_MODE_Pos) /*!< SCU SFSPD_8: MODE Mask */\r
-#define SCU_SFSPD_8_EPD_Pos 3 /*!< SCU SFSPD_8: EPD Position */\r
-#define SCU_SFSPD_8_EPD_Msk (0x01UL << SCU_SFSPD_8_EPD_Pos) /*!< SCU SFSPD_8: EPD Mask */\r
-#define SCU_SFSPD_8_EPUN_Pos 4 /*!< SCU SFSPD_8: EPUN Position */\r
-#define SCU_SFSPD_8_EPUN_Msk (0x01UL << SCU_SFSPD_8_EPUN_Pos) /*!< SCU SFSPD_8: EPUN Mask */\r
-#define SCU_SFSPD_8_EHS_Pos 5 /*!< SCU SFSPD_8: EHS Position */\r
-#define SCU_SFSPD_8_EHS_Msk (0x01UL << SCU_SFSPD_8_EHS_Pos) /*!< SCU SFSPD_8: EHS Mask */\r
-#define SCU_SFSPD_8_EZI_Pos 6 /*!< SCU SFSPD_8: EZI Position */\r
-#define SCU_SFSPD_8_EZI_Msk (0x01UL << SCU_SFSPD_8_EZI_Pos) /*!< SCU SFSPD_8: EZI Mask */\r
-#define SCU_SFSPD_8_EHD_Pos 8 /*!< SCU SFSPD_8: EHD Position */\r
-#define SCU_SFSPD_8_EHD_Msk (0x03UL << SCU_SFSPD_8_EHD_Pos) /*!< SCU SFSPD_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPD_9 ------------------------------------------\r
-#define SCU_SFSPD_9_MODE_Pos 0 /*!< SCU SFSPD_9: MODE Position */\r
-#define SCU_SFSPD_9_MODE_Msk (0x07UL << SCU_SFSPD_9_MODE_Pos) /*!< SCU SFSPD_9: MODE Mask */\r
-#define SCU_SFSPD_9_EPD_Pos 3 /*!< SCU SFSPD_9: EPD Position */\r
-#define SCU_SFSPD_9_EPD_Msk (0x01UL << SCU_SFSPD_9_EPD_Pos) /*!< SCU SFSPD_9: EPD Mask */\r
-#define SCU_SFSPD_9_EPUN_Pos 4 /*!< SCU SFSPD_9: EPUN Position */\r
-#define SCU_SFSPD_9_EPUN_Msk (0x01UL << SCU_SFSPD_9_EPUN_Pos) /*!< SCU SFSPD_9: EPUN Mask */\r
-#define SCU_SFSPD_9_EHS_Pos 5 /*!< SCU SFSPD_9: EHS Position */\r
-#define SCU_SFSPD_9_EHS_Msk (0x01UL << SCU_SFSPD_9_EHS_Pos) /*!< SCU SFSPD_9: EHS Mask */\r
-#define SCU_SFSPD_9_EZI_Pos 6 /*!< SCU SFSPD_9: EZI Position */\r
-#define SCU_SFSPD_9_EZI_Msk (0x01UL << SCU_SFSPD_9_EZI_Pos) /*!< SCU SFSPD_9: EZI Mask */\r
-#define SCU_SFSPD_9_EHD_Pos 8 /*!< SCU SFSPD_9: EHD Position */\r
-#define SCU_SFSPD_9_EHD_Msk (0x03UL << SCU_SFSPD_9_EHD_Pos) /*!< SCU SFSPD_9: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPD_10 ------------------------------------------\r
-#define SCU_SFSPD_10_MODE_Pos 0 /*!< SCU SFSPD_10: MODE Position */\r
-#define SCU_SFSPD_10_MODE_Msk (0x07UL << SCU_SFSPD_10_MODE_Pos) /*!< SCU SFSPD_10: MODE Mask */\r
-#define SCU_SFSPD_10_EPD_Pos 3 /*!< SCU SFSPD_10: EPD Position */\r
-#define SCU_SFSPD_10_EPD_Msk (0x01UL << SCU_SFSPD_10_EPD_Pos) /*!< SCU SFSPD_10: EPD Mask */\r
-#define SCU_SFSPD_10_EPUN_Pos 4 /*!< SCU SFSPD_10: EPUN Position */\r
-#define SCU_SFSPD_10_EPUN_Msk (0x01UL << SCU_SFSPD_10_EPUN_Pos) /*!< SCU SFSPD_10: EPUN Mask */\r
-#define SCU_SFSPD_10_EHS_Pos 5 /*!< SCU SFSPD_10: EHS Position */\r
-#define SCU_SFSPD_10_EHS_Msk (0x01UL << SCU_SFSPD_10_EHS_Pos) /*!< SCU SFSPD_10: EHS Mask */\r
-#define SCU_SFSPD_10_EZI_Pos 6 /*!< SCU SFSPD_10: EZI Position */\r
-#define SCU_SFSPD_10_EZI_Msk (0x01UL << SCU_SFSPD_10_EZI_Pos) /*!< SCU SFSPD_10: EZI Mask */\r
-#define SCU_SFSPD_10_EHD_Pos 8 /*!< SCU SFSPD_10: EHD Position */\r
-#define SCU_SFSPD_10_EHD_Msk (0x03UL << SCU_SFSPD_10_EHD_Pos) /*!< SCU SFSPD_10: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPD_11 ------------------------------------------\r
-#define SCU_SFSPD_11_MODE_Pos 0 /*!< SCU SFSPD_11: MODE Position */\r
-#define SCU_SFSPD_11_MODE_Msk (0x07UL << SCU_SFSPD_11_MODE_Pos) /*!< SCU SFSPD_11: MODE Mask */\r
-#define SCU_SFSPD_11_EPD_Pos 3 /*!< SCU SFSPD_11: EPD Position */\r
-#define SCU_SFSPD_11_EPD_Msk (0x01UL << SCU_SFSPD_11_EPD_Pos) /*!< SCU SFSPD_11: EPD Mask */\r
-#define SCU_SFSPD_11_EPUN_Pos 4 /*!< SCU SFSPD_11: EPUN Position */\r
-#define SCU_SFSPD_11_EPUN_Msk (0x01UL << SCU_SFSPD_11_EPUN_Pos) /*!< SCU SFSPD_11: EPUN Mask */\r
-#define SCU_SFSPD_11_EHS_Pos 5 /*!< SCU SFSPD_11: EHS Position */\r
-#define SCU_SFSPD_11_EHS_Msk (0x01UL << SCU_SFSPD_11_EHS_Pos) /*!< SCU SFSPD_11: EHS Mask */\r
-#define SCU_SFSPD_11_EZI_Pos 6 /*!< SCU SFSPD_11: EZI Position */\r
-#define SCU_SFSPD_11_EZI_Msk (0x01UL << SCU_SFSPD_11_EZI_Pos) /*!< SCU SFSPD_11: EZI Mask */\r
-#define SCU_SFSPD_11_EHD_Pos 8 /*!< SCU SFSPD_11: EHD Position */\r
-#define SCU_SFSPD_11_EHD_Msk (0x03UL << SCU_SFSPD_11_EHD_Pos) /*!< SCU SFSPD_11: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPD_12 ------------------------------------------\r
-#define SCU_SFSPD_12_MODE_Pos 0 /*!< SCU SFSPD_12: MODE Position */\r
-#define SCU_SFSPD_12_MODE_Msk (0x07UL << SCU_SFSPD_12_MODE_Pos) /*!< SCU SFSPD_12: MODE Mask */\r
-#define SCU_SFSPD_12_EPD_Pos 3 /*!< SCU SFSPD_12: EPD Position */\r
-#define SCU_SFSPD_12_EPD_Msk (0x01UL << SCU_SFSPD_12_EPD_Pos) /*!< SCU SFSPD_12: EPD Mask */\r
-#define SCU_SFSPD_12_EPUN_Pos 4 /*!< SCU SFSPD_12: EPUN Position */\r
-#define SCU_SFSPD_12_EPUN_Msk (0x01UL << SCU_SFSPD_12_EPUN_Pos) /*!< SCU SFSPD_12: EPUN Mask */\r
-#define SCU_SFSPD_12_EHS_Pos 5 /*!< SCU SFSPD_12: EHS Position */\r
-#define SCU_SFSPD_12_EHS_Msk (0x01UL << SCU_SFSPD_12_EHS_Pos) /*!< SCU SFSPD_12: EHS Mask */\r
-#define SCU_SFSPD_12_EZI_Pos 6 /*!< SCU SFSPD_12: EZI Position */\r
-#define SCU_SFSPD_12_EZI_Msk (0x01UL << SCU_SFSPD_12_EZI_Pos) /*!< SCU SFSPD_12: EZI Mask */\r
-#define SCU_SFSPD_12_EHD_Pos 8 /*!< SCU SFSPD_12: EHD Position */\r
-#define SCU_SFSPD_12_EHD_Msk (0x03UL << SCU_SFSPD_12_EHD_Pos) /*!< SCU SFSPD_12: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPD_13 ------------------------------------------\r
-#define SCU_SFSPD_13_MODE_Pos 0 /*!< SCU SFSPD_13: MODE Position */\r
-#define SCU_SFSPD_13_MODE_Msk (0x07UL << SCU_SFSPD_13_MODE_Pos) /*!< SCU SFSPD_13: MODE Mask */\r
-#define SCU_SFSPD_13_EPD_Pos 3 /*!< SCU SFSPD_13: EPD Position */\r
-#define SCU_SFSPD_13_EPD_Msk (0x01UL << SCU_SFSPD_13_EPD_Pos) /*!< SCU SFSPD_13: EPD Mask */\r
-#define SCU_SFSPD_13_EPUN_Pos 4 /*!< SCU SFSPD_13: EPUN Position */\r
-#define SCU_SFSPD_13_EPUN_Msk (0x01UL << SCU_SFSPD_13_EPUN_Pos) /*!< SCU SFSPD_13: EPUN Mask */\r
-#define SCU_SFSPD_13_EHS_Pos 5 /*!< SCU SFSPD_13: EHS Position */\r
-#define SCU_SFSPD_13_EHS_Msk (0x01UL << SCU_SFSPD_13_EHS_Pos) /*!< SCU SFSPD_13: EHS Mask */\r
-#define SCU_SFSPD_13_EZI_Pos 6 /*!< SCU SFSPD_13: EZI Position */\r
-#define SCU_SFSPD_13_EZI_Msk (0x01UL << SCU_SFSPD_13_EZI_Pos) /*!< SCU SFSPD_13: EZI Mask */\r
-#define SCU_SFSPD_13_EHD_Pos 8 /*!< SCU SFSPD_13: EHD Position */\r
-#define SCU_SFSPD_13_EHD_Msk (0x03UL << SCU_SFSPD_13_EHD_Pos) /*!< SCU SFSPD_13: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPD_14 ------------------------------------------\r
-#define SCU_SFSPD_14_MODE_Pos 0 /*!< SCU SFSPD_14: MODE Position */\r
-#define SCU_SFSPD_14_MODE_Msk (0x07UL << SCU_SFSPD_14_MODE_Pos) /*!< SCU SFSPD_14: MODE Mask */\r
-#define SCU_SFSPD_14_EPD_Pos 3 /*!< SCU SFSPD_14: EPD Position */\r
-#define SCU_SFSPD_14_EPD_Msk (0x01UL << SCU_SFSPD_14_EPD_Pos) /*!< SCU SFSPD_14: EPD Mask */\r
-#define SCU_SFSPD_14_EPUN_Pos 4 /*!< SCU SFSPD_14: EPUN Position */\r
-#define SCU_SFSPD_14_EPUN_Msk (0x01UL << SCU_SFSPD_14_EPUN_Pos) /*!< SCU SFSPD_14: EPUN Mask */\r
-#define SCU_SFSPD_14_EHS_Pos 5 /*!< SCU SFSPD_14: EHS Position */\r
-#define SCU_SFSPD_14_EHS_Msk (0x01UL << SCU_SFSPD_14_EHS_Pos) /*!< SCU SFSPD_14: EHS Mask */\r
-#define SCU_SFSPD_14_EZI_Pos 6 /*!< SCU SFSPD_14: EZI Position */\r
-#define SCU_SFSPD_14_EZI_Msk (0x01UL << SCU_SFSPD_14_EZI_Pos) /*!< SCU SFSPD_14: EZI Mask */\r
-#define SCU_SFSPD_14_EHD_Pos 8 /*!< SCU SFSPD_14: EHD Position */\r
-#define SCU_SFSPD_14_EHD_Msk (0x03UL << SCU_SFSPD_14_EHD_Pos) /*!< SCU SFSPD_14: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPD_15 ------------------------------------------\r
-#define SCU_SFSPD_15_MODE_Pos 0 /*!< SCU SFSPD_15: MODE Position */\r
-#define SCU_SFSPD_15_MODE_Msk (0x07UL << SCU_SFSPD_15_MODE_Pos) /*!< SCU SFSPD_15: MODE Mask */\r
-#define SCU_SFSPD_15_EPD_Pos 3 /*!< SCU SFSPD_15: EPD Position */\r
-#define SCU_SFSPD_15_EPD_Msk (0x01UL << SCU_SFSPD_15_EPD_Pos) /*!< SCU SFSPD_15: EPD Mask */\r
-#define SCU_SFSPD_15_EPUN_Pos 4 /*!< SCU SFSPD_15: EPUN Position */\r
-#define SCU_SFSPD_15_EPUN_Msk (0x01UL << SCU_SFSPD_15_EPUN_Pos) /*!< SCU SFSPD_15: EPUN Mask */\r
-#define SCU_SFSPD_15_EHS_Pos 5 /*!< SCU SFSPD_15: EHS Position */\r
-#define SCU_SFSPD_15_EHS_Msk (0x01UL << SCU_SFSPD_15_EHS_Pos) /*!< SCU SFSPD_15: EHS Mask */\r
-#define SCU_SFSPD_15_EZI_Pos 6 /*!< SCU SFSPD_15: EZI Position */\r
-#define SCU_SFSPD_15_EZI_Msk (0x01UL << SCU_SFSPD_15_EZI_Pos) /*!< SCU SFSPD_15: EZI Mask */\r
-#define SCU_SFSPD_15_EHD_Pos 8 /*!< SCU SFSPD_15: EHD Position */\r
-#define SCU_SFSPD_15_EHD_Msk (0x03UL << SCU_SFSPD_15_EHD_Pos) /*!< SCU SFSPD_15: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPD_16 ------------------------------------------\r
-#define SCU_SFSPD_16_MODE_Pos 0 /*!< SCU SFSPD_16: MODE Position */\r
-#define SCU_SFSPD_16_MODE_Msk (0x07UL << SCU_SFSPD_16_MODE_Pos) /*!< SCU SFSPD_16: MODE Mask */\r
-#define SCU_SFSPD_16_EPD_Pos 3 /*!< SCU SFSPD_16: EPD Position */\r
-#define SCU_SFSPD_16_EPD_Msk (0x01UL << SCU_SFSPD_16_EPD_Pos) /*!< SCU SFSPD_16: EPD Mask */\r
-#define SCU_SFSPD_16_EPUN_Pos 4 /*!< SCU SFSPD_16: EPUN Position */\r
-#define SCU_SFSPD_16_EPUN_Msk (0x01UL << SCU_SFSPD_16_EPUN_Pos) /*!< SCU SFSPD_16: EPUN Mask */\r
-#define SCU_SFSPD_16_EHS_Pos 5 /*!< SCU SFSPD_16: EHS Position */\r
-#define SCU_SFSPD_16_EHS_Msk (0x01UL << SCU_SFSPD_16_EHS_Pos) /*!< SCU SFSPD_16: EHS Mask */\r
-#define SCU_SFSPD_16_EZI_Pos 6 /*!< SCU SFSPD_16: EZI Position */\r
-#define SCU_SFSPD_16_EZI_Msk (0x01UL << SCU_SFSPD_16_EZI_Pos) /*!< SCU SFSPD_16: EZI Mask */\r
-#define SCU_SFSPD_16_EHD_Pos 8 /*!< SCU SFSPD_16: EHD Position */\r
-#define SCU_SFSPD_16_EHD_Msk (0x03UL << SCU_SFSPD_16_EHD_Pos) /*!< SCU SFSPD_16: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_0 ------------------------------------------\r
-#define SCU_SFSPE_0_MODE_Pos 0 /*!< SCU SFSPE_0: MODE Position */\r
-#define SCU_SFSPE_0_MODE_Msk (0x07UL << SCU_SFSPE_0_MODE_Pos) /*!< SCU SFSPE_0: MODE Mask */\r
-#define SCU_SFSPE_0_EPD_Pos 3 /*!< SCU SFSPE_0: EPD Position */\r
-#define SCU_SFSPE_0_EPD_Msk (0x01UL << SCU_SFSPE_0_EPD_Pos) /*!< SCU SFSPE_0: EPD Mask */\r
-#define SCU_SFSPE_0_EPUN_Pos 4 /*!< SCU SFSPE_0: EPUN Position */\r
-#define SCU_SFSPE_0_EPUN_Msk (0x01UL << SCU_SFSPE_0_EPUN_Pos) /*!< SCU SFSPE_0: EPUN Mask */\r
-#define SCU_SFSPE_0_EHS_Pos 5 /*!< SCU SFSPE_0: EHS Position */\r
-#define SCU_SFSPE_0_EHS_Msk (0x01UL << SCU_SFSPE_0_EHS_Pos) /*!< SCU SFSPE_0: EHS Mask */\r
-#define SCU_SFSPE_0_EZI_Pos 6 /*!< SCU SFSPE_0: EZI Position */\r
-#define SCU_SFSPE_0_EZI_Msk (0x01UL << SCU_SFSPE_0_EZI_Pos) /*!< SCU SFSPE_0: EZI Mask */\r
-#define SCU_SFSPE_0_EHD_Pos 8 /*!< SCU SFSPE_0: EHD Position */\r
-#define SCU_SFSPE_0_EHD_Msk (0x03UL << SCU_SFSPE_0_EHD_Pos) /*!< SCU SFSPE_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_1 ------------------------------------------\r
-#define SCU_SFSPE_1_MODE_Pos 0 /*!< SCU SFSPE_1: MODE Position */\r
-#define SCU_SFSPE_1_MODE_Msk (0x07UL << SCU_SFSPE_1_MODE_Pos) /*!< SCU SFSPE_1: MODE Mask */\r
-#define SCU_SFSPE_1_EPD_Pos 3 /*!< SCU SFSPE_1: EPD Position */\r
-#define SCU_SFSPE_1_EPD_Msk (0x01UL << SCU_SFSPE_1_EPD_Pos) /*!< SCU SFSPE_1: EPD Mask */\r
-#define SCU_SFSPE_1_EPUN_Pos 4 /*!< SCU SFSPE_1: EPUN Position */\r
-#define SCU_SFSPE_1_EPUN_Msk (0x01UL << SCU_SFSPE_1_EPUN_Pos) /*!< SCU SFSPE_1: EPUN Mask */\r
-#define SCU_SFSPE_1_EHS_Pos 5 /*!< SCU SFSPE_1: EHS Position */\r
-#define SCU_SFSPE_1_EHS_Msk (0x01UL << SCU_SFSPE_1_EHS_Pos) /*!< SCU SFSPE_1: EHS Mask */\r
-#define SCU_SFSPE_1_EZI_Pos 6 /*!< SCU SFSPE_1: EZI Position */\r
-#define SCU_SFSPE_1_EZI_Msk (0x01UL << SCU_SFSPE_1_EZI_Pos) /*!< SCU SFSPE_1: EZI Mask */\r
-#define SCU_SFSPE_1_EHD_Pos 8 /*!< SCU SFSPE_1: EHD Position */\r
-#define SCU_SFSPE_1_EHD_Msk (0x03UL << SCU_SFSPE_1_EHD_Pos) /*!< SCU SFSPE_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_2 ------------------------------------------\r
-#define SCU_SFSPE_2_MODE_Pos 0 /*!< SCU SFSPE_2: MODE Position */\r
-#define SCU_SFSPE_2_MODE_Msk (0x07UL << SCU_SFSPE_2_MODE_Pos) /*!< SCU SFSPE_2: MODE Mask */\r
-#define SCU_SFSPE_2_EPD_Pos 3 /*!< SCU SFSPE_2: EPD Position */\r
-#define SCU_SFSPE_2_EPD_Msk (0x01UL << SCU_SFSPE_2_EPD_Pos) /*!< SCU SFSPE_2: EPD Mask */\r
-#define SCU_SFSPE_2_EPUN_Pos 4 /*!< SCU SFSPE_2: EPUN Position */\r
-#define SCU_SFSPE_2_EPUN_Msk (0x01UL << SCU_SFSPE_2_EPUN_Pos) /*!< SCU SFSPE_2: EPUN Mask */\r
-#define SCU_SFSPE_2_EHS_Pos 5 /*!< SCU SFSPE_2: EHS Position */\r
-#define SCU_SFSPE_2_EHS_Msk (0x01UL << SCU_SFSPE_2_EHS_Pos) /*!< SCU SFSPE_2: EHS Mask */\r
-#define SCU_SFSPE_2_EZI_Pos 6 /*!< SCU SFSPE_2: EZI Position */\r
-#define SCU_SFSPE_2_EZI_Msk (0x01UL << SCU_SFSPE_2_EZI_Pos) /*!< SCU SFSPE_2: EZI Mask */\r
-#define SCU_SFSPE_2_EHD_Pos 8 /*!< SCU SFSPE_2: EHD Position */\r
-#define SCU_SFSPE_2_EHD_Msk (0x03UL << SCU_SFSPE_2_EHD_Pos) /*!< SCU SFSPE_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_3 ------------------------------------------\r
-#define SCU_SFSPE_3_MODE_Pos 0 /*!< SCU SFSPE_3: MODE Position */\r
-#define SCU_SFSPE_3_MODE_Msk (0x07UL << SCU_SFSPE_3_MODE_Pos) /*!< SCU SFSPE_3: MODE Mask */\r
-#define SCU_SFSPE_3_EPD_Pos 3 /*!< SCU SFSPE_3: EPD Position */\r
-#define SCU_SFSPE_3_EPD_Msk (0x01UL << SCU_SFSPE_3_EPD_Pos) /*!< SCU SFSPE_3: EPD Mask */\r
-#define SCU_SFSPE_3_EPUN_Pos 4 /*!< SCU SFSPE_3: EPUN Position */\r
-#define SCU_SFSPE_3_EPUN_Msk (0x01UL << SCU_SFSPE_3_EPUN_Pos) /*!< SCU SFSPE_3: EPUN Mask */\r
-#define SCU_SFSPE_3_EHS_Pos 5 /*!< SCU SFSPE_3: EHS Position */\r
-#define SCU_SFSPE_3_EHS_Msk (0x01UL << SCU_SFSPE_3_EHS_Pos) /*!< SCU SFSPE_3: EHS Mask */\r
-#define SCU_SFSPE_3_EZI_Pos 6 /*!< SCU SFSPE_3: EZI Position */\r
-#define SCU_SFSPE_3_EZI_Msk (0x01UL << SCU_SFSPE_3_EZI_Pos) /*!< SCU SFSPE_3: EZI Mask */\r
-#define SCU_SFSPE_3_EHD_Pos 8 /*!< SCU SFSPE_3: EHD Position */\r
-#define SCU_SFSPE_3_EHD_Msk (0x03UL << SCU_SFSPE_3_EHD_Pos) /*!< SCU SFSPE_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_4 ------------------------------------------\r
-#define SCU_SFSPE_4_MODE_Pos 0 /*!< SCU SFSPE_4: MODE Position */\r
-#define SCU_SFSPE_4_MODE_Msk (0x07UL << SCU_SFSPE_4_MODE_Pos) /*!< SCU SFSPE_4: MODE Mask */\r
-#define SCU_SFSPE_4_EPD_Pos 3 /*!< SCU SFSPE_4: EPD Position */\r
-#define SCU_SFSPE_4_EPD_Msk (0x01UL << SCU_SFSPE_4_EPD_Pos) /*!< SCU SFSPE_4: EPD Mask */\r
-#define SCU_SFSPE_4_EPUN_Pos 4 /*!< SCU SFSPE_4: EPUN Position */\r
-#define SCU_SFSPE_4_EPUN_Msk (0x01UL << SCU_SFSPE_4_EPUN_Pos) /*!< SCU SFSPE_4: EPUN Mask */\r
-#define SCU_SFSPE_4_EHS_Pos 5 /*!< SCU SFSPE_4: EHS Position */\r
-#define SCU_SFSPE_4_EHS_Msk (0x01UL << SCU_SFSPE_4_EHS_Pos) /*!< SCU SFSPE_4: EHS Mask */\r
-#define SCU_SFSPE_4_EZI_Pos 6 /*!< SCU SFSPE_4: EZI Position */\r
-#define SCU_SFSPE_4_EZI_Msk (0x01UL << SCU_SFSPE_4_EZI_Pos) /*!< SCU SFSPE_4: EZI Mask */\r
-#define SCU_SFSPE_4_EHD_Pos 8 /*!< SCU SFSPE_4: EHD Position */\r
-#define SCU_SFSPE_4_EHD_Msk (0x03UL << SCU_SFSPE_4_EHD_Pos) /*!< SCU SFSPE_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_5 ------------------------------------------\r
-#define SCU_SFSPE_5_MODE_Pos 0 /*!< SCU SFSPE_5: MODE Position */\r
-#define SCU_SFSPE_5_MODE_Msk (0x07UL << SCU_SFSPE_5_MODE_Pos) /*!< SCU SFSPE_5: MODE Mask */\r
-#define SCU_SFSPE_5_EPD_Pos 3 /*!< SCU SFSPE_5: EPD Position */\r
-#define SCU_SFSPE_5_EPD_Msk (0x01UL << SCU_SFSPE_5_EPD_Pos) /*!< SCU SFSPE_5: EPD Mask */\r
-#define SCU_SFSPE_5_EPUN_Pos 4 /*!< SCU SFSPE_5: EPUN Position */\r
-#define SCU_SFSPE_5_EPUN_Msk (0x01UL << SCU_SFSPE_5_EPUN_Pos) /*!< SCU SFSPE_5: EPUN Mask */\r
-#define SCU_SFSPE_5_EHS_Pos 5 /*!< SCU SFSPE_5: EHS Position */\r
-#define SCU_SFSPE_5_EHS_Msk (0x01UL << SCU_SFSPE_5_EHS_Pos) /*!< SCU SFSPE_5: EHS Mask */\r
-#define SCU_SFSPE_5_EZI_Pos 6 /*!< SCU SFSPE_5: EZI Position */\r
-#define SCU_SFSPE_5_EZI_Msk (0x01UL << SCU_SFSPE_5_EZI_Pos) /*!< SCU SFSPE_5: EZI Mask */\r
-#define SCU_SFSPE_5_EHD_Pos 8 /*!< SCU SFSPE_5: EHD Position */\r
-#define SCU_SFSPE_5_EHD_Msk (0x03UL << SCU_SFSPE_5_EHD_Pos) /*!< SCU SFSPE_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_6 ------------------------------------------\r
-#define SCU_SFSPE_6_MODE_Pos 0 /*!< SCU SFSPE_6: MODE Position */\r
-#define SCU_SFSPE_6_MODE_Msk (0x07UL << SCU_SFSPE_6_MODE_Pos) /*!< SCU SFSPE_6: MODE Mask */\r
-#define SCU_SFSPE_6_EPD_Pos 3 /*!< SCU SFSPE_6: EPD Position */\r
-#define SCU_SFSPE_6_EPD_Msk (0x01UL << SCU_SFSPE_6_EPD_Pos) /*!< SCU SFSPE_6: EPD Mask */\r
-#define SCU_SFSPE_6_EPUN_Pos 4 /*!< SCU SFSPE_6: EPUN Position */\r
-#define SCU_SFSPE_6_EPUN_Msk (0x01UL << SCU_SFSPE_6_EPUN_Pos) /*!< SCU SFSPE_6: EPUN Mask */\r
-#define SCU_SFSPE_6_EHS_Pos 5 /*!< SCU SFSPE_6: EHS Position */\r
-#define SCU_SFSPE_6_EHS_Msk (0x01UL << SCU_SFSPE_6_EHS_Pos) /*!< SCU SFSPE_6: EHS Mask */\r
-#define SCU_SFSPE_6_EZI_Pos 6 /*!< SCU SFSPE_6: EZI Position */\r
-#define SCU_SFSPE_6_EZI_Msk (0x01UL << SCU_SFSPE_6_EZI_Pos) /*!< SCU SFSPE_6: EZI Mask */\r
-#define SCU_SFSPE_6_EHD_Pos 8 /*!< SCU SFSPE_6: EHD Position */\r
-#define SCU_SFSPE_6_EHD_Msk (0x03UL << SCU_SFSPE_6_EHD_Pos) /*!< SCU SFSPE_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_7 ------------------------------------------\r
-#define SCU_SFSPE_7_MODE_Pos 0 /*!< SCU SFSPE_7: MODE Position */\r
-#define SCU_SFSPE_7_MODE_Msk (0x07UL << SCU_SFSPE_7_MODE_Pos) /*!< SCU SFSPE_7: MODE Mask */\r
-#define SCU_SFSPE_7_EPD_Pos 3 /*!< SCU SFSPE_7: EPD Position */\r
-#define SCU_SFSPE_7_EPD_Msk (0x01UL << SCU_SFSPE_7_EPD_Pos) /*!< SCU SFSPE_7: EPD Mask */\r
-#define SCU_SFSPE_7_EPUN_Pos 4 /*!< SCU SFSPE_7: EPUN Position */\r
-#define SCU_SFSPE_7_EPUN_Msk (0x01UL << SCU_SFSPE_7_EPUN_Pos) /*!< SCU SFSPE_7: EPUN Mask */\r
-#define SCU_SFSPE_7_EHS_Pos 5 /*!< SCU SFSPE_7: EHS Position */\r
-#define SCU_SFSPE_7_EHS_Msk (0x01UL << SCU_SFSPE_7_EHS_Pos) /*!< SCU SFSPE_7: EHS Mask */\r
-#define SCU_SFSPE_7_EZI_Pos 6 /*!< SCU SFSPE_7: EZI Position */\r
-#define SCU_SFSPE_7_EZI_Msk (0x01UL << SCU_SFSPE_7_EZI_Pos) /*!< SCU SFSPE_7: EZI Mask */\r
-#define SCU_SFSPE_7_EHD_Pos 8 /*!< SCU SFSPE_7: EHD Position */\r
-#define SCU_SFSPE_7_EHD_Msk (0x03UL << SCU_SFSPE_7_EHD_Pos) /*!< SCU SFSPE_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_8 ------------------------------------------\r
-#define SCU_SFSPE_8_MODE_Pos 0 /*!< SCU SFSPE_8: MODE Position */\r
-#define SCU_SFSPE_8_MODE_Msk (0x07UL << SCU_SFSPE_8_MODE_Pos) /*!< SCU SFSPE_8: MODE Mask */\r
-#define SCU_SFSPE_8_EPD_Pos 3 /*!< SCU SFSPE_8: EPD Position */\r
-#define SCU_SFSPE_8_EPD_Msk (0x01UL << SCU_SFSPE_8_EPD_Pos) /*!< SCU SFSPE_8: EPD Mask */\r
-#define SCU_SFSPE_8_EPUN_Pos 4 /*!< SCU SFSPE_8: EPUN Position */\r
-#define SCU_SFSPE_8_EPUN_Msk (0x01UL << SCU_SFSPE_8_EPUN_Pos) /*!< SCU SFSPE_8: EPUN Mask */\r
-#define SCU_SFSPE_8_EHS_Pos 5 /*!< SCU SFSPE_8: EHS Position */\r
-#define SCU_SFSPE_8_EHS_Msk (0x01UL << SCU_SFSPE_8_EHS_Pos) /*!< SCU SFSPE_8: EHS Mask */\r
-#define SCU_SFSPE_8_EZI_Pos 6 /*!< SCU SFSPE_8: EZI Position */\r
-#define SCU_SFSPE_8_EZI_Msk (0x01UL << SCU_SFSPE_8_EZI_Pos) /*!< SCU SFSPE_8: EZI Mask */\r
-#define SCU_SFSPE_8_EHD_Pos 8 /*!< SCU SFSPE_8: EHD Position */\r
-#define SCU_SFSPE_8_EHD_Msk (0x03UL << SCU_SFSPE_8_EHD_Pos) /*!< SCU SFSPE_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPE_9 ------------------------------------------\r
-#define SCU_SFSPE_9_MODE_Pos 0 /*!< SCU SFSPE_9: MODE Position */\r
-#define SCU_SFSPE_9_MODE_Msk (0x07UL << SCU_SFSPE_9_MODE_Pos) /*!< SCU SFSPE_9: MODE Mask */\r
-#define SCU_SFSPE_9_EPD_Pos 3 /*!< SCU SFSPE_9: EPD Position */\r
-#define SCU_SFSPE_9_EPD_Msk (0x01UL << SCU_SFSPE_9_EPD_Pos) /*!< SCU SFSPE_9: EPD Mask */\r
-#define SCU_SFSPE_9_EPUN_Pos 4 /*!< SCU SFSPE_9: EPUN Position */\r
-#define SCU_SFSPE_9_EPUN_Msk (0x01UL << SCU_SFSPE_9_EPUN_Pos) /*!< SCU SFSPE_9: EPUN Mask */\r
-#define SCU_SFSPE_9_EHS_Pos 5 /*!< SCU SFSPE_9: EHS Position */\r
-#define SCU_SFSPE_9_EHS_Msk (0x01UL << SCU_SFSPE_9_EHS_Pos) /*!< SCU SFSPE_9: EHS Mask */\r
-#define SCU_SFSPE_9_EZI_Pos 6 /*!< SCU SFSPE_9: EZI Position */\r
-#define SCU_SFSPE_9_EZI_Msk (0x01UL << SCU_SFSPE_9_EZI_Pos) /*!< SCU SFSPE_9: EZI Mask */\r
-#define SCU_SFSPE_9_EHD_Pos 8 /*!< SCU SFSPE_9: EHD Position */\r
-#define SCU_SFSPE_9_EHD_Msk (0x03UL << SCU_SFSPE_9_EHD_Pos) /*!< SCU SFSPE_9: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPE_10 ------------------------------------------\r
-#define SCU_SFSPE_10_MODE_Pos 0 /*!< SCU SFSPE_10: MODE Position */\r
-#define SCU_SFSPE_10_MODE_Msk (0x07UL << SCU_SFSPE_10_MODE_Pos) /*!< SCU SFSPE_10: MODE Mask */\r
-#define SCU_SFSPE_10_EPD_Pos 3 /*!< SCU SFSPE_10: EPD Position */\r
-#define SCU_SFSPE_10_EPD_Msk (0x01UL << SCU_SFSPE_10_EPD_Pos) /*!< SCU SFSPE_10: EPD Mask */\r
-#define SCU_SFSPE_10_EPUN_Pos 4 /*!< SCU SFSPE_10: EPUN Position */\r
-#define SCU_SFSPE_10_EPUN_Msk (0x01UL << SCU_SFSPE_10_EPUN_Pos) /*!< SCU SFSPE_10: EPUN Mask */\r
-#define SCU_SFSPE_10_EHS_Pos 5 /*!< SCU SFSPE_10: EHS Position */\r
-#define SCU_SFSPE_10_EHS_Msk (0x01UL << SCU_SFSPE_10_EHS_Pos) /*!< SCU SFSPE_10: EHS Mask */\r
-#define SCU_SFSPE_10_EZI_Pos 6 /*!< SCU SFSPE_10: EZI Position */\r
-#define SCU_SFSPE_10_EZI_Msk (0x01UL << SCU_SFSPE_10_EZI_Pos) /*!< SCU SFSPE_10: EZI Mask */\r
-#define SCU_SFSPE_10_EHD_Pos 8 /*!< SCU SFSPE_10: EHD Position */\r
-#define SCU_SFSPE_10_EHD_Msk (0x03UL << SCU_SFSPE_10_EHD_Pos) /*!< SCU SFSPE_10: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPE_11 ------------------------------------------\r
-#define SCU_SFSPE_11_MODE_Pos 0 /*!< SCU SFSPE_11: MODE Position */\r
-#define SCU_SFSPE_11_MODE_Msk (0x07UL << SCU_SFSPE_11_MODE_Pos) /*!< SCU SFSPE_11: MODE Mask */\r
-#define SCU_SFSPE_11_EPD_Pos 3 /*!< SCU SFSPE_11: EPD Position */\r
-#define SCU_SFSPE_11_EPD_Msk (0x01UL << SCU_SFSPE_11_EPD_Pos) /*!< SCU SFSPE_11: EPD Mask */\r
-#define SCU_SFSPE_11_EPUN_Pos 4 /*!< SCU SFSPE_11: EPUN Position */\r
-#define SCU_SFSPE_11_EPUN_Msk (0x01UL << SCU_SFSPE_11_EPUN_Pos) /*!< SCU SFSPE_11: EPUN Mask */\r
-#define SCU_SFSPE_11_EHS_Pos 5 /*!< SCU SFSPE_11: EHS Position */\r
-#define SCU_SFSPE_11_EHS_Msk (0x01UL << SCU_SFSPE_11_EHS_Pos) /*!< SCU SFSPE_11: EHS Mask */\r
-#define SCU_SFSPE_11_EZI_Pos 6 /*!< SCU SFSPE_11: EZI Position */\r
-#define SCU_SFSPE_11_EZI_Msk (0x01UL << SCU_SFSPE_11_EZI_Pos) /*!< SCU SFSPE_11: EZI Mask */\r
-#define SCU_SFSPE_11_EHD_Pos 8 /*!< SCU SFSPE_11: EHD Position */\r
-#define SCU_SFSPE_11_EHD_Msk (0x03UL << SCU_SFSPE_11_EHD_Pos) /*!< SCU SFSPE_11: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPE_12 ------------------------------------------\r
-#define SCU_SFSPE_12_MODE_Pos 0 /*!< SCU SFSPE_12: MODE Position */\r
-#define SCU_SFSPE_12_MODE_Msk (0x07UL << SCU_SFSPE_12_MODE_Pos) /*!< SCU SFSPE_12: MODE Mask */\r
-#define SCU_SFSPE_12_EPD_Pos 3 /*!< SCU SFSPE_12: EPD Position */\r
-#define SCU_SFSPE_12_EPD_Msk (0x01UL << SCU_SFSPE_12_EPD_Pos) /*!< SCU SFSPE_12: EPD Mask */\r
-#define SCU_SFSPE_12_EPUN_Pos 4 /*!< SCU SFSPE_12: EPUN Position */\r
-#define SCU_SFSPE_12_EPUN_Msk (0x01UL << SCU_SFSPE_12_EPUN_Pos) /*!< SCU SFSPE_12: EPUN Mask */\r
-#define SCU_SFSPE_12_EHS_Pos 5 /*!< SCU SFSPE_12: EHS Position */\r
-#define SCU_SFSPE_12_EHS_Msk (0x01UL << SCU_SFSPE_12_EHS_Pos) /*!< SCU SFSPE_12: EHS Mask */\r
-#define SCU_SFSPE_12_EZI_Pos 6 /*!< SCU SFSPE_12: EZI Position */\r
-#define SCU_SFSPE_12_EZI_Msk (0x01UL << SCU_SFSPE_12_EZI_Pos) /*!< SCU SFSPE_12: EZI Mask */\r
-#define SCU_SFSPE_12_EHD_Pos 8 /*!< SCU SFSPE_12: EHD Position */\r
-#define SCU_SFSPE_12_EHD_Msk (0x03UL << SCU_SFSPE_12_EHD_Pos) /*!< SCU SFSPE_12: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPE_13 ------------------------------------------\r
-#define SCU_SFSPE_13_MODE_Pos 0 /*!< SCU SFSPE_13: MODE Position */\r
-#define SCU_SFSPE_13_MODE_Msk (0x07UL << SCU_SFSPE_13_MODE_Pos) /*!< SCU SFSPE_13: MODE Mask */\r
-#define SCU_SFSPE_13_EPD_Pos 3 /*!< SCU SFSPE_13: EPD Position */\r
-#define SCU_SFSPE_13_EPD_Msk (0x01UL << SCU_SFSPE_13_EPD_Pos) /*!< SCU SFSPE_13: EPD Mask */\r
-#define SCU_SFSPE_13_EPUN_Pos 4 /*!< SCU SFSPE_13: EPUN Position */\r
-#define SCU_SFSPE_13_EPUN_Msk (0x01UL << SCU_SFSPE_13_EPUN_Pos) /*!< SCU SFSPE_13: EPUN Mask */\r
-#define SCU_SFSPE_13_EHS_Pos 5 /*!< SCU SFSPE_13: EHS Position */\r
-#define SCU_SFSPE_13_EHS_Msk (0x01UL << SCU_SFSPE_13_EHS_Pos) /*!< SCU SFSPE_13: EHS Mask */\r
-#define SCU_SFSPE_13_EZI_Pos 6 /*!< SCU SFSPE_13: EZI Position */\r
-#define SCU_SFSPE_13_EZI_Msk (0x01UL << SCU_SFSPE_13_EZI_Pos) /*!< SCU SFSPE_13: EZI Mask */\r
-#define SCU_SFSPE_13_EHD_Pos 8 /*!< SCU SFSPE_13: EHD Position */\r
-#define SCU_SFSPE_13_EHD_Msk (0x03UL << SCU_SFSPE_13_EHD_Pos) /*!< SCU SFSPE_13: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPE_14 ------------------------------------------\r
-#define SCU_SFSPE_14_MODE_Pos 0 /*!< SCU SFSPE_14: MODE Position */\r
-#define SCU_SFSPE_14_MODE_Msk (0x07UL << SCU_SFSPE_14_MODE_Pos) /*!< SCU SFSPE_14: MODE Mask */\r
-#define SCU_SFSPE_14_EPD_Pos 3 /*!< SCU SFSPE_14: EPD Position */\r
-#define SCU_SFSPE_14_EPD_Msk (0x01UL << SCU_SFSPE_14_EPD_Pos) /*!< SCU SFSPE_14: EPD Mask */\r
-#define SCU_SFSPE_14_EPUN_Pos 4 /*!< SCU SFSPE_14: EPUN Position */\r
-#define SCU_SFSPE_14_EPUN_Msk (0x01UL << SCU_SFSPE_14_EPUN_Pos) /*!< SCU SFSPE_14: EPUN Mask */\r
-#define SCU_SFSPE_14_EHS_Pos 5 /*!< SCU SFSPE_14: EHS Position */\r
-#define SCU_SFSPE_14_EHS_Msk (0x01UL << SCU_SFSPE_14_EHS_Pos) /*!< SCU SFSPE_14: EHS Mask */\r
-#define SCU_SFSPE_14_EZI_Pos 6 /*!< SCU SFSPE_14: EZI Position */\r
-#define SCU_SFSPE_14_EZI_Msk (0x01UL << SCU_SFSPE_14_EZI_Pos) /*!< SCU SFSPE_14: EZI Mask */\r
-#define SCU_SFSPE_14_EHD_Pos 8 /*!< SCU SFSPE_14: EHD Position */\r
-#define SCU_SFSPE_14_EHD_Msk (0x03UL << SCU_SFSPE_14_EHD_Pos) /*!< SCU SFSPE_14: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPE_15 ------------------------------------------\r
-#define SCU_SFSPE_15_MODE_Pos 0 /*!< SCU SFSPE_15: MODE Position */\r
-#define SCU_SFSPE_15_MODE_Msk (0x07UL << SCU_SFSPE_15_MODE_Pos) /*!< SCU SFSPE_15: MODE Mask */\r
-#define SCU_SFSPE_15_EPD_Pos 3 /*!< SCU SFSPE_15: EPD Position */\r
-#define SCU_SFSPE_15_EPD_Msk (0x01UL << SCU_SFSPE_15_EPD_Pos) /*!< SCU SFSPE_15: EPD Mask */\r
-#define SCU_SFSPE_15_EPUN_Pos 4 /*!< SCU SFSPE_15: EPUN Position */\r
-#define SCU_SFSPE_15_EPUN_Msk (0x01UL << SCU_SFSPE_15_EPUN_Pos) /*!< SCU SFSPE_15: EPUN Mask */\r
-#define SCU_SFSPE_15_EHS_Pos 5 /*!< SCU SFSPE_15: EHS Position */\r
-#define SCU_SFSPE_15_EHS_Msk (0x01UL << SCU_SFSPE_15_EHS_Pos) /*!< SCU SFSPE_15: EHS Mask */\r
-#define SCU_SFSPE_15_EZI_Pos 6 /*!< SCU SFSPE_15: EZI Position */\r
-#define SCU_SFSPE_15_EZI_Msk (0x01UL << SCU_SFSPE_15_EZI_Pos) /*!< SCU SFSPE_15: EZI Mask */\r
-#define SCU_SFSPE_15_EHD_Pos 8 /*!< SCU SFSPE_15: EHD Position */\r
-#define SCU_SFSPE_15_EHD_Msk (0x03UL << SCU_SFSPE_15_EHD_Pos) /*!< SCU SFSPE_15: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_0 ------------------------------------------\r
-#define SCU_SFSPF_0_MODE_Pos 0 /*!< SCU SFSPF_0: MODE Position */\r
-#define SCU_SFSPF_0_MODE_Msk (0x07UL << SCU_SFSPF_0_MODE_Pos) /*!< SCU SFSPF_0: MODE Mask */\r
-#define SCU_SFSPF_0_EPD_Pos 3 /*!< SCU SFSPF_0: EPD Position */\r
-#define SCU_SFSPF_0_EPD_Msk (0x01UL << SCU_SFSPF_0_EPD_Pos) /*!< SCU SFSPF_0: EPD Mask */\r
-#define SCU_SFSPF_0_EPUN_Pos 4 /*!< SCU SFSPF_0: EPUN Position */\r
-#define SCU_SFSPF_0_EPUN_Msk (0x01UL << SCU_SFSPF_0_EPUN_Pos) /*!< SCU SFSPF_0: EPUN Mask */\r
-#define SCU_SFSPF_0_EHS_Pos 5 /*!< SCU SFSPF_0: EHS Position */\r
-#define SCU_SFSPF_0_EHS_Msk (0x01UL << SCU_SFSPF_0_EHS_Pos) /*!< SCU SFSPF_0: EHS Mask */\r
-#define SCU_SFSPF_0_EZI_Pos 6 /*!< SCU SFSPF_0: EZI Position */\r
-#define SCU_SFSPF_0_EZI_Msk (0x01UL << SCU_SFSPF_0_EZI_Pos) /*!< SCU SFSPF_0: EZI Mask */\r
-#define SCU_SFSPF_0_EHD_Pos 8 /*!< SCU SFSPF_0: EHD Position */\r
-#define SCU_SFSPF_0_EHD_Msk (0x03UL << SCU_SFSPF_0_EHD_Pos) /*!< SCU SFSPF_0: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_1 ------------------------------------------\r
-#define SCU_SFSPF_1_MODE_Pos 0 /*!< SCU SFSPF_1: MODE Position */\r
-#define SCU_SFSPF_1_MODE_Msk (0x07UL << SCU_SFSPF_1_MODE_Pos) /*!< SCU SFSPF_1: MODE Mask */\r
-#define SCU_SFSPF_1_EPD_Pos 3 /*!< SCU SFSPF_1: EPD Position */\r
-#define SCU_SFSPF_1_EPD_Msk (0x01UL << SCU_SFSPF_1_EPD_Pos) /*!< SCU SFSPF_1: EPD Mask */\r
-#define SCU_SFSPF_1_EPUN_Pos 4 /*!< SCU SFSPF_1: EPUN Position */\r
-#define SCU_SFSPF_1_EPUN_Msk (0x01UL << SCU_SFSPF_1_EPUN_Pos) /*!< SCU SFSPF_1: EPUN Mask */\r
-#define SCU_SFSPF_1_EHS_Pos 5 /*!< SCU SFSPF_1: EHS Position */\r
-#define SCU_SFSPF_1_EHS_Msk (0x01UL << SCU_SFSPF_1_EHS_Pos) /*!< SCU SFSPF_1: EHS Mask */\r
-#define SCU_SFSPF_1_EZI_Pos 6 /*!< SCU SFSPF_1: EZI Position */\r
-#define SCU_SFSPF_1_EZI_Msk (0x01UL << SCU_SFSPF_1_EZI_Pos) /*!< SCU SFSPF_1: EZI Mask */\r
-#define SCU_SFSPF_1_EHD_Pos 8 /*!< SCU SFSPF_1: EHD Position */\r
-#define SCU_SFSPF_1_EHD_Msk (0x03UL << SCU_SFSPF_1_EHD_Pos) /*!< SCU SFSPF_1: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_2 ------------------------------------------\r
-#define SCU_SFSPF_2_MODE_Pos 0 /*!< SCU SFSPF_2: MODE Position */\r
-#define SCU_SFSPF_2_MODE_Msk (0x07UL << SCU_SFSPF_2_MODE_Pos) /*!< SCU SFSPF_2: MODE Mask */\r
-#define SCU_SFSPF_2_EPD_Pos 3 /*!< SCU SFSPF_2: EPD Position */\r
-#define SCU_SFSPF_2_EPD_Msk (0x01UL << SCU_SFSPF_2_EPD_Pos) /*!< SCU SFSPF_2: EPD Mask */\r
-#define SCU_SFSPF_2_EPUN_Pos 4 /*!< SCU SFSPF_2: EPUN Position */\r
-#define SCU_SFSPF_2_EPUN_Msk (0x01UL << SCU_SFSPF_2_EPUN_Pos) /*!< SCU SFSPF_2: EPUN Mask */\r
-#define SCU_SFSPF_2_EHS_Pos 5 /*!< SCU SFSPF_2: EHS Position */\r
-#define SCU_SFSPF_2_EHS_Msk (0x01UL << SCU_SFSPF_2_EHS_Pos) /*!< SCU SFSPF_2: EHS Mask */\r
-#define SCU_SFSPF_2_EZI_Pos 6 /*!< SCU SFSPF_2: EZI Position */\r
-#define SCU_SFSPF_2_EZI_Msk (0x01UL << SCU_SFSPF_2_EZI_Pos) /*!< SCU SFSPF_2: EZI Mask */\r
-#define SCU_SFSPF_2_EHD_Pos 8 /*!< SCU SFSPF_2: EHD Position */\r
-#define SCU_SFSPF_2_EHD_Msk (0x03UL << SCU_SFSPF_2_EHD_Pos) /*!< SCU SFSPF_2: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_3 ------------------------------------------\r
-#define SCU_SFSPF_3_MODE_Pos 0 /*!< SCU SFSPF_3: MODE Position */\r
-#define SCU_SFSPF_3_MODE_Msk (0x07UL << SCU_SFSPF_3_MODE_Pos) /*!< SCU SFSPF_3: MODE Mask */\r
-#define SCU_SFSPF_3_EPD_Pos 3 /*!< SCU SFSPF_3: EPD Position */\r
-#define SCU_SFSPF_3_EPD_Msk (0x01UL << SCU_SFSPF_3_EPD_Pos) /*!< SCU SFSPF_3: EPD Mask */\r
-#define SCU_SFSPF_3_EPUN_Pos 4 /*!< SCU SFSPF_3: EPUN Position */\r
-#define SCU_SFSPF_3_EPUN_Msk (0x01UL << SCU_SFSPF_3_EPUN_Pos) /*!< SCU SFSPF_3: EPUN Mask */\r
-#define SCU_SFSPF_3_EHS_Pos 5 /*!< SCU SFSPF_3: EHS Position */\r
-#define SCU_SFSPF_3_EHS_Msk (0x01UL << SCU_SFSPF_3_EHS_Pos) /*!< SCU SFSPF_3: EHS Mask */\r
-#define SCU_SFSPF_3_EZI_Pos 6 /*!< SCU SFSPF_3: EZI Position */\r
-#define SCU_SFSPF_3_EZI_Msk (0x01UL << SCU_SFSPF_3_EZI_Pos) /*!< SCU SFSPF_3: EZI Mask */\r
-#define SCU_SFSPF_3_EHD_Pos 8 /*!< SCU SFSPF_3: EHD Position */\r
-#define SCU_SFSPF_3_EHD_Msk (0x03UL << SCU_SFSPF_3_EHD_Pos) /*!< SCU SFSPF_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_4 ------------------------------------------\r
-#define SCU_SFSPF_4_MODE_Pos 0 /*!< SCU SFSPF_4: MODE Position */\r
-#define SCU_SFSPF_4_MODE_Msk (0x07UL << SCU_SFSPF_4_MODE_Pos) /*!< SCU SFSPF_4: MODE Mask */\r
-#define SCU_SFSPF_4_EPD_Pos 3 /*!< SCU SFSPF_4: EPD Position */\r
-#define SCU_SFSPF_4_EPD_Msk (0x01UL << SCU_SFSPF_4_EPD_Pos) /*!< SCU SFSPF_4: EPD Mask */\r
-#define SCU_SFSPF_4_EPUN_Pos 4 /*!< SCU SFSPF_4: EPUN Position */\r
-#define SCU_SFSPF_4_EPUN_Msk (0x01UL << SCU_SFSPF_4_EPUN_Pos) /*!< SCU SFSPF_4: EPUN Mask */\r
-#define SCU_SFSPF_4_EHS_Pos 5 /*!< SCU SFSPF_4: EHS Position */\r
-#define SCU_SFSPF_4_EHS_Msk (0x01UL << SCU_SFSPF_4_EHS_Pos) /*!< SCU SFSPF_4: EHS Mask */\r
-#define SCU_SFSPF_4_EZI_Pos 6 /*!< SCU SFSPF_4: EZI Position */\r
-#define SCU_SFSPF_4_EZI_Msk (0x01UL << SCU_SFSPF_4_EZI_Pos) /*!< SCU SFSPF_4: EZI Mask */\r
-#define SCU_SFSPF_4_EHD_Pos 8 /*!< SCU SFSPF_4: EHD Position */\r
-#define SCU_SFSPF_4_EHD_Msk (0x03UL << SCU_SFSPF_4_EHD_Pos) /*!< SCU SFSPF_4: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_5 ------------------------------------------\r
-#define SCU_SFSPF_5_MODE_Pos 0 /*!< SCU SFSPF_5: MODE Position */\r
-#define SCU_SFSPF_5_MODE_Msk (0x07UL << SCU_SFSPF_5_MODE_Pos) /*!< SCU SFSPF_5: MODE Mask */\r
-#define SCU_SFSPF_5_EPD_Pos 3 /*!< SCU SFSPF_5: EPD Position */\r
-#define SCU_SFSPF_5_EPD_Msk (0x01UL << SCU_SFSPF_5_EPD_Pos) /*!< SCU SFSPF_5: EPD Mask */\r
-#define SCU_SFSPF_5_EPUN_Pos 4 /*!< SCU SFSPF_5: EPUN Position */\r
-#define SCU_SFSPF_5_EPUN_Msk (0x01UL << SCU_SFSPF_5_EPUN_Pos) /*!< SCU SFSPF_5: EPUN Mask */\r
-#define SCU_SFSPF_5_EHS_Pos 5 /*!< SCU SFSPF_5: EHS Position */\r
-#define SCU_SFSPF_5_EHS_Msk (0x01UL << SCU_SFSPF_5_EHS_Pos) /*!< SCU SFSPF_5: EHS Mask */\r
-#define SCU_SFSPF_5_EZI_Pos 6 /*!< SCU SFSPF_5: EZI Position */\r
-#define SCU_SFSPF_5_EZI_Msk (0x01UL << SCU_SFSPF_5_EZI_Pos) /*!< SCU SFSPF_5: EZI Mask */\r
-#define SCU_SFSPF_5_EHD_Pos 8 /*!< SCU SFSPF_5: EHD Position */\r
-#define SCU_SFSPF_5_EHD_Msk (0x03UL << SCU_SFSPF_5_EHD_Pos) /*!< SCU SFSPF_5: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_6 ------------------------------------------\r
-#define SCU_SFSPF_6_MODE_Pos 0 /*!< SCU SFSPF_6: MODE Position */\r
-#define SCU_SFSPF_6_MODE_Msk (0x07UL << SCU_SFSPF_6_MODE_Pos) /*!< SCU SFSPF_6: MODE Mask */\r
-#define SCU_SFSPF_6_EPD_Pos 3 /*!< SCU SFSPF_6: EPD Position */\r
-#define SCU_SFSPF_6_EPD_Msk (0x01UL << SCU_SFSPF_6_EPD_Pos) /*!< SCU SFSPF_6: EPD Mask */\r
-#define SCU_SFSPF_6_EPUN_Pos 4 /*!< SCU SFSPF_6: EPUN Position */\r
-#define SCU_SFSPF_6_EPUN_Msk (0x01UL << SCU_SFSPF_6_EPUN_Pos) /*!< SCU SFSPF_6: EPUN Mask */\r
-#define SCU_SFSPF_6_EHS_Pos 5 /*!< SCU SFSPF_6: EHS Position */\r
-#define SCU_SFSPF_6_EHS_Msk (0x01UL << SCU_SFSPF_6_EHS_Pos) /*!< SCU SFSPF_6: EHS Mask */\r
-#define SCU_SFSPF_6_EZI_Pos 6 /*!< SCU SFSPF_6: EZI Position */\r
-#define SCU_SFSPF_6_EZI_Msk (0x01UL << SCU_SFSPF_6_EZI_Pos) /*!< SCU SFSPF_6: EZI Mask */\r
-#define SCU_SFSPF_6_EHD_Pos 8 /*!< SCU SFSPF_6: EHD Position */\r
-#define SCU_SFSPF_6_EHD_Msk (0x03UL << SCU_SFSPF_6_EHD_Pos) /*!< SCU SFSPF_6: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_7 ------------------------------------------\r
-#define SCU_SFSPF_7_MODE_Pos 0 /*!< SCU SFSPF_7: MODE Position */\r
-#define SCU_SFSPF_7_MODE_Msk (0x07UL << SCU_SFSPF_7_MODE_Pos) /*!< SCU SFSPF_7: MODE Mask */\r
-#define SCU_SFSPF_7_EPD_Pos 3 /*!< SCU SFSPF_7: EPD Position */\r
-#define SCU_SFSPF_7_EPD_Msk (0x01UL << SCU_SFSPF_7_EPD_Pos) /*!< SCU SFSPF_7: EPD Mask */\r
-#define SCU_SFSPF_7_EPUN_Pos 4 /*!< SCU SFSPF_7: EPUN Position */\r
-#define SCU_SFSPF_7_EPUN_Msk (0x01UL << SCU_SFSPF_7_EPUN_Pos) /*!< SCU SFSPF_7: EPUN Mask */\r
-#define SCU_SFSPF_7_EHS_Pos 5 /*!< SCU SFSPF_7: EHS Position */\r
-#define SCU_SFSPF_7_EHS_Msk (0x01UL << SCU_SFSPF_7_EHS_Pos) /*!< SCU SFSPF_7: EHS Mask */\r
-#define SCU_SFSPF_7_EZI_Pos 6 /*!< SCU SFSPF_7: EZI Position */\r
-#define SCU_SFSPF_7_EZI_Msk (0x01UL << SCU_SFSPF_7_EZI_Pos) /*!< SCU SFSPF_7: EZI Mask */\r
-#define SCU_SFSPF_7_EHD_Pos 8 /*!< SCU SFSPF_7: EHD Position */\r
-#define SCU_SFSPF_7_EHD_Msk (0x03UL << SCU_SFSPF_7_EHD_Pos) /*!< SCU SFSPF_7: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_8 ------------------------------------------\r
-#define SCU_SFSPF_8_MODE_Pos 0 /*!< SCU SFSPF_8: MODE Position */\r
-#define SCU_SFSPF_8_MODE_Msk (0x07UL << SCU_SFSPF_8_MODE_Pos) /*!< SCU SFSPF_8: MODE Mask */\r
-#define SCU_SFSPF_8_EPD_Pos 3 /*!< SCU SFSPF_8: EPD Position */\r
-#define SCU_SFSPF_8_EPD_Msk (0x01UL << SCU_SFSPF_8_EPD_Pos) /*!< SCU SFSPF_8: EPD Mask */\r
-#define SCU_SFSPF_8_EPUN_Pos 4 /*!< SCU SFSPF_8: EPUN Position */\r
-#define SCU_SFSPF_8_EPUN_Msk (0x01UL << SCU_SFSPF_8_EPUN_Pos) /*!< SCU SFSPF_8: EPUN Mask */\r
-#define SCU_SFSPF_8_EHS_Pos 5 /*!< SCU SFSPF_8: EHS Position */\r
-#define SCU_SFSPF_8_EHS_Msk (0x01UL << SCU_SFSPF_8_EHS_Pos) /*!< SCU SFSPF_8: EHS Mask */\r
-#define SCU_SFSPF_8_EZI_Pos 6 /*!< SCU SFSPF_8: EZI Position */\r
-#define SCU_SFSPF_8_EZI_Msk (0x01UL << SCU_SFSPF_8_EZI_Pos) /*!< SCU SFSPF_8: EZI Mask */\r
-#define SCU_SFSPF_8_EHD_Pos 8 /*!< SCU SFSPF_8: EHD Position */\r
-#define SCU_SFSPF_8_EHD_Msk (0x03UL << SCU_SFSPF_8_EHD_Pos) /*!< SCU SFSPF_8: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSPF_9 ------------------------------------------\r
-#define SCU_SFSPF_9_MODE_Pos 0 /*!< SCU SFSPF_9: MODE Position */\r
-#define SCU_SFSPF_9_MODE_Msk (0x07UL << SCU_SFSPF_9_MODE_Pos) /*!< SCU SFSPF_9: MODE Mask */\r
-#define SCU_SFSPF_9_EPD_Pos 3 /*!< SCU SFSPF_9: EPD Position */\r
-#define SCU_SFSPF_9_EPD_Msk (0x01UL << SCU_SFSPF_9_EPD_Pos) /*!< SCU SFSPF_9: EPD Mask */\r
-#define SCU_SFSPF_9_EPUN_Pos 4 /*!< SCU SFSPF_9: EPUN Position */\r
-#define SCU_SFSPF_9_EPUN_Msk (0x01UL << SCU_SFSPF_9_EPUN_Pos) /*!< SCU SFSPF_9: EPUN Mask */\r
-#define SCU_SFSPF_9_EHS_Pos 5 /*!< SCU SFSPF_9: EHS Position */\r
-#define SCU_SFSPF_9_EHS_Msk (0x01UL << SCU_SFSPF_9_EHS_Pos) /*!< SCU SFSPF_9: EHS Mask */\r
-#define SCU_SFSPF_9_EZI_Pos 6 /*!< SCU SFSPF_9: EZI Position */\r
-#define SCU_SFSPF_9_EZI_Msk (0x01UL << SCU_SFSPF_9_EZI_Pos) /*!< SCU SFSPF_9: EZI Mask */\r
-#define SCU_SFSPF_9_EHD_Pos 8 /*!< SCU SFSPF_9: EHD Position */\r
-#define SCU_SFSPF_9_EHD_Msk (0x03UL << SCU_SFSPF_9_EHD_Pos) /*!< SCU SFSPF_9: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPF_10 ------------------------------------------\r
-#define SCU_SFSPF_10_MODE_Pos 0 /*!< SCU SFSPF_10: MODE Position */\r
-#define SCU_SFSPF_10_MODE_Msk (0x07UL << SCU_SFSPF_10_MODE_Pos) /*!< SCU SFSPF_10: MODE Mask */\r
-#define SCU_SFSPF_10_EPD_Pos 3 /*!< SCU SFSPF_10: EPD Position */\r
-#define SCU_SFSPF_10_EPD_Msk (0x01UL << SCU_SFSPF_10_EPD_Pos) /*!< SCU SFSPF_10: EPD Mask */\r
-#define SCU_SFSPF_10_EPUN_Pos 4 /*!< SCU SFSPF_10: EPUN Position */\r
-#define SCU_SFSPF_10_EPUN_Msk (0x01UL << SCU_SFSPF_10_EPUN_Pos) /*!< SCU SFSPF_10: EPUN Mask */\r
-#define SCU_SFSPF_10_EHS_Pos 5 /*!< SCU SFSPF_10: EHS Position */\r
-#define SCU_SFSPF_10_EHS_Msk (0x01UL << SCU_SFSPF_10_EHS_Pos) /*!< SCU SFSPF_10: EHS Mask */\r
-#define SCU_SFSPF_10_EZI_Pos 6 /*!< SCU SFSPF_10: EZI Position */\r
-#define SCU_SFSPF_10_EZI_Msk (0x01UL << SCU_SFSPF_10_EZI_Pos) /*!< SCU SFSPF_10: EZI Mask */\r
-#define SCU_SFSPF_10_EHD_Pos 8 /*!< SCU SFSPF_10: EHD Position */\r
-#define SCU_SFSPF_10_EHD_Msk (0x03UL << SCU_SFSPF_10_EHD_Pos) /*!< SCU SFSPF_10: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSPF_11 ------------------------------------------\r
-#define SCU_SFSPF_11_MODE_Pos 0 /*!< SCU SFSPF_11: MODE Position */\r
-#define SCU_SFSPF_11_MODE_Msk (0x07UL << SCU_SFSPF_11_MODE_Pos) /*!< SCU SFSPF_11: MODE Mask */\r
-#define SCU_SFSPF_11_EPD_Pos 3 /*!< SCU SFSPF_11: EPD Position */\r
-#define SCU_SFSPF_11_EPD_Msk (0x01UL << SCU_SFSPF_11_EPD_Pos) /*!< SCU SFSPF_11: EPD Mask */\r
-#define SCU_SFSPF_11_EPUN_Pos 4 /*!< SCU SFSPF_11: EPUN Position */\r
-#define SCU_SFSPF_11_EPUN_Msk (0x01UL << SCU_SFSPF_11_EPUN_Pos) /*!< SCU SFSPF_11: EPUN Mask */\r
-#define SCU_SFSPF_11_EHS_Pos 5 /*!< SCU SFSPF_11: EHS Position */\r
-#define SCU_SFSPF_11_EHS_Msk (0x01UL << SCU_SFSPF_11_EHS_Pos) /*!< SCU SFSPF_11: EHS Mask */\r
-#define SCU_SFSPF_11_EZI_Pos 6 /*!< SCU SFSPF_11: EZI Position */\r
-#define SCU_SFSPF_11_EZI_Msk (0x01UL << SCU_SFSPF_11_EZI_Pos) /*!< SCU SFSPF_11: EZI Mask */\r
-#define SCU_SFSPF_11_EHD_Pos 8 /*!< SCU SFSPF_11: EHD Position */\r
-#define SCU_SFSPF_11_EHD_Msk (0x03UL << SCU_SFSPF_11_EHD_Pos) /*!< SCU SFSPF_11: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSCLK_0 ------------------------------------------\r
-#define SCU_SFSCLK_0_MODE_Pos 0 /*!< SCU SFSCLK_0: MODE Position */\r
-#define SCU_SFSCLK_0_MODE_Msk (0x07UL << SCU_SFSCLK_0_MODE_Pos) /*!< SCU SFSCLK_0: MODE Mask */\r
-#define SCU_SFSCLK_0_EPD_Pos 3 /*!< SCU SFSCLK_0: EPD Position */\r
-#define SCU_SFSCLK_0_EPD_Msk (0x01UL << SCU_SFSCLK_0_EPD_Pos) /*!< SCU SFSCLK_0: EPD Mask */\r
-#define SCU_SFSCLK_0_EPUN_Pos 4 /*!< SCU SFSCLK_0: EPUN Position */\r
-#define SCU_SFSCLK_0_EPUN_Msk (0x01UL << SCU_SFSCLK_0_EPUN_Pos) /*!< SCU SFSCLK_0: EPUN Mask */\r
-#define SCU_SFSCLK_0_EHS_Pos 5 /*!< SCU SFSCLK_0: EHS Position */\r
-#define SCU_SFSCLK_0_EHS_Msk (0x01UL << SCU_SFSCLK_0_EHS_Pos) /*!< SCU SFSCLK_0: EHS Mask */\r
-#define SCU_SFSCLK_0_EZI_Pos 6 /*!< SCU SFSCLK_0: EZI Position */\r
-#define SCU_SFSCLK_0_EZI_Msk (0x01UL << SCU_SFSCLK_0_EZI_Pos) /*!< SCU SFSCLK_0: EZI Mask */\r
-#define SCU_SFSCLK_0_EHD_Pos 8 /*!< SCU SFSCLK_0: EHD Position */\r
-#define SCU_SFSCLK_0_EHD_Msk (0x03UL << SCU_SFSCLK_0_EHD_Pos) /*!< SCU SFSCLK_0: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSCLK_1 ------------------------------------------\r
-#define SCU_SFSCLK_1_MODE_Pos 0 /*!< SCU SFSCLK_1: MODE Position */\r
-#define SCU_SFSCLK_1_MODE_Msk (0x07UL << SCU_SFSCLK_1_MODE_Pos) /*!< SCU SFSCLK_1: MODE Mask */\r
-#define SCU_SFSCLK_1_EPD_Pos 3 /*!< SCU SFSCLK_1: EPD Position */\r
-#define SCU_SFSCLK_1_EPD_Msk (0x01UL << SCU_SFSCLK_1_EPD_Pos) /*!< SCU SFSCLK_1: EPD Mask */\r
-#define SCU_SFSCLK_1_EPUN_Pos 4 /*!< SCU SFSCLK_1: EPUN Position */\r
-#define SCU_SFSCLK_1_EPUN_Msk (0x01UL << SCU_SFSCLK_1_EPUN_Pos) /*!< SCU SFSCLK_1: EPUN Mask */\r
-#define SCU_SFSCLK_1_EHS_Pos 5 /*!< SCU SFSCLK_1: EHS Position */\r
-#define SCU_SFSCLK_1_EHS_Msk (0x01UL << SCU_SFSCLK_1_EHS_Pos) /*!< SCU SFSCLK_1: EHS Mask */\r
-#define SCU_SFSCLK_1_EZI_Pos 6 /*!< SCU SFSCLK_1: EZI Position */\r
-#define SCU_SFSCLK_1_EZI_Msk (0x01UL << SCU_SFSCLK_1_EZI_Pos) /*!< SCU SFSCLK_1: EZI Mask */\r
-#define SCU_SFSCLK_1_EHD_Pos 8 /*!< SCU SFSCLK_1: EHD Position */\r
-#define SCU_SFSCLK_1_EHD_Msk (0x03UL << SCU_SFSCLK_1_EHD_Pos) /*!< SCU SFSCLK_1: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSCLK_2 ------------------------------------------\r
-#define SCU_SFSCLK_2_MODE_Pos 0 /*!< SCU SFSCLK_2: MODE Position */\r
-#define SCU_SFSCLK_2_MODE_Msk (0x07UL << SCU_SFSCLK_2_MODE_Pos) /*!< SCU SFSCLK_2: MODE Mask */\r
-#define SCU_SFSCLK_2_EPD_Pos 3 /*!< SCU SFSCLK_2: EPD Position */\r
-#define SCU_SFSCLK_2_EPD_Msk (0x01UL << SCU_SFSCLK_2_EPD_Pos) /*!< SCU SFSCLK_2: EPD Mask */\r
-#define SCU_SFSCLK_2_EPUN_Pos 4 /*!< SCU SFSCLK_2: EPUN Position */\r
-#define SCU_SFSCLK_2_EPUN_Msk (0x01UL << SCU_SFSCLK_2_EPUN_Pos) /*!< SCU SFSCLK_2: EPUN Mask */\r
-#define SCU_SFSCLK_2_EHS_Pos 5 /*!< SCU SFSCLK_2: EHS Position */\r
-#define SCU_SFSCLK_2_EHS_Msk (0x01UL << SCU_SFSCLK_2_EHS_Pos) /*!< SCU SFSCLK_2: EHS Mask */\r
-#define SCU_SFSCLK_2_EZI_Pos 6 /*!< SCU SFSCLK_2: EZI Position */\r
-#define SCU_SFSCLK_2_EZI_Msk (0x01UL << SCU_SFSCLK_2_EZI_Pos) /*!< SCU SFSCLK_2: EZI Mask */\r
-#define SCU_SFSCLK_2_EHD_Pos 8 /*!< SCU SFSCLK_2: EHD Position */\r
-#define SCU_SFSCLK_2_EHD_Msk (0x03UL << SCU_SFSCLK_2_EHD_Pos) /*!< SCU SFSCLK_2: EHD Mask */\r
-\r
-// -------------------------------------- SCU_SFSCLK_3 ------------------------------------------\r
-#define SCU_SFSCLK_3_MODE_Pos 0 /*!< SCU SFSCLK_3: MODE Position */\r
-#define SCU_SFSCLK_3_MODE_Msk (0x07UL << SCU_SFSCLK_3_MODE_Pos) /*!< SCU SFSCLK_3: MODE Mask */\r
-#define SCU_SFSCLK_3_EPD_Pos 3 /*!< SCU SFSCLK_3: EPD Position */\r
-#define SCU_SFSCLK_3_EPD_Msk (0x01UL << SCU_SFSCLK_3_EPD_Pos) /*!< SCU SFSCLK_3: EPD Mask */\r
-#define SCU_SFSCLK_3_EPUN_Pos 4 /*!< SCU SFSCLK_3: EPUN Position */\r
-#define SCU_SFSCLK_3_EPUN_Msk (0x01UL << SCU_SFSCLK_3_EPUN_Pos) /*!< SCU SFSCLK_3: EPUN Mask */\r
-#define SCU_SFSCLK_3_EHS_Pos 5 /*!< SCU SFSCLK_3: EHS Position */\r
-#define SCU_SFSCLK_3_EHS_Msk (0x01UL << SCU_SFSCLK_3_EHS_Pos) /*!< SCU SFSCLK_3: EHS Mask */\r
-#define SCU_SFSCLK_3_EZI_Pos 6 /*!< SCU SFSCLK_3: EZI Position */\r
-#define SCU_SFSCLK_3_EZI_Msk (0x01UL << SCU_SFSCLK_3_EZI_Pos) /*!< SCU SFSCLK_3: EZI Mask */\r
-#define SCU_SFSCLK_3_EHD_Pos 8 /*!< SCU SFSCLK_3: EHD Position */\r
-#define SCU_SFSCLK_3_EHD_Msk (0x03UL << SCU_SFSCLK_3_EHD_Pos) /*!< SCU SFSCLK_3: EHD Mask */\r
-\r
-// --------------------------------------- SCU_SFSUSB -------------------------------------------\r
-#define SCU_SFSUSB_USB_AIM_Pos 0 /*!< SCU SFSUSB: USB_AIM Position */\r
-#define SCU_SFSUSB_USB_AIM_Msk (0x01UL << SCU_SFSUSB_USB_AIM_Pos) /*!< SCU SFSUSB: USB_AIM Mask */\r
-#define SCU_SFSUSB_USB_ESEA_Pos 1 /*!< SCU SFSUSB: USB_ESEA Position */\r
-#define SCU_SFSUSB_USB_ESEA_Msk (0x01UL << SCU_SFSUSB_USB_ESEA_Pos) /*!< SCU SFSUSB: USB_ESEA Mask */\r
-\r
-// --------------------------------------- SCU_SFSI2C0 ------------------------------------------\r
-#define SCU_SFSI2C0_SDA_EHS_Pos 0 /*!< SCU SFSI2C0: SDA_EHS Position */\r
-#define SCU_SFSI2C0_SDA_EHS_Msk (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos) /*!< SCU SFSI2C0: SDA_EHS Mask */\r
-#define SCU_SFSI2C0_SCL_EHS_Pos 1 /*!< SCU SFSI2C0: SCL_EHS Position */\r
-#define SCU_SFSI2C0_SCL_EHS_Msk (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos) /*!< SCU SFSI2C0: SCL_EHS Mask */\r
-#define SCU_SFSI2C0_SCL_ECS_Pos 2 /*!< SCU SFSI2C0: SCL_ECS Position */\r
-#define SCU_SFSI2C0_SCL_ECS_Msk (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos) /*!< SCU SFSI2C0: SCL_ECS Mask */\r
-\r
-// --------------------------------------- SCU_ENAIO0 -------------------------------------------\r
-#define SCU_ENAIO0_ADC0_0_Pos 0 /*!< SCU ENAIO0: ADC0_0 Position */\r
-#define SCU_ENAIO0_ADC0_0_Msk (0x01UL << SCU_ENAIO0_ADC0_0_Pos) /*!< SCU ENAIO0: ADC0_0 Mask */\r
-#define SCU_ENAIO0_ADC0_1_Pos 1 /*!< SCU ENAIO0: ADC0_1 Position */\r
-#define SCU_ENAIO0_ADC0_1_Msk (0x01UL << SCU_ENAIO0_ADC0_1_Pos) /*!< SCU ENAIO0: ADC0_1 Mask */\r
-#define SCU_ENAIO0_ADC0_2_Pos 2 /*!< SCU ENAIO0: ADC0_2 Position */\r
-#define SCU_ENAIO0_ADC0_2_Msk (0x01UL << SCU_ENAIO0_ADC0_2_Pos) /*!< SCU ENAIO0: ADC0_2 Mask */\r
-#define SCU_ENAIO0_ADC0_3_Pos 3 /*!< SCU ENAIO0: ADC0_3 Position */\r
-#define SCU_ENAIO0_ADC0_3_Msk (0x01UL << SCU_ENAIO0_ADC0_3_Pos) /*!< SCU ENAIO0: ADC0_3 Mask */\r
-#define SCU_ENAIO0_ADC0_4_Pos 4 /*!< SCU ENAIO0: ADC0_4 Position */\r
-#define SCU_ENAIO0_ADC0_4_Msk (0x01UL << SCU_ENAIO0_ADC0_4_Pos) /*!< SCU ENAIO0: ADC0_4 Mask */\r
-#define SCU_ENAIO0_ADC0_5_Pos 5 /*!< SCU ENAIO0: ADC0_5 Position */\r
-#define SCU_ENAIO0_ADC0_5_Msk (0x01UL << SCU_ENAIO0_ADC0_5_Pos) /*!< SCU ENAIO0: ADC0_5 Mask */\r
-#define SCU_ENAIO0_ADC0_6_Pos 6 /*!< SCU ENAIO0: ADC0_6 Position */\r
-#define SCU_ENAIO0_ADC0_6_Msk (0x01UL << SCU_ENAIO0_ADC0_6_Pos) /*!< SCU ENAIO0: ADC0_6 Mask */\r
-\r
-// --------------------------------------- SCU_ENAIO1 -------------------------------------------\r
-#define SCU_ENAIO1_ADC1_0_Pos 0 /*!< SCU ENAIO1: ADC1_0 Position */\r
-#define SCU_ENAIO1_ADC1_0_Msk (0x01UL << SCU_ENAIO1_ADC1_0_Pos) /*!< SCU ENAIO1: ADC1_0 Mask */\r
-#define SCU_ENAIO1_ADC1_1_Pos 1 /*!< SCU ENAIO1: ADC1_1 Position */\r
-#define SCU_ENAIO1_ADC1_1_Msk (0x01UL << SCU_ENAIO1_ADC1_1_Pos) /*!< SCU ENAIO1: ADC1_1 Mask */\r
-#define SCU_ENAIO1_ADC1_2_Pos 2 /*!< SCU ENAIO1: ADC1_2 Position */\r
-#define SCU_ENAIO1_ADC1_2_Msk (0x01UL << SCU_ENAIO1_ADC1_2_Pos) /*!< SCU ENAIO1: ADC1_2 Mask */\r
-#define SCU_ENAIO1_ADC1_3_Pos 3 /*!< SCU ENAIO1: ADC1_3 Position */\r
-#define SCU_ENAIO1_ADC1_3_Msk (0x01UL << SCU_ENAIO1_ADC1_3_Pos) /*!< SCU ENAIO1: ADC1_3 Mask */\r
-#define SCU_ENAIO1_ADC1_4_Pos 4 /*!< SCU ENAIO1: ADC1_4 Position */\r
-#define SCU_ENAIO1_ADC1_4_Msk (0x01UL << SCU_ENAIO1_ADC1_4_Pos) /*!< SCU ENAIO1: ADC1_4 Mask */\r
-#define SCU_ENAIO1_ADC1_5_Pos 5 /*!< SCU ENAIO1: ADC1_5 Position */\r
-#define SCU_ENAIO1_ADC1_5_Msk (0x01UL << SCU_ENAIO1_ADC1_5_Pos) /*!< SCU ENAIO1: ADC1_5 Mask */\r
-#define SCU_ENAIO1_ADC1_6_Pos 6 /*!< SCU ENAIO1: ADC1_6 Position */\r
-#define SCU_ENAIO1_ADC1_6_Msk (0x01UL << SCU_ENAIO1_ADC1_6_Pos) /*!< SCU ENAIO1: ADC1_6 Mask */\r
-#define SCU_ENAIO1_ADC1_7_Pos 7 /*!< SCU ENAIO1: ADC1_7 Position */\r
-#define SCU_ENAIO1_ADC1_7_Msk (0x01UL << SCU_ENAIO1_ADC1_7_Pos) /*!< SCU ENAIO1: ADC1_7 Mask */\r
-\r
-// --------------------------------------- SCU_ENAIO2 -------------------------------------------\r
-#define SCU_ENAIO2_DAC_Pos 0 /*!< SCU ENAIO2: DAC Position */\r
-#define SCU_ENAIO2_DAC_Msk (0x01UL << SCU_ENAIO2_DAC_Pos) /*!< SCU ENAIO2: DAC Mask */\r
-#define SCU_ENAIO2_BG_Pos 4 /*!< SCU ENAIO2: BG Position */\r
-#define SCU_ENAIO2_BG_Msk (0x01UL << SCU_ENAIO2_BG_Pos) /*!< SCU ENAIO2: BG Mask */\r
-\r
-// ------------------------------------- SCU_EMCDELAYCLK ----------------------------------------\r
-#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos 0 /*!< SCU EMCDELAYCLK: CLK0_DELAY Position */\r
-#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK0_DELAY Mask */\r
-#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos 4 /*!< SCU EMCDELAYCLK: CLK1_DELAY Position */\r
-#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK1_DELAY Mask */\r
-#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos 8 /*!< SCU EMCDELAYCLK: CLK2_DELAY Position */\r
-#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK2_DELAY Mask */\r
-#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos 12 /*!< SCU EMCDELAYCLK: CLK3_DELAY Position */\r
-#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK3_DELAY Mask */\r
-#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos 16 /*!< SCU EMCDELAYCLK: CKE0_DELAY Position */\r
-#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE0_DELAY Mask */\r
-#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos 20 /*!< SCU EMCDELAYCLK: CKE1_DELAY Position */\r
-#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE1_DELAY Mask */\r
-#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos 24 /*!< SCU EMCDELAYCLK: CKE2_DELAY Position */\r
-#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE2_DELAY Mask */\r
-#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos 28 /*!< SCU EMCDELAYCLK: CKE3_DELAY Position */\r
-#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE3_DELAY Mask */\r
-\r
-// -------------------------------------- SCU_PINTSEL0 ------------------------------------------\r
-#define SCU_PINTSEL0_INTPIN0_Pos 0 /*!< SCU PINTSEL0: INTPIN0 Position */\r
-#define SCU_PINTSEL0_INTPIN0_Msk (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos) /*!< SCU PINTSEL0: INTPIN0 Mask */\r
-#define SCU_PINTSEL0_PORTSEL0_Pos 5 /*!< SCU PINTSEL0: PORTSEL0 Position */\r
-#define SCU_PINTSEL0_PORTSEL0_Msk (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos) /*!< SCU PINTSEL0: PORTSEL0 Mask */\r
-#define SCU_PINTSEL0_INTPIN1_Pos 8 /*!< SCU PINTSEL0: INTPIN1 Position */\r
-#define SCU_PINTSEL0_INTPIN1_Msk (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos) /*!< SCU PINTSEL0: INTPIN1 Mask */\r
-#define SCU_PINTSEL0_PORTSEL1_Pos 13 /*!< SCU PINTSEL0: PORTSEL1 Position */\r
-#define SCU_PINTSEL0_PORTSEL1_Msk (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos) /*!< SCU PINTSEL0: PORTSEL1 Mask */\r
-#define SCU_PINTSEL0_INTPIN2_Pos 16 /*!< SCU PINTSEL0: INTPIN2 Position */\r
-#define SCU_PINTSEL0_INTPIN2_Msk (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos) /*!< SCU PINTSEL0: INTPIN2 Mask */\r
-#define SCU_PINTSEL0_PORTSEL2_Pos 21 /*!< SCU PINTSEL0: PORTSEL2 Position */\r
-#define SCU_PINTSEL0_PORTSEL2_Msk (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos) /*!< SCU PINTSEL0: PORTSEL2 Mask */\r
-#define SCU_PINTSEL0_INTPIN3_Pos 24 /*!< SCU PINTSEL0: INTPIN3 Position */\r
-#define SCU_PINTSEL0_INTPIN3_Msk (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos) /*!< SCU PINTSEL0: INTPIN3 Mask */\r
-#define SCU_PINTSEL0_PORTSEL3_Pos 29 /*!< SCU PINTSEL0: PORTSEL3 Position */\r
-#define SCU_PINTSEL0_PORTSEL3_Msk (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos) /*!< SCU PINTSEL0: PORTSEL3 Mask */\r
-\r
-// -------------------------------------- SCU_PINTSEL1 ------------------------------------------\r
-#define SCU_PINTSEL1_INTPIN4_Pos 0 /*!< SCU PINTSEL1: INTPIN4 Position */\r
-#define SCU_PINTSEL1_INTPIN4_Msk (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos) /*!< SCU PINTSEL1: INTPIN4 Mask */\r
-#define SCU_PINTSEL1_PORTSEL4_Pos 5 /*!< SCU PINTSEL1: PORTSEL4 Position */\r
-#define SCU_PINTSEL1_PORTSEL4_Msk (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos) /*!< SCU PINTSEL1: PORTSEL4 Mask */\r
-#define SCU_PINTSEL1_INTPIN5_Pos 8 /*!< SCU PINTSEL1: INTPIN5 Position */\r
-#define SCU_PINTSEL1_INTPIN5_Msk (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos) /*!< SCU PINTSEL1: INTPIN5 Mask */\r
-#define SCU_PINTSEL1_PORTSEL5_Pos 13 /*!< SCU PINTSEL1: PORTSEL5 Position */\r
-#define SCU_PINTSEL1_PORTSEL5_Msk (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos) /*!< SCU PINTSEL1: PORTSEL5 Mask */\r
-#define SCU_PINTSEL1_INTPIN6_Pos 16 /*!< SCU PINTSEL1: INTPIN6 Position */\r
-#define SCU_PINTSEL1_INTPIN6_Msk (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos) /*!< SCU PINTSEL1: INTPIN6 Mask */\r
-#define SCU_PINTSEL1_PORTSEL6_Pos 21 /*!< SCU PINTSEL1: PORTSEL6 Position */\r
-#define SCU_PINTSEL1_PORTSEL6_Msk (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos) /*!< SCU PINTSEL1: PORTSEL6 Mask */\r
-#define SCU_PINTSEL1_INTPIN7_Pos 24 /*!< SCU PINTSEL1: INTPIN7 Position */\r
-#define SCU_PINTSEL1_INTPIN7_Msk (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos) /*!< SCU PINTSEL1: INTPIN7 Mask */\r
-#define SCU_PINTSEL1_PORTSEL7_Pos 29 /*!< SCU PINTSEL1: PORTSEL7 Position */\r
-#define SCU_PINTSEL1_PORTSEL7_Msk (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos) /*!< SCU PINTSEL1: PORTSEL7 Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GPIO_PIN_INT Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ------------------------------------ GPIO_PIN_INT_ISEL ---------------------------------------\r
-#define GPIO_PIN_INT_ISEL_PMODE0_Pos 0 /*!< GPIO_PIN_INT ISEL: PMODE0 Position */\r
-#define GPIO_PIN_INT_ISEL_PMODE0_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos) /*!< GPIO_PIN_INT ISEL: PMODE0 Mask */\r
-#define GPIO_PIN_INT_ISEL_PMODE1_Pos 1 /*!< GPIO_PIN_INT ISEL: PMODE1 Position */\r
-#define GPIO_PIN_INT_ISEL_PMODE1_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos) /*!< GPIO_PIN_INT ISEL: PMODE1 Mask */\r
-#define GPIO_PIN_INT_ISEL_PMODE2_Pos 2 /*!< GPIO_PIN_INT ISEL: PMODE2 Position */\r
-#define GPIO_PIN_INT_ISEL_PMODE2_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos) /*!< GPIO_PIN_INT ISEL: PMODE2 Mask */\r
-#define GPIO_PIN_INT_ISEL_PMODE3_Pos 3 /*!< GPIO_PIN_INT ISEL: PMODE3 Position */\r
-#define GPIO_PIN_INT_ISEL_PMODE3_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos) /*!< GPIO_PIN_INT ISEL: PMODE3 Mask */\r
-#define GPIO_PIN_INT_ISEL_PMODE4_Pos 4 /*!< GPIO_PIN_INT ISEL: PMODE4 Position */\r
-#define GPIO_PIN_INT_ISEL_PMODE4_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos) /*!< GPIO_PIN_INT ISEL: PMODE4 Mask */\r
-#define GPIO_PIN_INT_ISEL_PMODE5_Pos 5 /*!< GPIO_PIN_INT ISEL: PMODE5 Position */\r
-#define GPIO_PIN_INT_ISEL_PMODE5_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos) /*!< GPIO_PIN_INT ISEL: PMODE5 Mask */\r
-#define GPIO_PIN_INT_ISEL_PMODE6_Pos 6 /*!< GPIO_PIN_INT ISEL: PMODE6 Position */\r
-#define GPIO_PIN_INT_ISEL_PMODE6_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos) /*!< GPIO_PIN_INT ISEL: PMODE6 Mask */\r
-#define GPIO_PIN_INT_ISEL_PMODE7_Pos 7 /*!< GPIO_PIN_INT ISEL: PMODE7 Position */\r
-#define GPIO_PIN_INT_ISEL_PMODE7_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos) /*!< GPIO_PIN_INT ISEL: PMODE7 Mask */\r
-\r
-// ------------------------------------ GPIO_PIN_INT_IENR ---------------------------------------\r
-#define GPIO_PIN_INT_IENR_ENRL0_Pos 0 /*!< GPIO_PIN_INT IENR: ENRL0 Position */\r
-#define GPIO_PIN_INT_IENR_ENRL0_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos) /*!< GPIO_PIN_INT IENR: ENRL0 Mask */\r
-#define GPIO_PIN_INT_IENR_ENRL1_Pos 1 /*!< GPIO_PIN_INT IENR: ENRL1 Position */\r
-#define GPIO_PIN_INT_IENR_ENRL1_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos) /*!< GPIO_PIN_INT IENR: ENRL1 Mask */\r
-#define GPIO_PIN_INT_IENR_ENRL2_Pos 2 /*!< GPIO_PIN_INT IENR: ENRL2 Position */\r
-#define GPIO_PIN_INT_IENR_ENRL2_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos) /*!< GPIO_PIN_INT IENR: ENRL2 Mask */\r
-#define GPIO_PIN_INT_IENR_ENRL3_Pos 3 /*!< GPIO_PIN_INT IENR: ENRL3 Position */\r
-#define GPIO_PIN_INT_IENR_ENRL3_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos) /*!< GPIO_PIN_INT IENR: ENRL3 Mask */\r
-#define GPIO_PIN_INT_IENR_ENRL4_Pos 4 /*!< GPIO_PIN_INT IENR: ENRL4 Position */\r
-#define GPIO_PIN_INT_IENR_ENRL4_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos) /*!< GPIO_PIN_INT IENR: ENRL4 Mask */\r
-#define GPIO_PIN_INT_IENR_ENRL5_Pos 5 /*!< GPIO_PIN_INT IENR: ENRL5 Position */\r
-#define GPIO_PIN_INT_IENR_ENRL5_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos) /*!< GPIO_PIN_INT IENR: ENRL5 Mask */\r
-#define GPIO_PIN_INT_IENR_ENRL6_Pos 6 /*!< GPIO_PIN_INT IENR: ENRL6 Position */\r
-#define GPIO_PIN_INT_IENR_ENRL6_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos) /*!< GPIO_PIN_INT IENR: ENRL6 Mask */\r
-#define GPIO_PIN_INT_IENR_ENRL7_Pos 7 /*!< GPIO_PIN_INT IENR: ENRL7 Position */\r
-#define GPIO_PIN_INT_IENR_ENRL7_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos) /*!< GPIO_PIN_INT IENR: ENRL7 Mask */\r
-\r
-// ----------------------------------- GPIO_PIN_INT_SIENR ---------------------------------------\r
-#define GPIO_PIN_INT_SIENR_SETENRL0_Pos 0 /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */\r
-#define GPIO_PIN_INT_SIENR_SETENRL0_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask */\r
-#define GPIO_PIN_INT_SIENR_SETENRL1_Pos 1 /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */\r
-#define GPIO_PIN_INT_SIENR_SETENRL1_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask */\r
-#define GPIO_PIN_INT_SIENR_SETENRL2_Pos 2 /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */\r
-#define GPIO_PIN_INT_SIENR_SETENRL2_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask */\r
-#define GPIO_PIN_INT_SIENR_SETENRL3_Pos 3 /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */\r
-#define GPIO_PIN_INT_SIENR_SETENRL3_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask */\r
-#define GPIO_PIN_INT_SIENR_SETENRL4_Pos 4 /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */\r
-#define GPIO_PIN_INT_SIENR_SETENRL4_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask */\r
-#define GPIO_PIN_INT_SIENR_SETENRL5_Pos 5 /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */\r
-#define GPIO_PIN_INT_SIENR_SETENRL5_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask */\r
-#define GPIO_PIN_INT_SIENR_SETENRL6_Pos 6 /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */\r
-#define GPIO_PIN_INT_SIENR_SETENRL6_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask */\r
-#define GPIO_PIN_INT_SIENR_SETENRL7_Pos 7 /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */\r
-#define GPIO_PIN_INT_SIENR_SETENRL7_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask */\r
-\r
-// ----------------------------------- GPIO_PIN_INT_CIENR ---------------------------------------\r
-#define GPIO_PIN_INT_CIENR_CENRL0_Pos 0 /*!< GPIO_PIN_INT CIENR: CENRL0 Position */\r
-#define GPIO_PIN_INT_CIENR_CENRL0_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos) /*!< GPIO_PIN_INT CIENR: CENRL0 Mask */\r
-#define GPIO_PIN_INT_CIENR_CENRL1_Pos 1 /*!< GPIO_PIN_INT CIENR: CENRL1 Position */\r
-#define GPIO_PIN_INT_CIENR_CENRL1_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos) /*!< GPIO_PIN_INT CIENR: CENRL1 Mask */\r
-#define GPIO_PIN_INT_CIENR_CENRL2_Pos 2 /*!< GPIO_PIN_INT CIENR: CENRL2 Position */\r
-#define GPIO_PIN_INT_CIENR_CENRL2_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos) /*!< GPIO_PIN_INT CIENR: CENRL2 Mask */\r
-#define GPIO_PIN_INT_CIENR_CENRL3_Pos 3 /*!< GPIO_PIN_INT CIENR: CENRL3 Position */\r
-#define GPIO_PIN_INT_CIENR_CENRL3_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos) /*!< GPIO_PIN_INT CIENR: CENRL3 Mask */\r
-#define GPIO_PIN_INT_CIENR_CENRL4_Pos 4 /*!< GPIO_PIN_INT CIENR: CENRL4 Position */\r
-#define GPIO_PIN_INT_CIENR_CENRL4_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos) /*!< GPIO_PIN_INT CIENR: CENRL4 Mask */\r
-#define GPIO_PIN_INT_CIENR_CENRL5_Pos 5 /*!< GPIO_PIN_INT CIENR: CENRL5 Position */\r
-#define GPIO_PIN_INT_CIENR_CENRL5_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos) /*!< GPIO_PIN_INT CIENR: CENRL5 Mask */\r
-#define GPIO_PIN_INT_CIENR_CENRL6_Pos 6 /*!< GPIO_PIN_INT CIENR: CENRL6 Position */\r
-#define GPIO_PIN_INT_CIENR_CENRL6_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos) /*!< GPIO_PIN_INT CIENR: CENRL6 Mask */\r
-#define GPIO_PIN_INT_CIENR_CENRL7_Pos 7 /*!< GPIO_PIN_INT CIENR: CENRL7 Position */\r
-#define GPIO_PIN_INT_CIENR_CENRL7_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos) /*!< GPIO_PIN_INT CIENR: CENRL7 Mask */\r
-\r
-// ------------------------------------ GPIO_PIN_INT_IENF ---------------------------------------\r
-#define GPIO_PIN_INT_IENF_ENAF0_Pos 0 /*!< GPIO_PIN_INT IENF: ENAF0 Position */\r
-#define GPIO_PIN_INT_IENF_ENAF0_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos) /*!< GPIO_PIN_INT IENF: ENAF0 Mask */\r
-#define GPIO_PIN_INT_IENF_ENAF1_Pos 1 /*!< GPIO_PIN_INT IENF: ENAF1 Position */\r
-#define GPIO_PIN_INT_IENF_ENAF1_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos) /*!< GPIO_PIN_INT IENF: ENAF1 Mask */\r
-#define GPIO_PIN_INT_IENF_ENAF2_Pos 2 /*!< GPIO_PIN_INT IENF: ENAF2 Position */\r
-#define GPIO_PIN_INT_IENF_ENAF2_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos) /*!< GPIO_PIN_INT IENF: ENAF2 Mask */\r
-#define GPIO_PIN_INT_IENF_ENAF3_Pos 3 /*!< GPIO_PIN_INT IENF: ENAF3 Position */\r
-#define GPIO_PIN_INT_IENF_ENAF3_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos) /*!< GPIO_PIN_INT IENF: ENAF3 Mask */\r
-#define GPIO_PIN_INT_IENF_ENAF4_Pos 4 /*!< GPIO_PIN_INT IENF: ENAF4 Position */\r
-#define GPIO_PIN_INT_IENF_ENAF4_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos) /*!< GPIO_PIN_INT IENF: ENAF4 Mask */\r
-#define GPIO_PIN_INT_IENF_ENAF5_Pos 5 /*!< GPIO_PIN_INT IENF: ENAF5 Position */\r
-#define GPIO_PIN_INT_IENF_ENAF5_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos) /*!< GPIO_PIN_INT IENF: ENAF5 Mask */\r
-#define GPIO_PIN_INT_IENF_ENAF6_Pos 6 /*!< GPIO_PIN_INT IENF: ENAF6 Position */\r
-#define GPIO_PIN_INT_IENF_ENAF6_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos) /*!< GPIO_PIN_INT IENF: ENAF6 Mask */\r
-#define GPIO_PIN_INT_IENF_ENAF7_Pos 7 /*!< GPIO_PIN_INT IENF: ENAF7 Position */\r
-#define GPIO_PIN_INT_IENF_ENAF7_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos) /*!< GPIO_PIN_INT IENF: ENAF7 Mask */\r
-\r
-// ----------------------------------- GPIO_PIN_INT_SIENF ---------------------------------------\r
-#define GPIO_PIN_INT_SIENF_SETENAF0_Pos 0 /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */\r
-#define GPIO_PIN_INT_SIENF_SETENAF0_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask */\r
-#define GPIO_PIN_INT_SIENF_SETENAF1_Pos 1 /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */\r
-#define GPIO_PIN_INT_SIENF_SETENAF1_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask */\r
-#define GPIO_PIN_INT_SIENF_SETENAF2_Pos 2 /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */\r
-#define GPIO_PIN_INT_SIENF_SETENAF2_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask */\r
-#define GPIO_PIN_INT_SIENF_SETENAF3_Pos 3 /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */\r
-#define GPIO_PIN_INT_SIENF_SETENAF3_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask */\r
-#define GPIO_PIN_INT_SIENF_SETENAF4_Pos 4 /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */\r
-#define GPIO_PIN_INT_SIENF_SETENAF4_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask */\r
-#define GPIO_PIN_INT_SIENF_SETENAF5_Pos 5 /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */\r
-#define GPIO_PIN_INT_SIENF_SETENAF5_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask */\r
-#define GPIO_PIN_INT_SIENF_SETENAF6_Pos 6 /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */\r
-#define GPIO_PIN_INT_SIENF_SETENAF6_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask */\r
-#define GPIO_PIN_INT_SIENF_SETENAF7_Pos 7 /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */\r
-#define GPIO_PIN_INT_SIENF_SETENAF7_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask */\r
-\r
-// ----------------------------------- GPIO_PIN_INT_CIENF ---------------------------------------\r
-#define GPIO_PIN_INT_CIENF_CENAF0_Pos 0 /*!< GPIO_PIN_INT CIENF: CENAF0 Position */\r
-#define GPIO_PIN_INT_CIENF_CENAF0_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos) /*!< GPIO_PIN_INT CIENF: CENAF0 Mask */\r
-#define GPIO_PIN_INT_CIENF_CENAF1_Pos 1 /*!< GPIO_PIN_INT CIENF: CENAF1 Position */\r
-#define GPIO_PIN_INT_CIENF_CENAF1_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos) /*!< GPIO_PIN_INT CIENF: CENAF1 Mask */\r
-#define GPIO_PIN_INT_CIENF_CENAF2_Pos 2 /*!< GPIO_PIN_INT CIENF: CENAF2 Position */\r
-#define GPIO_PIN_INT_CIENF_CENAF2_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos) /*!< GPIO_PIN_INT CIENF: CENAF2 Mask */\r
-#define GPIO_PIN_INT_CIENF_CENAF3_Pos 3 /*!< GPIO_PIN_INT CIENF: CENAF3 Position */\r
-#define GPIO_PIN_INT_CIENF_CENAF3_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos) /*!< GPIO_PIN_INT CIENF: CENAF3 Mask */\r
-#define GPIO_PIN_INT_CIENF_CENAF4_Pos 4 /*!< GPIO_PIN_INT CIENF: CENAF4 Position */\r
-#define GPIO_PIN_INT_CIENF_CENAF4_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos) /*!< GPIO_PIN_INT CIENF: CENAF4 Mask */\r
-#define GPIO_PIN_INT_CIENF_CENAF5_Pos 5 /*!< GPIO_PIN_INT CIENF: CENAF5 Position */\r
-#define GPIO_PIN_INT_CIENF_CENAF5_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos) /*!< GPIO_PIN_INT CIENF: CENAF5 Mask */\r
-#define GPIO_PIN_INT_CIENF_CENAF6_Pos 6 /*!< GPIO_PIN_INT CIENF: CENAF6 Position */\r
-#define GPIO_PIN_INT_CIENF_CENAF6_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos) /*!< GPIO_PIN_INT CIENF: CENAF6 Mask */\r
-#define GPIO_PIN_INT_CIENF_CENAF7_Pos 7 /*!< GPIO_PIN_INT CIENF: CENAF7 Position */\r
-#define GPIO_PIN_INT_CIENF_CENAF7_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos) /*!< GPIO_PIN_INT CIENF: CENAF7 Mask */\r
-\r
-// ------------------------------------ GPIO_PIN_INT_RISE ---------------------------------------\r
-#define GPIO_PIN_INT_RISE_RDET0_Pos 0 /*!< GPIO_PIN_INT RISE: RDET0 Position */\r
-#define GPIO_PIN_INT_RISE_RDET0_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos) /*!< GPIO_PIN_INT RISE: RDET0 Mask */\r
-#define GPIO_PIN_INT_RISE_RDET1_Pos 1 /*!< GPIO_PIN_INT RISE: RDET1 Position */\r
-#define GPIO_PIN_INT_RISE_RDET1_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos) /*!< GPIO_PIN_INT RISE: RDET1 Mask */\r
-#define GPIO_PIN_INT_RISE_RDET2_Pos 2 /*!< GPIO_PIN_INT RISE: RDET2 Position */\r
-#define GPIO_PIN_INT_RISE_RDET2_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos) /*!< GPIO_PIN_INT RISE: RDET2 Mask */\r
-#define GPIO_PIN_INT_RISE_RDET3_Pos 3 /*!< GPIO_PIN_INT RISE: RDET3 Position */\r
-#define GPIO_PIN_INT_RISE_RDET3_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos) /*!< GPIO_PIN_INT RISE: RDET3 Mask */\r
-#define GPIO_PIN_INT_RISE_RDET4_Pos 4 /*!< GPIO_PIN_INT RISE: RDET4 Position */\r
-#define GPIO_PIN_INT_RISE_RDET4_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos) /*!< GPIO_PIN_INT RISE: RDET4 Mask */\r
-#define GPIO_PIN_INT_RISE_RDET5_Pos 5 /*!< GPIO_PIN_INT RISE: RDET5 Position */\r
-#define GPIO_PIN_INT_RISE_RDET5_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos) /*!< GPIO_PIN_INT RISE: RDET5 Mask */\r
-#define GPIO_PIN_INT_RISE_RDET6_Pos 6 /*!< GPIO_PIN_INT RISE: RDET6 Position */\r
-#define GPIO_PIN_INT_RISE_RDET6_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos) /*!< GPIO_PIN_INT RISE: RDET6 Mask */\r
-#define GPIO_PIN_INT_RISE_RDET7_Pos 7 /*!< GPIO_PIN_INT RISE: RDET7 Position */\r
-#define GPIO_PIN_INT_RISE_RDET7_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos) /*!< GPIO_PIN_INT RISE: RDET7 Mask */\r
-\r
-// ------------------------------------ GPIO_PIN_INT_FALL ---------------------------------------\r
-#define GPIO_PIN_INT_FALL_FDET0_Pos 0 /*!< GPIO_PIN_INT FALL: FDET0 Position */\r
-#define GPIO_PIN_INT_FALL_FDET0_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos) /*!< GPIO_PIN_INT FALL: FDET0 Mask */\r
-#define GPIO_PIN_INT_FALL_FDET1_Pos 1 /*!< GPIO_PIN_INT FALL: FDET1 Position */\r
-#define GPIO_PIN_INT_FALL_FDET1_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos) /*!< GPIO_PIN_INT FALL: FDET1 Mask */\r
-#define GPIO_PIN_INT_FALL_FDET2_Pos 2 /*!< GPIO_PIN_INT FALL: FDET2 Position */\r
-#define GPIO_PIN_INT_FALL_FDET2_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos) /*!< GPIO_PIN_INT FALL: FDET2 Mask */\r
-#define GPIO_PIN_INT_FALL_FDET3_Pos 3 /*!< GPIO_PIN_INT FALL: FDET3 Position */\r
-#define GPIO_PIN_INT_FALL_FDET3_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos) /*!< GPIO_PIN_INT FALL: FDET3 Mask */\r
-#define GPIO_PIN_INT_FALL_FDET4_Pos 4 /*!< GPIO_PIN_INT FALL: FDET4 Position */\r
-#define GPIO_PIN_INT_FALL_FDET4_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos) /*!< GPIO_PIN_INT FALL: FDET4 Mask */\r
-#define GPIO_PIN_INT_FALL_FDET5_Pos 5 /*!< GPIO_PIN_INT FALL: FDET5 Position */\r
-#define GPIO_PIN_INT_FALL_FDET5_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos) /*!< GPIO_PIN_INT FALL: FDET5 Mask */\r
-#define GPIO_PIN_INT_FALL_FDET6_Pos 6 /*!< GPIO_PIN_INT FALL: FDET6 Position */\r
-#define GPIO_PIN_INT_FALL_FDET6_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos) /*!< GPIO_PIN_INT FALL: FDET6 Mask */\r
-#define GPIO_PIN_INT_FALL_FDET7_Pos 7 /*!< GPIO_PIN_INT FALL: FDET7 Position */\r
-#define GPIO_PIN_INT_FALL_FDET7_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos) /*!< GPIO_PIN_INT FALL: FDET7 Mask */\r
-\r
-// ------------------------------------ GPIO_PIN_INT_IST ----------------------------------------\r
-#define GPIO_PIN_INT_IST_PSTAT0_Pos 0 /*!< GPIO_PIN_INT IST: PSTAT0 Position */\r
-#define GPIO_PIN_INT_IST_PSTAT0_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos) /*!< GPIO_PIN_INT IST: PSTAT0 Mask */\r
-#define GPIO_PIN_INT_IST_PSTAT1_Pos 1 /*!< GPIO_PIN_INT IST: PSTAT1 Position */\r
-#define GPIO_PIN_INT_IST_PSTAT1_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos) /*!< GPIO_PIN_INT IST: PSTAT1 Mask */\r
-#define GPIO_PIN_INT_IST_PSTAT2_Pos 2 /*!< GPIO_PIN_INT IST: PSTAT2 Position */\r
-#define GPIO_PIN_INT_IST_PSTAT2_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos) /*!< GPIO_PIN_INT IST: PSTAT2 Mask */\r
-#define GPIO_PIN_INT_IST_PSTAT3_Pos 3 /*!< GPIO_PIN_INT IST: PSTAT3 Position */\r
-#define GPIO_PIN_INT_IST_PSTAT3_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos) /*!< GPIO_PIN_INT IST: PSTAT3 Mask */\r
-#define GPIO_PIN_INT_IST_PSTAT4_Pos 4 /*!< GPIO_PIN_INT IST: PSTAT4 Position */\r
-#define GPIO_PIN_INT_IST_PSTAT4_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos) /*!< GPIO_PIN_INT IST: PSTAT4 Mask */\r
-#define GPIO_PIN_INT_IST_PSTAT5_Pos 5 /*!< GPIO_PIN_INT IST: PSTAT5 Position */\r
-#define GPIO_PIN_INT_IST_PSTAT5_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos) /*!< GPIO_PIN_INT IST: PSTAT5 Mask */\r
-#define GPIO_PIN_INT_IST_PSTAT6_Pos 6 /*!< GPIO_PIN_INT IST: PSTAT6 Position */\r
-#define GPIO_PIN_INT_IST_PSTAT6_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos) /*!< GPIO_PIN_INT IST: PSTAT6 Mask */\r
-#define GPIO_PIN_INT_IST_PSTAT7_Pos 7 /*!< GPIO_PIN_INT IST: PSTAT7 Position */\r
-#define GPIO_PIN_INT_IST_PSTAT7_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos) /*!< GPIO_PIN_INT IST: PSTAT7 Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GPIO_GROUP_INTn Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------- GPIO_GROUP_INTn_CTRL --------------------------------------\r
-#define GPIO_GROUP_INTn_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INTn CTRL: INT Position */\r
-#define GPIO_GROUP_INTn_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos) /*!< GPIO_GROUP_INTn CTRL: INT Mask */\r
-#define GPIO_GROUP_INTn_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INTn CTRL: COMB Position */\r
-#define GPIO_GROUP_INTn_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos) /*!< GPIO_GROUP_INTn CTRL: COMB Mask */\r
-#define GPIO_GROUP_INTn_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INTn CTRL: TRIG Position */\r
-#define GPIO_GROUP_INTn_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INTn CTRL: TRIG Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_POL0 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_POL1 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_POL2 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_POL3 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_POL4 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_POL5 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_POL6 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_POL7 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_ENA0 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_ENA1 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_ENA2 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_ENA3 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_ENA4 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_ENA5 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_ENA6 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INTn_PORT_ENA7 -----------------------------------\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */\r
-#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GPIO_GROUP_INT1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------- GPIO_GROUP_INT1_CTRL --------------------------------------\r
-#define GPIO_GROUP_INT1_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INT1 CTRL: INT Position */\r
-#define GPIO_GROUP_INT1_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos) /*!< GPIO_GROUP_INT1 CTRL: INT Mask */\r
-#define GPIO_GROUP_INT1_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INT1 CTRL: COMB Position */\r
-#define GPIO_GROUP_INT1_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos) /*!< GPIO_GROUP_INT1 CTRL: COMB Mask */\r
-#define GPIO_GROUP_INT1_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */\r
-#define GPIO_GROUP_INT1_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_POL0 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_POL1 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_POL2 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_POL3 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_POL4 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_POL5 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_POL6 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_POL7 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_ENA0 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_ENA1 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_ENA2 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_ENA3 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_ENA4 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_ENA5 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_ENA6 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */\r
-\r
-// -------------------------------- GPIO_GROUP_INT1_PORT_ENA7 -----------------------------------\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */\r
-#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- MCPWM Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- MCPWM_CON -------------------------------------------\r
-#define MCPWM_CON_RUN0_Pos 0 /*!< MCPWM CON: RUN0 Position */\r
-#define MCPWM_CON_RUN0_Msk (0x01UL << MCPWM_CON_RUN0_Pos) /*!< MCPWM CON: RUN0 Mask */\r
-#define MCPWM_CON_CENTER0_Pos 1 /*!< MCPWM CON: CENTER0 Position */\r
-#define MCPWM_CON_CENTER0_Msk (0x01UL << MCPWM_CON_CENTER0_Pos) /*!< MCPWM CON: CENTER0 Mask */\r
-#define MCPWM_CON_POLA0_Pos 2 /*!< MCPWM CON: POLA0 Position */\r
-#define MCPWM_CON_POLA0_Msk (0x01UL << MCPWM_CON_POLA0_Pos) /*!< MCPWM CON: POLA0 Mask */\r
-#define MCPWM_CON_DTE0_Pos 3 /*!< MCPWM CON: DTE0 Position */\r
-#define MCPWM_CON_DTE0_Msk (0x01UL << MCPWM_CON_DTE0_Pos) /*!< MCPWM CON: DTE0 Mask */\r
-#define MCPWM_CON_DISUP0_Pos 4 /*!< MCPWM CON: DISUP0 Position */\r
-#define MCPWM_CON_DISUP0_Msk (0x01UL << MCPWM_CON_DISUP0_Pos) /*!< MCPWM CON: DISUP0 Mask */\r
-#define MCPWM_CON_RUN1_Pos 8 /*!< MCPWM CON: RUN1 Position */\r
-#define MCPWM_CON_RUN1_Msk (0x01UL << MCPWM_CON_RUN1_Pos) /*!< MCPWM CON: RUN1 Mask */\r
-#define MCPWM_CON_CENTER1_Pos 9 /*!< MCPWM CON: CENTER1 Position */\r
-#define MCPWM_CON_CENTER1_Msk (0x01UL << MCPWM_CON_CENTER1_Pos) /*!< MCPWM CON: CENTER1 Mask */\r
-#define MCPWM_CON_POLA1_Pos 10 /*!< MCPWM CON: POLA1 Position */\r
-#define MCPWM_CON_POLA1_Msk (0x01UL << MCPWM_CON_POLA1_Pos) /*!< MCPWM CON: POLA1 Mask */\r
-#define MCPWM_CON_DTE1_Pos 11 /*!< MCPWM CON: DTE1 Position */\r
-#define MCPWM_CON_DTE1_Msk (0x01UL << MCPWM_CON_DTE1_Pos) /*!< MCPWM CON: DTE1 Mask */\r
-#define MCPWM_CON_DISUP1_Pos 12 /*!< MCPWM CON: DISUP1 Position */\r
-#define MCPWM_CON_DISUP1_Msk (0x01UL << MCPWM_CON_DISUP1_Pos) /*!< MCPWM CON: DISUP1 Mask */\r
-#define MCPWM_CON_RUN2_Pos 16 /*!< MCPWM CON: RUN2 Position */\r
-#define MCPWM_CON_RUN2_Msk (0x01UL << MCPWM_CON_RUN2_Pos) /*!< MCPWM CON: RUN2 Mask */\r
-#define MCPWM_CON_CENTER2_Pos 17 /*!< MCPWM CON: CENTER2 Position */\r
-#define MCPWM_CON_CENTER2_Msk (0x01UL << MCPWM_CON_CENTER2_Pos) /*!< MCPWM CON: CENTER2 Mask */\r
-#define MCPWM_CON_POLA2_Pos 18 /*!< MCPWM CON: POLA2 Position */\r
-#define MCPWM_CON_POLA2_Msk (0x01UL << MCPWM_CON_POLA2_Pos) /*!< MCPWM CON: POLA2 Mask */\r
-#define MCPWM_CON_DTE2_Pos 19 /*!< MCPWM CON: DTE2 Position */\r
-#define MCPWM_CON_DTE2_Msk (0x01UL << MCPWM_CON_DTE2_Pos) /*!< MCPWM CON: DTE2 Mask */\r
-#define MCPWM_CON_DISUP2_Pos 20 /*!< MCPWM CON: DISUP2 Position */\r
-#define MCPWM_CON_DISUP2_Msk (0x01UL << MCPWM_CON_DISUP2_Pos) /*!< MCPWM CON: DISUP2 Mask */\r
-#define MCPWM_CON_INVBDC_Pos 29 /*!< MCPWM CON: INVBDC Position */\r
-#define MCPWM_CON_INVBDC_Msk (0x01UL << MCPWM_CON_INVBDC_Pos) /*!< MCPWM CON: INVBDC Mask */\r
-#define MCPWM_CON_ACMODE_Pos 30 /*!< MCPWM CON: ACMODE Position */\r
-#define MCPWM_CON_ACMODE_Msk (0x01UL << MCPWM_CON_ACMODE_Pos) /*!< MCPWM CON: ACMODE Mask */\r
-#define MCPWM_CON_DCMODE_Pos 31 /*!< MCPWM CON: DCMODE Position */\r
-#define MCPWM_CON_DCMODE_Msk (0x01UL << MCPWM_CON_DCMODE_Pos) /*!< MCPWM CON: DCMODE Mask */\r
-\r
-// -------------------------------------- MCPWM_CON_SET -----------------------------------------\r
-#define MCPWM_CON_SET_RUN0_SET_Pos 0 /*!< MCPWM CON_SET: RUN0_SET Position */\r
-#define MCPWM_CON_SET_RUN0_SET_Msk (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos) /*!< MCPWM CON_SET: RUN0_SET Mask */\r
-#define MCPWM_CON_SET_CENTER0_SET_Pos 1 /*!< MCPWM CON_SET: CENTER0_SET Position */\r
-#define MCPWM_CON_SET_CENTER0_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos) /*!< MCPWM CON_SET: CENTER0_SET Mask */\r
-#define MCPWM_CON_SET_POLA0_SET_Pos 2 /*!< MCPWM CON_SET: POLA0_SET Position */\r
-#define MCPWM_CON_SET_POLA0_SET_Msk (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos) /*!< MCPWM CON_SET: POLA0_SET Mask */\r
-#define MCPWM_CON_SET_DTE0_SET_Pos 3 /*!< MCPWM CON_SET: DTE0_SET Position */\r
-#define MCPWM_CON_SET_DTE0_SET_Msk (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos) /*!< MCPWM CON_SET: DTE0_SET Mask */\r
-#define MCPWM_CON_SET_DISUP0_SET_Pos 4 /*!< MCPWM CON_SET: DISUP0_SET Position */\r
-#define MCPWM_CON_SET_DISUP0_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos) /*!< MCPWM CON_SET: DISUP0_SET Mask */\r
-#define MCPWM_CON_SET_RUN1_SET_Pos 8 /*!< MCPWM CON_SET: RUN1_SET Position */\r
-#define MCPWM_CON_SET_RUN1_SET_Msk (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos) /*!< MCPWM CON_SET: RUN1_SET Mask */\r
-#define MCPWM_CON_SET_CENTER1_SET_Pos 9 /*!< MCPWM CON_SET: CENTER1_SET Position */\r
-#define MCPWM_CON_SET_CENTER1_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos) /*!< MCPWM CON_SET: CENTER1_SET Mask */\r
-#define MCPWM_CON_SET_POLA1_SET_Pos 10 /*!< MCPWM CON_SET: POLA1_SET Position */\r
-#define MCPWM_CON_SET_POLA1_SET_Msk (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos) /*!< MCPWM CON_SET: POLA1_SET Mask */\r
-#define MCPWM_CON_SET_DTE1_SET_Pos 11 /*!< MCPWM CON_SET: DTE1_SET Position */\r
-#define MCPWM_CON_SET_DTE1_SET_Msk (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos) /*!< MCPWM CON_SET: DTE1_SET Mask */\r
-#define MCPWM_CON_SET_DISUP1_SET_Pos 12 /*!< MCPWM CON_SET: DISUP1_SET Position */\r
-#define MCPWM_CON_SET_DISUP1_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos) /*!< MCPWM CON_SET: DISUP1_SET Mask */\r
-#define MCPWM_CON_SET_RUN2_SET_Pos 16 /*!< MCPWM CON_SET: RUN2_SET Position */\r
-#define MCPWM_CON_SET_RUN2_SET_Msk (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos) /*!< MCPWM CON_SET: RUN2_SET Mask */\r
-#define MCPWM_CON_SET_CENTER2_SET_Pos 17 /*!< MCPWM CON_SET: CENTER2_SET Position */\r
-#define MCPWM_CON_SET_CENTER2_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos) /*!< MCPWM CON_SET: CENTER2_SET Mask */\r
-#define MCPWM_CON_SET_POLA2_SET_Pos 18 /*!< MCPWM CON_SET: POLA2_SET Position */\r
-#define MCPWM_CON_SET_POLA2_SET_Msk (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos) /*!< MCPWM CON_SET: POLA2_SET Mask */\r
-#define MCPWM_CON_SET_DTE2_SET_Pos 19 /*!< MCPWM CON_SET: DTE2_SET Position */\r
-#define MCPWM_CON_SET_DTE2_SET_Msk (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos) /*!< MCPWM CON_SET: DTE2_SET Mask */\r
-#define MCPWM_CON_SET_DISUP2_SET_Pos 20 /*!< MCPWM CON_SET: DISUP2_SET Position */\r
-#define MCPWM_CON_SET_DISUP2_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos) /*!< MCPWM CON_SET: DISUP2_SET Mask */\r
-#define MCPWM_CON_SET_INVBDC_SET_Pos 29 /*!< MCPWM CON_SET: INVBDC_SET Position */\r
-#define MCPWM_CON_SET_INVBDC_SET_Msk (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos) /*!< MCPWM CON_SET: INVBDC_SET Mask */\r
-#define MCPWM_CON_SET_ACMODE_SET_Pos 30 /*!< MCPWM CON_SET: ACMODE_SET Position */\r
-#define MCPWM_CON_SET_ACMODE_SET_Msk (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos) /*!< MCPWM CON_SET: ACMODE_SET Mask */\r
-#define MCPWM_CON_SET_DCMODE_SET_Pos 31 /*!< MCPWM CON_SET: DCMODE_SET Position */\r
-#define MCPWM_CON_SET_DCMODE_SET_Msk (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos) /*!< MCPWM CON_SET: DCMODE_SET Mask */\r
-\r
-// -------------------------------------- MCPWM_CON_CLR -----------------------------------------\r
-#define MCPWM_CON_CLR_RUN0_CLR_Pos 0 /*!< MCPWM CON_CLR: RUN0_CLR Position */\r
-#define MCPWM_CON_CLR_RUN0_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos) /*!< MCPWM CON_CLR: RUN0_CLR Mask */\r
-#define MCPWM_CON_CLR_CENTER0_CLR_Pos 1 /*!< MCPWM CON_CLR: CENTER0_CLR Position */\r
-#define MCPWM_CON_CLR_CENTER0_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos) /*!< MCPWM CON_CLR: CENTER0_CLR Mask */\r
-#define MCPWM_CON_CLR_POLA0_CLR_Pos 2 /*!< MCPWM CON_CLR: POLA0_CLR Position */\r
-#define MCPWM_CON_CLR_POLA0_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos) /*!< MCPWM CON_CLR: POLA0_CLR Mask */\r
-#define MCPWM_CON_CLR_DTE0_CLR_Pos 3 /*!< MCPWM CON_CLR: DTE0_CLR Position */\r
-#define MCPWM_CON_CLR_DTE0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos) /*!< MCPWM CON_CLR: DTE0_CLR Mask */\r
-#define MCPWM_CON_CLR_DISUP0_CLR_Pos 4 /*!< MCPWM CON_CLR: DISUP0_CLR Position */\r
-#define MCPWM_CON_CLR_DISUP0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos) /*!< MCPWM CON_CLR: DISUP0_CLR Mask */\r
-#define MCPWM_CON_CLR_RUN1_CLR_Pos 8 /*!< MCPWM CON_CLR: RUN1_CLR Position */\r
-#define MCPWM_CON_CLR_RUN1_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos) /*!< MCPWM CON_CLR: RUN1_CLR Mask */\r
-#define MCPWM_CON_CLR_CENTER1_CLR_Pos 9 /*!< MCPWM CON_CLR: CENTER1_CLR Position */\r
-#define MCPWM_CON_CLR_CENTER1_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos) /*!< MCPWM CON_CLR: CENTER1_CLR Mask */\r
-#define MCPWM_CON_CLR_POLA1_CLR_Pos 10 /*!< MCPWM CON_CLR: POLA1_CLR Position */\r
-#define MCPWM_CON_CLR_POLA1_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos) /*!< MCPWM CON_CLR: POLA1_CLR Mask */\r
-#define MCPWM_CON_CLR_DTE1_CLR_Pos 11 /*!< MCPWM CON_CLR: DTE1_CLR Position */\r
-#define MCPWM_CON_CLR_DTE1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos) /*!< MCPWM CON_CLR: DTE1_CLR Mask */\r
-#define MCPWM_CON_CLR_DISUP1_CLR_Pos 12 /*!< MCPWM CON_CLR: DISUP1_CLR Position */\r
-#define MCPWM_CON_CLR_DISUP1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos) /*!< MCPWM CON_CLR: DISUP1_CLR Mask */\r
-#define MCPWM_CON_CLR_RUN2_CLR_Pos 16 /*!< MCPWM CON_CLR: RUN2_CLR Position */\r
-#define MCPWM_CON_CLR_RUN2_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos) /*!< MCPWM CON_CLR: RUN2_CLR Mask */\r
-#define MCPWM_CON_CLR_CENTER2_CLR_Pos 17 /*!< MCPWM CON_CLR: CENTER2_CLR Position */\r
-#define MCPWM_CON_CLR_CENTER2_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos) /*!< MCPWM CON_CLR: CENTER2_CLR Mask */\r
-#define MCPWM_CON_CLR_POLA2_CLR_Pos 18 /*!< MCPWM CON_CLR: POLA2_CLR Position */\r
-#define MCPWM_CON_CLR_POLA2_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos) /*!< MCPWM CON_CLR: POLA2_CLR Mask */\r
-#define MCPWM_CON_CLR_DTE2_CLR_Pos 19 /*!< MCPWM CON_CLR: DTE2_CLR Position */\r
-#define MCPWM_CON_CLR_DTE2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos) /*!< MCPWM CON_CLR: DTE2_CLR Mask */\r
-#define MCPWM_CON_CLR_DISUP2_CLR_Pos 20 /*!< MCPWM CON_CLR: DISUP2_CLR Position */\r
-#define MCPWM_CON_CLR_DISUP2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos) /*!< MCPWM CON_CLR: DISUP2_CLR Mask */\r
-#define MCPWM_CON_CLR_INVBDC_CLR_Pos 29 /*!< MCPWM CON_CLR: INVBDC_CLR Position */\r
-#define MCPWM_CON_CLR_INVBDC_CLR_Msk (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos) /*!< MCPWM CON_CLR: INVBDC_CLR Mask */\r
-#define MCPWM_CON_CLR_ACMOD_CLR_Pos 30 /*!< MCPWM CON_CLR: ACMOD_CLR Position */\r
-#define MCPWM_CON_CLR_ACMOD_CLR_Msk (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos) /*!< MCPWM CON_CLR: ACMOD_CLR Mask */\r
-#define MCPWM_CON_CLR_DCMODE_CLR_Pos 31 /*!< MCPWM CON_CLR: DCMODE_CLR Position */\r
-#define MCPWM_CON_CLR_DCMODE_CLR_Msk (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos) /*!< MCPWM CON_CLR: DCMODE_CLR Mask */\r
-\r
-// -------------------------------------- MCPWM_CAPCON ------------------------------------------\r
-#define MCPWM_CAPCON_CAP0MCI0_RE_Pos 0 /*!< MCPWM CAPCON: CAP0MCI0_RE Position */\r
-#define MCPWM_CAPCON_CAP0MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_RE Mask */\r
-#define MCPWM_CAPCON_CAP0MCI0_FE_Pos 1 /*!< MCPWM CAPCON: CAP0MCI0_FE Position */\r
-#define MCPWM_CAPCON_CAP0MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_FE Mask */\r
-#define MCPWM_CAPCON_CAP0MCI1_RE_Pos 2 /*!< MCPWM CAPCON: CAP0MCI1_RE Position */\r
-#define MCPWM_CAPCON_CAP0MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_RE Mask */\r
-#define MCPWM_CAPCON_CAP0MCI1_FE_Pos 3 /*!< MCPWM CAPCON: CAP0MCI1_FE Position */\r
-#define MCPWM_CAPCON_CAP0MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_FE Mask */\r
-#define MCPWM_CAPCON_CAP0MCI2_RE_Pos 4 /*!< MCPWM CAPCON: CAP0MCI2_RE Position */\r
-#define MCPWM_CAPCON_CAP0MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_RE Mask */\r
-#define MCPWM_CAPCON_CAP0MCI2_FE_Pos 5 /*!< MCPWM CAPCON: CAP0MCI2_FE Position */\r
-#define MCPWM_CAPCON_CAP0MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_FE Mask */\r
-#define MCPWM_CAPCON_CAP1MCI0_RE_Pos 6 /*!< MCPWM CAPCON: CAP1MCI0_RE Position */\r
-#define MCPWM_CAPCON_CAP1MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_RE Mask */\r
-#define MCPWM_CAPCON_CAP1MCI0_FE_Pos 7 /*!< MCPWM CAPCON: CAP1MCI0_FE Position */\r
-#define MCPWM_CAPCON_CAP1MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_FE Mask */\r
-#define MCPWM_CAPCON_CAP1MCI1_RE_Pos 8 /*!< MCPWM CAPCON: CAP1MCI1_RE Position */\r
-#define MCPWM_CAPCON_CAP1MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_RE Mask */\r
-#define MCPWM_CAPCON_CAP1MCI1_FE_Pos 9 /*!< MCPWM CAPCON: CAP1MCI1_FE Position */\r
-#define MCPWM_CAPCON_CAP1MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_FE Mask */\r
-#define MCPWM_CAPCON_CAP1MCI2_RE_Pos 10 /*!< MCPWM CAPCON: CAP1MCI2_RE Position */\r
-#define MCPWM_CAPCON_CAP1MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_RE Mask */\r
-#define MCPWM_CAPCON_CAP1MCI2_FE_Pos 11 /*!< MCPWM CAPCON: CAP1MCI2_FE Position */\r
-#define MCPWM_CAPCON_CAP1MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_FE Mask */\r
-#define MCPWM_CAPCON_CAP2MCI0_RE_Pos 12 /*!< MCPWM CAPCON: CAP2MCI0_RE Position */\r
-#define MCPWM_CAPCON_CAP2MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_RE Mask */\r
-#define MCPWM_CAPCON_CAP2MCI0_FE_Pos 13 /*!< MCPWM CAPCON: CAP2MCI0_FE Position */\r
-#define MCPWM_CAPCON_CAP2MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_FE Mask */\r
-#define MCPWM_CAPCON_CAP2MCI1_RE_Pos 14 /*!< MCPWM CAPCON: CAP2MCI1_RE Position */\r
-#define MCPWM_CAPCON_CAP2MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_RE Mask */\r
-#define MCPWM_CAPCON_CAP2MCI1_FE_Pos 15 /*!< MCPWM CAPCON: CAP2MCI1_FE Position */\r
-#define MCPWM_CAPCON_CAP2MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_FE Mask */\r
-#define MCPWM_CAPCON_CAP2MCI2_RE_Pos 16 /*!< MCPWM CAPCON: CAP2MCI2_RE Position */\r
-#define MCPWM_CAPCON_CAP2MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_RE Mask */\r
-#define MCPWM_CAPCON_CAP2MCI2_FE_Pos 17 /*!< MCPWM CAPCON: CAP2MCI2_FE Position */\r
-#define MCPWM_CAPCON_CAP2MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_FE Mask */\r
-#define MCPWM_CAPCON_RT0_Pos 18 /*!< MCPWM CAPCON: RT0 Position */\r
-#define MCPWM_CAPCON_RT0_Msk (0x01UL << MCPWM_CAPCON_RT0_Pos) /*!< MCPWM CAPCON: RT0 Mask */\r
-#define MCPWM_CAPCON_RT1_Pos 19 /*!< MCPWM CAPCON: RT1 Position */\r
-#define MCPWM_CAPCON_RT1_Msk (0x01UL << MCPWM_CAPCON_RT1_Pos) /*!< MCPWM CAPCON: RT1 Mask */\r
-#define MCPWM_CAPCON_RT2_Pos 20 /*!< MCPWM CAPCON: RT2 Position */\r
-#define MCPWM_CAPCON_RT2_Msk (0x01UL << MCPWM_CAPCON_RT2_Pos) /*!< MCPWM CAPCON: RT2 Mask */\r
-#define MCPWM_CAPCON_HNFCAP0_Pos 21 /*!< MCPWM CAPCON: HNFCAP0 Position */\r
-#define MCPWM_CAPCON_HNFCAP0_Msk (0x01UL << MCPWM_CAPCON_HNFCAP0_Pos) /*!< MCPWM CAPCON: HNFCAP0 Mask */\r
-#define MCPWM_CAPCON_HNFCAP1_Pos 22 /*!< MCPWM CAPCON: HNFCAP1 Position */\r
-#define MCPWM_CAPCON_HNFCAP1_Msk (0x01UL << MCPWM_CAPCON_HNFCAP1_Pos) /*!< MCPWM CAPCON: HNFCAP1 Mask */\r
-#define MCPWM_CAPCON_HNFCAP2_Pos 23 /*!< MCPWM CAPCON: HNFCAP2 Position */\r
-#define MCPWM_CAPCON_HNFCAP2_Msk (0x01UL << MCPWM_CAPCON_HNFCAP2_Pos) /*!< MCPWM CAPCON: HNFCAP2 Mask */\r
-\r
-// ------------------------------------ MCPWM_CAPCON_SET ----------------------------------------\r
-#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos 0 /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos 1 /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos 2 /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos 3 /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos 4 /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos 5 /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos 6 /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos 7 /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos 8 /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos 9 /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos 10 /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos 11 /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos 12 /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos 13 /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos 14 /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos 15 /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos 16 /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */\r
-#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos 17 /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */\r
-#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */\r
-#define MCPWM_CAPCON_SET_RT0_SET_Pos 18 /*!< MCPWM CAPCON_SET: RT0_SET Position */\r
-#define MCPWM_CAPCON_SET_RT0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos) /*!< MCPWM CAPCON_SET: RT0_SET Mask */\r
-#define MCPWM_CAPCON_SET_RT1_SET_Pos 19 /*!< MCPWM CAPCON_SET: RT1_SET Position */\r
-#define MCPWM_CAPCON_SET_RT1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos) /*!< MCPWM CAPCON_SET: RT1_SET Mask */\r
-#define MCPWM_CAPCON_SET_RT2_SET_Pos 20 /*!< MCPWM CAPCON_SET: RT2_SET Position */\r
-#define MCPWM_CAPCON_SET_RT2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos) /*!< MCPWM CAPCON_SET: RT2_SET Mask */\r
-#define MCPWM_CAPCON_SET_HNFCAP0_SET_Pos 21 /*!< MCPWM CAPCON_SET: HNFCAP0_SET Position */\r
-#define MCPWM_CAPCON_SET_HNFCAP0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP0_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP0_SET Mask */\r
-#define MCPWM_CAPCON_SET_HNFCAP1_SET_Pos 22 /*!< MCPWM CAPCON_SET: HNFCAP1_SET Position */\r
-#define MCPWM_CAPCON_SET_HNFCAP1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP1_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP1_SET Mask */\r
-#define MCPWM_CAPCON_SET_HNFCAP2_SET_Pos 23 /*!< MCPWM CAPCON_SET: HNFCAP2_SET Position */\r
-#define MCPWM_CAPCON_SET_HNFCAP2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP2_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP2_SET Mask */\r
-\r
-// ------------------------------------ MCPWM_CAPCON_CLR ----------------------------------------\r
-#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos 0 /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos 1 /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos 2 /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos 3 /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos 4 /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos 5 /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos 6 /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos 7 /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos 8 /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos 9 /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos 10 /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos 11 /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos 12 /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos 13 /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos 14 /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos 15 /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos 16 /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos 17 /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */\r
-#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_RT0_CLR_Pos 18 /*!< MCPWM CAPCON_CLR: RT0_CLR Position */\r
-#define MCPWM_CAPCON_CLR_RT0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT0_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_RT1_CLR_Pos 19 /*!< MCPWM CAPCON_CLR: RT1_CLR Position */\r
-#define MCPWM_CAPCON_CLR_RT1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT1_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_RT2_CLR_Pos 20 /*!< MCPWM CAPCON_CLR: RT2_CLR Position */\r
-#define MCPWM_CAPCON_CLR_RT2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT2_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos 21 /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Position */\r
-#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos 22 /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Position */\r
-#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Mask */\r
-#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos 23 /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Position */\r
-#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Mask */\r
-\r
-// ---------------------------------------- MCPWM_TC0 -------------------------------------------\r
-#define MCPWM_TC0_MCTC_Pos 0 /*!< MCPWM TC0: MCTC Position */\r
-#define MCPWM_TC0_MCTC_Msk (0xffffffffUL << MCPWM_TC0_MCTC_Pos) /*!< MCPWM TC0: MCTC Mask */\r
-\r
-// ---------------------------------------- MCPWM_TC1 -------------------------------------------\r
-#define MCPWM_TC1_MCTC_Pos 0 /*!< MCPWM TC1: MCTC Position */\r
-#define MCPWM_TC1_MCTC_Msk (0xffffffffUL << MCPWM_TC1_MCTC_Pos) /*!< MCPWM TC1: MCTC Mask */\r
-\r
-// ---------------------------------------- MCPWM_TC2 -------------------------------------------\r
-#define MCPWM_TC2_MCTC_Pos 0 /*!< MCPWM TC2: MCTC Position */\r
-#define MCPWM_TC2_MCTC_Msk (0xffffffffUL << MCPWM_TC2_MCTC_Pos) /*!< MCPWM TC2: MCTC Mask */\r
-\r
-// --------------------------------------- MCPWM_LIM0 -------------------------------------------\r
-#define MCPWM_LIM0_MCLIM_Pos 0 /*!< MCPWM LIM0: MCLIM Position */\r
-#define MCPWM_LIM0_MCLIM_Msk (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos) /*!< MCPWM LIM0: MCLIM Mask */\r
-\r
-// --------------------------------------- MCPWM_LIM1 -------------------------------------------\r
-#define MCPWM_LIM1_MCLIM_Pos 0 /*!< MCPWM LIM1: MCLIM Position */\r
-#define MCPWM_LIM1_MCLIM_Msk (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos) /*!< MCPWM LIM1: MCLIM Mask */\r
-\r
-// --------------------------------------- MCPWM_LIM2 -------------------------------------------\r
-#define MCPWM_LIM2_MCLIM_Pos 0 /*!< MCPWM LIM2: MCLIM Position */\r
-#define MCPWM_LIM2_MCLIM_Msk (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos) /*!< MCPWM LIM2: MCLIM Mask */\r
-\r
-// --------------------------------------- MCPWM_MAT0 -------------------------------------------\r
-#define MCPWM_MAT0_MCMAT_Pos 0 /*!< MCPWM MAT0: MCMAT Position */\r
-#define MCPWM_MAT0_MCMAT_Msk (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos) /*!< MCPWM MAT0: MCMAT Mask */\r
-\r
-// --------------------------------------- MCPWM_MAT1 -------------------------------------------\r
-#define MCPWM_MAT1_MCMAT_Pos 0 /*!< MCPWM MAT1: MCMAT Position */\r
-#define MCPWM_MAT1_MCMAT_Msk (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos) /*!< MCPWM MAT1: MCMAT Mask */\r
-\r
-// --------------------------------------- MCPWM_MAT2 -------------------------------------------\r
-#define MCPWM_MAT2_MCMAT_Pos 0 /*!< MCPWM MAT2: MCMAT Position */\r
-#define MCPWM_MAT2_MCMAT_Msk (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos) /*!< MCPWM MAT2: MCMAT Mask */\r
-\r
-// ---------------------------------------- MCPWM_DT --------------------------------------------\r
-#define MCPWM_DT_DT0_Pos 0 /*!< MCPWM DT: DT0 Position */\r
-#define MCPWM_DT_DT0_Msk (0x000003ffUL << MCPWM_DT_DT0_Pos) /*!< MCPWM DT: DT0 Mask */\r
-#define MCPWM_DT_DT1_Pos 10 /*!< MCPWM DT: DT1 Position */\r
-#define MCPWM_DT_DT1_Msk (0x000003ffUL << MCPWM_DT_DT1_Pos) /*!< MCPWM DT: DT1 Mask */\r
-#define MCPWM_DT_DT2_Pos 20 /*!< MCPWM DT: DT2 Position */\r
-#define MCPWM_DT_DT2_Msk (0x000003ffUL << MCPWM_DT_DT2_Pos) /*!< MCPWM DT: DT2 Mask */\r
-\r
-// ---------------------------------------- MCPWM_CCP -------------------------------------------\r
-#define MCPWM_CCP_CCPA0_Pos 0 /*!< MCPWM CCP: CCPA0 Position */\r
-#define MCPWM_CCP_CCPA0_Msk (0x01UL << MCPWM_CCP_CCPA0_Pos) /*!< MCPWM CCP: CCPA0 Mask */\r
-#define MCPWM_CCP_CCPB0_Pos 1 /*!< MCPWM CCP: CCPB0 Position */\r
-#define MCPWM_CCP_CCPB0_Msk (0x01UL << MCPWM_CCP_CCPB0_Pos) /*!< MCPWM CCP: CCPB0 Mask */\r
-#define MCPWM_CCP_CCPA1_Pos 2 /*!< MCPWM CCP: CCPA1 Position */\r
-#define MCPWM_CCP_CCPA1_Msk (0x01UL << MCPWM_CCP_CCPA1_Pos) /*!< MCPWM CCP: CCPA1 Mask */\r
-#define MCPWM_CCP_CCPB1_Pos 3 /*!< MCPWM CCP: CCPB1 Position */\r
-#define MCPWM_CCP_CCPB1_Msk (0x01UL << MCPWM_CCP_CCPB1_Pos) /*!< MCPWM CCP: CCPB1 Mask */\r
-#define MCPWM_CCP_CCPA2_Pos 4 /*!< MCPWM CCP: CCPA2 Position */\r
-#define MCPWM_CCP_CCPA2_Msk (0x01UL << MCPWM_CCP_CCPA2_Pos) /*!< MCPWM CCP: CCPA2 Mask */\r
-#define MCPWM_CCP_CCPB2_Pos 5 /*!< MCPWM CCP: CCPB2 Position */\r
-#define MCPWM_CCP_CCPB2_Msk (0x01UL << MCPWM_CCP_CCPB2_Pos) /*!< MCPWM CCP: CCPB2 Mask */\r
-\r
-// --------------------------------------- MCPWM_CAP0 -------------------------------------------\r
-#define MCPWM_CAP0_CAP_Pos 0 /*!< MCPWM CAP0: CAP Position */\r
-#define MCPWM_CAP0_CAP_Msk (0xffffffffUL << MCPWM_CAP0_CAP_Pos) /*!< MCPWM CAP0: CAP Mask */\r
-\r
-// --------------------------------------- MCPWM_CAP1 -------------------------------------------\r
-#define MCPWM_CAP1_CAP_Pos 0 /*!< MCPWM CAP1: CAP Position */\r
-#define MCPWM_CAP1_CAP_Msk (0xffffffffUL << MCPWM_CAP1_CAP_Pos) /*!< MCPWM CAP1: CAP Mask */\r
-\r
-// --------------------------------------- MCPWM_CAP2 -------------------------------------------\r
-#define MCPWM_CAP2_CAP_Pos 0 /*!< MCPWM CAP2: CAP Position */\r
-#define MCPWM_CAP2_CAP_Msk (0xffffffffUL << MCPWM_CAP2_CAP_Pos) /*!< MCPWM CAP2: CAP Mask */\r
-\r
-// --------------------------------------- MCPWM_INTEN ------------------------------------------\r
-#define MCPWM_INTEN_ILIM0_Pos 0 /*!< MCPWM INTEN: ILIM0 Position */\r
-#define MCPWM_INTEN_ILIM0_Msk (0x01UL << MCPWM_INTEN_ILIM0_Pos) /*!< MCPWM INTEN: ILIM0 Mask */\r
-#define MCPWM_INTEN_IMAT0_Pos 1 /*!< MCPWM INTEN: IMAT0 Position */\r
-#define MCPWM_INTEN_IMAT0_Msk (0x01UL << MCPWM_INTEN_IMAT0_Pos) /*!< MCPWM INTEN: IMAT0 Mask */\r
-#define MCPWM_INTEN_ICAP0_Pos 2 /*!< MCPWM INTEN: ICAP0 Position */\r
-#define MCPWM_INTEN_ICAP0_Msk (0x01UL << MCPWM_INTEN_ICAP0_Pos) /*!< MCPWM INTEN: ICAP0 Mask */\r
-#define MCPWM_INTEN_ILIM1_Pos 4 /*!< MCPWM INTEN: ILIM1 Position */\r
-#define MCPWM_INTEN_ILIM1_Msk (0x01UL << MCPWM_INTEN_ILIM1_Pos) /*!< MCPWM INTEN: ILIM1 Mask */\r
-#define MCPWM_INTEN_IMAT1_Pos 5 /*!< MCPWM INTEN: IMAT1 Position */\r
-#define MCPWM_INTEN_IMAT1_Msk (0x01UL << MCPWM_INTEN_IMAT1_Pos) /*!< MCPWM INTEN: IMAT1 Mask */\r
-#define MCPWM_INTEN_ICAP1_Pos 6 /*!< MCPWM INTEN: ICAP1 Position */\r
-#define MCPWM_INTEN_ICAP1_Msk (0x01UL << MCPWM_INTEN_ICAP1_Pos) /*!< MCPWM INTEN: ICAP1 Mask */\r
-#define MCPWM_INTEN_ILIM2_Pos 8 /*!< MCPWM INTEN: ILIM2 Position */\r
-#define MCPWM_INTEN_ILIM2_Msk (0x01UL << MCPWM_INTEN_ILIM2_Pos) /*!< MCPWM INTEN: ILIM2 Mask */\r
-#define MCPWM_INTEN_IMAT2_Pos 9 /*!< MCPWM INTEN: IMAT2 Position */\r
-#define MCPWM_INTEN_IMAT2_Msk (0x01UL << MCPWM_INTEN_IMAT2_Pos) /*!< MCPWM INTEN: IMAT2 Mask */\r
-#define MCPWM_INTEN_ICAP2_Pos 10 /*!< MCPWM INTEN: ICAP2 Position */\r
-#define MCPWM_INTEN_ICAP2_Msk (0x01UL << MCPWM_INTEN_ICAP2_Pos) /*!< MCPWM INTEN: ICAP2 Mask */\r
-#define MCPWM_INTEN_ABORT_Pos 15 /*!< MCPWM INTEN: ABORT Position */\r
-#define MCPWM_INTEN_ABORT_Msk (0x01UL << MCPWM_INTEN_ABORT_Pos) /*!< MCPWM INTEN: ABORT Mask */\r
-\r
-// ------------------------------------- MCPWM_INTEN_SET ----------------------------------------\r
-#define MCPWM_INTEN_SET_ILIM0_SET_Pos 0 /*!< MCPWM INTEN_SET: ILIM0_SET Position */\r
-#define MCPWM_INTEN_SET_ILIM0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos) /*!< MCPWM INTEN_SET: ILIM0_SET Mask */\r
-#define MCPWM_INTEN_SET_IMAT0_SET_Pos 1 /*!< MCPWM INTEN_SET: IMAT0_SET Position */\r
-#define MCPWM_INTEN_SET_IMAT0_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos) /*!< MCPWM INTEN_SET: IMAT0_SET Mask */\r
-#define MCPWM_INTEN_SET_ICAP0_SET_Pos 2 /*!< MCPWM INTEN_SET: ICAP0_SET Position */\r
-#define MCPWM_INTEN_SET_ICAP0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos) /*!< MCPWM INTEN_SET: ICAP0_SET Mask */\r
-#define MCPWM_INTEN_SET_ILIM1_SET_Pos 4 /*!< MCPWM INTEN_SET: ILIM1_SET Position */\r
-#define MCPWM_INTEN_SET_ILIM1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos) /*!< MCPWM INTEN_SET: ILIM1_SET Mask */\r
-#define MCPWM_INTEN_SET_IMAT1_SET_Pos 5 /*!< MCPWM INTEN_SET: IMAT1_SET Position */\r
-#define MCPWM_INTEN_SET_IMAT1_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos) /*!< MCPWM INTEN_SET: IMAT1_SET Mask */\r
-#define MCPWM_INTEN_SET_ICAP1_SET_Pos 6 /*!< MCPWM INTEN_SET: ICAP1_SET Position */\r
-#define MCPWM_INTEN_SET_ICAP1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos) /*!< MCPWM INTEN_SET: ICAP1_SET Mask */\r
-#define MCPWM_INTEN_SET_ILIM2_SET_Pos 9 /*!< MCPWM INTEN_SET: ILIM2_SET Position */\r
-#define MCPWM_INTEN_SET_ILIM2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos) /*!< MCPWM INTEN_SET: ILIM2_SET Mask */\r
-#define MCPWM_INTEN_SET_IMAT2_SET_Pos 10 /*!< MCPWM INTEN_SET: IMAT2_SET Position */\r
-#define MCPWM_INTEN_SET_IMAT2_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos) /*!< MCPWM INTEN_SET: IMAT2_SET Mask */\r
-#define MCPWM_INTEN_SET_ICAP2_SET_Pos 11 /*!< MCPWM INTEN_SET: ICAP2_SET Position */\r
-#define MCPWM_INTEN_SET_ICAP2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos) /*!< MCPWM INTEN_SET: ICAP2_SET Mask */\r
-#define MCPWM_INTEN_SET_ABORT_SET_Pos 15 /*!< MCPWM INTEN_SET: ABORT_SET Position */\r
-#define MCPWM_INTEN_SET_ABORT_SET_Msk (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos) /*!< MCPWM INTEN_SET: ABORT_SET Mask */\r
-\r
-// ------------------------------------- MCPWM_INTEN_CLR ----------------------------------------\r
-#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos 0 /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */\r
-#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask */\r
-#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos 1 /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */\r
-#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask */\r
-#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos 2 /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */\r
-#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask */\r
-#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos 4 /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */\r
-#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask */\r
-#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos 5 /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */\r
-#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask */\r
-#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos 6 /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */\r
-#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask */\r
-#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos 8 /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */\r
-#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask */\r
-#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos 9 /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */\r
-#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask */\r
-#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos 10 /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */\r
-#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask */\r
-#define MCPWM_INTEN_CLR_ABORT_CLR_Pos 15 /*!< MCPWM INTEN_CLR: ABORT_CLR Position */\r
-#define MCPWM_INTEN_CLR_ABORT_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos) /*!< MCPWM INTEN_CLR: ABORT_CLR Mask */\r
-\r
-// -------------------------------------- MCPWM_CNTCON ------------------------------------------\r
-#define MCPWM_CNTCON_TC0MCI0_RE_Pos 0 /*!< MCPWM CNTCON: TC0MCI0_RE Position */\r
-#define MCPWM_CNTCON_TC0MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos) /*!< MCPWM CNTCON: TC0MCI0_RE Mask */\r
-#define MCPWM_CNTCON_TC0MCI0_FE_Pos 1 /*!< MCPWM CNTCON: TC0MCI0_FE Position */\r
-#define MCPWM_CNTCON_TC0MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos) /*!< MCPWM CNTCON: TC0MCI0_FE Mask */\r
-#define MCPWM_CNTCON_TC0MCI1_RE_Pos 2 /*!< MCPWM CNTCON: TC0MCI1_RE Position */\r
-#define MCPWM_CNTCON_TC0MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos) /*!< MCPWM CNTCON: TC0MCI1_RE Mask */\r
-#define MCPWM_CNTCON_TC0MCI1_FE_Pos 3 /*!< MCPWM CNTCON: TC0MCI1_FE Position */\r
-#define MCPWM_CNTCON_TC0MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos) /*!< MCPWM CNTCON: TC0MCI1_FE Mask */\r
-#define MCPWM_CNTCON_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON: TC0MCI2_RE Position */\r
-#define MCPWM_CNTCON_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON: TC0MCI2_RE Mask */\r
-#define MCPWM_CNTCON_TC0MCI2_FE_Pos 5 /*!< MCPWM CNTCON: TC0MCI2_FE Position */\r
-#define MCPWM_CNTCON_TC0MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos) /*!< MCPWM CNTCON: TC0MCI2_FE Mask */\r
-#define MCPWM_CNTCON_TC1MCI0_RE_Pos 6 /*!< MCPWM CNTCON: TC1MCI0_RE Position */\r
-#define MCPWM_CNTCON_TC1MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos) /*!< MCPWM CNTCON: TC1MCI0_RE Mask */\r
-#define MCPWM_CNTCON_TC1MCI0_FE_Pos 7 /*!< MCPWM CNTCON: TC1MCI0_FE Position */\r
-#define MCPWM_CNTCON_TC1MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos) /*!< MCPWM CNTCON: TC1MCI0_FE Mask */\r
-#define MCPWM_CNTCON_TC1MCI1_RE_Pos 8 /*!< MCPWM CNTCON: TC1MCI1_RE Position */\r
-#define MCPWM_CNTCON_TC1MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos) /*!< MCPWM CNTCON: TC1MCI1_RE Mask */\r
-#define MCPWM_CNTCON_TC1MCI1_FE_Pos 9 /*!< MCPWM CNTCON: TC1MCI1_FE Position */\r
-#define MCPWM_CNTCON_TC1MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos) /*!< MCPWM CNTCON: TC1MCI1_FE Mask */\r
-#define MCPWM_CNTCON_TC1MCI2_RE_Pos 10 /*!< MCPWM CNTCON: TC1MCI2_RE Position */\r
-#define MCPWM_CNTCON_TC1MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos) /*!< MCPWM CNTCON: TC1MCI2_RE Mask */\r
-#define MCPWM_CNTCON_TC1MCI2_FE_Pos 11 /*!< MCPWM CNTCON: TC1MCI2_FE Position */\r
-#define MCPWM_CNTCON_TC1MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos) /*!< MCPWM CNTCON: TC1MCI2_FE Mask */\r
-#define MCPWM_CNTCON_TC2MCI0_RE_Pos 12 /*!< MCPWM CNTCON: TC2MCI0_RE Position */\r
-#define MCPWM_CNTCON_TC2MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos) /*!< MCPWM CNTCON: TC2MCI0_RE Mask */\r
-#define MCPWM_CNTCON_TC2MCI0_FE_Pos 13 /*!< MCPWM CNTCON: TC2MCI0_FE Position */\r
-#define MCPWM_CNTCON_TC2MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos) /*!< MCPWM CNTCON: TC2MCI0_FE Mask */\r
-#define MCPWM_CNTCON_TC2MCI1_RE_Pos 14 /*!< MCPWM CNTCON: TC2MCI1_RE Position */\r
-#define MCPWM_CNTCON_TC2MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos) /*!< MCPWM CNTCON: TC2MCI1_RE Mask */\r
-#define MCPWM_CNTCON_TC2MCI1_FE_Pos 15 /*!< MCPWM CNTCON: TC2MCI1_FE Position */\r
-#define MCPWM_CNTCON_TC2MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos) /*!< MCPWM CNTCON: TC2MCI1_FE Mask */\r
-#define MCPWM_CNTCON_TC2MCI2_RE_Pos 16 /*!< MCPWM CNTCON: TC2MCI2_RE Position */\r
-#define MCPWM_CNTCON_TC2MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos) /*!< MCPWM CNTCON: TC2MCI2_RE Mask */\r
-#define MCPWM_CNTCON_TC2MCI2_FE_Pos 17 /*!< MCPWM CNTCON: TC2MCI2_FE Position */\r
-#define MCPWM_CNTCON_TC2MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos) /*!< MCPWM CNTCON: TC2MCI2_FE Mask */\r
-#define MCPWM_CNTCON_CNTR0_Pos 29 /*!< MCPWM CNTCON: CNTR0 Position */\r
-#define MCPWM_CNTCON_CNTR0_Msk (0x01UL << MCPWM_CNTCON_CNTR0_Pos) /*!< MCPWM CNTCON: CNTR0 Mask */\r
-#define MCPWM_CNTCON_CNTR1_Pos 30 /*!< MCPWM CNTCON: CNTR1 Position */\r
-#define MCPWM_CNTCON_CNTR1_Msk (0x01UL << MCPWM_CNTCON_CNTR1_Pos) /*!< MCPWM CNTCON: CNTR1 Mask */\r
-#define MCPWM_CNTCON_CNTR2_Pos 31 /*!< MCPWM CNTCON: CNTR2 Position */\r
-#define MCPWM_CNTCON_CNTR2_Msk (0x01UL << MCPWM_CNTCON_CNTR2_Pos) /*!< MCPWM CNTCON: CNTR2 Mask */\r
-\r
-// ------------------------------------ MCPWM_CNTCON_SET ----------------------------------------\r
-#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos 0 /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos 1 /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos 2 /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos 3 /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos 4 /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos 5 /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos 6 /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos 7 /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos 8 /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos 9 /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos 10 /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos 11 /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos 12 /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos 13 /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos 14 /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos 15 /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos 16 /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */\r
-#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos 17 /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */\r
-#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */\r
-#define MCPWM_CNTCON_SET_CNTR0_SET_Pos 29 /*!< MCPWM CNTCON_SET: CNTR0_SET Position */\r
-#define MCPWM_CNTCON_SET_CNTR0_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR0_SET Mask */\r
-#define MCPWM_CNTCON_SET_CNTR1_SET_Pos 30 /*!< MCPWM CNTCON_SET: CNTR1_SET Position */\r
-#define MCPWM_CNTCON_SET_CNTR1_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR1_SET Mask */\r
-#define MCPWM_CNTCON_SET_CNTR2_SET_Pos 31 /*!< MCPWM CNTCON_SET: CNTR2_SET Position */\r
-#define MCPWM_CNTCON_SET_CNTR2_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR2_SET Mask */\r
-\r
-// ------------------------------------ MCPWM_CNTCON_CLR ----------------------------------------\r
-#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos 0 /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos 1 /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos 2 /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos 3 /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */\r
-#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask */\r
-#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos 5 /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos 6 /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos 7 /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos 8 /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos 9 /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos 10 /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos 11 /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos 12 /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos 13 /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos 14 /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos 15 /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos 16 /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos 17 /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */\r
-#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos 29 /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */\r
-#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos 30 /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */\r
-#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask */\r
-#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos 31 /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */\r
-#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask */\r
-\r
-// --------------------------------------- MCPWM_INTF -------------------------------------------\r
-#define MCPWM_INTF_ILIM0_F_Pos 0 /*!< MCPWM INTF: ILIM0_F Position */\r
-#define MCPWM_INTF_ILIM0_F_Msk (0x01UL << MCPWM_INTF_ILIM0_F_Pos) /*!< MCPWM INTF: ILIM0_F Mask */\r
-#define MCPWM_INTF_IMAT0_F_Pos 1 /*!< MCPWM INTF: IMAT0_F Position */\r
-#define MCPWM_INTF_IMAT0_F_Msk (0x01UL << MCPWM_INTF_IMAT0_F_Pos) /*!< MCPWM INTF: IMAT0_F Mask */\r
-#define MCPWM_INTF_ICAP0_F_Pos 2 /*!< MCPWM INTF: ICAP0_F Position */\r
-#define MCPWM_INTF_ICAP0_F_Msk (0x01UL << MCPWM_INTF_ICAP0_F_Pos) /*!< MCPWM INTF: ICAP0_F Mask */\r
-#define MCPWM_INTF_ILIM1_F_Pos 4 /*!< MCPWM INTF: ILIM1_F Position */\r
-#define MCPWM_INTF_ILIM1_F_Msk (0x01UL << MCPWM_INTF_ILIM1_F_Pos) /*!< MCPWM INTF: ILIM1_F Mask */\r
-#define MCPWM_INTF_IMAT1_F_Pos 5 /*!< MCPWM INTF: IMAT1_F Position */\r
-#define MCPWM_INTF_IMAT1_F_Msk (0x01UL << MCPWM_INTF_IMAT1_F_Pos) /*!< MCPWM INTF: IMAT1_F Mask */\r
-#define MCPWM_INTF_ICAP1_F_Pos 6 /*!< MCPWM INTF: ICAP1_F Position */\r
-#define MCPWM_INTF_ICAP1_F_Msk (0x01UL << MCPWM_INTF_ICAP1_F_Pos) /*!< MCPWM INTF: ICAP1_F Mask */\r
-#define MCPWM_INTF_ILIM2_F_Pos 8 /*!< MCPWM INTF: ILIM2_F Position */\r
-#define MCPWM_INTF_ILIM2_F_Msk (0x01UL << MCPWM_INTF_ILIM2_F_Pos) /*!< MCPWM INTF: ILIM2_F Mask */\r
-#define MCPWM_INTF_IMAT2_F_Pos 9 /*!< MCPWM INTF: IMAT2_F Position */\r
-#define MCPWM_INTF_IMAT2_F_Msk (0x01UL << MCPWM_INTF_IMAT2_F_Pos) /*!< MCPWM INTF: IMAT2_F Mask */\r
-#define MCPWM_INTF_ICAP2_F_Pos 10 /*!< MCPWM INTF: ICAP2_F Position */\r
-#define MCPWM_INTF_ICAP2_F_Msk (0x01UL << MCPWM_INTF_ICAP2_F_Pos) /*!< MCPWM INTF: ICAP2_F Mask */\r
-#define MCPWM_INTF_ABORT_F_Pos 15 /*!< MCPWM INTF: ABORT_F Position */\r
-#define MCPWM_INTF_ABORT_F_Msk (0x01UL << MCPWM_INTF_ABORT_F_Pos) /*!< MCPWM INTF: ABORT_F Mask */\r
-\r
-// ------------------------------------- MCPWM_INTF_SET -----------------------------------------\r
-#define MCPWM_INTF_SET_ILIM0_F_SET_Pos 0 /*!< MCPWM INTF_SET: ILIM0_F_SET Position */\r
-#define MCPWM_INTF_SET_ILIM0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM0_F_SET Mask */\r
-#define MCPWM_INTF_SET_IMAT0_F_SET_Pos 1 /*!< MCPWM INTF_SET: IMAT0_F_SET Position */\r
-#define MCPWM_INTF_SET_IMAT0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT0_F_SET Mask */\r
-#define MCPWM_INTF_SET_ICAP0_F_SET_Pos 2 /*!< MCPWM INTF_SET: ICAP0_F_SET Position */\r
-#define MCPWM_INTF_SET_ICAP0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP0_F_SET Mask */\r
-#define MCPWM_INTF_SET_ILIM1_F_SET_Pos 4 /*!< MCPWM INTF_SET: ILIM1_F_SET Position */\r
-#define MCPWM_INTF_SET_ILIM1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM1_F_SET Mask */\r
-#define MCPWM_INTF_SET_IMAT1_F_SET_Pos 5 /*!< MCPWM INTF_SET: IMAT1_F_SET Position */\r
-#define MCPWM_INTF_SET_IMAT1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT1_F_SET Mask */\r
-#define MCPWM_INTF_SET_ICAP1_F_SET_Pos 6 /*!< MCPWM INTF_SET: ICAP1_F_SET Position */\r
-#define MCPWM_INTF_SET_ICAP1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP1_F_SET Mask */\r
-#define MCPWM_INTF_SET_ILIM2_F_SET_Pos 8 /*!< MCPWM INTF_SET: ILIM2_F_SET Position */\r
-#define MCPWM_INTF_SET_ILIM2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM2_F_SET Mask */\r
-#define MCPWM_INTF_SET_IMAT2_F_SET_Pos 9 /*!< MCPWM INTF_SET: IMAT2_F_SET Position */\r
-#define MCPWM_INTF_SET_IMAT2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT2_F_SET Mask */\r
-#define MCPWM_INTF_SET_ICAP2_F_SET_Pos 10 /*!< MCPWM INTF_SET: ICAP2_F_SET Position */\r
-#define MCPWM_INTF_SET_ICAP2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP2_F_SET Mask */\r
-#define MCPWM_INTF_SET_ABORT_F_SET_Pos 15 /*!< MCPWM INTF_SET: ABORT_F_SET Position */\r
-#define MCPWM_INTF_SET_ABORT_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos) /*!< MCPWM INTF_SET: ABORT_F_SET Mask */\r
-\r
-// ------------------------------------- MCPWM_INTF_CLR -----------------------------------------\r
-#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos 0 /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */\r
-#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask */\r
-#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos 1 /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */\r
-#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask */\r
-#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos 2 /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */\r
-#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask */\r
-#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos 4 /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */\r
-#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask */\r
-#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos 5 /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */\r
-#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask */\r
-#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos 6 /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */\r
-#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask */\r
-#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos 8 /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */\r
-#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask */\r
-#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos 9 /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */\r
-#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask */\r
-#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos 10 /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */\r
-#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask */\r
-#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos 15 /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */\r
-#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos) /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask */\r
-\r
-// -------------------------------------- MCPWM_CAP_CLR -----------------------------------------\r
-#define MCPWM_CAP_CLR_CAP_CLR0_Pos 0 /*!< MCPWM CAP_CLR: CAP_CLR0 Position */\r
-#define MCPWM_CAP_CLR_CAP_CLR0_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos) /*!< MCPWM CAP_CLR: CAP_CLR0 Mask */\r
-#define MCPWM_CAP_CLR_CAP_CLR1_Pos 1 /*!< MCPWM CAP_CLR: CAP_CLR1 Position */\r
-#define MCPWM_CAP_CLR_CAP_CLR1_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos) /*!< MCPWM CAP_CLR: CAP_CLR1 Mask */\r
-#define MCPWM_CAP_CLR_CAP_CLR2_Pos 2 /*!< MCPWM CAP_CLR: CAP_CLR2 Position */\r
-#define MCPWM_CAP_CLR_CAP_CLR2_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos) /*!< MCPWM CAP_CLR: CAP_CLR2 Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- I2C0 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- I2C0_CONSET ------------------------------------------\r
-#define I2C0_CONSET_AA_Pos 2 /*!< I2C0 CONSET: AA Position */\r
-#define I2C0_CONSET_AA_Msk (0x01UL << I2C0_CONSET_AA_Pos) /*!< I2C0 CONSET: AA Mask */\r
-#define I2C0_CONSET_SI_Pos 3 /*!< I2C0 CONSET: SI Position */\r
-#define I2C0_CONSET_SI_Msk (0x01UL << I2C0_CONSET_SI_Pos) /*!< I2C0 CONSET: SI Mask */\r
-#define I2C0_CONSET_STO_Pos 4 /*!< I2C0 CONSET: STO Position */\r
-#define I2C0_CONSET_STO_Msk (0x01UL << I2C0_CONSET_STO_Pos) /*!< I2C0 CONSET: STO Mask */\r
-#define I2C0_CONSET_STA_Pos 5 /*!< I2C0 CONSET: STA Position */\r
-#define I2C0_CONSET_STA_Msk (0x01UL << I2C0_CONSET_STA_Pos) /*!< I2C0 CONSET: STA Mask */\r
-#define I2C0_CONSET_I2EN_Pos 6 /*!< I2C0 CONSET: I2EN Position */\r
-#define I2C0_CONSET_I2EN_Msk (0x01UL << I2C0_CONSET_I2EN_Pos) /*!< I2C0 CONSET: I2EN Mask */\r
-\r
-// ---------------------------------------- I2C0_STAT -------------------------------------------\r
-#define I2C0_STAT_Status_Pos 3 /*!< I2C0 STAT: Status Position */\r
-#define I2C0_STAT_Status_Msk (0x1fUL << I2C0_STAT_Status_Pos) /*!< I2C0 STAT: Status Mask */\r
-\r
-// ---------------------------------------- I2C0_DAT --------------------------------------------\r
-#define I2C0_DAT_Data_Pos 0 /*!< I2C0 DAT: Data Position */\r
-#define I2C0_DAT_Data_Msk (0x000000ffUL << I2C0_DAT_Data_Pos) /*!< I2C0 DAT: Data Mask */\r
-\r
-// ---------------------------------------- I2C0_ADR0 -------------------------------------------\r
-#define I2C0_ADR0_GC_Pos 0 /*!< I2C0 ADR0: GC Position */\r
-#define I2C0_ADR0_GC_Msk (0x01UL << I2C0_ADR0_GC_Pos) /*!< I2C0 ADR0: GC Mask */\r
-#define I2C0_ADR0_Address_Pos 1 /*!< I2C0 ADR0: Address Position */\r
-#define I2C0_ADR0_Address_Msk (0x7fUL << I2C0_ADR0_Address_Pos) /*!< I2C0 ADR0: Address Mask */\r
-\r
-// ---------------------------------------- I2C0_SCLH -------------------------------------------\r
-#define I2C0_SCLH_SCLH_Pos 0 /*!< I2C0 SCLH: SCLH Position */\r
-#define I2C0_SCLH_SCLH_Msk (0x0000ffffUL << I2C0_SCLH_SCLH_Pos) /*!< I2C0 SCLH: SCLH Mask */\r
-\r
-// ---------------------------------------- I2C0_SCLL -------------------------------------------\r
-#define I2C0_SCLL_SCLL_Pos 0 /*!< I2C0 SCLL: SCLL Position */\r
-#define I2C0_SCLL_SCLL_Msk (0x0000ffffUL << I2C0_SCLL_SCLL_Pos) /*!< I2C0 SCLL: SCLL Mask */\r
-\r
-// --------------------------------------- I2C0_CONCLR ------------------------------------------\r
-#define I2C0_CONCLR_AAC_Pos 2 /*!< I2C0 CONCLR: AAC Position */\r
-#define I2C0_CONCLR_AAC_Msk (0x01UL << I2C0_CONCLR_AAC_Pos) /*!< I2C0 CONCLR: AAC Mask */\r
-#define I2C0_CONCLR_SIC_Pos 3 /*!< I2C0 CONCLR: SIC Position */\r
-#define I2C0_CONCLR_SIC_Msk (0x01UL << I2C0_CONCLR_SIC_Pos) /*!< I2C0 CONCLR: SIC Mask */\r
-#define I2C0_CONCLR_STAC_Pos 5 /*!< I2C0 CONCLR: STAC Position */\r
-#define I2C0_CONCLR_STAC_Msk (0x01UL << I2C0_CONCLR_STAC_Pos) /*!< I2C0 CONCLR: STAC Mask */\r
-#define I2C0_CONCLR_I2ENC_Pos 6 /*!< I2C0 CONCLR: I2ENC Position */\r
-#define I2C0_CONCLR_I2ENC_Msk (0x01UL << I2C0_CONCLR_I2ENC_Pos) /*!< I2C0 CONCLR: I2ENC Mask */\r
-\r
-// --------------------------------------- I2C0_MMCTRL ------------------------------------------\r
-#define I2C0_MMCTRL_MM_ENA_Pos 0 /*!< I2C0 MMCTRL: MM_ENA Position */\r
-#define I2C0_MMCTRL_MM_ENA_Msk (0x01UL << I2C0_MMCTRL_MM_ENA_Pos) /*!< I2C0 MMCTRL: MM_ENA Mask */\r
-#define I2C0_MMCTRL_ENA_SCL_Pos 1 /*!< I2C0 MMCTRL: ENA_SCL Position */\r
-#define I2C0_MMCTRL_ENA_SCL_Msk (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos) /*!< I2C0 MMCTRL: ENA_SCL Mask */\r
-#define I2C0_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C0 MMCTRL: MATCH_ALL Position */\r
-#define I2C0_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos) /*!< I2C0 MMCTRL: MATCH_ALL Mask */\r
-\r
-// ---------------------------------------- I2C0_ADR1 -------------------------------------------\r
-#define I2C0_ADR1_GC_Pos 0 /*!< I2C0 ADR1: GC Position */\r
-#define I2C0_ADR1_GC_Msk (0x01UL << I2C0_ADR1_GC_Pos) /*!< I2C0 ADR1: GC Mask */\r
-#define I2C0_ADR1_Address_Pos 1 /*!< I2C0 ADR1: Address Position */\r
-#define I2C0_ADR1_Address_Msk (0x7fUL << I2C0_ADR1_Address_Pos) /*!< I2C0 ADR1: Address Mask */\r
-\r
-// ---------------------------------------- I2C0_ADR2 -------------------------------------------\r
-#define I2C0_ADR2_GC_Pos 0 /*!< I2C0 ADR2: GC Position */\r
-#define I2C0_ADR2_GC_Msk (0x01UL << I2C0_ADR2_GC_Pos) /*!< I2C0 ADR2: GC Mask */\r
-#define I2C0_ADR2_Address_Pos 1 /*!< I2C0 ADR2: Address Position */\r
-#define I2C0_ADR2_Address_Msk (0x7fUL << I2C0_ADR2_Address_Pos) /*!< I2C0 ADR2: Address Mask */\r
-\r
-// ---------------------------------------- I2C0_ADR3 -------------------------------------------\r
-#define I2C0_ADR3_GC_Pos 0 /*!< I2C0 ADR3: GC Position */\r
-#define I2C0_ADR3_GC_Msk (0x01UL << I2C0_ADR3_GC_Pos) /*!< I2C0 ADR3: GC Mask */\r
-#define I2C0_ADR3_Address_Pos 1 /*!< I2C0 ADR3: Address Position */\r
-#define I2C0_ADR3_Address_Msk (0x7fUL << I2C0_ADR3_Address_Pos) /*!< I2C0 ADR3: Address Mask */\r
-\r
-// ------------------------------------ I2C0_DATA_BUFFER ----------------------------------------\r
-#define I2C0_DATA_BUFFER_Data_Pos 0 /*!< I2C0 DATA_BUFFER: Data Position */\r
-#define I2C0_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos) /*!< I2C0 DATA_BUFFER: Data Mask */\r
-\r
-// --------------------------------------- I2C0_MASK0 -------------------------------------------\r
-#define I2C0_MASK0_MASK_Pos 1 /*!< I2C0 MASK0: MASK Position */\r
-#define I2C0_MASK0_MASK_Msk (0x7fUL << I2C0_MASK0_MASK_Pos) /*!< I2C0 MASK0: MASK Mask */\r
-\r
-// --------------------------------------- I2C0_MASK1 -------------------------------------------\r
-#define I2C0_MASK1_MASK_Pos 1 /*!< I2C0 MASK1: MASK Position */\r
-#define I2C0_MASK1_MASK_Msk (0x7fUL << I2C0_MASK1_MASK_Pos) /*!< I2C0 MASK1: MASK Mask */\r
-\r
-// --------------------------------------- I2C0_MASK2 -------------------------------------------\r
-#define I2C0_MASK2_MASK_Pos 1 /*!< I2C0 MASK2: MASK Position */\r
-#define I2C0_MASK2_MASK_Msk (0x7fUL << I2C0_MASK2_MASK_Pos) /*!< I2C0 MASK2: MASK Mask */\r
-\r
-// --------------------------------------- I2C0_MASK3 -------------------------------------------\r
-#define I2C0_MASK3_MASK_Pos 1 /*!< I2C0 MASK3: MASK Position */\r
-#define I2C0_MASK3_MASK_Msk (0x7fUL << I2C0_MASK3_MASK_Pos) /*!< I2C0 MASK3: MASK Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- I2C1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- I2C1_CONSET ------------------------------------------\r
-#define I2C1_CONSET_AA_Pos 2 /*!< I2C1 CONSET: AA Position */\r
-#define I2C1_CONSET_AA_Msk (0x01UL << I2C1_CONSET_AA_Pos) /*!< I2C1 CONSET: AA Mask */\r
-#define I2C1_CONSET_SI_Pos 3 /*!< I2C1 CONSET: SI Position */\r
-#define I2C1_CONSET_SI_Msk (0x01UL << I2C1_CONSET_SI_Pos) /*!< I2C1 CONSET: SI Mask */\r
-#define I2C1_CONSET_STO_Pos 4 /*!< I2C1 CONSET: STO Position */\r
-#define I2C1_CONSET_STO_Msk (0x01UL << I2C1_CONSET_STO_Pos) /*!< I2C1 CONSET: STO Mask */\r
-#define I2C1_CONSET_STA_Pos 5 /*!< I2C1 CONSET: STA Position */\r
-#define I2C1_CONSET_STA_Msk (0x01UL << I2C1_CONSET_STA_Pos) /*!< I2C1 CONSET: STA Mask */\r
-#define I2C1_CONSET_I2EN_Pos 6 /*!< I2C1 CONSET: I2EN Position */\r
-#define I2C1_CONSET_I2EN_Msk (0x01UL << I2C1_CONSET_I2EN_Pos) /*!< I2C1 CONSET: I2EN Mask */\r
-\r
-// ---------------------------------------- I2C1_STAT -------------------------------------------\r
-#define I2C1_STAT_Status_Pos 3 /*!< I2C1 STAT: Status Position */\r
-#define I2C1_STAT_Status_Msk (0x1fUL << I2C1_STAT_Status_Pos) /*!< I2C1 STAT: Status Mask */\r
-\r
-// ---------------------------------------- I2C1_DAT --------------------------------------------\r
-#define I2C1_DAT_Data_Pos 0 /*!< I2C1 DAT: Data Position */\r
-#define I2C1_DAT_Data_Msk (0x000000ffUL << I2C1_DAT_Data_Pos) /*!< I2C1 DAT: Data Mask */\r
-\r
-// ---------------------------------------- I2C1_ADR0 -------------------------------------------\r
-#define I2C1_ADR0_GC_Pos 0 /*!< I2C1 ADR0: GC Position */\r
-#define I2C1_ADR0_GC_Msk (0x01UL << I2C1_ADR0_GC_Pos) /*!< I2C1 ADR0: GC Mask */\r
-#define I2C1_ADR0_Address_Pos 1 /*!< I2C1 ADR0: Address Position */\r
-#define I2C1_ADR0_Address_Msk (0x7fUL << I2C1_ADR0_Address_Pos) /*!< I2C1 ADR0: Address Mask */\r
-\r
-// ---------------------------------------- I2C1_SCLH -------------------------------------------\r
-#define I2C1_SCLH_SCLH_Pos 0 /*!< I2C1 SCLH: SCLH Position */\r
-#define I2C1_SCLH_SCLH_Msk (0x0000ffffUL << I2C1_SCLH_SCLH_Pos) /*!< I2C1 SCLH: SCLH Mask */\r
-\r
-// ---------------------------------------- I2C1_SCLL -------------------------------------------\r
-#define I2C1_SCLL_SCLL_Pos 0 /*!< I2C1 SCLL: SCLL Position */\r
-#define I2C1_SCLL_SCLL_Msk (0x0000ffffUL << I2C1_SCLL_SCLL_Pos) /*!< I2C1 SCLL: SCLL Mask */\r
-\r
-// --------------------------------------- I2C1_CONCLR ------------------------------------------\r
-#define I2C1_CONCLR_AAC_Pos 2 /*!< I2C1 CONCLR: AAC Position */\r
-#define I2C1_CONCLR_AAC_Msk (0x01UL << I2C1_CONCLR_AAC_Pos) /*!< I2C1 CONCLR: AAC Mask */\r
-#define I2C1_CONCLR_SIC_Pos 3 /*!< I2C1 CONCLR: SIC Position */\r
-#define I2C1_CONCLR_SIC_Msk (0x01UL << I2C1_CONCLR_SIC_Pos) /*!< I2C1 CONCLR: SIC Mask */\r
-#define I2C1_CONCLR_STAC_Pos 5 /*!< I2C1 CONCLR: STAC Position */\r
-#define I2C1_CONCLR_STAC_Msk (0x01UL << I2C1_CONCLR_STAC_Pos) /*!< I2C1 CONCLR: STAC Mask */\r
-#define I2C1_CONCLR_I2ENC_Pos 6 /*!< I2C1 CONCLR: I2ENC Position */\r
-#define I2C1_CONCLR_I2ENC_Msk (0x01UL << I2C1_CONCLR_I2ENC_Pos) /*!< I2C1 CONCLR: I2ENC Mask */\r
-\r
-// --------------------------------------- I2C1_MMCTRL ------------------------------------------\r
-#define I2C1_MMCTRL_MM_ENA_Pos 0 /*!< I2C1 MMCTRL: MM_ENA Position */\r
-#define I2C1_MMCTRL_MM_ENA_Msk (0x01UL << I2C1_MMCTRL_MM_ENA_Pos) /*!< I2C1 MMCTRL: MM_ENA Mask */\r
-#define I2C1_MMCTRL_ENA_SCL_Pos 1 /*!< I2C1 MMCTRL: ENA_SCL Position */\r
-#define I2C1_MMCTRL_ENA_SCL_Msk (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos) /*!< I2C1 MMCTRL: ENA_SCL Mask */\r
-#define I2C1_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C1 MMCTRL: MATCH_ALL Position */\r
-#define I2C1_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos) /*!< I2C1 MMCTRL: MATCH_ALL Mask */\r
-\r
-// ---------------------------------------- I2C1_ADR1 -------------------------------------------\r
-#define I2C1_ADR1_GC_Pos 0 /*!< I2C1 ADR1: GC Position */\r
-#define I2C1_ADR1_GC_Msk (0x01UL << I2C1_ADR1_GC_Pos) /*!< I2C1 ADR1: GC Mask */\r
-#define I2C1_ADR1_Address_Pos 1 /*!< I2C1 ADR1: Address Position */\r
-#define I2C1_ADR1_Address_Msk (0x7fUL << I2C1_ADR1_Address_Pos) /*!< I2C1 ADR1: Address Mask */\r
-\r
-// ---------------------------------------- I2C1_ADR2 -------------------------------------------\r
-#define I2C1_ADR2_GC_Pos 0 /*!< I2C1 ADR2: GC Position */\r
-#define I2C1_ADR2_GC_Msk (0x01UL << I2C1_ADR2_GC_Pos) /*!< I2C1 ADR2: GC Mask */\r
-#define I2C1_ADR2_Address_Pos 1 /*!< I2C1 ADR2: Address Position */\r
-#define I2C1_ADR2_Address_Msk (0x7fUL << I2C1_ADR2_Address_Pos) /*!< I2C1 ADR2: Address Mask */\r
-\r
-// ---------------------------------------- I2C1_ADR3 -------------------------------------------\r
-#define I2C1_ADR3_GC_Pos 0 /*!< I2C1 ADR3: GC Position */\r
-#define I2C1_ADR3_GC_Msk (0x01UL << I2C1_ADR3_GC_Pos) /*!< I2C1 ADR3: GC Mask */\r
-#define I2C1_ADR3_Address_Pos 1 /*!< I2C1 ADR3: Address Position */\r
-#define I2C1_ADR3_Address_Msk (0x7fUL << I2C1_ADR3_Address_Pos) /*!< I2C1 ADR3: Address Mask */\r
-\r
-// ------------------------------------ I2C1_DATA_BUFFER ----------------------------------------\r
-#define I2C1_DATA_BUFFER_Data_Pos 0 /*!< I2C1 DATA_BUFFER: Data Position */\r
-#define I2C1_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos) /*!< I2C1 DATA_BUFFER: Data Mask */\r
-\r
-// --------------------------------------- I2C1_MASK0 -------------------------------------------\r
-#define I2C1_MASK0_MASK_Pos 1 /*!< I2C1 MASK0: MASK Position */\r
-#define I2C1_MASK0_MASK_Msk (0x7fUL << I2C1_MASK0_MASK_Pos) /*!< I2C1 MASK0: MASK Mask */\r
-\r
-// --------------------------------------- I2C1_MASK1 -------------------------------------------\r
-#define I2C1_MASK1_MASK_Pos 1 /*!< I2C1 MASK1: MASK Position */\r
-#define I2C1_MASK1_MASK_Msk (0x7fUL << I2C1_MASK1_MASK_Pos) /*!< I2C1 MASK1: MASK Mask */\r
-\r
-// --------------------------------------- I2C1_MASK2 -------------------------------------------\r
-#define I2C1_MASK2_MASK_Pos 1 /*!< I2C1 MASK2: MASK Position */\r
-#define I2C1_MASK2_MASK_Msk (0x7fUL << I2C1_MASK2_MASK_Pos) /*!< I2C1 MASK2: MASK Mask */\r
-\r
-// --------------------------------------- I2C1_MASK3 -------------------------------------------\r
-#define I2C1_MASK3_MASK_Pos 1 /*!< I2C1 MASK3: MASK Position */\r
-#define I2C1_MASK3_MASK_Msk (0x7fUL << I2C1_MASK3_MASK_Pos) /*!< I2C1 MASK3: MASK Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- I2S0 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- I2S0_DAO --------------------------------------------\r
-#define I2S0_DAO_WORDWIDTH_Pos 0 /*!< I2S0 DAO: WORDWIDTH Position */\r
-#define I2S0_DAO_WORDWIDTH_Msk (0x03UL << I2S0_DAO_WORDWIDTH_Pos) /*!< I2S0 DAO: WORDWIDTH Mask */\r
-#define I2S0_DAO_MONO_Pos 2 /*!< I2S0 DAO: MONO Position */\r
-#define I2S0_DAO_MONO_Msk (0x01UL << I2S0_DAO_MONO_Pos) /*!< I2S0 DAO: MONO Mask */\r
-#define I2S0_DAO_STOP_Pos 3 /*!< I2S0 DAO: STOP Position */\r
-#define I2S0_DAO_STOP_Msk (0x01UL << I2S0_DAO_STOP_Pos) /*!< I2S0 DAO: STOP Mask */\r
-#define I2S0_DAO_RESET_Pos 4 /*!< I2S0 DAO: RESET Position */\r
-#define I2S0_DAO_RESET_Msk (0x01UL << I2S0_DAO_RESET_Pos) /*!< I2S0 DAO: RESET Mask */\r
-#define I2S0_DAO_WS_SEL_Pos 5 /*!< I2S0 DAO: WS_SEL Position */\r
-#define I2S0_DAO_WS_SEL_Msk (0x01UL << I2S0_DAO_WS_SEL_Pos) /*!< I2S0 DAO: WS_SEL Mask */\r
-#define I2S0_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAO: WS_HALFPERIOD Position */\r
-#define I2S0_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos) /*!< I2S0 DAO: WS_HALFPERIOD Mask */\r
-#define I2S0_DAO_MUTE_Pos 15 /*!< I2S0 DAO: MUTE Position */\r
-#define I2S0_DAO_MUTE_Msk (0x01UL << I2S0_DAO_MUTE_Pos) /*!< I2S0 DAO: MUTE Mask */\r
-\r
-// ---------------------------------------- I2S0_DAI --------------------------------------------\r
-#define I2S0_DAI_WORDWIDTH_Pos 0 /*!< I2S0 DAI: WORDWIDTH Position */\r
-#define I2S0_DAI_WORDWIDTH_Msk (0x03UL << I2S0_DAI_WORDWIDTH_Pos) /*!< I2S0 DAI: WORDWIDTH Mask */\r
-#define I2S0_DAI_MONO_Pos 2 /*!< I2S0 DAI: MONO Position */\r
-#define I2S0_DAI_MONO_Msk (0x01UL << I2S0_DAI_MONO_Pos) /*!< I2S0 DAI: MONO Mask */\r
-#define I2S0_DAI_STOP_Pos 3 /*!< I2S0 DAI: STOP Position */\r
-#define I2S0_DAI_STOP_Msk (0x01UL << I2S0_DAI_STOP_Pos) /*!< I2S0 DAI: STOP Mask */\r
-#define I2S0_DAI_RESET_Pos 4 /*!< I2S0 DAI: RESET Position */\r
-#define I2S0_DAI_RESET_Msk (0x01UL << I2S0_DAI_RESET_Pos) /*!< I2S0 DAI: RESET Mask */\r
-#define I2S0_DAI_WS_SEL_Pos 5 /*!< I2S0 DAI: WS_SEL Position */\r
-#define I2S0_DAI_WS_SEL_Msk (0x01UL << I2S0_DAI_WS_SEL_Pos) /*!< I2S0 DAI: WS_SEL Mask */\r
-#define I2S0_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAI: WS_HALFPERIOD Position */\r
-#define I2S0_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos) /*!< I2S0 DAI: WS_HALFPERIOD Mask */\r
-\r
-// --------------------------------------- I2S0_TXFIFO ------------------------------------------\r
-#define I2S0_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S0 TXFIFO: I2STXFIFO Position */\r
-#define I2S0_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos) /*!< I2S0 TXFIFO: I2STXFIFO Mask */\r
-\r
-// --------------------------------------- I2S0_RXFIFO ------------------------------------------\r
-#define I2S0_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S0 RXFIFO: I2SRXFIFO Position */\r
-#define I2S0_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos) /*!< I2S0 RXFIFO: I2SRXFIFO Mask */\r
-\r
-// --------------------------------------- I2S0_STATE -------------------------------------------\r
-#define I2S0_STATE_IRQ_Pos 0 /*!< I2S0 STATE: IRQ Position */\r
-#define I2S0_STATE_IRQ_Msk (0x01UL << I2S0_STATE_IRQ_Pos) /*!< I2S0 STATE: IRQ Mask */\r
-#define I2S0_STATE_DMAREQ1_Pos 1 /*!< I2S0 STATE: DMAREQ1 Position */\r
-#define I2S0_STATE_DMAREQ1_Msk (0x01UL << I2S0_STATE_DMAREQ1_Pos) /*!< I2S0 STATE: DMAREQ1 Mask */\r
-#define I2S0_STATE_DMAREQ2_Pos 2 /*!< I2S0 STATE: DMAREQ2 Position */\r
-#define I2S0_STATE_DMAREQ2_Msk (0x01UL << I2S0_STATE_DMAREQ2_Pos) /*!< I2S0 STATE: DMAREQ2 Mask */\r
-#define I2S0_STATE_RX_LEVEL_Pos 8 /*!< I2S0 STATE: RX_LEVEL Position */\r
-#define I2S0_STATE_RX_LEVEL_Msk (0x0fUL << I2S0_STATE_RX_LEVEL_Pos) /*!< I2S0 STATE: RX_LEVEL Mask */\r
-#define I2S0_STATE_TX_LEVEL_Pos 16 /*!< I2S0 STATE: TX_LEVEL Position */\r
-#define I2S0_STATE_TX_LEVEL_Msk (0x0fUL << I2S0_STATE_TX_LEVEL_Pos) /*!< I2S0 STATE: TX_LEVEL Mask */\r
-\r
-// ---------------------------------------- I2S0_DMA1 -------------------------------------------\r
-#define I2S0_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S0 DMA1: RX_DMA1_ENABLE Position */\r
-#define I2S0_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask */\r
-#define I2S0_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S0 DMA1: TX_DMA1_ENABLE Position */\r
-#define I2S0_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask */\r
-#define I2S0_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position */\r
-#define I2S0_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask */\r
-#define I2S0_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position */\r
-#define I2S0_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask */\r
-\r
-// ---------------------------------------- I2S0_DMA2 -------------------------------------------\r
-#define I2S0_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S0 DMA2: RX_DMA2_ENABLE Position */\r
-#define I2S0_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask */\r
-#define I2S0_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S0 DMA2: TX_DMA2_ENABLE Position */\r
-#define I2S0_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask */\r
-#define I2S0_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position */\r
-#define I2S0_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask */\r
-#define I2S0_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position */\r
-#define I2S0_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask */\r
-\r
-// ---------------------------------------- I2S0_IRQ --------------------------------------------\r
-#define I2S0_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S0 IRQ: RX_IRQ_ENABLE Position */\r
-#define I2S0_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask */\r
-#define I2S0_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S0 IRQ: TX_IRQ_ENABLE Position */\r
-#define I2S0_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask */\r
-#define I2S0_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S0 IRQ: RX_DEPTH_IRQ Position */\r
-#define I2S0_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask */\r
-#define I2S0_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S0 IRQ: TX_DEPTH_IRQ Position */\r
-#define I2S0_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask */\r
-\r
-// --------------------------------------- I2S0_TXRATE ------------------------------------------\r
-#define I2S0_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 TXRATE: Y_DIVIDER Position */\r
-#define I2S0_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos) /*!< I2S0 TXRATE: Y_DIVIDER Mask */\r
-#define I2S0_TXRATE_X_DIVIDER_Pos 8 /*!< I2S0 TXRATE: X_DIVIDER Position */\r
-#define I2S0_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos) /*!< I2S0 TXRATE: X_DIVIDER Mask */\r
-\r
-// --------------------------------------- I2S0_RXRATE ------------------------------------------\r
-#define I2S0_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 RXRATE: Y_DIVIDER Position */\r
-#define I2S0_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos) /*!< I2S0 RXRATE: Y_DIVIDER Mask */\r
-#define I2S0_RXRATE_X_DIVIDER_Pos 8 /*!< I2S0 RXRATE: X_DIVIDER Position */\r
-#define I2S0_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos) /*!< I2S0 RXRATE: X_DIVIDER Mask */\r
-\r
-// ------------------------------------- I2S0_TXBITRATE -----------------------------------------\r
-#define I2S0_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S0 TXBITRATE: TX_BITRATE Position */\r
-#define I2S0_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos) /*!< I2S0 TXBITRATE: TX_BITRATE Mask */\r
-\r
-// ------------------------------------- I2S0_RXBITRATE -----------------------------------------\r
-#define I2S0_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S0 RXBITRATE: RX_BITRATE Position */\r
-#define I2S0_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos) /*!< I2S0 RXBITRATE: RX_BITRATE Mask */\r
-\r
-// --------------------------------------- I2S0_TXMODE ------------------------------------------\r
-#define I2S0_TXMODE_TXCLKSEL_Pos 0 /*!< I2S0 TXMODE: TXCLKSEL Position */\r
-#define I2S0_TXMODE_TXCLKSEL_Msk (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos) /*!< I2S0 TXMODE: TXCLKSEL Mask */\r
-#define I2S0_TXMODE_TX4PIN_Pos 2 /*!< I2S0 TXMODE: TX4PIN Position */\r
-#define I2S0_TXMODE_TX4PIN_Msk (0x01UL << I2S0_TXMODE_TX4PIN_Pos) /*!< I2S0 TXMODE: TX4PIN Mask */\r
-#define I2S0_TXMODE_TXMCENA_Pos 3 /*!< I2S0 TXMODE: TXMCENA Position */\r
-#define I2S0_TXMODE_TXMCENA_Msk (0x01UL << I2S0_TXMODE_TXMCENA_Pos) /*!< I2S0 TXMODE: TXMCENA Mask */\r
-\r
-// --------------------------------------- I2S0_RXMODE ------------------------------------------\r
-#define I2S0_RXMODE_RXCLKSEL_Pos 0 /*!< I2S0 RXMODE: RXCLKSEL Position */\r
-#define I2S0_RXMODE_RXCLKSEL_Msk (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos) /*!< I2S0 RXMODE: RXCLKSEL Mask */\r
-#define I2S0_RXMODE_RX4PIN_Pos 2 /*!< I2S0 RXMODE: RX4PIN Position */\r
-#define I2S0_RXMODE_RX4PIN_Msk (0x01UL << I2S0_RXMODE_RX4PIN_Pos) /*!< I2S0 RXMODE: RX4PIN Mask */\r
-#define I2S0_RXMODE_RXMCENA_Pos 3 /*!< I2S0 RXMODE: RXMCENA Position */\r
-#define I2S0_RXMODE_RXMCENA_Msk (0x01UL << I2S0_RXMODE_RXMCENA_Pos) /*!< I2S0 RXMODE: RXMCENA Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- I2S1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------- I2S1_DAO --------------------------------------------\r
-#define I2S1_DAO_WORDWIDTH_Pos 0 /*!< I2S1 DAO: WORDWIDTH Position */\r
-#define I2S1_DAO_WORDWIDTH_Msk (0x03UL << I2S1_DAO_WORDWIDTH_Pos) /*!< I2S1 DAO: WORDWIDTH Mask */\r
-#define I2S1_DAO_MONO_Pos 2 /*!< I2S1 DAO: MONO Position */\r
-#define I2S1_DAO_MONO_Msk (0x01UL << I2S1_DAO_MONO_Pos) /*!< I2S1 DAO: MONO Mask */\r
-#define I2S1_DAO_STOP_Pos 3 /*!< I2S1 DAO: STOP Position */\r
-#define I2S1_DAO_STOP_Msk (0x01UL << I2S1_DAO_STOP_Pos) /*!< I2S1 DAO: STOP Mask */\r
-#define I2S1_DAO_RESET_Pos 4 /*!< I2S1 DAO: RESET Position */\r
-#define I2S1_DAO_RESET_Msk (0x01UL << I2S1_DAO_RESET_Pos) /*!< I2S1 DAO: RESET Mask */\r
-#define I2S1_DAO_WS_SEL_Pos 5 /*!< I2S1 DAO: WS_SEL Position */\r
-#define I2S1_DAO_WS_SEL_Msk (0x01UL << I2S1_DAO_WS_SEL_Pos) /*!< I2S1 DAO: WS_SEL Mask */\r
-#define I2S1_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAO: WS_HALFPERIOD Position */\r
-#define I2S1_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos) /*!< I2S1 DAO: WS_HALFPERIOD Mask */\r
-#define I2S1_DAO_MUTE_Pos 15 /*!< I2S1 DAO: MUTE Position */\r
-#define I2S1_DAO_MUTE_Msk (0x01UL << I2S1_DAO_MUTE_Pos) /*!< I2S1 DAO: MUTE Mask */\r
-\r
-// ---------------------------------------- I2S1_DAI --------------------------------------------\r
-#define I2S1_DAI_WORDWIDTH_Pos 0 /*!< I2S1 DAI: WORDWIDTH Position */\r
-#define I2S1_DAI_WORDWIDTH_Msk (0x03UL << I2S1_DAI_WORDWIDTH_Pos) /*!< I2S1 DAI: WORDWIDTH Mask */\r
-#define I2S1_DAI_MONO_Pos 2 /*!< I2S1 DAI: MONO Position */\r
-#define I2S1_DAI_MONO_Msk (0x01UL << I2S1_DAI_MONO_Pos) /*!< I2S1 DAI: MONO Mask */\r
-#define I2S1_DAI_STOP_Pos 3 /*!< I2S1 DAI: STOP Position */\r
-#define I2S1_DAI_STOP_Msk (0x01UL << I2S1_DAI_STOP_Pos) /*!< I2S1 DAI: STOP Mask */\r
-#define I2S1_DAI_RESET_Pos 4 /*!< I2S1 DAI: RESET Position */\r
-#define I2S1_DAI_RESET_Msk (0x01UL << I2S1_DAI_RESET_Pos) /*!< I2S1 DAI: RESET Mask */\r
-#define I2S1_DAI_WS_SEL_Pos 5 /*!< I2S1 DAI: WS_SEL Position */\r
-#define I2S1_DAI_WS_SEL_Msk (0x01UL << I2S1_DAI_WS_SEL_Pos) /*!< I2S1 DAI: WS_SEL Mask */\r
-#define I2S1_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAI: WS_HALFPERIOD Position */\r
-#define I2S1_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos) /*!< I2S1 DAI: WS_HALFPERIOD Mask */\r
-\r
-// --------------------------------------- I2S1_TXFIFO ------------------------------------------\r
-#define I2S1_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S1 TXFIFO: I2STXFIFO Position */\r
-#define I2S1_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos) /*!< I2S1 TXFIFO: I2STXFIFO Mask */\r
-\r
-// --------------------------------------- I2S1_RXFIFO ------------------------------------------\r
-#define I2S1_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S1 RXFIFO: I2SRXFIFO Position */\r
-#define I2S1_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos) /*!< I2S1 RXFIFO: I2SRXFIFO Mask */\r
-\r
-// --------------------------------------- I2S1_STATE -------------------------------------------\r
-#define I2S1_STATE_IRQ_Pos 0 /*!< I2S1 STATE: IRQ Position */\r
-#define I2S1_STATE_IRQ_Msk (0x01UL << I2S1_STATE_IRQ_Pos) /*!< I2S1 STATE: IRQ Mask */\r
-#define I2S1_STATE_DMAREQ1_Pos 1 /*!< I2S1 STATE: DMAREQ1 Position */\r
-#define I2S1_STATE_DMAREQ1_Msk (0x01UL << I2S1_STATE_DMAREQ1_Pos) /*!< I2S1 STATE: DMAREQ1 Mask */\r
-#define I2S1_STATE_DMAREQ2_Pos 2 /*!< I2S1 STATE: DMAREQ2 Position */\r
-#define I2S1_STATE_DMAREQ2_Msk (0x01UL << I2S1_STATE_DMAREQ2_Pos) /*!< I2S1 STATE: DMAREQ2 Mask */\r
-#define I2S1_STATE_RX_LEVEL_Pos 8 /*!< I2S1 STATE: RX_LEVEL Position */\r
-#define I2S1_STATE_RX_LEVEL_Msk (0x0fUL << I2S1_STATE_RX_LEVEL_Pos) /*!< I2S1 STATE: RX_LEVEL Mask */\r
-#define I2S1_STATE_TX_LEVEL_Pos 16 /*!< I2S1 STATE: TX_LEVEL Position */\r
-#define I2S1_STATE_TX_LEVEL_Msk (0x0fUL << I2S1_STATE_TX_LEVEL_Pos) /*!< I2S1 STATE: TX_LEVEL Mask */\r
-\r
-// ---------------------------------------- I2S1_DMA1 -------------------------------------------\r
-#define I2S1_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S1 DMA1: RX_DMA1_ENABLE Position */\r
-#define I2S1_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask */\r
-#define I2S1_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S1 DMA1: TX_DMA1_ENABLE Position */\r
-#define I2S1_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask */\r
-#define I2S1_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position */\r
-#define I2S1_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask */\r
-#define I2S1_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position */\r
-#define I2S1_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask */\r
-\r
-// ---------------------------------------- I2S1_DMA2 -------------------------------------------\r
-#define I2S1_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S1 DMA2: RX_DMA2_ENABLE Position */\r
-#define I2S1_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask */\r
-#define I2S1_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S1 DMA2: TX_DMA2_ENABLE Position */\r
-#define I2S1_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask */\r
-#define I2S1_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position */\r
-#define I2S1_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask */\r
-#define I2S1_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position */\r
-#define I2S1_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask */\r
-\r
-// ---------------------------------------- I2S1_IRQ --------------------------------------------\r
-#define I2S1_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S1 IRQ: RX_IRQ_ENABLE Position */\r
-#define I2S1_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask */\r
-#define I2S1_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S1 IRQ: TX_IRQ_ENABLE Position */\r
-#define I2S1_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask */\r
-#define I2S1_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S1 IRQ: RX_DEPTH_IRQ Position */\r
-#define I2S1_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask */\r
-#define I2S1_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S1 IRQ: TX_DEPTH_IRQ Position */\r
-#define I2S1_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask */\r
-\r
-// --------------------------------------- I2S1_TXRATE ------------------------------------------\r
-#define I2S1_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 TXRATE: Y_DIVIDER Position */\r
-#define I2S1_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos) /*!< I2S1 TXRATE: Y_DIVIDER Mask */\r
-#define I2S1_TXRATE_X_DIVIDER_Pos 8 /*!< I2S1 TXRATE: X_DIVIDER Position */\r
-#define I2S1_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos) /*!< I2S1 TXRATE: X_DIVIDER Mask */\r
-\r
-// --------------------------------------- I2S1_RXRATE ------------------------------------------\r
-#define I2S1_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 RXRATE: Y_DIVIDER Position */\r
-#define I2S1_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos) /*!< I2S1 RXRATE: Y_DIVIDER Mask */\r
-#define I2S1_RXRATE_X_DIVIDER_Pos 8 /*!< I2S1 RXRATE: X_DIVIDER Position */\r
-#define I2S1_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos) /*!< I2S1 RXRATE: X_DIVIDER Mask */\r
-\r
-// ------------------------------------- I2S1_TXBITRATE -----------------------------------------\r
-#define I2S1_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S1 TXBITRATE: TX_BITRATE Position */\r
-#define I2S1_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos) /*!< I2S1 TXBITRATE: TX_BITRATE Mask */\r
-\r
-// ------------------------------------- I2S1_RXBITRATE -----------------------------------------\r
-#define I2S1_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S1 RXBITRATE: RX_BITRATE Position */\r
-#define I2S1_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos) /*!< I2S1 RXBITRATE: RX_BITRATE Mask */\r
-\r
-// --------------------------------------- I2S1_TXMODE ------------------------------------------\r
-#define I2S1_TXMODE_TXCLKSEL_Pos 0 /*!< I2S1 TXMODE: TXCLKSEL Position */\r
-#define I2S1_TXMODE_TXCLKSEL_Msk (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos) /*!< I2S1 TXMODE: TXCLKSEL Mask */\r
-#define I2S1_TXMODE_TX4PIN_Pos 2 /*!< I2S1 TXMODE: TX4PIN Position */\r
-#define I2S1_TXMODE_TX4PIN_Msk (0x01UL << I2S1_TXMODE_TX4PIN_Pos) /*!< I2S1 TXMODE: TX4PIN Mask */\r
-#define I2S1_TXMODE_TXMCENA_Pos 3 /*!< I2S1 TXMODE: TXMCENA Position */\r
-#define I2S1_TXMODE_TXMCENA_Msk (0x01UL << I2S1_TXMODE_TXMCENA_Pos) /*!< I2S1 TXMODE: TXMCENA Mask */\r
-\r
-// --------------------------------------- I2S1_RXMODE ------------------------------------------\r
-#define I2S1_RXMODE_RXCLKSEL_Pos 0 /*!< I2S1 RXMODE: RXCLKSEL Position */\r
-#define I2S1_RXMODE_RXCLKSEL_Msk (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos) /*!< I2S1 RXMODE: RXCLKSEL Mask */\r
-#define I2S1_RXMODE_RX4PIN_Pos 2 /*!< I2S1 RXMODE: RX4PIN Position */\r
-#define I2S1_RXMODE_RX4PIN_Msk (0x01UL << I2S1_RXMODE_RX4PIN_Pos) /*!< I2S1 RXMODE: RX4PIN Mask */\r
-#define I2S1_RXMODE_RXMCENA_Pos 3 /*!< I2S1 RXMODE: RXMCENA Position */\r
-#define I2S1_RXMODE_RXMCENA_Msk (0x01UL << I2S1_RXMODE_RXMCENA_Pos) /*!< I2S1 RXMODE: RXMCENA Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- C_CAN1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- C_CAN1_CNTL ------------------------------------------\r
-#define C_CAN1_CNTL_INIT_Pos 0 /*!< C_CAN1 CNTL: INIT Position */\r
-#define C_CAN1_CNTL_INIT_Msk (0x01UL << C_CAN1_CNTL_INIT_Pos) /*!< C_CAN1 CNTL: INIT Mask */\r
-#define C_CAN1_CNTL_IE_Pos 1 /*!< C_CAN1 CNTL: IE Position */\r
-#define C_CAN1_CNTL_IE_Msk (0x01UL << C_CAN1_CNTL_IE_Pos) /*!< C_CAN1 CNTL: IE Mask */\r
-#define C_CAN1_CNTL_SIE_Pos 2 /*!< C_CAN1 CNTL: SIE Position */\r
-#define C_CAN1_CNTL_SIE_Msk (0x01UL << C_CAN1_CNTL_SIE_Pos) /*!< C_CAN1 CNTL: SIE Mask */\r
-#define C_CAN1_CNTL_EIE_Pos 3 /*!< C_CAN1 CNTL: EIE Position */\r
-#define C_CAN1_CNTL_EIE_Msk (0x01UL << C_CAN1_CNTL_EIE_Pos) /*!< C_CAN1 CNTL: EIE Mask */\r
-#define C_CAN1_CNTL_DAR_Pos 5 /*!< C_CAN1 CNTL: DAR Position */\r
-#define C_CAN1_CNTL_DAR_Msk (0x01UL << C_CAN1_CNTL_DAR_Pos) /*!< C_CAN1 CNTL: DAR Mask */\r
-#define C_CAN1_CNTL_CCE_Pos 6 /*!< C_CAN1 CNTL: CCE Position */\r
-#define C_CAN1_CNTL_CCE_Msk (0x01UL << C_CAN1_CNTL_CCE_Pos) /*!< C_CAN1 CNTL: CCE Mask */\r
-#define C_CAN1_CNTL_TEST_Pos 7 /*!< C_CAN1 CNTL: TEST Position */\r
-#define C_CAN1_CNTL_TEST_Msk (0x01UL << C_CAN1_CNTL_TEST_Pos) /*!< C_CAN1 CNTL: TEST Mask */\r
-\r
-// --------------------------------------- C_CAN1_STAT ------------------------------------------\r
-#define C_CAN1_STAT_LEC_Pos 0 /*!< C_CAN1 STAT: LEC Position */\r
-#define C_CAN1_STAT_LEC_Msk (0x07UL << C_CAN1_STAT_LEC_Pos) /*!< C_CAN1 STAT: LEC Mask */\r
-#define C_CAN1_STAT_TXOK_Pos 3 /*!< C_CAN1 STAT: TXOK Position */\r
-#define C_CAN1_STAT_TXOK_Msk (0x01UL << C_CAN1_STAT_TXOK_Pos) /*!< C_CAN1 STAT: TXOK Mask */\r
-#define C_CAN1_STAT_RXOK_Pos 4 /*!< C_CAN1 STAT: RXOK Position */\r
-#define C_CAN1_STAT_RXOK_Msk (0x01UL << C_CAN1_STAT_RXOK_Pos) /*!< C_CAN1 STAT: RXOK Mask */\r
-#define C_CAN1_STAT_EPASS_Pos 5 /*!< C_CAN1 STAT: EPASS Position */\r
-#define C_CAN1_STAT_EPASS_Msk (0x01UL << C_CAN1_STAT_EPASS_Pos) /*!< C_CAN1 STAT: EPASS Mask */\r
-#define C_CAN1_STAT_EWARN_Pos 6 /*!< C_CAN1 STAT: EWARN Position */\r
-#define C_CAN1_STAT_EWARN_Msk (0x01UL << C_CAN1_STAT_EWARN_Pos) /*!< C_CAN1 STAT: EWARN Mask */\r
-#define C_CAN1_STAT_BOFF_Pos 7 /*!< C_CAN1 STAT: BOFF Position */\r
-#define C_CAN1_STAT_BOFF_Msk (0x01UL << C_CAN1_STAT_BOFF_Pos) /*!< C_CAN1 STAT: BOFF Mask */\r
-\r
-// ---------------------------------------- C_CAN1_EC -------------------------------------------\r
-#define C_CAN1_EC_TEC_7_0_Pos 0 /*!< C_CAN1 EC: TEC_7_0 Position */\r
-#define C_CAN1_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos) /*!< C_CAN1 EC: TEC_7_0 Mask */\r
-#define C_CAN1_EC_REC_6_0_Pos 8 /*!< C_CAN1 EC: REC_6_0 Position */\r
-#define C_CAN1_EC_REC_6_0_Msk (0x7fUL << C_CAN1_EC_REC_6_0_Pos) /*!< C_CAN1 EC: REC_6_0 Mask */\r
-#define C_CAN1_EC_RP_Pos 15 /*!< C_CAN1 EC: RP Position */\r
-#define C_CAN1_EC_RP_Msk (0x01UL << C_CAN1_EC_RP_Pos) /*!< C_CAN1 EC: RP Mask */\r
-\r
-// ---------------------------------------- C_CAN1_BT -------------------------------------------\r
-#define C_CAN1_BT_BRP_Pos 0 /*!< C_CAN1 BT: BRP Position */\r
-#define C_CAN1_BT_BRP_Msk (0x3fUL << C_CAN1_BT_BRP_Pos) /*!< C_CAN1 BT: BRP Mask */\r
-#define C_CAN1_BT_SJW_Pos 6 /*!< C_CAN1 BT: SJW Position */\r
-#define C_CAN1_BT_SJW_Msk (0x03UL << C_CAN1_BT_SJW_Pos) /*!< C_CAN1 BT: SJW Mask */\r
-#define C_CAN1_BT_TSEG1_Pos 8 /*!< C_CAN1 BT: TSEG1 Position */\r
-#define C_CAN1_BT_TSEG1_Msk (0x0fUL << C_CAN1_BT_TSEG1_Pos) /*!< C_CAN1 BT: TSEG1 Mask */\r
-#define C_CAN1_BT_TSEG2_Pos 12 /*!< C_CAN1 BT: TSEG2 Position */\r
-#define C_CAN1_BT_TSEG2_Msk (0x07UL << C_CAN1_BT_TSEG2_Pos) /*!< C_CAN1 BT: TSEG2 Mask */\r
-\r
-// --------------------------------------- C_CAN1_INT -------------------------------------------\r
-#define C_CAN1_INT_INTID15_0_Pos 0 /*!< C_CAN1 INT: INTID15_0 Position */\r
-#define C_CAN1_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos) /*!< C_CAN1 INT: INTID15_0 Mask */\r
-\r
-// --------------------------------------- C_CAN1_TEST ------------------------------------------\r
-#define C_CAN1_TEST_BASIC_Pos 2 /*!< C_CAN1 TEST: BASIC Position */\r
-#define C_CAN1_TEST_BASIC_Msk (0x01UL << C_CAN1_TEST_BASIC_Pos) /*!< C_CAN1 TEST: BASIC Mask */\r
-#define C_CAN1_TEST_SILENT_Pos 3 /*!< C_CAN1 TEST: SILENT Position */\r
-#define C_CAN1_TEST_SILENT_Msk (0x01UL << C_CAN1_TEST_SILENT_Pos) /*!< C_CAN1 TEST: SILENT Mask */\r
-#define C_CAN1_TEST_LBACK_Pos 4 /*!< C_CAN1 TEST: LBACK Position */\r
-#define C_CAN1_TEST_LBACK_Msk (0x01UL << C_CAN1_TEST_LBACK_Pos) /*!< C_CAN1 TEST: LBACK Mask */\r
-#define C_CAN1_TEST_TX1_0_Pos 5 /*!< C_CAN1 TEST: TX1_0 Position */\r
-#define C_CAN1_TEST_TX1_0_Msk (0x03UL << C_CAN1_TEST_TX1_0_Pos) /*!< C_CAN1 TEST: TX1_0 Mask */\r
-#define C_CAN1_TEST_RX_Pos 7 /*!< C_CAN1 TEST: RX Position */\r
-#define C_CAN1_TEST_RX_Msk (0x01UL << C_CAN1_TEST_RX_Pos) /*!< C_CAN1 TEST: RX Mask */\r
-\r
-// --------------------------------------- C_CAN1_BRPE ------------------------------------------\r
-#define C_CAN1_BRPE_BRPE_Pos 0 /*!< C_CAN1 BRPE: BRPE Position */\r
-#define C_CAN1_BRPE_BRPE_Msk (0x0fUL << C_CAN1_BRPE_BRPE_Pos) /*!< C_CAN1 BRPE: BRPE Mask */\r
-\r
-// ------------------------------------ C_CAN1_IF1_CMDREQ ---------------------------------------\r
-#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */\r
-#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask */\r
-#define C_CAN1_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF1_CMDREQ: BUSY Position */\r
-#define C_CAN1_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF1_CMDREQ: BUSY Mask */\r
-\r
-// ----------------------------------- C_CAN1_IF1_CMDMSK_W --------------------------------------\r
-#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */\r
-#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask */\r
-#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */\r
-#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask */\r
-#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */\r
-#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask */\r
-#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */\r
-#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */\r
-#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position */\r
-#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask */\r
-#define C_CAN1_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_W: ARB Position */\r
-#define C_CAN1_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask */\r
-#define C_CAN1_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_W: MASK Position */\r
-#define C_CAN1_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask */\r
-#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */\r
-#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask */\r
-\r
-// ----------------------------------- C_CAN1_IF1_CMDMSK_R --------------------------------------\r
-#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */\r
-#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask */\r
-#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */\r
-#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask */\r
-#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */\r
-#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask */\r
-#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */\r
-#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */\r
-#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position */\r
-#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask */\r
-#define C_CAN1_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_R: ARB Position */\r
-#define C_CAN1_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask */\r
-#define C_CAN1_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_R: MASK Position */\r
-#define C_CAN1_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask */\r
-#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */\r
-#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF1_MSK1 ----------------------------------------\r
-#define C_CAN1_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF1_MSK1: MSK15_0 Position */\r
-#define C_CAN1_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF1_MSK2 ----------------------------------------\r
-#define C_CAN1_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF1_MSK2: MSK28_16 Position */\r
-#define C_CAN1_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask */\r
-#define C_CAN1_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF1_MSK2: MDIR Position */\r
-#define C_CAN1_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos) /*!< C_CAN1 IF1_MSK2: MDIR Mask */\r
-#define C_CAN1_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF1_MSK2: MXTD Position */\r
-#define C_CAN1_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos) /*!< C_CAN1 IF1_MSK2: MXTD Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF1_ARB1 ----------------------------------------\r
-#define C_CAN1_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF1_ARB1: ID15_0 Position */\r
-#define C_CAN1_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos) /*!< C_CAN1 IF1_ARB1: ID15_0 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF1_ARB2 ----------------------------------------\r
-#define C_CAN1_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF1_ARB2: ID28_16 Position */\r
-#define C_CAN1_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos) /*!< C_CAN1 IF1_ARB2: ID28_16 Mask */\r
-#define C_CAN1_IF1_ARB2_DIR_Pos 13 /*!< C_CAN1 IF1_ARB2: DIR Position */\r
-#define C_CAN1_IF1_ARB2_DIR_Msk (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos) /*!< C_CAN1 IF1_ARB2: DIR Mask */\r
-#define C_CAN1_IF1_ARB2_XTD_Pos 14 /*!< C_CAN1 IF1_ARB2: XTD Position */\r
-#define C_CAN1_IF1_ARB2_XTD_Msk (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos) /*!< C_CAN1 IF1_ARB2: XTD Mask */\r
-#define C_CAN1_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF1_ARB2: MSGVAL Position */\r
-#define C_CAN1_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF1_ARB2: MSGVAL Mask */\r
-\r
-// ------------------------------------ C_CAN1_IF1_MCTRL ----------------------------------------\r
-#define C_CAN1_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position */\r
-#define C_CAN1_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask */\r
-#define C_CAN1_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF1_MCTRL: EOB Position */\r
-#define C_CAN1_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos) /*!< C_CAN1 IF1_MCTRL: EOB Mask */\r
-#define C_CAN1_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF1_MCTRL: TXRQST Position */\r
-#define C_CAN1_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF1_MCTRL: TXRQST Mask */\r
-#define C_CAN1_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF1_MCTRL: RMTEN Position */\r
-#define C_CAN1_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF1_MCTRL: RMTEN Mask */\r
-#define C_CAN1_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF1_MCTRL: RXIE Position */\r
-#define C_CAN1_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos) /*!< C_CAN1 IF1_MCTRL: RXIE Mask */\r
-#define C_CAN1_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF1_MCTRL: TXIE Position */\r
-#define C_CAN1_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos) /*!< C_CAN1 IF1_MCTRL: TXIE Mask */\r
-#define C_CAN1_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF1_MCTRL: UMASK Position */\r
-#define C_CAN1_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos) /*!< C_CAN1 IF1_MCTRL: UMASK Mask */\r
-#define C_CAN1_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF1_MCTRL: INTPND Position */\r
-#define C_CAN1_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos) /*!< C_CAN1 IF1_MCTRL: INTPND Mask */\r
-#define C_CAN1_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF1_MCTRL: MSGLST Position */\r
-#define C_CAN1_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF1_MCTRL: MSGLST Mask */\r
-#define C_CAN1_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF1_MCTRL: NEWDAT Position */\r
-#define C_CAN1_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF1_DA1 -----------------------------------------\r
-#define C_CAN1_IF1_DA1_DATA0_Pos 0 /*!< C_CAN1 IF1_DA1: DATA0 Position */\r
-#define C_CAN1_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos) /*!< C_CAN1 IF1_DA1: DATA0 Mask */\r
-#define C_CAN1_IF1_DA1_DATA1_Pos 8 /*!< C_CAN1 IF1_DA1: DATA1 Position */\r
-#define C_CAN1_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos) /*!< C_CAN1 IF1_DA1: DATA1 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF1_DA2 -----------------------------------------\r
-#define C_CAN1_IF1_DA2_DATA2_Pos 0 /*!< C_CAN1 IF1_DA2: DATA2 Position */\r
-#define C_CAN1_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos) /*!< C_CAN1 IF1_DA2: DATA2 Mask */\r
-#define C_CAN1_IF1_DA2_DATA3_Pos 8 /*!< C_CAN1 IF1_DA2: DATA3 Position */\r
-#define C_CAN1_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos) /*!< C_CAN1 IF1_DA2: DATA3 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF1_DB1 -----------------------------------------\r
-#define C_CAN1_IF1_DB1_DATA4_Pos 0 /*!< C_CAN1 IF1_DB1: DATA4 Position */\r
-#define C_CAN1_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos) /*!< C_CAN1 IF1_DB1: DATA4 Mask */\r
-#define C_CAN1_IF1_DB1_DATA5_Pos 8 /*!< C_CAN1 IF1_DB1: DATA5 Position */\r
-#define C_CAN1_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos) /*!< C_CAN1 IF1_DB1: DATA5 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF1_DB2 -----------------------------------------\r
-#define C_CAN1_IF1_DB2_DATA6_Pos 0 /*!< C_CAN1 IF1_DB2: DATA6 Position */\r
-#define C_CAN1_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos) /*!< C_CAN1 IF1_DB2: DATA6 Mask */\r
-#define C_CAN1_IF1_DB2_DATA7_Pos 8 /*!< C_CAN1 IF1_DB2: DATA7 Position */\r
-#define C_CAN1_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos) /*!< C_CAN1 IF1_DB2: DATA7 Mask */\r
-\r
-// ------------------------------------ C_CAN1_IF2_CMDREQ ---------------------------------------\r
-#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */\r
-#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask */\r
-#define C_CAN1_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF2_CMDREQ: BUSY Position */\r
-#define C_CAN1_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF2_CMDREQ: BUSY Mask */\r
-\r
-// ----------------------------------- C_CAN1_IF2_CMDMSK_W --------------------------------------\r
-#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */\r
-#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask */\r
-#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */\r
-#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask */\r
-#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */\r
-#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask */\r
-#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */\r
-#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */\r
-#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position */\r
-#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask */\r
-#define C_CAN1_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_W: ARB Position */\r
-#define C_CAN1_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask */\r
-#define C_CAN1_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_W: MASK Position */\r
-#define C_CAN1_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask */\r
-#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */\r
-#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask */\r
-\r
-// ----------------------------------- C_CAN1_IF2_CMDMSK_R --------------------------------------\r
-#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */\r
-#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask */\r
-#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */\r
-#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask */\r
-#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */\r
-#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask */\r
-#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */\r
-#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */\r
-#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position */\r
-#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask */\r
-#define C_CAN1_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_R: ARB Position */\r
-#define C_CAN1_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask */\r
-#define C_CAN1_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_R: MASK Position */\r
-#define C_CAN1_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask */\r
-#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */\r
-#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF2_MSK1 ----------------------------------------\r
-#define C_CAN1_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF2_MSK1: MSK15_0 Position */\r
-#define C_CAN1_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF2_MSK2 ----------------------------------------\r
-#define C_CAN1_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF2_MSK2: MSK28_16 Position */\r
-#define C_CAN1_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask */\r
-#define C_CAN1_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF2_MSK2: MDIR Position */\r
-#define C_CAN1_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos) /*!< C_CAN1 IF2_MSK2: MDIR Mask */\r
-#define C_CAN1_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF2_MSK2: MXTD Position */\r
-#define C_CAN1_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos) /*!< C_CAN1 IF2_MSK2: MXTD Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF2_ARB1 ----------------------------------------\r
-#define C_CAN1_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF2_ARB1: ID15_0 Position */\r
-#define C_CAN1_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos) /*!< C_CAN1 IF2_ARB1: ID15_0 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF2_ARB2 ----------------------------------------\r
-#define C_CAN1_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF2_ARB2: ID28_16 Position */\r
-#define C_CAN1_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos) /*!< C_CAN1 IF2_ARB2: ID28_16 Mask */\r
-#define C_CAN1_IF2_ARB2_DIR_Pos 13 /*!< C_CAN1 IF2_ARB2: DIR Position */\r
-#define C_CAN1_IF2_ARB2_DIR_Msk (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos) /*!< C_CAN1 IF2_ARB2: DIR Mask */\r
-#define C_CAN1_IF2_ARB2_XTD_Pos 14 /*!< C_CAN1 IF2_ARB2: XTD Position */\r
-#define C_CAN1_IF2_ARB2_XTD_Msk (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos) /*!< C_CAN1 IF2_ARB2: XTD Mask */\r
-#define C_CAN1_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF2_ARB2: MSGVAL Position */\r
-#define C_CAN1_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF2_ARB2: MSGVAL Mask */\r
-\r
-// ------------------------------------ C_CAN1_IF2_MCTRL ----------------------------------------\r
-#define C_CAN1_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position */\r
-#define C_CAN1_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask */\r
-#define C_CAN1_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF2_MCTRL: EOB Position */\r
-#define C_CAN1_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos) /*!< C_CAN1 IF2_MCTRL: EOB Mask */\r
-#define C_CAN1_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF2_MCTRL: TXRQST Position */\r
-#define C_CAN1_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF2_MCTRL: TXRQST Mask */\r
-#define C_CAN1_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF2_MCTRL: RMTEN Position */\r
-#define C_CAN1_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF2_MCTRL: RMTEN Mask */\r
-#define C_CAN1_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF2_MCTRL: RXIE Position */\r
-#define C_CAN1_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos) /*!< C_CAN1 IF2_MCTRL: RXIE Mask */\r
-#define C_CAN1_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF2_MCTRL: TXIE Position */\r
-#define C_CAN1_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos) /*!< C_CAN1 IF2_MCTRL: TXIE Mask */\r
-#define C_CAN1_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF2_MCTRL: UMASK Position */\r
-#define C_CAN1_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos) /*!< C_CAN1 IF2_MCTRL: UMASK Mask */\r
-#define C_CAN1_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF2_MCTRL: INTPND Position */\r
-#define C_CAN1_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos) /*!< C_CAN1 IF2_MCTRL: INTPND Mask */\r
-#define C_CAN1_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF2_MCTRL: MSGLST Position */\r
-#define C_CAN1_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF2_MCTRL: MSGLST Mask */\r
-#define C_CAN1_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF2_MCTRL: NEWDAT Position */\r
-#define C_CAN1_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF2_DA1 -----------------------------------------\r
-#define C_CAN1_IF2_DA1_DATA0_Pos 0 /*!< C_CAN1 IF2_DA1: DATA0 Position */\r
-#define C_CAN1_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos) /*!< C_CAN1 IF2_DA1: DATA0 Mask */\r
-#define C_CAN1_IF2_DA1_DATA1_Pos 8 /*!< C_CAN1 IF2_DA1: DATA1 Position */\r
-#define C_CAN1_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos) /*!< C_CAN1 IF2_DA1: DATA1 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF2_DA2 -----------------------------------------\r
-#define C_CAN1_IF2_DA2_DATA2_Pos 0 /*!< C_CAN1 IF2_DA2: DATA2 Position */\r
-#define C_CAN1_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos) /*!< C_CAN1 IF2_DA2: DATA2 Mask */\r
-#define C_CAN1_IF2_DA2_DATA3_Pos 8 /*!< C_CAN1 IF2_DA2: DATA3 Position */\r
-#define C_CAN1_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos) /*!< C_CAN1 IF2_DA2: DATA3 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF2_DB1 -----------------------------------------\r
-#define C_CAN1_IF2_DB1_DATA4_Pos 0 /*!< C_CAN1 IF2_DB1: DATA4 Position */\r
-#define C_CAN1_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos) /*!< C_CAN1 IF2_DB1: DATA4 Mask */\r
-#define C_CAN1_IF2_DB1_DATA5_Pos 8 /*!< C_CAN1 IF2_DB1: DATA5 Position */\r
-#define C_CAN1_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos) /*!< C_CAN1 IF2_DB1: DATA5 Mask */\r
-\r
-// ------------------------------------- C_CAN1_IF2_DB2 -----------------------------------------\r
-#define C_CAN1_IF2_DB2_DATA6_Pos 0 /*!< C_CAN1 IF2_DB2: DATA6 Position */\r
-#define C_CAN1_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos) /*!< C_CAN1 IF2_DB2: DATA6 Mask */\r
-#define C_CAN1_IF2_DB2_DATA7_Pos 8 /*!< C_CAN1 IF2_DB2: DATA7 Position */\r
-#define C_CAN1_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos) /*!< C_CAN1 IF2_DB2: DATA7 Mask */\r
-\r
-// -------------------------------------- C_CAN1_TXREQ1 -----------------------------------------\r
-#define C_CAN1_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN1 TXREQ1: TXRQST16_1 Position */\r
-#define C_CAN1_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask */\r
-\r
-// -------------------------------------- C_CAN1_TXREQ2 -----------------------------------------\r
-#define C_CAN1_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */\r
-#define C_CAN1_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask */\r
-\r
-// --------------------------------------- C_CAN1_ND1 -------------------------------------------\r
-#define C_CAN1_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN1 ND1: NEWDAT16_1 Position */\r
-#define C_CAN1_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos) /*!< C_CAN1 ND1: NEWDAT16_1 Mask */\r
-\r
-// --------------------------------------- C_CAN1_ND2 -------------------------------------------\r
-#define C_CAN1_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN1 ND2: NEWDAT32_17 Position */\r
-#define C_CAN1_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos) /*!< C_CAN1 ND2: NEWDAT32_17 Mask */\r
-\r
-// --------------------------------------- C_CAN1_IR1 -------------------------------------------\r
-#define C_CAN1_IR1_INTPND16_1_Pos 0 /*!< C_CAN1 IR1: INTPND16_1 Position */\r
-#define C_CAN1_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos) /*!< C_CAN1 IR1: INTPND16_1 Mask */\r
-\r
-// --------------------------------------- C_CAN1_IR2 -------------------------------------------\r
-#define C_CAN1_IR2_INTPND32_17_Pos 0 /*!< C_CAN1 IR2: INTPND32_17 Position */\r
-#define C_CAN1_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos) /*!< C_CAN1 IR2: INTPND32_17 Mask */\r
-\r
-// -------------------------------------- C_CAN1_MSGV1 ------------------------------------------\r
-#define C_CAN1_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN1 MSGV1: MSGVAL16_1 Position */\r
-#define C_CAN1_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask */\r
-\r
-// -------------------------------------- C_CAN1_MSGV2 ------------------------------------------\r
-#define C_CAN1_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN1 MSGV2: MSGVAL32_17 Position */\r
-#define C_CAN1_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask */\r
-\r
-// -------------------------------------- C_CAN1_CLKDIV -----------------------------------------\r
-#define C_CAN1_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN1 CLKDIV: CLKDIVVAL Position */\r
-#define C_CAN1_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- RITIMER Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ------------------------------------- RITIMER_COMPVAL ----------------------------------------\r
-#define RITIMER_COMPVAL_RICOMP_Pos 0 /*!< RITIMER COMPVAL: RICOMP Position */\r
-#define RITIMER_COMPVAL_RICOMP_Msk (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos) /*!< RITIMER COMPVAL: RICOMP Mask */\r
-\r
-// -------------------------------------- RITIMER_MASK ------------------------------------------\r
-#define RITIMER_MASK_RIMASK_Pos 0 /*!< RITIMER MASK: RIMASK Position */\r
-#define RITIMER_MASK_RIMASK_Msk (0xffffffffUL << RITIMER_MASK_RIMASK_Pos) /*!< RITIMER MASK: RIMASK Mask */\r
-\r
-// -------------------------------------- RITIMER_CTRL ------------------------------------------\r
-#define RITIMER_CTRL_RITINT_Pos 0 /*!< RITIMER CTRL: RITINT Position */\r
-#define RITIMER_CTRL_RITINT_Msk (0x01UL << RITIMER_CTRL_RITINT_Pos) /*!< RITIMER CTRL: RITINT Mask */\r
-#define RITIMER_CTRL_RITENCLR_Pos 1 /*!< RITIMER CTRL: RITENCLR Position */\r
-#define RITIMER_CTRL_RITENCLR_Msk (0x01UL << RITIMER_CTRL_RITENCLR_Pos) /*!< RITIMER CTRL: RITENCLR Mask */\r
-#define RITIMER_CTRL_RITENBR_Pos 2 /*!< RITIMER CTRL: RITENBR Position */\r
-#define RITIMER_CTRL_RITENBR_Msk (0x01UL << RITIMER_CTRL_RITENBR_Pos) /*!< RITIMER CTRL: RITENBR Mask */\r
-#define RITIMER_CTRL_RITEN_Pos 3 /*!< RITIMER CTRL: RITEN Position */\r
-#define RITIMER_CTRL_RITEN_Msk (0x01UL << RITIMER_CTRL_RITEN_Pos) /*!< RITIMER CTRL: RITEN Mask */\r
-\r
-// ------------------------------------- RITIMER_COUNTER ----------------------------------------\r
-#define RITIMER_COUNTER_RICOUNTER_Pos 0 /*!< RITIMER COUNTER: RICOUNTER Position */\r
-#define RITIMER_COUNTER_RICOUNTER_Msk (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos) /*!< RITIMER COUNTER: RICOUNTER Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- QEI Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------- QEI_CON --------------------------------------------\r
-#define QEI_CON_RESP_Pos 0 /*!< QEI CON: RESP Position */\r
-#define QEI_CON_RESP_Msk (0x01UL << QEI_CON_RESP_Pos) /*!< QEI CON: RESP Mask */\r
-#define QEI_CON_RESPI_Pos 1 /*!< QEI CON: RESPI Position */\r
-#define QEI_CON_RESPI_Msk (0x01UL << QEI_CON_RESPI_Pos) /*!< QEI CON: RESPI Mask */\r
-#define QEI_CON_RESV_Pos 2 /*!< QEI CON: RESV Position */\r
-#define QEI_CON_RESV_Msk (0x01UL << QEI_CON_RESV_Pos) /*!< QEI CON: RESV Mask */\r
-#define QEI_CON_RESI_Pos 3 /*!< QEI CON: RESI Position */\r
-#define QEI_CON_RESI_Msk (0x01UL << QEI_CON_RESI_Pos) /*!< QEI CON: RESI Mask */\r
-\r
-// ---------------------------------------- QEI_STAT --------------------------------------------\r
-#define QEI_STAT_DIR_Pos 0 /*!< QEI STAT: DIR Position */\r
-#define QEI_STAT_DIR_Msk (0x01UL << QEI_STAT_DIR_Pos) /*!< QEI STAT: DIR Mask */\r
-\r
-// ---------------------------------------- QEI_CONF --------------------------------------------\r
-#define QEI_CONF_DIRINV_Pos 0 /*!< QEI CONF: DIRINV Position */\r
-#define QEI_CONF_DIRINV_Msk (0x01UL << QEI_CONF_DIRINV_Pos) /*!< QEI CONF: DIRINV Mask */\r
-#define QEI_CONF_SIGMODE_Pos 1 /*!< QEI CONF: SIGMODE Position */\r
-#define QEI_CONF_SIGMODE_Msk (0x01UL << QEI_CONF_SIGMODE_Pos) /*!< QEI CONF: SIGMODE Mask */\r
-#define QEI_CONF_CAPMODE_Pos 2 /*!< QEI CONF: CAPMODE Position */\r
-#define QEI_CONF_CAPMODE_Msk (0x01UL << QEI_CONF_CAPMODE_Pos) /*!< QEI CONF: CAPMODE Mask */\r
-#define QEI_CONF_INVINX_Pos 3 /*!< QEI CONF: INVINX Position */\r
-#define QEI_CONF_INVINX_Msk (0x01UL << QEI_CONF_INVINX_Pos) /*!< QEI CONF: INVINX Mask */\r
-#define QEI_CONF_CRESPI_Pos 4 /*!< QEI CONF: CRESPI Position */\r
-#define QEI_CONF_CRESPI_Msk (0x01UL << QEI_CONF_CRESPI_Pos) /*!< QEI CONF: CRESPI Mask */\r
-#define QEI_CONF_INXGATE_Pos 16 /*!< QEI CONF: INXGATE Position */\r
-#define QEI_CONF_INXGATE_Msk (0x0fUL << QEI_CONF_INXGATE_Pos) /*!< QEI CONF: INXGATE Mask */\r
-\r
-// ----------------------------------------- QEI_POS --------------------------------------------\r
-#define QEI_POS_POS_Pos 0 /*!< QEI POS: POS Position */\r
-#define QEI_POS_POS_Msk (0xffffffffUL << QEI_POS_POS_Pos) /*!< QEI POS: POS Mask */\r
-\r
-// --------------------------------------- QEI_MAXPOS -------------------------------------------\r
-#define QEI_MAXPOS_MAXPOS_Pos 0 /*!< QEI MAXPOS: MAXPOS Position */\r
-#define QEI_MAXPOS_MAXPOS_Msk (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos) /*!< QEI MAXPOS: MAXPOS Mask */\r
-\r
-// --------------------------------------- QEI_CMPOS0 -------------------------------------------\r
-#define QEI_CMPOS0_PCMP0_Pos 0 /*!< QEI CMPOS0: PCMP0 Position */\r
-#define QEI_CMPOS0_PCMP0_Msk (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos) /*!< QEI CMPOS0: PCMP0 Mask */\r
-\r
-// --------------------------------------- QEI_CMPOS1 -------------------------------------------\r
-#define QEI_CMPOS1_PCMP1_Pos 0 /*!< QEI CMPOS1: PCMP1 Position */\r
-#define QEI_CMPOS1_PCMP1_Msk (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos) /*!< QEI CMPOS1: PCMP1 Mask */\r
-\r
-// --------------------------------------- QEI_CMPOS2 -------------------------------------------\r
-#define QEI_CMPOS2_PCMP2_Pos 0 /*!< QEI CMPOS2: PCMP2 Position */\r
-#define QEI_CMPOS2_PCMP2_Msk (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos) /*!< QEI CMPOS2: PCMP2 Mask */\r
-\r
-// --------------------------------------- QEI_INXCNT -------------------------------------------\r
-#define QEI_INXCNT_ENCPOS_Pos 0 /*!< QEI INXCNT: ENCPOS Position */\r
-#define QEI_INXCNT_ENCPOS_Msk (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos) /*!< QEI INXCNT: ENCPOS Mask */\r
-\r
-// --------------------------------------- QEI_INXCMP0 ------------------------------------------\r
-#define QEI_INXCMP0_ICMP0_Pos 0 /*!< QEI INXCMP0: ICMP0 Position */\r
-#define QEI_INXCMP0_ICMP0_Msk (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos) /*!< QEI INXCMP0: ICMP0 Mask */\r
-\r
-// ---------------------------------------- QEI_LOAD --------------------------------------------\r
-#define QEI_LOAD_VELLOAD_Pos 0 /*!< QEI LOAD: VELLOAD Position */\r
-#define QEI_LOAD_VELLOAD_Msk (0xffffffffUL << QEI_LOAD_VELLOAD_Pos) /*!< QEI LOAD: VELLOAD Mask */\r
-\r
-// ---------------------------------------- QEI_TIME --------------------------------------------\r
-#define QEI_TIME_VELVAL_Pos 0 /*!< QEI TIME: VELVAL Position */\r
-#define QEI_TIME_VELVAL_Msk (0xffffffffUL << QEI_TIME_VELVAL_Pos) /*!< QEI TIME: VELVAL Mask */\r
-\r
-// ----------------------------------------- QEI_VEL --------------------------------------------\r
-#define QEI_VEL_VELPC_Pos 0 /*!< QEI VEL: VELPC Position */\r
-#define QEI_VEL_VELPC_Msk (0xffffffffUL << QEI_VEL_VELPC_Pos) /*!< QEI VEL: VELPC Mask */\r
-\r
-// ----------------------------------------- QEI_CAP --------------------------------------------\r
-#define QEI_CAP_VELCAP_Pos 0 /*!< QEI CAP: VELCAP Position */\r
-#define QEI_CAP_VELCAP_Msk (0xffffffffUL << QEI_CAP_VELCAP_Pos) /*!< QEI CAP: VELCAP Mask */\r
-\r
-// --------------------------------------- QEI_VELCOMP ------------------------------------------\r
-#define QEI_VELCOMP_VELCMP_Pos 0 /*!< QEI VELCOMP: VELCMP Position */\r
-#define QEI_VELCOMP_VELCMP_Msk (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos) /*!< QEI VELCOMP: VELCMP Mask */\r
-\r
-// -------------------------------------- QEI_FILTERPHA -----------------------------------------\r
-#define QEI_FILTERPHA_FILTA_Pos 0 /*!< QEI FILTERPHA: FILTA Position */\r
-#define QEI_FILTERPHA_FILTA_Msk (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos) /*!< QEI FILTERPHA: FILTA Mask */\r
-\r
-// -------------------------------------- QEI_FILTERPHB -----------------------------------------\r
-#define QEI_FILTERPHB_FILTB_Pos 0 /*!< QEI FILTERPHB: FILTB Position */\r
-#define QEI_FILTERPHB_FILTB_Msk (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos) /*!< QEI FILTERPHB: FILTB Mask */\r
-\r
-// -------------------------------------- QEI_FILTERINX -----------------------------------------\r
-#define QEI_FILTERINX_FITLINX_Pos 0 /*!< QEI FILTERINX: FITLINX Position */\r
-#define QEI_FILTERINX_FITLINX_Msk (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos) /*!< QEI FILTERINX: FITLINX Mask */\r
-\r
-// --------------------------------------- QEI_WINDOW -------------------------------------------\r
-#define QEI_WINDOW_WINDOW_Pos 0 /*!< QEI WINDOW: WINDOW Position */\r
-#define QEI_WINDOW_WINDOW_Msk (0xffffffffUL << QEI_WINDOW_WINDOW_Pos) /*!< QEI WINDOW: WINDOW Mask */\r
-\r
-// --------------------------------------- QEI_INXCMP1 ------------------------------------------\r
-#define QEI_INXCMP1_ICMP1_Pos 0 /*!< QEI INXCMP1: ICMP1 Position */\r
-#define QEI_INXCMP1_ICMP1_Msk (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos) /*!< QEI INXCMP1: ICMP1 Mask */\r
-\r
-// --------------------------------------- QEI_INXCMP2 ------------------------------------------\r
-#define QEI_INXCMP2_ICMP2_Pos 0 /*!< QEI INXCMP2: ICMP2 Position */\r
-#define QEI_INXCMP2_ICMP2_Msk (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos) /*!< QEI INXCMP2: ICMP2 Mask */\r
-\r
-// ----------------------------------------- QEI_IEC --------------------------------------------\r
-#define QEI_IEC_INX_EN_Pos 0 /*!< QEI IEC: INX_EN Position */\r
-#define QEI_IEC_INX_EN_Msk (0x01UL << QEI_IEC_INX_EN_Pos) /*!< QEI IEC: INX_EN Mask */\r
-#define QEI_IEC_TIM_EN_Pos 1 /*!< QEI IEC: TIM_EN Position */\r
-#define QEI_IEC_TIM_EN_Msk (0x01UL << QEI_IEC_TIM_EN_Pos) /*!< QEI IEC: TIM_EN Mask */\r
-#define QEI_IEC_VELC_EN_Pos 2 /*!< QEI IEC: VELC_EN Position */\r
-#define QEI_IEC_VELC_EN_Msk (0x01UL << QEI_IEC_VELC_EN_Pos) /*!< QEI IEC: VELC_EN Mask */\r
-#define QEI_IEC_DIR_EN_Pos 3 /*!< QEI IEC: DIR_EN Position */\r
-#define QEI_IEC_DIR_EN_Msk (0x01UL << QEI_IEC_DIR_EN_Pos) /*!< QEI IEC: DIR_EN Mask */\r
-#define QEI_IEC_ERR_EN_Pos 4 /*!< QEI IEC: ERR_EN Position */\r
-#define QEI_IEC_ERR_EN_Msk (0x01UL << QEI_IEC_ERR_EN_Pos) /*!< QEI IEC: ERR_EN Mask */\r
-#define QEI_IEC_ENCLK_EN_Pos 5 /*!< QEI IEC: ENCLK_EN Position */\r
-#define QEI_IEC_ENCLK_EN_Msk (0x01UL << QEI_IEC_ENCLK_EN_Pos) /*!< QEI IEC: ENCLK_EN Mask */\r
-#define QEI_IEC_POS0_Int_Pos 6 /*!< QEI IEC: POS0_Int Position */\r
-#define QEI_IEC_POS0_Int_Msk (0x01UL << QEI_IEC_POS0_Int_Pos) /*!< QEI IEC: POS0_Int Mask */\r
-#define QEI_IEC_POS1_Int_Pos 7 /*!< QEI IEC: POS1_Int Position */\r
-#define QEI_IEC_POS1_Int_Msk (0x01UL << QEI_IEC_POS1_Int_Pos) /*!< QEI IEC: POS1_Int Mask */\r
-#define QEI_IEC_POS2_Int_Pos 8 /*!< QEI IEC: POS2_Int Position */\r
-#define QEI_IEC_POS2_Int_Msk (0x01UL << QEI_IEC_POS2_Int_Pos) /*!< QEI IEC: POS2_Int Mask */\r
-#define QEI_IEC_REV_Int_Pos 9 /*!< QEI IEC: REV_Int Position */\r
-#define QEI_IEC_REV_Int_Msk (0x01UL << QEI_IEC_REV_Int_Pos) /*!< QEI IEC: REV_Int Mask */\r
-#define QEI_IEC_POS0REV_Int_Pos 10 /*!< QEI IEC: POS0REV_Int Position */\r
-#define QEI_IEC_POS0REV_Int_Msk (0x01UL << QEI_IEC_POS0REV_Int_Pos) /*!< QEI IEC: POS0REV_Int Mask */\r
-#define QEI_IEC_POS1REV_Int_Pos 11 /*!< QEI IEC: POS1REV_Int Position */\r
-#define QEI_IEC_POS1REV_Int_Msk (0x01UL << QEI_IEC_POS1REV_Int_Pos) /*!< QEI IEC: POS1REV_Int Mask */\r
-#define QEI_IEC_POS2REV_Int_Pos 12 /*!< QEI IEC: POS2REV_Int Position */\r
-#define QEI_IEC_POS2REV_Int_Msk (0x01UL << QEI_IEC_POS2REV_Int_Pos) /*!< QEI IEC: POS2REV_Int Mask */\r
-#define QEI_IEC_REV1_Int_Pos 13 /*!< QEI IEC: REV1_Int Position */\r
-#define QEI_IEC_REV1_Int_Msk (0x01UL << QEI_IEC_REV1_Int_Pos) /*!< QEI IEC: REV1_Int Mask */\r
-#define QEI_IEC_REV2_Int_Pos 14 /*!< QEI IEC: REV2_Int Position */\r
-#define QEI_IEC_REV2_Int_Msk (0x01UL << QEI_IEC_REV2_Int_Pos) /*!< QEI IEC: REV2_Int Mask */\r
-#define QEI_IEC_MAXPOS_Int_Pos 15 /*!< QEI IEC: MAXPOS_Int Position */\r
-#define QEI_IEC_MAXPOS_Int_Msk (0x01UL << QEI_IEC_MAXPOS_Int_Pos) /*!< QEI IEC: MAXPOS_Int Mask */\r
-\r
-// ----------------------------------------- QEI_IES --------------------------------------------\r
-#define QEI_IES_INX_EN_Pos 0 /*!< QEI IES: INX_EN Position */\r
-#define QEI_IES_INX_EN_Msk (0x01UL << QEI_IES_INX_EN_Pos) /*!< QEI IES: INX_EN Mask */\r
-#define QEI_IES_TIM_EN_Pos 1 /*!< QEI IES: TIM_EN Position */\r
-#define QEI_IES_TIM_EN_Msk (0x01UL << QEI_IES_TIM_EN_Pos) /*!< QEI IES: TIM_EN Mask */\r
-#define QEI_IES_VELC_EN_Pos 2 /*!< QEI IES: VELC_EN Position */\r
-#define QEI_IES_VELC_EN_Msk (0x01UL << QEI_IES_VELC_EN_Pos) /*!< QEI IES: VELC_EN Mask */\r
-#define QEI_IES_DIR_EN_Pos 3 /*!< QEI IES: DIR_EN Position */\r
-#define QEI_IES_DIR_EN_Msk (0x01UL << QEI_IES_DIR_EN_Pos) /*!< QEI IES: DIR_EN Mask */\r
-#define QEI_IES_ERR_EN_Pos 4 /*!< QEI IES: ERR_EN Position */\r
-#define QEI_IES_ERR_EN_Msk (0x01UL << QEI_IES_ERR_EN_Pos) /*!< QEI IES: ERR_EN Mask */\r
-#define QEI_IES_ENCLK_EN_Pos 5 /*!< QEI IES: ENCLK_EN Position */\r
-#define QEI_IES_ENCLK_EN_Msk (0x01UL << QEI_IES_ENCLK_EN_Pos) /*!< QEI IES: ENCLK_EN Mask */\r
-#define QEI_IES_POS0_Int_Pos 6 /*!< QEI IES: POS0_Int Position */\r
-#define QEI_IES_POS0_Int_Msk (0x01UL << QEI_IES_POS0_Int_Pos) /*!< QEI IES: POS0_Int Mask */\r
-#define QEI_IES_POS1_Int_Pos 7 /*!< QEI IES: POS1_Int Position */\r
-#define QEI_IES_POS1_Int_Msk (0x01UL << QEI_IES_POS1_Int_Pos) /*!< QEI IES: POS1_Int Mask */\r
-#define QEI_IES_POS2_Int_Pos 8 /*!< QEI IES: POS2_Int Position */\r
-#define QEI_IES_POS2_Int_Msk (0x01UL << QEI_IES_POS2_Int_Pos) /*!< QEI IES: POS2_Int Mask */\r
-#define QEI_IES_REV_Int_Pos 9 /*!< QEI IES: REV_Int Position */\r
-#define QEI_IES_REV_Int_Msk (0x01UL << QEI_IES_REV_Int_Pos) /*!< QEI IES: REV_Int Mask */\r
-#define QEI_IES_POS0REV_Int_Pos 10 /*!< QEI IES: POS0REV_Int Position */\r
-#define QEI_IES_POS0REV_Int_Msk (0x01UL << QEI_IES_POS0REV_Int_Pos) /*!< QEI IES: POS0REV_Int Mask */\r
-#define QEI_IES_POS1REV_Int_Pos 11 /*!< QEI IES: POS1REV_Int Position */\r
-#define QEI_IES_POS1REV_Int_Msk (0x01UL << QEI_IES_POS1REV_Int_Pos) /*!< QEI IES: POS1REV_Int Mask */\r
-#define QEI_IES_POS2REV_Int_Pos 12 /*!< QEI IES: POS2REV_Int Position */\r
-#define QEI_IES_POS2REV_Int_Msk (0x01UL << QEI_IES_POS2REV_Int_Pos) /*!< QEI IES: POS2REV_Int Mask */\r
-#define QEI_IES_REV1_Int_Pos 13 /*!< QEI IES: REV1_Int Position */\r
-#define QEI_IES_REV1_Int_Msk (0x01UL << QEI_IES_REV1_Int_Pos) /*!< QEI IES: REV1_Int Mask */\r
-#define QEI_IES_REV2_Int_Pos 14 /*!< QEI IES: REV2_Int Position */\r
-#define QEI_IES_REV2_Int_Msk (0x01UL << QEI_IES_REV2_Int_Pos) /*!< QEI IES: REV2_Int Mask */\r
-#define QEI_IES_MAXPOS_Int_Pos 15 /*!< QEI IES: MAXPOS_Int Position */\r
-#define QEI_IES_MAXPOS_Int_Msk (0x01UL << QEI_IES_MAXPOS_Int_Pos) /*!< QEI IES: MAXPOS_Int Mask */\r
-\r
-// --------------------------------------- QEI_INTSTAT ------------------------------------------\r
-#define QEI_INTSTAT_INX_Int_Pos 0 /*!< QEI INTSTAT: INX_Int Position */\r
-#define QEI_INTSTAT_INX_Int_Msk (0x01UL << QEI_INTSTAT_INX_Int_Pos) /*!< QEI INTSTAT: INX_Int Mask */\r
-#define QEI_INTSTAT_TIM_Int_Pos 1 /*!< QEI INTSTAT: TIM_Int Position */\r
-#define QEI_INTSTAT_TIM_Int_Msk (0x01UL << QEI_INTSTAT_TIM_Int_Pos) /*!< QEI INTSTAT: TIM_Int Mask */\r
-#define QEI_INTSTAT_VELC_Int_Pos 2 /*!< QEI INTSTAT: VELC_Int Position */\r
-#define QEI_INTSTAT_VELC_Int_Msk (0x01UL << QEI_INTSTAT_VELC_Int_Pos) /*!< QEI INTSTAT: VELC_Int Mask */\r
-#define QEI_INTSTAT_DIR_Int_Pos 3 /*!< QEI INTSTAT: DIR_Int Position */\r
-#define QEI_INTSTAT_DIR_Int_Msk (0x01UL << QEI_INTSTAT_DIR_Int_Pos) /*!< QEI INTSTAT: DIR_Int Mask */\r
-#define QEI_INTSTAT_ERR_Int_Pos 4 /*!< QEI INTSTAT: ERR_Int Position */\r
-#define QEI_INTSTAT_ERR_Int_Msk (0x01UL << QEI_INTSTAT_ERR_Int_Pos) /*!< QEI INTSTAT: ERR_Int Mask */\r
-#define QEI_INTSTAT_ENCLK_Int_Pos 5 /*!< QEI INTSTAT: ENCLK_Int Position */\r
-#define QEI_INTSTAT_ENCLK_Int_Msk (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos) /*!< QEI INTSTAT: ENCLK_Int Mask */\r
-#define QEI_INTSTAT_POS0_Int_Pos 6 /*!< QEI INTSTAT: POS0_Int Position */\r
-#define QEI_INTSTAT_POS0_Int_Msk (0x01UL << QEI_INTSTAT_POS0_Int_Pos) /*!< QEI INTSTAT: POS0_Int Mask */\r
-#define QEI_INTSTAT_POS1_Int_Pos 7 /*!< QEI INTSTAT: POS1_Int Position */\r
-#define QEI_INTSTAT_POS1_Int_Msk (0x01UL << QEI_INTSTAT_POS1_Int_Pos) /*!< QEI INTSTAT: POS1_Int Mask */\r
-#define QEI_INTSTAT_POS2_Int_Pos 8 /*!< QEI INTSTAT: POS2_Int Position */\r
-#define QEI_INTSTAT_POS2_Int_Msk (0x01UL << QEI_INTSTAT_POS2_Int_Pos) /*!< QEI INTSTAT: POS2_Int Mask */\r
-#define QEI_INTSTAT_REV_Int_Pos 9 /*!< QEI INTSTAT: REV_Int Position */\r
-#define QEI_INTSTAT_REV_Int_Msk (0x01UL << QEI_INTSTAT_REV_Int_Pos) /*!< QEI INTSTAT: REV_Int Mask */\r
-#define QEI_INTSTAT_POS0REV_Int_Pos 10 /*!< QEI INTSTAT: POS0REV_Int Position */\r
-#define QEI_INTSTAT_POS0REV_Int_Msk (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos) /*!< QEI INTSTAT: POS0REV_Int Mask */\r
-#define QEI_INTSTAT_POS1REV_Int_Pos 11 /*!< QEI INTSTAT: POS1REV_Int Position */\r
-#define QEI_INTSTAT_POS1REV_Int_Msk (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos) /*!< QEI INTSTAT: POS1REV_Int Mask */\r
-#define QEI_INTSTAT_POS2REV_Int_Pos 12 /*!< QEI INTSTAT: POS2REV_Int Position */\r
-#define QEI_INTSTAT_POS2REV_Int_Msk (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos) /*!< QEI INTSTAT: POS2REV_Int Mask */\r
-#define QEI_INTSTAT_REV1_Int_Pos 13 /*!< QEI INTSTAT: REV1_Int Position */\r
-#define QEI_INTSTAT_REV1_Int_Msk (0x01UL << QEI_INTSTAT_REV1_Int_Pos) /*!< QEI INTSTAT: REV1_Int Mask */\r
-#define QEI_INTSTAT_REV2_Int_Pos 14 /*!< QEI INTSTAT: REV2_Int Position */\r
-#define QEI_INTSTAT_REV2_Int_Msk (0x01UL << QEI_INTSTAT_REV2_Int_Pos) /*!< QEI INTSTAT: REV2_Int Mask */\r
-#define QEI_INTSTAT_MAXPOS_Int_Pos 15 /*!< QEI INTSTAT: MAXPOS_Int Position */\r
-#define QEI_INTSTAT_MAXPOS_Int_Msk (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos) /*!< QEI INTSTAT: MAXPOS_Int Mask */\r
-\r
-// ----------------------------------------- QEI_IE ---------------------------------------------\r
-#define QEI_IE_INX_Int_Pos 0 /*!< QEI IE: INX_Int Position */\r
-#define QEI_IE_INX_Int_Msk (0x01UL << QEI_IE_INX_Int_Pos) /*!< QEI IE: INX_Int Mask */\r
-#define QEI_IE_TIM_Int_Pos 1 /*!< QEI IE: TIM_Int Position */\r
-#define QEI_IE_TIM_Int_Msk (0x01UL << QEI_IE_TIM_Int_Pos) /*!< QEI IE: TIM_Int Mask */\r
-#define QEI_IE_VELC_Int_Pos 2 /*!< QEI IE: VELC_Int Position */\r
-#define QEI_IE_VELC_Int_Msk (0x01UL << QEI_IE_VELC_Int_Pos) /*!< QEI IE: VELC_Int Mask */\r
-#define QEI_IE_DIR_Int_Pos 3 /*!< QEI IE: DIR_Int Position */\r
-#define QEI_IE_DIR_Int_Msk (0x01UL << QEI_IE_DIR_Int_Pos) /*!< QEI IE: DIR_Int Mask */\r
-#define QEI_IE_ERR_Int_Pos 4 /*!< QEI IE: ERR_Int Position */\r
-#define QEI_IE_ERR_Int_Msk (0x01UL << QEI_IE_ERR_Int_Pos) /*!< QEI IE: ERR_Int Mask */\r
-#define QEI_IE_ENCLK_Int_Pos 5 /*!< QEI IE: ENCLK_Int Position */\r
-#define QEI_IE_ENCLK_Int_Msk (0x01UL << QEI_IE_ENCLK_Int_Pos) /*!< QEI IE: ENCLK_Int Mask */\r
-#define QEI_IE_POS0_Int_Pos 6 /*!< QEI IE: POS0_Int Position */\r
-#define QEI_IE_POS0_Int_Msk (0x01UL << QEI_IE_POS0_Int_Pos) /*!< QEI IE: POS0_Int Mask */\r
-#define QEI_IE_POS1_Int_Pos 7 /*!< QEI IE: POS1_Int Position */\r
-#define QEI_IE_POS1_Int_Msk (0x01UL << QEI_IE_POS1_Int_Pos) /*!< QEI IE: POS1_Int Mask */\r
-#define QEI_IE_POS2_Int_Pos 8 /*!< QEI IE: POS2_Int Position */\r
-#define QEI_IE_POS2_Int_Msk (0x01UL << QEI_IE_POS2_Int_Pos) /*!< QEI IE: POS2_Int Mask */\r
-#define QEI_IE_REV_Int_Pos 9 /*!< QEI IE: REV_Int Position */\r
-#define QEI_IE_REV_Int_Msk (0x01UL << QEI_IE_REV_Int_Pos) /*!< QEI IE: REV_Int Mask */\r
-#define QEI_IE_POS0REV_Int_Pos 10 /*!< QEI IE: POS0REV_Int Position */\r
-#define QEI_IE_POS0REV_Int_Msk (0x01UL << QEI_IE_POS0REV_Int_Pos) /*!< QEI IE: POS0REV_Int Mask */\r
-#define QEI_IE_POS1REV_Int_Pos 11 /*!< QEI IE: POS1REV_Int Position */\r
-#define QEI_IE_POS1REV_Int_Msk (0x01UL << QEI_IE_POS1REV_Int_Pos) /*!< QEI IE: POS1REV_Int Mask */\r
-#define QEI_IE_POS2REV_Int_Pos 12 /*!< QEI IE: POS2REV_Int Position */\r
-#define QEI_IE_POS2REV_Int_Msk (0x01UL << QEI_IE_POS2REV_Int_Pos) /*!< QEI IE: POS2REV_Int Mask */\r
-#define QEI_IE_REV1_Int_Pos 13 /*!< QEI IE: REV1_Int Position */\r
-#define QEI_IE_REV1_Int_Msk (0x01UL << QEI_IE_REV1_Int_Pos) /*!< QEI IE: REV1_Int Mask */\r
-#define QEI_IE_REV2_Int_Pos 14 /*!< QEI IE: REV2_Int Position */\r
-#define QEI_IE_REV2_Int_Msk (0x01UL << QEI_IE_REV2_Int_Pos) /*!< QEI IE: REV2_Int Mask */\r
-#define QEI_IE_MAXPOS_Int_Pos 15 /*!< QEI IE: MAXPOS_Int Position */\r
-#define QEI_IE_MAXPOS_Int_Msk (0x01UL << QEI_IE_MAXPOS_Int_Pos) /*!< QEI IE: MAXPOS_Int Mask */\r
-\r
-// ----------------------------------------- QEI_CLR --------------------------------------------\r
-#define QEI_CLR_INX_Int_Pos 0 /*!< QEI CLR: INX_Int Position */\r
-#define QEI_CLR_INX_Int_Msk (0x01UL << QEI_CLR_INX_Int_Pos) /*!< QEI CLR: INX_Int Mask */\r
-#define QEI_CLR_TIM_Int_Pos 1 /*!< QEI CLR: TIM_Int Position */\r
-#define QEI_CLR_TIM_Int_Msk (0x01UL << QEI_CLR_TIM_Int_Pos) /*!< QEI CLR: TIM_Int Mask */\r
-#define QEI_CLR_VELC_Int_Pos 2 /*!< QEI CLR: VELC_Int Position */\r
-#define QEI_CLR_VELC_Int_Msk (0x01UL << QEI_CLR_VELC_Int_Pos) /*!< QEI CLR: VELC_Int Mask */\r
-#define QEI_CLR_DIR_Int_Pos 3 /*!< QEI CLR: DIR_Int Position */\r
-#define QEI_CLR_DIR_Int_Msk (0x01UL << QEI_CLR_DIR_Int_Pos) /*!< QEI CLR: DIR_Int Mask */\r
-#define QEI_CLR_ERR_Int_Pos 4 /*!< QEI CLR: ERR_Int Position */\r
-#define QEI_CLR_ERR_Int_Msk (0x01UL << QEI_CLR_ERR_Int_Pos) /*!< QEI CLR: ERR_Int Mask */\r
-#define QEI_CLR_ENCLK_Int_Pos 5 /*!< QEI CLR: ENCLK_Int Position */\r
-#define QEI_CLR_ENCLK_Int_Msk (0x01UL << QEI_CLR_ENCLK_Int_Pos) /*!< QEI CLR: ENCLK_Int Mask */\r
-#define QEI_CLR_POS0_Int_Pos 6 /*!< QEI CLR: POS0_Int Position */\r
-#define QEI_CLR_POS0_Int_Msk (0x01UL << QEI_CLR_POS0_Int_Pos) /*!< QEI CLR: POS0_Int Mask */\r
-#define QEI_CLR_POS1_Int_Pos 7 /*!< QEI CLR: POS1_Int Position */\r
-#define QEI_CLR_POS1_Int_Msk (0x01UL << QEI_CLR_POS1_Int_Pos) /*!< QEI CLR: POS1_Int Mask */\r
-#define QEI_CLR_POS2_Int_Pos 8 /*!< QEI CLR: POS2_Int Position */\r
-#define QEI_CLR_POS2_Int_Msk (0x01UL << QEI_CLR_POS2_Int_Pos) /*!< QEI CLR: POS2_Int Mask */\r
-#define QEI_CLR_REV_Int_Pos 9 /*!< QEI CLR: REV_Int Position */\r
-#define QEI_CLR_REV_Int_Msk (0x01UL << QEI_CLR_REV_Int_Pos) /*!< QEI CLR: REV_Int Mask */\r
-#define QEI_CLR_POS0REV_Int_Pos 10 /*!< QEI CLR: POS0REV_Int Position */\r
-#define QEI_CLR_POS0REV_Int_Msk (0x01UL << QEI_CLR_POS0REV_Int_Pos) /*!< QEI CLR: POS0REV_Int Mask */\r
-#define QEI_CLR_POS1REV_Int_Pos 11 /*!< QEI CLR: POS1REV_Int Position */\r
-#define QEI_CLR_POS1REV_Int_Msk (0x01UL << QEI_CLR_POS1REV_Int_Pos) /*!< QEI CLR: POS1REV_Int Mask */\r
-#define QEI_CLR_REV1_Int_Pos 13 /*!< QEI CLR: REV1_Int Position */\r
-#define QEI_CLR_REV1_Int_Msk (0x01UL << QEI_CLR_REV1_Int_Pos) /*!< QEI CLR: REV1_Int Mask */\r
-#define QEI_CLR_REV2_Int_Pos 14 /*!< QEI CLR: REV2_Int Position */\r
-#define QEI_CLR_REV2_Int_Msk (0x01UL << QEI_CLR_REV2_Int_Pos) /*!< QEI CLR: REV2_Int Mask */\r
-#define QEI_CLR_MAXPOS_Int_Pos 15 /*!< QEI CLR: MAXPOS_Int Position */\r
-#define QEI_CLR_MAXPOS_Int_Msk (0x01UL << QEI_CLR_MAXPOS_Int_Pos) /*!< QEI CLR: MAXPOS_Int Mask */\r
-\r
-// ----------------------------------------- QEI_SET --------------------------------------------\r
-#define QEI_SET_INX_Int_Pos 0 /*!< QEI SET: INX_Int Position */\r
-#define QEI_SET_INX_Int_Msk (0x01UL << QEI_SET_INX_Int_Pos) /*!< QEI SET: INX_Int Mask */\r
-#define QEI_SET_TIM_Int_Pos 1 /*!< QEI SET: TIM_Int Position */\r
-#define QEI_SET_TIM_Int_Msk (0x01UL << QEI_SET_TIM_Int_Pos) /*!< QEI SET: TIM_Int Mask */\r
-#define QEI_SET_VELC_Int_Pos 2 /*!< QEI SET: VELC_Int Position */\r
-#define QEI_SET_VELC_Int_Msk (0x01UL << QEI_SET_VELC_Int_Pos) /*!< QEI SET: VELC_Int Mask */\r
-#define QEI_SET_DIR_Int_Pos 3 /*!< QEI SET: DIR_Int Position */\r
-#define QEI_SET_DIR_Int_Msk (0x01UL << QEI_SET_DIR_Int_Pos) /*!< QEI SET: DIR_Int Mask */\r
-#define QEI_SET_ERR_Int_Pos 4 /*!< QEI SET: ERR_Int Position */\r
-#define QEI_SET_ERR_Int_Msk (0x01UL << QEI_SET_ERR_Int_Pos) /*!< QEI SET: ERR_Int Mask */\r
-#define QEI_SET_ENCLK_Int_Pos 5 /*!< QEI SET: ENCLK_Int Position */\r
-#define QEI_SET_ENCLK_Int_Msk (0x01UL << QEI_SET_ENCLK_Int_Pos) /*!< QEI SET: ENCLK_Int Mask */\r
-#define QEI_SET_POS0_Int_Pos 6 /*!< QEI SET: POS0_Int Position */\r
-#define QEI_SET_POS0_Int_Msk (0x01UL << QEI_SET_POS0_Int_Pos) /*!< QEI SET: POS0_Int Mask */\r
-#define QEI_SET_POS1_Int_Pos 7 /*!< QEI SET: POS1_Int Position */\r
-#define QEI_SET_POS1_Int_Msk (0x01UL << QEI_SET_POS1_Int_Pos) /*!< QEI SET: POS1_Int Mask */\r
-#define QEI_SET_POS2_Int_Pos 8 /*!< QEI SET: POS2_Int Position */\r
-#define QEI_SET_POS2_Int_Msk (0x01UL << QEI_SET_POS2_Int_Pos) /*!< QEI SET: POS2_Int Mask */\r
-#define QEI_SET_REV_Int_Pos 9 /*!< QEI SET: REV_Int Position */\r
-#define QEI_SET_REV_Int_Msk (0x01UL << QEI_SET_REV_Int_Pos) /*!< QEI SET: REV_Int Mask */\r
-#define QEI_SET_POS0REV_Int_Pos 10 /*!< QEI SET: POS0REV_Int Position */\r
-#define QEI_SET_POS0REV_Int_Msk (0x01UL << QEI_SET_POS0REV_Int_Pos) /*!< QEI SET: POS0REV_Int Mask */\r
-#define QEI_SET_POS1REV_Int_Pos 11 /*!< QEI SET: POS1REV_Int Position */\r
-#define QEI_SET_POS1REV_Int_Msk (0x01UL << QEI_SET_POS1REV_Int_Pos) /*!< QEI SET: POS1REV_Int Mask */\r
-#define QEI_SET_POS2REV_Int_Pos 12 /*!< QEI SET: POS2REV_Int Position */\r
-#define QEI_SET_POS2REV_Int_Msk (0x01UL << QEI_SET_POS2REV_Int_Pos) /*!< QEI SET: POS2REV_Int Mask */\r
-#define QEI_SET_REV1_Int_Pos 13 /*!< QEI SET: REV1_Int Position */\r
-#define QEI_SET_REV1_Int_Msk (0x01UL << QEI_SET_REV1_Int_Pos) /*!< QEI SET: REV1_Int Mask */\r
-#define QEI_SET_REV2_Int_Pos 14 /*!< QEI SET: REV2_Int Position */\r
-#define QEI_SET_REV2_Int_Msk (0x01UL << QEI_SET_REV2_Int_Pos) /*!< QEI SET: REV2_Int Mask */\r
-#define QEI_SET_MAXPOS_Int_Pos 15 /*!< QEI SET: MAXPOS_Int Position */\r
-#define QEI_SET_MAXPOS_Int_Msk (0x01UL << QEI_SET_MAXPOS_Int_Pos) /*!< QEI SET: MAXPOS_Int Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GIMA Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ------------------------------------- GIMA_CAP0_0_IN -----------------------------------------\r
-#define GIMA_CAP0_0_IN_INV_Pos 0 /*!< GIMA CAP0_0_IN: INV Position */\r
-#define GIMA_CAP0_0_IN_INV_Msk (0x01UL << GIMA_CAP0_0_IN_INV_Pos) /*!< GIMA CAP0_0_IN: INV Mask */\r
-#define GIMA_CAP0_0_IN_EDGE_Pos 1 /*!< GIMA CAP0_0_IN: EDGE Position */\r
-#define GIMA_CAP0_0_IN_EDGE_Msk (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos) /*!< GIMA CAP0_0_IN: EDGE Mask */\r
-#define GIMA_CAP0_0_IN_SYNCH_Pos 2 /*!< GIMA CAP0_0_IN: SYNCH Position */\r
-#define GIMA_CAP0_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos) /*!< GIMA CAP0_0_IN: SYNCH Mask */\r
-#define GIMA_CAP0_0_IN_PULSE_Pos 3 /*!< GIMA CAP0_0_IN: PULSE Position */\r
-#define GIMA_CAP0_0_IN_PULSE_Msk (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos) /*!< GIMA CAP0_0_IN: PULSE Mask */\r
-#define GIMA_CAP0_0_IN_SELECT_Pos 4 /*!< GIMA CAP0_0_IN: SELECT Position */\r
-#define GIMA_CAP0_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos) /*!< GIMA CAP0_0_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP0_1_IN -----------------------------------------\r
-#define GIMA_CAP0_1_IN_INV_Pos 0 /*!< GIMA CAP0_1_IN: INV Position */\r
-#define GIMA_CAP0_1_IN_INV_Msk (0x01UL << GIMA_CAP0_1_IN_INV_Pos) /*!< GIMA CAP0_1_IN: INV Mask */\r
-#define GIMA_CAP0_1_IN_EDGE_Pos 1 /*!< GIMA CAP0_1_IN: EDGE Position */\r
-#define GIMA_CAP0_1_IN_EDGE_Msk (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos) /*!< GIMA CAP0_1_IN: EDGE Mask */\r
-#define GIMA_CAP0_1_IN_SYNCH_Pos 2 /*!< GIMA CAP0_1_IN: SYNCH Position */\r
-#define GIMA_CAP0_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos) /*!< GIMA CAP0_1_IN: SYNCH Mask */\r
-#define GIMA_CAP0_1_IN_PULSE_Pos 3 /*!< GIMA CAP0_1_IN: PULSE Position */\r
-#define GIMA_CAP0_1_IN_PULSE_Msk (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos) /*!< GIMA CAP0_1_IN: PULSE Mask */\r
-#define GIMA_CAP0_1_IN_SELECT_Pos 4 /*!< GIMA CAP0_1_IN: SELECT Position */\r
-#define GIMA_CAP0_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos) /*!< GIMA CAP0_1_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP0_2_IN -----------------------------------------\r
-#define GIMA_CAP0_2_IN_INV_Pos 0 /*!< GIMA CAP0_2_IN: INV Position */\r
-#define GIMA_CAP0_2_IN_INV_Msk (0x01UL << GIMA_CAP0_2_IN_INV_Pos) /*!< GIMA CAP0_2_IN: INV Mask */\r
-#define GIMA_CAP0_2_IN_EDGE_Pos 1 /*!< GIMA CAP0_2_IN: EDGE Position */\r
-#define GIMA_CAP0_2_IN_EDGE_Msk (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos) /*!< GIMA CAP0_2_IN: EDGE Mask */\r
-#define GIMA_CAP0_2_IN_SYNCH_Pos 2 /*!< GIMA CAP0_2_IN: SYNCH Position */\r
-#define GIMA_CAP0_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos) /*!< GIMA CAP0_2_IN: SYNCH Mask */\r
-#define GIMA_CAP0_2_IN_PULSE_Pos 3 /*!< GIMA CAP0_2_IN: PULSE Position */\r
-#define GIMA_CAP0_2_IN_PULSE_Msk (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos) /*!< GIMA CAP0_2_IN: PULSE Mask */\r
-#define GIMA_CAP0_2_IN_SELECT_Pos 4 /*!< GIMA CAP0_2_IN: SELECT Position */\r
-#define GIMA_CAP0_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos) /*!< GIMA CAP0_2_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP0_3_IN -----------------------------------------\r
-#define GIMA_CAP0_3_IN_INV_Pos 0 /*!< GIMA CAP0_3_IN: INV Position */\r
-#define GIMA_CAP0_3_IN_INV_Msk (0x01UL << GIMA_CAP0_3_IN_INV_Pos) /*!< GIMA CAP0_3_IN: INV Mask */\r
-#define GIMA_CAP0_3_IN_EDGE_Pos 1 /*!< GIMA CAP0_3_IN: EDGE Position */\r
-#define GIMA_CAP0_3_IN_EDGE_Msk (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos) /*!< GIMA CAP0_3_IN: EDGE Mask */\r
-#define GIMA_CAP0_3_IN_SYNCH_Pos 2 /*!< GIMA CAP0_3_IN: SYNCH Position */\r
-#define GIMA_CAP0_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos) /*!< GIMA CAP0_3_IN: SYNCH Mask */\r
-#define GIMA_CAP0_3_IN_PULSE_Pos 3 /*!< GIMA CAP0_3_IN: PULSE Position */\r
-#define GIMA_CAP0_3_IN_PULSE_Msk (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos) /*!< GIMA CAP0_3_IN: PULSE Mask */\r
-#define GIMA_CAP0_3_IN_SELECT_Pos 4 /*!< GIMA CAP0_3_IN: SELECT Position */\r
-#define GIMA_CAP0_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos) /*!< GIMA CAP0_3_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP1_0_IN -----------------------------------------\r
-#define GIMA_CAP1_0_IN_INV_Pos 0 /*!< GIMA CAP1_0_IN: INV Position */\r
-#define GIMA_CAP1_0_IN_INV_Msk (0x01UL << GIMA_CAP1_0_IN_INV_Pos) /*!< GIMA CAP1_0_IN: INV Mask */\r
-#define GIMA_CAP1_0_IN_EDGE_Pos 1 /*!< GIMA CAP1_0_IN: EDGE Position */\r
-#define GIMA_CAP1_0_IN_EDGE_Msk (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos) /*!< GIMA CAP1_0_IN: EDGE Mask */\r
-#define GIMA_CAP1_0_IN_SYNCH_Pos 2 /*!< GIMA CAP1_0_IN: SYNCH Position */\r
-#define GIMA_CAP1_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos) /*!< GIMA CAP1_0_IN: SYNCH Mask */\r
-#define GIMA_CAP1_0_IN_PULSE_Pos 3 /*!< GIMA CAP1_0_IN: PULSE Position */\r
-#define GIMA_CAP1_0_IN_PULSE_Msk (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos) /*!< GIMA CAP1_0_IN: PULSE Mask */\r
-#define GIMA_CAP1_0_IN_SELECT_Pos 4 /*!< GIMA CAP1_0_IN: SELECT Position */\r
-#define GIMA_CAP1_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos) /*!< GIMA CAP1_0_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP1_1_IN -----------------------------------------\r
-#define GIMA_CAP1_1_IN_INV_Pos 0 /*!< GIMA CAP1_1_IN: INV Position */\r
-#define GIMA_CAP1_1_IN_INV_Msk (0x01UL << GIMA_CAP1_1_IN_INV_Pos) /*!< GIMA CAP1_1_IN: INV Mask */\r
-#define GIMA_CAP1_1_IN_EDGE_Pos 1 /*!< GIMA CAP1_1_IN: EDGE Position */\r
-#define GIMA_CAP1_1_IN_EDGE_Msk (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos) /*!< GIMA CAP1_1_IN: EDGE Mask */\r
-#define GIMA_CAP1_1_IN_SYNCH_Pos 2 /*!< GIMA CAP1_1_IN: SYNCH Position */\r
-#define GIMA_CAP1_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos) /*!< GIMA CAP1_1_IN: SYNCH Mask */\r
-#define GIMA_CAP1_1_IN_PULSE_Pos 3 /*!< GIMA CAP1_1_IN: PULSE Position */\r
-#define GIMA_CAP1_1_IN_PULSE_Msk (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos) /*!< GIMA CAP1_1_IN: PULSE Mask */\r
-#define GIMA_CAP1_1_IN_SELECT_Pos 4 /*!< GIMA CAP1_1_IN: SELECT Position */\r
-#define GIMA_CAP1_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos) /*!< GIMA CAP1_1_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP1_2_IN -----------------------------------------\r
-#define GIMA_CAP1_2_IN_INV_Pos 0 /*!< GIMA CAP1_2_IN: INV Position */\r
-#define GIMA_CAP1_2_IN_INV_Msk (0x01UL << GIMA_CAP1_2_IN_INV_Pos) /*!< GIMA CAP1_2_IN: INV Mask */\r
-#define GIMA_CAP1_2_IN_EDGE_Pos 1 /*!< GIMA CAP1_2_IN: EDGE Position */\r
-#define GIMA_CAP1_2_IN_EDGE_Msk (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos) /*!< GIMA CAP1_2_IN: EDGE Mask */\r
-#define GIMA_CAP1_2_IN_SYNCH_Pos 2 /*!< GIMA CAP1_2_IN: SYNCH Position */\r
-#define GIMA_CAP1_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos) /*!< GIMA CAP1_2_IN: SYNCH Mask */\r
-#define GIMA_CAP1_2_IN_PULSE_Pos 3 /*!< GIMA CAP1_2_IN: PULSE Position */\r
-#define GIMA_CAP1_2_IN_PULSE_Msk (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos) /*!< GIMA CAP1_2_IN: PULSE Mask */\r
-#define GIMA_CAP1_2_IN_SELECT_Pos 4 /*!< GIMA CAP1_2_IN: SELECT Position */\r
-#define GIMA_CAP1_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos) /*!< GIMA CAP1_2_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP1_3_IN -----------------------------------------\r
-#define GIMA_CAP1_3_IN_INV_Pos 0 /*!< GIMA CAP1_3_IN: INV Position */\r
-#define GIMA_CAP1_3_IN_INV_Msk (0x01UL << GIMA_CAP1_3_IN_INV_Pos) /*!< GIMA CAP1_3_IN: INV Mask */\r
-#define GIMA_CAP1_3_IN_EDGE_Pos 1 /*!< GIMA CAP1_3_IN: EDGE Position */\r
-#define GIMA_CAP1_3_IN_EDGE_Msk (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos) /*!< GIMA CAP1_3_IN: EDGE Mask */\r
-#define GIMA_CAP1_3_IN_SYNCH_Pos 2 /*!< GIMA CAP1_3_IN: SYNCH Position */\r
-#define GIMA_CAP1_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos) /*!< GIMA CAP1_3_IN: SYNCH Mask */\r
-#define GIMA_CAP1_3_IN_PULSE_Pos 3 /*!< GIMA CAP1_3_IN: PULSE Position */\r
-#define GIMA_CAP1_3_IN_PULSE_Msk (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos) /*!< GIMA CAP1_3_IN: PULSE Mask */\r
-#define GIMA_CAP1_3_IN_SELECT_Pos 4 /*!< GIMA CAP1_3_IN: SELECT Position */\r
-#define GIMA_CAP1_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos) /*!< GIMA CAP1_3_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP2_0_IN -----------------------------------------\r
-#define GIMA_CAP2_0_IN_INV_Pos 0 /*!< GIMA CAP2_0_IN: INV Position */\r
-#define GIMA_CAP2_0_IN_INV_Msk (0x01UL << GIMA_CAP2_0_IN_INV_Pos) /*!< GIMA CAP2_0_IN: INV Mask */\r
-#define GIMA_CAP2_0_IN_EDGE_Pos 1 /*!< GIMA CAP2_0_IN: EDGE Position */\r
-#define GIMA_CAP2_0_IN_EDGE_Msk (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos) /*!< GIMA CAP2_0_IN: EDGE Mask */\r
-#define GIMA_CAP2_0_IN_SYNCH_Pos 2 /*!< GIMA CAP2_0_IN: SYNCH Position */\r
-#define GIMA_CAP2_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos) /*!< GIMA CAP2_0_IN: SYNCH Mask */\r
-#define GIMA_CAP2_0_IN_PULSE_Pos 3 /*!< GIMA CAP2_0_IN: PULSE Position */\r
-#define GIMA_CAP2_0_IN_PULSE_Msk (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos) /*!< GIMA CAP2_0_IN: PULSE Mask */\r
-#define GIMA_CAP2_0_IN_SELECT_Pos 4 /*!< GIMA CAP2_0_IN: SELECT Position */\r
-#define GIMA_CAP2_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos) /*!< GIMA CAP2_0_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP2_1_IN -----------------------------------------\r
-#define GIMA_CAP2_1_IN_INV_Pos 0 /*!< GIMA CAP2_1_IN: INV Position */\r
-#define GIMA_CAP2_1_IN_INV_Msk (0x01UL << GIMA_CAP2_1_IN_INV_Pos) /*!< GIMA CAP2_1_IN: INV Mask */\r
-#define GIMA_CAP2_1_IN_EDGE_Pos 1 /*!< GIMA CAP2_1_IN: EDGE Position */\r
-#define GIMA_CAP2_1_IN_EDGE_Msk (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos) /*!< GIMA CAP2_1_IN: EDGE Mask */\r
-#define GIMA_CAP2_1_IN_SYNCH_Pos 2 /*!< GIMA CAP2_1_IN: SYNCH Position */\r
-#define GIMA_CAP2_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos) /*!< GIMA CAP2_1_IN: SYNCH Mask */\r
-#define GIMA_CAP2_1_IN_PULSE_Pos 3 /*!< GIMA CAP2_1_IN: PULSE Position */\r
-#define GIMA_CAP2_1_IN_PULSE_Msk (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos) /*!< GIMA CAP2_1_IN: PULSE Mask */\r
-#define GIMA_CAP2_1_IN_SELECT_Pos 4 /*!< GIMA CAP2_1_IN: SELECT Position */\r
-#define GIMA_CAP2_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos) /*!< GIMA CAP2_1_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP2_2_IN -----------------------------------------\r
-#define GIMA_CAP2_2_IN_INV_Pos 0 /*!< GIMA CAP2_2_IN: INV Position */\r
-#define GIMA_CAP2_2_IN_INV_Msk (0x01UL << GIMA_CAP2_2_IN_INV_Pos) /*!< GIMA CAP2_2_IN: INV Mask */\r
-#define GIMA_CAP2_2_IN_EDGE_Pos 1 /*!< GIMA CAP2_2_IN: EDGE Position */\r
-#define GIMA_CAP2_2_IN_EDGE_Msk (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos) /*!< GIMA CAP2_2_IN: EDGE Mask */\r
-#define GIMA_CAP2_2_IN_SYNCH_Pos 2 /*!< GIMA CAP2_2_IN: SYNCH Position */\r
-#define GIMA_CAP2_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos) /*!< GIMA CAP2_2_IN: SYNCH Mask */\r
-#define GIMA_CAP2_2_IN_PULSE_Pos 3 /*!< GIMA CAP2_2_IN: PULSE Position */\r
-#define GIMA_CAP2_2_IN_PULSE_Msk (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos) /*!< GIMA CAP2_2_IN: PULSE Mask */\r
-#define GIMA_CAP2_2_IN_SELECT_Pos 4 /*!< GIMA CAP2_2_IN: SELECT Position */\r
-#define GIMA_CAP2_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos) /*!< GIMA CAP2_2_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP2_3_IN -----------------------------------------\r
-#define GIMA_CAP2_3_IN_INV_Pos 0 /*!< GIMA CAP2_3_IN: INV Position */\r
-#define GIMA_CAP2_3_IN_INV_Msk (0x01UL << GIMA_CAP2_3_IN_INV_Pos) /*!< GIMA CAP2_3_IN: INV Mask */\r
-#define GIMA_CAP2_3_IN_EDGE_Pos 1 /*!< GIMA CAP2_3_IN: EDGE Position */\r
-#define GIMA_CAP2_3_IN_EDGE_Msk (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos) /*!< GIMA CAP2_3_IN: EDGE Mask */\r
-#define GIMA_CAP2_3_IN_SYNCH_Pos 2 /*!< GIMA CAP2_3_IN: SYNCH Position */\r
-#define GIMA_CAP2_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos) /*!< GIMA CAP2_3_IN: SYNCH Mask */\r
-#define GIMA_CAP2_3_IN_PULSE_Pos 3 /*!< GIMA CAP2_3_IN: PULSE Position */\r
-#define GIMA_CAP2_3_IN_PULSE_Msk (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos) /*!< GIMA CAP2_3_IN: PULSE Mask */\r
-#define GIMA_CAP2_3_IN_SELECT_Pos 4 /*!< GIMA CAP2_3_IN: SELECT Position */\r
-#define GIMA_CAP2_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos) /*!< GIMA CAP2_3_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP3_0_IN -----------------------------------------\r
-#define GIMA_CAP3_0_IN_INV_Pos 0 /*!< GIMA CAP3_0_IN: INV Position */\r
-#define GIMA_CAP3_0_IN_INV_Msk (0x01UL << GIMA_CAP3_0_IN_INV_Pos) /*!< GIMA CAP3_0_IN: INV Mask */\r
-#define GIMA_CAP3_0_IN_EDGE_Pos 1 /*!< GIMA CAP3_0_IN: EDGE Position */\r
-#define GIMA_CAP3_0_IN_EDGE_Msk (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos) /*!< GIMA CAP3_0_IN: EDGE Mask */\r
-#define GIMA_CAP3_0_IN_SYNCH_Pos 2 /*!< GIMA CAP3_0_IN: SYNCH Position */\r
-#define GIMA_CAP3_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos) /*!< GIMA CAP3_0_IN: SYNCH Mask */\r
-#define GIMA_CAP3_0_IN_PULSE_Pos 3 /*!< GIMA CAP3_0_IN: PULSE Position */\r
-#define GIMA_CAP3_0_IN_PULSE_Msk (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos) /*!< GIMA CAP3_0_IN: PULSE Mask */\r
-#define GIMA_CAP3_0_IN_SELECT_Pos 4 /*!< GIMA CAP3_0_IN: SELECT Position */\r
-#define GIMA_CAP3_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos) /*!< GIMA CAP3_0_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP3_1_IN -----------------------------------------\r
-#define GIMA_CAP3_1_IN_INV_Pos 0 /*!< GIMA CAP3_1_IN: INV Position */\r
-#define GIMA_CAP3_1_IN_INV_Msk (0x01UL << GIMA_CAP3_1_IN_INV_Pos) /*!< GIMA CAP3_1_IN: INV Mask */\r
-#define GIMA_CAP3_1_IN_EDGE_Pos 1 /*!< GIMA CAP3_1_IN: EDGE Position */\r
-#define GIMA_CAP3_1_IN_EDGE_Msk (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos) /*!< GIMA CAP3_1_IN: EDGE Mask */\r
-#define GIMA_CAP3_1_IN_SYNCH_Pos 2 /*!< GIMA CAP3_1_IN: SYNCH Position */\r
-#define GIMA_CAP3_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos) /*!< GIMA CAP3_1_IN: SYNCH Mask */\r
-#define GIMA_CAP3_1_IN_PULSE_Pos 3 /*!< GIMA CAP3_1_IN: PULSE Position */\r
-#define GIMA_CAP3_1_IN_PULSE_Msk (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos) /*!< GIMA CAP3_1_IN: PULSE Mask */\r
-#define GIMA_CAP3_1_IN_SELECT_Pos 4 /*!< GIMA CAP3_1_IN: SELECT Position */\r
-#define GIMA_CAP3_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos) /*!< GIMA CAP3_1_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP3_2_IN -----------------------------------------\r
-#define GIMA_CAP3_2_IN_INV_Pos 0 /*!< GIMA CAP3_2_IN: INV Position */\r
-#define GIMA_CAP3_2_IN_INV_Msk (0x01UL << GIMA_CAP3_2_IN_INV_Pos) /*!< GIMA CAP3_2_IN: INV Mask */\r
-#define GIMA_CAP3_2_IN_EDGE_Pos 1 /*!< GIMA CAP3_2_IN: EDGE Position */\r
-#define GIMA_CAP3_2_IN_EDGE_Msk (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos) /*!< GIMA CAP3_2_IN: EDGE Mask */\r
-#define GIMA_CAP3_2_IN_SYNCH_Pos 2 /*!< GIMA CAP3_2_IN: SYNCH Position */\r
-#define GIMA_CAP3_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos) /*!< GIMA CAP3_2_IN: SYNCH Mask */\r
-#define GIMA_CAP3_2_IN_PULSE_Pos 3 /*!< GIMA CAP3_2_IN: PULSE Position */\r
-#define GIMA_CAP3_2_IN_PULSE_Msk (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos) /*!< GIMA CAP3_2_IN: PULSE Mask */\r
-#define GIMA_CAP3_2_IN_SELECT_Pos 4 /*!< GIMA CAP3_2_IN: SELECT Position */\r
-#define GIMA_CAP3_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos) /*!< GIMA CAP3_2_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CAP3_3_IN -----------------------------------------\r
-#define GIMA_CAP3_3_IN_INV_Pos 0 /*!< GIMA CAP3_3_IN: INV Position */\r
-#define GIMA_CAP3_3_IN_INV_Msk (0x01UL << GIMA_CAP3_3_IN_INV_Pos) /*!< GIMA CAP3_3_IN: INV Mask */\r
-#define GIMA_CAP3_3_IN_EDGE_Pos 1 /*!< GIMA CAP3_3_IN: EDGE Position */\r
-#define GIMA_CAP3_3_IN_EDGE_Msk (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos) /*!< GIMA CAP3_3_IN: EDGE Mask */\r
-#define GIMA_CAP3_3_IN_SYNCH_Pos 2 /*!< GIMA CAP3_3_IN: SYNCH Position */\r
-#define GIMA_CAP3_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos) /*!< GIMA CAP3_3_IN: SYNCH Mask */\r
-#define GIMA_CAP3_3_IN_PULSE_Pos 3 /*!< GIMA CAP3_3_IN: PULSE Position */\r
-#define GIMA_CAP3_3_IN_PULSE_Msk (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos) /*!< GIMA CAP3_3_IN: PULSE Mask */\r
-#define GIMA_CAP3_3_IN_SELECT_Pos 4 /*!< GIMA CAP3_3_IN: SELECT Position */\r
-#define GIMA_CAP3_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos) /*!< GIMA CAP3_3_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CTIN_0_IN -----------------------------------------\r
-#define GIMA_CTIN_0_IN_INV_Pos 0 /*!< GIMA CTIN_0_IN: INV Position */\r
-#define GIMA_CTIN_0_IN_INV_Msk (0x01UL << GIMA_CTIN_0_IN_INV_Pos) /*!< GIMA CTIN_0_IN: INV Mask */\r
-#define GIMA_CTIN_0_IN_EDGE_Pos 1 /*!< GIMA CTIN_0_IN: EDGE Position */\r
-#define GIMA_CTIN_0_IN_EDGE_Msk (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos) /*!< GIMA CTIN_0_IN: EDGE Mask */\r
-#define GIMA_CTIN_0_IN_SYNCH_Pos 2 /*!< GIMA CTIN_0_IN: SYNCH Position */\r
-#define GIMA_CTIN_0_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos) /*!< GIMA CTIN_0_IN: SYNCH Mask */\r
-#define GIMA_CTIN_0_IN_PULSE_Pos 3 /*!< GIMA CTIN_0_IN: PULSE Position */\r
-#define GIMA_CTIN_0_IN_PULSE_Msk (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos) /*!< GIMA CTIN_0_IN: PULSE Mask */\r
-#define GIMA_CTIN_0_IN_SELECT_Pos 4 /*!< GIMA CTIN_0_IN: SELECT Position */\r
-#define GIMA_CTIN_0_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos) /*!< GIMA CTIN_0_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CTIN_1_IN -----------------------------------------\r
-#define GIMA_CTIN_1_IN_INV_Pos 0 /*!< GIMA CTIN_1_IN: INV Position */\r
-#define GIMA_CTIN_1_IN_INV_Msk (0x01UL << GIMA_CTIN_1_IN_INV_Pos) /*!< GIMA CTIN_1_IN: INV Mask */\r
-#define GIMA_CTIN_1_IN_EDGE_Pos 1 /*!< GIMA CTIN_1_IN: EDGE Position */\r
-#define GIMA_CTIN_1_IN_EDGE_Msk (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos) /*!< GIMA CTIN_1_IN: EDGE Mask */\r
-#define GIMA_CTIN_1_IN_SYNCH_Pos 2 /*!< GIMA CTIN_1_IN: SYNCH Position */\r
-#define GIMA_CTIN_1_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos) /*!< GIMA CTIN_1_IN: SYNCH Mask */\r
-#define GIMA_CTIN_1_IN_PULSE_Pos 3 /*!< GIMA CTIN_1_IN: PULSE Position */\r
-#define GIMA_CTIN_1_IN_PULSE_Msk (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos) /*!< GIMA CTIN_1_IN: PULSE Mask */\r
-#define GIMA_CTIN_1_IN_SELECT_Pos 4 /*!< GIMA CTIN_1_IN: SELECT Position */\r
-#define GIMA_CTIN_1_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos) /*!< GIMA CTIN_1_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CTIN_2_IN -----------------------------------------\r
-#define GIMA_CTIN_2_IN_INV_Pos 0 /*!< GIMA CTIN_2_IN: INV Position */\r
-#define GIMA_CTIN_2_IN_INV_Msk (0x01UL << GIMA_CTIN_2_IN_INV_Pos) /*!< GIMA CTIN_2_IN: INV Mask */\r
-#define GIMA_CTIN_2_IN_EDGE_Pos 1 /*!< GIMA CTIN_2_IN: EDGE Position */\r
-#define GIMA_CTIN_2_IN_EDGE_Msk (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos) /*!< GIMA CTIN_2_IN: EDGE Mask */\r
-#define GIMA_CTIN_2_IN_SYNCH_Pos 2 /*!< GIMA CTIN_2_IN: SYNCH Position */\r
-#define GIMA_CTIN_2_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos) /*!< GIMA CTIN_2_IN: SYNCH Mask */\r
-#define GIMA_CTIN_2_IN_PULSE_Pos 3 /*!< GIMA CTIN_2_IN: PULSE Position */\r
-#define GIMA_CTIN_2_IN_PULSE_Msk (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos) /*!< GIMA CTIN_2_IN: PULSE Mask */\r
-#define GIMA_CTIN_2_IN_SELECT_Pos 4 /*!< GIMA CTIN_2_IN: SELECT Position */\r
-#define GIMA_CTIN_2_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos) /*!< GIMA CTIN_2_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CTIN_3_IN -----------------------------------------\r
-#define GIMA_CTIN_3_IN_INV_Pos 0 /*!< GIMA CTIN_3_IN: INV Position */\r
-#define GIMA_CTIN_3_IN_INV_Msk (0x01UL << GIMA_CTIN_3_IN_INV_Pos) /*!< GIMA CTIN_3_IN: INV Mask */\r
-#define GIMA_CTIN_3_IN_EDGE_Pos 1 /*!< GIMA CTIN_3_IN: EDGE Position */\r
-#define GIMA_CTIN_3_IN_EDGE_Msk (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos) /*!< GIMA CTIN_3_IN: EDGE Mask */\r
-#define GIMA_CTIN_3_IN_SYNCH_Pos 2 /*!< GIMA CTIN_3_IN: SYNCH Position */\r
-#define GIMA_CTIN_3_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos) /*!< GIMA CTIN_3_IN: SYNCH Mask */\r
-#define GIMA_CTIN_3_IN_PULSE_Pos 3 /*!< GIMA CTIN_3_IN: PULSE Position */\r
-#define GIMA_CTIN_3_IN_PULSE_Msk (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos) /*!< GIMA CTIN_3_IN: PULSE Mask */\r
-#define GIMA_CTIN_3_IN_SELECT_Pos 4 /*!< GIMA CTIN_3_IN: SELECT Position */\r
-#define GIMA_CTIN_3_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos) /*!< GIMA CTIN_3_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CTIN_4_IN -----------------------------------------\r
-#define GIMA_CTIN_4_IN_INV_Pos 0 /*!< GIMA CTIN_4_IN: INV Position */\r
-#define GIMA_CTIN_4_IN_INV_Msk (0x01UL << GIMA_CTIN_4_IN_INV_Pos) /*!< GIMA CTIN_4_IN: INV Mask */\r
-#define GIMA_CTIN_4_IN_EDGE_Pos 1 /*!< GIMA CTIN_4_IN: EDGE Position */\r
-#define GIMA_CTIN_4_IN_EDGE_Msk (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos) /*!< GIMA CTIN_4_IN: EDGE Mask */\r
-#define GIMA_CTIN_4_IN_SYNCH_Pos 2 /*!< GIMA CTIN_4_IN: SYNCH Position */\r
-#define GIMA_CTIN_4_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos) /*!< GIMA CTIN_4_IN: SYNCH Mask */\r
-#define GIMA_CTIN_4_IN_PULSE_Pos 3 /*!< GIMA CTIN_4_IN: PULSE Position */\r
-#define GIMA_CTIN_4_IN_PULSE_Msk (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos) /*!< GIMA CTIN_4_IN: PULSE Mask */\r
-#define GIMA_CTIN_4_IN_SELECT_Pos 4 /*!< GIMA CTIN_4_IN: SELECT Position */\r
-#define GIMA_CTIN_4_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos) /*!< GIMA CTIN_4_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CTIN_5_IN -----------------------------------------\r
-#define GIMA_CTIN_5_IN_INV_Pos 0 /*!< GIMA CTIN_5_IN: INV Position */\r
-#define GIMA_CTIN_5_IN_INV_Msk (0x01UL << GIMA_CTIN_5_IN_INV_Pos) /*!< GIMA CTIN_5_IN: INV Mask */\r
-#define GIMA_CTIN_5_IN_EDGE_Pos 1 /*!< GIMA CTIN_5_IN: EDGE Position */\r
-#define GIMA_CTIN_5_IN_EDGE_Msk (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos) /*!< GIMA CTIN_5_IN: EDGE Mask */\r
-#define GIMA_CTIN_5_IN_SYNCH_Pos 2 /*!< GIMA CTIN_5_IN: SYNCH Position */\r
-#define GIMA_CTIN_5_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos) /*!< GIMA CTIN_5_IN: SYNCH Mask */\r
-#define GIMA_CTIN_5_IN_PULSE_Pos 3 /*!< GIMA CTIN_5_IN: PULSE Position */\r
-#define GIMA_CTIN_5_IN_PULSE_Msk (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos) /*!< GIMA CTIN_5_IN: PULSE Mask */\r
-#define GIMA_CTIN_5_IN_SELECT_Pos 4 /*!< GIMA CTIN_5_IN: SELECT Position */\r
-#define GIMA_CTIN_5_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos) /*!< GIMA CTIN_5_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CTIN_6_IN -----------------------------------------\r
-#define GIMA_CTIN_6_IN_INV_Pos 0 /*!< GIMA CTIN_6_IN: INV Position */\r
-#define GIMA_CTIN_6_IN_INV_Msk (0x01UL << GIMA_CTIN_6_IN_INV_Pos) /*!< GIMA CTIN_6_IN: INV Mask */\r
-#define GIMA_CTIN_6_IN_EDGE_Pos 1 /*!< GIMA CTIN_6_IN: EDGE Position */\r
-#define GIMA_CTIN_6_IN_EDGE_Msk (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos) /*!< GIMA CTIN_6_IN: EDGE Mask */\r
-#define GIMA_CTIN_6_IN_SYNCH_Pos 2 /*!< GIMA CTIN_6_IN: SYNCH Position */\r
-#define GIMA_CTIN_6_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos) /*!< GIMA CTIN_6_IN: SYNCH Mask */\r
-#define GIMA_CTIN_6_IN_PULSE_Pos 3 /*!< GIMA CTIN_6_IN: PULSE Position */\r
-#define GIMA_CTIN_6_IN_PULSE_Msk (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos) /*!< GIMA CTIN_6_IN: PULSE Mask */\r
-#define GIMA_CTIN_6_IN_SELECT_Pos 4 /*!< GIMA CTIN_6_IN: SELECT Position */\r
-#define GIMA_CTIN_6_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos) /*!< GIMA CTIN_6_IN: SELECT Mask */\r
-\r
-// ------------------------------------- GIMA_CTIN_7_IN -----------------------------------------\r
-#define GIMA_CTIN_7_IN_INV_Pos 0 /*!< GIMA CTIN_7_IN: INV Position */\r
-#define GIMA_CTIN_7_IN_INV_Msk (0x01UL << GIMA_CTIN_7_IN_INV_Pos) /*!< GIMA CTIN_7_IN: INV Mask */\r
-#define GIMA_CTIN_7_IN_EDGE_Pos 1 /*!< GIMA CTIN_7_IN: EDGE Position */\r
-#define GIMA_CTIN_7_IN_EDGE_Msk (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos) /*!< GIMA CTIN_7_IN: EDGE Mask */\r
-#define GIMA_CTIN_7_IN_SYNCH_Pos 2 /*!< GIMA CTIN_7_IN: SYNCH Position */\r
-#define GIMA_CTIN_7_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos) /*!< GIMA CTIN_7_IN: SYNCH Mask */\r
-#define GIMA_CTIN_7_IN_PULSE_Pos 3 /*!< GIMA CTIN_7_IN: PULSE Position */\r
-#define GIMA_CTIN_7_IN_PULSE_Msk (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos) /*!< GIMA CTIN_7_IN: PULSE Mask */\r
-#define GIMA_CTIN_7_IN_SELECT_Pos 4 /*!< GIMA CTIN_7_IN: SELECT Position */\r
-#define GIMA_CTIN_7_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos) /*!< GIMA CTIN_7_IN: SELECT Mask */\r
-\r
-// ---------------------------------- GIMA_VADC_TRIGGER_IN --------------------------------------\r
-#define GIMA_VADC_TRIGGER_IN_INV_Pos 0 /*!< GIMA VADC_TRIGGER_IN: INV Position */\r
-#define GIMA_VADC_TRIGGER_IN_INV_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_INV_Pos) /*!< GIMA VADC_TRIGGER_IN: INV Mask */\r
-#define GIMA_VADC_TRIGGER_IN_EDGE_Pos 1 /*!< GIMA VADC_TRIGGER_IN: EDGE Position */\r
-#define GIMA_VADC_TRIGGER_IN_EDGE_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_EDGE_Pos) /*!< GIMA VADC_TRIGGER_IN: EDGE Mask */\r
-#define GIMA_VADC_TRIGGER_IN_SYNCH_Pos 2 /*!< GIMA VADC_TRIGGER_IN: SYNCH Position */\r
-#define GIMA_VADC_TRIGGER_IN_SYNCH_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_SYNCH_Pos) /*!< GIMA VADC_TRIGGER_IN: SYNCH Mask */\r
-#define GIMA_VADC_TRIGGER_IN_PULSE_Pos 3 /*!< GIMA VADC_TRIGGER_IN: PULSE Position */\r
-#define GIMA_VADC_TRIGGER_IN_PULSE_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_PULSE_Pos) /*!< GIMA VADC_TRIGGER_IN: PULSE Mask */\r
-#define GIMA_VADC_TRIGGER_IN_SELECT_Pos 4 /*!< GIMA VADC_TRIGGER_IN: SELECT Position */\r
-#define GIMA_VADC_TRIGGER_IN_SELECT_Msk (0x0fUL << GIMA_VADC_TRIGGER_IN_SELECT_Pos) /*!< GIMA VADC_TRIGGER_IN: SELECT Mask */\r
-\r
-// --------------------------------- GIMA_EVENTROUTER_13_IN -------------------------------------\r
-#define GIMA_EVENTROUTER_13_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_13_IN: INV Position */\r
-#define GIMA_EVENTROUTER_13_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos) /*!< GIMA EVENTROUTER_13_IN: INV Mask */\r
-#define GIMA_EVENTROUTER_13_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_13_IN: EDGE Position */\r
-#define GIMA_EVENTROUTER_13_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_13_IN: EDGE Mask */\r
-#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */\r
-#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask */\r
-#define GIMA_EVENTROUTER_13_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_13_IN: PULSE Position */\r
-#define GIMA_EVENTROUTER_13_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_13_IN: PULSE Mask */\r
-#define GIMA_EVENTROUTER_13_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_13_IN: SELECT Position */\r
-#define GIMA_EVENTROUTER_13_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */\r
-\r
-// --------------------------------- GIMA_EVENTROUTER_14_IN -------------------------------------\r
-#define GIMA_EVENTROUTER_14_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_14_IN: INV Position */\r
-#define GIMA_EVENTROUTER_14_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos) /*!< GIMA EVENTROUTER_14_IN: INV Mask */\r
-#define GIMA_EVENTROUTER_14_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_14_IN: EDGE Position */\r
-#define GIMA_EVENTROUTER_14_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_14_IN: EDGE Mask */\r
-#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */\r
-#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask */\r
-#define GIMA_EVENTROUTER_14_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_14_IN: PULSE Position */\r
-#define GIMA_EVENTROUTER_14_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_14_IN: PULSE Mask */\r
-#define GIMA_EVENTROUTER_14_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_14_IN: SELECT Position */\r
-#define GIMA_EVENTROUTER_14_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */\r
-\r
-// --------------------------------- GIMA_EVENTROUTER_16_IN -------------------------------------\r
-#define GIMA_EVENTROUTER_16_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_16_IN: INV Position */\r
-#define GIMA_EVENTROUTER_16_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos) /*!< GIMA EVENTROUTER_16_IN: INV Mask */\r
-#define GIMA_EVENTROUTER_16_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_16_IN: EDGE Position */\r
-#define GIMA_EVENTROUTER_16_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_16_IN: EDGE Mask */\r
-#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */\r
-#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask */\r
-#define GIMA_EVENTROUTER_16_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_16_IN: PULSE Position */\r
-#define GIMA_EVENTROUTER_16_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_16_IN: PULSE Mask */\r
-#define GIMA_EVENTROUTER_16_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_16_IN: SELECT Position */\r
-#define GIMA_EVENTROUTER_16_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */\r
-\r
-// ------------------------------------ GIMA_ADCSTART0_IN ---------------------------------------\r
-#define GIMA_ADCSTART0_IN_INV_Pos 0 /*!< GIMA ADCSTART0_IN: INV Position */\r
-#define GIMA_ADCSTART0_IN_INV_Msk (0x01UL << GIMA_ADCSTART0_IN_INV_Pos) /*!< GIMA ADCSTART0_IN: INV Mask */\r
-#define GIMA_ADCSTART0_IN_EDGE_Pos 1 /*!< GIMA ADCSTART0_IN: EDGE Position */\r
-#define GIMA_ADCSTART0_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos) /*!< GIMA ADCSTART0_IN: EDGE Mask */\r
-#define GIMA_ADCSTART0_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART0_IN: SYNCH Position */\r
-#define GIMA_ADCSTART0_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos) /*!< GIMA ADCSTART0_IN: SYNCH Mask */\r
-#define GIMA_ADCSTART0_IN_PULSE_Pos 3 /*!< GIMA ADCSTART0_IN: PULSE Position */\r
-#define GIMA_ADCSTART0_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos) /*!< GIMA ADCSTART0_IN: PULSE Mask */\r
-#define GIMA_ADCSTART0_IN_SELECT_Pos 4 /*!< GIMA ADCSTART0_IN: SELECT Position */\r
-#define GIMA_ADCSTART0_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos) /*!< GIMA ADCSTART0_IN: SELECT Mask */\r
-\r
-// ------------------------------------ GIMA_ADCSTART1_IN ---------------------------------------\r
-#define GIMA_ADCSTART1_IN_INV_Pos 0 /*!< GIMA ADCSTART1_IN: INV Position */\r
-#define GIMA_ADCSTART1_IN_INV_Msk (0x01UL << GIMA_ADCSTART1_IN_INV_Pos) /*!< GIMA ADCSTART1_IN: INV Mask */\r
-#define GIMA_ADCSTART1_IN_EDGE_Pos 1 /*!< GIMA ADCSTART1_IN: EDGE Position */\r
-#define GIMA_ADCSTART1_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos) /*!< GIMA ADCSTART1_IN: EDGE Mask */\r
-#define GIMA_ADCSTART1_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART1_IN: SYNCH Position */\r
-#define GIMA_ADCSTART1_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos) /*!< GIMA ADCSTART1_IN: SYNCH Mask */\r
-#define GIMA_ADCSTART1_IN_PULSE_Pos 3 /*!< GIMA ADCSTART1_IN: PULSE Position */\r
-#define GIMA_ADCSTART1_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos) /*!< GIMA ADCSTART1_IN: PULSE Mask */\r
-#define GIMA_ADCSTART1_IN_SELECT_Pos 4 /*!< GIMA ADCSTART1_IN: SELECT Position */\r
-#define GIMA_ADCSTART1_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos) /*!< GIMA ADCSTART1_IN: SELECT Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- DAC Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------- DAC_CR ---------------------------------------------\r
-#define DAC_CR_VALUE_Pos 6 /*!< DAC CR: VALUE Position */\r
-#define DAC_CR_VALUE_Msk (0x000003ffUL << DAC_CR_VALUE_Pos) /*!< DAC CR: VALUE Mask */\r
-#define DAC_CR_BIAS_Pos 16 /*!< DAC CR: BIAS Position */\r
-#define DAC_CR_BIAS_Msk (0x01UL << DAC_CR_BIAS_Pos) /*!< DAC CR: BIAS Mask */\r
-\r
-// ---------------------------------------- DAC_CTRL --------------------------------------------\r
-#define DAC_CTRL_INT_DMA_REQ_Pos 0 /*!< DAC CTRL: INT_DMA_REQ Position */\r
-#define DAC_CTRL_INT_DMA_REQ_Msk (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos) /*!< DAC CTRL: INT_DMA_REQ Mask */\r
-#define DAC_CTRL_DBLBUF_ENA_Pos 1 /*!< DAC CTRL: DBLBUF_ENA Position */\r
-#define DAC_CTRL_DBLBUF_ENA_Msk (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos) /*!< DAC CTRL: DBLBUF_ENA Mask */\r
-#define DAC_CTRL_CNT_ENA_Pos 2 /*!< DAC CTRL: CNT_ENA Position */\r
-#define DAC_CTRL_CNT_ENA_Msk (0x01UL << DAC_CTRL_CNT_ENA_Pos) /*!< DAC CTRL: CNT_ENA Mask */\r
-#define DAC_CTRL_DMA_ENA_Pos 3 /*!< DAC CTRL: DMA_ENA Position */\r
-#define DAC_CTRL_DMA_ENA_Msk (0x01UL << DAC_CTRL_DMA_ENA_Pos) /*!< DAC CTRL: DMA_ENA Mask */\r
-\r
-// --------------------------------------- DAC_CNTVAL -------------------------------------------\r
-#define DAC_CNTVAL_VALUE_Pos 0 /*!< DAC CNTVAL: VALUE Position */\r
-#define DAC_CNTVAL_VALUE_Msk (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos) /*!< DAC CNTVAL: VALUE Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- C_CAN0 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// --------------------------------------- C_CAN0_CNTL ------------------------------------------\r
-#define C_CAN0_CNTL_INIT_Pos 0 /*!< C_CAN0 CNTL: INIT Position */\r
-#define C_CAN0_CNTL_INIT_Msk (0x01UL << C_CAN0_CNTL_INIT_Pos) /*!< C_CAN0 CNTL: INIT Mask */\r
-#define C_CAN0_CNTL_IE_Pos 1 /*!< C_CAN0 CNTL: IE Position */\r
-#define C_CAN0_CNTL_IE_Msk (0x01UL << C_CAN0_CNTL_IE_Pos) /*!< C_CAN0 CNTL: IE Mask */\r
-#define C_CAN0_CNTL_SIE_Pos 2 /*!< C_CAN0 CNTL: SIE Position */\r
-#define C_CAN0_CNTL_SIE_Msk (0x01UL << C_CAN0_CNTL_SIE_Pos) /*!< C_CAN0 CNTL: SIE Mask */\r
-#define C_CAN0_CNTL_EIE_Pos 3 /*!< C_CAN0 CNTL: EIE Position */\r
-#define C_CAN0_CNTL_EIE_Msk (0x01UL << C_CAN0_CNTL_EIE_Pos) /*!< C_CAN0 CNTL: EIE Mask */\r
-#define C_CAN0_CNTL_DAR_Pos 5 /*!< C_CAN0 CNTL: DAR Position */\r
-#define C_CAN0_CNTL_DAR_Msk (0x01UL << C_CAN0_CNTL_DAR_Pos) /*!< C_CAN0 CNTL: DAR Mask */\r
-#define C_CAN0_CNTL_CCE_Pos 6 /*!< C_CAN0 CNTL: CCE Position */\r
-#define C_CAN0_CNTL_CCE_Msk (0x01UL << C_CAN0_CNTL_CCE_Pos) /*!< C_CAN0 CNTL: CCE Mask */\r
-#define C_CAN0_CNTL_TEST_Pos 7 /*!< C_CAN0 CNTL: TEST Position */\r
-#define C_CAN0_CNTL_TEST_Msk (0x01UL << C_CAN0_CNTL_TEST_Pos) /*!< C_CAN0 CNTL: TEST Mask */\r
-\r
-// --------------------------------------- C_CAN0_STAT ------------------------------------------\r
-#define C_CAN0_STAT_LEC_Pos 0 /*!< C_CAN0 STAT: LEC Position */\r
-#define C_CAN0_STAT_LEC_Msk (0x07UL << C_CAN0_STAT_LEC_Pos) /*!< C_CAN0 STAT: LEC Mask */\r
-#define C_CAN0_STAT_TXOK_Pos 3 /*!< C_CAN0 STAT: TXOK Position */\r
-#define C_CAN0_STAT_TXOK_Msk (0x01UL << C_CAN0_STAT_TXOK_Pos) /*!< C_CAN0 STAT: TXOK Mask */\r
-#define C_CAN0_STAT_RXOK_Pos 4 /*!< C_CAN0 STAT: RXOK Position */\r
-#define C_CAN0_STAT_RXOK_Msk (0x01UL << C_CAN0_STAT_RXOK_Pos) /*!< C_CAN0 STAT: RXOK Mask */\r
-#define C_CAN0_STAT_EPASS_Pos 5 /*!< C_CAN0 STAT: EPASS Position */\r
-#define C_CAN0_STAT_EPASS_Msk (0x01UL << C_CAN0_STAT_EPASS_Pos) /*!< C_CAN0 STAT: EPASS Mask */\r
-#define C_CAN0_STAT_EWARN_Pos 6 /*!< C_CAN0 STAT: EWARN Position */\r
-#define C_CAN0_STAT_EWARN_Msk (0x01UL << C_CAN0_STAT_EWARN_Pos) /*!< C_CAN0 STAT: EWARN Mask */\r
-#define C_CAN0_STAT_BOFF_Pos 7 /*!< C_CAN0 STAT: BOFF Position */\r
-#define C_CAN0_STAT_BOFF_Msk (0x01UL << C_CAN0_STAT_BOFF_Pos) /*!< C_CAN0 STAT: BOFF Mask */\r
-\r
-// ---------------------------------------- C_CAN0_EC -------------------------------------------\r
-#define C_CAN0_EC_TEC_7_0_Pos 0 /*!< C_CAN0 EC: TEC_7_0 Position */\r
-#define C_CAN0_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos) /*!< C_CAN0 EC: TEC_7_0 Mask */\r
-#define C_CAN0_EC_REC_6_0_Pos 8 /*!< C_CAN0 EC: REC_6_0 Position */\r
-#define C_CAN0_EC_REC_6_0_Msk (0x7fUL << C_CAN0_EC_REC_6_0_Pos) /*!< C_CAN0 EC: REC_6_0 Mask */\r
-#define C_CAN0_EC_RP_Pos 15 /*!< C_CAN0 EC: RP Position */\r
-#define C_CAN0_EC_RP_Msk (0x01UL << C_CAN0_EC_RP_Pos) /*!< C_CAN0 EC: RP Mask */\r
-\r
-// ---------------------------------------- C_CAN0_BT -------------------------------------------\r
-#define C_CAN0_BT_BRP_Pos 0 /*!< C_CAN0 BT: BRP Position */\r
-#define C_CAN0_BT_BRP_Msk (0x3fUL << C_CAN0_BT_BRP_Pos) /*!< C_CAN0 BT: BRP Mask */\r
-#define C_CAN0_BT_SJW_Pos 6 /*!< C_CAN0 BT: SJW Position */\r
-#define C_CAN0_BT_SJW_Msk (0x03UL << C_CAN0_BT_SJW_Pos) /*!< C_CAN0 BT: SJW Mask */\r
-#define C_CAN0_BT_TSEG1_Pos 8 /*!< C_CAN0 BT: TSEG1 Position */\r
-#define C_CAN0_BT_TSEG1_Msk (0x0fUL << C_CAN0_BT_TSEG1_Pos) /*!< C_CAN0 BT: TSEG1 Mask */\r
-#define C_CAN0_BT_TSEG2_Pos 12 /*!< C_CAN0 BT: TSEG2 Position */\r
-#define C_CAN0_BT_TSEG2_Msk (0x07UL << C_CAN0_BT_TSEG2_Pos) /*!< C_CAN0 BT: TSEG2 Mask */\r
-\r
-// --------------------------------------- C_CAN0_INT -------------------------------------------\r
-#define C_CAN0_INT_INTID15_0_Pos 0 /*!< C_CAN0 INT: INTID15_0 Position */\r
-#define C_CAN0_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos) /*!< C_CAN0 INT: INTID15_0 Mask */\r
-\r
-// --------------------------------------- C_CAN0_TEST ------------------------------------------\r
-#define C_CAN0_TEST_BASIC_Pos 2 /*!< C_CAN0 TEST: BASIC Position */\r
-#define C_CAN0_TEST_BASIC_Msk (0x01UL << C_CAN0_TEST_BASIC_Pos) /*!< C_CAN0 TEST: BASIC Mask */\r
-#define C_CAN0_TEST_SILENT_Pos 3 /*!< C_CAN0 TEST: SILENT Position */\r
-#define C_CAN0_TEST_SILENT_Msk (0x01UL << C_CAN0_TEST_SILENT_Pos) /*!< C_CAN0 TEST: SILENT Mask */\r
-#define C_CAN0_TEST_LBACK_Pos 4 /*!< C_CAN0 TEST: LBACK Position */\r
-#define C_CAN0_TEST_LBACK_Msk (0x01UL << C_CAN0_TEST_LBACK_Pos) /*!< C_CAN0 TEST: LBACK Mask */\r
-#define C_CAN0_TEST_TX1_0_Pos 5 /*!< C_CAN0 TEST: TX1_0 Position */\r
-#define C_CAN0_TEST_TX1_0_Msk (0x03UL << C_CAN0_TEST_TX1_0_Pos) /*!< C_CAN0 TEST: TX1_0 Mask */\r
-#define C_CAN0_TEST_RX_Pos 7 /*!< C_CAN0 TEST: RX Position */\r
-#define C_CAN0_TEST_RX_Msk (0x01UL << C_CAN0_TEST_RX_Pos) /*!< C_CAN0 TEST: RX Mask */\r
-\r
-// --------------------------------------- C_CAN0_BRPE ------------------------------------------\r
-#define C_CAN0_BRPE_BRPE_Pos 0 /*!< C_CAN0 BRPE: BRPE Position */\r
-#define C_CAN0_BRPE_BRPE_Msk (0x0fUL << C_CAN0_BRPE_BRPE_Pos) /*!< C_CAN0 BRPE: BRPE Mask */\r
-\r
-// ------------------------------------ C_CAN0_IF1_CMDREQ ---------------------------------------\r
-#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */\r
-#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask */\r
-#define C_CAN0_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF1_CMDREQ: BUSY Position */\r
-#define C_CAN0_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF1_CMDREQ: BUSY Mask */\r
-\r
-// ----------------------------------- C_CAN0_IF1_CMDMSK_R --------------------------------------\r
-#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */\r
-#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask */\r
-#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */\r
-#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask */\r
-#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */\r
-#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask */\r
-#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */\r
-#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */\r
-#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position */\r
-#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask */\r
-#define C_CAN0_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_R: ARB Position */\r
-#define C_CAN0_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask */\r
-#define C_CAN0_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_R: MASK Position */\r
-#define C_CAN0_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask */\r
-#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */\r
-#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask */\r
-\r
-// ----------------------------------- C_CAN0_IF1_CMDMSK_W --------------------------------------\r
-#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */\r
-#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask */\r
-#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */\r
-#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask */\r
-#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */\r
-#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask */\r
-#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */\r
-#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */\r
-#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position */\r
-#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask */\r
-#define C_CAN0_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_W: ARB Position */\r
-#define C_CAN0_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask */\r
-#define C_CAN0_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_W: MASK Position */\r
-#define C_CAN0_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask */\r
-#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */\r
-#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF1_MSK1 ----------------------------------------\r
-#define C_CAN0_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF1_MSK1: MSK15_0 Position */\r
-#define C_CAN0_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF1_MSK2 ----------------------------------------\r
-#define C_CAN0_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF1_MSK2: MSK28_16 Position */\r
-#define C_CAN0_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask */\r
-#define C_CAN0_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF1_MSK2: MDIR Position */\r
-#define C_CAN0_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos) /*!< C_CAN0 IF1_MSK2: MDIR Mask */\r
-#define C_CAN0_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF1_MSK2: MXTD Position */\r
-#define C_CAN0_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos) /*!< C_CAN0 IF1_MSK2: MXTD Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF1_ARB1 ----------------------------------------\r
-#define C_CAN0_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF1_ARB1: ID15_0 Position */\r
-#define C_CAN0_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos) /*!< C_CAN0 IF1_ARB1: ID15_0 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF1_ARB2 ----------------------------------------\r
-#define C_CAN0_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF1_ARB2: ID28_16 Position */\r
-#define C_CAN0_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos) /*!< C_CAN0 IF1_ARB2: ID28_16 Mask */\r
-#define C_CAN0_IF1_ARB2_DIR_Pos 13 /*!< C_CAN0 IF1_ARB2: DIR Position */\r
-#define C_CAN0_IF1_ARB2_DIR_Msk (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos) /*!< C_CAN0 IF1_ARB2: DIR Mask */\r
-#define C_CAN0_IF1_ARB2_XTD_Pos 14 /*!< C_CAN0 IF1_ARB2: XTD Position */\r
-#define C_CAN0_IF1_ARB2_XTD_Msk (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos) /*!< C_CAN0 IF1_ARB2: XTD Mask */\r
-#define C_CAN0_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF1_ARB2: MSGVAL Position */\r
-#define C_CAN0_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF1_ARB2: MSGVAL Mask */\r
-\r
-// ------------------------------------ C_CAN0_IF1_MCTRL ----------------------------------------\r
-#define C_CAN0_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position */\r
-#define C_CAN0_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask */\r
-#define C_CAN0_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF1_MCTRL: EOB Position */\r
-#define C_CAN0_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos) /*!< C_CAN0 IF1_MCTRL: EOB Mask */\r
-#define C_CAN0_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF1_MCTRL: TXRQST Position */\r
-#define C_CAN0_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF1_MCTRL: TXRQST Mask */\r
-#define C_CAN0_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF1_MCTRL: RMTEN Position */\r
-#define C_CAN0_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF1_MCTRL: RMTEN Mask */\r
-#define C_CAN0_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF1_MCTRL: RXIE Position */\r
-#define C_CAN0_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos) /*!< C_CAN0 IF1_MCTRL: RXIE Mask */\r
-#define C_CAN0_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF1_MCTRL: TXIE Position */\r
-#define C_CAN0_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos) /*!< C_CAN0 IF1_MCTRL: TXIE Mask */\r
-#define C_CAN0_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF1_MCTRL: UMASK Position */\r
-#define C_CAN0_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos) /*!< C_CAN0 IF1_MCTRL: UMASK Mask */\r
-#define C_CAN0_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF1_MCTRL: INTPND Position */\r
-#define C_CAN0_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos) /*!< C_CAN0 IF1_MCTRL: INTPND Mask */\r
-#define C_CAN0_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF1_MCTRL: MSGLST Position */\r
-#define C_CAN0_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF1_MCTRL: MSGLST Mask */\r
-#define C_CAN0_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF1_MCTRL: NEWDAT Position */\r
-#define C_CAN0_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF1_DA1 -----------------------------------------\r
-#define C_CAN0_IF1_DA1_DATA0_Pos 0 /*!< C_CAN0 IF1_DA1: DATA0 Position */\r
-#define C_CAN0_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos) /*!< C_CAN0 IF1_DA1: DATA0 Mask */\r
-#define C_CAN0_IF1_DA1_DATA1_Pos 8 /*!< C_CAN0 IF1_DA1: DATA1 Position */\r
-#define C_CAN0_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos) /*!< C_CAN0 IF1_DA1: DATA1 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF1_DA2 -----------------------------------------\r
-#define C_CAN0_IF1_DA2_DATA2_Pos 0 /*!< C_CAN0 IF1_DA2: DATA2 Position */\r
-#define C_CAN0_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos) /*!< C_CAN0 IF1_DA2: DATA2 Mask */\r
-#define C_CAN0_IF1_DA2_DATA3_Pos 8 /*!< C_CAN0 IF1_DA2: DATA3 Position */\r
-#define C_CAN0_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos) /*!< C_CAN0 IF1_DA2: DATA3 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF1_DB1 -----------------------------------------\r
-#define C_CAN0_IF1_DB1_DATA4_Pos 0 /*!< C_CAN0 IF1_DB1: DATA4 Position */\r
-#define C_CAN0_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos) /*!< C_CAN0 IF1_DB1: DATA4 Mask */\r
-#define C_CAN0_IF1_DB1_DATA5_Pos 8 /*!< C_CAN0 IF1_DB1: DATA5 Position */\r
-#define C_CAN0_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos) /*!< C_CAN0 IF1_DB1: DATA5 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF1_DB2 -----------------------------------------\r
-#define C_CAN0_IF1_DB2_DATA6_Pos 0 /*!< C_CAN0 IF1_DB2: DATA6 Position */\r
-#define C_CAN0_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos) /*!< C_CAN0 IF1_DB2: DATA6 Mask */\r
-#define C_CAN0_IF1_DB2_DATA7_Pos 8 /*!< C_CAN0 IF1_DB2: DATA7 Position */\r
-#define C_CAN0_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos) /*!< C_CAN0 IF1_DB2: DATA7 Mask */\r
-\r
-// ------------------------------------ C_CAN0_IF2_CMDREQ ---------------------------------------\r
-#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */\r
-#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask */\r
-#define C_CAN0_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF2_CMDREQ: BUSY Position */\r
-#define C_CAN0_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF2_CMDREQ: BUSY Mask */\r
-\r
-// ----------------------------------- C_CAN0_IF2_CMDMSK_R --------------------------------------\r
-#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */\r
-#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask */\r
-#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */\r
-#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask */\r
-#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */\r
-#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask */\r
-#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */\r
-#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */\r
-#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position */\r
-#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask */\r
-#define C_CAN0_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_R: ARB Position */\r
-#define C_CAN0_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask */\r
-#define C_CAN0_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_R: MASK Position */\r
-#define C_CAN0_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask */\r
-#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */\r
-#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask */\r
-\r
-// ----------------------------------- C_CAN0_IF2_CMDMSK_W --------------------------------------\r
-#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */\r
-#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask */\r
-#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */\r
-#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask */\r
-#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */\r
-#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask */\r
-#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */\r
-#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */\r
-#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position */\r
-#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask */\r
-#define C_CAN0_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_W: ARB Position */\r
-#define C_CAN0_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask */\r
-#define C_CAN0_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_W: MASK Position */\r
-#define C_CAN0_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask */\r
-#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */\r
-#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF2_MSK1 ----------------------------------------\r
-#define C_CAN0_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF2_MSK1: MSK15_0 Position */\r
-#define C_CAN0_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF2_MSK2 ----------------------------------------\r
-#define C_CAN0_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF2_MSK2: MSK28_16 Position */\r
-#define C_CAN0_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask */\r
-#define C_CAN0_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF2_MSK2: MDIR Position */\r
-#define C_CAN0_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos) /*!< C_CAN0 IF2_MSK2: MDIR Mask */\r
-#define C_CAN0_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF2_MSK2: MXTD Position */\r
-#define C_CAN0_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos) /*!< C_CAN0 IF2_MSK2: MXTD Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF2_ARB1 ----------------------------------------\r
-#define C_CAN0_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF2_ARB1: ID15_0 Position */\r
-#define C_CAN0_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos) /*!< C_CAN0 IF2_ARB1: ID15_0 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF2_ARB2 ----------------------------------------\r
-#define C_CAN0_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF2_ARB2: ID28_16 Position */\r
-#define C_CAN0_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos) /*!< C_CAN0 IF2_ARB2: ID28_16 Mask */\r
-#define C_CAN0_IF2_ARB2_DIR_Pos 13 /*!< C_CAN0 IF2_ARB2: DIR Position */\r
-#define C_CAN0_IF2_ARB2_DIR_Msk (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos) /*!< C_CAN0 IF2_ARB2: DIR Mask */\r
-#define C_CAN0_IF2_ARB2_XTD_Pos 14 /*!< C_CAN0 IF2_ARB2: XTD Position */\r
-#define C_CAN0_IF2_ARB2_XTD_Msk (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos) /*!< C_CAN0 IF2_ARB2: XTD Mask */\r
-#define C_CAN0_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF2_ARB2: MSGVAL Position */\r
-#define C_CAN0_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF2_ARB2: MSGVAL Mask */\r
-\r
-// ------------------------------------ C_CAN0_IF2_MCTRL ----------------------------------------\r
-#define C_CAN0_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position */\r
-#define C_CAN0_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask */\r
-#define C_CAN0_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF2_MCTRL: EOB Position */\r
-#define C_CAN0_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos) /*!< C_CAN0 IF2_MCTRL: EOB Mask */\r
-#define C_CAN0_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF2_MCTRL: TXRQST Position */\r
-#define C_CAN0_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF2_MCTRL: TXRQST Mask */\r
-#define C_CAN0_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF2_MCTRL: RMTEN Position */\r
-#define C_CAN0_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF2_MCTRL: RMTEN Mask */\r
-#define C_CAN0_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF2_MCTRL: RXIE Position */\r
-#define C_CAN0_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos) /*!< C_CAN0 IF2_MCTRL: RXIE Mask */\r
-#define C_CAN0_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF2_MCTRL: TXIE Position */\r
-#define C_CAN0_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos) /*!< C_CAN0 IF2_MCTRL: TXIE Mask */\r
-#define C_CAN0_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF2_MCTRL: UMASK Position */\r
-#define C_CAN0_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos) /*!< C_CAN0 IF2_MCTRL: UMASK Mask */\r
-#define C_CAN0_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF2_MCTRL: INTPND Position */\r
-#define C_CAN0_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos) /*!< C_CAN0 IF2_MCTRL: INTPND Mask */\r
-#define C_CAN0_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF2_MCTRL: MSGLST Position */\r
-#define C_CAN0_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF2_MCTRL: MSGLST Mask */\r
-#define C_CAN0_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF2_MCTRL: NEWDAT Position */\r
-#define C_CAN0_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF2_DA1 -----------------------------------------\r
-#define C_CAN0_IF2_DA1_DATA0_Pos 0 /*!< C_CAN0 IF2_DA1: DATA0 Position */\r
-#define C_CAN0_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos) /*!< C_CAN0 IF2_DA1: DATA0 Mask */\r
-#define C_CAN0_IF2_DA1_DATA1_Pos 8 /*!< C_CAN0 IF2_DA1: DATA1 Position */\r
-#define C_CAN0_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos) /*!< C_CAN0 IF2_DA1: DATA1 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF2_DA2 -----------------------------------------\r
-#define C_CAN0_IF2_DA2_DATA2_Pos 0 /*!< C_CAN0 IF2_DA2: DATA2 Position */\r
-#define C_CAN0_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos) /*!< C_CAN0 IF2_DA2: DATA2 Mask */\r
-#define C_CAN0_IF2_DA2_DATA3_Pos 8 /*!< C_CAN0 IF2_DA2: DATA3 Position */\r
-#define C_CAN0_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos) /*!< C_CAN0 IF2_DA2: DATA3 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF2_DB1 -----------------------------------------\r
-#define C_CAN0_IF2_DB1_DATA4_Pos 0 /*!< C_CAN0 IF2_DB1: DATA4 Position */\r
-#define C_CAN0_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos) /*!< C_CAN0 IF2_DB1: DATA4 Mask */\r
-#define C_CAN0_IF2_DB1_DATA5_Pos 8 /*!< C_CAN0 IF2_DB1: DATA5 Position */\r
-#define C_CAN0_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos) /*!< C_CAN0 IF2_DB1: DATA5 Mask */\r
-\r
-// ------------------------------------- C_CAN0_IF2_DB2 -----------------------------------------\r
-#define C_CAN0_IF2_DB2_DATA6_Pos 0 /*!< C_CAN0 IF2_DB2: DATA6 Position */\r
-#define C_CAN0_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos) /*!< C_CAN0 IF2_DB2: DATA6 Mask */\r
-#define C_CAN0_IF2_DB2_DATA7_Pos 8 /*!< C_CAN0 IF2_DB2: DATA7 Position */\r
-#define C_CAN0_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos) /*!< C_CAN0 IF2_DB2: DATA7 Mask */\r
-\r
-// -------------------------------------- C_CAN0_TXREQ1 -----------------------------------------\r
-#define C_CAN0_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN0 TXREQ1: TXRQST16_1 Position */\r
-#define C_CAN0_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask */\r
-\r
-// -------------------------------------- C_CAN0_TXREQ2 -----------------------------------------\r
-#define C_CAN0_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */\r
-#define C_CAN0_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask */\r
-\r
-// --------------------------------------- C_CAN0_ND1 -------------------------------------------\r
-#define C_CAN0_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN0 ND1: NEWDAT16_1 Position */\r
-#define C_CAN0_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos) /*!< C_CAN0 ND1: NEWDAT16_1 Mask */\r
-\r
-// --------------------------------------- C_CAN0_ND2 -------------------------------------------\r
-#define C_CAN0_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN0 ND2: NEWDAT32_17 Position */\r
-#define C_CAN0_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos) /*!< C_CAN0 ND2: NEWDAT32_17 Mask */\r
-\r
-// --------------------------------------- C_CAN0_IR1 -------------------------------------------\r
-#define C_CAN0_IR1_INTPND16_1_Pos 0 /*!< C_CAN0 IR1: INTPND16_1 Position */\r
-#define C_CAN0_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos) /*!< C_CAN0 IR1: INTPND16_1 Mask */\r
-\r
-// --------------------------------------- C_CAN0_IR2 -------------------------------------------\r
-#define C_CAN0_IR2_INTPND32_17_Pos 0 /*!< C_CAN0 IR2: INTPND32_17 Position */\r
-#define C_CAN0_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos) /*!< C_CAN0 IR2: INTPND32_17 Mask */\r
-\r
-// -------------------------------------- C_CAN0_MSGV1 ------------------------------------------\r
-#define C_CAN0_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN0 MSGV1: MSGVAL16_1 Position */\r
-#define C_CAN0_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask */\r
-\r
-// -------------------------------------- C_CAN0_MSGV2 ------------------------------------------\r
-#define C_CAN0_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN0 MSGV2: MSGVAL32_17 Position */\r
-#define C_CAN0_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask */\r
-\r
-// -------------------------------------- C_CAN0_CLKDIV -----------------------------------------\r
-#define C_CAN0_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN0 CLKDIV: CLKDIVVAL Position */\r
-#define C_CAN0_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- ADC0 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------- ADC0_CR --------------------------------------------\r
-#define ADC0_CR_SEL_Pos 0 /*!< ADC0 CR: SEL Position */\r
-#define ADC0_CR_SEL_Msk (0x000000ffUL << ADC0_CR_SEL_Pos) /*!< ADC0 CR: SEL Mask */\r
-#define ADC0_CR_CLKDIV_Pos 8 /*!< ADC0 CR: CLKDIV Position */\r
-#define ADC0_CR_CLKDIV_Msk (0x000000ffUL << ADC0_CR_CLKDIV_Pos) /*!< ADC0 CR: CLKDIV Mask */\r
-#define ADC0_CR_BURST_Pos 16 /*!< ADC0 CR: BURST Position */\r
-#define ADC0_CR_BURST_Msk (0x01UL << ADC0_CR_BURST_Pos) /*!< ADC0 CR: BURST Mask */\r
-#define ADC0_CR_CLKS_Pos 17 /*!< ADC0 CR: CLKS Position */\r
-#define ADC0_CR_CLKS_Msk (0x07UL << ADC0_CR_CLKS_Pos) /*!< ADC0 CR: CLKS Mask */\r
-#define ADC0_CR_PDN_Pos 21 /*!< ADC0 CR: PDN Position */\r
-#define ADC0_CR_PDN_Msk (0x01UL << ADC0_CR_PDN_Pos) /*!< ADC0 CR: PDN Mask */\r
-#define ADC0_CR_START_Pos 24 /*!< ADC0 CR: START Position */\r
-#define ADC0_CR_START_Msk (0x07UL << ADC0_CR_START_Pos) /*!< ADC0 CR: START Mask */\r
-#define ADC0_CR_EDGE_Pos 27 /*!< ADC0 CR: EDGE Position */\r
-#define ADC0_CR_EDGE_Msk (0x01UL << ADC0_CR_EDGE_Pos) /*!< ADC0 CR: EDGE Mask */\r
-\r
-// ---------------------------------------- ADC0_GDR --------------------------------------------\r
-#define ADC0_GDR_V_VREF_Pos 6 /*!< ADC0 GDR: V_VREF Position */\r
-#define ADC0_GDR_V_VREF_Msk (0x000003ffUL << ADC0_GDR_V_VREF_Pos) /*!< ADC0 GDR: V_VREF Mask */\r
-#define ADC0_GDR_CHN_Pos 24 /*!< ADC0 GDR: CHN Position */\r
-#define ADC0_GDR_CHN_Msk (0x07UL << ADC0_GDR_CHN_Pos) /*!< ADC0 GDR: CHN Mask */\r
-#define ADC0_GDR_OVERRUN_Pos 30 /*!< ADC0 GDR: OVERRUN Position */\r
-#define ADC0_GDR_OVERRUN_Msk (0x01UL << ADC0_GDR_OVERRUN_Pos) /*!< ADC0 GDR: OVERRUN Mask */\r
-#define ADC0_GDR_DONE_Pos 31 /*!< ADC0 GDR: DONE Position */\r
-#define ADC0_GDR_DONE_Msk (0x01UL << ADC0_GDR_DONE_Pos) /*!< ADC0 GDR: DONE Mask */\r
-\r
-// --------------------------------------- ADC0_INTEN -------------------------------------------\r
-#define ADC0_INTEN_ADINTEN_Pos 0 /*!< ADC0 INTEN: ADINTEN Position */\r
-#define ADC0_INTEN_ADINTEN_Msk (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos) /*!< ADC0 INTEN: ADINTEN Mask */\r
-#define ADC0_INTEN_ADGINTEN_Pos 8 /*!< ADC0 INTEN: ADGINTEN Position */\r
-#define ADC0_INTEN_ADGINTEN_Msk (0x01UL << ADC0_INTEN_ADGINTEN_Pos) /*!< ADC0 INTEN: ADGINTEN Mask */\r
-\r
-// ---------------------------------------- ADC0_DR0 --------------------------------------------\r
-#define ADC0_DR0_V_VREF_Pos 6 /*!< ADC0 DR0: V_VREF Position */\r
-#define ADC0_DR0_V_VREF_Msk (0x000003ffUL << ADC0_DR0_V_VREF_Pos) /*!< ADC0 DR0: V_VREF Mask */\r
-#define ADC0_DR0_OVERRUN_Pos 30 /*!< ADC0 DR0: OVERRUN Position */\r
-#define ADC0_DR0_OVERRUN_Msk (0x01UL << ADC0_DR0_OVERRUN_Pos) /*!< ADC0 DR0: OVERRUN Mask */\r
-#define ADC0_DR0_DONE_Pos 31 /*!< ADC0 DR0: DONE Position */\r
-#define ADC0_DR0_DONE_Msk (0x01UL << ADC0_DR0_DONE_Pos) /*!< ADC0 DR0: DONE Mask */\r
-\r
-// ---------------------------------------- ADC0_DR1 --------------------------------------------\r
-#define ADC0_DR1_V_VREF_Pos 6 /*!< ADC0 DR1: V_VREF Position */\r
-#define ADC0_DR1_V_VREF_Msk (0x000003ffUL << ADC0_DR1_V_VREF_Pos) /*!< ADC0 DR1: V_VREF Mask */\r
-#define ADC0_DR1_OVERRUN_Pos 30 /*!< ADC0 DR1: OVERRUN Position */\r
-#define ADC0_DR1_OVERRUN_Msk (0x01UL << ADC0_DR1_OVERRUN_Pos) /*!< ADC0 DR1: OVERRUN Mask */\r
-#define ADC0_DR1_DONE_Pos 31 /*!< ADC0 DR1: DONE Position */\r
-#define ADC0_DR1_DONE_Msk (0x01UL << ADC0_DR1_DONE_Pos) /*!< ADC0 DR1: DONE Mask */\r
-\r
-// ---------------------------------------- ADC0_DR2 --------------------------------------------\r
-#define ADC0_DR2_V_VREF_Pos 6 /*!< ADC0 DR2: V_VREF Position */\r
-#define ADC0_DR2_V_VREF_Msk (0x000003ffUL << ADC0_DR2_V_VREF_Pos) /*!< ADC0 DR2: V_VREF Mask */\r
-#define ADC0_DR2_OVERRUN_Pos 30 /*!< ADC0 DR2: OVERRUN Position */\r
-#define ADC0_DR2_OVERRUN_Msk (0x01UL << ADC0_DR2_OVERRUN_Pos) /*!< ADC0 DR2: OVERRUN Mask */\r
-#define ADC0_DR2_DONE_Pos 31 /*!< ADC0 DR2: DONE Position */\r
-#define ADC0_DR2_DONE_Msk (0x01UL << ADC0_DR2_DONE_Pos) /*!< ADC0 DR2: DONE Mask */\r
-\r
-// ---------------------------------------- ADC0_DR3 --------------------------------------------\r
-#define ADC0_DR3_V_VREF_Pos 6 /*!< ADC0 DR3: V_VREF Position */\r
-#define ADC0_DR3_V_VREF_Msk (0x000003ffUL << ADC0_DR3_V_VREF_Pos) /*!< ADC0 DR3: V_VREF Mask */\r
-#define ADC0_DR3_OVERRUN_Pos 30 /*!< ADC0 DR3: OVERRUN Position */\r
-#define ADC0_DR3_OVERRUN_Msk (0x01UL << ADC0_DR3_OVERRUN_Pos) /*!< ADC0 DR3: OVERRUN Mask */\r
-#define ADC0_DR3_DONE_Pos 31 /*!< ADC0 DR3: DONE Position */\r
-#define ADC0_DR3_DONE_Msk (0x01UL << ADC0_DR3_DONE_Pos) /*!< ADC0 DR3: DONE Mask */\r
-\r
-// ---------------------------------------- ADC0_DR4 --------------------------------------------\r
-#define ADC0_DR4_V_VREF_Pos 6 /*!< ADC0 DR4: V_VREF Position */\r
-#define ADC0_DR4_V_VREF_Msk (0x000003ffUL << ADC0_DR4_V_VREF_Pos) /*!< ADC0 DR4: V_VREF Mask */\r
-#define ADC0_DR4_OVERRUN_Pos 30 /*!< ADC0 DR4: OVERRUN Position */\r
-#define ADC0_DR4_OVERRUN_Msk (0x01UL << ADC0_DR4_OVERRUN_Pos) /*!< ADC0 DR4: OVERRUN Mask */\r
-#define ADC0_DR4_DONE_Pos 31 /*!< ADC0 DR4: DONE Position */\r
-#define ADC0_DR4_DONE_Msk (0x01UL << ADC0_DR4_DONE_Pos) /*!< ADC0 DR4: DONE Mask */\r
-\r
-// ---------------------------------------- ADC0_DR5 --------------------------------------------\r
-#define ADC0_DR5_V_VREF_Pos 6 /*!< ADC0 DR5: V_VREF Position */\r
-#define ADC0_DR5_V_VREF_Msk (0x000003ffUL << ADC0_DR5_V_VREF_Pos) /*!< ADC0 DR5: V_VREF Mask */\r
-#define ADC0_DR5_OVERRUN_Pos 30 /*!< ADC0 DR5: OVERRUN Position */\r
-#define ADC0_DR5_OVERRUN_Msk (0x01UL << ADC0_DR5_OVERRUN_Pos) /*!< ADC0 DR5: OVERRUN Mask */\r
-#define ADC0_DR5_DONE_Pos 31 /*!< ADC0 DR5: DONE Position */\r
-#define ADC0_DR5_DONE_Msk (0x01UL << ADC0_DR5_DONE_Pos) /*!< ADC0 DR5: DONE Mask */\r
-\r
-// ---------------------------------------- ADC0_DR6 --------------------------------------------\r
-#define ADC0_DR6_V_VREF_Pos 6 /*!< ADC0 DR6: V_VREF Position */\r
-#define ADC0_DR6_V_VREF_Msk (0x000003ffUL << ADC0_DR6_V_VREF_Pos) /*!< ADC0 DR6: V_VREF Mask */\r
-#define ADC0_DR6_OVERRUN_Pos 30 /*!< ADC0 DR6: OVERRUN Position */\r
-#define ADC0_DR6_OVERRUN_Msk (0x01UL << ADC0_DR6_OVERRUN_Pos) /*!< ADC0 DR6: OVERRUN Mask */\r
-#define ADC0_DR6_DONE_Pos 31 /*!< ADC0 DR6: DONE Position */\r
-#define ADC0_DR6_DONE_Msk (0x01UL << ADC0_DR6_DONE_Pos) /*!< ADC0 DR6: DONE Mask */\r
-\r
-// ---------------------------------------- ADC0_DR7 --------------------------------------------\r
-#define ADC0_DR7_V_VREF_Pos 6 /*!< ADC0 DR7: V_VREF Position */\r
-#define ADC0_DR7_V_VREF_Msk (0x000003ffUL << ADC0_DR7_V_VREF_Pos) /*!< ADC0 DR7: V_VREF Mask */\r
-#define ADC0_DR7_OVERRUN_Pos 30 /*!< ADC0 DR7: OVERRUN Position */\r
-#define ADC0_DR7_OVERRUN_Msk (0x01UL << ADC0_DR7_OVERRUN_Pos) /*!< ADC0 DR7: OVERRUN Mask */\r
-#define ADC0_DR7_DONE_Pos 31 /*!< ADC0 DR7: DONE Position */\r
-#define ADC0_DR7_DONE_Msk (0x01UL << ADC0_DR7_DONE_Pos) /*!< ADC0 DR7: DONE Mask */\r
-\r
-// ---------------------------------------- ADC0_STAT -------------------------------------------\r
-#define ADC0_STAT_DONE_Pos 0 /*!< ADC0 STAT: DONE Position */\r
-#define ADC0_STAT_DONE_Msk (0x000000ffUL << ADC0_STAT_DONE_Pos) /*!< ADC0 STAT: DONE Mask */\r
-#define ADC0_STAT_OVERUN_Pos 8 /*!< ADC0 STAT: OVERUN Position */\r
-#define ADC0_STAT_OVERUN_Msk (0x000000ffUL << ADC0_STAT_OVERUN_Pos) /*!< ADC0 STAT: OVERUN Mask */\r
-#define ADC0_STAT_ADINT_Pos 16 /*!< ADC0 STAT: ADINT Position */\r
-#define ADC0_STAT_ADINT_Msk (0x01UL << ADC0_STAT_ADINT_Pos) /*!< ADC0 STAT: ADINT Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- ADC1 Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------- ADC1_CR --------------------------------------------\r
-#define ADC1_CR_SEL_Pos 0 /*!< ADC1 CR: SEL Position */\r
-#define ADC1_CR_SEL_Msk (0x000000ffUL << ADC1_CR_SEL_Pos) /*!< ADC1 CR: SEL Mask */\r
-#define ADC1_CR_CLKDIV_Pos 8 /*!< ADC1 CR: CLKDIV Position */\r
-#define ADC1_CR_CLKDIV_Msk (0x000000ffUL << ADC1_CR_CLKDIV_Pos) /*!< ADC1 CR: CLKDIV Mask */\r
-#define ADC1_CR_BURST_Pos 16 /*!< ADC1 CR: BURST Position */\r
-#define ADC1_CR_BURST_Msk (0x01UL << ADC1_CR_BURST_Pos) /*!< ADC1 CR: BURST Mask */\r
-#define ADC1_CR_CLKS_Pos 17 /*!< ADC1 CR: CLKS Position */\r
-#define ADC1_CR_CLKS_Msk (0x07UL << ADC1_CR_CLKS_Pos) /*!< ADC1 CR: CLKS Mask */\r
-#define ADC1_CR_PDN_Pos 21 /*!< ADC1 CR: PDN Position */\r
-#define ADC1_CR_PDN_Msk (0x01UL << ADC1_CR_PDN_Pos) /*!< ADC1 CR: PDN Mask */\r
-#define ADC1_CR_START_Pos 24 /*!< ADC1 CR: START Position */\r
-#define ADC1_CR_START_Msk (0x07UL << ADC1_CR_START_Pos) /*!< ADC1 CR: START Mask */\r
-#define ADC1_CR_EDGE_Pos 27 /*!< ADC1 CR: EDGE Position */\r
-#define ADC1_CR_EDGE_Msk (0x01UL << ADC1_CR_EDGE_Pos) /*!< ADC1 CR: EDGE Mask */\r
-\r
-// ---------------------------------------- ADC1_GDR --------------------------------------------\r
-#define ADC1_GDR_V_VREF_Pos 6 /*!< ADC1 GDR: V_VREF Position */\r
-#define ADC1_GDR_V_VREF_Msk (0x000003ffUL << ADC1_GDR_V_VREF_Pos) /*!< ADC1 GDR: V_VREF Mask */\r
-#define ADC1_GDR_CHN_Pos 24 /*!< ADC1 GDR: CHN Position */\r
-#define ADC1_GDR_CHN_Msk (0x07UL << ADC1_GDR_CHN_Pos) /*!< ADC1 GDR: CHN Mask */\r
-#define ADC1_GDR_OVERRUN_Pos 30 /*!< ADC1 GDR: OVERRUN Position */\r
-#define ADC1_GDR_OVERRUN_Msk (0x01UL << ADC1_GDR_OVERRUN_Pos) /*!< ADC1 GDR: OVERRUN Mask */\r
-#define ADC1_GDR_DONE_Pos 31 /*!< ADC1 GDR: DONE Position */\r
-#define ADC1_GDR_DONE_Msk (0x01UL << ADC1_GDR_DONE_Pos) /*!< ADC1 GDR: DONE Mask */\r
-\r
-// --------------------------------------- ADC1_INTEN -------------------------------------------\r
-#define ADC1_INTEN_ADINTEN_Pos 0 /*!< ADC1 INTEN: ADINTEN Position */\r
-#define ADC1_INTEN_ADINTEN_Msk (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos) /*!< ADC1 INTEN: ADINTEN Mask */\r
-#define ADC1_INTEN_ADGINTEN_Pos 8 /*!< ADC1 INTEN: ADGINTEN Position */\r
-#define ADC1_INTEN_ADGINTEN_Msk (0x01UL << ADC1_INTEN_ADGINTEN_Pos) /*!< ADC1 INTEN: ADGINTEN Mask */\r
-\r
-// ---------------------------------------- ADC1_DR0 --------------------------------------------\r
-#define ADC1_DR0_V_VREF_Pos 6 /*!< ADC1 DR0: V_VREF Position */\r
-#define ADC1_DR0_V_VREF_Msk (0x000003ffUL << ADC1_DR0_V_VREF_Pos) /*!< ADC1 DR0: V_VREF Mask */\r
-#define ADC1_DR0_OVERRUN_Pos 30 /*!< ADC1 DR0: OVERRUN Position */\r
-#define ADC1_DR0_OVERRUN_Msk (0x01UL << ADC1_DR0_OVERRUN_Pos) /*!< ADC1 DR0: OVERRUN Mask */\r
-#define ADC1_DR0_DONE_Pos 31 /*!< ADC1 DR0: DONE Position */\r
-#define ADC1_DR0_DONE_Msk (0x01UL << ADC1_DR0_DONE_Pos) /*!< ADC1 DR0: DONE Mask */\r
-\r
-// ---------------------------------------- ADC1_DR1 --------------------------------------------\r
-#define ADC1_DR1_V_VREF_Pos 6 /*!< ADC1 DR1: V_VREF Position */\r
-#define ADC1_DR1_V_VREF_Msk (0x000003ffUL << ADC1_DR1_V_VREF_Pos) /*!< ADC1 DR1: V_VREF Mask */\r
-#define ADC1_DR1_OVERRUN_Pos 30 /*!< ADC1 DR1: OVERRUN Position */\r
-#define ADC1_DR1_OVERRUN_Msk (0x01UL << ADC1_DR1_OVERRUN_Pos) /*!< ADC1 DR1: OVERRUN Mask */\r
-#define ADC1_DR1_DONE_Pos 31 /*!< ADC1 DR1: DONE Position */\r
-#define ADC1_DR1_DONE_Msk (0x01UL << ADC1_DR1_DONE_Pos) /*!< ADC1 DR1: DONE Mask */\r
-\r
-// ---------------------------------------- ADC1_DR2 --------------------------------------------\r
-#define ADC1_DR2_V_VREF_Pos 6 /*!< ADC1 DR2: V_VREF Position */\r
-#define ADC1_DR2_V_VREF_Msk (0x000003ffUL << ADC1_DR2_V_VREF_Pos) /*!< ADC1 DR2: V_VREF Mask */\r
-#define ADC1_DR2_OVERRUN_Pos 30 /*!< ADC1 DR2: OVERRUN Position */\r
-#define ADC1_DR2_OVERRUN_Msk (0x01UL << ADC1_DR2_OVERRUN_Pos) /*!< ADC1 DR2: OVERRUN Mask */\r
-#define ADC1_DR2_DONE_Pos 31 /*!< ADC1 DR2: DONE Position */\r
-#define ADC1_DR2_DONE_Msk (0x01UL << ADC1_DR2_DONE_Pos) /*!< ADC1 DR2: DONE Mask */\r
-\r
-// ---------------------------------------- ADC1_DR3 --------------------------------------------\r
-#define ADC1_DR3_V_VREF_Pos 6 /*!< ADC1 DR3: V_VREF Position */\r
-#define ADC1_DR3_V_VREF_Msk (0x000003ffUL << ADC1_DR3_V_VREF_Pos) /*!< ADC1 DR3: V_VREF Mask */\r
-#define ADC1_DR3_OVERRUN_Pos 30 /*!< ADC1 DR3: OVERRUN Position */\r
-#define ADC1_DR3_OVERRUN_Msk (0x01UL << ADC1_DR3_OVERRUN_Pos) /*!< ADC1 DR3: OVERRUN Mask */\r
-#define ADC1_DR3_DONE_Pos 31 /*!< ADC1 DR3: DONE Position */\r
-#define ADC1_DR3_DONE_Msk (0x01UL << ADC1_DR3_DONE_Pos) /*!< ADC1 DR3: DONE Mask */\r
-\r
-// ---------------------------------------- ADC1_DR4 --------------------------------------------\r
-#define ADC1_DR4_V_VREF_Pos 6 /*!< ADC1 DR4: V_VREF Position */\r
-#define ADC1_DR4_V_VREF_Msk (0x000003ffUL << ADC1_DR4_V_VREF_Pos) /*!< ADC1 DR4: V_VREF Mask */\r
-#define ADC1_DR4_OVERRUN_Pos 30 /*!< ADC1 DR4: OVERRUN Position */\r
-#define ADC1_DR4_OVERRUN_Msk (0x01UL << ADC1_DR4_OVERRUN_Pos) /*!< ADC1 DR4: OVERRUN Mask */\r
-#define ADC1_DR4_DONE_Pos 31 /*!< ADC1 DR4: DONE Position */\r
-#define ADC1_DR4_DONE_Msk (0x01UL << ADC1_DR4_DONE_Pos) /*!< ADC1 DR4: DONE Mask */\r
-\r
-// ---------------------------------------- ADC1_DR5 --------------------------------------------\r
-#define ADC1_DR5_V_VREF_Pos 6 /*!< ADC1 DR5: V_VREF Position */\r
-#define ADC1_DR5_V_VREF_Msk (0x000003ffUL << ADC1_DR5_V_VREF_Pos) /*!< ADC1 DR5: V_VREF Mask */\r
-#define ADC1_DR5_OVERRUN_Pos 30 /*!< ADC1 DR5: OVERRUN Position */\r
-#define ADC1_DR5_OVERRUN_Msk (0x01UL << ADC1_DR5_OVERRUN_Pos) /*!< ADC1 DR5: OVERRUN Mask */\r
-#define ADC1_DR5_DONE_Pos 31 /*!< ADC1 DR5: DONE Position */\r
-#define ADC1_DR5_DONE_Msk (0x01UL << ADC1_DR5_DONE_Pos) /*!< ADC1 DR5: DONE Mask */\r
-\r
-// ---------------------------------------- ADC1_DR6 --------------------------------------------\r
-#define ADC1_DR6_V_VREF_Pos 6 /*!< ADC1 DR6: V_VREF Position */\r
-#define ADC1_DR6_V_VREF_Msk (0x000003ffUL << ADC1_DR6_V_VREF_Pos) /*!< ADC1 DR6: V_VREF Mask */\r
-#define ADC1_DR6_OVERRUN_Pos 30 /*!< ADC1 DR6: OVERRUN Position */\r
-#define ADC1_DR6_OVERRUN_Msk (0x01UL << ADC1_DR6_OVERRUN_Pos) /*!< ADC1 DR6: OVERRUN Mask */\r
-#define ADC1_DR6_DONE_Pos 31 /*!< ADC1 DR6: DONE Position */\r
-#define ADC1_DR6_DONE_Msk (0x01UL << ADC1_DR6_DONE_Pos) /*!< ADC1 DR6: DONE Mask */\r
-\r
-// ---------------------------------------- ADC1_DR7 --------------------------------------------\r
-#define ADC1_DR7_V_VREF_Pos 6 /*!< ADC1 DR7: V_VREF Position */\r
-#define ADC1_DR7_V_VREF_Msk (0x000003ffUL << ADC1_DR7_V_VREF_Pos) /*!< ADC1 DR7: V_VREF Mask */\r
-#define ADC1_DR7_OVERRUN_Pos 30 /*!< ADC1 DR7: OVERRUN Position */\r
-#define ADC1_DR7_OVERRUN_Msk (0x01UL << ADC1_DR7_OVERRUN_Pos) /*!< ADC1 DR7: OVERRUN Mask */\r
-#define ADC1_DR7_DONE_Pos 31 /*!< ADC1 DR7: DONE Position */\r
-#define ADC1_DR7_DONE_Msk (0x01UL << ADC1_DR7_DONE_Pos) /*!< ADC1 DR7: DONE Mask */\r
-\r
-// ---------------------------------------- ADC1_STAT -------------------------------------------\r
-#define ADC1_STAT_DONE_Pos 0 /*!< ADC1 STAT: DONE Position */\r
-#define ADC1_STAT_DONE_Msk (0x000000ffUL << ADC1_STAT_DONE_Pos) /*!< ADC1 STAT: DONE Mask */\r
-#define ADC1_STAT_OVERUN_Pos 8 /*!< ADC1 STAT: OVERUN Position */\r
-#define ADC1_STAT_OVERUN_Msk (0x000000ffUL << ADC1_STAT_OVERUN_Pos) /*!< ADC1 STAT: OVERUN Mask */\r
-#define ADC1_STAT_ADINT_Pos 16 /*!< ADC1 STAT: ADINT Position */\r
-#define ADC1_STAT_ADINT_Msk (0x01UL << ADC1_STAT_ADINT_Pos) /*!< ADC1 STAT: ADINT Mask */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- GPIO_PORT Position & Mask -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// -------------------------------------- GPIO_PORT_B0 ------------------------------------------\r
-#define GPIO_PORT_B0_PBYTE_Pos 0 /*!< GPIO_PORT B0: PBYTE Position */\r
-#define GPIO_PORT_B0_PBYTE_Msk (0x01UL << GPIO_PORT_B0_PBYTE_Pos) /*!< GPIO_PORT B0: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B1 ------------------------------------------\r
-#define GPIO_PORT_B1_PBYTE_Pos 0 /*!< GPIO_PORT B1: PBYTE Position */\r
-#define GPIO_PORT_B1_PBYTE_Msk (0x01UL << GPIO_PORT_B1_PBYTE_Pos) /*!< GPIO_PORT B1: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B2 ------------------------------------------\r
-#define GPIO_PORT_B2_PBYTE_Pos 0 /*!< GPIO_PORT B2: PBYTE Position */\r
-#define GPIO_PORT_B2_PBYTE_Msk (0x01UL << GPIO_PORT_B2_PBYTE_Pos) /*!< GPIO_PORT B2: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B3 ------------------------------------------\r
-#define GPIO_PORT_B3_PBYTE_Pos 0 /*!< GPIO_PORT B3: PBYTE Position */\r
-#define GPIO_PORT_B3_PBYTE_Msk (0x01UL << GPIO_PORT_B3_PBYTE_Pos) /*!< GPIO_PORT B3: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B4 ------------------------------------------\r
-#define GPIO_PORT_B4_PBYTE_Pos 0 /*!< GPIO_PORT B4: PBYTE Position */\r
-#define GPIO_PORT_B4_PBYTE_Msk (0x01UL << GPIO_PORT_B4_PBYTE_Pos) /*!< GPIO_PORT B4: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B5 ------------------------------------------\r
-#define GPIO_PORT_B5_PBYTE_Pos 0 /*!< GPIO_PORT B5: PBYTE Position */\r
-#define GPIO_PORT_B5_PBYTE_Msk (0x01UL << GPIO_PORT_B5_PBYTE_Pos) /*!< GPIO_PORT B5: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B6 ------------------------------------------\r
-#define GPIO_PORT_B6_PBYTE_Pos 0 /*!< GPIO_PORT B6: PBYTE Position */\r
-#define GPIO_PORT_B6_PBYTE_Msk (0x01UL << GPIO_PORT_B6_PBYTE_Pos) /*!< GPIO_PORT B6: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B7 ------------------------------------------\r
-#define GPIO_PORT_B7_PBYTE_Pos 0 /*!< GPIO_PORT B7: PBYTE Position */\r
-#define GPIO_PORT_B7_PBYTE_Msk (0x01UL << GPIO_PORT_B7_PBYTE_Pos) /*!< GPIO_PORT B7: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B8 ------------------------------------------\r
-#define GPIO_PORT_B8_PBYTE_Pos 0 /*!< GPIO_PORT B8: PBYTE Position */\r
-#define GPIO_PORT_B8_PBYTE_Msk (0x01UL << GPIO_PORT_B8_PBYTE_Pos) /*!< GPIO_PORT B8: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B9 ------------------------------------------\r
-#define GPIO_PORT_B9_PBYTE_Pos 0 /*!< GPIO_PORT B9: PBYTE Position */\r
-#define GPIO_PORT_B9_PBYTE_Msk (0x01UL << GPIO_PORT_B9_PBYTE_Pos) /*!< GPIO_PORT B9: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B10 -----------------------------------------\r
-#define GPIO_PORT_B10_PBYTE_Pos 0 /*!< GPIO_PORT B10: PBYTE Position */\r
-#define GPIO_PORT_B10_PBYTE_Msk (0x01UL << GPIO_PORT_B10_PBYTE_Pos) /*!< GPIO_PORT B10: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B11 -----------------------------------------\r
-#define GPIO_PORT_B11_PBYTE_Pos 0 /*!< GPIO_PORT B11: PBYTE Position */\r
-#define GPIO_PORT_B11_PBYTE_Msk (0x01UL << GPIO_PORT_B11_PBYTE_Pos) /*!< GPIO_PORT B11: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B12 -----------------------------------------\r
-#define GPIO_PORT_B12_PBYTE_Pos 0 /*!< GPIO_PORT B12: PBYTE Position */\r
-#define GPIO_PORT_B12_PBYTE_Msk (0x01UL << GPIO_PORT_B12_PBYTE_Pos) /*!< GPIO_PORT B12: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B13 -----------------------------------------\r
-#define GPIO_PORT_B13_PBYTE_Pos 0 /*!< GPIO_PORT B13: PBYTE Position */\r
-#define GPIO_PORT_B13_PBYTE_Msk (0x01UL << GPIO_PORT_B13_PBYTE_Pos) /*!< GPIO_PORT B13: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B14 -----------------------------------------\r
-#define GPIO_PORT_B14_PBYTE_Pos 0 /*!< GPIO_PORT B14: PBYTE Position */\r
-#define GPIO_PORT_B14_PBYTE_Msk (0x01UL << GPIO_PORT_B14_PBYTE_Pos) /*!< GPIO_PORT B14: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B15 -----------------------------------------\r
-#define GPIO_PORT_B15_PBYTE_Pos 0 /*!< GPIO_PORT B15: PBYTE Position */\r
-#define GPIO_PORT_B15_PBYTE_Msk (0x01UL << GPIO_PORT_B15_PBYTE_Pos) /*!< GPIO_PORT B15: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B16 -----------------------------------------\r
-#define GPIO_PORT_B16_PBYTE_Pos 0 /*!< GPIO_PORT B16: PBYTE Position */\r
-#define GPIO_PORT_B16_PBYTE_Msk (0x01UL << GPIO_PORT_B16_PBYTE_Pos) /*!< GPIO_PORT B16: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B17 -----------------------------------------\r
-#define GPIO_PORT_B17_PBYTE_Pos 0 /*!< GPIO_PORT B17: PBYTE Position */\r
-#define GPIO_PORT_B17_PBYTE_Msk (0x01UL << GPIO_PORT_B17_PBYTE_Pos) /*!< GPIO_PORT B17: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B18 -----------------------------------------\r
-#define GPIO_PORT_B18_PBYTE_Pos 0 /*!< GPIO_PORT B18: PBYTE Position */\r
-#define GPIO_PORT_B18_PBYTE_Msk (0x01UL << GPIO_PORT_B18_PBYTE_Pos) /*!< GPIO_PORT B18: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B19 -----------------------------------------\r
-#define GPIO_PORT_B19_PBYTE_Pos 0 /*!< GPIO_PORT B19: PBYTE Position */\r
-#define GPIO_PORT_B19_PBYTE_Msk (0x01UL << GPIO_PORT_B19_PBYTE_Pos) /*!< GPIO_PORT B19: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B20 -----------------------------------------\r
-#define GPIO_PORT_B20_PBYTE_Pos 0 /*!< GPIO_PORT B20: PBYTE Position */\r
-#define GPIO_PORT_B20_PBYTE_Msk (0x01UL << GPIO_PORT_B20_PBYTE_Pos) /*!< GPIO_PORT B20: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B21 -----------------------------------------\r
-#define GPIO_PORT_B21_PBYTE_Pos 0 /*!< GPIO_PORT B21: PBYTE Position */\r
-#define GPIO_PORT_B21_PBYTE_Msk (0x01UL << GPIO_PORT_B21_PBYTE_Pos) /*!< GPIO_PORT B21: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B22 -----------------------------------------\r
-#define GPIO_PORT_B22_PBYTE_Pos 0 /*!< GPIO_PORT B22: PBYTE Position */\r
-#define GPIO_PORT_B22_PBYTE_Msk (0x01UL << GPIO_PORT_B22_PBYTE_Pos) /*!< GPIO_PORT B22: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B23 -----------------------------------------\r
-#define GPIO_PORT_B23_PBYTE_Pos 0 /*!< GPIO_PORT B23: PBYTE Position */\r
-#define GPIO_PORT_B23_PBYTE_Msk (0x01UL << GPIO_PORT_B23_PBYTE_Pos) /*!< GPIO_PORT B23: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B24 -----------------------------------------\r
-#define GPIO_PORT_B24_PBYTE_Pos 0 /*!< GPIO_PORT B24: PBYTE Position */\r
-#define GPIO_PORT_B24_PBYTE_Msk (0x01UL << GPIO_PORT_B24_PBYTE_Pos) /*!< GPIO_PORT B24: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B25 -----------------------------------------\r
-#define GPIO_PORT_B25_PBYTE_Pos 0 /*!< GPIO_PORT B25: PBYTE Position */\r
-#define GPIO_PORT_B25_PBYTE_Msk (0x01UL << GPIO_PORT_B25_PBYTE_Pos) /*!< GPIO_PORT B25: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B26 -----------------------------------------\r
-#define GPIO_PORT_B26_PBYTE_Pos 0 /*!< GPIO_PORT B26: PBYTE Position */\r
-#define GPIO_PORT_B26_PBYTE_Msk (0x01UL << GPIO_PORT_B26_PBYTE_Pos) /*!< GPIO_PORT B26: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B27 -----------------------------------------\r
-#define GPIO_PORT_B27_PBYTE_Pos 0 /*!< GPIO_PORT B27: PBYTE Position */\r
-#define GPIO_PORT_B27_PBYTE_Msk (0x01UL << GPIO_PORT_B27_PBYTE_Pos) /*!< GPIO_PORT B27: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B28 -----------------------------------------\r
-#define GPIO_PORT_B28_PBYTE_Pos 0 /*!< GPIO_PORT B28: PBYTE Position */\r
-#define GPIO_PORT_B28_PBYTE_Msk (0x01UL << GPIO_PORT_B28_PBYTE_Pos) /*!< GPIO_PORT B28: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B29 -----------------------------------------\r
-#define GPIO_PORT_B29_PBYTE_Pos 0 /*!< GPIO_PORT B29: PBYTE Position */\r
-#define GPIO_PORT_B29_PBYTE_Msk (0x01UL << GPIO_PORT_B29_PBYTE_Pos) /*!< GPIO_PORT B29: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B30 -----------------------------------------\r
-#define GPIO_PORT_B30_PBYTE_Pos 0 /*!< GPIO_PORT B30: PBYTE Position */\r
-#define GPIO_PORT_B30_PBYTE_Msk (0x01UL << GPIO_PORT_B30_PBYTE_Pos) /*!< GPIO_PORT B30: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B31 -----------------------------------------\r
-#define GPIO_PORT_B31_PBYTE_Pos 0 /*!< GPIO_PORT B31: PBYTE Position */\r
-#define GPIO_PORT_B31_PBYTE_Msk (0x01UL << GPIO_PORT_B31_PBYTE_Pos) /*!< GPIO_PORT B31: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B32 -----------------------------------------\r
-#define GPIO_PORT_B32_PBYTE_Pos 0 /*!< GPIO_PORT B32: PBYTE Position */\r
-#define GPIO_PORT_B32_PBYTE_Msk (0x01UL << GPIO_PORT_B32_PBYTE_Pos) /*!< GPIO_PORT B32: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B33 -----------------------------------------\r
-#define GPIO_PORT_B33_PBYTE_Pos 0 /*!< GPIO_PORT B33: PBYTE Position */\r
-#define GPIO_PORT_B33_PBYTE_Msk (0x01UL << GPIO_PORT_B33_PBYTE_Pos) /*!< GPIO_PORT B33: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B34 -----------------------------------------\r
-#define GPIO_PORT_B34_PBYTE_Pos 0 /*!< GPIO_PORT B34: PBYTE Position */\r
-#define GPIO_PORT_B34_PBYTE_Msk (0x01UL << GPIO_PORT_B34_PBYTE_Pos) /*!< GPIO_PORT B34: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B35 -----------------------------------------\r
-#define GPIO_PORT_B35_PBYTE_Pos 0 /*!< GPIO_PORT B35: PBYTE Position */\r
-#define GPIO_PORT_B35_PBYTE_Msk (0x01UL << GPIO_PORT_B35_PBYTE_Pos) /*!< GPIO_PORT B35: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B36 -----------------------------------------\r
-#define GPIO_PORT_B36_PBYTE_Pos 0 /*!< GPIO_PORT B36: PBYTE Position */\r
-#define GPIO_PORT_B36_PBYTE_Msk (0x01UL << GPIO_PORT_B36_PBYTE_Pos) /*!< GPIO_PORT B36: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B37 -----------------------------------------\r
-#define GPIO_PORT_B37_PBYTE_Pos 0 /*!< GPIO_PORT B37: PBYTE Position */\r
-#define GPIO_PORT_B37_PBYTE_Msk (0x01UL << GPIO_PORT_B37_PBYTE_Pos) /*!< GPIO_PORT B37: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B38 -----------------------------------------\r
-#define GPIO_PORT_B38_PBYTE_Pos 0 /*!< GPIO_PORT B38: PBYTE Position */\r
-#define GPIO_PORT_B38_PBYTE_Msk (0x01UL << GPIO_PORT_B38_PBYTE_Pos) /*!< GPIO_PORT B38: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B39 -----------------------------------------\r
-#define GPIO_PORT_B39_PBYTE_Pos 0 /*!< GPIO_PORT B39: PBYTE Position */\r
-#define GPIO_PORT_B39_PBYTE_Msk (0x01UL << GPIO_PORT_B39_PBYTE_Pos) /*!< GPIO_PORT B39: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B40 -----------------------------------------\r
-#define GPIO_PORT_B40_PBYTE_Pos 0 /*!< GPIO_PORT B40: PBYTE Position */\r
-#define GPIO_PORT_B40_PBYTE_Msk (0x01UL << GPIO_PORT_B40_PBYTE_Pos) /*!< GPIO_PORT B40: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B41 -----------------------------------------\r
-#define GPIO_PORT_B41_PBYTE_Pos 0 /*!< GPIO_PORT B41: PBYTE Position */\r
-#define GPIO_PORT_B41_PBYTE_Msk (0x01UL << GPIO_PORT_B41_PBYTE_Pos) /*!< GPIO_PORT B41: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B42 -----------------------------------------\r
-#define GPIO_PORT_B42_PBYTE_Pos 0 /*!< GPIO_PORT B42: PBYTE Position */\r
-#define GPIO_PORT_B42_PBYTE_Msk (0x01UL << GPIO_PORT_B42_PBYTE_Pos) /*!< GPIO_PORT B42: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B43 -----------------------------------------\r
-#define GPIO_PORT_B43_PBYTE_Pos 0 /*!< GPIO_PORT B43: PBYTE Position */\r
-#define GPIO_PORT_B43_PBYTE_Msk (0x01UL << GPIO_PORT_B43_PBYTE_Pos) /*!< GPIO_PORT B43: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B44 -----------------------------------------\r
-#define GPIO_PORT_B44_PBYTE_Pos 0 /*!< GPIO_PORT B44: PBYTE Position */\r
-#define GPIO_PORT_B44_PBYTE_Msk (0x01UL << GPIO_PORT_B44_PBYTE_Pos) /*!< GPIO_PORT B44: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B45 -----------------------------------------\r
-#define GPIO_PORT_B45_PBYTE_Pos 0 /*!< GPIO_PORT B45: PBYTE Position */\r
-#define GPIO_PORT_B45_PBYTE_Msk (0x01UL << GPIO_PORT_B45_PBYTE_Pos) /*!< GPIO_PORT B45: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B46 -----------------------------------------\r
-#define GPIO_PORT_B46_PBYTE_Pos 0 /*!< GPIO_PORT B46: PBYTE Position */\r
-#define GPIO_PORT_B46_PBYTE_Msk (0x01UL << GPIO_PORT_B46_PBYTE_Pos) /*!< GPIO_PORT B46: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B47 -----------------------------------------\r
-#define GPIO_PORT_B47_PBYTE_Pos 0 /*!< GPIO_PORT B47: PBYTE Position */\r
-#define GPIO_PORT_B47_PBYTE_Msk (0x01UL << GPIO_PORT_B47_PBYTE_Pos) /*!< GPIO_PORT B47: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B48 -----------------------------------------\r
-#define GPIO_PORT_B48_PBYTE_Pos 0 /*!< GPIO_PORT B48: PBYTE Position */\r
-#define GPIO_PORT_B48_PBYTE_Msk (0x01UL << GPIO_PORT_B48_PBYTE_Pos) /*!< GPIO_PORT B48: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B49 -----------------------------------------\r
-#define GPIO_PORT_B49_PBYTE_Pos 0 /*!< GPIO_PORT B49: PBYTE Position */\r
-#define GPIO_PORT_B49_PBYTE_Msk (0x01UL << GPIO_PORT_B49_PBYTE_Pos) /*!< GPIO_PORT B49: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B50 -----------------------------------------\r
-#define GPIO_PORT_B50_PBYTE_Pos 0 /*!< GPIO_PORT B50: PBYTE Position */\r
-#define GPIO_PORT_B50_PBYTE_Msk (0x01UL << GPIO_PORT_B50_PBYTE_Pos) /*!< GPIO_PORT B50: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B51 -----------------------------------------\r
-#define GPIO_PORT_B51_PBYTE_Pos 0 /*!< GPIO_PORT B51: PBYTE Position */\r
-#define GPIO_PORT_B51_PBYTE_Msk (0x01UL << GPIO_PORT_B51_PBYTE_Pos) /*!< GPIO_PORT B51: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B52 -----------------------------------------\r
-#define GPIO_PORT_B52_PBYTE_Pos 0 /*!< GPIO_PORT B52: PBYTE Position */\r
-#define GPIO_PORT_B52_PBYTE_Msk (0x01UL << GPIO_PORT_B52_PBYTE_Pos) /*!< GPIO_PORT B52: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B53 -----------------------------------------\r
-#define GPIO_PORT_B53_PBYTE_Pos 0 /*!< GPIO_PORT B53: PBYTE Position */\r
-#define GPIO_PORT_B53_PBYTE_Msk (0x01UL << GPIO_PORT_B53_PBYTE_Pos) /*!< GPIO_PORT B53: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B54 -----------------------------------------\r
-#define GPIO_PORT_B54_PBYTE_Pos 0 /*!< GPIO_PORT B54: PBYTE Position */\r
-#define GPIO_PORT_B54_PBYTE_Msk (0x01UL << GPIO_PORT_B54_PBYTE_Pos) /*!< GPIO_PORT B54: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B55 -----------------------------------------\r
-#define GPIO_PORT_B55_PBYTE_Pos 0 /*!< GPIO_PORT B55: PBYTE Position */\r
-#define GPIO_PORT_B55_PBYTE_Msk (0x01UL << GPIO_PORT_B55_PBYTE_Pos) /*!< GPIO_PORT B55: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B56 -----------------------------------------\r
-#define GPIO_PORT_B56_PBYTE_Pos 0 /*!< GPIO_PORT B56: PBYTE Position */\r
-#define GPIO_PORT_B56_PBYTE_Msk (0x01UL << GPIO_PORT_B56_PBYTE_Pos) /*!< GPIO_PORT B56: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B57 -----------------------------------------\r
-#define GPIO_PORT_B57_PBYTE_Pos 0 /*!< GPIO_PORT B57: PBYTE Position */\r
-#define GPIO_PORT_B57_PBYTE_Msk (0x01UL << GPIO_PORT_B57_PBYTE_Pos) /*!< GPIO_PORT B57: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B58 -----------------------------------------\r
-#define GPIO_PORT_B58_PBYTE_Pos 0 /*!< GPIO_PORT B58: PBYTE Position */\r
-#define GPIO_PORT_B58_PBYTE_Msk (0x01UL << GPIO_PORT_B58_PBYTE_Pos) /*!< GPIO_PORT B58: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B59 -----------------------------------------\r
-#define GPIO_PORT_B59_PBYTE_Pos 0 /*!< GPIO_PORT B59: PBYTE Position */\r
-#define GPIO_PORT_B59_PBYTE_Msk (0x01UL << GPIO_PORT_B59_PBYTE_Pos) /*!< GPIO_PORT B59: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B60 -----------------------------------------\r
-#define GPIO_PORT_B60_PBYTE_Pos 0 /*!< GPIO_PORT B60: PBYTE Position */\r
-#define GPIO_PORT_B60_PBYTE_Msk (0x01UL << GPIO_PORT_B60_PBYTE_Pos) /*!< GPIO_PORT B60: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B61 -----------------------------------------\r
-#define GPIO_PORT_B61_PBYTE_Pos 0 /*!< GPIO_PORT B61: PBYTE Position */\r
-#define GPIO_PORT_B61_PBYTE_Msk (0x01UL << GPIO_PORT_B61_PBYTE_Pos) /*!< GPIO_PORT B61: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B62 -----------------------------------------\r
-#define GPIO_PORT_B62_PBYTE_Pos 0 /*!< GPIO_PORT B62: PBYTE Position */\r
-#define GPIO_PORT_B62_PBYTE_Msk (0x01UL << GPIO_PORT_B62_PBYTE_Pos) /*!< GPIO_PORT B62: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B63 -----------------------------------------\r
-#define GPIO_PORT_B63_PBYTE_Pos 0 /*!< GPIO_PORT B63: PBYTE Position */\r
-#define GPIO_PORT_B63_PBYTE_Msk (0x01UL << GPIO_PORT_B63_PBYTE_Pos) /*!< GPIO_PORT B63: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B64 -----------------------------------------\r
-#define GPIO_PORT_B64_PBYTE_Pos 0 /*!< GPIO_PORT B64: PBYTE Position */\r
-#define GPIO_PORT_B64_PBYTE_Msk (0x01UL << GPIO_PORT_B64_PBYTE_Pos) /*!< GPIO_PORT B64: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B65 -----------------------------------------\r
-#define GPIO_PORT_B65_PBYTE_Pos 0 /*!< GPIO_PORT B65: PBYTE Position */\r
-#define GPIO_PORT_B65_PBYTE_Msk (0x01UL << GPIO_PORT_B65_PBYTE_Pos) /*!< GPIO_PORT B65: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B66 -----------------------------------------\r
-#define GPIO_PORT_B66_PBYTE_Pos 0 /*!< GPIO_PORT B66: PBYTE Position */\r
-#define GPIO_PORT_B66_PBYTE_Msk (0x01UL << GPIO_PORT_B66_PBYTE_Pos) /*!< GPIO_PORT B66: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B67 -----------------------------------------\r
-#define GPIO_PORT_B67_PBYTE_Pos 0 /*!< GPIO_PORT B67: PBYTE Position */\r
-#define GPIO_PORT_B67_PBYTE_Msk (0x01UL << GPIO_PORT_B67_PBYTE_Pos) /*!< GPIO_PORT B67: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B68 -----------------------------------------\r
-#define GPIO_PORT_B68_PBYTE_Pos 0 /*!< GPIO_PORT B68: PBYTE Position */\r
-#define GPIO_PORT_B68_PBYTE_Msk (0x01UL << GPIO_PORT_B68_PBYTE_Pos) /*!< GPIO_PORT B68: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B69 -----------------------------------------\r
-#define GPIO_PORT_B69_PBYTE_Pos 0 /*!< GPIO_PORT B69: PBYTE Position */\r
-#define GPIO_PORT_B69_PBYTE_Msk (0x01UL << GPIO_PORT_B69_PBYTE_Pos) /*!< GPIO_PORT B69: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B70 -----------------------------------------\r
-#define GPIO_PORT_B70_PBYTE_Pos 0 /*!< GPIO_PORT B70: PBYTE Position */\r
-#define GPIO_PORT_B70_PBYTE_Msk (0x01UL << GPIO_PORT_B70_PBYTE_Pos) /*!< GPIO_PORT B70: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B71 -----------------------------------------\r
-#define GPIO_PORT_B71_PBYTE_Pos 0 /*!< GPIO_PORT B71: PBYTE Position */\r
-#define GPIO_PORT_B71_PBYTE_Msk (0x01UL << GPIO_PORT_B71_PBYTE_Pos) /*!< GPIO_PORT B71: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B72 -----------------------------------------\r
-#define GPIO_PORT_B72_PBYTE_Pos 0 /*!< GPIO_PORT B72: PBYTE Position */\r
-#define GPIO_PORT_B72_PBYTE_Msk (0x01UL << GPIO_PORT_B72_PBYTE_Pos) /*!< GPIO_PORT B72: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B73 -----------------------------------------\r
-#define GPIO_PORT_B73_PBYTE_Pos 0 /*!< GPIO_PORT B73: PBYTE Position */\r
-#define GPIO_PORT_B73_PBYTE_Msk (0x01UL << GPIO_PORT_B73_PBYTE_Pos) /*!< GPIO_PORT B73: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B74 -----------------------------------------\r
-#define GPIO_PORT_B74_PBYTE_Pos 0 /*!< GPIO_PORT B74: PBYTE Position */\r
-#define GPIO_PORT_B74_PBYTE_Msk (0x01UL << GPIO_PORT_B74_PBYTE_Pos) /*!< GPIO_PORT B74: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B75 -----------------------------------------\r
-#define GPIO_PORT_B75_PBYTE_Pos 0 /*!< GPIO_PORT B75: PBYTE Position */\r
-#define GPIO_PORT_B75_PBYTE_Msk (0x01UL << GPIO_PORT_B75_PBYTE_Pos) /*!< GPIO_PORT B75: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B76 -----------------------------------------\r
-#define GPIO_PORT_B76_PBYTE_Pos 0 /*!< GPIO_PORT B76: PBYTE Position */\r
-#define GPIO_PORT_B76_PBYTE_Msk (0x01UL << GPIO_PORT_B76_PBYTE_Pos) /*!< GPIO_PORT B76: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B77 -----------------------------------------\r
-#define GPIO_PORT_B77_PBYTE_Pos 0 /*!< GPIO_PORT B77: PBYTE Position */\r
-#define GPIO_PORT_B77_PBYTE_Msk (0x01UL << GPIO_PORT_B77_PBYTE_Pos) /*!< GPIO_PORT B77: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B78 -----------------------------------------\r
-#define GPIO_PORT_B78_PBYTE_Pos 0 /*!< GPIO_PORT B78: PBYTE Position */\r
-#define GPIO_PORT_B78_PBYTE_Msk (0x01UL << GPIO_PORT_B78_PBYTE_Pos) /*!< GPIO_PORT B78: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B79 -----------------------------------------\r
-#define GPIO_PORT_B79_PBYTE_Pos 0 /*!< GPIO_PORT B79: PBYTE Position */\r
-#define GPIO_PORT_B79_PBYTE_Msk (0x01UL << GPIO_PORT_B79_PBYTE_Pos) /*!< GPIO_PORT B79: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B80 -----------------------------------------\r
-#define GPIO_PORT_B80_PBYTE_Pos 0 /*!< GPIO_PORT B80: PBYTE Position */\r
-#define GPIO_PORT_B80_PBYTE_Msk (0x01UL << GPIO_PORT_B80_PBYTE_Pos) /*!< GPIO_PORT B80: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B81 -----------------------------------------\r
-#define GPIO_PORT_B81_PBYTE_Pos 0 /*!< GPIO_PORT B81: PBYTE Position */\r
-#define GPIO_PORT_B81_PBYTE_Msk (0x01UL << GPIO_PORT_B81_PBYTE_Pos) /*!< GPIO_PORT B81: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B82 -----------------------------------------\r
-#define GPIO_PORT_B82_PBYTE_Pos 0 /*!< GPIO_PORT B82: PBYTE Position */\r
-#define GPIO_PORT_B82_PBYTE_Msk (0x01UL << GPIO_PORT_B82_PBYTE_Pos) /*!< GPIO_PORT B82: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B83 -----------------------------------------\r
-#define GPIO_PORT_B83_PBYTE_Pos 0 /*!< GPIO_PORT B83: PBYTE Position */\r
-#define GPIO_PORT_B83_PBYTE_Msk (0x01UL << GPIO_PORT_B83_PBYTE_Pos) /*!< GPIO_PORT B83: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B84 -----------------------------------------\r
-#define GPIO_PORT_B84_PBYTE_Pos 0 /*!< GPIO_PORT B84: PBYTE Position */\r
-#define GPIO_PORT_B84_PBYTE_Msk (0x01UL << GPIO_PORT_B84_PBYTE_Pos) /*!< GPIO_PORT B84: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B85 -----------------------------------------\r
-#define GPIO_PORT_B85_PBYTE_Pos 0 /*!< GPIO_PORT B85: PBYTE Position */\r
-#define GPIO_PORT_B85_PBYTE_Msk (0x01UL << GPIO_PORT_B85_PBYTE_Pos) /*!< GPIO_PORT B85: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B86 -----------------------------------------\r
-#define GPIO_PORT_B86_PBYTE_Pos 0 /*!< GPIO_PORT B86: PBYTE Position */\r
-#define GPIO_PORT_B86_PBYTE_Msk (0x01UL << GPIO_PORT_B86_PBYTE_Pos) /*!< GPIO_PORT B86: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B87 -----------------------------------------\r
-#define GPIO_PORT_B87_PBYTE_Pos 0 /*!< GPIO_PORT B87: PBYTE Position */\r
-#define GPIO_PORT_B87_PBYTE_Msk (0x01UL << GPIO_PORT_B87_PBYTE_Pos) /*!< GPIO_PORT B87: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B88 -----------------------------------------\r
-#define GPIO_PORT_B88_PBYTE_Pos 0 /*!< GPIO_PORT B88: PBYTE Position */\r
-#define GPIO_PORT_B88_PBYTE_Msk (0x01UL << GPIO_PORT_B88_PBYTE_Pos) /*!< GPIO_PORT B88: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B89 -----------------------------------------\r
-#define GPIO_PORT_B89_PBYTE_Pos 0 /*!< GPIO_PORT B89: PBYTE Position */\r
-#define GPIO_PORT_B89_PBYTE_Msk (0x01UL << GPIO_PORT_B89_PBYTE_Pos) /*!< GPIO_PORT B89: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B90 -----------------------------------------\r
-#define GPIO_PORT_B90_PBYTE_Pos 0 /*!< GPIO_PORT B90: PBYTE Position */\r
-#define GPIO_PORT_B90_PBYTE_Msk (0x01UL << GPIO_PORT_B90_PBYTE_Pos) /*!< GPIO_PORT B90: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B91 -----------------------------------------\r
-#define GPIO_PORT_B91_PBYTE_Pos 0 /*!< GPIO_PORT B91: PBYTE Position */\r
-#define GPIO_PORT_B91_PBYTE_Msk (0x01UL << GPIO_PORT_B91_PBYTE_Pos) /*!< GPIO_PORT B91: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B92 -----------------------------------------\r
-#define GPIO_PORT_B92_PBYTE_Pos 0 /*!< GPIO_PORT B92: PBYTE Position */\r
-#define GPIO_PORT_B92_PBYTE_Msk (0x01UL << GPIO_PORT_B92_PBYTE_Pos) /*!< GPIO_PORT B92: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B93 -----------------------------------------\r
-#define GPIO_PORT_B93_PBYTE_Pos 0 /*!< GPIO_PORT B93: PBYTE Position */\r
-#define GPIO_PORT_B93_PBYTE_Msk (0x01UL << GPIO_PORT_B93_PBYTE_Pos) /*!< GPIO_PORT B93: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B94 -----------------------------------------\r
-#define GPIO_PORT_B94_PBYTE_Pos 0 /*!< GPIO_PORT B94: PBYTE Position */\r
-#define GPIO_PORT_B94_PBYTE_Msk (0x01UL << GPIO_PORT_B94_PBYTE_Pos) /*!< GPIO_PORT B94: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B95 -----------------------------------------\r
-#define GPIO_PORT_B95_PBYTE_Pos 0 /*!< GPIO_PORT B95: PBYTE Position */\r
-#define GPIO_PORT_B95_PBYTE_Msk (0x01UL << GPIO_PORT_B95_PBYTE_Pos) /*!< GPIO_PORT B95: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B96 -----------------------------------------\r
-#define GPIO_PORT_B96_PBYTE_Pos 0 /*!< GPIO_PORT B96: PBYTE Position */\r
-#define GPIO_PORT_B96_PBYTE_Msk (0x01UL << GPIO_PORT_B96_PBYTE_Pos) /*!< GPIO_PORT B96: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B97 -----------------------------------------\r
-#define GPIO_PORT_B97_PBYTE_Pos 0 /*!< GPIO_PORT B97: PBYTE Position */\r
-#define GPIO_PORT_B97_PBYTE_Msk (0x01UL << GPIO_PORT_B97_PBYTE_Pos) /*!< GPIO_PORT B97: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B98 -----------------------------------------\r
-#define GPIO_PORT_B98_PBYTE_Pos 0 /*!< GPIO_PORT B98: PBYTE Position */\r
-#define GPIO_PORT_B98_PBYTE_Msk (0x01UL << GPIO_PORT_B98_PBYTE_Pos) /*!< GPIO_PORT B98: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_B99 -----------------------------------------\r
-#define GPIO_PORT_B99_PBYTE_Pos 0 /*!< GPIO_PORT B99: PBYTE Position */\r
-#define GPIO_PORT_B99_PBYTE_Msk (0x01UL << GPIO_PORT_B99_PBYTE_Pos) /*!< GPIO_PORT B99: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B100 -----------------------------------------\r
-#define GPIO_PORT_B100_PBYTE_Pos 0 /*!< GPIO_PORT B100: PBYTE Position */\r
-#define GPIO_PORT_B100_PBYTE_Msk (0x01UL << GPIO_PORT_B100_PBYTE_Pos) /*!< GPIO_PORT B100: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B101 -----------------------------------------\r
-#define GPIO_PORT_B101_PBYTE_Pos 0 /*!< GPIO_PORT B101: PBYTE Position */\r
-#define GPIO_PORT_B101_PBYTE_Msk (0x01UL << GPIO_PORT_B101_PBYTE_Pos) /*!< GPIO_PORT B101: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B102 -----------------------------------------\r
-#define GPIO_PORT_B102_PBYTE_Pos 0 /*!< GPIO_PORT B102: PBYTE Position */\r
-#define GPIO_PORT_B102_PBYTE_Msk (0x01UL << GPIO_PORT_B102_PBYTE_Pos) /*!< GPIO_PORT B102: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B103 -----------------------------------------\r
-#define GPIO_PORT_B103_PBYTE_Pos 0 /*!< GPIO_PORT B103: PBYTE Position */\r
-#define GPIO_PORT_B103_PBYTE_Msk (0x01UL << GPIO_PORT_B103_PBYTE_Pos) /*!< GPIO_PORT B103: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B104 -----------------------------------------\r
-#define GPIO_PORT_B104_PBYTE_Pos 0 /*!< GPIO_PORT B104: PBYTE Position */\r
-#define GPIO_PORT_B104_PBYTE_Msk (0x01UL << GPIO_PORT_B104_PBYTE_Pos) /*!< GPIO_PORT B104: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B105 -----------------------------------------\r
-#define GPIO_PORT_B105_PBYTE_Pos 0 /*!< GPIO_PORT B105: PBYTE Position */\r
-#define GPIO_PORT_B105_PBYTE_Msk (0x01UL << GPIO_PORT_B105_PBYTE_Pos) /*!< GPIO_PORT B105: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B106 -----------------------------------------\r
-#define GPIO_PORT_B106_PBYTE_Pos 0 /*!< GPIO_PORT B106: PBYTE Position */\r
-#define GPIO_PORT_B106_PBYTE_Msk (0x01UL << GPIO_PORT_B106_PBYTE_Pos) /*!< GPIO_PORT B106: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B107 -----------------------------------------\r
-#define GPIO_PORT_B107_PBYTE_Pos 0 /*!< GPIO_PORT B107: PBYTE Position */\r
-#define GPIO_PORT_B107_PBYTE_Msk (0x01UL << GPIO_PORT_B107_PBYTE_Pos) /*!< GPIO_PORT B107: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B108 -----------------------------------------\r
-#define GPIO_PORT_B108_PBYTE_Pos 0 /*!< GPIO_PORT B108: PBYTE Position */\r
-#define GPIO_PORT_B108_PBYTE_Msk (0x01UL << GPIO_PORT_B108_PBYTE_Pos) /*!< GPIO_PORT B108: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B109 -----------------------------------------\r
-#define GPIO_PORT_B109_PBYTE_Pos 0 /*!< GPIO_PORT B109: PBYTE Position */\r
-#define GPIO_PORT_B109_PBYTE_Msk (0x01UL << GPIO_PORT_B109_PBYTE_Pos) /*!< GPIO_PORT B109: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B110 -----------------------------------------\r
-#define GPIO_PORT_B110_PBYTE_Pos 0 /*!< GPIO_PORT B110: PBYTE Position */\r
-#define GPIO_PORT_B110_PBYTE_Msk (0x01UL << GPIO_PORT_B110_PBYTE_Pos) /*!< GPIO_PORT B110: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B111 -----------------------------------------\r
-#define GPIO_PORT_B111_PBYTE_Pos 0 /*!< GPIO_PORT B111: PBYTE Position */\r
-#define GPIO_PORT_B111_PBYTE_Msk (0x01UL << GPIO_PORT_B111_PBYTE_Pos) /*!< GPIO_PORT B111: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B112 -----------------------------------------\r
-#define GPIO_PORT_B112_PBYTE_Pos 0 /*!< GPIO_PORT B112: PBYTE Position */\r
-#define GPIO_PORT_B112_PBYTE_Msk (0x01UL << GPIO_PORT_B112_PBYTE_Pos) /*!< GPIO_PORT B112: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B113 -----------------------------------------\r
-#define GPIO_PORT_B113_PBYTE_Pos 0 /*!< GPIO_PORT B113: PBYTE Position */\r
-#define GPIO_PORT_B113_PBYTE_Msk (0x01UL << GPIO_PORT_B113_PBYTE_Pos) /*!< GPIO_PORT B113: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B114 -----------------------------------------\r
-#define GPIO_PORT_B114_PBYTE_Pos 0 /*!< GPIO_PORT B114: PBYTE Position */\r
-#define GPIO_PORT_B114_PBYTE_Msk (0x01UL << GPIO_PORT_B114_PBYTE_Pos) /*!< GPIO_PORT B114: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B115 -----------------------------------------\r
-#define GPIO_PORT_B115_PBYTE_Pos 0 /*!< GPIO_PORT B115: PBYTE Position */\r
-#define GPIO_PORT_B115_PBYTE_Msk (0x01UL << GPIO_PORT_B115_PBYTE_Pos) /*!< GPIO_PORT B115: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B116 -----------------------------------------\r
-#define GPIO_PORT_B116_PBYTE_Pos 0 /*!< GPIO_PORT B116: PBYTE Position */\r
-#define GPIO_PORT_B116_PBYTE_Msk (0x01UL << GPIO_PORT_B116_PBYTE_Pos) /*!< GPIO_PORT B116: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B117 -----------------------------------------\r
-#define GPIO_PORT_B117_PBYTE_Pos 0 /*!< GPIO_PORT B117: PBYTE Position */\r
-#define GPIO_PORT_B117_PBYTE_Msk (0x01UL << GPIO_PORT_B117_PBYTE_Pos) /*!< GPIO_PORT B117: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B118 -----------------------------------------\r
-#define GPIO_PORT_B118_PBYTE_Pos 0 /*!< GPIO_PORT B118: PBYTE Position */\r
-#define GPIO_PORT_B118_PBYTE_Msk (0x01UL << GPIO_PORT_B118_PBYTE_Pos) /*!< GPIO_PORT B118: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B119 -----------------------------------------\r
-#define GPIO_PORT_B119_PBYTE_Pos 0 /*!< GPIO_PORT B119: PBYTE Position */\r
-#define GPIO_PORT_B119_PBYTE_Msk (0x01UL << GPIO_PORT_B119_PBYTE_Pos) /*!< GPIO_PORT B119: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B120 -----------------------------------------\r
-#define GPIO_PORT_B120_PBYTE_Pos 0 /*!< GPIO_PORT B120: PBYTE Position */\r
-#define GPIO_PORT_B120_PBYTE_Msk (0x01UL << GPIO_PORT_B120_PBYTE_Pos) /*!< GPIO_PORT B120: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B121 -----------------------------------------\r
-#define GPIO_PORT_B121_PBYTE_Pos 0 /*!< GPIO_PORT B121: PBYTE Position */\r
-#define GPIO_PORT_B121_PBYTE_Msk (0x01UL << GPIO_PORT_B121_PBYTE_Pos) /*!< GPIO_PORT B121: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B122 -----------------------------------------\r
-#define GPIO_PORT_B122_PBYTE_Pos 0 /*!< GPIO_PORT B122: PBYTE Position */\r
-#define GPIO_PORT_B122_PBYTE_Msk (0x01UL << GPIO_PORT_B122_PBYTE_Pos) /*!< GPIO_PORT B122: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B123 -----------------------------------------\r
-#define GPIO_PORT_B123_PBYTE_Pos 0 /*!< GPIO_PORT B123: PBYTE Position */\r
-#define GPIO_PORT_B123_PBYTE_Msk (0x01UL << GPIO_PORT_B123_PBYTE_Pos) /*!< GPIO_PORT B123: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B124 -----------------------------------------\r
-#define GPIO_PORT_B124_PBYTE_Pos 0 /*!< GPIO_PORT B124: PBYTE Position */\r
-#define GPIO_PORT_B124_PBYTE_Msk (0x01UL << GPIO_PORT_B124_PBYTE_Pos) /*!< GPIO_PORT B124: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B125 -----------------------------------------\r
-#define GPIO_PORT_B125_PBYTE_Pos 0 /*!< GPIO_PORT B125: PBYTE Position */\r
-#define GPIO_PORT_B125_PBYTE_Msk (0x01UL << GPIO_PORT_B125_PBYTE_Pos) /*!< GPIO_PORT B125: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B126 -----------------------------------------\r
-#define GPIO_PORT_B126_PBYTE_Pos 0 /*!< GPIO_PORT B126: PBYTE Position */\r
-#define GPIO_PORT_B126_PBYTE_Msk (0x01UL << GPIO_PORT_B126_PBYTE_Pos) /*!< GPIO_PORT B126: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B127 -----------------------------------------\r
-#define GPIO_PORT_B127_PBYTE_Pos 0 /*!< GPIO_PORT B127: PBYTE Position */\r
-#define GPIO_PORT_B127_PBYTE_Msk (0x01UL << GPIO_PORT_B127_PBYTE_Pos) /*!< GPIO_PORT B127: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B128 -----------------------------------------\r
-#define GPIO_PORT_B128_PBYTE_Pos 0 /*!< GPIO_PORT B128: PBYTE Position */\r
-#define GPIO_PORT_B128_PBYTE_Msk (0x01UL << GPIO_PORT_B128_PBYTE_Pos) /*!< GPIO_PORT B128: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B129 -----------------------------------------\r
-#define GPIO_PORT_B129_PBYTE_Pos 0 /*!< GPIO_PORT B129: PBYTE Position */\r
-#define GPIO_PORT_B129_PBYTE_Msk (0x01UL << GPIO_PORT_B129_PBYTE_Pos) /*!< GPIO_PORT B129: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B130 -----------------------------------------\r
-#define GPIO_PORT_B130_PBYTE_Pos 0 /*!< GPIO_PORT B130: PBYTE Position */\r
-#define GPIO_PORT_B130_PBYTE_Msk (0x01UL << GPIO_PORT_B130_PBYTE_Pos) /*!< GPIO_PORT B130: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B131 -----------------------------------------\r
-#define GPIO_PORT_B131_PBYTE_Pos 0 /*!< GPIO_PORT B131: PBYTE Position */\r
-#define GPIO_PORT_B131_PBYTE_Msk (0x01UL << GPIO_PORT_B131_PBYTE_Pos) /*!< GPIO_PORT B131: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B132 -----------------------------------------\r
-#define GPIO_PORT_B132_PBYTE_Pos 0 /*!< GPIO_PORT B132: PBYTE Position */\r
-#define GPIO_PORT_B132_PBYTE_Msk (0x01UL << GPIO_PORT_B132_PBYTE_Pos) /*!< GPIO_PORT B132: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B133 -----------------------------------------\r
-#define GPIO_PORT_B133_PBYTE_Pos 0 /*!< GPIO_PORT B133: PBYTE Position */\r
-#define GPIO_PORT_B133_PBYTE_Msk (0x01UL << GPIO_PORT_B133_PBYTE_Pos) /*!< GPIO_PORT B133: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B134 -----------------------------------------\r
-#define GPIO_PORT_B134_PBYTE_Pos 0 /*!< GPIO_PORT B134: PBYTE Position */\r
-#define GPIO_PORT_B134_PBYTE_Msk (0x01UL << GPIO_PORT_B134_PBYTE_Pos) /*!< GPIO_PORT B134: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B135 -----------------------------------------\r
-#define GPIO_PORT_B135_PBYTE_Pos 0 /*!< GPIO_PORT B135: PBYTE Position */\r
-#define GPIO_PORT_B135_PBYTE_Msk (0x01UL << GPIO_PORT_B135_PBYTE_Pos) /*!< GPIO_PORT B135: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B136 -----------------------------------------\r
-#define GPIO_PORT_B136_PBYTE_Pos 0 /*!< GPIO_PORT B136: PBYTE Position */\r
-#define GPIO_PORT_B136_PBYTE_Msk (0x01UL << GPIO_PORT_B136_PBYTE_Pos) /*!< GPIO_PORT B136: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B137 -----------------------------------------\r
-#define GPIO_PORT_B137_PBYTE_Pos 0 /*!< GPIO_PORT B137: PBYTE Position */\r
-#define GPIO_PORT_B137_PBYTE_Msk (0x01UL << GPIO_PORT_B137_PBYTE_Pos) /*!< GPIO_PORT B137: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B138 -----------------------------------------\r
-#define GPIO_PORT_B138_PBYTE_Pos 0 /*!< GPIO_PORT B138: PBYTE Position */\r
-#define GPIO_PORT_B138_PBYTE_Msk (0x01UL << GPIO_PORT_B138_PBYTE_Pos) /*!< GPIO_PORT B138: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B139 -----------------------------------------\r
-#define GPIO_PORT_B139_PBYTE_Pos 0 /*!< GPIO_PORT B139: PBYTE Position */\r
-#define GPIO_PORT_B139_PBYTE_Msk (0x01UL << GPIO_PORT_B139_PBYTE_Pos) /*!< GPIO_PORT B139: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B140 -----------------------------------------\r
-#define GPIO_PORT_B140_PBYTE_Pos 0 /*!< GPIO_PORT B140: PBYTE Position */\r
-#define GPIO_PORT_B140_PBYTE_Msk (0x01UL << GPIO_PORT_B140_PBYTE_Pos) /*!< GPIO_PORT B140: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B141 -----------------------------------------\r
-#define GPIO_PORT_B141_PBYTE_Pos 0 /*!< GPIO_PORT B141: PBYTE Position */\r
-#define GPIO_PORT_B141_PBYTE_Msk (0x01UL << GPIO_PORT_B141_PBYTE_Pos) /*!< GPIO_PORT B141: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B142 -----------------------------------------\r
-#define GPIO_PORT_B142_PBYTE_Pos 0 /*!< GPIO_PORT B142: PBYTE Position */\r
-#define GPIO_PORT_B142_PBYTE_Msk (0x01UL << GPIO_PORT_B142_PBYTE_Pos) /*!< GPIO_PORT B142: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B143 -----------------------------------------\r
-#define GPIO_PORT_B143_PBYTE_Pos 0 /*!< GPIO_PORT B143: PBYTE Position */\r
-#define GPIO_PORT_B143_PBYTE_Msk (0x01UL << GPIO_PORT_B143_PBYTE_Pos) /*!< GPIO_PORT B143: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B144 -----------------------------------------\r
-#define GPIO_PORT_B144_PBYTE_Pos 0 /*!< GPIO_PORT B144: PBYTE Position */\r
-#define GPIO_PORT_B144_PBYTE_Msk (0x01UL << GPIO_PORT_B144_PBYTE_Pos) /*!< GPIO_PORT B144: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B145 -----------------------------------------\r
-#define GPIO_PORT_B145_PBYTE_Pos 0 /*!< GPIO_PORT B145: PBYTE Position */\r
-#define GPIO_PORT_B145_PBYTE_Msk (0x01UL << GPIO_PORT_B145_PBYTE_Pos) /*!< GPIO_PORT B145: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B146 -----------------------------------------\r
-#define GPIO_PORT_B146_PBYTE_Pos 0 /*!< GPIO_PORT B146: PBYTE Position */\r
-#define GPIO_PORT_B146_PBYTE_Msk (0x01UL << GPIO_PORT_B146_PBYTE_Pos) /*!< GPIO_PORT B146: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B147 -----------------------------------------\r
-#define GPIO_PORT_B147_PBYTE_Pos 0 /*!< GPIO_PORT B147: PBYTE Position */\r
-#define GPIO_PORT_B147_PBYTE_Msk (0x01UL << GPIO_PORT_B147_PBYTE_Pos) /*!< GPIO_PORT B147: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B148 -----------------------------------------\r
-#define GPIO_PORT_B148_PBYTE_Pos 0 /*!< GPIO_PORT B148: PBYTE Position */\r
-#define GPIO_PORT_B148_PBYTE_Msk (0x01UL << GPIO_PORT_B148_PBYTE_Pos) /*!< GPIO_PORT B148: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B149 -----------------------------------------\r
-#define GPIO_PORT_B149_PBYTE_Pos 0 /*!< GPIO_PORT B149: PBYTE Position */\r
-#define GPIO_PORT_B149_PBYTE_Msk (0x01UL << GPIO_PORT_B149_PBYTE_Pos) /*!< GPIO_PORT B149: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B150 -----------------------------------------\r
-#define GPIO_PORT_B150_PBYTE_Pos 0 /*!< GPIO_PORT B150: PBYTE Position */\r
-#define GPIO_PORT_B150_PBYTE_Msk (0x01UL << GPIO_PORT_B150_PBYTE_Pos) /*!< GPIO_PORT B150: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B151 -----------------------------------------\r
-#define GPIO_PORT_B151_PBYTE_Pos 0 /*!< GPIO_PORT B151: PBYTE Position */\r
-#define GPIO_PORT_B151_PBYTE_Msk (0x01UL << GPIO_PORT_B151_PBYTE_Pos) /*!< GPIO_PORT B151: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B152 -----------------------------------------\r
-#define GPIO_PORT_B152_PBYTE_Pos 0 /*!< GPIO_PORT B152: PBYTE Position */\r
-#define GPIO_PORT_B152_PBYTE_Msk (0x01UL << GPIO_PORT_B152_PBYTE_Pos) /*!< GPIO_PORT B152: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B153 -----------------------------------------\r
-#define GPIO_PORT_B153_PBYTE_Pos 0 /*!< GPIO_PORT B153: PBYTE Position */\r
-#define GPIO_PORT_B153_PBYTE_Msk (0x01UL << GPIO_PORT_B153_PBYTE_Pos) /*!< GPIO_PORT B153: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B154 -----------------------------------------\r
-#define GPIO_PORT_B154_PBYTE_Pos 0 /*!< GPIO_PORT B154: PBYTE Position */\r
-#define GPIO_PORT_B154_PBYTE_Msk (0x01UL << GPIO_PORT_B154_PBYTE_Pos) /*!< GPIO_PORT B154: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B155 -----------------------------------------\r
-#define GPIO_PORT_B155_PBYTE_Pos 0 /*!< GPIO_PORT B155: PBYTE Position */\r
-#define GPIO_PORT_B155_PBYTE_Msk (0x01UL << GPIO_PORT_B155_PBYTE_Pos) /*!< GPIO_PORT B155: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B156 -----------------------------------------\r
-#define GPIO_PORT_B156_PBYTE_Pos 0 /*!< GPIO_PORT B156: PBYTE Position */\r
-#define GPIO_PORT_B156_PBYTE_Msk (0x01UL << GPIO_PORT_B156_PBYTE_Pos) /*!< GPIO_PORT B156: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B157 -----------------------------------------\r
-#define GPIO_PORT_B157_PBYTE_Pos 0 /*!< GPIO_PORT B157: PBYTE Position */\r
-#define GPIO_PORT_B157_PBYTE_Msk (0x01UL << GPIO_PORT_B157_PBYTE_Pos) /*!< GPIO_PORT B157: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B158 -----------------------------------------\r
-#define GPIO_PORT_B158_PBYTE_Pos 0 /*!< GPIO_PORT B158: PBYTE Position */\r
-#define GPIO_PORT_B158_PBYTE_Msk (0x01UL << GPIO_PORT_B158_PBYTE_Pos) /*!< GPIO_PORT B158: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B159 -----------------------------------------\r
-#define GPIO_PORT_B159_PBYTE_Pos 0 /*!< GPIO_PORT B159: PBYTE Position */\r
-#define GPIO_PORT_B159_PBYTE_Msk (0x01UL << GPIO_PORT_B159_PBYTE_Pos) /*!< GPIO_PORT B159: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B160 -----------------------------------------\r
-#define GPIO_PORT_B160_PBYTE_Pos 0 /*!< GPIO_PORT B160: PBYTE Position */\r
-#define GPIO_PORT_B160_PBYTE_Msk (0x01UL << GPIO_PORT_B160_PBYTE_Pos) /*!< GPIO_PORT B160: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B161 -----------------------------------------\r
-#define GPIO_PORT_B161_PBYTE_Pos 0 /*!< GPIO_PORT B161: PBYTE Position */\r
-#define GPIO_PORT_B161_PBYTE_Msk (0x01UL << GPIO_PORT_B161_PBYTE_Pos) /*!< GPIO_PORT B161: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B162 -----------------------------------------\r
-#define GPIO_PORT_B162_PBYTE_Pos 0 /*!< GPIO_PORT B162: PBYTE Position */\r
-#define GPIO_PORT_B162_PBYTE_Msk (0x01UL << GPIO_PORT_B162_PBYTE_Pos) /*!< GPIO_PORT B162: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B163 -----------------------------------------\r
-#define GPIO_PORT_B163_PBYTE_Pos 0 /*!< GPIO_PORT B163: PBYTE Position */\r
-#define GPIO_PORT_B163_PBYTE_Msk (0x01UL << GPIO_PORT_B163_PBYTE_Pos) /*!< GPIO_PORT B163: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B164 -----------------------------------------\r
-#define GPIO_PORT_B164_PBYTE_Pos 0 /*!< GPIO_PORT B164: PBYTE Position */\r
-#define GPIO_PORT_B164_PBYTE_Msk (0x01UL << GPIO_PORT_B164_PBYTE_Pos) /*!< GPIO_PORT B164: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B165 -----------------------------------------\r
-#define GPIO_PORT_B165_PBYTE_Pos 0 /*!< GPIO_PORT B165: PBYTE Position */\r
-#define GPIO_PORT_B165_PBYTE_Msk (0x01UL << GPIO_PORT_B165_PBYTE_Pos) /*!< GPIO_PORT B165: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B166 -----------------------------------------\r
-#define GPIO_PORT_B166_PBYTE_Pos 0 /*!< GPIO_PORT B166: PBYTE Position */\r
-#define GPIO_PORT_B166_PBYTE_Msk (0x01UL << GPIO_PORT_B166_PBYTE_Pos) /*!< GPIO_PORT B166: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B167 -----------------------------------------\r
-#define GPIO_PORT_B167_PBYTE_Pos 0 /*!< GPIO_PORT B167: PBYTE Position */\r
-#define GPIO_PORT_B167_PBYTE_Msk (0x01UL << GPIO_PORT_B167_PBYTE_Pos) /*!< GPIO_PORT B167: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B168 -----------------------------------------\r
-#define GPIO_PORT_B168_PBYTE_Pos 0 /*!< GPIO_PORT B168: PBYTE Position */\r
-#define GPIO_PORT_B168_PBYTE_Msk (0x01UL << GPIO_PORT_B168_PBYTE_Pos) /*!< GPIO_PORT B168: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B169 -----------------------------------------\r
-#define GPIO_PORT_B169_PBYTE_Pos 0 /*!< GPIO_PORT B169: PBYTE Position */\r
-#define GPIO_PORT_B169_PBYTE_Msk (0x01UL << GPIO_PORT_B169_PBYTE_Pos) /*!< GPIO_PORT B169: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B170 -----------------------------------------\r
-#define GPIO_PORT_B170_PBYTE_Pos 0 /*!< GPIO_PORT B170: PBYTE Position */\r
-#define GPIO_PORT_B170_PBYTE_Msk (0x01UL << GPIO_PORT_B170_PBYTE_Pos) /*!< GPIO_PORT B170: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B171 -----------------------------------------\r
-#define GPIO_PORT_B171_PBYTE_Pos 0 /*!< GPIO_PORT B171: PBYTE Position */\r
-#define GPIO_PORT_B171_PBYTE_Msk (0x01UL << GPIO_PORT_B171_PBYTE_Pos) /*!< GPIO_PORT B171: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B172 -----------------------------------------\r
-#define GPIO_PORT_B172_PBYTE_Pos 0 /*!< GPIO_PORT B172: PBYTE Position */\r
-#define GPIO_PORT_B172_PBYTE_Msk (0x01UL << GPIO_PORT_B172_PBYTE_Pos) /*!< GPIO_PORT B172: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B173 -----------------------------------------\r
-#define GPIO_PORT_B173_PBYTE_Pos 0 /*!< GPIO_PORT B173: PBYTE Position */\r
-#define GPIO_PORT_B173_PBYTE_Msk (0x01UL << GPIO_PORT_B173_PBYTE_Pos) /*!< GPIO_PORT B173: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B174 -----------------------------------------\r
-#define GPIO_PORT_B174_PBYTE_Pos 0 /*!< GPIO_PORT B174: PBYTE Position */\r
-#define GPIO_PORT_B174_PBYTE_Msk (0x01UL << GPIO_PORT_B174_PBYTE_Pos) /*!< GPIO_PORT B174: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B175 -----------------------------------------\r
-#define GPIO_PORT_B175_PBYTE_Pos 0 /*!< GPIO_PORT B175: PBYTE Position */\r
-#define GPIO_PORT_B175_PBYTE_Msk (0x01UL << GPIO_PORT_B175_PBYTE_Pos) /*!< GPIO_PORT B175: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B176 -----------------------------------------\r
-#define GPIO_PORT_B176_PBYTE_Pos 0 /*!< GPIO_PORT B176: PBYTE Position */\r
-#define GPIO_PORT_B176_PBYTE_Msk (0x01UL << GPIO_PORT_B176_PBYTE_Pos) /*!< GPIO_PORT B176: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B177 -----------------------------------------\r
-#define GPIO_PORT_B177_PBYTE_Pos 0 /*!< GPIO_PORT B177: PBYTE Position */\r
-#define GPIO_PORT_B177_PBYTE_Msk (0x01UL << GPIO_PORT_B177_PBYTE_Pos) /*!< GPIO_PORT B177: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B178 -----------------------------------------\r
-#define GPIO_PORT_B178_PBYTE_Pos 0 /*!< GPIO_PORT B178: PBYTE Position */\r
-#define GPIO_PORT_B178_PBYTE_Msk (0x01UL << GPIO_PORT_B178_PBYTE_Pos) /*!< GPIO_PORT B178: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B179 -----------------------------------------\r
-#define GPIO_PORT_B179_PBYTE_Pos 0 /*!< GPIO_PORT B179: PBYTE Position */\r
-#define GPIO_PORT_B179_PBYTE_Msk (0x01UL << GPIO_PORT_B179_PBYTE_Pos) /*!< GPIO_PORT B179: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B180 -----------------------------------------\r
-#define GPIO_PORT_B180_PBYTE_Pos 0 /*!< GPIO_PORT B180: PBYTE Position */\r
-#define GPIO_PORT_B180_PBYTE_Msk (0x01UL << GPIO_PORT_B180_PBYTE_Pos) /*!< GPIO_PORT B180: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B181 -----------------------------------------\r
-#define GPIO_PORT_B181_PBYTE_Pos 0 /*!< GPIO_PORT B181: PBYTE Position */\r
-#define GPIO_PORT_B181_PBYTE_Msk (0x01UL << GPIO_PORT_B181_PBYTE_Pos) /*!< GPIO_PORT B181: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B182 -----------------------------------------\r
-#define GPIO_PORT_B182_PBYTE_Pos 0 /*!< GPIO_PORT B182: PBYTE Position */\r
-#define GPIO_PORT_B182_PBYTE_Msk (0x01UL << GPIO_PORT_B182_PBYTE_Pos) /*!< GPIO_PORT B182: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B183 -----------------------------------------\r
-#define GPIO_PORT_B183_PBYTE_Pos 0 /*!< GPIO_PORT B183: PBYTE Position */\r
-#define GPIO_PORT_B183_PBYTE_Msk (0x01UL << GPIO_PORT_B183_PBYTE_Pos) /*!< GPIO_PORT B183: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B184 -----------------------------------------\r
-#define GPIO_PORT_B184_PBYTE_Pos 0 /*!< GPIO_PORT B184: PBYTE Position */\r
-#define GPIO_PORT_B184_PBYTE_Msk (0x01UL << GPIO_PORT_B184_PBYTE_Pos) /*!< GPIO_PORT B184: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B185 -----------------------------------------\r
-#define GPIO_PORT_B185_PBYTE_Pos 0 /*!< GPIO_PORT B185: PBYTE Position */\r
-#define GPIO_PORT_B185_PBYTE_Msk (0x01UL << GPIO_PORT_B185_PBYTE_Pos) /*!< GPIO_PORT B185: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B186 -----------------------------------------\r
-#define GPIO_PORT_B186_PBYTE_Pos 0 /*!< GPIO_PORT B186: PBYTE Position */\r
-#define GPIO_PORT_B186_PBYTE_Msk (0x01UL << GPIO_PORT_B186_PBYTE_Pos) /*!< GPIO_PORT B186: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B187 -----------------------------------------\r
-#define GPIO_PORT_B187_PBYTE_Pos 0 /*!< GPIO_PORT B187: PBYTE Position */\r
-#define GPIO_PORT_B187_PBYTE_Msk (0x01UL << GPIO_PORT_B187_PBYTE_Pos) /*!< GPIO_PORT B187: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B188 -----------------------------------------\r
-#define GPIO_PORT_B188_PBYTE_Pos 0 /*!< GPIO_PORT B188: PBYTE Position */\r
-#define GPIO_PORT_B188_PBYTE_Msk (0x01UL << GPIO_PORT_B188_PBYTE_Pos) /*!< GPIO_PORT B188: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B189 -----------------------------------------\r
-#define GPIO_PORT_B189_PBYTE_Pos 0 /*!< GPIO_PORT B189: PBYTE Position */\r
-#define GPIO_PORT_B189_PBYTE_Msk (0x01UL << GPIO_PORT_B189_PBYTE_Pos) /*!< GPIO_PORT B189: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B190 -----------------------------------------\r
-#define GPIO_PORT_B190_PBYTE_Pos 0 /*!< GPIO_PORT B190: PBYTE Position */\r
-#define GPIO_PORT_B190_PBYTE_Msk (0x01UL << GPIO_PORT_B190_PBYTE_Pos) /*!< GPIO_PORT B190: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B191 -----------------------------------------\r
-#define GPIO_PORT_B191_PBYTE_Pos 0 /*!< GPIO_PORT B191: PBYTE Position */\r
-#define GPIO_PORT_B191_PBYTE_Msk (0x01UL << GPIO_PORT_B191_PBYTE_Pos) /*!< GPIO_PORT B191: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B192 -----------------------------------------\r
-#define GPIO_PORT_B192_PBYTE_Pos 0 /*!< GPIO_PORT B192: PBYTE Position */\r
-#define GPIO_PORT_B192_PBYTE_Msk (0x01UL << GPIO_PORT_B192_PBYTE_Pos) /*!< GPIO_PORT B192: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B193 -----------------------------------------\r
-#define GPIO_PORT_B193_PBYTE_Pos 0 /*!< GPIO_PORT B193: PBYTE Position */\r
-#define GPIO_PORT_B193_PBYTE_Msk (0x01UL << GPIO_PORT_B193_PBYTE_Pos) /*!< GPIO_PORT B193: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B194 -----------------------------------------\r
-#define GPIO_PORT_B194_PBYTE_Pos 0 /*!< GPIO_PORT B194: PBYTE Position */\r
-#define GPIO_PORT_B194_PBYTE_Msk (0x01UL << GPIO_PORT_B194_PBYTE_Pos) /*!< GPIO_PORT B194: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B195 -----------------------------------------\r
-#define GPIO_PORT_B195_PBYTE_Pos 0 /*!< GPIO_PORT B195: PBYTE Position */\r
-#define GPIO_PORT_B195_PBYTE_Msk (0x01UL << GPIO_PORT_B195_PBYTE_Pos) /*!< GPIO_PORT B195: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B196 -----------------------------------------\r
-#define GPIO_PORT_B196_PBYTE_Pos 0 /*!< GPIO_PORT B196: PBYTE Position */\r
-#define GPIO_PORT_B196_PBYTE_Msk (0x01UL << GPIO_PORT_B196_PBYTE_Pos) /*!< GPIO_PORT B196: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B197 -----------------------------------------\r
-#define GPIO_PORT_B197_PBYTE_Pos 0 /*!< GPIO_PORT B197: PBYTE Position */\r
-#define GPIO_PORT_B197_PBYTE_Msk (0x01UL << GPIO_PORT_B197_PBYTE_Pos) /*!< GPIO_PORT B197: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B198 -----------------------------------------\r
-#define GPIO_PORT_B198_PBYTE_Pos 0 /*!< GPIO_PORT B198: PBYTE Position */\r
-#define GPIO_PORT_B198_PBYTE_Msk (0x01UL << GPIO_PORT_B198_PBYTE_Pos) /*!< GPIO_PORT B198: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B199 -----------------------------------------\r
-#define GPIO_PORT_B199_PBYTE_Pos 0 /*!< GPIO_PORT B199: PBYTE Position */\r
-#define GPIO_PORT_B199_PBYTE_Msk (0x01UL << GPIO_PORT_B199_PBYTE_Pos) /*!< GPIO_PORT B199: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B200 -----------------------------------------\r
-#define GPIO_PORT_B200_PBYTE_Pos 0 /*!< GPIO_PORT B200: PBYTE Position */\r
-#define GPIO_PORT_B200_PBYTE_Msk (0x01UL << GPIO_PORT_B200_PBYTE_Pos) /*!< GPIO_PORT B200: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B201 -----------------------------------------\r
-#define GPIO_PORT_B201_PBYTE_Pos 0 /*!< GPIO_PORT B201: PBYTE Position */\r
-#define GPIO_PORT_B201_PBYTE_Msk (0x01UL << GPIO_PORT_B201_PBYTE_Pos) /*!< GPIO_PORT B201: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B202 -----------------------------------------\r
-#define GPIO_PORT_B202_PBYTE_Pos 0 /*!< GPIO_PORT B202: PBYTE Position */\r
-#define GPIO_PORT_B202_PBYTE_Msk (0x01UL << GPIO_PORT_B202_PBYTE_Pos) /*!< GPIO_PORT B202: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B203 -----------------------------------------\r
-#define GPIO_PORT_B203_PBYTE_Pos 0 /*!< GPIO_PORT B203: PBYTE Position */\r
-#define GPIO_PORT_B203_PBYTE_Msk (0x01UL << GPIO_PORT_B203_PBYTE_Pos) /*!< GPIO_PORT B203: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B204 -----------------------------------------\r
-#define GPIO_PORT_B204_PBYTE_Pos 0 /*!< GPIO_PORT B204: PBYTE Position */\r
-#define GPIO_PORT_B204_PBYTE_Msk (0x01UL << GPIO_PORT_B204_PBYTE_Pos) /*!< GPIO_PORT B204: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B205 -----------------------------------------\r
-#define GPIO_PORT_B205_PBYTE_Pos 0 /*!< GPIO_PORT B205: PBYTE Position */\r
-#define GPIO_PORT_B205_PBYTE_Msk (0x01UL << GPIO_PORT_B205_PBYTE_Pos) /*!< GPIO_PORT B205: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B206 -----------------------------------------\r
-#define GPIO_PORT_B206_PBYTE_Pos 0 /*!< GPIO_PORT B206: PBYTE Position */\r
-#define GPIO_PORT_B206_PBYTE_Msk (0x01UL << GPIO_PORT_B206_PBYTE_Pos) /*!< GPIO_PORT B206: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B207 -----------------------------------------\r
-#define GPIO_PORT_B207_PBYTE_Pos 0 /*!< GPIO_PORT B207: PBYTE Position */\r
-#define GPIO_PORT_B207_PBYTE_Msk (0x01UL << GPIO_PORT_B207_PBYTE_Pos) /*!< GPIO_PORT B207: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B208 -----------------------------------------\r
-#define GPIO_PORT_B208_PBYTE_Pos 0 /*!< GPIO_PORT B208: PBYTE Position */\r
-#define GPIO_PORT_B208_PBYTE_Msk (0x01UL << GPIO_PORT_B208_PBYTE_Pos) /*!< GPIO_PORT B208: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B209 -----------------------------------------\r
-#define GPIO_PORT_B209_PBYTE_Pos 0 /*!< GPIO_PORT B209: PBYTE Position */\r
-#define GPIO_PORT_B209_PBYTE_Msk (0x01UL << GPIO_PORT_B209_PBYTE_Pos) /*!< GPIO_PORT B209: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B210 -----------------------------------------\r
-#define GPIO_PORT_B210_PBYTE_Pos 0 /*!< GPIO_PORT B210: PBYTE Position */\r
-#define GPIO_PORT_B210_PBYTE_Msk (0x01UL << GPIO_PORT_B210_PBYTE_Pos) /*!< GPIO_PORT B210: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B211 -----------------------------------------\r
-#define GPIO_PORT_B211_PBYTE_Pos 0 /*!< GPIO_PORT B211: PBYTE Position */\r
-#define GPIO_PORT_B211_PBYTE_Msk (0x01UL << GPIO_PORT_B211_PBYTE_Pos) /*!< GPIO_PORT B211: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B212 -----------------------------------------\r
-#define GPIO_PORT_B212_PBYTE_Pos 0 /*!< GPIO_PORT B212: PBYTE Position */\r
-#define GPIO_PORT_B212_PBYTE_Msk (0x01UL << GPIO_PORT_B212_PBYTE_Pos) /*!< GPIO_PORT B212: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B213 -----------------------------------------\r
-#define GPIO_PORT_B213_PBYTE_Pos 0 /*!< GPIO_PORT B213: PBYTE Position */\r
-#define GPIO_PORT_B213_PBYTE_Msk (0x01UL << GPIO_PORT_B213_PBYTE_Pos) /*!< GPIO_PORT B213: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B214 -----------------------------------------\r
-#define GPIO_PORT_B214_PBYTE_Pos 0 /*!< GPIO_PORT B214: PBYTE Position */\r
-#define GPIO_PORT_B214_PBYTE_Msk (0x01UL << GPIO_PORT_B214_PBYTE_Pos) /*!< GPIO_PORT B214: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B215 -----------------------------------------\r
-#define GPIO_PORT_B215_PBYTE_Pos 0 /*!< GPIO_PORT B215: PBYTE Position */\r
-#define GPIO_PORT_B215_PBYTE_Msk (0x01UL << GPIO_PORT_B215_PBYTE_Pos) /*!< GPIO_PORT B215: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B216 -----------------------------------------\r
-#define GPIO_PORT_B216_PBYTE_Pos 0 /*!< GPIO_PORT B216: PBYTE Position */\r
-#define GPIO_PORT_B216_PBYTE_Msk (0x01UL << GPIO_PORT_B216_PBYTE_Pos) /*!< GPIO_PORT B216: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B217 -----------------------------------------\r
-#define GPIO_PORT_B217_PBYTE_Pos 0 /*!< GPIO_PORT B217: PBYTE Position */\r
-#define GPIO_PORT_B217_PBYTE_Msk (0x01UL << GPIO_PORT_B217_PBYTE_Pos) /*!< GPIO_PORT B217: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B218 -----------------------------------------\r
-#define GPIO_PORT_B218_PBYTE_Pos 0 /*!< GPIO_PORT B218: PBYTE Position */\r
-#define GPIO_PORT_B218_PBYTE_Msk (0x01UL << GPIO_PORT_B218_PBYTE_Pos) /*!< GPIO_PORT B218: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B219 -----------------------------------------\r
-#define GPIO_PORT_B219_PBYTE_Pos 0 /*!< GPIO_PORT B219: PBYTE Position */\r
-#define GPIO_PORT_B219_PBYTE_Msk (0x01UL << GPIO_PORT_B219_PBYTE_Pos) /*!< GPIO_PORT B219: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B220 -----------------------------------------\r
-#define GPIO_PORT_B220_PBYTE_Pos 0 /*!< GPIO_PORT B220: PBYTE Position */\r
-#define GPIO_PORT_B220_PBYTE_Msk (0x01UL << GPIO_PORT_B220_PBYTE_Pos) /*!< GPIO_PORT B220: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B221 -----------------------------------------\r
-#define GPIO_PORT_B221_PBYTE_Pos 0 /*!< GPIO_PORT B221: PBYTE Position */\r
-#define GPIO_PORT_B221_PBYTE_Msk (0x01UL << GPIO_PORT_B221_PBYTE_Pos) /*!< GPIO_PORT B221: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B222 -----------------------------------------\r
-#define GPIO_PORT_B222_PBYTE_Pos 0 /*!< GPIO_PORT B222: PBYTE Position */\r
-#define GPIO_PORT_B222_PBYTE_Msk (0x01UL << GPIO_PORT_B222_PBYTE_Pos) /*!< GPIO_PORT B222: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B223 -----------------------------------------\r
-#define GPIO_PORT_B223_PBYTE_Pos 0 /*!< GPIO_PORT B223: PBYTE Position */\r
-#define GPIO_PORT_B223_PBYTE_Msk (0x01UL << GPIO_PORT_B223_PBYTE_Pos) /*!< GPIO_PORT B223: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B224 -----------------------------------------\r
-#define GPIO_PORT_B224_PBYTE_Pos 0 /*!< GPIO_PORT B224: PBYTE Position */\r
-#define GPIO_PORT_B224_PBYTE_Msk (0x01UL << GPIO_PORT_B224_PBYTE_Pos) /*!< GPIO_PORT B224: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B225 -----------------------------------------\r
-#define GPIO_PORT_B225_PBYTE_Pos 0 /*!< GPIO_PORT B225: PBYTE Position */\r
-#define GPIO_PORT_B225_PBYTE_Msk (0x01UL << GPIO_PORT_B225_PBYTE_Pos) /*!< GPIO_PORT B225: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B226 -----------------------------------------\r
-#define GPIO_PORT_B226_PBYTE_Pos 0 /*!< GPIO_PORT B226: PBYTE Position */\r
-#define GPIO_PORT_B226_PBYTE_Msk (0x01UL << GPIO_PORT_B226_PBYTE_Pos) /*!< GPIO_PORT B226: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B227 -----------------------------------------\r
-#define GPIO_PORT_B227_PBYTE_Pos 0 /*!< GPIO_PORT B227: PBYTE Position */\r
-#define GPIO_PORT_B227_PBYTE_Msk (0x01UL << GPIO_PORT_B227_PBYTE_Pos) /*!< GPIO_PORT B227: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B228 -----------------------------------------\r
-#define GPIO_PORT_B228_PBYTE_Pos 0 /*!< GPIO_PORT B228: PBYTE Position */\r
-#define GPIO_PORT_B228_PBYTE_Msk (0x01UL << GPIO_PORT_B228_PBYTE_Pos) /*!< GPIO_PORT B228: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B229 -----------------------------------------\r
-#define GPIO_PORT_B229_PBYTE_Pos 0 /*!< GPIO_PORT B229: PBYTE Position */\r
-#define GPIO_PORT_B229_PBYTE_Msk (0x01UL << GPIO_PORT_B229_PBYTE_Pos) /*!< GPIO_PORT B229: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B230 -----------------------------------------\r
-#define GPIO_PORT_B230_PBYTE_Pos 0 /*!< GPIO_PORT B230: PBYTE Position */\r
-#define GPIO_PORT_B230_PBYTE_Msk (0x01UL << GPIO_PORT_B230_PBYTE_Pos) /*!< GPIO_PORT B230: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B231 -----------------------------------------\r
-#define GPIO_PORT_B231_PBYTE_Pos 0 /*!< GPIO_PORT B231: PBYTE Position */\r
-#define GPIO_PORT_B231_PBYTE_Msk (0x01UL << GPIO_PORT_B231_PBYTE_Pos) /*!< GPIO_PORT B231: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B232 -----------------------------------------\r
-#define GPIO_PORT_B232_PBYTE_Pos 0 /*!< GPIO_PORT B232: PBYTE Position */\r
-#define GPIO_PORT_B232_PBYTE_Msk (0x01UL << GPIO_PORT_B232_PBYTE_Pos) /*!< GPIO_PORT B232: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B233 -----------------------------------------\r
-#define GPIO_PORT_B233_PBYTE_Pos 0 /*!< GPIO_PORT B233: PBYTE Position */\r
-#define GPIO_PORT_B233_PBYTE_Msk (0x01UL << GPIO_PORT_B233_PBYTE_Pos) /*!< GPIO_PORT B233: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B234 -----------------------------------------\r
-#define GPIO_PORT_B234_PBYTE_Pos 0 /*!< GPIO_PORT B234: PBYTE Position */\r
-#define GPIO_PORT_B234_PBYTE_Msk (0x01UL << GPIO_PORT_B234_PBYTE_Pos) /*!< GPIO_PORT B234: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B235 -----------------------------------------\r
-#define GPIO_PORT_B235_PBYTE_Pos 0 /*!< GPIO_PORT B235: PBYTE Position */\r
-#define GPIO_PORT_B235_PBYTE_Msk (0x01UL << GPIO_PORT_B235_PBYTE_Pos) /*!< GPIO_PORT B235: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B236 -----------------------------------------\r
-#define GPIO_PORT_B236_PBYTE_Pos 0 /*!< GPIO_PORT B236: PBYTE Position */\r
-#define GPIO_PORT_B236_PBYTE_Msk (0x01UL << GPIO_PORT_B236_PBYTE_Pos) /*!< GPIO_PORT B236: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B237 -----------------------------------------\r
-#define GPIO_PORT_B237_PBYTE_Pos 0 /*!< GPIO_PORT B237: PBYTE Position */\r
-#define GPIO_PORT_B237_PBYTE_Msk (0x01UL << GPIO_PORT_B237_PBYTE_Pos) /*!< GPIO_PORT B237: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B238 -----------------------------------------\r
-#define GPIO_PORT_B238_PBYTE_Pos 0 /*!< GPIO_PORT B238: PBYTE Position */\r
-#define GPIO_PORT_B238_PBYTE_Msk (0x01UL << GPIO_PORT_B238_PBYTE_Pos) /*!< GPIO_PORT B238: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B239 -----------------------------------------\r
-#define GPIO_PORT_B239_PBYTE_Pos 0 /*!< GPIO_PORT B239: PBYTE Position */\r
-#define GPIO_PORT_B239_PBYTE_Msk (0x01UL << GPIO_PORT_B239_PBYTE_Pos) /*!< GPIO_PORT B239: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B240 -----------------------------------------\r
-#define GPIO_PORT_B240_PBYTE_Pos 0 /*!< GPIO_PORT B240: PBYTE Position */\r
-#define GPIO_PORT_B240_PBYTE_Msk (0x01UL << GPIO_PORT_B240_PBYTE_Pos) /*!< GPIO_PORT B240: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B241 -----------------------------------------\r
-#define GPIO_PORT_B241_PBYTE_Pos 0 /*!< GPIO_PORT B241: PBYTE Position */\r
-#define GPIO_PORT_B241_PBYTE_Msk (0x01UL << GPIO_PORT_B241_PBYTE_Pos) /*!< GPIO_PORT B241: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B242 -----------------------------------------\r
-#define GPIO_PORT_B242_PBYTE_Pos 0 /*!< GPIO_PORT B242: PBYTE Position */\r
-#define GPIO_PORT_B242_PBYTE_Msk (0x01UL << GPIO_PORT_B242_PBYTE_Pos) /*!< GPIO_PORT B242: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B243 -----------------------------------------\r
-#define GPIO_PORT_B243_PBYTE_Pos 0 /*!< GPIO_PORT B243: PBYTE Position */\r
-#define GPIO_PORT_B243_PBYTE_Msk (0x01UL << GPIO_PORT_B243_PBYTE_Pos) /*!< GPIO_PORT B243: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B244 -----------------------------------------\r
-#define GPIO_PORT_B244_PBYTE_Pos 0 /*!< GPIO_PORT B244: PBYTE Position */\r
-#define GPIO_PORT_B244_PBYTE_Msk (0x01UL << GPIO_PORT_B244_PBYTE_Pos) /*!< GPIO_PORT B244: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B245 -----------------------------------------\r
-#define GPIO_PORT_B245_PBYTE_Pos 0 /*!< GPIO_PORT B245: PBYTE Position */\r
-#define GPIO_PORT_B245_PBYTE_Msk (0x01UL << GPIO_PORT_B245_PBYTE_Pos) /*!< GPIO_PORT B245: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B246 -----------------------------------------\r
-#define GPIO_PORT_B246_PBYTE_Pos 0 /*!< GPIO_PORT B246: PBYTE Position */\r
-#define GPIO_PORT_B246_PBYTE_Msk (0x01UL << GPIO_PORT_B246_PBYTE_Pos) /*!< GPIO_PORT B246: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B247 -----------------------------------------\r
-#define GPIO_PORT_B247_PBYTE_Pos 0 /*!< GPIO_PORT B247: PBYTE Position */\r
-#define GPIO_PORT_B247_PBYTE_Msk (0x01UL << GPIO_PORT_B247_PBYTE_Pos) /*!< GPIO_PORT B247: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B248 -----------------------------------------\r
-#define GPIO_PORT_B248_PBYTE_Pos 0 /*!< GPIO_PORT B248: PBYTE Position */\r
-#define GPIO_PORT_B248_PBYTE_Msk (0x01UL << GPIO_PORT_B248_PBYTE_Pos) /*!< GPIO_PORT B248: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B249 -----------------------------------------\r
-#define GPIO_PORT_B249_PBYTE_Pos 0 /*!< GPIO_PORT B249: PBYTE Position */\r
-#define GPIO_PORT_B249_PBYTE_Msk (0x01UL << GPIO_PORT_B249_PBYTE_Pos) /*!< GPIO_PORT B249: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B250 -----------------------------------------\r
-#define GPIO_PORT_B250_PBYTE_Pos 0 /*!< GPIO_PORT B250: PBYTE Position */\r
-#define GPIO_PORT_B250_PBYTE_Msk (0x01UL << GPIO_PORT_B250_PBYTE_Pos) /*!< GPIO_PORT B250: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B251 -----------------------------------------\r
-#define GPIO_PORT_B251_PBYTE_Pos 0 /*!< GPIO_PORT B251: PBYTE Position */\r
-#define GPIO_PORT_B251_PBYTE_Msk (0x01UL << GPIO_PORT_B251_PBYTE_Pos) /*!< GPIO_PORT B251: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B252 -----------------------------------------\r
-#define GPIO_PORT_B252_PBYTE_Pos 0 /*!< GPIO_PORT B252: PBYTE Position */\r
-#define GPIO_PORT_B252_PBYTE_Msk (0x01UL << GPIO_PORT_B252_PBYTE_Pos) /*!< GPIO_PORT B252: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B253 -----------------------------------------\r
-#define GPIO_PORT_B253_PBYTE_Pos 0 /*!< GPIO_PORT B253: PBYTE Position */\r
-#define GPIO_PORT_B253_PBYTE_Msk (0x01UL << GPIO_PORT_B253_PBYTE_Pos) /*!< GPIO_PORT B253: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B254 -----------------------------------------\r
-#define GPIO_PORT_B254_PBYTE_Pos 0 /*!< GPIO_PORT B254: PBYTE Position */\r
-#define GPIO_PORT_B254_PBYTE_Msk (0x01UL << GPIO_PORT_B254_PBYTE_Pos) /*!< GPIO_PORT B254: PBYTE Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_B255 -----------------------------------------\r
-#define GPIO_PORT_B255_PBYTE_Pos 0 /*!< GPIO_PORT B255: PBYTE Position */\r
-#define GPIO_PORT_B255_PBYTE_Msk (0x01UL << GPIO_PORT_B255_PBYTE_Pos) /*!< GPIO_PORT B255: PBYTE Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W0 ------------------------------------------\r
-#define GPIO_PORT_W0_PWORD_Pos 0 /*!< GPIO_PORT W0: PWORD Position */\r
-#define GPIO_PORT_W0_PWORD_Msk (0xffffffffUL << GPIO_PORT_W0_PWORD_Pos) /*!< GPIO_PORT W0: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W1 ------------------------------------------\r
-#define GPIO_PORT_W1_PWORD_Pos 0 /*!< GPIO_PORT W1: PWORD Position */\r
-#define GPIO_PORT_W1_PWORD_Msk (0xffffffffUL << GPIO_PORT_W1_PWORD_Pos) /*!< GPIO_PORT W1: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W2 ------------------------------------------\r
-#define GPIO_PORT_W2_PWORD_Pos 0 /*!< GPIO_PORT W2: PWORD Position */\r
-#define GPIO_PORT_W2_PWORD_Msk (0xffffffffUL << GPIO_PORT_W2_PWORD_Pos) /*!< GPIO_PORT W2: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W3 ------------------------------------------\r
-#define GPIO_PORT_W3_PWORD_Pos 0 /*!< GPIO_PORT W3: PWORD Position */\r
-#define GPIO_PORT_W3_PWORD_Msk (0xffffffffUL << GPIO_PORT_W3_PWORD_Pos) /*!< GPIO_PORT W3: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W4 ------------------------------------------\r
-#define GPIO_PORT_W4_PWORD_Pos 0 /*!< GPIO_PORT W4: PWORD Position */\r
-#define GPIO_PORT_W4_PWORD_Msk (0xffffffffUL << GPIO_PORT_W4_PWORD_Pos) /*!< GPIO_PORT W4: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W5 ------------------------------------------\r
-#define GPIO_PORT_W5_PWORD_Pos 0 /*!< GPIO_PORT W5: PWORD Position */\r
-#define GPIO_PORT_W5_PWORD_Msk (0xffffffffUL << GPIO_PORT_W5_PWORD_Pos) /*!< GPIO_PORT W5: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W6 ------------------------------------------\r
-#define GPIO_PORT_W6_PWORD_Pos 0 /*!< GPIO_PORT W6: PWORD Position */\r
-#define GPIO_PORT_W6_PWORD_Msk (0xffffffffUL << GPIO_PORT_W6_PWORD_Pos) /*!< GPIO_PORT W6: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W7 ------------------------------------------\r
-#define GPIO_PORT_W7_PWORD_Pos 0 /*!< GPIO_PORT W7: PWORD Position */\r
-#define GPIO_PORT_W7_PWORD_Msk (0xffffffffUL << GPIO_PORT_W7_PWORD_Pos) /*!< GPIO_PORT W7: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W8 ------------------------------------------\r
-#define GPIO_PORT_W8_PWORD_Pos 0 /*!< GPIO_PORT W8: PWORD Position */\r
-#define GPIO_PORT_W8_PWORD_Msk (0xffffffffUL << GPIO_PORT_W8_PWORD_Pos) /*!< GPIO_PORT W8: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W9 ------------------------------------------\r
-#define GPIO_PORT_W9_PWORD_Pos 0 /*!< GPIO_PORT W9: PWORD Position */\r
-#define GPIO_PORT_W9_PWORD_Msk (0xffffffffUL << GPIO_PORT_W9_PWORD_Pos) /*!< GPIO_PORT W9: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W10 -----------------------------------------\r
-#define GPIO_PORT_W10_PWORD_Pos 0 /*!< GPIO_PORT W10: PWORD Position */\r
-#define GPIO_PORT_W10_PWORD_Msk (0xffffffffUL << GPIO_PORT_W10_PWORD_Pos) /*!< GPIO_PORT W10: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W11 -----------------------------------------\r
-#define GPIO_PORT_W11_PWORD_Pos 0 /*!< GPIO_PORT W11: PWORD Position */\r
-#define GPIO_PORT_W11_PWORD_Msk (0xffffffffUL << GPIO_PORT_W11_PWORD_Pos) /*!< GPIO_PORT W11: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W12 -----------------------------------------\r
-#define GPIO_PORT_W12_PWORD_Pos 0 /*!< GPIO_PORT W12: PWORD Position */\r
-#define GPIO_PORT_W12_PWORD_Msk (0xffffffffUL << GPIO_PORT_W12_PWORD_Pos) /*!< GPIO_PORT W12: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W13 -----------------------------------------\r
-#define GPIO_PORT_W13_PWORD_Pos 0 /*!< GPIO_PORT W13: PWORD Position */\r
-#define GPIO_PORT_W13_PWORD_Msk (0xffffffffUL << GPIO_PORT_W13_PWORD_Pos) /*!< GPIO_PORT W13: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W14 -----------------------------------------\r
-#define GPIO_PORT_W14_PWORD_Pos 0 /*!< GPIO_PORT W14: PWORD Position */\r
-#define GPIO_PORT_W14_PWORD_Msk (0xffffffffUL << GPIO_PORT_W14_PWORD_Pos) /*!< GPIO_PORT W14: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W15 -----------------------------------------\r
-#define GPIO_PORT_W15_PWORD_Pos 0 /*!< GPIO_PORT W15: PWORD Position */\r
-#define GPIO_PORT_W15_PWORD_Msk (0xffffffffUL << GPIO_PORT_W15_PWORD_Pos) /*!< GPIO_PORT W15: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W16 -----------------------------------------\r
-#define GPIO_PORT_W16_PWORD_Pos 0 /*!< GPIO_PORT W16: PWORD Position */\r
-#define GPIO_PORT_W16_PWORD_Msk (0xffffffffUL << GPIO_PORT_W16_PWORD_Pos) /*!< GPIO_PORT W16: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W17 -----------------------------------------\r
-#define GPIO_PORT_W17_PWORD_Pos 0 /*!< GPIO_PORT W17: PWORD Position */\r
-#define GPIO_PORT_W17_PWORD_Msk (0xffffffffUL << GPIO_PORT_W17_PWORD_Pos) /*!< GPIO_PORT W17: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W18 -----------------------------------------\r
-#define GPIO_PORT_W18_PWORD_Pos 0 /*!< GPIO_PORT W18: PWORD Position */\r
-#define GPIO_PORT_W18_PWORD_Msk (0xffffffffUL << GPIO_PORT_W18_PWORD_Pos) /*!< GPIO_PORT W18: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W19 -----------------------------------------\r
-#define GPIO_PORT_W19_PWORD_Pos 0 /*!< GPIO_PORT W19: PWORD Position */\r
-#define GPIO_PORT_W19_PWORD_Msk (0xffffffffUL << GPIO_PORT_W19_PWORD_Pos) /*!< GPIO_PORT W19: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W20 -----------------------------------------\r
-#define GPIO_PORT_W20_PWORD_Pos 0 /*!< GPIO_PORT W20: PWORD Position */\r
-#define GPIO_PORT_W20_PWORD_Msk (0xffffffffUL << GPIO_PORT_W20_PWORD_Pos) /*!< GPIO_PORT W20: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W21 -----------------------------------------\r
-#define GPIO_PORT_W21_PWORD_Pos 0 /*!< GPIO_PORT W21: PWORD Position */\r
-#define GPIO_PORT_W21_PWORD_Msk (0xffffffffUL << GPIO_PORT_W21_PWORD_Pos) /*!< GPIO_PORT W21: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W22 -----------------------------------------\r
-#define GPIO_PORT_W22_PWORD_Pos 0 /*!< GPIO_PORT W22: PWORD Position */\r
-#define GPIO_PORT_W22_PWORD_Msk (0xffffffffUL << GPIO_PORT_W22_PWORD_Pos) /*!< GPIO_PORT W22: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W23 -----------------------------------------\r
-#define GPIO_PORT_W23_PWORD_Pos 0 /*!< GPIO_PORT W23: PWORD Position */\r
-#define GPIO_PORT_W23_PWORD_Msk (0xffffffffUL << GPIO_PORT_W23_PWORD_Pos) /*!< GPIO_PORT W23: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W24 -----------------------------------------\r
-#define GPIO_PORT_W24_PWORD_Pos 0 /*!< GPIO_PORT W24: PWORD Position */\r
-#define GPIO_PORT_W24_PWORD_Msk (0xffffffffUL << GPIO_PORT_W24_PWORD_Pos) /*!< GPIO_PORT W24: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W25 -----------------------------------------\r
-#define GPIO_PORT_W25_PWORD_Pos 0 /*!< GPIO_PORT W25: PWORD Position */\r
-#define GPIO_PORT_W25_PWORD_Msk (0xffffffffUL << GPIO_PORT_W25_PWORD_Pos) /*!< GPIO_PORT W25: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W26 -----------------------------------------\r
-#define GPIO_PORT_W26_PWORD_Pos 0 /*!< GPIO_PORT W26: PWORD Position */\r
-#define GPIO_PORT_W26_PWORD_Msk (0xffffffffUL << GPIO_PORT_W26_PWORD_Pos) /*!< GPIO_PORT W26: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W27 -----------------------------------------\r
-#define GPIO_PORT_W27_PWORD_Pos 0 /*!< GPIO_PORT W27: PWORD Position */\r
-#define GPIO_PORT_W27_PWORD_Msk (0xffffffffUL << GPIO_PORT_W27_PWORD_Pos) /*!< GPIO_PORT W27: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W28 -----------------------------------------\r
-#define GPIO_PORT_W28_PWORD_Pos 0 /*!< GPIO_PORT W28: PWORD Position */\r
-#define GPIO_PORT_W28_PWORD_Msk (0xffffffffUL << GPIO_PORT_W28_PWORD_Pos) /*!< GPIO_PORT W28: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W29 -----------------------------------------\r
-#define GPIO_PORT_W29_PWORD_Pos 0 /*!< GPIO_PORT W29: PWORD Position */\r
-#define GPIO_PORT_W29_PWORD_Msk (0xffffffffUL << GPIO_PORT_W29_PWORD_Pos) /*!< GPIO_PORT W29: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W30 -----------------------------------------\r
-#define GPIO_PORT_W30_PWORD_Pos 0 /*!< GPIO_PORT W30: PWORD Position */\r
-#define GPIO_PORT_W30_PWORD_Msk (0xffffffffUL << GPIO_PORT_W30_PWORD_Pos) /*!< GPIO_PORT W30: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W31 -----------------------------------------\r
-#define GPIO_PORT_W31_PWORD_Pos 0 /*!< GPIO_PORT W31: PWORD Position */\r
-#define GPIO_PORT_W31_PWORD_Msk (0xffffffffUL << GPIO_PORT_W31_PWORD_Pos) /*!< GPIO_PORT W31: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W32 -----------------------------------------\r
-#define GPIO_PORT_W32_PWORD_Pos 0 /*!< GPIO_PORT W32: PWORD Position */\r
-#define GPIO_PORT_W32_PWORD_Msk (0xffffffffUL << GPIO_PORT_W32_PWORD_Pos) /*!< GPIO_PORT W32: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W33 -----------------------------------------\r
-#define GPIO_PORT_W33_PWORD_Pos 0 /*!< GPIO_PORT W33: PWORD Position */\r
-#define GPIO_PORT_W33_PWORD_Msk (0xffffffffUL << GPIO_PORT_W33_PWORD_Pos) /*!< GPIO_PORT W33: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W34 -----------------------------------------\r
-#define GPIO_PORT_W34_PWORD_Pos 0 /*!< GPIO_PORT W34: PWORD Position */\r
-#define GPIO_PORT_W34_PWORD_Msk (0xffffffffUL << GPIO_PORT_W34_PWORD_Pos) /*!< GPIO_PORT W34: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W35 -----------------------------------------\r
-#define GPIO_PORT_W35_PWORD_Pos 0 /*!< GPIO_PORT W35: PWORD Position */\r
-#define GPIO_PORT_W35_PWORD_Msk (0xffffffffUL << GPIO_PORT_W35_PWORD_Pos) /*!< GPIO_PORT W35: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W36 -----------------------------------------\r
-#define GPIO_PORT_W36_PWORD_Pos 0 /*!< GPIO_PORT W36: PWORD Position */\r
-#define GPIO_PORT_W36_PWORD_Msk (0xffffffffUL << GPIO_PORT_W36_PWORD_Pos) /*!< GPIO_PORT W36: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W37 -----------------------------------------\r
-#define GPIO_PORT_W37_PWORD_Pos 0 /*!< GPIO_PORT W37: PWORD Position */\r
-#define GPIO_PORT_W37_PWORD_Msk (0xffffffffUL << GPIO_PORT_W37_PWORD_Pos) /*!< GPIO_PORT W37: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W38 -----------------------------------------\r
-#define GPIO_PORT_W38_PWORD_Pos 0 /*!< GPIO_PORT W38: PWORD Position */\r
-#define GPIO_PORT_W38_PWORD_Msk (0xffffffffUL << GPIO_PORT_W38_PWORD_Pos) /*!< GPIO_PORT W38: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W39 -----------------------------------------\r
-#define GPIO_PORT_W39_PWORD_Pos 0 /*!< GPIO_PORT W39: PWORD Position */\r
-#define GPIO_PORT_W39_PWORD_Msk (0xffffffffUL << GPIO_PORT_W39_PWORD_Pos) /*!< GPIO_PORT W39: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W40 -----------------------------------------\r
-#define GPIO_PORT_W40_PWORD_Pos 0 /*!< GPIO_PORT W40: PWORD Position */\r
-#define GPIO_PORT_W40_PWORD_Msk (0xffffffffUL << GPIO_PORT_W40_PWORD_Pos) /*!< GPIO_PORT W40: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W41 -----------------------------------------\r
-#define GPIO_PORT_W41_PWORD_Pos 0 /*!< GPIO_PORT W41: PWORD Position */\r
-#define GPIO_PORT_W41_PWORD_Msk (0xffffffffUL << GPIO_PORT_W41_PWORD_Pos) /*!< GPIO_PORT W41: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W42 -----------------------------------------\r
-#define GPIO_PORT_W42_PWORD_Pos 0 /*!< GPIO_PORT W42: PWORD Position */\r
-#define GPIO_PORT_W42_PWORD_Msk (0xffffffffUL << GPIO_PORT_W42_PWORD_Pos) /*!< GPIO_PORT W42: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W43 -----------------------------------------\r
-#define GPIO_PORT_W43_PWORD_Pos 0 /*!< GPIO_PORT W43: PWORD Position */\r
-#define GPIO_PORT_W43_PWORD_Msk (0xffffffffUL << GPIO_PORT_W43_PWORD_Pos) /*!< GPIO_PORT W43: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W44 -----------------------------------------\r
-#define GPIO_PORT_W44_PWORD_Pos 0 /*!< GPIO_PORT W44: PWORD Position */\r
-#define GPIO_PORT_W44_PWORD_Msk (0xffffffffUL << GPIO_PORT_W44_PWORD_Pos) /*!< GPIO_PORT W44: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W45 -----------------------------------------\r
-#define GPIO_PORT_W45_PWORD_Pos 0 /*!< GPIO_PORT W45: PWORD Position */\r
-#define GPIO_PORT_W45_PWORD_Msk (0xffffffffUL << GPIO_PORT_W45_PWORD_Pos) /*!< GPIO_PORT W45: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W46 -----------------------------------------\r
-#define GPIO_PORT_W46_PWORD_Pos 0 /*!< GPIO_PORT W46: PWORD Position */\r
-#define GPIO_PORT_W46_PWORD_Msk (0xffffffffUL << GPIO_PORT_W46_PWORD_Pos) /*!< GPIO_PORT W46: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W47 -----------------------------------------\r
-#define GPIO_PORT_W47_PWORD_Pos 0 /*!< GPIO_PORT W47: PWORD Position */\r
-#define GPIO_PORT_W47_PWORD_Msk (0xffffffffUL << GPIO_PORT_W47_PWORD_Pos) /*!< GPIO_PORT W47: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W48 -----------------------------------------\r
-#define GPIO_PORT_W48_PWORD_Pos 0 /*!< GPIO_PORT W48: PWORD Position */\r
-#define GPIO_PORT_W48_PWORD_Msk (0xffffffffUL << GPIO_PORT_W48_PWORD_Pos) /*!< GPIO_PORT W48: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W49 -----------------------------------------\r
-#define GPIO_PORT_W49_PWORD_Pos 0 /*!< GPIO_PORT W49: PWORD Position */\r
-#define GPIO_PORT_W49_PWORD_Msk (0xffffffffUL << GPIO_PORT_W49_PWORD_Pos) /*!< GPIO_PORT W49: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W50 -----------------------------------------\r
-#define GPIO_PORT_W50_PWORD_Pos 0 /*!< GPIO_PORT W50: PWORD Position */\r
-#define GPIO_PORT_W50_PWORD_Msk (0xffffffffUL << GPIO_PORT_W50_PWORD_Pos) /*!< GPIO_PORT W50: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W51 -----------------------------------------\r
-#define GPIO_PORT_W51_PWORD_Pos 0 /*!< GPIO_PORT W51: PWORD Position */\r
-#define GPIO_PORT_W51_PWORD_Msk (0xffffffffUL << GPIO_PORT_W51_PWORD_Pos) /*!< GPIO_PORT W51: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W52 -----------------------------------------\r
-#define GPIO_PORT_W52_PWORD_Pos 0 /*!< GPIO_PORT W52: PWORD Position */\r
-#define GPIO_PORT_W52_PWORD_Msk (0xffffffffUL << GPIO_PORT_W52_PWORD_Pos) /*!< GPIO_PORT W52: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W53 -----------------------------------------\r
-#define GPIO_PORT_W53_PWORD_Pos 0 /*!< GPIO_PORT W53: PWORD Position */\r
-#define GPIO_PORT_W53_PWORD_Msk (0xffffffffUL << GPIO_PORT_W53_PWORD_Pos) /*!< GPIO_PORT W53: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W54 -----------------------------------------\r
-#define GPIO_PORT_W54_PWORD_Pos 0 /*!< GPIO_PORT W54: PWORD Position */\r
-#define GPIO_PORT_W54_PWORD_Msk (0xffffffffUL << GPIO_PORT_W54_PWORD_Pos) /*!< GPIO_PORT W54: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W55 -----------------------------------------\r
-#define GPIO_PORT_W55_PWORD_Pos 0 /*!< GPIO_PORT W55: PWORD Position */\r
-#define GPIO_PORT_W55_PWORD_Msk (0xffffffffUL << GPIO_PORT_W55_PWORD_Pos) /*!< GPIO_PORT W55: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W56 -----------------------------------------\r
-#define GPIO_PORT_W56_PWORD_Pos 0 /*!< GPIO_PORT W56: PWORD Position */\r
-#define GPIO_PORT_W56_PWORD_Msk (0xffffffffUL << GPIO_PORT_W56_PWORD_Pos) /*!< GPIO_PORT W56: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W57 -----------------------------------------\r
-#define GPIO_PORT_W57_PWORD_Pos 0 /*!< GPIO_PORT W57: PWORD Position */\r
-#define GPIO_PORT_W57_PWORD_Msk (0xffffffffUL << GPIO_PORT_W57_PWORD_Pos) /*!< GPIO_PORT W57: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W58 -----------------------------------------\r
-#define GPIO_PORT_W58_PWORD_Pos 0 /*!< GPIO_PORT W58: PWORD Position */\r
-#define GPIO_PORT_W58_PWORD_Msk (0xffffffffUL << GPIO_PORT_W58_PWORD_Pos) /*!< GPIO_PORT W58: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W59 -----------------------------------------\r
-#define GPIO_PORT_W59_PWORD_Pos 0 /*!< GPIO_PORT W59: PWORD Position */\r
-#define GPIO_PORT_W59_PWORD_Msk (0xffffffffUL << GPIO_PORT_W59_PWORD_Pos) /*!< GPIO_PORT W59: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W60 -----------------------------------------\r
-#define GPIO_PORT_W60_PWORD_Pos 0 /*!< GPIO_PORT W60: PWORD Position */\r
-#define GPIO_PORT_W60_PWORD_Msk (0xffffffffUL << GPIO_PORT_W60_PWORD_Pos) /*!< GPIO_PORT W60: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W61 -----------------------------------------\r
-#define GPIO_PORT_W61_PWORD_Pos 0 /*!< GPIO_PORT W61: PWORD Position */\r
-#define GPIO_PORT_W61_PWORD_Msk (0xffffffffUL << GPIO_PORT_W61_PWORD_Pos) /*!< GPIO_PORT W61: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W62 -----------------------------------------\r
-#define GPIO_PORT_W62_PWORD_Pos 0 /*!< GPIO_PORT W62: PWORD Position */\r
-#define GPIO_PORT_W62_PWORD_Msk (0xffffffffUL << GPIO_PORT_W62_PWORD_Pos) /*!< GPIO_PORT W62: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W63 -----------------------------------------\r
-#define GPIO_PORT_W63_PWORD_Pos 0 /*!< GPIO_PORT W63: PWORD Position */\r
-#define GPIO_PORT_W63_PWORD_Msk (0xffffffffUL << GPIO_PORT_W63_PWORD_Pos) /*!< GPIO_PORT W63: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W64 -----------------------------------------\r
-#define GPIO_PORT_W64_PWORD_Pos 0 /*!< GPIO_PORT W64: PWORD Position */\r
-#define GPIO_PORT_W64_PWORD_Msk (0xffffffffUL << GPIO_PORT_W64_PWORD_Pos) /*!< GPIO_PORT W64: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W65 -----------------------------------------\r
-#define GPIO_PORT_W65_PWORD_Pos 0 /*!< GPIO_PORT W65: PWORD Position */\r
-#define GPIO_PORT_W65_PWORD_Msk (0xffffffffUL << GPIO_PORT_W65_PWORD_Pos) /*!< GPIO_PORT W65: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W66 -----------------------------------------\r
-#define GPIO_PORT_W66_PWORD_Pos 0 /*!< GPIO_PORT W66: PWORD Position */\r
-#define GPIO_PORT_W66_PWORD_Msk (0xffffffffUL << GPIO_PORT_W66_PWORD_Pos) /*!< GPIO_PORT W66: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W67 -----------------------------------------\r
-#define GPIO_PORT_W67_PWORD_Pos 0 /*!< GPIO_PORT W67: PWORD Position */\r
-#define GPIO_PORT_W67_PWORD_Msk (0xffffffffUL << GPIO_PORT_W67_PWORD_Pos) /*!< GPIO_PORT W67: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W68 -----------------------------------------\r
-#define GPIO_PORT_W68_PWORD_Pos 0 /*!< GPIO_PORT W68: PWORD Position */\r
-#define GPIO_PORT_W68_PWORD_Msk (0xffffffffUL << GPIO_PORT_W68_PWORD_Pos) /*!< GPIO_PORT W68: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W69 -----------------------------------------\r
-#define GPIO_PORT_W69_PWORD_Pos 0 /*!< GPIO_PORT W69: PWORD Position */\r
-#define GPIO_PORT_W69_PWORD_Msk (0xffffffffUL << GPIO_PORT_W69_PWORD_Pos) /*!< GPIO_PORT W69: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W70 -----------------------------------------\r
-#define GPIO_PORT_W70_PWORD_Pos 0 /*!< GPIO_PORT W70: PWORD Position */\r
-#define GPIO_PORT_W70_PWORD_Msk (0xffffffffUL << GPIO_PORT_W70_PWORD_Pos) /*!< GPIO_PORT W70: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W71 -----------------------------------------\r
-#define GPIO_PORT_W71_PWORD_Pos 0 /*!< GPIO_PORT W71: PWORD Position */\r
-#define GPIO_PORT_W71_PWORD_Msk (0xffffffffUL << GPIO_PORT_W71_PWORD_Pos) /*!< GPIO_PORT W71: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W72 -----------------------------------------\r
-#define GPIO_PORT_W72_PWORD_Pos 0 /*!< GPIO_PORT W72: PWORD Position */\r
-#define GPIO_PORT_W72_PWORD_Msk (0xffffffffUL << GPIO_PORT_W72_PWORD_Pos) /*!< GPIO_PORT W72: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W73 -----------------------------------------\r
-#define GPIO_PORT_W73_PWORD_Pos 0 /*!< GPIO_PORT W73: PWORD Position */\r
-#define GPIO_PORT_W73_PWORD_Msk (0xffffffffUL << GPIO_PORT_W73_PWORD_Pos) /*!< GPIO_PORT W73: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W74 -----------------------------------------\r
-#define GPIO_PORT_W74_PWORD_Pos 0 /*!< GPIO_PORT W74: PWORD Position */\r
-#define GPIO_PORT_W74_PWORD_Msk (0xffffffffUL << GPIO_PORT_W74_PWORD_Pos) /*!< GPIO_PORT W74: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W75 -----------------------------------------\r
-#define GPIO_PORT_W75_PWORD_Pos 0 /*!< GPIO_PORT W75: PWORD Position */\r
-#define GPIO_PORT_W75_PWORD_Msk (0xffffffffUL << GPIO_PORT_W75_PWORD_Pos) /*!< GPIO_PORT W75: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W76 -----------------------------------------\r
-#define GPIO_PORT_W76_PWORD_Pos 0 /*!< GPIO_PORT W76: PWORD Position */\r
-#define GPIO_PORT_W76_PWORD_Msk (0xffffffffUL << GPIO_PORT_W76_PWORD_Pos) /*!< GPIO_PORT W76: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W77 -----------------------------------------\r
-#define GPIO_PORT_W77_PWORD_Pos 0 /*!< GPIO_PORT W77: PWORD Position */\r
-#define GPIO_PORT_W77_PWORD_Msk (0xffffffffUL << GPIO_PORT_W77_PWORD_Pos) /*!< GPIO_PORT W77: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W78 -----------------------------------------\r
-#define GPIO_PORT_W78_PWORD_Pos 0 /*!< GPIO_PORT W78: PWORD Position */\r
-#define GPIO_PORT_W78_PWORD_Msk (0xffffffffUL << GPIO_PORT_W78_PWORD_Pos) /*!< GPIO_PORT W78: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W79 -----------------------------------------\r
-#define GPIO_PORT_W79_PWORD_Pos 0 /*!< GPIO_PORT W79: PWORD Position */\r
-#define GPIO_PORT_W79_PWORD_Msk (0xffffffffUL << GPIO_PORT_W79_PWORD_Pos) /*!< GPIO_PORT W79: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W80 -----------------------------------------\r
-#define GPIO_PORT_W80_PWORD_Pos 0 /*!< GPIO_PORT W80: PWORD Position */\r
-#define GPIO_PORT_W80_PWORD_Msk (0xffffffffUL << GPIO_PORT_W80_PWORD_Pos) /*!< GPIO_PORT W80: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W81 -----------------------------------------\r
-#define GPIO_PORT_W81_PWORD_Pos 0 /*!< GPIO_PORT W81: PWORD Position */\r
-#define GPIO_PORT_W81_PWORD_Msk (0xffffffffUL << GPIO_PORT_W81_PWORD_Pos) /*!< GPIO_PORT W81: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W82 -----------------------------------------\r
-#define GPIO_PORT_W82_PWORD_Pos 0 /*!< GPIO_PORT W82: PWORD Position */\r
-#define GPIO_PORT_W82_PWORD_Msk (0xffffffffUL << GPIO_PORT_W82_PWORD_Pos) /*!< GPIO_PORT W82: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W83 -----------------------------------------\r
-#define GPIO_PORT_W83_PWORD_Pos 0 /*!< GPIO_PORT W83: PWORD Position */\r
-#define GPIO_PORT_W83_PWORD_Msk (0xffffffffUL << GPIO_PORT_W83_PWORD_Pos) /*!< GPIO_PORT W83: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W84 -----------------------------------------\r
-#define GPIO_PORT_W84_PWORD_Pos 0 /*!< GPIO_PORT W84: PWORD Position */\r
-#define GPIO_PORT_W84_PWORD_Msk (0xffffffffUL << GPIO_PORT_W84_PWORD_Pos) /*!< GPIO_PORT W84: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W85 -----------------------------------------\r
-#define GPIO_PORT_W85_PWORD_Pos 0 /*!< GPIO_PORT W85: PWORD Position */\r
-#define GPIO_PORT_W85_PWORD_Msk (0xffffffffUL << GPIO_PORT_W85_PWORD_Pos) /*!< GPIO_PORT W85: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W86 -----------------------------------------\r
-#define GPIO_PORT_W86_PWORD_Pos 0 /*!< GPIO_PORT W86: PWORD Position */\r
-#define GPIO_PORT_W86_PWORD_Msk (0xffffffffUL << GPIO_PORT_W86_PWORD_Pos) /*!< GPIO_PORT W86: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W87 -----------------------------------------\r
-#define GPIO_PORT_W87_PWORD_Pos 0 /*!< GPIO_PORT W87: PWORD Position */\r
-#define GPIO_PORT_W87_PWORD_Msk (0xffffffffUL << GPIO_PORT_W87_PWORD_Pos) /*!< GPIO_PORT W87: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W88 -----------------------------------------\r
-#define GPIO_PORT_W88_PWORD_Pos 0 /*!< GPIO_PORT W88: PWORD Position */\r
-#define GPIO_PORT_W88_PWORD_Msk (0xffffffffUL << GPIO_PORT_W88_PWORD_Pos) /*!< GPIO_PORT W88: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W89 -----------------------------------------\r
-#define GPIO_PORT_W89_PWORD_Pos 0 /*!< GPIO_PORT W89: PWORD Position */\r
-#define GPIO_PORT_W89_PWORD_Msk (0xffffffffUL << GPIO_PORT_W89_PWORD_Pos) /*!< GPIO_PORT W89: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W90 -----------------------------------------\r
-#define GPIO_PORT_W90_PWORD_Pos 0 /*!< GPIO_PORT W90: PWORD Position */\r
-#define GPIO_PORT_W90_PWORD_Msk (0xffffffffUL << GPIO_PORT_W90_PWORD_Pos) /*!< GPIO_PORT W90: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W91 -----------------------------------------\r
-#define GPIO_PORT_W91_PWORD_Pos 0 /*!< GPIO_PORT W91: PWORD Position */\r
-#define GPIO_PORT_W91_PWORD_Msk (0xffffffffUL << GPIO_PORT_W91_PWORD_Pos) /*!< GPIO_PORT W91: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W92 -----------------------------------------\r
-#define GPIO_PORT_W92_PWORD_Pos 0 /*!< GPIO_PORT W92: PWORD Position */\r
-#define GPIO_PORT_W92_PWORD_Msk (0xffffffffUL << GPIO_PORT_W92_PWORD_Pos) /*!< GPIO_PORT W92: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W93 -----------------------------------------\r
-#define GPIO_PORT_W93_PWORD_Pos 0 /*!< GPIO_PORT W93: PWORD Position */\r
-#define GPIO_PORT_W93_PWORD_Msk (0xffffffffUL << GPIO_PORT_W93_PWORD_Pos) /*!< GPIO_PORT W93: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W94 -----------------------------------------\r
-#define GPIO_PORT_W94_PWORD_Pos 0 /*!< GPIO_PORT W94: PWORD Position */\r
-#define GPIO_PORT_W94_PWORD_Msk (0xffffffffUL << GPIO_PORT_W94_PWORD_Pos) /*!< GPIO_PORT W94: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W95 -----------------------------------------\r
-#define GPIO_PORT_W95_PWORD_Pos 0 /*!< GPIO_PORT W95: PWORD Position */\r
-#define GPIO_PORT_W95_PWORD_Msk (0xffffffffUL << GPIO_PORT_W95_PWORD_Pos) /*!< GPIO_PORT W95: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W96 -----------------------------------------\r
-#define GPIO_PORT_W96_PWORD_Pos 0 /*!< GPIO_PORT W96: PWORD Position */\r
-#define GPIO_PORT_W96_PWORD_Msk (0xffffffffUL << GPIO_PORT_W96_PWORD_Pos) /*!< GPIO_PORT W96: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W97 -----------------------------------------\r
-#define GPIO_PORT_W97_PWORD_Pos 0 /*!< GPIO_PORT W97: PWORD Position */\r
-#define GPIO_PORT_W97_PWORD_Msk (0xffffffffUL << GPIO_PORT_W97_PWORD_Pos) /*!< GPIO_PORT W97: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W98 -----------------------------------------\r
-#define GPIO_PORT_W98_PWORD_Pos 0 /*!< GPIO_PORT W98: PWORD Position */\r
-#define GPIO_PORT_W98_PWORD_Msk (0xffffffffUL << GPIO_PORT_W98_PWORD_Pos) /*!< GPIO_PORT W98: PWORD Mask */\r
-\r
-// -------------------------------------- GPIO_PORT_W99 -----------------------------------------\r
-#define GPIO_PORT_W99_PWORD_Pos 0 /*!< GPIO_PORT W99: PWORD Position */\r
-#define GPIO_PORT_W99_PWORD_Msk (0xffffffffUL << GPIO_PORT_W99_PWORD_Pos) /*!< GPIO_PORT W99: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W100 -----------------------------------------\r
-#define GPIO_PORT_W100_PWORD_Pos 0 /*!< GPIO_PORT W100: PWORD Position */\r
-#define GPIO_PORT_W100_PWORD_Msk (0xffffffffUL << GPIO_PORT_W100_PWORD_Pos) /*!< GPIO_PORT W100: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W101 -----------------------------------------\r
-#define GPIO_PORT_W101_PWORD_Pos 0 /*!< GPIO_PORT W101: PWORD Position */\r
-#define GPIO_PORT_W101_PWORD_Msk (0xffffffffUL << GPIO_PORT_W101_PWORD_Pos) /*!< GPIO_PORT W101: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W102 -----------------------------------------\r
-#define GPIO_PORT_W102_PWORD_Pos 0 /*!< GPIO_PORT W102: PWORD Position */\r
-#define GPIO_PORT_W102_PWORD_Msk (0xffffffffUL << GPIO_PORT_W102_PWORD_Pos) /*!< GPIO_PORT W102: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W103 -----------------------------------------\r
-#define GPIO_PORT_W103_PWORD_Pos 0 /*!< GPIO_PORT W103: PWORD Position */\r
-#define GPIO_PORT_W103_PWORD_Msk (0xffffffffUL << GPIO_PORT_W103_PWORD_Pos) /*!< GPIO_PORT W103: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W104 -----------------------------------------\r
-#define GPIO_PORT_W104_PWORD_Pos 0 /*!< GPIO_PORT W104: PWORD Position */\r
-#define GPIO_PORT_W104_PWORD_Msk (0xffffffffUL << GPIO_PORT_W104_PWORD_Pos) /*!< GPIO_PORT W104: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W105 -----------------------------------------\r
-#define GPIO_PORT_W105_PWORD_Pos 0 /*!< GPIO_PORT W105: PWORD Position */\r
-#define GPIO_PORT_W105_PWORD_Msk (0xffffffffUL << GPIO_PORT_W105_PWORD_Pos) /*!< GPIO_PORT W105: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W106 -----------------------------------------\r
-#define GPIO_PORT_W106_PWORD_Pos 0 /*!< GPIO_PORT W106: PWORD Position */\r
-#define GPIO_PORT_W106_PWORD_Msk (0xffffffffUL << GPIO_PORT_W106_PWORD_Pos) /*!< GPIO_PORT W106: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W107 -----------------------------------------\r
-#define GPIO_PORT_W107_PWORD_Pos 0 /*!< GPIO_PORT W107: PWORD Position */\r
-#define GPIO_PORT_W107_PWORD_Msk (0xffffffffUL << GPIO_PORT_W107_PWORD_Pos) /*!< GPIO_PORT W107: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W108 -----------------------------------------\r
-#define GPIO_PORT_W108_PWORD_Pos 0 /*!< GPIO_PORT W108: PWORD Position */\r
-#define GPIO_PORT_W108_PWORD_Msk (0xffffffffUL << GPIO_PORT_W108_PWORD_Pos) /*!< GPIO_PORT W108: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W109 -----------------------------------------\r
-#define GPIO_PORT_W109_PWORD_Pos 0 /*!< GPIO_PORT W109: PWORD Position */\r
-#define GPIO_PORT_W109_PWORD_Msk (0xffffffffUL << GPIO_PORT_W109_PWORD_Pos) /*!< GPIO_PORT W109: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W110 -----------------------------------------\r
-#define GPIO_PORT_W110_PWORD_Pos 0 /*!< GPIO_PORT W110: PWORD Position */\r
-#define GPIO_PORT_W110_PWORD_Msk (0xffffffffUL << GPIO_PORT_W110_PWORD_Pos) /*!< GPIO_PORT W110: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W111 -----------------------------------------\r
-#define GPIO_PORT_W111_PWORD_Pos 0 /*!< GPIO_PORT W111: PWORD Position */\r
-#define GPIO_PORT_W111_PWORD_Msk (0xffffffffUL << GPIO_PORT_W111_PWORD_Pos) /*!< GPIO_PORT W111: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W112 -----------------------------------------\r
-#define GPIO_PORT_W112_PWORD_Pos 0 /*!< GPIO_PORT W112: PWORD Position */\r
-#define GPIO_PORT_W112_PWORD_Msk (0xffffffffUL << GPIO_PORT_W112_PWORD_Pos) /*!< GPIO_PORT W112: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W113 -----------------------------------------\r
-#define GPIO_PORT_W113_PWORD_Pos 0 /*!< GPIO_PORT W113: PWORD Position */\r
-#define GPIO_PORT_W113_PWORD_Msk (0xffffffffUL << GPIO_PORT_W113_PWORD_Pos) /*!< GPIO_PORT W113: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W114 -----------------------------------------\r
-#define GPIO_PORT_W114_PWORD_Pos 0 /*!< GPIO_PORT W114: PWORD Position */\r
-#define GPIO_PORT_W114_PWORD_Msk (0xffffffffUL << GPIO_PORT_W114_PWORD_Pos) /*!< GPIO_PORT W114: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W115 -----------------------------------------\r
-#define GPIO_PORT_W115_PWORD_Pos 0 /*!< GPIO_PORT W115: PWORD Position */\r
-#define GPIO_PORT_W115_PWORD_Msk (0xffffffffUL << GPIO_PORT_W115_PWORD_Pos) /*!< GPIO_PORT W115: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W116 -----------------------------------------\r
-#define GPIO_PORT_W116_PWORD_Pos 0 /*!< GPIO_PORT W116: PWORD Position */\r
-#define GPIO_PORT_W116_PWORD_Msk (0xffffffffUL << GPIO_PORT_W116_PWORD_Pos) /*!< GPIO_PORT W116: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W117 -----------------------------------------\r
-#define GPIO_PORT_W117_PWORD_Pos 0 /*!< GPIO_PORT W117: PWORD Position */\r
-#define GPIO_PORT_W117_PWORD_Msk (0xffffffffUL << GPIO_PORT_W117_PWORD_Pos) /*!< GPIO_PORT W117: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W118 -----------------------------------------\r
-#define GPIO_PORT_W118_PWORD_Pos 0 /*!< GPIO_PORT W118: PWORD Position */\r
-#define GPIO_PORT_W118_PWORD_Msk (0xffffffffUL << GPIO_PORT_W118_PWORD_Pos) /*!< GPIO_PORT W118: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W119 -----------------------------------------\r
-#define GPIO_PORT_W119_PWORD_Pos 0 /*!< GPIO_PORT W119: PWORD Position */\r
-#define GPIO_PORT_W119_PWORD_Msk (0xffffffffUL << GPIO_PORT_W119_PWORD_Pos) /*!< GPIO_PORT W119: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W120 -----------------------------------------\r
-#define GPIO_PORT_W120_PWORD_Pos 0 /*!< GPIO_PORT W120: PWORD Position */\r
-#define GPIO_PORT_W120_PWORD_Msk (0xffffffffUL << GPIO_PORT_W120_PWORD_Pos) /*!< GPIO_PORT W120: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W121 -----------------------------------------\r
-#define GPIO_PORT_W121_PWORD_Pos 0 /*!< GPIO_PORT W121: PWORD Position */\r
-#define GPIO_PORT_W121_PWORD_Msk (0xffffffffUL << GPIO_PORT_W121_PWORD_Pos) /*!< GPIO_PORT W121: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W122 -----------------------------------------\r
-#define GPIO_PORT_W122_PWORD_Pos 0 /*!< GPIO_PORT W122: PWORD Position */\r
-#define GPIO_PORT_W122_PWORD_Msk (0xffffffffUL << GPIO_PORT_W122_PWORD_Pos) /*!< GPIO_PORT W122: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W123 -----------------------------------------\r
-#define GPIO_PORT_W123_PWORD_Pos 0 /*!< GPIO_PORT W123: PWORD Position */\r
-#define GPIO_PORT_W123_PWORD_Msk (0xffffffffUL << GPIO_PORT_W123_PWORD_Pos) /*!< GPIO_PORT W123: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W124 -----------------------------------------\r
-#define GPIO_PORT_W124_PWORD_Pos 0 /*!< GPIO_PORT W124: PWORD Position */\r
-#define GPIO_PORT_W124_PWORD_Msk (0xffffffffUL << GPIO_PORT_W124_PWORD_Pos) /*!< GPIO_PORT W124: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W125 -----------------------------------------\r
-#define GPIO_PORT_W125_PWORD_Pos 0 /*!< GPIO_PORT W125: PWORD Position */\r
-#define GPIO_PORT_W125_PWORD_Msk (0xffffffffUL << GPIO_PORT_W125_PWORD_Pos) /*!< GPIO_PORT W125: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W126 -----------------------------------------\r
-#define GPIO_PORT_W126_PWORD_Pos 0 /*!< GPIO_PORT W126: PWORD Position */\r
-#define GPIO_PORT_W126_PWORD_Msk (0xffffffffUL << GPIO_PORT_W126_PWORD_Pos) /*!< GPIO_PORT W126: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W127 -----------------------------------------\r
-#define GPIO_PORT_W127_PWORD_Pos 0 /*!< GPIO_PORT W127: PWORD Position */\r
-#define GPIO_PORT_W127_PWORD_Msk (0xffffffffUL << GPIO_PORT_W127_PWORD_Pos) /*!< GPIO_PORT W127: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W128 -----------------------------------------\r
-#define GPIO_PORT_W128_PWORD_Pos 0 /*!< GPIO_PORT W128: PWORD Position */\r
-#define GPIO_PORT_W128_PWORD_Msk (0xffffffffUL << GPIO_PORT_W128_PWORD_Pos) /*!< GPIO_PORT W128: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W129 -----------------------------------------\r
-#define GPIO_PORT_W129_PWORD_Pos 0 /*!< GPIO_PORT W129: PWORD Position */\r
-#define GPIO_PORT_W129_PWORD_Msk (0xffffffffUL << GPIO_PORT_W129_PWORD_Pos) /*!< GPIO_PORT W129: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W130 -----------------------------------------\r
-#define GPIO_PORT_W130_PWORD_Pos 0 /*!< GPIO_PORT W130: PWORD Position */\r
-#define GPIO_PORT_W130_PWORD_Msk (0xffffffffUL << GPIO_PORT_W130_PWORD_Pos) /*!< GPIO_PORT W130: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W131 -----------------------------------------\r
-#define GPIO_PORT_W131_PWORD_Pos 0 /*!< GPIO_PORT W131: PWORD Position */\r
-#define GPIO_PORT_W131_PWORD_Msk (0xffffffffUL << GPIO_PORT_W131_PWORD_Pos) /*!< GPIO_PORT W131: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W132 -----------------------------------------\r
-#define GPIO_PORT_W132_PWORD_Pos 0 /*!< GPIO_PORT W132: PWORD Position */\r
-#define GPIO_PORT_W132_PWORD_Msk (0xffffffffUL << GPIO_PORT_W132_PWORD_Pos) /*!< GPIO_PORT W132: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W133 -----------------------------------------\r
-#define GPIO_PORT_W133_PWORD_Pos 0 /*!< GPIO_PORT W133: PWORD Position */\r
-#define GPIO_PORT_W133_PWORD_Msk (0xffffffffUL << GPIO_PORT_W133_PWORD_Pos) /*!< GPIO_PORT W133: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W134 -----------------------------------------\r
-#define GPIO_PORT_W134_PWORD_Pos 0 /*!< GPIO_PORT W134: PWORD Position */\r
-#define GPIO_PORT_W134_PWORD_Msk (0xffffffffUL << GPIO_PORT_W134_PWORD_Pos) /*!< GPIO_PORT W134: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W135 -----------------------------------------\r
-#define GPIO_PORT_W135_PWORD_Pos 0 /*!< GPIO_PORT W135: PWORD Position */\r
-#define GPIO_PORT_W135_PWORD_Msk (0xffffffffUL << GPIO_PORT_W135_PWORD_Pos) /*!< GPIO_PORT W135: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W136 -----------------------------------------\r
-#define GPIO_PORT_W136_PWORD_Pos 0 /*!< GPIO_PORT W136: PWORD Position */\r
-#define GPIO_PORT_W136_PWORD_Msk (0xffffffffUL << GPIO_PORT_W136_PWORD_Pos) /*!< GPIO_PORT W136: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W137 -----------------------------------------\r
-#define GPIO_PORT_W137_PWORD_Pos 0 /*!< GPIO_PORT W137: PWORD Position */\r
-#define GPIO_PORT_W137_PWORD_Msk (0xffffffffUL << GPIO_PORT_W137_PWORD_Pos) /*!< GPIO_PORT W137: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W138 -----------------------------------------\r
-#define GPIO_PORT_W138_PWORD_Pos 0 /*!< GPIO_PORT W138: PWORD Position */\r
-#define GPIO_PORT_W138_PWORD_Msk (0xffffffffUL << GPIO_PORT_W138_PWORD_Pos) /*!< GPIO_PORT W138: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W139 -----------------------------------------\r
-#define GPIO_PORT_W139_PWORD_Pos 0 /*!< GPIO_PORT W139: PWORD Position */\r
-#define GPIO_PORT_W139_PWORD_Msk (0xffffffffUL << GPIO_PORT_W139_PWORD_Pos) /*!< GPIO_PORT W139: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W140 -----------------------------------------\r
-#define GPIO_PORT_W140_PWORD_Pos 0 /*!< GPIO_PORT W140: PWORD Position */\r
-#define GPIO_PORT_W140_PWORD_Msk (0xffffffffUL << GPIO_PORT_W140_PWORD_Pos) /*!< GPIO_PORT W140: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W141 -----------------------------------------\r
-#define GPIO_PORT_W141_PWORD_Pos 0 /*!< GPIO_PORT W141: PWORD Position */\r
-#define GPIO_PORT_W141_PWORD_Msk (0xffffffffUL << GPIO_PORT_W141_PWORD_Pos) /*!< GPIO_PORT W141: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W142 -----------------------------------------\r
-#define GPIO_PORT_W142_PWORD_Pos 0 /*!< GPIO_PORT W142: PWORD Position */\r
-#define GPIO_PORT_W142_PWORD_Msk (0xffffffffUL << GPIO_PORT_W142_PWORD_Pos) /*!< GPIO_PORT W142: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W143 -----------------------------------------\r
-#define GPIO_PORT_W143_PWORD_Pos 0 /*!< GPIO_PORT W143: PWORD Position */\r
-#define GPIO_PORT_W143_PWORD_Msk (0xffffffffUL << GPIO_PORT_W143_PWORD_Pos) /*!< GPIO_PORT W143: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W144 -----------------------------------------\r
-#define GPIO_PORT_W144_PWORD_Pos 0 /*!< GPIO_PORT W144: PWORD Position */\r
-#define GPIO_PORT_W144_PWORD_Msk (0xffffffffUL << GPIO_PORT_W144_PWORD_Pos) /*!< GPIO_PORT W144: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W145 -----------------------------------------\r
-#define GPIO_PORT_W145_PWORD_Pos 0 /*!< GPIO_PORT W145: PWORD Position */\r
-#define GPIO_PORT_W145_PWORD_Msk (0xffffffffUL << GPIO_PORT_W145_PWORD_Pos) /*!< GPIO_PORT W145: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W146 -----------------------------------------\r
-#define GPIO_PORT_W146_PWORD_Pos 0 /*!< GPIO_PORT W146: PWORD Position */\r
-#define GPIO_PORT_W146_PWORD_Msk (0xffffffffUL << GPIO_PORT_W146_PWORD_Pos) /*!< GPIO_PORT W146: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W147 -----------------------------------------\r
-#define GPIO_PORT_W147_PWORD_Pos 0 /*!< GPIO_PORT W147: PWORD Position */\r
-#define GPIO_PORT_W147_PWORD_Msk (0xffffffffUL << GPIO_PORT_W147_PWORD_Pos) /*!< GPIO_PORT W147: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W148 -----------------------------------------\r
-#define GPIO_PORT_W148_PWORD_Pos 0 /*!< GPIO_PORT W148: PWORD Position */\r
-#define GPIO_PORT_W148_PWORD_Msk (0xffffffffUL << GPIO_PORT_W148_PWORD_Pos) /*!< GPIO_PORT W148: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W149 -----------------------------------------\r
-#define GPIO_PORT_W149_PWORD_Pos 0 /*!< GPIO_PORT W149: PWORD Position */\r
-#define GPIO_PORT_W149_PWORD_Msk (0xffffffffUL << GPIO_PORT_W149_PWORD_Pos) /*!< GPIO_PORT W149: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W150 -----------------------------------------\r
-#define GPIO_PORT_W150_PWORD_Pos 0 /*!< GPIO_PORT W150: PWORD Position */\r
-#define GPIO_PORT_W150_PWORD_Msk (0xffffffffUL << GPIO_PORT_W150_PWORD_Pos) /*!< GPIO_PORT W150: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W151 -----------------------------------------\r
-#define GPIO_PORT_W151_PWORD_Pos 0 /*!< GPIO_PORT W151: PWORD Position */\r
-#define GPIO_PORT_W151_PWORD_Msk (0xffffffffUL << GPIO_PORT_W151_PWORD_Pos) /*!< GPIO_PORT W151: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W152 -----------------------------------------\r
-#define GPIO_PORT_W152_PWORD_Pos 0 /*!< GPIO_PORT W152: PWORD Position */\r
-#define GPIO_PORT_W152_PWORD_Msk (0xffffffffUL << GPIO_PORT_W152_PWORD_Pos) /*!< GPIO_PORT W152: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W153 -----------------------------------------\r
-#define GPIO_PORT_W153_PWORD_Pos 0 /*!< GPIO_PORT W153: PWORD Position */\r
-#define GPIO_PORT_W153_PWORD_Msk (0xffffffffUL << GPIO_PORT_W153_PWORD_Pos) /*!< GPIO_PORT W153: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W154 -----------------------------------------\r
-#define GPIO_PORT_W154_PWORD_Pos 0 /*!< GPIO_PORT W154: PWORD Position */\r
-#define GPIO_PORT_W154_PWORD_Msk (0xffffffffUL << GPIO_PORT_W154_PWORD_Pos) /*!< GPIO_PORT W154: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W155 -----------------------------------------\r
-#define GPIO_PORT_W155_PWORD_Pos 0 /*!< GPIO_PORT W155: PWORD Position */\r
-#define GPIO_PORT_W155_PWORD_Msk (0xffffffffUL << GPIO_PORT_W155_PWORD_Pos) /*!< GPIO_PORT W155: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W156 -----------------------------------------\r
-#define GPIO_PORT_W156_PWORD_Pos 0 /*!< GPIO_PORT W156: PWORD Position */\r
-#define GPIO_PORT_W156_PWORD_Msk (0xffffffffUL << GPIO_PORT_W156_PWORD_Pos) /*!< GPIO_PORT W156: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W157 -----------------------------------------\r
-#define GPIO_PORT_W157_PWORD_Pos 0 /*!< GPIO_PORT W157: PWORD Position */\r
-#define GPIO_PORT_W157_PWORD_Msk (0xffffffffUL << GPIO_PORT_W157_PWORD_Pos) /*!< GPIO_PORT W157: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W158 -----------------------------------------\r
-#define GPIO_PORT_W158_PWORD_Pos 0 /*!< GPIO_PORT W158: PWORD Position */\r
-#define GPIO_PORT_W158_PWORD_Msk (0xffffffffUL << GPIO_PORT_W158_PWORD_Pos) /*!< GPIO_PORT W158: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W159 -----------------------------------------\r
-#define GPIO_PORT_W159_PWORD_Pos 0 /*!< GPIO_PORT W159: PWORD Position */\r
-#define GPIO_PORT_W159_PWORD_Msk (0xffffffffUL << GPIO_PORT_W159_PWORD_Pos) /*!< GPIO_PORT W159: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W160 -----------------------------------------\r
-#define GPIO_PORT_W160_PWORD_Pos 0 /*!< GPIO_PORT W160: PWORD Position */\r
-#define GPIO_PORT_W160_PWORD_Msk (0xffffffffUL << GPIO_PORT_W160_PWORD_Pos) /*!< GPIO_PORT W160: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W161 -----------------------------------------\r
-#define GPIO_PORT_W161_PWORD_Pos 0 /*!< GPIO_PORT W161: PWORD Position */\r
-#define GPIO_PORT_W161_PWORD_Msk (0xffffffffUL << GPIO_PORT_W161_PWORD_Pos) /*!< GPIO_PORT W161: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W162 -----------------------------------------\r
-#define GPIO_PORT_W162_PWORD_Pos 0 /*!< GPIO_PORT W162: PWORD Position */\r
-#define GPIO_PORT_W162_PWORD_Msk (0xffffffffUL << GPIO_PORT_W162_PWORD_Pos) /*!< GPIO_PORT W162: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W163 -----------------------------------------\r
-#define GPIO_PORT_W163_PWORD_Pos 0 /*!< GPIO_PORT W163: PWORD Position */\r
-#define GPIO_PORT_W163_PWORD_Msk (0xffffffffUL << GPIO_PORT_W163_PWORD_Pos) /*!< GPIO_PORT W163: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W164 -----------------------------------------\r
-#define GPIO_PORT_W164_PWORD_Pos 0 /*!< GPIO_PORT W164: PWORD Position */\r
-#define GPIO_PORT_W164_PWORD_Msk (0xffffffffUL << GPIO_PORT_W164_PWORD_Pos) /*!< GPIO_PORT W164: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W165 -----------------------------------------\r
-#define GPIO_PORT_W165_PWORD_Pos 0 /*!< GPIO_PORT W165: PWORD Position */\r
-#define GPIO_PORT_W165_PWORD_Msk (0xffffffffUL << GPIO_PORT_W165_PWORD_Pos) /*!< GPIO_PORT W165: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W166 -----------------------------------------\r
-#define GPIO_PORT_W166_PWORD_Pos 0 /*!< GPIO_PORT W166: PWORD Position */\r
-#define GPIO_PORT_W166_PWORD_Msk (0xffffffffUL << GPIO_PORT_W166_PWORD_Pos) /*!< GPIO_PORT W166: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W167 -----------------------------------------\r
-#define GPIO_PORT_W167_PWORD_Pos 0 /*!< GPIO_PORT W167: PWORD Position */\r
-#define GPIO_PORT_W167_PWORD_Msk (0xffffffffUL << GPIO_PORT_W167_PWORD_Pos) /*!< GPIO_PORT W167: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W168 -----------------------------------------\r
-#define GPIO_PORT_W168_PWORD_Pos 0 /*!< GPIO_PORT W168: PWORD Position */\r
-#define GPIO_PORT_W168_PWORD_Msk (0xffffffffUL << GPIO_PORT_W168_PWORD_Pos) /*!< GPIO_PORT W168: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W169 -----------------------------------------\r
-#define GPIO_PORT_W169_PWORD_Pos 0 /*!< GPIO_PORT W169: PWORD Position */\r
-#define GPIO_PORT_W169_PWORD_Msk (0xffffffffUL << GPIO_PORT_W169_PWORD_Pos) /*!< GPIO_PORT W169: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W170 -----------------------------------------\r
-#define GPIO_PORT_W170_PWORD_Pos 0 /*!< GPIO_PORT W170: PWORD Position */\r
-#define GPIO_PORT_W170_PWORD_Msk (0xffffffffUL << GPIO_PORT_W170_PWORD_Pos) /*!< GPIO_PORT W170: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W171 -----------------------------------------\r
-#define GPIO_PORT_W171_PWORD_Pos 0 /*!< GPIO_PORT W171: PWORD Position */\r
-#define GPIO_PORT_W171_PWORD_Msk (0xffffffffUL << GPIO_PORT_W171_PWORD_Pos) /*!< GPIO_PORT W171: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W172 -----------------------------------------\r
-#define GPIO_PORT_W172_PWORD_Pos 0 /*!< GPIO_PORT W172: PWORD Position */\r
-#define GPIO_PORT_W172_PWORD_Msk (0xffffffffUL << GPIO_PORT_W172_PWORD_Pos) /*!< GPIO_PORT W172: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W173 -----------------------------------------\r
-#define GPIO_PORT_W173_PWORD_Pos 0 /*!< GPIO_PORT W173: PWORD Position */\r
-#define GPIO_PORT_W173_PWORD_Msk (0xffffffffUL << GPIO_PORT_W173_PWORD_Pos) /*!< GPIO_PORT W173: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W174 -----------------------------------------\r
-#define GPIO_PORT_W174_PWORD_Pos 0 /*!< GPIO_PORT W174: PWORD Position */\r
-#define GPIO_PORT_W174_PWORD_Msk (0xffffffffUL << GPIO_PORT_W174_PWORD_Pos) /*!< GPIO_PORT W174: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W175 -----------------------------------------\r
-#define GPIO_PORT_W175_PWORD_Pos 0 /*!< GPIO_PORT W175: PWORD Position */\r
-#define GPIO_PORT_W175_PWORD_Msk (0xffffffffUL << GPIO_PORT_W175_PWORD_Pos) /*!< GPIO_PORT W175: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W176 -----------------------------------------\r
-#define GPIO_PORT_W176_PWORD_Pos 0 /*!< GPIO_PORT W176: PWORD Position */\r
-#define GPIO_PORT_W176_PWORD_Msk (0xffffffffUL << GPIO_PORT_W176_PWORD_Pos) /*!< GPIO_PORT W176: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W177 -----------------------------------------\r
-#define GPIO_PORT_W177_PWORD_Pos 0 /*!< GPIO_PORT W177: PWORD Position */\r
-#define GPIO_PORT_W177_PWORD_Msk (0xffffffffUL << GPIO_PORT_W177_PWORD_Pos) /*!< GPIO_PORT W177: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W178 -----------------------------------------\r
-#define GPIO_PORT_W178_PWORD_Pos 0 /*!< GPIO_PORT W178: PWORD Position */\r
-#define GPIO_PORT_W178_PWORD_Msk (0xffffffffUL << GPIO_PORT_W178_PWORD_Pos) /*!< GPIO_PORT W178: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W179 -----------------------------------------\r
-#define GPIO_PORT_W179_PWORD_Pos 0 /*!< GPIO_PORT W179: PWORD Position */\r
-#define GPIO_PORT_W179_PWORD_Msk (0xffffffffUL << GPIO_PORT_W179_PWORD_Pos) /*!< GPIO_PORT W179: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W180 -----------------------------------------\r
-#define GPIO_PORT_W180_PWORD_Pos 0 /*!< GPIO_PORT W180: PWORD Position */\r
-#define GPIO_PORT_W180_PWORD_Msk (0xffffffffUL << GPIO_PORT_W180_PWORD_Pos) /*!< GPIO_PORT W180: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W181 -----------------------------------------\r
-#define GPIO_PORT_W181_PWORD_Pos 0 /*!< GPIO_PORT W181: PWORD Position */\r
-#define GPIO_PORT_W181_PWORD_Msk (0xffffffffUL << GPIO_PORT_W181_PWORD_Pos) /*!< GPIO_PORT W181: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W182 -----------------------------------------\r
-#define GPIO_PORT_W182_PWORD_Pos 0 /*!< GPIO_PORT W182: PWORD Position */\r
-#define GPIO_PORT_W182_PWORD_Msk (0xffffffffUL << GPIO_PORT_W182_PWORD_Pos) /*!< GPIO_PORT W182: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W183 -----------------------------------------\r
-#define GPIO_PORT_W183_PWORD_Pos 0 /*!< GPIO_PORT W183: PWORD Position */\r
-#define GPIO_PORT_W183_PWORD_Msk (0xffffffffUL << GPIO_PORT_W183_PWORD_Pos) /*!< GPIO_PORT W183: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W184 -----------------------------------------\r
-#define GPIO_PORT_W184_PWORD_Pos 0 /*!< GPIO_PORT W184: PWORD Position */\r
-#define GPIO_PORT_W184_PWORD_Msk (0xffffffffUL << GPIO_PORT_W184_PWORD_Pos) /*!< GPIO_PORT W184: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W185 -----------------------------------------\r
-#define GPIO_PORT_W185_PWORD_Pos 0 /*!< GPIO_PORT W185: PWORD Position */\r
-#define GPIO_PORT_W185_PWORD_Msk (0xffffffffUL << GPIO_PORT_W185_PWORD_Pos) /*!< GPIO_PORT W185: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W186 -----------------------------------------\r
-#define GPIO_PORT_W186_PWORD_Pos 0 /*!< GPIO_PORT W186: PWORD Position */\r
-#define GPIO_PORT_W186_PWORD_Msk (0xffffffffUL << GPIO_PORT_W186_PWORD_Pos) /*!< GPIO_PORT W186: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W187 -----------------------------------------\r
-#define GPIO_PORT_W187_PWORD_Pos 0 /*!< GPIO_PORT W187: PWORD Position */\r
-#define GPIO_PORT_W187_PWORD_Msk (0xffffffffUL << GPIO_PORT_W187_PWORD_Pos) /*!< GPIO_PORT W187: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W188 -----------------------------------------\r
-#define GPIO_PORT_W188_PWORD_Pos 0 /*!< GPIO_PORT W188: PWORD Position */\r
-#define GPIO_PORT_W188_PWORD_Msk (0xffffffffUL << GPIO_PORT_W188_PWORD_Pos) /*!< GPIO_PORT W188: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W189 -----------------------------------------\r
-#define GPIO_PORT_W189_PWORD_Pos 0 /*!< GPIO_PORT W189: PWORD Position */\r
-#define GPIO_PORT_W189_PWORD_Msk (0xffffffffUL << GPIO_PORT_W189_PWORD_Pos) /*!< GPIO_PORT W189: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W190 -----------------------------------------\r
-#define GPIO_PORT_W190_PWORD_Pos 0 /*!< GPIO_PORT W190: PWORD Position */\r
-#define GPIO_PORT_W190_PWORD_Msk (0xffffffffUL << GPIO_PORT_W190_PWORD_Pos) /*!< GPIO_PORT W190: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W191 -----------------------------------------\r
-#define GPIO_PORT_W191_PWORD_Pos 0 /*!< GPIO_PORT W191: PWORD Position */\r
-#define GPIO_PORT_W191_PWORD_Msk (0xffffffffUL << GPIO_PORT_W191_PWORD_Pos) /*!< GPIO_PORT W191: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W192 -----------------------------------------\r
-#define GPIO_PORT_W192_PWORD_Pos 0 /*!< GPIO_PORT W192: PWORD Position */\r
-#define GPIO_PORT_W192_PWORD_Msk (0xffffffffUL << GPIO_PORT_W192_PWORD_Pos) /*!< GPIO_PORT W192: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W193 -----------------------------------------\r
-#define GPIO_PORT_W193_PWORD_Pos 0 /*!< GPIO_PORT W193: PWORD Position */\r
-#define GPIO_PORT_W193_PWORD_Msk (0xffffffffUL << GPIO_PORT_W193_PWORD_Pos) /*!< GPIO_PORT W193: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W194 -----------------------------------------\r
-#define GPIO_PORT_W194_PWORD_Pos 0 /*!< GPIO_PORT W194: PWORD Position */\r
-#define GPIO_PORT_W194_PWORD_Msk (0xffffffffUL << GPIO_PORT_W194_PWORD_Pos) /*!< GPIO_PORT W194: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W195 -----------------------------------------\r
-#define GPIO_PORT_W195_PWORD_Pos 0 /*!< GPIO_PORT W195: PWORD Position */\r
-#define GPIO_PORT_W195_PWORD_Msk (0xffffffffUL << GPIO_PORT_W195_PWORD_Pos) /*!< GPIO_PORT W195: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W196 -----------------------------------------\r
-#define GPIO_PORT_W196_PWORD_Pos 0 /*!< GPIO_PORT W196: PWORD Position */\r
-#define GPIO_PORT_W196_PWORD_Msk (0xffffffffUL << GPIO_PORT_W196_PWORD_Pos) /*!< GPIO_PORT W196: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W197 -----------------------------------------\r
-#define GPIO_PORT_W197_PWORD_Pos 0 /*!< GPIO_PORT W197: PWORD Position */\r
-#define GPIO_PORT_W197_PWORD_Msk (0xffffffffUL << GPIO_PORT_W197_PWORD_Pos) /*!< GPIO_PORT W197: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W198 -----------------------------------------\r
-#define GPIO_PORT_W198_PWORD_Pos 0 /*!< GPIO_PORT W198: PWORD Position */\r
-#define GPIO_PORT_W198_PWORD_Msk (0xffffffffUL << GPIO_PORT_W198_PWORD_Pos) /*!< GPIO_PORT W198: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W199 -----------------------------------------\r
-#define GPIO_PORT_W199_PWORD_Pos 0 /*!< GPIO_PORT W199: PWORD Position */\r
-#define GPIO_PORT_W199_PWORD_Msk (0xffffffffUL << GPIO_PORT_W199_PWORD_Pos) /*!< GPIO_PORT W199: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W200 -----------------------------------------\r
-#define GPIO_PORT_W200_PWORD_Pos 0 /*!< GPIO_PORT W200: PWORD Position */\r
-#define GPIO_PORT_W200_PWORD_Msk (0xffffffffUL << GPIO_PORT_W200_PWORD_Pos) /*!< GPIO_PORT W200: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W201 -----------------------------------------\r
-#define GPIO_PORT_W201_PWORD_Pos 0 /*!< GPIO_PORT W201: PWORD Position */\r
-#define GPIO_PORT_W201_PWORD_Msk (0xffffffffUL << GPIO_PORT_W201_PWORD_Pos) /*!< GPIO_PORT W201: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W202 -----------------------------------------\r
-#define GPIO_PORT_W202_PWORD_Pos 0 /*!< GPIO_PORT W202: PWORD Position */\r
-#define GPIO_PORT_W202_PWORD_Msk (0xffffffffUL << GPIO_PORT_W202_PWORD_Pos) /*!< GPIO_PORT W202: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W203 -----------------------------------------\r
-#define GPIO_PORT_W203_PWORD_Pos 0 /*!< GPIO_PORT W203: PWORD Position */\r
-#define GPIO_PORT_W203_PWORD_Msk (0xffffffffUL << GPIO_PORT_W203_PWORD_Pos) /*!< GPIO_PORT W203: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W204 -----------------------------------------\r
-#define GPIO_PORT_W204_PWORD_Pos 0 /*!< GPIO_PORT W204: PWORD Position */\r
-#define GPIO_PORT_W204_PWORD_Msk (0xffffffffUL << GPIO_PORT_W204_PWORD_Pos) /*!< GPIO_PORT W204: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W205 -----------------------------------------\r
-#define GPIO_PORT_W205_PWORD_Pos 0 /*!< GPIO_PORT W205: PWORD Position */\r
-#define GPIO_PORT_W205_PWORD_Msk (0xffffffffUL << GPIO_PORT_W205_PWORD_Pos) /*!< GPIO_PORT W205: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W206 -----------------------------------------\r
-#define GPIO_PORT_W206_PWORD_Pos 0 /*!< GPIO_PORT W206: PWORD Position */\r
-#define GPIO_PORT_W206_PWORD_Msk (0xffffffffUL << GPIO_PORT_W206_PWORD_Pos) /*!< GPIO_PORT W206: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W207 -----------------------------------------\r
-#define GPIO_PORT_W207_PWORD_Pos 0 /*!< GPIO_PORT W207: PWORD Position */\r
-#define GPIO_PORT_W207_PWORD_Msk (0xffffffffUL << GPIO_PORT_W207_PWORD_Pos) /*!< GPIO_PORT W207: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W208 -----------------------------------------\r
-#define GPIO_PORT_W208_PWORD_Pos 0 /*!< GPIO_PORT W208: PWORD Position */\r
-#define GPIO_PORT_W208_PWORD_Msk (0xffffffffUL << GPIO_PORT_W208_PWORD_Pos) /*!< GPIO_PORT W208: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W209 -----------------------------------------\r
-#define GPIO_PORT_W209_PWORD_Pos 0 /*!< GPIO_PORT W209: PWORD Position */\r
-#define GPIO_PORT_W209_PWORD_Msk (0xffffffffUL << GPIO_PORT_W209_PWORD_Pos) /*!< GPIO_PORT W209: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W210 -----------------------------------------\r
-#define GPIO_PORT_W210_PWORD_Pos 0 /*!< GPIO_PORT W210: PWORD Position */\r
-#define GPIO_PORT_W210_PWORD_Msk (0xffffffffUL << GPIO_PORT_W210_PWORD_Pos) /*!< GPIO_PORT W210: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W211 -----------------------------------------\r
-#define GPIO_PORT_W211_PWORD_Pos 0 /*!< GPIO_PORT W211: PWORD Position */\r
-#define GPIO_PORT_W211_PWORD_Msk (0xffffffffUL << GPIO_PORT_W211_PWORD_Pos) /*!< GPIO_PORT W211: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W212 -----------------------------------------\r
-#define GPIO_PORT_W212_PWORD_Pos 0 /*!< GPIO_PORT W212: PWORD Position */\r
-#define GPIO_PORT_W212_PWORD_Msk (0xffffffffUL << GPIO_PORT_W212_PWORD_Pos) /*!< GPIO_PORT W212: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W213 -----------------------------------------\r
-#define GPIO_PORT_W213_PWORD_Pos 0 /*!< GPIO_PORT W213: PWORD Position */\r
-#define GPIO_PORT_W213_PWORD_Msk (0xffffffffUL << GPIO_PORT_W213_PWORD_Pos) /*!< GPIO_PORT W213: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W214 -----------------------------------------\r
-#define GPIO_PORT_W214_PWORD_Pos 0 /*!< GPIO_PORT W214: PWORD Position */\r
-#define GPIO_PORT_W214_PWORD_Msk (0xffffffffUL << GPIO_PORT_W214_PWORD_Pos) /*!< GPIO_PORT W214: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W215 -----------------------------------------\r
-#define GPIO_PORT_W215_PWORD_Pos 0 /*!< GPIO_PORT W215: PWORD Position */\r
-#define GPIO_PORT_W215_PWORD_Msk (0xffffffffUL << GPIO_PORT_W215_PWORD_Pos) /*!< GPIO_PORT W215: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W216 -----------------------------------------\r
-#define GPIO_PORT_W216_PWORD_Pos 0 /*!< GPIO_PORT W216: PWORD Position */\r
-#define GPIO_PORT_W216_PWORD_Msk (0xffffffffUL << GPIO_PORT_W216_PWORD_Pos) /*!< GPIO_PORT W216: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W217 -----------------------------------------\r
-#define GPIO_PORT_W217_PWORD_Pos 0 /*!< GPIO_PORT W217: PWORD Position */\r
-#define GPIO_PORT_W217_PWORD_Msk (0xffffffffUL << GPIO_PORT_W217_PWORD_Pos) /*!< GPIO_PORT W217: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W218 -----------------------------------------\r
-#define GPIO_PORT_W218_PWORD_Pos 0 /*!< GPIO_PORT W218: PWORD Position */\r
-#define GPIO_PORT_W218_PWORD_Msk (0xffffffffUL << GPIO_PORT_W218_PWORD_Pos) /*!< GPIO_PORT W218: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W219 -----------------------------------------\r
-#define GPIO_PORT_W219_PWORD_Pos 0 /*!< GPIO_PORT W219: PWORD Position */\r
-#define GPIO_PORT_W219_PWORD_Msk (0xffffffffUL << GPIO_PORT_W219_PWORD_Pos) /*!< GPIO_PORT W219: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W220 -----------------------------------------\r
-#define GPIO_PORT_W220_PWORD_Pos 0 /*!< GPIO_PORT W220: PWORD Position */\r
-#define GPIO_PORT_W220_PWORD_Msk (0xffffffffUL << GPIO_PORT_W220_PWORD_Pos) /*!< GPIO_PORT W220: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W221 -----------------------------------------\r
-#define GPIO_PORT_W221_PWORD_Pos 0 /*!< GPIO_PORT W221: PWORD Position */\r
-#define GPIO_PORT_W221_PWORD_Msk (0xffffffffUL << GPIO_PORT_W221_PWORD_Pos) /*!< GPIO_PORT W221: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W222 -----------------------------------------\r
-#define GPIO_PORT_W222_PWORD_Pos 0 /*!< GPIO_PORT W222: PWORD Position */\r
-#define GPIO_PORT_W222_PWORD_Msk (0xffffffffUL << GPIO_PORT_W222_PWORD_Pos) /*!< GPIO_PORT W222: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W223 -----------------------------------------\r
-#define GPIO_PORT_W223_PWORD_Pos 0 /*!< GPIO_PORT W223: PWORD Position */\r
-#define GPIO_PORT_W223_PWORD_Msk (0xffffffffUL << GPIO_PORT_W223_PWORD_Pos) /*!< GPIO_PORT W223: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W224 -----------------------------------------\r
-#define GPIO_PORT_W224_PWORD_Pos 0 /*!< GPIO_PORT W224: PWORD Position */\r
-#define GPIO_PORT_W224_PWORD_Msk (0xffffffffUL << GPIO_PORT_W224_PWORD_Pos) /*!< GPIO_PORT W224: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W225 -----------------------------------------\r
-#define GPIO_PORT_W225_PWORD_Pos 0 /*!< GPIO_PORT W225: PWORD Position */\r
-#define GPIO_PORT_W225_PWORD_Msk (0xffffffffUL << GPIO_PORT_W225_PWORD_Pos) /*!< GPIO_PORT W225: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W226 -----------------------------------------\r
-#define GPIO_PORT_W226_PWORD_Pos 0 /*!< GPIO_PORT W226: PWORD Position */\r
-#define GPIO_PORT_W226_PWORD_Msk (0xffffffffUL << GPIO_PORT_W226_PWORD_Pos) /*!< GPIO_PORT W226: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W227 -----------------------------------------\r
-#define GPIO_PORT_W227_PWORD_Pos 0 /*!< GPIO_PORT W227: PWORD Position */\r
-#define GPIO_PORT_W227_PWORD_Msk (0xffffffffUL << GPIO_PORT_W227_PWORD_Pos) /*!< GPIO_PORT W227: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W228 -----------------------------------------\r
-#define GPIO_PORT_W228_PWORD_Pos 0 /*!< GPIO_PORT W228: PWORD Position */\r
-#define GPIO_PORT_W228_PWORD_Msk (0xffffffffUL << GPIO_PORT_W228_PWORD_Pos) /*!< GPIO_PORT W228: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W229 -----------------------------------------\r
-#define GPIO_PORT_W229_PWORD_Pos 0 /*!< GPIO_PORT W229: PWORD Position */\r
-#define GPIO_PORT_W229_PWORD_Msk (0xffffffffUL << GPIO_PORT_W229_PWORD_Pos) /*!< GPIO_PORT W229: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W230 -----------------------------------------\r
-#define GPIO_PORT_W230_PWORD_Pos 0 /*!< GPIO_PORT W230: PWORD Position */\r
-#define GPIO_PORT_W230_PWORD_Msk (0xffffffffUL << GPIO_PORT_W230_PWORD_Pos) /*!< GPIO_PORT W230: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W231 -----------------------------------------\r
-#define GPIO_PORT_W231_PWORD_Pos 0 /*!< GPIO_PORT W231: PWORD Position */\r
-#define GPIO_PORT_W231_PWORD_Msk (0xffffffffUL << GPIO_PORT_W231_PWORD_Pos) /*!< GPIO_PORT W231: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W232 -----------------------------------------\r
-#define GPIO_PORT_W232_PWORD_Pos 0 /*!< GPIO_PORT W232: PWORD Position */\r
-#define GPIO_PORT_W232_PWORD_Msk (0xffffffffUL << GPIO_PORT_W232_PWORD_Pos) /*!< GPIO_PORT W232: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W233 -----------------------------------------\r
-#define GPIO_PORT_W233_PWORD_Pos 0 /*!< GPIO_PORT W233: PWORD Position */\r
-#define GPIO_PORT_W233_PWORD_Msk (0xffffffffUL << GPIO_PORT_W233_PWORD_Pos) /*!< GPIO_PORT W233: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W234 -----------------------------------------\r
-#define GPIO_PORT_W234_PWORD_Pos 0 /*!< GPIO_PORT W234: PWORD Position */\r
-#define GPIO_PORT_W234_PWORD_Msk (0xffffffffUL << GPIO_PORT_W234_PWORD_Pos) /*!< GPIO_PORT W234: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W235 -----------------------------------------\r
-#define GPIO_PORT_W235_PWORD_Pos 0 /*!< GPIO_PORT W235: PWORD Position */\r
-#define GPIO_PORT_W235_PWORD_Msk (0xffffffffUL << GPIO_PORT_W235_PWORD_Pos) /*!< GPIO_PORT W235: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W236 -----------------------------------------\r
-#define GPIO_PORT_W236_PWORD_Pos 0 /*!< GPIO_PORT W236: PWORD Position */\r
-#define GPIO_PORT_W236_PWORD_Msk (0xffffffffUL << GPIO_PORT_W236_PWORD_Pos) /*!< GPIO_PORT W236: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W237 -----------------------------------------\r
-#define GPIO_PORT_W237_PWORD_Pos 0 /*!< GPIO_PORT W237: PWORD Position */\r
-#define GPIO_PORT_W237_PWORD_Msk (0xffffffffUL << GPIO_PORT_W237_PWORD_Pos) /*!< GPIO_PORT W237: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W238 -----------------------------------------\r
-#define GPIO_PORT_W238_PWORD_Pos 0 /*!< GPIO_PORT W238: PWORD Position */\r
-#define GPIO_PORT_W238_PWORD_Msk (0xffffffffUL << GPIO_PORT_W238_PWORD_Pos) /*!< GPIO_PORT W238: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W239 -----------------------------------------\r
-#define GPIO_PORT_W239_PWORD_Pos 0 /*!< GPIO_PORT W239: PWORD Position */\r
-#define GPIO_PORT_W239_PWORD_Msk (0xffffffffUL << GPIO_PORT_W239_PWORD_Pos) /*!< GPIO_PORT W239: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W240 -----------------------------------------\r
-#define GPIO_PORT_W240_PWORD_Pos 0 /*!< GPIO_PORT W240: PWORD Position */\r
-#define GPIO_PORT_W240_PWORD_Msk (0xffffffffUL << GPIO_PORT_W240_PWORD_Pos) /*!< GPIO_PORT W240: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W241 -----------------------------------------\r
-#define GPIO_PORT_W241_PWORD_Pos 0 /*!< GPIO_PORT W241: PWORD Position */\r
-#define GPIO_PORT_W241_PWORD_Msk (0xffffffffUL << GPIO_PORT_W241_PWORD_Pos) /*!< GPIO_PORT W241: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W242 -----------------------------------------\r
-#define GPIO_PORT_W242_PWORD_Pos 0 /*!< GPIO_PORT W242: PWORD Position */\r
-#define GPIO_PORT_W242_PWORD_Msk (0xffffffffUL << GPIO_PORT_W242_PWORD_Pos) /*!< GPIO_PORT W242: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W243 -----------------------------------------\r
-#define GPIO_PORT_W243_PWORD_Pos 0 /*!< GPIO_PORT W243: PWORD Position */\r
-#define GPIO_PORT_W243_PWORD_Msk (0xffffffffUL << GPIO_PORT_W243_PWORD_Pos) /*!< GPIO_PORT W243: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W244 -----------------------------------------\r
-#define GPIO_PORT_W244_PWORD_Pos 0 /*!< GPIO_PORT W244: PWORD Position */\r
-#define GPIO_PORT_W244_PWORD_Msk (0xffffffffUL << GPIO_PORT_W244_PWORD_Pos) /*!< GPIO_PORT W244: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W245 -----------------------------------------\r
-#define GPIO_PORT_W245_PWORD_Pos 0 /*!< GPIO_PORT W245: PWORD Position */\r
-#define GPIO_PORT_W245_PWORD_Msk (0xffffffffUL << GPIO_PORT_W245_PWORD_Pos) /*!< GPIO_PORT W245: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W246 -----------------------------------------\r
-#define GPIO_PORT_W246_PWORD_Pos 0 /*!< GPIO_PORT W246: PWORD Position */\r
-#define GPIO_PORT_W246_PWORD_Msk (0xffffffffUL << GPIO_PORT_W246_PWORD_Pos) /*!< GPIO_PORT W246: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W247 -----------------------------------------\r
-#define GPIO_PORT_W247_PWORD_Pos 0 /*!< GPIO_PORT W247: PWORD Position */\r
-#define GPIO_PORT_W247_PWORD_Msk (0xffffffffUL << GPIO_PORT_W247_PWORD_Pos) /*!< GPIO_PORT W247: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W248 -----------------------------------------\r
-#define GPIO_PORT_W248_PWORD_Pos 0 /*!< GPIO_PORT W248: PWORD Position */\r
-#define GPIO_PORT_W248_PWORD_Msk (0xffffffffUL << GPIO_PORT_W248_PWORD_Pos) /*!< GPIO_PORT W248: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W249 -----------------------------------------\r
-#define GPIO_PORT_W249_PWORD_Pos 0 /*!< GPIO_PORT W249: PWORD Position */\r
-#define GPIO_PORT_W249_PWORD_Msk (0xffffffffUL << GPIO_PORT_W249_PWORD_Pos) /*!< GPIO_PORT W249: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W250 -----------------------------------------\r
-#define GPIO_PORT_W250_PWORD_Pos 0 /*!< GPIO_PORT W250: PWORD Position */\r
-#define GPIO_PORT_W250_PWORD_Msk (0xffffffffUL << GPIO_PORT_W250_PWORD_Pos) /*!< GPIO_PORT W250: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W251 -----------------------------------------\r
-#define GPIO_PORT_W251_PWORD_Pos 0 /*!< GPIO_PORT W251: PWORD Position */\r
-#define GPIO_PORT_W251_PWORD_Msk (0xffffffffUL << GPIO_PORT_W251_PWORD_Pos) /*!< GPIO_PORT W251: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W252 -----------------------------------------\r
-#define GPIO_PORT_W252_PWORD_Pos 0 /*!< GPIO_PORT W252: PWORD Position */\r
-#define GPIO_PORT_W252_PWORD_Msk (0xffffffffUL << GPIO_PORT_W252_PWORD_Pos) /*!< GPIO_PORT W252: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W253 -----------------------------------------\r
-#define GPIO_PORT_W253_PWORD_Pos 0 /*!< GPIO_PORT W253: PWORD Position */\r
-#define GPIO_PORT_W253_PWORD_Msk (0xffffffffUL << GPIO_PORT_W253_PWORD_Pos) /*!< GPIO_PORT W253: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W254 -----------------------------------------\r
-#define GPIO_PORT_W254_PWORD_Pos 0 /*!< GPIO_PORT W254: PWORD Position */\r
-#define GPIO_PORT_W254_PWORD_Msk (0xffffffffUL << GPIO_PORT_W254_PWORD_Pos) /*!< GPIO_PORT W254: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_W255 -----------------------------------------\r
-#define GPIO_PORT_W255_PWORD_Pos 0 /*!< GPIO_PORT W255: PWORD Position */\r
-#define GPIO_PORT_W255_PWORD_Msk (0xffffffffUL << GPIO_PORT_W255_PWORD_Pos) /*!< GPIO_PORT W255: PWORD Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_DIR0 -----------------------------------------\r
-#define GPIO_PORT_DIR0_DIRP0_Pos 0 /*!< GPIO_PORT DIR0: DIRP0 Position */\r
-#define GPIO_PORT_DIR0_DIRP0_Msk (0x01UL << GPIO_PORT_DIR0_DIRP0_Pos) /*!< GPIO_PORT DIR0: DIRP0 Mask */\r
-#define GPIO_PORT_DIR0_DIRP1_Pos 1 /*!< GPIO_PORT DIR0: DIRP1 Position */\r
-#define GPIO_PORT_DIR0_DIRP1_Msk (0x01UL << GPIO_PORT_DIR0_DIRP1_Pos) /*!< GPIO_PORT DIR0: DIRP1 Mask */\r
-#define GPIO_PORT_DIR0_DIRP2_Pos 2 /*!< GPIO_PORT DIR0: DIRP2 Position */\r
-#define GPIO_PORT_DIR0_DIRP2_Msk (0x01UL << GPIO_PORT_DIR0_DIRP2_Pos) /*!< GPIO_PORT DIR0: DIRP2 Mask */\r
-#define GPIO_PORT_DIR0_DIRP3_Pos 3 /*!< GPIO_PORT DIR0: DIRP3 Position */\r
-#define GPIO_PORT_DIR0_DIRP3_Msk (0x01UL << GPIO_PORT_DIR0_DIRP3_Pos) /*!< GPIO_PORT DIR0: DIRP3 Mask */\r
-#define GPIO_PORT_DIR0_DIRP4_Pos 4 /*!< GPIO_PORT DIR0: DIRP4 Position */\r
-#define GPIO_PORT_DIR0_DIRP4_Msk (0x01UL << GPIO_PORT_DIR0_DIRP4_Pos) /*!< GPIO_PORT DIR0: DIRP4 Mask */\r
-#define GPIO_PORT_DIR0_DIRP5_Pos 5 /*!< GPIO_PORT DIR0: DIRP5 Position */\r
-#define GPIO_PORT_DIR0_DIRP5_Msk (0x01UL << GPIO_PORT_DIR0_DIRP5_Pos) /*!< GPIO_PORT DIR0: DIRP5 Mask */\r
-#define GPIO_PORT_DIR0_DIRP6_Pos 6 /*!< GPIO_PORT DIR0: DIRP6 Position */\r
-#define GPIO_PORT_DIR0_DIRP6_Msk (0x01UL << GPIO_PORT_DIR0_DIRP6_Pos) /*!< GPIO_PORT DIR0: DIRP6 Mask */\r
-#define GPIO_PORT_DIR0_DIRP7_Pos 7 /*!< GPIO_PORT DIR0: DIRP7 Position */\r
-#define GPIO_PORT_DIR0_DIRP7_Msk (0x01UL << GPIO_PORT_DIR0_DIRP7_Pos) /*!< GPIO_PORT DIR0: DIRP7 Mask */\r
-#define GPIO_PORT_DIR0_DIRP8_Pos 8 /*!< GPIO_PORT DIR0: DIRP8 Position */\r
-#define GPIO_PORT_DIR0_DIRP8_Msk (0x01UL << GPIO_PORT_DIR0_DIRP8_Pos) /*!< GPIO_PORT DIR0: DIRP8 Mask */\r
-#define GPIO_PORT_DIR0_DIRP9_Pos 9 /*!< GPIO_PORT DIR0: DIRP9 Position */\r
-#define GPIO_PORT_DIR0_DIRP9_Msk (0x01UL << GPIO_PORT_DIR0_DIRP9_Pos) /*!< GPIO_PORT DIR0: DIRP9 Mask */\r
-#define GPIO_PORT_DIR0_DIRP10_Pos 10 /*!< GPIO_PORT DIR0: DIRP10 Position */\r
-#define GPIO_PORT_DIR0_DIRP10_Msk (0x01UL << GPIO_PORT_DIR0_DIRP10_Pos) /*!< GPIO_PORT DIR0: DIRP10 Mask */\r
-#define GPIO_PORT_DIR0_DIRP11_Pos 11 /*!< GPIO_PORT DIR0: DIRP11 Position */\r
-#define GPIO_PORT_DIR0_DIRP11_Msk (0x01UL << GPIO_PORT_DIR0_DIRP11_Pos) /*!< GPIO_PORT DIR0: DIRP11 Mask */\r
-#define GPIO_PORT_DIR0_DIRP12_Pos 12 /*!< GPIO_PORT DIR0: DIRP12 Position */\r
-#define GPIO_PORT_DIR0_DIRP12_Msk (0x01UL << GPIO_PORT_DIR0_DIRP12_Pos) /*!< GPIO_PORT DIR0: DIRP12 Mask */\r
-#define GPIO_PORT_DIR0_DIRP13_Pos 13 /*!< GPIO_PORT DIR0: DIRP13 Position */\r
-#define GPIO_PORT_DIR0_DIRP13_Msk (0x01UL << GPIO_PORT_DIR0_DIRP13_Pos) /*!< GPIO_PORT DIR0: DIRP13 Mask */\r
-#define GPIO_PORT_DIR0_DIRP14_Pos 14 /*!< GPIO_PORT DIR0: DIRP14 Position */\r
-#define GPIO_PORT_DIR0_DIRP14_Msk (0x01UL << GPIO_PORT_DIR0_DIRP14_Pos) /*!< GPIO_PORT DIR0: DIRP14 Mask */\r
-#define GPIO_PORT_DIR0_DIRP15_Pos 15 /*!< GPIO_PORT DIR0: DIRP15 Position */\r
-#define GPIO_PORT_DIR0_DIRP15_Msk (0x01UL << GPIO_PORT_DIR0_DIRP15_Pos) /*!< GPIO_PORT DIR0: DIRP15 Mask */\r
-#define GPIO_PORT_DIR0_DIRP16_Pos 16 /*!< GPIO_PORT DIR0: DIRP16 Position */\r
-#define GPIO_PORT_DIR0_DIRP16_Msk (0x01UL << GPIO_PORT_DIR0_DIRP16_Pos) /*!< GPIO_PORT DIR0: DIRP16 Mask */\r
-#define GPIO_PORT_DIR0_DIRP17_Pos 17 /*!< GPIO_PORT DIR0: DIRP17 Position */\r
-#define GPIO_PORT_DIR0_DIRP17_Msk (0x01UL << GPIO_PORT_DIR0_DIRP17_Pos) /*!< GPIO_PORT DIR0: DIRP17 Mask */\r
-#define GPIO_PORT_DIR0_DIRP18_Pos 18 /*!< GPIO_PORT DIR0: DIRP18 Position */\r
-#define GPIO_PORT_DIR0_DIRP18_Msk (0x01UL << GPIO_PORT_DIR0_DIRP18_Pos) /*!< GPIO_PORT DIR0: DIRP18 Mask */\r
-#define GPIO_PORT_DIR0_DIRP19_Pos 19 /*!< GPIO_PORT DIR0: DIRP19 Position */\r
-#define GPIO_PORT_DIR0_DIRP19_Msk (0x01UL << GPIO_PORT_DIR0_DIRP19_Pos) /*!< GPIO_PORT DIR0: DIRP19 Mask */\r
-#define GPIO_PORT_DIR0_DIRP20_Pos 20 /*!< GPIO_PORT DIR0: DIRP20 Position */\r
-#define GPIO_PORT_DIR0_DIRP20_Msk (0x01UL << GPIO_PORT_DIR0_DIRP20_Pos) /*!< GPIO_PORT DIR0: DIRP20 Mask */\r
-#define GPIO_PORT_DIR0_DIRP21_Pos 21 /*!< GPIO_PORT DIR0: DIRP21 Position */\r
-#define GPIO_PORT_DIR0_DIRP21_Msk (0x01UL << GPIO_PORT_DIR0_DIRP21_Pos) /*!< GPIO_PORT DIR0: DIRP21 Mask */\r
-#define GPIO_PORT_DIR0_DIRP22_Pos 22 /*!< GPIO_PORT DIR0: DIRP22 Position */\r
-#define GPIO_PORT_DIR0_DIRP22_Msk (0x01UL << GPIO_PORT_DIR0_DIRP22_Pos) /*!< GPIO_PORT DIR0: DIRP22 Mask */\r
-#define GPIO_PORT_DIR0_DIRP23_Pos 23 /*!< GPIO_PORT DIR0: DIRP23 Position */\r
-#define GPIO_PORT_DIR0_DIRP23_Msk (0x01UL << GPIO_PORT_DIR0_DIRP23_Pos) /*!< GPIO_PORT DIR0: DIRP23 Mask */\r
-#define GPIO_PORT_DIR0_DIRP24_Pos 24 /*!< GPIO_PORT DIR0: DIRP24 Position */\r
-#define GPIO_PORT_DIR0_DIRP24_Msk (0x01UL << GPIO_PORT_DIR0_DIRP24_Pos) /*!< GPIO_PORT DIR0: DIRP24 Mask */\r
-#define GPIO_PORT_DIR0_DIRP25_Pos 25 /*!< GPIO_PORT DIR0: DIRP25 Position */\r
-#define GPIO_PORT_DIR0_DIRP25_Msk (0x01UL << GPIO_PORT_DIR0_DIRP25_Pos) /*!< GPIO_PORT DIR0: DIRP25 Mask */\r
-#define GPIO_PORT_DIR0_DIRP26_Pos 26 /*!< GPIO_PORT DIR0: DIRP26 Position */\r
-#define GPIO_PORT_DIR0_DIRP26_Msk (0x01UL << GPIO_PORT_DIR0_DIRP26_Pos) /*!< GPIO_PORT DIR0: DIRP26 Mask */\r
-#define GPIO_PORT_DIR0_DIRP27_Pos 27 /*!< GPIO_PORT DIR0: DIRP27 Position */\r
-#define GPIO_PORT_DIR0_DIRP27_Msk (0x01UL << GPIO_PORT_DIR0_DIRP27_Pos) /*!< GPIO_PORT DIR0: DIRP27 Mask */\r
-#define GPIO_PORT_DIR0_DIRP28_Pos 28 /*!< GPIO_PORT DIR0: DIRP28 Position */\r
-#define GPIO_PORT_DIR0_DIRP28_Msk (0x01UL << GPIO_PORT_DIR0_DIRP28_Pos) /*!< GPIO_PORT DIR0: DIRP28 Mask */\r
-#define GPIO_PORT_DIR0_DIRP29_Pos 29 /*!< GPIO_PORT DIR0: DIRP29 Position */\r
-#define GPIO_PORT_DIR0_DIRP29_Msk (0x01UL << GPIO_PORT_DIR0_DIRP29_Pos) /*!< GPIO_PORT DIR0: DIRP29 Mask */\r
-#define GPIO_PORT_DIR0_DIRP30_Pos 30 /*!< GPIO_PORT DIR0: DIRP30 Position */\r
-#define GPIO_PORT_DIR0_DIRP30_Msk (0x01UL << GPIO_PORT_DIR0_DIRP30_Pos) /*!< GPIO_PORT DIR0: DIRP30 Mask */\r
-#define GPIO_PORT_DIR0_DIRP31_Pos 31 /*!< GPIO_PORT DIR0: DIRP31 Position */\r
-#define GPIO_PORT_DIR0_DIRP31_Msk (0x01UL << GPIO_PORT_DIR0_DIRP31_Pos) /*!< GPIO_PORT DIR0: DIRP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_DIR1 -----------------------------------------\r
-#define GPIO_PORT_DIR1_DIRP0_Pos 0 /*!< GPIO_PORT DIR1: DIRP0 Position */\r
-#define GPIO_PORT_DIR1_DIRP0_Msk (0x01UL << GPIO_PORT_DIR1_DIRP0_Pos) /*!< GPIO_PORT DIR1: DIRP0 Mask */\r
-#define GPIO_PORT_DIR1_DIRP1_Pos 1 /*!< GPIO_PORT DIR1: DIRP1 Position */\r
-#define GPIO_PORT_DIR1_DIRP1_Msk (0x01UL << GPIO_PORT_DIR1_DIRP1_Pos) /*!< GPIO_PORT DIR1: DIRP1 Mask */\r
-#define GPIO_PORT_DIR1_DIRP2_Pos 2 /*!< GPIO_PORT DIR1: DIRP2 Position */\r
-#define GPIO_PORT_DIR1_DIRP2_Msk (0x01UL << GPIO_PORT_DIR1_DIRP2_Pos) /*!< GPIO_PORT DIR1: DIRP2 Mask */\r
-#define GPIO_PORT_DIR1_DIRP3_Pos 3 /*!< GPIO_PORT DIR1: DIRP3 Position */\r
-#define GPIO_PORT_DIR1_DIRP3_Msk (0x01UL << GPIO_PORT_DIR1_DIRP3_Pos) /*!< GPIO_PORT DIR1: DIRP3 Mask */\r
-#define GPIO_PORT_DIR1_DIRP4_Pos 4 /*!< GPIO_PORT DIR1: DIRP4 Position */\r
-#define GPIO_PORT_DIR1_DIRP4_Msk (0x01UL << GPIO_PORT_DIR1_DIRP4_Pos) /*!< GPIO_PORT DIR1: DIRP4 Mask */\r
-#define GPIO_PORT_DIR1_DIRP5_Pos 5 /*!< GPIO_PORT DIR1: DIRP5 Position */\r
-#define GPIO_PORT_DIR1_DIRP5_Msk (0x01UL << GPIO_PORT_DIR1_DIRP5_Pos) /*!< GPIO_PORT DIR1: DIRP5 Mask */\r
-#define GPIO_PORT_DIR1_DIRP6_Pos 6 /*!< GPIO_PORT DIR1: DIRP6 Position */\r
-#define GPIO_PORT_DIR1_DIRP6_Msk (0x01UL << GPIO_PORT_DIR1_DIRP6_Pos) /*!< GPIO_PORT DIR1: DIRP6 Mask */\r
-#define GPIO_PORT_DIR1_DIRP7_Pos 7 /*!< GPIO_PORT DIR1: DIRP7 Position */\r
-#define GPIO_PORT_DIR1_DIRP7_Msk (0x01UL << GPIO_PORT_DIR1_DIRP7_Pos) /*!< GPIO_PORT DIR1: DIRP7 Mask */\r
-#define GPIO_PORT_DIR1_DIRP8_Pos 8 /*!< GPIO_PORT DIR1: DIRP8 Position */\r
-#define GPIO_PORT_DIR1_DIRP8_Msk (0x01UL << GPIO_PORT_DIR1_DIRP8_Pos) /*!< GPIO_PORT DIR1: DIRP8 Mask */\r
-#define GPIO_PORT_DIR1_DIRP9_Pos 9 /*!< GPIO_PORT DIR1: DIRP9 Position */\r
-#define GPIO_PORT_DIR1_DIRP9_Msk (0x01UL << GPIO_PORT_DIR1_DIRP9_Pos) /*!< GPIO_PORT DIR1: DIRP9 Mask */\r
-#define GPIO_PORT_DIR1_DIRP10_Pos 10 /*!< GPIO_PORT DIR1: DIRP10 Position */\r
-#define GPIO_PORT_DIR1_DIRP10_Msk (0x01UL << GPIO_PORT_DIR1_DIRP10_Pos) /*!< GPIO_PORT DIR1: DIRP10 Mask */\r
-#define GPIO_PORT_DIR1_DIRP11_Pos 11 /*!< GPIO_PORT DIR1: DIRP11 Position */\r
-#define GPIO_PORT_DIR1_DIRP11_Msk (0x01UL << GPIO_PORT_DIR1_DIRP11_Pos) /*!< GPIO_PORT DIR1: DIRP11 Mask */\r
-#define GPIO_PORT_DIR1_DIRP12_Pos 12 /*!< GPIO_PORT DIR1: DIRP12 Position */\r
-#define GPIO_PORT_DIR1_DIRP12_Msk (0x01UL << GPIO_PORT_DIR1_DIRP12_Pos) /*!< GPIO_PORT DIR1: DIRP12 Mask */\r
-#define GPIO_PORT_DIR1_DIRP13_Pos 13 /*!< GPIO_PORT DIR1: DIRP13 Position */\r
-#define GPIO_PORT_DIR1_DIRP13_Msk (0x01UL << GPIO_PORT_DIR1_DIRP13_Pos) /*!< GPIO_PORT DIR1: DIRP13 Mask */\r
-#define GPIO_PORT_DIR1_DIRP14_Pos 14 /*!< GPIO_PORT DIR1: DIRP14 Position */\r
-#define GPIO_PORT_DIR1_DIRP14_Msk (0x01UL << GPIO_PORT_DIR1_DIRP14_Pos) /*!< GPIO_PORT DIR1: DIRP14 Mask */\r
-#define GPIO_PORT_DIR1_DIRP15_Pos 15 /*!< GPIO_PORT DIR1: DIRP15 Position */\r
-#define GPIO_PORT_DIR1_DIRP15_Msk (0x01UL << GPIO_PORT_DIR1_DIRP15_Pos) /*!< GPIO_PORT DIR1: DIRP15 Mask */\r
-#define GPIO_PORT_DIR1_DIRP16_Pos 16 /*!< GPIO_PORT DIR1: DIRP16 Position */\r
-#define GPIO_PORT_DIR1_DIRP16_Msk (0x01UL << GPIO_PORT_DIR1_DIRP16_Pos) /*!< GPIO_PORT DIR1: DIRP16 Mask */\r
-#define GPIO_PORT_DIR1_DIRP17_Pos 17 /*!< GPIO_PORT DIR1: DIRP17 Position */\r
-#define GPIO_PORT_DIR1_DIRP17_Msk (0x01UL << GPIO_PORT_DIR1_DIRP17_Pos) /*!< GPIO_PORT DIR1: DIRP17 Mask */\r
-#define GPIO_PORT_DIR1_DIRP18_Pos 18 /*!< GPIO_PORT DIR1: DIRP18 Position */\r
-#define GPIO_PORT_DIR1_DIRP18_Msk (0x01UL << GPIO_PORT_DIR1_DIRP18_Pos) /*!< GPIO_PORT DIR1: DIRP18 Mask */\r
-#define GPIO_PORT_DIR1_DIRP19_Pos 19 /*!< GPIO_PORT DIR1: DIRP19 Position */\r
-#define GPIO_PORT_DIR1_DIRP19_Msk (0x01UL << GPIO_PORT_DIR1_DIRP19_Pos) /*!< GPIO_PORT DIR1: DIRP19 Mask */\r
-#define GPIO_PORT_DIR1_DIRP20_Pos 20 /*!< GPIO_PORT DIR1: DIRP20 Position */\r
-#define GPIO_PORT_DIR1_DIRP20_Msk (0x01UL << GPIO_PORT_DIR1_DIRP20_Pos) /*!< GPIO_PORT DIR1: DIRP20 Mask */\r
-#define GPIO_PORT_DIR1_DIRP21_Pos 21 /*!< GPIO_PORT DIR1: DIRP21 Position */\r
-#define GPIO_PORT_DIR1_DIRP21_Msk (0x01UL << GPIO_PORT_DIR1_DIRP21_Pos) /*!< GPIO_PORT DIR1: DIRP21 Mask */\r
-#define GPIO_PORT_DIR1_DIRP22_Pos 22 /*!< GPIO_PORT DIR1: DIRP22 Position */\r
-#define GPIO_PORT_DIR1_DIRP22_Msk (0x01UL << GPIO_PORT_DIR1_DIRP22_Pos) /*!< GPIO_PORT DIR1: DIRP22 Mask */\r
-#define GPIO_PORT_DIR1_DIRP23_Pos 23 /*!< GPIO_PORT DIR1: DIRP23 Position */\r
-#define GPIO_PORT_DIR1_DIRP23_Msk (0x01UL << GPIO_PORT_DIR1_DIRP23_Pos) /*!< GPIO_PORT DIR1: DIRP23 Mask */\r
-#define GPIO_PORT_DIR1_DIRP24_Pos 24 /*!< GPIO_PORT DIR1: DIRP24 Position */\r
-#define GPIO_PORT_DIR1_DIRP24_Msk (0x01UL << GPIO_PORT_DIR1_DIRP24_Pos) /*!< GPIO_PORT DIR1: DIRP24 Mask */\r
-#define GPIO_PORT_DIR1_DIRP25_Pos 25 /*!< GPIO_PORT DIR1: DIRP25 Position */\r
-#define GPIO_PORT_DIR1_DIRP25_Msk (0x01UL << GPIO_PORT_DIR1_DIRP25_Pos) /*!< GPIO_PORT DIR1: DIRP25 Mask */\r
-#define GPIO_PORT_DIR1_DIRP26_Pos 26 /*!< GPIO_PORT DIR1: DIRP26 Position */\r
-#define GPIO_PORT_DIR1_DIRP26_Msk (0x01UL << GPIO_PORT_DIR1_DIRP26_Pos) /*!< GPIO_PORT DIR1: DIRP26 Mask */\r
-#define GPIO_PORT_DIR1_DIRP27_Pos 27 /*!< GPIO_PORT DIR1: DIRP27 Position */\r
-#define GPIO_PORT_DIR1_DIRP27_Msk (0x01UL << GPIO_PORT_DIR1_DIRP27_Pos) /*!< GPIO_PORT DIR1: DIRP27 Mask */\r
-#define GPIO_PORT_DIR1_DIRP28_Pos 28 /*!< GPIO_PORT DIR1: DIRP28 Position */\r
-#define GPIO_PORT_DIR1_DIRP28_Msk (0x01UL << GPIO_PORT_DIR1_DIRP28_Pos) /*!< GPIO_PORT DIR1: DIRP28 Mask */\r
-#define GPIO_PORT_DIR1_DIRP29_Pos 29 /*!< GPIO_PORT DIR1: DIRP29 Position */\r
-#define GPIO_PORT_DIR1_DIRP29_Msk (0x01UL << GPIO_PORT_DIR1_DIRP29_Pos) /*!< GPIO_PORT DIR1: DIRP29 Mask */\r
-#define GPIO_PORT_DIR1_DIRP30_Pos 30 /*!< GPIO_PORT DIR1: DIRP30 Position */\r
-#define GPIO_PORT_DIR1_DIRP30_Msk (0x01UL << GPIO_PORT_DIR1_DIRP30_Pos) /*!< GPIO_PORT DIR1: DIRP30 Mask */\r
-#define GPIO_PORT_DIR1_DIRP31_Pos 31 /*!< GPIO_PORT DIR1: DIRP31 Position */\r
-#define GPIO_PORT_DIR1_DIRP31_Msk (0x01UL << GPIO_PORT_DIR1_DIRP31_Pos) /*!< GPIO_PORT DIR1: DIRP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_DIR2 -----------------------------------------\r
-#define GPIO_PORT_DIR2_DIRP0_Pos 0 /*!< GPIO_PORT DIR2: DIRP0 Position */\r
-#define GPIO_PORT_DIR2_DIRP0_Msk (0x01UL << GPIO_PORT_DIR2_DIRP0_Pos) /*!< GPIO_PORT DIR2: DIRP0 Mask */\r
-#define GPIO_PORT_DIR2_DIRP1_Pos 1 /*!< GPIO_PORT DIR2: DIRP1 Position */\r
-#define GPIO_PORT_DIR2_DIRP1_Msk (0x01UL << GPIO_PORT_DIR2_DIRP1_Pos) /*!< GPIO_PORT DIR2: DIRP1 Mask */\r
-#define GPIO_PORT_DIR2_DIRP2_Pos 2 /*!< GPIO_PORT DIR2: DIRP2 Position */\r
-#define GPIO_PORT_DIR2_DIRP2_Msk (0x01UL << GPIO_PORT_DIR2_DIRP2_Pos) /*!< GPIO_PORT DIR2: DIRP2 Mask */\r
-#define GPIO_PORT_DIR2_DIRP3_Pos 3 /*!< GPIO_PORT DIR2: DIRP3 Position */\r
-#define GPIO_PORT_DIR2_DIRP3_Msk (0x01UL << GPIO_PORT_DIR2_DIRP3_Pos) /*!< GPIO_PORT DIR2: DIRP3 Mask */\r
-#define GPIO_PORT_DIR2_DIRP4_Pos 4 /*!< GPIO_PORT DIR2: DIRP4 Position */\r
-#define GPIO_PORT_DIR2_DIRP4_Msk (0x01UL << GPIO_PORT_DIR2_DIRP4_Pos) /*!< GPIO_PORT DIR2: DIRP4 Mask */\r
-#define GPIO_PORT_DIR2_DIRP5_Pos 5 /*!< GPIO_PORT DIR2: DIRP5 Position */\r
-#define GPIO_PORT_DIR2_DIRP5_Msk (0x01UL << GPIO_PORT_DIR2_DIRP5_Pos) /*!< GPIO_PORT DIR2: DIRP5 Mask */\r
-#define GPIO_PORT_DIR2_DIRP6_Pos 6 /*!< GPIO_PORT DIR2: DIRP6 Position */\r
-#define GPIO_PORT_DIR2_DIRP6_Msk (0x01UL << GPIO_PORT_DIR2_DIRP6_Pos) /*!< GPIO_PORT DIR2: DIRP6 Mask */\r
-#define GPIO_PORT_DIR2_DIRP7_Pos 7 /*!< GPIO_PORT DIR2: DIRP7 Position */\r
-#define GPIO_PORT_DIR2_DIRP7_Msk (0x01UL << GPIO_PORT_DIR2_DIRP7_Pos) /*!< GPIO_PORT DIR2: DIRP7 Mask */\r
-#define GPIO_PORT_DIR2_DIRP8_Pos 8 /*!< GPIO_PORT DIR2: DIRP8 Position */\r
-#define GPIO_PORT_DIR2_DIRP8_Msk (0x01UL << GPIO_PORT_DIR2_DIRP8_Pos) /*!< GPIO_PORT DIR2: DIRP8 Mask */\r
-#define GPIO_PORT_DIR2_DIRP9_Pos 9 /*!< GPIO_PORT DIR2: DIRP9 Position */\r
-#define GPIO_PORT_DIR2_DIRP9_Msk (0x01UL << GPIO_PORT_DIR2_DIRP9_Pos) /*!< GPIO_PORT DIR2: DIRP9 Mask */\r
-#define GPIO_PORT_DIR2_DIRP10_Pos 10 /*!< GPIO_PORT DIR2: DIRP10 Position */\r
-#define GPIO_PORT_DIR2_DIRP10_Msk (0x01UL << GPIO_PORT_DIR2_DIRP10_Pos) /*!< GPIO_PORT DIR2: DIRP10 Mask */\r
-#define GPIO_PORT_DIR2_DIRP11_Pos 11 /*!< GPIO_PORT DIR2: DIRP11 Position */\r
-#define GPIO_PORT_DIR2_DIRP11_Msk (0x01UL << GPIO_PORT_DIR2_DIRP11_Pos) /*!< GPIO_PORT DIR2: DIRP11 Mask */\r
-#define GPIO_PORT_DIR2_DIRP12_Pos 12 /*!< GPIO_PORT DIR2: DIRP12 Position */\r
-#define GPIO_PORT_DIR2_DIRP12_Msk (0x01UL << GPIO_PORT_DIR2_DIRP12_Pos) /*!< GPIO_PORT DIR2: DIRP12 Mask */\r
-#define GPIO_PORT_DIR2_DIRP13_Pos 13 /*!< GPIO_PORT DIR2: DIRP13 Position */\r
-#define GPIO_PORT_DIR2_DIRP13_Msk (0x01UL << GPIO_PORT_DIR2_DIRP13_Pos) /*!< GPIO_PORT DIR2: DIRP13 Mask */\r
-#define GPIO_PORT_DIR2_DIRP14_Pos 14 /*!< GPIO_PORT DIR2: DIRP14 Position */\r
-#define GPIO_PORT_DIR2_DIRP14_Msk (0x01UL << GPIO_PORT_DIR2_DIRP14_Pos) /*!< GPIO_PORT DIR2: DIRP14 Mask */\r
-#define GPIO_PORT_DIR2_DIRP15_Pos 15 /*!< GPIO_PORT DIR2: DIRP15 Position */\r
-#define GPIO_PORT_DIR2_DIRP15_Msk (0x01UL << GPIO_PORT_DIR2_DIRP15_Pos) /*!< GPIO_PORT DIR2: DIRP15 Mask */\r
-#define GPIO_PORT_DIR2_DIRP16_Pos 16 /*!< GPIO_PORT DIR2: DIRP16 Position */\r
-#define GPIO_PORT_DIR2_DIRP16_Msk (0x01UL << GPIO_PORT_DIR2_DIRP16_Pos) /*!< GPIO_PORT DIR2: DIRP16 Mask */\r
-#define GPIO_PORT_DIR2_DIRP17_Pos 17 /*!< GPIO_PORT DIR2: DIRP17 Position */\r
-#define GPIO_PORT_DIR2_DIRP17_Msk (0x01UL << GPIO_PORT_DIR2_DIRP17_Pos) /*!< GPIO_PORT DIR2: DIRP17 Mask */\r
-#define GPIO_PORT_DIR2_DIRP18_Pos 18 /*!< GPIO_PORT DIR2: DIRP18 Position */\r
-#define GPIO_PORT_DIR2_DIRP18_Msk (0x01UL << GPIO_PORT_DIR2_DIRP18_Pos) /*!< GPIO_PORT DIR2: DIRP18 Mask */\r
-#define GPIO_PORT_DIR2_DIRP19_Pos 19 /*!< GPIO_PORT DIR2: DIRP19 Position */\r
-#define GPIO_PORT_DIR2_DIRP19_Msk (0x01UL << GPIO_PORT_DIR2_DIRP19_Pos) /*!< GPIO_PORT DIR2: DIRP19 Mask */\r
-#define GPIO_PORT_DIR2_DIRP20_Pos 20 /*!< GPIO_PORT DIR2: DIRP20 Position */\r
-#define GPIO_PORT_DIR2_DIRP20_Msk (0x01UL << GPIO_PORT_DIR2_DIRP20_Pos) /*!< GPIO_PORT DIR2: DIRP20 Mask */\r
-#define GPIO_PORT_DIR2_DIRP21_Pos 21 /*!< GPIO_PORT DIR2: DIRP21 Position */\r
-#define GPIO_PORT_DIR2_DIRP21_Msk (0x01UL << GPIO_PORT_DIR2_DIRP21_Pos) /*!< GPIO_PORT DIR2: DIRP21 Mask */\r
-#define GPIO_PORT_DIR2_DIRP22_Pos 22 /*!< GPIO_PORT DIR2: DIRP22 Position */\r
-#define GPIO_PORT_DIR2_DIRP22_Msk (0x01UL << GPIO_PORT_DIR2_DIRP22_Pos) /*!< GPIO_PORT DIR2: DIRP22 Mask */\r
-#define GPIO_PORT_DIR2_DIRP23_Pos 23 /*!< GPIO_PORT DIR2: DIRP23 Position */\r
-#define GPIO_PORT_DIR2_DIRP23_Msk (0x01UL << GPIO_PORT_DIR2_DIRP23_Pos) /*!< GPIO_PORT DIR2: DIRP23 Mask */\r
-#define GPIO_PORT_DIR2_DIRP24_Pos 24 /*!< GPIO_PORT DIR2: DIRP24 Position */\r
-#define GPIO_PORT_DIR2_DIRP24_Msk (0x01UL << GPIO_PORT_DIR2_DIRP24_Pos) /*!< GPIO_PORT DIR2: DIRP24 Mask */\r
-#define GPIO_PORT_DIR2_DIRP25_Pos 25 /*!< GPIO_PORT DIR2: DIRP25 Position */\r
-#define GPIO_PORT_DIR2_DIRP25_Msk (0x01UL << GPIO_PORT_DIR2_DIRP25_Pos) /*!< GPIO_PORT DIR2: DIRP25 Mask */\r
-#define GPIO_PORT_DIR2_DIRP26_Pos 26 /*!< GPIO_PORT DIR2: DIRP26 Position */\r
-#define GPIO_PORT_DIR2_DIRP26_Msk (0x01UL << GPIO_PORT_DIR2_DIRP26_Pos) /*!< GPIO_PORT DIR2: DIRP26 Mask */\r
-#define GPIO_PORT_DIR2_DIRP27_Pos 27 /*!< GPIO_PORT DIR2: DIRP27 Position */\r
-#define GPIO_PORT_DIR2_DIRP27_Msk (0x01UL << GPIO_PORT_DIR2_DIRP27_Pos) /*!< GPIO_PORT DIR2: DIRP27 Mask */\r
-#define GPIO_PORT_DIR2_DIRP28_Pos 28 /*!< GPIO_PORT DIR2: DIRP28 Position */\r
-#define GPIO_PORT_DIR2_DIRP28_Msk (0x01UL << GPIO_PORT_DIR2_DIRP28_Pos) /*!< GPIO_PORT DIR2: DIRP28 Mask */\r
-#define GPIO_PORT_DIR2_DIRP29_Pos 29 /*!< GPIO_PORT DIR2: DIRP29 Position */\r
-#define GPIO_PORT_DIR2_DIRP29_Msk (0x01UL << GPIO_PORT_DIR2_DIRP29_Pos) /*!< GPIO_PORT DIR2: DIRP29 Mask */\r
-#define GPIO_PORT_DIR2_DIRP30_Pos 30 /*!< GPIO_PORT DIR2: DIRP30 Position */\r
-#define GPIO_PORT_DIR2_DIRP30_Msk (0x01UL << GPIO_PORT_DIR2_DIRP30_Pos) /*!< GPIO_PORT DIR2: DIRP30 Mask */\r
-#define GPIO_PORT_DIR2_DIRP31_Pos 31 /*!< GPIO_PORT DIR2: DIRP31 Position */\r
-#define GPIO_PORT_DIR2_DIRP31_Msk (0x01UL << GPIO_PORT_DIR2_DIRP31_Pos) /*!< GPIO_PORT DIR2: DIRP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_DIR3 -----------------------------------------\r
-#define GPIO_PORT_DIR3_DIRP0_Pos 0 /*!< GPIO_PORT DIR3: DIRP0 Position */\r
-#define GPIO_PORT_DIR3_DIRP0_Msk (0x01UL << GPIO_PORT_DIR3_DIRP0_Pos) /*!< GPIO_PORT DIR3: DIRP0 Mask */\r
-#define GPIO_PORT_DIR3_DIRP1_Pos 1 /*!< GPIO_PORT DIR3: DIRP1 Position */\r
-#define GPIO_PORT_DIR3_DIRP1_Msk (0x01UL << GPIO_PORT_DIR3_DIRP1_Pos) /*!< GPIO_PORT DIR3: DIRP1 Mask */\r
-#define GPIO_PORT_DIR3_DIRP2_Pos 2 /*!< GPIO_PORT DIR3: DIRP2 Position */\r
-#define GPIO_PORT_DIR3_DIRP2_Msk (0x01UL << GPIO_PORT_DIR3_DIRP2_Pos) /*!< GPIO_PORT DIR3: DIRP2 Mask */\r
-#define GPIO_PORT_DIR3_DIRP3_Pos 3 /*!< GPIO_PORT DIR3: DIRP3 Position */\r
-#define GPIO_PORT_DIR3_DIRP3_Msk (0x01UL << GPIO_PORT_DIR3_DIRP3_Pos) /*!< GPIO_PORT DIR3: DIRP3 Mask */\r
-#define GPIO_PORT_DIR3_DIRP4_Pos 4 /*!< GPIO_PORT DIR3: DIRP4 Position */\r
-#define GPIO_PORT_DIR3_DIRP4_Msk (0x01UL << GPIO_PORT_DIR3_DIRP4_Pos) /*!< GPIO_PORT DIR3: DIRP4 Mask */\r
-#define GPIO_PORT_DIR3_DIRP5_Pos 5 /*!< GPIO_PORT DIR3: DIRP5 Position */\r
-#define GPIO_PORT_DIR3_DIRP5_Msk (0x01UL << GPIO_PORT_DIR3_DIRP5_Pos) /*!< GPIO_PORT DIR3: DIRP5 Mask */\r
-#define GPIO_PORT_DIR3_DIRP6_Pos 6 /*!< GPIO_PORT DIR3: DIRP6 Position */\r
-#define GPIO_PORT_DIR3_DIRP6_Msk (0x01UL << GPIO_PORT_DIR3_DIRP6_Pos) /*!< GPIO_PORT DIR3: DIRP6 Mask */\r
-#define GPIO_PORT_DIR3_DIRP7_Pos 7 /*!< GPIO_PORT DIR3: DIRP7 Position */\r
-#define GPIO_PORT_DIR3_DIRP7_Msk (0x01UL << GPIO_PORT_DIR3_DIRP7_Pos) /*!< GPIO_PORT DIR3: DIRP7 Mask */\r
-#define GPIO_PORT_DIR3_DIRP8_Pos 8 /*!< GPIO_PORT DIR3: DIRP8 Position */\r
-#define GPIO_PORT_DIR3_DIRP8_Msk (0x01UL << GPIO_PORT_DIR3_DIRP8_Pos) /*!< GPIO_PORT DIR3: DIRP8 Mask */\r
-#define GPIO_PORT_DIR3_DIRP9_Pos 9 /*!< GPIO_PORT DIR3: DIRP9 Position */\r
-#define GPIO_PORT_DIR3_DIRP9_Msk (0x01UL << GPIO_PORT_DIR3_DIRP9_Pos) /*!< GPIO_PORT DIR3: DIRP9 Mask */\r
-#define GPIO_PORT_DIR3_DIRP10_Pos 10 /*!< GPIO_PORT DIR3: DIRP10 Position */\r
-#define GPIO_PORT_DIR3_DIRP10_Msk (0x01UL << GPIO_PORT_DIR3_DIRP10_Pos) /*!< GPIO_PORT DIR3: DIRP10 Mask */\r
-#define GPIO_PORT_DIR3_DIRP11_Pos 11 /*!< GPIO_PORT DIR3: DIRP11 Position */\r
-#define GPIO_PORT_DIR3_DIRP11_Msk (0x01UL << GPIO_PORT_DIR3_DIRP11_Pos) /*!< GPIO_PORT DIR3: DIRP11 Mask */\r
-#define GPIO_PORT_DIR3_DIRP12_Pos 12 /*!< GPIO_PORT DIR3: DIRP12 Position */\r
-#define GPIO_PORT_DIR3_DIRP12_Msk (0x01UL << GPIO_PORT_DIR3_DIRP12_Pos) /*!< GPIO_PORT DIR3: DIRP12 Mask */\r
-#define GPIO_PORT_DIR3_DIRP13_Pos 13 /*!< GPIO_PORT DIR3: DIRP13 Position */\r
-#define GPIO_PORT_DIR3_DIRP13_Msk (0x01UL << GPIO_PORT_DIR3_DIRP13_Pos) /*!< GPIO_PORT DIR3: DIRP13 Mask */\r
-#define GPIO_PORT_DIR3_DIRP14_Pos 14 /*!< GPIO_PORT DIR3: DIRP14 Position */\r
-#define GPIO_PORT_DIR3_DIRP14_Msk (0x01UL << GPIO_PORT_DIR3_DIRP14_Pos) /*!< GPIO_PORT DIR3: DIRP14 Mask */\r
-#define GPIO_PORT_DIR3_DIRP15_Pos 15 /*!< GPIO_PORT DIR3: DIRP15 Position */\r
-#define GPIO_PORT_DIR3_DIRP15_Msk (0x01UL << GPIO_PORT_DIR3_DIRP15_Pos) /*!< GPIO_PORT DIR3: DIRP15 Mask */\r
-#define GPIO_PORT_DIR3_DIRP16_Pos 16 /*!< GPIO_PORT DIR3: DIRP16 Position */\r
-#define GPIO_PORT_DIR3_DIRP16_Msk (0x01UL << GPIO_PORT_DIR3_DIRP16_Pos) /*!< GPIO_PORT DIR3: DIRP16 Mask */\r
-#define GPIO_PORT_DIR3_DIRP17_Pos 17 /*!< GPIO_PORT DIR3: DIRP17 Position */\r
-#define GPIO_PORT_DIR3_DIRP17_Msk (0x01UL << GPIO_PORT_DIR3_DIRP17_Pos) /*!< GPIO_PORT DIR3: DIRP17 Mask */\r
-#define GPIO_PORT_DIR3_DIRP18_Pos 18 /*!< GPIO_PORT DIR3: DIRP18 Position */\r
-#define GPIO_PORT_DIR3_DIRP18_Msk (0x01UL << GPIO_PORT_DIR3_DIRP18_Pos) /*!< GPIO_PORT DIR3: DIRP18 Mask */\r
-#define GPIO_PORT_DIR3_DIRP19_Pos 19 /*!< GPIO_PORT DIR3: DIRP19 Position */\r
-#define GPIO_PORT_DIR3_DIRP19_Msk (0x01UL << GPIO_PORT_DIR3_DIRP19_Pos) /*!< GPIO_PORT DIR3: DIRP19 Mask */\r
-#define GPIO_PORT_DIR3_DIRP20_Pos 20 /*!< GPIO_PORT DIR3: DIRP20 Position */\r
-#define GPIO_PORT_DIR3_DIRP20_Msk (0x01UL << GPIO_PORT_DIR3_DIRP20_Pos) /*!< GPIO_PORT DIR3: DIRP20 Mask */\r
-#define GPIO_PORT_DIR3_DIRP21_Pos 21 /*!< GPIO_PORT DIR3: DIRP21 Position */\r
-#define GPIO_PORT_DIR3_DIRP21_Msk (0x01UL << GPIO_PORT_DIR3_DIRP21_Pos) /*!< GPIO_PORT DIR3: DIRP21 Mask */\r
-#define GPIO_PORT_DIR3_DIRP22_Pos 22 /*!< GPIO_PORT DIR3: DIRP22 Position */\r
-#define GPIO_PORT_DIR3_DIRP22_Msk (0x01UL << GPIO_PORT_DIR3_DIRP22_Pos) /*!< GPIO_PORT DIR3: DIRP22 Mask */\r
-#define GPIO_PORT_DIR3_DIRP23_Pos 23 /*!< GPIO_PORT DIR3: DIRP23 Position */\r
-#define GPIO_PORT_DIR3_DIRP23_Msk (0x01UL << GPIO_PORT_DIR3_DIRP23_Pos) /*!< GPIO_PORT DIR3: DIRP23 Mask */\r
-#define GPIO_PORT_DIR3_DIRP24_Pos 24 /*!< GPIO_PORT DIR3: DIRP24 Position */\r
-#define GPIO_PORT_DIR3_DIRP24_Msk (0x01UL << GPIO_PORT_DIR3_DIRP24_Pos) /*!< GPIO_PORT DIR3: DIRP24 Mask */\r
-#define GPIO_PORT_DIR3_DIRP25_Pos 25 /*!< GPIO_PORT DIR3: DIRP25 Position */\r
-#define GPIO_PORT_DIR3_DIRP25_Msk (0x01UL << GPIO_PORT_DIR3_DIRP25_Pos) /*!< GPIO_PORT DIR3: DIRP25 Mask */\r
-#define GPIO_PORT_DIR3_DIRP26_Pos 26 /*!< GPIO_PORT DIR3: DIRP26 Position */\r
-#define GPIO_PORT_DIR3_DIRP26_Msk (0x01UL << GPIO_PORT_DIR3_DIRP26_Pos) /*!< GPIO_PORT DIR3: DIRP26 Mask */\r
-#define GPIO_PORT_DIR3_DIRP27_Pos 27 /*!< GPIO_PORT DIR3: DIRP27 Position */\r
-#define GPIO_PORT_DIR3_DIRP27_Msk (0x01UL << GPIO_PORT_DIR3_DIRP27_Pos) /*!< GPIO_PORT DIR3: DIRP27 Mask */\r
-#define GPIO_PORT_DIR3_DIRP28_Pos 28 /*!< GPIO_PORT DIR3: DIRP28 Position */\r
-#define GPIO_PORT_DIR3_DIRP28_Msk (0x01UL << GPIO_PORT_DIR3_DIRP28_Pos) /*!< GPIO_PORT DIR3: DIRP28 Mask */\r
-#define GPIO_PORT_DIR3_DIRP29_Pos 29 /*!< GPIO_PORT DIR3: DIRP29 Position */\r
-#define GPIO_PORT_DIR3_DIRP29_Msk (0x01UL << GPIO_PORT_DIR3_DIRP29_Pos) /*!< GPIO_PORT DIR3: DIRP29 Mask */\r
-#define GPIO_PORT_DIR3_DIRP30_Pos 30 /*!< GPIO_PORT DIR3: DIRP30 Position */\r
-#define GPIO_PORT_DIR3_DIRP30_Msk (0x01UL << GPIO_PORT_DIR3_DIRP30_Pos) /*!< GPIO_PORT DIR3: DIRP30 Mask */\r
-#define GPIO_PORT_DIR3_DIRP31_Pos 31 /*!< GPIO_PORT DIR3: DIRP31 Position */\r
-#define GPIO_PORT_DIR3_DIRP31_Msk (0x01UL << GPIO_PORT_DIR3_DIRP31_Pos) /*!< GPIO_PORT DIR3: DIRP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_DIR4 -----------------------------------------\r
-#define GPIO_PORT_DIR4_DIRP0_Pos 0 /*!< GPIO_PORT DIR4: DIRP0 Position */\r
-#define GPIO_PORT_DIR4_DIRP0_Msk (0x01UL << GPIO_PORT_DIR4_DIRP0_Pos) /*!< GPIO_PORT DIR4: DIRP0 Mask */\r
-#define GPIO_PORT_DIR4_DIRP1_Pos 1 /*!< GPIO_PORT DIR4: DIRP1 Position */\r
-#define GPIO_PORT_DIR4_DIRP1_Msk (0x01UL << GPIO_PORT_DIR4_DIRP1_Pos) /*!< GPIO_PORT DIR4: DIRP1 Mask */\r
-#define GPIO_PORT_DIR4_DIRP2_Pos 2 /*!< GPIO_PORT DIR4: DIRP2 Position */\r
-#define GPIO_PORT_DIR4_DIRP2_Msk (0x01UL << GPIO_PORT_DIR4_DIRP2_Pos) /*!< GPIO_PORT DIR4: DIRP2 Mask */\r
-#define GPIO_PORT_DIR4_DIRP3_Pos 3 /*!< GPIO_PORT DIR4: DIRP3 Position */\r
-#define GPIO_PORT_DIR4_DIRP3_Msk (0x01UL << GPIO_PORT_DIR4_DIRP3_Pos) /*!< GPIO_PORT DIR4: DIRP3 Mask */\r
-#define GPIO_PORT_DIR4_DIRP4_Pos 4 /*!< GPIO_PORT DIR4: DIRP4 Position */\r
-#define GPIO_PORT_DIR4_DIRP4_Msk (0x01UL << GPIO_PORT_DIR4_DIRP4_Pos) /*!< GPIO_PORT DIR4: DIRP4 Mask */\r
-#define GPIO_PORT_DIR4_DIRP5_Pos 5 /*!< GPIO_PORT DIR4: DIRP5 Position */\r
-#define GPIO_PORT_DIR4_DIRP5_Msk (0x01UL << GPIO_PORT_DIR4_DIRP5_Pos) /*!< GPIO_PORT DIR4: DIRP5 Mask */\r
-#define GPIO_PORT_DIR4_DIRP6_Pos 6 /*!< GPIO_PORT DIR4: DIRP6 Position */\r
-#define GPIO_PORT_DIR4_DIRP6_Msk (0x01UL << GPIO_PORT_DIR4_DIRP6_Pos) /*!< GPIO_PORT DIR4: DIRP6 Mask */\r
-#define GPIO_PORT_DIR4_DIRP7_Pos 7 /*!< GPIO_PORT DIR4: DIRP7 Position */\r
-#define GPIO_PORT_DIR4_DIRP7_Msk (0x01UL << GPIO_PORT_DIR4_DIRP7_Pos) /*!< GPIO_PORT DIR4: DIRP7 Mask */\r
-#define GPIO_PORT_DIR4_DIRP8_Pos 8 /*!< GPIO_PORT DIR4: DIRP8 Position */\r
-#define GPIO_PORT_DIR4_DIRP8_Msk (0x01UL << GPIO_PORT_DIR4_DIRP8_Pos) /*!< GPIO_PORT DIR4: DIRP8 Mask */\r
-#define GPIO_PORT_DIR4_DIRP9_Pos 9 /*!< GPIO_PORT DIR4: DIRP9 Position */\r
-#define GPIO_PORT_DIR4_DIRP9_Msk (0x01UL << GPIO_PORT_DIR4_DIRP9_Pos) /*!< GPIO_PORT DIR4: DIRP9 Mask */\r
-#define GPIO_PORT_DIR4_DIRP10_Pos 10 /*!< GPIO_PORT DIR4: DIRP10 Position */\r
-#define GPIO_PORT_DIR4_DIRP10_Msk (0x01UL << GPIO_PORT_DIR4_DIRP10_Pos) /*!< GPIO_PORT DIR4: DIRP10 Mask */\r
-#define GPIO_PORT_DIR4_DIRP11_Pos 11 /*!< GPIO_PORT DIR4: DIRP11 Position */\r
-#define GPIO_PORT_DIR4_DIRP11_Msk (0x01UL << GPIO_PORT_DIR4_DIRP11_Pos) /*!< GPIO_PORT DIR4: DIRP11 Mask */\r
-#define GPIO_PORT_DIR4_DIRP12_Pos 12 /*!< GPIO_PORT DIR4: DIRP12 Position */\r
-#define GPIO_PORT_DIR4_DIRP12_Msk (0x01UL << GPIO_PORT_DIR4_DIRP12_Pos) /*!< GPIO_PORT DIR4: DIRP12 Mask */\r
-#define GPIO_PORT_DIR4_DIRP13_Pos 13 /*!< GPIO_PORT DIR4: DIRP13 Position */\r
-#define GPIO_PORT_DIR4_DIRP13_Msk (0x01UL << GPIO_PORT_DIR4_DIRP13_Pos) /*!< GPIO_PORT DIR4: DIRP13 Mask */\r
-#define GPIO_PORT_DIR4_DIRP14_Pos 14 /*!< GPIO_PORT DIR4: DIRP14 Position */\r
-#define GPIO_PORT_DIR4_DIRP14_Msk (0x01UL << GPIO_PORT_DIR4_DIRP14_Pos) /*!< GPIO_PORT DIR4: DIRP14 Mask */\r
-#define GPIO_PORT_DIR4_DIRP15_Pos 15 /*!< GPIO_PORT DIR4: DIRP15 Position */\r
-#define GPIO_PORT_DIR4_DIRP15_Msk (0x01UL << GPIO_PORT_DIR4_DIRP15_Pos) /*!< GPIO_PORT DIR4: DIRP15 Mask */\r
-#define GPIO_PORT_DIR4_DIRP16_Pos 16 /*!< GPIO_PORT DIR4: DIRP16 Position */\r
-#define GPIO_PORT_DIR4_DIRP16_Msk (0x01UL << GPIO_PORT_DIR4_DIRP16_Pos) /*!< GPIO_PORT DIR4: DIRP16 Mask */\r
-#define GPIO_PORT_DIR4_DIRP17_Pos 17 /*!< GPIO_PORT DIR4: DIRP17 Position */\r
-#define GPIO_PORT_DIR4_DIRP17_Msk (0x01UL << GPIO_PORT_DIR4_DIRP17_Pos) /*!< GPIO_PORT DIR4: DIRP17 Mask */\r
-#define GPIO_PORT_DIR4_DIRP18_Pos 18 /*!< GPIO_PORT DIR4: DIRP18 Position */\r
-#define GPIO_PORT_DIR4_DIRP18_Msk (0x01UL << GPIO_PORT_DIR4_DIRP18_Pos) /*!< GPIO_PORT DIR4: DIRP18 Mask */\r
-#define GPIO_PORT_DIR4_DIRP19_Pos 19 /*!< GPIO_PORT DIR4: DIRP19 Position */\r
-#define GPIO_PORT_DIR4_DIRP19_Msk (0x01UL << GPIO_PORT_DIR4_DIRP19_Pos) /*!< GPIO_PORT DIR4: DIRP19 Mask */\r
-#define GPIO_PORT_DIR4_DIRP20_Pos 20 /*!< GPIO_PORT DIR4: DIRP20 Position */\r
-#define GPIO_PORT_DIR4_DIRP20_Msk (0x01UL << GPIO_PORT_DIR4_DIRP20_Pos) /*!< GPIO_PORT DIR4: DIRP20 Mask */\r
-#define GPIO_PORT_DIR4_DIRP21_Pos 21 /*!< GPIO_PORT DIR4: DIRP21 Position */\r
-#define GPIO_PORT_DIR4_DIRP21_Msk (0x01UL << GPIO_PORT_DIR4_DIRP21_Pos) /*!< GPIO_PORT DIR4: DIRP21 Mask */\r
-#define GPIO_PORT_DIR4_DIRP22_Pos 22 /*!< GPIO_PORT DIR4: DIRP22 Position */\r
-#define GPIO_PORT_DIR4_DIRP22_Msk (0x01UL << GPIO_PORT_DIR4_DIRP22_Pos) /*!< GPIO_PORT DIR4: DIRP22 Mask */\r
-#define GPIO_PORT_DIR4_DIRP23_Pos 23 /*!< GPIO_PORT DIR4: DIRP23 Position */\r
-#define GPIO_PORT_DIR4_DIRP23_Msk (0x01UL << GPIO_PORT_DIR4_DIRP23_Pos) /*!< GPIO_PORT DIR4: DIRP23 Mask */\r
-#define GPIO_PORT_DIR4_DIRP24_Pos 24 /*!< GPIO_PORT DIR4: DIRP24 Position */\r
-#define GPIO_PORT_DIR4_DIRP24_Msk (0x01UL << GPIO_PORT_DIR4_DIRP24_Pos) /*!< GPIO_PORT DIR4: DIRP24 Mask */\r
-#define GPIO_PORT_DIR4_DIRP25_Pos 25 /*!< GPIO_PORT DIR4: DIRP25 Position */\r
-#define GPIO_PORT_DIR4_DIRP25_Msk (0x01UL << GPIO_PORT_DIR4_DIRP25_Pos) /*!< GPIO_PORT DIR4: DIRP25 Mask */\r
-#define GPIO_PORT_DIR4_DIRP26_Pos 26 /*!< GPIO_PORT DIR4: DIRP26 Position */\r
-#define GPIO_PORT_DIR4_DIRP26_Msk (0x01UL << GPIO_PORT_DIR4_DIRP26_Pos) /*!< GPIO_PORT DIR4: DIRP26 Mask */\r
-#define GPIO_PORT_DIR4_DIRP27_Pos 27 /*!< GPIO_PORT DIR4: DIRP27 Position */\r
-#define GPIO_PORT_DIR4_DIRP27_Msk (0x01UL << GPIO_PORT_DIR4_DIRP27_Pos) /*!< GPIO_PORT DIR4: DIRP27 Mask */\r
-#define GPIO_PORT_DIR4_DIRP28_Pos 28 /*!< GPIO_PORT DIR4: DIRP28 Position */\r
-#define GPIO_PORT_DIR4_DIRP28_Msk (0x01UL << GPIO_PORT_DIR4_DIRP28_Pos) /*!< GPIO_PORT DIR4: DIRP28 Mask */\r
-#define GPIO_PORT_DIR4_DIRP29_Pos 29 /*!< GPIO_PORT DIR4: DIRP29 Position */\r
-#define GPIO_PORT_DIR4_DIRP29_Msk (0x01UL << GPIO_PORT_DIR4_DIRP29_Pos) /*!< GPIO_PORT DIR4: DIRP29 Mask */\r
-#define GPIO_PORT_DIR4_DIRP30_Pos 30 /*!< GPIO_PORT DIR4: DIRP30 Position */\r
-#define GPIO_PORT_DIR4_DIRP30_Msk (0x01UL << GPIO_PORT_DIR4_DIRP30_Pos) /*!< GPIO_PORT DIR4: DIRP30 Mask */\r
-#define GPIO_PORT_DIR4_DIRP31_Pos 31 /*!< GPIO_PORT DIR4: DIRP31 Position */\r
-#define GPIO_PORT_DIR4_DIRP31_Msk (0x01UL << GPIO_PORT_DIR4_DIRP31_Pos) /*!< GPIO_PORT DIR4: DIRP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_DIR5 -----------------------------------------\r
-#define GPIO_PORT_DIR5_DIRP0_Pos 0 /*!< GPIO_PORT DIR5: DIRP0 Position */\r
-#define GPIO_PORT_DIR5_DIRP0_Msk (0x01UL << GPIO_PORT_DIR5_DIRP0_Pos) /*!< GPIO_PORT DIR5: DIRP0 Mask */\r
-#define GPIO_PORT_DIR5_DIRP1_Pos 1 /*!< GPIO_PORT DIR5: DIRP1 Position */\r
-#define GPIO_PORT_DIR5_DIRP1_Msk (0x01UL << GPIO_PORT_DIR5_DIRP1_Pos) /*!< GPIO_PORT DIR5: DIRP1 Mask */\r
-#define GPIO_PORT_DIR5_DIRP2_Pos 2 /*!< GPIO_PORT DIR5: DIRP2 Position */\r
-#define GPIO_PORT_DIR5_DIRP2_Msk (0x01UL << GPIO_PORT_DIR5_DIRP2_Pos) /*!< GPIO_PORT DIR5: DIRP2 Mask */\r
-#define GPIO_PORT_DIR5_DIRP3_Pos 3 /*!< GPIO_PORT DIR5: DIRP3 Position */\r
-#define GPIO_PORT_DIR5_DIRP3_Msk (0x01UL << GPIO_PORT_DIR5_DIRP3_Pos) /*!< GPIO_PORT DIR5: DIRP3 Mask */\r
-#define GPIO_PORT_DIR5_DIRP4_Pos 4 /*!< GPIO_PORT DIR5: DIRP4 Position */\r
-#define GPIO_PORT_DIR5_DIRP4_Msk (0x01UL << GPIO_PORT_DIR5_DIRP4_Pos) /*!< GPIO_PORT DIR5: DIRP4 Mask */\r
-#define GPIO_PORT_DIR5_DIRP5_Pos 5 /*!< GPIO_PORT DIR5: DIRP5 Position */\r
-#define GPIO_PORT_DIR5_DIRP5_Msk (0x01UL << GPIO_PORT_DIR5_DIRP5_Pos) /*!< GPIO_PORT DIR5: DIRP5 Mask */\r
-#define GPIO_PORT_DIR5_DIRP6_Pos 6 /*!< GPIO_PORT DIR5: DIRP6 Position */\r
-#define GPIO_PORT_DIR5_DIRP6_Msk (0x01UL << GPIO_PORT_DIR5_DIRP6_Pos) /*!< GPIO_PORT DIR5: DIRP6 Mask */\r
-#define GPIO_PORT_DIR5_DIRP7_Pos 7 /*!< GPIO_PORT DIR5: DIRP7 Position */\r
-#define GPIO_PORT_DIR5_DIRP7_Msk (0x01UL << GPIO_PORT_DIR5_DIRP7_Pos) /*!< GPIO_PORT DIR5: DIRP7 Mask */\r
-#define GPIO_PORT_DIR5_DIRP8_Pos 8 /*!< GPIO_PORT DIR5: DIRP8 Position */\r
-#define GPIO_PORT_DIR5_DIRP8_Msk (0x01UL << GPIO_PORT_DIR5_DIRP8_Pos) /*!< GPIO_PORT DIR5: DIRP8 Mask */\r
-#define GPIO_PORT_DIR5_DIRP9_Pos 9 /*!< GPIO_PORT DIR5: DIRP9 Position */\r
-#define GPIO_PORT_DIR5_DIRP9_Msk (0x01UL << GPIO_PORT_DIR5_DIRP9_Pos) /*!< GPIO_PORT DIR5: DIRP9 Mask */\r
-#define GPIO_PORT_DIR5_DIRP10_Pos 10 /*!< GPIO_PORT DIR5: DIRP10 Position */\r
-#define GPIO_PORT_DIR5_DIRP10_Msk (0x01UL << GPIO_PORT_DIR5_DIRP10_Pos) /*!< GPIO_PORT DIR5: DIRP10 Mask */\r
-#define GPIO_PORT_DIR5_DIRP11_Pos 11 /*!< GPIO_PORT DIR5: DIRP11 Position */\r
-#define GPIO_PORT_DIR5_DIRP11_Msk (0x01UL << GPIO_PORT_DIR5_DIRP11_Pos) /*!< GPIO_PORT DIR5: DIRP11 Mask */\r
-#define GPIO_PORT_DIR5_DIRP12_Pos 12 /*!< GPIO_PORT DIR5: DIRP12 Position */\r
-#define GPIO_PORT_DIR5_DIRP12_Msk (0x01UL << GPIO_PORT_DIR5_DIRP12_Pos) /*!< GPIO_PORT DIR5: DIRP12 Mask */\r
-#define GPIO_PORT_DIR5_DIRP13_Pos 13 /*!< GPIO_PORT DIR5: DIRP13 Position */\r
-#define GPIO_PORT_DIR5_DIRP13_Msk (0x01UL << GPIO_PORT_DIR5_DIRP13_Pos) /*!< GPIO_PORT DIR5: DIRP13 Mask */\r
-#define GPIO_PORT_DIR5_DIRP14_Pos 14 /*!< GPIO_PORT DIR5: DIRP14 Position */\r
-#define GPIO_PORT_DIR5_DIRP14_Msk (0x01UL << GPIO_PORT_DIR5_DIRP14_Pos) /*!< GPIO_PORT DIR5: DIRP14 Mask */\r
-#define GPIO_PORT_DIR5_DIRP15_Pos 15 /*!< GPIO_PORT DIR5: DIRP15 Position */\r
-#define GPIO_PORT_DIR5_DIRP15_Msk (0x01UL << GPIO_PORT_DIR5_DIRP15_Pos) /*!< GPIO_PORT DIR5: DIRP15 Mask */\r
-#define GPIO_PORT_DIR5_DIRP16_Pos 16 /*!< GPIO_PORT DIR5: DIRP16 Position */\r
-#define GPIO_PORT_DIR5_DIRP16_Msk (0x01UL << GPIO_PORT_DIR5_DIRP16_Pos) /*!< GPIO_PORT DIR5: DIRP16 Mask */\r
-#define GPIO_PORT_DIR5_DIRP17_Pos 17 /*!< GPIO_PORT DIR5: DIRP17 Position */\r
-#define GPIO_PORT_DIR5_DIRP17_Msk (0x01UL << GPIO_PORT_DIR5_DIRP17_Pos) /*!< GPIO_PORT DIR5: DIRP17 Mask */\r
-#define GPIO_PORT_DIR5_DIRP18_Pos 18 /*!< GPIO_PORT DIR5: DIRP18 Position */\r
-#define GPIO_PORT_DIR5_DIRP18_Msk (0x01UL << GPIO_PORT_DIR5_DIRP18_Pos) /*!< GPIO_PORT DIR5: DIRP18 Mask */\r
-#define GPIO_PORT_DIR5_DIRP19_Pos 19 /*!< GPIO_PORT DIR5: DIRP19 Position */\r
-#define GPIO_PORT_DIR5_DIRP19_Msk (0x01UL << GPIO_PORT_DIR5_DIRP19_Pos) /*!< GPIO_PORT DIR5: DIRP19 Mask */\r
-#define GPIO_PORT_DIR5_DIRP20_Pos 20 /*!< GPIO_PORT DIR5: DIRP20 Position */\r
-#define GPIO_PORT_DIR5_DIRP20_Msk (0x01UL << GPIO_PORT_DIR5_DIRP20_Pos) /*!< GPIO_PORT DIR5: DIRP20 Mask */\r
-#define GPIO_PORT_DIR5_DIRP21_Pos 21 /*!< GPIO_PORT DIR5: DIRP21 Position */\r
-#define GPIO_PORT_DIR5_DIRP21_Msk (0x01UL << GPIO_PORT_DIR5_DIRP21_Pos) /*!< GPIO_PORT DIR5: DIRP21 Mask */\r
-#define GPIO_PORT_DIR5_DIRP22_Pos 22 /*!< GPIO_PORT DIR5: DIRP22 Position */\r
-#define GPIO_PORT_DIR5_DIRP22_Msk (0x01UL << GPIO_PORT_DIR5_DIRP22_Pos) /*!< GPIO_PORT DIR5: DIRP22 Mask */\r
-#define GPIO_PORT_DIR5_DIRP23_Pos 23 /*!< GPIO_PORT DIR5: DIRP23 Position */\r
-#define GPIO_PORT_DIR5_DIRP23_Msk (0x01UL << GPIO_PORT_DIR5_DIRP23_Pos) /*!< GPIO_PORT DIR5: DIRP23 Mask */\r
-#define GPIO_PORT_DIR5_DIRP24_Pos 24 /*!< GPIO_PORT DIR5: DIRP24 Position */\r
-#define GPIO_PORT_DIR5_DIRP24_Msk (0x01UL << GPIO_PORT_DIR5_DIRP24_Pos) /*!< GPIO_PORT DIR5: DIRP24 Mask */\r
-#define GPIO_PORT_DIR5_DIRP25_Pos 25 /*!< GPIO_PORT DIR5: DIRP25 Position */\r
-#define GPIO_PORT_DIR5_DIRP25_Msk (0x01UL << GPIO_PORT_DIR5_DIRP25_Pos) /*!< GPIO_PORT DIR5: DIRP25 Mask */\r
-#define GPIO_PORT_DIR5_DIRP26_Pos 26 /*!< GPIO_PORT DIR5: DIRP26 Position */\r
-#define GPIO_PORT_DIR5_DIRP26_Msk (0x01UL << GPIO_PORT_DIR5_DIRP26_Pos) /*!< GPIO_PORT DIR5: DIRP26 Mask */\r
-#define GPIO_PORT_DIR5_DIRP27_Pos 27 /*!< GPIO_PORT DIR5: DIRP27 Position */\r
-#define GPIO_PORT_DIR5_DIRP27_Msk (0x01UL << GPIO_PORT_DIR5_DIRP27_Pos) /*!< GPIO_PORT DIR5: DIRP27 Mask */\r
-#define GPIO_PORT_DIR5_DIRP28_Pos 28 /*!< GPIO_PORT DIR5: DIRP28 Position */\r
-#define GPIO_PORT_DIR5_DIRP28_Msk (0x01UL << GPIO_PORT_DIR5_DIRP28_Pos) /*!< GPIO_PORT DIR5: DIRP28 Mask */\r
-#define GPIO_PORT_DIR5_DIRP29_Pos 29 /*!< GPIO_PORT DIR5: DIRP29 Position */\r
-#define GPIO_PORT_DIR5_DIRP29_Msk (0x01UL << GPIO_PORT_DIR5_DIRP29_Pos) /*!< GPIO_PORT DIR5: DIRP29 Mask */\r
-#define GPIO_PORT_DIR5_DIRP30_Pos 30 /*!< GPIO_PORT DIR5: DIRP30 Position */\r
-#define GPIO_PORT_DIR5_DIRP30_Msk (0x01UL << GPIO_PORT_DIR5_DIRP30_Pos) /*!< GPIO_PORT DIR5: DIRP30 Mask */\r
-#define GPIO_PORT_DIR5_DIRP31_Pos 31 /*!< GPIO_PORT DIR5: DIRP31 Position */\r
-#define GPIO_PORT_DIR5_DIRP31_Msk (0x01UL << GPIO_PORT_DIR5_DIRP31_Pos) /*!< GPIO_PORT DIR5: DIRP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_DIR6 -----------------------------------------\r
-#define GPIO_PORT_DIR6_DIRP0_Pos 0 /*!< GPIO_PORT DIR6: DIRP0 Position */\r
-#define GPIO_PORT_DIR6_DIRP0_Msk (0x01UL << GPIO_PORT_DIR6_DIRP0_Pos) /*!< GPIO_PORT DIR6: DIRP0 Mask */\r
-#define GPIO_PORT_DIR6_DIRP1_Pos 1 /*!< GPIO_PORT DIR6: DIRP1 Position */\r
-#define GPIO_PORT_DIR6_DIRP1_Msk (0x01UL << GPIO_PORT_DIR6_DIRP1_Pos) /*!< GPIO_PORT DIR6: DIRP1 Mask */\r
-#define GPIO_PORT_DIR6_DIRP2_Pos 2 /*!< GPIO_PORT DIR6: DIRP2 Position */\r
-#define GPIO_PORT_DIR6_DIRP2_Msk (0x01UL << GPIO_PORT_DIR6_DIRP2_Pos) /*!< GPIO_PORT DIR6: DIRP2 Mask */\r
-#define GPIO_PORT_DIR6_DIRP3_Pos 3 /*!< GPIO_PORT DIR6: DIRP3 Position */\r
-#define GPIO_PORT_DIR6_DIRP3_Msk (0x01UL << GPIO_PORT_DIR6_DIRP3_Pos) /*!< GPIO_PORT DIR6: DIRP3 Mask */\r
-#define GPIO_PORT_DIR6_DIRP4_Pos 4 /*!< GPIO_PORT DIR6: DIRP4 Position */\r
-#define GPIO_PORT_DIR6_DIRP4_Msk (0x01UL << GPIO_PORT_DIR6_DIRP4_Pos) /*!< GPIO_PORT DIR6: DIRP4 Mask */\r
-#define GPIO_PORT_DIR6_DIRP5_Pos 5 /*!< GPIO_PORT DIR6: DIRP5 Position */\r
-#define GPIO_PORT_DIR6_DIRP5_Msk (0x01UL << GPIO_PORT_DIR6_DIRP5_Pos) /*!< GPIO_PORT DIR6: DIRP5 Mask */\r
-#define GPIO_PORT_DIR6_DIRP6_Pos 6 /*!< GPIO_PORT DIR6: DIRP6 Position */\r
-#define GPIO_PORT_DIR6_DIRP6_Msk (0x01UL << GPIO_PORT_DIR6_DIRP6_Pos) /*!< GPIO_PORT DIR6: DIRP6 Mask */\r
-#define GPIO_PORT_DIR6_DIRP7_Pos 7 /*!< GPIO_PORT DIR6: DIRP7 Position */\r
-#define GPIO_PORT_DIR6_DIRP7_Msk (0x01UL << GPIO_PORT_DIR6_DIRP7_Pos) /*!< GPIO_PORT DIR6: DIRP7 Mask */\r
-#define GPIO_PORT_DIR6_DIRP8_Pos 8 /*!< GPIO_PORT DIR6: DIRP8 Position */\r
-#define GPIO_PORT_DIR6_DIRP8_Msk (0x01UL << GPIO_PORT_DIR6_DIRP8_Pos) /*!< GPIO_PORT DIR6: DIRP8 Mask */\r
-#define GPIO_PORT_DIR6_DIRP9_Pos 9 /*!< GPIO_PORT DIR6: DIRP9 Position */\r
-#define GPIO_PORT_DIR6_DIRP9_Msk (0x01UL << GPIO_PORT_DIR6_DIRP9_Pos) /*!< GPIO_PORT DIR6: DIRP9 Mask */\r
-#define GPIO_PORT_DIR6_DIRP10_Pos 10 /*!< GPIO_PORT DIR6: DIRP10 Position */\r
-#define GPIO_PORT_DIR6_DIRP10_Msk (0x01UL << GPIO_PORT_DIR6_DIRP10_Pos) /*!< GPIO_PORT DIR6: DIRP10 Mask */\r
-#define GPIO_PORT_DIR6_DIRP11_Pos 11 /*!< GPIO_PORT DIR6: DIRP11 Position */\r
-#define GPIO_PORT_DIR6_DIRP11_Msk (0x01UL << GPIO_PORT_DIR6_DIRP11_Pos) /*!< GPIO_PORT DIR6: DIRP11 Mask */\r
-#define GPIO_PORT_DIR6_DIRP12_Pos 12 /*!< GPIO_PORT DIR6: DIRP12 Position */\r
-#define GPIO_PORT_DIR6_DIRP12_Msk (0x01UL << GPIO_PORT_DIR6_DIRP12_Pos) /*!< GPIO_PORT DIR6: DIRP12 Mask */\r
-#define GPIO_PORT_DIR6_DIRP13_Pos 13 /*!< GPIO_PORT DIR6: DIRP13 Position */\r
-#define GPIO_PORT_DIR6_DIRP13_Msk (0x01UL << GPIO_PORT_DIR6_DIRP13_Pos) /*!< GPIO_PORT DIR6: DIRP13 Mask */\r
-#define GPIO_PORT_DIR6_DIRP14_Pos 14 /*!< GPIO_PORT DIR6: DIRP14 Position */\r
-#define GPIO_PORT_DIR6_DIRP14_Msk (0x01UL << GPIO_PORT_DIR6_DIRP14_Pos) /*!< GPIO_PORT DIR6: DIRP14 Mask */\r
-#define GPIO_PORT_DIR6_DIRP15_Pos 15 /*!< GPIO_PORT DIR6: DIRP15 Position */\r
-#define GPIO_PORT_DIR6_DIRP15_Msk (0x01UL << GPIO_PORT_DIR6_DIRP15_Pos) /*!< GPIO_PORT DIR6: DIRP15 Mask */\r
-#define GPIO_PORT_DIR6_DIRP16_Pos 16 /*!< GPIO_PORT DIR6: DIRP16 Position */\r
-#define GPIO_PORT_DIR6_DIRP16_Msk (0x01UL << GPIO_PORT_DIR6_DIRP16_Pos) /*!< GPIO_PORT DIR6: DIRP16 Mask */\r
-#define GPIO_PORT_DIR6_DIRP17_Pos 17 /*!< GPIO_PORT DIR6: DIRP17 Position */\r
-#define GPIO_PORT_DIR6_DIRP17_Msk (0x01UL << GPIO_PORT_DIR6_DIRP17_Pos) /*!< GPIO_PORT DIR6: DIRP17 Mask */\r
-#define GPIO_PORT_DIR6_DIRP18_Pos 18 /*!< GPIO_PORT DIR6: DIRP18 Position */\r
-#define GPIO_PORT_DIR6_DIRP18_Msk (0x01UL << GPIO_PORT_DIR6_DIRP18_Pos) /*!< GPIO_PORT DIR6: DIRP18 Mask */\r
-#define GPIO_PORT_DIR6_DIRP19_Pos 19 /*!< GPIO_PORT DIR6: DIRP19 Position */\r
-#define GPIO_PORT_DIR6_DIRP19_Msk (0x01UL << GPIO_PORT_DIR6_DIRP19_Pos) /*!< GPIO_PORT DIR6: DIRP19 Mask */\r
-#define GPIO_PORT_DIR6_DIRP20_Pos 20 /*!< GPIO_PORT DIR6: DIRP20 Position */\r
-#define GPIO_PORT_DIR6_DIRP20_Msk (0x01UL << GPIO_PORT_DIR6_DIRP20_Pos) /*!< GPIO_PORT DIR6: DIRP20 Mask */\r
-#define GPIO_PORT_DIR6_DIRP21_Pos 21 /*!< GPIO_PORT DIR6: DIRP21 Position */\r
-#define GPIO_PORT_DIR6_DIRP21_Msk (0x01UL << GPIO_PORT_DIR6_DIRP21_Pos) /*!< GPIO_PORT DIR6: DIRP21 Mask */\r
-#define GPIO_PORT_DIR6_DIRP22_Pos 22 /*!< GPIO_PORT DIR6: DIRP22 Position */\r
-#define GPIO_PORT_DIR6_DIRP22_Msk (0x01UL << GPIO_PORT_DIR6_DIRP22_Pos) /*!< GPIO_PORT DIR6: DIRP22 Mask */\r
-#define GPIO_PORT_DIR6_DIRP23_Pos 23 /*!< GPIO_PORT DIR6: DIRP23 Position */\r
-#define GPIO_PORT_DIR6_DIRP23_Msk (0x01UL << GPIO_PORT_DIR6_DIRP23_Pos) /*!< GPIO_PORT DIR6: DIRP23 Mask */\r
-#define GPIO_PORT_DIR6_DIRP24_Pos 24 /*!< GPIO_PORT DIR6: DIRP24 Position */\r
-#define GPIO_PORT_DIR6_DIRP24_Msk (0x01UL << GPIO_PORT_DIR6_DIRP24_Pos) /*!< GPIO_PORT DIR6: DIRP24 Mask */\r
-#define GPIO_PORT_DIR6_DIRP25_Pos 25 /*!< GPIO_PORT DIR6: DIRP25 Position */\r
-#define GPIO_PORT_DIR6_DIRP25_Msk (0x01UL << GPIO_PORT_DIR6_DIRP25_Pos) /*!< GPIO_PORT DIR6: DIRP25 Mask */\r
-#define GPIO_PORT_DIR6_DIRP26_Pos 26 /*!< GPIO_PORT DIR6: DIRP26 Position */\r
-#define GPIO_PORT_DIR6_DIRP26_Msk (0x01UL << GPIO_PORT_DIR6_DIRP26_Pos) /*!< GPIO_PORT DIR6: DIRP26 Mask */\r
-#define GPIO_PORT_DIR6_DIRP27_Pos 27 /*!< GPIO_PORT DIR6: DIRP27 Position */\r
-#define GPIO_PORT_DIR6_DIRP27_Msk (0x01UL << GPIO_PORT_DIR6_DIRP27_Pos) /*!< GPIO_PORT DIR6: DIRP27 Mask */\r
-#define GPIO_PORT_DIR6_DIRP28_Pos 28 /*!< GPIO_PORT DIR6: DIRP28 Position */\r
-#define GPIO_PORT_DIR6_DIRP28_Msk (0x01UL << GPIO_PORT_DIR6_DIRP28_Pos) /*!< GPIO_PORT DIR6: DIRP28 Mask */\r
-#define GPIO_PORT_DIR6_DIRP29_Pos 29 /*!< GPIO_PORT DIR6: DIRP29 Position */\r
-#define GPIO_PORT_DIR6_DIRP29_Msk (0x01UL << GPIO_PORT_DIR6_DIRP29_Pos) /*!< GPIO_PORT DIR6: DIRP29 Mask */\r
-#define GPIO_PORT_DIR6_DIRP30_Pos 30 /*!< GPIO_PORT DIR6: DIRP30 Position */\r
-#define GPIO_PORT_DIR6_DIRP30_Msk (0x01UL << GPIO_PORT_DIR6_DIRP30_Pos) /*!< GPIO_PORT DIR6: DIRP30 Mask */\r
-#define GPIO_PORT_DIR6_DIRP31_Pos 31 /*!< GPIO_PORT DIR6: DIRP31 Position */\r
-#define GPIO_PORT_DIR6_DIRP31_Msk (0x01UL << GPIO_PORT_DIR6_DIRP31_Pos) /*!< GPIO_PORT DIR6: DIRP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_DIR7 -----------------------------------------\r
-#define GPIO_PORT_DIR7_DIRP0_Pos 0 /*!< GPIO_PORT DIR7: DIRP0 Position */\r
-#define GPIO_PORT_DIR7_DIRP0_Msk (0x01UL << GPIO_PORT_DIR7_DIRP0_Pos) /*!< GPIO_PORT DIR7: DIRP0 Mask */\r
-#define GPIO_PORT_DIR7_DIRP1_Pos 1 /*!< GPIO_PORT DIR7: DIRP1 Position */\r
-#define GPIO_PORT_DIR7_DIRP1_Msk (0x01UL << GPIO_PORT_DIR7_DIRP1_Pos) /*!< GPIO_PORT DIR7: DIRP1 Mask */\r
-#define GPIO_PORT_DIR7_DIRP2_Pos 2 /*!< GPIO_PORT DIR7: DIRP2 Position */\r
-#define GPIO_PORT_DIR7_DIRP2_Msk (0x01UL << GPIO_PORT_DIR7_DIRP2_Pos) /*!< GPIO_PORT DIR7: DIRP2 Mask */\r
-#define GPIO_PORT_DIR7_DIRP3_Pos 3 /*!< GPIO_PORT DIR7: DIRP3 Position */\r
-#define GPIO_PORT_DIR7_DIRP3_Msk (0x01UL << GPIO_PORT_DIR7_DIRP3_Pos) /*!< GPIO_PORT DIR7: DIRP3 Mask */\r
-#define GPIO_PORT_DIR7_DIRP4_Pos 4 /*!< GPIO_PORT DIR7: DIRP4 Position */\r
-#define GPIO_PORT_DIR7_DIRP4_Msk (0x01UL << GPIO_PORT_DIR7_DIRP4_Pos) /*!< GPIO_PORT DIR7: DIRP4 Mask */\r
-#define GPIO_PORT_DIR7_DIRP5_Pos 5 /*!< GPIO_PORT DIR7: DIRP5 Position */\r
-#define GPIO_PORT_DIR7_DIRP5_Msk (0x01UL << GPIO_PORT_DIR7_DIRP5_Pos) /*!< GPIO_PORT DIR7: DIRP5 Mask */\r
-#define GPIO_PORT_DIR7_DIRP6_Pos 6 /*!< GPIO_PORT DIR7: DIRP6 Position */\r
-#define GPIO_PORT_DIR7_DIRP6_Msk (0x01UL << GPIO_PORT_DIR7_DIRP6_Pos) /*!< GPIO_PORT DIR7: DIRP6 Mask */\r
-#define GPIO_PORT_DIR7_DIRP7_Pos 7 /*!< GPIO_PORT DIR7: DIRP7 Position */\r
-#define GPIO_PORT_DIR7_DIRP7_Msk (0x01UL << GPIO_PORT_DIR7_DIRP7_Pos) /*!< GPIO_PORT DIR7: DIRP7 Mask */\r
-#define GPIO_PORT_DIR7_DIRP8_Pos 8 /*!< GPIO_PORT DIR7: DIRP8 Position */\r
-#define GPIO_PORT_DIR7_DIRP8_Msk (0x01UL << GPIO_PORT_DIR7_DIRP8_Pos) /*!< GPIO_PORT DIR7: DIRP8 Mask */\r
-#define GPIO_PORT_DIR7_DIRP9_Pos 9 /*!< GPIO_PORT DIR7: DIRP9 Position */\r
-#define GPIO_PORT_DIR7_DIRP9_Msk (0x01UL << GPIO_PORT_DIR7_DIRP9_Pos) /*!< GPIO_PORT DIR7: DIRP9 Mask */\r
-#define GPIO_PORT_DIR7_DIRP10_Pos 10 /*!< GPIO_PORT DIR7: DIRP10 Position */\r
-#define GPIO_PORT_DIR7_DIRP10_Msk (0x01UL << GPIO_PORT_DIR7_DIRP10_Pos) /*!< GPIO_PORT DIR7: DIRP10 Mask */\r
-#define GPIO_PORT_DIR7_DIRP11_Pos 11 /*!< GPIO_PORT DIR7: DIRP11 Position */\r
-#define GPIO_PORT_DIR7_DIRP11_Msk (0x01UL << GPIO_PORT_DIR7_DIRP11_Pos) /*!< GPIO_PORT DIR7: DIRP11 Mask */\r
-#define GPIO_PORT_DIR7_DIRP12_Pos 12 /*!< GPIO_PORT DIR7: DIRP12 Position */\r
-#define GPIO_PORT_DIR7_DIRP12_Msk (0x01UL << GPIO_PORT_DIR7_DIRP12_Pos) /*!< GPIO_PORT DIR7: DIRP12 Mask */\r
-#define GPIO_PORT_DIR7_DIRP13_Pos 13 /*!< GPIO_PORT DIR7: DIRP13 Position */\r
-#define GPIO_PORT_DIR7_DIRP13_Msk (0x01UL << GPIO_PORT_DIR7_DIRP13_Pos) /*!< GPIO_PORT DIR7: DIRP13 Mask */\r
-#define GPIO_PORT_DIR7_DIRP14_Pos 14 /*!< GPIO_PORT DIR7: DIRP14 Position */\r
-#define GPIO_PORT_DIR7_DIRP14_Msk (0x01UL << GPIO_PORT_DIR7_DIRP14_Pos) /*!< GPIO_PORT DIR7: DIRP14 Mask */\r
-#define GPIO_PORT_DIR7_DIRP15_Pos 15 /*!< GPIO_PORT DIR7: DIRP15 Position */\r
-#define GPIO_PORT_DIR7_DIRP15_Msk (0x01UL << GPIO_PORT_DIR7_DIRP15_Pos) /*!< GPIO_PORT DIR7: DIRP15 Mask */\r
-#define GPIO_PORT_DIR7_DIRP16_Pos 16 /*!< GPIO_PORT DIR7: DIRP16 Position */\r
-#define GPIO_PORT_DIR7_DIRP16_Msk (0x01UL << GPIO_PORT_DIR7_DIRP16_Pos) /*!< GPIO_PORT DIR7: DIRP16 Mask */\r
-#define GPIO_PORT_DIR7_DIRP17_Pos 17 /*!< GPIO_PORT DIR7: DIRP17 Position */\r
-#define GPIO_PORT_DIR7_DIRP17_Msk (0x01UL << GPIO_PORT_DIR7_DIRP17_Pos) /*!< GPIO_PORT DIR7: DIRP17 Mask */\r
-#define GPIO_PORT_DIR7_DIRP18_Pos 18 /*!< GPIO_PORT DIR7: DIRP18 Position */\r
-#define GPIO_PORT_DIR7_DIRP18_Msk (0x01UL << GPIO_PORT_DIR7_DIRP18_Pos) /*!< GPIO_PORT DIR7: DIRP18 Mask */\r
-#define GPIO_PORT_DIR7_DIRP19_Pos 19 /*!< GPIO_PORT DIR7: DIRP19 Position */\r
-#define GPIO_PORT_DIR7_DIRP19_Msk (0x01UL << GPIO_PORT_DIR7_DIRP19_Pos) /*!< GPIO_PORT DIR7: DIRP19 Mask */\r
-#define GPIO_PORT_DIR7_DIRP20_Pos 20 /*!< GPIO_PORT DIR7: DIRP20 Position */\r
-#define GPIO_PORT_DIR7_DIRP20_Msk (0x01UL << GPIO_PORT_DIR7_DIRP20_Pos) /*!< GPIO_PORT DIR7: DIRP20 Mask */\r
-#define GPIO_PORT_DIR7_DIRP21_Pos 21 /*!< GPIO_PORT DIR7: DIRP21 Position */\r
-#define GPIO_PORT_DIR7_DIRP21_Msk (0x01UL << GPIO_PORT_DIR7_DIRP21_Pos) /*!< GPIO_PORT DIR7: DIRP21 Mask */\r
-#define GPIO_PORT_DIR7_DIRP22_Pos 22 /*!< GPIO_PORT DIR7: DIRP22 Position */\r
-#define GPIO_PORT_DIR7_DIRP22_Msk (0x01UL << GPIO_PORT_DIR7_DIRP22_Pos) /*!< GPIO_PORT DIR7: DIRP22 Mask */\r
-#define GPIO_PORT_DIR7_DIRP23_Pos 23 /*!< GPIO_PORT DIR7: DIRP23 Position */\r
-#define GPIO_PORT_DIR7_DIRP23_Msk (0x01UL << GPIO_PORT_DIR7_DIRP23_Pos) /*!< GPIO_PORT DIR7: DIRP23 Mask */\r
-#define GPIO_PORT_DIR7_DIRP24_Pos 24 /*!< GPIO_PORT DIR7: DIRP24 Position */\r
-#define GPIO_PORT_DIR7_DIRP24_Msk (0x01UL << GPIO_PORT_DIR7_DIRP24_Pos) /*!< GPIO_PORT DIR7: DIRP24 Mask */\r
-#define GPIO_PORT_DIR7_DIRP25_Pos 25 /*!< GPIO_PORT DIR7: DIRP25 Position */\r
-#define GPIO_PORT_DIR7_DIRP25_Msk (0x01UL << GPIO_PORT_DIR7_DIRP25_Pos) /*!< GPIO_PORT DIR7: DIRP25 Mask */\r
-#define GPIO_PORT_DIR7_DIRP26_Pos 26 /*!< GPIO_PORT DIR7: DIRP26 Position */\r
-#define GPIO_PORT_DIR7_DIRP26_Msk (0x01UL << GPIO_PORT_DIR7_DIRP26_Pos) /*!< GPIO_PORT DIR7: DIRP26 Mask */\r
-#define GPIO_PORT_DIR7_DIRP27_Pos 27 /*!< GPIO_PORT DIR7: DIRP27 Position */\r
-#define GPIO_PORT_DIR7_DIRP27_Msk (0x01UL << GPIO_PORT_DIR7_DIRP27_Pos) /*!< GPIO_PORT DIR7: DIRP27 Mask */\r
-#define GPIO_PORT_DIR7_DIRP28_Pos 28 /*!< GPIO_PORT DIR7: DIRP28 Position */\r
-#define GPIO_PORT_DIR7_DIRP28_Msk (0x01UL << GPIO_PORT_DIR7_DIRP28_Pos) /*!< GPIO_PORT DIR7: DIRP28 Mask */\r
-#define GPIO_PORT_DIR7_DIRP29_Pos 29 /*!< GPIO_PORT DIR7: DIRP29 Position */\r
-#define GPIO_PORT_DIR7_DIRP29_Msk (0x01UL << GPIO_PORT_DIR7_DIRP29_Pos) /*!< GPIO_PORT DIR7: DIRP29 Mask */\r
-#define GPIO_PORT_DIR7_DIRP30_Pos 30 /*!< GPIO_PORT DIR7: DIRP30 Position */\r
-#define GPIO_PORT_DIR7_DIRP30_Msk (0x01UL << GPIO_PORT_DIR7_DIRP30_Pos) /*!< GPIO_PORT DIR7: DIRP30 Mask */\r
-#define GPIO_PORT_DIR7_DIRP31_Pos 31 /*!< GPIO_PORT DIR7: DIRP31 Position */\r
-#define GPIO_PORT_DIR7_DIRP31_Msk (0x01UL << GPIO_PORT_DIR7_DIRP31_Pos) /*!< GPIO_PORT DIR7: DIRP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MASK0 ----------------------------------------\r
-#define GPIO_PORT_MASK0_MASKP0_Pos 0 /*!< GPIO_PORT MASK0: MASKP0 Position */\r
-#define GPIO_PORT_MASK0_MASKP0_Msk (0x01UL << GPIO_PORT_MASK0_MASKP0_Pos) /*!< GPIO_PORT MASK0: MASKP0 Mask */\r
-#define GPIO_PORT_MASK0_MASKP1_Pos 1 /*!< GPIO_PORT MASK0: MASKP1 Position */\r
-#define GPIO_PORT_MASK0_MASKP1_Msk (0x01UL << GPIO_PORT_MASK0_MASKP1_Pos) /*!< GPIO_PORT MASK0: MASKP1 Mask */\r
-#define GPIO_PORT_MASK0_MASKP2_Pos 2 /*!< GPIO_PORT MASK0: MASKP2 Position */\r
-#define GPIO_PORT_MASK0_MASKP2_Msk (0x01UL << GPIO_PORT_MASK0_MASKP2_Pos) /*!< GPIO_PORT MASK0: MASKP2 Mask */\r
-#define GPIO_PORT_MASK0_MASKP3_Pos 3 /*!< GPIO_PORT MASK0: MASKP3 Position */\r
-#define GPIO_PORT_MASK0_MASKP3_Msk (0x01UL << GPIO_PORT_MASK0_MASKP3_Pos) /*!< GPIO_PORT MASK0: MASKP3 Mask */\r
-#define GPIO_PORT_MASK0_MASKP4_Pos 4 /*!< GPIO_PORT MASK0: MASKP4 Position */\r
-#define GPIO_PORT_MASK0_MASKP4_Msk (0x01UL << GPIO_PORT_MASK0_MASKP4_Pos) /*!< GPIO_PORT MASK0: MASKP4 Mask */\r
-#define GPIO_PORT_MASK0_MASKP5_Pos 5 /*!< GPIO_PORT MASK0: MASKP5 Position */\r
-#define GPIO_PORT_MASK0_MASKP5_Msk (0x01UL << GPIO_PORT_MASK0_MASKP5_Pos) /*!< GPIO_PORT MASK0: MASKP5 Mask */\r
-#define GPIO_PORT_MASK0_MASKP6_Pos 6 /*!< GPIO_PORT MASK0: MASKP6 Position */\r
-#define GPIO_PORT_MASK0_MASKP6_Msk (0x01UL << GPIO_PORT_MASK0_MASKP6_Pos) /*!< GPIO_PORT MASK0: MASKP6 Mask */\r
-#define GPIO_PORT_MASK0_MASKP7_Pos 7 /*!< GPIO_PORT MASK0: MASKP7 Position */\r
-#define GPIO_PORT_MASK0_MASKP7_Msk (0x01UL << GPIO_PORT_MASK0_MASKP7_Pos) /*!< GPIO_PORT MASK0: MASKP7 Mask */\r
-#define GPIO_PORT_MASK0_MASKP8_Pos 8 /*!< GPIO_PORT MASK0: MASKP8 Position */\r
-#define GPIO_PORT_MASK0_MASKP8_Msk (0x01UL << GPIO_PORT_MASK0_MASKP8_Pos) /*!< GPIO_PORT MASK0: MASKP8 Mask */\r
-#define GPIO_PORT_MASK0_MASKP9_Pos 9 /*!< GPIO_PORT MASK0: MASKP9 Position */\r
-#define GPIO_PORT_MASK0_MASKP9_Msk (0x01UL << GPIO_PORT_MASK0_MASKP9_Pos) /*!< GPIO_PORT MASK0: MASKP9 Mask */\r
-#define GPIO_PORT_MASK0_MASKP10_Pos 10 /*!< GPIO_PORT MASK0: MASKP10 Position */\r
-#define GPIO_PORT_MASK0_MASKP10_Msk (0x01UL << GPIO_PORT_MASK0_MASKP10_Pos) /*!< GPIO_PORT MASK0: MASKP10 Mask */\r
-#define GPIO_PORT_MASK0_MASKP11_Pos 11 /*!< GPIO_PORT MASK0: MASKP11 Position */\r
-#define GPIO_PORT_MASK0_MASKP11_Msk (0x01UL << GPIO_PORT_MASK0_MASKP11_Pos) /*!< GPIO_PORT MASK0: MASKP11 Mask */\r
-#define GPIO_PORT_MASK0_MASKP12_Pos 12 /*!< GPIO_PORT MASK0: MASKP12 Position */\r
-#define GPIO_PORT_MASK0_MASKP12_Msk (0x01UL << GPIO_PORT_MASK0_MASKP12_Pos) /*!< GPIO_PORT MASK0: MASKP12 Mask */\r
-#define GPIO_PORT_MASK0_MASKP13_Pos 13 /*!< GPIO_PORT MASK0: MASKP13 Position */\r
-#define GPIO_PORT_MASK0_MASKP13_Msk (0x01UL << GPIO_PORT_MASK0_MASKP13_Pos) /*!< GPIO_PORT MASK0: MASKP13 Mask */\r
-#define GPIO_PORT_MASK0_MASKP14_Pos 14 /*!< GPIO_PORT MASK0: MASKP14 Position */\r
-#define GPIO_PORT_MASK0_MASKP14_Msk (0x01UL << GPIO_PORT_MASK0_MASKP14_Pos) /*!< GPIO_PORT MASK0: MASKP14 Mask */\r
-#define GPIO_PORT_MASK0_MASKP15_Pos 15 /*!< GPIO_PORT MASK0: MASKP15 Position */\r
-#define GPIO_PORT_MASK0_MASKP15_Msk (0x01UL << GPIO_PORT_MASK0_MASKP15_Pos) /*!< GPIO_PORT MASK0: MASKP15 Mask */\r
-#define GPIO_PORT_MASK0_MASKP16_Pos 16 /*!< GPIO_PORT MASK0: MASKP16 Position */\r
-#define GPIO_PORT_MASK0_MASKP16_Msk (0x01UL << GPIO_PORT_MASK0_MASKP16_Pos) /*!< GPIO_PORT MASK0: MASKP16 Mask */\r
-#define GPIO_PORT_MASK0_MASKP17_Pos 17 /*!< GPIO_PORT MASK0: MASKP17 Position */\r
-#define GPIO_PORT_MASK0_MASKP17_Msk (0x01UL << GPIO_PORT_MASK0_MASKP17_Pos) /*!< GPIO_PORT MASK0: MASKP17 Mask */\r
-#define GPIO_PORT_MASK0_MASKP18_Pos 18 /*!< GPIO_PORT MASK0: MASKP18 Position */\r
-#define GPIO_PORT_MASK0_MASKP18_Msk (0x01UL << GPIO_PORT_MASK0_MASKP18_Pos) /*!< GPIO_PORT MASK0: MASKP18 Mask */\r
-#define GPIO_PORT_MASK0_MASKP19_Pos 19 /*!< GPIO_PORT MASK0: MASKP19 Position */\r
-#define GPIO_PORT_MASK0_MASKP19_Msk (0x01UL << GPIO_PORT_MASK0_MASKP19_Pos) /*!< GPIO_PORT MASK0: MASKP19 Mask */\r
-#define GPIO_PORT_MASK0_MASKP20_Pos 20 /*!< GPIO_PORT MASK0: MASKP20 Position */\r
-#define GPIO_PORT_MASK0_MASKP20_Msk (0x01UL << GPIO_PORT_MASK0_MASKP20_Pos) /*!< GPIO_PORT MASK0: MASKP20 Mask */\r
-#define GPIO_PORT_MASK0_MASKP21_Pos 21 /*!< GPIO_PORT MASK0: MASKP21 Position */\r
-#define GPIO_PORT_MASK0_MASKP21_Msk (0x01UL << GPIO_PORT_MASK0_MASKP21_Pos) /*!< GPIO_PORT MASK0: MASKP21 Mask */\r
-#define GPIO_PORT_MASK0_MASKP22_Pos 22 /*!< GPIO_PORT MASK0: MASKP22 Position */\r
-#define GPIO_PORT_MASK0_MASKP22_Msk (0x01UL << GPIO_PORT_MASK0_MASKP22_Pos) /*!< GPIO_PORT MASK0: MASKP22 Mask */\r
-#define GPIO_PORT_MASK0_MASKP23_Pos 23 /*!< GPIO_PORT MASK0: MASKP23 Position */\r
-#define GPIO_PORT_MASK0_MASKP23_Msk (0x01UL << GPIO_PORT_MASK0_MASKP23_Pos) /*!< GPIO_PORT MASK0: MASKP23 Mask */\r
-#define GPIO_PORT_MASK0_MASKP24_Pos 24 /*!< GPIO_PORT MASK0: MASKP24 Position */\r
-#define GPIO_PORT_MASK0_MASKP24_Msk (0x01UL << GPIO_PORT_MASK0_MASKP24_Pos) /*!< GPIO_PORT MASK0: MASKP24 Mask */\r
-#define GPIO_PORT_MASK0_MASKP25_Pos 25 /*!< GPIO_PORT MASK0: MASKP25 Position */\r
-#define GPIO_PORT_MASK0_MASKP25_Msk (0x01UL << GPIO_PORT_MASK0_MASKP25_Pos) /*!< GPIO_PORT MASK0: MASKP25 Mask */\r
-#define GPIO_PORT_MASK0_MASKP26_Pos 26 /*!< GPIO_PORT MASK0: MASKP26 Position */\r
-#define GPIO_PORT_MASK0_MASKP26_Msk (0x01UL << GPIO_PORT_MASK0_MASKP26_Pos) /*!< GPIO_PORT MASK0: MASKP26 Mask */\r
-#define GPIO_PORT_MASK0_MASKP27_Pos 27 /*!< GPIO_PORT MASK0: MASKP27 Position */\r
-#define GPIO_PORT_MASK0_MASKP27_Msk (0x01UL << GPIO_PORT_MASK0_MASKP27_Pos) /*!< GPIO_PORT MASK0: MASKP27 Mask */\r
-#define GPIO_PORT_MASK0_MASKP28_Pos 28 /*!< GPIO_PORT MASK0: MASKP28 Position */\r
-#define GPIO_PORT_MASK0_MASKP28_Msk (0x01UL << GPIO_PORT_MASK0_MASKP28_Pos) /*!< GPIO_PORT MASK0: MASKP28 Mask */\r
-#define GPIO_PORT_MASK0_MASKP29_Pos 29 /*!< GPIO_PORT MASK0: MASKP29 Position */\r
-#define GPIO_PORT_MASK0_MASKP29_Msk (0x01UL << GPIO_PORT_MASK0_MASKP29_Pos) /*!< GPIO_PORT MASK0: MASKP29 Mask */\r
-#define GPIO_PORT_MASK0_MASKP30_Pos 30 /*!< GPIO_PORT MASK0: MASKP30 Position */\r
-#define GPIO_PORT_MASK0_MASKP30_Msk (0x01UL << GPIO_PORT_MASK0_MASKP30_Pos) /*!< GPIO_PORT MASK0: MASKP30 Mask */\r
-#define GPIO_PORT_MASK0_MASKP31_Pos 31 /*!< GPIO_PORT MASK0: MASKP31 Position */\r
-#define GPIO_PORT_MASK0_MASKP31_Msk (0x01UL << GPIO_PORT_MASK0_MASKP31_Pos) /*!< GPIO_PORT MASK0: MASKP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MASK1 ----------------------------------------\r
-#define GPIO_PORT_MASK1_MASKP0_Pos 0 /*!< GPIO_PORT MASK1: MASKP0 Position */\r
-#define GPIO_PORT_MASK1_MASKP0_Msk (0x01UL << GPIO_PORT_MASK1_MASKP0_Pos) /*!< GPIO_PORT MASK1: MASKP0 Mask */\r
-#define GPIO_PORT_MASK1_MASKP1_Pos 1 /*!< GPIO_PORT MASK1: MASKP1 Position */\r
-#define GPIO_PORT_MASK1_MASKP1_Msk (0x01UL << GPIO_PORT_MASK1_MASKP1_Pos) /*!< GPIO_PORT MASK1: MASKP1 Mask */\r
-#define GPIO_PORT_MASK1_MASKP2_Pos 2 /*!< GPIO_PORT MASK1: MASKP2 Position */\r
-#define GPIO_PORT_MASK1_MASKP2_Msk (0x01UL << GPIO_PORT_MASK1_MASKP2_Pos) /*!< GPIO_PORT MASK1: MASKP2 Mask */\r
-#define GPIO_PORT_MASK1_MASKP3_Pos 3 /*!< GPIO_PORT MASK1: MASKP3 Position */\r
-#define GPIO_PORT_MASK1_MASKP3_Msk (0x01UL << GPIO_PORT_MASK1_MASKP3_Pos) /*!< GPIO_PORT MASK1: MASKP3 Mask */\r
-#define GPIO_PORT_MASK1_MASKP4_Pos 4 /*!< GPIO_PORT MASK1: MASKP4 Position */\r
-#define GPIO_PORT_MASK1_MASKP4_Msk (0x01UL << GPIO_PORT_MASK1_MASKP4_Pos) /*!< GPIO_PORT MASK1: MASKP4 Mask */\r
-#define GPIO_PORT_MASK1_MASKP5_Pos 5 /*!< GPIO_PORT MASK1: MASKP5 Position */\r
-#define GPIO_PORT_MASK1_MASKP5_Msk (0x01UL << GPIO_PORT_MASK1_MASKP5_Pos) /*!< GPIO_PORT MASK1: MASKP5 Mask */\r
-#define GPIO_PORT_MASK1_MASKP6_Pos 6 /*!< GPIO_PORT MASK1: MASKP6 Position */\r
-#define GPIO_PORT_MASK1_MASKP6_Msk (0x01UL << GPIO_PORT_MASK1_MASKP6_Pos) /*!< GPIO_PORT MASK1: MASKP6 Mask */\r
-#define GPIO_PORT_MASK1_MASKP7_Pos 7 /*!< GPIO_PORT MASK1: MASKP7 Position */\r
-#define GPIO_PORT_MASK1_MASKP7_Msk (0x01UL << GPIO_PORT_MASK1_MASKP7_Pos) /*!< GPIO_PORT MASK1: MASKP7 Mask */\r
-#define GPIO_PORT_MASK1_MASKP8_Pos 8 /*!< GPIO_PORT MASK1: MASKP8 Position */\r
-#define GPIO_PORT_MASK1_MASKP8_Msk (0x01UL << GPIO_PORT_MASK1_MASKP8_Pos) /*!< GPIO_PORT MASK1: MASKP8 Mask */\r
-#define GPIO_PORT_MASK1_MASKP9_Pos 9 /*!< GPIO_PORT MASK1: MASKP9 Position */\r
-#define GPIO_PORT_MASK1_MASKP9_Msk (0x01UL << GPIO_PORT_MASK1_MASKP9_Pos) /*!< GPIO_PORT MASK1: MASKP9 Mask */\r
-#define GPIO_PORT_MASK1_MASKP10_Pos 10 /*!< GPIO_PORT MASK1: MASKP10 Position */\r
-#define GPIO_PORT_MASK1_MASKP10_Msk (0x01UL << GPIO_PORT_MASK1_MASKP10_Pos) /*!< GPIO_PORT MASK1: MASKP10 Mask */\r
-#define GPIO_PORT_MASK1_MASKP11_Pos 11 /*!< GPIO_PORT MASK1: MASKP11 Position */\r
-#define GPIO_PORT_MASK1_MASKP11_Msk (0x01UL << GPIO_PORT_MASK1_MASKP11_Pos) /*!< GPIO_PORT MASK1: MASKP11 Mask */\r
-#define GPIO_PORT_MASK1_MASKP12_Pos 12 /*!< GPIO_PORT MASK1: MASKP12 Position */\r
-#define GPIO_PORT_MASK1_MASKP12_Msk (0x01UL << GPIO_PORT_MASK1_MASKP12_Pos) /*!< GPIO_PORT MASK1: MASKP12 Mask */\r
-#define GPIO_PORT_MASK1_MASKP13_Pos 13 /*!< GPIO_PORT MASK1: MASKP13 Position */\r
-#define GPIO_PORT_MASK1_MASKP13_Msk (0x01UL << GPIO_PORT_MASK1_MASKP13_Pos) /*!< GPIO_PORT MASK1: MASKP13 Mask */\r
-#define GPIO_PORT_MASK1_MASKP14_Pos 14 /*!< GPIO_PORT MASK1: MASKP14 Position */\r
-#define GPIO_PORT_MASK1_MASKP14_Msk (0x01UL << GPIO_PORT_MASK1_MASKP14_Pos) /*!< GPIO_PORT MASK1: MASKP14 Mask */\r
-#define GPIO_PORT_MASK1_MASKP15_Pos 15 /*!< GPIO_PORT MASK1: MASKP15 Position */\r
-#define GPIO_PORT_MASK1_MASKP15_Msk (0x01UL << GPIO_PORT_MASK1_MASKP15_Pos) /*!< GPIO_PORT MASK1: MASKP15 Mask */\r
-#define GPIO_PORT_MASK1_MASKP16_Pos 16 /*!< GPIO_PORT MASK1: MASKP16 Position */\r
-#define GPIO_PORT_MASK1_MASKP16_Msk (0x01UL << GPIO_PORT_MASK1_MASKP16_Pos) /*!< GPIO_PORT MASK1: MASKP16 Mask */\r
-#define GPIO_PORT_MASK1_MASKP17_Pos 17 /*!< GPIO_PORT MASK1: MASKP17 Position */\r
-#define GPIO_PORT_MASK1_MASKP17_Msk (0x01UL << GPIO_PORT_MASK1_MASKP17_Pos) /*!< GPIO_PORT MASK1: MASKP17 Mask */\r
-#define GPIO_PORT_MASK1_MASKP18_Pos 18 /*!< GPIO_PORT MASK1: MASKP18 Position */\r
-#define GPIO_PORT_MASK1_MASKP18_Msk (0x01UL << GPIO_PORT_MASK1_MASKP18_Pos) /*!< GPIO_PORT MASK1: MASKP18 Mask */\r
-#define GPIO_PORT_MASK1_MASKP19_Pos 19 /*!< GPIO_PORT MASK1: MASKP19 Position */\r
-#define GPIO_PORT_MASK1_MASKP19_Msk (0x01UL << GPIO_PORT_MASK1_MASKP19_Pos) /*!< GPIO_PORT MASK1: MASKP19 Mask */\r
-#define GPIO_PORT_MASK1_MASKP20_Pos 20 /*!< GPIO_PORT MASK1: MASKP20 Position */\r
-#define GPIO_PORT_MASK1_MASKP20_Msk (0x01UL << GPIO_PORT_MASK1_MASKP20_Pos) /*!< GPIO_PORT MASK1: MASKP20 Mask */\r
-#define GPIO_PORT_MASK1_MASKP21_Pos 21 /*!< GPIO_PORT MASK1: MASKP21 Position */\r
-#define GPIO_PORT_MASK1_MASKP21_Msk (0x01UL << GPIO_PORT_MASK1_MASKP21_Pos) /*!< GPIO_PORT MASK1: MASKP21 Mask */\r
-#define GPIO_PORT_MASK1_MASKP22_Pos 22 /*!< GPIO_PORT MASK1: MASKP22 Position */\r
-#define GPIO_PORT_MASK1_MASKP22_Msk (0x01UL << GPIO_PORT_MASK1_MASKP22_Pos) /*!< GPIO_PORT MASK1: MASKP22 Mask */\r
-#define GPIO_PORT_MASK1_MASKP23_Pos 23 /*!< GPIO_PORT MASK1: MASKP23 Position */\r
-#define GPIO_PORT_MASK1_MASKP23_Msk (0x01UL << GPIO_PORT_MASK1_MASKP23_Pos) /*!< GPIO_PORT MASK1: MASKP23 Mask */\r
-#define GPIO_PORT_MASK1_MASKP24_Pos 24 /*!< GPIO_PORT MASK1: MASKP24 Position */\r
-#define GPIO_PORT_MASK1_MASKP24_Msk (0x01UL << GPIO_PORT_MASK1_MASKP24_Pos) /*!< GPIO_PORT MASK1: MASKP24 Mask */\r
-#define GPIO_PORT_MASK1_MASKP25_Pos 25 /*!< GPIO_PORT MASK1: MASKP25 Position */\r
-#define GPIO_PORT_MASK1_MASKP25_Msk (0x01UL << GPIO_PORT_MASK1_MASKP25_Pos) /*!< GPIO_PORT MASK1: MASKP25 Mask */\r
-#define GPIO_PORT_MASK1_MASKP26_Pos 26 /*!< GPIO_PORT MASK1: MASKP26 Position */\r
-#define GPIO_PORT_MASK1_MASKP26_Msk (0x01UL << GPIO_PORT_MASK1_MASKP26_Pos) /*!< GPIO_PORT MASK1: MASKP26 Mask */\r
-#define GPIO_PORT_MASK1_MASKP27_Pos 27 /*!< GPIO_PORT MASK1: MASKP27 Position */\r
-#define GPIO_PORT_MASK1_MASKP27_Msk (0x01UL << GPIO_PORT_MASK1_MASKP27_Pos) /*!< GPIO_PORT MASK1: MASKP27 Mask */\r
-#define GPIO_PORT_MASK1_MASKP28_Pos 28 /*!< GPIO_PORT MASK1: MASKP28 Position */\r
-#define GPIO_PORT_MASK1_MASKP28_Msk (0x01UL << GPIO_PORT_MASK1_MASKP28_Pos) /*!< GPIO_PORT MASK1: MASKP28 Mask */\r
-#define GPIO_PORT_MASK1_MASKP29_Pos 29 /*!< GPIO_PORT MASK1: MASKP29 Position */\r
-#define GPIO_PORT_MASK1_MASKP29_Msk (0x01UL << GPIO_PORT_MASK1_MASKP29_Pos) /*!< GPIO_PORT MASK1: MASKP29 Mask */\r
-#define GPIO_PORT_MASK1_MASKP30_Pos 30 /*!< GPIO_PORT MASK1: MASKP30 Position */\r
-#define GPIO_PORT_MASK1_MASKP30_Msk (0x01UL << GPIO_PORT_MASK1_MASKP30_Pos) /*!< GPIO_PORT MASK1: MASKP30 Mask */\r
-#define GPIO_PORT_MASK1_MASKP31_Pos 31 /*!< GPIO_PORT MASK1: MASKP31 Position */\r
-#define GPIO_PORT_MASK1_MASKP31_Msk (0x01UL << GPIO_PORT_MASK1_MASKP31_Pos) /*!< GPIO_PORT MASK1: MASKP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MASK2 ----------------------------------------\r
-#define GPIO_PORT_MASK2_MASKP0_Pos 0 /*!< GPIO_PORT MASK2: MASKP0 Position */\r
-#define GPIO_PORT_MASK2_MASKP0_Msk (0x01UL << GPIO_PORT_MASK2_MASKP0_Pos) /*!< GPIO_PORT MASK2: MASKP0 Mask */\r
-#define GPIO_PORT_MASK2_MASKP1_Pos 1 /*!< GPIO_PORT MASK2: MASKP1 Position */\r
-#define GPIO_PORT_MASK2_MASKP1_Msk (0x01UL << GPIO_PORT_MASK2_MASKP1_Pos) /*!< GPIO_PORT MASK2: MASKP1 Mask */\r
-#define GPIO_PORT_MASK2_MASKP2_Pos 2 /*!< GPIO_PORT MASK2: MASKP2 Position */\r
-#define GPIO_PORT_MASK2_MASKP2_Msk (0x01UL << GPIO_PORT_MASK2_MASKP2_Pos) /*!< GPIO_PORT MASK2: MASKP2 Mask */\r
-#define GPIO_PORT_MASK2_MASKP3_Pos 3 /*!< GPIO_PORT MASK2: MASKP3 Position */\r
-#define GPIO_PORT_MASK2_MASKP3_Msk (0x01UL << GPIO_PORT_MASK2_MASKP3_Pos) /*!< GPIO_PORT MASK2: MASKP3 Mask */\r
-#define GPIO_PORT_MASK2_MASKP4_Pos 4 /*!< GPIO_PORT MASK2: MASKP4 Position */\r
-#define GPIO_PORT_MASK2_MASKP4_Msk (0x01UL << GPIO_PORT_MASK2_MASKP4_Pos) /*!< GPIO_PORT MASK2: MASKP4 Mask */\r
-#define GPIO_PORT_MASK2_MASKP5_Pos 5 /*!< GPIO_PORT MASK2: MASKP5 Position */\r
-#define GPIO_PORT_MASK2_MASKP5_Msk (0x01UL << GPIO_PORT_MASK2_MASKP5_Pos) /*!< GPIO_PORT MASK2: MASKP5 Mask */\r
-#define GPIO_PORT_MASK2_MASKP6_Pos 6 /*!< GPIO_PORT MASK2: MASKP6 Position */\r
-#define GPIO_PORT_MASK2_MASKP6_Msk (0x01UL << GPIO_PORT_MASK2_MASKP6_Pos) /*!< GPIO_PORT MASK2: MASKP6 Mask */\r
-#define GPIO_PORT_MASK2_MASKP7_Pos 7 /*!< GPIO_PORT MASK2: MASKP7 Position */\r
-#define GPIO_PORT_MASK2_MASKP7_Msk (0x01UL << GPIO_PORT_MASK2_MASKP7_Pos) /*!< GPIO_PORT MASK2: MASKP7 Mask */\r
-#define GPIO_PORT_MASK2_MASKP8_Pos 8 /*!< GPIO_PORT MASK2: MASKP8 Position */\r
-#define GPIO_PORT_MASK2_MASKP8_Msk (0x01UL << GPIO_PORT_MASK2_MASKP8_Pos) /*!< GPIO_PORT MASK2: MASKP8 Mask */\r
-#define GPIO_PORT_MASK2_MASKP9_Pos 9 /*!< GPIO_PORT MASK2: MASKP9 Position */\r
-#define GPIO_PORT_MASK2_MASKP9_Msk (0x01UL << GPIO_PORT_MASK2_MASKP9_Pos) /*!< GPIO_PORT MASK2: MASKP9 Mask */\r
-#define GPIO_PORT_MASK2_MASKP10_Pos 10 /*!< GPIO_PORT MASK2: MASKP10 Position */\r
-#define GPIO_PORT_MASK2_MASKP10_Msk (0x01UL << GPIO_PORT_MASK2_MASKP10_Pos) /*!< GPIO_PORT MASK2: MASKP10 Mask */\r
-#define GPIO_PORT_MASK2_MASKP11_Pos 11 /*!< GPIO_PORT MASK2: MASKP11 Position */\r
-#define GPIO_PORT_MASK2_MASKP11_Msk (0x01UL << GPIO_PORT_MASK2_MASKP11_Pos) /*!< GPIO_PORT MASK2: MASKP11 Mask */\r
-#define GPIO_PORT_MASK2_MASKP12_Pos 12 /*!< GPIO_PORT MASK2: MASKP12 Position */\r
-#define GPIO_PORT_MASK2_MASKP12_Msk (0x01UL << GPIO_PORT_MASK2_MASKP12_Pos) /*!< GPIO_PORT MASK2: MASKP12 Mask */\r
-#define GPIO_PORT_MASK2_MASKP13_Pos 13 /*!< GPIO_PORT MASK2: MASKP13 Position */\r
-#define GPIO_PORT_MASK2_MASKP13_Msk (0x01UL << GPIO_PORT_MASK2_MASKP13_Pos) /*!< GPIO_PORT MASK2: MASKP13 Mask */\r
-#define GPIO_PORT_MASK2_MASKP14_Pos 14 /*!< GPIO_PORT MASK2: MASKP14 Position */\r
-#define GPIO_PORT_MASK2_MASKP14_Msk (0x01UL << GPIO_PORT_MASK2_MASKP14_Pos) /*!< GPIO_PORT MASK2: MASKP14 Mask */\r
-#define GPIO_PORT_MASK2_MASKP15_Pos 15 /*!< GPIO_PORT MASK2: MASKP15 Position */\r
-#define GPIO_PORT_MASK2_MASKP15_Msk (0x01UL << GPIO_PORT_MASK2_MASKP15_Pos) /*!< GPIO_PORT MASK2: MASKP15 Mask */\r
-#define GPIO_PORT_MASK2_MASKP16_Pos 16 /*!< GPIO_PORT MASK2: MASKP16 Position */\r
-#define GPIO_PORT_MASK2_MASKP16_Msk (0x01UL << GPIO_PORT_MASK2_MASKP16_Pos) /*!< GPIO_PORT MASK2: MASKP16 Mask */\r
-#define GPIO_PORT_MASK2_MASKP17_Pos 17 /*!< GPIO_PORT MASK2: MASKP17 Position */\r
-#define GPIO_PORT_MASK2_MASKP17_Msk (0x01UL << GPIO_PORT_MASK2_MASKP17_Pos) /*!< GPIO_PORT MASK2: MASKP17 Mask */\r
-#define GPIO_PORT_MASK2_MASKP18_Pos 18 /*!< GPIO_PORT MASK2: MASKP18 Position */\r
-#define GPIO_PORT_MASK2_MASKP18_Msk (0x01UL << GPIO_PORT_MASK2_MASKP18_Pos) /*!< GPIO_PORT MASK2: MASKP18 Mask */\r
-#define GPIO_PORT_MASK2_MASKP19_Pos 19 /*!< GPIO_PORT MASK2: MASKP19 Position */\r
-#define GPIO_PORT_MASK2_MASKP19_Msk (0x01UL << GPIO_PORT_MASK2_MASKP19_Pos) /*!< GPIO_PORT MASK2: MASKP19 Mask */\r
-#define GPIO_PORT_MASK2_MASKP20_Pos 20 /*!< GPIO_PORT MASK2: MASKP20 Position */\r
-#define GPIO_PORT_MASK2_MASKP20_Msk (0x01UL << GPIO_PORT_MASK2_MASKP20_Pos) /*!< GPIO_PORT MASK2: MASKP20 Mask */\r
-#define GPIO_PORT_MASK2_MASKP21_Pos 21 /*!< GPIO_PORT MASK2: MASKP21 Position */\r
-#define GPIO_PORT_MASK2_MASKP21_Msk (0x01UL << GPIO_PORT_MASK2_MASKP21_Pos) /*!< GPIO_PORT MASK2: MASKP21 Mask */\r
-#define GPIO_PORT_MASK2_MASKP22_Pos 22 /*!< GPIO_PORT MASK2: MASKP22 Position */\r
-#define GPIO_PORT_MASK2_MASKP22_Msk (0x01UL << GPIO_PORT_MASK2_MASKP22_Pos) /*!< GPIO_PORT MASK2: MASKP22 Mask */\r
-#define GPIO_PORT_MASK2_MASKP23_Pos 23 /*!< GPIO_PORT MASK2: MASKP23 Position */\r
-#define GPIO_PORT_MASK2_MASKP23_Msk (0x01UL << GPIO_PORT_MASK2_MASKP23_Pos) /*!< GPIO_PORT MASK2: MASKP23 Mask */\r
-#define GPIO_PORT_MASK2_MASKP24_Pos 24 /*!< GPIO_PORT MASK2: MASKP24 Position */\r
-#define GPIO_PORT_MASK2_MASKP24_Msk (0x01UL << GPIO_PORT_MASK2_MASKP24_Pos) /*!< GPIO_PORT MASK2: MASKP24 Mask */\r
-#define GPIO_PORT_MASK2_MASKP25_Pos 25 /*!< GPIO_PORT MASK2: MASKP25 Position */\r
-#define GPIO_PORT_MASK2_MASKP25_Msk (0x01UL << GPIO_PORT_MASK2_MASKP25_Pos) /*!< GPIO_PORT MASK2: MASKP25 Mask */\r
-#define GPIO_PORT_MASK2_MASKP26_Pos 26 /*!< GPIO_PORT MASK2: MASKP26 Position */\r
-#define GPIO_PORT_MASK2_MASKP26_Msk (0x01UL << GPIO_PORT_MASK2_MASKP26_Pos) /*!< GPIO_PORT MASK2: MASKP26 Mask */\r
-#define GPIO_PORT_MASK2_MASKP27_Pos 27 /*!< GPIO_PORT MASK2: MASKP27 Position */\r
-#define GPIO_PORT_MASK2_MASKP27_Msk (0x01UL << GPIO_PORT_MASK2_MASKP27_Pos) /*!< GPIO_PORT MASK2: MASKP27 Mask */\r
-#define GPIO_PORT_MASK2_MASKP28_Pos 28 /*!< GPIO_PORT MASK2: MASKP28 Position */\r
-#define GPIO_PORT_MASK2_MASKP28_Msk (0x01UL << GPIO_PORT_MASK2_MASKP28_Pos) /*!< GPIO_PORT MASK2: MASKP28 Mask */\r
-#define GPIO_PORT_MASK2_MASKP29_Pos 29 /*!< GPIO_PORT MASK2: MASKP29 Position */\r
-#define GPIO_PORT_MASK2_MASKP29_Msk (0x01UL << GPIO_PORT_MASK2_MASKP29_Pos) /*!< GPIO_PORT MASK2: MASKP29 Mask */\r
-#define GPIO_PORT_MASK2_MASKP30_Pos 30 /*!< GPIO_PORT MASK2: MASKP30 Position */\r
-#define GPIO_PORT_MASK2_MASKP30_Msk (0x01UL << GPIO_PORT_MASK2_MASKP30_Pos) /*!< GPIO_PORT MASK2: MASKP30 Mask */\r
-#define GPIO_PORT_MASK2_MASKP31_Pos 31 /*!< GPIO_PORT MASK2: MASKP31 Position */\r
-#define GPIO_PORT_MASK2_MASKP31_Msk (0x01UL << GPIO_PORT_MASK2_MASKP31_Pos) /*!< GPIO_PORT MASK2: MASKP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MASK3 ----------------------------------------\r
-#define GPIO_PORT_MASK3_MASKP0_Pos 0 /*!< GPIO_PORT MASK3: MASKP0 Position */\r
-#define GPIO_PORT_MASK3_MASKP0_Msk (0x01UL << GPIO_PORT_MASK3_MASKP0_Pos) /*!< GPIO_PORT MASK3: MASKP0 Mask */\r
-#define GPIO_PORT_MASK3_MASKP1_Pos 1 /*!< GPIO_PORT MASK3: MASKP1 Position */\r
-#define GPIO_PORT_MASK3_MASKP1_Msk (0x01UL << GPIO_PORT_MASK3_MASKP1_Pos) /*!< GPIO_PORT MASK3: MASKP1 Mask */\r
-#define GPIO_PORT_MASK3_MASKP2_Pos 2 /*!< GPIO_PORT MASK3: MASKP2 Position */\r
-#define GPIO_PORT_MASK3_MASKP2_Msk (0x01UL << GPIO_PORT_MASK3_MASKP2_Pos) /*!< GPIO_PORT MASK3: MASKP2 Mask */\r
-#define GPIO_PORT_MASK3_MASKP3_Pos 3 /*!< GPIO_PORT MASK3: MASKP3 Position */\r
-#define GPIO_PORT_MASK3_MASKP3_Msk (0x01UL << GPIO_PORT_MASK3_MASKP3_Pos) /*!< GPIO_PORT MASK3: MASKP3 Mask */\r
-#define GPIO_PORT_MASK3_MASKP4_Pos 4 /*!< GPIO_PORT MASK3: MASKP4 Position */\r
-#define GPIO_PORT_MASK3_MASKP4_Msk (0x01UL << GPIO_PORT_MASK3_MASKP4_Pos) /*!< GPIO_PORT MASK3: MASKP4 Mask */\r
-#define GPIO_PORT_MASK3_MASKP5_Pos 5 /*!< GPIO_PORT MASK3: MASKP5 Position */\r
-#define GPIO_PORT_MASK3_MASKP5_Msk (0x01UL << GPIO_PORT_MASK3_MASKP5_Pos) /*!< GPIO_PORT MASK3: MASKP5 Mask */\r
-#define GPIO_PORT_MASK3_MASKP6_Pos 6 /*!< GPIO_PORT MASK3: MASKP6 Position */\r
-#define GPIO_PORT_MASK3_MASKP6_Msk (0x01UL << GPIO_PORT_MASK3_MASKP6_Pos) /*!< GPIO_PORT MASK3: MASKP6 Mask */\r
-#define GPIO_PORT_MASK3_MASKP7_Pos 7 /*!< GPIO_PORT MASK3: MASKP7 Position */\r
-#define GPIO_PORT_MASK3_MASKP7_Msk (0x01UL << GPIO_PORT_MASK3_MASKP7_Pos) /*!< GPIO_PORT MASK3: MASKP7 Mask */\r
-#define GPIO_PORT_MASK3_MASKP8_Pos 8 /*!< GPIO_PORT MASK3: MASKP8 Position */\r
-#define GPIO_PORT_MASK3_MASKP8_Msk (0x01UL << GPIO_PORT_MASK3_MASKP8_Pos) /*!< GPIO_PORT MASK3: MASKP8 Mask */\r
-#define GPIO_PORT_MASK3_MASKP9_Pos 9 /*!< GPIO_PORT MASK3: MASKP9 Position */\r
-#define GPIO_PORT_MASK3_MASKP9_Msk (0x01UL << GPIO_PORT_MASK3_MASKP9_Pos) /*!< GPIO_PORT MASK3: MASKP9 Mask */\r
-#define GPIO_PORT_MASK3_MASKP10_Pos 10 /*!< GPIO_PORT MASK3: MASKP10 Position */\r
-#define GPIO_PORT_MASK3_MASKP10_Msk (0x01UL << GPIO_PORT_MASK3_MASKP10_Pos) /*!< GPIO_PORT MASK3: MASKP10 Mask */\r
-#define GPIO_PORT_MASK3_MASKP11_Pos 11 /*!< GPIO_PORT MASK3: MASKP11 Position */\r
-#define GPIO_PORT_MASK3_MASKP11_Msk (0x01UL << GPIO_PORT_MASK3_MASKP11_Pos) /*!< GPIO_PORT MASK3: MASKP11 Mask */\r
-#define GPIO_PORT_MASK3_MASKP12_Pos 12 /*!< GPIO_PORT MASK3: MASKP12 Position */\r
-#define GPIO_PORT_MASK3_MASKP12_Msk (0x01UL << GPIO_PORT_MASK3_MASKP12_Pos) /*!< GPIO_PORT MASK3: MASKP12 Mask */\r
-#define GPIO_PORT_MASK3_MASKP13_Pos 13 /*!< GPIO_PORT MASK3: MASKP13 Position */\r
-#define GPIO_PORT_MASK3_MASKP13_Msk (0x01UL << GPIO_PORT_MASK3_MASKP13_Pos) /*!< GPIO_PORT MASK3: MASKP13 Mask */\r
-#define GPIO_PORT_MASK3_MASKP14_Pos 14 /*!< GPIO_PORT MASK3: MASKP14 Position */\r
-#define GPIO_PORT_MASK3_MASKP14_Msk (0x01UL << GPIO_PORT_MASK3_MASKP14_Pos) /*!< GPIO_PORT MASK3: MASKP14 Mask */\r
-#define GPIO_PORT_MASK3_MASKP15_Pos 15 /*!< GPIO_PORT MASK3: MASKP15 Position */\r
-#define GPIO_PORT_MASK3_MASKP15_Msk (0x01UL << GPIO_PORT_MASK3_MASKP15_Pos) /*!< GPIO_PORT MASK3: MASKP15 Mask */\r
-#define GPIO_PORT_MASK3_MASKP16_Pos 16 /*!< GPIO_PORT MASK3: MASKP16 Position */\r
-#define GPIO_PORT_MASK3_MASKP16_Msk (0x01UL << GPIO_PORT_MASK3_MASKP16_Pos) /*!< GPIO_PORT MASK3: MASKP16 Mask */\r
-#define GPIO_PORT_MASK3_MASKP17_Pos 17 /*!< GPIO_PORT MASK3: MASKP17 Position */\r
-#define GPIO_PORT_MASK3_MASKP17_Msk (0x01UL << GPIO_PORT_MASK3_MASKP17_Pos) /*!< GPIO_PORT MASK3: MASKP17 Mask */\r
-#define GPIO_PORT_MASK3_MASKP18_Pos 18 /*!< GPIO_PORT MASK3: MASKP18 Position */\r
-#define GPIO_PORT_MASK3_MASKP18_Msk (0x01UL << GPIO_PORT_MASK3_MASKP18_Pos) /*!< GPIO_PORT MASK3: MASKP18 Mask */\r
-#define GPIO_PORT_MASK3_MASKP19_Pos 19 /*!< GPIO_PORT MASK3: MASKP19 Position */\r
-#define GPIO_PORT_MASK3_MASKP19_Msk (0x01UL << GPIO_PORT_MASK3_MASKP19_Pos) /*!< GPIO_PORT MASK3: MASKP19 Mask */\r
-#define GPIO_PORT_MASK3_MASKP20_Pos 20 /*!< GPIO_PORT MASK3: MASKP20 Position */\r
-#define GPIO_PORT_MASK3_MASKP20_Msk (0x01UL << GPIO_PORT_MASK3_MASKP20_Pos) /*!< GPIO_PORT MASK3: MASKP20 Mask */\r
-#define GPIO_PORT_MASK3_MASKP21_Pos 21 /*!< GPIO_PORT MASK3: MASKP21 Position */\r
-#define GPIO_PORT_MASK3_MASKP21_Msk (0x01UL << GPIO_PORT_MASK3_MASKP21_Pos) /*!< GPIO_PORT MASK3: MASKP21 Mask */\r
-#define GPIO_PORT_MASK3_MASKP22_Pos 22 /*!< GPIO_PORT MASK3: MASKP22 Position */\r
-#define GPIO_PORT_MASK3_MASKP22_Msk (0x01UL << GPIO_PORT_MASK3_MASKP22_Pos) /*!< GPIO_PORT MASK3: MASKP22 Mask */\r
-#define GPIO_PORT_MASK3_MASKP23_Pos 23 /*!< GPIO_PORT MASK3: MASKP23 Position */\r
-#define GPIO_PORT_MASK3_MASKP23_Msk (0x01UL << GPIO_PORT_MASK3_MASKP23_Pos) /*!< GPIO_PORT MASK3: MASKP23 Mask */\r
-#define GPIO_PORT_MASK3_MASKP24_Pos 24 /*!< GPIO_PORT MASK3: MASKP24 Position */\r
-#define GPIO_PORT_MASK3_MASKP24_Msk (0x01UL << GPIO_PORT_MASK3_MASKP24_Pos) /*!< GPIO_PORT MASK3: MASKP24 Mask */\r
-#define GPIO_PORT_MASK3_MASKP25_Pos 25 /*!< GPIO_PORT MASK3: MASKP25 Position */\r
-#define GPIO_PORT_MASK3_MASKP25_Msk (0x01UL << GPIO_PORT_MASK3_MASKP25_Pos) /*!< GPIO_PORT MASK3: MASKP25 Mask */\r
-#define GPIO_PORT_MASK3_MASKP26_Pos 26 /*!< GPIO_PORT MASK3: MASKP26 Position */\r
-#define GPIO_PORT_MASK3_MASKP26_Msk (0x01UL << GPIO_PORT_MASK3_MASKP26_Pos) /*!< GPIO_PORT MASK3: MASKP26 Mask */\r
-#define GPIO_PORT_MASK3_MASKP27_Pos 27 /*!< GPIO_PORT MASK3: MASKP27 Position */\r
-#define GPIO_PORT_MASK3_MASKP27_Msk (0x01UL << GPIO_PORT_MASK3_MASKP27_Pos) /*!< GPIO_PORT MASK3: MASKP27 Mask */\r
-#define GPIO_PORT_MASK3_MASKP28_Pos 28 /*!< GPIO_PORT MASK3: MASKP28 Position */\r
-#define GPIO_PORT_MASK3_MASKP28_Msk (0x01UL << GPIO_PORT_MASK3_MASKP28_Pos) /*!< GPIO_PORT MASK3: MASKP28 Mask */\r
-#define GPIO_PORT_MASK3_MASKP29_Pos 29 /*!< GPIO_PORT MASK3: MASKP29 Position */\r
-#define GPIO_PORT_MASK3_MASKP29_Msk (0x01UL << GPIO_PORT_MASK3_MASKP29_Pos) /*!< GPIO_PORT MASK3: MASKP29 Mask */\r
-#define GPIO_PORT_MASK3_MASKP30_Pos 30 /*!< GPIO_PORT MASK3: MASKP30 Position */\r
-#define GPIO_PORT_MASK3_MASKP30_Msk (0x01UL << GPIO_PORT_MASK3_MASKP30_Pos) /*!< GPIO_PORT MASK3: MASKP30 Mask */\r
-#define GPIO_PORT_MASK3_MASKP31_Pos 31 /*!< GPIO_PORT MASK3: MASKP31 Position */\r
-#define GPIO_PORT_MASK3_MASKP31_Msk (0x01UL << GPIO_PORT_MASK3_MASKP31_Pos) /*!< GPIO_PORT MASK3: MASKP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MASK4 ----------------------------------------\r
-#define GPIO_PORT_MASK4_MASKP0_Pos 0 /*!< GPIO_PORT MASK4: MASKP0 Position */\r
-#define GPIO_PORT_MASK4_MASKP0_Msk (0x01UL << GPIO_PORT_MASK4_MASKP0_Pos) /*!< GPIO_PORT MASK4: MASKP0 Mask */\r
-#define GPIO_PORT_MASK4_MASKP1_Pos 1 /*!< GPIO_PORT MASK4: MASKP1 Position */\r
-#define GPIO_PORT_MASK4_MASKP1_Msk (0x01UL << GPIO_PORT_MASK4_MASKP1_Pos) /*!< GPIO_PORT MASK4: MASKP1 Mask */\r
-#define GPIO_PORT_MASK4_MASKP2_Pos 2 /*!< GPIO_PORT MASK4: MASKP2 Position */\r
-#define GPIO_PORT_MASK4_MASKP2_Msk (0x01UL << GPIO_PORT_MASK4_MASKP2_Pos) /*!< GPIO_PORT MASK4: MASKP2 Mask */\r
-#define GPIO_PORT_MASK4_MASKP3_Pos 3 /*!< GPIO_PORT MASK4: MASKP3 Position */\r
-#define GPIO_PORT_MASK4_MASKP3_Msk (0x01UL << GPIO_PORT_MASK4_MASKP3_Pos) /*!< GPIO_PORT MASK4: MASKP3 Mask */\r
-#define GPIO_PORT_MASK4_MASKP4_Pos 4 /*!< GPIO_PORT MASK4: MASKP4 Position */\r
-#define GPIO_PORT_MASK4_MASKP4_Msk (0x01UL << GPIO_PORT_MASK4_MASKP4_Pos) /*!< GPIO_PORT MASK4: MASKP4 Mask */\r
-#define GPIO_PORT_MASK4_MASKP5_Pos 5 /*!< GPIO_PORT MASK4: MASKP5 Position */\r
-#define GPIO_PORT_MASK4_MASKP5_Msk (0x01UL << GPIO_PORT_MASK4_MASKP5_Pos) /*!< GPIO_PORT MASK4: MASKP5 Mask */\r
-#define GPIO_PORT_MASK4_MASKP6_Pos 6 /*!< GPIO_PORT MASK4: MASKP6 Position */\r
-#define GPIO_PORT_MASK4_MASKP6_Msk (0x01UL << GPIO_PORT_MASK4_MASKP6_Pos) /*!< GPIO_PORT MASK4: MASKP6 Mask */\r
-#define GPIO_PORT_MASK4_MASKP7_Pos 7 /*!< GPIO_PORT MASK4: MASKP7 Position */\r
-#define GPIO_PORT_MASK4_MASKP7_Msk (0x01UL << GPIO_PORT_MASK4_MASKP7_Pos) /*!< GPIO_PORT MASK4: MASKP7 Mask */\r
-#define GPIO_PORT_MASK4_MASKP8_Pos 8 /*!< GPIO_PORT MASK4: MASKP8 Position */\r
-#define GPIO_PORT_MASK4_MASKP8_Msk (0x01UL << GPIO_PORT_MASK4_MASKP8_Pos) /*!< GPIO_PORT MASK4: MASKP8 Mask */\r
-#define GPIO_PORT_MASK4_MASKP9_Pos 9 /*!< GPIO_PORT MASK4: MASKP9 Position */\r
-#define GPIO_PORT_MASK4_MASKP9_Msk (0x01UL << GPIO_PORT_MASK4_MASKP9_Pos) /*!< GPIO_PORT MASK4: MASKP9 Mask */\r
-#define GPIO_PORT_MASK4_MASKP10_Pos 10 /*!< GPIO_PORT MASK4: MASKP10 Position */\r
-#define GPIO_PORT_MASK4_MASKP10_Msk (0x01UL << GPIO_PORT_MASK4_MASKP10_Pos) /*!< GPIO_PORT MASK4: MASKP10 Mask */\r
-#define GPIO_PORT_MASK4_MASKP11_Pos 11 /*!< GPIO_PORT MASK4: MASKP11 Position */\r
-#define GPIO_PORT_MASK4_MASKP11_Msk (0x01UL << GPIO_PORT_MASK4_MASKP11_Pos) /*!< GPIO_PORT MASK4: MASKP11 Mask */\r
-#define GPIO_PORT_MASK4_MASKP12_Pos 12 /*!< GPIO_PORT MASK4: MASKP12 Position */\r
-#define GPIO_PORT_MASK4_MASKP12_Msk (0x01UL << GPIO_PORT_MASK4_MASKP12_Pos) /*!< GPIO_PORT MASK4: MASKP12 Mask */\r
-#define GPIO_PORT_MASK4_MASKP13_Pos 13 /*!< GPIO_PORT MASK4: MASKP13 Position */\r
-#define GPIO_PORT_MASK4_MASKP13_Msk (0x01UL << GPIO_PORT_MASK4_MASKP13_Pos) /*!< GPIO_PORT MASK4: MASKP13 Mask */\r
-#define GPIO_PORT_MASK4_MASKP14_Pos 14 /*!< GPIO_PORT MASK4: MASKP14 Position */\r
-#define GPIO_PORT_MASK4_MASKP14_Msk (0x01UL << GPIO_PORT_MASK4_MASKP14_Pos) /*!< GPIO_PORT MASK4: MASKP14 Mask */\r
-#define GPIO_PORT_MASK4_MASKP15_Pos 15 /*!< GPIO_PORT MASK4: MASKP15 Position */\r
-#define GPIO_PORT_MASK4_MASKP15_Msk (0x01UL << GPIO_PORT_MASK4_MASKP15_Pos) /*!< GPIO_PORT MASK4: MASKP15 Mask */\r
-#define GPIO_PORT_MASK4_MASKP16_Pos 16 /*!< GPIO_PORT MASK4: MASKP16 Position */\r
-#define GPIO_PORT_MASK4_MASKP16_Msk (0x01UL << GPIO_PORT_MASK4_MASKP16_Pos) /*!< GPIO_PORT MASK4: MASKP16 Mask */\r
-#define GPIO_PORT_MASK4_MASKP17_Pos 17 /*!< GPIO_PORT MASK4: MASKP17 Position */\r
-#define GPIO_PORT_MASK4_MASKP17_Msk (0x01UL << GPIO_PORT_MASK4_MASKP17_Pos) /*!< GPIO_PORT MASK4: MASKP17 Mask */\r
-#define GPIO_PORT_MASK4_MASKP18_Pos 18 /*!< GPIO_PORT MASK4: MASKP18 Position */\r
-#define GPIO_PORT_MASK4_MASKP18_Msk (0x01UL << GPIO_PORT_MASK4_MASKP18_Pos) /*!< GPIO_PORT MASK4: MASKP18 Mask */\r
-#define GPIO_PORT_MASK4_MASKP19_Pos 19 /*!< GPIO_PORT MASK4: MASKP19 Position */\r
-#define GPIO_PORT_MASK4_MASKP19_Msk (0x01UL << GPIO_PORT_MASK4_MASKP19_Pos) /*!< GPIO_PORT MASK4: MASKP19 Mask */\r
-#define GPIO_PORT_MASK4_MASKP20_Pos 20 /*!< GPIO_PORT MASK4: MASKP20 Position */\r
-#define GPIO_PORT_MASK4_MASKP20_Msk (0x01UL << GPIO_PORT_MASK4_MASKP20_Pos) /*!< GPIO_PORT MASK4: MASKP20 Mask */\r
-#define GPIO_PORT_MASK4_MASKP21_Pos 21 /*!< GPIO_PORT MASK4: MASKP21 Position */\r
-#define GPIO_PORT_MASK4_MASKP21_Msk (0x01UL << GPIO_PORT_MASK4_MASKP21_Pos) /*!< GPIO_PORT MASK4: MASKP21 Mask */\r
-#define GPIO_PORT_MASK4_MASKP22_Pos 22 /*!< GPIO_PORT MASK4: MASKP22 Position */\r
-#define GPIO_PORT_MASK4_MASKP22_Msk (0x01UL << GPIO_PORT_MASK4_MASKP22_Pos) /*!< GPIO_PORT MASK4: MASKP22 Mask */\r
-#define GPIO_PORT_MASK4_MASKP23_Pos 23 /*!< GPIO_PORT MASK4: MASKP23 Position */\r
-#define GPIO_PORT_MASK4_MASKP23_Msk (0x01UL << GPIO_PORT_MASK4_MASKP23_Pos) /*!< GPIO_PORT MASK4: MASKP23 Mask */\r
-#define GPIO_PORT_MASK4_MASKP24_Pos 24 /*!< GPIO_PORT MASK4: MASKP24 Position */\r
-#define GPIO_PORT_MASK4_MASKP24_Msk (0x01UL << GPIO_PORT_MASK4_MASKP24_Pos) /*!< GPIO_PORT MASK4: MASKP24 Mask */\r
-#define GPIO_PORT_MASK4_MASKP25_Pos 25 /*!< GPIO_PORT MASK4: MASKP25 Position */\r
-#define GPIO_PORT_MASK4_MASKP25_Msk (0x01UL << GPIO_PORT_MASK4_MASKP25_Pos) /*!< GPIO_PORT MASK4: MASKP25 Mask */\r
-#define GPIO_PORT_MASK4_MASKP26_Pos 26 /*!< GPIO_PORT MASK4: MASKP26 Position */\r
-#define GPIO_PORT_MASK4_MASKP26_Msk (0x01UL << GPIO_PORT_MASK4_MASKP26_Pos) /*!< GPIO_PORT MASK4: MASKP26 Mask */\r
-#define GPIO_PORT_MASK4_MASKP27_Pos 27 /*!< GPIO_PORT MASK4: MASKP27 Position */\r
-#define GPIO_PORT_MASK4_MASKP27_Msk (0x01UL << GPIO_PORT_MASK4_MASKP27_Pos) /*!< GPIO_PORT MASK4: MASKP27 Mask */\r
-#define GPIO_PORT_MASK4_MASKP28_Pos 28 /*!< GPIO_PORT MASK4: MASKP28 Position */\r
-#define GPIO_PORT_MASK4_MASKP28_Msk (0x01UL << GPIO_PORT_MASK4_MASKP28_Pos) /*!< GPIO_PORT MASK4: MASKP28 Mask */\r
-#define GPIO_PORT_MASK4_MASKP29_Pos 29 /*!< GPIO_PORT MASK4: MASKP29 Position */\r
-#define GPIO_PORT_MASK4_MASKP29_Msk (0x01UL << GPIO_PORT_MASK4_MASKP29_Pos) /*!< GPIO_PORT MASK4: MASKP29 Mask */\r
-#define GPIO_PORT_MASK4_MASKP30_Pos 30 /*!< GPIO_PORT MASK4: MASKP30 Position */\r
-#define GPIO_PORT_MASK4_MASKP30_Msk (0x01UL << GPIO_PORT_MASK4_MASKP30_Pos) /*!< GPIO_PORT MASK4: MASKP30 Mask */\r
-#define GPIO_PORT_MASK4_MASKP31_Pos 31 /*!< GPIO_PORT MASK4: MASKP31 Position */\r
-#define GPIO_PORT_MASK4_MASKP31_Msk (0x01UL << GPIO_PORT_MASK4_MASKP31_Pos) /*!< GPIO_PORT MASK4: MASKP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MASK5 ----------------------------------------\r
-#define GPIO_PORT_MASK5_MASKP0_Pos 0 /*!< GPIO_PORT MASK5: MASKP0 Position */\r
-#define GPIO_PORT_MASK5_MASKP0_Msk (0x01UL << GPIO_PORT_MASK5_MASKP0_Pos) /*!< GPIO_PORT MASK5: MASKP0 Mask */\r
-#define GPIO_PORT_MASK5_MASKP1_Pos 1 /*!< GPIO_PORT MASK5: MASKP1 Position */\r
-#define GPIO_PORT_MASK5_MASKP1_Msk (0x01UL << GPIO_PORT_MASK5_MASKP1_Pos) /*!< GPIO_PORT MASK5: MASKP1 Mask */\r
-#define GPIO_PORT_MASK5_MASKP2_Pos 2 /*!< GPIO_PORT MASK5: MASKP2 Position */\r
-#define GPIO_PORT_MASK5_MASKP2_Msk (0x01UL << GPIO_PORT_MASK5_MASKP2_Pos) /*!< GPIO_PORT MASK5: MASKP2 Mask */\r
-#define GPIO_PORT_MASK5_MASKP3_Pos 3 /*!< GPIO_PORT MASK5: MASKP3 Position */\r
-#define GPIO_PORT_MASK5_MASKP3_Msk (0x01UL << GPIO_PORT_MASK5_MASKP3_Pos) /*!< GPIO_PORT MASK5: MASKP3 Mask */\r
-#define GPIO_PORT_MASK5_MASKP4_Pos 4 /*!< GPIO_PORT MASK5: MASKP4 Position */\r
-#define GPIO_PORT_MASK5_MASKP4_Msk (0x01UL << GPIO_PORT_MASK5_MASKP4_Pos) /*!< GPIO_PORT MASK5: MASKP4 Mask */\r
-#define GPIO_PORT_MASK5_MASKP5_Pos 5 /*!< GPIO_PORT MASK5: MASKP5 Position */\r
-#define GPIO_PORT_MASK5_MASKP5_Msk (0x01UL << GPIO_PORT_MASK5_MASKP5_Pos) /*!< GPIO_PORT MASK5: MASKP5 Mask */\r
-#define GPIO_PORT_MASK5_MASKP6_Pos 6 /*!< GPIO_PORT MASK5: MASKP6 Position */\r
-#define GPIO_PORT_MASK5_MASKP6_Msk (0x01UL << GPIO_PORT_MASK5_MASKP6_Pos) /*!< GPIO_PORT MASK5: MASKP6 Mask */\r
-#define GPIO_PORT_MASK5_MASKP7_Pos 7 /*!< GPIO_PORT MASK5: MASKP7 Position */\r
-#define GPIO_PORT_MASK5_MASKP7_Msk (0x01UL << GPIO_PORT_MASK5_MASKP7_Pos) /*!< GPIO_PORT MASK5: MASKP7 Mask */\r
-#define GPIO_PORT_MASK5_MASKP8_Pos 8 /*!< GPIO_PORT MASK5: MASKP8 Position */\r
-#define GPIO_PORT_MASK5_MASKP8_Msk (0x01UL << GPIO_PORT_MASK5_MASKP8_Pos) /*!< GPIO_PORT MASK5: MASKP8 Mask */\r
-#define GPIO_PORT_MASK5_MASKP9_Pos 9 /*!< GPIO_PORT MASK5: MASKP9 Position */\r
-#define GPIO_PORT_MASK5_MASKP9_Msk (0x01UL << GPIO_PORT_MASK5_MASKP9_Pos) /*!< GPIO_PORT MASK5: MASKP9 Mask */\r
-#define GPIO_PORT_MASK5_MASKP10_Pos 10 /*!< GPIO_PORT MASK5: MASKP10 Position */\r
-#define GPIO_PORT_MASK5_MASKP10_Msk (0x01UL << GPIO_PORT_MASK5_MASKP10_Pos) /*!< GPIO_PORT MASK5: MASKP10 Mask */\r
-#define GPIO_PORT_MASK5_MASKP11_Pos 11 /*!< GPIO_PORT MASK5: MASKP11 Position */\r
-#define GPIO_PORT_MASK5_MASKP11_Msk (0x01UL << GPIO_PORT_MASK5_MASKP11_Pos) /*!< GPIO_PORT MASK5: MASKP11 Mask */\r
-#define GPIO_PORT_MASK5_MASKP12_Pos 12 /*!< GPIO_PORT MASK5: MASKP12 Position */\r
-#define GPIO_PORT_MASK5_MASKP12_Msk (0x01UL << GPIO_PORT_MASK5_MASKP12_Pos) /*!< GPIO_PORT MASK5: MASKP12 Mask */\r
-#define GPIO_PORT_MASK5_MASKP13_Pos 13 /*!< GPIO_PORT MASK5: MASKP13 Position */\r
-#define GPIO_PORT_MASK5_MASKP13_Msk (0x01UL << GPIO_PORT_MASK5_MASKP13_Pos) /*!< GPIO_PORT MASK5: MASKP13 Mask */\r
-#define GPIO_PORT_MASK5_MASKP14_Pos 14 /*!< GPIO_PORT MASK5: MASKP14 Position */\r
-#define GPIO_PORT_MASK5_MASKP14_Msk (0x01UL << GPIO_PORT_MASK5_MASKP14_Pos) /*!< GPIO_PORT MASK5: MASKP14 Mask */\r
-#define GPIO_PORT_MASK5_MASKP15_Pos 15 /*!< GPIO_PORT MASK5: MASKP15 Position */\r
-#define GPIO_PORT_MASK5_MASKP15_Msk (0x01UL << GPIO_PORT_MASK5_MASKP15_Pos) /*!< GPIO_PORT MASK5: MASKP15 Mask */\r
-#define GPIO_PORT_MASK5_MASKP16_Pos 16 /*!< GPIO_PORT MASK5: MASKP16 Position */\r
-#define GPIO_PORT_MASK5_MASKP16_Msk (0x01UL << GPIO_PORT_MASK5_MASKP16_Pos) /*!< GPIO_PORT MASK5: MASKP16 Mask */\r
-#define GPIO_PORT_MASK5_MASKP17_Pos 17 /*!< GPIO_PORT MASK5: MASKP17 Position */\r
-#define GPIO_PORT_MASK5_MASKP17_Msk (0x01UL << GPIO_PORT_MASK5_MASKP17_Pos) /*!< GPIO_PORT MASK5: MASKP17 Mask */\r
-#define GPIO_PORT_MASK5_MASKP18_Pos 18 /*!< GPIO_PORT MASK5: MASKP18 Position */\r
-#define GPIO_PORT_MASK5_MASKP18_Msk (0x01UL << GPIO_PORT_MASK5_MASKP18_Pos) /*!< GPIO_PORT MASK5: MASKP18 Mask */\r
-#define GPIO_PORT_MASK5_MASKP19_Pos 19 /*!< GPIO_PORT MASK5: MASKP19 Position */\r
-#define GPIO_PORT_MASK5_MASKP19_Msk (0x01UL << GPIO_PORT_MASK5_MASKP19_Pos) /*!< GPIO_PORT MASK5: MASKP19 Mask */\r
-#define GPIO_PORT_MASK5_MASKP20_Pos 20 /*!< GPIO_PORT MASK5: MASKP20 Position */\r
-#define GPIO_PORT_MASK5_MASKP20_Msk (0x01UL << GPIO_PORT_MASK5_MASKP20_Pos) /*!< GPIO_PORT MASK5: MASKP20 Mask */\r
-#define GPIO_PORT_MASK5_MASKP21_Pos 21 /*!< GPIO_PORT MASK5: MASKP21 Position */\r
-#define GPIO_PORT_MASK5_MASKP21_Msk (0x01UL << GPIO_PORT_MASK5_MASKP21_Pos) /*!< GPIO_PORT MASK5: MASKP21 Mask */\r
-#define GPIO_PORT_MASK5_MASKP22_Pos 22 /*!< GPIO_PORT MASK5: MASKP22 Position */\r
-#define GPIO_PORT_MASK5_MASKP22_Msk (0x01UL << GPIO_PORT_MASK5_MASKP22_Pos) /*!< GPIO_PORT MASK5: MASKP22 Mask */\r
-#define GPIO_PORT_MASK5_MASKP23_Pos 23 /*!< GPIO_PORT MASK5: MASKP23 Position */\r
-#define GPIO_PORT_MASK5_MASKP23_Msk (0x01UL << GPIO_PORT_MASK5_MASKP23_Pos) /*!< GPIO_PORT MASK5: MASKP23 Mask */\r
-#define GPIO_PORT_MASK5_MASKP24_Pos 24 /*!< GPIO_PORT MASK5: MASKP24 Position */\r
-#define GPIO_PORT_MASK5_MASKP24_Msk (0x01UL << GPIO_PORT_MASK5_MASKP24_Pos) /*!< GPIO_PORT MASK5: MASKP24 Mask */\r
-#define GPIO_PORT_MASK5_MASKP25_Pos 25 /*!< GPIO_PORT MASK5: MASKP25 Position */\r
-#define GPIO_PORT_MASK5_MASKP25_Msk (0x01UL << GPIO_PORT_MASK5_MASKP25_Pos) /*!< GPIO_PORT MASK5: MASKP25 Mask */\r
-#define GPIO_PORT_MASK5_MASKP26_Pos 26 /*!< GPIO_PORT MASK5: MASKP26 Position */\r
-#define GPIO_PORT_MASK5_MASKP26_Msk (0x01UL << GPIO_PORT_MASK5_MASKP26_Pos) /*!< GPIO_PORT MASK5: MASKP26 Mask */\r
-#define GPIO_PORT_MASK5_MASKP27_Pos 27 /*!< GPIO_PORT MASK5: MASKP27 Position */\r
-#define GPIO_PORT_MASK5_MASKP27_Msk (0x01UL << GPIO_PORT_MASK5_MASKP27_Pos) /*!< GPIO_PORT MASK5: MASKP27 Mask */\r
-#define GPIO_PORT_MASK5_MASKP28_Pos 28 /*!< GPIO_PORT MASK5: MASKP28 Position */\r
-#define GPIO_PORT_MASK5_MASKP28_Msk (0x01UL << GPIO_PORT_MASK5_MASKP28_Pos) /*!< GPIO_PORT MASK5: MASKP28 Mask */\r
-#define GPIO_PORT_MASK5_MASKP29_Pos 29 /*!< GPIO_PORT MASK5: MASKP29 Position */\r
-#define GPIO_PORT_MASK5_MASKP29_Msk (0x01UL << GPIO_PORT_MASK5_MASKP29_Pos) /*!< GPIO_PORT MASK5: MASKP29 Mask */\r
-#define GPIO_PORT_MASK5_MASKP30_Pos 30 /*!< GPIO_PORT MASK5: MASKP30 Position */\r
-#define GPIO_PORT_MASK5_MASKP30_Msk (0x01UL << GPIO_PORT_MASK5_MASKP30_Pos) /*!< GPIO_PORT MASK5: MASKP30 Mask */\r
-#define GPIO_PORT_MASK5_MASKP31_Pos 31 /*!< GPIO_PORT MASK5: MASKP31 Position */\r
-#define GPIO_PORT_MASK5_MASKP31_Msk (0x01UL << GPIO_PORT_MASK5_MASKP31_Pos) /*!< GPIO_PORT MASK5: MASKP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MASK6 ----------------------------------------\r
-#define GPIO_PORT_MASK6_MASKP0_Pos 0 /*!< GPIO_PORT MASK6: MASKP0 Position */\r
-#define GPIO_PORT_MASK6_MASKP0_Msk (0x01UL << GPIO_PORT_MASK6_MASKP0_Pos) /*!< GPIO_PORT MASK6: MASKP0 Mask */\r
-#define GPIO_PORT_MASK6_MASKP1_Pos 1 /*!< GPIO_PORT MASK6: MASKP1 Position */\r
-#define GPIO_PORT_MASK6_MASKP1_Msk (0x01UL << GPIO_PORT_MASK6_MASKP1_Pos) /*!< GPIO_PORT MASK6: MASKP1 Mask */\r
-#define GPIO_PORT_MASK6_MASKP2_Pos 2 /*!< GPIO_PORT MASK6: MASKP2 Position */\r
-#define GPIO_PORT_MASK6_MASKP2_Msk (0x01UL << GPIO_PORT_MASK6_MASKP2_Pos) /*!< GPIO_PORT MASK6: MASKP2 Mask */\r
-#define GPIO_PORT_MASK6_MASKP3_Pos 3 /*!< GPIO_PORT MASK6: MASKP3 Position */\r
-#define GPIO_PORT_MASK6_MASKP3_Msk (0x01UL << GPIO_PORT_MASK6_MASKP3_Pos) /*!< GPIO_PORT MASK6: MASKP3 Mask */\r
-#define GPIO_PORT_MASK6_MASKP4_Pos 4 /*!< GPIO_PORT MASK6: MASKP4 Position */\r
-#define GPIO_PORT_MASK6_MASKP4_Msk (0x01UL << GPIO_PORT_MASK6_MASKP4_Pos) /*!< GPIO_PORT MASK6: MASKP4 Mask */\r
-#define GPIO_PORT_MASK6_MASKP5_Pos 5 /*!< GPIO_PORT MASK6: MASKP5 Position */\r
-#define GPIO_PORT_MASK6_MASKP5_Msk (0x01UL << GPIO_PORT_MASK6_MASKP5_Pos) /*!< GPIO_PORT MASK6: MASKP5 Mask */\r
-#define GPIO_PORT_MASK6_MASKP6_Pos 6 /*!< GPIO_PORT MASK6: MASKP6 Position */\r
-#define GPIO_PORT_MASK6_MASKP6_Msk (0x01UL << GPIO_PORT_MASK6_MASKP6_Pos) /*!< GPIO_PORT MASK6: MASKP6 Mask */\r
-#define GPIO_PORT_MASK6_MASKP7_Pos 7 /*!< GPIO_PORT MASK6: MASKP7 Position */\r
-#define GPIO_PORT_MASK6_MASKP7_Msk (0x01UL << GPIO_PORT_MASK6_MASKP7_Pos) /*!< GPIO_PORT MASK6: MASKP7 Mask */\r
-#define GPIO_PORT_MASK6_MASKP8_Pos 8 /*!< GPIO_PORT MASK6: MASKP8 Position */\r
-#define GPIO_PORT_MASK6_MASKP8_Msk (0x01UL << GPIO_PORT_MASK6_MASKP8_Pos) /*!< GPIO_PORT MASK6: MASKP8 Mask */\r
-#define GPIO_PORT_MASK6_MASKP9_Pos 9 /*!< GPIO_PORT MASK6: MASKP9 Position */\r
-#define GPIO_PORT_MASK6_MASKP9_Msk (0x01UL << GPIO_PORT_MASK6_MASKP9_Pos) /*!< GPIO_PORT MASK6: MASKP9 Mask */\r
-#define GPIO_PORT_MASK6_MASKP10_Pos 10 /*!< GPIO_PORT MASK6: MASKP10 Position */\r
-#define GPIO_PORT_MASK6_MASKP10_Msk (0x01UL << GPIO_PORT_MASK6_MASKP10_Pos) /*!< GPIO_PORT MASK6: MASKP10 Mask */\r
-#define GPIO_PORT_MASK6_MASKP11_Pos 11 /*!< GPIO_PORT MASK6: MASKP11 Position */\r
-#define GPIO_PORT_MASK6_MASKP11_Msk (0x01UL << GPIO_PORT_MASK6_MASKP11_Pos) /*!< GPIO_PORT MASK6: MASKP11 Mask */\r
-#define GPIO_PORT_MASK6_MASKP12_Pos 12 /*!< GPIO_PORT MASK6: MASKP12 Position */\r
-#define GPIO_PORT_MASK6_MASKP12_Msk (0x01UL << GPIO_PORT_MASK6_MASKP12_Pos) /*!< GPIO_PORT MASK6: MASKP12 Mask */\r
-#define GPIO_PORT_MASK6_MASKP13_Pos 13 /*!< GPIO_PORT MASK6: MASKP13 Position */\r
-#define GPIO_PORT_MASK6_MASKP13_Msk (0x01UL << GPIO_PORT_MASK6_MASKP13_Pos) /*!< GPIO_PORT MASK6: MASKP13 Mask */\r
-#define GPIO_PORT_MASK6_MASKP14_Pos 14 /*!< GPIO_PORT MASK6: MASKP14 Position */\r
-#define GPIO_PORT_MASK6_MASKP14_Msk (0x01UL << GPIO_PORT_MASK6_MASKP14_Pos) /*!< GPIO_PORT MASK6: MASKP14 Mask */\r
-#define GPIO_PORT_MASK6_MASKP15_Pos 15 /*!< GPIO_PORT MASK6: MASKP15 Position */\r
-#define GPIO_PORT_MASK6_MASKP15_Msk (0x01UL << GPIO_PORT_MASK6_MASKP15_Pos) /*!< GPIO_PORT MASK6: MASKP15 Mask */\r
-#define GPIO_PORT_MASK6_MASKP16_Pos 16 /*!< GPIO_PORT MASK6: MASKP16 Position */\r
-#define GPIO_PORT_MASK6_MASKP16_Msk (0x01UL << GPIO_PORT_MASK6_MASKP16_Pos) /*!< GPIO_PORT MASK6: MASKP16 Mask */\r
-#define GPIO_PORT_MASK6_MASKP17_Pos 17 /*!< GPIO_PORT MASK6: MASKP17 Position */\r
-#define GPIO_PORT_MASK6_MASKP17_Msk (0x01UL << GPIO_PORT_MASK6_MASKP17_Pos) /*!< GPIO_PORT MASK6: MASKP17 Mask */\r
-#define GPIO_PORT_MASK6_MASKP18_Pos 18 /*!< GPIO_PORT MASK6: MASKP18 Position */\r
-#define GPIO_PORT_MASK6_MASKP18_Msk (0x01UL << GPIO_PORT_MASK6_MASKP18_Pos) /*!< GPIO_PORT MASK6: MASKP18 Mask */\r
-#define GPIO_PORT_MASK6_MASKP19_Pos 19 /*!< GPIO_PORT MASK6: MASKP19 Position */\r
-#define GPIO_PORT_MASK6_MASKP19_Msk (0x01UL << GPIO_PORT_MASK6_MASKP19_Pos) /*!< GPIO_PORT MASK6: MASKP19 Mask */\r
-#define GPIO_PORT_MASK6_MASKP20_Pos 20 /*!< GPIO_PORT MASK6: MASKP20 Position */\r
-#define GPIO_PORT_MASK6_MASKP20_Msk (0x01UL << GPIO_PORT_MASK6_MASKP20_Pos) /*!< GPIO_PORT MASK6: MASKP20 Mask */\r
-#define GPIO_PORT_MASK6_MASKP21_Pos 21 /*!< GPIO_PORT MASK6: MASKP21 Position */\r
-#define GPIO_PORT_MASK6_MASKP21_Msk (0x01UL << GPIO_PORT_MASK6_MASKP21_Pos) /*!< GPIO_PORT MASK6: MASKP21 Mask */\r
-#define GPIO_PORT_MASK6_MASKP22_Pos 22 /*!< GPIO_PORT MASK6: MASKP22 Position */\r
-#define GPIO_PORT_MASK6_MASKP22_Msk (0x01UL << GPIO_PORT_MASK6_MASKP22_Pos) /*!< GPIO_PORT MASK6: MASKP22 Mask */\r
-#define GPIO_PORT_MASK6_MASKP23_Pos 23 /*!< GPIO_PORT MASK6: MASKP23 Position */\r
-#define GPIO_PORT_MASK6_MASKP23_Msk (0x01UL << GPIO_PORT_MASK6_MASKP23_Pos) /*!< GPIO_PORT MASK6: MASKP23 Mask */\r
-#define GPIO_PORT_MASK6_MASKP24_Pos 24 /*!< GPIO_PORT MASK6: MASKP24 Position */\r
-#define GPIO_PORT_MASK6_MASKP24_Msk (0x01UL << GPIO_PORT_MASK6_MASKP24_Pos) /*!< GPIO_PORT MASK6: MASKP24 Mask */\r
-#define GPIO_PORT_MASK6_MASKP25_Pos 25 /*!< GPIO_PORT MASK6: MASKP25 Position */\r
-#define GPIO_PORT_MASK6_MASKP25_Msk (0x01UL << GPIO_PORT_MASK6_MASKP25_Pos) /*!< GPIO_PORT MASK6: MASKP25 Mask */\r
-#define GPIO_PORT_MASK6_MASKP26_Pos 26 /*!< GPIO_PORT MASK6: MASKP26 Position */\r
-#define GPIO_PORT_MASK6_MASKP26_Msk (0x01UL << GPIO_PORT_MASK6_MASKP26_Pos) /*!< GPIO_PORT MASK6: MASKP26 Mask */\r
-#define GPIO_PORT_MASK6_MASKP27_Pos 27 /*!< GPIO_PORT MASK6: MASKP27 Position */\r
-#define GPIO_PORT_MASK6_MASKP27_Msk (0x01UL << GPIO_PORT_MASK6_MASKP27_Pos) /*!< GPIO_PORT MASK6: MASKP27 Mask */\r
-#define GPIO_PORT_MASK6_MASKP28_Pos 28 /*!< GPIO_PORT MASK6: MASKP28 Position */\r
-#define GPIO_PORT_MASK6_MASKP28_Msk (0x01UL << GPIO_PORT_MASK6_MASKP28_Pos) /*!< GPIO_PORT MASK6: MASKP28 Mask */\r
-#define GPIO_PORT_MASK6_MASKP29_Pos 29 /*!< GPIO_PORT MASK6: MASKP29 Position */\r
-#define GPIO_PORT_MASK6_MASKP29_Msk (0x01UL << GPIO_PORT_MASK6_MASKP29_Pos) /*!< GPIO_PORT MASK6: MASKP29 Mask */\r
-#define GPIO_PORT_MASK6_MASKP30_Pos 30 /*!< GPIO_PORT MASK6: MASKP30 Position */\r
-#define GPIO_PORT_MASK6_MASKP30_Msk (0x01UL << GPIO_PORT_MASK6_MASKP30_Pos) /*!< GPIO_PORT MASK6: MASKP30 Mask */\r
-#define GPIO_PORT_MASK6_MASKP31_Pos 31 /*!< GPIO_PORT MASK6: MASKP31 Position */\r
-#define GPIO_PORT_MASK6_MASKP31_Msk (0x01UL << GPIO_PORT_MASK6_MASKP31_Pos) /*!< GPIO_PORT MASK6: MASKP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MASK7 ----------------------------------------\r
-#define GPIO_PORT_MASK7_MASKP0_Pos 0 /*!< GPIO_PORT MASK7: MASKP0 Position */\r
-#define GPIO_PORT_MASK7_MASKP0_Msk (0x01UL << GPIO_PORT_MASK7_MASKP0_Pos) /*!< GPIO_PORT MASK7: MASKP0 Mask */\r
-#define GPIO_PORT_MASK7_MASKP1_Pos 1 /*!< GPIO_PORT MASK7: MASKP1 Position */\r
-#define GPIO_PORT_MASK7_MASKP1_Msk (0x01UL << GPIO_PORT_MASK7_MASKP1_Pos) /*!< GPIO_PORT MASK7: MASKP1 Mask */\r
-#define GPIO_PORT_MASK7_MASKP2_Pos 2 /*!< GPIO_PORT MASK7: MASKP2 Position */\r
-#define GPIO_PORT_MASK7_MASKP2_Msk (0x01UL << GPIO_PORT_MASK7_MASKP2_Pos) /*!< GPIO_PORT MASK7: MASKP2 Mask */\r
-#define GPIO_PORT_MASK7_MASKP3_Pos 3 /*!< GPIO_PORT MASK7: MASKP3 Position */\r
-#define GPIO_PORT_MASK7_MASKP3_Msk (0x01UL << GPIO_PORT_MASK7_MASKP3_Pos) /*!< GPIO_PORT MASK7: MASKP3 Mask */\r
-#define GPIO_PORT_MASK7_MASKP4_Pos 4 /*!< GPIO_PORT MASK7: MASKP4 Position */\r
-#define GPIO_PORT_MASK7_MASKP4_Msk (0x01UL << GPIO_PORT_MASK7_MASKP4_Pos) /*!< GPIO_PORT MASK7: MASKP4 Mask */\r
-#define GPIO_PORT_MASK7_MASKP5_Pos 5 /*!< GPIO_PORT MASK7: MASKP5 Position */\r
-#define GPIO_PORT_MASK7_MASKP5_Msk (0x01UL << GPIO_PORT_MASK7_MASKP5_Pos) /*!< GPIO_PORT MASK7: MASKP5 Mask */\r
-#define GPIO_PORT_MASK7_MASKP6_Pos 6 /*!< GPIO_PORT MASK7: MASKP6 Position */\r
-#define GPIO_PORT_MASK7_MASKP6_Msk (0x01UL << GPIO_PORT_MASK7_MASKP6_Pos) /*!< GPIO_PORT MASK7: MASKP6 Mask */\r
-#define GPIO_PORT_MASK7_MASKP7_Pos 7 /*!< GPIO_PORT MASK7: MASKP7 Position */\r
-#define GPIO_PORT_MASK7_MASKP7_Msk (0x01UL << GPIO_PORT_MASK7_MASKP7_Pos) /*!< GPIO_PORT MASK7: MASKP7 Mask */\r
-#define GPIO_PORT_MASK7_MASKP8_Pos 8 /*!< GPIO_PORT MASK7: MASKP8 Position */\r
-#define GPIO_PORT_MASK7_MASKP8_Msk (0x01UL << GPIO_PORT_MASK7_MASKP8_Pos) /*!< GPIO_PORT MASK7: MASKP8 Mask */\r
-#define GPIO_PORT_MASK7_MASKP9_Pos 9 /*!< GPIO_PORT MASK7: MASKP9 Position */\r
-#define GPIO_PORT_MASK7_MASKP9_Msk (0x01UL << GPIO_PORT_MASK7_MASKP9_Pos) /*!< GPIO_PORT MASK7: MASKP9 Mask */\r
-#define GPIO_PORT_MASK7_MASKP10_Pos 10 /*!< GPIO_PORT MASK7: MASKP10 Position */\r
-#define GPIO_PORT_MASK7_MASKP10_Msk (0x01UL << GPIO_PORT_MASK7_MASKP10_Pos) /*!< GPIO_PORT MASK7: MASKP10 Mask */\r
-#define GPIO_PORT_MASK7_MASKP11_Pos 11 /*!< GPIO_PORT MASK7: MASKP11 Position */\r
-#define GPIO_PORT_MASK7_MASKP11_Msk (0x01UL << GPIO_PORT_MASK7_MASKP11_Pos) /*!< GPIO_PORT MASK7: MASKP11 Mask */\r
-#define GPIO_PORT_MASK7_MASKP12_Pos 12 /*!< GPIO_PORT MASK7: MASKP12 Position */\r
-#define GPIO_PORT_MASK7_MASKP12_Msk (0x01UL << GPIO_PORT_MASK7_MASKP12_Pos) /*!< GPIO_PORT MASK7: MASKP12 Mask */\r
-#define GPIO_PORT_MASK7_MASKP13_Pos 13 /*!< GPIO_PORT MASK7: MASKP13 Position */\r
-#define GPIO_PORT_MASK7_MASKP13_Msk (0x01UL << GPIO_PORT_MASK7_MASKP13_Pos) /*!< GPIO_PORT MASK7: MASKP13 Mask */\r
-#define GPIO_PORT_MASK7_MASKP14_Pos 14 /*!< GPIO_PORT MASK7: MASKP14 Position */\r
-#define GPIO_PORT_MASK7_MASKP14_Msk (0x01UL << GPIO_PORT_MASK7_MASKP14_Pos) /*!< GPIO_PORT MASK7: MASKP14 Mask */\r
-#define GPIO_PORT_MASK7_MASKP15_Pos 15 /*!< GPIO_PORT MASK7: MASKP15 Position */\r
-#define GPIO_PORT_MASK7_MASKP15_Msk (0x01UL << GPIO_PORT_MASK7_MASKP15_Pos) /*!< GPIO_PORT MASK7: MASKP15 Mask */\r
-#define GPIO_PORT_MASK7_MASKP16_Pos 16 /*!< GPIO_PORT MASK7: MASKP16 Position */\r
-#define GPIO_PORT_MASK7_MASKP16_Msk (0x01UL << GPIO_PORT_MASK7_MASKP16_Pos) /*!< GPIO_PORT MASK7: MASKP16 Mask */\r
-#define GPIO_PORT_MASK7_MASKP17_Pos 17 /*!< GPIO_PORT MASK7: MASKP17 Position */\r
-#define GPIO_PORT_MASK7_MASKP17_Msk (0x01UL << GPIO_PORT_MASK7_MASKP17_Pos) /*!< GPIO_PORT MASK7: MASKP17 Mask */\r
-#define GPIO_PORT_MASK7_MASKP18_Pos 18 /*!< GPIO_PORT MASK7: MASKP18 Position */\r
-#define GPIO_PORT_MASK7_MASKP18_Msk (0x01UL << GPIO_PORT_MASK7_MASKP18_Pos) /*!< GPIO_PORT MASK7: MASKP18 Mask */\r
-#define GPIO_PORT_MASK7_MASKP19_Pos 19 /*!< GPIO_PORT MASK7: MASKP19 Position */\r
-#define GPIO_PORT_MASK7_MASKP19_Msk (0x01UL << GPIO_PORT_MASK7_MASKP19_Pos) /*!< GPIO_PORT MASK7: MASKP19 Mask */\r
-#define GPIO_PORT_MASK7_MASKP20_Pos 20 /*!< GPIO_PORT MASK7: MASKP20 Position */\r
-#define GPIO_PORT_MASK7_MASKP20_Msk (0x01UL << GPIO_PORT_MASK7_MASKP20_Pos) /*!< GPIO_PORT MASK7: MASKP20 Mask */\r
-#define GPIO_PORT_MASK7_MASKP21_Pos 21 /*!< GPIO_PORT MASK7: MASKP21 Position */\r
-#define GPIO_PORT_MASK7_MASKP21_Msk (0x01UL << GPIO_PORT_MASK7_MASKP21_Pos) /*!< GPIO_PORT MASK7: MASKP21 Mask */\r
-#define GPIO_PORT_MASK7_MASKP22_Pos 22 /*!< GPIO_PORT MASK7: MASKP22 Position */\r
-#define GPIO_PORT_MASK7_MASKP22_Msk (0x01UL << GPIO_PORT_MASK7_MASKP22_Pos) /*!< GPIO_PORT MASK7: MASKP22 Mask */\r
-#define GPIO_PORT_MASK7_MASKP23_Pos 23 /*!< GPIO_PORT MASK7: MASKP23 Position */\r
-#define GPIO_PORT_MASK7_MASKP23_Msk (0x01UL << GPIO_PORT_MASK7_MASKP23_Pos) /*!< GPIO_PORT MASK7: MASKP23 Mask */\r
-#define GPIO_PORT_MASK7_MASKP24_Pos 24 /*!< GPIO_PORT MASK7: MASKP24 Position */\r
-#define GPIO_PORT_MASK7_MASKP24_Msk (0x01UL << GPIO_PORT_MASK7_MASKP24_Pos) /*!< GPIO_PORT MASK7: MASKP24 Mask */\r
-#define GPIO_PORT_MASK7_MASKP25_Pos 25 /*!< GPIO_PORT MASK7: MASKP25 Position */\r
-#define GPIO_PORT_MASK7_MASKP25_Msk (0x01UL << GPIO_PORT_MASK7_MASKP25_Pos) /*!< GPIO_PORT MASK7: MASKP25 Mask */\r
-#define GPIO_PORT_MASK7_MASKP26_Pos 26 /*!< GPIO_PORT MASK7: MASKP26 Position */\r
-#define GPIO_PORT_MASK7_MASKP26_Msk (0x01UL << GPIO_PORT_MASK7_MASKP26_Pos) /*!< GPIO_PORT MASK7: MASKP26 Mask */\r
-#define GPIO_PORT_MASK7_MASKP27_Pos 27 /*!< GPIO_PORT MASK7: MASKP27 Position */\r
-#define GPIO_PORT_MASK7_MASKP27_Msk (0x01UL << GPIO_PORT_MASK7_MASKP27_Pos) /*!< GPIO_PORT MASK7: MASKP27 Mask */\r
-#define GPIO_PORT_MASK7_MASKP28_Pos 28 /*!< GPIO_PORT MASK7: MASKP28 Position */\r
-#define GPIO_PORT_MASK7_MASKP28_Msk (0x01UL << GPIO_PORT_MASK7_MASKP28_Pos) /*!< GPIO_PORT MASK7: MASKP28 Mask */\r
-#define GPIO_PORT_MASK7_MASKP29_Pos 29 /*!< GPIO_PORT MASK7: MASKP29 Position */\r
-#define GPIO_PORT_MASK7_MASKP29_Msk (0x01UL << GPIO_PORT_MASK7_MASKP29_Pos) /*!< GPIO_PORT MASK7: MASKP29 Mask */\r
-#define GPIO_PORT_MASK7_MASKP30_Pos 30 /*!< GPIO_PORT MASK7: MASKP30 Position */\r
-#define GPIO_PORT_MASK7_MASKP30_Msk (0x01UL << GPIO_PORT_MASK7_MASKP30_Pos) /*!< GPIO_PORT MASK7: MASKP30 Mask */\r
-#define GPIO_PORT_MASK7_MASKP31_Pos 31 /*!< GPIO_PORT MASK7: MASKP31 Position */\r
-#define GPIO_PORT_MASK7_MASKP31_Msk (0x01UL << GPIO_PORT_MASK7_MASKP31_Pos) /*!< GPIO_PORT MASK7: MASKP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_PIN0 -----------------------------------------\r
-#define GPIO_PORT_PIN0_PORT0_Pos 0 /*!< GPIO_PORT PIN0: PORT0 Position */\r
-#define GPIO_PORT_PIN0_PORT0_Msk (0x01UL << GPIO_PORT_PIN0_PORT0_Pos) /*!< GPIO_PORT PIN0: PORT0 Mask */\r
-#define GPIO_PORT_PIN0_PORT1_Pos 1 /*!< GPIO_PORT PIN0: PORT1 Position */\r
-#define GPIO_PORT_PIN0_PORT1_Msk (0x01UL << GPIO_PORT_PIN0_PORT1_Pos) /*!< GPIO_PORT PIN0: PORT1 Mask */\r
-#define GPIO_PORT_PIN0_PORT2_Pos 2 /*!< GPIO_PORT PIN0: PORT2 Position */\r
-#define GPIO_PORT_PIN0_PORT2_Msk (0x01UL << GPIO_PORT_PIN0_PORT2_Pos) /*!< GPIO_PORT PIN0: PORT2 Mask */\r
-#define GPIO_PORT_PIN0_PORT3_Pos 3 /*!< GPIO_PORT PIN0: PORT3 Position */\r
-#define GPIO_PORT_PIN0_PORT3_Msk (0x01UL << GPIO_PORT_PIN0_PORT3_Pos) /*!< GPIO_PORT PIN0: PORT3 Mask */\r
-#define GPIO_PORT_PIN0_PORT4_Pos 4 /*!< GPIO_PORT PIN0: PORT4 Position */\r
-#define GPIO_PORT_PIN0_PORT4_Msk (0x01UL << GPIO_PORT_PIN0_PORT4_Pos) /*!< GPIO_PORT PIN0: PORT4 Mask */\r
-#define GPIO_PORT_PIN0_PORT5_Pos 5 /*!< GPIO_PORT PIN0: PORT5 Position */\r
-#define GPIO_PORT_PIN0_PORT5_Msk (0x01UL << GPIO_PORT_PIN0_PORT5_Pos) /*!< GPIO_PORT PIN0: PORT5 Mask */\r
-#define GPIO_PORT_PIN0_PORT6_Pos 6 /*!< GPIO_PORT PIN0: PORT6 Position */\r
-#define GPIO_PORT_PIN0_PORT6_Msk (0x01UL << GPIO_PORT_PIN0_PORT6_Pos) /*!< GPIO_PORT PIN0: PORT6 Mask */\r
-#define GPIO_PORT_PIN0_PORT7_Pos 7 /*!< GPIO_PORT PIN0: PORT7 Position */\r
-#define GPIO_PORT_PIN0_PORT7_Msk (0x01UL << GPIO_PORT_PIN0_PORT7_Pos) /*!< GPIO_PORT PIN0: PORT7 Mask */\r
-#define GPIO_PORT_PIN0_PORT8_Pos 8 /*!< GPIO_PORT PIN0: PORT8 Position */\r
-#define GPIO_PORT_PIN0_PORT8_Msk (0x01UL << GPIO_PORT_PIN0_PORT8_Pos) /*!< GPIO_PORT PIN0: PORT8 Mask */\r
-#define GPIO_PORT_PIN0_PORT9_Pos 9 /*!< GPIO_PORT PIN0: PORT9 Position */\r
-#define GPIO_PORT_PIN0_PORT9_Msk (0x01UL << GPIO_PORT_PIN0_PORT9_Pos) /*!< GPIO_PORT PIN0: PORT9 Mask */\r
-#define GPIO_PORT_PIN0_PORT10_Pos 10 /*!< GPIO_PORT PIN0: PORT10 Position */\r
-#define GPIO_PORT_PIN0_PORT10_Msk (0x01UL << GPIO_PORT_PIN0_PORT10_Pos) /*!< GPIO_PORT PIN0: PORT10 Mask */\r
-#define GPIO_PORT_PIN0_PORT11_Pos 11 /*!< GPIO_PORT PIN0: PORT11 Position */\r
-#define GPIO_PORT_PIN0_PORT11_Msk (0x01UL << GPIO_PORT_PIN0_PORT11_Pos) /*!< GPIO_PORT PIN0: PORT11 Mask */\r
-#define GPIO_PORT_PIN0_PORT12_Pos 12 /*!< GPIO_PORT PIN0: PORT12 Position */\r
-#define GPIO_PORT_PIN0_PORT12_Msk (0x01UL << GPIO_PORT_PIN0_PORT12_Pos) /*!< GPIO_PORT PIN0: PORT12 Mask */\r
-#define GPIO_PORT_PIN0_PORT13_Pos 13 /*!< GPIO_PORT PIN0: PORT13 Position */\r
-#define GPIO_PORT_PIN0_PORT13_Msk (0x01UL << GPIO_PORT_PIN0_PORT13_Pos) /*!< GPIO_PORT PIN0: PORT13 Mask */\r
-#define GPIO_PORT_PIN0_PORT14_Pos 14 /*!< GPIO_PORT PIN0: PORT14 Position */\r
-#define GPIO_PORT_PIN0_PORT14_Msk (0x01UL << GPIO_PORT_PIN0_PORT14_Pos) /*!< GPIO_PORT PIN0: PORT14 Mask */\r
-#define GPIO_PORT_PIN0_PORT15_Pos 15 /*!< GPIO_PORT PIN0: PORT15 Position */\r
-#define GPIO_PORT_PIN0_PORT15_Msk (0x01UL << GPIO_PORT_PIN0_PORT15_Pos) /*!< GPIO_PORT PIN0: PORT15 Mask */\r
-#define GPIO_PORT_PIN0_PORT16_Pos 16 /*!< GPIO_PORT PIN0: PORT16 Position */\r
-#define GPIO_PORT_PIN0_PORT16_Msk (0x01UL << GPIO_PORT_PIN0_PORT16_Pos) /*!< GPIO_PORT PIN0: PORT16 Mask */\r
-#define GPIO_PORT_PIN0_PORT17_Pos 17 /*!< GPIO_PORT PIN0: PORT17 Position */\r
-#define GPIO_PORT_PIN0_PORT17_Msk (0x01UL << GPIO_PORT_PIN0_PORT17_Pos) /*!< GPIO_PORT PIN0: PORT17 Mask */\r
-#define GPIO_PORT_PIN0_PORT18_Pos 18 /*!< GPIO_PORT PIN0: PORT18 Position */\r
-#define GPIO_PORT_PIN0_PORT18_Msk (0x01UL << GPIO_PORT_PIN0_PORT18_Pos) /*!< GPIO_PORT PIN0: PORT18 Mask */\r
-#define GPIO_PORT_PIN0_PORT19_Pos 19 /*!< GPIO_PORT PIN0: PORT19 Position */\r
-#define GPIO_PORT_PIN0_PORT19_Msk (0x01UL << GPIO_PORT_PIN0_PORT19_Pos) /*!< GPIO_PORT PIN0: PORT19 Mask */\r
-#define GPIO_PORT_PIN0_PORT20_Pos 20 /*!< GPIO_PORT PIN0: PORT20 Position */\r
-#define GPIO_PORT_PIN0_PORT20_Msk (0x01UL << GPIO_PORT_PIN0_PORT20_Pos) /*!< GPIO_PORT PIN0: PORT20 Mask */\r
-#define GPIO_PORT_PIN0_PORT21_Pos 21 /*!< GPIO_PORT PIN0: PORT21 Position */\r
-#define GPIO_PORT_PIN0_PORT21_Msk (0x01UL << GPIO_PORT_PIN0_PORT21_Pos) /*!< GPIO_PORT PIN0: PORT21 Mask */\r
-#define GPIO_PORT_PIN0_PORT22_Pos 22 /*!< GPIO_PORT PIN0: PORT22 Position */\r
-#define GPIO_PORT_PIN0_PORT22_Msk (0x01UL << GPIO_PORT_PIN0_PORT22_Pos) /*!< GPIO_PORT PIN0: PORT22 Mask */\r
-#define GPIO_PORT_PIN0_PORT23_Pos 23 /*!< GPIO_PORT PIN0: PORT23 Position */\r
-#define GPIO_PORT_PIN0_PORT23_Msk (0x01UL << GPIO_PORT_PIN0_PORT23_Pos) /*!< GPIO_PORT PIN0: PORT23 Mask */\r
-#define GPIO_PORT_PIN0_PORT24_Pos 24 /*!< GPIO_PORT PIN0: PORT24 Position */\r
-#define GPIO_PORT_PIN0_PORT24_Msk (0x01UL << GPIO_PORT_PIN0_PORT24_Pos) /*!< GPIO_PORT PIN0: PORT24 Mask */\r
-#define GPIO_PORT_PIN0_PORT25_Pos 25 /*!< GPIO_PORT PIN0: PORT25 Position */\r
-#define GPIO_PORT_PIN0_PORT25_Msk (0x01UL << GPIO_PORT_PIN0_PORT25_Pos) /*!< GPIO_PORT PIN0: PORT25 Mask */\r
-#define GPIO_PORT_PIN0_PORT26_Pos 26 /*!< GPIO_PORT PIN0: PORT26 Position */\r
-#define GPIO_PORT_PIN0_PORT26_Msk (0x01UL << GPIO_PORT_PIN0_PORT26_Pos) /*!< GPIO_PORT PIN0: PORT26 Mask */\r
-#define GPIO_PORT_PIN0_PORT27_Pos 27 /*!< GPIO_PORT PIN0: PORT27 Position */\r
-#define GPIO_PORT_PIN0_PORT27_Msk (0x01UL << GPIO_PORT_PIN0_PORT27_Pos) /*!< GPIO_PORT PIN0: PORT27 Mask */\r
-#define GPIO_PORT_PIN0_PORT28_Pos 28 /*!< GPIO_PORT PIN0: PORT28 Position */\r
-#define GPIO_PORT_PIN0_PORT28_Msk (0x01UL << GPIO_PORT_PIN0_PORT28_Pos) /*!< GPIO_PORT PIN0: PORT28 Mask */\r
-#define GPIO_PORT_PIN0_PORT29_Pos 29 /*!< GPIO_PORT PIN0: PORT29 Position */\r
-#define GPIO_PORT_PIN0_PORT29_Msk (0x01UL << GPIO_PORT_PIN0_PORT29_Pos) /*!< GPIO_PORT PIN0: PORT29 Mask */\r
-#define GPIO_PORT_PIN0_PORT30_Pos 30 /*!< GPIO_PORT PIN0: PORT30 Position */\r
-#define GPIO_PORT_PIN0_PORT30_Msk (0x01UL << GPIO_PORT_PIN0_PORT30_Pos) /*!< GPIO_PORT PIN0: PORT30 Mask */\r
-#define GPIO_PORT_PIN0_PORT31_Pos 31 /*!< GPIO_PORT PIN0: PORT31 Position */\r
-#define GPIO_PORT_PIN0_PORT31_Msk (0x01UL << GPIO_PORT_PIN0_PORT31_Pos) /*!< GPIO_PORT PIN0: PORT31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_PIN1 -----------------------------------------\r
-#define GPIO_PORT_PIN1_PORT0_Pos 0 /*!< GPIO_PORT PIN1: PORT0 Position */\r
-#define GPIO_PORT_PIN1_PORT0_Msk (0x01UL << GPIO_PORT_PIN1_PORT0_Pos) /*!< GPIO_PORT PIN1: PORT0 Mask */\r
-#define GPIO_PORT_PIN1_PORT1_Pos 1 /*!< GPIO_PORT PIN1: PORT1 Position */\r
-#define GPIO_PORT_PIN1_PORT1_Msk (0x01UL << GPIO_PORT_PIN1_PORT1_Pos) /*!< GPIO_PORT PIN1: PORT1 Mask */\r
-#define GPIO_PORT_PIN1_PORT2_Pos 2 /*!< GPIO_PORT PIN1: PORT2 Position */\r
-#define GPIO_PORT_PIN1_PORT2_Msk (0x01UL << GPIO_PORT_PIN1_PORT2_Pos) /*!< GPIO_PORT PIN1: PORT2 Mask */\r
-#define GPIO_PORT_PIN1_PORT3_Pos 3 /*!< GPIO_PORT PIN1: PORT3 Position */\r
-#define GPIO_PORT_PIN1_PORT3_Msk (0x01UL << GPIO_PORT_PIN1_PORT3_Pos) /*!< GPIO_PORT PIN1: PORT3 Mask */\r
-#define GPIO_PORT_PIN1_PORT4_Pos 4 /*!< GPIO_PORT PIN1: PORT4 Position */\r
-#define GPIO_PORT_PIN1_PORT4_Msk (0x01UL << GPIO_PORT_PIN1_PORT4_Pos) /*!< GPIO_PORT PIN1: PORT4 Mask */\r
-#define GPIO_PORT_PIN1_PORT5_Pos 5 /*!< GPIO_PORT PIN1: PORT5 Position */\r
-#define GPIO_PORT_PIN1_PORT5_Msk (0x01UL << GPIO_PORT_PIN1_PORT5_Pos) /*!< GPIO_PORT PIN1: PORT5 Mask */\r
-#define GPIO_PORT_PIN1_PORT6_Pos 6 /*!< GPIO_PORT PIN1: PORT6 Position */\r
-#define GPIO_PORT_PIN1_PORT6_Msk (0x01UL << GPIO_PORT_PIN1_PORT6_Pos) /*!< GPIO_PORT PIN1: PORT6 Mask */\r
-#define GPIO_PORT_PIN1_PORT7_Pos 7 /*!< GPIO_PORT PIN1: PORT7 Position */\r
-#define GPIO_PORT_PIN1_PORT7_Msk (0x01UL << GPIO_PORT_PIN1_PORT7_Pos) /*!< GPIO_PORT PIN1: PORT7 Mask */\r
-#define GPIO_PORT_PIN1_PORT8_Pos 8 /*!< GPIO_PORT PIN1: PORT8 Position */\r
-#define GPIO_PORT_PIN1_PORT8_Msk (0x01UL << GPIO_PORT_PIN1_PORT8_Pos) /*!< GPIO_PORT PIN1: PORT8 Mask */\r
-#define GPIO_PORT_PIN1_PORT9_Pos 9 /*!< GPIO_PORT PIN1: PORT9 Position */\r
-#define GPIO_PORT_PIN1_PORT9_Msk (0x01UL << GPIO_PORT_PIN1_PORT9_Pos) /*!< GPIO_PORT PIN1: PORT9 Mask */\r
-#define GPIO_PORT_PIN1_PORT10_Pos 10 /*!< GPIO_PORT PIN1: PORT10 Position */\r
-#define GPIO_PORT_PIN1_PORT10_Msk (0x01UL << GPIO_PORT_PIN1_PORT10_Pos) /*!< GPIO_PORT PIN1: PORT10 Mask */\r
-#define GPIO_PORT_PIN1_PORT11_Pos 11 /*!< GPIO_PORT PIN1: PORT11 Position */\r
-#define GPIO_PORT_PIN1_PORT11_Msk (0x01UL << GPIO_PORT_PIN1_PORT11_Pos) /*!< GPIO_PORT PIN1: PORT11 Mask */\r
-#define GPIO_PORT_PIN1_PORT12_Pos 12 /*!< GPIO_PORT PIN1: PORT12 Position */\r
-#define GPIO_PORT_PIN1_PORT12_Msk (0x01UL << GPIO_PORT_PIN1_PORT12_Pos) /*!< GPIO_PORT PIN1: PORT12 Mask */\r
-#define GPIO_PORT_PIN1_PORT13_Pos 13 /*!< GPIO_PORT PIN1: PORT13 Position */\r
-#define GPIO_PORT_PIN1_PORT13_Msk (0x01UL << GPIO_PORT_PIN1_PORT13_Pos) /*!< GPIO_PORT PIN1: PORT13 Mask */\r
-#define GPIO_PORT_PIN1_PORT14_Pos 14 /*!< GPIO_PORT PIN1: PORT14 Position */\r
-#define GPIO_PORT_PIN1_PORT14_Msk (0x01UL << GPIO_PORT_PIN1_PORT14_Pos) /*!< GPIO_PORT PIN1: PORT14 Mask */\r
-#define GPIO_PORT_PIN1_PORT15_Pos 15 /*!< GPIO_PORT PIN1: PORT15 Position */\r
-#define GPIO_PORT_PIN1_PORT15_Msk (0x01UL << GPIO_PORT_PIN1_PORT15_Pos) /*!< GPIO_PORT PIN1: PORT15 Mask */\r
-#define GPIO_PORT_PIN1_PORT16_Pos 16 /*!< GPIO_PORT PIN1: PORT16 Position */\r
-#define GPIO_PORT_PIN1_PORT16_Msk (0x01UL << GPIO_PORT_PIN1_PORT16_Pos) /*!< GPIO_PORT PIN1: PORT16 Mask */\r
-#define GPIO_PORT_PIN1_PORT17_Pos 17 /*!< GPIO_PORT PIN1: PORT17 Position */\r
-#define GPIO_PORT_PIN1_PORT17_Msk (0x01UL << GPIO_PORT_PIN1_PORT17_Pos) /*!< GPIO_PORT PIN1: PORT17 Mask */\r
-#define GPIO_PORT_PIN1_PORT18_Pos 18 /*!< GPIO_PORT PIN1: PORT18 Position */\r
-#define GPIO_PORT_PIN1_PORT18_Msk (0x01UL << GPIO_PORT_PIN1_PORT18_Pos) /*!< GPIO_PORT PIN1: PORT18 Mask */\r
-#define GPIO_PORT_PIN1_PORT19_Pos 19 /*!< GPIO_PORT PIN1: PORT19 Position */\r
-#define GPIO_PORT_PIN1_PORT19_Msk (0x01UL << GPIO_PORT_PIN1_PORT19_Pos) /*!< GPIO_PORT PIN1: PORT19 Mask */\r
-#define GPIO_PORT_PIN1_PORT20_Pos 20 /*!< GPIO_PORT PIN1: PORT20 Position */\r
-#define GPIO_PORT_PIN1_PORT20_Msk (0x01UL << GPIO_PORT_PIN1_PORT20_Pos) /*!< GPIO_PORT PIN1: PORT20 Mask */\r
-#define GPIO_PORT_PIN1_PORT21_Pos 21 /*!< GPIO_PORT PIN1: PORT21 Position */\r
-#define GPIO_PORT_PIN1_PORT21_Msk (0x01UL << GPIO_PORT_PIN1_PORT21_Pos) /*!< GPIO_PORT PIN1: PORT21 Mask */\r
-#define GPIO_PORT_PIN1_PORT22_Pos 22 /*!< GPIO_PORT PIN1: PORT22 Position */\r
-#define GPIO_PORT_PIN1_PORT22_Msk (0x01UL << GPIO_PORT_PIN1_PORT22_Pos) /*!< GPIO_PORT PIN1: PORT22 Mask */\r
-#define GPIO_PORT_PIN1_PORT23_Pos 23 /*!< GPIO_PORT PIN1: PORT23 Position */\r
-#define GPIO_PORT_PIN1_PORT23_Msk (0x01UL << GPIO_PORT_PIN1_PORT23_Pos) /*!< GPIO_PORT PIN1: PORT23 Mask */\r
-#define GPIO_PORT_PIN1_PORT24_Pos 24 /*!< GPIO_PORT PIN1: PORT24 Position */\r
-#define GPIO_PORT_PIN1_PORT24_Msk (0x01UL << GPIO_PORT_PIN1_PORT24_Pos) /*!< GPIO_PORT PIN1: PORT24 Mask */\r
-#define GPIO_PORT_PIN1_PORT25_Pos 25 /*!< GPIO_PORT PIN1: PORT25 Position */\r
-#define GPIO_PORT_PIN1_PORT25_Msk (0x01UL << GPIO_PORT_PIN1_PORT25_Pos) /*!< GPIO_PORT PIN1: PORT25 Mask */\r
-#define GPIO_PORT_PIN1_PORT26_Pos 26 /*!< GPIO_PORT PIN1: PORT26 Position */\r
-#define GPIO_PORT_PIN1_PORT26_Msk (0x01UL << GPIO_PORT_PIN1_PORT26_Pos) /*!< GPIO_PORT PIN1: PORT26 Mask */\r
-#define GPIO_PORT_PIN1_PORT27_Pos 27 /*!< GPIO_PORT PIN1: PORT27 Position */\r
-#define GPIO_PORT_PIN1_PORT27_Msk (0x01UL << GPIO_PORT_PIN1_PORT27_Pos) /*!< GPIO_PORT PIN1: PORT27 Mask */\r
-#define GPIO_PORT_PIN1_PORT28_Pos 28 /*!< GPIO_PORT PIN1: PORT28 Position */\r
-#define GPIO_PORT_PIN1_PORT28_Msk (0x01UL << GPIO_PORT_PIN1_PORT28_Pos) /*!< GPIO_PORT PIN1: PORT28 Mask */\r
-#define GPIO_PORT_PIN1_PORT29_Pos 29 /*!< GPIO_PORT PIN1: PORT29 Position */\r
-#define GPIO_PORT_PIN1_PORT29_Msk (0x01UL << GPIO_PORT_PIN1_PORT29_Pos) /*!< GPIO_PORT PIN1: PORT29 Mask */\r
-#define GPIO_PORT_PIN1_PORT30_Pos 30 /*!< GPIO_PORT PIN1: PORT30 Position */\r
-#define GPIO_PORT_PIN1_PORT30_Msk (0x01UL << GPIO_PORT_PIN1_PORT30_Pos) /*!< GPIO_PORT PIN1: PORT30 Mask */\r
-#define GPIO_PORT_PIN1_PORT31_Pos 31 /*!< GPIO_PORT PIN1: PORT31 Position */\r
-#define GPIO_PORT_PIN1_PORT31_Msk (0x01UL << GPIO_PORT_PIN1_PORT31_Pos) /*!< GPIO_PORT PIN1: PORT31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_PIN2 -----------------------------------------\r
-#define GPIO_PORT_PIN2_PORT0_Pos 0 /*!< GPIO_PORT PIN2: PORT0 Position */\r
-#define GPIO_PORT_PIN2_PORT0_Msk (0x01UL << GPIO_PORT_PIN2_PORT0_Pos) /*!< GPIO_PORT PIN2: PORT0 Mask */\r
-#define GPIO_PORT_PIN2_PORT1_Pos 1 /*!< GPIO_PORT PIN2: PORT1 Position */\r
-#define GPIO_PORT_PIN2_PORT1_Msk (0x01UL << GPIO_PORT_PIN2_PORT1_Pos) /*!< GPIO_PORT PIN2: PORT1 Mask */\r
-#define GPIO_PORT_PIN2_PORT2_Pos 2 /*!< GPIO_PORT PIN2: PORT2 Position */\r
-#define GPIO_PORT_PIN2_PORT2_Msk (0x01UL << GPIO_PORT_PIN2_PORT2_Pos) /*!< GPIO_PORT PIN2: PORT2 Mask */\r
-#define GPIO_PORT_PIN2_PORT3_Pos 3 /*!< GPIO_PORT PIN2: PORT3 Position */\r
-#define GPIO_PORT_PIN2_PORT3_Msk (0x01UL << GPIO_PORT_PIN2_PORT3_Pos) /*!< GPIO_PORT PIN2: PORT3 Mask */\r
-#define GPIO_PORT_PIN2_PORT4_Pos 4 /*!< GPIO_PORT PIN2: PORT4 Position */\r
-#define GPIO_PORT_PIN2_PORT4_Msk (0x01UL << GPIO_PORT_PIN2_PORT4_Pos) /*!< GPIO_PORT PIN2: PORT4 Mask */\r
-#define GPIO_PORT_PIN2_PORT5_Pos 5 /*!< GPIO_PORT PIN2: PORT5 Position */\r
-#define GPIO_PORT_PIN2_PORT5_Msk (0x01UL << GPIO_PORT_PIN2_PORT5_Pos) /*!< GPIO_PORT PIN2: PORT5 Mask */\r
-#define GPIO_PORT_PIN2_PORT6_Pos 6 /*!< GPIO_PORT PIN2: PORT6 Position */\r
-#define GPIO_PORT_PIN2_PORT6_Msk (0x01UL << GPIO_PORT_PIN2_PORT6_Pos) /*!< GPIO_PORT PIN2: PORT6 Mask */\r
-#define GPIO_PORT_PIN2_PORT7_Pos 7 /*!< GPIO_PORT PIN2: PORT7 Position */\r
-#define GPIO_PORT_PIN2_PORT7_Msk (0x01UL << GPIO_PORT_PIN2_PORT7_Pos) /*!< GPIO_PORT PIN2: PORT7 Mask */\r
-#define GPIO_PORT_PIN2_PORT8_Pos 8 /*!< GPIO_PORT PIN2: PORT8 Position */\r
-#define GPIO_PORT_PIN2_PORT8_Msk (0x01UL << GPIO_PORT_PIN2_PORT8_Pos) /*!< GPIO_PORT PIN2: PORT8 Mask */\r
-#define GPIO_PORT_PIN2_PORT9_Pos 9 /*!< GPIO_PORT PIN2: PORT9 Position */\r
-#define GPIO_PORT_PIN2_PORT9_Msk (0x01UL << GPIO_PORT_PIN2_PORT9_Pos) /*!< GPIO_PORT PIN2: PORT9 Mask */\r
-#define GPIO_PORT_PIN2_PORT10_Pos 10 /*!< GPIO_PORT PIN2: PORT10 Position */\r
-#define GPIO_PORT_PIN2_PORT10_Msk (0x01UL << GPIO_PORT_PIN2_PORT10_Pos) /*!< GPIO_PORT PIN2: PORT10 Mask */\r
-#define GPIO_PORT_PIN2_PORT11_Pos 11 /*!< GPIO_PORT PIN2: PORT11 Position */\r
-#define GPIO_PORT_PIN2_PORT11_Msk (0x01UL << GPIO_PORT_PIN2_PORT11_Pos) /*!< GPIO_PORT PIN2: PORT11 Mask */\r
-#define GPIO_PORT_PIN2_PORT12_Pos 12 /*!< GPIO_PORT PIN2: PORT12 Position */\r
-#define GPIO_PORT_PIN2_PORT12_Msk (0x01UL << GPIO_PORT_PIN2_PORT12_Pos) /*!< GPIO_PORT PIN2: PORT12 Mask */\r
-#define GPIO_PORT_PIN2_PORT13_Pos 13 /*!< GPIO_PORT PIN2: PORT13 Position */\r
-#define GPIO_PORT_PIN2_PORT13_Msk (0x01UL << GPIO_PORT_PIN2_PORT13_Pos) /*!< GPIO_PORT PIN2: PORT13 Mask */\r
-#define GPIO_PORT_PIN2_PORT14_Pos 14 /*!< GPIO_PORT PIN2: PORT14 Position */\r
-#define GPIO_PORT_PIN2_PORT14_Msk (0x01UL << GPIO_PORT_PIN2_PORT14_Pos) /*!< GPIO_PORT PIN2: PORT14 Mask */\r
-#define GPIO_PORT_PIN2_PORT15_Pos 15 /*!< GPIO_PORT PIN2: PORT15 Position */\r
-#define GPIO_PORT_PIN2_PORT15_Msk (0x01UL << GPIO_PORT_PIN2_PORT15_Pos) /*!< GPIO_PORT PIN2: PORT15 Mask */\r
-#define GPIO_PORT_PIN2_PORT16_Pos 16 /*!< GPIO_PORT PIN2: PORT16 Position */\r
-#define GPIO_PORT_PIN2_PORT16_Msk (0x01UL << GPIO_PORT_PIN2_PORT16_Pos) /*!< GPIO_PORT PIN2: PORT16 Mask */\r
-#define GPIO_PORT_PIN2_PORT17_Pos 17 /*!< GPIO_PORT PIN2: PORT17 Position */\r
-#define GPIO_PORT_PIN2_PORT17_Msk (0x01UL << GPIO_PORT_PIN2_PORT17_Pos) /*!< GPIO_PORT PIN2: PORT17 Mask */\r
-#define GPIO_PORT_PIN2_PORT18_Pos 18 /*!< GPIO_PORT PIN2: PORT18 Position */\r
-#define GPIO_PORT_PIN2_PORT18_Msk (0x01UL << GPIO_PORT_PIN2_PORT18_Pos) /*!< GPIO_PORT PIN2: PORT18 Mask */\r
-#define GPIO_PORT_PIN2_PORT19_Pos 19 /*!< GPIO_PORT PIN2: PORT19 Position */\r
-#define GPIO_PORT_PIN2_PORT19_Msk (0x01UL << GPIO_PORT_PIN2_PORT19_Pos) /*!< GPIO_PORT PIN2: PORT19 Mask */\r
-#define GPIO_PORT_PIN2_PORT20_Pos 20 /*!< GPIO_PORT PIN2: PORT20 Position */\r
-#define GPIO_PORT_PIN2_PORT20_Msk (0x01UL << GPIO_PORT_PIN2_PORT20_Pos) /*!< GPIO_PORT PIN2: PORT20 Mask */\r
-#define GPIO_PORT_PIN2_PORT21_Pos 21 /*!< GPIO_PORT PIN2: PORT21 Position */\r
-#define GPIO_PORT_PIN2_PORT21_Msk (0x01UL << GPIO_PORT_PIN2_PORT21_Pos) /*!< GPIO_PORT PIN2: PORT21 Mask */\r
-#define GPIO_PORT_PIN2_PORT22_Pos 22 /*!< GPIO_PORT PIN2: PORT22 Position */\r
-#define GPIO_PORT_PIN2_PORT22_Msk (0x01UL << GPIO_PORT_PIN2_PORT22_Pos) /*!< GPIO_PORT PIN2: PORT22 Mask */\r
-#define GPIO_PORT_PIN2_PORT23_Pos 23 /*!< GPIO_PORT PIN2: PORT23 Position */\r
-#define GPIO_PORT_PIN2_PORT23_Msk (0x01UL << GPIO_PORT_PIN2_PORT23_Pos) /*!< GPIO_PORT PIN2: PORT23 Mask */\r
-#define GPIO_PORT_PIN2_PORT24_Pos 24 /*!< GPIO_PORT PIN2: PORT24 Position */\r
-#define GPIO_PORT_PIN2_PORT24_Msk (0x01UL << GPIO_PORT_PIN2_PORT24_Pos) /*!< GPIO_PORT PIN2: PORT24 Mask */\r
-#define GPIO_PORT_PIN2_PORT25_Pos 25 /*!< GPIO_PORT PIN2: PORT25 Position */\r
-#define GPIO_PORT_PIN2_PORT25_Msk (0x01UL << GPIO_PORT_PIN2_PORT25_Pos) /*!< GPIO_PORT PIN2: PORT25 Mask */\r
-#define GPIO_PORT_PIN2_PORT26_Pos 26 /*!< GPIO_PORT PIN2: PORT26 Position */\r
-#define GPIO_PORT_PIN2_PORT26_Msk (0x01UL << GPIO_PORT_PIN2_PORT26_Pos) /*!< GPIO_PORT PIN2: PORT26 Mask */\r
-#define GPIO_PORT_PIN2_PORT27_Pos 27 /*!< GPIO_PORT PIN2: PORT27 Position */\r
-#define GPIO_PORT_PIN2_PORT27_Msk (0x01UL << GPIO_PORT_PIN2_PORT27_Pos) /*!< GPIO_PORT PIN2: PORT27 Mask */\r
-#define GPIO_PORT_PIN2_PORT28_Pos 28 /*!< GPIO_PORT PIN2: PORT28 Position */\r
-#define GPIO_PORT_PIN2_PORT28_Msk (0x01UL << GPIO_PORT_PIN2_PORT28_Pos) /*!< GPIO_PORT PIN2: PORT28 Mask */\r
-#define GPIO_PORT_PIN2_PORT29_Pos 29 /*!< GPIO_PORT PIN2: PORT29 Position */\r
-#define GPIO_PORT_PIN2_PORT29_Msk (0x01UL << GPIO_PORT_PIN2_PORT29_Pos) /*!< GPIO_PORT PIN2: PORT29 Mask */\r
-#define GPIO_PORT_PIN2_PORT30_Pos 30 /*!< GPIO_PORT PIN2: PORT30 Position */\r
-#define GPIO_PORT_PIN2_PORT30_Msk (0x01UL << GPIO_PORT_PIN2_PORT30_Pos) /*!< GPIO_PORT PIN2: PORT30 Mask */\r
-#define GPIO_PORT_PIN2_PORT31_Pos 31 /*!< GPIO_PORT PIN2: PORT31 Position */\r
-#define GPIO_PORT_PIN2_PORT31_Msk (0x01UL << GPIO_PORT_PIN2_PORT31_Pos) /*!< GPIO_PORT PIN2: PORT31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_PIN3 -----------------------------------------\r
-#define GPIO_PORT_PIN3_PORT0_Pos 0 /*!< GPIO_PORT PIN3: PORT0 Position */\r
-#define GPIO_PORT_PIN3_PORT0_Msk (0x01UL << GPIO_PORT_PIN3_PORT0_Pos) /*!< GPIO_PORT PIN3: PORT0 Mask */\r
-#define GPIO_PORT_PIN3_PORT1_Pos 1 /*!< GPIO_PORT PIN3: PORT1 Position */\r
-#define GPIO_PORT_PIN3_PORT1_Msk (0x01UL << GPIO_PORT_PIN3_PORT1_Pos) /*!< GPIO_PORT PIN3: PORT1 Mask */\r
-#define GPIO_PORT_PIN3_PORT2_Pos 2 /*!< GPIO_PORT PIN3: PORT2 Position */\r
-#define GPIO_PORT_PIN3_PORT2_Msk (0x01UL << GPIO_PORT_PIN3_PORT2_Pos) /*!< GPIO_PORT PIN3: PORT2 Mask */\r
-#define GPIO_PORT_PIN3_PORT3_Pos 3 /*!< GPIO_PORT PIN3: PORT3 Position */\r
-#define GPIO_PORT_PIN3_PORT3_Msk (0x01UL << GPIO_PORT_PIN3_PORT3_Pos) /*!< GPIO_PORT PIN3: PORT3 Mask */\r
-#define GPIO_PORT_PIN3_PORT4_Pos 4 /*!< GPIO_PORT PIN3: PORT4 Position */\r
-#define GPIO_PORT_PIN3_PORT4_Msk (0x01UL << GPIO_PORT_PIN3_PORT4_Pos) /*!< GPIO_PORT PIN3: PORT4 Mask */\r
-#define GPIO_PORT_PIN3_PORT5_Pos 5 /*!< GPIO_PORT PIN3: PORT5 Position */\r
-#define GPIO_PORT_PIN3_PORT5_Msk (0x01UL << GPIO_PORT_PIN3_PORT5_Pos) /*!< GPIO_PORT PIN3: PORT5 Mask */\r
-#define GPIO_PORT_PIN3_PORT6_Pos 6 /*!< GPIO_PORT PIN3: PORT6 Position */\r
-#define GPIO_PORT_PIN3_PORT6_Msk (0x01UL << GPIO_PORT_PIN3_PORT6_Pos) /*!< GPIO_PORT PIN3: PORT6 Mask */\r
-#define GPIO_PORT_PIN3_PORT7_Pos 7 /*!< GPIO_PORT PIN3: PORT7 Position */\r
-#define GPIO_PORT_PIN3_PORT7_Msk (0x01UL << GPIO_PORT_PIN3_PORT7_Pos) /*!< GPIO_PORT PIN3: PORT7 Mask */\r
-#define GPIO_PORT_PIN3_PORT8_Pos 8 /*!< GPIO_PORT PIN3: PORT8 Position */\r
-#define GPIO_PORT_PIN3_PORT8_Msk (0x01UL << GPIO_PORT_PIN3_PORT8_Pos) /*!< GPIO_PORT PIN3: PORT8 Mask */\r
-#define GPIO_PORT_PIN3_PORT9_Pos 9 /*!< GPIO_PORT PIN3: PORT9 Position */\r
-#define GPIO_PORT_PIN3_PORT9_Msk (0x01UL << GPIO_PORT_PIN3_PORT9_Pos) /*!< GPIO_PORT PIN3: PORT9 Mask */\r
-#define GPIO_PORT_PIN3_PORT10_Pos 10 /*!< GPIO_PORT PIN3: PORT10 Position */\r
-#define GPIO_PORT_PIN3_PORT10_Msk (0x01UL << GPIO_PORT_PIN3_PORT10_Pos) /*!< GPIO_PORT PIN3: PORT10 Mask */\r
-#define GPIO_PORT_PIN3_PORT11_Pos 11 /*!< GPIO_PORT PIN3: PORT11 Position */\r
-#define GPIO_PORT_PIN3_PORT11_Msk (0x01UL << GPIO_PORT_PIN3_PORT11_Pos) /*!< GPIO_PORT PIN3: PORT11 Mask */\r
-#define GPIO_PORT_PIN3_PORT12_Pos 12 /*!< GPIO_PORT PIN3: PORT12 Position */\r
-#define GPIO_PORT_PIN3_PORT12_Msk (0x01UL << GPIO_PORT_PIN3_PORT12_Pos) /*!< GPIO_PORT PIN3: PORT12 Mask */\r
-#define GPIO_PORT_PIN3_PORT13_Pos 13 /*!< GPIO_PORT PIN3: PORT13 Position */\r
-#define GPIO_PORT_PIN3_PORT13_Msk (0x01UL << GPIO_PORT_PIN3_PORT13_Pos) /*!< GPIO_PORT PIN3: PORT13 Mask */\r
-#define GPIO_PORT_PIN3_PORT14_Pos 14 /*!< GPIO_PORT PIN3: PORT14 Position */\r
-#define GPIO_PORT_PIN3_PORT14_Msk (0x01UL << GPIO_PORT_PIN3_PORT14_Pos) /*!< GPIO_PORT PIN3: PORT14 Mask */\r
-#define GPIO_PORT_PIN3_PORT15_Pos 15 /*!< GPIO_PORT PIN3: PORT15 Position */\r
-#define GPIO_PORT_PIN3_PORT15_Msk (0x01UL << GPIO_PORT_PIN3_PORT15_Pos) /*!< GPIO_PORT PIN3: PORT15 Mask */\r
-#define GPIO_PORT_PIN3_PORT16_Pos 16 /*!< GPIO_PORT PIN3: PORT16 Position */\r
-#define GPIO_PORT_PIN3_PORT16_Msk (0x01UL << GPIO_PORT_PIN3_PORT16_Pos) /*!< GPIO_PORT PIN3: PORT16 Mask */\r
-#define GPIO_PORT_PIN3_PORT17_Pos 17 /*!< GPIO_PORT PIN3: PORT17 Position */\r
-#define GPIO_PORT_PIN3_PORT17_Msk (0x01UL << GPIO_PORT_PIN3_PORT17_Pos) /*!< GPIO_PORT PIN3: PORT17 Mask */\r
-#define GPIO_PORT_PIN3_PORT18_Pos 18 /*!< GPIO_PORT PIN3: PORT18 Position */\r
-#define GPIO_PORT_PIN3_PORT18_Msk (0x01UL << GPIO_PORT_PIN3_PORT18_Pos) /*!< GPIO_PORT PIN3: PORT18 Mask */\r
-#define GPIO_PORT_PIN3_PORT19_Pos 19 /*!< GPIO_PORT PIN3: PORT19 Position */\r
-#define GPIO_PORT_PIN3_PORT19_Msk (0x01UL << GPIO_PORT_PIN3_PORT19_Pos) /*!< GPIO_PORT PIN3: PORT19 Mask */\r
-#define GPIO_PORT_PIN3_PORT20_Pos 20 /*!< GPIO_PORT PIN3: PORT20 Position */\r
-#define GPIO_PORT_PIN3_PORT20_Msk (0x01UL << GPIO_PORT_PIN3_PORT20_Pos) /*!< GPIO_PORT PIN3: PORT20 Mask */\r
-#define GPIO_PORT_PIN3_PORT21_Pos 21 /*!< GPIO_PORT PIN3: PORT21 Position */\r
-#define GPIO_PORT_PIN3_PORT21_Msk (0x01UL << GPIO_PORT_PIN3_PORT21_Pos) /*!< GPIO_PORT PIN3: PORT21 Mask */\r
-#define GPIO_PORT_PIN3_PORT22_Pos 22 /*!< GPIO_PORT PIN3: PORT22 Position */\r
-#define GPIO_PORT_PIN3_PORT22_Msk (0x01UL << GPIO_PORT_PIN3_PORT22_Pos) /*!< GPIO_PORT PIN3: PORT22 Mask */\r
-#define GPIO_PORT_PIN3_PORT23_Pos 23 /*!< GPIO_PORT PIN3: PORT23 Position */\r
-#define GPIO_PORT_PIN3_PORT23_Msk (0x01UL << GPIO_PORT_PIN3_PORT23_Pos) /*!< GPIO_PORT PIN3: PORT23 Mask */\r
-#define GPIO_PORT_PIN3_PORT24_Pos 24 /*!< GPIO_PORT PIN3: PORT24 Position */\r
-#define GPIO_PORT_PIN3_PORT24_Msk (0x01UL << GPIO_PORT_PIN3_PORT24_Pos) /*!< GPIO_PORT PIN3: PORT24 Mask */\r
-#define GPIO_PORT_PIN3_PORT25_Pos 25 /*!< GPIO_PORT PIN3: PORT25 Position */\r
-#define GPIO_PORT_PIN3_PORT25_Msk (0x01UL << GPIO_PORT_PIN3_PORT25_Pos) /*!< GPIO_PORT PIN3: PORT25 Mask */\r
-#define GPIO_PORT_PIN3_PORT26_Pos 26 /*!< GPIO_PORT PIN3: PORT26 Position */\r
-#define GPIO_PORT_PIN3_PORT26_Msk (0x01UL << GPIO_PORT_PIN3_PORT26_Pos) /*!< GPIO_PORT PIN3: PORT26 Mask */\r
-#define GPIO_PORT_PIN3_PORT27_Pos 27 /*!< GPIO_PORT PIN3: PORT27 Position */\r
-#define GPIO_PORT_PIN3_PORT27_Msk (0x01UL << GPIO_PORT_PIN3_PORT27_Pos) /*!< GPIO_PORT PIN3: PORT27 Mask */\r
-#define GPIO_PORT_PIN3_PORT28_Pos 28 /*!< GPIO_PORT PIN3: PORT28 Position */\r
-#define GPIO_PORT_PIN3_PORT28_Msk (0x01UL << GPIO_PORT_PIN3_PORT28_Pos) /*!< GPIO_PORT PIN3: PORT28 Mask */\r
-#define GPIO_PORT_PIN3_PORT29_Pos 29 /*!< GPIO_PORT PIN3: PORT29 Position */\r
-#define GPIO_PORT_PIN3_PORT29_Msk (0x01UL << GPIO_PORT_PIN3_PORT29_Pos) /*!< GPIO_PORT PIN3: PORT29 Mask */\r
-#define GPIO_PORT_PIN3_PORT30_Pos 30 /*!< GPIO_PORT PIN3: PORT30 Position */\r
-#define GPIO_PORT_PIN3_PORT30_Msk (0x01UL << GPIO_PORT_PIN3_PORT30_Pos) /*!< GPIO_PORT PIN3: PORT30 Mask */\r
-#define GPIO_PORT_PIN3_PORT31_Pos 31 /*!< GPIO_PORT PIN3: PORT31 Position */\r
-#define GPIO_PORT_PIN3_PORT31_Msk (0x01UL << GPIO_PORT_PIN3_PORT31_Pos) /*!< GPIO_PORT PIN3: PORT31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_PIN4 -----------------------------------------\r
-#define GPIO_PORT_PIN4_PORT0_Pos 0 /*!< GPIO_PORT PIN4: PORT0 Position */\r
-#define GPIO_PORT_PIN4_PORT0_Msk (0x01UL << GPIO_PORT_PIN4_PORT0_Pos) /*!< GPIO_PORT PIN4: PORT0 Mask */\r
-#define GPIO_PORT_PIN4_PORT1_Pos 1 /*!< GPIO_PORT PIN4: PORT1 Position */\r
-#define GPIO_PORT_PIN4_PORT1_Msk (0x01UL << GPIO_PORT_PIN4_PORT1_Pos) /*!< GPIO_PORT PIN4: PORT1 Mask */\r
-#define GPIO_PORT_PIN4_PORT2_Pos 2 /*!< GPIO_PORT PIN4: PORT2 Position */\r
-#define GPIO_PORT_PIN4_PORT2_Msk (0x01UL << GPIO_PORT_PIN4_PORT2_Pos) /*!< GPIO_PORT PIN4: PORT2 Mask */\r
-#define GPIO_PORT_PIN4_PORT3_Pos 3 /*!< GPIO_PORT PIN4: PORT3 Position */\r
-#define GPIO_PORT_PIN4_PORT3_Msk (0x01UL << GPIO_PORT_PIN4_PORT3_Pos) /*!< GPIO_PORT PIN4: PORT3 Mask */\r
-#define GPIO_PORT_PIN4_PORT4_Pos 4 /*!< GPIO_PORT PIN4: PORT4 Position */\r
-#define GPIO_PORT_PIN4_PORT4_Msk (0x01UL << GPIO_PORT_PIN4_PORT4_Pos) /*!< GPIO_PORT PIN4: PORT4 Mask */\r
-#define GPIO_PORT_PIN4_PORT5_Pos 5 /*!< GPIO_PORT PIN4: PORT5 Position */\r
-#define GPIO_PORT_PIN4_PORT5_Msk (0x01UL << GPIO_PORT_PIN4_PORT5_Pos) /*!< GPIO_PORT PIN4: PORT5 Mask */\r
-#define GPIO_PORT_PIN4_PORT6_Pos 6 /*!< GPIO_PORT PIN4: PORT6 Position */\r
-#define GPIO_PORT_PIN4_PORT6_Msk (0x01UL << GPIO_PORT_PIN4_PORT6_Pos) /*!< GPIO_PORT PIN4: PORT6 Mask */\r
-#define GPIO_PORT_PIN4_PORT7_Pos 7 /*!< GPIO_PORT PIN4: PORT7 Position */\r
-#define GPIO_PORT_PIN4_PORT7_Msk (0x01UL << GPIO_PORT_PIN4_PORT7_Pos) /*!< GPIO_PORT PIN4: PORT7 Mask */\r
-#define GPIO_PORT_PIN4_PORT8_Pos 8 /*!< GPIO_PORT PIN4: PORT8 Position */\r
-#define GPIO_PORT_PIN4_PORT8_Msk (0x01UL << GPIO_PORT_PIN4_PORT8_Pos) /*!< GPIO_PORT PIN4: PORT8 Mask */\r
-#define GPIO_PORT_PIN4_PORT9_Pos 9 /*!< GPIO_PORT PIN4: PORT9 Position */\r
-#define GPIO_PORT_PIN4_PORT9_Msk (0x01UL << GPIO_PORT_PIN4_PORT9_Pos) /*!< GPIO_PORT PIN4: PORT9 Mask */\r
-#define GPIO_PORT_PIN4_PORT10_Pos 10 /*!< GPIO_PORT PIN4: PORT10 Position */\r
-#define GPIO_PORT_PIN4_PORT10_Msk (0x01UL << GPIO_PORT_PIN4_PORT10_Pos) /*!< GPIO_PORT PIN4: PORT10 Mask */\r
-#define GPIO_PORT_PIN4_PORT11_Pos 11 /*!< GPIO_PORT PIN4: PORT11 Position */\r
-#define GPIO_PORT_PIN4_PORT11_Msk (0x01UL << GPIO_PORT_PIN4_PORT11_Pos) /*!< GPIO_PORT PIN4: PORT11 Mask */\r
-#define GPIO_PORT_PIN4_PORT12_Pos 12 /*!< GPIO_PORT PIN4: PORT12 Position */\r
-#define GPIO_PORT_PIN4_PORT12_Msk (0x01UL << GPIO_PORT_PIN4_PORT12_Pos) /*!< GPIO_PORT PIN4: PORT12 Mask */\r
-#define GPIO_PORT_PIN4_PORT13_Pos 13 /*!< GPIO_PORT PIN4: PORT13 Position */\r
-#define GPIO_PORT_PIN4_PORT13_Msk (0x01UL << GPIO_PORT_PIN4_PORT13_Pos) /*!< GPIO_PORT PIN4: PORT13 Mask */\r
-#define GPIO_PORT_PIN4_PORT14_Pos 14 /*!< GPIO_PORT PIN4: PORT14 Position */\r
-#define GPIO_PORT_PIN4_PORT14_Msk (0x01UL << GPIO_PORT_PIN4_PORT14_Pos) /*!< GPIO_PORT PIN4: PORT14 Mask */\r
-#define GPIO_PORT_PIN4_PORT15_Pos 15 /*!< GPIO_PORT PIN4: PORT15 Position */\r
-#define GPIO_PORT_PIN4_PORT15_Msk (0x01UL << GPIO_PORT_PIN4_PORT15_Pos) /*!< GPIO_PORT PIN4: PORT15 Mask */\r
-#define GPIO_PORT_PIN4_PORT16_Pos 16 /*!< GPIO_PORT PIN4: PORT16 Position */\r
-#define GPIO_PORT_PIN4_PORT16_Msk (0x01UL << GPIO_PORT_PIN4_PORT16_Pos) /*!< GPIO_PORT PIN4: PORT16 Mask */\r
-#define GPIO_PORT_PIN4_PORT17_Pos 17 /*!< GPIO_PORT PIN4: PORT17 Position */\r
-#define GPIO_PORT_PIN4_PORT17_Msk (0x01UL << GPIO_PORT_PIN4_PORT17_Pos) /*!< GPIO_PORT PIN4: PORT17 Mask */\r
-#define GPIO_PORT_PIN4_PORT18_Pos 18 /*!< GPIO_PORT PIN4: PORT18 Position */\r
-#define GPIO_PORT_PIN4_PORT18_Msk (0x01UL << GPIO_PORT_PIN4_PORT18_Pos) /*!< GPIO_PORT PIN4: PORT18 Mask */\r
-#define GPIO_PORT_PIN4_PORT19_Pos 19 /*!< GPIO_PORT PIN4: PORT19 Position */\r
-#define GPIO_PORT_PIN4_PORT19_Msk (0x01UL << GPIO_PORT_PIN4_PORT19_Pos) /*!< GPIO_PORT PIN4: PORT19 Mask */\r
-#define GPIO_PORT_PIN4_PORT20_Pos 20 /*!< GPIO_PORT PIN4: PORT20 Position */\r
-#define GPIO_PORT_PIN4_PORT20_Msk (0x01UL << GPIO_PORT_PIN4_PORT20_Pos) /*!< GPIO_PORT PIN4: PORT20 Mask */\r
-#define GPIO_PORT_PIN4_PORT21_Pos 21 /*!< GPIO_PORT PIN4: PORT21 Position */\r
-#define GPIO_PORT_PIN4_PORT21_Msk (0x01UL << GPIO_PORT_PIN4_PORT21_Pos) /*!< GPIO_PORT PIN4: PORT21 Mask */\r
-#define GPIO_PORT_PIN4_PORT22_Pos 22 /*!< GPIO_PORT PIN4: PORT22 Position */\r
-#define GPIO_PORT_PIN4_PORT22_Msk (0x01UL << GPIO_PORT_PIN4_PORT22_Pos) /*!< GPIO_PORT PIN4: PORT22 Mask */\r
-#define GPIO_PORT_PIN4_PORT23_Pos 23 /*!< GPIO_PORT PIN4: PORT23 Position */\r
-#define GPIO_PORT_PIN4_PORT23_Msk (0x01UL << GPIO_PORT_PIN4_PORT23_Pos) /*!< GPIO_PORT PIN4: PORT23 Mask */\r
-#define GPIO_PORT_PIN4_PORT24_Pos 24 /*!< GPIO_PORT PIN4: PORT24 Position */\r
-#define GPIO_PORT_PIN4_PORT24_Msk (0x01UL << GPIO_PORT_PIN4_PORT24_Pos) /*!< GPIO_PORT PIN4: PORT24 Mask */\r
-#define GPIO_PORT_PIN4_PORT25_Pos 25 /*!< GPIO_PORT PIN4: PORT25 Position */\r
-#define GPIO_PORT_PIN4_PORT25_Msk (0x01UL << GPIO_PORT_PIN4_PORT25_Pos) /*!< GPIO_PORT PIN4: PORT25 Mask */\r
-#define GPIO_PORT_PIN4_PORT26_Pos 26 /*!< GPIO_PORT PIN4: PORT26 Position */\r
-#define GPIO_PORT_PIN4_PORT26_Msk (0x01UL << GPIO_PORT_PIN4_PORT26_Pos) /*!< GPIO_PORT PIN4: PORT26 Mask */\r
-#define GPIO_PORT_PIN4_PORT27_Pos 27 /*!< GPIO_PORT PIN4: PORT27 Position */\r
-#define GPIO_PORT_PIN4_PORT27_Msk (0x01UL << GPIO_PORT_PIN4_PORT27_Pos) /*!< GPIO_PORT PIN4: PORT27 Mask */\r
-#define GPIO_PORT_PIN4_PORT28_Pos 28 /*!< GPIO_PORT PIN4: PORT28 Position */\r
-#define GPIO_PORT_PIN4_PORT28_Msk (0x01UL << GPIO_PORT_PIN4_PORT28_Pos) /*!< GPIO_PORT PIN4: PORT28 Mask */\r
-#define GPIO_PORT_PIN4_PORT29_Pos 29 /*!< GPIO_PORT PIN4: PORT29 Position */\r
-#define GPIO_PORT_PIN4_PORT29_Msk (0x01UL << GPIO_PORT_PIN4_PORT29_Pos) /*!< GPIO_PORT PIN4: PORT29 Mask */\r
-#define GPIO_PORT_PIN4_PORT30_Pos 30 /*!< GPIO_PORT PIN4: PORT30 Position */\r
-#define GPIO_PORT_PIN4_PORT30_Msk (0x01UL << GPIO_PORT_PIN4_PORT30_Pos) /*!< GPIO_PORT PIN4: PORT30 Mask */\r
-#define GPIO_PORT_PIN4_PORT31_Pos 31 /*!< GPIO_PORT PIN4: PORT31 Position */\r
-#define GPIO_PORT_PIN4_PORT31_Msk (0x01UL << GPIO_PORT_PIN4_PORT31_Pos) /*!< GPIO_PORT PIN4: PORT31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_PIN5 -----------------------------------------\r
-#define GPIO_PORT_PIN5_PORT0_Pos 0 /*!< GPIO_PORT PIN5: PORT0 Position */\r
-#define GPIO_PORT_PIN5_PORT0_Msk (0x01UL << GPIO_PORT_PIN5_PORT0_Pos) /*!< GPIO_PORT PIN5: PORT0 Mask */\r
-#define GPIO_PORT_PIN5_PORT1_Pos 1 /*!< GPIO_PORT PIN5: PORT1 Position */\r
-#define GPIO_PORT_PIN5_PORT1_Msk (0x01UL << GPIO_PORT_PIN5_PORT1_Pos) /*!< GPIO_PORT PIN5: PORT1 Mask */\r
-#define GPIO_PORT_PIN5_PORT2_Pos 2 /*!< GPIO_PORT PIN5: PORT2 Position */\r
-#define GPIO_PORT_PIN5_PORT2_Msk (0x01UL << GPIO_PORT_PIN5_PORT2_Pos) /*!< GPIO_PORT PIN5: PORT2 Mask */\r
-#define GPIO_PORT_PIN5_PORT3_Pos 3 /*!< GPIO_PORT PIN5: PORT3 Position */\r
-#define GPIO_PORT_PIN5_PORT3_Msk (0x01UL << GPIO_PORT_PIN5_PORT3_Pos) /*!< GPIO_PORT PIN5: PORT3 Mask */\r
-#define GPIO_PORT_PIN5_PORT4_Pos 4 /*!< GPIO_PORT PIN5: PORT4 Position */\r
-#define GPIO_PORT_PIN5_PORT4_Msk (0x01UL << GPIO_PORT_PIN5_PORT4_Pos) /*!< GPIO_PORT PIN5: PORT4 Mask */\r
-#define GPIO_PORT_PIN5_PORT5_Pos 5 /*!< GPIO_PORT PIN5: PORT5 Position */\r
-#define GPIO_PORT_PIN5_PORT5_Msk (0x01UL << GPIO_PORT_PIN5_PORT5_Pos) /*!< GPIO_PORT PIN5: PORT5 Mask */\r
-#define GPIO_PORT_PIN5_PORT6_Pos 6 /*!< GPIO_PORT PIN5: PORT6 Position */\r
-#define GPIO_PORT_PIN5_PORT6_Msk (0x01UL << GPIO_PORT_PIN5_PORT6_Pos) /*!< GPIO_PORT PIN5: PORT6 Mask */\r
-#define GPIO_PORT_PIN5_PORT7_Pos 7 /*!< GPIO_PORT PIN5: PORT7 Position */\r
-#define GPIO_PORT_PIN5_PORT7_Msk (0x01UL << GPIO_PORT_PIN5_PORT7_Pos) /*!< GPIO_PORT PIN5: PORT7 Mask */\r
-#define GPIO_PORT_PIN5_PORT8_Pos 8 /*!< GPIO_PORT PIN5: PORT8 Position */\r
-#define GPIO_PORT_PIN5_PORT8_Msk (0x01UL << GPIO_PORT_PIN5_PORT8_Pos) /*!< GPIO_PORT PIN5: PORT8 Mask */\r
-#define GPIO_PORT_PIN5_PORT9_Pos 9 /*!< GPIO_PORT PIN5: PORT9 Position */\r
-#define GPIO_PORT_PIN5_PORT9_Msk (0x01UL << GPIO_PORT_PIN5_PORT9_Pos) /*!< GPIO_PORT PIN5: PORT9 Mask */\r
-#define GPIO_PORT_PIN5_PORT10_Pos 10 /*!< GPIO_PORT PIN5: PORT10 Position */\r
-#define GPIO_PORT_PIN5_PORT10_Msk (0x01UL << GPIO_PORT_PIN5_PORT10_Pos) /*!< GPIO_PORT PIN5: PORT10 Mask */\r
-#define GPIO_PORT_PIN5_PORT11_Pos 11 /*!< GPIO_PORT PIN5: PORT11 Position */\r
-#define GPIO_PORT_PIN5_PORT11_Msk (0x01UL << GPIO_PORT_PIN5_PORT11_Pos) /*!< GPIO_PORT PIN5: PORT11 Mask */\r
-#define GPIO_PORT_PIN5_PORT12_Pos 12 /*!< GPIO_PORT PIN5: PORT12 Position */\r
-#define GPIO_PORT_PIN5_PORT12_Msk (0x01UL << GPIO_PORT_PIN5_PORT12_Pos) /*!< GPIO_PORT PIN5: PORT12 Mask */\r
-#define GPIO_PORT_PIN5_PORT13_Pos 13 /*!< GPIO_PORT PIN5: PORT13 Position */\r
-#define GPIO_PORT_PIN5_PORT13_Msk (0x01UL << GPIO_PORT_PIN5_PORT13_Pos) /*!< GPIO_PORT PIN5: PORT13 Mask */\r
-#define GPIO_PORT_PIN5_PORT14_Pos 14 /*!< GPIO_PORT PIN5: PORT14 Position */\r
-#define GPIO_PORT_PIN5_PORT14_Msk (0x01UL << GPIO_PORT_PIN5_PORT14_Pos) /*!< GPIO_PORT PIN5: PORT14 Mask */\r
-#define GPIO_PORT_PIN5_PORT15_Pos 15 /*!< GPIO_PORT PIN5: PORT15 Position */\r
-#define GPIO_PORT_PIN5_PORT15_Msk (0x01UL << GPIO_PORT_PIN5_PORT15_Pos) /*!< GPIO_PORT PIN5: PORT15 Mask */\r
-#define GPIO_PORT_PIN5_PORT16_Pos 16 /*!< GPIO_PORT PIN5: PORT16 Position */\r
-#define GPIO_PORT_PIN5_PORT16_Msk (0x01UL << GPIO_PORT_PIN5_PORT16_Pos) /*!< GPIO_PORT PIN5: PORT16 Mask */\r
-#define GPIO_PORT_PIN5_PORT17_Pos 17 /*!< GPIO_PORT PIN5: PORT17 Position */\r
-#define GPIO_PORT_PIN5_PORT17_Msk (0x01UL << GPIO_PORT_PIN5_PORT17_Pos) /*!< GPIO_PORT PIN5: PORT17 Mask */\r
-#define GPIO_PORT_PIN5_PORT18_Pos 18 /*!< GPIO_PORT PIN5: PORT18 Position */\r
-#define GPIO_PORT_PIN5_PORT18_Msk (0x01UL << GPIO_PORT_PIN5_PORT18_Pos) /*!< GPIO_PORT PIN5: PORT18 Mask */\r
-#define GPIO_PORT_PIN5_PORT19_Pos 19 /*!< GPIO_PORT PIN5: PORT19 Position */\r
-#define GPIO_PORT_PIN5_PORT19_Msk (0x01UL << GPIO_PORT_PIN5_PORT19_Pos) /*!< GPIO_PORT PIN5: PORT19 Mask */\r
-#define GPIO_PORT_PIN5_PORT20_Pos 20 /*!< GPIO_PORT PIN5: PORT20 Position */\r
-#define GPIO_PORT_PIN5_PORT20_Msk (0x01UL << GPIO_PORT_PIN5_PORT20_Pos) /*!< GPIO_PORT PIN5: PORT20 Mask */\r
-#define GPIO_PORT_PIN5_PORT21_Pos 21 /*!< GPIO_PORT PIN5: PORT21 Position */\r
-#define GPIO_PORT_PIN5_PORT21_Msk (0x01UL << GPIO_PORT_PIN5_PORT21_Pos) /*!< GPIO_PORT PIN5: PORT21 Mask */\r
-#define GPIO_PORT_PIN5_PORT22_Pos 22 /*!< GPIO_PORT PIN5: PORT22 Position */\r
-#define GPIO_PORT_PIN5_PORT22_Msk (0x01UL << GPIO_PORT_PIN5_PORT22_Pos) /*!< GPIO_PORT PIN5: PORT22 Mask */\r
-#define GPIO_PORT_PIN5_PORT23_Pos 23 /*!< GPIO_PORT PIN5: PORT23 Position */\r
-#define GPIO_PORT_PIN5_PORT23_Msk (0x01UL << GPIO_PORT_PIN5_PORT23_Pos) /*!< GPIO_PORT PIN5: PORT23 Mask */\r
-#define GPIO_PORT_PIN5_PORT24_Pos 24 /*!< GPIO_PORT PIN5: PORT24 Position */\r
-#define GPIO_PORT_PIN5_PORT24_Msk (0x01UL << GPIO_PORT_PIN5_PORT24_Pos) /*!< GPIO_PORT PIN5: PORT24 Mask */\r
-#define GPIO_PORT_PIN5_PORT25_Pos 25 /*!< GPIO_PORT PIN5: PORT25 Position */\r
-#define GPIO_PORT_PIN5_PORT25_Msk (0x01UL << GPIO_PORT_PIN5_PORT25_Pos) /*!< GPIO_PORT PIN5: PORT25 Mask */\r
-#define GPIO_PORT_PIN5_PORT26_Pos 26 /*!< GPIO_PORT PIN5: PORT26 Position */\r
-#define GPIO_PORT_PIN5_PORT26_Msk (0x01UL << GPIO_PORT_PIN5_PORT26_Pos) /*!< GPIO_PORT PIN5: PORT26 Mask */\r
-#define GPIO_PORT_PIN5_PORT27_Pos 27 /*!< GPIO_PORT PIN5: PORT27 Position */\r
-#define GPIO_PORT_PIN5_PORT27_Msk (0x01UL << GPIO_PORT_PIN5_PORT27_Pos) /*!< GPIO_PORT PIN5: PORT27 Mask */\r
-#define GPIO_PORT_PIN5_PORT28_Pos 28 /*!< GPIO_PORT PIN5: PORT28 Position */\r
-#define GPIO_PORT_PIN5_PORT28_Msk (0x01UL << GPIO_PORT_PIN5_PORT28_Pos) /*!< GPIO_PORT PIN5: PORT28 Mask */\r
-#define GPIO_PORT_PIN5_PORT29_Pos 29 /*!< GPIO_PORT PIN5: PORT29 Position */\r
-#define GPIO_PORT_PIN5_PORT29_Msk (0x01UL << GPIO_PORT_PIN5_PORT29_Pos) /*!< GPIO_PORT PIN5: PORT29 Mask */\r
-#define GPIO_PORT_PIN5_PORT30_Pos 30 /*!< GPIO_PORT PIN5: PORT30 Position */\r
-#define GPIO_PORT_PIN5_PORT30_Msk (0x01UL << GPIO_PORT_PIN5_PORT30_Pos) /*!< GPIO_PORT PIN5: PORT30 Mask */\r
-#define GPIO_PORT_PIN5_PORT31_Pos 31 /*!< GPIO_PORT PIN5: PORT31 Position */\r
-#define GPIO_PORT_PIN5_PORT31_Msk (0x01UL << GPIO_PORT_PIN5_PORT31_Pos) /*!< GPIO_PORT PIN5: PORT31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_PIN6 -----------------------------------------\r
-#define GPIO_PORT_PIN6_PORT0_Pos 0 /*!< GPIO_PORT PIN6: PORT0 Position */\r
-#define GPIO_PORT_PIN6_PORT0_Msk (0x01UL << GPIO_PORT_PIN6_PORT0_Pos) /*!< GPIO_PORT PIN6: PORT0 Mask */\r
-#define GPIO_PORT_PIN6_PORT1_Pos 1 /*!< GPIO_PORT PIN6: PORT1 Position */\r
-#define GPIO_PORT_PIN6_PORT1_Msk (0x01UL << GPIO_PORT_PIN6_PORT1_Pos) /*!< GPIO_PORT PIN6: PORT1 Mask */\r
-#define GPIO_PORT_PIN6_PORT2_Pos 2 /*!< GPIO_PORT PIN6: PORT2 Position */\r
-#define GPIO_PORT_PIN6_PORT2_Msk (0x01UL << GPIO_PORT_PIN6_PORT2_Pos) /*!< GPIO_PORT PIN6: PORT2 Mask */\r
-#define GPIO_PORT_PIN6_PORT3_Pos 3 /*!< GPIO_PORT PIN6: PORT3 Position */\r
-#define GPIO_PORT_PIN6_PORT3_Msk (0x01UL << GPIO_PORT_PIN6_PORT3_Pos) /*!< GPIO_PORT PIN6: PORT3 Mask */\r
-#define GPIO_PORT_PIN6_PORT4_Pos 4 /*!< GPIO_PORT PIN6: PORT4 Position */\r
-#define GPIO_PORT_PIN6_PORT4_Msk (0x01UL << GPIO_PORT_PIN6_PORT4_Pos) /*!< GPIO_PORT PIN6: PORT4 Mask */\r
-#define GPIO_PORT_PIN6_PORT5_Pos 5 /*!< GPIO_PORT PIN6: PORT5 Position */\r
-#define GPIO_PORT_PIN6_PORT5_Msk (0x01UL << GPIO_PORT_PIN6_PORT5_Pos) /*!< GPIO_PORT PIN6: PORT5 Mask */\r
-#define GPIO_PORT_PIN6_PORT6_Pos 6 /*!< GPIO_PORT PIN6: PORT6 Position */\r
-#define GPIO_PORT_PIN6_PORT6_Msk (0x01UL << GPIO_PORT_PIN6_PORT6_Pos) /*!< GPIO_PORT PIN6: PORT6 Mask */\r
-#define GPIO_PORT_PIN6_PORT7_Pos 7 /*!< GPIO_PORT PIN6: PORT7 Position */\r
-#define GPIO_PORT_PIN6_PORT7_Msk (0x01UL << GPIO_PORT_PIN6_PORT7_Pos) /*!< GPIO_PORT PIN6: PORT7 Mask */\r
-#define GPIO_PORT_PIN6_PORT8_Pos 8 /*!< GPIO_PORT PIN6: PORT8 Position */\r
-#define GPIO_PORT_PIN6_PORT8_Msk (0x01UL << GPIO_PORT_PIN6_PORT8_Pos) /*!< GPIO_PORT PIN6: PORT8 Mask */\r
-#define GPIO_PORT_PIN6_PORT9_Pos 9 /*!< GPIO_PORT PIN6: PORT9 Position */\r
-#define GPIO_PORT_PIN6_PORT9_Msk (0x01UL << GPIO_PORT_PIN6_PORT9_Pos) /*!< GPIO_PORT PIN6: PORT9 Mask */\r
-#define GPIO_PORT_PIN6_PORT10_Pos 10 /*!< GPIO_PORT PIN6: PORT10 Position */\r
-#define GPIO_PORT_PIN6_PORT10_Msk (0x01UL << GPIO_PORT_PIN6_PORT10_Pos) /*!< GPIO_PORT PIN6: PORT10 Mask */\r
-#define GPIO_PORT_PIN6_PORT11_Pos 11 /*!< GPIO_PORT PIN6: PORT11 Position */\r
-#define GPIO_PORT_PIN6_PORT11_Msk (0x01UL << GPIO_PORT_PIN6_PORT11_Pos) /*!< GPIO_PORT PIN6: PORT11 Mask */\r
-#define GPIO_PORT_PIN6_PORT12_Pos 12 /*!< GPIO_PORT PIN6: PORT12 Position */\r
-#define GPIO_PORT_PIN6_PORT12_Msk (0x01UL << GPIO_PORT_PIN6_PORT12_Pos) /*!< GPIO_PORT PIN6: PORT12 Mask */\r
-#define GPIO_PORT_PIN6_PORT13_Pos 13 /*!< GPIO_PORT PIN6: PORT13 Position */\r
-#define GPIO_PORT_PIN6_PORT13_Msk (0x01UL << GPIO_PORT_PIN6_PORT13_Pos) /*!< GPIO_PORT PIN6: PORT13 Mask */\r
-#define GPIO_PORT_PIN6_PORT14_Pos 14 /*!< GPIO_PORT PIN6: PORT14 Position */\r
-#define GPIO_PORT_PIN6_PORT14_Msk (0x01UL << GPIO_PORT_PIN6_PORT14_Pos) /*!< GPIO_PORT PIN6: PORT14 Mask */\r
-#define GPIO_PORT_PIN6_PORT15_Pos 15 /*!< GPIO_PORT PIN6: PORT15 Position */\r
-#define GPIO_PORT_PIN6_PORT15_Msk (0x01UL << GPIO_PORT_PIN6_PORT15_Pos) /*!< GPIO_PORT PIN6: PORT15 Mask */\r
-#define GPIO_PORT_PIN6_PORT16_Pos 16 /*!< GPIO_PORT PIN6: PORT16 Position */\r
-#define GPIO_PORT_PIN6_PORT16_Msk (0x01UL << GPIO_PORT_PIN6_PORT16_Pos) /*!< GPIO_PORT PIN6: PORT16 Mask */\r
-#define GPIO_PORT_PIN6_PORT17_Pos 17 /*!< GPIO_PORT PIN6: PORT17 Position */\r
-#define GPIO_PORT_PIN6_PORT17_Msk (0x01UL << GPIO_PORT_PIN6_PORT17_Pos) /*!< GPIO_PORT PIN6: PORT17 Mask */\r
-#define GPIO_PORT_PIN6_PORT18_Pos 18 /*!< GPIO_PORT PIN6: PORT18 Position */\r
-#define GPIO_PORT_PIN6_PORT18_Msk (0x01UL << GPIO_PORT_PIN6_PORT18_Pos) /*!< GPIO_PORT PIN6: PORT18 Mask */\r
-#define GPIO_PORT_PIN6_PORT19_Pos 19 /*!< GPIO_PORT PIN6: PORT19 Position */\r
-#define GPIO_PORT_PIN6_PORT19_Msk (0x01UL << GPIO_PORT_PIN6_PORT19_Pos) /*!< GPIO_PORT PIN6: PORT19 Mask */\r
-#define GPIO_PORT_PIN6_PORT20_Pos 20 /*!< GPIO_PORT PIN6: PORT20 Position */\r
-#define GPIO_PORT_PIN6_PORT20_Msk (0x01UL << GPIO_PORT_PIN6_PORT20_Pos) /*!< GPIO_PORT PIN6: PORT20 Mask */\r
-#define GPIO_PORT_PIN6_PORT21_Pos 21 /*!< GPIO_PORT PIN6: PORT21 Position */\r
-#define GPIO_PORT_PIN6_PORT21_Msk (0x01UL << GPIO_PORT_PIN6_PORT21_Pos) /*!< GPIO_PORT PIN6: PORT21 Mask */\r
-#define GPIO_PORT_PIN6_PORT22_Pos 22 /*!< GPIO_PORT PIN6: PORT22 Position */\r
-#define GPIO_PORT_PIN6_PORT22_Msk (0x01UL << GPIO_PORT_PIN6_PORT22_Pos) /*!< GPIO_PORT PIN6: PORT22 Mask */\r
-#define GPIO_PORT_PIN6_PORT23_Pos 23 /*!< GPIO_PORT PIN6: PORT23 Position */\r
-#define GPIO_PORT_PIN6_PORT23_Msk (0x01UL << GPIO_PORT_PIN6_PORT23_Pos) /*!< GPIO_PORT PIN6: PORT23 Mask */\r
-#define GPIO_PORT_PIN6_PORT24_Pos 24 /*!< GPIO_PORT PIN6: PORT24 Position */\r
-#define GPIO_PORT_PIN6_PORT24_Msk (0x01UL << GPIO_PORT_PIN6_PORT24_Pos) /*!< GPIO_PORT PIN6: PORT24 Mask */\r
-#define GPIO_PORT_PIN6_PORT25_Pos 25 /*!< GPIO_PORT PIN6: PORT25 Position */\r
-#define GPIO_PORT_PIN6_PORT25_Msk (0x01UL << GPIO_PORT_PIN6_PORT25_Pos) /*!< GPIO_PORT PIN6: PORT25 Mask */\r
-#define GPIO_PORT_PIN6_PORT26_Pos 26 /*!< GPIO_PORT PIN6: PORT26 Position */\r
-#define GPIO_PORT_PIN6_PORT26_Msk (0x01UL << GPIO_PORT_PIN6_PORT26_Pos) /*!< GPIO_PORT PIN6: PORT26 Mask */\r
-#define GPIO_PORT_PIN6_PORT27_Pos 27 /*!< GPIO_PORT PIN6: PORT27 Position */\r
-#define GPIO_PORT_PIN6_PORT27_Msk (0x01UL << GPIO_PORT_PIN6_PORT27_Pos) /*!< GPIO_PORT PIN6: PORT27 Mask */\r
-#define GPIO_PORT_PIN6_PORT28_Pos 28 /*!< GPIO_PORT PIN6: PORT28 Position */\r
-#define GPIO_PORT_PIN6_PORT28_Msk (0x01UL << GPIO_PORT_PIN6_PORT28_Pos) /*!< GPIO_PORT PIN6: PORT28 Mask */\r
-#define GPIO_PORT_PIN6_PORT29_Pos 29 /*!< GPIO_PORT PIN6: PORT29 Position */\r
-#define GPIO_PORT_PIN6_PORT29_Msk (0x01UL << GPIO_PORT_PIN6_PORT29_Pos) /*!< GPIO_PORT PIN6: PORT29 Mask */\r
-#define GPIO_PORT_PIN6_PORT30_Pos 30 /*!< GPIO_PORT PIN6: PORT30 Position */\r
-#define GPIO_PORT_PIN6_PORT30_Msk (0x01UL << GPIO_PORT_PIN6_PORT30_Pos) /*!< GPIO_PORT PIN6: PORT30 Mask */\r
-#define GPIO_PORT_PIN6_PORT31_Pos 31 /*!< GPIO_PORT PIN6: PORT31 Position */\r
-#define GPIO_PORT_PIN6_PORT31_Msk (0x01UL << GPIO_PORT_PIN6_PORT31_Pos) /*!< GPIO_PORT PIN6: PORT31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_PIN7 -----------------------------------------\r
-#define GPIO_PORT_PIN7_PORT0_Pos 0 /*!< GPIO_PORT PIN7: PORT0 Position */\r
-#define GPIO_PORT_PIN7_PORT0_Msk (0x01UL << GPIO_PORT_PIN7_PORT0_Pos) /*!< GPIO_PORT PIN7: PORT0 Mask */\r
-#define GPIO_PORT_PIN7_PORT1_Pos 1 /*!< GPIO_PORT PIN7: PORT1 Position */\r
-#define GPIO_PORT_PIN7_PORT1_Msk (0x01UL << GPIO_PORT_PIN7_PORT1_Pos) /*!< GPIO_PORT PIN7: PORT1 Mask */\r
-#define GPIO_PORT_PIN7_PORT2_Pos 2 /*!< GPIO_PORT PIN7: PORT2 Position */\r
-#define GPIO_PORT_PIN7_PORT2_Msk (0x01UL << GPIO_PORT_PIN7_PORT2_Pos) /*!< GPIO_PORT PIN7: PORT2 Mask */\r
-#define GPIO_PORT_PIN7_PORT3_Pos 3 /*!< GPIO_PORT PIN7: PORT3 Position */\r
-#define GPIO_PORT_PIN7_PORT3_Msk (0x01UL << GPIO_PORT_PIN7_PORT3_Pos) /*!< GPIO_PORT PIN7: PORT3 Mask */\r
-#define GPIO_PORT_PIN7_PORT4_Pos 4 /*!< GPIO_PORT PIN7: PORT4 Position */\r
-#define GPIO_PORT_PIN7_PORT4_Msk (0x01UL << GPIO_PORT_PIN7_PORT4_Pos) /*!< GPIO_PORT PIN7: PORT4 Mask */\r
-#define GPIO_PORT_PIN7_PORT5_Pos 5 /*!< GPIO_PORT PIN7: PORT5 Position */\r
-#define GPIO_PORT_PIN7_PORT5_Msk (0x01UL << GPIO_PORT_PIN7_PORT5_Pos) /*!< GPIO_PORT PIN7: PORT5 Mask */\r
-#define GPIO_PORT_PIN7_PORT6_Pos 6 /*!< GPIO_PORT PIN7: PORT6 Position */\r
-#define GPIO_PORT_PIN7_PORT6_Msk (0x01UL << GPIO_PORT_PIN7_PORT6_Pos) /*!< GPIO_PORT PIN7: PORT6 Mask */\r
-#define GPIO_PORT_PIN7_PORT7_Pos 7 /*!< GPIO_PORT PIN7: PORT7 Position */\r
-#define GPIO_PORT_PIN7_PORT7_Msk (0x01UL << GPIO_PORT_PIN7_PORT7_Pos) /*!< GPIO_PORT PIN7: PORT7 Mask */\r
-#define GPIO_PORT_PIN7_PORT8_Pos 8 /*!< GPIO_PORT PIN7: PORT8 Position */\r
-#define GPIO_PORT_PIN7_PORT8_Msk (0x01UL << GPIO_PORT_PIN7_PORT8_Pos) /*!< GPIO_PORT PIN7: PORT8 Mask */\r
-#define GPIO_PORT_PIN7_PORT9_Pos 9 /*!< GPIO_PORT PIN7: PORT9 Position */\r
-#define GPIO_PORT_PIN7_PORT9_Msk (0x01UL << GPIO_PORT_PIN7_PORT9_Pos) /*!< GPIO_PORT PIN7: PORT9 Mask */\r
-#define GPIO_PORT_PIN7_PORT10_Pos 10 /*!< GPIO_PORT PIN7: PORT10 Position */\r
-#define GPIO_PORT_PIN7_PORT10_Msk (0x01UL << GPIO_PORT_PIN7_PORT10_Pos) /*!< GPIO_PORT PIN7: PORT10 Mask */\r
-#define GPIO_PORT_PIN7_PORT11_Pos 11 /*!< GPIO_PORT PIN7: PORT11 Position */\r
-#define GPIO_PORT_PIN7_PORT11_Msk (0x01UL << GPIO_PORT_PIN7_PORT11_Pos) /*!< GPIO_PORT PIN7: PORT11 Mask */\r
-#define GPIO_PORT_PIN7_PORT12_Pos 12 /*!< GPIO_PORT PIN7: PORT12 Position */\r
-#define GPIO_PORT_PIN7_PORT12_Msk (0x01UL << GPIO_PORT_PIN7_PORT12_Pos) /*!< GPIO_PORT PIN7: PORT12 Mask */\r
-#define GPIO_PORT_PIN7_PORT13_Pos 13 /*!< GPIO_PORT PIN7: PORT13 Position */\r
-#define GPIO_PORT_PIN7_PORT13_Msk (0x01UL << GPIO_PORT_PIN7_PORT13_Pos) /*!< GPIO_PORT PIN7: PORT13 Mask */\r
-#define GPIO_PORT_PIN7_PORT14_Pos 14 /*!< GPIO_PORT PIN7: PORT14 Position */\r
-#define GPIO_PORT_PIN7_PORT14_Msk (0x01UL << GPIO_PORT_PIN7_PORT14_Pos) /*!< GPIO_PORT PIN7: PORT14 Mask */\r
-#define GPIO_PORT_PIN7_PORT15_Pos 15 /*!< GPIO_PORT PIN7: PORT15 Position */\r
-#define GPIO_PORT_PIN7_PORT15_Msk (0x01UL << GPIO_PORT_PIN7_PORT15_Pos) /*!< GPIO_PORT PIN7: PORT15 Mask */\r
-#define GPIO_PORT_PIN7_PORT16_Pos 16 /*!< GPIO_PORT PIN7: PORT16 Position */\r
-#define GPIO_PORT_PIN7_PORT16_Msk (0x01UL << GPIO_PORT_PIN7_PORT16_Pos) /*!< GPIO_PORT PIN7: PORT16 Mask */\r
-#define GPIO_PORT_PIN7_PORT17_Pos 17 /*!< GPIO_PORT PIN7: PORT17 Position */\r
-#define GPIO_PORT_PIN7_PORT17_Msk (0x01UL << GPIO_PORT_PIN7_PORT17_Pos) /*!< GPIO_PORT PIN7: PORT17 Mask */\r
-#define GPIO_PORT_PIN7_PORT18_Pos 18 /*!< GPIO_PORT PIN7: PORT18 Position */\r
-#define GPIO_PORT_PIN7_PORT18_Msk (0x01UL << GPIO_PORT_PIN7_PORT18_Pos) /*!< GPIO_PORT PIN7: PORT18 Mask */\r
-#define GPIO_PORT_PIN7_PORT19_Pos 19 /*!< GPIO_PORT PIN7: PORT19 Position */\r
-#define GPIO_PORT_PIN7_PORT19_Msk (0x01UL << GPIO_PORT_PIN7_PORT19_Pos) /*!< GPIO_PORT PIN7: PORT19 Mask */\r
-#define GPIO_PORT_PIN7_PORT20_Pos 20 /*!< GPIO_PORT PIN7: PORT20 Position */\r
-#define GPIO_PORT_PIN7_PORT20_Msk (0x01UL << GPIO_PORT_PIN7_PORT20_Pos) /*!< GPIO_PORT PIN7: PORT20 Mask */\r
-#define GPIO_PORT_PIN7_PORT21_Pos 21 /*!< GPIO_PORT PIN7: PORT21 Position */\r
-#define GPIO_PORT_PIN7_PORT21_Msk (0x01UL << GPIO_PORT_PIN7_PORT21_Pos) /*!< GPIO_PORT PIN7: PORT21 Mask */\r
-#define GPIO_PORT_PIN7_PORT22_Pos 22 /*!< GPIO_PORT PIN7: PORT22 Position */\r
-#define GPIO_PORT_PIN7_PORT22_Msk (0x01UL << GPIO_PORT_PIN7_PORT22_Pos) /*!< GPIO_PORT PIN7: PORT22 Mask */\r
-#define GPIO_PORT_PIN7_PORT23_Pos 23 /*!< GPIO_PORT PIN7: PORT23 Position */\r
-#define GPIO_PORT_PIN7_PORT23_Msk (0x01UL << GPIO_PORT_PIN7_PORT23_Pos) /*!< GPIO_PORT PIN7: PORT23 Mask */\r
-#define GPIO_PORT_PIN7_PORT24_Pos 24 /*!< GPIO_PORT PIN7: PORT24 Position */\r
-#define GPIO_PORT_PIN7_PORT24_Msk (0x01UL << GPIO_PORT_PIN7_PORT24_Pos) /*!< GPIO_PORT PIN7: PORT24 Mask */\r
-#define GPIO_PORT_PIN7_PORT25_Pos 25 /*!< GPIO_PORT PIN7: PORT25 Position */\r
-#define GPIO_PORT_PIN7_PORT25_Msk (0x01UL << GPIO_PORT_PIN7_PORT25_Pos) /*!< GPIO_PORT PIN7: PORT25 Mask */\r
-#define GPIO_PORT_PIN7_PORT26_Pos 26 /*!< GPIO_PORT PIN7: PORT26 Position */\r
-#define GPIO_PORT_PIN7_PORT26_Msk (0x01UL << GPIO_PORT_PIN7_PORT26_Pos) /*!< GPIO_PORT PIN7: PORT26 Mask */\r
-#define GPIO_PORT_PIN7_PORT27_Pos 27 /*!< GPIO_PORT PIN7: PORT27 Position */\r
-#define GPIO_PORT_PIN7_PORT27_Msk (0x01UL << GPIO_PORT_PIN7_PORT27_Pos) /*!< GPIO_PORT PIN7: PORT27 Mask */\r
-#define GPIO_PORT_PIN7_PORT28_Pos 28 /*!< GPIO_PORT PIN7: PORT28 Position */\r
-#define GPIO_PORT_PIN7_PORT28_Msk (0x01UL << GPIO_PORT_PIN7_PORT28_Pos) /*!< GPIO_PORT PIN7: PORT28 Mask */\r
-#define GPIO_PORT_PIN7_PORT29_Pos 29 /*!< GPIO_PORT PIN7: PORT29 Position */\r
-#define GPIO_PORT_PIN7_PORT29_Msk (0x01UL << GPIO_PORT_PIN7_PORT29_Pos) /*!< GPIO_PORT PIN7: PORT29 Mask */\r
-#define GPIO_PORT_PIN7_PORT30_Pos 30 /*!< GPIO_PORT PIN7: PORT30 Position */\r
-#define GPIO_PORT_PIN7_PORT30_Msk (0x01UL << GPIO_PORT_PIN7_PORT30_Pos) /*!< GPIO_PORT PIN7: PORT30 Mask */\r
-#define GPIO_PORT_PIN7_PORT31_Pos 31 /*!< GPIO_PORT PIN7: PORT31 Position */\r
-#define GPIO_PORT_PIN7_PORT31_Msk (0x01UL << GPIO_PORT_PIN7_PORT31_Pos) /*!< GPIO_PORT PIN7: PORT31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MPIN0 ----------------------------------------\r
-#define GPIO_PORT_MPIN0_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN0: MPORTP0 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP0_Pos) /*!< GPIO_PORT MPIN0: MPORTP0 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN0: MPORTP1 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP1_Pos) /*!< GPIO_PORT MPIN0: MPORTP1 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN0: MPORTP2 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP2_Pos) /*!< GPIO_PORT MPIN0: MPORTP2 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN0: MPORTP3 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP3_Pos) /*!< GPIO_PORT MPIN0: MPORTP3 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN0: MPORTP4 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP4_Pos) /*!< GPIO_PORT MPIN0: MPORTP4 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN0: MPORTP5 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP5_Pos) /*!< GPIO_PORT MPIN0: MPORTP5 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN0: MPORTP6 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP6_Pos) /*!< GPIO_PORT MPIN0: MPORTP6 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN0: MPORTP7 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP7_Pos) /*!< GPIO_PORT MPIN0: MPORTP7 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN0: MPORTP8 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP8_Pos) /*!< GPIO_PORT MPIN0: MPORTP8 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN0: MPORTP9 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP9_Pos) /*!< GPIO_PORT MPIN0: MPORTP9 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN0: MPORTP10 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP10_Pos) /*!< GPIO_PORT MPIN0: MPORTP10 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN0: MPORTP11 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP11_Pos) /*!< GPIO_PORT MPIN0: MPORTP11 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN0: MPORTP12 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP12_Pos) /*!< GPIO_PORT MPIN0: MPORTP12 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN0: MPORTP13 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP13_Pos) /*!< GPIO_PORT MPIN0: MPORTP13 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN0: MPORTP14 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP14_Pos) /*!< GPIO_PORT MPIN0: MPORTP14 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN0: MPORTP15 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP15_Pos) /*!< GPIO_PORT MPIN0: MPORTP15 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN0: MPORTP16 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP16_Pos) /*!< GPIO_PORT MPIN0: MPORTP16 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN0: MPORTP17 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP17_Pos) /*!< GPIO_PORT MPIN0: MPORTP17 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN0: MPORTP18 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP18_Pos) /*!< GPIO_PORT MPIN0: MPORTP18 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN0: MPORTP19 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP19_Pos) /*!< GPIO_PORT MPIN0: MPORTP19 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN0: MPORTP20 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP20_Pos) /*!< GPIO_PORT MPIN0: MPORTP20 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN0: MPORTP21 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP21_Pos) /*!< GPIO_PORT MPIN0: MPORTP21 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN0: MPORTP22 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP22_Pos) /*!< GPIO_PORT MPIN0: MPORTP22 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN0: MPORTP23 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP23_Pos) /*!< GPIO_PORT MPIN0: MPORTP23 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN0: MPORTP24 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP24_Pos) /*!< GPIO_PORT MPIN0: MPORTP24 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN0: MPORTP25 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP25_Pos) /*!< GPIO_PORT MPIN0: MPORTP25 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN0: MPORTP26 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP26_Pos) /*!< GPIO_PORT MPIN0: MPORTP26 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN0: MPORTP27 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP27_Pos) /*!< GPIO_PORT MPIN0: MPORTP27 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN0: MPORTP28 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP28_Pos) /*!< GPIO_PORT MPIN0: MPORTP28 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN0: MPORTP29 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP29_Pos) /*!< GPIO_PORT MPIN0: MPORTP29 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN0: MPORTP30 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP30_Pos) /*!< GPIO_PORT MPIN0: MPORTP30 Mask */\r
-#define GPIO_PORT_MPIN0_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN0: MPORTP31 Position */\r
-#define GPIO_PORT_MPIN0_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP31_Pos) /*!< GPIO_PORT MPIN0: MPORTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MPIN1 ----------------------------------------\r
-#define GPIO_PORT_MPIN1_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN1: MPORTP0 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP0_Pos) /*!< GPIO_PORT MPIN1: MPORTP0 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN1: MPORTP1 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP1_Pos) /*!< GPIO_PORT MPIN1: MPORTP1 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN1: MPORTP2 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP2_Pos) /*!< GPIO_PORT MPIN1: MPORTP2 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN1: MPORTP3 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP3_Pos) /*!< GPIO_PORT MPIN1: MPORTP3 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN1: MPORTP4 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP4_Pos) /*!< GPIO_PORT MPIN1: MPORTP4 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN1: MPORTP5 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP5_Pos) /*!< GPIO_PORT MPIN1: MPORTP5 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN1: MPORTP6 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP6_Pos) /*!< GPIO_PORT MPIN1: MPORTP6 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN1: MPORTP7 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP7_Pos) /*!< GPIO_PORT MPIN1: MPORTP7 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN1: MPORTP8 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP8_Pos) /*!< GPIO_PORT MPIN1: MPORTP8 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN1: MPORTP9 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP9_Pos) /*!< GPIO_PORT MPIN1: MPORTP9 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN1: MPORTP10 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP10_Pos) /*!< GPIO_PORT MPIN1: MPORTP10 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN1: MPORTP11 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP11_Pos) /*!< GPIO_PORT MPIN1: MPORTP11 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN1: MPORTP12 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP12_Pos) /*!< GPIO_PORT MPIN1: MPORTP12 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN1: MPORTP13 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP13_Pos) /*!< GPIO_PORT MPIN1: MPORTP13 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN1: MPORTP14 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP14_Pos) /*!< GPIO_PORT MPIN1: MPORTP14 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN1: MPORTP15 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP15_Pos) /*!< GPIO_PORT MPIN1: MPORTP15 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN1: MPORTP16 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP16_Pos) /*!< GPIO_PORT MPIN1: MPORTP16 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN1: MPORTP17 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP17_Pos) /*!< GPIO_PORT MPIN1: MPORTP17 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN1: MPORTP18 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP18_Pos) /*!< GPIO_PORT MPIN1: MPORTP18 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN1: MPORTP19 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP19_Pos) /*!< GPIO_PORT MPIN1: MPORTP19 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN1: MPORTP20 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP20_Pos) /*!< GPIO_PORT MPIN1: MPORTP20 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN1: MPORTP21 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP21_Pos) /*!< GPIO_PORT MPIN1: MPORTP21 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN1: MPORTP22 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP22_Pos) /*!< GPIO_PORT MPIN1: MPORTP22 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN1: MPORTP23 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP23_Pos) /*!< GPIO_PORT MPIN1: MPORTP23 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN1: MPORTP24 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP24_Pos) /*!< GPIO_PORT MPIN1: MPORTP24 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN1: MPORTP25 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP25_Pos) /*!< GPIO_PORT MPIN1: MPORTP25 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN1: MPORTP26 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP26_Pos) /*!< GPIO_PORT MPIN1: MPORTP26 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN1: MPORTP27 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP27_Pos) /*!< GPIO_PORT MPIN1: MPORTP27 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN1: MPORTP28 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP28_Pos) /*!< GPIO_PORT MPIN1: MPORTP28 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN1: MPORTP29 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP29_Pos) /*!< GPIO_PORT MPIN1: MPORTP29 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN1: MPORTP30 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP30_Pos) /*!< GPIO_PORT MPIN1: MPORTP30 Mask */\r
-#define GPIO_PORT_MPIN1_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN1: MPORTP31 Position */\r
-#define GPIO_PORT_MPIN1_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP31_Pos) /*!< GPIO_PORT MPIN1: MPORTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MPIN2 ----------------------------------------\r
-#define GPIO_PORT_MPIN2_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN2: MPORTP0 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP0_Pos) /*!< GPIO_PORT MPIN2: MPORTP0 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN2: MPORTP1 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP1_Pos) /*!< GPIO_PORT MPIN2: MPORTP1 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN2: MPORTP2 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP2_Pos) /*!< GPIO_PORT MPIN2: MPORTP2 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN2: MPORTP3 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP3_Pos) /*!< GPIO_PORT MPIN2: MPORTP3 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN2: MPORTP4 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP4_Pos) /*!< GPIO_PORT MPIN2: MPORTP4 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN2: MPORTP5 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP5_Pos) /*!< GPIO_PORT MPIN2: MPORTP5 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN2: MPORTP6 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP6_Pos) /*!< GPIO_PORT MPIN2: MPORTP6 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN2: MPORTP7 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP7_Pos) /*!< GPIO_PORT MPIN2: MPORTP7 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN2: MPORTP8 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP8_Pos) /*!< GPIO_PORT MPIN2: MPORTP8 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN2: MPORTP9 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP9_Pos) /*!< GPIO_PORT MPIN2: MPORTP9 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN2: MPORTP10 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP10_Pos) /*!< GPIO_PORT MPIN2: MPORTP10 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN2: MPORTP11 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP11_Pos) /*!< GPIO_PORT MPIN2: MPORTP11 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN2: MPORTP12 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP12_Pos) /*!< GPIO_PORT MPIN2: MPORTP12 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN2: MPORTP13 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP13_Pos) /*!< GPIO_PORT MPIN2: MPORTP13 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN2: MPORTP14 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP14_Pos) /*!< GPIO_PORT MPIN2: MPORTP14 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN2: MPORTP15 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP15_Pos) /*!< GPIO_PORT MPIN2: MPORTP15 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN2: MPORTP16 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP16_Pos) /*!< GPIO_PORT MPIN2: MPORTP16 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN2: MPORTP17 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP17_Pos) /*!< GPIO_PORT MPIN2: MPORTP17 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN2: MPORTP18 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP18_Pos) /*!< GPIO_PORT MPIN2: MPORTP18 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN2: MPORTP19 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP19_Pos) /*!< GPIO_PORT MPIN2: MPORTP19 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN2: MPORTP20 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP20_Pos) /*!< GPIO_PORT MPIN2: MPORTP20 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN2: MPORTP21 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP21_Pos) /*!< GPIO_PORT MPIN2: MPORTP21 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN2: MPORTP22 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP22_Pos) /*!< GPIO_PORT MPIN2: MPORTP22 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN2: MPORTP23 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP23_Pos) /*!< GPIO_PORT MPIN2: MPORTP23 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN2: MPORTP24 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP24_Pos) /*!< GPIO_PORT MPIN2: MPORTP24 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN2: MPORTP25 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP25_Pos) /*!< GPIO_PORT MPIN2: MPORTP25 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN2: MPORTP26 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP26_Pos) /*!< GPIO_PORT MPIN2: MPORTP26 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN2: MPORTP27 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP27_Pos) /*!< GPIO_PORT MPIN2: MPORTP27 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN2: MPORTP28 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP28_Pos) /*!< GPIO_PORT MPIN2: MPORTP28 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN2: MPORTP29 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP29_Pos) /*!< GPIO_PORT MPIN2: MPORTP29 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN2: MPORTP30 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP30_Pos) /*!< GPIO_PORT MPIN2: MPORTP30 Mask */\r
-#define GPIO_PORT_MPIN2_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN2: MPORTP31 Position */\r
-#define GPIO_PORT_MPIN2_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP31_Pos) /*!< GPIO_PORT MPIN2: MPORTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MPIN3 ----------------------------------------\r
-#define GPIO_PORT_MPIN3_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN3: MPORTP0 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP0_Pos) /*!< GPIO_PORT MPIN3: MPORTP0 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN3: MPORTP1 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP1_Pos) /*!< GPIO_PORT MPIN3: MPORTP1 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN3: MPORTP2 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP2_Pos) /*!< GPIO_PORT MPIN3: MPORTP2 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN3: MPORTP3 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP3_Pos) /*!< GPIO_PORT MPIN3: MPORTP3 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN3: MPORTP4 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP4_Pos) /*!< GPIO_PORT MPIN3: MPORTP4 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN3: MPORTP5 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP5_Pos) /*!< GPIO_PORT MPIN3: MPORTP5 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN3: MPORTP6 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP6_Pos) /*!< GPIO_PORT MPIN3: MPORTP6 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN3: MPORTP7 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP7_Pos) /*!< GPIO_PORT MPIN3: MPORTP7 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN3: MPORTP8 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP8_Pos) /*!< GPIO_PORT MPIN3: MPORTP8 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN3: MPORTP9 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP9_Pos) /*!< GPIO_PORT MPIN3: MPORTP9 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN3: MPORTP10 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP10_Pos) /*!< GPIO_PORT MPIN3: MPORTP10 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN3: MPORTP11 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP11_Pos) /*!< GPIO_PORT MPIN3: MPORTP11 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN3: MPORTP12 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP12_Pos) /*!< GPIO_PORT MPIN3: MPORTP12 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN3: MPORTP13 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP13_Pos) /*!< GPIO_PORT MPIN3: MPORTP13 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN3: MPORTP14 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP14_Pos) /*!< GPIO_PORT MPIN3: MPORTP14 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN3: MPORTP15 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP15_Pos) /*!< GPIO_PORT MPIN3: MPORTP15 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN3: MPORTP16 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP16_Pos) /*!< GPIO_PORT MPIN3: MPORTP16 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN3: MPORTP17 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP17_Pos) /*!< GPIO_PORT MPIN3: MPORTP17 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN3: MPORTP18 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP18_Pos) /*!< GPIO_PORT MPIN3: MPORTP18 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN3: MPORTP19 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP19_Pos) /*!< GPIO_PORT MPIN3: MPORTP19 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN3: MPORTP20 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP20_Pos) /*!< GPIO_PORT MPIN3: MPORTP20 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN3: MPORTP21 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP21_Pos) /*!< GPIO_PORT MPIN3: MPORTP21 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN3: MPORTP22 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP22_Pos) /*!< GPIO_PORT MPIN3: MPORTP22 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN3: MPORTP23 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP23_Pos) /*!< GPIO_PORT MPIN3: MPORTP23 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN3: MPORTP24 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP24_Pos) /*!< GPIO_PORT MPIN3: MPORTP24 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN3: MPORTP25 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP25_Pos) /*!< GPIO_PORT MPIN3: MPORTP25 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN3: MPORTP26 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP26_Pos) /*!< GPIO_PORT MPIN3: MPORTP26 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN3: MPORTP27 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP27_Pos) /*!< GPIO_PORT MPIN3: MPORTP27 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN3: MPORTP28 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP28_Pos) /*!< GPIO_PORT MPIN3: MPORTP28 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN3: MPORTP29 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP29_Pos) /*!< GPIO_PORT MPIN3: MPORTP29 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN3: MPORTP30 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP30_Pos) /*!< GPIO_PORT MPIN3: MPORTP30 Mask */\r
-#define GPIO_PORT_MPIN3_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN3: MPORTP31 Position */\r
-#define GPIO_PORT_MPIN3_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP31_Pos) /*!< GPIO_PORT MPIN3: MPORTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MPIN4 ----------------------------------------\r
-#define GPIO_PORT_MPIN4_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN4: MPORTP0 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP0_Pos) /*!< GPIO_PORT MPIN4: MPORTP0 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN4: MPORTP1 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP1_Pos) /*!< GPIO_PORT MPIN4: MPORTP1 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN4: MPORTP2 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP2_Pos) /*!< GPIO_PORT MPIN4: MPORTP2 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN4: MPORTP3 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP3_Pos) /*!< GPIO_PORT MPIN4: MPORTP3 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN4: MPORTP4 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP4_Pos) /*!< GPIO_PORT MPIN4: MPORTP4 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN4: MPORTP5 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP5_Pos) /*!< GPIO_PORT MPIN4: MPORTP5 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN4: MPORTP6 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP6_Pos) /*!< GPIO_PORT MPIN4: MPORTP6 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN4: MPORTP7 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP7_Pos) /*!< GPIO_PORT MPIN4: MPORTP7 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN4: MPORTP8 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP8_Pos) /*!< GPIO_PORT MPIN4: MPORTP8 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN4: MPORTP9 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP9_Pos) /*!< GPIO_PORT MPIN4: MPORTP9 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN4: MPORTP10 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP10_Pos) /*!< GPIO_PORT MPIN4: MPORTP10 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN4: MPORTP11 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP11_Pos) /*!< GPIO_PORT MPIN4: MPORTP11 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN4: MPORTP12 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP12_Pos) /*!< GPIO_PORT MPIN4: MPORTP12 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN4: MPORTP13 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP13_Pos) /*!< GPIO_PORT MPIN4: MPORTP13 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN4: MPORTP14 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP14_Pos) /*!< GPIO_PORT MPIN4: MPORTP14 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN4: MPORTP15 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP15_Pos) /*!< GPIO_PORT MPIN4: MPORTP15 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN4: MPORTP16 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP16_Pos) /*!< GPIO_PORT MPIN4: MPORTP16 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN4: MPORTP17 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP17_Pos) /*!< GPIO_PORT MPIN4: MPORTP17 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN4: MPORTP18 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP18_Pos) /*!< GPIO_PORT MPIN4: MPORTP18 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN4: MPORTP19 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP19_Pos) /*!< GPIO_PORT MPIN4: MPORTP19 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN4: MPORTP20 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP20_Pos) /*!< GPIO_PORT MPIN4: MPORTP20 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN4: MPORTP21 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP21_Pos) /*!< GPIO_PORT MPIN4: MPORTP21 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN4: MPORTP22 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP22_Pos) /*!< GPIO_PORT MPIN4: MPORTP22 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN4: MPORTP23 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP23_Pos) /*!< GPIO_PORT MPIN4: MPORTP23 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN4: MPORTP24 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP24_Pos) /*!< GPIO_PORT MPIN4: MPORTP24 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN4: MPORTP25 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP25_Pos) /*!< GPIO_PORT MPIN4: MPORTP25 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN4: MPORTP26 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP26_Pos) /*!< GPIO_PORT MPIN4: MPORTP26 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN4: MPORTP27 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP27_Pos) /*!< GPIO_PORT MPIN4: MPORTP27 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN4: MPORTP28 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP28_Pos) /*!< GPIO_PORT MPIN4: MPORTP28 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN4: MPORTP29 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP29_Pos) /*!< GPIO_PORT MPIN4: MPORTP29 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN4: MPORTP30 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP30_Pos) /*!< GPIO_PORT MPIN4: MPORTP30 Mask */\r
-#define GPIO_PORT_MPIN4_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN4: MPORTP31 Position */\r
-#define GPIO_PORT_MPIN4_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP31_Pos) /*!< GPIO_PORT MPIN4: MPORTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MPIN5 ----------------------------------------\r
-#define GPIO_PORT_MPIN5_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN5: MPORTP0 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP0_Pos) /*!< GPIO_PORT MPIN5: MPORTP0 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN5: MPORTP1 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP1_Pos) /*!< GPIO_PORT MPIN5: MPORTP1 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN5: MPORTP2 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP2_Pos) /*!< GPIO_PORT MPIN5: MPORTP2 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN5: MPORTP3 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP3_Pos) /*!< GPIO_PORT MPIN5: MPORTP3 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN5: MPORTP4 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP4_Pos) /*!< GPIO_PORT MPIN5: MPORTP4 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN5: MPORTP5 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP5_Pos) /*!< GPIO_PORT MPIN5: MPORTP5 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN5: MPORTP6 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP6_Pos) /*!< GPIO_PORT MPIN5: MPORTP6 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN5: MPORTP7 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP7_Pos) /*!< GPIO_PORT MPIN5: MPORTP7 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN5: MPORTP8 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP8_Pos) /*!< GPIO_PORT MPIN5: MPORTP8 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN5: MPORTP9 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP9_Pos) /*!< GPIO_PORT MPIN5: MPORTP9 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN5: MPORTP10 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP10_Pos) /*!< GPIO_PORT MPIN5: MPORTP10 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN5: MPORTP11 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP11_Pos) /*!< GPIO_PORT MPIN5: MPORTP11 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN5: MPORTP12 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP12_Pos) /*!< GPIO_PORT MPIN5: MPORTP12 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN5: MPORTP13 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP13_Pos) /*!< GPIO_PORT MPIN5: MPORTP13 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN5: MPORTP14 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP14_Pos) /*!< GPIO_PORT MPIN5: MPORTP14 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN5: MPORTP15 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP15_Pos) /*!< GPIO_PORT MPIN5: MPORTP15 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN5: MPORTP16 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP16_Pos) /*!< GPIO_PORT MPIN5: MPORTP16 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN5: MPORTP17 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP17_Pos) /*!< GPIO_PORT MPIN5: MPORTP17 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN5: MPORTP18 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP18_Pos) /*!< GPIO_PORT MPIN5: MPORTP18 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN5: MPORTP19 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP19_Pos) /*!< GPIO_PORT MPIN5: MPORTP19 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN5: MPORTP20 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP20_Pos) /*!< GPIO_PORT MPIN5: MPORTP20 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN5: MPORTP21 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP21_Pos) /*!< GPIO_PORT MPIN5: MPORTP21 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN5: MPORTP22 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP22_Pos) /*!< GPIO_PORT MPIN5: MPORTP22 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN5: MPORTP23 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP23_Pos) /*!< GPIO_PORT MPIN5: MPORTP23 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN5: MPORTP24 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP24_Pos) /*!< GPIO_PORT MPIN5: MPORTP24 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN5: MPORTP25 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP25_Pos) /*!< GPIO_PORT MPIN5: MPORTP25 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN5: MPORTP26 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP26_Pos) /*!< GPIO_PORT MPIN5: MPORTP26 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN5: MPORTP27 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP27_Pos) /*!< GPIO_PORT MPIN5: MPORTP27 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN5: MPORTP28 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP28_Pos) /*!< GPIO_PORT MPIN5: MPORTP28 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN5: MPORTP29 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP29_Pos) /*!< GPIO_PORT MPIN5: MPORTP29 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN5: MPORTP30 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP30_Pos) /*!< GPIO_PORT MPIN5: MPORTP30 Mask */\r
-#define GPIO_PORT_MPIN5_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN5: MPORTP31 Position */\r
-#define GPIO_PORT_MPIN5_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP31_Pos) /*!< GPIO_PORT MPIN5: MPORTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MPIN6 ----------------------------------------\r
-#define GPIO_PORT_MPIN6_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN6: MPORTP0 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP0_Pos) /*!< GPIO_PORT MPIN6: MPORTP0 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN6: MPORTP1 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP1_Pos) /*!< GPIO_PORT MPIN6: MPORTP1 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN6: MPORTP2 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP2_Pos) /*!< GPIO_PORT MPIN6: MPORTP2 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN6: MPORTP3 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP3_Pos) /*!< GPIO_PORT MPIN6: MPORTP3 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN6: MPORTP4 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP4_Pos) /*!< GPIO_PORT MPIN6: MPORTP4 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN6: MPORTP5 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP5_Pos) /*!< GPIO_PORT MPIN6: MPORTP5 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN6: MPORTP6 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP6_Pos) /*!< GPIO_PORT MPIN6: MPORTP6 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN6: MPORTP7 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP7_Pos) /*!< GPIO_PORT MPIN6: MPORTP7 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN6: MPORTP8 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP8_Pos) /*!< GPIO_PORT MPIN6: MPORTP8 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN6: MPORTP9 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP9_Pos) /*!< GPIO_PORT MPIN6: MPORTP9 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN6: MPORTP10 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP10_Pos) /*!< GPIO_PORT MPIN6: MPORTP10 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN6: MPORTP11 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP11_Pos) /*!< GPIO_PORT MPIN6: MPORTP11 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN6: MPORTP12 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP12_Pos) /*!< GPIO_PORT MPIN6: MPORTP12 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN6: MPORTP13 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP13_Pos) /*!< GPIO_PORT MPIN6: MPORTP13 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN6: MPORTP14 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP14_Pos) /*!< GPIO_PORT MPIN6: MPORTP14 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN6: MPORTP15 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP15_Pos) /*!< GPIO_PORT MPIN6: MPORTP15 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN6: MPORTP16 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP16_Pos) /*!< GPIO_PORT MPIN6: MPORTP16 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN6: MPORTP17 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP17_Pos) /*!< GPIO_PORT MPIN6: MPORTP17 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN6: MPORTP18 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP18_Pos) /*!< GPIO_PORT MPIN6: MPORTP18 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN6: MPORTP19 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP19_Pos) /*!< GPIO_PORT MPIN6: MPORTP19 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN6: MPORTP20 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP20_Pos) /*!< GPIO_PORT MPIN6: MPORTP20 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN6: MPORTP21 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP21_Pos) /*!< GPIO_PORT MPIN6: MPORTP21 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN6: MPORTP22 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP22_Pos) /*!< GPIO_PORT MPIN6: MPORTP22 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN6: MPORTP23 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP23_Pos) /*!< GPIO_PORT MPIN6: MPORTP23 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN6: MPORTP24 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP24_Pos) /*!< GPIO_PORT MPIN6: MPORTP24 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN6: MPORTP25 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP25_Pos) /*!< GPIO_PORT MPIN6: MPORTP25 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN6: MPORTP26 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP26_Pos) /*!< GPIO_PORT MPIN6: MPORTP26 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN6: MPORTP27 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP27_Pos) /*!< GPIO_PORT MPIN6: MPORTP27 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN6: MPORTP28 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP28_Pos) /*!< GPIO_PORT MPIN6: MPORTP28 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN6: MPORTP29 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP29_Pos) /*!< GPIO_PORT MPIN6: MPORTP29 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN6: MPORTP30 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP30_Pos) /*!< GPIO_PORT MPIN6: MPORTP30 Mask */\r
-#define GPIO_PORT_MPIN6_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN6: MPORTP31 Position */\r
-#define GPIO_PORT_MPIN6_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP31_Pos) /*!< GPIO_PORT MPIN6: MPORTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_MPIN7 ----------------------------------------\r
-#define GPIO_PORT_MPIN7_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN7: MPORTP0 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP0_Pos) /*!< GPIO_PORT MPIN7: MPORTP0 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN7: MPORTP1 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP1_Pos) /*!< GPIO_PORT MPIN7: MPORTP1 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN7: MPORTP2 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP2_Pos) /*!< GPIO_PORT MPIN7: MPORTP2 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN7: MPORTP3 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP3_Pos) /*!< GPIO_PORT MPIN7: MPORTP3 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN7: MPORTP4 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP4_Pos) /*!< GPIO_PORT MPIN7: MPORTP4 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN7: MPORTP5 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP5_Pos) /*!< GPIO_PORT MPIN7: MPORTP5 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN7: MPORTP6 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP6_Pos) /*!< GPIO_PORT MPIN7: MPORTP6 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN7: MPORTP7 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP7_Pos) /*!< GPIO_PORT MPIN7: MPORTP7 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN7: MPORTP8 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP8_Pos) /*!< GPIO_PORT MPIN7: MPORTP8 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN7: MPORTP9 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP9_Pos) /*!< GPIO_PORT MPIN7: MPORTP9 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN7: MPORTP10 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP10_Pos) /*!< GPIO_PORT MPIN7: MPORTP10 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN7: MPORTP11 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP11_Pos) /*!< GPIO_PORT MPIN7: MPORTP11 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN7: MPORTP12 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP12_Pos) /*!< GPIO_PORT MPIN7: MPORTP12 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN7: MPORTP13 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP13_Pos) /*!< GPIO_PORT MPIN7: MPORTP13 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN7: MPORTP14 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP14_Pos) /*!< GPIO_PORT MPIN7: MPORTP14 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN7: MPORTP15 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP15_Pos) /*!< GPIO_PORT MPIN7: MPORTP15 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN7: MPORTP16 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP16_Pos) /*!< GPIO_PORT MPIN7: MPORTP16 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN7: MPORTP17 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP17_Pos) /*!< GPIO_PORT MPIN7: MPORTP17 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN7: MPORTP18 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP18_Pos) /*!< GPIO_PORT MPIN7: MPORTP18 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN7: MPORTP19 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP19_Pos) /*!< GPIO_PORT MPIN7: MPORTP19 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN7: MPORTP20 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP20_Pos) /*!< GPIO_PORT MPIN7: MPORTP20 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN7: MPORTP21 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP21_Pos) /*!< GPIO_PORT MPIN7: MPORTP21 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN7: MPORTP22 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP22_Pos) /*!< GPIO_PORT MPIN7: MPORTP22 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN7: MPORTP23 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP23_Pos) /*!< GPIO_PORT MPIN7: MPORTP23 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN7: MPORTP24 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP24_Pos) /*!< GPIO_PORT MPIN7: MPORTP24 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN7: MPORTP25 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP25_Pos) /*!< GPIO_PORT MPIN7: MPORTP25 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN7: MPORTP26 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP26_Pos) /*!< GPIO_PORT MPIN7: MPORTP26 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN7: MPORTP27 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP27_Pos) /*!< GPIO_PORT MPIN7: MPORTP27 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN7: MPORTP28 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP28_Pos) /*!< GPIO_PORT MPIN7: MPORTP28 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN7: MPORTP29 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP29_Pos) /*!< GPIO_PORT MPIN7: MPORTP29 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN7: MPORTP30 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP30_Pos) /*!< GPIO_PORT MPIN7: MPORTP30 Mask */\r
-#define GPIO_PORT_MPIN7_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN7: MPORTP31 Position */\r
-#define GPIO_PORT_MPIN7_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP31_Pos) /*!< GPIO_PORT MPIN7: MPORTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_SET0 -----------------------------------------\r
-#define GPIO_PORT_SET0_SETP0_Pos 0 /*!< GPIO_PORT SET0: SETP0 Position */\r
-#define GPIO_PORT_SET0_SETP0_Msk (0x01UL << GPIO_PORT_SET0_SETP0_Pos) /*!< GPIO_PORT SET0: SETP0 Mask */\r
-#define GPIO_PORT_SET0_SETP1_Pos 1 /*!< GPIO_PORT SET0: SETP1 Position */\r
-#define GPIO_PORT_SET0_SETP1_Msk (0x01UL << GPIO_PORT_SET0_SETP1_Pos) /*!< GPIO_PORT SET0: SETP1 Mask */\r
-#define GPIO_PORT_SET0_SETP2_Pos 2 /*!< GPIO_PORT SET0: SETP2 Position */\r
-#define GPIO_PORT_SET0_SETP2_Msk (0x01UL << GPIO_PORT_SET0_SETP2_Pos) /*!< GPIO_PORT SET0: SETP2 Mask */\r
-#define GPIO_PORT_SET0_SETP3_Pos 3 /*!< GPIO_PORT SET0: SETP3 Position */\r
-#define GPIO_PORT_SET0_SETP3_Msk (0x01UL << GPIO_PORT_SET0_SETP3_Pos) /*!< GPIO_PORT SET0: SETP3 Mask */\r
-#define GPIO_PORT_SET0_SETP4_Pos 4 /*!< GPIO_PORT SET0: SETP4 Position */\r
-#define GPIO_PORT_SET0_SETP4_Msk (0x01UL << GPIO_PORT_SET0_SETP4_Pos) /*!< GPIO_PORT SET0: SETP4 Mask */\r
-#define GPIO_PORT_SET0_SETP5_Pos 5 /*!< GPIO_PORT SET0: SETP5 Position */\r
-#define GPIO_PORT_SET0_SETP5_Msk (0x01UL << GPIO_PORT_SET0_SETP5_Pos) /*!< GPIO_PORT SET0: SETP5 Mask */\r
-#define GPIO_PORT_SET0_SETP6_Pos 6 /*!< GPIO_PORT SET0: SETP6 Position */\r
-#define GPIO_PORT_SET0_SETP6_Msk (0x01UL << GPIO_PORT_SET0_SETP6_Pos) /*!< GPIO_PORT SET0: SETP6 Mask */\r
-#define GPIO_PORT_SET0_SETP7_Pos 7 /*!< GPIO_PORT SET0: SETP7 Position */\r
-#define GPIO_PORT_SET0_SETP7_Msk (0x01UL << GPIO_PORT_SET0_SETP7_Pos) /*!< GPIO_PORT SET0: SETP7 Mask */\r
-#define GPIO_PORT_SET0_SETP8_Pos 8 /*!< GPIO_PORT SET0: SETP8 Position */\r
-#define GPIO_PORT_SET0_SETP8_Msk (0x01UL << GPIO_PORT_SET0_SETP8_Pos) /*!< GPIO_PORT SET0: SETP8 Mask */\r
-#define GPIO_PORT_SET0_SETP9_Pos 9 /*!< GPIO_PORT SET0: SETP9 Position */\r
-#define GPIO_PORT_SET0_SETP9_Msk (0x01UL << GPIO_PORT_SET0_SETP9_Pos) /*!< GPIO_PORT SET0: SETP9 Mask */\r
-#define GPIO_PORT_SET0_SETP10_Pos 10 /*!< GPIO_PORT SET0: SETP10 Position */\r
-#define GPIO_PORT_SET0_SETP10_Msk (0x01UL << GPIO_PORT_SET0_SETP10_Pos) /*!< GPIO_PORT SET0: SETP10 Mask */\r
-#define GPIO_PORT_SET0_SETP11_Pos 11 /*!< GPIO_PORT SET0: SETP11 Position */\r
-#define GPIO_PORT_SET0_SETP11_Msk (0x01UL << GPIO_PORT_SET0_SETP11_Pos) /*!< GPIO_PORT SET0: SETP11 Mask */\r
-#define GPIO_PORT_SET0_SETP12_Pos 12 /*!< GPIO_PORT SET0: SETP12 Position */\r
-#define GPIO_PORT_SET0_SETP12_Msk (0x01UL << GPIO_PORT_SET0_SETP12_Pos) /*!< GPIO_PORT SET0: SETP12 Mask */\r
-#define GPIO_PORT_SET0_SETP13_Pos 13 /*!< GPIO_PORT SET0: SETP13 Position */\r
-#define GPIO_PORT_SET0_SETP13_Msk (0x01UL << GPIO_PORT_SET0_SETP13_Pos) /*!< GPIO_PORT SET0: SETP13 Mask */\r
-#define GPIO_PORT_SET0_SETP14_Pos 14 /*!< GPIO_PORT SET0: SETP14 Position */\r
-#define GPIO_PORT_SET0_SETP14_Msk (0x01UL << GPIO_PORT_SET0_SETP14_Pos) /*!< GPIO_PORT SET0: SETP14 Mask */\r
-#define GPIO_PORT_SET0_SETP15_Pos 15 /*!< GPIO_PORT SET0: SETP15 Position */\r
-#define GPIO_PORT_SET0_SETP15_Msk (0x01UL << GPIO_PORT_SET0_SETP15_Pos) /*!< GPIO_PORT SET0: SETP15 Mask */\r
-#define GPIO_PORT_SET0_SETP16_Pos 16 /*!< GPIO_PORT SET0: SETP16 Position */\r
-#define GPIO_PORT_SET0_SETP16_Msk (0x01UL << GPIO_PORT_SET0_SETP16_Pos) /*!< GPIO_PORT SET0: SETP16 Mask */\r
-#define GPIO_PORT_SET0_SETP17_Pos 17 /*!< GPIO_PORT SET0: SETP17 Position */\r
-#define GPIO_PORT_SET0_SETP17_Msk (0x01UL << GPIO_PORT_SET0_SETP17_Pos) /*!< GPIO_PORT SET0: SETP17 Mask */\r
-#define GPIO_PORT_SET0_SETP18_Pos 18 /*!< GPIO_PORT SET0: SETP18 Position */\r
-#define GPIO_PORT_SET0_SETP18_Msk (0x01UL << GPIO_PORT_SET0_SETP18_Pos) /*!< GPIO_PORT SET0: SETP18 Mask */\r
-#define GPIO_PORT_SET0_SETP19_Pos 19 /*!< GPIO_PORT SET0: SETP19 Position */\r
-#define GPIO_PORT_SET0_SETP19_Msk (0x01UL << GPIO_PORT_SET0_SETP19_Pos) /*!< GPIO_PORT SET0: SETP19 Mask */\r
-#define GPIO_PORT_SET0_SETP20_Pos 20 /*!< GPIO_PORT SET0: SETP20 Position */\r
-#define GPIO_PORT_SET0_SETP20_Msk (0x01UL << GPIO_PORT_SET0_SETP20_Pos) /*!< GPIO_PORT SET0: SETP20 Mask */\r
-#define GPIO_PORT_SET0_SETP21_Pos 21 /*!< GPIO_PORT SET0: SETP21 Position */\r
-#define GPIO_PORT_SET0_SETP21_Msk (0x01UL << GPIO_PORT_SET0_SETP21_Pos) /*!< GPIO_PORT SET0: SETP21 Mask */\r
-#define GPIO_PORT_SET0_SETP22_Pos 22 /*!< GPIO_PORT SET0: SETP22 Position */\r
-#define GPIO_PORT_SET0_SETP22_Msk (0x01UL << GPIO_PORT_SET0_SETP22_Pos) /*!< GPIO_PORT SET0: SETP22 Mask */\r
-#define GPIO_PORT_SET0_SETP23_Pos 23 /*!< GPIO_PORT SET0: SETP23 Position */\r
-#define GPIO_PORT_SET0_SETP23_Msk (0x01UL << GPIO_PORT_SET0_SETP23_Pos) /*!< GPIO_PORT SET0: SETP23 Mask */\r
-#define GPIO_PORT_SET0_SETP24_Pos 24 /*!< GPIO_PORT SET0: SETP24 Position */\r
-#define GPIO_PORT_SET0_SETP24_Msk (0x01UL << GPIO_PORT_SET0_SETP24_Pos) /*!< GPIO_PORT SET0: SETP24 Mask */\r
-#define GPIO_PORT_SET0_SETP25_Pos 25 /*!< GPIO_PORT SET0: SETP25 Position */\r
-#define GPIO_PORT_SET0_SETP25_Msk (0x01UL << GPIO_PORT_SET0_SETP25_Pos) /*!< GPIO_PORT SET0: SETP25 Mask */\r
-#define GPIO_PORT_SET0_SETP26_Pos 26 /*!< GPIO_PORT SET0: SETP26 Position */\r
-#define GPIO_PORT_SET0_SETP26_Msk (0x01UL << GPIO_PORT_SET0_SETP26_Pos) /*!< GPIO_PORT SET0: SETP26 Mask */\r
-#define GPIO_PORT_SET0_SETP27_Pos 27 /*!< GPIO_PORT SET0: SETP27 Position */\r
-#define GPIO_PORT_SET0_SETP27_Msk (0x01UL << GPIO_PORT_SET0_SETP27_Pos) /*!< GPIO_PORT SET0: SETP27 Mask */\r
-#define GPIO_PORT_SET0_SETP28_Pos 28 /*!< GPIO_PORT SET0: SETP28 Position */\r
-#define GPIO_PORT_SET0_SETP28_Msk (0x01UL << GPIO_PORT_SET0_SETP28_Pos) /*!< GPIO_PORT SET0: SETP28 Mask */\r
-#define GPIO_PORT_SET0_SETP29_Pos 29 /*!< GPIO_PORT SET0: SETP29 Position */\r
-#define GPIO_PORT_SET0_SETP29_Msk (0x01UL << GPIO_PORT_SET0_SETP29_Pos) /*!< GPIO_PORT SET0: SETP29 Mask */\r
-#define GPIO_PORT_SET0_SETP30_Pos 30 /*!< GPIO_PORT SET0: SETP30 Position */\r
-#define GPIO_PORT_SET0_SETP30_Msk (0x01UL << GPIO_PORT_SET0_SETP30_Pos) /*!< GPIO_PORT SET0: SETP30 Mask */\r
-#define GPIO_PORT_SET0_SETP31_Pos 31 /*!< GPIO_PORT SET0: SETP31 Position */\r
-#define GPIO_PORT_SET0_SETP31_Msk (0x01UL << GPIO_PORT_SET0_SETP31_Pos) /*!< GPIO_PORT SET0: SETP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_SET1 -----------------------------------------\r
-#define GPIO_PORT_SET1_SETP0_Pos 0 /*!< GPIO_PORT SET1: SETP0 Position */\r
-#define GPIO_PORT_SET1_SETP0_Msk (0x01UL << GPIO_PORT_SET1_SETP0_Pos) /*!< GPIO_PORT SET1: SETP0 Mask */\r
-#define GPIO_PORT_SET1_SETP1_Pos 1 /*!< GPIO_PORT SET1: SETP1 Position */\r
-#define GPIO_PORT_SET1_SETP1_Msk (0x01UL << GPIO_PORT_SET1_SETP1_Pos) /*!< GPIO_PORT SET1: SETP1 Mask */\r
-#define GPIO_PORT_SET1_SETP2_Pos 2 /*!< GPIO_PORT SET1: SETP2 Position */\r
-#define GPIO_PORT_SET1_SETP2_Msk (0x01UL << GPIO_PORT_SET1_SETP2_Pos) /*!< GPIO_PORT SET1: SETP2 Mask */\r
-#define GPIO_PORT_SET1_SETP3_Pos 3 /*!< GPIO_PORT SET1: SETP3 Position */\r
-#define GPIO_PORT_SET1_SETP3_Msk (0x01UL << GPIO_PORT_SET1_SETP3_Pos) /*!< GPIO_PORT SET1: SETP3 Mask */\r
-#define GPIO_PORT_SET1_SETP4_Pos 4 /*!< GPIO_PORT SET1: SETP4 Position */\r
-#define GPIO_PORT_SET1_SETP4_Msk (0x01UL << GPIO_PORT_SET1_SETP4_Pos) /*!< GPIO_PORT SET1: SETP4 Mask */\r
-#define GPIO_PORT_SET1_SETP5_Pos 5 /*!< GPIO_PORT SET1: SETP5 Position */\r
-#define GPIO_PORT_SET1_SETP5_Msk (0x01UL << GPIO_PORT_SET1_SETP5_Pos) /*!< GPIO_PORT SET1: SETP5 Mask */\r
-#define GPIO_PORT_SET1_SETP6_Pos 6 /*!< GPIO_PORT SET1: SETP6 Position */\r
-#define GPIO_PORT_SET1_SETP6_Msk (0x01UL << GPIO_PORT_SET1_SETP6_Pos) /*!< GPIO_PORT SET1: SETP6 Mask */\r
-#define GPIO_PORT_SET1_SETP7_Pos 7 /*!< GPIO_PORT SET1: SETP7 Position */\r
-#define GPIO_PORT_SET1_SETP7_Msk (0x01UL << GPIO_PORT_SET1_SETP7_Pos) /*!< GPIO_PORT SET1: SETP7 Mask */\r
-#define GPIO_PORT_SET1_SETP8_Pos 8 /*!< GPIO_PORT SET1: SETP8 Position */\r
-#define GPIO_PORT_SET1_SETP8_Msk (0x01UL << GPIO_PORT_SET1_SETP8_Pos) /*!< GPIO_PORT SET1: SETP8 Mask */\r
-#define GPIO_PORT_SET1_SETP9_Pos 9 /*!< GPIO_PORT SET1: SETP9 Position */\r
-#define GPIO_PORT_SET1_SETP9_Msk (0x01UL << GPIO_PORT_SET1_SETP9_Pos) /*!< GPIO_PORT SET1: SETP9 Mask */\r
-#define GPIO_PORT_SET1_SETP10_Pos 10 /*!< GPIO_PORT SET1: SETP10 Position */\r
-#define GPIO_PORT_SET1_SETP10_Msk (0x01UL << GPIO_PORT_SET1_SETP10_Pos) /*!< GPIO_PORT SET1: SETP10 Mask */\r
-#define GPIO_PORT_SET1_SETP11_Pos 11 /*!< GPIO_PORT SET1: SETP11 Position */\r
-#define GPIO_PORT_SET1_SETP11_Msk (0x01UL << GPIO_PORT_SET1_SETP11_Pos) /*!< GPIO_PORT SET1: SETP11 Mask */\r
-#define GPIO_PORT_SET1_SETP12_Pos 12 /*!< GPIO_PORT SET1: SETP12 Position */\r
-#define GPIO_PORT_SET1_SETP12_Msk (0x01UL << GPIO_PORT_SET1_SETP12_Pos) /*!< GPIO_PORT SET1: SETP12 Mask */\r
-#define GPIO_PORT_SET1_SETP13_Pos 13 /*!< GPIO_PORT SET1: SETP13 Position */\r
-#define GPIO_PORT_SET1_SETP13_Msk (0x01UL << GPIO_PORT_SET1_SETP13_Pos) /*!< GPIO_PORT SET1: SETP13 Mask */\r
-#define GPIO_PORT_SET1_SETP14_Pos 14 /*!< GPIO_PORT SET1: SETP14 Position */\r
-#define GPIO_PORT_SET1_SETP14_Msk (0x01UL << GPIO_PORT_SET1_SETP14_Pos) /*!< GPIO_PORT SET1: SETP14 Mask */\r
-#define GPIO_PORT_SET1_SETP15_Pos 15 /*!< GPIO_PORT SET1: SETP15 Position */\r
-#define GPIO_PORT_SET1_SETP15_Msk (0x01UL << GPIO_PORT_SET1_SETP15_Pos) /*!< GPIO_PORT SET1: SETP15 Mask */\r
-#define GPIO_PORT_SET1_SETP16_Pos 16 /*!< GPIO_PORT SET1: SETP16 Position */\r
-#define GPIO_PORT_SET1_SETP16_Msk (0x01UL << GPIO_PORT_SET1_SETP16_Pos) /*!< GPIO_PORT SET1: SETP16 Mask */\r
-#define GPIO_PORT_SET1_SETP17_Pos 17 /*!< GPIO_PORT SET1: SETP17 Position */\r
-#define GPIO_PORT_SET1_SETP17_Msk (0x01UL << GPIO_PORT_SET1_SETP17_Pos) /*!< GPIO_PORT SET1: SETP17 Mask */\r
-#define GPIO_PORT_SET1_SETP18_Pos 18 /*!< GPIO_PORT SET1: SETP18 Position */\r
-#define GPIO_PORT_SET1_SETP18_Msk (0x01UL << GPIO_PORT_SET1_SETP18_Pos) /*!< GPIO_PORT SET1: SETP18 Mask */\r
-#define GPIO_PORT_SET1_SETP19_Pos 19 /*!< GPIO_PORT SET1: SETP19 Position */\r
-#define GPIO_PORT_SET1_SETP19_Msk (0x01UL << GPIO_PORT_SET1_SETP19_Pos) /*!< GPIO_PORT SET1: SETP19 Mask */\r
-#define GPIO_PORT_SET1_SETP20_Pos 20 /*!< GPIO_PORT SET1: SETP20 Position */\r
-#define GPIO_PORT_SET1_SETP20_Msk (0x01UL << GPIO_PORT_SET1_SETP20_Pos) /*!< GPIO_PORT SET1: SETP20 Mask */\r
-#define GPIO_PORT_SET1_SETP21_Pos 21 /*!< GPIO_PORT SET1: SETP21 Position */\r
-#define GPIO_PORT_SET1_SETP21_Msk (0x01UL << GPIO_PORT_SET1_SETP21_Pos) /*!< GPIO_PORT SET1: SETP21 Mask */\r
-#define GPIO_PORT_SET1_SETP22_Pos 22 /*!< GPIO_PORT SET1: SETP22 Position */\r
-#define GPIO_PORT_SET1_SETP22_Msk (0x01UL << GPIO_PORT_SET1_SETP22_Pos) /*!< GPIO_PORT SET1: SETP22 Mask */\r
-#define GPIO_PORT_SET1_SETP23_Pos 23 /*!< GPIO_PORT SET1: SETP23 Position */\r
-#define GPIO_PORT_SET1_SETP23_Msk (0x01UL << GPIO_PORT_SET1_SETP23_Pos) /*!< GPIO_PORT SET1: SETP23 Mask */\r
-#define GPIO_PORT_SET1_SETP24_Pos 24 /*!< GPIO_PORT SET1: SETP24 Position */\r
-#define GPIO_PORT_SET1_SETP24_Msk (0x01UL << GPIO_PORT_SET1_SETP24_Pos) /*!< GPIO_PORT SET1: SETP24 Mask */\r
-#define GPIO_PORT_SET1_SETP25_Pos 25 /*!< GPIO_PORT SET1: SETP25 Position */\r
-#define GPIO_PORT_SET1_SETP25_Msk (0x01UL << GPIO_PORT_SET1_SETP25_Pos) /*!< GPIO_PORT SET1: SETP25 Mask */\r
-#define GPIO_PORT_SET1_SETP26_Pos 26 /*!< GPIO_PORT SET1: SETP26 Position */\r
-#define GPIO_PORT_SET1_SETP26_Msk (0x01UL << GPIO_PORT_SET1_SETP26_Pos) /*!< GPIO_PORT SET1: SETP26 Mask */\r
-#define GPIO_PORT_SET1_SETP27_Pos 27 /*!< GPIO_PORT SET1: SETP27 Position */\r
-#define GPIO_PORT_SET1_SETP27_Msk (0x01UL << GPIO_PORT_SET1_SETP27_Pos) /*!< GPIO_PORT SET1: SETP27 Mask */\r
-#define GPIO_PORT_SET1_SETP28_Pos 28 /*!< GPIO_PORT SET1: SETP28 Position */\r
-#define GPIO_PORT_SET1_SETP28_Msk (0x01UL << GPIO_PORT_SET1_SETP28_Pos) /*!< GPIO_PORT SET1: SETP28 Mask */\r
-#define GPIO_PORT_SET1_SETP29_Pos 29 /*!< GPIO_PORT SET1: SETP29 Position */\r
-#define GPIO_PORT_SET1_SETP29_Msk (0x01UL << GPIO_PORT_SET1_SETP29_Pos) /*!< GPIO_PORT SET1: SETP29 Mask */\r
-#define GPIO_PORT_SET1_SETP30_Pos 30 /*!< GPIO_PORT SET1: SETP30 Position */\r
-#define GPIO_PORT_SET1_SETP30_Msk (0x01UL << GPIO_PORT_SET1_SETP30_Pos) /*!< GPIO_PORT SET1: SETP30 Mask */\r
-#define GPIO_PORT_SET1_SETP31_Pos 31 /*!< GPIO_PORT SET1: SETP31 Position */\r
-#define GPIO_PORT_SET1_SETP31_Msk (0x01UL << GPIO_PORT_SET1_SETP31_Pos) /*!< GPIO_PORT SET1: SETP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_SET2 -----------------------------------------\r
-#define GPIO_PORT_SET2_SETP0_Pos 0 /*!< GPIO_PORT SET2: SETP0 Position */\r
-#define GPIO_PORT_SET2_SETP0_Msk (0x01UL << GPIO_PORT_SET2_SETP0_Pos) /*!< GPIO_PORT SET2: SETP0 Mask */\r
-#define GPIO_PORT_SET2_SETP1_Pos 1 /*!< GPIO_PORT SET2: SETP1 Position */\r
-#define GPIO_PORT_SET2_SETP1_Msk (0x01UL << GPIO_PORT_SET2_SETP1_Pos) /*!< GPIO_PORT SET2: SETP1 Mask */\r
-#define GPIO_PORT_SET2_SETP2_Pos 2 /*!< GPIO_PORT SET2: SETP2 Position */\r
-#define GPIO_PORT_SET2_SETP2_Msk (0x01UL << GPIO_PORT_SET2_SETP2_Pos) /*!< GPIO_PORT SET2: SETP2 Mask */\r
-#define GPIO_PORT_SET2_SETP3_Pos 3 /*!< GPIO_PORT SET2: SETP3 Position */\r
-#define GPIO_PORT_SET2_SETP3_Msk (0x01UL << GPIO_PORT_SET2_SETP3_Pos) /*!< GPIO_PORT SET2: SETP3 Mask */\r
-#define GPIO_PORT_SET2_SETP4_Pos 4 /*!< GPIO_PORT SET2: SETP4 Position */\r
-#define GPIO_PORT_SET2_SETP4_Msk (0x01UL << GPIO_PORT_SET2_SETP4_Pos) /*!< GPIO_PORT SET2: SETP4 Mask */\r
-#define GPIO_PORT_SET2_SETP5_Pos 5 /*!< GPIO_PORT SET2: SETP5 Position */\r
-#define GPIO_PORT_SET2_SETP5_Msk (0x01UL << GPIO_PORT_SET2_SETP5_Pos) /*!< GPIO_PORT SET2: SETP5 Mask */\r
-#define GPIO_PORT_SET2_SETP6_Pos 6 /*!< GPIO_PORT SET2: SETP6 Position */\r
-#define GPIO_PORT_SET2_SETP6_Msk (0x01UL << GPIO_PORT_SET2_SETP6_Pos) /*!< GPIO_PORT SET2: SETP6 Mask */\r
-#define GPIO_PORT_SET2_SETP7_Pos 7 /*!< GPIO_PORT SET2: SETP7 Position */\r
-#define GPIO_PORT_SET2_SETP7_Msk (0x01UL << GPIO_PORT_SET2_SETP7_Pos) /*!< GPIO_PORT SET2: SETP7 Mask */\r
-#define GPIO_PORT_SET2_SETP8_Pos 8 /*!< GPIO_PORT SET2: SETP8 Position */\r
-#define GPIO_PORT_SET2_SETP8_Msk (0x01UL << GPIO_PORT_SET2_SETP8_Pos) /*!< GPIO_PORT SET2: SETP8 Mask */\r
-#define GPIO_PORT_SET2_SETP9_Pos 9 /*!< GPIO_PORT SET2: SETP9 Position */\r
-#define GPIO_PORT_SET2_SETP9_Msk (0x01UL << GPIO_PORT_SET2_SETP9_Pos) /*!< GPIO_PORT SET2: SETP9 Mask */\r
-#define GPIO_PORT_SET2_SETP10_Pos 10 /*!< GPIO_PORT SET2: SETP10 Position */\r
-#define GPIO_PORT_SET2_SETP10_Msk (0x01UL << GPIO_PORT_SET2_SETP10_Pos) /*!< GPIO_PORT SET2: SETP10 Mask */\r
-#define GPIO_PORT_SET2_SETP11_Pos 11 /*!< GPIO_PORT SET2: SETP11 Position */\r
-#define GPIO_PORT_SET2_SETP11_Msk (0x01UL << GPIO_PORT_SET2_SETP11_Pos) /*!< GPIO_PORT SET2: SETP11 Mask */\r
-#define GPIO_PORT_SET2_SETP12_Pos 12 /*!< GPIO_PORT SET2: SETP12 Position */\r
-#define GPIO_PORT_SET2_SETP12_Msk (0x01UL << GPIO_PORT_SET2_SETP12_Pos) /*!< GPIO_PORT SET2: SETP12 Mask */\r
-#define GPIO_PORT_SET2_SETP13_Pos 13 /*!< GPIO_PORT SET2: SETP13 Position */\r
-#define GPIO_PORT_SET2_SETP13_Msk (0x01UL << GPIO_PORT_SET2_SETP13_Pos) /*!< GPIO_PORT SET2: SETP13 Mask */\r
-#define GPIO_PORT_SET2_SETP14_Pos 14 /*!< GPIO_PORT SET2: SETP14 Position */\r
-#define GPIO_PORT_SET2_SETP14_Msk (0x01UL << GPIO_PORT_SET2_SETP14_Pos) /*!< GPIO_PORT SET2: SETP14 Mask */\r
-#define GPIO_PORT_SET2_SETP15_Pos 15 /*!< GPIO_PORT SET2: SETP15 Position */\r
-#define GPIO_PORT_SET2_SETP15_Msk (0x01UL << GPIO_PORT_SET2_SETP15_Pos) /*!< GPIO_PORT SET2: SETP15 Mask */\r
-#define GPIO_PORT_SET2_SETP16_Pos 16 /*!< GPIO_PORT SET2: SETP16 Position */\r
-#define GPIO_PORT_SET2_SETP16_Msk (0x01UL << GPIO_PORT_SET2_SETP16_Pos) /*!< GPIO_PORT SET2: SETP16 Mask */\r
-#define GPIO_PORT_SET2_SETP17_Pos 17 /*!< GPIO_PORT SET2: SETP17 Position */\r
-#define GPIO_PORT_SET2_SETP17_Msk (0x01UL << GPIO_PORT_SET2_SETP17_Pos) /*!< GPIO_PORT SET2: SETP17 Mask */\r
-#define GPIO_PORT_SET2_SETP18_Pos 18 /*!< GPIO_PORT SET2: SETP18 Position */\r
-#define GPIO_PORT_SET2_SETP18_Msk (0x01UL << GPIO_PORT_SET2_SETP18_Pos) /*!< GPIO_PORT SET2: SETP18 Mask */\r
-#define GPIO_PORT_SET2_SETP19_Pos 19 /*!< GPIO_PORT SET2: SETP19 Position */\r
-#define GPIO_PORT_SET2_SETP19_Msk (0x01UL << GPIO_PORT_SET2_SETP19_Pos) /*!< GPIO_PORT SET2: SETP19 Mask */\r
-#define GPIO_PORT_SET2_SETP20_Pos 20 /*!< GPIO_PORT SET2: SETP20 Position */\r
-#define GPIO_PORT_SET2_SETP20_Msk (0x01UL << GPIO_PORT_SET2_SETP20_Pos) /*!< GPIO_PORT SET2: SETP20 Mask */\r
-#define GPIO_PORT_SET2_SETP21_Pos 21 /*!< GPIO_PORT SET2: SETP21 Position */\r
-#define GPIO_PORT_SET2_SETP21_Msk (0x01UL << GPIO_PORT_SET2_SETP21_Pos) /*!< GPIO_PORT SET2: SETP21 Mask */\r
-#define GPIO_PORT_SET2_SETP22_Pos 22 /*!< GPIO_PORT SET2: SETP22 Position */\r
-#define GPIO_PORT_SET2_SETP22_Msk (0x01UL << GPIO_PORT_SET2_SETP22_Pos) /*!< GPIO_PORT SET2: SETP22 Mask */\r
-#define GPIO_PORT_SET2_SETP23_Pos 23 /*!< GPIO_PORT SET2: SETP23 Position */\r
-#define GPIO_PORT_SET2_SETP23_Msk (0x01UL << GPIO_PORT_SET2_SETP23_Pos) /*!< GPIO_PORT SET2: SETP23 Mask */\r
-#define GPIO_PORT_SET2_SETP24_Pos 24 /*!< GPIO_PORT SET2: SETP24 Position */\r
-#define GPIO_PORT_SET2_SETP24_Msk (0x01UL << GPIO_PORT_SET2_SETP24_Pos) /*!< GPIO_PORT SET2: SETP24 Mask */\r
-#define GPIO_PORT_SET2_SETP25_Pos 25 /*!< GPIO_PORT SET2: SETP25 Position */\r
-#define GPIO_PORT_SET2_SETP25_Msk (0x01UL << GPIO_PORT_SET2_SETP25_Pos) /*!< GPIO_PORT SET2: SETP25 Mask */\r
-#define GPIO_PORT_SET2_SETP26_Pos 26 /*!< GPIO_PORT SET2: SETP26 Position */\r
-#define GPIO_PORT_SET2_SETP26_Msk (0x01UL << GPIO_PORT_SET2_SETP26_Pos) /*!< GPIO_PORT SET2: SETP26 Mask */\r
-#define GPIO_PORT_SET2_SETP27_Pos 27 /*!< GPIO_PORT SET2: SETP27 Position */\r
-#define GPIO_PORT_SET2_SETP27_Msk (0x01UL << GPIO_PORT_SET2_SETP27_Pos) /*!< GPIO_PORT SET2: SETP27 Mask */\r
-#define GPIO_PORT_SET2_SETP28_Pos 28 /*!< GPIO_PORT SET2: SETP28 Position */\r
-#define GPIO_PORT_SET2_SETP28_Msk (0x01UL << GPIO_PORT_SET2_SETP28_Pos) /*!< GPIO_PORT SET2: SETP28 Mask */\r
-#define GPIO_PORT_SET2_SETP29_Pos 29 /*!< GPIO_PORT SET2: SETP29 Position */\r
-#define GPIO_PORT_SET2_SETP29_Msk (0x01UL << GPIO_PORT_SET2_SETP29_Pos) /*!< GPIO_PORT SET2: SETP29 Mask */\r
-#define GPIO_PORT_SET2_SETP30_Pos 30 /*!< GPIO_PORT SET2: SETP30 Position */\r
-#define GPIO_PORT_SET2_SETP30_Msk (0x01UL << GPIO_PORT_SET2_SETP30_Pos) /*!< GPIO_PORT SET2: SETP30 Mask */\r
-#define GPIO_PORT_SET2_SETP31_Pos 31 /*!< GPIO_PORT SET2: SETP31 Position */\r
-#define GPIO_PORT_SET2_SETP31_Msk (0x01UL << GPIO_PORT_SET2_SETP31_Pos) /*!< GPIO_PORT SET2: SETP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_SET3 -----------------------------------------\r
-#define GPIO_PORT_SET3_SETP0_Pos 0 /*!< GPIO_PORT SET3: SETP0 Position */\r
-#define GPIO_PORT_SET3_SETP0_Msk (0x01UL << GPIO_PORT_SET3_SETP0_Pos) /*!< GPIO_PORT SET3: SETP0 Mask */\r
-#define GPIO_PORT_SET3_SETP1_Pos 1 /*!< GPIO_PORT SET3: SETP1 Position */\r
-#define GPIO_PORT_SET3_SETP1_Msk (0x01UL << GPIO_PORT_SET3_SETP1_Pos) /*!< GPIO_PORT SET3: SETP1 Mask */\r
-#define GPIO_PORT_SET3_SETP2_Pos 2 /*!< GPIO_PORT SET3: SETP2 Position */\r
-#define GPIO_PORT_SET3_SETP2_Msk (0x01UL << GPIO_PORT_SET3_SETP2_Pos) /*!< GPIO_PORT SET3: SETP2 Mask */\r
-#define GPIO_PORT_SET3_SETP3_Pos 3 /*!< GPIO_PORT SET3: SETP3 Position */\r
-#define GPIO_PORT_SET3_SETP3_Msk (0x01UL << GPIO_PORT_SET3_SETP3_Pos) /*!< GPIO_PORT SET3: SETP3 Mask */\r
-#define GPIO_PORT_SET3_SETP4_Pos 4 /*!< GPIO_PORT SET3: SETP4 Position */\r
-#define GPIO_PORT_SET3_SETP4_Msk (0x01UL << GPIO_PORT_SET3_SETP4_Pos) /*!< GPIO_PORT SET3: SETP4 Mask */\r
-#define GPIO_PORT_SET3_SETP5_Pos 5 /*!< GPIO_PORT SET3: SETP5 Position */\r
-#define GPIO_PORT_SET3_SETP5_Msk (0x01UL << GPIO_PORT_SET3_SETP5_Pos) /*!< GPIO_PORT SET3: SETP5 Mask */\r
-#define GPIO_PORT_SET3_SETP6_Pos 6 /*!< GPIO_PORT SET3: SETP6 Position */\r
-#define GPIO_PORT_SET3_SETP6_Msk (0x01UL << GPIO_PORT_SET3_SETP6_Pos) /*!< GPIO_PORT SET3: SETP6 Mask */\r
-#define GPIO_PORT_SET3_SETP7_Pos 7 /*!< GPIO_PORT SET3: SETP7 Position */\r
-#define GPIO_PORT_SET3_SETP7_Msk (0x01UL << GPIO_PORT_SET3_SETP7_Pos) /*!< GPIO_PORT SET3: SETP7 Mask */\r
-#define GPIO_PORT_SET3_SETP8_Pos 8 /*!< GPIO_PORT SET3: SETP8 Position */\r
-#define GPIO_PORT_SET3_SETP8_Msk (0x01UL << GPIO_PORT_SET3_SETP8_Pos) /*!< GPIO_PORT SET3: SETP8 Mask */\r
-#define GPIO_PORT_SET3_SETP9_Pos 9 /*!< GPIO_PORT SET3: SETP9 Position */\r
-#define GPIO_PORT_SET3_SETP9_Msk (0x01UL << GPIO_PORT_SET3_SETP9_Pos) /*!< GPIO_PORT SET3: SETP9 Mask */\r
-#define GPIO_PORT_SET3_SETP10_Pos 10 /*!< GPIO_PORT SET3: SETP10 Position */\r
-#define GPIO_PORT_SET3_SETP10_Msk (0x01UL << GPIO_PORT_SET3_SETP10_Pos) /*!< GPIO_PORT SET3: SETP10 Mask */\r
-#define GPIO_PORT_SET3_SETP11_Pos 11 /*!< GPIO_PORT SET3: SETP11 Position */\r
-#define GPIO_PORT_SET3_SETP11_Msk (0x01UL << GPIO_PORT_SET3_SETP11_Pos) /*!< GPIO_PORT SET3: SETP11 Mask */\r
-#define GPIO_PORT_SET3_SETP12_Pos 12 /*!< GPIO_PORT SET3: SETP12 Position */\r
-#define GPIO_PORT_SET3_SETP12_Msk (0x01UL << GPIO_PORT_SET3_SETP12_Pos) /*!< GPIO_PORT SET3: SETP12 Mask */\r
-#define GPIO_PORT_SET3_SETP13_Pos 13 /*!< GPIO_PORT SET3: SETP13 Position */\r
-#define GPIO_PORT_SET3_SETP13_Msk (0x01UL << GPIO_PORT_SET3_SETP13_Pos) /*!< GPIO_PORT SET3: SETP13 Mask */\r
-#define GPIO_PORT_SET3_SETP14_Pos 14 /*!< GPIO_PORT SET3: SETP14 Position */\r
-#define GPIO_PORT_SET3_SETP14_Msk (0x01UL << GPIO_PORT_SET3_SETP14_Pos) /*!< GPIO_PORT SET3: SETP14 Mask */\r
-#define GPIO_PORT_SET3_SETP15_Pos 15 /*!< GPIO_PORT SET3: SETP15 Position */\r
-#define GPIO_PORT_SET3_SETP15_Msk (0x01UL << GPIO_PORT_SET3_SETP15_Pos) /*!< GPIO_PORT SET3: SETP15 Mask */\r
-#define GPIO_PORT_SET3_SETP16_Pos 16 /*!< GPIO_PORT SET3: SETP16 Position */\r
-#define GPIO_PORT_SET3_SETP16_Msk (0x01UL << GPIO_PORT_SET3_SETP16_Pos) /*!< GPIO_PORT SET3: SETP16 Mask */\r
-#define GPIO_PORT_SET3_SETP17_Pos 17 /*!< GPIO_PORT SET3: SETP17 Position */\r
-#define GPIO_PORT_SET3_SETP17_Msk (0x01UL << GPIO_PORT_SET3_SETP17_Pos) /*!< GPIO_PORT SET3: SETP17 Mask */\r
-#define GPIO_PORT_SET3_SETP18_Pos 18 /*!< GPIO_PORT SET3: SETP18 Position */\r
-#define GPIO_PORT_SET3_SETP18_Msk (0x01UL << GPIO_PORT_SET3_SETP18_Pos) /*!< GPIO_PORT SET3: SETP18 Mask */\r
-#define GPIO_PORT_SET3_SETP19_Pos 19 /*!< GPIO_PORT SET3: SETP19 Position */\r
-#define GPIO_PORT_SET3_SETP19_Msk (0x01UL << GPIO_PORT_SET3_SETP19_Pos) /*!< GPIO_PORT SET3: SETP19 Mask */\r
-#define GPIO_PORT_SET3_SETP20_Pos 20 /*!< GPIO_PORT SET3: SETP20 Position */\r
-#define GPIO_PORT_SET3_SETP20_Msk (0x01UL << GPIO_PORT_SET3_SETP20_Pos) /*!< GPIO_PORT SET3: SETP20 Mask */\r
-#define GPIO_PORT_SET3_SETP21_Pos 21 /*!< GPIO_PORT SET3: SETP21 Position */\r
-#define GPIO_PORT_SET3_SETP21_Msk (0x01UL << GPIO_PORT_SET3_SETP21_Pos) /*!< GPIO_PORT SET3: SETP21 Mask */\r
-#define GPIO_PORT_SET3_SETP22_Pos 22 /*!< GPIO_PORT SET3: SETP22 Position */\r
-#define GPIO_PORT_SET3_SETP22_Msk (0x01UL << GPIO_PORT_SET3_SETP22_Pos) /*!< GPIO_PORT SET3: SETP22 Mask */\r
-#define GPIO_PORT_SET3_SETP23_Pos 23 /*!< GPIO_PORT SET3: SETP23 Position */\r
-#define GPIO_PORT_SET3_SETP23_Msk (0x01UL << GPIO_PORT_SET3_SETP23_Pos) /*!< GPIO_PORT SET3: SETP23 Mask */\r
-#define GPIO_PORT_SET3_SETP24_Pos 24 /*!< GPIO_PORT SET3: SETP24 Position */\r
-#define GPIO_PORT_SET3_SETP24_Msk (0x01UL << GPIO_PORT_SET3_SETP24_Pos) /*!< GPIO_PORT SET3: SETP24 Mask */\r
-#define GPIO_PORT_SET3_SETP25_Pos 25 /*!< GPIO_PORT SET3: SETP25 Position */\r
-#define GPIO_PORT_SET3_SETP25_Msk (0x01UL << GPIO_PORT_SET3_SETP25_Pos) /*!< GPIO_PORT SET3: SETP25 Mask */\r
-#define GPIO_PORT_SET3_SETP26_Pos 26 /*!< GPIO_PORT SET3: SETP26 Position */\r
-#define GPIO_PORT_SET3_SETP26_Msk (0x01UL << GPIO_PORT_SET3_SETP26_Pos) /*!< GPIO_PORT SET3: SETP26 Mask */\r
-#define GPIO_PORT_SET3_SETP27_Pos 27 /*!< GPIO_PORT SET3: SETP27 Position */\r
-#define GPIO_PORT_SET3_SETP27_Msk (0x01UL << GPIO_PORT_SET3_SETP27_Pos) /*!< GPIO_PORT SET3: SETP27 Mask */\r
-#define GPIO_PORT_SET3_SETP28_Pos 28 /*!< GPIO_PORT SET3: SETP28 Position */\r
-#define GPIO_PORT_SET3_SETP28_Msk (0x01UL << GPIO_PORT_SET3_SETP28_Pos) /*!< GPIO_PORT SET3: SETP28 Mask */\r
-#define GPIO_PORT_SET3_SETP29_Pos 29 /*!< GPIO_PORT SET3: SETP29 Position */\r
-#define GPIO_PORT_SET3_SETP29_Msk (0x01UL << GPIO_PORT_SET3_SETP29_Pos) /*!< GPIO_PORT SET3: SETP29 Mask */\r
-#define GPIO_PORT_SET3_SETP30_Pos 30 /*!< GPIO_PORT SET3: SETP30 Position */\r
-#define GPIO_PORT_SET3_SETP30_Msk (0x01UL << GPIO_PORT_SET3_SETP30_Pos) /*!< GPIO_PORT SET3: SETP30 Mask */\r
-#define GPIO_PORT_SET3_SETP31_Pos 31 /*!< GPIO_PORT SET3: SETP31 Position */\r
-#define GPIO_PORT_SET3_SETP31_Msk (0x01UL << GPIO_PORT_SET3_SETP31_Pos) /*!< GPIO_PORT SET3: SETP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_SET4 -----------------------------------------\r
-#define GPIO_PORT_SET4_SETP0_Pos 0 /*!< GPIO_PORT SET4: SETP0 Position */\r
-#define GPIO_PORT_SET4_SETP0_Msk (0x01UL << GPIO_PORT_SET4_SETP0_Pos) /*!< GPIO_PORT SET4: SETP0 Mask */\r
-#define GPIO_PORT_SET4_SETP1_Pos 1 /*!< GPIO_PORT SET4: SETP1 Position */\r
-#define GPIO_PORT_SET4_SETP1_Msk (0x01UL << GPIO_PORT_SET4_SETP1_Pos) /*!< GPIO_PORT SET4: SETP1 Mask */\r
-#define GPIO_PORT_SET4_SETP2_Pos 2 /*!< GPIO_PORT SET4: SETP2 Position */\r
-#define GPIO_PORT_SET4_SETP2_Msk (0x01UL << GPIO_PORT_SET4_SETP2_Pos) /*!< GPIO_PORT SET4: SETP2 Mask */\r
-#define GPIO_PORT_SET4_SETP3_Pos 3 /*!< GPIO_PORT SET4: SETP3 Position */\r
-#define GPIO_PORT_SET4_SETP3_Msk (0x01UL << GPIO_PORT_SET4_SETP3_Pos) /*!< GPIO_PORT SET4: SETP3 Mask */\r
-#define GPIO_PORT_SET4_SETP4_Pos 4 /*!< GPIO_PORT SET4: SETP4 Position */\r
-#define GPIO_PORT_SET4_SETP4_Msk (0x01UL << GPIO_PORT_SET4_SETP4_Pos) /*!< GPIO_PORT SET4: SETP4 Mask */\r
-#define GPIO_PORT_SET4_SETP5_Pos 5 /*!< GPIO_PORT SET4: SETP5 Position */\r
-#define GPIO_PORT_SET4_SETP5_Msk (0x01UL << GPIO_PORT_SET4_SETP5_Pos) /*!< GPIO_PORT SET4: SETP5 Mask */\r
-#define GPIO_PORT_SET4_SETP6_Pos 6 /*!< GPIO_PORT SET4: SETP6 Position */\r
-#define GPIO_PORT_SET4_SETP6_Msk (0x01UL << GPIO_PORT_SET4_SETP6_Pos) /*!< GPIO_PORT SET4: SETP6 Mask */\r
-#define GPIO_PORT_SET4_SETP7_Pos 7 /*!< GPIO_PORT SET4: SETP7 Position */\r
-#define GPIO_PORT_SET4_SETP7_Msk (0x01UL << GPIO_PORT_SET4_SETP7_Pos) /*!< GPIO_PORT SET4: SETP7 Mask */\r
-#define GPIO_PORT_SET4_SETP8_Pos 8 /*!< GPIO_PORT SET4: SETP8 Position */\r
-#define GPIO_PORT_SET4_SETP8_Msk (0x01UL << GPIO_PORT_SET4_SETP8_Pos) /*!< GPIO_PORT SET4: SETP8 Mask */\r
-#define GPIO_PORT_SET4_SETP9_Pos 9 /*!< GPIO_PORT SET4: SETP9 Position */\r
-#define GPIO_PORT_SET4_SETP9_Msk (0x01UL << GPIO_PORT_SET4_SETP9_Pos) /*!< GPIO_PORT SET4: SETP9 Mask */\r
-#define GPIO_PORT_SET4_SETP10_Pos 10 /*!< GPIO_PORT SET4: SETP10 Position */\r
-#define GPIO_PORT_SET4_SETP10_Msk (0x01UL << GPIO_PORT_SET4_SETP10_Pos) /*!< GPIO_PORT SET4: SETP10 Mask */\r
-#define GPIO_PORT_SET4_SETP11_Pos 11 /*!< GPIO_PORT SET4: SETP11 Position */\r
-#define GPIO_PORT_SET4_SETP11_Msk (0x01UL << GPIO_PORT_SET4_SETP11_Pos) /*!< GPIO_PORT SET4: SETP11 Mask */\r
-#define GPIO_PORT_SET4_SETP12_Pos 12 /*!< GPIO_PORT SET4: SETP12 Position */\r
-#define GPIO_PORT_SET4_SETP12_Msk (0x01UL << GPIO_PORT_SET4_SETP12_Pos) /*!< GPIO_PORT SET4: SETP12 Mask */\r
-#define GPIO_PORT_SET4_SETP13_Pos 13 /*!< GPIO_PORT SET4: SETP13 Position */\r
-#define GPIO_PORT_SET4_SETP13_Msk (0x01UL << GPIO_PORT_SET4_SETP13_Pos) /*!< GPIO_PORT SET4: SETP13 Mask */\r
-#define GPIO_PORT_SET4_SETP14_Pos 14 /*!< GPIO_PORT SET4: SETP14 Position */\r
-#define GPIO_PORT_SET4_SETP14_Msk (0x01UL << GPIO_PORT_SET4_SETP14_Pos) /*!< GPIO_PORT SET4: SETP14 Mask */\r
-#define GPIO_PORT_SET4_SETP15_Pos 15 /*!< GPIO_PORT SET4: SETP15 Position */\r
-#define GPIO_PORT_SET4_SETP15_Msk (0x01UL << GPIO_PORT_SET4_SETP15_Pos) /*!< GPIO_PORT SET4: SETP15 Mask */\r
-#define GPIO_PORT_SET4_SETP16_Pos 16 /*!< GPIO_PORT SET4: SETP16 Position */\r
-#define GPIO_PORT_SET4_SETP16_Msk (0x01UL << GPIO_PORT_SET4_SETP16_Pos) /*!< GPIO_PORT SET4: SETP16 Mask */\r
-#define GPIO_PORT_SET4_SETP17_Pos 17 /*!< GPIO_PORT SET4: SETP17 Position */\r
-#define GPIO_PORT_SET4_SETP17_Msk (0x01UL << GPIO_PORT_SET4_SETP17_Pos) /*!< GPIO_PORT SET4: SETP17 Mask */\r
-#define GPIO_PORT_SET4_SETP18_Pos 18 /*!< GPIO_PORT SET4: SETP18 Position */\r
-#define GPIO_PORT_SET4_SETP18_Msk (0x01UL << GPIO_PORT_SET4_SETP18_Pos) /*!< GPIO_PORT SET4: SETP18 Mask */\r
-#define GPIO_PORT_SET4_SETP19_Pos 19 /*!< GPIO_PORT SET4: SETP19 Position */\r
-#define GPIO_PORT_SET4_SETP19_Msk (0x01UL << GPIO_PORT_SET4_SETP19_Pos) /*!< GPIO_PORT SET4: SETP19 Mask */\r
-#define GPIO_PORT_SET4_SETP20_Pos 20 /*!< GPIO_PORT SET4: SETP20 Position */\r
-#define GPIO_PORT_SET4_SETP20_Msk (0x01UL << GPIO_PORT_SET4_SETP20_Pos) /*!< GPIO_PORT SET4: SETP20 Mask */\r
-#define GPIO_PORT_SET4_SETP21_Pos 21 /*!< GPIO_PORT SET4: SETP21 Position */\r
-#define GPIO_PORT_SET4_SETP21_Msk (0x01UL << GPIO_PORT_SET4_SETP21_Pos) /*!< GPIO_PORT SET4: SETP21 Mask */\r
-#define GPIO_PORT_SET4_SETP22_Pos 22 /*!< GPIO_PORT SET4: SETP22 Position */\r
-#define GPIO_PORT_SET4_SETP22_Msk (0x01UL << GPIO_PORT_SET4_SETP22_Pos) /*!< GPIO_PORT SET4: SETP22 Mask */\r
-#define GPIO_PORT_SET4_SETP23_Pos 23 /*!< GPIO_PORT SET4: SETP23 Position */\r
-#define GPIO_PORT_SET4_SETP23_Msk (0x01UL << GPIO_PORT_SET4_SETP23_Pos) /*!< GPIO_PORT SET4: SETP23 Mask */\r
-#define GPIO_PORT_SET4_SETP24_Pos 24 /*!< GPIO_PORT SET4: SETP24 Position */\r
-#define GPIO_PORT_SET4_SETP24_Msk (0x01UL << GPIO_PORT_SET4_SETP24_Pos) /*!< GPIO_PORT SET4: SETP24 Mask */\r
-#define GPIO_PORT_SET4_SETP25_Pos 25 /*!< GPIO_PORT SET4: SETP25 Position */\r
-#define GPIO_PORT_SET4_SETP25_Msk (0x01UL << GPIO_PORT_SET4_SETP25_Pos) /*!< GPIO_PORT SET4: SETP25 Mask */\r
-#define GPIO_PORT_SET4_SETP26_Pos 26 /*!< GPIO_PORT SET4: SETP26 Position */\r
-#define GPIO_PORT_SET4_SETP26_Msk (0x01UL << GPIO_PORT_SET4_SETP26_Pos) /*!< GPIO_PORT SET4: SETP26 Mask */\r
-#define GPIO_PORT_SET4_SETP27_Pos 27 /*!< GPIO_PORT SET4: SETP27 Position */\r
-#define GPIO_PORT_SET4_SETP27_Msk (0x01UL << GPIO_PORT_SET4_SETP27_Pos) /*!< GPIO_PORT SET4: SETP27 Mask */\r
-#define GPIO_PORT_SET4_SETP28_Pos 28 /*!< GPIO_PORT SET4: SETP28 Position */\r
-#define GPIO_PORT_SET4_SETP28_Msk (0x01UL << GPIO_PORT_SET4_SETP28_Pos) /*!< GPIO_PORT SET4: SETP28 Mask */\r
-#define GPIO_PORT_SET4_SETP29_Pos 29 /*!< GPIO_PORT SET4: SETP29 Position */\r
-#define GPIO_PORT_SET4_SETP29_Msk (0x01UL << GPIO_PORT_SET4_SETP29_Pos) /*!< GPIO_PORT SET4: SETP29 Mask */\r
-#define GPIO_PORT_SET4_SETP30_Pos 30 /*!< GPIO_PORT SET4: SETP30 Position */\r
-#define GPIO_PORT_SET4_SETP30_Msk (0x01UL << GPIO_PORT_SET4_SETP30_Pos) /*!< GPIO_PORT SET4: SETP30 Mask */\r
-#define GPIO_PORT_SET4_SETP31_Pos 31 /*!< GPIO_PORT SET4: SETP31 Position */\r
-#define GPIO_PORT_SET4_SETP31_Msk (0x01UL << GPIO_PORT_SET4_SETP31_Pos) /*!< GPIO_PORT SET4: SETP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_SET5 -----------------------------------------\r
-#define GPIO_PORT_SET5_SETP0_Pos 0 /*!< GPIO_PORT SET5: SETP0 Position */\r
-#define GPIO_PORT_SET5_SETP0_Msk (0x01UL << GPIO_PORT_SET5_SETP0_Pos) /*!< GPIO_PORT SET5: SETP0 Mask */\r
-#define GPIO_PORT_SET5_SETP1_Pos 1 /*!< GPIO_PORT SET5: SETP1 Position */\r
-#define GPIO_PORT_SET5_SETP1_Msk (0x01UL << GPIO_PORT_SET5_SETP1_Pos) /*!< GPIO_PORT SET5: SETP1 Mask */\r
-#define GPIO_PORT_SET5_SETP2_Pos 2 /*!< GPIO_PORT SET5: SETP2 Position */\r
-#define GPIO_PORT_SET5_SETP2_Msk (0x01UL << GPIO_PORT_SET5_SETP2_Pos) /*!< GPIO_PORT SET5: SETP2 Mask */\r
-#define GPIO_PORT_SET5_SETP3_Pos 3 /*!< GPIO_PORT SET5: SETP3 Position */\r
-#define GPIO_PORT_SET5_SETP3_Msk (0x01UL << GPIO_PORT_SET5_SETP3_Pos) /*!< GPIO_PORT SET5: SETP3 Mask */\r
-#define GPIO_PORT_SET5_SETP4_Pos 4 /*!< GPIO_PORT SET5: SETP4 Position */\r
-#define GPIO_PORT_SET5_SETP4_Msk (0x01UL << GPIO_PORT_SET5_SETP4_Pos) /*!< GPIO_PORT SET5: SETP4 Mask */\r
-#define GPIO_PORT_SET5_SETP5_Pos 5 /*!< GPIO_PORT SET5: SETP5 Position */\r
-#define GPIO_PORT_SET5_SETP5_Msk (0x01UL << GPIO_PORT_SET5_SETP5_Pos) /*!< GPIO_PORT SET5: SETP5 Mask */\r
-#define GPIO_PORT_SET5_SETP6_Pos 6 /*!< GPIO_PORT SET5: SETP6 Position */\r
-#define GPIO_PORT_SET5_SETP6_Msk (0x01UL << GPIO_PORT_SET5_SETP6_Pos) /*!< GPIO_PORT SET5: SETP6 Mask */\r
-#define GPIO_PORT_SET5_SETP7_Pos 7 /*!< GPIO_PORT SET5: SETP7 Position */\r
-#define GPIO_PORT_SET5_SETP7_Msk (0x01UL << GPIO_PORT_SET5_SETP7_Pos) /*!< GPIO_PORT SET5: SETP7 Mask */\r
-#define GPIO_PORT_SET5_SETP8_Pos 8 /*!< GPIO_PORT SET5: SETP8 Position */\r
-#define GPIO_PORT_SET5_SETP8_Msk (0x01UL << GPIO_PORT_SET5_SETP8_Pos) /*!< GPIO_PORT SET5: SETP8 Mask */\r
-#define GPIO_PORT_SET5_SETP9_Pos 9 /*!< GPIO_PORT SET5: SETP9 Position */\r
-#define GPIO_PORT_SET5_SETP9_Msk (0x01UL << GPIO_PORT_SET5_SETP9_Pos) /*!< GPIO_PORT SET5: SETP9 Mask */\r
-#define GPIO_PORT_SET5_SETP10_Pos 10 /*!< GPIO_PORT SET5: SETP10 Position */\r
-#define GPIO_PORT_SET5_SETP10_Msk (0x01UL << GPIO_PORT_SET5_SETP10_Pos) /*!< GPIO_PORT SET5: SETP10 Mask */\r
-#define GPIO_PORT_SET5_SETP11_Pos 11 /*!< GPIO_PORT SET5: SETP11 Position */\r
-#define GPIO_PORT_SET5_SETP11_Msk (0x01UL << GPIO_PORT_SET5_SETP11_Pos) /*!< GPIO_PORT SET5: SETP11 Mask */\r
-#define GPIO_PORT_SET5_SETP12_Pos 12 /*!< GPIO_PORT SET5: SETP12 Position */\r
-#define GPIO_PORT_SET5_SETP12_Msk (0x01UL << GPIO_PORT_SET5_SETP12_Pos) /*!< GPIO_PORT SET5: SETP12 Mask */\r
-#define GPIO_PORT_SET5_SETP13_Pos 13 /*!< GPIO_PORT SET5: SETP13 Position */\r
-#define GPIO_PORT_SET5_SETP13_Msk (0x01UL << GPIO_PORT_SET5_SETP13_Pos) /*!< GPIO_PORT SET5: SETP13 Mask */\r
-#define GPIO_PORT_SET5_SETP14_Pos 14 /*!< GPIO_PORT SET5: SETP14 Position */\r
-#define GPIO_PORT_SET5_SETP14_Msk (0x01UL << GPIO_PORT_SET5_SETP14_Pos) /*!< GPIO_PORT SET5: SETP14 Mask */\r
-#define GPIO_PORT_SET5_SETP15_Pos 15 /*!< GPIO_PORT SET5: SETP15 Position */\r
-#define GPIO_PORT_SET5_SETP15_Msk (0x01UL << GPIO_PORT_SET5_SETP15_Pos) /*!< GPIO_PORT SET5: SETP15 Mask */\r
-#define GPIO_PORT_SET5_SETP16_Pos 16 /*!< GPIO_PORT SET5: SETP16 Position */\r
-#define GPIO_PORT_SET5_SETP16_Msk (0x01UL << GPIO_PORT_SET5_SETP16_Pos) /*!< GPIO_PORT SET5: SETP16 Mask */\r
-#define GPIO_PORT_SET5_SETP17_Pos 17 /*!< GPIO_PORT SET5: SETP17 Position */\r
-#define GPIO_PORT_SET5_SETP17_Msk (0x01UL << GPIO_PORT_SET5_SETP17_Pos) /*!< GPIO_PORT SET5: SETP17 Mask */\r
-#define GPIO_PORT_SET5_SETP18_Pos 18 /*!< GPIO_PORT SET5: SETP18 Position */\r
-#define GPIO_PORT_SET5_SETP18_Msk (0x01UL << GPIO_PORT_SET5_SETP18_Pos) /*!< GPIO_PORT SET5: SETP18 Mask */\r
-#define GPIO_PORT_SET5_SETP19_Pos 19 /*!< GPIO_PORT SET5: SETP19 Position */\r
-#define GPIO_PORT_SET5_SETP19_Msk (0x01UL << GPIO_PORT_SET5_SETP19_Pos) /*!< GPIO_PORT SET5: SETP19 Mask */\r
-#define GPIO_PORT_SET5_SETP20_Pos 20 /*!< GPIO_PORT SET5: SETP20 Position */\r
-#define GPIO_PORT_SET5_SETP20_Msk (0x01UL << GPIO_PORT_SET5_SETP20_Pos) /*!< GPIO_PORT SET5: SETP20 Mask */\r
-#define GPIO_PORT_SET5_SETP21_Pos 21 /*!< GPIO_PORT SET5: SETP21 Position */\r
-#define GPIO_PORT_SET5_SETP21_Msk (0x01UL << GPIO_PORT_SET5_SETP21_Pos) /*!< GPIO_PORT SET5: SETP21 Mask */\r
-#define GPIO_PORT_SET5_SETP22_Pos 22 /*!< GPIO_PORT SET5: SETP22 Position */\r
-#define GPIO_PORT_SET5_SETP22_Msk (0x01UL << GPIO_PORT_SET5_SETP22_Pos) /*!< GPIO_PORT SET5: SETP22 Mask */\r
-#define GPIO_PORT_SET5_SETP23_Pos 23 /*!< GPIO_PORT SET5: SETP23 Position */\r
-#define GPIO_PORT_SET5_SETP23_Msk (0x01UL << GPIO_PORT_SET5_SETP23_Pos) /*!< GPIO_PORT SET5: SETP23 Mask */\r
-#define GPIO_PORT_SET5_SETP24_Pos 24 /*!< GPIO_PORT SET5: SETP24 Position */\r
-#define GPIO_PORT_SET5_SETP24_Msk (0x01UL << GPIO_PORT_SET5_SETP24_Pos) /*!< GPIO_PORT SET5: SETP24 Mask */\r
-#define GPIO_PORT_SET5_SETP25_Pos 25 /*!< GPIO_PORT SET5: SETP25 Position */\r
-#define GPIO_PORT_SET5_SETP25_Msk (0x01UL << GPIO_PORT_SET5_SETP25_Pos) /*!< GPIO_PORT SET5: SETP25 Mask */\r
-#define GPIO_PORT_SET5_SETP26_Pos 26 /*!< GPIO_PORT SET5: SETP26 Position */\r
-#define GPIO_PORT_SET5_SETP26_Msk (0x01UL << GPIO_PORT_SET5_SETP26_Pos) /*!< GPIO_PORT SET5: SETP26 Mask */\r
-#define GPIO_PORT_SET5_SETP27_Pos 27 /*!< GPIO_PORT SET5: SETP27 Position */\r
-#define GPIO_PORT_SET5_SETP27_Msk (0x01UL << GPIO_PORT_SET5_SETP27_Pos) /*!< GPIO_PORT SET5: SETP27 Mask */\r
-#define GPIO_PORT_SET5_SETP28_Pos 28 /*!< GPIO_PORT SET5: SETP28 Position */\r
-#define GPIO_PORT_SET5_SETP28_Msk (0x01UL << GPIO_PORT_SET5_SETP28_Pos) /*!< GPIO_PORT SET5: SETP28 Mask */\r
-#define GPIO_PORT_SET5_SETP29_Pos 29 /*!< GPIO_PORT SET5: SETP29 Position */\r
-#define GPIO_PORT_SET5_SETP29_Msk (0x01UL << GPIO_PORT_SET5_SETP29_Pos) /*!< GPIO_PORT SET5: SETP29 Mask */\r
-#define GPIO_PORT_SET5_SETP30_Pos 30 /*!< GPIO_PORT SET5: SETP30 Position */\r
-#define GPIO_PORT_SET5_SETP30_Msk (0x01UL << GPIO_PORT_SET5_SETP30_Pos) /*!< GPIO_PORT SET5: SETP30 Mask */\r
-#define GPIO_PORT_SET5_SETP31_Pos 31 /*!< GPIO_PORT SET5: SETP31 Position */\r
-#define GPIO_PORT_SET5_SETP31_Msk (0x01UL << GPIO_PORT_SET5_SETP31_Pos) /*!< GPIO_PORT SET5: SETP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_SET6 -----------------------------------------\r
-#define GPIO_PORT_SET6_SETP0_Pos 0 /*!< GPIO_PORT SET6: SETP0 Position */\r
-#define GPIO_PORT_SET6_SETP0_Msk (0x01UL << GPIO_PORT_SET6_SETP0_Pos) /*!< GPIO_PORT SET6: SETP0 Mask */\r
-#define GPIO_PORT_SET6_SETP1_Pos 1 /*!< GPIO_PORT SET6: SETP1 Position */\r
-#define GPIO_PORT_SET6_SETP1_Msk (0x01UL << GPIO_PORT_SET6_SETP1_Pos) /*!< GPIO_PORT SET6: SETP1 Mask */\r
-#define GPIO_PORT_SET6_SETP2_Pos 2 /*!< GPIO_PORT SET6: SETP2 Position */\r
-#define GPIO_PORT_SET6_SETP2_Msk (0x01UL << GPIO_PORT_SET6_SETP2_Pos) /*!< GPIO_PORT SET6: SETP2 Mask */\r
-#define GPIO_PORT_SET6_SETP3_Pos 3 /*!< GPIO_PORT SET6: SETP3 Position */\r
-#define GPIO_PORT_SET6_SETP3_Msk (0x01UL << GPIO_PORT_SET6_SETP3_Pos) /*!< GPIO_PORT SET6: SETP3 Mask */\r
-#define GPIO_PORT_SET6_SETP4_Pos 4 /*!< GPIO_PORT SET6: SETP4 Position */\r
-#define GPIO_PORT_SET6_SETP4_Msk (0x01UL << GPIO_PORT_SET6_SETP4_Pos) /*!< GPIO_PORT SET6: SETP4 Mask */\r
-#define GPIO_PORT_SET6_SETP5_Pos 5 /*!< GPIO_PORT SET6: SETP5 Position */\r
-#define GPIO_PORT_SET6_SETP5_Msk (0x01UL << GPIO_PORT_SET6_SETP5_Pos) /*!< GPIO_PORT SET6: SETP5 Mask */\r
-#define GPIO_PORT_SET6_SETP6_Pos 6 /*!< GPIO_PORT SET6: SETP6 Position */\r
-#define GPIO_PORT_SET6_SETP6_Msk (0x01UL << GPIO_PORT_SET6_SETP6_Pos) /*!< GPIO_PORT SET6: SETP6 Mask */\r
-#define GPIO_PORT_SET6_SETP7_Pos 7 /*!< GPIO_PORT SET6: SETP7 Position */\r
-#define GPIO_PORT_SET6_SETP7_Msk (0x01UL << GPIO_PORT_SET6_SETP7_Pos) /*!< GPIO_PORT SET6: SETP7 Mask */\r
-#define GPIO_PORT_SET6_SETP8_Pos 8 /*!< GPIO_PORT SET6: SETP8 Position */\r
-#define GPIO_PORT_SET6_SETP8_Msk (0x01UL << GPIO_PORT_SET6_SETP8_Pos) /*!< GPIO_PORT SET6: SETP8 Mask */\r
-#define GPIO_PORT_SET6_SETP9_Pos 9 /*!< GPIO_PORT SET6: SETP9 Position */\r
-#define GPIO_PORT_SET6_SETP9_Msk (0x01UL << GPIO_PORT_SET6_SETP9_Pos) /*!< GPIO_PORT SET6: SETP9 Mask */\r
-#define GPIO_PORT_SET6_SETP10_Pos 10 /*!< GPIO_PORT SET6: SETP10 Position */\r
-#define GPIO_PORT_SET6_SETP10_Msk (0x01UL << GPIO_PORT_SET6_SETP10_Pos) /*!< GPIO_PORT SET6: SETP10 Mask */\r
-#define GPIO_PORT_SET6_SETP11_Pos 11 /*!< GPIO_PORT SET6: SETP11 Position */\r
-#define GPIO_PORT_SET6_SETP11_Msk (0x01UL << GPIO_PORT_SET6_SETP11_Pos) /*!< GPIO_PORT SET6: SETP11 Mask */\r
-#define GPIO_PORT_SET6_SETP12_Pos 12 /*!< GPIO_PORT SET6: SETP12 Position */\r
-#define GPIO_PORT_SET6_SETP12_Msk (0x01UL << GPIO_PORT_SET6_SETP12_Pos) /*!< GPIO_PORT SET6: SETP12 Mask */\r
-#define GPIO_PORT_SET6_SETP13_Pos 13 /*!< GPIO_PORT SET6: SETP13 Position */\r
-#define GPIO_PORT_SET6_SETP13_Msk (0x01UL << GPIO_PORT_SET6_SETP13_Pos) /*!< GPIO_PORT SET6: SETP13 Mask */\r
-#define GPIO_PORT_SET6_SETP14_Pos 14 /*!< GPIO_PORT SET6: SETP14 Position */\r
-#define GPIO_PORT_SET6_SETP14_Msk (0x01UL << GPIO_PORT_SET6_SETP14_Pos) /*!< GPIO_PORT SET6: SETP14 Mask */\r
-#define GPIO_PORT_SET6_SETP15_Pos 15 /*!< GPIO_PORT SET6: SETP15 Position */\r
-#define GPIO_PORT_SET6_SETP15_Msk (0x01UL << GPIO_PORT_SET6_SETP15_Pos) /*!< GPIO_PORT SET6: SETP15 Mask */\r
-#define GPIO_PORT_SET6_SETP16_Pos 16 /*!< GPIO_PORT SET6: SETP16 Position */\r
-#define GPIO_PORT_SET6_SETP16_Msk (0x01UL << GPIO_PORT_SET6_SETP16_Pos) /*!< GPIO_PORT SET6: SETP16 Mask */\r
-#define GPIO_PORT_SET6_SETP17_Pos 17 /*!< GPIO_PORT SET6: SETP17 Position */\r
-#define GPIO_PORT_SET6_SETP17_Msk (0x01UL << GPIO_PORT_SET6_SETP17_Pos) /*!< GPIO_PORT SET6: SETP17 Mask */\r
-#define GPIO_PORT_SET6_SETP18_Pos 18 /*!< GPIO_PORT SET6: SETP18 Position */\r
-#define GPIO_PORT_SET6_SETP18_Msk (0x01UL << GPIO_PORT_SET6_SETP18_Pos) /*!< GPIO_PORT SET6: SETP18 Mask */\r
-#define GPIO_PORT_SET6_SETP19_Pos 19 /*!< GPIO_PORT SET6: SETP19 Position */\r
-#define GPIO_PORT_SET6_SETP19_Msk (0x01UL << GPIO_PORT_SET6_SETP19_Pos) /*!< GPIO_PORT SET6: SETP19 Mask */\r
-#define GPIO_PORT_SET6_SETP20_Pos 20 /*!< GPIO_PORT SET6: SETP20 Position */\r
-#define GPIO_PORT_SET6_SETP20_Msk (0x01UL << GPIO_PORT_SET6_SETP20_Pos) /*!< GPIO_PORT SET6: SETP20 Mask */\r
-#define GPIO_PORT_SET6_SETP21_Pos 21 /*!< GPIO_PORT SET6: SETP21 Position */\r
-#define GPIO_PORT_SET6_SETP21_Msk (0x01UL << GPIO_PORT_SET6_SETP21_Pos) /*!< GPIO_PORT SET6: SETP21 Mask */\r
-#define GPIO_PORT_SET6_SETP22_Pos 22 /*!< GPIO_PORT SET6: SETP22 Position */\r
-#define GPIO_PORT_SET6_SETP22_Msk (0x01UL << GPIO_PORT_SET6_SETP22_Pos) /*!< GPIO_PORT SET6: SETP22 Mask */\r
-#define GPIO_PORT_SET6_SETP23_Pos 23 /*!< GPIO_PORT SET6: SETP23 Position */\r
-#define GPIO_PORT_SET6_SETP23_Msk (0x01UL << GPIO_PORT_SET6_SETP23_Pos) /*!< GPIO_PORT SET6: SETP23 Mask */\r
-#define GPIO_PORT_SET6_SETP24_Pos 24 /*!< GPIO_PORT SET6: SETP24 Position */\r
-#define GPIO_PORT_SET6_SETP24_Msk (0x01UL << GPIO_PORT_SET6_SETP24_Pos) /*!< GPIO_PORT SET6: SETP24 Mask */\r
-#define GPIO_PORT_SET6_SETP25_Pos 25 /*!< GPIO_PORT SET6: SETP25 Position */\r
-#define GPIO_PORT_SET6_SETP25_Msk (0x01UL << GPIO_PORT_SET6_SETP25_Pos) /*!< GPIO_PORT SET6: SETP25 Mask */\r
-#define GPIO_PORT_SET6_SETP26_Pos 26 /*!< GPIO_PORT SET6: SETP26 Position */\r
-#define GPIO_PORT_SET6_SETP26_Msk (0x01UL << GPIO_PORT_SET6_SETP26_Pos) /*!< GPIO_PORT SET6: SETP26 Mask */\r
-#define GPIO_PORT_SET6_SETP27_Pos 27 /*!< GPIO_PORT SET6: SETP27 Position */\r
-#define GPIO_PORT_SET6_SETP27_Msk (0x01UL << GPIO_PORT_SET6_SETP27_Pos) /*!< GPIO_PORT SET6: SETP27 Mask */\r
-#define GPIO_PORT_SET6_SETP28_Pos 28 /*!< GPIO_PORT SET6: SETP28 Position */\r
-#define GPIO_PORT_SET6_SETP28_Msk (0x01UL << GPIO_PORT_SET6_SETP28_Pos) /*!< GPIO_PORT SET6: SETP28 Mask */\r
-#define GPIO_PORT_SET6_SETP29_Pos 29 /*!< GPIO_PORT SET6: SETP29 Position */\r
-#define GPIO_PORT_SET6_SETP29_Msk (0x01UL << GPIO_PORT_SET6_SETP29_Pos) /*!< GPIO_PORT SET6: SETP29 Mask */\r
-#define GPIO_PORT_SET6_SETP30_Pos 30 /*!< GPIO_PORT SET6: SETP30 Position */\r
-#define GPIO_PORT_SET6_SETP30_Msk (0x01UL << GPIO_PORT_SET6_SETP30_Pos) /*!< GPIO_PORT SET6: SETP30 Mask */\r
-#define GPIO_PORT_SET6_SETP31_Pos 31 /*!< GPIO_PORT SET6: SETP31 Position */\r
-#define GPIO_PORT_SET6_SETP31_Msk (0x01UL << GPIO_PORT_SET6_SETP31_Pos) /*!< GPIO_PORT SET6: SETP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_SET7 -----------------------------------------\r
-#define GPIO_PORT_SET7_SETP0_Pos 0 /*!< GPIO_PORT SET7: SETP0 Position */\r
-#define GPIO_PORT_SET7_SETP0_Msk (0x01UL << GPIO_PORT_SET7_SETP0_Pos) /*!< GPIO_PORT SET7: SETP0 Mask */\r
-#define GPIO_PORT_SET7_SETP1_Pos 1 /*!< GPIO_PORT SET7: SETP1 Position */\r
-#define GPIO_PORT_SET7_SETP1_Msk (0x01UL << GPIO_PORT_SET7_SETP1_Pos) /*!< GPIO_PORT SET7: SETP1 Mask */\r
-#define GPIO_PORT_SET7_SETP2_Pos 2 /*!< GPIO_PORT SET7: SETP2 Position */\r
-#define GPIO_PORT_SET7_SETP2_Msk (0x01UL << GPIO_PORT_SET7_SETP2_Pos) /*!< GPIO_PORT SET7: SETP2 Mask */\r
-#define GPIO_PORT_SET7_SETP3_Pos 3 /*!< GPIO_PORT SET7: SETP3 Position */\r
-#define GPIO_PORT_SET7_SETP3_Msk (0x01UL << GPIO_PORT_SET7_SETP3_Pos) /*!< GPIO_PORT SET7: SETP3 Mask */\r
-#define GPIO_PORT_SET7_SETP4_Pos 4 /*!< GPIO_PORT SET7: SETP4 Position */\r
-#define GPIO_PORT_SET7_SETP4_Msk (0x01UL << GPIO_PORT_SET7_SETP4_Pos) /*!< GPIO_PORT SET7: SETP4 Mask */\r
-#define GPIO_PORT_SET7_SETP5_Pos 5 /*!< GPIO_PORT SET7: SETP5 Position */\r
-#define GPIO_PORT_SET7_SETP5_Msk (0x01UL << GPIO_PORT_SET7_SETP5_Pos) /*!< GPIO_PORT SET7: SETP5 Mask */\r
-#define GPIO_PORT_SET7_SETP6_Pos 6 /*!< GPIO_PORT SET7: SETP6 Position */\r
-#define GPIO_PORT_SET7_SETP6_Msk (0x01UL << GPIO_PORT_SET7_SETP6_Pos) /*!< GPIO_PORT SET7: SETP6 Mask */\r
-#define GPIO_PORT_SET7_SETP7_Pos 7 /*!< GPIO_PORT SET7: SETP7 Position */\r
-#define GPIO_PORT_SET7_SETP7_Msk (0x01UL << GPIO_PORT_SET7_SETP7_Pos) /*!< GPIO_PORT SET7: SETP7 Mask */\r
-#define GPIO_PORT_SET7_SETP8_Pos 8 /*!< GPIO_PORT SET7: SETP8 Position */\r
-#define GPIO_PORT_SET7_SETP8_Msk (0x01UL << GPIO_PORT_SET7_SETP8_Pos) /*!< GPIO_PORT SET7: SETP8 Mask */\r
-#define GPIO_PORT_SET7_SETP9_Pos 9 /*!< GPIO_PORT SET7: SETP9 Position */\r
-#define GPIO_PORT_SET7_SETP9_Msk (0x01UL << GPIO_PORT_SET7_SETP9_Pos) /*!< GPIO_PORT SET7: SETP9 Mask */\r
-#define GPIO_PORT_SET7_SETP10_Pos 10 /*!< GPIO_PORT SET7: SETP10 Position */\r
-#define GPIO_PORT_SET7_SETP10_Msk (0x01UL << GPIO_PORT_SET7_SETP10_Pos) /*!< GPIO_PORT SET7: SETP10 Mask */\r
-#define GPIO_PORT_SET7_SETP11_Pos 11 /*!< GPIO_PORT SET7: SETP11 Position */\r
-#define GPIO_PORT_SET7_SETP11_Msk (0x01UL << GPIO_PORT_SET7_SETP11_Pos) /*!< GPIO_PORT SET7: SETP11 Mask */\r
-#define GPIO_PORT_SET7_SETP12_Pos 12 /*!< GPIO_PORT SET7: SETP12 Position */\r
-#define GPIO_PORT_SET7_SETP12_Msk (0x01UL << GPIO_PORT_SET7_SETP12_Pos) /*!< GPIO_PORT SET7: SETP12 Mask */\r
-#define GPIO_PORT_SET7_SETP13_Pos 13 /*!< GPIO_PORT SET7: SETP13 Position */\r
-#define GPIO_PORT_SET7_SETP13_Msk (0x01UL << GPIO_PORT_SET7_SETP13_Pos) /*!< GPIO_PORT SET7: SETP13 Mask */\r
-#define GPIO_PORT_SET7_SETP14_Pos 14 /*!< GPIO_PORT SET7: SETP14 Position */\r
-#define GPIO_PORT_SET7_SETP14_Msk (0x01UL << GPIO_PORT_SET7_SETP14_Pos) /*!< GPIO_PORT SET7: SETP14 Mask */\r
-#define GPIO_PORT_SET7_SETP15_Pos 15 /*!< GPIO_PORT SET7: SETP15 Position */\r
-#define GPIO_PORT_SET7_SETP15_Msk (0x01UL << GPIO_PORT_SET7_SETP15_Pos) /*!< GPIO_PORT SET7: SETP15 Mask */\r
-#define GPIO_PORT_SET7_SETP16_Pos 16 /*!< GPIO_PORT SET7: SETP16 Position */\r
-#define GPIO_PORT_SET7_SETP16_Msk (0x01UL << GPIO_PORT_SET7_SETP16_Pos) /*!< GPIO_PORT SET7: SETP16 Mask */\r
-#define GPIO_PORT_SET7_SETP17_Pos 17 /*!< GPIO_PORT SET7: SETP17 Position */\r
-#define GPIO_PORT_SET7_SETP17_Msk (0x01UL << GPIO_PORT_SET7_SETP17_Pos) /*!< GPIO_PORT SET7: SETP17 Mask */\r
-#define GPIO_PORT_SET7_SETP18_Pos 18 /*!< GPIO_PORT SET7: SETP18 Position */\r
-#define GPIO_PORT_SET7_SETP18_Msk (0x01UL << GPIO_PORT_SET7_SETP18_Pos) /*!< GPIO_PORT SET7: SETP18 Mask */\r
-#define GPIO_PORT_SET7_SETP19_Pos 19 /*!< GPIO_PORT SET7: SETP19 Position */\r
-#define GPIO_PORT_SET7_SETP19_Msk (0x01UL << GPIO_PORT_SET7_SETP19_Pos) /*!< GPIO_PORT SET7: SETP19 Mask */\r
-#define GPIO_PORT_SET7_SETP20_Pos 20 /*!< GPIO_PORT SET7: SETP20 Position */\r
-#define GPIO_PORT_SET7_SETP20_Msk (0x01UL << GPIO_PORT_SET7_SETP20_Pos) /*!< GPIO_PORT SET7: SETP20 Mask */\r
-#define GPIO_PORT_SET7_SETP21_Pos 21 /*!< GPIO_PORT SET7: SETP21 Position */\r
-#define GPIO_PORT_SET7_SETP21_Msk (0x01UL << GPIO_PORT_SET7_SETP21_Pos) /*!< GPIO_PORT SET7: SETP21 Mask */\r
-#define GPIO_PORT_SET7_SETP22_Pos 22 /*!< GPIO_PORT SET7: SETP22 Position */\r
-#define GPIO_PORT_SET7_SETP22_Msk (0x01UL << GPIO_PORT_SET7_SETP22_Pos) /*!< GPIO_PORT SET7: SETP22 Mask */\r
-#define GPIO_PORT_SET7_SETP23_Pos 23 /*!< GPIO_PORT SET7: SETP23 Position */\r
-#define GPIO_PORT_SET7_SETP23_Msk (0x01UL << GPIO_PORT_SET7_SETP23_Pos) /*!< GPIO_PORT SET7: SETP23 Mask */\r
-#define GPIO_PORT_SET7_SETP24_Pos 24 /*!< GPIO_PORT SET7: SETP24 Position */\r
-#define GPIO_PORT_SET7_SETP24_Msk (0x01UL << GPIO_PORT_SET7_SETP24_Pos) /*!< GPIO_PORT SET7: SETP24 Mask */\r
-#define GPIO_PORT_SET7_SETP25_Pos 25 /*!< GPIO_PORT SET7: SETP25 Position */\r
-#define GPIO_PORT_SET7_SETP25_Msk (0x01UL << GPIO_PORT_SET7_SETP25_Pos) /*!< GPIO_PORT SET7: SETP25 Mask */\r
-#define GPIO_PORT_SET7_SETP26_Pos 26 /*!< GPIO_PORT SET7: SETP26 Position */\r
-#define GPIO_PORT_SET7_SETP26_Msk (0x01UL << GPIO_PORT_SET7_SETP26_Pos) /*!< GPIO_PORT SET7: SETP26 Mask */\r
-#define GPIO_PORT_SET7_SETP27_Pos 27 /*!< GPIO_PORT SET7: SETP27 Position */\r
-#define GPIO_PORT_SET7_SETP27_Msk (0x01UL << GPIO_PORT_SET7_SETP27_Pos) /*!< GPIO_PORT SET7: SETP27 Mask */\r
-#define GPIO_PORT_SET7_SETP28_Pos 28 /*!< GPIO_PORT SET7: SETP28 Position */\r
-#define GPIO_PORT_SET7_SETP28_Msk (0x01UL << GPIO_PORT_SET7_SETP28_Pos) /*!< GPIO_PORT SET7: SETP28 Mask */\r
-#define GPIO_PORT_SET7_SETP29_Pos 29 /*!< GPIO_PORT SET7: SETP29 Position */\r
-#define GPIO_PORT_SET7_SETP29_Msk (0x01UL << GPIO_PORT_SET7_SETP29_Pos) /*!< GPIO_PORT SET7: SETP29 Mask */\r
-#define GPIO_PORT_SET7_SETP30_Pos 30 /*!< GPIO_PORT SET7: SETP30 Position */\r
-#define GPIO_PORT_SET7_SETP30_Msk (0x01UL << GPIO_PORT_SET7_SETP30_Pos) /*!< GPIO_PORT SET7: SETP30 Mask */\r
-#define GPIO_PORT_SET7_SETP31_Pos 31 /*!< GPIO_PORT SET7: SETP31 Position */\r
-#define GPIO_PORT_SET7_SETP31_Msk (0x01UL << GPIO_PORT_SET7_SETP31_Pos) /*!< GPIO_PORT SET7: SETP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_CLR0 -----------------------------------------\r
-#define GPIO_PORT_CLR0_CLRP00_Pos 0 /*!< GPIO_PORT CLR0: CLRP00 Position */\r
-#define GPIO_PORT_CLR0_CLRP00_Msk (0x01UL << GPIO_PORT_CLR0_CLRP00_Pos) /*!< GPIO_PORT CLR0: CLRP00 Mask */\r
-#define GPIO_PORT_CLR0_CLRP01_Pos 1 /*!< GPIO_PORT CLR0: CLRP01 Position */\r
-#define GPIO_PORT_CLR0_CLRP01_Msk (0x01UL << GPIO_PORT_CLR0_CLRP01_Pos) /*!< GPIO_PORT CLR0: CLRP01 Mask */\r
-#define GPIO_PORT_CLR0_CLRP02_Pos 2 /*!< GPIO_PORT CLR0: CLRP02 Position */\r
-#define GPIO_PORT_CLR0_CLRP02_Msk (0x01UL << GPIO_PORT_CLR0_CLRP02_Pos) /*!< GPIO_PORT CLR0: CLRP02 Mask */\r
-#define GPIO_PORT_CLR0_CLRP03_Pos 3 /*!< GPIO_PORT CLR0: CLRP03 Position */\r
-#define GPIO_PORT_CLR0_CLRP03_Msk (0x01UL << GPIO_PORT_CLR0_CLRP03_Pos) /*!< GPIO_PORT CLR0: CLRP03 Mask */\r
-#define GPIO_PORT_CLR0_CLRP04_Pos 4 /*!< GPIO_PORT CLR0: CLRP04 Position */\r
-#define GPIO_PORT_CLR0_CLRP04_Msk (0x01UL << GPIO_PORT_CLR0_CLRP04_Pos) /*!< GPIO_PORT CLR0: CLRP04 Mask */\r
-#define GPIO_PORT_CLR0_CLRP05_Pos 5 /*!< GPIO_PORT CLR0: CLRP05 Position */\r
-#define GPIO_PORT_CLR0_CLRP05_Msk (0x01UL << GPIO_PORT_CLR0_CLRP05_Pos) /*!< GPIO_PORT CLR0: CLRP05 Mask */\r
-#define GPIO_PORT_CLR0_CLRP06_Pos 6 /*!< GPIO_PORT CLR0: CLRP06 Position */\r
-#define GPIO_PORT_CLR0_CLRP06_Msk (0x01UL << GPIO_PORT_CLR0_CLRP06_Pos) /*!< GPIO_PORT CLR0: CLRP06 Mask */\r
-#define GPIO_PORT_CLR0_CLRP07_Pos 7 /*!< GPIO_PORT CLR0: CLRP07 Position */\r
-#define GPIO_PORT_CLR0_CLRP07_Msk (0x01UL << GPIO_PORT_CLR0_CLRP07_Pos) /*!< GPIO_PORT CLR0: CLRP07 Mask */\r
-#define GPIO_PORT_CLR0_CLRP08_Pos 8 /*!< GPIO_PORT CLR0: CLRP08 Position */\r
-#define GPIO_PORT_CLR0_CLRP08_Msk (0x01UL << GPIO_PORT_CLR0_CLRP08_Pos) /*!< GPIO_PORT CLR0: CLRP08 Mask */\r
-#define GPIO_PORT_CLR0_CLRP09_Pos 9 /*!< GPIO_PORT CLR0: CLRP09 Position */\r
-#define GPIO_PORT_CLR0_CLRP09_Msk (0x01UL << GPIO_PORT_CLR0_CLRP09_Pos) /*!< GPIO_PORT CLR0: CLRP09 Mask */\r
-#define GPIO_PORT_CLR0_CLRP010_Pos 10 /*!< GPIO_PORT CLR0: CLRP010 Position */\r
-#define GPIO_PORT_CLR0_CLRP010_Msk (0x01UL << GPIO_PORT_CLR0_CLRP010_Pos) /*!< GPIO_PORT CLR0: CLRP010 Mask */\r
-#define GPIO_PORT_CLR0_CLRP011_Pos 11 /*!< GPIO_PORT CLR0: CLRP011 Position */\r
-#define GPIO_PORT_CLR0_CLRP011_Msk (0x01UL << GPIO_PORT_CLR0_CLRP011_Pos) /*!< GPIO_PORT CLR0: CLRP011 Mask */\r
-#define GPIO_PORT_CLR0_CLRP012_Pos 12 /*!< GPIO_PORT CLR0: CLRP012 Position */\r
-#define GPIO_PORT_CLR0_CLRP012_Msk (0x01UL << GPIO_PORT_CLR0_CLRP012_Pos) /*!< GPIO_PORT CLR0: CLRP012 Mask */\r
-#define GPIO_PORT_CLR0_CLRP013_Pos 13 /*!< GPIO_PORT CLR0: CLRP013 Position */\r
-#define GPIO_PORT_CLR0_CLRP013_Msk (0x01UL << GPIO_PORT_CLR0_CLRP013_Pos) /*!< GPIO_PORT CLR0: CLRP013 Mask */\r
-#define GPIO_PORT_CLR0_CLRP014_Pos 14 /*!< GPIO_PORT CLR0: CLRP014 Position */\r
-#define GPIO_PORT_CLR0_CLRP014_Msk (0x01UL << GPIO_PORT_CLR0_CLRP014_Pos) /*!< GPIO_PORT CLR0: CLRP014 Mask */\r
-#define GPIO_PORT_CLR0_CLRP015_Pos 15 /*!< GPIO_PORT CLR0: CLRP015 Position */\r
-#define GPIO_PORT_CLR0_CLRP015_Msk (0x01UL << GPIO_PORT_CLR0_CLRP015_Pos) /*!< GPIO_PORT CLR0: CLRP015 Mask */\r
-#define GPIO_PORT_CLR0_CLRP016_Pos 16 /*!< GPIO_PORT CLR0: CLRP016 Position */\r
-#define GPIO_PORT_CLR0_CLRP016_Msk (0x01UL << GPIO_PORT_CLR0_CLRP016_Pos) /*!< GPIO_PORT CLR0: CLRP016 Mask */\r
-#define GPIO_PORT_CLR0_CLRP017_Pos 17 /*!< GPIO_PORT CLR0: CLRP017 Position */\r
-#define GPIO_PORT_CLR0_CLRP017_Msk (0x01UL << GPIO_PORT_CLR0_CLRP017_Pos) /*!< GPIO_PORT CLR0: CLRP017 Mask */\r
-#define GPIO_PORT_CLR0_CLRP018_Pos 18 /*!< GPIO_PORT CLR0: CLRP018 Position */\r
-#define GPIO_PORT_CLR0_CLRP018_Msk (0x01UL << GPIO_PORT_CLR0_CLRP018_Pos) /*!< GPIO_PORT CLR0: CLRP018 Mask */\r
-#define GPIO_PORT_CLR0_CLRP019_Pos 19 /*!< GPIO_PORT CLR0: CLRP019 Position */\r
-#define GPIO_PORT_CLR0_CLRP019_Msk (0x01UL << GPIO_PORT_CLR0_CLRP019_Pos) /*!< GPIO_PORT CLR0: CLRP019 Mask */\r
-#define GPIO_PORT_CLR0_CLRP020_Pos 20 /*!< GPIO_PORT CLR0: CLRP020 Position */\r
-#define GPIO_PORT_CLR0_CLRP020_Msk (0x01UL << GPIO_PORT_CLR0_CLRP020_Pos) /*!< GPIO_PORT CLR0: CLRP020 Mask */\r
-#define GPIO_PORT_CLR0_CLRP021_Pos 21 /*!< GPIO_PORT CLR0: CLRP021 Position */\r
-#define GPIO_PORT_CLR0_CLRP021_Msk (0x01UL << GPIO_PORT_CLR0_CLRP021_Pos) /*!< GPIO_PORT CLR0: CLRP021 Mask */\r
-#define GPIO_PORT_CLR0_CLRP022_Pos 22 /*!< GPIO_PORT CLR0: CLRP022 Position */\r
-#define GPIO_PORT_CLR0_CLRP022_Msk (0x01UL << GPIO_PORT_CLR0_CLRP022_Pos) /*!< GPIO_PORT CLR0: CLRP022 Mask */\r
-#define GPIO_PORT_CLR0_CLRP023_Pos 23 /*!< GPIO_PORT CLR0: CLRP023 Position */\r
-#define GPIO_PORT_CLR0_CLRP023_Msk (0x01UL << GPIO_PORT_CLR0_CLRP023_Pos) /*!< GPIO_PORT CLR0: CLRP023 Mask */\r
-#define GPIO_PORT_CLR0_CLRP024_Pos 24 /*!< GPIO_PORT CLR0: CLRP024 Position */\r
-#define GPIO_PORT_CLR0_CLRP024_Msk (0x01UL << GPIO_PORT_CLR0_CLRP024_Pos) /*!< GPIO_PORT CLR0: CLRP024 Mask */\r
-#define GPIO_PORT_CLR0_CLRP025_Pos 25 /*!< GPIO_PORT CLR0: CLRP025 Position */\r
-#define GPIO_PORT_CLR0_CLRP025_Msk (0x01UL << GPIO_PORT_CLR0_CLRP025_Pos) /*!< GPIO_PORT CLR0: CLRP025 Mask */\r
-#define GPIO_PORT_CLR0_CLRP026_Pos 26 /*!< GPIO_PORT CLR0: CLRP026 Position */\r
-#define GPIO_PORT_CLR0_CLRP026_Msk (0x01UL << GPIO_PORT_CLR0_CLRP026_Pos) /*!< GPIO_PORT CLR0: CLRP026 Mask */\r
-#define GPIO_PORT_CLR0_CLRP027_Pos 27 /*!< GPIO_PORT CLR0: CLRP027 Position */\r
-#define GPIO_PORT_CLR0_CLRP027_Msk (0x01UL << GPIO_PORT_CLR0_CLRP027_Pos) /*!< GPIO_PORT CLR0: CLRP027 Mask */\r
-#define GPIO_PORT_CLR0_CLRP028_Pos 28 /*!< GPIO_PORT CLR0: CLRP028 Position */\r
-#define GPIO_PORT_CLR0_CLRP028_Msk (0x01UL << GPIO_PORT_CLR0_CLRP028_Pos) /*!< GPIO_PORT CLR0: CLRP028 Mask */\r
-#define GPIO_PORT_CLR0_CLRP029_Pos 29 /*!< GPIO_PORT CLR0: CLRP029 Position */\r
-#define GPIO_PORT_CLR0_CLRP029_Msk (0x01UL << GPIO_PORT_CLR0_CLRP029_Pos) /*!< GPIO_PORT CLR0: CLRP029 Mask */\r
-#define GPIO_PORT_CLR0_CLRP030_Pos 30 /*!< GPIO_PORT CLR0: CLRP030 Position */\r
-#define GPIO_PORT_CLR0_CLRP030_Msk (0x01UL << GPIO_PORT_CLR0_CLRP030_Pos) /*!< GPIO_PORT CLR0: CLRP030 Mask */\r
-#define GPIO_PORT_CLR0_CLRP031_Pos 31 /*!< GPIO_PORT CLR0: CLRP031 Position */\r
-#define GPIO_PORT_CLR0_CLRP031_Msk (0x01UL << GPIO_PORT_CLR0_CLRP031_Pos) /*!< GPIO_PORT CLR0: CLRP031 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_CLR1 -----------------------------------------\r
-#define GPIO_PORT_CLR1_CLRP00_Pos 0 /*!< GPIO_PORT CLR1: CLRP00 Position */\r
-#define GPIO_PORT_CLR1_CLRP00_Msk (0x01UL << GPIO_PORT_CLR1_CLRP00_Pos) /*!< GPIO_PORT CLR1: CLRP00 Mask */\r
-#define GPIO_PORT_CLR1_CLRP01_Pos 1 /*!< GPIO_PORT CLR1: CLRP01 Position */\r
-#define GPIO_PORT_CLR1_CLRP01_Msk (0x01UL << GPIO_PORT_CLR1_CLRP01_Pos) /*!< GPIO_PORT CLR1: CLRP01 Mask */\r
-#define GPIO_PORT_CLR1_CLRP02_Pos 2 /*!< GPIO_PORT CLR1: CLRP02 Position */\r
-#define GPIO_PORT_CLR1_CLRP02_Msk (0x01UL << GPIO_PORT_CLR1_CLRP02_Pos) /*!< GPIO_PORT CLR1: CLRP02 Mask */\r
-#define GPIO_PORT_CLR1_CLRP03_Pos 3 /*!< GPIO_PORT CLR1: CLRP03 Position */\r
-#define GPIO_PORT_CLR1_CLRP03_Msk (0x01UL << GPIO_PORT_CLR1_CLRP03_Pos) /*!< GPIO_PORT CLR1: CLRP03 Mask */\r
-#define GPIO_PORT_CLR1_CLRP04_Pos 4 /*!< GPIO_PORT CLR1: CLRP04 Position */\r
-#define GPIO_PORT_CLR1_CLRP04_Msk (0x01UL << GPIO_PORT_CLR1_CLRP04_Pos) /*!< GPIO_PORT CLR1: CLRP04 Mask */\r
-#define GPIO_PORT_CLR1_CLRP05_Pos 5 /*!< GPIO_PORT CLR1: CLRP05 Position */\r
-#define GPIO_PORT_CLR1_CLRP05_Msk (0x01UL << GPIO_PORT_CLR1_CLRP05_Pos) /*!< GPIO_PORT CLR1: CLRP05 Mask */\r
-#define GPIO_PORT_CLR1_CLRP06_Pos 6 /*!< GPIO_PORT CLR1: CLRP06 Position */\r
-#define GPIO_PORT_CLR1_CLRP06_Msk (0x01UL << GPIO_PORT_CLR1_CLRP06_Pos) /*!< GPIO_PORT CLR1: CLRP06 Mask */\r
-#define GPIO_PORT_CLR1_CLRP07_Pos 7 /*!< GPIO_PORT CLR1: CLRP07 Position */\r
-#define GPIO_PORT_CLR1_CLRP07_Msk (0x01UL << GPIO_PORT_CLR1_CLRP07_Pos) /*!< GPIO_PORT CLR1: CLRP07 Mask */\r
-#define GPIO_PORT_CLR1_CLRP08_Pos 8 /*!< GPIO_PORT CLR1: CLRP08 Position */\r
-#define GPIO_PORT_CLR1_CLRP08_Msk (0x01UL << GPIO_PORT_CLR1_CLRP08_Pos) /*!< GPIO_PORT CLR1: CLRP08 Mask */\r
-#define GPIO_PORT_CLR1_CLRP09_Pos 9 /*!< GPIO_PORT CLR1: CLRP09 Position */\r
-#define GPIO_PORT_CLR1_CLRP09_Msk (0x01UL << GPIO_PORT_CLR1_CLRP09_Pos) /*!< GPIO_PORT CLR1: CLRP09 Mask */\r
-#define GPIO_PORT_CLR1_CLRP010_Pos 10 /*!< GPIO_PORT CLR1: CLRP010 Position */\r
-#define GPIO_PORT_CLR1_CLRP010_Msk (0x01UL << GPIO_PORT_CLR1_CLRP010_Pos) /*!< GPIO_PORT CLR1: CLRP010 Mask */\r
-#define GPIO_PORT_CLR1_CLRP011_Pos 11 /*!< GPIO_PORT CLR1: CLRP011 Position */\r
-#define GPIO_PORT_CLR1_CLRP011_Msk (0x01UL << GPIO_PORT_CLR1_CLRP011_Pos) /*!< GPIO_PORT CLR1: CLRP011 Mask */\r
-#define GPIO_PORT_CLR1_CLRP012_Pos 12 /*!< GPIO_PORT CLR1: CLRP012 Position */\r
-#define GPIO_PORT_CLR1_CLRP012_Msk (0x01UL << GPIO_PORT_CLR1_CLRP012_Pos) /*!< GPIO_PORT CLR1: CLRP012 Mask */\r
-#define GPIO_PORT_CLR1_CLRP013_Pos 13 /*!< GPIO_PORT CLR1: CLRP013 Position */\r
-#define GPIO_PORT_CLR1_CLRP013_Msk (0x01UL << GPIO_PORT_CLR1_CLRP013_Pos) /*!< GPIO_PORT CLR1: CLRP013 Mask */\r
-#define GPIO_PORT_CLR1_CLRP014_Pos 14 /*!< GPIO_PORT CLR1: CLRP014 Position */\r
-#define GPIO_PORT_CLR1_CLRP014_Msk (0x01UL << GPIO_PORT_CLR1_CLRP014_Pos) /*!< GPIO_PORT CLR1: CLRP014 Mask */\r
-#define GPIO_PORT_CLR1_CLRP015_Pos 15 /*!< GPIO_PORT CLR1: CLRP015 Position */\r
-#define GPIO_PORT_CLR1_CLRP015_Msk (0x01UL << GPIO_PORT_CLR1_CLRP015_Pos) /*!< GPIO_PORT CLR1: CLRP015 Mask */\r
-#define GPIO_PORT_CLR1_CLRP016_Pos 16 /*!< GPIO_PORT CLR1: CLRP016 Position */\r
-#define GPIO_PORT_CLR1_CLRP016_Msk (0x01UL << GPIO_PORT_CLR1_CLRP016_Pos) /*!< GPIO_PORT CLR1: CLRP016 Mask */\r
-#define GPIO_PORT_CLR1_CLRP017_Pos 17 /*!< GPIO_PORT CLR1: CLRP017 Position */\r
-#define GPIO_PORT_CLR1_CLRP017_Msk (0x01UL << GPIO_PORT_CLR1_CLRP017_Pos) /*!< GPIO_PORT CLR1: CLRP017 Mask */\r
-#define GPIO_PORT_CLR1_CLRP018_Pos 18 /*!< GPIO_PORT CLR1: CLRP018 Position */\r
-#define GPIO_PORT_CLR1_CLRP018_Msk (0x01UL << GPIO_PORT_CLR1_CLRP018_Pos) /*!< GPIO_PORT CLR1: CLRP018 Mask */\r
-#define GPIO_PORT_CLR1_CLRP019_Pos 19 /*!< GPIO_PORT CLR1: CLRP019 Position */\r
-#define GPIO_PORT_CLR1_CLRP019_Msk (0x01UL << GPIO_PORT_CLR1_CLRP019_Pos) /*!< GPIO_PORT CLR1: CLRP019 Mask */\r
-#define GPIO_PORT_CLR1_CLRP020_Pos 20 /*!< GPIO_PORT CLR1: CLRP020 Position */\r
-#define GPIO_PORT_CLR1_CLRP020_Msk (0x01UL << GPIO_PORT_CLR1_CLRP020_Pos) /*!< GPIO_PORT CLR1: CLRP020 Mask */\r
-#define GPIO_PORT_CLR1_CLRP021_Pos 21 /*!< GPIO_PORT CLR1: CLRP021 Position */\r
-#define GPIO_PORT_CLR1_CLRP021_Msk (0x01UL << GPIO_PORT_CLR1_CLRP021_Pos) /*!< GPIO_PORT CLR1: CLRP021 Mask */\r
-#define GPIO_PORT_CLR1_CLRP022_Pos 22 /*!< GPIO_PORT CLR1: CLRP022 Position */\r
-#define GPIO_PORT_CLR1_CLRP022_Msk (0x01UL << GPIO_PORT_CLR1_CLRP022_Pos) /*!< GPIO_PORT CLR1: CLRP022 Mask */\r
-#define GPIO_PORT_CLR1_CLRP023_Pos 23 /*!< GPIO_PORT CLR1: CLRP023 Position */\r
-#define GPIO_PORT_CLR1_CLRP023_Msk (0x01UL << GPIO_PORT_CLR1_CLRP023_Pos) /*!< GPIO_PORT CLR1: CLRP023 Mask */\r
-#define GPIO_PORT_CLR1_CLRP024_Pos 24 /*!< GPIO_PORT CLR1: CLRP024 Position */\r
-#define GPIO_PORT_CLR1_CLRP024_Msk (0x01UL << GPIO_PORT_CLR1_CLRP024_Pos) /*!< GPIO_PORT CLR1: CLRP024 Mask */\r
-#define GPIO_PORT_CLR1_CLRP025_Pos 25 /*!< GPIO_PORT CLR1: CLRP025 Position */\r
-#define GPIO_PORT_CLR1_CLRP025_Msk (0x01UL << GPIO_PORT_CLR1_CLRP025_Pos) /*!< GPIO_PORT CLR1: CLRP025 Mask */\r
-#define GPIO_PORT_CLR1_CLRP026_Pos 26 /*!< GPIO_PORT CLR1: CLRP026 Position */\r
-#define GPIO_PORT_CLR1_CLRP026_Msk (0x01UL << GPIO_PORT_CLR1_CLRP026_Pos) /*!< GPIO_PORT CLR1: CLRP026 Mask */\r
-#define GPIO_PORT_CLR1_CLRP027_Pos 27 /*!< GPIO_PORT CLR1: CLRP027 Position */\r
-#define GPIO_PORT_CLR1_CLRP027_Msk (0x01UL << GPIO_PORT_CLR1_CLRP027_Pos) /*!< GPIO_PORT CLR1: CLRP027 Mask */\r
-#define GPIO_PORT_CLR1_CLRP028_Pos 28 /*!< GPIO_PORT CLR1: CLRP028 Position */\r
-#define GPIO_PORT_CLR1_CLRP028_Msk (0x01UL << GPIO_PORT_CLR1_CLRP028_Pos) /*!< GPIO_PORT CLR1: CLRP028 Mask */\r
-#define GPIO_PORT_CLR1_CLRP029_Pos 29 /*!< GPIO_PORT CLR1: CLRP029 Position */\r
-#define GPIO_PORT_CLR1_CLRP029_Msk (0x01UL << GPIO_PORT_CLR1_CLRP029_Pos) /*!< GPIO_PORT CLR1: CLRP029 Mask */\r
-#define GPIO_PORT_CLR1_CLRP030_Pos 30 /*!< GPIO_PORT CLR1: CLRP030 Position */\r
-#define GPIO_PORT_CLR1_CLRP030_Msk (0x01UL << GPIO_PORT_CLR1_CLRP030_Pos) /*!< GPIO_PORT CLR1: CLRP030 Mask */\r
-#define GPIO_PORT_CLR1_CLRP031_Pos 31 /*!< GPIO_PORT CLR1: CLRP031 Position */\r
-#define GPIO_PORT_CLR1_CLRP031_Msk (0x01UL << GPIO_PORT_CLR1_CLRP031_Pos) /*!< GPIO_PORT CLR1: CLRP031 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_CLR2 -----------------------------------------\r
-#define GPIO_PORT_CLR2_CLRP00_Pos 0 /*!< GPIO_PORT CLR2: CLRP00 Position */\r
-#define GPIO_PORT_CLR2_CLRP00_Msk (0x01UL << GPIO_PORT_CLR2_CLRP00_Pos) /*!< GPIO_PORT CLR2: CLRP00 Mask */\r
-#define GPIO_PORT_CLR2_CLRP01_Pos 1 /*!< GPIO_PORT CLR2: CLRP01 Position */\r
-#define GPIO_PORT_CLR2_CLRP01_Msk (0x01UL << GPIO_PORT_CLR2_CLRP01_Pos) /*!< GPIO_PORT CLR2: CLRP01 Mask */\r
-#define GPIO_PORT_CLR2_CLRP02_Pos 2 /*!< GPIO_PORT CLR2: CLRP02 Position */\r
-#define GPIO_PORT_CLR2_CLRP02_Msk (0x01UL << GPIO_PORT_CLR2_CLRP02_Pos) /*!< GPIO_PORT CLR2: CLRP02 Mask */\r
-#define GPIO_PORT_CLR2_CLRP03_Pos 3 /*!< GPIO_PORT CLR2: CLRP03 Position */\r
-#define GPIO_PORT_CLR2_CLRP03_Msk (0x01UL << GPIO_PORT_CLR2_CLRP03_Pos) /*!< GPIO_PORT CLR2: CLRP03 Mask */\r
-#define GPIO_PORT_CLR2_CLRP04_Pos 4 /*!< GPIO_PORT CLR2: CLRP04 Position */\r
-#define GPIO_PORT_CLR2_CLRP04_Msk (0x01UL << GPIO_PORT_CLR2_CLRP04_Pos) /*!< GPIO_PORT CLR2: CLRP04 Mask */\r
-#define GPIO_PORT_CLR2_CLRP05_Pos 5 /*!< GPIO_PORT CLR2: CLRP05 Position */\r
-#define GPIO_PORT_CLR2_CLRP05_Msk (0x01UL << GPIO_PORT_CLR2_CLRP05_Pos) /*!< GPIO_PORT CLR2: CLRP05 Mask */\r
-#define GPIO_PORT_CLR2_CLRP06_Pos 6 /*!< GPIO_PORT CLR2: CLRP06 Position */\r
-#define GPIO_PORT_CLR2_CLRP06_Msk (0x01UL << GPIO_PORT_CLR2_CLRP06_Pos) /*!< GPIO_PORT CLR2: CLRP06 Mask */\r
-#define GPIO_PORT_CLR2_CLRP07_Pos 7 /*!< GPIO_PORT CLR2: CLRP07 Position */\r
-#define GPIO_PORT_CLR2_CLRP07_Msk (0x01UL << GPIO_PORT_CLR2_CLRP07_Pos) /*!< GPIO_PORT CLR2: CLRP07 Mask */\r
-#define GPIO_PORT_CLR2_CLRP08_Pos 8 /*!< GPIO_PORT CLR2: CLRP08 Position */\r
-#define GPIO_PORT_CLR2_CLRP08_Msk (0x01UL << GPIO_PORT_CLR2_CLRP08_Pos) /*!< GPIO_PORT CLR2: CLRP08 Mask */\r
-#define GPIO_PORT_CLR2_CLRP09_Pos 9 /*!< GPIO_PORT CLR2: CLRP09 Position */\r
-#define GPIO_PORT_CLR2_CLRP09_Msk (0x01UL << GPIO_PORT_CLR2_CLRP09_Pos) /*!< GPIO_PORT CLR2: CLRP09 Mask */\r
-#define GPIO_PORT_CLR2_CLRP010_Pos 10 /*!< GPIO_PORT CLR2: CLRP010 Position */\r
-#define GPIO_PORT_CLR2_CLRP010_Msk (0x01UL << GPIO_PORT_CLR2_CLRP010_Pos) /*!< GPIO_PORT CLR2: CLRP010 Mask */\r
-#define GPIO_PORT_CLR2_CLRP011_Pos 11 /*!< GPIO_PORT CLR2: CLRP011 Position */\r
-#define GPIO_PORT_CLR2_CLRP011_Msk (0x01UL << GPIO_PORT_CLR2_CLRP011_Pos) /*!< GPIO_PORT CLR2: CLRP011 Mask */\r
-#define GPIO_PORT_CLR2_CLRP012_Pos 12 /*!< GPIO_PORT CLR2: CLRP012 Position */\r
-#define GPIO_PORT_CLR2_CLRP012_Msk (0x01UL << GPIO_PORT_CLR2_CLRP012_Pos) /*!< GPIO_PORT CLR2: CLRP012 Mask */\r
-#define GPIO_PORT_CLR2_CLRP013_Pos 13 /*!< GPIO_PORT CLR2: CLRP013 Position */\r
-#define GPIO_PORT_CLR2_CLRP013_Msk (0x01UL << GPIO_PORT_CLR2_CLRP013_Pos) /*!< GPIO_PORT CLR2: CLRP013 Mask */\r
-#define GPIO_PORT_CLR2_CLRP014_Pos 14 /*!< GPIO_PORT CLR2: CLRP014 Position */\r
-#define GPIO_PORT_CLR2_CLRP014_Msk (0x01UL << GPIO_PORT_CLR2_CLRP014_Pos) /*!< GPIO_PORT CLR2: CLRP014 Mask */\r
-#define GPIO_PORT_CLR2_CLRP015_Pos 15 /*!< GPIO_PORT CLR2: CLRP015 Position */\r
-#define GPIO_PORT_CLR2_CLRP015_Msk (0x01UL << GPIO_PORT_CLR2_CLRP015_Pos) /*!< GPIO_PORT CLR2: CLRP015 Mask */\r
-#define GPIO_PORT_CLR2_CLRP016_Pos 16 /*!< GPIO_PORT CLR2: CLRP016 Position */\r
-#define GPIO_PORT_CLR2_CLRP016_Msk (0x01UL << GPIO_PORT_CLR2_CLRP016_Pos) /*!< GPIO_PORT CLR2: CLRP016 Mask */\r
-#define GPIO_PORT_CLR2_CLRP017_Pos 17 /*!< GPIO_PORT CLR2: CLRP017 Position */\r
-#define GPIO_PORT_CLR2_CLRP017_Msk (0x01UL << GPIO_PORT_CLR2_CLRP017_Pos) /*!< GPIO_PORT CLR2: CLRP017 Mask */\r
-#define GPIO_PORT_CLR2_CLRP018_Pos 18 /*!< GPIO_PORT CLR2: CLRP018 Position */\r
-#define GPIO_PORT_CLR2_CLRP018_Msk (0x01UL << GPIO_PORT_CLR2_CLRP018_Pos) /*!< GPIO_PORT CLR2: CLRP018 Mask */\r
-#define GPIO_PORT_CLR2_CLRP019_Pos 19 /*!< GPIO_PORT CLR2: CLRP019 Position */\r
-#define GPIO_PORT_CLR2_CLRP019_Msk (0x01UL << GPIO_PORT_CLR2_CLRP019_Pos) /*!< GPIO_PORT CLR2: CLRP019 Mask */\r
-#define GPIO_PORT_CLR2_CLRP020_Pos 20 /*!< GPIO_PORT CLR2: CLRP020 Position */\r
-#define GPIO_PORT_CLR2_CLRP020_Msk (0x01UL << GPIO_PORT_CLR2_CLRP020_Pos) /*!< GPIO_PORT CLR2: CLRP020 Mask */\r
-#define GPIO_PORT_CLR2_CLRP021_Pos 21 /*!< GPIO_PORT CLR2: CLRP021 Position */\r
-#define GPIO_PORT_CLR2_CLRP021_Msk (0x01UL << GPIO_PORT_CLR2_CLRP021_Pos) /*!< GPIO_PORT CLR2: CLRP021 Mask */\r
-#define GPIO_PORT_CLR2_CLRP022_Pos 22 /*!< GPIO_PORT CLR2: CLRP022 Position */\r
-#define GPIO_PORT_CLR2_CLRP022_Msk (0x01UL << GPIO_PORT_CLR2_CLRP022_Pos) /*!< GPIO_PORT CLR2: CLRP022 Mask */\r
-#define GPIO_PORT_CLR2_CLRP023_Pos 23 /*!< GPIO_PORT CLR2: CLRP023 Position */\r
-#define GPIO_PORT_CLR2_CLRP023_Msk (0x01UL << GPIO_PORT_CLR2_CLRP023_Pos) /*!< GPIO_PORT CLR2: CLRP023 Mask */\r
-#define GPIO_PORT_CLR2_CLRP024_Pos 24 /*!< GPIO_PORT CLR2: CLRP024 Position */\r
-#define GPIO_PORT_CLR2_CLRP024_Msk (0x01UL << GPIO_PORT_CLR2_CLRP024_Pos) /*!< GPIO_PORT CLR2: CLRP024 Mask */\r
-#define GPIO_PORT_CLR2_CLRP025_Pos 25 /*!< GPIO_PORT CLR2: CLRP025 Position */\r
-#define GPIO_PORT_CLR2_CLRP025_Msk (0x01UL << GPIO_PORT_CLR2_CLRP025_Pos) /*!< GPIO_PORT CLR2: CLRP025 Mask */\r
-#define GPIO_PORT_CLR2_CLRP026_Pos 26 /*!< GPIO_PORT CLR2: CLRP026 Position */\r
-#define GPIO_PORT_CLR2_CLRP026_Msk (0x01UL << GPIO_PORT_CLR2_CLRP026_Pos) /*!< GPIO_PORT CLR2: CLRP026 Mask */\r
-#define GPIO_PORT_CLR2_CLRP027_Pos 27 /*!< GPIO_PORT CLR2: CLRP027 Position */\r
-#define GPIO_PORT_CLR2_CLRP027_Msk (0x01UL << GPIO_PORT_CLR2_CLRP027_Pos) /*!< GPIO_PORT CLR2: CLRP027 Mask */\r
-#define GPIO_PORT_CLR2_CLRP028_Pos 28 /*!< GPIO_PORT CLR2: CLRP028 Position */\r
-#define GPIO_PORT_CLR2_CLRP028_Msk (0x01UL << GPIO_PORT_CLR2_CLRP028_Pos) /*!< GPIO_PORT CLR2: CLRP028 Mask */\r
-#define GPIO_PORT_CLR2_CLRP029_Pos 29 /*!< GPIO_PORT CLR2: CLRP029 Position */\r
-#define GPIO_PORT_CLR2_CLRP029_Msk (0x01UL << GPIO_PORT_CLR2_CLRP029_Pos) /*!< GPIO_PORT CLR2: CLRP029 Mask */\r
-#define GPIO_PORT_CLR2_CLRP030_Pos 30 /*!< GPIO_PORT CLR2: CLRP030 Position */\r
-#define GPIO_PORT_CLR2_CLRP030_Msk (0x01UL << GPIO_PORT_CLR2_CLRP030_Pos) /*!< GPIO_PORT CLR2: CLRP030 Mask */\r
-#define GPIO_PORT_CLR2_CLRP031_Pos 31 /*!< GPIO_PORT CLR2: CLRP031 Position */\r
-#define GPIO_PORT_CLR2_CLRP031_Msk (0x01UL << GPIO_PORT_CLR2_CLRP031_Pos) /*!< GPIO_PORT CLR2: CLRP031 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_CLR3 -----------------------------------------\r
-#define GPIO_PORT_CLR3_CLRP00_Pos 0 /*!< GPIO_PORT CLR3: CLRP00 Position */\r
-#define GPIO_PORT_CLR3_CLRP00_Msk (0x01UL << GPIO_PORT_CLR3_CLRP00_Pos) /*!< GPIO_PORT CLR3: CLRP00 Mask */\r
-#define GPIO_PORT_CLR3_CLRP01_Pos 1 /*!< GPIO_PORT CLR3: CLRP01 Position */\r
-#define GPIO_PORT_CLR3_CLRP01_Msk (0x01UL << GPIO_PORT_CLR3_CLRP01_Pos) /*!< GPIO_PORT CLR3: CLRP01 Mask */\r
-#define GPIO_PORT_CLR3_CLRP02_Pos 2 /*!< GPIO_PORT CLR3: CLRP02 Position */\r
-#define GPIO_PORT_CLR3_CLRP02_Msk (0x01UL << GPIO_PORT_CLR3_CLRP02_Pos) /*!< GPIO_PORT CLR3: CLRP02 Mask */\r
-#define GPIO_PORT_CLR3_CLRP03_Pos 3 /*!< GPIO_PORT CLR3: CLRP03 Position */\r
-#define GPIO_PORT_CLR3_CLRP03_Msk (0x01UL << GPIO_PORT_CLR3_CLRP03_Pos) /*!< GPIO_PORT CLR3: CLRP03 Mask */\r
-#define GPIO_PORT_CLR3_CLRP04_Pos 4 /*!< GPIO_PORT CLR3: CLRP04 Position */\r
-#define GPIO_PORT_CLR3_CLRP04_Msk (0x01UL << GPIO_PORT_CLR3_CLRP04_Pos) /*!< GPIO_PORT CLR3: CLRP04 Mask */\r
-#define GPIO_PORT_CLR3_CLRP05_Pos 5 /*!< GPIO_PORT CLR3: CLRP05 Position */\r
-#define GPIO_PORT_CLR3_CLRP05_Msk (0x01UL << GPIO_PORT_CLR3_CLRP05_Pos) /*!< GPIO_PORT CLR3: CLRP05 Mask */\r
-#define GPIO_PORT_CLR3_CLRP06_Pos 6 /*!< GPIO_PORT CLR3: CLRP06 Position */\r
-#define GPIO_PORT_CLR3_CLRP06_Msk (0x01UL << GPIO_PORT_CLR3_CLRP06_Pos) /*!< GPIO_PORT CLR3: CLRP06 Mask */\r
-#define GPIO_PORT_CLR3_CLRP07_Pos 7 /*!< GPIO_PORT CLR3: CLRP07 Position */\r
-#define GPIO_PORT_CLR3_CLRP07_Msk (0x01UL << GPIO_PORT_CLR3_CLRP07_Pos) /*!< GPIO_PORT CLR3: CLRP07 Mask */\r
-#define GPIO_PORT_CLR3_CLRP08_Pos 8 /*!< GPIO_PORT CLR3: CLRP08 Position */\r
-#define GPIO_PORT_CLR3_CLRP08_Msk (0x01UL << GPIO_PORT_CLR3_CLRP08_Pos) /*!< GPIO_PORT CLR3: CLRP08 Mask */\r
-#define GPIO_PORT_CLR3_CLRP09_Pos 9 /*!< GPIO_PORT CLR3: CLRP09 Position */\r
-#define GPIO_PORT_CLR3_CLRP09_Msk (0x01UL << GPIO_PORT_CLR3_CLRP09_Pos) /*!< GPIO_PORT CLR3: CLRP09 Mask */\r
-#define GPIO_PORT_CLR3_CLRP010_Pos 10 /*!< GPIO_PORT CLR3: CLRP010 Position */\r
-#define GPIO_PORT_CLR3_CLRP010_Msk (0x01UL << GPIO_PORT_CLR3_CLRP010_Pos) /*!< GPIO_PORT CLR3: CLRP010 Mask */\r
-#define GPIO_PORT_CLR3_CLRP011_Pos 11 /*!< GPIO_PORT CLR3: CLRP011 Position */\r
-#define GPIO_PORT_CLR3_CLRP011_Msk (0x01UL << GPIO_PORT_CLR3_CLRP011_Pos) /*!< GPIO_PORT CLR3: CLRP011 Mask */\r
-#define GPIO_PORT_CLR3_CLRP012_Pos 12 /*!< GPIO_PORT CLR3: CLRP012 Position */\r
-#define GPIO_PORT_CLR3_CLRP012_Msk (0x01UL << GPIO_PORT_CLR3_CLRP012_Pos) /*!< GPIO_PORT CLR3: CLRP012 Mask */\r
-#define GPIO_PORT_CLR3_CLRP013_Pos 13 /*!< GPIO_PORT CLR3: CLRP013 Position */\r
-#define GPIO_PORT_CLR3_CLRP013_Msk (0x01UL << GPIO_PORT_CLR3_CLRP013_Pos) /*!< GPIO_PORT CLR3: CLRP013 Mask */\r
-#define GPIO_PORT_CLR3_CLRP014_Pos 14 /*!< GPIO_PORT CLR3: CLRP014 Position */\r
-#define GPIO_PORT_CLR3_CLRP014_Msk (0x01UL << GPIO_PORT_CLR3_CLRP014_Pos) /*!< GPIO_PORT CLR3: CLRP014 Mask */\r
-#define GPIO_PORT_CLR3_CLRP015_Pos 15 /*!< GPIO_PORT CLR3: CLRP015 Position */\r
-#define GPIO_PORT_CLR3_CLRP015_Msk (0x01UL << GPIO_PORT_CLR3_CLRP015_Pos) /*!< GPIO_PORT CLR3: CLRP015 Mask */\r
-#define GPIO_PORT_CLR3_CLRP016_Pos 16 /*!< GPIO_PORT CLR3: CLRP016 Position */\r
-#define GPIO_PORT_CLR3_CLRP016_Msk (0x01UL << GPIO_PORT_CLR3_CLRP016_Pos) /*!< GPIO_PORT CLR3: CLRP016 Mask */\r
-#define GPIO_PORT_CLR3_CLRP017_Pos 17 /*!< GPIO_PORT CLR3: CLRP017 Position */\r
-#define GPIO_PORT_CLR3_CLRP017_Msk (0x01UL << GPIO_PORT_CLR3_CLRP017_Pos) /*!< GPIO_PORT CLR3: CLRP017 Mask */\r
-#define GPIO_PORT_CLR3_CLRP018_Pos 18 /*!< GPIO_PORT CLR3: CLRP018 Position */\r
-#define GPIO_PORT_CLR3_CLRP018_Msk (0x01UL << GPIO_PORT_CLR3_CLRP018_Pos) /*!< GPIO_PORT CLR3: CLRP018 Mask */\r
-#define GPIO_PORT_CLR3_CLRP019_Pos 19 /*!< GPIO_PORT CLR3: CLRP019 Position */\r
-#define GPIO_PORT_CLR3_CLRP019_Msk (0x01UL << GPIO_PORT_CLR3_CLRP019_Pos) /*!< GPIO_PORT CLR3: CLRP019 Mask */\r
-#define GPIO_PORT_CLR3_CLRP020_Pos 20 /*!< GPIO_PORT CLR3: CLRP020 Position */\r
-#define GPIO_PORT_CLR3_CLRP020_Msk (0x01UL << GPIO_PORT_CLR3_CLRP020_Pos) /*!< GPIO_PORT CLR3: CLRP020 Mask */\r
-#define GPIO_PORT_CLR3_CLRP021_Pos 21 /*!< GPIO_PORT CLR3: CLRP021 Position */\r
-#define GPIO_PORT_CLR3_CLRP021_Msk (0x01UL << GPIO_PORT_CLR3_CLRP021_Pos) /*!< GPIO_PORT CLR3: CLRP021 Mask */\r
-#define GPIO_PORT_CLR3_CLRP022_Pos 22 /*!< GPIO_PORT CLR3: CLRP022 Position */\r
-#define GPIO_PORT_CLR3_CLRP022_Msk (0x01UL << GPIO_PORT_CLR3_CLRP022_Pos) /*!< GPIO_PORT CLR3: CLRP022 Mask */\r
-#define GPIO_PORT_CLR3_CLRP023_Pos 23 /*!< GPIO_PORT CLR3: CLRP023 Position */\r
-#define GPIO_PORT_CLR3_CLRP023_Msk (0x01UL << GPIO_PORT_CLR3_CLRP023_Pos) /*!< GPIO_PORT CLR3: CLRP023 Mask */\r
-#define GPIO_PORT_CLR3_CLRP024_Pos 24 /*!< GPIO_PORT CLR3: CLRP024 Position */\r
-#define GPIO_PORT_CLR3_CLRP024_Msk (0x01UL << GPIO_PORT_CLR3_CLRP024_Pos) /*!< GPIO_PORT CLR3: CLRP024 Mask */\r
-#define GPIO_PORT_CLR3_CLRP025_Pos 25 /*!< GPIO_PORT CLR3: CLRP025 Position */\r
-#define GPIO_PORT_CLR3_CLRP025_Msk (0x01UL << GPIO_PORT_CLR3_CLRP025_Pos) /*!< GPIO_PORT CLR3: CLRP025 Mask */\r
-#define GPIO_PORT_CLR3_CLRP026_Pos 26 /*!< GPIO_PORT CLR3: CLRP026 Position */\r
-#define GPIO_PORT_CLR3_CLRP026_Msk (0x01UL << GPIO_PORT_CLR3_CLRP026_Pos) /*!< GPIO_PORT CLR3: CLRP026 Mask */\r
-#define GPIO_PORT_CLR3_CLRP027_Pos 27 /*!< GPIO_PORT CLR3: CLRP027 Position */\r
-#define GPIO_PORT_CLR3_CLRP027_Msk (0x01UL << GPIO_PORT_CLR3_CLRP027_Pos) /*!< GPIO_PORT CLR3: CLRP027 Mask */\r
-#define GPIO_PORT_CLR3_CLRP028_Pos 28 /*!< GPIO_PORT CLR3: CLRP028 Position */\r
-#define GPIO_PORT_CLR3_CLRP028_Msk (0x01UL << GPIO_PORT_CLR3_CLRP028_Pos) /*!< GPIO_PORT CLR3: CLRP028 Mask */\r
-#define GPIO_PORT_CLR3_CLRP029_Pos 29 /*!< GPIO_PORT CLR3: CLRP029 Position */\r
-#define GPIO_PORT_CLR3_CLRP029_Msk (0x01UL << GPIO_PORT_CLR3_CLRP029_Pos) /*!< GPIO_PORT CLR3: CLRP029 Mask */\r
-#define GPIO_PORT_CLR3_CLRP030_Pos 30 /*!< GPIO_PORT CLR3: CLRP030 Position */\r
-#define GPIO_PORT_CLR3_CLRP030_Msk (0x01UL << GPIO_PORT_CLR3_CLRP030_Pos) /*!< GPIO_PORT CLR3: CLRP030 Mask */\r
-#define GPIO_PORT_CLR3_CLRP031_Pos 31 /*!< GPIO_PORT CLR3: CLRP031 Position */\r
-#define GPIO_PORT_CLR3_CLRP031_Msk (0x01UL << GPIO_PORT_CLR3_CLRP031_Pos) /*!< GPIO_PORT CLR3: CLRP031 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_CLR4 -----------------------------------------\r
-#define GPIO_PORT_CLR4_CLRP00_Pos 0 /*!< GPIO_PORT CLR4: CLRP00 Position */\r
-#define GPIO_PORT_CLR4_CLRP00_Msk (0x01UL << GPIO_PORT_CLR4_CLRP00_Pos) /*!< GPIO_PORT CLR4: CLRP00 Mask */\r
-#define GPIO_PORT_CLR4_CLRP01_Pos 1 /*!< GPIO_PORT CLR4: CLRP01 Position */\r
-#define GPIO_PORT_CLR4_CLRP01_Msk (0x01UL << GPIO_PORT_CLR4_CLRP01_Pos) /*!< GPIO_PORT CLR4: CLRP01 Mask */\r
-#define GPIO_PORT_CLR4_CLRP02_Pos 2 /*!< GPIO_PORT CLR4: CLRP02 Position */\r
-#define GPIO_PORT_CLR4_CLRP02_Msk (0x01UL << GPIO_PORT_CLR4_CLRP02_Pos) /*!< GPIO_PORT CLR4: CLRP02 Mask */\r
-#define GPIO_PORT_CLR4_CLRP03_Pos 3 /*!< GPIO_PORT CLR4: CLRP03 Position */\r
-#define GPIO_PORT_CLR4_CLRP03_Msk (0x01UL << GPIO_PORT_CLR4_CLRP03_Pos) /*!< GPIO_PORT CLR4: CLRP03 Mask */\r
-#define GPIO_PORT_CLR4_CLRP04_Pos 4 /*!< GPIO_PORT CLR4: CLRP04 Position */\r
-#define GPIO_PORT_CLR4_CLRP04_Msk (0x01UL << GPIO_PORT_CLR4_CLRP04_Pos) /*!< GPIO_PORT CLR4: CLRP04 Mask */\r
-#define GPIO_PORT_CLR4_CLRP05_Pos 5 /*!< GPIO_PORT CLR4: CLRP05 Position */\r
-#define GPIO_PORT_CLR4_CLRP05_Msk (0x01UL << GPIO_PORT_CLR4_CLRP05_Pos) /*!< GPIO_PORT CLR4: CLRP05 Mask */\r
-#define GPIO_PORT_CLR4_CLRP06_Pos 6 /*!< GPIO_PORT CLR4: CLRP06 Position */\r
-#define GPIO_PORT_CLR4_CLRP06_Msk (0x01UL << GPIO_PORT_CLR4_CLRP06_Pos) /*!< GPIO_PORT CLR4: CLRP06 Mask */\r
-#define GPIO_PORT_CLR4_CLRP07_Pos 7 /*!< GPIO_PORT CLR4: CLRP07 Position */\r
-#define GPIO_PORT_CLR4_CLRP07_Msk (0x01UL << GPIO_PORT_CLR4_CLRP07_Pos) /*!< GPIO_PORT CLR4: CLRP07 Mask */\r
-#define GPIO_PORT_CLR4_CLRP08_Pos 8 /*!< GPIO_PORT CLR4: CLRP08 Position */\r
-#define GPIO_PORT_CLR4_CLRP08_Msk (0x01UL << GPIO_PORT_CLR4_CLRP08_Pos) /*!< GPIO_PORT CLR4: CLRP08 Mask */\r
-#define GPIO_PORT_CLR4_CLRP09_Pos 9 /*!< GPIO_PORT CLR4: CLRP09 Position */\r
-#define GPIO_PORT_CLR4_CLRP09_Msk (0x01UL << GPIO_PORT_CLR4_CLRP09_Pos) /*!< GPIO_PORT CLR4: CLRP09 Mask */\r
-#define GPIO_PORT_CLR4_CLRP010_Pos 10 /*!< GPIO_PORT CLR4: CLRP010 Position */\r
-#define GPIO_PORT_CLR4_CLRP010_Msk (0x01UL << GPIO_PORT_CLR4_CLRP010_Pos) /*!< GPIO_PORT CLR4: CLRP010 Mask */\r
-#define GPIO_PORT_CLR4_CLRP011_Pos 11 /*!< GPIO_PORT CLR4: CLRP011 Position */\r
-#define GPIO_PORT_CLR4_CLRP011_Msk (0x01UL << GPIO_PORT_CLR4_CLRP011_Pos) /*!< GPIO_PORT CLR4: CLRP011 Mask */\r
-#define GPIO_PORT_CLR4_CLRP012_Pos 12 /*!< GPIO_PORT CLR4: CLRP012 Position */\r
-#define GPIO_PORT_CLR4_CLRP012_Msk (0x01UL << GPIO_PORT_CLR4_CLRP012_Pos) /*!< GPIO_PORT CLR4: CLRP012 Mask */\r
-#define GPIO_PORT_CLR4_CLRP013_Pos 13 /*!< GPIO_PORT CLR4: CLRP013 Position */\r
-#define GPIO_PORT_CLR4_CLRP013_Msk (0x01UL << GPIO_PORT_CLR4_CLRP013_Pos) /*!< GPIO_PORT CLR4: CLRP013 Mask */\r
-#define GPIO_PORT_CLR4_CLRP014_Pos 14 /*!< GPIO_PORT CLR4: CLRP014 Position */\r
-#define GPIO_PORT_CLR4_CLRP014_Msk (0x01UL << GPIO_PORT_CLR4_CLRP014_Pos) /*!< GPIO_PORT CLR4: CLRP014 Mask */\r
-#define GPIO_PORT_CLR4_CLRP015_Pos 15 /*!< GPIO_PORT CLR4: CLRP015 Position */\r
-#define GPIO_PORT_CLR4_CLRP015_Msk (0x01UL << GPIO_PORT_CLR4_CLRP015_Pos) /*!< GPIO_PORT CLR4: CLRP015 Mask */\r
-#define GPIO_PORT_CLR4_CLRP016_Pos 16 /*!< GPIO_PORT CLR4: CLRP016 Position */\r
-#define GPIO_PORT_CLR4_CLRP016_Msk (0x01UL << GPIO_PORT_CLR4_CLRP016_Pos) /*!< GPIO_PORT CLR4: CLRP016 Mask */\r
-#define GPIO_PORT_CLR4_CLRP017_Pos 17 /*!< GPIO_PORT CLR4: CLRP017 Position */\r
-#define GPIO_PORT_CLR4_CLRP017_Msk (0x01UL << GPIO_PORT_CLR4_CLRP017_Pos) /*!< GPIO_PORT CLR4: CLRP017 Mask */\r
-#define GPIO_PORT_CLR4_CLRP018_Pos 18 /*!< GPIO_PORT CLR4: CLRP018 Position */\r
-#define GPIO_PORT_CLR4_CLRP018_Msk (0x01UL << GPIO_PORT_CLR4_CLRP018_Pos) /*!< GPIO_PORT CLR4: CLRP018 Mask */\r
-#define GPIO_PORT_CLR4_CLRP019_Pos 19 /*!< GPIO_PORT CLR4: CLRP019 Position */\r
-#define GPIO_PORT_CLR4_CLRP019_Msk (0x01UL << GPIO_PORT_CLR4_CLRP019_Pos) /*!< GPIO_PORT CLR4: CLRP019 Mask */\r
-#define GPIO_PORT_CLR4_CLRP020_Pos 20 /*!< GPIO_PORT CLR4: CLRP020 Position */\r
-#define GPIO_PORT_CLR4_CLRP020_Msk (0x01UL << GPIO_PORT_CLR4_CLRP020_Pos) /*!< GPIO_PORT CLR4: CLRP020 Mask */\r
-#define GPIO_PORT_CLR4_CLRP021_Pos 21 /*!< GPIO_PORT CLR4: CLRP021 Position */\r
-#define GPIO_PORT_CLR4_CLRP021_Msk (0x01UL << GPIO_PORT_CLR4_CLRP021_Pos) /*!< GPIO_PORT CLR4: CLRP021 Mask */\r
-#define GPIO_PORT_CLR4_CLRP022_Pos 22 /*!< GPIO_PORT CLR4: CLRP022 Position */\r
-#define GPIO_PORT_CLR4_CLRP022_Msk (0x01UL << GPIO_PORT_CLR4_CLRP022_Pos) /*!< GPIO_PORT CLR4: CLRP022 Mask */\r
-#define GPIO_PORT_CLR4_CLRP023_Pos 23 /*!< GPIO_PORT CLR4: CLRP023 Position */\r
-#define GPIO_PORT_CLR4_CLRP023_Msk (0x01UL << GPIO_PORT_CLR4_CLRP023_Pos) /*!< GPIO_PORT CLR4: CLRP023 Mask */\r
-#define GPIO_PORT_CLR4_CLRP024_Pos 24 /*!< GPIO_PORT CLR4: CLRP024 Position */\r
-#define GPIO_PORT_CLR4_CLRP024_Msk (0x01UL << GPIO_PORT_CLR4_CLRP024_Pos) /*!< GPIO_PORT CLR4: CLRP024 Mask */\r
-#define GPIO_PORT_CLR4_CLRP025_Pos 25 /*!< GPIO_PORT CLR4: CLRP025 Position */\r
-#define GPIO_PORT_CLR4_CLRP025_Msk (0x01UL << GPIO_PORT_CLR4_CLRP025_Pos) /*!< GPIO_PORT CLR4: CLRP025 Mask */\r
-#define GPIO_PORT_CLR4_CLRP026_Pos 26 /*!< GPIO_PORT CLR4: CLRP026 Position */\r
-#define GPIO_PORT_CLR4_CLRP026_Msk (0x01UL << GPIO_PORT_CLR4_CLRP026_Pos) /*!< GPIO_PORT CLR4: CLRP026 Mask */\r
-#define GPIO_PORT_CLR4_CLRP027_Pos 27 /*!< GPIO_PORT CLR4: CLRP027 Position */\r
-#define GPIO_PORT_CLR4_CLRP027_Msk (0x01UL << GPIO_PORT_CLR4_CLRP027_Pos) /*!< GPIO_PORT CLR4: CLRP027 Mask */\r
-#define GPIO_PORT_CLR4_CLRP028_Pos 28 /*!< GPIO_PORT CLR4: CLRP028 Position */\r
-#define GPIO_PORT_CLR4_CLRP028_Msk (0x01UL << GPIO_PORT_CLR4_CLRP028_Pos) /*!< GPIO_PORT CLR4: CLRP028 Mask */\r
-#define GPIO_PORT_CLR4_CLRP029_Pos 29 /*!< GPIO_PORT CLR4: CLRP029 Position */\r
-#define GPIO_PORT_CLR4_CLRP029_Msk (0x01UL << GPIO_PORT_CLR4_CLRP029_Pos) /*!< GPIO_PORT CLR4: CLRP029 Mask */\r
-#define GPIO_PORT_CLR4_CLRP030_Pos 30 /*!< GPIO_PORT CLR4: CLRP030 Position */\r
-#define GPIO_PORT_CLR4_CLRP030_Msk (0x01UL << GPIO_PORT_CLR4_CLRP030_Pos) /*!< GPIO_PORT CLR4: CLRP030 Mask */\r
-#define GPIO_PORT_CLR4_CLRP031_Pos 31 /*!< GPIO_PORT CLR4: CLRP031 Position */\r
-#define GPIO_PORT_CLR4_CLRP031_Msk (0x01UL << GPIO_PORT_CLR4_CLRP031_Pos) /*!< GPIO_PORT CLR4: CLRP031 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_CLR5 -----------------------------------------\r
-#define GPIO_PORT_CLR5_CLRP00_Pos 0 /*!< GPIO_PORT CLR5: CLRP00 Position */\r
-#define GPIO_PORT_CLR5_CLRP00_Msk (0x01UL << GPIO_PORT_CLR5_CLRP00_Pos) /*!< GPIO_PORT CLR5: CLRP00 Mask */\r
-#define GPIO_PORT_CLR5_CLRP01_Pos 1 /*!< GPIO_PORT CLR5: CLRP01 Position */\r
-#define GPIO_PORT_CLR5_CLRP01_Msk (0x01UL << GPIO_PORT_CLR5_CLRP01_Pos) /*!< GPIO_PORT CLR5: CLRP01 Mask */\r
-#define GPIO_PORT_CLR5_CLRP02_Pos 2 /*!< GPIO_PORT CLR5: CLRP02 Position */\r
-#define GPIO_PORT_CLR5_CLRP02_Msk (0x01UL << GPIO_PORT_CLR5_CLRP02_Pos) /*!< GPIO_PORT CLR5: CLRP02 Mask */\r
-#define GPIO_PORT_CLR5_CLRP03_Pos 3 /*!< GPIO_PORT CLR5: CLRP03 Position */\r
-#define GPIO_PORT_CLR5_CLRP03_Msk (0x01UL << GPIO_PORT_CLR5_CLRP03_Pos) /*!< GPIO_PORT CLR5: CLRP03 Mask */\r
-#define GPIO_PORT_CLR5_CLRP04_Pos 4 /*!< GPIO_PORT CLR5: CLRP04 Position */\r
-#define GPIO_PORT_CLR5_CLRP04_Msk (0x01UL << GPIO_PORT_CLR5_CLRP04_Pos) /*!< GPIO_PORT CLR5: CLRP04 Mask */\r
-#define GPIO_PORT_CLR5_CLRP05_Pos 5 /*!< GPIO_PORT CLR5: CLRP05 Position */\r
-#define GPIO_PORT_CLR5_CLRP05_Msk (0x01UL << GPIO_PORT_CLR5_CLRP05_Pos) /*!< GPIO_PORT CLR5: CLRP05 Mask */\r
-#define GPIO_PORT_CLR5_CLRP06_Pos 6 /*!< GPIO_PORT CLR5: CLRP06 Position */\r
-#define GPIO_PORT_CLR5_CLRP06_Msk (0x01UL << GPIO_PORT_CLR5_CLRP06_Pos) /*!< GPIO_PORT CLR5: CLRP06 Mask */\r
-#define GPIO_PORT_CLR5_CLRP07_Pos 7 /*!< GPIO_PORT CLR5: CLRP07 Position */\r
-#define GPIO_PORT_CLR5_CLRP07_Msk (0x01UL << GPIO_PORT_CLR5_CLRP07_Pos) /*!< GPIO_PORT CLR5: CLRP07 Mask */\r
-#define GPIO_PORT_CLR5_CLRP08_Pos 8 /*!< GPIO_PORT CLR5: CLRP08 Position */\r
-#define GPIO_PORT_CLR5_CLRP08_Msk (0x01UL << GPIO_PORT_CLR5_CLRP08_Pos) /*!< GPIO_PORT CLR5: CLRP08 Mask */\r
-#define GPIO_PORT_CLR5_CLRP09_Pos 9 /*!< GPIO_PORT CLR5: CLRP09 Position */\r
-#define GPIO_PORT_CLR5_CLRP09_Msk (0x01UL << GPIO_PORT_CLR5_CLRP09_Pos) /*!< GPIO_PORT CLR5: CLRP09 Mask */\r
-#define GPIO_PORT_CLR5_CLRP010_Pos 10 /*!< GPIO_PORT CLR5: CLRP010 Position */\r
-#define GPIO_PORT_CLR5_CLRP010_Msk (0x01UL << GPIO_PORT_CLR5_CLRP010_Pos) /*!< GPIO_PORT CLR5: CLRP010 Mask */\r
-#define GPIO_PORT_CLR5_CLRP011_Pos 11 /*!< GPIO_PORT CLR5: CLRP011 Position */\r
-#define GPIO_PORT_CLR5_CLRP011_Msk (0x01UL << GPIO_PORT_CLR5_CLRP011_Pos) /*!< GPIO_PORT CLR5: CLRP011 Mask */\r
-#define GPIO_PORT_CLR5_CLRP012_Pos 12 /*!< GPIO_PORT CLR5: CLRP012 Position */\r
-#define GPIO_PORT_CLR5_CLRP012_Msk (0x01UL << GPIO_PORT_CLR5_CLRP012_Pos) /*!< GPIO_PORT CLR5: CLRP012 Mask */\r
-#define GPIO_PORT_CLR5_CLRP013_Pos 13 /*!< GPIO_PORT CLR5: CLRP013 Position */\r
-#define GPIO_PORT_CLR5_CLRP013_Msk (0x01UL << GPIO_PORT_CLR5_CLRP013_Pos) /*!< GPIO_PORT CLR5: CLRP013 Mask */\r
-#define GPIO_PORT_CLR5_CLRP014_Pos 14 /*!< GPIO_PORT CLR5: CLRP014 Position */\r
-#define GPIO_PORT_CLR5_CLRP014_Msk (0x01UL << GPIO_PORT_CLR5_CLRP014_Pos) /*!< GPIO_PORT CLR5: CLRP014 Mask */\r
-#define GPIO_PORT_CLR5_CLRP015_Pos 15 /*!< GPIO_PORT CLR5: CLRP015 Position */\r
-#define GPIO_PORT_CLR5_CLRP015_Msk (0x01UL << GPIO_PORT_CLR5_CLRP015_Pos) /*!< GPIO_PORT CLR5: CLRP015 Mask */\r
-#define GPIO_PORT_CLR5_CLRP016_Pos 16 /*!< GPIO_PORT CLR5: CLRP016 Position */\r
-#define GPIO_PORT_CLR5_CLRP016_Msk (0x01UL << GPIO_PORT_CLR5_CLRP016_Pos) /*!< GPIO_PORT CLR5: CLRP016 Mask */\r
-#define GPIO_PORT_CLR5_CLRP017_Pos 17 /*!< GPIO_PORT CLR5: CLRP017 Position */\r
-#define GPIO_PORT_CLR5_CLRP017_Msk (0x01UL << GPIO_PORT_CLR5_CLRP017_Pos) /*!< GPIO_PORT CLR5: CLRP017 Mask */\r
-#define GPIO_PORT_CLR5_CLRP018_Pos 18 /*!< GPIO_PORT CLR5: CLRP018 Position */\r
-#define GPIO_PORT_CLR5_CLRP018_Msk (0x01UL << GPIO_PORT_CLR5_CLRP018_Pos) /*!< GPIO_PORT CLR5: CLRP018 Mask */\r
-#define GPIO_PORT_CLR5_CLRP019_Pos 19 /*!< GPIO_PORT CLR5: CLRP019 Position */\r
-#define GPIO_PORT_CLR5_CLRP019_Msk (0x01UL << GPIO_PORT_CLR5_CLRP019_Pos) /*!< GPIO_PORT CLR5: CLRP019 Mask */\r
-#define GPIO_PORT_CLR5_CLRP020_Pos 20 /*!< GPIO_PORT CLR5: CLRP020 Position */\r
-#define GPIO_PORT_CLR5_CLRP020_Msk (0x01UL << GPIO_PORT_CLR5_CLRP020_Pos) /*!< GPIO_PORT CLR5: CLRP020 Mask */\r
-#define GPIO_PORT_CLR5_CLRP021_Pos 21 /*!< GPIO_PORT CLR5: CLRP021 Position */\r
-#define GPIO_PORT_CLR5_CLRP021_Msk (0x01UL << GPIO_PORT_CLR5_CLRP021_Pos) /*!< GPIO_PORT CLR5: CLRP021 Mask */\r
-#define GPIO_PORT_CLR5_CLRP022_Pos 22 /*!< GPIO_PORT CLR5: CLRP022 Position */\r
-#define GPIO_PORT_CLR5_CLRP022_Msk (0x01UL << GPIO_PORT_CLR5_CLRP022_Pos) /*!< GPIO_PORT CLR5: CLRP022 Mask */\r
-#define GPIO_PORT_CLR5_CLRP023_Pos 23 /*!< GPIO_PORT CLR5: CLRP023 Position */\r
-#define GPIO_PORT_CLR5_CLRP023_Msk (0x01UL << GPIO_PORT_CLR5_CLRP023_Pos) /*!< GPIO_PORT CLR5: CLRP023 Mask */\r
-#define GPIO_PORT_CLR5_CLRP024_Pos 24 /*!< GPIO_PORT CLR5: CLRP024 Position */\r
-#define GPIO_PORT_CLR5_CLRP024_Msk (0x01UL << GPIO_PORT_CLR5_CLRP024_Pos) /*!< GPIO_PORT CLR5: CLRP024 Mask */\r
-#define GPIO_PORT_CLR5_CLRP025_Pos 25 /*!< GPIO_PORT CLR5: CLRP025 Position */\r
-#define GPIO_PORT_CLR5_CLRP025_Msk (0x01UL << GPIO_PORT_CLR5_CLRP025_Pos) /*!< GPIO_PORT CLR5: CLRP025 Mask */\r
-#define GPIO_PORT_CLR5_CLRP026_Pos 26 /*!< GPIO_PORT CLR5: CLRP026 Position */\r
-#define GPIO_PORT_CLR5_CLRP026_Msk (0x01UL << GPIO_PORT_CLR5_CLRP026_Pos) /*!< GPIO_PORT CLR5: CLRP026 Mask */\r
-#define GPIO_PORT_CLR5_CLRP027_Pos 27 /*!< GPIO_PORT CLR5: CLRP027 Position */\r
-#define GPIO_PORT_CLR5_CLRP027_Msk (0x01UL << GPIO_PORT_CLR5_CLRP027_Pos) /*!< GPIO_PORT CLR5: CLRP027 Mask */\r
-#define GPIO_PORT_CLR5_CLRP028_Pos 28 /*!< GPIO_PORT CLR5: CLRP028 Position */\r
-#define GPIO_PORT_CLR5_CLRP028_Msk (0x01UL << GPIO_PORT_CLR5_CLRP028_Pos) /*!< GPIO_PORT CLR5: CLRP028 Mask */\r
-#define GPIO_PORT_CLR5_CLRP029_Pos 29 /*!< GPIO_PORT CLR5: CLRP029 Position */\r
-#define GPIO_PORT_CLR5_CLRP029_Msk (0x01UL << GPIO_PORT_CLR5_CLRP029_Pos) /*!< GPIO_PORT CLR5: CLRP029 Mask */\r
-#define GPIO_PORT_CLR5_CLRP030_Pos 30 /*!< GPIO_PORT CLR5: CLRP030 Position */\r
-#define GPIO_PORT_CLR5_CLRP030_Msk (0x01UL << GPIO_PORT_CLR5_CLRP030_Pos) /*!< GPIO_PORT CLR5: CLRP030 Mask */\r
-#define GPIO_PORT_CLR5_CLRP031_Pos 31 /*!< GPIO_PORT CLR5: CLRP031 Position */\r
-#define GPIO_PORT_CLR5_CLRP031_Msk (0x01UL << GPIO_PORT_CLR5_CLRP031_Pos) /*!< GPIO_PORT CLR5: CLRP031 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_CLR6 -----------------------------------------\r
-#define GPIO_PORT_CLR6_CLRP00_Pos 0 /*!< GPIO_PORT CLR6: CLRP00 Position */\r
-#define GPIO_PORT_CLR6_CLRP00_Msk (0x01UL << GPIO_PORT_CLR6_CLRP00_Pos) /*!< GPIO_PORT CLR6: CLRP00 Mask */\r
-#define GPIO_PORT_CLR6_CLRP01_Pos 1 /*!< GPIO_PORT CLR6: CLRP01 Position */\r
-#define GPIO_PORT_CLR6_CLRP01_Msk (0x01UL << GPIO_PORT_CLR6_CLRP01_Pos) /*!< GPIO_PORT CLR6: CLRP01 Mask */\r
-#define GPIO_PORT_CLR6_CLRP02_Pos 2 /*!< GPIO_PORT CLR6: CLRP02 Position */\r
-#define GPIO_PORT_CLR6_CLRP02_Msk (0x01UL << GPIO_PORT_CLR6_CLRP02_Pos) /*!< GPIO_PORT CLR6: CLRP02 Mask */\r
-#define GPIO_PORT_CLR6_CLRP03_Pos 3 /*!< GPIO_PORT CLR6: CLRP03 Position */\r
-#define GPIO_PORT_CLR6_CLRP03_Msk (0x01UL << GPIO_PORT_CLR6_CLRP03_Pos) /*!< GPIO_PORT CLR6: CLRP03 Mask */\r
-#define GPIO_PORT_CLR6_CLRP04_Pos 4 /*!< GPIO_PORT CLR6: CLRP04 Position */\r
-#define GPIO_PORT_CLR6_CLRP04_Msk (0x01UL << GPIO_PORT_CLR6_CLRP04_Pos) /*!< GPIO_PORT CLR6: CLRP04 Mask */\r
-#define GPIO_PORT_CLR6_CLRP05_Pos 5 /*!< GPIO_PORT CLR6: CLRP05 Position */\r
-#define GPIO_PORT_CLR6_CLRP05_Msk (0x01UL << GPIO_PORT_CLR6_CLRP05_Pos) /*!< GPIO_PORT CLR6: CLRP05 Mask */\r
-#define GPIO_PORT_CLR6_CLRP06_Pos 6 /*!< GPIO_PORT CLR6: CLRP06 Position */\r
-#define GPIO_PORT_CLR6_CLRP06_Msk (0x01UL << GPIO_PORT_CLR6_CLRP06_Pos) /*!< GPIO_PORT CLR6: CLRP06 Mask */\r
-#define GPIO_PORT_CLR6_CLRP07_Pos 7 /*!< GPIO_PORT CLR6: CLRP07 Position */\r
-#define GPIO_PORT_CLR6_CLRP07_Msk (0x01UL << GPIO_PORT_CLR6_CLRP07_Pos) /*!< GPIO_PORT CLR6: CLRP07 Mask */\r
-#define GPIO_PORT_CLR6_CLRP08_Pos 8 /*!< GPIO_PORT CLR6: CLRP08 Position */\r
-#define GPIO_PORT_CLR6_CLRP08_Msk (0x01UL << GPIO_PORT_CLR6_CLRP08_Pos) /*!< GPIO_PORT CLR6: CLRP08 Mask */\r
-#define GPIO_PORT_CLR6_CLRP09_Pos 9 /*!< GPIO_PORT CLR6: CLRP09 Position */\r
-#define GPIO_PORT_CLR6_CLRP09_Msk (0x01UL << GPIO_PORT_CLR6_CLRP09_Pos) /*!< GPIO_PORT CLR6: CLRP09 Mask */\r
-#define GPIO_PORT_CLR6_CLRP010_Pos 10 /*!< GPIO_PORT CLR6: CLRP010 Position */\r
-#define GPIO_PORT_CLR6_CLRP010_Msk (0x01UL << GPIO_PORT_CLR6_CLRP010_Pos) /*!< GPIO_PORT CLR6: CLRP010 Mask */\r
-#define GPIO_PORT_CLR6_CLRP011_Pos 11 /*!< GPIO_PORT CLR6: CLRP011 Position */\r
-#define GPIO_PORT_CLR6_CLRP011_Msk (0x01UL << GPIO_PORT_CLR6_CLRP011_Pos) /*!< GPIO_PORT CLR6: CLRP011 Mask */\r
-#define GPIO_PORT_CLR6_CLRP012_Pos 12 /*!< GPIO_PORT CLR6: CLRP012 Position */\r
-#define GPIO_PORT_CLR6_CLRP012_Msk (0x01UL << GPIO_PORT_CLR6_CLRP012_Pos) /*!< GPIO_PORT CLR6: CLRP012 Mask */\r
-#define GPIO_PORT_CLR6_CLRP013_Pos 13 /*!< GPIO_PORT CLR6: CLRP013 Position */\r
-#define GPIO_PORT_CLR6_CLRP013_Msk (0x01UL << GPIO_PORT_CLR6_CLRP013_Pos) /*!< GPIO_PORT CLR6: CLRP013 Mask */\r
-#define GPIO_PORT_CLR6_CLRP014_Pos 14 /*!< GPIO_PORT CLR6: CLRP014 Position */\r
-#define GPIO_PORT_CLR6_CLRP014_Msk (0x01UL << GPIO_PORT_CLR6_CLRP014_Pos) /*!< GPIO_PORT CLR6: CLRP014 Mask */\r
-#define GPIO_PORT_CLR6_CLRP015_Pos 15 /*!< GPIO_PORT CLR6: CLRP015 Position */\r
-#define GPIO_PORT_CLR6_CLRP015_Msk (0x01UL << GPIO_PORT_CLR6_CLRP015_Pos) /*!< GPIO_PORT CLR6: CLRP015 Mask */\r
-#define GPIO_PORT_CLR6_CLRP016_Pos 16 /*!< GPIO_PORT CLR6: CLRP016 Position */\r
-#define GPIO_PORT_CLR6_CLRP016_Msk (0x01UL << GPIO_PORT_CLR6_CLRP016_Pos) /*!< GPIO_PORT CLR6: CLRP016 Mask */\r
-#define GPIO_PORT_CLR6_CLRP017_Pos 17 /*!< GPIO_PORT CLR6: CLRP017 Position */\r
-#define GPIO_PORT_CLR6_CLRP017_Msk (0x01UL << GPIO_PORT_CLR6_CLRP017_Pos) /*!< GPIO_PORT CLR6: CLRP017 Mask */\r
-#define GPIO_PORT_CLR6_CLRP018_Pos 18 /*!< GPIO_PORT CLR6: CLRP018 Position */\r
-#define GPIO_PORT_CLR6_CLRP018_Msk (0x01UL << GPIO_PORT_CLR6_CLRP018_Pos) /*!< GPIO_PORT CLR6: CLRP018 Mask */\r
-#define GPIO_PORT_CLR6_CLRP019_Pos 19 /*!< GPIO_PORT CLR6: CLRP019 Position */\r
-#define GPIO_PORT_CLR6_CLRP019_Msk (0x01UL << GPIO_PORT_CLR6_CLRP019_Pos) /*!< GPIO_PORT CLR6: CLRP019 Mask */\r
-#define GPIO_PORT_CLR6_CLRP020_Pos 20 /*!< GPIO_PORT CLR6: CLRP020 Position */\r
-#define GPIO_PORT_CLR6_CLRP020_Msk (0x01UL << GPIO_PORT_CLR6_CLRP020_Pos) /*!< GPIO_PORT CLR6: CLRP020 Mask */\r
-#define GPIO_PORT_CLR6_CLRP021_Pos 21 /*!< GPIO_PORT CLR6: CLRP021 Position */\r
-#define GPIO_PORT_CLR6_CLRP021_Msk (0x01UL << GPIO_PORT_CLR6_CLRP021_Pos) /*!< GPIO_PORT CLR6: CLRP021 Mask */\r
-#define GPIO_PORT_CLR6_CLRP022_Pos 22 /*!< GPIO_PORT CLR6: CLRP022 Position */\r
-#define GPIO_PORT_CLR6_CLRP022_Msk (0x01UL << GPIO_PORT_CLR6_CLRP022_Pos) /*!< GPIO_PORT CLR6: CLRP022 Mask */\r
-#define GPIO_PORT_CLR6_CLRP023_Pos 23 /*!< GPIO_PORT CLR6: CLRP023 Position */\r
-#define GPIO_PORT_CLR6_CLRP023_Msk (0x01UL << GPIO_PORT_CLR6_CLRP023_Pos) /*!< GPIO_PORT CLR6: CLRP023 Mask */\r
-#define GPIO_PORT_CLR6_CLRP024_Pos 24 /*!< GPIO_PORT CLR6: CLRP024 Position */\r
-#define GPIO_PORT_CLR6_CLRP024_Msk (0x01UL << GPIO_PORT_CLR6_CLRP024_Pos) /*!< GPIO_PORT CLR6: CLRP024 Mask */\r
-#define GPIO_PORT_CLR6_CLRP025_Pos 25 /*!< GPIO_PORT CLR6: CLRP025 Position */\r
-#define GPIO_PORT_CLR6_CLRP025_Msk (0x01UL << GPIO_PORT_CLR6_CLRP025_Pos) /*!< GPIO_PORT CLR6: CLRP025 Mask */\r
-#define GPIO_PORT_CLR6_CLRP026_Pos 26 /*!< GPIO_PORT CLR6: CLRP026 Position */\r
-#define GPIO_PORT_CLR6_CLRP026_Msk (0x01UL << GPIO_PORT_CLR6_CLRP026_Pos) /*!< GPIO_PORT CLR6: CLRP026 Mask */\r
-#define GPIO_PORT_CLR6_CLRP027_Pos 27 /*!< GPIO_PORT CLR6: CLRP027 Position */\r
-#define GPIO_PORT_CLR6_CLRP027_Msk (0x01UL << GPIO_PORT_CLR6_CLRP027_Pos) /*!< GPIO_PORT CLR6: CLRP027 Mask */\r
-#define GPIO_PORT_CLR6_CLRP028_Pos 28 /*!< GPIO_PORT CLR6: CLRP028 Position */\r
-#define GPIO_PORT_CLR6_CLRP028_Msk (0x01UL << GPIO_PORT_CLR6_CLRP028_Pos) /*!< GPIO_PORT CLR6: CLRP028 Mask */\r
-#define GPIO_PORT_CLR6_CLRP029_Pos 29 /*!< GPIO_PORT CLR6: CLRP029 Position */\r
-#define GPIO_PORT_CLR6_CLRP029_Msk (0x01UL << GPIO_PORT_CLR6_CLRP029_Pos) /*!< GPIO_PORT CLR6: CLRP029 Mask */\r
-#define GPIO_PORT_CLR6_CLRP030_Pos 30 /*!< GPIO_PORT CLR6: CLRP030 Position */\r
-#define GPIO_PORT_CLR6_CLRP030_Msk (0x01UL << GPIO_PORT_CLR6_CLRP030_Pos) /*!< GPIO_PORT CLR6: CLRP030 Mask */\r
-#define GPIO_PORT_CLR6_CLRP031_Pos 31 /*!< GPIO_PORT CLR6: CLRP031 Position */\r
-#define GPIO_PORT_CLR6_CLRP031_Msk (0x01UL << GPIO_PORT_CLR6_CLRP031_Pos) /*!< GPIO_PORT CLR6: CLRP031 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_CLR7 -----------------------------------------\r
-#define GPIO_PORT_CLR7_CLRP00_Pos 0 /*!< GPIO_PORT CLR7: CLRP00 Position */\r
-#define GPIO_PORT_CLR7_CLRP00_Msk (0x01UL << GPIO_PORT_CLR7_CLRP00_Pos) /*!< GPIO_PORT CLR7: CLRP00 Mask */\r
-#define GPIO_PORT_CLR7_CLRP01_Pos 1 /*!< GPIO_PORT CLR7: CLRP01 Position */\r
-#define GPIO_PORT_CLR7_CLRP01_Msk (0x01UL << GPIO_PORT_CLR7_CLRP01_Pos) /*!< GPIO_PORT CLR7: CLRP01 Mask */\r
-#define GPIO_PORT_CLR7_CLRP02_Pos 2 /*!< GPIO_PORT CLR7: CLRP02 Position */\r
-#define GPIO_PORT_CLR7_CLRP02_Msk (0x01UL << GPIO_PORT_CLR7_CLRP02_Pos) /*!< GPIO_PORT CLR7: CLRP02 Mask */\r
-#define GPIO_PORT_CLR7_CLRP03_Pos 3 /*!< GPIO_PORT CLR7: CLRP03 Position */\r
-#define GPIO_PORT_CLR7_CLRP03_Msk (0x01UL << GPIO_PORT_CLR7_CLRP03_Pos) /*!< GPIO_PORT CLR7: CLRP03 Mask */\r
-#define GPIO_PORT_CLR7_CLRP04_Pos 4 /*!< GPIO_PORT CLR7: CLRP04 Position */\r
-#define GPIO_PORT_CLR7_CLRP04_Msk (0x01UL << GPIO_PORT_CLR7_CLRP04_Pos) /*!< GPIO_PORT CLR7: CLRP04 Mask */\r
-#define GPIO_PORT_CLR7_CLRP05_Pos 5 /*!< GPIO_PORT CLR7: CLRP05 Position */\r
-#define GPIO_PORT_CLR7_CLRP05_Msk (0x01UL << GPIO_PORT_CLR7_CLRP05_Pos) /*!< GPIO_PORT CLR7: CLRP05 Mask */\r
-#define GPIO_PORT_CLR7_CLRP06_Pos 6 /*!< GPIO_PORT CLR7: CLRP06 Position */\r
-#define GPIO_PORT_CLR7_CLRP06_Msk (0x01UL << GPIO_PORT_CLR7_CLRP06_Pos) /*!< GPIO_PORT CLR7: CLRP06 Mask */\r
-#define GPIO_PORT_CLR7_CLRP07_Pos 7 /*!< GPIO_PORT CLR7: CLRP07 Position */\r
-#define GPIO_PORT_CLR7_CLRP07_Msk (0x01UL << GPIO_PORT_CLR7_CLRP07_Pos) /*!< GPIO_PORT CLR7: CLRP07 Mask */\r
-#define GPIO_PORT_CLR7_CLRP08_Pos 8 /*!< GPIO_PORT CLR7: CLRP08 Position */\r
-#define GPIO_PORT_CLR7_CLRP08_Msk (0x01UL << GPIO_PORT_CLR7_CLRP08_Pos) /*!< GPIO_PORT CLR7: CLRP08 Mask */\r
-#define GPIO_PORT_CLR7_CLRP09_Pos 9 /*!< GPIO_PORT CLR7: CLRP09 Position */\r
-#define GPIO_PORT_CLR7_CLRP09_Msk (0x01UL << GPIO_PORT_CLR7_CLRP09_Pos) /*!< GPIO_PORT CLR7: CLRP09 Mask */\r
-#define GPIO_PORT_CLR7_CLRP010_Pos 10 /*!< GPIO_PORT CLR7: CLRP010 Position */\r
-#define GPIO_PORT_CLR7_CLRP010_Msk (0x01UL << GPIO_PORT_CLR7_CLRP010_Pos) /*!< GPIO_PORT CLR7: CLRP010 Mask */\r
-#define GPIO_PORT_CLR7_CLRP011_Pos 11 /*!< GPIO_PORT CLR7: CLRP011 Position */\r
-#define GPIO_PORT_CLR7_CLRP011_Msk (0x01UL << GPIO_PORT_CLR7_CLRP011_Pos) /*!< GPIO_PORT CLR7: CLRP011 Mask */\r
-#define GPIO_PORT_CLR7_CLRP012_Pos 12 /*!< GPIO_PORT CLR7: CLRP012 Position */\r
-#define GPIO_PORT_CLR7_CLRP012_Msk (0x01UL << GPIO_PORT_CLR7_CLRP012_Pos) /*!< GPIO_PORT CLR7: CLRP012 Mask */\r
-#define GPIO_PORT_CLR7_CLRP013_Pos 13 /*!< GPIO_PORT CLR7: CLRP013 Position */\r
-#define GPIO_PORT_CLR7_CLRP013_Msk (0x01UL << GPIO_PORT_CLR7_CLRP013_Pos) /*!< GPIO_PORT CLR7: CLRP013 Mask */\r
-#define GPIO_PORT_CLR7_CLRP014_Pos 14 /*!< GPIO_PORT CLR7: CLRP014 Position */\r
-#define GPIO_PORT_CLR7_CLRP014_Msk (0x01UL << GPIO_PORT_CLR7_CLRP014_Pos) /*!< GPIO_PORT CLR7: CLRP014 Mask */\r
-#define GPIO_PORT_CLR7_CLRP015_Pos 15 /*!< GPIO_PORT CLR7: CLRP015 Position */\r
-#define GPIO_PORT_CLR7_CLRP015_Msk (0x01UL << GPIO_PORT_CLR7_CLRP015_Pos) /*!< GPIO_PORT CLR7: CLRP015 Mask */\r
-#define GPIO_PORT_CLR7_CLRP016_Pos 16 /*!< GPIO_PORT CLR7: CLRP016 Position */\r
-#define GPIO_PORT_CLR7_CLRP016_Msk (0x01UL << GPIO_PORT_CLR7_CLRP016_Pos) /*!< GPIO_PORT CLR7: CLRP016 Mask */\r
-#define GPIO_PORT_CLR7_CLRP017_Pos 17 /*!< GPIO_PORT CLR7: CLRP017 Position */\r
-#define GPIO_PORT_CLR7_CLRP017_Msk (0x01UL << GPIO_PORT_CLR7_CLRP017_Pos) /*!< GPIO_PORT CLR7: CLRP017 Mask */\r
-#define GPIO_PORT_CLR7_CLRP018_Pos 18 /*!< GPIO_PORT CLR7: CLRP018 Position */\r
-#define GPIO_PORT_CLR7_CLRP018_Msk (0x01UL << GPIO_PORT_CLR7_CLRP018_Pos) /*!< GPIO_PORT CLR7: CLRP018 Mask */\r
-#define GPIO_PORT_CLR7_CLRP019_Pos 19 /*!< GPIO_PORT CLR7: CLRP019 Position */\r
-#define GPIO_PORT_CLR7_CLRP019_Msk (0x01UL << GPIO_PORT_CLR7_CLRP019_Pos) /*!< GPIO_PORT CLR7: CLRP019 Mask */\r
-#define GPIO_PORT_CLR7_CLRP020_Pos 20 /*!< GPIO_PORT CLR7: CLRP020 Position */\r
-#define GPIO_PORT_CLR7_CLRP020_Msk (0x01UL << GPIO_PORT_CLR7_CLRP020_Pos) /*!< GPIO_PORT CLR7: CLRP020 Mask */\r
-#define GPIO_PORT_CLR7_CLRP021_Pos 21 /*!< GPIO_PORT CLR7: CLRP021 Position */\r
-#define GPIO_PORT_CLR7_CLRP021_Msk (0x01UL << GPIO_PORT_CLR7_CLRP021_Pos) /*!< GPIO_PORT CLR7: CLRP021 Mask */\r
-#define GPIO_PORT_CLR7_CLRP022_Pos 22 /*!< GPIO_PORT CLR7: CLRP022 Position */\r
-#define GPIO_PORT_CLR7_CLRP022_Msk (0x01UL << GPIO_PORT_CLR7_CLRP022_Pos) /*!< GPIO_PORT CLR7: CLRP022 Mask */\r
-#define GPIO_PORT_CLR7_CLRP023_Pos 23 /*!< GPIO_PORT CLR7: CLRP023 Position */\r
-#define GPIO_PORT_CLR7_CLRP023_Msk (0x01UL << GPIO_PORT_CLR7_CLRP023_Pos) /*!< GPIO_PORT CLR7: CLRP023 Mask */\r
-#define GPIO_PORT_CLR7_CLRP024_Pos 24 /*!< GPIO_PORT CLR7: CLRP024 Position */\r
-#define GPIO_PORT_CLR7_CLRP024_Msk (0x01UL << GPIO_PORT_CLR7_CLRP024_Pos) /*!< GPIO_PORT CLR7: CLRP024 Mask */\r
-#define GPIO_PORT_CLR7_CLRP025_Pos 25 /*!< GPIO_PORT CLR7: CLRP025 Position */\r
-#define GPIO_PORT_CLR7_CLRP025_Msk (0x01UL << GPIO_PORT_CLR7_CLRP025_Pos) /*!< GPIO_PORT CLR7: CLRP025 Mask */\r
-#define GPIO_PORT_CLR7_CLRP026_Pos 26 /*!< GPIO_PORT CLR7: CLRP026 Position */\r
-#define GPIO_PORT_CLR7_CLRP026_Msk (0x01UL << GPIO_PORT_CLR7_CLRP026_Pos) /*!< GPIO_PORT CLR7: CLRP026 Mask */\r
-#define GPIO_PORT_CLR7_CLRP027_Pos 27 /*!< GPIO_PORT CLR7: CLRP027 Position */\r
-#define GPIO_PORT_CLR7_CLRP027_Msk (0x01UL << GPIO_PORT_CLR7_CLRP027_Pos) /*!< GPIO_PORT CLR7: CLRP027 Mask */\r
-#define GPIO_PORT_CLR7_CLRP028_Pos 28 /*!< GPIO_PORT CLR7: CLRP028 Position */\r
-#define GPIO_PORT_CLR7_CLRP028_Msk (0x01UL << GPIO_PORT_CLR7_CLRP028_Pos) /*!< GPIO_PORT CLR7: CLRP028 Mask */\r
-#define GPIO_PORT_CLR7_CLRP029_Pos 29 /*!< GPIO_PORT CLR7: CLRP029 Position */\r
-#define GPIO_PORT_CLR7_CLRP029_Msk (0x01UL << GPIO_PORT_CLR7_CLRP029_Pos) /*!< GPIO_PORT CLR7: CLRP029 Mask */\r
-#define GPIO_PORT_CLR7_CLRP030_Pos 30 /*!< GPIO_PORT CLR7: CLRP030 Position */\r
-#define GPIO_PORT_CLR7_CLRP030_Msk (0x01UL << GPIO_PORT_CLR7_CLRP030_Pos) /*!< GPIO_PORT CLR7: CLRP030 Mask */\r
-#define GPIO_PORT_CLR7_CLRP031_Pos 31 /*!< GPIO_PORT CLR7: CLRP031 Position */\r
-#define GPIO_PORT_CLR7_CLRP031_Msk (0x01UL << GPIO_PORT_CLR7_CLRP031_Pos) /*!< GPIO_PORT CLR7: CLRP031 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_NOT0 -----------------------------------------\r
-#define GPIO_PORT_NOT0_NOTP0_Pos 0 /*!< GPIO_PORT NOT0: NOTP0 Position */\r
-#define GPIO_PORT_NOT0_NOTP0_Msk (0x01UL << GPIO_PORT_NOT0_NOTP0_Pos) /*!< GPIO_PORT NOT0: NOTP0 Mask */\r
-#define GPIO_PORT_NOT0_NOTP1_Pos 1 /*!< GPIO_PORT NOT0: NOTP1 Position */\r
-#define GPIO_PORT_NOT0_NOTP1_Msk (0x01UL << GPIO_PORT_NOT0_NOTP1_Pos) /*!< GPIO_PORT NOT0: NOTP1 Mask */\r
-#define GPIO_PORT_NOT0_NOTP2_Pos 2 /*!< GPIO_PORT NOT0: NOTP2 Position */\r
-#define GPIO_PORT_NOT0_NOTP2_Msk (0x01UL << GPIO_PORT_NOT0_NOTP2_Pos) /*!< GPIO_PORT NOT0: NOTP2 Mask */\r
-#define GPIO_PORT_NOT0_NOTP3_Pos 3 /*!< GPIO_PORT NOT0: NOTP3 Position */\r
-#define GPIO_PORT_NOT0_NOTP3_Msk (0x01UL << GPIO_PORT_NOT0_NOTP3_Pos) /*!< GPIO_PORT NOT0: NOTP3 Mask */\r
-#define GPIO_PORT_NOT0_NOTP4_Pos 4 /*!< GPIO_PORT NOT0: NOTP4 Position */\r
-#define GPIO_PORT_NOT0_NOTP4_Msk (0x01UL << GPIO_PORT_NOT0_NOTP4_Pos) /*!< GPIO_PORT NOT0: NOTP4 Mask */\r
-#define GPIO_PORT_NOT0_NOTP5_Pos 5 /*!< GPIO_PORT NOT0: NOTP5 Position */\r
-#define GPIO_PORT_NOT0_NOTP5_Msk (0x01UL << GPIO_PORT_NOT0_NOTP5_Pos) /*!< GPIO_PORT NOT0: NOTP5 Mask */\r
-#define GPIO_PORT_NOT0_NOTP6_Pos 6 /*!< GPIO_PORT NOT0: NOTP6 Position */\r
-#define GPIO_PORT_NOT0_NOTP6_Msk (0x01UL << GPIO_PORT_NOT0_NOTP6_Pos) /*!< GPIO_PORT NOT0: NOTP6 Mask */\r
-#define GPIO_PORT_NOT0_NOTP7_Pos 7 /*!< GPIO_PORT NOT0: NOTP7 Position */\r
-#define GPIO_PORT_NOT0_NOTP7_Msk (0x01UL << GPIO_PORT_NOT0_NOTP7_Pos) /*!< GPIO_PORT NOT0: NOTP7 Mask */\r
-#define GPIO_PORT_NOT0_NOTP8_Pos 8 /*!< GPIO_PORT NOT0: NOTP8 Position */\r
-#define GPIO_PORT_NOT0_NOTP8_Msk (0x01UL << GPIO_PORT_NOT0_NOTP8_Pos) /*!< GPIO_PORT NOT0: NOTP8 Mask */\r
-#define GPIO_PORT_NOT0_NOTP9_Pos 9 /*!< GPIO_PORT NOT0: NOTP9 Position */\r
-#define GPIO_PORT_NOT0_NOTP9_Msk (0x01UL << GPIO_PORT_NOT0_NOTP9_Pos) /*!< GPIO_PORT NOT0: NOTP9 Mask */\r
-#define GPIO_PORT_NOT0_NOTP10_Pos 10 /*!< GPIO_PORT NOT0: NOTP10 Position */\r
-#define GPIO_PORT_NOT0_NOTP10_Msk (0x01UL << GPIO_PORT_NOT0_NOTP10_Pos) /*!< GPIO_PORT NOT0: NOTP10 Mask */\r
-#define GPIO_PORT_NOT0_NOTP11_Pos 11 /*!< GPIO_PORT NOT0: NOTP11 Position */\r
-#define GPIO_PORT_NOT0_NOTP11_Msk (0x01UL << GPIO_PORT_NOT0_NOTP11_Pos) /*!< GPIO_PORT NOT0: NOTP11 Mask */\r
-#define GPIO_PORT_NOT0_NOTP12_Pos 12 /*!< GPIO_PORT NOT0: NOTP12 Position */\r
-#define GPIO_PORT_NOT0_NOTP12_Msk (0x01UL << GPIO_PORT_NOT0_NOTP12_Pos) /*!< GPIO_PORT NOT0: NOTP12 Mask */\r
-#define GPIO_PORT_NOT0_NOTP13_Pos 13 /*!< GPIO_PORT NOT0: NOTP13 Position */\r
-#define GPIO_PORT_NOT0_NOTP13_Msk (0x01UL << GPIO_PORT_NOT0_NOTP13_Pos) /*!< GPIO_PORT NOT0: NOTP13 Mask */\r
-#define GPIO_PORT_NOT0_NOTP14_Pos 14 /*!< GPIO_PORT NOT0: NOTP14 Position */\r
-#define GPIO_PORT_NOT0_NOTP14_Msk (0x01UL << GPIO_PORT_NOT0_NOTP14_Pos) /*!< GPIO_PORT NOT0: NOTP14 Mask */\r
-#define GPIO_PORT_NOT0_NOTP15_Pos 15 /*!< GPIO_PORT NOT0: NOTP15 Position */\r
-#define GPIO_PORT_NOT0_NOTP15_Msk (0x01UL << GPIO_PORT_NOT0_NOTP15_Pos) /*!< GPIO_PORT NOT0: NOTP15 Mask */\r
-#define GPIO_PORT_NOT0_NOTP16_Pos 16 /*!< GPIO_PORT NOT0: NOTP16 Position */\r
-#define GPIO_PORT_NOT0_NOTP16_Msk (0x01UL << GPIO_PORT_NOT0_NOTP16_Pos) /*!< GPIO_PORT NOT0: NOTP16 Mask */\r
-#define GPIO_PORT_NOT0_NOTP17_Pos 17 /*!< GPIO_PORT NOT0: NOTP17 Position */\r
-#define GPIO_PORT_NOT0_NOTP17_Msk (0x01UL << GPIO_PORT_NOT0_NOTP17_Pos) /*!< GPIO_PORT NOT0: NOTP17 Mask */\r
-#define GPIO_PORT_NOT0_NOTP18_Pos 18 /*!< GPIO_PORT NOT0: NOTP18 Position */\r
-#define GPIO_PORT_NOT0_NOTP18_Msk (0x01UL << GPIO_PORT_NOT0_NOTP18_Pos) /*!< GPIO_PORT NOT0: NOTP18 Mask */\r
-#define GPIO_PORT_NOT0_NOTP19_Pos 19 /*!< GPIO_PORT NOT0: NOTP19 Position */\r
-#define GPIO_PORT_NOT0_NOTP19_Msk (0x01UL << GPIO_PORT_NOT0_NOTP19_Pos) /*!< GPIO_PORT NOT0: NOTP19 Mask */\r
-#define GPIO_PORT_NOT0_NOTP20_Pos 20 /*!< GPIO_PORT NOT0: NOTP20 Position */\r
-#define GPIO_PORT_NOT0_NOTP20_Msk (0x01UL << GPIO_PORT_NOT0_NOTP20_Pos) /*!< GPIO_PORT NOT0: NOTP20 Mask */\r
-#define GPIO_PORT_NOT0_NOTP21_Pos 21 /*!< GPIO_PORT NOT0: NOTP21 Position */\r
-#define GPIO_PORT_NOT0_NOTP21_Msk (0x01UL << GPIO_PORT_NOT0_NOTP21_Pos) /*!< GPIO_PORT NOT0: NOTP21 Mask */\r
-#define GPIO_PORT_NOT0_NOTP22_Pos 22 /*!< GPIO_PORT NOT0: NOTP22 Position */\r
-#define GPIO_PORT_NOT0_NOTP22_Msk (0x01UL << GPIO_PORT_NOT0_NOTP22_Pos) /*!< GPIO_PORT NOT0: NOTP22 Mask */\r
-#define GPIO_PORT_NOT0_NOTP23_Pos 23 /*!< GPIO_PORT NOT0: NOTP23 Position */\r
-#define GPIO_PORT_NOT0_NOTP23_Msk (0x01UL << GPIO_PORT_NOT0_NOTP23_Pos) /*!< GPIO_PORT NOT0: NOTP23 Mask */\r
-#define GPIO_PORT_NOT0_NOTP24_Pos 24 /*!< GPIO_PORT NOT0: NOTP24 Position */\r
-#define GPIO_PORT_NOT0_NOTP24_Msk (0x01UL << GPIO_PORT_NOT0_NOTP24_Pos) /*!< GPIO_PORT NOT0: NOTP24 Mask */\r
-#define GPIO_PORT_NOT0_NOTP25_Pos 25 /*!< GPIO_PORT NOT0: NOTP25 Position */\r
-#define GPIO_PORT_NOT0_NOTP25_Msk (0x01UL << GPIO_PORT_NOT0_NOTP25_Pos) /*!< GPIO_PORT NOT0: NOTP25 Mask */\r
-#define GPIO_PORT_NOT0_NOTP26_Pos 26 /*!< GPIO_PORT NOT0: NOTP26 Position */\r
-#define GPIO_PORT_NOT0_NOTP26_Msk (0x01UL << GPIO_PORT_NOT0_NOTP26_Pos) /*!< GPIO_PORT NOT0: NOTP26 Mask */\r
-#define GPIO_PORT_NOT0_NOTP27_Pos 27 /*!< GPIO_PORT NOT0: NOTP27 Position */\r
-#define GPIO_PORT_NOT0_NOTP27_Msk (0x01UL << GPIO_PORT_NOT0_NOTP27_Pos) /*!< GPIO_PORT NOT0: NOTP27 Mask */\r
-#define GPIO_PORT_NOT0_NOTP28_Pos 28 /*!< GPIO_PORT NOT0: NOTP28 Position */\r
-#define GPIO_PORT_NOT0_NOTP28_Msk (0x01UL << GPIO_PORT_NOT0_NOTP28_Pos) /*!< GPIO_PORT NOT0: NOTP28 Mask */\r
-#define GPIO_PORT_NOT0_NOTP29_Pos 29 /*!< GPIO_PORT NOT0: NOTP29 Position */\r
-#define GPIO_PORT_NOT0_NOTP29_Msk (0x01UL << GPIO_PORT_NOT0_NOTP29_Pos) /*!< GPIO_PORT NOT0: NOTP29 Mask */\r
-#define GPIO_PORT_NOT0_NOTP30_Pos 30 /*!< GPIO_PORT NOT0: NOTP30 Position */\r
-#define GPIO_PORT_NOT0_NOTP30_Msk (0x01UL << GPIO_PORT_NOT0_NOTP30_Pos) /*!< GPIO_PORT NOT0: NOTP30 Mask */\r
-#define GPIO_PORT_NOT0_NOTP31_Pos 31 /*!< GPIO_PORT NOT0: NOTP31 Position */\r
-#define GPIO_PORT_NOT0_NOTP31_Msk (0x01UL << GPIO_PORT_NOT0_NOTP31_Pos) /*!< GPIO_PORT NOT0: NOTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_NOT1 -----------------------------------------\r
-#define GPIO_PORT_NOT1_NOTP0_Pos 0 /*!< GPIO_PORT NOT1: NOTP0 Position */\r
-#define GPIO_PORT_NOT1_NOTP0_Msk (0x01UL << GPIO_PORT_NOT1_NOTP0_Pos) /*!< GPIO_PORT NOT1: NOTP0 Mask */\r
-#define GPIO_PORT_NOT1_NOTP1_Pos 1 /*!< GPIO_PORT NOT1: NOTP1 Position */\r
-#define GPIO_PORT_NOT1_NOTP1_Msk (0x01UL << GPIO_PORT_NOT1_NOTP1_Pos) /*!< GPIO_PORT NOT1: NOTP1 Mask */\r
-#define GPIO_PORT_NOT1_NOTP2_Pos 2 /*!< GPIO_PORT NOT1: NOTP2 Position */\r
-#define GPIO_PORT_NOT1_NOTP2_Msk (0x01UL << GPIO_PORT_NOT1_NOTP2_Pos) /*!< GPIO_PORT NOT1: NOTP2 Mask */\r
-#define GPIO_PORT_NOT1_NOTP3_Pos 3 /*!< GPIO_PORT NOT1: NOTP3 Position */\r
-#define GPIO_PORT_NOT1_NOTP3_Msk (0x01UL << GPIO_PORT_NOT1_NOTP3_Pos) /*!< GPIO_PORT NOT1: NOTP3 Mask */\r
-#define GPIO_PORT_NOT1_NOTP4_Pos 4 /*!< GPIO_PORT NOT1: NOTP4 Position */\r
-#define GPIO_PORT_NOT1_NOTP4_Msk (0x01UL << GPIO_PORT_NOT1_NOTP4_Pos) /*!< GPIO_PORT NOT1: NOTP4 Mask */\r
-#define GPIO_PORT_NOT1_NOTP5_Pos 5 /*!< GPIO_PORT NOT1: NOTP5 Position */\r
-#define GPIO_PORT_NOT1_NOTP5_Msk (0x01UL << GPIO_PORT_NOT1_NOTP5_Pos) /*!< GPIO_PORT NOT1: NOTP5 Mask */\r
-#define GPIO_PORT_NOT1_NOTP6_Pos 6 /*!< GPIO_PORT NOT1: NOTP6 Position */\r
-#define GPIO_PORT_NOT1_NOTP6_Msk (0x01UL << GPIO_PORT_NOT1_NOTP6_Pos) /*!< GPIO_PORT NOT1: NOTP6 Mask */\r
-#define GPIO_PORT_NOT1_NOTP7_Pos 7 /*!< GPIO_PORT NOT1: NOTP7 Position */\r
-#define GPIO_PORT_NOT1_NOTP7_Msk (0x01UL << GPIO_PORT_NOT1_NOTP7_Pos) /*!< GPIO_PORT NOT1: NOTP7 Mask */\r
-#define GPIO_PORT_NOT1_NOTP8_Pos 8 /*!< GPIO_PORT NOT1: NOTP8 Position */\r
-#define GPIO_PORT_NOT1_NOTP8_Msk (0x01UL << GPIO_PORT_NOT1_NOTP8_Pos) /*!< GPIO_PORT NOT1: NOTP8 Mask */\r
-#define GPIO_PORT_NOT1_NOTP9_Pos 9 /*!< GPIO_PORT NOT1: NOTP9 Position */\r
-#define GPIO_PORT_NOT1_NOTP9_Msk (0x01UL << GPIO_PORT_NOT1_NOTP9_Pos) /*!< GPIO_PORT NOT1: NOTP9 Mask */\r
-#define GPIO_PORT_NOT1_NOTP10_Pos 10 /*!< GPIO_PORT NOT1: NOTP10 Position */\r
-#define GPIO_PORT_NOT1_NOTP10_Msk (0x01UL << GPIO_PORT_NOT1_NOTP10_Pos) /*!< GPIO_PORT NOT1: NOTP10 Mask */\r
-#define GPIO_PORT_NOT1_NOTP11_Pos 11 /*!< GPIO_PORT NOT1: NOTP11 Position */\r
-#define GPIO_PORT_NOT1_NOTP11_Msk (0x01UL << GPIO_PORT_NOT1_NOTP11_Pos) /*!< GPIO_PORT NOT1: NOTP11 Mask */\r
-#define GPIO_PORT_NOT1_NOTP12_Pos 12 /*!< GPIO_PORT NOT1: NOTP12 Position */\r
-#define GPIO_PORT_NOT1_NOTP12_Msk (0x01UL << GPIO_PORT_NOT1_NOTP12_Pos) /*!< GPIO_PORT NOT1: NOTP12 Mask */\r
-#define GPIO_PORT_NOT1_NOTP13_Pos 13 /*!< GPIO_PORT NOT1: NOTP13 Position */\r
-#define GPIO_PORT_NOT1_NOTP13_Msk (0x01UL << GPIO_PORT_NOT1_NOTP13_Pos) /*!< GPIO_PORT NOT1: NOTP13 Mask */\r
-#define GPIO_PORT_NOT1_NOTP14_Pos 14 /*!< GPIO_PORT NOT1: NOTP14 Position */\r
-#define GPIO_PORT_NOT1_NOTP14_Msk (0x01UL << GPIO_PORT_NOT1_NOTP14_Pos) /*!< GPIO_PORT NOT1: NOTP14 Mask */\r
-#define GPIO_PORT_NOT1_NOTP15_Pos 15 /*!< GPIO_PORT NOT1: NOTP15 Position */\r
-#define GPIO_PORT_NOT1_NOTP15_Msk (0x01UL << GPIO_PORT_NOT1_NOTP15_Pos) /*!< GPIO_PORT NOT1: NOTP15 Mask */\r
-#define GPIO_PORT_NOT1_NOTP16_Pos 16 /*!< GPIO_PORT NOT1: NOTP16 Position */\r
-#define GPIO_PORT_NOT1_NOTP16_Msk (0x01UL << GPIO_PORT_NOT1_NOTP16_Pos) /*!< GPIO_PORT NOT1: NOTP16 Mask */\r
-#define GPIO_PORT_NOT1_NOTP17_Pos 17 /*!< GPIO_PORT NOT1: NOTP17 Position */\r
-#define GPIO_PORT_NOT1_NOTP17_Msk (0x01UL << GPIO_PORT_NOT1_NOTP17_Pos) /*!< GPIO_PORT NOT1: NOTP17 Mask */\r
-#define GPIO_PORT_NOT1_NOTP18_Pos 18 /*!< GPIO_PORT NOT1: NOTP18 Position */\r
-#define GPIO_PORT_NOT1_NOTP18_Msk (0x01UL << GPIO_PORT_NOT1_NOTP18_Pos) /*!< GPIO_PORT NOT1: NOTP18 Mask */\r
-#define GPIO_PORT_NOT1_NOTP19_Pos 19 /*!< GPIO_PORT NOT1: NOTP19 Position */\r
-#define GPIO_PORT_NOT1_NOTP19_Msk (0x01UL << GPIO_PORT_NOT1_NOTP19_Pos) /*!< GPIO_PORT NOT1: NOTP19 Mask */\r
-#define GPIO_PORT_NOT1_NOTP20_Pos 20 /*!< GPIO_PORT NOT1: NOTP20 Position */\r
-#define GPIO_PORT_NOT1_NOTP20_Msk (0x01UL << GPIO_PORT_NOT1_NOTP20_Pos) /*!< GPIO_PORT NOT1: NOTP20 Mask */\r
-#define GPIO_PORT_NOT1_NOTP21_Pos 21 /*!< GPIO_PORT NOT1: NOTP21 Position */\r
-#define GPIO_PORT_NOT1_NOTP21_Msk (0x01UL << GPIO_PORT_NOT1_NOTP21_Pos) /*!< GPIO_PORT NOT1: NOTP21 Mask */\r
-#define GPIO_PORT_NOT1_NOTP22_Pos 22 /*!< GPIO_PORT NOT1: NOTP22 Position */\r
-#define GPIO_PORT_NOT1_NOTP22_Msk (0x01UL << GPIO_PORT_NOT1_NOTP22_Pos) /*!< GPIO_PORT NOT1: NOTP22 Mask */\r
-#define GPIO_PORT_NOT1_NOTP23_Pos 23 /*!< GPIO_PORT NOT1: NOTP23 Position */\r
-#define GPIO_PORT_NOT1_NOTP23_Msk (0x01UL << GPIO_PORT_NOT1_NOTP23_Pos) /*!< GPIO_PORT NOT1: NOTP23 Mask */\r
-#define GPIO_PORT_NOT1_NOTP24_Pos 24 /*!< GPIO_PORT NOT1: NOTP24 Position */\r
-#define GPIO_PORT_NOT1_NOTP24_Msk (0x01UL << GPIO_PORT_NOT1_NOTP24_Pos) /*!< GPIO_PORT NOT1: NOTP24 Mask */\r
-#define GPIO_PORT_NOT1_NOTP25_Pos 25 /*!< GPIO_PORT NOT1: NOTP25 Position */\r
-#define GPIO_PORT_NOT1_NOTP25_Msk (0x01UL << GPIO_PORT_NOT1_NOTP25_Pos) /*!< GPIO_PORT NOT1: NOTP25 Mask */\r
-#define GPIO_PORT_NOT1_NOTP26_Pos 26 /*!< GPIO_PORT NOT1: NOTP26 Position */\r
-#define GPIO_PORT_NOT1_NOTP26_Msk (0x01UL << GPIO_PORT_NOT1_NOTP26_Pos) /*!< GPIO_PORT NOT1: NOTP26 Mask */\r
-#define GPIO_PORT_NOT1_NOTP27_Pos 27 /*!< GPIO_PORT NOT1: NOTP27 Position */\r
-#define GPIO_PORT_NOT1_NOTP27_Msk (0x01UL << GPIO_PORT_NOT1_NOTP27_Pos) /*!< GPIO_PORT NOT1: NOTP27 Mask */\r
-#define GPIO_PORT_NOT1_NOTP28_Pos 28 /*!< GPIO_PORT NOT1: NOTP28 Position */\r
-#define GPIO_PORT_NOT1_NOTP28_Msk (0x01UL << GPIO_PORT_NOT1_NOTP28_Pos) /*!< GPIO_PORT NOT1: NOTP28 Mask */\r
-#define GPIO_PORT_NOT1_NOTP29_Pos 29 /*!< GPIO_PORT NOT1: NOTP29 Position */\r
-#define GPIO_PORT_NOT1_NOTP29_Msk (0x01UL << GPIO_PORT_NOT1_NOTP29_Pos) /*!< GPIO_PORT NOT1: NOTP29 Mask */\r
-#define GPIO_PORT_NOT1_NOTP30_Pos 30 /*!< GPIO_PORT NOT1: NOTP30 Position */\r
-#define GPIO_PORT_NOT1_NOTP30_Msk (0x01UL << GPIO_PORT_NOT1_NOTP30_Pos) /*!< GPIO_PORT NOT1: NOTP30 Mask */\r
-#define GPIO_PORT_NOT1_NOTP31_Pos 31 /*!< GPIO_PORT NOT1: NOTP31 Position */\r
-#define GPIO_PORT_NOT1_NOTP31_Msk (0x01UL << GPIO_PORT_NOT1_NOTP31_Pos) /*!< GPIO_PORT NOT1: NOTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_NOT2 -----------------------------------------\r
-#define GPIO_PORT_NOT2_NOTP0_Pos 0 /*!< GPIO_PORT NOT2: NOTP0 Position */\r
-#define GPIO_PORT_NOT2_NOTP0_Msk (0x01UL << GPIO_PORT_NOT2_NOTP0_Pos) /*!< GPIO_PORT NOT2: NOTP0 Mask */\r
-#define GPIO_PORT_NOT2_NOTP1_Pos 1 /*!< GPIO_PORT NOT2: NOTP1 Position */\r
-#define GPIO_PORT_NOT2_NOTP1_Msk (0x01UL << GPIO_PORT_NOT2_NOTP1_Pos) /*!< GPIO_PORT NOT2: NOTP1 Mask */\r
-#define GPIO_PORT_NOT2_NOTP2_Pos 2 /*!< GPIO_PORT NOT2: NOTP2 Position */\r
-#define GPIO_PORT_NOT2_NOTP2_Msk (0x01UL << GPIO_PORT_NOT2_NOTP2_Pos) /*!< GPIO_PORT NOT2: NOTP2 Mask */\r
-#define GPIO_PORT_NOT2_NOTP3_Pos 3 /*!< GPIO_PORT NOT2: NOTP3 Position */\r
-#define GPIO_PORT_NOT2_NOTP3_Msk (0x01UL << GPIO_PORT_NOT2_NOTP3_Pos) /*!< GPIO_PORT NOT2: NOTP3 Mask */\r
-#define GPIO_PORT_NOT2_NOTP4_Pos 4 /*!< GPIO_PORT NOT2: NOTP4 Position */\r
-#define GPIO_PORT_NOT2_NOTP4_Msk (0x01UL << GPIO_PORT_NOT2_NOTP4_Pos) /*!< GPIO_PORT NOT2: NOTP4 Mask */\r
-#define GPIO_PORT_NOT2_NOTP5_Pos 5 /*!< GPIO_PORT NOT2: NOTP5 Position */\r
-#define GPIO_PORT_NOT2_NOTP5_Msk (0x01UL << GPIO_PORT_NOT2_NOTP5_Pos) /*!< GPIO_PORT NOT2: NOTP5 Mask */\r
-#define GPIO_PORT_NOT2_NOTP6_Pos 6 /*!< GPIO_PORT NOT2: NOTP6 Position */\r
-#define GPIO_PORT_NOT2_NOTP6_Msk (0x01UL << GPIO_PORT_NOT2_NOTP6_Pos) /*!< GPIO_PORT NOT2: NOTP6 Mask */\r
-#define GPIO_PORT_NOT2_NOTP7_Pos 7 /*!< GPIO_PORT NOT2: NOTP7 Position */\r
-#define GPIO_PORT_NOT2_NOTP7_Msk (0x01UL << GPIO_PORT_NOT2_NOTP7_Pos) /*!< GPIO_PORT NOT2: NOTP7 Mask */\r
-#define GPIO_PORT_NOT2_NOTP8_Pos 8 /*!< GPIO_PORT NOT2: NOTP8 Position */\r
-#define GPIO_PORT_NOT2_NOTP8_Msk (0x01UL << GPIO_PORT_NOT2_NOTP8_Pos) /*!< GPIO_PORT NOT2: NOTP8 Mask */\r
-#define GPIO_PORT_NOT2_NOTP9_Pos 9 /*!< GPIO_PORT NOT2: NOTP9 Position */\r
-#define GPIO_PORT_NOT2_NOTP9_Msk (0x01UL << GPIO_PORT_NOT2_NOTP9_Pos) /*!< GPIO_PORT NOT2: NOTP9 Mask */\r
-#define GPIO_PORT_NOT2_NOTP10_Pos 10 /*!< GPIO_PORT NOT2: NOTP10 Position */\r
-#define GPIO_PORT_NOT2_NOTP10_Msk (0x01UL << GPIO_PORT_NOT2_NOTP10_Pos) /*!< GPIO_PORT NOT2: NOTP10 Mask */\r
-#define GPIO_PORT_NOT2_NOTP11_Pos 11 /*!< GPIO_PORT NOT2: NOTP11 Position */\r
-#define GPIO_PORT_NOT2_NOTP11_Msk (0x01UL << GPIO_PORT_NOT2_NOTP11_Pos) /*!< GPIO_PORT NOT2: NOTP11 Mask */\r
-#define GPIO_PORT_NOT2_NOTP12_Pos 12 /*!< GPIO_PORT NOT2: NOTP12 Position */\r
-#define GPIO_PORT_NOT2_NOTP12_Msk (0x01UL << GPIO_PORT_NOT2_NOTP12_Pos) /*!< GPIO_PORT NOT2: NOTP12 Mask */\r
-#define GPIO_PORT_NOT2_NOTP13_Pos 13 /*!< GPIO_PORT NOT2: NOTP13 Position */\r
-#define GPIO_PORT_NOT2_NOTP13_Msk (0x01UL << GPIO_PORT_NOT2_NOTP13_Pos) /*!< GPIO_PORT NOT2: NOTP13 Mask */\r
-#define GPIO_PORT_NOT2_NOTP14_Pos 14 /*!< GPIO_PORT NOT2: NOTP14 Position */\r
-#define GPIO_PORT_NOT2_NOTP14_Msk (0x01UL << GPIO_PORT_NOT2_NOTP14_Pos) /*!< GPIO_PORT NOT2: NOTP14 Mask */\r
-#define GPIO_PORT_NOT2_NOTP15_Pos 15 /*!< GPIO_PORT NOT2: NOTP15 Position */\r
-#define GPIO_PORT_NOT2_NOTP15_Msk (0x01UL << GPIO_PORT_NOT2_NOTP15_Pos) /*!< GPIO_PORT NOT2: NOTP15 Mask */\r
-#define GPIO_PORT_NOT2_NOTP16_Pos 16 /*!< GPIO_PORT NOT2: NOTP16 Position */\r
-#define GPIO_PORT_NOT2_NOTP16_Msk (0x01UL << GPIO_PORT_NOT2_NOTP16_Pos) /*!< GPIO_PORT NOT2: NOTP16 Mask */\r
-#define GPIO_PORT_NOT2_NOTP17_Pos 17 /*!< GPIO_PORT NOT2: NOTP17 Position */\r
-#define GPIO_PORT_NOT2_NOTP17_Msk (0x01UL << GPIO_PORT_NOT2_NOTP17_Pos) /*!< GPIO_PORT NOT2: NOTP17 Mask */\r
-#define GPIO_PORT_NOT2_NOTP18_Pos 18 /*!< GPIO_PORT NOT2: NOTP18 Position */\r
-#define GPIO_PORT_NOT2_NOTP18_Msk (0x01UL << GPIO_PORT_NOT2_NOTP18_Pos) /*!< GPIO_PORT NOT2: NOTP18 Mask */\r
-#define GPIO_PORT_NOT2_NOTP19_Pos 19 /*!< GPIO_PORT NOT2: NOTP19 Position */\r
-#define GPIO_PORT_NOT2_NOTP19_Msk (0x01UL << GPIO_PORT_NOT2_NOTP19_Pos) /*!< GPIO_PORT NOT2: NOTP19 Mask */\r
-#define GPIO_PORT_NOT2_NOTP20_Pos 20 /*!< GPIO_PORT NOT2: NOTP20 Position */\r
-#define GPIO_PORT_NOT2_NOTP20_Msk (0x01UL << GPIO_PORT_NOT2_NOTP20_Pos) /*!< GPIO_PORT NOT2: NOTP20 Mask */\r
-#define GPIO_PORT_NOT2_NOTP21_Pos 21 /*!< GPIO_PORT NOT2: NOTP21 Position */\r
-#define GPIO_PORT_NOT2_NOTP21_Msk (0x01UL << GPIO_PORT_NOT2_NOTP21_Pos) /*!< GPIO_PORT NOT2: NOTP21 Mask */\r
-#define GPIO_PORT_NOT2_NOTP22_Pos 22 /*!< GPIO_PORT NOT2: NOTP22 Position */\r
-#define GPIO_PORT_NOT2_NOTP22_Msk (0x01UL << GPIO_PORT_NOT2_NOTP22_Pos) /*!< GPIO_PORT NOT2: NOTP22 Mask */\r
-#define GPIO_PORT_NOT2_NOTP23_Pos 23 /*!< GPIO_PORT NOT2: NOTP23 Position */\r
-#define GPIO_PORT_NOT2_NOTP23_Msk (0x01UL << GPIO_PORT_NOT2_NOTP23_Pos) /*!< GPIO_PORT NOT2: NOTP23 Mask */\r
-#define GPIO_PORT_NOT2_NOTP24_Pos 24 /*!< GPIO_PORT NOT2: NOTP24 Position */\r
-#define GPIO_PORT_NOT2_NOTP24_Msk (0x01UL << GPIO_PORT_NOT2_NOTP24_Pos) /*!< GPIO_PORT NOT2: NOTP24 Mask */\r
-#define GPIO_PORT_NOT2_NOTP25_Pos 25 /*!< GPIO_PORT NOT2: NOTP25 Position */\r
-#define GPIO_PORT_NOT2_NOTP25_Msk (0x01UL << GPIO_PORT_NOT2_NOTP25_Pos) /*!< GPIO_PORT NOT2: NOTP25 Mask */\r
-#define GPIO_PORT_NOT2_NOTP26_Pos 26 /*!< GPIO_PORT NOT2: NOTP26 Position */\r
-#define GPIO_PORT_NOT2_NOTP26_Msk (0x01UL << GPIO_PORT_NOT2_NOTP26_Pos) /*!< GPIO_PORT NOT2: NOTP26 Mask */\r
-#define GPIO_PORT_NOT2_NOTP27_Pos 27 /*!< GPIO_PORT NOT2: NOTP27 Position */\r
-#define GPIO_PORT_NOT2_NOTP27_Msk (0x01UL << GPIO_PORT_NOT2_NOTP27_Pos) /*!< GPIO_PORT NOT2: NOTP27 Mask */\r
-#define GPIO_PORT_NOT2_NOTP28_Pos 28 /*!< GPIO_PORT NOT2: NOTP28 Position */\r
-#define GPIO_PORT_NOT2_NOTP28_Msk (0x01UL << GPIO_PORT_NOT2_NOTP28_Pos) /*!< GPIO_PORT NOT2: NOTP28 Mask */\r
-#define GPIO_PORT_NOT2_NOTP29_Pos 29 /*!< GPIO_PORT NOT2: NOTP29 Position */\r
-#define GPIO_PORT_NOT2_NOTP29_Msk (0x01UL << GPIO_PORT_NOT2_NOTP29_Pos) /*!< GPIO_PORT NOT2: NOTP29 Mask */\r
-#define GPIO_PORT_NOT2_NOTP30_Pos 30 /*!< GPIO_PORT NOT2: NOTP30 Position */\r
-#define GPIO_PORT_NOT2_NOTP30_Msk (0x01UL << GPIO_PORT_NOT2_NOTP30_Pos) /*!< GPIO_PORT NOT2: NOTP30 Mask */\r
-#define GPIO_PORT_NOT2_NOTP31_Pos 31 /*!< GPIO_PORT NOT2: NOTP31 Position */\r
-#define GPIO_PORT_NOT2_NOTP31_Msk (0x01UL << GPIO_PORT_NOT2_NOTP31_Pos) /*!< GPIO_PORT NOT2: NOTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_NOT3 -----------------------------------------\r
-#define GPIO_PORT_NOT3_NOTP0_Pos 0 /*!< GPIO_PORT NOT3: NOTP0 Position */\r
-#define GPIO_PORT_NOT3_NOTP0_Msk (0x01UL << GPIO_PORT_NOT3_NOTP0_Pos) /*!< GPIO_PORT NOT3: NOTP0 Mask */\r
-#define GPIO_PORT_NOT3_NOTP1_Pos 1 /*!< GPIO_PORT NOT3: NOTP1 Position */\r
-#define GPIO_PORT_NOT3_NOTP1_Msk (0x01UL << GPIO_PORT_NOT3_NOTP1_Pos) /*!< GPIO_PORT NOT3: NOTP1 Mask */\r
-#define GPIO_PORT_NOT3_NOTP2_Pos 2 /*!< GPIO_PORT NOT3: NOTP2 Position */\r
-#define GPIO_PORT_NOT3_NOTP2_Msk (0x01UL << GPIO_PORT_NOT3_NOTP2_Pos) /*!< GPIO_PORT NOT3: NOTP2 Mask */\r
-#define GPIO_PORT_NOT3_NOTP3_Pos 3 /*!< GPIO_PORT NOT3: NOTP3 Position */\r
-#define GPIO_PORT_NOT3_NOTP3_Msk (0x01UL << GPIO_PORT_NOT3_NOTP3_Pos) /*!< GPIO_PORT NOT3: NOTP3 Mask */\r
-#define GPIO_PORT_NOT3_NOTP4_Pos 4 /*!< GPIO_PORT NOT3: NOTP4 Position */\r
-#define GPIO_PORT_NOT3_NOTP4_Msk (0x01UL << GPIO_PORT_NOT3_NOTP4_Pos) /*!< GPIO_PORT NOT3: NOTP4 Mask */\r
-#define GPIO_PORT_NOT3_NOTP5_Pos 5 /*!< GPIO_PORT NOT3: NOTP5 Position */\r
-#define GPIO_PORT_NOT3_NOTP5_Msk (0x01UL << GPIO_PORT_NOT3_NOTP5_Pos) /*!< GPIO_PORT NOT3: NOTP5 Mask */\r
-#define GPIO_PORT_NOT3_NOTP6_Pos 6 /*!< GPIO_PORT NOT3: NOTP6 Position */\r
-#define GPIO_PORT_NOT3_NOTP6_Msk (0x01UL << GPIO_PORT_NOT3_NOTP6_Pos) /*!< GPIO_PORT NOT3: NOTP6 Mask */\r
-#define GPIO_PORT_NOT3_NOTP7_Pos 7 /*!< GPIO_PORT NOT3: NOTP7 Position */\r
-#define GPIO_PORT_NOT3_NOTP7_Msk (0x01UL << GPIO_PORT_NOT3_NOTP7_Pos) /*!< GPIO_PORT NOT3: NOTP7 Mask */\r
-#define GPIO_PORT_NOT3_NOTP8_Pos 8 /*!< GPIO_PORT NOT3: NOTP8 Position */\r
-#define GPIO_PORT_NOT3_NOTP8_Msk (0x01UL << GPIO_PORT_NOT3_NOTP8_Pos) /*!< GPIO_PORT NOT3: NOTP8 Mask */\r
-#define GPIO_PORT_NOT3_NOTP9_Pos 9 /*!< GPIO_PORT NOT3: NOTP9 Position */\r
-#define GPIO_PORT_NOT3_NOTP9_Msk (0x01UL << GPIO_PORT_NOT3_NOTP9_Pos) /*!< GPIO_PORT NOT3: NOTP9 Mask */\r
-#define GPIO_PORT_NOT3_NOTP10_Pos 10 /*!< GPIO_PORT NOT3: NOTP10 Position */\r
-#define GPIO_PORT_NOT3_NOTP10_Msk (0x01UL << GPIO_PORT_NOT3_NOTP10_Pos) /*!< GPIO_PORT NOT3: NOTP10 Mask */\r
-#define GPIO_PORT_NOT3_NOTP11_Pos 11 /*!< GPIO_PORT NOT3: NOTP11 Position */\r
-#define GPIO_PORT_NOT3_NOTP11_Msk (0x01UL << GPIO_PORT_NOT3_NOTP11_Pos) /*!< GPIO_PORT NOT3: NOTP11 Mask */\r
-#define GPIO_PORT_NOT3_NOTP12_Pos 12 /*!< GPIO_PORT NOT3: NOTP12 Position */\r
-#define GPIO_PORT_NOT3_NOTP12_Msk (0x01UL << GPIO_PORT_NOT3_NOTP12_Pos) /*!< GPIO_PORT NOT3: NOTP12 Mask */\r
-#define GPIO_PORT_NOT3_NOTP13_Pos 13 /*!< GPIO_PORT NOT3: NOTP13 Position */\r
-#define GPIO_PORT_NOT3_NOTP13_Msk (0x01UL << GPIO_PORT_NOT3_NOTP13_Pos) /*!< GPIO_PORT NOT3: NOTP13 Mask */\r
-#define GPIO_PORT_NOT3_NOTP14_Pos 14 /*!< GPIO_PORT NOT3: NOTP14 Position */\r
-#define GPIO_PORT_NOT3_NOTP14_Msk (0x01UL << GPIO_PORT_NOT3_NOTP14_Pos) /*!< GPIO_PORT NOT3: NOTP14 Mask */\r
-#define GPIO_PORT_NOT3_NOTP15_Pos 15 /*!< GPIO_PORT NOT3: NOTP15 Position */\r
-#define GPIO_PORT_NOT3_NOTP15_Msk (0x01UL << GPIO_PORT_NOT3_NOTP15_Pos) /*!< GPIO_PORT NOT3: NOTP15 Mask */\r
-#define GPIO_PORT_NOT3_NOTP16_Pos 16 /*!< GPIO_PORT NOT3: NOTP16 Position */\r
-#define GPIO_PORT_NOT3_NOTP16_Msk (0x01UL << GPIO_PORT_NOT3_NOTP16_Pos) /*!< GPIO_PORT NOT3: NOTP16 Mask */\r
-#define GPIO_PORT_NOT3_NOTP17_Pos 17 /*!< GPIO_PORT NOT3: NOTP17 Position */\r
-#define GPIO_PORT_NOT3_NOTP17_Msk (0x01UL << GPIO_PORT_NOT3_NOTP17_Pos) /*!< GPIO_PORT NOT3: NOTP17 Mask */\r
-#define GPIO_PORT_NOT3_NOTP18_Pos 18 /*!< GPIO_PORT NOT3: NOTP18 Position */\r
-#define GPIO_PORT_NOT3_NOTP18_Msk (0x01UL << GPIO_PORT_NOT3_NOTP18_Pos) /*!< GPIO_PORT NOT3: NOTP18 Mask */\r
-#define GPIO_PORT_NOT3_NOTP19_Pos 19 /*!< GPIO_PORT NOT3: NOTP19 Position */\r
-#define GPIO_PORT_NOT3_NOTP19_Msk (0x01UL << GPIO_PORT_NOT3_NOTP19_Pos) /*!< GPIO_PORT NOT3: NOTP19 Mask */\r
-#define GPIO_PORT_NOT3_NOTP20_Pos 20 /*!< GPIO_PORT NOT3: NOTP20 Position */\r
-#define GPIO_PORT_NOT3_NOTP20_Msk (0x01UL << GPIO_PORT_NOT3_NOTP20_Pos) /*!< GPIO_PORT NOT3: NOTP20 Mask */\r
-#define GPIO_PORT_NOT3_NOTP21_Pos 21 /*!< GPIO_PORT NOT3: NOTP21 Position */\r
-#define GPIO_PORT_NOT3_NOTP21_Msk (0x01UL << GPIO_PORT_NOT3_NOTP21_Pos) /*!< GPIO_PORT NOT3: NOTP21 Mask */\r
-#define GPIO_PORT_NOT3_NOTP22_Pos 22 /*!< GPIO_PORT NOT3: NOTP22 Position */\r
-#define GPIO_PORT_NOT3_NOTP22_Msk (0x01UL << GPIO_PORT_NOT3_NOTP22_Pos) /*!< GPIO_PORT NOT3: NOTP22 Mask */\r
-#define GPIO_PORT_NOT3_NOTP23_Pos 23 /*!< GPIO_PORT NOT3: NOTP23 Position */\r
-#define GPIO_PORT_NOT3_NOTP23_Msk (0x01UL << GPIO_PORT_NOT3_NOTP23_Pos) /*!< GPIO_PORT NOT3: NOTP23 Mask */\r
-#define GPIO_PORT_NOT3_NOTP24_Pos 24 /*!< GPIO_PORT NOT3: NOTP24 Position */\r
-#define GPIO_PORT_NOT3_NOTP24_Msk (0x01UL << GPIO_PORT_NOT3_NOTP24_Pos) /*!< GPIO_PORT NOT3: NOTP24 Mask */\r
-#define GPIO_PORT_NOT3_NOTP25_Pos 25 /*!< GPIO_PORT NOT3: NOTP25 Position */\r
-#define GPIO_PORT_NOT3_NOTP25_Msk (0x01UL << GPIO_PORT_NOT3_NOTP25_Pos) /*!< GPIO_PORT NOT3: NOTP25 Mask */\r
-#define GPIO_PORT_NOT3_NOTP26_Pos 26 /*!< GPIO_PORT NOT3: NOTP26 Position */\r
-#define GPIO_PORT_NOT3_NOTP26_Msk (0x01UL << GPIO_PORT_NOT3_NOTP26_Pos) /*!< GPIO_PORT NOT3: NOTP26 Mask */\r
-#define GPIO_PORT_NOT3_NOTP27_Pos 27 /*!< GPIO_PORT NOT3: NOTP27 Position */\r
-#define GPIO_PORT_NOT3_NOTP27_Msk (0x01UL << GPIO_PORT_NOT3_NOTP27_Pos) /*!< GPIO_PORT NOT3: NOTP27 Mask */\r
-#define GPIO_PORT_NOT3_NOTP28_Pos 28 /*!< GPIO_PORT NOT3: NOTP28 Position */\r
-#define GPIO_PORT_NOT3_NOTP28_Msk (0x01UL << GPIO_PORT_NOT3_NOTP28_Pos) /*!< GPIO_PORT NOT3: NOTP28 Mask */\r
-#define GPIO_PORT_NOT3_NOTP29_Pos 29 /*!< GPIO_PORT NOT3: NOTP29 Position */\r
-#define GPIO_PORT_NOT3_NOTP29_Msk (0x01UL << GPIO_PORT_NOT3_NOTP29_Pos) /*!< GPIO_PORT NOT3: NOTP29 Mask */\r
-#define GPIO_PORT_NOT3_NOTP30_Pos 30 /*!< GPIO_PORT NOT3: NOTP30 Position */\r
-#define GPIO_PORT_NOT3_NOTP30_Msk (0x01UL << GPIO_PORT_NOT3_NOTP30_Pos) /*!< GPIO_PORT NOT3: NOTP30 Mask */\r
-#define GPIO_PORT_NOT3_NOTP31_Pos 31 /*!< GPIO_PORT NOT3: NOTP31 Position */\r
-#define GPIO_PORT_NOT3_NOTP31_Msk (0x01UL << GPIO_PORT_NOT3_NOTP31_Pos) /*!< GPIO_PORT NOT3: NOTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_NOT4 -----------------------------------------\r
-#define GPIO_PORT_NOT4_NOTP0_Pos 0 /*!< GPIO_PORT NOT4: NOTP0 Position */\r
-#define GPIO_PORT_NOT4_NOTP0_Msk (0x01UL << GPIO_PORT_NOT4_NOTP0_Pos) /*!< GPIO_PORT NOT4: NOTP0 Mask */\r
-#define GPIO_PORT_NOT4_NOTP1_Pos 1 /*!< GPIO_PORT NOT4: NOTP1 Position */\r
-#define GPIO_PORT_NOT4_NOTP1_Msk (0x01UL << GPIO_PORT_NOT4_NOTP1_Pos) /*!< GPIO_PORT NOT4: NOTP1 Mask */\r
-#define GPIO_PORT_NOT4_NOTP2_Pos 2 /*!< GPIO_PORT NOT4: NOTP2 Position */\r
-#define GPIO_PORT_NOT4_NOTP2_Msk (0x01UL << GPIO_PORT_NOT4_NOTP2_Pos) /*!< GPIO_PORT NOT4: NOTP2 Mask */\r
-#define GPIO_PORT_NOT4_NOTP3_Pos 3 /*!< GPIO_PORT NOT4: NOTP3 Position */\r
-#define GPIO_PORT_NOT4_NOTP3_Msk (0x01UL << GPIO_PORT_NOT4_NOTP3_Pos) /*!< GPIO_PORT NOT4: NOTP3 Mask */\r
-#define GPIO_PORT_NOT4_NOTP4_Pos 4 /*!< GPIO_PORT NOT4: NOTP4 Position */\r
-#define GPIO_PORT_NOT4_NOTP4_Msk (0x01UL << GPIO_PORT_NOT4_NOTP4_Pos) /*!< GPIO_PORT NOT4: NOTP4 Mask */\r
-#define GPIO_PORT_NOT4_NOTP5_Pos 5 /*!< GPIO_PORT NOT4: NOTP5 Position */\r
-#define GPIO_PORT_NOT4_NOTP5_Msk (0x01UL << GPIO_PORT_NOT4_NOTP5_Pos) /*!< GPIO_PORT NOT4: NOTP5 Mask */\r
-#define GPIO_PORT_NOT4_NOTP6_Pos 6 /*!< GPIO_PORT NOT4: NOTP6 Position */\r
-#define GPIO_PORT_NOT4_NOTP6_Msk (0x01UL << GPIO_PORT_NOT4_NOTP6_Pos) /*!< GPIO_PORT NOT4: NOTP6 Mask */\r
-#define GPIO_PORT_NOT4_NOTP7_Pos 7 /*!< GPIO_PORT NOT4: NOTP7 Position */\r
-#define GPIO_PORT_NOT4_NOTP7_Msk (0x01UL << GPIO_PORT_NOT4_NOTP7_Pos) /*!< GPIO_PORT NOT4: NOTP7 Mask */\r
-#define GPIO_PORT_NOT4_NOTP8_Pos 8 /*!< GPIO_PORT NOT4: NOTP8 Position */\r
-#define GPIO_PORT_NOT4_NOTP8_Msk (0x01UL << GPIO_PORT_NOT4_NOTP8_Pos) /*!< GPIO_PORT NOT4: NOTP8 Mask */\r
-#define GPIO_PORT_NOT4_NOTP9_Pos 9 /*!< GPIO_PORT NOT4: NOTP9 Position */\r
-#define GPIO_PORT_NOT4_NOTP9_Msk (0x01UL << GPIO_PORT_NOT4_NOTP9_Pos) /*!< GPIO_PORT NOT4: NOTP9 Mask */\r
-#define GPIO_PORT_NOT4_NOTP10_Pos 10 /*!< GPIO_PORT NOT4: NOTP10 Position */\r
-#define GPIO_PORT_NOT4_NOTP10_Msk (0x01UL << GPIO_PORT_NOT4_NOTP10_Pos) /*!< GPIO_PORT NOT4: NOTP10 Mask */\r
-#define GPIO_PORT_NOT4_NOTP11_Pos 11 /*!< GPIO_PORT NOT4: NOTP11 Position */\r
-#define GPIO_PORT_NOT4_NOTP11_Msk (0x01UL << GPIO_PORT_NOT4_NOTP11_Pos) /*!< GPIO_PORT NOT4: NOTP11 Mask */\r
-#define GPIO_PORT_NOT4_NOTP12_Pos 12 /*!< GPIO_PORT NOT4: NOTP12 Position */\r
-#define GPIO_PORT_NOT4_NOTP12_Msk (0x01UL << GPIO_PORT_NOT4_NOTP12_Pos) /*!< GPIO_PORT NOT4: NOTP12 Mask */\r
-#define GPIO_PORT_NOT4_NOTP13_Pos 13 /*!< GPIO_PORT NOT4: NOTP13 Position */\r
-#define GPIO_PORT_NOT4_NOTP13_Msk (0x01UL << GPIO_PORT_NOT4_NOTP13_Pos) /*!< GPIO_PORT NOT4: NOTP13 Mask */\r
-#define GPIO_PORT_NOT4_NOTP14_Pos 14 /*!< GPIO_PORT NOT4: NOTP14 Position */\r
-#define GPIO_PORT_NOT4_NOTP14_Msk (0x01UL << GPIO_PORT_NOT4_NOTP14_Pos) /*!< GPIO_PORT NOT4: NOTP14 Mask */\r
-#define GPIO_PORT_NOT4_NOTP15_Pos 15 /*!< GPIO_PORT NOT4: NOTP15 Position */\r
-#define GPIO_PORT_NOT4_NOTP15_Msk (0x01UL << GPIO_PORT_NOT4_NOTP15_Pos) /*!< GPIO_PORT NOT4: NOTP15 Mask */\r
-#define GPIO_PORT_NOT4_NOTP16_Pos 16 /*!< GPIO_PORT NOT4: NOTP16 Position */\r
-#define GPIO_PORT_NOT4_NOTP16_Msk (0x01UL << GPIO_PORT_NOT4_NOTP16_Pos) /*!< GPIO_PORT NOT4: NOTP16 Mask */\r
-#define GPIO_PORT_NOT4_NOTP17_Pos 17 /*!< GPIO_PORT NOT4: NOTP17 Position */\r
-#define GPIO_PORT_NOT4_NOTP17_Msk (0x01UL << GPIO_PORT_NOT4_NOTP17_Pos) /*!< GPIO_PORT NOT4: NOTP17 Mask */\r
-#define GPIO_PORT_NOT4_NOTP18_Pos 18 /*!< GPIO_PORT NOT4: NOTP18 Position */\r
-#define GPIO_PORT_NOT4_NOTP18_Msk (0x01UL << GPIO_PORT_NOT4_NOTP18_Pos) /*!< GPIO_PORT NOT4: NOTP18 Mask */\r
-#define GPIO_PORT_NOT4_NOTP19_Pos 19 /*!< GPIO_PORT NOT4: NOTP19 Position */\r
-#define GPIO_PORT_NOT4_NOTP19_Msk (0x01UL << GPIO_PORT_NOT4_NOTP19_Pos) /*!< GPIO_PORT NOT4: NOTP19 Mask */\r
-#define GPIO_PORT_NOT4_NOTP20_Pos 20 /*!< GPIO_PORT NOT4: NOTP20 Position */\r
-#define GPIO_PORT_NOT4_NOTP20_Msk (0x01UL << GPIO_PORT_NOT4_NOTP20_Pos) /*!< GPIO_PORT NOT4: NOTP20 Mask */\r
-#define GPIO_PORT_NOT4_NOTP21_Pos 21 /*!< GPIO_PORT NOT4: NOTP21 Position */\r
-#define GPIO_PORT_NOT4_NOTP21_Msk (0x01UL << GPIO_PORT_NOT4_NOTP21_Pos) /*!< GPIO_PORT NOT4: NOTP21 Mask */\r
-#define GPIO_PORT_NOT4_NOTP22_Pos 22 /*!< GPIO_PORT NOT4: NOTP22 Position */\r
-#define GPIO_PORT_NOT4_NOTP22_Msk (0x01UL << GPIO_PORT_NOT4_NOTP22_Pos) /*!< GPIO_PORT NOT4: NOTP22 Mask */\r
-#define GPIO_PORT_NOT4_NOTP23_Pos 23 /*!< GPIO_PORT NOT4: NOTP23 Position */\r
-#define GPIO_PORT_NOT4_NOTP23_Msk (0x01UL << GPIO_PORT_NOT4_NOTP23_Pos) /*!< GPIO_PORT NOT4: NOTP23 Mask */\r
-#define GPIO_PORT_NOT4_NOTP24_Pos 24 /*!< GPIO_PORT NOT4: NOTP24 Position */\r
-#define GPIO_PORT_NOT4_NOTP24_Msk (0x01UL << GPIO_PORT_NOT4_NOTP24_Pos) /*!< GPIO_PORT NOT4: NOTP24 Mask */\r
-#define GPIO_PORT_NOT4_NOTP25_Pos 25 /*!< GPIO_PORT NOT4: NOTP25 Position */\r
-#define GPIO_PORT_NOT4_NOTP25_Msk (0x01UL << GPIO_PORT_NOT4_NOTP25_Pos) /*!< GPIO_PORT NOT4: NOTP25 Mask */\r
-#define GPIO_PORT_NOT4_NOTP26_Pos 26 /*!< GPIO_PORT NOT4: NOTP26 Position */\r
-#define GPIO_PORT_NOT4_NOTP26_Msk (0x01UL << GPIO_PORT_NOT4_NOTP26_Pos) /*!< GPIO_PORT NOT4: NOTP26 Mask */\r
-#define GPIO_PORT_NOT4_NOTP27_Pos 27 /*!< GPIO_PORT NOT4: NOTP27 Position */\r
-#define GPIO_PORT_NOT4_NOTP27_Msk (0x01UL << GPIO_PORT_NOT4_NOTP27_Pos) /*!< GPIO_PORT NOT4: NOTP27 Mask */\r
-#define GPIO_PORT_NOT4_NOTP28_Pos 28 /*!< GPIO_PORT NOT4: NOTP28 Position */\r
-#define GPIO_PORT_NOT4_NOTP28_Msk (0x01UL << GPIO_PORT_NOT4_NOTP28_Pos) /*!< GPIO_PORT NOT4: NOTP28 Mask */\r
-#define GPIO_PORT_NOT4_NOTP29_Pos 29 /*!< GPIO_PORT NOT4: NOTP29 Position */\r
-#define GPIO_PORT_NOT4_NOTP29_Msk (0x01UL << GPIO_PORT_NOT4_NOTP29_Pos) /*!< GPIO_PORT NOT4: NOTP29 Mask */\r
-#define GPIO_PORT_NOT4_NOTP30_Pos 30 /*!< GPIO_PORT NOT4: NOTP30 Position */\r
-#define GPIO_PORT_NOT4_NOTP30_Msk (0x01UL << GPIO_PORT_NOT4_NOTP30_Pos) /*!< GPIO_PORT NOT4: NOTP30 Mask */\r
-#define GPIO_PORT_NOT4_NOTP31_Pos 31 /*!< GPIO_PORT NOT4: NOTP31 Position */\r
-#define GPIO_PORT_NOT4_NOTP31_Msk (0x01UL << GPIO_PORT_NOT4_NOTP31_Pos) /*!< GPIO_PORT NOT4: NOTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_NOT5 -----------------------------------------\r
-#define GPIO_PORT_NOT5_NOTP0_Pos 0 /*!< GPIO_PORT NOT5: NOTP0 Position */\r
-#define GPIO_PORT_NOT5_NOTP0_Msk (0x01UL << GPIO_PORT_NOT5_NOTP0_Pos) /*!< GPIO_PORT NOT5: NOTP0 Mask */\r
-#define GPIO_PORT_NOT5_NOTP1_Pos 1 /*!< GPIO_PORT NOT5: NOTP1 Position */\r
-#define GPIO_PORT_NOT5_NOTP1_Msk (0x01UL << GPIO_PORT_NOT5_NOTP1_Pos) /*!< GPIO_PORT NOT5: NOTP1 Mask */\r
-#define GPIO_PORT_NOT5_NOTP2_Pos 2 /*!< GPIO_PORT NOT5: NOTP2 Position */\r
-#define GPIO_PORT_NOT5_NOTP2_Msk (0x01UL << GPIO_PORT_NOT5_NOTP2_Pos) /*!< GPIO_PORT NOT5: NOTP2 Mask */\r
-#define GPIO_PORT_NOT5_NOTP3_Pos 3 /*!< GPIO_PORT NOT5: NOTP3 Position */\r
-#define GPIO_PORT_NOT5_NOTP3_Msk (0x01UL << GPIO_PORT_NOT5_NOTP3_Pos) /*!< GPIO_PORT NOT5: NOTP3 Mask */\r
-#define GPIO_PORT_NOT5_NOTP4_Pos 4 /*!< GPIO_PORT NOT5: NOTP4 Position */\r
-#define GPIO_PORT_NOT5_NOTP4_Msk (0x01UL << GPIO_PORT_NOT5_NOTP4_Pos) /*!< GPIO_PORT NOT5: NOTP4 Mask */\r
-#define GPIO_PORT_NOT5_NOTP5_Pos 5 /*!< GPIO_PORT NOT5: NOTP5 Position */\r
-#define GPIO_PORT_NOT5_NOTP5_Msk (0x01UL << GPIO_PORT_NOT5_NOTP5_Pos) /*!< GPIO_PORT NOT5: NOTP5 Mask */\r
-#define GPIO_PORT_NOT5_NOTP6_Pos 6 /*!< GPIO_PORT NOT5: NOTP6 Position */\r
-#define GPIO_PORT_NOT5_NOTP6_Msk (0x01UL << GPIO_PORT_NOT5_NOTP6_Pos) /*!< GPIO_PORT NOT5: NOTP6 Mask */\r
-#define GPIO_PORT_NOT5_NOTP7_Pos 7 /*!< GPIO_PORT NOT5: NOTP7 Position */\r
-#define GPIO_PORT_NOT5_NOTP7_Msk (0x01UL << GPIO_PORT_NOT5_NOTP7_Pos) /*!< GPIO_PORT NOT5: NOTP7 Mask */\r
-#define GPIO_PORT_NOT5_NOTP8_Pos 8 /*!< GPIO_PORT NOT5: NOTP8 Position */\r
-#define GPIO_PORT_NOT5_NOTP8_Msk (0x01UL << GPIO_PORT_NOT5_NOTP8_Pos) /*!< GPIO_PORT NOT5: NOTP8 Mask */\r
-#define GPIO_PORT_NOT5_NOTP9_Pos 9 /*!< GPIO_PORT NOT5: NOTP9 Position */\r
-#define GPIO_PORT_NOT5_NOTP9_Msk (0x01UL << GPIO_PORT_NOT5_NOTP9_Pos) /*!< GPIO_PORT NOT5: NOTP9 Mask */\r
-#define GPIO_PORT_NOT5_NOTP10_Pos 10 /*!< GPIO_PORT NOT5: NOTP10 Position */\r
-#define GPIO_PORT_NOT5_NOTP10_Msk (0x01UL << GPIO_PORT_NOT5_NOTP10_Pos) /*!< GPIO_PORT NOT5: NOTP10 Mask */\r
-#define GPIO_PORT_NOT5_NOTP11_Pos 11 /*!< GPIO_PORT NOT5: NOTP11 Position */\r
-#define GPIO_PORT_NOT5_NOTP11_Msk (0x01UL << GPIO_PORT_NOT5_NOTP11_Pos) /*!< GPIO_PORT NOT5: NOTP11 Mask */\r
-#define GPIO_PORT_NOT5_NOTP12_Pos 12 /*!< GPIO_PORT NOT5: NOTP12 Position */\r
-#define GPIO_PORT_NOT5_NOTP12_Msk (0x01UL << GPIO_PORT_NOT5_NOTP12_Pos) /*!< GPIO_PORT NOT5: NOTP12 Mask */\r
-#define GPIO_PORT_NOT5_NOTP13_Pos 13 /*!< GPIO_PORT NOT5: NOTP13 Position */\r
-#define GPIO_PORT_NOT5_NOTP13_Msk (0x01UL << GPIO_PORT_NOT5_NOTP13_Pos) /*!< GPIO_PORT NOT5: NOTP13 Mask */\r
-#define GPIO_PORT_NOT5_NOTP14_Pos 14 /*!< GPIO_PORT NOT5: NOTP14 Position */\r
-#define GPIO_PORT_NOT5_NOTP14_Msk (0x01UL << GPIO_PORT_NOT5_NOTP14_Pos) /*!< GPIO_PORT NOT5: NOTP14 Mask */\r
-#define GPIO_PORT_NOT5_NOTP15_Pos 15 /*!< GPIO_PORT NOT5: NOTP15 Position */\r
-#define GPIO_PORT_NOT5_NOTP15_Msk (0x01UL << GPIO_PORT_NOT5_NOTP15_Pos) /*!< GPIO_PORT NOT5: NOTP15 Mask */\r
-#define GPIO_PORT_NOT5_NOTP16_Pos 16 /*!< GPIO_PORT NOT5: NOTP16 Position */\r
-#define GPIO_PORT_NOT5_NOTP16_Msk (0x01UL << GPIO_PORT_NOT5_NOTP16_Pos) /*!< GPIO_PORT NOT5: NOTP16 Mask */\r
-#define GPIO_PORT_NOT5_NOTP17_Pos 17 /*!< GPIO_PORT NOT5: NOTP17 Position */\r
-#define GPIO_PORT_NOT5_NOTP17_Msk (0x01UL << GPIO_PORT_NOT5_NOTP17_Pos) /*!< GPIO_PORT NOT5: NOTP17 Mask */\r
-#define GPIO_PORT_NOT5_NOTP18_Pos 18 /*!< GPIO_PORT NOT5: NOTP18 Position */\r
-#define GPIO_PORT_NOT5_NOTP18_Msk (0x01UL << GPIO_PORT_NOT5_NOTP18_Pos) /*!< GPIO_PORT NOT5: NOTP18 Mask */\r
-#define GPIO_PORT_NOT5_NOTP19_Pos 19 /*!< GPIO_PORT NOT5: NOTP19 Position */\r
-#define GPIO_PORT_NOT5_NOTP19_Msk (0x01UL << GPIO_PORT_NOT5_NOTP19_Pos) /*!< GPIO_PORT NOT5: NOTP19 Mask */\r
-#define GPIO_PORT_NOT5_NOTP20_Pos 20 /*!< GPIO_PORT NOT5: NOTP20 Position */\r
-#define GPIO_PORT_NOT5_NOTP20_Msk (0x01UL << GPIO_PORT_NOT5_NOTP20_Pos) /*!< GPIO_PORT NOT5: NOTP20 Mask */\r
-#define GPIO_PORT_NOT5_NOTP21_Pos 21 /*!< GPIO_PORT NOT5: NOTP21 Position */\r
-#define GPIO_PORT_NOT5_NOTP21_Msk (0x01UL << GPIO_PORT_NOT5_NOTP21_Pos) /*!< GPIO_PORT NOT5: NOTP21 Mask */\r
-#define GPIO_PORT_NOT5_NOTP22_Pos 22 /*!< GPIO_PORT NOT5: NOTP22 Position */\r
-#define GPIO_PORT_NOT5_NOTP22_Msk (0x01UL << GPIO_PORT_NOT5_NOTP22_Pos) /*!< GPIO_PORT NOT5: NOTP22 Mask */\r
-#define GPIO_PORT_NOT5_NOTP23_Pos 23 /*!< GPIO_PORT NOT5: NOTP23 Position */\r
-#define GPIO_PORT_NOT5_NOTP23_Msk (0x01UL << GPIO_PORT_NOT5_NOTP23_Pos) /*!< GPIO_PORT NOT5: NOTP23 Mask */\r
-#define GPIO_PORT_NOT5_NOTP24_Pos 24 /*!< GPIO_PORT NOT5: NOTP24 Position */\r
-#define GPIO_PORT_NOT5_NOTP24_Msk (0x01UL << GPIO_PORT_NOT5_NOTP24_Pos) /*!< GPIO_PORT NOT5: NOTP24 Mask */\r
-#define GPIO_PORT_NOT5_NOTP25_Pos 25 /*!< GPIO_PORT NOT5: NOTP25 Position */\r
-#define GPIO_PORT_NOT5_NOTP25_Msk (0x01UL << GPIO_PORT_NOT5_NOTP25_Pos) /*!< GPIO_PORT NOT5: NOTP25 Mask */\r
-#define GPIO_PORT_NOT5_NOTP26_Pos 26 /*!< GPIO_PORT NOT5: NOTP26 Position */\r
-#define GPIO_PORT_NOT5_NOTP26_Msk (0x01UL << GPIO_PORT_NOT5_NOTP26_Pos) /*!< GPIO_PORT NOT5: NOTP26 Mask */\r
-#define GPIO_PORT_NOT5_NOTP27_Pos 27 /*!< GPIO_PORT NOT5: NOTP27 Position */\r
-#define GPIO_PORT_NOT5_NOTP27_Msk (0x01UL << GPIO_PORT_NOT5_NOTP27_Pos) /*!< GPIO_PORT NOT5: NOTP27 Mask */\r
-#define GPIO_PORT_NOT5_NOTP28_Pos 28 /*!< GPIO_PORT NOT5: NOTP28 Position */\r
-#define GPIO_PORT_NOT5_NOTP28_Msk (0x01UL << GPIO_PORT_NOT5_NOTP28_Pos) /*!< GPIO_PORT NOT5: NOTP28 Mask */\r
-#define GPIO_PORT_NOT5_NOTP29_Pos 29 /*!< GPIO_PORT NOT5: NOTP29 Position */\r
-#define GPIO_PORT_NOT5_NOTP29_Msk (0x01UL << GPIO_PORT_NOT5_NOTP29_Pos) /*!< GPIO_PORT NOT5: NOTP29 Mask */\r
-#define GPIO_PORT_NOT5_NOTP30_Pos 30 /*!< GPIO_PORT NOT5: NOTP30 Position */\r
-#define GPIO_PORT_NOT5_NOTP30_Msk (0x01UL << GPIO_PORT_NOT5_NOTP30_Pos) /*!< GPIO_PORT NOT5: NOTP30 Mask */\r
-#define GPIO_PORT_NOT5_NOTP31_Pos 31 /*!< GPIO_PORT NOT5: NOTP31 Position */\r
-#define GPIO_PORT_NOT5_NOTP31_Msk (0x01UL << GPIO_PORT_NOT5_NOTP31_Pos) /*!< GPIO_PORT NOT5: NOTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_NOT6 -----------------------------------------\r
-#define GPIO_PORT_NOT6_NOTP0_Pos 0 /*!< GPIO_PORT NOT6: NOTP0 Position */\r
-#define GPIO_PORT_NOT6_NOTP0_Msk (0x01UL << GPIO_PORT_NOT6_NOTP0_Pos) /*!< GPIO_PORT NOT6: NOTP0 Mask */\r
-#define GPIO_PORT_NOT6_NOTP1_Pos 1 /*!< GPIO_PORT NOT6: NOTP1 Position */\r
-#define GPIO_PORT_NOT6_NOTP1_Msk (0x01UL << GPIO_PORT_NOT6_NOTP1_Pos) /*!< GPIO_PORT NOT6: NOTP1 Mask */\r
-#define GPIO_PORT_NOT6_NOTP2_Pos 2 /*!< GPIO_PORT NOT6: NOTP2 Position */\r
-#define GPIO_PORT_NOT6_NOTP2_Msk (0x01UL << GPIO_PORT_NOT6_NOTP2_Pos) /*!< GPIO_PORT NOT6: NOTP2 Mask */\r
-#define GPIO_PORT_NOT6_NOTP3_Pos 3 /*!< GPIO_PORT NOT6: NOTP3 Position */\r
-#define GPIO_PORT_NOT6_NOTP3_Msk (0x01UL << GPIO_PORT_NOT6_NOTP3_Pos) /*!< GPIO_PORT NOT6: NOTP3 Mask */\r
-#define GPIO_PORT_NOT6_NOTP4_Pos 4 /*!< GPIO_PORT NOT6: NOTP4 Position */\r
-#define GPIO_PORT_NOT6_NOTP4_Msk (0x01UL << GPIO_PORT_NOT6_NOTP4_Pos) /*!< GPIO_PORT NOT6: NOTP4 Mask */\r
-#define GPIO_PORT_NOT6_NOTP5_Pos 5 /*!< GPIO_PORT NOT6: NOTP5 Position */\r
-#define GPIO_PORT_NOT6_NOTP5_Msk (0x01UL << GPIO_PORT_NOT6_NOTP5_Pos) /*!< GPIO_PORT NOT6: NOTP5 Mask */\r
-#define GPIO_PORT_NOT6_NOTP6_Pos 6 /*!< GPIO_PORT NOT6: NOTP6 Position */\r
-#define GPIO_PORT_NOT6_NOTP6_Msk (0x01UL << GPIO_PORT_NOT6_NOTP6_Pos) /*!< GPIO_PORT NOT6: NOTP6 Mask */\r
-#define GPIO_PORT_NOT6_NOTP7_Pos 7 /*!< GPIO_PORT NOT6: NOTP7 Position */\r
-#define GPIO_PORT_NOT6_NOTP7_Msk (0x01UL << GPIO_PORT_NOT6_NOTP7_Pos) /*!< GPIO_PORT NOT6: NOTP7 Mask */\r
-#define GPIO_PORT_NOT6_NOTP8_Pos 8 /*!< GPIO_PORT NOT6: NOTP8 Position */\r
-#define GPIO_PORT_NOT6_NOTP8_Msk (0x01UL << GPIO_PORT_NOT6_NOTP8_Pos) /*!< GPIO_PORT NOT6: NOTP8 Mask */\r
-#define GPIO_PORT_NOT6_NOTP9_Pos 9 /*!< GPIO_PORT NOT6: NOTP9 Position */\r
-#define GPIO_PORT_NOT6_NOTP9_Msk (0x01UL << GPIO_PORT_NOT6_NOTP9_Pos) /*!< GPIO_PORT NOT6: NOTP9 Mask */\r
-#define GPIO_PORT_NOT6_NOTP10_Pos 10 /*!< GPIO_PORT NOT6: NOTP10 Position */\r
-#define GPIO_PORT_NOT6_NOTP10_Msk (0x01UL << GPIO_PORT_NOT6_NOTP10_Pos) /*!< GPIO_PORT NOT6: NOTP10 Mask */\r
-#define GPIO_PORT_NOT6_NOTP11_Pos 11 /*!< GPIO_PORT NOT6: NOTP11 Position */\r
-#define GPIO_PORT_NOT6_NOTP11_Msk (0x01UL << GPIO_PORT_NOT6_NOTP11_Pos) /*!< GPIO_PORT NOT6: NOTP11 Mask */\r
-#define GPIO_PORT_NOT6_NOTP12_Pos 12 /*!< GPIO_PORT NOT6: NOTP12 Position */\r
-#define GPIO_PORT_NOT6_NOTP12_Msk (0x01UL << GPIO_PORT_NOT6_NOTP12_Pos) /*!< GPIO_PORT NOT6: NOTP12 Mask */\r
-#define GPIO_PORT_NOT6_NOTP13_Pos 13 /*!< GPIO_PORT NOT6: NOTP13 Position */\r
-#define GPIO_PORT_NOT6_NOTP13_Msk (0x01UL << GPIO_PORT_NOT6_NOTP13_Pos) /*!< GPIO_PORT NOT6: NOTP13 Mask */\r
-#define GPIO_PORT_NOT6_NOTP14_Pos 14 /*!< GPIO_PORT NOT6: NOTP14 Position */\r
-#define GPIO_PORT_NOT6_NOTP14_Msk (0x01UL << GPIO_PORT_NOT6_NOTP14_Pos) /*!< GPIO_PORT NOT6: NOTP14 Mask */\r
-#define GPIO_PORT_NOT6_NOTP15_Pos 15 /*!< GPIO_PORT NOT6: NOTP15 Position */\r
-#define GPIO_PORT_NOT6_NOTP15_Msk (0x01UL << GPIO_PORT_NOT6_NOTP15_Pos) /*!< GPIO_PORT NOT6: NOTP15 Mask */\r
-#define GPIO_PORT_NOT6_NOTP16_Pos 16 /*!< GPIO_PORT NOT6: NOTP16 Position */\r
-#define GPIO_PORT_NOT6_NOTP16_Msk (0x01UL << GPIO_PORT_NOT6_NOTP16_Pos) /*!< GPIO_PORT NOT6: NOTP16 Mask */\r
-#define GPIO_PORT_NOT6_NOTP17_Pos 17 /*!< GPIO_PORT NOT6: NOTP17 Position */\r
-#define GPIO_PORT_NOT6_NOTP17_Msk (0x01UL << GPIO_PORT_NOT6_NOTP17_Pos) /*!< GPIO_PORT NOT6: NOTP17 Mask */\r
-#define GPIO_PORT_NOT6_NOTP18_Pos 18 /*!< GPIO_PORT NOT6: NOTP18 Position */\r
-#define GPIO_PORT_NOT6_NOTP18_Msk (0x01UL << GPIO_PORT_NOT6_NOTP18_Pos) /*!< GPIO_PORT NOT6: NOTP18 Mask */\r
-#define GPIO_PORT_NOT6_NOTP19_Pos 19 /*!< GPIO_PORT NOT6: NOTP19 Position */\r
-#define GPIO_PORT_NOT6_NOTP19_Msk (0x01UL << GPIO_PORT_NOT6_NOTP19_Pos) /*!< GPIO_PORT NOT6: NOTP19 Mask */\r
-#define GPIO_PORT_NOT6_NOTP20_Pos 20 /*!< GPIO_PORT NOT6: NOTP20 Position */\r
-#define GPIO_PORT_NOT6_NOTP20_Msk (0x01UL << GPIO_PORT_NOT6_NOTP20_Pos) /*!< GPIO_PORT NOT6: NOTP20 Mask */\r
-#define GPIO_PORT_NOT6_NOTP21_Pos 21 /*!< GPIO_PORT NOT6: NOTP21 Position */\r
-#define GPIO_PORT_NOT6_NOTP21_Msk (0x01UL << GPIO_PORT_NOT6_NOTP21_Pos) /*!< GPIO_PORT NOT6: NOTP21 Mask */\r
-#define GPIO_PORT_NOT6_NOTP22_Pos 22 /*!< GPIO_PORT NOT6: NOTP22 Position */\r
-#define GPIO_PORT_NOT6_NOTP22_Msk (0x01UL << GPIO_PORT_NOT6_NOTP22_Pos) /*!< GPIO_PORT NOT6: NOTP22 Mask */\r
-#define GPIO_PORT_NOT6_NOTP23_Pos 23 /*!< GPIO_PORT NOT6: NOTP23 Position */\r
-#define GPIO_PORT_NOT6_NOTP23_Msk (0x01UL << GPIO_PORT_NOT6_NOTP23_Pos) /*!< GPIO_PORT NOT6: NOTP23 Mask */\r
-#define GPIO_PORT_NOT6_NOTP24_Pos 24 /*!< GPIO_PORT NOT6: NOTP24 Position */\r
-#define GPIO_PORT_NOT6_NOTP24_Msk (0x01UL << GPIO_PORT_NOT6_NOTP24_Pos) /*!< GPIO_PORT NOT6: NOTP24 Mask */\r
-#define GPIO_PORT_NOT6_NOTP25_Pos 25 /*!< GPIO_PORT NOT6: NOTP25 Position */\r
-#define GPIO_PORT_NOT6_NOTP25_Msk (0x01UL << GPIO_PORT_NOT6_NOTP25_Pos) /*!< GPIO_PORT NOT6: NOTP25 Mask */\r
-#define GPIO_PORT_NOT6_NOTP26_Pos 26 /*!< GPIO_PORT NOT6: NOTP26 Position */\r
-#define GPIO_PORT_NOT6_NOTP26_Msk (0x01UL << GPIO_PORT_NOT6_NOTP26_Pos) /*!< GPIO_PORT NOT6: NOTP26 Mask */\r
-#define GPIO_PORT_NOT6_NOTP27_Pos 27 /*!< GPIO_PORT NOT6: NOTP27 Position */\r
-#define GPIO_PORT_NOT6_NOTP27_Msk (0x01UL << GPIO_PORT_NOT6_NOTP27_Pos) /*!< GPIO_PORT NOT6: NOTP27 Mask */\r
-#define GPIO_PORT_NOT6_NOTP28_Pos 28 /*!< GPIO_PORT NOT6: NOTP28 Position */\r
-#define GPIO_PORT_NOT6_NOTP28_Msk (0x01UL << GPIO_PORT_NOT6_NOTP28_Pos) /*!< GPIO_PORT NOT6: NOTP28 Mask */\r
-#define GPIO_PORT_NOT6_NOTP29_Pos 29 /*!< GPIO_PORT NOT6: NOTP29 Position */\r
-#define GPIO_PORT_NOT6_NOTP29_Msk (0x01UL << GPIO_PORT_NOT6_NOTP29_Pos) /*!< GPIO_PORT NOT6: NOTP29 Mask */\r
-#define GPIO_PORT_NOT6_NOTP30_Pos 30 /*!< GPIO_PORT NOT6: NOTP30 Position */\r
-#define GPIO_PORT_NOT6_NOTP30_Msk (0x01UL << GPIO_PORT_NOT6_NOTP30_Pos) /*!< GPIO_PORT NOT6: NOTP30 Mask */\r
-#define GPIO_PORT_NOT6_NOTP31_Pos 31 /*!< GPIO_PORT NOT6: NOTP31 Position */\r
-#define GPIO_PORT_NOT6_NOTP31_Msk (0x01UL << GPIO_PORT_NOT6_NOTP31_Pos) /*!< GPIO_PORT NOT6: NOTP31 Mask */\r
-\r
-// ------------------------------------- GPIO_PORT_NOT7 -----------------------------------------\r
-#define GPIO_PORT_NOT7_NOTP0_Pos 0 /*!< GPIO_PORT NOT7: NOTP0 Position */\r
-#define GPIO_PORT_NOT7_NOTP0_Msk (0x01UL << GPIO_PORT_NOT7_NOTP0_Pos) /*!< GPIO_PORT NOT7: NOTP0 Mask */\r
-#define GPIO_PORT_NOT7_NOTP1_Pos 1 /*!< GPIO_PORT NOT7: NOTP1 Position */\r
-#define GPIO_PORT_NOT7_NOTP1_Msk (0x01UL << GPIO_PORT_NOT7_NOTP1_Pos) /*!< GPIO_PORT NOT7: NOTP1 Mask */\r
-#define GPIO_PORT_NOT7_NOTP2_Pos 2 /*!< GPIO_PORT NOT7: NOTP2 Position */\r
-#define GPIO_PORT_NOT7_NOTP2_Msk (0x01UL << GPIO_PORT_NOT7_NOTP2_Pos) /*!< GPIO_PORT NOT7: NOTP2 Mask */\r
-#define GPIO_PORT_NOT7_NOTP3_Pos 3 /*!< GPIO_PORT NOT7: NOTP3 Position */\r
-#define GPIO_PORT_NOT7_NOTP3_Msk (0x01UL << GPIO_PORT_NOT7_NOTP3_Pos) /*!< GPIO_PORT NOT7: NOTP3 Mask */\r
-#define GPIO_PORT_NOT7_NOTP4_Pos 4 /*!< GPIO_PORT NOT7: NOTP4 Position */\r
-#define GPIO_PORT_NOT7_NOTP4_Msk (0x01UL << GPIO_PORT_NOT7_NOTP4_Pos) /*!< GPIO_PORT NOT7: NOTP4 Mask */\r
-#define GPIO_PORT_NOT7_NOTP5_Pos 5 /*!< GPIO_PORT NOT7: NOTP5 Position */\r
-#define GPIO_PORT_NOT7_NOTP5_Msk (0x01UL << GPIO_PORT_NOT7_NOTP5_Pos) /*!< GPIO_PORT NOT7: NOTP5 Mask */\r
-#define GPIO_PORT_NOT7_NOTP6_Pos 6 /*!< GPIO_PORT NOT7: NOTP6 Position */\r
-#define GPIO_PORT_NOT7_NOTP6_Msk (0x01UL << GPIO_PORT_NOT7_NOTP6_Pos) /*!< GPIO_PORT NOT7: NOTP6 Mask */\r
-#define GPIO_PORT_NOT7_NOTP7_Pos 7 /*!< GPIO_PORT NOT7: NOTP7 Position */\r
-#define GPIO_PORT_NOT7_NOTP7_Msk (0x01UL << GPIO_PORT_NOT7_NOTP7_Pos) /*!< GPIO_PORT NOT7: NOTP7 Mask */\r
-#define GPIO_PORT_NOT7_NOTP8_Pos 8 /*!< GPIO_PORT NOT7: NOTP8 Position */\r
-#define GPIO_PORT_NOT7_NOTP8_Msk (0x01UL << GPIO_PORT_NOT7_NOTP8_Pos) /*!< GPIO_PORT NOT7: NOTP8 Mask */\r
-#define GPIO_PORT_NOT7_NOTP9_Pos 9 /*!< GPIO_PORT NOT7: NOTP9 Position */\r
-#define GPIO_PORT_NOT7_NOTP9_Msk (0x01UL << GPIO_PORT_NOT7_NOTP9_Pos) /*!< GPIO_PORT NOT7: NOTP9 Mask */\r
-#define GPIO_PORT_NOT7_NOTP10_Pos 10 /*!< GPIO_PORT NOT7: NOTP10 Position */\r
-#define GPIO_PORT_NOT7_NOTP10_Msk (0x01UL << GPIO_PORT_NOT7_NOTP10_Pos) /*!< GPIO_PORT NOT7: NOTP10 Mask */\r
-#define GPIO_PORT_NOT7_NOTP11_Pos 11 /*!< GPIO_PORT NOT7: NOTP11 Position */\r
-#define GPIO_PORT_NOT7_NOTP11_Msk (0x01UL << GPIO_PORT_NOT7_NOTP11_Pos) /*!< GPIO_PORT NOT7: NOTP11 Mask */\r
-#define GPIO_PORT_NOT7_NOTP12_Pos 12 /*!< GPIO_PORT NOT7: NOTP12 Position */\r
-#define GPIO_PORT_NOT7_NOTP12_Msk (0x01UL << GPIO_PORT_NOT7_NOTP12_Pos) /*!< GPIO_PORT NOT7: NOTP12 Mask */\r
-#define GPIO_PORT_NOT7_NOTP13_Pos 13 /*!< GPIO_PORT NOT7: NOTP13 Position */\r
-#define GPIO_PORT_NOT7_NOTP13_Msk (0x01UL << GPIO_PORT_NOT7_NOTP13_Pos) /*!< GPIO_PORT NOT7: NOTP13 Mask */\r
-#define GPIO_PORT_NOT7_NOTP14_Pos 14 /*!< GPIO_PORT NOT7: NOTP14 Position */\r
-#define GPIO_PORT_NOT7_NOTP14_Msk (0x01UL << GPIO_PORT_NOT7_NOTP14_Pos) /*!< GPIO_PORT NOT7: NOTP14 Mask */\r
-#define GPIO_PORT_NOT7_NOTP15_Pos 15 /*!< GPIO_PORT NOT7: NOTP15 Position */\r
-#define GPIO_PORT_NOT7_NOTP15_Msk (0x01UL << GPIO_PORT_NOT7_NOTP15_Pos) /*!< GPIO_PORT NOT7: NOTP15 Mask */\r
-#define GPIO_PORT_NOT7_NOTP16_Pos 16 /*!< GPIO_PORT NOT7: NOTP16 Position */\r
-#define GPIO_PORT_NOT7_NOTP16_Msk (0x01UL << GPIO_PORT_NOT7_NOTP16_Pos) /*!< GPIO_PORT NOT7: NOTP16 Mask */\r
-#define GPIO_PORT_NOT7_NOTP17_Pos 17 /*!< GPIO_PORT NOT7: NOTP17 Position */\r
-#define GPIO_PORT_NOT7_NOTP17_Msk (0x01UL << GPIO_PORT_NOT7_NOTP17_Pos) /*!< GPIO_PORT NOT7: NOTP17 Mask */\r
-#define GPIO_PORT_NOT7_NOTP18_Pos 18 /*!< GPIO_PORT NOT7: NOTP18 Position */\r
-#define GPIO_PORT_NOT7_NOTP18_Msk (0x01UL << GPIO_PORT_NOT7_NOTP18_Pos) /*!< GPIO_PORT NOT7: NOTP18 Mask */\r
-#define GPIO_PORT_NOT7_NOTP19_Pos 19 /*!< GPIO_PORT NOT7: NOTP19 Position */\r
-#define GPIO_PORT_NOT7_NOTP19_Msk (0x01UL << GPIO_PORT_NOT7_NOTP19_Pos) /*!< GPIO_PORT NOT7: NOTP19 Mask */\r
-#define GPIO_PORT_NOT7_NOTP20_Pos 20 /*!< GPIO_PORT NOT7: NOTP20 Position */\r
-#define GPIO_PORT_NOT7_NOTP20_Msk (0x01UL << GPIO_PORT_NOT7_NOTP20_Pos) /*!< GPIO_PORT NOT7: NOTP20 Mask */\r
-#define GPIO_PORT_NOT7_NOTP21_Pos 21 /*!< GPIO_PORT NOT7: NOTP21 Position */\r
-#define GPIO_PORT_NOT7_NOTP21_Msk (0x01UL << GPIO_PORT_NOT7_NOTP21_Pos) /*!< GPIO_PORT NOT7: NOTP21 Mask */\r
-#define GPIO_PORT_NOT7_NOTP22_Pos 22 /*!< GPIO_PORT NOT7: NOTP22 Position */\r
-#define GPIO_PORT_NOT7_NOTP22_Msk (0x01UL << GPIO_PORT_NOT7_NOTP22_Pos) /*!< GPIO_PORT NOT7: NOTP22 Mask */\r
-#define GPIO_PORT_NOT7_NOTP23_Pos 23 /*!< GPIO_PORT NOT7: NOTP23 Position */\r
-#define GPIO_PORT_NOT7_NOTP23_Msk (0x01UL << GPIO_PORT_NOT7_NOTP23_Pos) /*!< GPIO_PORT NOT7: NOTP23 Mask */\r
-#define GPIO_PORT_NOT7_NOTP24_Pos 24 /*!< GPIO_PORT NOT7: NOTP24 Position */\r
-#define GPIO_PORT_NOT7_NOTP24_Msk (0x01UL << GPIO_PORT_NOT7_NOTP24_Pos) /*!< GPIO_PORT NOT7: NOTP24 Mask */\r
-#define GPIO_PORT_NOT7_NOTP25_Pos 25 /*!< GPIO_PORT NOT7: NOTP25 Position */\r
-#define GPIO_PORT_NOT7_NOTP25_Msk (0x01UL << GPIO_PORT_NOT7_NOTP25_Pos) /*!< GPIO_PORT NOT7: NOTP25 Mask */\r
-#define GPIO_PORT_NOT7_NOTP26_Pos 26 /*!< GPIO_PORT NOT7: NOTP26 Position */\r
-#define GPIO_PORT_NOT7_NOTP26_Msk (0x01UL << GPIO_PORT_NOT7_NOTP26_Pos) /*!< GPIO_PORT NOT7: NOTP26 Mask */\r
-#define GPIO_PORT_NOT7_NOTP27_Pos 27 /*!< GPIO_PORT NOT7: NOTP27 Position */\r
-#define GPIO_PORT_NOT7_NOTP27_Msk (0x01UL << GPIO_PORT_NOT7_NOTP27_Pos) /*!< GPIO_PORT NOT7: NOTP27 Mask */\r
-#define GPIO_PORT_NOT7_NOTP28_Pos 28 /*!< GPIO_PORT NOT7: NOTP28 Position */\r
-#define GPIO_PORT_NOT7_NOTP28_Msk (0x01UL << GPIO_PORT_NOT7_NOTP28_Pos) /*!< GPIO_PORT NOT7: NOTP28 Mask */\r
-#define GPIO_PORT_NOT7_NOTP29_Pos 29 /*!< GPIO_PORT NOT7: NOTP29 Position */\r
-#define GPIO_PORT_NOT7_NOTP29_Msk (0x01UL << GPIO_PORT_NOT7_NOTP29_Pos) /*!< GPIO_PORT NOT7: NOTP29 Mask */\r
-#define GPIO_PORT_NOT7_NOTP30_Pos 30 /*!< GPIO_PORT NOT7: NOTP30 Position */\r
-#define GPIO_PORT_NOT7_NOTP30_Msk (0x01UL << GPIO_PORT_NOT7_NOTP30_Pos) /*!< GPIO_PORT NOT7: NOTP30 Mask */\r
-#define GPIO_PORT_NOT7_NOTP31_Pos 31 /*!< GPIO_PORT NOT7: NOTP31 Position */\r
-#define GPIO_PORT_NOT7_NOTP31_Msk (0x01UL << GPIO_PORT_NOT7_NOTP31_Pos) /*!< GPIO_PORT NOT7: NOTP31 Mask */\r
-\r
-#endif\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- Peripheral memory map -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-#define LPC_SCT_BASE 0x40000000\r
-#define LPC_GPDMA_BASE 0x40002000\r
-#define LPC_SDMMC_BASE 0x40004000\r
-#define LPC_EMC_BASE 0x40005000\r
-#define LPC_USB0_BASE 0x40006000\r
-#define LPC_USB1_BASE 0x40007000\r
-#define LPC_LCD_BASE 0x40008000\r
-#define LPC_ETHERNET_BASE 0x40010000\r
-#define LPC_ATIMER_BASE 0x40040000\r
-#define LPC_REGFILE_BASE 0x40041000\r
-#define LPC_PMC_BASE 0x40042000\r
-#define LPC_CREG_BASE 0x40043000\r
-#define LPC_EVENTROUTER_BASE 0x40044000\r
-#define LPC_RTC_BASE 0x40046000\r
-#define LPC_CGU_BASE 0x40050000\r
-#define LPC_CCU1_BASE 0x40051000\r
-#define LPC_CCU2_BASE 0x40052000\r
-#define LPC_RGU_BASE 0x40053000\r
-#define LPC_WWDT_BASE 0x40080000\r
-#define LPC_USART0_BASE 0x40081000\r
-#define LPC_USART2_BASE 0x400C1000\r
-#define LPC_USART3_BASE 0x400C2000\r
-#define LPC_UART1_BASE 0x40082000\r
-#define LPC_SSP0_BASE 0x40083000\r
-#define LPC_SSP1_BASE 0x400C5000\r
-#define LPC_TIMER0_BASE 0x40084000\r
-#define LPC_TIMER1_BASE 0x40085000\r
-#define LPC_TIMER2_BASE 0x400C3000\r
-#define LPC_TIMER3_BASE 0x400C4000\r
-#define LPC_SCU_BASE 0x40086000\r
-#define LPC_GPIO_PIN_INT_BASE 0x40087000\r
-#define LPC_GPIO_GROUP_INTn_BASE 0x40088000\r
-#define LPC_GPIO_GROUP_INT1_BASE 0x40089000\r
-#define LPC_MCPWM_BASE 0x400A0000\r
-#define LPC_I2C0_BASE 0x400A1000\r
-#define LPC_I2C1_BASE 0x400E0000\r
-#define LPC_I2S0_BASE 0x400A2000\r
-#define LPC_I2S1_BASE 0x400A3000\r
-#define LPC_C_CAN1_BASE 0x400A4000\r
-#define LPC_RITIMER_BASE 0x400C0000\r
-#define LPC_QEI_BASE 0x400C6000\r
-#define LPC_GIMA_BASE 0x400C7000\r
-#define LPC_DAC_BASE 0x400E1000\r
-#define LPC_C_CAN0_BASE 0x400E2000\r
-#define LPC_ADC0_BASE 0x400E3000\r
-#define LPC_ADC1_BASE 0x400E4000\r
-#define LPC_GPIO_PORT_BASE 0x400F4000\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// ----- Peripheral declaration -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)\r
-#define LPC_GPDMA ((LPC_GPDMA_Type *) LPC_GPDMA_BASE)\r
-#define LPC_SDMMC ((LPC_SDMMC_Type *) LPC_SDMMC_BASE)\r
-#define LPC_EMC ((LPC_EMC_Type *) LPC_EMC_BASE)\r
-#define LPC_USB0 ((LPC_USB0_Type *) LPC_USB0_BASE)\r
-#define LPC_USB1 ((LPC_USB1_Type *) LPC_USB1_BASE)\r
-#define LPC_LCD ((LPC_LCD_Type *) LPC_LCD_BASE)\r
-#define LPC_ETHERNET ((LPC_ETHERNET_Type *) LPC_ETHERNET_BASE)\r
-#define LPC_ATIMER ((LPC_ATIMER_Type *) LPC_ATIMER_BASE)\r
-#define LPC_REGFILE ((LPC_REGFILE_Type *) LPC_REGFILE_BASE)\r
-#define LPC_PMC ((LPC_PMC_Type *) LPC_PMC_BASE)\r
-#define LPC_CREG ((LPC_CREG_Type *) LPC_CREG_BASE)\r
-#define LPC_EVENTROUTER ((LPC_EVENTROUTER_Type *) LPC_EVENTROUTER_BASE)\r
-#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)\r
-#define LPC_CGU ((LPC_CGU_Type *) LPC_CGU_BASE)\r
-#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE)\r
-#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE)\r
-#define LPC_RGU ((LPC_RGU_Type *) LPC_RGU_BASE)\r
-#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)\r
-#define LPC_USART0 ((LPC_USARTn_Type *) LPC_USART0_BASE)\r
-#define LPC_USART2 ((LPC_USARTn_Type *) LPC_USART2_BASE)\r
-#define LPC_USART3 ((LPC_USARTn_Type *) LPC_USART3_BASE)\r
-#define LPC_UART1 ((LPC_UART1_Type *) LPC_UART1_BASE)\r
-#define LPC_SSP0 ((LPC_SSPn_Type *) LPC_SSP0_BASE)\r
-#define LPC_SSP1 ((LPC_SSPn_Type *) LPC_SSP1_BASE)\r
-#define LPC_TIMER0 ((LPC_TIMERn_Type *) LPC_TIMER0_BASE)\r
-#define LPC_TIMER1 ((LPC_TIMERn_Type *) LPC_TIMER1_BASE)\r
-#define LPC_TIMER2 ((LPC_TIMERn_Type *) LPC_TIMER2_BASE)\r
-#define LPC_TIMER3 ((LPC_TIMERn_Type *) LPC_TIMER3_BASE)\r
-#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE)\r
-#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)\r
-#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE)\r
-#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE)\r
-#define LPC_MCPWM ((LPC_MCPWM_Type *) LPC_MCPWM_BASE)\r
-#define LPC_I2C0 ((LPC_I2Cn_Type *) LPC_I2C0_BASE)\r
-#define LPC_I2C1 ((LPC_I2Cn_Type *) LPC_I2C1_BASE)\r
-#define LPC_I2S0 ((LPC_I2Sn_Type *) LPC_I2S0_BASE)\r
-#define LPC_I2S1 ((LPC_I2Sn_Type *) LPC_I2S1_BASE)\r
-#define LPC_C_CAN1 ((LPC_C_CANn_Type *) LPC_C_CAN1_BASE)\r
-#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)\r
-#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)\r
-#define LPC_GIMA ((LPC_GIMA_Type *) LPC_GIMA_BASE)\r
-#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)\r
-#define LPC_C_CAN0 ((LPC_C_CANn_Type *) LPC_C_CAN0_BASE)\r
-#define LPC_ADC0 ((LPC_ADCn_Type *) LPC_ADC0_BASE)\r
-#define LPC_ADC1 ((LPC_ADCn_Type *) LPC_ADC1_BASE)\r
-#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)\r
-\r
-\r
-\r
-/** @} */ /* End of group Device_Peripheral_Registers */\r
-/** @} */ /* End of group LPC18xx */\r
-/** @} */ /* End of group (null) */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif // __LPC18XX_H__\r
-\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm3.h\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V2.10\r
- * @date 19. July 2011\r
- *\r
- * @note\r
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
- * processor based microcontrollers. This file can be freely distributed\r
- * within development tools that are supporting such ARM based processors.\r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#endif\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-#ifndef __CORE_CM3_H_GENERIC\r
-#define __CORE_CM3_H_GENERIC\r
-\r
-\r
-/** \mainpage CMSIS Cortex-M3\r
-\r
- This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.\r
- It consists of:\r
-\r
- - Cortex-M Core Register Definitions\r
- - Cortex-M functions\r
- - Cortex-M instructions\r
-\r
- The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease\r
- access to the Cortex-M Core\r
- */\r
-\r
-/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates following MISRA-C2004 Rules:\r
- \r
- - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'. \r
-\r
- - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
- \r
- - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code. \r
-\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions\r
- This file defines all structures and symbols for CMSIS core:\r
- - CMSIS version number\r
- - Cortex-M core\r
- - Cortex-M core Revision Number\r
- @{\r
- */\r
-\r
-/* CMSIS CM3 definitions */\r
-#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */\r
-#define __FPU_USED 0\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- /* add preprocessor checks */\r
-#endif\r
-\r
-#include <stdint.h> /*!< standard types definitions */\r
-#include "core_cmInstr.h" /*!< Core Instruction Access */\r
-#include "core_cmFunc.h" /*!< Core Function Access */\r
-\r
-#endif /* __CORE_CM3_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM3_H_DEPENDANT\r
-#define __CORE_CM3_H_DEPENDANT\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM3_REV\r
- #define __CM3_REV 0x0200\r
- #warning "__CM3_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
-\r
-/*@} end of group CMSIS_core_definitions */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_core_register CMSIS Core Register\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
-*/\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE CMSIS Core\r
- Type definitions for the Cortex-M Core Registers\r
- @{\r
- */\r
-\r
-/** \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC CMSIS NVIC\r
- Type definitions for the Cortex-M NVIC Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB CMSIS SCB\r
- Type definitions for the Cortex-M System Control Block Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5];\r
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB\r
- Type definitions for the Cortex-M System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1];\r
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1[1];\r
-#endif\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick CMSIS SysTick\r
- Type definitions for the Cortex-M System Timer Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM CMSIS ITM\r
- Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __O union\r
- {\r
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */\r
-#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-#if (__MPU_PRESENT == 1)\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU CMSIS MPU\r
- Type definitions for the Cortex-M Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug CMSIS Core Debug\r
- Type definitions for the Cortex-M Core Debug Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions\r
- @{\r
- */\r
-\r
-/** \brief Set Priority Grouping\r
-\r
- This function sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-\r
- \param [in] PriorityGroup Priority grouping field\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/** \brief Get Priority Grouping\r
-\r
- This function gets the priority grouping from NVIC Interrupt Controller.\r
- Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
-\r
- \return Priority grouping field\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
-}\r
-\r
-\r
-/** \brief Enable External Interrupt\r
-\r
- This function enables a device specific interrupt in the NVIC interrupt controller.\r
- The interrupt number cannot be a negative value.\r
-\r
- \param [in] IRQn Number of the external interrupt to enable\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
-\r
-\r
-/** \brief Disable External Interrupt\r
-\r
- This function disables a device specific interrupt in the NVIC interrupt controller.\r
- The interrupt number cannot be a negative value.\r
-\r
- \param [in] IRQn Number of the external interrupt to disable\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-\r
-/** \brief Get Pending Interrupt\r
-\r
- This function reads the pending register in the NVIC and returns the pending bit\r
- for the specified interrupt.\r
-\r
- \param [in] IRQn Number of the interrupt for get pending\r
- \return 0 Interrupt status is not pending\r
- \return 1 Interrupt status is pending\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-\r
-/** \brief Set Pending Interrupt\r
-\r
- This function sets the pending bit for the specified interrupt.\r
- The interrupt number cannot be a negative value.\r
-\r
- \param [in] IRQn Number of the interrupt for set pending\r
- */\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-\r
-/** \brief Clear Pending Interrupt\r
-\r
- This function clears the pending bit for the specified interrupt.\r
- The interrupt number cannot be a negative value.\r
-\r
- \param [in] IRQn Number of the interrupt for clear pending\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-\r
-/** \brief Get Active Interrupt\r
-\r
- This function reads the active register in NVIC and returns the active bit.\r
- \param [in] IRQn Number of the interrupt for get active\r
- \return 0 Interrupt status is not active\r
- \return 1 Interrupt status is active\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-\r
-/** \brief Set Interrupt Priority\r
-\r
- This function sets the priority for the specified interrupt. The interrupt\r
- number can be positive to specify an external (device specific)\r
- interrupt, or negative to specify an internal (core) interrupt.\r
-\r
- Note: The priority cannot be set for every core interrupt.\r
-\r
- \param [in] IRQn Number of the interrupt for set priority\r
- \param [in] priority Priority to set\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-\r
-/** \brief Get Interrupt Priority\r
-\r
- This function reads the priority for the specified interrupt. The interrupt\r
- number can be positive to specify an external (device specific)\r
- interrupt, or negative to specify an internal (core) interrupt.\r
-\r
- The returned priority value is automatically aligned to the implemented\r
- priority bits of the microcontroller.\r
-\r
- \param [in] IRQn Number of the interrupt for get priority\r
- \return Interrupt Priority\r
- */\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/** \brief Encode Priority\r
-\r
- This function encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value and sub priority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
-\r
- The returned priority value can be used for NVIC_SetPriority(...) function\r
-\r
- \param [in] PriorityGroup Used priority group\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0)\r
- \param [in] SubPriority Sub priority value (starting from 0)\r
- \return Encoded priority for the interrupt\r
- */\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/** \brief Decode Priority\r
-\r
- This function decodes an interrupt priority value with the given priority group to\r
- preemptive priority value and sub priority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
-\r
- The priority value can be retrieved with NVIC_GetPriority(...) function\r
-\r
- \param [in] Priority Priority value\r
- \param [in] PriorityGroup Used priority group\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0)\r
- \param [out] pSubPriority Sub priority value (starting from 0)\r
- */\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-/** \brief System Reset\r
-\r
- This function initiate a system reset request to reset the MCU.\r
- */\r
-static __INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0)\r
-\r
-/** \brief System Tick Configuration\r
-\r
- This function initialises the system tick timer and its interrupt and start the system tick timer.\r
- Counter is in free running mode to generate periodical interrupts.\r
-\r
- \param [in] ticks Number of ticks between two interrupts\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
-\r
-\r
-/** \brief ITM Send Character\r
-\r
- This function transmits a character via the ITM channel 0.\r
- It just returns when no debugger is connected that has booked the output.\r
- It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
-\r
- \param [in] ch Character to transmit\r
- \return Character to transmit\r
- */\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/** \brief ITM Receive Character\r
-\r
- This function inputs a character via external variable ITM_RxBuffer.\r
- It just returns when no debugger is connected that has booked the output.\r
- It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
-\r
- \return Received character\r
- \return -1 No character received\r
- */\r
-static __INLINE int32_t ITM_ReceiveChar (void) {\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/** \brief ITM Check Character\r
-\r
- This function checks external variable ITM_RxBuffer whether a character is available or not.\r
- It returns '1' if a character is available and '0' if no character is available.\r
-\r
- \return 0 No character available\r
- \return 1 Character available\r
- */\r
-static __INLINE int32_t ITM_CheckChar (void) {\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-#endif /* __CORE_CM3_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmFunc.h\r
- * @brief CMSIS Cortex-M Core Function Access Header File\r
- * @version V2.10\r
- * @date 26. July 2011\r
- *\r
- * @note\r
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CORE_CMFUNC_H\r
-#define __CORE_CMFUNC_H\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface \r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
- */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-\r
-/** \brief Get ISPR Register\r
-\r
- This function returns the content of the ISPR Register.\r
-\r
- \return ISPR Register value\r
- */\r
-static __INLINE uint32_t __get_IPSR(void)\r
-{\r
- register uint32_t __regIPSR __ASM("ipsr");\r
- return(__regIPSR);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-static __INLINE uint32_t __get_APSR(void)\r
-{\r
- register uint32_t __regAPSR __ASM("apsr");\r
- return(__regAPSR);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-static __INLINE uint32_t __get_xPSR(void)\r
-{\r
- register uint32_t __regXPSR __ASM("xpsr");\r
- return(__regXPSR);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-static __INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- return(__regProcessStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- __regProcessStackPointer = topOfProcStack;\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-static __INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- return(__regMainStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- __regMainStackPointer = topOfMainStack;\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
-\r
- This function assigns the given value to the Priority Mask Register.\r
-\r
- \param [in] priMask Priority Mask\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
- \r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Enable FIQ\r
-\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __enable_fault_irq __enable_fiq\r
-\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
- \r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & (uint32_t)1);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-static __INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- return(__regfpscr);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-static __INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- __regfpscr = (fpscr);\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/** \brief Enable IRQ Interrupts\r
-\r
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)\r
-{\r
- __ASM volatile ("cpsie i");\r
-}\r
-\r
-\r
-/** \brief Disable IRQ Interrupts\r
-\r
- This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)\r
-{\r
- __ASM volatile ("cpsid i");\r
-}\r
-\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) );\r
-}\r
-\r
-\r
-/** \brief Get ISPR Register\r
-\r
- This function returns the content of the ISPR Register.\r
-\r
- \return ISPR Register value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
- return(result);\r
-}\r
- \r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
- return(result);\r
-}\r
- \r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
-\r
- This function assigns the given value to the Priority Mask Register.\r
-\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
-}\r
- \r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Enable FIQ\r
-\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsie f");\r
-}\r
-\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsid f");\r
-}\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
-}\r
-\r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- uint32_t result;\r
-\r
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
- return(result);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-#endif /* __CORE_CMFUNC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmInstr.h\r
- * @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V2.10\r
- * @date 19. July 2011\r
- *\r
- * @note\r
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CORE_CMINSTR_H\r
-#define __CORE_CMINSTR_H\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP __nop\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-#define __WFI __wfi\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE __wfe\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV __sev\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor, \r
- so that all instructions following the ISB are fetched from cache or \r
- memory, after the instruction has been completed.\r
- */\r
-#define __ISB() __isb(0xF)\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier. \r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() __dsb(0xF)\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before \r
- and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() __dmb(0xF)\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV __rev\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-static __INLINE __ASM uint32_t __REV16(uint32_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-static __INLINE __ASM int32_t __REVSH(int32_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __RBIT __rbit\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-#define __CLREX __clrex\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT __ssat\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT __usat\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __clz \r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)\r
-{\r
- __ASM volatile ("nop");\r
-}\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)\r
-{\r
- __ASM volatile ("wfi");\r
-}\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)\r
-{\r
- __ASM volatile ("wfe");\r
-}\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)\r
-{\r
- __ASM volatile ("sev");\r
-}\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor, \r
- so that all instructions following the ISB are fetched from cache or \r
- memory, after the instruction has been completed.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)\r
-{\r
- __ASM volatile ("isb");\r
-}\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier. \r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)\r
-{\r
- __ASM volatile ("dsb");\r
-}\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before \r
- and after the instruction, without ensuring their completion.\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)\r
-{\r
- __ASM volatile ("dmb");\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
- uint8_t result;\r
- \r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
- uint16_t result;\r
- \r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
- \r
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)\r
-{\r
- __ASM volatile ("clrex");\r
-}\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)\r
-{\r
- uint8_t result;\r
- \r
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-#endif /* __CORE_CMINSTR_H */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ debug_frmwrk.h 2011-06-02\r
-*//**\r
-* @file debug_frmwrk.h\r
-* @brief Contains some utilities that used for debugging through UART\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup DEBUG_FRMWRK DEBUG FRAMEWORK\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef DEBUG_FRMWRK_H_\r
-#define DEBUG_FRMWRK_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_uart.h"\r
-\r
-#define VCOM_DEBUG_MESSEGES\r
-//#define UART_DEBUG_MESSEGES\r
-\r
-#define USED_UART_DEBUG_PORT 1\r
-\r
-#if (USED_UART_DEBUG_PORT==0)\r
-#define DEBUG_UART_PORT LPC_UART0\r
-#elif (USED_UART_DEBUG_PORT==1)\r
-#define DEBUG_UART_PORT LPC_UART1\r
-#endif\r
-\r
-#define _DBG(x) _db_msg((LPC_USARTn_Type*)DEBUG_UART_PORT, x)\r
-#define _DBG_(x) _db_msg_((LPC_USARTn_Type*)DEBUG_UART_PORT, x)\r
-#define _DBC(x) _db_char((LPC_USARTn_Type*)DEBUG_UART_PORT, x)\r
-#define _DBD(x) _db_dec((LPC_USARTn_Type*)DEBUG_UART_PORT, x)\r
-#define _DBD16(x) _db_dec_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)\r
-#define _DBD32(x) _db_dec_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)\r
-#define _DBH(x) _db_hex((LPC_USARTn_Type*)DEBUG_UART_PORT, x)\r
-#define _DBH16(x) _db_hex_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)\r
-#define _DBH32(x) _db_hex_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)\r
-#define _DG _db_get_char((LPC_USARTn_Type*)DEBUG_UART_PORT)\r
-void lpc_printf (const char *format, ...);\r
-\r
-extern void (*_db_msg)(LPC_USARTn_Type *UARTx, const void *s);\r
-extern void (*_db_msg_)(LPC_USARTn_Type *UARTx, const void *s);\r
-extern void (*_db_char)(LPC_USARTn_Type *UARTx, uint8_t ch);\r
-extern void (*_db_dec)(LPC_USARTn_Type *UARTx, uint8_t decn);\r
-extern void (*_db_dec_16)(LPC_USARTn_Type *UARTx, uint16_t decn);\r
-extern void (*_db_dec_32)(LPC_USARTn_Type *UARTx, uint32_t decn);\r
-extern void (*_db_hex)(LPC_USARTn_Type *UARTx, uint8_t hexn);\r
-extern void (*_db_hex_16)(LPC_USARTn_Type *UARTx, uint16_t hexn);\r
-extern void (*_db_hex_32)(LPC_USARTn_Type *UARTx, uint32_t hexn);\r
-extern uint8_t (*_db_get_char)(LPC_USARTn_Type *UARTx);\r
-\r
-void UARTPutChar (LPC_USARTn_Type *UARTx, uint8_t ch);\r
-void UARTPuts(LPC_USARTn_Type *UARTx, const void *str);\r
-void UARTPuts_(LPC_USARTn_Type *UARTx, const void *str);\r
-void UARTPutDec(LPC_USARTn_Type *UARTx, uint8_t decnum);\r
-void UARTPutDec16(LPC_USARTn_Type *UARTx, uint16_t decnum);\r
-void UARTPutDec32(LPC_USARTn_Type *UARTx, uint32_t decnum);\r
-void UARTPutHex (LPC_USARTn_Type *UARTx, uint8_t hexnum);\r
-void UARTPutHex16 (LPC_USARTn_Type *UARTx, uint16_t hexnum);\r
-void UARTPutHex32 (LPC_USARTn_Type *UARTx, uint32_t hexnum);\r
-uint8_t UARTGetChar (LPC_USARTn_Type *UARTx);\r
-void debug_frmwrk_init(void);\r
-\r
-#endif /* DEBUG_FRMWRK_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_adc.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_adc.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for ADC firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup ADC ADC (Analog to Digital Converter)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_ADC_H_\r
-#define LPC18XX_ADC_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Private macros ------------------------------------------------------------- */\r
-/** @defgroup ADC_Private_Macros ADC Private Macros\r
- * @{\r
- */\r
-\r
-/* -------------------------- BIT DEFINITIONS ----------------------------------- */\r
-/*********************************************************************//**\r
- * Macro defines for ADC control register\r
- **********************************************************************/\r
-/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */\r
-#define ADC_CR_CH_SEL(n) ((1UL << n))\r
-/** The APB clock (PCLK) is divided by (this value plus one)\r
-* to produce the clock for the A/D */\r
-#define ADC_CR_CLKDIV(n) ((n<<8))\r
-/** Repeated conversions A/D enable bit */\r
-#define ADC_CR_BURST ((1UL<<16))\r
-/** number of accuracy bits */\r
-#define ADC_CR_BITACC(n) (((n)<<17))\r
-/** ADC convert in power down mode */\r
-#define ADC_CR_PDN ((1UL<<21))\r
-/** Start mask bits */\r
-#define ADC_CR_START_MASK ((7UL<<24))\r
-/** Select Start Mode */\r
-#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))\r
-/** Start conversion now */\r
-#define ADC_CR_START_NOW ((1UL<<24))\r
-/** Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */\r
-#define ADC_CR_START_CTOUT15 ((2UL<<24))\r
-/** Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */\r
-#define ADC_CR_START_CTOUT8 ((3UL<<24))\r
-/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */\r
-#define ADC_CR_START_ADCTRIG0 ((4UL<<24))\r
-/** Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */\r
-#define ADC_CR_START_ADCTRIG1 ((5UL<<24))\r
-/** Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */\r
-#define ADC_CR_START_MCOA2 ((6UL<<24))\r
-/** Start conversion on a falling edge on the selected CAP/MAT signal */\r
-#define ADC_CR_EDGE ((1UL<<27))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for ADC Global Data register\r
- **********************************************************************/\r
-/** When DONE is 1, this field contains result value of ADC conversion */\r
-#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))\r
-/** These bits contain the channel from which the LS bits were converted */\r
-#define ADC_GDR_CH(n) (((n>>24)&0x7))\r
-/** This bit is 1 in burst mode if the results of one or\r
- * more conversions was (were) lost */\r
-#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))\r
-/** This bit is set to 1 when an A/D conversion completes */\r
-#define ADC_GDR_DONE_FLAG ((1UL<<31))\r
-\r
-/** This bits is used to mask for Channel */\r
-#define ADC_GDR_CH_MASK ((7UL<<24))\r
-/*********************************************************************//**\r
- * Macro defines for ADC Interrupt register\r
- **********************************************************************/\r
-/** These bits allow control over which A/D channels generate\r
- * interrupts for conversion completion */\r
-#define ADC_INTEN_CH(n) ((1UL<<n))\r
-/** When 1, enables the global DONE flag in ADDR to generate an interrupt */\r
-#define ADC_INTEN_GLOBAL ((1UL<<8))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for ADC Data register\r
- **********************************************************************/\r
-/** When DONE is 1, this field contains result value of ADC conversion */\r
-#define ADC_DR_RESULT(n) (((n>>6)&0x3FF))\r
-/** These bits mirror the OVERRRUN status flags that appear in the\r
- * result register for each A/D channel */\r
-#define ADC_DR_OVERRUN_FLAG ((1UL<<30))\r
-/** This bit is set to 1 when an A/D conversion completes. It is cleared\r
- * when this register is read */\r
-#define ADC_DR_DONE_FLAG ((1UL<<31))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for ADC Status register\r
-**********************************************************************/\r
-/** These bits mirror the DONE status flags that appear in the result\r
- * register for each A/D channel */\r
-#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))\r
-/** These bits mirror the OVERRRUN status flags that appear in the\r
- * result register for each A/D channel */\r
-#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))\r
-/** This bit is the A/D interrupt flag */\r
-#define ADC_STAT_INT_FLAG ((1UL<<16))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for ADC Trim register\r
-**********************************************************************/\r
-/** Offset trim bits for ADC operation */\r
-#define ADC_ADCOFFS(n) (((n&0xF)<<4))\r
-/** Written to boot code*/\r
-#define ADC_TRIM(n) (((n&0xF)<<8))\r
-\r
-/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */\r
-/** Check ADC parameter */\r
-#define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC0) || ((uint32_t *)n)==((uint32_t *)LPC_ADC1))\r
-\r
-/** Check ADC state parameter */\r
-#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING))\r
-\r
-/** Check ADC state parameter */\r
-#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE))\r
-\r
-/** Check ADC rate parameter */\r
-#define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000))\r
-\r
-/** Check ADC bits accuracy parameter */\r
-#define PARAM_ADC_BITSACC(x) ((x>=3)&&(x<=10))\r
-\r
-/** Check ADC channel selection parameter */\r
-#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\\r
-||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\\r
-||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\\r
-||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7))\r
-\r
-/** Check ADC start option parameter */\r
-#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\\r
-||(OPT == ADC_START_ON_CTOUT15)||(OPT == ADC_START_ON_CTOUT8)\\r
-||(OPT == ADC_START_ON_ADCTRIG0)||(OPT == ADC_START_ON_ADCTRIG1)\\r
-||(OPT == ADC_START_ON_MCOA2))\r
-\r
-/** Check ADC interrupt type parameter */\r
-#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\\r
-||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\\r
-||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\\r
-||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\\r
-||(OPT == ADC_ADGINTEN))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup ADC_Public_Types ADC Public Types\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief ADC enumeration\r
- **********************************************************************/\r
-/** @brief Channel Selection */\r
-typedef enum\r
-{\r
- ADC_CHANNEL_0 = 0, /*!< Channel 0 */\r
- ADC_CHANNEL_1, /*!< Channel 1 */\r
- ADC_CHANNEL_2, /*!< Channel 2 */\r
- ADC_CHANNEL_3, /*!< Channel 3 */\r
- ADC_CHANNEL_4, /*!< Channel 4 */\r
- ADC_CHANNEL_5, /*!< Channel 5 */\r
- ADC_CHANNEL_6, /*!< Channel 6 */\r
- ADC_CHANNEL_7 /*!< Channel 7 */\r
-}ADC_CHANNEL_SELECTION;\r
-\r
-/** @brief Type of start option */\r
-typedef enum\r
-{\r
- ADC_START_CONTINUOUS =0, /*!< Continuous mode */\r
- ADC_START_NOW, /*!< Start conversion now */\r
- ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected\r
- * by bit 27 occurs on CTOUT_15 */\r
- ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected\r
- * by bit 27 occurs on CTOUT_8 */\r
- ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected\r
- * by bit 27 occurs on ADCTRIG0 */\r
- ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected\r
- * by bit 27 occurs on ADCTRIG1 */\r
- ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected\r
- * by bit 27 occurs on Motocon PWM output MCOA2 */\r
-} ADC_START_OPT;\r
-\r
-\r
-/** @brief Type of edge when start conversion on the selected CAP/MAT signal */\r
-typedef enum\r
-{\r
- ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge\r
- *on the selected CAP/MAT signal */\r
- ADC_START_ON_FALLING /*!< Start conversion on a falling edge\r
- *on the selected CAP/MAT signal */\r
-} ADC_START_ON_EDGE_OPT;\r
-\r
-/** @brief* ADC type interrupt enum */\r
-typedef enum\r
-{\r
- ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */\r
- ADC_ADINTEN1, /*!< Interrupt channel 1 */\r
- ADC_ADINTEN2, /*!< Interrupt channel 2 */\r
- ADC_ADINTEN3, /*!< Interrupt channel 3 */\r
- ADC_ADINTEN4, /*!< Interrupt channel 4 */\r
- ADC_ADINTEN5, /*!< Interrupt channel 5 */\r
- ADC_ADINTEN6, /*!< Interrupt channel 6 */\r
- ADC_ADINTEN7, /*!< Interrupt channel 7 */\r
- ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */\r
-}ADC_TYPE_INT_OPT;\r
-\r
-/** @brief ADC Data status */\r
-typedef enum\r
-{\r
- ADC_DATA_BURST = 0, /*Burst bit*/\r
- ADC_DATA_DONE /*Done bit*/\r
-}ADC_DATA_STATUS;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup ADC_Public_Functions ADC Public Functions\r
- * @{\r
- */\r
-/* Init/DeInit ADC peripheral ----------------*/\r
-void ADC_Init(LPC_ADCn_Type *ADCx, uint32_t rate, uint8_t bits_accuracy);\r
-void ADC_DeInit(LPC_ADCn_Type *ADCx);\r
-\r
-/* Enable/Disable ADC functions --------------*/\r
-void ADC_BurstCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);\r
-void ADC_PowerdownCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);\r
-void ADC_StartCmd(LPC_ADCn_Type *ADCx, uint8_t start_mode);\r
-void ADC_ChannelCmd (LPC_ADCn_Type *ADCx, uint8_t Channel, FunctionalState NewState);\r
-\r
-/* Configure ADC functions -------------------*/\r
-void ADC_EdgeStartConfig(LPC_ADCn_Type *ADCx, uint8_t EdgeOption);\r
-void ADC_IntConfig (LPC_ADCn_Type *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);\r
-\r
-/* Get ADC information functions -------------------*/\r
-uint16_t ADC_ChannelGetData(LPC_ADCn_Type *ADCx, uint8_t channel);\r
-FlagStatus ADC_ChannelGetStatus(LPC_ADCn_Type *ADCx, uint8_t channel, uint32_t StatusType);\r
-uint32_t ADC_GlobalGetData(LPC_ADCn_Type *ADCx);\r
-FlagStatus ADC_GlobalGetStatus(LPC_ADCn_Type *ADCx, uint32_t StatusType);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* LPC18XX_ADC_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_atimer.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_atimer.h\r
-* @brief Contains all functions support for Alarm Timer firmware\r
-* library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup ATIMER ATIMER (Alarm Timer)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef __LPC18XX_ATIMER_H_\r
-#define __LPC18XX_ATIMER_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup ATIMER_Private_Macros ALARM Timer Private Macros\r
- * @{\r
- */\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-/** Macro to determine if it is valid ALARM TIMER peripheral */\r
-#define PARAM_ATIMERx(n) (((uint32_t *)n)==((uint32_t *)LPC_ATIMER))\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup ATIMER_Public_Functions ATIMER Public Functions\r
- * @{\r
- */\r
-\r
-\r
-/* Init/DeInit ATIMER functions -----------*/\r
-void ATIMER_Init(LPC_ATIMER_Type *ATIMERx, uint32_t PresetValue);\r
-void ATIMER_DeInit(LPC_ATIMER_Type *ATIMERx);\r
-\r
-/* ATIMER interrupt functions -------------*/\r
-void ATIMER_IntEnable(LPC_ATIMER_Type *ATIMERx);\r
-void ATIMER_IntDisable(LPC_ATIMER_Type *ATIMERx);\r
-void ATIMER_ClearIntStatus(LPC_ATIMER_Type *ATIMERx);\r
-void ATIMER_SetIntStatus(LPC_ATIMER_Type *ATIMERx);\r
-\r
-/* ATIMER configuration functions --------*/\r
-void ATIMER_UpdatePresetValue(LPC_ATIMER_Type *ATIMERx,uint32_t PresetValue);\r
-uint32_t ATIMER_GetPresetValue(LPC_ATIMER_Type *ATIMERx);\r
-\r
-/**\r
- * @}\r
- */\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __LPC18XX_ATIMER_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_can.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_can.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for CAN firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup C_CAN C_CAN (Controller Area Network)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef __LPC18XX_CAN_H\r
-#define __LPC18XX_CAN_H\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup C_CAN_Public_Macros C_CAN Public Macros\r
- * @{\r
- */\r
-\r
-/** In BASIC_MODE IF1 registers are used directly as TX buffer, IF2 registers are used as RX buffer.\r
- * If not BASIC_MODE use message objects and IF registers to communicate with message buffers\r
- */\r
-#define BASIC_MODE 0\r
-\r
-/** In Silent Mode, the CAN controller is able to receive valid data frames and valid remote\r
- * frames, but it sends only recessive bits on the CAN bus, and it cannot start a transmission\r
- */\r
-#define SILENT_MODE 0\r
-\r
-/** In Loop-back Mode, the CAN Core treats its own transmitted messages as received messages\r
- * and stores them (if they pass acceptance filtering) into a Receive Buffer.\r
- */\r
-#define LOOPBACK_MODE 0\r
-\r
-/** Enables receiving remote frame requests */\r
-#define REMOTE_ENABLE 1\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private Macros -------------------------------------------------------------- */\r
-/** @defgroup C_CAN_Private_Macros C_CAN Private Macros\r
- * @{\r
- */\r
-\r
-/** MAX CAN message obj */\r
-#define CAN_MSG_OBJ_MAX 0x0020\r
-/** MAX data length */\r
-#define CAN_DLC_MAX 8\r
-\r
-/********************************************************************//**\r
- * BRP+1 = Fpclk/(CANBitRate * QUANTAValue)\r
- * QUANTAValue = 1 + (Tseg1+1) + (Tseg2+1)\r
- * QUANTA value varies based on the Fpclk and sample point\r
- * e.g. (1) sample point is 87.5%, Fpclk is 48Mhz\r
- * the QUANTA should be 16\r
- * (2) sample point is 90%, Fpclk is 12.5Mhz\r
- * the QUANTA should be 10\r
- * Fpclk = Fclk /APBDIV\r
- * or\r
- * BitRate = Fcclk/(APBDIV * (BRP+1) * ((Tseg1+1)+(Tseg2+1)+1))\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief CAN Bit Timing Values definitions at 8Mhz\r
- **********************************************************************/\r
-/** Bitrate: 100K */\r
-#define CAN_BITRATE100K12MHZ 0x00004509\r
-/** Bitrate: 125K */\r
-#define CAN_BITRATE125K12MHZ 0x00004507\r
-/** Bitrate: 250K */\r
-#define CAN_BITRATE250K12MHZ 0x00004503\r
-/** Bitrate: 500K */\r
-#define CAN_BITRATE500K12MHZ 0x00004501\r
-/** Bitrate: 1000K */\r
-#define CAN_BITRATE1000K12MHZ 0x00004500\r
-\r
-/*********************************************************************//**\r
- * @brief CAN Bit Timing Values definitions at 16Mhz\r
- **********************************************************************/\r
-/** Bitrate: 100K */\r
-#define CAN_BITRATE100K16MHZ 0x00005809\r
-/** Bitrate: 125K */\r
-#define CAN_BITRATE125K16MHZ 0x00005807\r
-/** Bitrate: 250K */\r
-#define CAN_BITRATE250K16MHZ 0x00005803\r
-/** Bitrate: 500K */\r
-#define CAN_BITRATE500K16MHZ 0x00005801\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief CAN Bit Timing Values definitions at 24Mhz\r
- **********************************************************************/\r
-/** Bitrate: 100K */\r
-#define CAN_BITRATE100K24MHZ 0x00007E09\r
-/** Bitrate: 125K */\r
-#define CAN_BITRATE125K24MHZ 0x0000450F\r
-/** Bitrate: 250K */\r
-#define CAN_BITRATE250K24MHZ 0x00004507\r
-/** Bitrate: 500K */\r
-#define CAN_BITRATE500K24MHZ 0x00004503\r
-/** Bitrate: 1000K */\r
-#define CAN_BITRATE1000K24MHZ 0x00004501\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup CAN_Public_Types CAN Public Types\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief CAN enumeration\r
- **********************************************************************/\r
-\r
-/**\r
- * @brief CAN interface register type definition\r
- */\r
-typedef enum CCAN_IFREG\r
-{\r
- CMDREQ = 0, /**< Command request */\r
- CMDMSK = 1, /**< Command mask */\r
- MSK1 = 2, /**< Mask 1 */\r
- MSK2 = 3, /**< Mask 2 */\r
- ARB1 = 4, /**< Arbitration 1 */\r
- ARB2 = 5, /**< Arbitration 2 */\r
- MCTRL = 6, /**< Message control */\r
- DA1 = 7, /**< Data A1 */\r
- DA2 = 8, /**< Data A2 */\r
- DB1 = 9, /**< Data B1 */\r
- DB2 = 10 /**< Data B2 */\r
-}CCAN_IFREG_Type;\r
-\r
-/**\r
- * @brief CAN Clock division rate type definition\r
- */\r
-typedef enum CCAN_CLKDIV\r
-{\r
- CLKDIV1 = 0,\r
- CLKDIV2 = 1,\r
- CLKDIV3 = 2,\r
- CLKDIV5 = 3,\r
- CLKDIV9 = 4,\r
- CLKDIV17 = 5,\r
- CLKDIV33 = 6,\r
- CLKDIV65 = 7\r
-}CCAN_CLKDIV_Type;\r
-\r
-\r
-/********************************************************************//**\r
-* @brief Data structure definition for a CAN message\r
-**********************************************************************/\r
-/**\r
- * @brief CAN message object structure\r
- */\r
-typedef struct\r
-{\r
- uint32_t id; /**< ID of message, if bit 30 is set then this is extended frame */\r
- uint32_t dlc; /**< Message data length */\r
- uint8_t data[8]; /**< Message data */\r
-} message_object;\r
-\r
-/**\r
- * @brief CAN call-back function\r
- */\r
-typedef void (*MSG_CB)(uint32_t msg_no);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup CAN_Public_Functions CAN Public Functions\r
- * @{\r
- */\r
-\r
-void CAN_IRQHandler (void);\r
-void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb);\r
-\r
-void CAN_ConfigureRxMessageObjects( void );\r
-void CAN_RxInt_MessageProcess( uint8_t MsgObjNo );\r
-void CAN_TxInt_MessageProcess( uint8_t MsgObjNo );\r
-\r
-void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr );\r
-void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable);\r
-void CAN_ReadMsg(uint32_t msg_no, message_object* buff);\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* __LPC18XX_CAN_H */\r
-\r
-/**\r
- * @}\r
- */\r
-/*****************************************************************************\r
-** End Of File\r
-******************************************************************************/\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_cgu.h 2011-06-02\r
-*//**\r
-* @file llpc18xx_cgu.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for Clock Generation and Clock Control firmware\r
-* library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup CGU CGU (Clock Generation Unit)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_CGU_H_\r
-#define LPC18XX_CGU_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Private Macros -------------------------------------------------------------- */\r
-/** @defgroup CGU_Private_Macros CGU Private Macros\r
- * @{\r
- */\r
-\r
-/** Branch clocks from CGU_BASE_SAFE */\r
-#define CGU_ENTITY_NONE CGU_ENTITY_NUM\r
-\r
-/** Check bit at specific position is clear or not */\r
-#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))\r
-/** Check bit at specific position is set or not */\r
-#define ISBITSET(x,bit) (x&(1<<bit))\r
-/** Set mask */\r
-#define ISMASKSET(x,mask) (x&mask)\r
-\r
-/** CGU number of clock source */\r
-#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)\r
-\r
-/*********************************************************************//**\r
- * Macro defines for CGU control mask bit definitions\r
- **********************************************************************/\r
-/** CGU control enable mask bit */\r
-#define CGU_CTRL_EN_MASK 1\r
-/** CGU control clock-source mask bit */\r
-#define CGU_CTRL_SRC_MASK (0xF<<24)\r
-/** CGU control auto block mask bit */\r
-#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)\r
-\r
-/*********************************************************************//**\r
- * Macro defines for CGU PLL1 mask bit definitions\r
- **********************************************************************/\r
-/** CGU PLL1 feedback select mask bit */\r
-#define CGU_PLL1_FBSEL_MASK (1<<6)\r
-/** CGU PLL1 Input clock bypass control mask bit */\r
-#define CGU_PLL1_BYPASS_MASK (1<<1)\r
-/** CGU PLL1 direct CCO output mask bit */\r
-#define CGU_PLL1_DIRECT_MASK (1<<7)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup CGU_Public_Types CGU Public Types\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief CGU enumeration\r
- **********************************************************************/\r
-/*\r
- * @brief CGU clock source enumerate definition
- */\r
-typedef enum {\r
- /* Clock Source */\r
- CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */\r
- CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */\r
- CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */\r
- CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */\r
- CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */\r
- CGU_CLKSRC_TCK, /**< TCK clock source */\r
- CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/\r
- CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */\r
- CGU_CLKSRC_PLL0_AUDIO,\r
- CGU_CLKSRC_PLL1, /**< PLL1 clock source */\r
- CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */\r
- CGU_CLKSRC_IDIVB, /**< IDIVB clock source */\r
- CGU_CLKSRC_IDIVC, /**< IDIVC clock source */\r
- CGU_CLKSRC_IDIVD, /**< IDIVD clock source */\r
- CGU_CLKSRC_IDIVE, /**< IDIVE clock source */\r
-\r
- /* Base */\r
- CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */\r
- CGU_BASE_USB0, /**< USB0 base clock */\r
- CGU_BASE_USB1 = CGU_BASE_USB0 + 2, /**< USB1 base clock */\r
- CGU_BASE_M3, /**< ARM Cortex-M3 Core base clock */\r
- CGU_BASE_SPIFI, /**< SPIFI base clock */\r
- //CGU_BASE_SPI,\r
- CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */\r
- CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */\r
- CGU_BASE_APB1, /**< APB peripheral block #1 base clock */\r
- CGU_BASE_APB3, /**< APB peripheral block #3 base clock */\r
- CGU_BASE_LCD, /**< LCD base clock */\r
- CGU_BASE_ENET_CSR,\r
- CGU_BASE_SDIO, /**< SDIO base clock */\r
- CGU_BASE_SSP0, /**< SSP0 base clock */\r
- CGU_BASE_SSP1, /**< SSP1 base clock */\r
- CGU_BASE_UART0, /**< UART0 base clock */\r
- CGU_BASE_UART1, /**< UART1 base clock */\r
- CGU_BASE_UART2, /**< UART2 base clock */\r
- CGU_BASE_UART3, /**< UART3 base clock */\r
- CGU_BASE_CLKOUT, /**< CLKOUT base clock */\r
- CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,\r
- CGU_BASE_OUT0,\r
- CGU_BASE_OUT1,\r
- CGU_ENTITY_NUM /**< Number or clock source entity */\r
-} CGU_ENTITY_T;\r
-\r
-/*\r
- * @brief CGU PPL0 mode enumerate definition\r
- */\r
-typedef enum {\r
- CGU_PLL0_MODE_1d = 0,\r
- CGU_PLL0_MODE_1c,\r
- CGU_PLL0_MODE_1b,\r
- CGU_PLL0_MODE_1a\r
-}CGU_PLL0_MODE;\r
-\r
-/*\r
- * @brief CGU peripheral enumerate definition\r
- */\r
-typedef enum {\r
- CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */\r
- CGU_PERIPHERAL_ADC1, /**< ADC1 */\r
- CGU_PERIPHERAL_AES, /**< AES */\r
-// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,\r
- CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */\r
- CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */\r
- CGU_PERIPHERAL_CAN, /**< CAN */\r
- CGU_PERIPHERAL_CREG, /**< CREG */\r
- CGU_PERIPHERAL_DAC, /**< DAC */\r
- CGU_PERIPHERAL_DMA, /**< DMA */\r
- CGU_PERIPHERAL_EMC, /**< EMC */\r
- CGU_PERIPHERAL_ETHERNET, /**< Ethernet */\r
- CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */\r
- CGU_PERIPHERAL_GPIO, /**< GPIO */\r
- CGU_PERIPHERAL_I2C0, /**< I2C0 */\r
- CGU_PERIPHERAL_I2C1, /**< I2C1 */\r
- CGU_PERIPHERAL_I2S, /**< I2S */\r
- CGU_PERIPHERAL_LCD, /**< LCD */\r
- CGU_PERIPHERAL_M3CORE, /**< ARM Cortex-M3 Core */\r
- CGU_PERIPHERAL_M3_BUS, /**< ARM Cortex-M3 Bus */\r
- CGU_PERIPHERAL_MOTOCON, /**< Motor Control */\r
- CGU_PERIPHERAL_QEI, /**< QEI */\r
- CGU_PERIPHERAL_RITIMER, /**< RIT Timer */\r
- CGU_PERIPHERAL_SCT, /**< SCT */\r
- CGU_PERIPHERAL_SCU, /**< SCU */\r
- CGU_PERIPHERAL_SDIO, /**< SDIO */\r
- CGU_PERIPHERAL_SPIFI, /**< SPIFI */\r
- CGU_PERIPHERAL_SSP0, /**< SSP0 */\r
- CGU_PERIPHERAL_SSP1, /**< SSP1 */\r
- CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */\r
- CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */\r
- CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */\r
- CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */\r
- CGU_PERIPHERAL_UART0, /**< UART0 */\r
- CGU_PERIPHERAL_UART1, /**< UART1 */\r
- CGU_PERIPHERAL_UART2, /**< UART2 */\r
- CGU_PERIPHERAL_UART3, /**< UART3 */\r
- CGU_PERIPHERAL_USB0, /**< USB0 */\r
- CGU_PERIPHERAL_USB1, /**< USB1 */\r
- CGU_PERIPHERAL_WWDT, /**< WWDT */\r
- CGU_PERIPHERAL_NUM\r
-} CGU_PERIPHERAL_T;\r
-\r
-/**\r
- * @brief CGU error status enumerate definition\r
- */\r
-typedef enum {\r
- CGU_ERROR_SUCCESS = 0,\r
- CGU_ERROR_CONNECT_TOGETHER,\r
- CGU_ERROR_INVALID_ENTITY,\r
- CGU_ERROR_INVALID_CLOCK_SOURCE,\r
- CGU_ERROR_INVALID_PARAM,\r
- CGU_ERROR_FREQ_OUTOF_RANGE\r
-} CGU_ERROR;\r
-\r
-/********************************************************************//**\r
-* @brief CGU structure definitions\r
-**********************************************************************/\r
-/*\r
- * @brief CGU peripheral clock structure
- */\r
-typedef struct {\r
- uint8_t RegBaseEntity; /**< Base register address */\r
- uint16_t RegBranchOffset; /**< Branch register offset */\r
- uint8_t PerBaseEntity; /**< Base peripheral address */\r
- uint16_t PerBranchOffset; /**< Base peripheral offset */\r
- uint8_t next; /**< Pointer to next structure */\r
-} CGU_PERIPHERAL_S;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup CGU_Public_Functions CGU Public Functions\r
- * @{\r
- */\r
-\r
-/** Clock generate initialize/de-initialize */\r
-uint32_t CGU_Init(void);\r
-uint32_t CGU_DeInit(void);\r
-\r
-/** Clock Generator and Clock Control */\r
-uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);\r
-uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);\r
-\r
-/** Clock Source and Base Clock operation */\r
-uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);\r
-uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);\r
-uint32_t CGU_SetPLL0(void);\r
-uint32_t CGU_SetPLL1(uint32_t mult);\r
-uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);\r
-uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);\r
-uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);\r
-void CGU_UpdateClock(void);\r
-uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_CGU_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/***********************************************************************//**\r
- * @file lpc18xx_clkpwr.h\r
- * @brief Contains all macro definitions and function prototypes\r
- * support for Clock and Power Control firmware library on LPC18xx\r
- * @version 1.0\r
- * @date 14. Dec. 2010\r
- * @author NXP MCU SW Application Team\r
- **************************************************************************\r
- * Software that is described herein is for illustrative purposes only\r
- * which provides customers with programming information regarding the\r
- * products. This software is supplied "AS IS" without any warranties.\r
- * NXP Semiconductors assumes no responsibility or liability for the\r
- * use of the software, conveys no license or title under any patent,\r
- * copyright, or mask work right to the product. NXP Semiconductors\r
- * reserves the right to make changes in the software without\r
- * notification. NXP Semiconductors also make no representation or\r
- * warranty that such application will be suitable for the specified\r
- * use without further testing or modification.\r
- **************************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup CLKPWR CLKPWR\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_CLKPWR_H_\r
-#define LPC18XX_CLKPWR_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros\r
- * @{\r
- */\r
-\r
-typedef enum {\r
- /* Clock Source */\r
- CLKPWR_CLKSRC_32KHZ_OSC = 0,\r
- CLKPWR_CLKSRC_IRC,\r
- CLKPWR_CLKSRC_ENET_RX_CLK,\r
- CLKPWR_CLKSRC_ENET_TX_CLK,\r
- CLKPWR_CLKSRC_GP_CLKIN,\r
- CLKPWR_CLKSRC_TCK,\r
- CLKPWR_CLKSRC_XTAL_OSC,\r
- CLKPWR_CLKSRC_PLL0,\r
- CLKPWR_CLKSRC_PLL1,\r
- CLKPWR_CLKSRC_IDIVA = CLKPWR_CLKSRC_PLL1 + 3,\r
- CLKPWR_CLKSRC_IDIVB,\r
- CLKPWR_CLKSRC_IDIVC,\r
- CLKPWR_CLKSRC_IDIVD,\r
- CLKPWR_CLKSRC_IDIVE,\r
-\r
- /* Base */\r
- CLKPWR_BASE_SAFE,\r
- CLKPWR_BASE_USB0,\r
- CLKPWR_BASE_USB1 = CLKPWR_BASE_USB0 + 2,\r
- CLKPWR_BASE_M3,\r
- CLKPWR_BASE_SPIFI,\r
- //CLKPWR_BASE_SPI,\r
- CLKPWR_BASE_PHY_RX = CLKPWR_BASE_SPIFI + 2,\r
- CLKPWR_BASE_PHY_TX,\r
- CLKPWR_BASE_APB1,\r
- CLKPWR_BASE_APB3,\r
- CLKPWR_BASE_LCD,\r
- CLKPWR_BASE_SDIO = CLKPWR_BASE_LCD + 2,\r
- CLKPWR_BASE_SSP0,\r
- CLKPWR_BASE_SSP1,\r
- CLKPWR_BASE_UART0,\r
- CLKPWR_BASE_UART1,\r
- CLKPWR_BASE_UART2,\r
- CLKPWR_BASE_UART3,\r
- CLKPWR_BASE_CLKOUT,\r
- CLKPWR_ENTITY_NUM\r
-} CLKPWR_ENTITY_T;\r
-\r
-#define CLKPWR_CLKSRC_NUM (CLKPWR_CLKSRC_IDIVE+1)\r
-\r
-typedef enum {\r
- CLKPWR_PLL0_MODE_1d = 0,\r
- CLKPWR_PLL0_MODE_1c,\r
- CLKPWR_PLL0_MODE_1b,\r
- CLKPWR_PLL0_MODE_1a,\r
-}CLKPWR_PLL0_MODE;\r
-\r
-typedef enum {\r
- CLKPWR_PERIPHERAL_ADC0 = 0,\r
- CLKPWR_PERIPHERAL_ADC1,\r
- CLKPWR_PERIPHERAL_AES,\r
-// CLKPWR_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,\r
- CLKPWR_PERIPHERAL_APB1_BUS,\r
- CLKPWR_PERIPHERAL_APB3_BUS,\r
- CLKPWR_PERIPHERAL_CAN,\r
- CLKPWR_PERIPHERAL_CREG,\r
- CLKPWR_PERIPHERAL_DAC,\r
- CLKPWR_PERIPHERAL_DMA,\r
- CLKPWR_PERIPHERAL_EMC,\r
- CLKPWR_PERIPHERAL_ETHERNET,\r
- CLKPWR_PERIPHERAL_ETHERNET_TX, //HIDE\r
- CLKPWR_PERIPHERAL_GPIO,\r
- CLKPWR_PERIPHERAL_I2C0,\r
- CLKPWR_PERIPHERAL_I2C1,\r
- CLKPWR_PERIPHERAL_I2S,\r
- CLKPWR_PERIPHERAL_LCD,\r
- CLKPWR_PERIPHERAL_M3CORE,\r
- CLKPWR_PERIPHERAL_M3_BUS,\r
- CLKPWR_PERIPHERAL_MOTOCON,\r
- CLKPWR_PERIPHERAL_QEI,\r
- CLKPWR_PERIPHERAL_RITIMER,\r
- CLKPWR_PERIPHERAL_SCT,\r
- CLKPWR_PERIPHERAL_SCU,\r
- CLKPWR_PERIPHERAL_SDIO,\r
- CLKPWR_PERIPHERAL_SPIFI,\r
- CLKPWR_PERIPHERAL_SSP0,\r
- CLKPWR_PERIPHERAL_SSP1,\r
- CLKPWR_PERIPHERAL_TIMER0,\r
- CLKPWR_PERIPHERAL_TIMER1,\r
- CLKPWR_PERIPHERAL_TIMER2,\r
- CLKPWR_PERIPHERAL_TIMER3,\r
- CLKPWR_PERIPHERAL_UART0,\r
- CLKPWR_PERIPHERAL_UART1,\r
- CLKPWR_PERIPHERAL_UART2,\r
- CLKPWR_PERIPHERAL_UART3,\r
- CLKPWR_PERIPHERAL_USB0,\r
- CLKPWR_PERIPHERAL_USB1,\r
- CLKPWR_PERIPHERAL_WWDT,\r
- CLKPWR_PERIPHERAL_NUM\r
-} CLKPWR_PERIPHERAL_T;\r
-//typedef CLKPWR_CLK_T CLKPWR_BASE_T;\r
-\r
-typedef struct {\r
- uint8_t RegBaseEntity;\r
- uint16_t RegBranchOffset;\r
- uint8_t PerBaseEntity;\r
- uint16_t PerBranchOffset;\r
- uint8_t next;\r
-} CLKPWR_PERIPHERAL_S;\r
-\r
-typedef enum {\r
- CLKPWR_ERROR_SUCCESS = 0,\r
- CLKPWR_ERROR_CONNECT_TOGETHER,\r
- CLKPWR_ERROR_INVALID_ENTITY,\r
- CLKPWR_ERROR_INVALID_CLOCK_SOURCE,\r
- CLKPWR_ERROR_INVALID_PARAM,\r
- CLKPWR_ERROR_FREQ_OUTOF_RANGE\r
-} CLKPWR_ERROR;\r
-\r
-/* Branch clocks from CLKPWR_BASE_SAFE */\r
-\r
-#define CLKPWR_ENTITY_NONE CLKPWR_ENTITY_NUM\r
-\r
-#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))\r
-#define ISBITSET(x,bit) (x&(1<<bit))\r
-#define ISMASKSET(x,mask) (x&mask)\r
-\r
-#define CLKPWR_CTRL_EN_MASK 1\r
-#define CLKPWR_CTRL_SRC_MASK (0xF<<24)\r
-#define CLKPWR_CTRL_AUTOBLOCK_MASK (1<<11)\r
-#define CLKPWR_PLL1_FBSEL_MASK (1<<6)\r
-#define CLKPWR_PLL1_BYPASS_MASK (1<<1)\r
-#define CLKPWR_PLL1_DIRECT_MASK (1<<7)\r
-\r
-#define CLKPWR_SLEEP_MODE_DEEP_SLEEP 0x3F00AA\r
-#define CLKPWR_SLEEP_MODE_POWER_DOWN 0x3FFCBA\r
-#define CLKPWR_SLEEP_MODE_DEEP_POWER_DOWN 0x3FFF7F\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions\r
- * @{\r
- */\r
-/* Clock Generator */\r
-\r
-uint32_t CLKPWR_ConfigPWR (CLKPWR_PERIPHERAL_T PPType, FunctionalState en);\r
-\r
-uint32_t CLKPWR_GetPCLKFrequency (CLKPWR_PERIPHERAL_T Clock);\r
-\r
-/* Clock Source and Base Clock operation */\r
-uint32_t CLKPWR_SetXTALOSC(uint32_t ClockFrequency);\r
-uint32_t CLKPWR_SetDIV(CLKPWR_ENTITY_T SelectDivider, uint32_t divisor);\r
-uint32_t CLKPWR_SetPLL0(void);\r
-uint32_t CLKPWR_SetPLL1(uint32_t mult);\r
-uint32_t CLKPWR_EnableEntity(CLKPWR_ENTITY_T ClockEntity, uint32_t en);\r
-uint32_t CLKPWR_EntityConnect(CLKPWR_ENTITY_T ClockSource, CLKPWR_ENTITY_T ClockEntity);\r
-uint32_t CLKPWR_GetBaseStatus(CLKPWR_ENTITY_T Base);\r
-\r
-void CLKPWR_UpdateClock(void);\r
-uint32_t CLKPWR_RealFrequencyCompare(CLKPWR_ENTITY_T Clock, CLKPWR_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);\r
-\r
-uint32_t CLKPWR_Init(void);\r
-uint32_t CLKPWR_DeInit(void);\r
-\r
-void CLKPWR_Sleep(void);\r
-void CLKPWR_DeepSleep(void);\r
-void CLKPWR_PowerDown(void);\r
-void CLKPWR_DeepPowerDown(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_CLKPWR_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_dac.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_dac.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for DAC firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup DAC DAC (Digital to Analog Converter)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_DAC_H_\r
-#define LPC18XX_DAC_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup DAC_Private_Macros DAC Private Macros\r
- * @{\r
- */\r
-\r
-/** After the selected settling time after this field is written with a\r
-new VALUE, the voltage on the AOUT pin (with respect to VSSA)\r
-is VALUE/1024 × VREF */\r
-#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6))\r
-/** If this bit = 0: The settling time of the DAC is 1 microsecond max,\r
- * and the maximum current is 700 microAmpere\r
- * If this bit = 1: The settling time of the DAC is 2.5 microsecond\r
- * and the maximum current is 350 microAmpere */\r
-#define DAC_BIAS_EN ((uint32_t)(1<<16))\r
-/** Value to reload interrupt DMA counter */\r
-#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff))\r
-\r
-/** DCAR double buffering */\r
-#define DAC_DBLBUF_ENA ((uint32_t)(1<<1))\r
-/** DCAR Time out count enable */\r
-#define DAC_CNT_ENA ((uint32_t)(1<<2))\r
-/** DCAR DMA access */\r
-#define DAC_DMA_ENA ((uint32_t)(1<<3))\r
-/** DCAR DACCTRL mask bit */\r
-#define DAC_DACCTRL_MASK ((uint32_t)(0x0F))\r
-\r
-/** Macro to determine if it is valid DAC peripheral */\r
-#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC))\r
-\r
-/** Macro to check DAC current optional parameter */\r
-#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\\r
-||(OPTION == DAC_MAX_CURRENT_350uA))\r
-\r
-/**\r
- * @}\r
- */\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup DAC_Public_Types DAC Public Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Current option in DAC configuration option */\r
-typedef enum\r
-{\r
- DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max,\r
- and the maximum current is 700 uA */\r
- DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us\r
- and the maximum current is 350 uA */\r
-} DAC_CURRENT_OPT;\r
-\r
-/**\r
- * @brief Configuration for DAC converter control register */\r
-typedef struct\r
-{\r
-\r
- uint8_t DBLBUF_ENA; /**<\r
- -0: Disable DACR double buffering\r
- -1: when bit CNT_ENA, enable DACR double buffering feature\r
- */\r
- uint8_t CNT_ENA; /*!<\r
- -0: Time out counter is disable\r
- -1: Time out conter is enable\r
- */\r
- uint8_t DMA_ENA; /*!<\r
- -0: DMA access is disable\r
- -1: DMA burst request\r
- */\r
- uint8_t RESERVED;\r
-\r
-} DAC_CONVERTER_CFG_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup DAC_Public_Functions DAC Public Functions\r
- * @{\r
- */\r
-\r
-void DAC_Init(LPC_DAC_Type *DACx);\r
-void DAC_UpdateValue (LPC_DAC_Type *DACx, uint32_t dac_value);\r
-void DAC_SetBias (LPC_DAC_Type *DACx,uint32_t bias);\r
-void DAC_ConfigDAConverterControl (LPC_DAC_Type *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);\r
-void DAC_SetDMATimeOut(LPC_DAC_Type *DACx,uint32_t time_out);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* LPC18XX_DAC_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************
-* $Id: lpc43xx_emc.h 8765 2011-12-08 00:51:21Z nxp21346 $ lpc43xx_emc.h 2011-12-07
-*//**
-* @file lpc43xx_emc.h
-* @brief Contains all functions support for Clock Generation and Control
-* firmware library on lpc43xx
-* @version 1.0
-* @date 07. December. 2011
-* @author NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#define __CRYSTAL (12000000UL) /* Crystal Oscillator frequency */
-#define __PLLMULT (15)
-#define __PLLOUTHZ (__CRYSTAL * __PLLMULT)
-#define __EMCDIV (2)
-#define __EMCHZ (__PLLOUTHZ / __EMCDIV)
-
-void MemoryPinInit(void);
-void EMCFlashInit(void);
-
-/* SDRAM Address Base for DYCS0*/
-#define SDRAM_BASE_ADDR 0x28000000
-#define FLASH_BASE_ADDR 0x1C000000
-
-#define EMC_SDRAM_WIDTH_8_BITS 0
-#define EMC_SDRAM_WIDTH_16_BITS 1
-#define EMC_SDRAM_WIDTH_32_BITS 2
-
-#define EMC_SDRAM_SIZE_16_MBITS 0
-#define EMC_SDRAM_SIZE_64_MBITS 1
-#define EMC_SDRAM_SIZE_128_MBITS 2
-#define EMC_SDRAM_SIZE_256_MBITS 3
-#define EMC_SDRAM_SIZE_512_MBITS 4
-
-#define EMC_SDRAM_DATA_BUS_16_BITS 0
-#define EMC_SDRAM_DATA_BUS_32_BITS 1
-
-#define EMC_B_ENABLE (1 << 19)
-#define EMC_ENABLE (1 << 0)
-#define EMC_CE_ENABLE (1 << 0)
-#define EMC_CS_ENABLE (1 << 1)
-#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
-#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
-#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
-#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
-#define EMC_INIT(i) ((i) << 7)
-#define EMC_NORMAL (0)
-#define EMC_MODE (1)
-#define EMC_PRECHARGE_ALL (2)
-#define EMC_NOP (3)
-
-/* The Hitex LPC18xx Evaluation board contains a 64Mb SDRAM with a 16-bit data bus */
-#define SDRAM_SIZE_BYTES (1024UL * 1024UL * 8UL)
-#define SDRAM_WIDTH EMC_SDRAM_WIDTH_16_BITS
-#define SDRAM_SIZE_MBITS EMC_SDRAM_SIZE_64_MBITS
-#define SDRAM_DATA_BUS_BITS EMC_SDRAM_DATA_BUS_16_BITS
-#define SDRAM_COL_ADDR_BITS 8
-#define CLK0_DELAY 0
-
-void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits);
-void emc_WaitUS(volatile uint32_t us);
-void emc_WaitMS(uint32_t ms);
-
-
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_evrt.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_evrt.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for Event Router firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup EVRT EVRT (Event Router)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_EVRT_H_\r
-#define LPC18XX_EVRT_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup EVRT_Private_Macros EVRT Private Macros\r
- * @{\r
- */\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-/** Macro to determine if it is valid EVRT peripheral */\r
-#define PARAM_EVRTx(x) (((uint32_t *)x)==((uint32_t *)LPC_EVENTROUTER))\r
-\r
-/* Macro check EVRT source */\r
-#define PARAM_EVRT_SOURCE(n) ((n==EVRT_SRC_WAKEUP0) || (n==EVRT_SRC_WAKEUP1) \\r
-|| (n==EVRT_SRC_WAKEUP2) || (n==EVRT_SRC_WAKEUP3) \\r
-|| (n==EVRT_SRC_ATIMER) || (n==EVRT_SRC_RTC) \\r
-|| (n==EVRT_SRC_BOD1) || (n==EVRT_SRC_WWDT) \\r
-|| (n==EVRT_SRC_ETHERNET) || (n==EVRT_SRC_USB0) \\r
-|| (n==EVRT_SRC_USB1) || (n==EVRT_SRC_CCAN) || (n==EVRT_SRC_SDIO) \\r
-|| (n==EVRT_SRC_COMBINE_TIMER2) || (n==EVRT_SRC_COMBINE_TIMER6) \\r
-|| (n==EVRT_SRC_QEI) || (n==EVRT_SRC_COMBINE_TIMER14) \\r
-|| (n==EVRT_SRC_RESET)) \\r
-\r
-/* Macro check EVRT source active type*/\r
-#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n==EVRT_SRC_ACTIVE_LOW_LEVEL) || (n==EVRT_SRC_ACTIVE_HIGH_LEVEL) \\r
- || (n==EVRT_SRC_ACTIVE_FALLING_EDGE) || (n==EVRT_SRC_ACTIVE_RISING_EDGE))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup EVRT_Public_Types EVRT Public Types\r
- * @{\r
- */\r
-\r
-/** @brief EVRT input sources */\r
-typedef enum {\r
- EVRT_SRC_WAKEUP0, /**< WAKEUP0 event router source */\r
- EVRT_SRC_WAKEUP1, /**< WAKEUP1 event router source */\r
- EVRT_SRC_WAKEUP2, /**< WAKEUP2 event router source */\r
- EVRT_SRC_WAKEUP3, /**< WAKEUP3 event router source */\r
- EVRT_SRC_ATIMER, /**< Alarm timer event router source */\r
- EVRT_SRC_RTC, /**< RTC event router source */\r
- EVRT_SRC_BOD1, /**< BOD event router source */\r
- EVRT_SRC_WWDT, /**< WWDT event router source */\r
- EVRT_SRC_ETHERNET, /**< Ethernet event router source */\r
- EVRT_SRC_USB0, /**< USB0 event router source */\r
- EVRT_SRC_USB1, /**< USB1 event router source */\r
- EVRT_SRC_SDIO, /**< Reserved */\r
- EVRT_SRC_CCAN, /**< C_CAN event router source */\r
- EVRT_SRC_COMBINE_TIMER2, /**< Combined timer 2 event router source */\r
- EVRT_SRC_COMBINE_TIMER6, /**< Combined timer 6 event router source */\r
- EVRT_SRC_QEI, /**< QEI event router source */\r
- EVRT_SRC_COMBINE_TIMER14, /**< Combined timer 14 event router source */\r
- EVRT_SRC_RESERVED1, /**< Reserved */\r
- EVRT_SRC_RESERVED2, /**< Reserved */\r
- EVRT_SRC_RESET /**< Reset event router source */\r
-} EVRT_SRC_ENUM;\r
-\r
-\r
-/** @brief EVRT input sources detecting type */\r
-typedef enum {\r
- EVRT_SRC_ACTIVE_LOW_LEVEL, /**< Active low level */\r
- EVRT_SRC_ACTIVE_HIGH_LEVEL, /**< Active high level */\r
- EVRT_SRC_ACTIVE_FALLING_EDGE, /**< Active falling edge */\r
- EVRT_SRC_ACTIVE_RISING_EDGE /**< Active rising edge */\r
-}EVRT_SRC_ACTIVE_TYPE;\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup EVRT_Public_Functions EVRT Public Functions\r
- * @{\r
- */\r
-\r
-void EVRT_Init (LPC_EVENTROUTER_Type *EVRTx);\r
-void EVRT_DeInit(LPC_EVENTROUTER_Type *EVRTx);\r
-\r
-void EVRT_ConfigIntSrcActiveType(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type);\r
-void EVRT_SetUpIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, FunctionalState state);\r
-Bool EVRT_IsSourceInterrupting(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src);\r
-void EVRT_ClrPendIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_EVRT_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_gpdma.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_gpdma.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for GPDMA firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup GPDMA GPDMA (General Purpose DMA)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_GPDMA_H_\r
-#define LPC18XX_GPDMA_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup GPDMA_Public_Macros GPDMA Public Macros\r
- * @{\r
- */\r
-\r
-/** DMA Connection number definitions */\r
-#define GPDMA_CONN_SPIFI ((0UL)) /**< SPIFI */\r
-#define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */\r
-#define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */\r
-#define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */\r
-#define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */\r
-#define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */\r
-#define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */\r
-#define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */\r
-#define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */\r
-#define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */\r
-#define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */\r
-#define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */\r
-#define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */\r
-#define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */\r
-#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */\r
-#define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/\r
-#define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */\r
-#define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */\r
-#define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/\r
-#define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */\r
-#define GPDMA_CONN_I2S_Channel_0 ((20UL)) /**< I2S channel 0 */\r
-#define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */\r
-#define GPDMA_CONN_I2S_Channel_1 ((22UL)) /**< I2S channel 1 */\r
-#define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */\r
-#define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */\r
-#define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */\r
-#define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */\r
-#define GPDMA_CONN_DAC ((27UL)) /**< DAC */\r
-\r
-/** GPDMA Transfer type definitions */\r
-#define GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA ((0UL)) /**< Memory to memory - DMA control */\r
-#define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA ((1UL)) /**< Memory to peripheral - DMA control */\r
-#define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA ((2UL)) /**< Peripheral to memory - DMA control */\r
-#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA ((3UL)) /**< Source peripheral to destination peripheral - DMA control */\r
-#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL ((4UL)) /**< Source peripheral to destination peripheral - destination peripheral control */\r
-#define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL ((5UL)) /**< Memory to peripheral - peripheral control */\r
-#define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL ((6UL)) /**< Peripheral to memory - peripheral control */\r
-#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL ((7UL)) /**< Source peripheral to destination peripheral - source peripheral control */\r
-\r
-/** Burst size in Source and Destination definitions */\r
-#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */\r
-#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */\r
-#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */\r
-#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */\r
-#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */\r
-#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */\r
-#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */\r
-#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */\r
-\r
-/** Width in Source transfer width and Destination transfer width definitions */\r
-#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */\r
-#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */\r
-#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */\r
-\r
-/** LPC_GPDMA base addresses */\r
-#define LPC_GPDMACH0_BASE 0x40002100\r
-#define LPC_GPDMACH1_BASE 0x40002120\r
-#define LPC_GPDMACH2_BASE 0x40002140\r
-#define LPC_GPDMACH3_BASE 0x40002160\r
-#define LPC_GPDMACH4_BASE 0x40002180\r
-#define LPC_GPDMACH5_BASE 0x400021A0\r
-#define LPC_GPDMACH6_BASE 0x400021C0\r
-#define LPC_GPDMACH7_BASE 0x400021E0\r
-\r
-/* LPC_GPDMA channels definitions */\r
-#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )\r
-#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )\r
-#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )\r
-#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )\r
-#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )\r
-#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )\r
-#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )\r
-#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup GPDMA_Private_Macros GPDMA Private Macros\r
- * @{\r
- */\r
-\r
-/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
-/*********************************************************************//**\r
- * Macro defines for DMA Interrupt Status register\r
- **********************************************************************/\r
-#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))\r
-#define GPDMA_DMACIntStat_BITMASK ((0xFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Interrupt Terminal Count Request Status register\r
- **********************************************************************/\r
-#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))\r
-#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Interrupt Terminal Count Request Clear register\r
- **********************************************************************/\r
-#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))\r
-#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Interrupt Error Status register\r
- **********************************************************************/\r
-#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))\r
-#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Interrupt Error Clear register\r
- **********************************************************************/\r
-#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))\r
-#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Raw Interrupt Terminal Count Status register\r
- **********************************************************************/\r
-#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))\r
-#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Raw Error Interrupt Status register\r
- **********************************************************************/\r
-#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))\r
-#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Enabled Channel register\r
- **********************************************************************/\r
-#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))\r
-#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Software Burst Request register\r
- **********************************************************************/\r
-#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))\r
-#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Software Single Request register\r
- **********************************************************************/\r
-#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))\r
-#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Software Last Burst Request register\r
- **********************************************************************/\r
-#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))\r
-#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Software Last Single Request register\r
- **********************************************************************/\r
-#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))\r
-#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Configuration register\r
- **********************************************************************/\r
-#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/\r
-#define GPDMA_DMACConfig_M0 ((0x02)) /**< AHB Master 0 endianness configuration*/\r
-#define GPDMA_DMACConfig_M1 ((0x04)) /**< AHB Master 1 endianness configuration*/\r
-#define GPDMA_DMACConfig_BITMASK ((0x07))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Synchronization register\r
- **********************************************************************/\r
-#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))\r
-#define GPDMA_DMACSync_BITMASK ((0xFFFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Channel Linked List Item registers\r
- **********************************************************************/\r
-/** DMA Channel Linked List Item registers bit mask*/\r
-#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA channel control registers\r
- **********************************************************************/\r
-#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/\r
-#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/\r
-#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/\r
-#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/\r
-#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/\r
-#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL<<24)) /**< Source AHB master select*/\r
-#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL<<25)) /**< Destination AHB master select*/\r
-#define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/\r
-#define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/\r
-#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/\r
-#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/\r
-#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/\r
-#define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */\r
-/** DMA channel control registers bit mask */\r
-#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA Channel Configuration registers\r
- **********************************************************************/\r
-#define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/\r
-#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/\r
-#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/\r
-#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/\r
-#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/\r
-#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/\r
-#define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/\r
-#define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/\r
-#define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/\r
-/** DMA Channel Configuration registers bit mask */\r
-#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-/* Macros check GPDMA channel */\r
-#define PARAM_GPDMA_CHANNEL(n) (n<=7)\r
-\r
-/* Macros check GPDMA connection type */\r
-#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SPIFI) || (n==GPDMA_CONN_DAC) \\r
-|| (n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \\r
-|| (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \\r
-|| (n==GPDMA_CONN_ADC_0) || (n==GPDMA_CONN_ADC_1) \\r
-|| (n==GPDMA_CONN_I2S_Channel_0) || (n==GPDMA_CONN_I2S_Channel_1) \\r
-|| (n==GPDMA_CONN_SCT_0) || (n==GPDMA_CONN_SCT_1) \\r
-|| (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \\r
-|| (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \\r
-|| (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \\r
-|| (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \\r
-|| (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \\r
-|| (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \\r
-|| (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \\r
-|| (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))\r
-\r
-/* Macros check GPDMA burst size type */\r
-#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \\r
-|| (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \\r
-|| (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \\r
-|| (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))\r
-\r
-/* Macros check GPDMA width type */\r
-#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \\r
-|| (n==GPDMA_WIDTH_WORD))\r
-\r
-/* Macros check GPDMA status type */\r
-#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \\r
-|| (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \\r
-|| (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))\r
-\r
-/* Macros check GPDMA transfer type */\r
-#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA) \\r
-||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA)\\r
-||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL)\\r
-||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL))\r
-\r
-/* Macros check GPDMA state clear type */\r
-#define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup GPDMA_Public_Types GPDMA Public Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief GPDMA Channel Registers\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CSrcAddr;\r
- __IO uint32_t CDestAddr;\r
- __IO uint32_t CLLI;\r
- __IO uint32_t CControl;\r
- __IO uint32_t CConfig;\r
-} LPC_GPDMACH_TypeDef;\r
-\r
-/**\r
- * @brief GPDMA Status enumeration\r
- */\r
-typedef enum {\r
- GPDMA_STAT_INT, /**< GPDMA Interrupt Status */\r
- GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */\r
- GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */\r
- GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */\r
- GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */\r
- GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */\r
-} GPDMA_Status_Type;\r
-\r
-/**\r
- * @brief GPDMA Interrupt clear status enumeration\r
- */\r
-typedef enum{\r
- GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */\r
- GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */\r
-}GPDMA_StateClear_Type;\r
-\r
-/**\r
- * @brief GPDMA Channel configuration structure type definition\r
- */\r
-typedef struct {\r
- uint32_t ChannelNum; /**< DMA channel number, should be in\r
- range from 0 to 7.\r
- Note: DMA channel 0 has the highest priority\r
- and DMA channel 7 the lowest priority.\r
- */\r
- uint32_t TransferSize; /**< Length/Size of transfer */\r
- uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */\r
- uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as\r
- GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */\r
- uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as\r
- GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */\r
- uint32_t TransferType; /**< Transfer Type, should be one of the following:\r
- - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: Memory to memory - DMA control\r
- - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: Memory to peripheral - DMA control\r
- - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: Peripheral to memory - DMA control\r
- - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: Source peripheral to destination peripheral - DMA control\r
- - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: Source peripheral to destination peripheral - destination peripheral control\r
- - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: Memory to peripheral - peripheral control\r
- - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: Peripheral to memory - peripheral control\r
- - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL: Source peripheral to destination peripheral - source peripheral control\r
- */\r
- uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as\r
- GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of\r
- following:\r
- - GPDMA_CONN_SSP0_Tx: SSP0, Tx\r
- - GPDMA_CONN_SSP0_Rx: SSP0, Rx\r
- - GPDMA_CONN_SSP1_Tx: SSP1, Tx\r
- - GPDMA_CONN_SSP1_Rx: SSP1, Rx\r
- - GPDMA_CONN_ADC_0: ADC0\r
- - GPDMA_CONN_ADC_1: ADC1\r
- - GPDMA_CONN_SCT_0: SCT0\r
- - GPDMA_CONN_SCT_1: SCT1\r
- - GPDMA_CONN_I2S_Channel_0: I2S Channel 0\r
- - GPDMA_CONN_I2S_Channel_1: I2S Channel 1\r
- - GPDMA_CONN_DAC: DAC\r
- - GPDMA_CONN_SPIFI: SPIFI\r
- - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0\r
- - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1\r
- - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0\r
- - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1\r
- - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0\r
- - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1\r
- - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0\r
- - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1\r
- */\r
- uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as\r
- GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of\r
- following:\r
- - GPDMA_CONN_SSP0_Tx: SSP0, Tx\r
- - GPDMA_CONN_SSP0_Rx: SSP0, Rx\r
- - GPDMA_CONN_SSP1_Tx: SSP1, Tx\r
- - GPDMA_CONN_SSP1_Rx: SSP1, Rx\r
- - GPDMA_CONN_ADC_0: ADC0\r
- - GPDMA_CONN_ADC_1: ADC1\r
- - GPDMA_CONN_SCT_0: SCT0\r
- - GPDMA_CONN_SCT_1: SCT1\r
- - GPDMA_CONN_I2S_Channel_0: I2S Channel 0\r
- - GPDMA_CONN_I2S_Channel_1: I2S Channel 1\r
- - GPDMA_CONN_DAC: DAC\r
- - GPDMA_CONN_SPIFI: SPIFI\r
- - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0\r
- - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1\r
- - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0\r
- - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1\r
- - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0\r
- - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1\r
- - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0\r
- - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1\r
- */\r
- uint32_t DMALLI; /**< Linker List Item structure data address\r
- if there's no Linker List, set as '0'\r
- */\r
-} GPDMA_Channel_CFG_Type;\r
-\r
-/**\r
- * @brief GPDMA Linker List Item structure type definition\r
- */\r
-typedef struct {\r
- uint32_t SrcAddr; /**< Source Address */\r
- uint32_t DstAddr; /**< Destination address */\r
- uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */\r
- uint32_t Control; /**< GPDMA Control of this LLI */\r
-} GPDMA_LLI_Type;\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup GPDMA_Public_Functions GPDMA Public Functions\r
- * @{\r
- */\r
-\r
-void GPDMA_Init(void);\r
-\r
-Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);\r
-IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);\r
-void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);\r
-void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_GPDMA_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_gpio.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_gpio.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for GPIO firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup GPIO GPIO (General Purpose I/O)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_GPIO_H_\r
-#define LPC18XX_GPIO_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup GPIO_Public_Macros GPIO Public Macros\r
- * @{\r
- */\r
-#if 0\r
-/** General LPC GPIO Base */\r
-#define LPC_GPIO_BASE LPC_GPIO0_BASE\r
-/** Fast GPIO port 0 byte accessible definition */\r
-#define GPIO0_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x00))\r
-/** Fast GPIO port 1 byte accessible definition */\r
-#define GPIO1_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x20))\r
-/** Fast GPIO port 2 byte accessible definition */\r
-#define GPIO2_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x40))\r
-/** Fast GPIO port 3 byte accessible definition */\r
-#define GPIO3_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x60))\r
-/** Fast GPIO port 4 byte accessible definition */\r
-#define GPIO4_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x80))\r
-\r
-\r
-/** Fast GPIO port 0 half-word accessible definition */\r
-#define GPIO0_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x00))\r
-/** Fast GPIO port 1 half-word accessible definition */\r
-#define GPIO1_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x20))\r
-/** Fast GPIO port 2 half-word accessible definition */\r
-#define GPIO2_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x40))\r
-/** Fast GPIO port 3 half-word accessible definition */\r
-#define GPIO3_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x60))\r
-/** Fast GPIO port 4 half-word accessible definition */\r
-#define GPIO4_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x80))\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup GPIO_Public_Types GPIO Public Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Fast GPIO port byte type definition\r
- */\r
- #if 0\r
-typedef struct {\r
- __IO uint8_t FIODIR[4]; /**< FIO direction register in byte-align */\r
- uint32_t RESERVED0[3]; /**< Reserved */\r
- __IO uint8_t FIOMASK[4]; /**< FIO mask register in byte-align */\r
- __IO uint8_t FIOPIN[4]; /**< FIO pin register in byte align */\r
- __IO uint8_t FIOSET[4]; /**< FIO set register in byte-align */\r
- __O uint8_t FIOCLR[4]; /**< FIO clear register in byte-align */\r
-} GPIO_Byte_TypeDef;\r
-#endif\r
-\r
-/**\r
- * @brief Fast GPIO port half-word type definition\r
- */\r
- #if 0\r
-typedef struct {\r
- __IO uint16_t FIODIRL; /**< FIO direction register lower halfword part */\r
- __IO uint16_t FIODIRU; /**< FIO direction register upper halfword part */\r
- uint32_t RESERVED0[3]; /**< Reserved */\r
- __IO uint16_t FIOMASKL; /**< FIO mask register lower halfword part */\r
- __IO uint16_t FIOMASKU; /**< FIO mask register upper halfword part */\r
- __IO uint16_t FIOPINL; /**< FIO pin register lower halfword part */\r
- __IO uint16_t FIOPINU; /**< FIO pin register upper halfword part */\r
- __IO uint16_t FIOSETL; /**< FIO set register lower halfword part */\r
- __IO uint16_t FIOSETU; /**< FIO set register upper halfword part */\r
- __O uint16_t FIOCLRL; /**< FIO clear register lower halfword part */\r
- __O uint16_t FIOCLRU; /**< FIO clear register upper halfword part */\r
-} GPIO_HalfWord_TypeDef;\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup GPIO_Public_Functions GPIO Public Functions\r
- * @{\r
- */\r
-\r
-/* GPIO style ------------------------------- */\r
-void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);\r
-void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);\r
-void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);\r
-uint32_t GPIO_ReadValue(uint8_t portNum);\r
-\r
-#ifdef GPIO_INT\r
-void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);\r
-FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);\r
-void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);\r
-#endif\r
-\r
-\r
-/* FIO (word-accessible) style ------------------------------- */\r
-void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);\r
-void FIO_SetValue(uint8_t portNum, uint32_t bitValue);\r
-void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);\r
-uint32_t FIO_ReadValue(uint8_t portNum);\r
-void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);\r
-\r
-#ifdef GPIO_INT\r
-void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);\r
-FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);\r
-void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);\r
-#endif\r
-\r
-#if 0\r
-/* FIO (halfword-accessible) style ------------------------------- */\r
-void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir);\r
-void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue);\r
-void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);\r
-void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);\r
-uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum);\r
-\r
-\r
-/* FIO (byte-accessible) style ------------------------------- */\r
-void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir);\r
-void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue);\r
-void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);\r
-void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);\r
-uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum);\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_GPIO_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_i2c.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_i2c.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for I2C firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup I2C I2C (Inter-Integrated Circuit)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_I2C_H_\r
-#define LPC18XX_I2C_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup I2C_Private_Macros I2C Private Macros\r
- * @{\r
- */\r
-\r
-/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
-/*******************************************************************//**\r
- * I2C Control Set register description\r
- *********************************************************************/\r
-#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */\r
-#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */\r
-#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */\r
-#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */\r
-#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */\r
-\r
-/*******************************************************************//**\r
- * I2C Control Clear register description\r
- *********************************************************************/\r
-/** Assert acknowledge Clear bit */\r
-#define I2C_I2CONCLR_AAC ((1<<2))\r
-/** I2C interrupt Clear bit */\r
-#define I2C_I2CONCLR_SIC ((1<<3))\r
-/** START flag Clear bit */\r
-#define I2C_I2CONCLR_STAC ((1<<5))\r
-/** I2C interface Disable bit */\r
-#define I2C_I2CONCLR_I2ENC ((1<<6))\r
-\r
-/********************************************************************//**\r
- * I2C Status Code definition (I2C Status register)\r
- *********************************************************************/\r
-/* Return Code in I2C status register */\r
-#define I2C_STAT_CODE_BITMASK ((0xF8))\r
-\r
-/* I2C return status code definitions ----------------------------- */\r
-\r
-/** No relevant information */\r
-#define I2C_I2STAT_NO_INF ((0xF8))\r
-\r
-/* Master transmit mode -------------------------------------------- */\r
-/** A start condition has been transmitted */\r
-#define I2C_I2STAT_M_TX_START ((0x08))\r
-/** A repeat start condition has been transmitted */\r
-#define I2C_I2STAT_M_TX_RESTART ((0x10))\r
-/** SLA+W has been transmitted, ACK has been received */\r
-#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))\r
-/** SLA+W has been transmitted, NACK has been received */\r
-#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))\r
-/** Data has been transmitted, ACK has been received */\r
-#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))\r
-/** Data has been transmitted, NACK has been received */\r
-#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))\r
-/** Arbitration lost in SLA+R/W or Data bytes */\r
-#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))\r
-\r
-/* Master receive mode -------------------------------------------- */\r
-/** A start condition has been transmitted */\r
-#define I2C_I2STAT_M_RX_START ((0x08))\r
-/** A repeat start condition has been transmitted */\r
-#define I2C_I2STAT_M_RX_RESTART ((0x10))\r
-/** Arbitration lost */\r
-#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))\r
-/** SLA+R has been transmitted, ACK has been received */\r
-#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))\r
-/** SLA+R has been transmitted, NACK has been received */\r
-#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))\r
-/** Data has been received, ACK has been returned */\r
-#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))\r
-/** Data has been received, NACK has been return */\r
-#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))\r
-\r
-/* Slave receive mode -------------------------------------------- */\r
-/** Own slave address has been received, ACK has been returned */\r
-#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))\r
-\r
-/** Arbitration lost in SLA+R/W as master */\r
-#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))\r
-/** Own SLA+W has been received, ACK returned */\r
-//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))\r
-\r
-/** General call address has been received, ACK has been returned */\r
-#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))\r
-\r
-/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */\r
-#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))\r
-/** General call address has been received, ACK has been returned */\r
-//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))\r
-\r
-/** Previously addressed with own SLV address;\r
- * Data has been received, ACK has been return */\r
-#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))\r
-/** Previously addressed with own SLA;\r
- * Data has been received and NOT ACK has been return */\r
-#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))\r
-/** Previously addressed with General Call;\r
- * Data has been received and ACK has been return */\r
-#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))\r
-/** Previously addressed with General Call;\r
- * Data has been received and NOT ACK has been return */\r
-#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))\r
-/** A STOP condition or repeated START condition has\r
- * been received while still addressed as SLV/REC\r
- * (Slave Receive) or SLV/TRX (Slave Transmit) */\r
-#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))\r
-\r
-/** Slave transmit mode */\r
-/** Own SLA+R has been received, ACK has been returned */\r
-#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))\r
-\r
-/** Arbitration lost in SLA+R/W as master */\r
-#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))\r
-/** Own SLA+R has been received, ACK has been returned */\r
-//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))\r
-\r
-/** Data has been transmitted, ACK has been received */\r
-#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))\r
-/** Data has been transmitted, NACK has been received */\r
-#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))\r
-/** Last data byte in I2DAT has been transmitted (AA = 0);\r
- ACK has been received */\r
-#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))\r
-\r
-/** Time out in case of using I2C slave mode */\r
-#define I2C_SLAVE_TIME_OUT 0x10000UL\r
-\r
-/********************************************************************//**\r
- * I2C Data register definition\r
- *********************************************************************/\r
-/** Mask for I2DAT register*/\r
-#define I2C_I2DAT_BITMASK ((0xFF))\r
-\r
-/** Idle data value will be send out in slave mode in case of the actual\r
- * expecting data requested from the master is greater than its sending data\r
- * length that can be supported */\r
-#define I2C_I2DAT_IDLE_CHAR (0xFF)\r
-\r
-/********************************************************************//**\r
- * I2C Monitor mode control register description\r
- *********************************************************************/\r
-#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */\r
-#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */\r
-#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */\r
-#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */\r
-\r
-/********************************************************************//**\r
- * I2C Data buffer register description\r
- *********************************************************************/\r
-/** I2C Data buffer register bit mask */\r
-#define I2DATA_BUFFER_BITMASK ((0xFF))\r
-\r
-/********************************************************************//**\r
- * I2C Slave Address registers definition\r
- *********************************************************************/\r
-/** General Call enable bit */\r
-#define I2C_I2ADR_GC ((1<<0))\r
-/** I2C Slave Address registers bit mask */\r
-#define I2C_I2ADR_BITMASK ((0xFF))\r
-\r
-/********************************************************************//**\r
- * I2C Mask Register definition\r
- *********************************************************************/\r
-/** I2C Mask Register mask field */\r
-#define I2C_I2MASK_MASK(n) ((n&0xFE))\r
-\r
-/********************************************************************//**\r
- * I2C SCL HIGH duty cycle Register definition\r
- *********************************************************************/\r
-/** I2C SCL HIGH duty cycle Register bit mask */\r
-#define I2C_I2SCLH_BITMASK ((0xFFFF))\r
-\r
-/********************************************************************//**\r
- * I2C SCL LOW duty cycle Register definition\r
- *********************************************************************/\r
-/** I2C SCL LOW duty cycle Register bit mask */\r
-#define I2C_I2SCLL_BITMASK ((0xFFFF))\r
-\r
-/* I2C status values */\r
-#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */\r
-#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */\r
-#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */\r
-\r
-/*********************************************************************//**\r
- * I2C monitor control configuration defines\r
- **********************************************************************/\r
-#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */\r
-#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-/* Macros check I2C slave address */\r
-#define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)\r
-\r
-/** Macro to determine if it is valid SSP port number */\r
-#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \\r
-|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)))\r
-\r
-/* Macros check I2C monitor configuration type */\r
-#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup I2C_Public_Types I2C Public Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief I2C Own slave address setting structure
- */\r
-typedef struct {\r
- uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,\r
- should be in range from 0..3\r
- */\r
- uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */\r
- uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality\r
- when I2C control being in Slave mode, should be:\r
- - ENABLE: Enable General Call function.\r
- - DISABLE: Disable General Call function.\r
- */\r
- uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)\r
- which is set to '1' will cause an automatic compare on\r
- the corresponding bit of the received address when it\r
- is compared to the SlaveAddr_7bit value associated with this\r
- mask register. In other words, bits in SlaveAddr_7bit value\r
- which are masked are not taken into account in determining\r
- an address match\r
- */\r
-} I2C_OWNSLAVEADDR_CFG_Type;\r
-\r
-\r
-/**\r
- * @brief Master transfer setup data structure definitions\r
- */\r
-typedef struct\r
-{\r
- uint32_t sl_addr7bit; /**< Slave address in 7bit mode */\r
- uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit\r
- is not used */\r
- uint32_t tx_length; /**< Transmit data length - 0 if data transmit\r
- is not used*/\r
- uint32_t tx_count; /**< Current Transmit data counter */\r
- uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive\r
- is not used */\r
- uint32_t rx_length; /**< Receive data length - 0 if data receive is\r
- not used */\r
- uint32_t rx_count; /**< Current Receive data counter */\r
- uint32_t retransmissions_max; /**< Max Re-Transmission value */\r
- uint32_t retransmissions_count; /**< Current Re-Transmission counter */\r
- uint32_t status; /**< Current status of I2C activity */\r
- void (*callback)(void); /**< Pointer to Call back function when transmission complete\r
- used in interrupt transfer mode */\r
-} I2C_M_SETUP_Type;\r
-\r
-\r
-/**\r
- * @brief Slave transfer setup data structure definitions\r
- */\r
-typedef struct\r
-{\r
- uint8_t* tx_data; /**< Pointer to transmit data - NULL if data transmit is not used */\r
- uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used */\r
- uint32_t tx_count; /**< Current transmit data counter */\r
- uint8_t* rx_data; /**< Pointer to receive data - NULL if data received is not used */\r
- uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */\r
- uint32_t rx_count; /**< Current receive data counter */\r
- uint32_t status; /**< Current status of I2C activity */\r
- void (*callback)(void); /**< Pointer to call-back function when transmission complete\r
- used by interrupt transfer mode */\r
-} I2C_S_SETUP_Type;\r
-\r
-/**\r
- * @brief Transfer option type definitions\r
- */\r
-typedef enum {\r
- I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */\r
- I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */\r
-} I2C_TRANSFER_OPT_Type;\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup I2C_Public_Functions I2C Public Functions\r
- * @{\r
- */\r
-\r
-/* I2C Init/DeInit functions ---------- */\r
-void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate);\r
-void I2C_DeInit(LPC_I2Cn_Type* I2Cx);\r
-//void I2C_SetClock (LPC_I2Cn_Type *I2Cx, uint32_t target_clock);\r
-void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState);\r
-\r
-/* I2C transfer data functions -------- */\r
-Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, \\r
- I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);\r
-Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, \\r
- I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);\r
-uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx);\r
-uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx);\r
-\r
-\r
-void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);\r
-uint8_t I2C_GetLastStatusCode(LPC_I2Cn_Type* I2Cx);\r
-\r
-/* I2C Monitor functions ---------------*/\r
-void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);\r
-void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState);\r
-uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx);\r
-BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size);\r
-\r
-/* I2C Interrupt handler functions ------*/\r
-void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState);\r
-void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx);\r
-void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx);\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_I2C_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_i2s.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_i2s.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for I2S firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup I2S I2S (Inter-IC Sound)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_I2S_H_\r
-#define LPC18XX_I2S_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup I2S_Private_Macros I2S Private Macros\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * I2S configuration parameter defines\r
- **********************************************************************/\r
-/** I2S Wordwidth bit */\r
-#define I2S_WORDWIDTH_8 ((uint32_t)(0))\r
-#define I2S_WORDWIDTH_16 ((uint32_t)(1))\r
-#define I2S_WORDWIDTH_32 ((uint32_t)(3))\r
-/** I2S Channel bit */\r
-#define I2S_STEREO ((uint32_t)(0))\r
-#define I2S_MONO ((uint32_t)(1))\r
-/** I2S Master/Slave mode bit */\r
-#define I2S_MASTER_MODE ((uint8_t)(0))\r
-#define I2S_SLAVE_MODE ((uint8_t)(1))\r
-/** I2S Stop bit */\r
-#define I2S_STOP_ENABLE ((uint8_t)(1))\r
-#define I2S_STOP_DISABLE ((uint8_t)(0))\r
-/** I2S Reset bit */\r
-#define I2S_RESET_ENABLE ((uint8_t)(1))\r
-#define I2S_RESET_DISABLE ((uint8_t)(0))\r
-/** I2S Mute bit */\r
-#define I2S_MUTE_ENABLE ((uint8_t)(1))\r
-#define I2S_MUTE_DISABLE ((uint8_t)(0))\r
-/** I2S Transmit/Receive bit */\r
-#define I2S_TX_MODE ((uint8_t)(0))\r
-#define I2S_RX_MODE ((uint8_t)(1))\r
-/** I2S Clock Select bit */\r
-#define I2S_CLKSEL_FRDCLK ((uint8_t)(0))\r
-#define I2S_CLKSEL_MCLK ((uint8_t)(2))\r
-/** I2S 4-pin Mode bit */\r
-#define I2S_4PIN_ENABLE ((uint8_t)(1))\r
-#define I2S_4PIN_DISABLE ((uint8_t)(0))\r
-/** I2S MCLK Enable bit */\r
-#define I2S_MCLK_ENABLE ((uint8_t)(1))\r
-#define I2S_MCLK_DISABLE ((uint8_t)(0))\r
-/** I2S select DMA bit */\r
-#define I2S_DMA_1 ((uint8_t)(0))\r
-#define I2S_DMA_2 ((uint8_t)(1))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DAO-Digital Audio Output register\r
- **********************************************************************/\r
-/** I2S wordwide - the number of bytes in data*/\r
-#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */\r
-#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */\r
-#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */\r
-/** I2S control mono or stereo format */\r
-#define I2S_DAO_MONO ((uint32_t)(1<<2))\r
-/** I2S control stop mode */\r
-#define I2S_DAO_STOP ((uint32_t)(1<<3))\r
-/** I2S control reset mode */\r
-#define I2S_DAO_RESET ((uint32_t)(1<<4))\r
-/** I2S control master/slave mode */\r
-#define I2S_DAO_SLAVE ((uint32_t)(1<<5))\r
-/** I2S word select half period minus one */\r
-#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))\r
-/** I2S control mute mode */\r
-#define I2S_DAO_MUTE ((uint32_t)(1<<15))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DAI-Digital Audio Input register\r
-**********************************************************************/\r
-/** I2S wordwide - the number of bytes in data*/\r
-#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */\r
-#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */\r
-#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */\r
-/** I2S control mono or stereo format */\r
-#define I2S_DAI_MONO ((uint32_t)(1<<2))\r
-/** I2S control stop mode */\r
-#define I2S_DAI_STOP ((uint32_t)(1<<3))\r
-/** I2S control reset mode */\r
-#define I2S_DAI_RESET ((uint32_t)(1<<4))\r
-/** I2S control master/slave mode */\r
-#define I2S_DAI_SLAVE ((uint32_t)(1<<5))\r
-/** I2S word select half period minus one (9 bits)*/\r
-#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))\r
-/** I2S control mute mode */\r
-#define I2S_DAI_MUTE ((uint32_t)(1<<15))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for STAT register (Status Feedback register)\r
-**********************************************************************/\r
-/** I2S Status Receive or Transmit Interrupt */\r
-#define I2S_STATE_IRQ ((uint32_t)(1))\r
-/** I2S Status Receive or Transmit DMA1 */\r
-#define I2S_STATE_DMA1 ((uint32_t)(1<<1))\r
-/** I2S Status Receive or Transmit DMA2 */\r
-#define I2S_STATE_DMA2 ((uint32_t)(1<<2))\r
-/** I2S Status Current level of the Receive FIFO (5 bits)*/\r
-#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))\r
-/** I2S Status Current level of the Transmit FIFO (5 bits)*/\r
-#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA1 register (DMA1 Configuration register)\r
-**********************************************************************/\r
-/** I2S control DMA1 for I2S receive */\r
-#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))\r
-/** I2S control DMA1 for I2S transmit */\r
-#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))\r
-/** I2S set FIFO level that trigger a receive DMA request on DMA1 */\r
-#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))\r
-/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */\r
-#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMA2 register (DMA2 Configuration register)\r
-**********************************************************************/\r
-/** I2S control DMA2 for I2S receive */\r
-#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))\r
-/** I2S control DMA1 for I2S transmit */\r
-#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))\r
-/** I2S set FIFO level that trigger a receive DMA request on DMA1 */\r
-#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))\r
-/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */\r
-#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))\r
-\r
-/*********************************************************************//**\r
-* Macro defines for IRQ register (Interrupt Request Control register)\r
-**********************************************************************/\r
-/** I2S control I2S receive interrupt */\r
-#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))\r
-/** I2S control I2S transmit interrupt */\r
-#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))\r
-/** I2S set the FIFO level on which to create an irq request */\r
-#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))\r
-/** I2S set the FIFO level on which to create an irq request */\r
-#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))\r
-\r
-/********************************************************************************//**\r
- * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)\r
-*********************************************************************************/\r
-/** I2S Transmit MCLK rate denominator */\r
-#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))\r
-/** I2S Transmit MCLK rate denominator */\r
-#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))\r
-/** I2S Receive MCLK rate denominator */\r
-#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))\r
-/** I2S Receive MCLK rate denominator */\r
-#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))\r
-\r
-/*************************************************************************************//**\r
- * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)\r
-**************************************************************************************/\r
-#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))\r
-#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))\r
-\r
-/**********************************************************************************//**\r
- * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)\r
-************************************************************************************/\r
-/** I2S Transmit select clock source (2 bits)*/\r
-#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))\r
-/** I2S Transmit control 4-pin mode */\r
-#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))\r
-/** I2S Transmit control the TX_MCLK output */\r
-#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))\r
-/** I2S Receive select clock source */\r
-#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))\r
-/** I2S Receive control 4-pin mode */\r
-#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))\r
-/** I2S Receive control the TX_MCLK output */\r
-#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))\r
-\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-/** Macro to determine if it is valid I2S peripheral */\r
-#define PARAM_I2Sx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2S0)) || (((uint32_t *)n)==((uint32_t *)LPC_I2S1)))\r
-/** Macro to check Data to send valid */\r
-#define PRAM_I2S_FREQ(freq) ((freq>=8000)&&(freq <= 96000))\r
-/* Macro check I2S word width type */\r
-#define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\\r
-||(n==I2S_WORDWIDTH_32))\r
-/* Macro check I2S channel type */\r
-#define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))\r
-/* Macro check I2S master/slave mode */\r
-#define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))\r
-/* Macro check I2S stop mode */\r
-#define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))\r
-/* Macro check I2S reset mode */\r
-#define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))\r
-/* Macro check I2S reset mode */\r
-#define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))\r
-/* Macro check I2S transmit/receive mode */\r
-#define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))\r
-/* Macro check I2S clock select mode */\r
-#define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))\r
-/* Macro check I2S 4-pin mode */\r
-#define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))\r
-/* Macro check I2S MCLK mode */\r
-#define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))\r
-/* Macro check I2S DMA mode */\r
-#define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))\r
-/* Macro check I2S DMA depth value */\r
-#define PARAM_I2S_DMA_DEPTH(n) ((n<=31))\r
-/* Macro check I2S irq level value */\r
-#define PARAM_I2S_IRQ_LEVEL(n) ((n<=31))\r
-/* Macro check I2S half-period value */\r
-#define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512))\r
-/* Macro check I2S bit-rate value */\r
-#define PARAM_I2S_BITRATE(n) ((n<=63))\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup I2S_Public_Types I2S Public Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief I2S configuration structure definition\r
- */\r
-typedef struct {\r
- uint8_t wordwidth; /** the number of bytes in data as follow:\r
- -I2S_WORDWIDTH_8: 8 bit data\r
- -I2S_WORDWIDTH_16: 16 bit data\r
- -I2S_WORDWIDTH_32: 32 bit data */\r
- uint8_t mono; /** Set mono/stereo mode, should be:\r
- - I2S_STEREO: stereo mode\r
- - I2S_MONO: mono mode */\r
- uint8_t stop; /** Disables accesses on FIFOs, should be:\r
- - I2S_STOP_ENABLE: enable stop mode\r
- - I2S_STOP_DISABLE: disable stop mode */\r
- uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:\r
- - I2S_RESET_ENABLE: enable reset mode\r
- - I2S_RESET_DISABLE: disable reset mode */\r
- uint8_t ws_sel; /** Set Master/Slave mode, should be:\r
- - I2S_MASTER_MODE: I2S master mode\r
- - I2S_SLAVE_MODE: I2S slave mode */\r
- uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:\r
- - I2S_MUTE_ENABLE: enable mute mode\r
- - I2S_MUTE_DISABLE: disable mute mode */\r
- uint8_t Reserved0[2];\r
-} I2S_CFG_Type;\r
-\r
-/**\r
- * @brief I2S DMA configuration structure definition\r
- */\r
-typedef struct {\r
- uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:\r
- - I2S_DMA_1: DMA1\r
- - I2S_DMA_2: DMA2 */\r
- uint8_t depth; /** FIFO level that triggers a DMA request */\r
- uint8_t Reserved0[2];\r
-}I2S_DMAConf_Type;\r
-\r
-/**\r
- * @brief I2S mode configuration structure definition\r
- */\r
-typedef struct{\r
- uint8_t clksel; /** Clock source selection, should be:\r
- - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output\r
- - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */\r
- uint8_t fpin; /** Select four pin mode, should be:\r
- - I2S_4PIN_ENABLE: 4-pin enable\r
- - I2S_4PIN_DISABLE: 4-pin disable */\r
- uint8_t mcena; /** Select MCLK mode, should be:\r
- - I2S_MCLK_ENABLE: MCLK enable for output\r
- - I2S_MCLK_DISABLE: MCLK disable for output */\r
- uint8_t Reserved;\r
-}I2S_MODEConf_Type;\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup I2S_Public_Functions I2S Public Functions\r
- * @{\r
- */\r
-/* I2S Init/DeInit functions ---------*/\r
-void I2S_Init(LPC_I2Sn_Type *I2Sx);\r
-void I2S_DeInit(LPC_I2Sn_Type *I2Sx);\r
-\r
-/* I2S configuration functions --------*/\r
-void I2S_Config(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);\r
-Status I2S_FreqConfig(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode);\r
-void I2S_SetBitRate(LPC_I2Sn_Type *I2Sx, uint8_t bitrate, uint8_t TRMode);\r
-void I2S_ModeConfig(LPC_I2Sn_Type *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);\r
-uint8_t I2S_GetLevel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);\r
-\r
-/* I2S operate functions -------------*/\r
-void I2S_Send(LPC_I2Sn_Type *I2Sx, uint32_t BufferData);\r
-uint32_t I2S_Receive(LPC_I2Sn_Type* I2Sx);\r
-void I2S_Start(LPC_I2Sn_Type *I2Sx);\r
-void I2S_Pause(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);\r
-void I2S_Mute(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);\r
-void I2S_Stop(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);\r
-\r
-/* I2S DMA functions ----------------*/\r
-void I2S_DMAConfig(LPC_I2Sn_Type *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);\r
-void I2S_DMACmd(LPC_I2Sn_Type *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);\r
-\r
-/* I2S IRQ functions ----------------*/\r
-void I2S_IRQCmd(LPC_I2Sn_Type *I2Sx,uint8_t TRMode, FunctionalState NewState);\r
-void I2S_IRQConfig(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, uint8_t level);\r
-FunctionalState I2S_GetIRQStatus(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);\r
-uint8_t I2S_GetIRQDepth(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* LPC18XX_I2S_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_lcd.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_lcd.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for LCD Driver\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup LCD LCD\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef __LPC18XX_LCD_H_\r
-#define __LPC18XX_LCD_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup LCD_Private_Macros LCD Private Macros\r
- * @{\r
- */\r
-\r
-/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
-/* LCD control enable bit */\r
-#define CLCDC_LCDCTRL_ENABLE _BIT(0)\r
-/* LCD control power enable bit */\r
-#define CLCDC_LCDCTRL_PWR _BIT(11)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup LCD_Public_Types LCD Public Types\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief LCD enumeration\r
- **********************************************************************/\r
-\r
-/** @brief LCD Interrupt Source */\r
-typedef enum{\r
- LCD_INT_FUF = _BIT(1), /* FIFO underflow bit */\r
- LCD_INT_LNBU = _BIT(2), /* LCD next base address update bit */\r
- LCD_INT_VCOMP = _BIT(3), /* vertical compare bit */\r
- LCD_INT_BER = _BIT(4) /* AHB master error interrupt bit */\r
-} LCD_INT_SRC;\r
-\r
-/** @brief LCD signal polarity */\r
-typedef enum {\r
- LCD_SIGNAL_ACTIVE_HIGH = 0,\r
- LCD_SIGNAL_ACTIVE_LOW = 1\r
-} LCD_SIGNAL_POLARITY_OPT;\r
-\r
-/** @brief LCD clock edge polarity */\r
-typedef enum {\r
- LCD_CLK_RISING = 0,\r
- LCD_CLK_FALLING= 1\r
-} LCD_CLK_EDGE_OPT;\r
-\r
-/** @brief LCD bits per pixel and pixel format */\r
-typedef enum {\r
- LCD_BPP1 = 0,\r
- LCD_BPP2,\r
- LCD_BPP4,\r
- LCD_BPP8,\r
- LCD_BPP16,\r
- LCD_BPP24,\r
- LCD_BPP16_565,\r
- LCD_BPP12_444\r
-}LCD_PIXEL_FORMAT_OPT;\r
-\r
-/** @brief LCD color format */\r
-typedef enum {\r
- LCD_COLOR_FORMAT_RGB = 0,\r
- LCD_COLOR_FORMAT_BGR\r
-}LCD_COLOR_FORMAT_OPT;\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief LCD structure definitions\r
- **********************************************************************/\r
-/** @brief LCD Palette entry format */\r
-typedef struct\r
-{\r
- uint32_t Rl:5;\r
- uint32_t Gl:5;\r
- uint32_t Bl:5;\r
- uint32_t Il:1;\r
- uint32_t Ru:5;\r
- uint32_t Gu:5;\r
- uint32_t Bu:5;\r
- uint32_t Iu:1;\r
-} LCD_PALETTE_ENTRY_Type;\r
-\r
-/** @brief LCD cursor format in 1 byte LBBP */\r
-typedef struct\r
-{\r
- uint8_t Pixel3:2;\r
- uint8_t Pixel2:2;\r
- uint8_t Pixel1:2;\r
- uint8_t Pixel0:2;\r
-} LCD_CURSOR_PIXEL_Type;\r
-\r
-/** @brief LCD cursor size */\r
-typedef enum\r
-{\r
- LCD_CURSOR_32x32 = 0,\r
- LCD_CURSOR_64x64\r
-} LCD_CURSOR_SIZE_OPT;\r
-\r
-/** @brief LCD panel type */\r
-typedef enum\r
-{\r
- LCD_TFT = 0x02, /* standard TFT */\r
- LCD_MONO_4 = 0x01, /* 4-bit STN mono */\r
- LCD_MONO_8 = 0x05, /* 8-bit STN mono */\r
- LCD_CSTN = 0x00 /* color STN */\r
-} LCD_PANEL_OPT;\r
-\r
-/** @brief LCD porch configuration structure */\r
-typedef struct {\r
- uint16_t front; /* front porch setting in clocks */\r
- uint16_t back; /* back porch setting in clocks */\r
-}LCD_PORCHCFG_Type;\r
-\r
-/** @brief LCD configuration structure */\r
-typedef struct {\r
- uint16_t screen_width; /* Pixels per line */\r
- uint16_t screen_height; /* Lines per panel */\r
- LCD_PORCHCFG_Type horizontal_porch; /* porch setting for horizontal */\r
- LCD_PORCHCFG_Type vertical_porch; /* porch setting for vertical */\r
- uint16_t HSync_pulse_width; /* HSYNC pulse width in clocks */\r
- uint16_t VSync_pulse_width; /* VSYNC pulse width in clocks */\r
- uint8_t ac_bias_frequency; /* AC bias frequency in clocks */\r
- LCD_SIGNAL_POLARITY_OPT HSync_pol; /* HSYNC polarity */\r
- LCD_SIGNAL_POLARITY_OPT VSync_pol; /* VSYNC polarity */\r
- LCD_CLK_EDGE_OPT panel_clk_edge; /* Panel Clock Edge Polarity */\r
- LCD_SIGNAL_POLARITY_OPT OE_pol; /* Output Enable polarity */\r
- uint32_t line_end_delay; /* 0 if not use */\r
- LCD_PIXEL_FORMAT_OPT bits_per_pixel; /* Maximum bits per pixel the display supports */\r
- LCD_PANEL_OPT lcd_panel_type; /* LCD panel type */\r
- LCD_COLOR_FORMAT_OPT color_format; /* BGR or RGB */\r
- Bool dual_panel; /* Dual panel, TRUE = dual panel display */\r
- uint16_t pcd;\r
-} LCD_CFG_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup LCD_Public_Functions LCD Public Functions\r
- * @{\r
- */\r
-\r
-void LCD_Init(LPC_LCD_Type *LCDx, LCD_CFG_Type *LCD_ConfigStruct);\r
-void LCD_DeInit(LPC_LCD_Type *LCDx);\r
-\r
-void LCD_Power(LPC_LCD_Type *LCDx, FunctionalState OnOff);\r
-void LCD_Enable(LPC_LCD_Type *LCDx, FunctionalState EnDis);\r
-void LCD_SetFrameBuffer(LPC_LCD_Type *LCDx, void* buffer);\r
-void LCD_SetLPFrameBuffer(LPC_LCD_Type *LCDx, void* buffer);\r
-void LCD_LoadPalette(LPC_LCD_Type *LCDx, void* palette);\r
-void LCD_SetInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int);\r
-void LCD_ClrInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int);\r
-LCD_INT_SRC LCD_GetInterrupt(LPC_LCD_Type *LCDx);\r
-\r
-void LCD_Cursor_Config(LPC_LCD_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, Bool sync);\r
-void LCD_Cursor_WriteImage(LPC_LCD_Type *LCDx, uint8_t cursor_num, void* Image);\r
-void* LCD_Cursor_GetImageBufferAddress(LPC_LCD_Type *LCDx, uint8_t cursor_num);\r
-void LCD_Cursor_Enable(LPC_LCD_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff);\r
-void LCD_Cursor_LoadPalette0(LPC_LCD_Type *LCDx, uint32_t palette_color);\r
-void LCD_Cursor_LoadPalette1(LPC_LCD_Type *LCDx, uint32_t palette_color);\r
-void LCD_Cursor_SetInterrupt(LPC_LCD_Type *LCDx);\r
-void LCD_Cursor_ClrInterrupt(LPC_LCD_Type *LCDx);\r
-void LCD_Cursor_SetPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y);\r
-void LCD_Cursor_SetClipPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __LPC18XX_LCD_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/*\r
- * Modified for Code Red tools to prevent redefinition of DEBUG macro\r
- * 2011/12/29\r
- */\r
-/**********************************************************************\r
-* $Id$ lpc18xx_libcfg_default.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_libcfg_default.h\r
-* @brief Default Library configuration header file\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Library Configuration group ----------------------------------------------------------- */\r
-/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_LIBCFG_DEFAULT_H_\r
-#define LPC18XX_LIBCFG_DEFAULT_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc_types.h"\r
-\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros\r
- * @{\r
- */\r
-\r
-/************************** DEBUG MODE DEFINITIONS *********************************/\r
-/* Un-comment the line below to compile the library in DEBUG mode, this will expanse\r
- the "CHECK_PARAM" macro in the FW library code */\r
-\r
-#ifndef __CODE_RED\r
-#define DEBUG\r
-#endif\r
-\r
-\r
-/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/\r
-\r
-/* Comment the line below to disable the specific peripheral inclusion */\r
-\r
-/* GPIO ------------------------------- */\r
-#define _GPIO\r
-\r
-/* EXTI ------------------------------- */\r
-#define _EXTI\r
-\r
-/* UART ------------------------------- */\r
-#define _UART\r
-#define _UART0\r
-#define _UART1\r
-#define _UART2\r
-#define _UART3\r
-\r
-/* SPI ------------------------------- */\r
-#define _SPI\r
-\r
-/* SYSTICK --------------------------- */\r
-#define _SYSTICK\r
-\r
-/* SSP ------------------------------- */\r
-#define _SSP\r
-#define _SSP0\r
-#define _SSP1\r
-\r
-\r
-/* I2C ------------------------------- */\r
-#define _I2C\r
-#define _I2C0\r
-#define _I2C1\r
-#define _I2C2\r
-\r
-/* TIMER ------------------------------- */\r
-#define _TIM\r
-\r
-/* WWDT ------------------------------- */\r
-#define _WWDT\r
-\r
-\r
-/* GPDMA ------------------------------- */\r
-#define _GPDMA\r
-\r
-\r
-/* DAC ------------------------------- */\r
-#define _DAC\r
-\r
-/* DAC ------------------------------- */\r
-#define _ADC\r
-\r
-\r
-/* PWM ------------------------------- */\r
-#define _PWM\r
-#define _PWM1\r
-\r
-/* RTC ------------------------------- */\r
-#define _RTC\r
-\r
-/* I2S ------------------------------- */\r
-#define _I2S\r
-\r
-/* USB device ------------------------------- */\r
-#define _USBDEV\r
-#define _USB_DMA\r
-\r
-/* QEI ------------------------------- */\r
-#define _QEI\r
-\r
-/* MCPWM ------------------------------- */\r
-#define _MCPWM\r
-\r
-/* CAN--------------------------------*/\r
-#define _C_CAN\r
-\r
-/* RIT ------------------------------- */\r
-#define _RIT\r
-\r
-/* EMAC ------------------------------ */\r
-#define _EMAC\r
-\r
-/* SCT ------------------------------ */\r
-#define _SCT\r
-\r
-/* LCD ------------------------------ */\r
-#define _LCD\r
-\r
-/* ATIMER ------------------------------ */\r
-#define _ATIMER\r
-\r
-/* RGU ------------------------------ */\r
-#define _RGU\r
-\r
-/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/\r
-\r
-#ifdef DEBUG\r
-/*******************************************************************************\r
-* @brief The CHECK_PARAM macro is used for function's parameters check.\r
-* It is used only if the library is compiled in DEBUG mode.\r
-* @param[in] expr - If expr is false, it calls check_failed() function\r
-* which reports the name of the source file and the source\r
-* line number of the call that failed.\r
-* - If expr is true, it returns no value.\r
-* @return None\r
-*******************************************************************************/\r
-#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))\r
-#else\r
-#define CHECK_PARAM(expr)\r
-#endif /* DEBUG */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions\r
- * @{\r
- */\r
-\r
-#ifdef DEBUG\r
-void check_failed(uint8_t *file, uint32_t line);\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* LPC18XX_LIBCFG_DEFAULT_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_mcpwm.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_mcpwm.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for Motor Control PWM firmware library on LPC18XX\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup MCPWM MCPWM (Motor Control PWM)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_MCPWM_H_\r
-#define LPC18XX_MCPWM_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup MCPWM_Private_Macros MCPWM Private Macros\r
- * @{\r
- */\r
-/** Edge aligned mode for channel in MCPWM */\r
-#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))\r
-/** Center aligned mode for channel in MCPWM */\r
-#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))\r
-\r
-/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */\r
-#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))\r
-/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */\r
-#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))\r
-\r
-/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of\r
- * the six output pins under the control of the bits in this register */\r
-#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */\r
-#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */\r
-#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */\r
-#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */\r
-#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */\r
-#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */\r
-\r
-/* Interrupt type in MCPWM */\r
-/** Limit interrupt for channel (0) */\r
-#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)\r
-/** Match interrupt for channel (0) */\r
-#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)\r
-/** Capture interrupt for channel (0) */\r
-#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)\r
-\r
-/** Limit interrupt for channel (1) */\r
-#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)\r
-/** Match interrupt for channel (1) */\r
-#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)\r
-/** Capture interrupt for channel (1) */\r
-#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)\r
-\r
-/** Limit interrupt for channel (2) */\r
-#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)\r
-/** Match interrupt for channel (2) */\r
-#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)\r
-/** Capture interrupt for channel (2) */\r
-#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)\r
-\r
-/** Fast abort interrupt */\r
-#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT\r
-\r
-/*********************************************************************//**\r
- * Macro defines for MCPWM Control register\r
- **********************************************************************/\r
-/* MCPWM Control register, these macro definitions below can be applied for these\r
- * register type:\r
- * - MCPWM Control read address\r
- * - MCPWM Control set address\r
- * - MCPWM Control clear address\r
- */\r
-/**< Stops/starts timer channel n */\r
-#define MCPWM_CON_RUN(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0))\r
-/**< Edge/center aligned operation for channel n */\r
-#define MCPWM_CON_CENTER(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0))\r
-/**< Select polarity of the MCOAn and MCOBn pin */\r
-#define MCPWM_CON_POLAR(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0))\r
-/**< Control the dead-time feature for channel n */\r
-#define MCPWM_CON_DTE(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0))\r
-/**< Enable/Disable update of functional register for channel n */\r
-#define MCPWM_CON_DISUP(n) (((n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0))\r
-/**< Control the polarity for all 3 channels */\r
-#define MCPWM_CON_INVBDC ((uint32_t)(1<<29))\r
-/**< 3-phase AC mode select */\r
-#define MCPWM_CON_ACMODE ((uint32_t)(1<<30))\r
-/**< 3-phase DC mode select */\r
-#define MCPWM_CON_DCMODE (((uint32_t)1<<31))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for MCPWM Capture Control register\r
- **********************************************************************/\r
-/* Capture Control register, these macro definitions below can be applied for these\r
- * register type:\r
- * - MCPWM Capture Control read address\r
- * - MCPWM Capture Control set address\r
- * - MCPWM Capture control clear address\r
- */\r
-/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */\r
-#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))\r
-/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */\r
-#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))\r
-/** TC(n) is reset by channel (n) capture event */\r
-#define MCPWM_CAPCON_RT(n) (((n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0))\r
-/** Hardware noise filter: channel (n) capture events are delayed */\r
-#define MCPWM_CAPCON_HNFCAP(n) (((n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for MCPWM Interrupt register\r
- **********************************************************************/\r
-/* Interrupt registers, these macro definitions below can be applied for these\r
- * register type:\r
- * - MCPWM Interrupt Enable read address\r
- * - MCPWM Interrupt Enable set address\r
- * - MCPWM Interrupt Enable clear address\r
- * - MCPWM Interrupt Flags read address\r
- * - MCPWM Interrupt Flags set address\r
- * - MCPWM Interrupt Flags clear address\r
- */\r
-/** Limit interrupt for channel (n) */\r
-#define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))\r
-/** Match interrupt for channel (n) */\r
-#define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))\r
-/** Capture interrupt for channel (n) */\r
-#define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))\r
-/** Fast abort interrupt */\r
-#define MCPWM_INT_ABORT ((uint32_t)(1<<15))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for MCPWM Count Control register\r
- **********************************************************************/\r
-/* MCPWM Count Control register, these macro definitions below can be applied for these\r
- * register type:\r
- * - MCPWM Count Control read address\r
- * - MCPWM Count Control set address\r
- * - MCPWM Count Control clear address\r
- */\r
-/** Counter(tc) advances on a rising edge on MCI(mci) pin */\r
-#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))\r
-/** Counter(cnt) advances on a falling edge on MCI(mci) pin */\r
-#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))\r
-/** Channel (n) is in counter mode */\r
-#define MCPWM_CNTCON_CNTR(n) (((n<=2)) ? ((uint32_t)(1<<(29+n))) : (0))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for MCPWM Dead-time register\r
- **********************************************************************/\r
-/** Dead time value x for channel n */\r
-#define MCPWM_DT(n,x) (((n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for MCPWM Communication Pattern register\r
- **********************************************************************/\r
-#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */\r
-#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */\r
-#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */\r
-#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */\r
-#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */\r
-#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for MCPWM Capture clear address register\r
- **********************************************************************/\r
-/** Clear the MCCAP (n) register */\r
-#define MCPWM_CAPCLR_CAP(n) (((n<=2)) ? ((uint32_t)(1<<n)) : (0))\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup MCPWM_Public_Types MCPWM Public Types\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief MCPWM enumeration\r
- **********************************************************************/\r
-/**\r
- * @brief MCPWM channel identifier definition\r
- */\r
-typedef enum\r
-{\r
- MCPWM_CHANNEL_0 = 0, /**< MCPWM channel 0 */\r
- MCPWM_CHANNEL_1, /**< MCPWM channel 1 */\r
- MCPWM_CHANNEL_2 /**< MCPWM channel 2 */\r
-} en_MCPWM_Channel_Id;\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief MCPWM structure definitions\r
- **********************************************************************/\r
-/**\r
- * @brief Motor Control PWM Channel Configuration structure type definition\r
- */\r
-typedef struct {\r
- uint32_t channelType; /**< Edge/center aligned mode for this channel,\r
- should be:\r
- - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode\r
- - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode\r
- */\r
- uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be:\r
- - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH\r
- - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW\r
- */\r
- uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be:\r
- - ENABLE.\r
- - DISABLE.\r
- */\r
- uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */\r
- uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers,\r
- should be:\r
- - ENABLE.\r
- - DISABLE.\r
- */\r
- uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */\r
- uint32_t channelPeriodValue; /**< MCPWM Period value */\r
- uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */\r
-} MCPWM_CHANNEL_CFG_Type;\r
-\r
-/**\r
- * @brief MCPWM Capture Configuration type definition\r
- */\r
-typedef struct {\r
- uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */\r
- uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be:\r
- - ENABLE.\r
- - DISABLE.\r
- */\r
- uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be:\r
- - ENABLE.\r
- - DISABLE.\r
- */\r
- uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be:\r
- - ENABLE.\r
- - DISABLE.\r
- */\r
- uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be:\r
- - ENABLE.\r
- - DISABLE.\r
- */\r
-} MCPWM_CAPTURE_CFG_Type;\r
-\r
-\r
-/**\r
- * @brief MCPWM Count Control Configuration type definition\r
- */\r
-typedef struct {\r
- uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */\r
- uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be:\r
- - ENABLE.\r
- - DISABLE.\r
- */\r
- uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be:\r
- - ENABLE.\r
- - DISABLE.\r
- */\r
-} MCPWM_COUNT_CFG_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup MCPWM_Public_Functions MCPWM Public Functions\r
- * @{\r
- */\r
-\r
-void MCPWM_Init(LPC_MCPWM_Type *MCPWMx);\r
-void MCPWM_ConfigChannel(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,\r
- MCPWM_CHANNEL_CFG_Type * channelSetup);\r
-void MCPWM_WriteToShadow(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,\r
- MCPWM_CHANNEL_CFG_Type *channelSetup);\r
-void MCPWM_ConfigCapture(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,\r
- MCPWM_CAPTURE_CFG_Type *captureConfig);\r
-void MCPWM_ClearCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);\r
-uint32_t MCPWM_GetCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);\r
-void MCPWM_CountConfig(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,\r
- uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);\r
-void MCPWM_Start(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);\r
-void MCPWM_Stop(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);\r
-void MCPWM_ACMode(LPC_MCPWM_Type *MCPWMx,uint32_t acMode);\r
-void MCPWM_DCMode(LPC_MCPWM_Type *MCPWMx, uint32_t dcMode,\r
- uint32_t outputInvered, uint32_t outputPattern);\r
-void MCPWM_IntConfig(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType, FunctionalState NewState);\r
-void MCPWM_IntSet(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);\r
-void MCPWM_IntClear(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);\r
-FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_MCPWM_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_nvic.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_nvic.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for Nesting Vectored Interrupt firmware library\r
-* on LPC18XX\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup NVIC NVIC (Nested Vector Interrupt Controller)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_NVIC_H_\r
-#define LPC18XX_NVIC_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup NVIC_Public_Functions NVIC Public Functions\r
- * @{\r
- */\r
-\r
-void NVIC_SetVTOR(uint32_t offset);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_NVIC_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_pwr.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_pwr.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for Power Control firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup PWR PWR (Power Control)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_PWR_H_\r
-#define LPC18XX_PWR_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup PWR_Private_Macros PWR Private Macros\r
- * @{\r
- */\r
-#define PWR_SLEEP_MODE_DEEP_SLEEP 0x3F00AA\r
-#define PWR_SLEEP_MODE_POWER_DOWN 0x30FCBA\r
-#define PWR_SLEEP_MODE_DEEP_POWER_DOWN 0x3FFF7F\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup PWR_Public_Functions PWR Public Functions\r
- * @{\r
- */\r
-/* Clock Generator */\r
-void PWR_Sleep(void);\r
-void PWR_DeepSleep(void);\r
-void PWR_PowerDown(void);\r
-void PWR_DeepPowerDown(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_PWR_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_qei.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_qei.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for QEI firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup QEI QEI (Quadrature Encoder Interface)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_QEI_H_\r
-#define LPC18XX_QEI_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup QEI_Private_Macros QEI Private Macros\r
- * @{\r
- */\r
-\r
-/** QEI peripheral numver definition */\r
-#define QEI_0 (0) /** Always 0 - because we just have only one QEI peripheral */\r
-\r
-/** QEI Reset types */\r
-#define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */\r
-#define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */\r
-#define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */\r
-#define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */\r
-\r
-/** QEI Direction Invert Type Option */\r
-#define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */\r
-#define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */\r
-\r
-/** QEI Signal Mode Option */\r
-#define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */\r
-#define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */\r
-\r
-/** QEI Capture Mode Option */\r
-#define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */\r
-#define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/\r
-\r
-/** QEI Invert Index Signal Option */\r
-#define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */\r
-#define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */\r
-\r
-/** QEI timer reload option */\r
-#define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */\r
-#define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */\r
-\r
-/** QEI Flag Status type */\r
-#define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */\r
-\r
-/** QEI Compare Position channel option */\r
-#define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */\r
-#define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */\r
-#define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */\r
-\r
-/** QEI interrupt flag type */\r
-#define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */\r
-#define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */\r
-#define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */\r
-#define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */\r
-#define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */\r
-#define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */\r
-#define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the\r
- current position interrupt */\r
-#define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the\r
- current position interrupt */\r
-#define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the\r
- current position interrupt */\r
-#define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current\r
- index count interrupt */\r
-#define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */\r
-#define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */\r
-#define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */\r
-\r
-\r
-/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
-/* Quadrature Encoder Interface Control Register Definition --------------------- */\r
-/*********************************************************************//**\r
- * Macro defines for QEI Control register\r
- **********************************************************************/\r
-#define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */\r
-#define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */\r
-#define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */\r
-#define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */\r
-#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for QEI Configuration register\r
- **********************************************************************/\r
-#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */\r
-#define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */\r
-#define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */\r
-#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */\r
-#define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for QEI Status register\r
- **********************************************************************/\r
-#define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */\r
-#define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */\r
-\r
-/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */\r
-/*********************************************************************//**\r
- * Macro defines for QEI Interrupt Status register\r
- **********************************************************************/\r
-#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */\r
-#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */\r
-#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */\r
-#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */\r
-#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */\r
-#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */\r
-#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the\r
- current position */\r
-#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the\r
- current position */\r
-#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the\r
- current position */\r
-#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current\r
- index count */\r
-#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when\r
- both the POS0_Int bit is set and the REV_Int is set */\r
-#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when\r
- both the POS1_Int bit is set and the REV_Int is set */\r
-#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when\r
- both the POS2_Int bit is set and the REV_Int is set */\r
-#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for QEI Interrupt Set register\r
- **********************************************************************/\r
-#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */\r
-#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */\r
-#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */\r
-#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */\r
-#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */\r
-#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */\r
-#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the\r
- current position */\r
-#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the\r
- current position */\r
-#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the\r
- current position */\r
-#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current\r
- index count */\r
-#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */\r
-#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */\r
-#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */\r
-#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for QEI Interrupt Clear register\r
- **********************************************************************/\r
-#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */\r
-#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */\r
-#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */\r
-#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */\r
-#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */\r
-#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */\r
-#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the\r
- current position */\r
-#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the\r
- current position */\r
-#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the\r
- current position */\r
-#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current\r
- index count */\r
-#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */\r
-#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */\r
-#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */\r
-#define QEI_INTCLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Clear register bit-mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for QEI Interrupt Enable register\r
- **********************************************************************/\r
-#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */\r
-#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */\r
-#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */\r
-#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */\r
-#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */\r
-#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */\r
-#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the\r
- current position */\r
-#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the\r
- current position */\r
-#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the\r
- current position */\r
-#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current\r
- index count */\r
-#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */\r
-#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */\r
-#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */\r
-#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for QEI Interrupt Enable Set register\r
- **********************************************************************/\r
-#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */\r
-#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */\r
-#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */\r
-#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */\r
-#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */\r
-#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */\r
-#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the\r
- current position */\r
-#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the\r
- current position */\r
-#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the\r
- current position */\r
-#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current\r
- index count */\r
-#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */\r
-#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */\r
-#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */\r
-#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for QEI Interrupt Enable Clear register\r
- **********************************************************************/\r
-#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */\r
-#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */\r
-#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */\r
-#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */\r
-#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */\r
-#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */\r
-#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the\r
- current position */\r
-#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the\r
- current position */\r
-#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the\r
- current position */\r
-#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current\r
- index count */\r
-#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */\r
-#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */\r
-#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */\r
-#define QEI_IECLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Enable Clear register bit-mask */\r
-\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-/* Macro check QEI peripheral */\r
-#define PARAM_QEIx(n) ((n==LPC_QEI))\r
-\r
-/* Macro check QEI reset type */\r
-#define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \\r
-|| (n==QEI_RESET_POSOnIDX) \\r
-|| (n==QEI_RESET_VEL) \\r
-|| (n==QEI_RESET_IDX))\r
-\r
-/* Macro check QEI Direction invert mode */\r
-#define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))\r
-\r
-/* Macro check QEI signal mode */\r
-#define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))\r
-\r
-/* Macro check QEI Capture mode */\r
-#define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))\r
-\r
-/* Macro check QEI Invert index mode */\r
-#define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))\r
-\r
-/* Macro check QEI Direction invert mode */\r
-#define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))\r
-\r
-/* Macro check QEI status type */\r
-#define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR))\r
-\r
-/* Macro check QEI combine position type */\r
-#define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))\r
-\r
-/* Macro check QEI interrupt flag type */\r
-#define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \\r
-|| (n==QEI_INTFLAG_TIM_Int) \\r
-|| (n==QEI_INTFLAG_VELC_Int) \\r
-|| (n==QEI_INTFLAG_DIR_Int) \\r
-|| (n==QEI_INTFLAG_ERR_Int) \\r
-|| (n==QEI_INTFLAG_ENCLK_Int) \\r
-|| (n==QEI_INTFLAG_POS0_Int) \\r
-|| (n==QEI_INTFLAG_POS1_Int) \\r
-|| (n==QEI_INTFLAG_POS2_Int) \\r
-|| (n==QEI_INTFLAG_REV_Int) \\r
-|| (n==QEI_INTFLAG_POS0REV_Int) \\r
-|| (n==QEI_INTFLAG_POS1REV_Int) \\r
-|| (n==QEI_INTFLAG_POS2REV_Int))\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup QEI_Public_Types QEI Public Types\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief QEI structure definitions\r
- **********************************************************************/\r
-/**\r
- * @brief QEI Configuration structure type definition\r
- */\r
-typedef struct {\r
- uint32_t DirectionInvert :1; /**< Direction invert option:\r
- - QEI_DIRINV_NONE: QEI Direction is normal\r
- - QEI_DIRINV_CMPL: QEI Direction is complemented\r
- */\r
- uint32_t SignalMode :1; /**< Signal mode Option:\r
- - QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode\r
- - QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode\r
- */\r
- uint32_t CaptureMode :1; /**< Capture Mode Option:\r
- - QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)\r
- - QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)\r
- */\r
- uint32_t InvertIndex :1; /**< Invert Index Option:\r
- - QEI_INVINX_NONE: the sense of the index input is normal\r
- - QEI_INVINX_EN: inverts the sense of the index input\r
- */\r
-} QEI_CFG_Type;\r
-\r
-/**\r
- * @brief Timer Reload Configuration structure type definition\r
- */\r
-typedef struct {\r
-\r
- uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be:\r
- - QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value\r
- - QEI_TIMERRELOAD_USVAL: Reload value in microsecond value\r
- */\r
- uint8_t Reserved[3];\r
- uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched\r
- with Velocity Timer Reload Option\r
- */\r
-} QEI_RELOADCFG_Type;\r
-\r
-typedef struct\r
-{\r
- uint32_t PHA_FilterVal; /**< FILTERPHA register input */\r
- uint32_t PHB_FilterVal; /**< FILTERPHB register input */\r
- uint32_t INX_FilterVal; /**< FILTERINX register input */\r
-} st_Qei_FilterCfg;\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup QEI_Public_Functions QEI Public Functions\r
- * @{\r
- */\r
-\r
-void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct);\r
-void QEI_DeInit(uint8_t qeiId);\r
-\r
-void QEI_Reset(uint8_t qeiId, uint32_t ulResetType);\r
-void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct);\r
-FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType);\r
-uint32_t QEI_GetPosition(uint8_t qeiId);\r
-void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos);\r
-void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp);\r
-uint32_t QEI_GetIndex(uint8_t qeiId);\r
-void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp);\r
-void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct);\r
-uint32_t QEI_GetTimer(uint8_t qeiId);\r
-uint32_t QEI_GetVelocity(uint8_t qeiId);\r
-uint32_t QEI_GetVelocityCap(uint8_t qeiId);\r
-void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp);\r
-void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal);\r
-uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR);\r
-\r
-FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType);\r
-void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState);\r
-void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType);\r
-void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType);\r
-\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_QEI_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_rgu.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_rgu.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for RGU firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup RGU RGU (Reset Generation Unit)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_RGU_H_\r
-#define LPC18XX_RGU_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup RGU_Public_Types RGU Public Types\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief RGU enumeration\r
- **********************************************************************/\r
-/** @brief Out Reset Signal Generated by RGU */\r
-typedef enum\r
-{\r
- RGU_SIG_CORE = 0, /**< Core reset signal */\r
- RGU_SIG_PERIPH, /**< Peripheral reset signal */\r
- RGU_SIG_MASTER, /**< Master reset signal */\r
- RGU_SIG_WWDT = 4, /**< WWDT reset signal */\r
- RGU_SIG_CREG, /**< CREG reset signal */\r
- RGU_SIG_BUS = 8, /**< Bus reset signal */\r
- RGU_SIG_SCU, /**< SCU reset signal */\r
- RGU_SIG_PINMUX, /**< Pin mux reset signal */\r
- RGU_SIG_M3 = 13, /**< Cortex-M3 reset signal */\r
- RGU_SIG_LCD = 16, /**< LCD reset signal */\r
- RGU_SIG_USB0, /**< USB0 reset signal */\r
- RGU_SIG_USB1, /**< USB1 reset signal */\r
- RGU_SIG_DMA, /**< DMA reset signal */\r
- RGU_SIG_SDIO, /**< SDIO reset signal */\r
- RGU_SIG_EMC, /**< EMC reset signal */\r
- RGU_SIG_ETHERNET, /**< Ethernet reset signal */\r
- RGU_SIG_AES, /**< AES reset signal */\r
- RGU_SIG_GPIO = 28, /**< GPIO reset signal */\r
- RGU_SIG_TIMER0 = 32, /**< TIMER 0 reset signal */\r
- RGU_SIG_TIMER1, /**< TIMER 1 reset signal */\r
- RGU_SIG_TIMER2, /**< TIMER 2 reset signal */\r
- RGU_SIG_TIMER3, /**< TIMER 3 reset signal */\r
- RGU_SIG_RITIMER, /**< RIT timer reset signal */\r
- RGU_SIG_SCT, /**< SCT reset signal */\r
- RGU_SIG_MOTOCONPWM, /**< Motor control reset signal */\r
- RGU_SIG_QEI, /**< QEI reset signal */\r
- RGU_SIG_ADC0, /**< ADC0 reset signal */\r
- RGU_SIG_ADC1, /**< ADC1 reset signal */\r
- RGU_SIG_DAC, /**< DAC reset signal */\r
- RGU_SIG_UART0 = 44, /**< UART0 reset signal */\r
- RGU_SIG_UART1, /**< UART1 reset signal */\r
- RGU_SIG_UART2, /**< UART2 reset signal */\r
- RGU_SIG_UART3, /**< UART3 reset signal */\r
- RGU_SIG_I2C0, /**< I2C0 reset signal */\r
- RGU_SIG_I2C1, /**< I2C1 reset signal */\r
- RGU_SIG_SSP0, /**< SSP0 reset signal */\r
- RGU_SIG_SSP1, /**< SSP1 reset signal */\r
- RGU_SIG_I2S, /**< I2S reset signal */\r
- RGU_SIG_SPIFI, /**< SPIFI reset signal */\r
- RGU_SIG_CAN = 55 /**< CAN reset signal */\r
-}RGU_SIG;\r
-\r
-/** @brief Reset Cause Source */\r
-typedef enum {\r
- RGU_SRC_NONE, /**< No source */\r
- RGU_SRC_SOFT, /**< Software reset source */\r
- RGU_SRC_EXT, /**< External reset source */\r
- RGU_SRC_CORE, /**< Core reset source */\r
- RGU_SRC_PERIPH, /**< Peripheral reset source*/\r
- RGU_SRC_MASTER, /**< Master reset source */\r
- RGU_SRC_BOD, /**< BOD reset source */\r
- RGU_SRC_WWDT /**< WWDT reset source */\r
-}RGU_SRC;\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup RGU_Public_Functions RGU Public Functions\r
- * @{\r
- */\r
-/* RGU peripheral control function ----------------*/\r
-void RGU_SoftReset(RGU_SIG ResetSignal);\r
-RGU_SRC RGU_GetSource(RGU_SIG ResetSignal);\r
-Bool RGU_GetSignalStatus(RGU_SIG ResetSignal);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* LPC18XX_RGU_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_rit.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_rit.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for RIT firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup RIT RIT (Repetitive Interrupt Timer)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_RIT_H_\r
-#define LPC18XX_RIT_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup RIT_Private_Macros RIT Private Macros\r
- * @{\r
- */\r
-\r
-/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
-/*********************************************************************//**\r
- * Macro defines for RIT control register\r
- **********************************************************************/\r
-/** Set interrupt flag when the counter value equals the masked compare value */\r
-#define RIT_CTRL_INTEN ((uint32_t) (1))\r
-/** Set timer enable clear to 0 when the counter value equals the masked compare value */\r
-#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))\r
-/** Set timer enable on debug */\r
-#define RIT_CTRL_ENBR ((uint32_t) _BIT(2))\r
-/** Set timer enable */\r
-#define RIT_CTRL_TEN ((uint32_t) _BIT(3))\r
-\r
-/** Macro to determine if it is valid RIT peripheral */\r
-#define PARAM_RITx(n) (((uint32_t *)n)==((uint32_t *)LPC_RITIMER))\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup RIT_Public_Functions RIT Public Functions\r
- * @{\r
- */\r
-/* RIT Init/DeInit functions */\r
-void RIT_Init(LPC_RITIMER_Type *RITx);\r
-void RIT_DeInit(LPC_RITIMER_Type *RITx);\r
-\r
-/* RIT config timer functions */\r
-void RIT_TimerConfig(LPC_RITIMER_Type *RITx, uint32_t time_interval);\r
-\r
-/* Enable/Disable RIT functions */\r
-void RIT_TimerClearCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);\r
-void RIT_Cmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);\r
-void RIT_TimerDebugCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);\r
-\r
-/* RIT Interrupt functions */\r
-IntStatus RIT_GetIntStatus(LPC_RITIMER_Type *RITx);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_RIT_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_rtc.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_rtc.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for RTC firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup RTC RTC (Real-Time Clock)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_RTC_H_\r
-#define LPC18XX_RTC_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup RTC_Private_Macros RTC Private Macros\r
- * @{\r
- */\r
-\r
-/* ----------------------- BIT DEFINITIONS ----------------------------------- */\r
-/* Miscellaneous register group --------------------------------------------- */\r
-/**********************************************************************\r
-* ILR register definitions\r
-**********************************************************************/\r
-/** ILR register mask */\r
-#define RTC_ILR_BITMASK ((0x00000003))\r
-/** Bit inform the source interrupt is counter increment*/\r
-#define RTC_IRL_RTCCIF ((1<<0))\r
-/** Bit inform the source interrupt is alarm match*/\r
-#define RTC_IRL_RTCALF ((1<<1))\r
-\r
-/**********************************************************************\r
-* CCR register definitions\r
-**********************************************************************/\r
-/** CCR register mask */\r
-#define RTC_CCR_BITMASK ((0x00000013))\r
-/** Clock enable */\r
-#define RTC_CCR_CLKEN ((1<<0))\r
-/** Clock reset */\r
-#define RTC_CCR_CTCRST ((1<<1))\r
-/** Calibration counter enable */\r
-#define RTC_CCR_CCALEN ((1<<4))\r
-\r
-/**********************************************************************\r
-* CIIR register definitions\r
-**********************************************************************/\r
-/** Counter Increment Interrupt bit for second */\r
-#define RTC_CIIR_IMSEC ((1<<0))\r
-/** Counter Increment Interrupt bit for minute */\r
-#define RTC_CIIR_IMMIN ((1<<1))\r
-/** Counter Increment Interrupt bit for hour */\r
-#define RTC_CIIR_IMHOUR ((1<<2))\r
-/** Counter Increment Interrupt bit for day of month */\r
-#define RTC_CIIR_IMDOM ((1<<3))\r
-/** Counter Increment Interrupt bit for day of week */\r
-#define RTC_CIIR_IMDOW ((1<<4))\r
-/** Counter Increment Interrupt bit for day of year */\r
-#define RTC_CIIR_IMDOY ((1<<5))\r
-/** Counter Increment Interrupt bit for month */\r
-#define RTC_CIIR_IMMON ((1<<6))\r
-/** Counter Increment Interrupt bit for year */\r
-#define RTC_CIIR_IMYEAR ((1<<7))\r
-/** CIIR bit mask */\r
-#define RTC_CIIR_BITMASK ((0xFF))\r
-\r
-/**********************************************************************\r
-* AMR register definitions\r
-**********************************************************************/\r
-/** Counter Increment Select Mask bit for second */\r
-#define RTC_AMR_AMRSEC ((1<<0))\r
-/** Counter Increment Select Mask bit for minute */\r
-#define RTC_AMR_AMRMIN ((1<<1))\r
-/** Counter Increment Select Mask bit for hour */\r
-#define RTC_AMR_AMRHOUR ((1<<2))\r
-/** Counter Increment Select Mask bit for day of month */\r
-#define RTC_AMR_AMRDOM ((1<<3))\r
-/** Counter Increment Select Mask bit for day of week */\r
-#define RTC_AMR_AMRDOW ((1<<4))\r
-/** Counter Increment Select Mask bit for day of year */\r
-#define RTC_AMR_AMRDOY ((1<<5))\r
-/** Counter Increment Select Mask bit for month */\r
-#define RTC_AMR_AMRMON ((1<<6))\r
-/** Counter Increment Select Mask bit for year */\r
-#define RTC_AMR_AMRYEAR ((1<<7))\r
-/** AMR bit mask */\r
-#define RTC_AMR_BITMASK ((0xFF))\r
-\r
-/**********************************************************************\r
-* RTC_AUX register definitions\r
-**********************************************************************/\r
-/** RTC Oscillator Fail detect flag */\r
-#define RTC_AUX_RTC_OSCF ((1<<4))\r
-\r
-/**********************************************************************\r
-* RTC_AUXEN register definitions\r
-**********************************************************************/\r
-/** Oscillator Fail Detect interrupt enable*/\r
-#define RTC_AUXEN_RTC_OSCFEN ((1<<4))\r
-\r
-/* Consolidated time register group ----------------------------------- */\r
-/**********************************************************************\r
-* Consolidated Time Register 0 definitions\r
-**********************************************************************/\r
-#define RTC_CTIME0_SECONDS_MASK ((0x3F))\r
-#define RTC_CTIME0_MINUTES_MASK ((0x3F00))\r
-#define RTC_CTIME0_HOURS_MASK ((0x1F0000))\r
-#define RTC_CTIME0_DOW_MASK ((0x7000000))\r
-\r
-/**********************************************************************\r
-* Consolidated Time Register 1 definitions\r
-**********************************************************************/\r
-#define RTC_CTIME1_DOM_MASK ((0x1F))\r
-#define RTC_CTIME1_MONTH_MASK ((0xF00))\r
-#define RTC_CTIME1_YEAR_MASK ((0xFFF0000))\r
-\r
-/**********************************************************************\r
-* Consolidated Time Register 2 definitions\r
-**********************************************************************/\r
-#define RTC_CTIME2_DOY_MASK ((0xFFF))\r
-\r
-/**********************************************************************\r
-* Time Counter Group and Alarm register group\r
-**********************************************************************/\r
-/** SEC register mask */\r
-#define RTC_SEC_MASK (0x0000003F)\r
-/** MIN register mask */\r
-#define RTC_MIN_MASK (0x0000003F)\r
-/** HOUR register mask */\r
-#define RTC_HOUR_MASK (0x0000001F)\r
-/** DOM register mask */\r
-#define RTC_DOM_MASK (0x0000001F)\r
-/** DOW register mask */\r
-#define RTC_DOW_MASK (0x00000007)\r
-/** DOY register mask */\r
-#define RTC_DOY_MASK (0x000001FF)\r
-/** MONTH register mask */\r
-#define RTC_MONTH_MASK (0x0000000F)\r
-/** YEAR register mask */\r
-#define RTC_YEAR_MASK (0x00000FFF)\r
-\r
-#define RTC_SECOND_MAX 59 /*!< Maximum value of second */\r
-#define RTC_MINUTE_MAX 59 /*!< Maximum value of minute*/\r
-#define RTC_HOUR_MAX 23 /*!< Maximum value of hour*/\r
-#define RTC_MONTH_MIN 1 /*!< Minimum value of month*/\r
-#define RTC_MONTH_MAX 12 /*!< Maximum value of month*/\r
-#define RTC_DAYOFMONTH_MIN 1 /*!< Minimum value of day of month*/\r
-#define RTC_DAYOFMONTH_MAX 31 /*!< Maximum value of day of month*/\r
-#define RTC_DAYOFWEEK_MAX 6 /*!< Maximum value of day of week*/\r
-#define RTC_DAYOFYEAR_MIN 1 /*!< Minimum value of day of year*/\r
-#define RTC_DAYOFYEAR_MAX 366 /*!< Maximum value of day of year*/\r
-#define RTC_YEAR_MAX 4095 /*!< Maximum value of year*/\r
-\r
-/**********************************************************************\r
-* Calibration register\r
-**********************************************************************/\r
-/* Calibration register */\r
-/** Calibration value */\r
-#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))\r
-/** Calibration direction */\r
-#define RTC_CALIBRATION_LIBDIR ((1<<17))\r
-/** Calibration max value */\r
-#define RTC_CALIBRATION_MAX ((0x20000))\r
-/** Calibration definitions */\r
-#define RTC_CALIB_DIR_FORWARD ((uint8_t)(0))\r
-#define RTC_CALIB_DIR_BACKWARD ((uint8_t)(1))\r
-\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-/** Macro to determine if it is valid RTC peripheral */\r
-#define PARAM_RTCx(x) (((uint32_t *)x)==((uint32_t *)LPC_RTC))\r
-\r
-/* Macro check RTC interrupt type */\r
-#define PARAM_RTC_INT(n) ((n==RTC_INT_COUNTER_INCREASE) || (n==RTC_INT_ALARM))\r
-\r
-/* Macro check RTC time type */\r
-#define PARAM_RTC_TIMETYPE(n) ((n==RTC_TIMETYPE_SECOND) || (n==RTC_TIMETYPE_MINUTE) \\r
-|| (n==RTC_TIMETYPE_HOUR) || (n==RTC_TIMETYPE_DAYOFWEEK) \\r
-|| (n==RTC_TIMETYPE_DAYOFMONTH) || (n==RTC_TIMETYPE_DAYOFYEAR) \\r
-|| (n==RTC_TIMETYPE_MONTH) || (n==RTC_TIMETYPE_YEAR))\r
-\r
-/* Macro check RTC calibration type */\r
-#define PARAM_RTC_CALIB_DIR(n) ((n==RTC_CALIB_DIR_FORWARD) || (n==RTC_CALIB_DIR_BACKWARD))\r
-\r
-/* Macro check RTC GPREG type */\r
-#define PARAM_RTC_GPREG_CH(n) ((n<=63))\r
-\r
-/* RTC GPREG base address*/\r
-#define RTC_GPREG_BASE 0x40041000\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup RTC_Public_Types RTC Public Types\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief RTC enumeration\r
- **********************************************************************/\r
-/** @brief RTC interrupt source */\r
-typedef enum {\r
- RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */\r
- RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */\r
-} RTC_INT_OPT;\r
-\r
-\r
-/** @brief RTC time type option */\r
-typedef enum {\r
- RTC_TIMETYPE_SECOND = 0, /*!< Second */\r
- RTC_TIMETYPE_MINUTE = 1, /*!< Month */\r
- RTC_TIMETYPE_HOUR = 2, /*!< Hour */\r
- RTC_TIMETYPE_DAYOFWEEK = 3, /*!< Day of week */\r
- RTC_TIMETYPE_DAYOFMONTH = 4, /*!< Day of month */\r
- RTC_TIMETYPE_DAYOFYEAR = 5, /*!< Day of year */\r
- RTC_TIMETYPE_MONTH = 6, /*!< Month */\r
- RTC_TIMETYPE_YEAR = 7 /*!< Year */\r
-} RTC_TIMETYPE_Num;\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief RTC structure definitions\r
- **********************************************************************/\r
-/** @brief Time structure definitions for easy manipulate the data */\r
-typedef struct {\r
- uint32_t SEC; /*!< Seconds Register */\r
- uint32_t MIN; /*!< Minutes Register */\r
- uint32_t HOUR; /*!< Hours Register */\r
- uint32_t DOM; /*!< Day of Month Register */\r
- uint32_t DOW; /*!< Day of Week Register */\r
- uint32_t DOY; /*!< Day of Year Register */\r
- uint32_t MONTH; /*!< Months Register */\r
- uint32_t YEAR; /*!< Years Register */\r
-} RTC_TIME_Type;\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup RTC_Public_Functions RTC Public Functions\r
- * @{\r
- */\r
-\r
-void RTC_Init (LPC_RTC_Type *RTCx);\r
-void RTC_DeInit(LPC_RTC_Type *RTCx);\r
-\r
-void RTC_ResetClockTickCounter(LPC_RTC_Type *RTCx);\r
-void RTC_Cmd (LPC_RTC_Type *RTCx, FunctionalState NewState);\r
-\r
-void RTC_SetTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t TimeValue);\r
-uint32_t RTC_GetTime(LPC_RTC_Type *RTCx, uint32_t Timetype);\r
-\r
-void RTC_SetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);\r
-void RTC_GetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);\r
-\r
-void RTC_AlarmIntConfig (LPC_RTC_Type *RTCx, uint32_t AlarmTimeType, FunctionalState NewState);\r
-void RTC_SetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t ALValue);\r
-uint32_t RTC_GetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype);\r
-void RTC_SetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);\r
-void RTC_GetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);\r
-\r
-void RTC_CntIncrIntConfig (LPC_RTC_Type *RTCx, uint32_t CntIncrIntType, FunctionalState NewState);\r
-IntStatus RTC_GetIntPending (LPC_RTC_Type *RTCx, uint32_t IntType);\r
-void RTC_ClearIntPending (LPC_RTC_Type *RTCx, uint32_t IntType);\r
-\r
-void RTC_CalibCounterCmd(LPC_RTC_Type *RTCx, FunctionalState NewState);\r
-void RTC_CalibConfig(LPC_RTC_Type *RTCx, uint32_t CalibValue, uint8_t CalibDir);\r
-\r
-void RTC_WriteGPREG (LPC_RTC_Type *RTCx, uint8_t Channel, uint32_t Value);\r
-uint32_t RTC_ReadGPREG (LPC_RTC_Type *RTCx, uint8_t Channel);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_RTC_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_sct.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_sct.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for SCT firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup SCT SCT (State Configurable Timer)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_SCT_H_\r
-#define LPC18XX_SCT_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Private macros ------------------------------------------------------------- */\r
-/** @defgroup SCT_Private_Macros SCT Private Macros\r
- * @{\r
- */\r
-\r
-/* -------------------------- BIT DEFINITIONS ----------------------------------- */\r
-/*********************************************************************//**\r
- * Macro defines for SCT configuration register\r
- **********************************************************************/\r
-/** Selects 16/32 bit counter */\r
-#define SCT_CONFIG_16BIT_COUNTER 0x00000000\r
-#define SCT_CONFIG_32BIT_COUNTER 0x00000001\r
-\r
-/*********************************************************************//**\r
- * Macro defines for SCT control register\r
- **********************************************************************/\r
-/** Stop low counter */\r
-#define SCT_CTRL_STOP_L (1<<1)\r
-/** Halt low counter */\r
-#define SCT_CTRL_HALT_L (1<<2)\r
-/** Clear low or unified counter */\r
-#define SCT_CTRL_CLRCTR_L (1<<3)\r
-/** Direction for low or unified counter */\r
-#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0\r
-#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1\r
-#define SCT_CTRL_BIDIR_L(x) (((x)&0x01)<<4)\r
-/** Prescale clock for low or unified counter */\r
-#define SCT_CTRL_PRE_L(x) (((x)&0xFF)<<5)\r
-\r
-/** Stop high counter */\r
-#define SCT_CTRL_STOP_H (1<<17)\r
-/** Halt high counter */\r
-#define SCT_CTRL_HALT_H (1<<18)\r
-/** Clear high counter */\r
-#define SCT_CTRL_CLRCTR_H (1<<19)\r
-/** Direction for high counter */\r
-#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0\r
-#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1\r
-#define SCT_CTRL_BIDIR_H(x) (((x)&0x01)<<20)\r
-/** Prescale clock for high counter */\r
-#define SCT_CTRL_PRE_H(x) (((x)&0xFF)<<21)\r
-/*********************************************************************//**\r
- * Macro defines for SCT Conflict resolution register\r
-**********************************************************************/\r
-/** Define conflict solution */\r
-#define SCT_RES_NOCHANGE (0)\r
-#define SCT_RES_SET_OUTPUT (1)\r
-#define SCT_RES_CLEAR_OUTPUT (2)\r
-#define SCT_RES_TOGGLE_OUTPUT (3)\r
-\r
-/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */\r
-/** Check SCT output number */\r
-#define PARAM_SCT_OUTPUT_NUM(n) ((n)<= CONFIG_SCT_nOU )\r
-\r
-/** Check SCT counter type */\r
-#define PARAM_SCT_CONFIG_COUNTER_TYPE(n) ((n==SCT_CONFIG_16BIT_COUNTER)||(n==SCT_CONFIG_32BIT_COUNTER))\r
-\r
-/** Check SCT conflict solution */\r
-#define PARAM_SCT_RES(n) ((n==SCT_RES_NOCHANGE)||(n==SCT_RES_SET_OUTPUT)\\r
- ||(n==SCT_RES_CLEAR_OUTPUT)||(n==SCT_RES_TOGGLE_OUTPUT))\r
-\r
-/** Check SCT event number */\r
-#define PARAM_SCT_EVENT(n) ((n) <= 15)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup SCT_Public_Functions SCT Public Functions\r
- * @{\r
- */\r
-\r
-void SCT_Config(uint32_t value);\r
-void SCT_ControlSet(uint32_t value, FunctionalState ena);\r
-void SCT_ConflictResolutionSet(uint8_t outnum, uint8_t value);\r
-void SCT_EventFlagClear(uint8_t even_num);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* LPC18XX_SCT_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_scu.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_scu.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for SCU firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup SCU SCU (System Control Unit)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef __SCU_H\r
-#define __SCU_H\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Private macros ------------------------------------------------------------- */\r
-/** @defgroup SCT_Private_Macros SCT Private Macros\r
- * @{\r
- */\r
-\r
-/** Port offset definition */\r
-#define PORT_OFFSET 0x80\r
-/** Pin offset definition */\r
-#define PIN_OFFSET 0x04\r
-\r
-/* Pin modes */\r
-#define MD_PUP (0x0<<3)\r
-#define MD_BUK (0x1<<3)\r
-#define MD_PLN (0x2<<3)\r
-#define MD_PDN (0x3<<3)\r
-#define MD_EHS (0x1<<5)\r
-#define MD_EZI (0x1<<6)\r
-#define MD_ZI (0x1<<7)\r
-#define MD_EHD0 (0x1<<8)\r
-#define MD_EHD1 (0x1<<8)\r
-#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)\r
-// 0xF0\r
-\r
-/* Pin function */\r
-#define FUNC0 0x0 /** Function 0 */\r
-#define FUNC1 0x1 /** Function 1 */\r
-#define FUNC2 0x2 /** Function 2 */\r
-#define FUNC3 0x3 /** Function 3 */\r
-#define FUNC4 0x4\r
-#define FUNC5 0x5\r
-#define FUNC6 0x6\r
-#define FUNC7 0x7\r
-/**\r
- * @}\r
- */\r
-\r
-#define LPC_SCU_PIN(po, pi) (*(volatile int *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4)) )\r
-#define LPC_SCU_CLK(c) (*(volatile int *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4)) )\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup SCU_Public_Functions SCU Public Functions\r
- * @{\r
- */\r
-\r
-void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* end __SCU_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_ssp.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_ssp.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for SSP firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup SSP SSP (Synchronous Serial Port)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC18XX_SSP_H_\r
-#define LPC18XX_SSP_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup SSP_Private_Macros SSP Private Macros\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * SSP configuration parameter defines\r
- **********************************************************************/\r
-/** Clock phase control bit */\r
-#define SSP_CPHA_FIRST ((uint32_t)(0))\r
-#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND\r
-\r
-\r
-/** Clock polarity control bit */\r
-/* There's no bug here!!!\r
- * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.\r
- * That means the active clock is in HI state.\r
- * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock\r
- * high between frames. That means the active clock is in LO state.\r
- */\r
-#define SSP_CPOL_HI ((uint32_t)(0))\r
-#define SSP_CPOL_LO SSP_CR0_CPOL_HI\r
-\r
-/** SSP master mode enable */\r
-#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN\r
-#define SSP_MASTER_MODE ((uint32_t)(0))\r
-\r
-/** SSP data bit number defines */\r
-#define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */\r
-#define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */\r
-#define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */\r
-#define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */\r
-#define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */\r
-#define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */\r
-#define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */\r
-#define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */\r
-#define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */\r
-#define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */\r
-#define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */\r
-#define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */\r
-#define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */\r
-\r
-/** SSP Frame Format definition */\r
-/** Motorola SPI mode */\r
-#define SSP_FRAME_SPI SSP_CR0_FRF_SPI\r
-/** TI synchronous serial mode */\r
-#define SSP_FRAME_TI SSP_CR0_FRF_TI\r
-/** National Micro-wire mode */\r
-#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE\r
-\r
-/*********************************************************************//**\r
- * SSP Status defines\r
- **********************************************************************/\r
-/** SSP status TX FIFO Empty bit */\r
-#define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE\r
-/** SSP status TX FIFO not full bit */\r
-#define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF\r
-/** SSP status RX FIFO not empty bit */\r
-#define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE\r
-/** SSP status RX FIFO full bit */\r
-#define SSP_STAT_RXFIFO_FULL SSP_SR_RFF\r
-/** SSP status SSP Busy bit */\r
-#define SSP_STAT_BUSY SSP_SR_BSY\r
-\r
-/*********************************************************************//**\r
- * SSP Interrupt Configuration defines\r
- **********************************************************************/\r
-/** Receive Overrun */\r
-#define SSP_INTCFG_ROR SSP_IMSC_ROR\r
-/** Receive TimeOut */\r
-#define SSP_INTCFG_RT SSP_IMSC_RT\r
-/** Rx FIFO is at least half full */\r
-#define SSP_INTCFG_RX SSP_IMSC_RX\r
-/** Tx FIFO is at least half empty */\r
-#define SSP_INTCFG_TX SSP_IMSC_TX\r
-\r
-/*********************************************************************//**\r
- * SSP Configured Interrupt Status defines\r
- **********************************************************************/\r
-/** Receive Overrun */\r
-#define SSP_INTSTAT_ROR SSP_MIS_ROR\r
-/** Receive TimeOut */\r
-#define SSP_INTSTAT_RT SSP_MIS_RT\r
-/** Rx FIFO is at least half full */\r
-#define SSP_INTSTAT_RX SSP_MIS_RX\r
-/** Tx FIFO is at least half empty */\r
-#define SSP_INTSTAT_TX SSP_MIS_TX\r
-\r
-/*********************************************************************//**\r
- * SSP Raw Interrupt Status defines\r
- **********************************************************************/\r
-/** Receive Overrun */\r
-#define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR\r
-/** Receive TimeOut */\r
-#define SSP_INTSTAT_RAW_RT SSP_RIS_RT\r
-/** Rx FIFO is at least half full */\r
-#define SSP_INTSTAT_RAW_RX SSP_RIS_RX\r
-/** Tx FIFO is at least half empty */\r
-#define SSP_INTSTAT_RAW_TX SSP_RIS_TX\r
-\r
-/*********************************************************************//**\r
- * SSP Interrupt Clear defines\r
- **********************************************************************/\r
-/** Writing a 1 to this bit clears the "frame was received when\r
- * RxFIFO was full" interrupt */\r
-#define SSP_INTCLR_ROR SSP_ICR_ROR\r
-/** Writing a 1 to this bit clears the "Rx FIFO was not empty and\r
- * has not been read for a timeout period" interrupt */\r
-#define SSP_INTCLR_RT SSP_ICR_RT\r
-\r
-/*********************************************************************//**\r
- * SSP DMA defines\r
- **********************************************************************/\r
-/** SSP bit for enabling RX DMA */\r
-#define SSP_DMA_TX SSP_DMA_RXDMA_EN\r
-/** SSP bit for enabling TX DMA */\r
-#define SSP_DMA_RX SSP_DMA_TXDMA_EN\r
-\r
-/* SSP Status Implementation definitions */\r
-#define SSP_STAT_DONE (1UL<<8) /**< Done */\r
-#define SSP_STAT_ERROR (1UL<<9) /**< Error */\r
-\r
-\r
-/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
-/*********************************************************************//**\r
- * Macro defines for CR0 register\r
- **********************************************************************/\r
-/** SSP data size select, must be 4 bits to 16 bits */\r
-#define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))\r
-/** SSP control 0 Motorola SPI mode */\r
-#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))\r
-/** SSP control 0 TI synchronous serial mode */\r
-#define SSP_CR0_FRF_TI ((uint32_t)(1<<4))\r
-/** SSP control 0 National Micro-wire mode */\r
-#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))\r
-/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the\r
- bus clock high between frames, (0) = low */\r
-#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))\r
-/** SPI clock out phase bit (used in SPI mode only), (1) = captures data\r
- on the second clock transition of the frame, (0) = first */\r
-#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))\r
-/** SSP serial clock rate value load macro, divider rate is\r
- PERIPH_CLK / (cpsr * (SCR + 1)) */\r
-#define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))\r
-/** SSP CR0 bit mask */\r
-#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for CR1 register\r
- **********************************************************************/\r
-/** SSP control 1 loopback mode enable bit */\r
-#define SSP_CR1_LBM_EN ((uint32_t)(1<<0))\r
-/** SSP control 1 enable bit */\r
-#define SSP_CR1_SSP_EN ((uint32_t)(1<<1))\r
-/** SSP control 1 slave enable */\r
-#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))\r
-/** SSP control 1 slave out disable bit, disables transmit line in slave\r
- mode */\r
-#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))\r
-/** SSP CR1 bit mask */\r
-#define SSP_CR1_BITMASK ((uint32_t)(0x0F))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DR register\r
- **********************************************************************/\r
-/** SSP data bit mask */\r
-#define SSP_DR_BITMASK(n) ((n)&0xFFFF)\r
-\r
-/*********************************************************************//**\r
- * Macro defines for SR register\r
- **********************************************************************/\r
-/** SSP status TX FIFO Empty bit */\r
-#define SSP_SR_TFE ((uint32_t)(1<<0))\r
-/** SSP status TX FIFO not full bit */\r
-#define SSP_SR_TNF ((uint32_t)(1<<1))\r
-/** SSP status RX FIFO not empty bit */\r
-#define SSP_SR_RNE ((uint32_t)(1<<2))\r
-/** SSP status RX FIFO full bit */\r
-#define SSP_SR_RFF ((uint32_t)(1<<3))\r
-/** SSP status SSP Busy bit */\r
-#define SSP_SR_BSY ((uint32_t)(1<<4))\r
-/** SSP SR bit mask */\r
-#define SSP_SR_BITMASK ((uint32_t)(0x1F))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for CPSR register\r
- **********************************************************************/\r
-/** SSP clock prescaler */\r
-#define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))\r
-/** SSP CPSR bit mask */\r
-#define SSP_CPSR_BITMASK ((uint32_t)(0xFF))\r
-\r
-/*********************************************************************//**\r
- * Macro define for (IMSC) Interrupt Mask Set/Clear registers\r
- **********************************************************************/\r
-/** Receive Overrun */\r
-#define SSP_IMSC_ROR ((uint32_t)(1<<0))\r
-/** Receive TimeOut */\r
-#define SSP_IMSC_RT ((uint32_t)(1<<1))\r
-/** Rx FIFO is at least half full */\r
-#define SSP_IMSC_RX ((uint32_t)(1<<2))\r
-/** Tx FIFO is at least half empty */\r
-#define SSP_IMSC_TX ((uint32_t)(1<<3))\r
-/** IMSC bit mask */\r
-#define SSP_IMSC_BITMASK ((uint32_t)(0x0F))\r
-\r
-/*********************************************************************//**\r
- * Macro define for (RIS) Raw Interrupt Status registers\r
- **********************************************************************/\r
-/** Receive Overrun */\r
-#define SSP_RIS_ROR ((uint32_t)(1<<0))\r
-/** Receive TimeOut */\r
-#define SSP_RIS_RT ((uint32_t)(1<<1))\r
-/** Rx FIFO is at least half full */\r
-#define SSP_RIS_RX ((uint32_t)(1<<2))\r
-/** Tx FIFO is at least half empty */\r
-#define SSP_RIS_TX ((uint32_t)(1<<3))\r
-/** RIS bit mask */\r
-#define SSP_RIS_BITMASK ((uint32_t)(0x0F))\r
-\r
-/*********************************************************************//**\r
- * Macro define for (MIS) Masked Interrupt Status registers\r
- **********************************************************************/\r
-/** Receive Overrun */\r
-#define SSP_MIS_ROR ((uint32_t)(1<<0))\r
-/** Receive TimeOut */\r
-#define SSP_MIS_RT ((uint32_t)(1<<1))\r
-/** Rx FIFO is at least half full */\r
-#define SSP_MIS_RX ((uint32_t)(1<<2))\r
-/** Tx FIFO is at least half empty */\r
-#define SSP_MIS_TX ((uint32_t)(1<<3))\r
-/** MIS bit mask */\r
-#define SSP_MIS_BITMASK ((uint32_t)(0x0F))\r
-\r
-/*********************************************************************//**\r
- * Macro define for (ICR) Interrupt Clear registers\r
- **********************************************************************/\r
-/** Writing a 1 to this bit clears the "frame was received when\r
- * RxFIFO was full" interrupt */\r
-#define SSP_ICR_ROR ((uint32_t)(1<<0))\r
-/** Writing a 1 to this bit clears the "Rx FIFO was not empty and\r
- * has not been read for a timeout period" interrupt */\r
-#define SSP_ICR_RT ((uint32_t)(1<<1))\r
-/** ICR bit mask */\r
-#define SSP_ICR_BITMASK ((uint32_t)(0x03))\r
-\r
-/*********************************************************************//**\r
- * Macro defines for DMACR register\r
- **********************************************************************/\r
-/** SSP bit for enabling RX DMA */\r
-#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))\r
-/** SSP bit for enabling TX DMA */\r
-#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))\r
-/** DMACR bit mask */\r
-#define SSP_DMA_BITMASK ((uint32_t)(0x03))\r
-\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-/** Macro to determine if it is valid SSP port number */\r
-#define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \\r
-|| (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))\r
-\r
-/** Macro check clock phase control mode */\r
-#define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))\r
-\r
-/** Macro check clock polarity mode */\r
-#define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))\r
-\r
-/* Macro check master/slave mode */\r
-#define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))\r
-\r
-/* Macro check databit value */\r
-#define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \\r
-|| (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \\r
-|| (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \\r
-|| (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \\r
-|| (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \\r
-|| (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \\r
-|| (n==SSP_DATABIT_15))\r
-\r
-/* Macro check frame type */\r
-#define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\\r
-|| (n==SSP_FRAME_MICROWIRE))\r
-\r
-/* Macro check SSP status */\r
-#define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \\r
-|| (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \\r
-|| (n==SSP_STAT_BUSY))\r
-\r
-/* Macro check interrupt configuration */\r
-#define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \\r
-|| (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))\r
-\r
-/* Macro check interrupt status value */\r
-#define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \\r
-|| (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))\r
-\r
-/* Macro check interrupt status raw value */\r
-#define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \\r
-|| (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))\r
-\r
-/* Macro check interrupt clear mode */\r
-#define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))\r
-\r
-/* Macro check DMA mode */\r
-#define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup SSP_Public_Types SSP Public Types\r
- * @{\r
- */\r
-\r
-/** @brief SSP configuration structure */\r
-typedef struct {\r
- uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,\r
- where x is in range from 4 - 16 */\r
- uint32_t CPHA; /** Clock phase, should be:\r
- - SSP_CPHA_FIRST: first clock edge\r
- - SSP_CPHA_SECOND: second clock edge */\r
- uint32_t CPOL; /** Clock polarity, should be:\r
- - SSP_CPOL_HI: high level\r
- - SSP_CPOL_LO: low level */\r
- uint32_t Mode; /** SSP mode, should be:\r
- - SSP_MASTER_MODE: Master mode\r
- - SSP_SLAVE_MODE: Slave mode */\r
- uint32_t FrameFormat; /** Frame Format:\r
- - SSP_FRAME_SPI: Motorola SPI frame format\r
- - SSP_FRAME_TI: TI frame format\r
- - SSP_FRAME_MICROWIRE: National Microwire frame format */\r
- uint32_t ClockRate; /** Clock rate,in Hz */\r
-} SSP_CFG_Type;\r
-\r
-/**\r
- * @brief SSP Transfer Type definitions\r
- */\r
-typedef enum {\r
- SSP_TRANSFER_POLLING = 0, /**< Polling transfer */\r
- SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */\r
-} SSP_TRANSFER_Type;\r
-\r
-/**\r
- * @brief SPI Data configuration structure definitions\r
- */\r
-typedef struct {\r
- void *tx_data; /**< Pointer to transmit data */\r
- uint32_t tx_cnt; /**< Transmit counter */\r
- void *rx_data; /**< Pointer to transmit data */\r
- uint32_t rx_cnt; /**< Receive counter */\r
- uint32_t length; /**< Length of transfer data */\r
- uint32_t status; /**< Current status of SSP activity */\r
-} SSP_DATA_SETUP_Type;\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup SSP_Public_Functions SSP Public Functions\r
- * @{\r
- */\r
-\r
-void SSP_Init(LPC_SSPn_Type *SSPx, SSP_CFG_Type *SSP_ConfigStruct);\r
-void SSP_DeInit(LPC_SSPn_Type* SSPx);\r
-\r
-void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);\r
-void SSP_Cmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);\r
-void SSP_LoopBackCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);\r
-void SSP_SlaveOutputCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);\r
-void SSP_SendData(LPC_SSPn_Type* SSPx, uint16_t Data);\r
-uint16_t SSP_ReceiveData(LPC_SSPn_Type* SSPx);\r
-int32_t SSP_ReadWrite (LPC_SSPn_Type *SSPx, SSP_DATA_SETUP_Type *dataCfg, \\r
- SSP_TRANSFER_Type xfType);\r
-FlagStatus SSP_GetStatus(LPC_SSPn_Type* SSPx, uint32_t FlagType);\r
-uint8_t SSP_GetDataSize(LPC_SSPn_Type* SSPx);\r
-void SSP_IntConfig(LPC_SSPn_Type *SSPx, uint32_t IntType, FunctionalState NewState);\r
-IntStatus SSP_GetRawIntStatus(LPC_SSPn_Type *SSPx, uint32_t RawIntType);\r
-IntStatus SSP_GetIntStatus (LPC_SSPn_Type *SSPx, uint32_t IntType);\r
-void SSP_ClearIntPending(LPC_SSPn_Type *SSPx, uint32_t IntType);\r
-void SSP_DMACmd(LPC_SSPn_Type *SSPx, uint32_t DMAMode, FunctionalState NewState);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_SSP_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_timer.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_timer.h\r
-* @brief Contains all functions support for Timer firmware library\r
-* on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup TIMER TIMER\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef __LPC18XX_TIMER_H_\r
-#define __LPC18XX_TIMER_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup TIMER_Private_Macros TIMER Private Macros\r
- * @{\r
- */\r
-\r
-/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
-/**********************************************************************\r
-** Interrupt information\r
-**********************************************************************/\r
-/** Macro to clean interrupt pending */\r
-#define TIM_IR_CLR(n) _BIT(n)\r
-\r
-/**********************************************************************\r
-** Timer interrupt register definitions\r
-**********************************************************************/\r
-/** Macro for getting a timer match interrupt bit */\r
-#define TIM_MATCH_INT(n) (_BIT(n & 0x0F))\r
-/** Macro for getting a capture event interrupt bit */\r
-#define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4)))\r
-\r
-/**********************************************************************\r
-* Timer control register definitions\r
-**********************************************************************/\r
-/** Timer/counter enable bit */\r
-#define TIM_ENABLE ((uint32_t)(1<<0))\r
-/** Timer/counter reset bit */\r
-#define TIM_RESET ((uint32_t)(1<<1))\r
-/** Timer control bit mask */\r
-#define TIM_TCR_MASKBIT ((uint32_t)(3))\r
-\r
-/**********************************************************************\r
-* Timer match control register definitions\r
-**********************************************************************/\r
-/** Bit location for interrupt on MRx match, n = 0 to 3 */\r
-#define TIM_INT_ON_MATCH(n) (_BIT((n * 3)))\r
-/** Bit location for reset on MRx match, n = 0 to 3 */\r
-#define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1)))\r
-/** Bit location for stop on MRx match, n = 0 to 3 */\r
-#define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2)))\r
-/** Timer Match control bit mask */\r
-#define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF))\r
-/** Timer Match control bit mask for specific channel*/\r
-#define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))\r
-\r
-/**********************************************************************\r
-* Timer capture control register definitions\r
-**********************************************************************/\r
-/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */\r
-#define TIM_CAP_RISING(n) (_BIT((n * 3)))\r
-/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */\r
-#define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1)))\r
-/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */\r
-#define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2)))\r
-/** Mask bit for rising and falling edge bit */\r
-#define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03))\r
-/** Timer capture control bit mask */\r
-#define TIM_CCR_MASKBIT ((uint32_t)(0x3F))\r
-/** Timer Capture control bit mask for specific channel*/\r
-#define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))\r
-\r
-/**********************************************************************\r
-* Timer external match register definitions\r
-**********************************************************************/\r
-/** Bit location for output state change of MAT.n when external match\r
- happens, n = 0 to 3 */\r
-#define TIM_EM(n) _BIT(n)\r
-/** Output state change of MAT.n when external match happens: no change */\r
-#define TIM_EM_NOTHING ((uint8_t)(0x0))\r
-/** Output state change of MAT.n when external match happens: low */\r
-#define TIM_EM_LOW ((uint8_t)(0x1))\r
-/** Output state change of MAT.n when external match happens: high */\r
-#define TIM_EM_HIGH ((uint8_t)(0x2))\r
-/** Output state change of MAT.n when external match happens: toggle */\r
-#define TIM_EM_TOGGLE ((uint8_t)(0x3))\r
-/** Macro for setting for the MAT.n change state bits */\r
-#define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03)))\r
-/** Mask for the MAT.n change state bits */\r
-#define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03))\r
-/** Timer external match bit mask */\r
-#define TIM_EMR_MASKBIT 0x0FFF\r
-\r
-/**********************************************************************\r
-* Timer Count Control Register definitions\r
-**********************************************************************/\r
-/** Mask to get the Counter/timer mode bits */\r
-#define TIM_CTCR_MODE_MASK 0x3\r
-/** Mask to get the count input select bits */\r
-#define TIM_CTCR_INPUT_MASK 0xC\r
-/** Timer Count control bit mask */\r
-#define TIM_CTCR_MASKBIT 0xF\r
-#define TIM_COUNTER_MODE ((uint8_t)(1))\r
-\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-/** Macro to determine if it is valid TIMER peripheral */\r
-#define PARAM_TIMx(n) ((((uint32_t *)n)==((uint32_t *)LPC_TIMER0)) || (((uint32_t *)n)==((uint32_t *)LPC_TIMER1)) \\r
-|| (((uint32_t *)n)==((uint32_t *)LPC_TIMER2)) || (((uint32_t *)n)==((uint32_t *)LPC_TIMER3)))\r
-\r
-/* Macro check interrupt type */\r
-#define PARAM_TIM_INT_TYPE(TYPE) ((TYPE ==TIM_MR0_INT)||(TYPE ==TIM_MR1_INT)\\r
-||(TYPE ==TIM_MR2_INT)||(TYPE ==TIM_MR3_INT)\\r
-||(TYPE ==TIM_CR0_INT)||(TYPE ==TIM_CR1_INT)\\r
-||(TYPE ==TIM_CR2_INT)||(TYPE ==TIM_CR3_INT))\r
-\r
-/* Macro check TIMER mode */\r
-#define PARAM_TIM_MODE_OPT(MODE) ((MODE == TIM_TIMER_MODE)||(MODE == TIM_COUNTER_RISING_MODE)\\r
-|| (MODE == TIM_COUNTER_RISING_MODE)||(MODE == TIM_COUNTER_RISING_MODE))\r
-\r
-/* Macro check TIMER prescale value */\r
-#define PARAM_TIM_PRESCALE_OPT(OPT) ((OPT == TIM_PRESCALE_TICKVAL)||(OPT == TIM_PRESCALE_USVAL))\r
-\r
-/* Macro check TIMER counter intput mode */\r
-#define PARAM_TIM_COUNTER_INPUT_OPT(OPT) ((OPT == TIM_COUNTER_INCAP0)||(OPT == TIM_COUNTER_INCAP1)\\r
- ||(OPT == TIM_COUNTER_INCAP2)||(OPT == TIM_COUNTER_INCAP3))\r
-\r
-/* Macro check TIMER external match mode */\r
-#define PARAM_TIM_EXTMATCH_OPT(OPT) ((OPT == TIM_EXTMATCH_NOTHING)||(OPT == TIM_EXTMATCH_LOW)\\r
-||(OPT == TIM_EXTMATCH_HIGH)||(OPT == TIM_EXTMATCH_TOGGLE))\r
-\r
-/* Macro check TIMER external match mode */\r
-#define PARAM_TIM_CAP_MODE_OPT(OPT) ((OPT == TIM_CAPTURE_NONE)||(OPT == TIM_CAPTURE_RISING) \\r
-||(OPT == TIM_CAPTURE_FALLING)||(OPT == TIM_CAPTURE_ANY))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup TIMER_Public_Types TIMER Public Types\r
- * @{\r
- */\r
-\r
-/***********************************************************************\r
- * @brief Timer device enumeration\r
-**********************************************************************/\r
-/** @brief interrupt type */\r
-typedef enum\r
-{\r
- TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/\r
- TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/\r
- TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/\r
- TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/\r
- TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/\r
- TIM_CR1_INT =5, /*!< interrupt for Capture channel 1*/\r
- TIM_CR2_INT =6, /*!< interrupt for Capture channel 1*/\r
- TIM_CR3_INT =7 /*!< interrupt for Capture channel 1*/\r
-}TIM_INT_TYPE;\r
-\r
-/** @brief Timer/counter operating mode */\r
-typedef enum\r
-{\r
- TIM_TIMER_MODE = 0, /*!< Timer mode */\r
- TIM_COUNTER_RISING_MODE, /*!< Counter rising mode */\r
- TIM_COUNTER_FALLING_MODE, /*!< Counter falling mode */\r
- TIM_COUNTER_ANY_MODE /*!< Counter on both edges */\r
-} TIM_MODE_OPT;\r
-\r
-/** @brief Timer/Counter prescale option */\r
-typedef enum\r
-{\r
- TIM_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */\r
- TIM_PRESCALE_USVAL /*!< Prescale in microsecond value */\r
-} TIM_PRESCALE_OPT;\r
-\r
-/** @brief Counter input option */\r
-typedef enum\r
-{\r
- TIM_COUNTER_INCAP0 = 0, /*!< CAPn.0 input pin for TIMERn */\r
- TIM_COUNTER_INCAP1, /*!< CAPn.1 input pin for TIMERn */\r
- TIM_COUNTER_INCAP2, /*!< CAPn.2 input pin for TIMERn */\r
- TIM_COUNTER_INCAP3 /*!< CAPn.3 input pin for TIMERn */\r
-} TIM_COUNTER_INPUT_OPT;\r
-\r
-/** @brief Timer/Counter external match option */\r
-typedef enum\r
-{\r
- TIM_EXTMATCH_NOTHING = 0, /*!< Do nothing for external output pin if match */\r
- TIM_EXTMATCH_LOW, /*!< Force external output pin to low if match */\r
- TIM_EXTMATCH_HIGH, /*!< Force external output pin to high if match */\r
- TIM_EXTMATCH_TOGGLE /*!< Toggle external output pin if match */\r
-}TIM_EXTMATCH_OPT;\r
-\r
-/** @brief Timer/counter capture mode options */\r
-typedef enum {\r
- TIM_CAPTURE_NONE = 0, /*!< No Capture */\r
- TIM_CAPTURE_RISING, /*!< Rising capture mode */\r
- TIM_CAPTURE_FALLING, /*!< Falling capture mode */\r
- TIM_CAPTURE_ANY /*!< On both edges */\r
-} TIM_CAP_MODE_OPT;\r
-\r
-/***********************************************************************\r
- * @brief Timer structure definitions\r
-**********************************************************************/\r
-/** @brief Configuration structure in TIMER mode */\r
-typedef struct\r
-{\r
-\r
- uint8_t PrescaleOption; /**< Timer Prescale option, should be:\r
- - TIM_PRESCALE_TICKVAL: Prescale in absolute value\r
- - TIM_PRESCALE_USVAL: Prescale in microsecond value\r
- */\r
- uint8_t Reserved[3]; /**< Reserved */\r
- uint32_t PrescaleValue; /**< Prescale value */\r
-} TIM_TIMERCFG_Type;\r
-\r
-/** @brief Configuration structure in COUNTER mode */\r
-typedef struct {\r
-\r
- uint8_t CounterOption; /**< Counter Option, should be:\r
- - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn\r
- - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn\r
- */\r
- uint8_t CountInputSelect;\r
- uint8_t Reserved[2];\r
-} TIM_COUNTERCFG_Type;\r
-\r
-/** @brief Match channel configuration structure */\r
-typedef struct {\r
- uint8_t MatchChannel; /**< Match channel, should be in range\r
- from 0..3 */\r
- uint8_t IntOnMatch; /**< Interrupt On match, should be:\r
- - ENABLE: Enable this function.\r
- - DISABLE: Disable this function.\r
- */\r
- uint8_t StopOnMatch; /**< Stop On match, should be:\r
- - ENABLE: Enable this function.\r
- - DISABLE: Disable this function.\r
- */\r
- uint8_t ResetOnMatch; /**< Reset On match, should be:\r
- - ENABLE: Enable this function.\r
- - DISABLE: Disable this function.\r
- */\r
-\r
- uint8_t ExtMatchOutputType; /**< External Match Output type, should be:\r
- - TIM_EXTMATCH_NOTHING: Do nothing for external output pin if match\r
- - TIM_EXTMATCH_LOW: Force external output pin to low if match\r
- - TIM_EXTMATCH_HIGH: Force external output pin to high if match\r
- - TIM_EXTMATCH_TOGGLE: Toggle external output pin if match.\r
- */\r
- uint8_t Reserved[3]; /** Reserved */\r
- uint32_t MatchValue; /** Match value */\r
-} TIM_MATCHCFG_Type;\r
-\r
-/** @brief Capture Input configuration structure */\r
-typedef struct {\r
- uint8_t CaptureChannel; /**< Capture channel, should be in range\r
- from 0..1 */\r
- uint8_t RisingEdge; /**< caption rising edge, should be:\r
- - ENABLE: Enable rising edge.\r
- - DISABLE: Disable this function.\r
- */\r
- uint8_t FallingEdge; /**< caption falling edge, should be:\r
- - ENABLE: Enable falling edge.\r
- - DISABLE: Disable this function.\r
- */\r
- uint8_t IntOnCaption; /**< Interrupt On caption, should be:\r
- - ENABLE: Enable interrupt function.\r
- - DISABLE: Disable this function.\r
- */\r
-\r
-} TIM_CAPTURECFG_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup TIMER_Public_Functions TIMER Public Functions\r
- * @{\r
- */\r
-/* Init/DeInit TIM functions -----------*/\r
-void TIM_Init(LPC_TIMERn_Type *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);\r
-void TIM_DeInit(LPC_TIMERn_Type *TIMx);\r
-\r
-/* TIM interrupt functions -------------*/\r
-void TIM_ClearIntPending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);\r
-void TIM_ClearIntCapturePending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);\r
-FlagStatus TIM_GetIntStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);\r
-FlagStatus TIM_GetIntCaptureStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);\r
-\r
-/* TIM configuration functions --------*/\r
-void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);\r
-void TIM_ConfigMatch(LPC_TIMERn_Type *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct);\r
-void TIM_UpdateMatchValue(LPC_TIMERn_Type *TIMx,uint8_t MatchChannel, uint32_t MatchValue);\r
-void TIM_SetMatchExt(LPC_TIMERn_Type *TIMx,TIM_EXTMATCH_OPT ext_match );\r
-void TIM_ConfigCapture(LPC_TIMERn_Type *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct);\r
-void TIM_Cmd(LPC_TIMERn_Type *TIMx, FunctionalState NewState);\r
-\r
-uint32_t TIM_GetCaptureValue(LPC_TIMERn_Type *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel);\r
-void TIM_ResetCounter(LPC_TIMERn_Type *TIMx);\r
-void TIM_Waitus(uint32_t time);\r
-void TIM_Waitms(uint32_t time);\r
-/**\r
- * @}\r
- */\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __LPC18XX_TIMER_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_uart.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_uart.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for UART firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup UART UART\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef __LPC18XX_UART_H\r
-#define __LPC18XX_UART_H\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup UART_Public_Macros UART Public Macros\r
- * @{\r
- */\r
-\r
-/** UART time-out definitions in case of using Read() and Write function\r
- * with Blocking Flag mode\r
- */\r
-#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup UART_Private_Macros UART Private Macros\r
- * @{\r
- */\r
-\r
-/* Accepted Error baud rate value (in percent unit) */\r
-#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */\r
-\r
-\r
-/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UARTn Receiver Buffer Register\r
- **********************************************************************/\r
-#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UARTn Transmit Holding Register\r
- **********************************************************************/\r
-#define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UARTn Divisor Latch LSB register\r
- **********************************************************************/\r
-#define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */\r
-#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UARTn Divisor Latch MSB register\r
- **********************************************************************/\r
-#define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */\r
-#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART interrupt enable register\r
- **********************************************************************/\r
-#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/\r
-#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/\r
-#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/\r
-#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */\r
-#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */\r
-#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */\r
-#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */\r
-#define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */\r
-#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART interrupt identification register\r
- **********************************************************************/\r
-#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */\r
-#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/\r
-#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/\r
-#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/\r
-#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/\r
-#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/\r
-#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */\r
-#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */\r
-#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */\r
-#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */\r
-#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART FIFO control register\r
- **********************************************************************/\r
-#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */\r
-#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */\r
-#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */\r
-#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */\r
-#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */\r
-#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */\r
-#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */\r
-#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */\r
-#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */\r
-#define UART_TX_FIFO_SIZE (16)\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART line control register\r
- **********************************************************************/\r
-#define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */\r
-#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */\r
-#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */\r
-#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */\r
-#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */\r
-#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */\r
-#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */\r
-#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */\r
-#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */\r
-#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */\r
-#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */\r
-#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */\r
-#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART1 Modem Control Register\r
- **********************************************************************/\r
-#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */\r
-#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */\r
-#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */\r
-#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */\r
-#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */\r
-#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART line status register\r
- **********************************************************************/\r
-#define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/\r
-#define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/\r
-#define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/\r
-#define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/\r
-#define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/\r
-#define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/\r
-#define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/\r
-#define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/\r
-#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART Modem (UART1 only) status register\r
- **********************************************************************/\r
-#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */\r
-#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */\r
-#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */\r
-#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */\r
-#define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */\r
-#define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */\r
-#define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */\r
-#define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */\r
-#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART Scratch Pad Register\r
- **********************************************************************/\r
-#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART Auto baudrate control register\r
- **********************************************************************/\r
-#define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */\r
-#define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */\r
-#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */\r
-#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */\r
-#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */\r
-#define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART IrDA control register\r
- **********************************************************************/\r
-#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */\r
-#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */\r
-#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */\r
-#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */\r
-#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART half duplex register\r
- **********************************************************************/\r
-#define UART_HDEN_HDEN ((uint32_t)(1<<0)) /**< enable half-duplex mode*/\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART smart card interface control register\r
- **********************************************************************/\r
-#define UART_SCICTRL_SCIEN ((uint32_t)(1<<0)) /**< enable asynchronous half-duplex smart card interface*/\r
-#define UART_SCICTRL_NACKDIS ((uint32_t)(1<<1)) /**< NACK response is inhibited*/\r
-#define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(1<<2)) /**< ISO7816-3 protocol T1 is selected*/\r
-#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) /**< number of retransmission*/\r
-#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /**< Extra guard time*/\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART synchronous control register\r
- **********************************************************************/\r
-#define UART_SYNCCTRL_SYNC ((uint32_t)(1<<0)) /**< enable synchronous mode*/\r
-#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t)(1<<1)) /**< synchronous master mode*/\r
-#define UART_SYNCCTRL_FES ((uint32_t)(1<<2)) /**< sample on falling edge*/\r
-#define UART_SYNCCTRL_TSBYPASS ((uint32_t)(1<<3)) /**< to be defined*/\r
-#define UART_SYNCCTRL_CSCEN ((uint32_t)(1<<4)) /**< continuous running clock enable (master mode only)*/\r
-#define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t)(1<<5)) /**< do not send start/stop bit*/\r
-#define UART_SYNCCTRL_CCCLR ((uint32_t)(1<<6)) /**< stop continuous clock*/\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART Fractional divider register\r
- **********************************************************************/\r
-#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */\r
-#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */\r
-#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART Tx Enable register\r
- **********************************************************************/\r
-#define UART1_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */\r
-#define UART1_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */\r
-#define UART0_2_3_TER_TXEN ((uint8_t)(1<<0)) /*!< Transmit enable bit */\r
-#define UART0_2_3_TER_BITMASK ((uint8_t)(0x01)) /**< UART Transmit Enable Register bit mask */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART1 RS485 Control register\r
- **********************************************************************/\r
-#define UART_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)\r
- is disabled */\r
-#define UART_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */\r
-#define UART_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */\r
-#define UART_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled\r
- (bit DCTRL = 1), pin DTR is used for direction control */\r
-#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */\r
-#define UART_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction\r
- control signal on the RTS (or DTR) pin. The direction control pin\r
- will be driven to logic "1" when the transmitter has data to be sent */\r
-#define UART_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART1 RS-485 Address Match register\r
- **********************************************************************/\r
-#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART1 RS-485 Delay value register\r
- **********************************************************************/\r
-/* Macro defines for UART1 RS-485 Delay value register */\r
-#define UART_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */\r
-\r
-/*********************************************************************//**\r
- * Macro defines for Macro defines for UART FIFO Level register\r
- **********************************************************************/\r
-#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */\r
-#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */\r
-#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */\r
-\r
-\r
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
-\r
-/** Macro to check the input UART_DATABIT parameters */\r
-#define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\\r
-|| (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))\r
-\r
-/** Macro to check the input UART_STOPBIT parameters */\r
-#define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))\r
-\r
-/** Macro to check the input UART_PARITY parameters */\r
-#define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \\r
-|| (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \\r
-|| (parity==UART_PARITY_SP_0))\r
-\r
-/** Macro to check the input UART_FIFO parameters */\r
-#define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \\r
-|| (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \\r
-|| (fifo==UART_FIFO_TRGLEV3))\r
-\r
-/** Macro to check the input UART_INTCFG parameters */\r
-#define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \\r
-|| (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \\r
-|| (IntCfg==UART_INTCFG_ABTO))\r
-\r
-/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */\r
-#define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))\r
-\r
-/** Macro to check the input UART_AUTOBAUD_MODE parameters */\r
-#define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))\r
-\r
-/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */\r
-#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \\r
- (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))\r
-\r
-/** Macro to check the input UART_IrDA_PULSEDIV parameters */\r
-#define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \\r
-|| (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \\r
-|| (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \\r
-|| (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))\r
-\r
-/* Macro to check the input UART1_SignalState parameters */\r
-#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))\r
-\r
-/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */\r
-#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))\r
-\r
-/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */\r
-#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \\r
-|| (x==UART1_MODEM_MODE_AUTO_CTS))\r
-\r
-/** Macro to check the direction control pin type */\r
-#define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART_RS485_DIRCTRL_RTS) || (x==UART_RS485_DIRCTRL_DTR)|| (x==UART_RS485_DIRCTRL_DIR))\r
-\r
-/* Macro to determine if it is valid UART port number */\r
-#define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_USART0)) \\r
-|| (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \\r
-|| (((uint32_t *)x)==((uint32_t *)LPC_USART2)) \\r
-|| (((uint32_t *)x)==((uint32_t *)LPC_USART3)))\r
-#define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_USART3))\r
-#define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))\r
-\r
-/** Macro to check the input value for UART_RS485_CFG_MATCHADDRVALUE parameter */\r
-#define PARAM_UART_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))\r
-\r
-/** Macro to check the input value for UART_RS485_CFG_DELAYVALUE parameter */\r
-#define PARAM_UART_RS485_CFG_DELAYVALUE(x) ((x<0xFF))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup UART_Public_Types UART Public Types\r
- * @{\r
- */\r
-\r
-/***********************************************************************\r
- * @brief UART enumeration\r
-**********************************************************************/\r
-/**\r
- * @brief UART Databit type definitions\r
- */\r
-typedef enum {\r
- UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */\r
- UART_DATABIT_6, /*!< UART 6 bit data mode */\r
- UART_DATABIT_7, /*!< UART 7 bit data mode */\r
- UART_DATABIT_8 /*!< UART 8 bit data mode */\r
-} UART_DATABIT_Type;\r
-\r
-/**\r
- * @brief UART Stop bit type definitions\r
- */\r
-typedef enum {\r
- UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */\r
- UART_STOPBIT_2 /*!< UART Two Stop Bits Select */\r
-} UART_STOPBIT_Type;\r
-\r
-/**\r
- * @brief UART Parity type definitions\r
- */\r
-typedef enum {\r
- UART_PARITY_NONE = 0, /*!< No parity */\r
- UART_PARITY_ODD, /*!< Odd parity */\r
- UART_PARITY_EVEN, /*!< Even parity */\r
- UART_PARITY_SP_1, /*!< Forced "1" stick parity */\r
- UART_PARITY_SP_0 /*!< Forced "0" stick parity */\r
-} UART_PARITY_Type;\r
-\r
-/**\r
- * @brief FIFO Level type definitions\r
- */\r
-typedef enum {\r
- UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */\r
- UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */\r
- UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */\r
- UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */\r
-} UART_FITO_LEVEL_Type;\r
-\r
-\r
-/********************************************************************//**\r
-* @brief UART Interrupt Type definitions\r
-**********************************************************************/\r
-typedef enum {\r
- UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/\r
- UART_INTCFG_THRE, /*!< THR Interrupt enable*/\r
- UART_INTCFG_RLS, /*!< RX line status interrupt enable*/\r
- UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */\r
- UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */\r
- UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */\r
- UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */\r
-} UART_INT_Type;\r
-\r
-/**\r
- * @brief UART Line Status Type definition\r
- */\r
-typedef enum {\r
- UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/\r
- UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/\r
- UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/\r
- UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/\r
- UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/\r
- UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/\r
- UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/\r
- UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/\r
-} UART_LS_Type;\r
-\r
-/**\r
- * @brief UART Auto-baudrate mode type definition\r
- */\r
-typedef enum {\r
- UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */\r
- UART_AUTOBAUD_MODE1 /**< UART Auto baudrate Mode 1 */\r
-} UART_AB_MODE_Type;\r
-\r
-/**\r
- * @brief Auto Baudrate mode configuration type definition\r
- */\r
-typedef struct {\r
- UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */\r
- FunctionalState AutoRestart; /**< Auto Restart state */\r
-} UART_AB_CFG_Type;\r
-\r
-/**\r
- * @brief UART End of Auto-baudrate type definition\r
- */\r
-typedef enum {\r
- UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */\r
- UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */\r
-}UART_ABEO_Type;\r
-\r
-/**\r
- * UART IrDA Control type Definition\r
- */\r
-typedef enum {\r
- UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk\r
- - Configures the pulse when FixPulseEn = 1 */\r
- UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk\r
- - Configures the pulse when FixPulseEn = 1 */\r
- UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk\r
- - Configures the pulse when FixPulseEn = 1 */\r
- UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk\r
- - Configures the pulse when FixPulseEn = 1 */\r
- UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk\r
- - Configures the pulse when FixPulseEn = 1 */\r
- UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk\r
- - Configures the pulse when FixPulseEn = 1 */\r
- UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk\r
- - Configures the pulse when FixPulseEn = 1 */\r
- UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk\r
- - Configures the pulse when FixPulseEn = 1 */\r
-} UART_IrDA_PULSE_Type;\r
-\r
-/********************************************************************//**\r
-* @brief UART1 Full modem - Signal states definition\r
-**********************************************************************/\r
-typedef enum {\r
- INACTIVE = 0, /* In-active state */\r
- ACTIVE = !INACTIVE /* Active state */\r
-}UART1_SignalState;\r
-\r
-/**\r
- * @brief UART modem status type definition\r
- */\r
-typedef enum {\r
- UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */\r
- UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */\r
- UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */\r
- UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */\r
- UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */\r
- UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */\r
- UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */\r
- UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */\r
-} UART_MODEM_STAT_type;\r
-\r
-/**\r
- * @brief Modem output pin type definition\r
- */\r
-typedef enum {\r
- UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */\r
- UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */\r
-} UART_MODEM_PIN_Type;\r
-\r
-/**\r
- * @brief UART Modem mode type definition\r
- */\r
-typedef enum {\r
- UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */\r
- UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */\r
- UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */\r
-} UART_MODEM_MODE_Type;\r
-\r
-/**\r
- * @brief UART Direction Control Pin type definition\r
- */\r
-typedef enum {\r
- UART_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */\r
- UART_RS485_DIRCTRL_DTR, /**< Pin DTR is used for direction control */\r
- UART_RS485_DIRCTRL_DIR /**< Pin DIR is used for direction control */\r
-} UART_RS485_DIRCTRL_PIN_Type;\r
-\r
-\r
-/********************************************************************//**\r
-* @brief UART Configuration Structure definition\r
-**********************************************************************/\r
-typedef struct {\r
- uint32_t Baud_rate; /**< UART baud rate */\r
- UART_PARITY_Type Parity; /**< Parity selection, should be:\r
- - UART_PARITY_NONE: No parity\r
- - UART_PARITY_ODD: Odd parity\r
- - UART_PARITY_EVEN: Even parity\r
- - UART_PARITY_SP_1: Forced "1" stick parity\r
- - UART_PARITY_SP_0: Forced "0" stick parity\r
- */\r
- UART_DATABIT_Type Databits; /**< Number of data bits, should be:\r
- - UART_DATABIT_5: UART 5 bit data mode\r
- - UART_DATABIT_6: UART 6 bit data mode\r
- - UART_DATABIT_7: UART 7 bit data mode\r
- - UART_DATABIT_8: UART 8 bit data mode\r
- */\r
- UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:\r
- - UART_STOPBIT_1: UART 1 Stop Bits Select\r
- - UART_STOPBIT_2: UART 2 Stop Bits Select\r
- */\r
-} UART_CFG_Type;\r
-\r
-/********************************************************************//**\r
-* @brief UART FIFO Configuration Structure definition\r
-**********************************************************************/\r
-\r
-typedef struct {\r
- FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:\r
- - ENABLE: Reset Rx FIFO in UART\r
- - DISABLE: Do not reset Rx FIFO in UART\r
- */\r
- FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:\r
- - ENABLE: Reset Tx FIFO in UART\r
- - DISABLE: Do not reset Tx FIFO in UART\r
- */\r
- FunctionalState FIFO_DMAMode; /**< DMA mode, should be:\r
- - ENABLE: Enable DMA mode in UART\r
- - DISABLE: Disable DMA mode in UART\r
- */\r
- UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:\r
- - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character\r
- - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character\r
- - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character\r
- - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character\r
- */\r
-} UART_FIFO_CFG_Type;\r
-\r
-/********************************************************************//**\r
-* @brief UART1 Full modem - RS485 Control configuration type\r
-**********************************************************************/\r
-typedef struct {\r
- FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:\r
- - ENABLE: Enable this function.\r
- - DISABLE: Disable this function. */\r
- FunctionalState Rx_State; /*!< Receiver State:\r
- - ENABLE: Enable Receiver.\r
- - DISABLE: Disable Receiver. */\r
- FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:\r
- - ENABLE: ENABLE this function.\r
- - DISABLE: Disable this function. */\r
- FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:\r
- - ENABLE: Enable this function.\r
- - DISABLE: Disable this function. */\r
- UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:\r
- - UART1_RS485_DIRCTRL_RTS:\r
- pin RTS is used for direction control.\r
- - UART1_RS485_DIRCTRL_DTR:\r
- pin DTR is used for direction control. */\r
- SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on\r
- the RTS (or DTR) pin:\r
- - RESET: The direction control pin will be driven\r
- to logic "0" when the transmitter has data to be sent.\r
- - SET: The direction control pin will be driven\r
- to logic "1" when the transmitter has data to be sent. */\r
- uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */\r
- uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */\r
-} UART_RS485_CTRLCFG_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup UART_Public_Functions UART Public Functions\r
- * @{\r
- */\r
-/* UART Init/DeInit functions --------------------------------------------------*/\r
-void UART_Init(LPC_USARTn_Type *UARTx, UART_CFG_Type *UART_ConfigStruct);\r
-void UART_DeInit(LPC_USARTn_Type* UARTx);\r
-void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);\r
-\r
-/* UART Send/Receive functions -------------------------------------------------*/\r
-void UART_SendByte(LPC_USARTn_Type* UARTx, uint8_t Data);\r
-uint8_t UART_ReceiveByte(LPC_USARTn_Type* UARTx);\r
-uint32_t UART_Send(LPC_USARTn_Type *UARTx, uint8_t *txbuf,\r
- uint32_t buflen, TRANSFER_BLOCK_Type flag);\r
-uint32_t UART_Receive(LPC_USARTn_Type *UARTx, uint8_t *rxbuf, \\r
- uint32_t buflen, TRANSFER_BLOCK_Type flag);\r
-\r
-/* UART FIFO functions ----------------------------------------------------------*/\r
-void UART_FIFOConfig(LPC_USARTn_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg);\r
-void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);\r
-\r
-/* UART operate functions -------------------------------------------------------*/\r
-void UART_IntConfig(LPC_USARTn_Type *UARTx, UART_INT_Type UARTIntCfg, \\r
- FunctionalState NewState);\r
-void UART_ABCmd(LPC_USARTn_Type *UARTx, UART_AB_CFG_Type *ABConfigStruct, \\r
- FunctionalState NewState);\r
-void UART_TxCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);\r
-uint8_t UART_GetLineStatus(LPC_USARTn_Type* UARTx);\r
-FlagStatus UART_CheckBusy(LPC_USARTn_Type *UARTx);\r
-void UART_ForceBreak(LPC_USARTn_Type* UARTx);\r
-\r
-/* UART1 FullModem functions ----------------------------------------------------*/\r
-void UART_FullModemForcePinState(LPC_UART1_Type *UARTx, UART_MODEM_PIN_Type Pin, \\r
- UART1_SignalState NewState);\r
-void UART_FullModemConfigMode(LPC_UART1_Type *UARTx, UART_MODEM_MODE_Type Mode, \\r
- FunctionalState NewState);\r
-uint8_t UART_FullModemGetStatus(LPC_UART1_Type *UARTx);\r
-\r
-/* UART RS485 functions ----------------------------------------------------------*/\r
-void UART_RS485Config(LPC_USARTn_Type *UARTx, \\r
- UART_RS485_CTRLCFG_Type *RS485ConfigStruct);\r
-void UART_RS485ReceiverCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);\r
-void UART_RS485SendSlvAddr(LPC_USARTn_Type *UARTx, uint8_t SlvAddr);\r
-uint32_t UART_RS485SendData(LPC_USARTn_Type *UARTx, uint8_t *pData, uint32_t size);\r
-\r
-/* UART IrDA functions-------------------------------------------------------------*/\r
-void UART_IrDAInvtInputCmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);\r
-void UART_IrDACmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);\r
-void UART_IrDAPulseDivConfig(LPC_USARTn_Type *UARTx, UART_IrDA_PULSE_Type PulseDiv);\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* __LPC18XX_UART_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-#ifndef _LPC18XX_UTILS_H\r
-#define _LPC18XX_UTILS_H\r
-\r
-#include "lpc_types.h"\r
-extern uint32_t msec;\r
-extern volatile uint32_t u32Milliseconds;\r
-void SysTick_Handler (void);\r
-int timer_delay_us( int cnt);\r
-int timer_delay_ms( int cnt);\r
-#endif\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_wwdt.h 2011-06-02\r
-*//**\r
-* @file lpc18xx_wwdt.h\r
-* @brief Contains all macro definitions and function prototypes\r
-* support for WWDT firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @defgroup WWDT WWDT (Windowed WatchDog Timer)\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-\r
-#ifndef LPC18XX_WWDT_H_\r
-#define LPC18XX_WWDT_H_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc_types.h"\r
-\r
-\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup WWDT_Public_Macros WWDT Public Macros\r
- * @{\r
- */\r
-/** WDT oscillator frequency value */\r
-#define WDT_OSC (12000000UL) /* WWDT uses IRC clock */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @defgroup WWDT_Private_Macros WWDT Private Macros\r
- * @{\r
- */\r
-// time is calculated by usec\r
-#define WDT_GET_FROM_USEC(time) ((time*10)/((WWDT_US_INDEX *10 * 4)/WDT_OSC))\r
-#define WDT_GET_USEC(counter) ((counter * ((WWDT_US_INDEX *10 * 4)/WDT_OSC))/10)\r
-\r
-\r
-/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
-/** WWDT interrupt enable bit */\r
-#define WWDT_WDMOD_WDEN ((uint32_t)(1<<0))\r
-/** WWDT interrupt enable bit */\r
-#define WWDT_WDMOD_WDRESET ((uint32_t)(1<<1))\r
-/** WWDT time out flag bit */\r
-#define WWDT_WDMOD_WDTOF ((uint32_t)(1<<2))\r
-/** WDT Time Out flag bit */\r
-#define WWDT_WDMOD_WDINT ((uint32_t)(1<<3))\r
-/** WWDT Protect flag bit */\r
-#define WWDT_WDMOD_WDPROTECT ((uint32_t)(1<<4))\r
-\r
-/** Define divider index for microsecond ( us ) */\r
-#define WWDT_US_INDEX ((uint32_t)(1000000))\r
-\r
-/** WWDT Time out minimum value */\r
-#define WWDT_TIMEOUT_MIN ((uint32_t)(0xFF))\r
-/** WWDT Time out maximum value */\r
-#define WWDT_TIMEOUT_MAX ((uint32_t)(0x00FFFFFF))\r
-\r
-/** WWDT Warning minimum value */\r
-#define WWDT_WARNINT_MIN ((uint32_t)(0xFF))\r
-/** WWDT Warning maximum value */\r
-#define WWDT_WARNINT_MAX ((uint32_t)(0x000003FF))\r
-\r
-/** WWDT Windowed minimum value */\r
-#define WWDT_WINDOW_MIN ((uint32_t)(0xFF))\r
-/** WWDT Windowed minimum value */\r
-#define WWDT_WINDOW_MAX ((uint32_t)(0x00FFFFFF))\r
-\r
-/** WWDT timer constant register mask */\r
-#define WWDT_WDTC_MASK ((uint32_t)(0x00FFFFFF))\r
-/** WWDT warning value register mask */\r
-#define WWDT_WDWARNINT_MASK ((uint32_t)(0x000003FF))\r
-/** WWDT feed sequence register mask */\r
-#define WWDT_WDFEED_MASK ((uint32_t)(0x000000FF))\r
-\r
-/** WWDT flag */\r
-#define WWDT_WARNINT_FLAG ((uint8_t)(0))\r
-#define WWDT_TIMEOUT_FLAG ((uint8_t)(1))\r
-\r
-/** WWDT mode definitions */\r
-#define WWDT_PROTECT_MODE ((uint8_t)(0))\r
-#define WWDT_RESET_MODE ((uint8_t)(1))\r
-\r
-\r
-/* WWDT Timer value definition (us) */\r
-#define WWDT_TIMEOUT_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MIN)))//microseconds\r
-#define WWDT_TIMEOUT_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MAX)))\r
-\r
-#define WWDT_TIMEWARN_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MIN)))\r
-#define WWDT_TIMEWARN_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MAX)))\r
-\r
-#define WWDT_TIMEWINDOWED_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MIN)))\r
-#define WWDT_TIMEWINDOWED_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MAX)))\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup WWDT_Public_Types WWDT Public Types\r
- * @{\r
- */\r
-/********************************************************************//**\r
- * @brief WWDT structure definitions\r
- **********************************************************************/\r
-typedef struct Wdt_Config\r
-{\r
- uint8_t wdtReset; /**< if ENABLE -> the Reset bit is enabled */\r
- uint8_t wdtProtect; /**< if ENABLE -> the Protect bit is enabled */\r
- uint32_t wdtTmrConst; /**< Set the constant value to timeout the WDT (us) */\r
- uint32_t wdtWarningVal; /**< Set the value to warn the WDT with interrupt (us) */\r
- uint32_t wdtWindowVal; /**< Set a window vaule for WDT (us) */\r
-}st_Wdt_Config;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @defgroup WWDT_Public_Functions WWDT Public Functions\r
- * @{\r
- */\r
-\r
-void WWDT_Init(void);\r
-void WWDT_UpdateTimeOut(uint32_t TimeOut);\r
-void WWDT_Feed (void);\r
-void WWDT_SetWarning(uint32_t WarnTime);\r
-void WWDT_SetWindow(uint32_t WindowedTime);\r
-void WWDT_Configure(st_Wdt_Config wdtCfg);\r
-void WWDT_Start(void);\r
-FlagStatus WWDT_GetStatus (uint8_t Status);\r
-void WWDT_ClearStatusFlag (uint8_t flag);\r
-uint32_t WWDT_GetCurrentCount(void);\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* LPC18XX_WWDT_H_ */\r
-\r
-/**\r
- * @}\r
- */\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc_types.h 2011-06-02\r
-*//**\r
-* @file lpc_types.h\r
-* @brief Contains the NXP ABL typedefs for C standard types.\r
-* It is intended to be used in ISO C conforming development\r
-* environments and checks for this insofar as it is possible\r
-* to do so.\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Type group ----------------------------------------------------------- */\r
-/** @defgroup LPC_Types LPC_Types\r
- * @ingroup LPC1800CMSIS_FwLib_Drivers\r
- * @{\r
- */\r
-\r
-#ifndef LPC_TYPES_H\r
-#define LPC_TYPES_H\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include <stdint.h>\r
-\r
-\r
-/* Public Types --------------------------------------------------------------- */\r
-/** @defgroup LPC_Types_Public_Types LPC_Types Public Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Boolean Type definition\r
- */\r
-typedef enum {FALSE = 0, TRUE = !FALSE} Bool;\r
-\r
-/**\r
- * @brief Flag Status and Interrupt Flag Status type definition\r
- */\r
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;\r
-#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))\r
-\r
-/**\r
- * @brief Functional State Definition\r
- */\r
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
-#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))\r
-\r
-/**\r
- * @ Status type definition\r
- */\r
-typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;\r
-\r
-\r
-/**\r
- * Read/Write transfer type mode (Block or non-block)\r
- */\r
-typedef enum\r
-{\r
- NONE_BLOCKING = 0, /**< None Blocking type */\r
- BLOCKING, /**< Blocking type */\r
-} TRANSFER_BLOCK_Type;\r
-\r
-\r
-/** Pointer to Function returning Void (any number of parameters) */\r
-typedef void (*PFV)();\r
-\r
-/** Pointer to Function returning int32_t (any number of parameters) */\r
-typedef int32_t(*PFI)();\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Macros -------------------------------------------------------------- */\r
-/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros\r
- * @{\r
- */\r
-\r
-/* _BIT(n) sets the bit at position "n"\r
- * _BIT(n) is intended to be used in "OR" and "AND" expressions:\r
- * e.g., "(_BIT(3) | _BIT(7))".\r
- */\r
-#undef _BIT\r
-/* Set bit macro */\r
-#define _BIT(n) (1<<(n))\r
-\r
-/* _SBF(f,v) sets the bit field starting at position "f" to value "v".\r
- * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:\r
- * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"\r
- */\r
-#undef _SBF\r
-/* Set bit field macro */\r
-#define _SBF(f,v) ((v)<<(f))\r
-\r
-/* _BITMASK constructs a symbol with 'field_width' least significant\r
- * bits set.\r
- * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF\r
- * The symbol is intended to be used to limit the bit field width\r
- * thusly:\r
- * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.\r
- * If "any_expression" results in a value that is larger than can be\r
- * contained in 'x' bits, the bits above 'x - 1' are masked off. When\r
- * used with the _SBF example above, the example would be written:\r
- * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))\r
- * This ensures that the value written to a_reg is no wider than\r
- * 16 bits, and makes the code easier to read and understand.\r
- */\r
-#undef _BITMASK\r
-/* Bitmask creation macro */\r
-#define _BITMASK(field_width) ( _BIT(field_width) - 1)\r
-\r
-/* NULL pointer */\r
-#ifndef NULL\r
-#define NULL ((void*) 0)\r
-#endif\r
-\r
-/* Number of elements in an array */\r
-#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))\r
-\r
-/* Static data/function define */\r
-#define STATIC static\r
-/* External data/function define */\r
-#define EXTERN extern\r
-\r
-#if !defined(MAX)\r
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))\r
-#endif\r
-#if !defined(MIN)\r
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Old Type Definition compatibility ------------------------------------------ */\r
-/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types\r
- * @{\r
- */\r
-\r
-/** SMA type for character type */\r
-typedef char CHAR;\r
-\r
-/** SMA type for 8 bit unsigned value */\r
-typedef uint8_t UNS_8;\r
-\r
-/** SMA type for 8 bit signed value */\r
-typedef int8_t INT_8;\r
-\r
-/** SMA type for 16 bit unsigned value */\r
-typedef uint16_t UNS_16;\r
-\r
-/** SMA type for 16 bit signed value */\r
-typedef int16_t INT_16;\r
-\r
-/** SMA type for 32 bit unsigned value */\r
-typedef uint32_t UNS_32;\r
-\r
-/** SMA type for 32 bit signed value */\r
-typedef int32_t INT_32;\r
-\r
-/** SMA type for 64 bit signed value */\r
-typedef int64_t INT_64;\r
-\r
-/** SMA type for 64 bit unsigned value */\r
-typedef uint64_t UNS_64;\r
-\r
-/** 32 bit boolean type */\r
-typedef Bool BOOL_32;\r
-\r
-/** 16 bit boolean type */\r
-typedef Bool BOOL_16;\r
-\r
-/** 8 bit boolean type */\r
-typedef Bool BOOL_8;\r
-\r
-#ifdef __CC_ARM\r
-#define INLINE __inline\r
-#else\r
-#define INLINE inline\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-#endif /* LPC_TYPES_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/***********************************************************************
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#ifndef SPIFI_ROM_API_H
-#define SPIFI_ROM_API_H
-
-#include <stdint.h>
-/* define the symbol TESTING in the environment if test output desired */
-
-/* maintain LONGEST_PROT >= the length (in bytes) of the largest
- protection block of any serial flash that this driver handles */
-#define LONGEST_PROT 68
-
-typedef uint8_t uc;
-
-#ifndef NULL
-#define NULL ((void *)0)
-#endif
-
-/* protection/sector descriptors */
-typedef struct {
- uint32_t base;
- uc flags;
- int8_t log2;
- uint16_t rept;
-} protEnt;
-/* bits in the flags byte */
-enum {RWPROT=1};
-
-/* overall data structure includes # sectors, length of protection reg,
- array of descriptors
-typedef struct {
- uint16_t sectors;
- uint16_t protBytes;
- protEnt *entries;
-} protDesc; */
-
-typedef union {
- uint16_t hw;
- uc byte[2];
-}stat_t;
-/* the object that init returns, and other routines use as an operand */
-typedef struct {
- uint32_t base, regbase, devSize, memSize;
- uc mfger, devType, devID, busy;
- stat_t stat;
- uint16_t reserved;
- uint16_t set_prot, write_prot;
- uint32_t mem_cmd, prog_cmd;
- uint16_t sectors, protBytes;
- uint32_t opts, errCheck;
- uc erase_shifts[4], erase_ops[4];
- protEnt *protEnts;
- char prot[LONGEST_PROT];
-} SPIFIobj;
-
-/* operands of program and erase */
-typedef struct {
- char *dest;
- uint32_t length;
- char *scratch;
- int32_t protect;
- uint32_t options;
-} SPIFIopers;
-
-/* instruction classes for wait_busy */
-typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type;
-
-/* bits in options operands (MODE3, RCVCLK, and FULLCLK
- have the same relationship as in the Control register) */
-#define S_MODE3 1
-#define S_MODE0 0
-#define S_MINIMAL 2
-#define S_MAXIMAL 0
-#define S_FORCE_ERASE 4
-#define S_ERASE_NOT_REQD 8
-#define S_CALLER_ERASE 8
-#define S_ERASE_AS_REQD 0
-#define S_VERIFY_PROG 0x10
-#define S_VERIFY_ERASE 0x20
-#define S_NO_VERIFY 0
-#define S_RCVCLK 0x80
-#define S_INTCLK 0
-#define S_FULLCLK 0x40
-#define S_HALFCLK 0
-#define S_DUAL 0x100
-#define S_CALLER_PROT 0x200
-#define S_DRIVER_PROT 0
-
-/* the following values in the first post-address memory command byte work
- for all known quad devices that support "no opcode" operation */
-#define NO_OPCODE_FOLLOWS 0xA5
-#define OPCODE_FOLLOWS 0xFF
-
-/* basic SPI commands for serial flash */
-#define BASE_READ_CMD (CMD_RD<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|UNL_DATA)
-#define FAST_READ_CMD (CMD_READ_FAST<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|1<<INTLEN_SHIFT|UNL_DATA)
-#define BASE_PROG_CMD (CMD_PROG<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|DOUT)
-
-/* the length of a standard program command is 256 on all devices */
-#define PROG_SIZE 256
-
-/* options in obj->opts (mostly for setMulti) */
-/* used by Winbond: send 0xA3 command so hardware can read faster */
-#define OPT_SEND_A3 1
-/* used by SST: send 0x38 command to enable quad and allow full command set */
-#define OPT_SEND_38 2
-/* used by Winbond and others: read status reg 2, check it,
- if necessary write it back with Quad Enable set */
-#define OPT_35_OR02_01 4
-/* used by Atmel: read Configuration register, if necessary set Quad Enable */
-#define OPT_3F_OR80_3E 8
-/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */
-#define OPT_65_CLR_C0_61 0x10
-/* used by Numonyx: send 0x81 command to write Volatile Configuration Register
- to set # dummy bytes and allow XIP mode */
-#define OPT_81 0x20
-/* set for devices without full device erase command (Numonyx type 0x40) */
-#define OPT_NO_DEV_ERASE 0x40
-/* used by Macronix: status reg 2 includes selection between write-protect
- in status reg and command-based */
-#define OPT_WPSEL 0x80
-/* set when protection data has been read into the SPIFI object */
-#define OPT_PROT_READ 0x100
-/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */
-#define OPT_4BAD 0x200
-/* set if setMulti should set the Dual bit in Control reg */
-#define OPT_DUAL 0x400
-/* send "# dummy bits" in C0 command to Winbond */
-#define OPT_C0 0x800
-/* set QE for Chingis */
-#define OPT_05_OR40_01 0x1000
-/* write status does not go busy */
-#define OPT_01_NO_BUSY 0x2000
-/* protection mode bits moved from protMode byte to opts Fri May 13 2011 */
-#define OPT_PROT_STAT 0x4000
-#define OPT_PROT_REG 0x8000
-#define OPT_PROT_CMD3 0x10000
-#define OPT_PROT_CMDE 0x20000
-#define OPT_PROT_MASK 0x3C000
-
-#define OPT_ALL_QUAD 0x40000
-
-#ifndef OMIT_ROM_TABLE
-/* interface to ROM API */
-typedef struct {
- int32_t (*spifi_init) (SPIFIobj *obj, uint32_t csHigh, uint32_t options,
- uint32_t mhz);
- int32_t (*spifi_program) (SPIFIobj *obj, char *source, SPIFIopers *opers);
- int32_t (*spifi_erase) (SPIFIobj *obj, SPIFIopers *opers);
- /* mode switching */
- void (*cancel_mem_mode)(SPIFIobj *obj);
- void (*set_mem_mode) (SPIFIobj *obj);
-
- /* mid level functions */
- int32_t (*checkAd) (SPIFIobj *obj, SPIFIopers *opers);
- int32_t (*setProt) (SPIFIobj *obj, SPIFIopers *opers, char *change,
- char *saveProt);
- int32_t (*check_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
- uint32_t check_program);
- int32_t (*send_erase_cmd) (SPIFIobj *obj, uint8_t op, uint32_t addr);
- uint32_t (*ck_erase) (SPIFIobj *obj, uint32_t *addr, uint32_t length);
- int32_t (*prog_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
- uint32_t *left_in_page);
- uint32_t (*ck_prog) (SPIFIobj *obj, char *source, char *dest, uint32_t length);
-
- /* low level functions */
- void(*setSize) (SPIFIobj *obj, int32_t value);
- int32_t (*setDev) (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd,
- uint32_t prog_cmd);
- uint32_t (*cmd) (uc op, uc addrLen, uc intLen, uint16_t len);
- uint32_t (*readAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr);
- void (*send04) (SPIFIobj *obj, uc op, uc len, uint32_t value);
- void (*wren_sendAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
- int32_t (*write_stat) (SPIFIobj *obj, uc len, uint16_t value);
- int32_t (*wait_busy) (SPIFIobj *obj, uc prog_or_erase);
-} SPIFI_RTNS;
-
-#define define_spifi_romPtr(name) const SPIFI_RTNS *name=*((SPIFI_RTNS **)SPIFI_ROM_PTR)
-#endif /* OMIT_ROM_TABLE */
-
-#ifdef USE_SPIFI_LIB
-extern SPIFI_RTNS spifi_table;
-#endif /* USE_SPIFI_LIB */
-
-/* example of using this interface:
-#include "spifi_rom_api.h"
-#define CSHIGH 4
-#define SPIFI_MHZ 80
-#define source_data_ad (char *)1234
-
- int32_t rc;
- SPIFIopers opers;
-
- define_spifi_romPtr(spifi);
- SPIFIobj *obj = malloc(sizeof(SPIFIobj));
- if (!obj) { can't allocate memory }
-
- rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ);
- if (rc) { investigate init error rc }
- printf ("the serial flash contains %d bytes\n", obj->devSize);
-
- opers.dest = where_to_program;
- opers.length = how_many_bytes;
- opers.scratch = NULL; // unprogrammed data is not saved/restored
- opers.protect = -1; // save & restore protection
- opers.options = S_VERIFY_PROG;
-
- rc = spifi->spifi_program (obj, source_data_ad, &opers);
- if (rc) { investigate program error rc }
-*/
-
-/* these are for normal users, including boot code */
-int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz);
-int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers);
-int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers);
-
-/* these are used by the manufacturer-specific init functions */
-void setSize (SPIFIobj *obj, int32_t value);
-int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd);
-uint32_t read04(SPIFIobj *obj, uc op, uc len);
-int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value);
-void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen);
-
-/* needs to be defined for each platform */
-void pullMISO(int high);
-
-#ifdef TESTING
-/* used by testing code */
-unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors);
-/* predeclare a debug routine */
-void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value);
-#endif
-
-#endif /* SPIFI_ROM_API_H */
+++ /dev/null
-/**********************************************************************\r
-* $Id$ system_LPC18xx.h 2011-06-02\r
-*//**\r
-* @file system_LPC18xx.h\r
-* @brief Cortex-M3 Device System Header File for NXP LPC18xx Series.\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-#ifndef __SYSTEM_LPC18xx_H\r
-#define __SYSTEM_LPC18xx_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-#include <stdint.h>\r
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
-\r
-/**\r
- * Initialize the system\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Setup the microcontroller system.\r
- * Initialize the System and update the SystemCoreClock variable.\r
- */\r
-extern void SystemInit (void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __SYSTEM_LPC18xx_H */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ debug_frmwrk.c 2011-06-02\r
-*//**\r
-* @file debug_frmwrk.c\r
-* @brief Contains some utilities that used for debugging through UART\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup DEBUG_FRMWRK\r
- * @{\r
- */\r
-\r
-#ifndef _DEBUG_FRMWRK_\r
-#define _DEBUG_FRMWRK_\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "debug_frmwrk.h"\r
-#include "lpc18xx_scu.h"\r
-#include <stdarg.h>\r
-#include <stdio.h>\r
-\r
-#ifdef CDC_DEBUG_MESSEGES\r
-#include "usbhw.h"\r
-#include "cdcuser.h"\r
-#include "CDCdemo.h"\r
-#include "lpc18xx_utils.h"\r
-#include <string.h>\r
-#endif\r
-\r
-/* Debug framework */\r
-\r
-void (*_db_msg)(LPC_USARTn_Type *UARTx, const void *s);\r
-void (*_db_msg_)(LPC_USARTn_Type *UARTx, const void *s);\r
-void (*_db_char)(LPC_USARTn_Type *UARTx, uint8_t ch);\r
-void (*_db_dec)(LPC_USARTn_Type *UARTx, uint8_t decn);\r
-void (*_db_dec_16)(LPC_USARTn_Type *UARTx, uint16_t decn);\r
-void (*_db_dec_32)(LPC_USARTn_Type *UARTx, uint32_t decn);\r
-void (*_db_hex)(LPC_USARTn_Type *UARTx, uint8_t hexn);\r
-void (*_db_hex_16)(LPC_USARTn_Type *UARTx, uint16_t hexn);\r
-void (*_db_hex_32)(LPC_USARTn_Type *UARTx, uint32_t hexn);\r
-uint8_t (*_db_get_char)(LPC_USARTn_Type *UARTx);\r
-\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Puts a character to UART port\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @param[in] ch Character to put\r
- * @return None\r
- **********************************************************************/\r
-void UARTPutChar (LPC_USARTn_Type *UARTx, uint8_t ch)\r
-{\r
- UART_Send(UARTx, &ch, 1, BLOCKING);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get a character to UART port\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @return character value that returned\r
- **********************************************************************/\r
-uint8_t UARTGetChar (LPC_USARTn_Type *UARTx)\r
-{\r
- uint8_t tmp = 0;\r
- UART_Receive(UARTx, &tmp, 1, BLOCKING);\r
- return(tmp);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Puts a string to UART port\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @param[in] str string to put\r
- * @return None\r
- **********************************************************************/\r
-void UARTPuts(LPC_USARTn_Type *UARTx, const void *str)\r
-{\r
-#ifdef CDC_DEBUG_MESSEGES\r
- int num_of_bytes=0;\r
- num_of_bytes = strlen(str);\r
- timer_delay_us(num_of_bytes);\r
- \r
- USB_WriteEP (CDC_DEP_IN, (unsigned char *)str, num_of_bytes);\r
-#else\r
- uint8_t *s = (uint8_t *) str;\r
-\r
- while (*s)\r
- {\r
- UARTPutChar(UARTx, *s++);\r
- }\r
-#endif \r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Puts a string to UART port and print new line\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @param[in] str String to put\r
- * @return None\r
- **********************************************************************/\r
-void UARTPuts_(LPC_USARTn_Type *UARTx, const void *str)\r
-{\r
- UARTPuts (UARTx, str);\r
- UARTPuts (UARTx, "\n\r");\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Puts a decimal number to UART port\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @param[in] decnum Decimal number (8-bit long)\r
- * @return None\r
- **********************************************************************/\r
-void UARTPutDec(LPC_USARTn_Type *UARTx, uint8_t decnum)\r
-{\r
- uint8_t c1=decnum%10;\r
- uint8_t c2=(decnum/10)%10;\r
- uint8_t c3=(decnum/100)%10;\r
- UARTPutChar(UARTx, '0'+c3);\r
- UARTPutChar(UARTx, '0'+c2);\r
- UARTPutChar(UARTx, '0'+c1);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Puts a decimal number to UART port\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @param[in] decnum Decimal number (8-bit long)\r
- * @return None\r
- **********************************************************************/\r
-void UARTPutDec16(LPC_USARTn_Type *UARTx, uint16_t decnum)\r
-{\r
- uint8_t c1=decnum%10;\r
- uint8_t c2=(decnum/10)%10;\r
- uint8_t c3=(decnum/100)%10;\r
- uint8_t c4=(decnum/1000)%10;\r
- uint8_t c5=(decnum/10000)%10;\r
- UARTPutChar(UARTx, '0'+c5);\r
- UARTPutChar(UARTx, '0'+c4);\r
- UARTPutChar(UARTx, '0'+c3);\r
- UARTPutChar(UARTx, '0'+c2);\r
- UARTPutChar(UARTx, '0'+c1);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Puts a decimal number to UART port\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @param[in] decnum Decimal number (8-bit long)\r
- * @return None\r
- **********************************************************************/\r
-void UARTPutDec32(LPC_USARTn_Type *UARTx, uint32_t decnum)\r
-{\r
- uint8_t c1=decnum%10;\r
- uint8_t c2=(decnum/10)%10;\r
- uint8_t c3=(decnum/100)%10;\r
- uint8_t c4=(decnum/1000)%10;\r
- uint8_t c5=(decnum/10000)%10;\r
- uint8_t c6=(decnum/100000)%10;\r
- uint8_t c7=(decnum/1000000)%10;\r
- uint8_t c8=(decnum/10000000)%10;\r
- uint8_t c9=(decnum/100000000)%10;\r
- uint8_t c10=(decnum/1000000000)%10;\r
- UARTPutChar(UARTx, '0'+c10);\r
- UARTPutChar(UARTx, '0'+c9);\r
- UARTPutChar(UARTx, '0'+c8);\r
- UARTPutChar(UARTx, '0'+c7);\r
- UARTPutChar(UARTx, '0'+c6);\r
- UARTPutChar(UARTx, '0'+c5);\r
- UARTPutChar(UARTx, '0'+c4);\r
- UARTPutChar(UARTx, '0'+c3);\r
- UARTPutChar(UARTx, '0'+c2);\r
- UARTPutChar(UARTx, '0'+c1);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Puts a hex number to UART port\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @param[in] hexnum Hex number (8-bit long)\r
- * @return None\r
- **********************************************************************/\r
-void UARTPutHex (LPC_USARTn_Type *UARTx, uint8_t hexnum)\r
-{\r
- uint8_t nibble, i;\r
-\r
- UARTPuts(UARTx, "0x");\r
- i = 1;\r
- do {\r
- nibble = (hexnum >> (4*i)) & 0x0F;\r
- UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble));\r
- } while (i--);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Puts a hex number to UART port\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @param[in] hexnum Hex number (16-bit long)\r
- * @return None\r
- **********************************************************************/\r
-void UARTPutHex16 (LPC_USARTn_Type *UARTx, uint16_t hexnum)\r
-{\r
- uint8_t nibble, i;\r
-\r
- UARTPuts(UARTx, "0x");\r
- i = 3;\r
- do {\r
- nibble = (hexnum >> (4*i)) & 0x0F;\r
- UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble));\r
- } while (i--);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Puts a hex number to UART port\r
- * @param[in] UARTx Pointer to UART peripheral\r
- * @param[in] hexnum Hex number (32-bit long)\r
- * @return None\r
- **********************************************************************/\r
-void UARTPutHex32 (LPC_USARTn_Type *UARTx, uint32_t hexnum)\r
-{\r
- uint8_t nibble, i;\r
-\r
- UARTPuts(UARTx, "0x");\r
- i = 7;\r
- do {\r
- nibble = (hexnum >> (4*i)) & 0x0F;\r
- UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble));\r
- } while (i--);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief print function that supports format as same as printf()\r
- * function of <stdio.h> library\r
- * @param[in] format formated string to be print\r
- * @return None\r
- **********************************************************************/\r
-void lpc_printf (const char *format, ...)\r
-{\r
- char buffer[512 + 1];\r
- va_list vArgs;\r
- va_start(vArgs, format);\r
- vsprintf((char *)buffer, (char const *)format, vArgs);\r
- va_end(vArgs);\r
-\r
- _DBG(buffer);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Initialize Debug frame work through initializing UART port\r
- * @param[in] None\r
- * @return None\r
- **********************************************************************/\r
-void debug_frmwrk_init(void)\r
-{\r
-#ifdef UART_DEBUG_MESSEGES\r
-\r
- UART_CFG_Type UARTConfigStruct;\r
-\r
-#if (USED_UART_DEBUG_PORT==0)\r
- /*\r
- * Initialize UART0 pin connect NGX board\r
- */\r
- scu_pinmux(0xF ,10 , MD_PDN|MD_EZI, FUNC1); // P6.4 UART0_TXD\r
- scu_pinmux(0xF ,11 , MD_PDN|MD_EZI, FUNC1); // P6.5 UART0_RXD\r
-#elif (USED_UART_DEBUG_PORT==1)\r
- /*\r
- * Initialize UART1 pin connect\r
- */\r
- scu_pinmux(0x1 ,13 , MD_PDN, FUNC1); // PC.13 : UART1_TXD\r
- scu_pinmux(0x1 ,14 , MD_PLN|MD_EZI|MD_ZI, FUNC1); // PC.14 : UART1_RXD\r
-#endif\r
-\r
- /* Initialize UART Configuration parameter structure to default state:\r
- * Baudrate = 9600bps\r
- * 8 data bit\r
- * 1 Stop bit\r
- * None parity\r
- */\r
- UART_ConfigStructInit(&UARTConfigStruct);\r
-\r
- // Initialize DEBUG_UART_PORT peripheral with given to corresponding parameter\r
- UART_Init((LPC_USARTn_Type*)DEBUG_UART_PORT, &UARTConfigStruct);\r
-\r
- // Enable UART Transmit\r
- UART_TxCmd((LPC_USARTn_Type*)DEBUG_UART_PORT, ENABLE);\r
-#endif\r
-#ifdef CDC_DEBUG_MESSEGES\r
- CDC_init(); //wait for usb enumeration\r
-\r
-#endif\r
-\r
- _db_msg = UARTPuts;\r
- _db_msg_ = UARTPuts_;\r
- _db_char = UARTPutChar;\r
- _db_hex = UARTPutHex;\r
- _db_hex_16 = UARTPutHex16;\r
- _db_hex_32 = UARTPutHex32;\r
- _db_dec = UARTPutDec;\r
- _db_dec_16 = UARTPutDec16;\r
- _db_dec_32 = UARTPutDec32;\r
- _db_get_char = UARTGetChar;\r
-}\r
-\r
-#endif /* _DEBUG_FRMWRK_ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_adc.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_adc.c\r
-* @brief Contains all functions support for ADC firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup ADC\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_adc.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _ADC\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup ADC_Public_Functions\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief Initial for ADC\r
- * + Set bit PCADC\r
- * + Set clock for ADC\r
- * + Set Clock Frequency\r
- * @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
- * @param[in] rate ADC conversion rate, should be <=200KHz\r
- * @param[in] bits_accuracy number of bits accuracy, should be <=10 bits and >=3bits\r
- * @return None\r
- **********************************************************************/\r
-void ADC_Init(LPC_ADCn_Type *ADCx, uint32_t rate, uint8_t bits_accuracy)\r
-{\r
- uint32_t temp, tmpreg, ADCbitrate;\r
-\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
- CHECK_PARAM(PARAM_ADC_RATE(rate));\r
-\r
- // Turn on power and clock\r
- //CGU_ConfigPPWR (CGU_PCONP_PCAD, ENABLE);\r
-\r
- ADCx->CR = 0;\r
-\r
- //Enable PDN bit\r
- tmpreg = ADC_CR_PDN;\r
- // Set clock frequency\r
- if(ADCx == LPC_ADC0)\r
- temp = CGU_GetPCLKFrequency(CGU_PERIPHERAL_ADC0);\r
- else if(ADCx == LPC_ADC1)\r
- temp = CGU_GetPCLKFrequency(CGU_PERIPHERAL_ADC1);\r
- /* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for\r
- * A/D converter, which should be less than or equal to 13MHz.\r
- * A fully conversion requires (bits_accuracy+1) of these clocks.\r
- * ADC clock = PCLK_ADC0 / (CLKDIV + 1);\r
- * ADC rate = ADC clock / (bits_accuracy+1);
- */\r
- ADCbitrate = (rate * (bits_accuracy+1));\r
- temp = ((temp*2 + ADCbitrate) / (ADCbitrate*2)) - 1;//get the round value by fomular: (2*A + B)/(2*B)\r
- tmpreg |= ADC_CR_CLKDIV(temp) | ADC_CR_BITACC(10 - bits_accuracy);\r
-\r
- ADCx->CR = tmpreg;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
-* @brief Close ADC\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @return None\r
-**********************************************************************/\r
-void ADC_DeInit(LPC_ADCn_Type *ADCx)\r
-{\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
-\r
- // Clear PDN bit\r
- ADCx->CR &= ~ADC_CR_PDN;\r
- // Turn on power and clock\r
- //CGU_ConfigPPWR (CGU_PCONP_PCAD, DISABLE);\r
-}\r
-\r
-\r
-///*********************************************************************//**\r
-//* @brief Get Result conversion from A/D data register\r
-//* @param[in] channel number which want to read back the result\r
-//* @return Result of conversion\r
-//*********************************************************************/\r
-//uint32_t ADC_GetData(uint32_t channel)\r
-//{\r
-// uint32_t adc_value;\r
-//\r
-// CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel));\r
-//\r
-// adc_value = *(uint32_t *)((&LPC_ADC->DR0) + channel);\r
-// return ADC_GDR_RESULT(adc_value);\r
-//}\r
-\r
-/*********************************************************************//**\r
-* @brief Set start mode for ADC\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @param[in] start_mode Start mode choose one of modes in\r
-* 'ADC_START_OPT' enumeration type definition, should be:\r
-* - ADC_START_CONTINUOUS\r
-* - ADC_START_NOW\r
-* - ADC_START_ON_EINT0\r
-* - ADC_START_ON_CAP01\r
-* - ADC_START_ON_MAT01\r
-* - ADC_START_ON_MAT03\r
-* - ADC_START_ON_MAT10\r
-* - ADC_START_ON_MAT11\r
-* @return None\r
-*********************************************************************/\r
-void ADC_StartCmd(LPC_ADCn_Type *ADCx, uint8_t start_mode)\r
-{\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
- CHECK_PARAM(PARAM_ADC_START_OPT(start_mode));\r
-\r
- ADCx->CR &= ~ADC_CR_START_MASK;\r
- ADCx->CR |=ADC_CR_START_MODE_SEL((uint32_t)start_mode);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
-* @brief ADC Burst mode setting\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @param[in] NewState\r
-* - 1: Set Burst mode\r
-* - 0: reset Burst mode\r
-* @return None\r
-**********************************************************************/\r
-void ADC_BurstCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
-\r
- ADCx->CR &= ~ADC_CR_BURST;\r
- if (NewState){\r
- ADCx->CR |= ADC_CR_BURST;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Set AD conversion in power mode\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @param[in] NewState\r
-* - 1: AD converter is optional\r
-* - 0: AD Converter is in power down mode\r
-* @return None\r
-**********************************************************************/\r
-void ADC_PowerdownCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
-\r
- ADCx->CR &= ~ADC_CR_PDN;\r
- if (NewState){\r
- ADCx->CR |= ADC_CR_PDN;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Set Edge start configuration\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @param[in] EdgeOption is ADC_START_ON_RISING and ADC_START_ON_FALLING\r
-* - 0: ADC_START_ON_RISING\r
-* - 1: ADC_START_ON_FALLING\r
-* @return None\r
-**********************************************************************/\r
-void ADC_EdgeStartConfig(LPC_ADCn_Type *ADCx, uint8_t EdgeOption)\r
-{\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
- CHECK_PARAM(PARAM_ADC_START_ON_EDGE_OPT(EdgeOption));\r
-\r
- ADCx->CR &= ~ADC_CR_EDGE;\r
- if (EdgeOption){\r
- ADCx->CR |= ADC_CR_EDGE;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief ADC interrupt configuration\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @param[in] IntType: type of interrupt, should be:\r
-* - ADC_ADINTEN0: Interrupt channel 0\r
-* - ADC_ADINTEN1: Interrupt channel 1\r
-* ...\r
-* - ADC_ADINTEN7: Interrupt channel 7\r
-* - ADC_ADGINTEN: Individual channel/global flag done generate an interrupt\r
-* @param[in] NewState:\r
-* - SET : enable ADC interrupt\r
-* - RESET: disable ADC interrupt\r
-* @return None\r
-**********************************************************************/\r
-void ADC_IntConfig (LPC_ADCn_Type *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
- CHECK_PARAM(PARAM_ADC_TYPE_INT_OPT(IntType));\r
-\r
- ADCx->INTEN &= ~ADC_INTEN_CH(IntType);\r
- if (NewState){\r
- ADCx->INTEN |= ADC_INTEN_CH(IntType);\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Enable/Disable ADC channel number\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @param[in] Channel channel number\r
-* @param[in] NewState New state, should be:\r
-* - ENABLE\r
-* - DISABLE\r
-* @return None\r
-**********************************************************************/\r
-void ADC_ChannelCmd (LPC_ADCn_Type *ADCx, uint8_t Channel, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
- CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(Channel));\r
-\r
- if (NewState == ENABLE) {\r
- ADCx->CR |= ADC_CR_CH_SEL(Channel);\r
- } else {\r
- ADCx->CR &= ~ADC_CR_CH_SEL(Channel);\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Get ADC result\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @param[in] channel channel number, should be 0...7\r
-* @return Converted data\r
-**********************************************************************/\r
-uint16_t ADC_ChannelGetData(LPC_ADCn_Type *ADCx, uint8_t channel)\r
-{\r
- uint32_t adc_value;\r
-\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
- CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel));\r
-\r
- adc_value = *(uint32_t *) ((&(ADCx->DR[0])) + channel);\r
- return ADC_DR_RESULT(adc_value);\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Get ADC Channel status from ADC data register\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @param[in] channel: channel number, should be 0..7\r
-* @param[in] StatusType\r
-* - 0: Burst status\r
-* - 1: Done status\r
-* @return Channel status, could be:\r
-* - SET\r
-* - RESET\r
-**********************************************************************/\r
-FlagStatus ADC_ChannelGetStatus(LPC_ADCn_Type *ADCx, uint8_t channel, uint32_t StatusType)\r
-{\r
- uint32_t temp;\r
-\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
- CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel));\r
- CHECK_PARAM(PARAM_ADC_DATA_STATUS(StatusType));\r
-\r
- temp = *(uint32_t *) ((&ADCx->DR[0]) + channel);\r
- if (StatusType) {\r
- temp &= ADC_DR_DONE_FLAG;\r
- }else{\r
- temp &= ADC_DR_OVERRUN_FLAG;\r
- }\r
- if (temp) {\r
- return SET;\r
- } else {\r
- return RESET;\r
- }\r
-\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Get ADC Data from AD Global register\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @return Result of conversion\r
-**********************************************************************/\r
-uint32_t ADC_GlobalGetData(LPC_ADCn_Type *ADCx)\r
-{\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
-\r
- return ((uint32_t)(ADCx->GDR));\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Get ADC Chanel status from AD global data register\r
-* @param[in] ADCx pointer to LPC_ADCn_Type, should be: LPC_ADC\r
-* @param[in] StatusType\r
-* - 0: Burst status\r
-* - 1: Done status\r
-* @return SET / RESET\r
-**********************************************************************/\r
-FlagStatus ADC_GlobalGetStatus(LPC_ADCn_Type *ADCx, uint32_t StatusType)\r
-{\r
- uint32_t temp;\r
-\r
- CHECK_PARAM(PARAM_ADCx(ADCx));\r
- CHECK_PARAM(PARAM_ADC_DATA_STATUS(StatusType));\r
-\r
- temp = ADCx->GDR;\r
- if (StatusType){\r
- temp &= ADC_DR_DONE_FLAG;\r
- }else{\r
- temp &= ADC_DR_OVERRUN_FLAG;\r
- }\r
- if (temp){\r
- return SET;\r
- }else{\r
- return RESET;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _ADC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_atimer.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_atimer.c\r
-* @brief Contains all functions support for Alarm Timer firmware\r
-* library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup ATIMER\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_atimer.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-#ifdef _ATIMER\r
-\r
-/* Private Functions ---------------------------------------------------------- */\r
-\r
-/*********************************************************************//**\r
- * @brief Initial Alarm Timer device\r
- * @param[in] ATIMERx Timer selection, should be: LPC_ATIMER\r
- * @param[in] PresetValue Count of 1/1024s for Alarm\r
- * @return None\r
- **********************************************************************/\r
-void ATIMER_Init(LPC_ATIMER_Type *ATIMERx, uint32_t PresetValue)\r
-{\r
- CHECK_PARAM(PARAM_ATIMERx(ATIMERx));\r
-\r
- //set power\r
- if (ATIMERx== LPC_ATIMER)\r
- {\r
- /*Set Clock Here */\r
- CGU_EnableEntity(CGU_CLKSRC_32KHZ_OSC, ENABLE);\r
- }\r
-\r
- ATIMER_UpdatePresetValue(ATIMERx, PresetValue);\r
- // Clear interrupt pending\r
- ATIMER_ClearIntStatus(ATIMERx);\r
-\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Close ATIMER device\r
- * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER\r
- * @return None\r
- **********************************************************************/\r
-void ATIMER_DeInit (LPC_ATIMER_Type *ATIMERx)\r
-{\r
- CHECK_PARAM(PARAM_ATIMERx(ATIMERx));\r
- // Disable atimer\r
- ATIMER_ClearIntStatus(ATIMERx);\r
- ATIMER_IntDisable(ATIMERx);\r
-\r
- // Disable power\r
-// if (ATIMERx== LPC_ATIMER0)\r
-// CGU_ConfigPPWR (CGU_PCONP_PCATIMER0, DISABLE);\r
-\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Clear ATIMER Interrupt Status\r
- * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER\r
- * @return None\r
- **********************************************************************/\r
-void ATIMER_ClearIntStatus(LPC_ATIMER_Type *ATIMERx)\r
-{\r
- CHECK_PARAM(PARAM_ATIMERx(ATIMERx));\r
- ATIMERx->CLR_STAT = 1;\r
- while((ATIMERx->STATUS & 1) == 1);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set ATIMER Interrupt Status\r
- * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER\r
- * @return None\r
- **********************************************************************/\r
-void ATIMER_SetIntStatus(LPC_ATIMER_Type *ATIMERx)\r
-{\r
- CHECK_PARAM(PARAM_ATIMERx(ATIMERx));\r
- ATIMERx->SET_STAT = 1;\r
- while((ATIMERx->STATUS & 1) == 0);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable ATIMER Interrupt\r
- * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER\r
- * @return None\r
- **********************************************************************/\r
-void ATIMER_IntEnable(LPC_ATIMER_Type *ATIMERx)\r
-{\r
- CHECK_PARAM(PARAM_ATIMERx(ATIMERx));\r
- ATIMERx->SET_EN = 1;\r
- while((ATIMERx->ENABLE & 1) == 0);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Disable ATIMER Interrupt\r
- * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER\r
- * @return None\r
- **********************************************************************/\r
-void ATIMER_IntDisable(LPC_ATIMER_Type *ATIMERx)\r
-{\r
- CHECK_PARAM(PARAM_ATIMERx(ATIMERx));\r
- ATIMERx->CLR_EN = 1;\r
- while((ATIMERx->ENABLE & 1) == 1);\r
-}\r
-/*********************************************************************//**\r
- * @brief Update Preset value\r
- * @param[in] ATIMERx Pointer to timer device, should be: LPC_ATIMER\r
- * @param[in] PresetValue updated preset value\r
- * @return None\r
- **********************************************************************/\r
-void ATIMER_UpdatePresetValue(LPC_ATIMER_Type *ATIMERx,uint32_t PresetValue)\r
-{\r
- CHECK_PARAM(PARAM_ATIMERx(ATIMERx));\r
- ATIMERx->PRESET = PresetValue;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Read value of preset register\r
- * @param[in] ATIMERx Pointer to timer/counter device, should be: LPC_ATIMER\r
- * @return Value of capture register\r
- **********************************************************************/\r
-uint32_t ATIMER_GetPresetValue(LPC_ATIMER_Type *ATIMERx)\r
-{\r
- CHECK_PARAM(PARAM_ATIMERx(ATIMERx));\r
- return ATIMERx->PRESET;\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _ATIMER */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_can.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_can.c\r
-* @brief Contains all functions support for C CAN firmware library\r
-* on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup C_CAN\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc18xx_can.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-#ifdef _C_CAN\r
-\r
-/* Private Macros ---------------------------------------------------------- */\r
-#ifndef __GNUC__\r
-/* Macro for reading and writing to CCAN IF registers */\r
-#define CAN_IF_Read(reg, IFsel) (LPC_C_CAN0->##IFsel##_##reg)\r
-#define CAN_IF_Write(reg, IFsel, val) (LPC_C_CAN0->##IFsel##_##reg=val)\r
-\r
-/* Macro for writing IF to specific RAM message object */\r
-#define CAN_IF_readBuf(IFsel,msg) \\r
- LPC_C_CAN0->##IFsel##_##CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \\r
- LPC_C_CAN0->##IFsel##_##CMDREQ=msg; \\r
- while (LPC_C_CAN0->##IFsel##_##CMDREQ & IFCREQ_BUSY );\r
-\r
-/* Macro for reading specific RAM message object to IF */\r
-#define CAN_IF_writeBuf(IFsel,msg) \\r
- LPC_C_CAN0->##IFsel##_##CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \\r
- LPC_C_CAN0->##IFsel##_##CMDREQ=msg; \\r
- while (LPC_C_CAN0->##IFsel##_##CMDREQ & IFCREQ_BUSY );\r
-#else\r
-#define CAN_IF_Read(reg, IFsel) (LPC_C_CAN0->IFsel##_##reg)\r
-#define CAN_IF_Write(reg, IFsel, val) (LPC_C_CAN0->IFsel ## _ ## reg = val)\r
-\r
-/* Macro for writing IF to specific RAM message object */\r
-#define CAN_IF_readBuf(IFsel,msg) \\r
- LPC_C_CAN0->IFsel##_##CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \\r
- LPC_C_CAN0->IFsel##_##CMDREQ=msg; \\r
- while (LPC_C_CAN0->IFsel##_##CMDREQ & IFCREQ_BUSY );\r
-\r
-/* Macro for reading specific RAM message object to IF */\r
-#define CAN_IF_writeBuf(IFsel,msg) \\r
- LPC_C_CAN0->IFsel##_##CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB; \\r
- LPC_C_CAN0->IFsel##_##CMDREQ=msg; \\r
- while (LPC_C_CAN0->IFsel##_##CMDREQ & IFCREQ_BUSY );\r
-#endif\r
-\r
-#define IF1 0\r
-#define IF2 1\r
-\r
-#define CAN_STATUS_INTERRUPT 0x8000 /* 0x0001-0x0020 are the # of the message\r
- object */\r
- /* 0x8000 is the status interrupt */\r
-\r
-/* CAN Message interface register definitions */\r
-/* bit field of IF command request n register */\r
-#define IFCREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when\r
- RD/WR done */\r
-/* CAN CTRL register */\r
-#define CTRL_INIT (1 << 0)\r
-#define CTRL_IE (1 << 1)\r
-#define CTRL_SIE (1 << 2)\r
-#define CTRL_EIE (1 << 3)\r
-#define CTRL_DAR (1 << 5)\r
-#define CTRL_CCE (1 << 6)\r
-#define CTRL_TEST (1 << 7)\r
-\r
-/* CAN Test register */\r
-#define TEST_BASIC (1 << 2)\r
-#define TEST_SILENT (1 << 3)\r
-#define TEST_LBACK (1 << 4)\r
-\r
-/* CAN Status register */\r
-#define STAT_LEC (0x7 << 0)\r
-#define STAT_TXOK (1 << 3)\r
-#define STAT_RXOK (1 << 4)\r
-#define STAT_EPASS (1 << 5)\r
-#define STAT_EWARN (1 << 6)\r
-#define STAT_BOFF (1 << 7)\r
-\r
-#define NO_ERR 0 // No Error\r
-#define STUFF_ERR 1 // Stuff Error : More than 5 equal bits in a sequence have occurred in a part\r
- // of a received message where this is not allowed.\r
-#define FORM_ERR 2 // Form Error : A fixed format part of a received frame has the wrong format.\r
-#define ACK_ERR 3 // AckError : The message this CAN Core transmitted was not acknowledged\r
- // by another node.\r
-#define BIT1_ERR 4 // Bit1Error : During the transmission of a message (with the exception of\r
- // the arbitration field), the device wanted to send a recessive level (bit of\r
- // logical value �1�), but the monitored bus value was dominant.\r
-#define BIT0_ERR 5 // Bit0Error : During the transmission of a message (or acknowledge bit,\r
- // or active error flag, or overload flag), the device wanted to send a\r
- // LOW/dominant level (data or identifier bit logical value �0�), but the\r
- // monitored Bus value was HIGH/recessive. During busoff recovery this\r
- // status is set each time a\r
- // sequence of 11 HIGH/recessive bits has been monitored. This enables\r
- // the CPU to monitor the proceeding of the busoff recovery sequence\r
- // (indicating the bus is not stuck at LOW/dominant or continuously\r
- // disturbed).\r
-#define CRC_ERR 6 // CRCError: The CRC checksum was incorrect in the message received.\r
-\r
-\r
-/* bit field of IF command mask register */\r
-#define DATAB (1 << 0) /* 1 is transfer data byte 4-7 to message object, 0 is not */\r
-#define DATAA (1 << 1) /* 1 is transfer data byte 0-3 to message object, 0 is not */\r
-#define NEWDAT (1 << 2) /* Clear NEWDAT bit in the message object */\r
-#define CLRINTPND (1 << 3)\r
-#define CTRL (1 << 4) /* 1 is transfer the CTRL bit to the message object, 0 is not */\r
-#define ARB (1 << 5) /* 1 is transfer the ARB bits to the message object, 0 is not */\r
-#define MASK (1 << 6) /* 1 is transfer the MASK bit to the message object, 0 is not */\r
-#define WR (1 << 7) /* 0 is READ, 1 is WRITE */\r
-#define RD 0x0000\r
-\r
-/* bit field of IF mask 2 register */\r
-#define MASK_MXTD (1 << 15) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */\r
-#define MASK_MDIR (1 << 14) /* 1 direction bit is used in the RX filter unit, 0 is not */\r
-\r
-/* bit field of IF identifier 2 register */\r
-#define ID_MVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */\r
-#define ID_MTD (1 << 14) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */\r
-#define ID_DIR (1 << 13) /* 1 direction bit is used in the RX filter unit, 0 is not */\r
-\r
-/* bit field of IF message control register */\r
-#define NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */\r
-#define MLST (1 << 14) /* 1 indicates a message loss. */\r
-#define INTP (1 << 13) /* 1 indicates message object is an interrupt source */\r
-#define UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */\r
-#define TXIE (1 << 11) /* 1 is TX interrupt enabled */\r
-#define RXIE (1 << 10) /* 1 is RX interrupt enabled */\r
-\r
-#if REMOTE_ENABLE\r
- #define RMTEN (1 << 9) /* 1 is remote frame enabled */\r
-#else\r
- #define RMTEN 0\r
-#endif\r
-\r
-#define TXRQ (1 << 8) /* 1 is TxRqst enabled */\r
-#define EOB (1 << 7) /* End of buffer, always write to 1 */\r
-#define DLC 0x000F /* bit mask for DLC */\r
-\r
-#define ID_STD_MASK 0x07FF\r
-#define ID_EXT_MASK 0x1FFFFFFF\r
-#define DLC_MASK 0x0F\r
-\r
-/* Private Variables ---------------------------------------------------------- */\r
-/* Statistics of all the interrupts */\r
-/* Buss off status counter */\r
-volatile uint32_t BOffCnt = 0;\r
-/* Warning status counter. At least one of the error counters\r
- in the EML has reached the error warning limit of 96 */\r
-volatile uint32_t EWarnCnt = 0;\r
-/* More than 5 equal bits in a sequence in received message */\r
-volatile uint32_t StuffErrCnt = 0;\r
-/* Wrong format of fixed format part of a received frame */\r
-volatile uint32_t FormErrCnt = 0;\r
-/* Transmitted message not acknowledged. */\r
-volatile uint32_t AckErrCnt = 0;\r
-/* Send a HIGH/recessive level, but monitored LOW/dominant */\r
-volatile uint32_t Bit1ErrCnt = 0;\r
-/* Send a LOW/dominant level, but monitored HIGH/recessive */\r
-volatile uint32_t Bit0ErrCnt = 0;\r
-/* The CRC checksum was incorrect in the message received */\r
-volatile uint32_t CRCErrCnt = 0;\r
-/* Message object new data error counter */\r
-volatile uint32_t ND1ErrCnt = 0;\r
-\r
-MSG_CB TX_cb, RX_cb;\r
-\r
-message_object can_buff[CAN_MSG_OBJ_MAX];\r
-message_object recv_buff;\r
-\r
-#if CAN_DEBUG\r
-uint32_t CANStatusLog[100];\r
-uint32_t CANStatusLogCount = 0;\r
-#endif\r
-\r
-//#ifdef __GNUC__\r
-//uint32_t CAN_IF_Read(uint32_t reg,uint32_t IFsel){\r
-// if(IFsel == IF1){\r
-// return (LPC_C_CAN0->IF1_reg);\r
-// }else{\r
-// return (LPC_C_CAN0->IF2_reg);\r
-// }\r
-//}\r
-//void CAN_IF_Write(uint32_t reg, uint32_t IFsel,uint32_t val){\r
-// if(IFsel == IF1){\r
-// (LPC_C_CAN0->IF1_reg=val);\r
-// }else{\r
-// (LPC_C_CAN0->IF2_reg=val);\r
-// }\r
-//}\r
-//\r
-///* Macro for writing IF to specific RAM message object */\r
-//void CAN_IF_readBuf(uint32_t IFsel,uint32_t msg){\r
-// if(IFsel == IF1){\r
-// LPC_C_CAN0->IF1_CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;\r
-// LPC_C_CAN0->IF1_CMDREQ=msg;\r
-// while (LPC_C_CAN0->IF1_CMDREQ & IFCREQ_BUSY );\r
-// }else{\r
-// LPC_C_CAN0->IF2_CMDMSK_W=RD|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;\r
-// LPC_C_CAN0->IF2_CMDREQ=msg;\r
-// while (LPC_C_CAN0->IF2_CMDREQ & IFCREQ_BUSY );\r
-// }\r
-//\r
-//}\r
-//\r
-///* Macro for reading specific RAM message object to IF */\r
-//void CAN_IF_writeBuf(uint32_t IFsel,uint32_t msg){\r
-// if(IFsel == IF1){\r
-// LPC_C_CAN0->IF1_CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;\r
-// LPC_C_CAN0->IF1_CMDREQ=msg;\r
-// while (LPC_C_CAN0->IF1_CMDREQ & IFCREQ_BUSY );\r
-// }else{\r
-// LPC_C_CAN0->IF2_CMDMSK_W=WR|MASK|ARB|CTRL|CLRINTPND|DATAA|DATAB;\r
-// LPC_C_CAN0->IF2_CMDREQ=msg;\r
-// while (LPC_C_CAN0->IF2_CMDREQ & IFCREQ_BUSY );\r
-// }\r
-//}\r
-//#endif\r
-\r
-/*********************************************************************//**\r
- * @brief Handle valid received message\r
- * @param[in] msg_no Message Object number\r
- * @return None\r
- **********************************************************************/\r
-void CAN_RxInt_MessageProcess( uint8_t msg_no )\r
-{\r
- uint32_t msg_id;\r
- uint32_t *p_add;\r
- uint32_t reg1, reg2;\r
-\r
- /* Import message object to IF2 */\r
- CAN_IF_readBuf(IF2, msg_no); /* Read the message into the IF registers */\r
-\r
- p_add = (uint32_t *)&recv_buff;\r
-\r
- if( CAN_IF_Read(ARB2, IF2) & ID_MTD ) /* bit 28-0 is 29 bit extended frame */\r
- {\r
- /* mask off MsgVal and Dir */\r
- reg1 = CAN_IF_Read(ARB1, IF2);\r
- reg2 = CAN_IF_Read(ARB2, IF2);\r
- msg_id = (reg1|(reg2<<16));\r
- }\r
- else\r
- {\r
- /* bit 28-18 is 11-bit standard frame */\r
- msg_id = (CAN_IF_Read(ARB2, IF2) &0x1FFF) >> 2;\r
- }\r
-\r
- p_add[0] = msg_id;\r
- p_add[1] = CAN_IF_Read(MCTRL, IF2) & 0x000F; /* Get Msg Obj Data length */\r
- p_add[2] = (CAN_IF_Read(DA2, IF2)<<16) | CAN_IF_Read(DA1, IF2);\r
- p_add[3] = (CAN_IF_Read(DB2, IF2)<<16) | CAN_IF_Read(DB1, IF2);\r
-\r
- /* Clear interrupt pending bit */\r
- CAN_IF_Write(MCTRL, IF2, UMSK|RXIE|EOB|CAN_DLC_MAX);\r
- /* Save changes to message RAM */\r
- CAN_IF_writeBuf(IF2, msg_no);\r
-\r
- return;\r
-}\r
-/*********************************************************************//**\r
- * @brief Handle valid transmit message\r
- * @param[in] msg_no Message Object number\r
- * @return None\r
- **********************************************************************/\r
-void CAN_TxInt_MessageProcess( uint8_t msg_no )\r
-{\r
- /* Clear interrupt pending bit */\r
- CAN_IF_Write(MCTRL, IF2, UMSK|RXIE|EOB|CAN_DLC_MAX);\r
- /* Save changes to message RAM */\r
- CAN_IF_writeBuf(IF2,msg_no);\r
- return;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief CAN interrupt handler\r
- * @param[in] None\r
- * @return None\r
- **********************************************************************/\r
-volatile uint32_t nd_tmp;\r
-void CAN_IRQHandler(void)\r
-{\r
- uint32_t canstat = 0;\r
- uint32_t can_int, msg_no;\r
-\r
- while ( (can_int = LPC_C_CAN0->INT) != 0 ) /* While interrupt is pending */\r
- {\r
- canstat = LPC_C_CAN0->STAT; /* Read CAN status register */\r
-\r
- if ( can_int & CAN_STATUS_INTERRUPT )\r
- {\r
- /* Passive state monitored frequently in main. */\r
-\r
- if ( canstat & STAT_EWARN )\r
- {\r
- EWarnCnt++;\r
- return;\r
- }\r
- if ( canstat & STAT_BOFF )\r
- {\r
- BOffCnt++;\r
- return;\r
- }\r
-\r
- switch (canstat&STAT_LEC) /* LEC Last Error Code (Type of the last error to occur on the CAN bus) */\r
- {\r
- case NO_ERR:\r
- break;\r
- case STUFF_ERR:\r
- StuffErrCnt++;\r
- break;\r
- case FORM_ERR:\r
- FormErrCnt++;\r
- break;\r
- case ACK_ERR:\r
- AckErrCnt++;\r
- break;\r
- case BIT1_ERR:\r
- Bit1ErrCnt++;\r
- break;\r
- case BIT0_ERR:\r
- Bit0ErrCnt++;\r
- break;\r
- case CRC_ERR:\r
- CRCErrCnt++;\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- /* Clear all warning/error states except RXOK/TXOK */\r
- LPC_C_CAN0->STAT &= STAT_RXOK|STAT_TXOK;\r
- }\r
- else\r
- {\r
- if ( (canstat & STAT_LEC) == 0 ) /* NO ERROR */\r
- {\r
- msg_no = can_int & 0x7FFF;\r
- if((msg_no >= 1 ) && (msg_no <= 16))\r
- {\r
- LPC_C_CAN0->STAT &= ~STAT_RXOK;\r
- /* Check if message number is correct by reading NEWDAT registers.\r
- By reading out the NEWDAT bits, the CPU can check for which Message\r
- Object the data portion was updated\r
- Only first 16 message object used for receive : only use ND1 */\r
- if((1<<(msg_no-1)) != LPC_C_CAN0->ND1)\r
- {\r
- /* message object does not contain new data! */\r
- ND1ErrCnt++;\r
- break;\r
- }\r
- CAN_RxInt_MessageProcess(msg_no);\r
- RX_cb(msg_no);\r
- }\r
- else\r
- {\r
- LPC_C_CAN0->STAT &= ~STAT_TXOK;\r
- CAN_TxInt_MessageProcess(msg_no);\r
- TX_cb(msg_no);\r
- }\r
- }\r
- }\r
- }\r
- return;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Initialize CAN peripheral\r
- * @param[in] BitClk CAN bit clock setting\r
- * @param[in] ClkDiv CAN bit clock setting\r
- * @param[in] Tx_cb point to call-back function when transmitted\r
- * @param[in] Rx_cb point to call-back function when received\r
- * @return None\r
- **********************************************************************/\r
-void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb)\r
-{\r
-\r
- RX_cb = Rx_cb;\r
- TX_cb = Tx_cb;\r
- if ( !(LPC_C_CAN0->CNTL & CTRL_INIT) )\r
- {\r
- /* If it's in normal operation already, stop it, reconfigure\r
- everything first, then restart. */\r
- LPC_C_CAN0->CNTL |= CTRL_INIT; /* Default state */\r
- }\r
-\r
- LPC_C_CAN0->CLKDIV = ClkDiv; /* Divider for CAN VPB3 clock */\r
- LPC_C_CAN0->CNTL |= CTRL_CCE; /* Start configuring bit timing */\r
- LPC_C_CAN0->BT = BitClk;\r
- LPC_C_CAN0->BRPE = 0x0000;\r
- LPC_C_CAN0->CNTL &= ~CTRL_CCE; /* Stop configuring bit timing */\r
-\r
- LPC_C_CAN0->CNTL &= ~CTRL_INIT; /* Initialization finished, normal operation now. */\r
- while ( LPC_C_CAN0->CNTL & CTRL_INIT );\r
-\r
- /* By default, auto TX is enabled, enable all related interrupts */\r
- LPC_C_CAN0->CNTL |= (CTRL_IE|CTRL_SIE|CTRL_EIE);\r
- return;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Send a message to the CAN port\r
- * @param[in] msg_no message object number\r
- * @param[in] msg_ptr msg buffer pointer\r
- * @return None\r
- **********************************************************************/\r
-void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr )\r
-{\r
- uint32_t tx_id, Length;\r
-\r
- if(msg_ptr == NULL) return;\r
-\r
- /* first is the ID, second is length, the next four are data */\r
- tx_id = *msg_ptr++;\r
- Length = *msg_ptr++;\r
-\r
- if(Length>CAN_DLC_MAX)Length = CAN_DLC_MAX;\r
- CAN_IF_Write(MCTRL, IF1, UMSK|TXIE|TXRQ|EOB|RMTEN|(Length & DLC_MASK));\r
- CAN_IF_Write(DA1, IF1, *msg_ptr); /* Lower two bytes of message pointer */\r
- CAN_IF_Write(DA2, IF1, (*msg_ptr++)>>16); /* Upper two bytes of message pointer */\r
- CAN_IF_Write(DB1, IF1, *msg_ptr); /* Lower two bytes of message pointer */\r
- CAN_IF_Write(DB2, IF1, (*msg_ptr)>>16); /* Upper two bytes of message pointer */\r
-\r
- /* Configure arbitration */\r
- if(!(tx_id & (0x1<<30))) /* bit 30 is 0, standard frame */\r
- {\r
- /* Mxtd: 0, Mdir: 1, Mask is 0x7FF */\r
- CAN_IF_Write(MSK2, IF1, MASK_MDIR | (ID_STD_MASK << 2));\r
- CAN_IF_Write(MSK1, IF1, 0x0000);\r
-\r
- /* MsgVal: 1, Mtd: 0, Dir: 1, ID = 0x200 */\r
- CAN_IF_Write(ARB1, IF1, 0x0000);\r
- CAN_IF_Write(ARB2, IF1, ID_MVAL| ID_DIR | (tx_id << 2));\r
- }\r
- else /* Extended frame */\r
- {\r
- /* Mxtd: 1, Mdir: 1, Mask is 0x7FF */\r
- CAN_IF_Write(MSK2, IF1, MASK_MXTD | MASK_MDIR | (ID_EXT_MASK >> 16));\r
- CAN_IF_Write(MSK1, IF1, ID_EXT_MASK & 0x0000FFFF);\r
-\r
- /* MsgVal: 1, Mtd: 1, Dir: 1, ID = 0x200000 */\r
- CAN_IF_Write(ARB1, IF1, tx_id & 0x0000FFFF);\r
- CAN_IF_Write(ARB2, IF1, ID_MVAL|ID_MTD | ID_DIR | (tx_id >> 16));\r
- }\r
-\r
- /* Write changes to message RAM */\r
- CAN_IF_writeBuf(IF1, msg_no);\r
-\r
- return;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Listen for a message on CAN bus\r
- * @param[in] msg_no message object number\r
- * @param[in] msg_ptr msg buffer pointer\r
- * @param[in] RemoteEnable Enable/disable remote frame support, should be:\r
- * - TRUE: enable\r
- * - FALSE: disable\r
- * @return None\r
- **********************************************************************/\r
-void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable)\r
-{\r
- uint32_t rx_id = *msg_ptr;\r
- uint32_t rmten = 0;\r
- if(RemoteEnable){\r
- rmten = 1<<8;\r
- }\r
- if(!(rx_id & (0x1<<30))){ /* standard frame */\r
-\r
- /* Mxtd: 0, Mdir: 0, Mask is 0x7FF */\r
- CAN_IF_Write(MSK1, IF1, 0x0000);\r
- CAN_IF_Write(MSK2, IF1, ID_STD_MASK << 2);\r
- /* MsgVal: 1, Mtd: 0, Dir: 0 */\r
- CAN_IF_Write(ARB1, IF1, 0x0000);\r
- CAN_IF_Write(MCTRL, IF1, rmten|UMSK|RXIE|EOB|CAN_DLC_MAX);\r
- CAN_IF_Write(DA1, IF1, 0x0000);\r
- CAN_IF_Write(DA2, IF1, 0x0000);\r
- CAN_IF_Write(DB1, IF1, 0x0000);\r
- CAN_IF_Write(DB2, IF1, 0x0000);\r
- CAN_IF_Write(ARB2, IF1, ID_MVAL | ((rx_id) << 2));\r
- /* Transfer data to message RAM */\r
- CAN_IF_writeBuf(IF1, msg_no);\r
- }\r
-\r
- else{\r
- rx_id &= (0x1<<30)-1 ; /* Mask ID bit */\r
- /* Mxtd: 1, Mdir: 0, Mask is 0x1FFFFFFF */\r
- CAN_IF_Write(MSK1, IF1, ID_EXT_MASK & 0xFFFF);\r
- CAN_IF_Write(MSK2, IF1, MASK_MXTD | (ID_EXT_MASK >> 16));\r
- /* MsgVal: 1, Mtd: 1, Dir: 0 */\r
- CAN_IF_Write(ARB1, IF1, (rx_id) & 0xFFFF);\r
- CAN_IF_Write(MCTRL, IF1, rmten|UMSK|RXIE|EOB|CAN_DLC_MAX);\r
- CAN_IF_Write(DA1, IF1, 0x0000);\r
- CAN_IF_Write(DA2, IF1, 0x0000);\r
- CAN_IF_Write(DB1, IF1, 0x0000);\r
- CAN_IF_Write(DB2, IF1, 0x0000);\r
- CAN_IF_Write(ARB2, IF1, ID_MVAL | ID_MTD | ((rx_id) >> 16));\r
- /* Transfer data to message RAM */\r
- CAN_IF_writeBuf(IF1, msg_no);\r
- }\r
- return;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Read a message from Message RAM to buffer\r
- * @param[in] msg_no message object number\r
- * @param[in] buff msg buffer pointer\r
- * @return None\r
- **********************************************************************/\r
-void CAN_ReadMsg(uint32_t msg_no, message_object* buff){\r
- int i;\r
- buff->id = recv_buff.id;\r
- buff->dlc = recv_buff.dlc;\r
- if(recv_buff.dlc>CAN_DLC_MAX) recv_buff.dlc = CAN_DLC_MAX;\r
- for(i=0;i<recv_buff.dlc;i++)\r
- buff->data[i] = recv_buff.data[i];\r
-}\r
-\r
-#endif /* _C_CAN*/\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_cgu.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_cgu.c\r
-* @brief Contains all functions support for Clock Generation and Control\r
-* firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup CGU\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc_types.h"\r
-#include "lpc18xx_scu.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/** This define used to fix mistake when run with IAR compiler */\r
-#ifdef __ICCARM__\r
-#define CGU_BRANCH_STATUS_ENABLE_MASK 0x80000001\r
-#else\r
-#define CGU_BRANCH_STATUS_ENABLE_MASK 0x01\r
-#endif\r
-\r
-/*TODO List:\r
- * SET PLL0\r
- * UPDATE Clock from PLL0\r
- * SetDIV uncheck value\r
- * GetBaseStatus BASE_SAFE\r
- * */\r
-/* Local definition */\r
-#define CGU_ADDRESS32(x,y) (*(uint32_t*)((uint32_t)x+y))\r
-\r
-/* Local Variable */\r
-const int16_t CGU_Entity_ControlReg_Offset[CGU_ENTITY_NUM] = {\r
- -1, //CGU_CLKSRC_32KHZ_OSC,\r
- -1, //CGU_CLKSRC_IRC,\r
- -1, //CGU_CLKSRC_ENET_RX_CLK,\r
- -1, //CGU_CLKSRC_ENET_TX_CLK,\r
- -1, //CGU_CLKSRC_GP_CLKIN,\r
- -1, //CGU_CLKSRC_TCK,\r
- 0x18, //CGU_CLKSRC_XTAL_OSC,\r
- 0x20, //CGU_CLKSRC_PLL0,\r
- 0x30, //CGU_CLKSRC_PLL0_AUDIO **REV A**\r
- 0x44, //CGU_CLKSRC_PLL1,\r
- -1, //CGU_CLKSRC_RESERVE,\r
- -1, //CGU_CLKSRC_RESERVE,\r
- 0x48, //CGU_CLKSRC_IDIVA,,\r
- 0x4C, //CGU_CLKSRC_IDIVB,\r
- 0x50, //CGU_CLKSRC_IDIVC,\r
- 0x54, //CGU_CLKSRC_IDIVD,\r
- 0x58, //CGU_CLKSRC_IDIVE,\r
-\r
- 0x5C, //CGU_BASE_SAFE,\r
- 0x60, //CGU_BASE_USB0,\r
- -1, //CGU_BASE_RESERVE,\r
- 0x68, //CGU_BASE_USB1,\r
- 0x6C, //CGU_BASE_M3,\r
- 0x70, //CGU_BASE_SPIFI,\r
- -1, //CGU_BASE_RESERVE,\r
- 0x78, //CGU_BASE_PHY_RX,\r
- 0x7C, //CGU_BASE_PHY_TX,\r
- 0x80, //CGU_BASE_APB1,\r
- 0x84, //CGU_BASE_APB3,\r
- 0x88, //CGU_BASE_LCD,\r
- 0X8C, //CGU_BASE_ENET_CSR, **REV A**\r
- 0x90, //CGU_BASE_SDIO,\r
- 0x94, //CGU_BASE_SSP0,\r
- 0x98, //CGU_BASE_SSP1,\r
- 0x9C, //CGU_BASE_UART0,\r
- 0xA0, //CGU_BASE_UART1,\r
- 0xA4, //CGU_BASE_UART2,\r
- 0xA8, //CGU_BASE_UART3,\r
- 0xAC, //CGU_BASE_CLKOUT\r
- -1,\r
- -1,\r
- -1,\r
- -1,\r
- 0xC0, //CGU_BASE_APLL\r
- 0xC4, //CGU_BASE_OUT0\r
- 0xC8 //CGU_BASE_OUT1\r
-};\r
-\r
-const uint8_t CGU_ConnectAlloc_Tbl[CGU_CLKSRC_NUM][CGU_ENTITY_NUM] = {\r
-// 3 I E E G T X P P P x x D D D D D S U x U M S x P P A A L E S S S U U U U C x x x x A O O\r
-// 2 R R T P C T L L L I I I I I A S S 3 P H H P P C N D S S R R R R O P U U\r
-// C X X I K A 0 A 1 A B C D E F B B F RxTx1 3 D T I 0 1 0 1 2 3 L T T\r
- {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_32KHZ_OSC = 0,*/\r
- {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,1,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IRC,*/\r
- {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_RX_CLK,*/\r
- {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_ENET_TX_CLK,*/\r
- {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_GP_CLKIN,*/\r
- {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0},/*CGU_CLKSRC_TCK,*/\r
- {0,0,0,0,0,0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_XTAL_OSC,*/\r
- {0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,1},/*CGU_CLKSRC_PLL0,*/\r
- {0,0,0,0,0,0,0,0,0,1,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL0_AUDIO,*/\r
- {0,0,0,0,0,0,0,1,1,0,0,0,1,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_PLL1,*/\r
- {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},\r
- {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},\r
- {0,0,0,0,0,0,0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,*/\r
- {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVB,*/\r
- {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVC,*/\r
- {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1},/*CGU_CLKSRC_IDIVD,*/\r
- {0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,1,1,1}/*CGU_CLKSRC_IDIVE,*/\r
-};\r
-\r
-const CGU_PERIPHERAL_S CGU_PERIPHERAL_Info[CGU_PERIPHERAL_NUM] = {\r
- /* Register Clock | Peripheral Clock\r
- | BASE | BRANCH | BASE | BRANCH */\r
- {CGU_BASE_APB3, 0x1118, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC0,\r
- {CGU_BASE_APB3, 0x1120, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_ADC1,\r
- {CGU_BASE_M3, 0x1460, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_AES,\r
- //// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,\r
- {CGU_BASE_APB1, 0x1200, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB1_BUS,\r
- {CGU_BASE_APB3, 0x1100, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_APB3_BUS,\r
- {CGU_BASE_APB3, 0x1128, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CAN0,\r
- {CGU_BASE_M3, 0x1538, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_CREG,\r
- {CGU_BASE_APB3, 0x1110, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DAC,\r
- {CGU_BASE_M3, 0x1440, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_DMA,\r
- {CGU_BASE_M3, 0x1430, CGU_BASE_M3, 0x1478, 0},//CGU_PERIPHERAL_EMC,\r
- {CGU_BASE_M3, 0x1420, CGU_BASE_PHY_RX, 0x0000, CGU_PERIPHERAL_ETHERNET_TX},//CGU_PERIPHERAL_ETHERNET,\r
- {CGU_ENTITY_NONE,0x0000, CGU_BASE_PHY_TX, 0x0000, 0},//CGU_PERIPHERAL_ETHERNET_TX\r
- {CGU_BASE_M3, 0x1410, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_GPIO,\r
- {CGU_BASE_APB1, 0x1210, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C0,\r
- {CGU_BASE_APB3, 0x1108, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2C1,\r
- {CGU_BASE_APB1, 0x1218, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_I2S,\r
- {CGU_BASE_M3, 0x1418, CGU_BASE_LCD, 0x0000, 0},//CGU_PERIPHERAL_LCD,\r
- {CGU_BASE_M3, 0x1448, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3CORE,\r
- {CGU_BASE_M3, 0x1400, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_M3_BUS,\r
- {CGU_BASE_APB1, 0x1208, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_MOTOCON,\r
- {CGU_BASE_M3, 0x1630, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_QEI,\r
- {CGU_BASE_M3, 0x1600, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_RITIMER,\r
- {CGU_BASE_M3, 0x1468, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCT,\r
- {CGU_BASE_M3, 0x1530, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_SCU,\r
- {CGU_BASE_M3, 0x1438, CGU_BASE_SDIO, 0x2800, 0},//CGU_PERIPHERAL_SDIO,\r
- {CGU_BASE_M3, 0x1408, CGU_BASE_SPIFI, 0x1300, 0},//CGU_PERIPHERAL_SPIFI,\r
- {CGU_BASE_M3, 0x1518, CGU_BASE_SSP0, 0x2700, 0},//CGU_PERIPHERAL_SSP0,\r
- {CGU_BASE_M3, 0x1628, CGU_BASE_SSP1, 0x2600, 0},//CGU_PERIPHERAL_SSP1,\r
- {CGU_BASE_M3, 0x1520, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER0,\r
- {CGU_BASE_M3, 0x1528, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER1,\r
- {CGU_BASE_M3, 0x1618, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER2,\r
- {CGU_BASE_M3, 0x1620, CGU_ENTITY_NONE, 0x0000, 0},//CGU_PERIPHERAL_TIMER3,\r
- {CGU_BASE_M3, 0x1508, CGU_BASE_UART0, 0x2500, 0},//CGU_PERIPHERAL_UART0,\r
- {CGU_BASE_M3, 0x1510, CGU_BASE_UART1, 0x2400, 0},//CGU_PERIPHERAL_UART1,\r
- {CGU_BASE_M3, 0x1608, CGU_BASE_UART2, 0x2300, 0},//CGU_PERIPHERAL_UART2,\r
- {CGU_BASE_M3, 0x1610, CGU_BASE_UART3, 0x2200, 0},//CGU_PERIPHERAL_UART3,\r
- {CGU_BASE_M3, 0x1428, CGU_BASE_USB0, 0x1800, 0},//CGU_PERIPHERAL_USB0,\r
- {CGU_BASE_M3, 0x1470, CGU_BASE_USB1, 0x1900, 0},//CGU_PERIPHERAL_USB1,\r
- {CGU_BASE_M3, 0x1500, CGU_BASE_SAFE, 0x0000, 0},//CGU_PERIPHERAL_WWDT,\r
-};\r
-\r
-uint32_t CGU_ClockSourceFrequency[CGU_CLKSRC_NUM] = {0,12000000,0,0,0,0, 0, 480000000,0,0,0,0,0,0,0,0,0};\r
-\r
-#define CGU_CGU_ADDR ((uint32_t)LPC_CGU)\r
-#define CGU_REG_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].RegBaseEntity]))\r
-#define CGU_REG_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset))\r
-#define CGU_REG_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4))\r
-\r
-#define CGU_PER_BASE_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_Entity_ControlReg_Offset[CGU_PERIPHERAL_Info[x].PerBaseEntity]))\r
-#define CGU_PER_BRANCH_CTRL(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset))\r
-#define CGU_PER_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4))\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Initialize default clock for LPC1800 Eval board\r
- * @param[in] None\r
- * @return Initialize status, could be:\r
- * - CGU_ERROR_SUCCESS: successful\r
- * - Other: error\r
- **********************************************************************/\r
-uint32_t CGU_Init(void){\r
- CGU_SetXTALOSC(12000000);\r
- CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);\r
- CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);\r
- // Disable PLL1 CPU hang???\r
- //CGU_EnableEntity(CGU_CLKSRC_PLL1, DISABLE);\r
- CGU_SetPLL1(10);\r
- CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);\r
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);\r
- CGU_UpdateClock();\r
- return 0;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Configure power for individual peripheral\r
- * @param[in] PPType peripheral type, should be:\r
- * - CGU_PERIPHERAL_ADC0 :ADC0\r
- * - CGU_PERIPHERAL_ADC1 :ADC1\r
- * - CGU_PERIPHERAL_AES :AES\r
- * - CGU_PERIPHERAL_APB1_BUS :APB1 bus\r
- * - CGU_PERIPHERAL_APB3_BUS :APB3 bus\r
- * - CGU_PERIPHERAL_CAN :CAN\r
- * - CGU_PERIPHERAL_CREG :CREG\r
- * - CGU_PERIPHERAL_DAC :DAC\r
- * - CGU_PERIPHERAL_DMA :DMA\r
- * - CGU_PERIPHERAL_EMC :EMC\r
- * - CGU_PERIPHERAL_ETHERNET :ETHERNET\r
- * - CGU_PERIPHERAL_GPIO :GPIO\r
- * - CGU_PERIPHERAL_I2C0 :I2C0\r
- * - CGU_PERIPHERAL_I2C1 :I2C1\r
- * - CGU_PERIPHERAL_I2S :I2S\r
- * - CGU_PERIPHERAL_LCD :LCD\r
- * - CGU_PERIPHERAL_M3CORE :M3 core\r
- * - CGU_PERIPHERAL_M3_BUS :M3 bus\r
- * - CGU_PERIPHERAL_MOTOCON :Motor control\r
- * - CGU_PERIPHERAL_QEI :QEI\r
- * - CGU_PERIPHERAL_RITIMER :RIT timer\r
- * - CGU_PERIPHERAL_SCT :SCT\r
- * - CGU_PERIPHERAL_SCU :SCU\r
- * - CGU_PERIPHERAL_SDIO :SDIO\r
- * - CGU_PERIPHERAL_SPIFI :SPIFI\r
- * - CGU_PERIPHERAL_SSP0 :SSP0\r
- * - CGU_PERIPHERAL_SSP1 :SSP1\r
- * - CGU_PERIPHERAL_TIMER0 :TIMER0\r
- * - CGU_PERIPHERAL_TIMER1 :TIMER1\r
- * - CGU_PERIPHERAL_TIMER2 :TIMER2\r
- * - CGU_PERIPHERAL_TIMER3 :TIMER3\r
- * - CGU_PERIPHERAL_UART0 :UART0\r
- * - CGU_PERIPHERAL_UART1 :UART1\r
- * - CGU_PERIPHERAL_UART2 :UART2\r
- * - CGU_PERIPHERAL_UART3 :UART3\r
- * - CGU_PERIPHERAL_USB0 :USB0\r
- * - CGU_PERIPHERAL_USB1 :USB1\r
- * - CGU_PERIPHERAL_WWDT :WWDT\r
- * @param[in] en status, should be:\r
- * - ENABLE: Enable power\r
- * - DISABLE: Disable power\r
- * @return Configure status, could be:\r
- * - CGU_ERROR_SUCCESS: successful\r
- * - Other: error\r
- **********************************************************************/\r
-uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en){\r
- if(PPType >= CGU_PERIPHERAL_WWDT && PPType <= CGU_PERIPHERAL_ADC0)\r
- return CGU_ERROR_INVALID_PARAM;\r
- if(en == DISABLE){/* Going to disable clock */\r
- /*Get Reg branch status */\r
- if(CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0 &&\r
- CGU_REG_BRANCH_STATUS(PPType) & 1){\r
- CGU_REG_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */\r
- while(CGU_REG_BRANCH_STATUS(PPType) & 1);\r
- }\r
- /* GetBase Status*/\r
- if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) &&\r
- CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity) == 0){\r
- /* Disable Base */\r
- CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity,0);\r
- }\r
-\r
- /* Same for Peripheral */\r
- if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && (CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){\r
- CGU_PER_BRANCH_CTRL(PPType) &= ~1; /* Disable branch clock */\r
- while(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK);\r
- }\r
- /* GetBase Status*/\r
- if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity!=CGU_ENTITY_NONE) &&\r
- CGU_GetBaseStatus((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity) == 0){\r
- /* Disable Base */\r
- CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity,0);\r
- }\r
- }else{\r
- /* enable */\r
- /* GetBase Status*/\r
- if((CGU_PERIPHERAL_Info[PPType].RegBaseEntity!=CGU_ENTITY_NONE) && CGU_REG_BASE_CTRL(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK){\r
- /* Enable Base */\r
- CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].RegBaseEntity, 1);\r
- }\r
- /*Get Reg branch status */\r
- if((CGU_PERIPHERAL_Info[PPType].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){\r
- CGU_REG_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */\r
- while(!(CGU_REG_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));\r
- }\r
-\r
- /* Same for Peripheral */\r
- /* GetBase Status*/\r
- if((CGU_PERIPHERAL_Info[PPType].PerBaseEntity != CGU_ENTITY_NONE) &&\r
- (CGU_PER_BASE_CTRL(PPType) & 1)){\r
- /* Enable Base */\r
- CGU_EnableEntity((CGU_ENTITY_T)CGU_PERIPHERAL_Info[PPType].PerBaseEntity, 1);\r
- }\r
- /*Get Reg branch status */\r
- if((CGU_PERIPHERAL_Info[PPType].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK)){\r
- CGU_PER_BRANCH_CTRL(PPType) |= 1; /* Enable branch clock */\r
- while(!(CGU_PER_BRANCH_STATUS(PPType) & CGU_BRANCH_STATUS_ENABLE_MASK));\r
- }\r
-\r
- }\r
-\r
- if(CGU_PERIPHERAL_Info[PPType].next){\r
- return CGU_ConfigPWR((CGU_PERIPHERAL_T)CGU_PERIPHERAL_Info[PPType].next, en);\r
- }\r
- return CGU_ERROR_SUCCESS;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get peripheral clock frequency\r
- * @param[in] Clock Peripheral type, should be:\r
- * - CGU_PERIPHERAL_ADC0 :ADC0\r
- * - CGU_PERIPHERAL_ADC1 :ADC1\r
- * - CGU_PERIPHERAL_AES :AES\r
- * - CGU_PERIPHERAL_APB1_BUS :APB1 bus\r
- * - CGU_PERIPHERAL_APB3_BUS :APB3 bus\r
- * - CGU_PERIPHERAL_CAN :CAN\r
- * - CGU_PERIPHERAL_CREG :CREG\r
- * - CGU_PERIPHERAL_DAC :DAC\r
- * - CGU_PERIPHERAL_DMA :DMA\r
- * - CGU_PERIPHERAL_EMC :EMC\r
- * - CGU_PERIPHERAL_ETHERNET :ETHERNET\r
- * - CGU_PERIPHERAL_GPIO :GPIO\r
- * - CGU_PERIPHERAL_I2C0 :I2C0\r
- * - CGU_PERIPHERAL_I2C1 :I2C1\r
- * - CGU_PERIPHERAL_I2S :I2S\r
- * - CGU_PERIPHERAL_LCD :LCD\r
- * - CGU_PERIPHERAL_M3CORE :M3 core\r
- * - CGU_PERIPHERAL_M3_BUS :M3 bus\r
- * - CGU_PERIPHERAL_MOTOCON :Motor control\r
- * - CGU_PERIPHERAL_QEI :QEI\r
- * - CGU_PERIPHERAL_RITIMER :RIT timer\r
- * - CGU_PERIPHERAL_SCT :SCT\r
- * - CGU_PERIPHERAL_SCU :SCU\r
- * - CGU_PERIPHERAL_SDIO :SDIO\r
- * - CGU_PERIPHERAL_SPIFI :SPIFI\r
- * - CGU_PERIPHERAL_SSP0 :SSP0\r
- * - CGU_PERIPHERAL_SSP1 :SSP1\r
- * - CGU_PERIPHERAL_TIMER0 :TIMER0\r
- * - CGU_PERIPHERAL_TIMER1 :TIMER1\r
- * - CGU_PERIPHERAL_TIMER2 :TIMER2\r
- * - CGU_PERIPHERAL_TIMER3 :TIMER3\r
- * - CGU_PERIPHERAL_UART0 :UART0\r
- * - CGU_PERIPHERAL_UART1 :UART1\r
- * - CGU_PERIPHERAL_UART2 :UART2\r
- * - CGU_PERIPHERAL_UART3 :UART3\r
- * - CGU_PERIPHERAL_USB0 :USB0\r
- * - CGU_PERIPHERAL_USB1 :USB1\r
- * - CGU_PERIPHERAL_WWDT :WWDT\r
- * @return Return frequently value\r
- **********************************************************************/\r
-uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock){\r
- uint32_t ClkSrc;\r
- if(Clock >= CGU_PERIPHERAL_WWDT && Clock <= CGU_PERIPHERAL_ADC0)\r
- return CGU_ERROR_INVALID_PARAM;\r
-\r
- if(CGU_PERIPHERAL_Info[Clock].PerBaseEntity != CGU_ENTITY_NONE){\r
- /* Get Base Clock Source */\r
- ClkSrc = (CGU_PER_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;\r
- /* GetBase Status*/\r
- if(CGU_PER_BASE_CTRL(Clock) & 1)\r
- return 0;\r
- /* check Branch if it is enabled */\r
- if((CGU_PERIPHERAL_Info[Clock].PerBranchOffset!= 0) && !(CGU_PER_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;\r
- }else{\r
- if(CGU_REG_BASE_CTRL(Clock) & 1) return 0;\r
- ClkSrc = (CGU_REG_BASE_CTRL(Clock) & CGU_CTRL_SRC_MASK) >> 24;\r
- /* check Branch if it is enabled */\r
- if((CGU_PERIPHERAL_Info[Clock].RegBranchOffset!= 0) && !(CGU_REG_BRANCH_STATUS(Clock) & CGU_BRANCH_STATUS_ENABLE_MASK)) return 0;\r
- }\r
- return CGU_ClockSourceFrequency[ClkSrc];\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Update clock\r
- * @param[in] None\r
- * @return None\r
- **********************************************************************/\r
-void CGU_UpdateClock(void){\r
- uint32_t ClkSrc;\r
- uint32_t div;\r
- uint32_t divisor;\r
- int32_t RegOffset;\r
- /* 32OSC */\r
- if(ISBITSET(LPC_CREG->CREG0,1) && ISBITCLR(LPC_CREG->CREG0,3))\r
- CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 32768;\r
- else\r
- CGU_ClockSourceFrequency[CGU_CLKSRC_32KHZ_OSC] = 0;\r
- /*PLL0*/\r
- /* PLL1 */\r
- if(ISBITCLR(LPC_CGU->PLL1_CTRL,1) /* Enabled */\r
- && (LPC_CGU->PLL1_STAT&1)){ /* Locked? */\r
- ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;\r
- CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = CGU_ClockSourceFrequency[ClkSrc] *\r
- (((LPC_CGU->PLL1_CTRL>>16)&0xFF)+1);\r
- }else\r
- CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = 0;\r
-\r
- /* DIV */\r
- for(div = CGU_CLKSRC_IDIVA; div <= CGU_CLKSRC_IDIVE; div++){\r
- RegOffset = CGU_Entity_ControlReg_Offset[div];\r
- if(ISBITCLR(CGU_ADDRESS32(LPC_CGU,RegOffset),1)){\r
- ClkSrc = (CGU_ADDRESS32(LPC_CGU,RegOffset) & CGU_CTRL_SRC_MASK) >> 24;\r
- divisor = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>2) & 0xFF;\r
- divisor ++;\r
- CGU_ClockSourceFrequency[div] = CGU_ClockSourceFrequency[ClkSrc] / divisor;\r
- }else\r
- CGU_ClockSourceFrequency[div] = 0;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set XTAL oscillator value\r
- * @param[in] ClockFrequency XTAL Frequency value\r
- * @return Setting status, could be:\r
- * - CGU_ERROR_SUCCESS: successful\r
- * - CGU_ERROR_FREQ_OUTOF_RANGE: XTAL value set is out of range\r
- **********************************************************************/\r
-uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency){\r
- if(ClockFrequency < 15000000){\r
- LPC_CGU->XTAL_OSC_CTRL &= ~(1<<2);\r
- }else if(ClockFrequency < 25000000){\r
- LPC_CGU->XTAL_OSC_CTRL |= (1<<2);\r
- }else\r
- return CGU_ERROR_FREQ_OUTOF_RANGE;\r
-\r
- CGU_ClockSourceFrequency[CGU_CLKSRC_XTAL_OSC] = ClockFrequency;\r
- return CGU_ERROR_SUCCESS;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set clock divider\r
- * @param[in] SelectDivider Clock source, should be:\r
- * - CGU_CLKSRC_IDIVA :Integer divider register A\r
- * - CGU_CLKSRC_IDIVB :Integer divider register B\r
- * - CGU_CLKSRC_IDIVC :Integer divider register C\r
- * - CGU_CLKSRC_IDIVD :Integer divider register D\r
- * - CGU_CLKSRC_IDIVE :Integer divider register E\r
- * @param[in] divisor Divisor value, should be: 0..255\r
- * @return Setting status, could be:\r
- * - CGU_ERROR_SUCCESS: successful\r
- * - CGU_ERROR_INVALID_ENTITY: Invalid entity\r
- **********************************************************************/\r
-/* divisor number must >=1*/\r
-uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor){\r
- int32_t RegOffset;\r
- uint32_t tempReg;\r
- if(SelectDivider>=CGU_CLKSRC_IDIVA && SelectDivider<=CGU_CLKSRC_IDIVE){\r
- RegOffset = CGU_Entity_ControlReg_Offset[SelectDivider];\r
- if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;\r
- tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);\r
- tempReg &= ~(0xFF<<2);\r
- tempReg |= ((divisor-1)&0xFF)<<2;\r
- CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;\r
- return CGU_ERROR_SUCCESS;\r
- }\r
- return CGU_ERROR_INVALID_ENTITY;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable clock entity\r
- * @param[in] ClockEntity Clock entity, should be:\r
- * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator\r
- * - CGU_CLKSRC_IRC :IRC clock\r
- * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock\r
- * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock\r
- * - CGU_CLKSRC_GP_CLKIN :General purpose input clock\r
- * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator\r
- * - CGU_CLKSRC_PLL0 :PLL0 clock\r
- * - CGU_CLKSRC_PLL1 :PLL1 clock\r
- * - CGU_CLKSRC_IDIVA :Integer divider register A\r
- * - CGU_CLKSRC_IDIVB :Integer divider register B\r
- * - CGU_CLKSRC_IDIVC :Integer divider register C\r
- * - CGU_CLKSRC_IDIVD :Integer divider register D\r
- * - CGU_CLKSRC_IDIVE :Integer divider register E\r
- * - CGU_BASE_SAFE :Base safe clock (always on)for WDT\r
- * - CGU_BASE_USB0 :Base clock for USB0\r
- * - CGU_BASE_USB1 :Base clock for USB1\r
- * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
- * and APB peripheral blocks #0 and #2\r
- * - CGU_BASE_SPIFI :Base clock for SPIFI\r
- * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx\r
- * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx\r
- * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
- * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
- * - CGU_BASE_LCD :Base clock for LCD\r
- * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
- * - CGU_BASE_SSP0 :Base clock for SSP0\r
- * - CGU_BASE_SSP1 :Base clock for SSP1\r
- * - CGU_BASE_UART0 :Base clock for UART0\r
- * - CGU_BASE_UART1 :Base clock for UART1\r
- * - CGU_BASE_UART2 :Base clock for UART2\r
- * - CGU_BASE_UART3 :Base clock for UART3\r
- * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin\r
- * @param[in] en status, should be:\r
- * - ENABLE: Enable power\r
- * - DISABLE: Disable power\r
- * @return Setting status, could be:\r
- * - CGU_ERROR_SUCCESS: successful\r
- * - CGU_ERROR_INVALID_ENTITY: Invalid entity\r
- **********************************************************************/\r
-uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en){\r
- int32_t RegOffset;\r
- int32_t i;\r
- if(ClockEntity == CGU_CLKSRC_32KHZ_OSC){\r
- if(en){\r
- LPC_CREG->CREG0 &= ~((1<<3)|(1<<2));\r
- LPC_CREG->CREG0 |= (1<<1)|(1<<0);\r
- }else{\r
- LPC_CREG->CREG0 &= ~((1<<1)|(1<<0));\r
- LPC_CREG->CREG0 |= (1<<3);\r
- }\r
- for(i = 0;i<1000000;i++);\r
-\r
- }else if(ClockEntity == CGU_CLKSRC_ENET_RX_CLK){\r
- scu_pinmux(0xC ,0 , MD_PLN, FUNC3);\r
-\r
- }else if(ClockEntity == CGU_CLKSRC_ENET_TX_CLK){\r
- scu_pinmux(0x1 ,19 , MD_PLN, FUNC0);\r
-\r
- }else if(ClockEntity == CGU_CLKSRC_GP_CLKIN){\r
-\r
- }else if(ClockEntity == CGU_CLKSRC_TCK){\r
-\r
- }else if(ClockEntity == CGU_CLKSRC_XTAL_OSC){\r
- if(!en)\r
- LPC_CGU->XTAL_OSC_CTRL |= CGU_CTRL_EN_MASK;\r
- else\r
- LPC_CGU->XTAL_OSC_CTRL &= ~CGU_CTRL_EN_MASK;\r
- /*Delay for stable clock*/\r
- for(i = 0;i<1000000;i++);\r
-\r
- }else{\r
- RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];\r
- if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;\r
- if(!en){\r
- CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) |= CGU_CTRL_EN_MASK;\r
- }else{\r
- CGU_ADDRESS32(CGU_CGU_ADDR,RegOffset) &= ~CGU_CTRL_EN_MASK;\r
- /*if PLL is selected check if it is locked */\r
- if(ClockEntity == CGU_CLKSRC_PLL0){\r
- while((LPC_CGU->PLL0USB_STAT&1) == 0x0);\r
- }\r
- if(ClockEntity == CGU_CLKSRC_PLL1){\r
- while((LPC_CGU->PLL1_STAT&1) == 0x0);\r
- /*post check lock status */\r
- if(!(LPC_CGU->PLL1_STAT&1))\r
- while(1);\r
- }\r
- }\r
- }\r
- return CGU_ERROR_SUCCESS;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Connect entity clock source\r
- * @param[in] ClockSource Clock source, should be:\r
- * - CGU_CLKSRC_32KHZ_OSC :32Khz oscillator\r
- * - CGU_CLKSRC_IRC :IRC clock\r
- * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock\r
- * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock\r
- * - CGU_CLKSRC_GP_CLKIN :General purpose input clock\r
- * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator\r
- * - CGU_CLKSRC_PLL0 :PLL0 clock\r
- * - CGU_CLKSRC_PLL1 :PLL1 clock\r
- * - CGU_CLKSRC_IDIVA :Integer divider register A\r
- * - CGU_CLKSRC_IDIVB :Integer divider register B\r
- * - CGU_CLKSRC_IDIVC :Integer divider register C\r
- * - CGU_CLKSRC_IDIVD :Integer divider register D\r
- * - CGU_CLKSRC_IDIVE :Integer divider register E\r
- * @param[in] ClockEntity Clock entity, should be:\r
- * - CGU_CLKSRC_PLL0 :PLL0 clock\r
- * - CGU_CLKSRC_PLL1 :PLL1 clock\r
- * - CGU_CLKSRC_IDIVA :Integer divider register A\r
- * - CGU_CLKSRC_IDIVB :Integer divider register B\r
- * - CGU_CLKSRC_IDIVC :Integer divider register C\r
- * - CGU_CLKSRC_IDIVD :Integer divider register D\r
- * - CGU_CLKSRC_IDIVE :Integer divider register E\r
- * - CGU_BASE_SAFE :Base safe clock (always on)for WDT\r
- * - CGU_BASE_USB0 :Base clock for USB0\r
- * - CGU_BASE_USB1 :Base clock for USB1\r
- * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
- * and APB peripheral blocks #0 and #2\r
- * - CGU_BASE_SPIFI :Base clock for SPIFI\r
- * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx\r
- * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx\r
- * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
- * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
- * - CGU_BASE_LCD :Base clock for LCD\r
- * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
- * - CGU_BASE_SSP0 :Base clock for SSP0\r
- * - CGU_BASE_SSP1 :Base clock for SSP1\r
- * - CGU_BASE_UART0 :Base clock for UART0\r
- * - CGU_BASE_UART1 :Base clock for UART1\r
- * - CGU_BASE_UART2 :Base clock for UART2\r
- * - CGU_BASE_UART3 :Base clock for UART3\r
- * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin\r
- * @return Setting status, could be:\r
- * - CGU_ERROR_SUCCESS: successful\r
- * - CGU_ERROR_CONNECT_TOGETHER: Error when 2 clock source connect together\r
- * - CGU_ERROR_INVALID_CLOCK_SOURCE: Invalid clock source error\r
- * - CGU_ERROR_INVALID_ENTITY: Invalid entity error\r
- **********************************************************************/\r
-/* Connect one entity into clock source */\r
-uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity){\r
- int32_t RegOffset;\r
- uint32_t tempReg;\r
-\r
- if(ClockSource > CGU_CLKSRC_IDIVE)\r
- return CGU_ERROR_INVALID_CLOCK_SOURCE;\r
-\r
- if(ClockEntity >= CGU_CLKSRC_PLL0 && ClockEntity <= CGU_BASE_CLKOUT){\r
- if(CGU_ConnectAlloc_Tbl[ClockSource][ClockEntity]){\r
- RegOffset = CGU_Entity_ControlReg_Offset[ClockSource];\r
- if(RegOffset != -1){\r
- if(ClockEntity<=CGU_CLKSRC_IDIVE &&\r
- ClockEntity>=CGU_CLKSRC_PLL0)\r
- {\r
- //RegOffset = (CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)&0xF;\r
- if(((CGU_ADDRESS32(LPC_CGU,RegOffset)>>24)& 0xF) == ClockEntity)\r
- return CGU_ERROR_CONNECT_TOGETHER;\r
- }\r
- }\r
- RegOffset = CGU_Entity_ControlReg_Offset[ClockEntity];\r
- if(RegOffset == -1) return CGU_ERROR_INVALID_ENTITY;\r
- tempReg = CGU_ADDRESS32(LPC_CGU,RegOffset);\r
- tempReg &= ~CGU_CTRL_SRC_MASK;\r
- tempReg |= ClockSource<<24 | CGU_CTRL_AUTOBLOCK_MASK;\r
- CGU_ADDRESS32(LPC_CGU,RegOffset) = tempReg;\r
- return CGU_ERROR_SUCCESS;\r
- }else\r
- return CGU_ERROR_INVALID_CLOCK_SOURCE;\r
- }else\r
- return CGU_ERROR_INVALID_ENTITY;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get current USB PLL clock from XTAL\r
- * @param[in] None\r
- * @return Returned clock value\r
- **********************************************************************/\r
-uint32_t CGU_SetPLL0(void){\r
- // Setup PLL550 to generate 480MHz from 12 MHz crystal\r
- LPC_CGU->PLL0USB_CTRL |= 1; // Power down PLL\r
- // P N\r
- LPC_CGU->PLL0USB_NP_DIV = (98<<0) | (514<<12);\r
- // SELP SELI SELR MDEC\r
- LPC_CGU->PLL0USB_MDIV = (0xB<<17)|(0x10<<22)|(0<<28)|(0x7FFA<<0);\r
- LPC_CGU->PLL0USB_CTRL =(CGU_CLKSRC_XTAL_OSC<<24) | (0x3<<2) | (1<<4);\r
- return CGU_ERROR_SUCCESS;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Setting PLL1\r
- * @param[in] mult Multiple value\r
- * @return Setting status, could be:\r
- * - CGU_ERROR_SUCCESS: successful\r
- * - CGU_ERROR_INVALID_PARAM: Invalid parameter error\r
- **********************************************************************/\r
-uint32_t CGU_SetPLL1(uint32_t mult){\r
- uint32_t msel=0, nsel=0, psel=0, pval=1;\r
- uint32_t freq;\r
- uint32_t ClkSrc = (LPC_CGU->PLL1_CTRL & CGU_CTRL_SRC_MASK)>>24;\r
- freq = CGU_ClockSourceFrequency[ClkSrc];\r
- freq *= mult;\r
- msel = mult-1;\r
-\r
- LPC_CGU->PLL1_CTRL &= ~(CGU_PLL1_FBSEL_MASK |\r
- CGU_PLL1_BYPASS_MASK |\r
- CGU_PLL1_DIRECT_MASK |\r
- (0x03<<8) | (0xFF<<16) | (0x03<<12));\r
-\r
- if(freq<156000000){\r
- //psel is encoded such that 0=1, 1=2, 2=4, 3=8\r
- while(2*(pval)*freq < 156000000) {\r
- psel++;\r
- pval*=2;\r
- }\r
-// if(2*(pval)*freq > 320000000) {\r
-// //THIS IS OUT OF RANGE!!!\r
-// //HOW DO WE ASSERT IN SAMPLE CODE?\r
-// //__breakpoint(0);\r
-// return CGU_ERROR_INVALID_PARAM;\r
-// }\r
- LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) | CGU_PLL1_FBSEL_MASK;\r
- }else if(freq<320000000){\r
- LPC_CGU->PLL1_CTRL |= (msel<<16) | (nsel<<12) | (psel<<8) |CGU_PLL1_DIRECT_MASK | CGU_PLL1_FBSEL_MASK;\r
- }else\r
- return CGU_ERROR_INVALID_PARAM;\r
-\r
- return CGU_ERROR_SUCCESS;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get current base status\r
- * @param[in] Base Base type, should be:\r
- * - CGU_BASE_USB0 :Base clock for USB0\r
- * - CGU_BASE_USB1 :Base clock for USB1\r
- * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
- * and APB peripheral blocks #0 and #2\r
- * - CGU_BASE_SPIFI :Base clock for SPIFI\r
- * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
- * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
- * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
- * - CGU_BASE_SSP0 :Base clock for SSP0\r
- * - CGU_BASE_SSP1 :Base clock for SSP1\r
- * - CGU_BASE_UART0 :Base clock for UART0\r
- * - CGU_BASE_UART1 :Base clock for UART1\r
- * - CGU_BASE_UART2 :Base clock for UART2\r
- * - CGU_BASE_UART3 :Base clock for UART3\r
- * @return Always return 0\r
- **********************************************************************/\r
-uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base){\r
- switch(Base){\r
- /*CCU1*/\r
- case CGU_BASE_APB3:\r
- return LPC_CCU1->BASE_STAT & 1;\r
-\r
- case CGU_BASE_APB1:\r
- return (LPC_CCU1->BASE_STAT>>1) & 1;\r
-\r
- case CGU_BASE_SPIFI:\r
- return (LPC_CCU1->BASE_STAT>>2) & 1;\r
-\r
- case CGU_BASE_M3:\r
- return (LPC_CCU1->BASE_STAT>>3) & 1;\r
-\r
- case CGU_BASE_USB0:\r
- return (LPC_CCU1->BASE_STAT>>7) & 1;\r
-\r
- case CGU_BASE_USB1:\r
- return (LPC_CCU1->BASE_STAT>>8) & 1;\r
-\r
- /*CCU2*/\r
- case CGU_BASE_UART3:\r
- return (LPC_CCU2->BASE_STAT>>1) & 1;\r
-\r
- case CGU_BASE_UART2:\r
- return (LPC_CCU2->BASE_STAT>>2) & 1;\r
-\r
- case CGU_BASE_UART1:\r
- return (LPC_CCU2->BASE_STAT>>3) & 1;\r
-\r
- case CGU_BASE_UART0:\r
- return (LPC_CCU2->BASE_STAT>>4) & 1;\r
-\r
- case CGU_BASE_SSP1:\r
- return (LPC_CCU2->BASE_STAT>>5) & 1;\r
-\r
- case CGU_BASE_SSP0:\r
- return (LPC_CCU2->BASE_STAT>>6) & 1;\r
-\r
- case CGU_BASE_SDIO:\r
- return (LPC_CCU2->BASE_STAT>>7) & 1;\r
-\r
- /*BASE SAFE is used by WWDT and RGU*/\r
- case CGU_BASE_SAFE:\r
- break;\r
- default:\r
- break;\r
- }\r
- return 0;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Compare one source clock to IRC clock\r
- * @param[in] Clock Clock entity that will be compared to IRC, should be:\r
- * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator\r
- * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock\r
- * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock\r
- * - CGU_CLKSRC_GP_CLKIN :General purpose input clock\r
- * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator\r
- * - CGU_CLKSRC_PLL0 :PLL0 clock\r
- * - CGU_CLKSRC_PLL1 :PLL1 clock\r
- * - CGU_CLKSRC_IDIVA :Integer divider register A\r
- * - CGU_CLKSRC_IDIVB :Integer divider register B\r
- * - CGU_CLKSRC_IDIVC :Integer divider register C\r
- * - CGU_CLKSRC_IDIVD :Integer divider register D\r
- * - CGU_CLKSRC_IDIVE :Integer divider register E\r
- * - CGU_BASE_SAFE :Base safe clock (always on)for WDT\r
- * - CGU_BASE_USB0 :Base clock for USB0\r
- * - CGU_BASE_USB1 :Base clock for USB1\r
- * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
- * and APB peripheral blocks #0 and #2\r
- * - CGU_BASE_SPIFI :Base clock for SPIFI\r
- * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx\r
- * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx\r
- * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
- * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
- * - CGU_BASE_LCD :Base clock for LCD\r
- * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
- * - CGU_BASE_SSP0 :Base clock for SSP0\r
- * - CGU_BASE_SSP1 :Base clock for SSP1\r
- * - CGU_BASE_UART0 :Base clock for UART0\r
- * - CGU_BASE_UART1 :Base clock for UART1\r
- * - CGU_BASE_UART2 :Base clock for UART2\r
- * - CGU_BASE_UART3 :Base clock for UART3\r
- * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin\r
- * @param[in] m Multiple value pointer\r
- * @param[in] d Divider value pointer\r
- * @return Compare status, could be:\r
- * - (-1): fail\r
- * - 0: successful\r
- * @note Formula used to compare:\r
- * FClock = F_IRC* m / d\r
- **********************************************************************/\r
-int CGU_FrequencyMonitor(CGU_ENTITY_T Clock, uint32_t *m, uint32_t *d){\r
- uint32_t n,c,temp;\r
- int i;\r
-\r
- /* Maximum allow RCOUNT number */\r
- c= 511;\r
- /* Check Source Clock Freq is larger or smaller */\r
- LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;\r
- while(LPC_CGU->FREQ_MON & (1 <<23));\r
- for(i=0;i<10000;i++);\r
- temp = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;\r
-\r
- if(temp == 0) /* too low F < 12000000/511*/\r
- return -1;\r
- if(temp > 511){ /* larger */\r
-\r
- c = 511 - (LPC_CGU->FREQ_MON&0x1FF);\r
- }else{\r
- do{\r
- c--;\r
- LPC_CGU->FREQ_MON = (Clock<<24) | 1<<23 | c;\r
- while(LPC_CGU->FREQ_MON & (1 <<23));\r
- for(i=0;i<10000;i++);\r
- n = (LPC_CGU->FREQ_MON >>9) & 0x3FFF;\r
- }while(n==temp);\r
- c++;\r
- }\r
- *m = temp;\r
- *d = c;\r
- return 0;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Compare one source clock to another source clock\r
- * @param[in] Clock Clock entity that will be compared to second source, should be:\r
- * - CGU_CLKSRC_32KHZ_OSC :32Khz crystal oscillator\r
- * - CGU_CLKSRC_ENET_RX_CLK :Ethernet receive clock\r
- * - CGU_CLKSRC_ENET_TX_CLK :Ethernet transmit clock\r
- * - CGU_CLKSRC_GP_CLKIN :General purpose input clock\r
- * - CGU_CLKSRC_XTAL_OSC :Crystal oscillator\r
- * - CGU_CLKSRC_PLL0 :PLL0 clock\r
- * - CGU_CLKSRC_PLL1 :PLL1 clock\r
- * - CGU_CLKSRC_IDIVA :Integer divider register A\r
- * - CGU_CLKSRC_IDIVB :Integer divider register B\r
- * - CGU_CLKSRC_IDIVC :Integer divider register C\r
- * - CGU_CLKSRC_IDIVD :Integer divider register D\r
- * - CGU_CLKSRC_IDIVE :Integer divider register E\r
- * - CGU_BASE_SAFE :Base safe clock (always on)for WDT\r
- * - CGU_BASE_USB0 :Base clock for USB0\r
- * - CGU_BASE_USB1 :Base clock for USB1\r
- * - CGU_BASE_M3 :System base clock for ARM Cortex-M3 core\r
- * and APB peripheral blocks #0 and #2\r
- * - CGU_BASE_SPIFI :Base clock for SPIFI\r
- * - CGU_BASE_PHY_RX :Base clock for Ethernet PHY Rx\r
- * - CGU_BASE_PHY_TX :Base clock for Ethernet PHY Tx\r
- * - CGU_BASE_APB1 :Base clock for APB peripheral block #1\r
- * - CGU_BASE_APB3 :Base clock for APB peripheral block #3\r
- * - CGU_BASE_LCD :Base clock for LCD\r
- * - CGU_BASE_SDIO :Base clock for SDIO card reader\r
- * - CGU_BASE_SSP0 :Base clock for SSP0\r
- * - CGU_BASE_SSP1 :Base clock for SSP1\r
- * - CGU_BASE_UART0 :Base clock for UART0\r
- * - CGU_BASE_UART1 :Base clock for UART1\r
- * - CGU_BASE_UART2 :Base clock for UART2\r
- * - CGU_BASE_UART3 :Base clock for UART3\r
- * - CGU_BASE_CLKOUT :Base clock for CLKOUT pin\r
- * @param[in] CompareToClock Clock source that to be compared to first source, should be different\r
- * to first source.\r
- * @param[in] m Multiple value pointer\r
- * @param[in] d Divider value pointer\r
- * @return Compare status, could be:\r
- * - (-1): fail\r
- * - 0: successful\r
- * @note Formula used to compare:\r
- * FClock = m*FCompareToClock/d\r
- **********************************************************************/\r
-uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d){\r
- uint32_t m1,m2,d1,d2;\r
- /* Check Parameter */\r
- if((Clock>CGU_CLKSRC_IDIVE) || (CompareToClock>CGU_CLKSRC_IDIVE))\r
- return CGU_ERROR_INVALID_PARAM;\r
- /* Check for Clock Enable - Not yet implement\r
- * The Comparator will hang if Clock has not been set*/\r
- CGU_FrequencyMonitor(Clock, &m1, &d1);\r
- CGU_FrequencyMonitor(CompareToClock, &m2, &d2);\r
- *m= m1*d2;\r
- *d= d1*m2;\r
- return 0;\r
-\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_dac.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_dac.c\r
-* @brief Contains all functions support for DAC firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup DAC\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_dac.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _DAC\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup DAC_Public_Functions\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief Initial ADC configuration\r
- * - Maximum current is 700 uA\r
- * - Value to AOUT is 0\r
- * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC\r
- * @return None\r
- ***********************************************************************/\r
-void DAC_Init(LPC_DAC_Type *DACx)\r
-{\r
- CHECK_PARAM(PARAM_DACx(DACx));\r
- /* Set default clock divider for DAC */\r
- //LPC_CGU->BASE_VPB3_CLK = (SRC_PL160M_0<<24) | (1<<11); // ABP3 base clock use PLL1 and auto block\r
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB3);\r
- //Set maximum current output\r
- DAC_SetBias(LPC_DAC,DAC_MAX_CURRENT_700uA);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Update value to DAC\r
- * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC\r
- * @param[in] dac_value value 10 bit to be converted to output\r
- * @return None\r
- ***********************************************************************/\r
-void DAC_UpdateValue (LPC_DAC_Type *DACx,uint32_t dac_value)\r
-{\r
- uint32_t tmp;\r
- CHECK_PARAM(PARAM_DACx(DACx));\r
- tmp = DACx->CR & DAC_BIAS_EN;\r
- tmp |= DAC_VALUE(dac_value);\r
- // Update value\r
- DACx->CR = tmp;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set Maximum current for DAC\r
- * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC\r
- * @param[in] bias Using Bias value, should be:\r
- * - 0 is 700 uA\r
- * - 1 is 350 uA\r
- * @return None\r
- ***********************************************************************/\r
-void DAC_SetBias (LPC_DAC_Type *DACx,uint32_t bias)\r
-{\r
- CHECK_PARAM(PARAM_DAC_CURRENT_OPT(bias));\r
- DACx->CR &=~DAC_BIAS_EN;\r
- if (bias == DAC_MAX_CURRENT_350uA)\r
- {\r
- DACx->CR |= DAC_BIAS_EN;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief To enable the DMA operation and control DMA timer\r
- * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC\r
- * @param[in] DAC_ConverterConfigStruct pointer to DAC_CONVERTER_CFG_Type\r
- * - DBLBUF_ENA :enable/disable DACR double buffering feature\r
- * - CNT_ENA :enable/disable timer out counter\r
- * - DMA_ENA :enable/disable DMA access\r
- * @return None\r
- ***********************************************************************/\r
-void DAC_ConfigDAConverterControl (LPC_DAC_Type *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct)\r
-{\r
- CHECK_PARAM(PARAM_DACx(DACx));\r
- DACx->CTRL &= ~DAC_DACCTRL_MASK;\r
- if (DAC_ConverterConfigStruct->DBLBUF_ENA)\r
- DACx->CTRL |= DAC_DBLBUF_ENA;\r
- if (DAC_ConverterConfigStruct->CNT_ENA)\r
- DACx->CTRL |= DAC_CNT_ENA;\r
- if (DAC_ConverterConfigStruct->DMA_ENA)\r
- DACx->CTRL |= DAC_DMA_ENA;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set reload value for interrupt/DMA counter\r
- * @param[in] DACx pointer to LPC_DAC_Type, should be: LPC_DAC\r
- * @param[in] time_out time out to reload for interrupt/DMA counter\r
- * @return None\r
- ***********************************************************************/\r
-void DAC_SetDMATimeOut(LPC_DAC_Type *DACx, uint32_t time_out)\r
-{\r
- CHECK_PARAM(PARAM_DACx(DACx));\r
- DACx->CNTVAL = DAC_CCNT_VALUE(time_out);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _DAC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************
-* $Id: lpc18xx_emc.c 8765 2011-12-08 00:51:21Z nxp21346 $ lpc18xx_emc.c 2011-12-07
-*//**
-* @file lpc18xx_emc.c
-* @brief Contains all functions support for Clock Generation and Control
-* firmware library on lpc18xx
-* @version 1.0
-* @date 07. December. 2011
-* @author NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#include "LPC18xx.h"
-#include "lpc18xx_emc.h"
-#include "lpc18xx_scu.h"
-
-#define M32(x) *((uint32_t *)x)
-#define DELAYCYCLES(ns) (ns / ((1.0 / __EMCHZ) * 1E9))
-
-void emc_WaitUS(volatile uint32_t us)
-{
- us *= (SystemCoreClock / 1000000) / 3;
- while(us--);
-}
-
-void emc_WaitMS(uint32_t ms)
-{
- emc_WaitUS(ms * 1000);
-}
-
-void MemoryPinInit(void)
-{
- /* select correct functions on the GPIOs */
-
-#if 1
- /* DATA LINES 0..31 > D0..D31 */
- /* P1_7 - EXTBUS_D0 \97 External memory data line 0 */
- scu_pinmux(0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_7: D0 (function 0) errata */
- scu_pinmux(0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_8: D1 (function 0) errata */
- scu_pinmux(0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_9: D2 (function 0) errata */
- scu_pinmux(0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_10: D3 (function 0) errata */
- scu_pinmux(0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_11: D4 (function 0) errata */
- scu_pinmux(0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_12: D5 (function 0) errata */
- scu_pinmux(0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_13: D6 (function 0) errata */
- scu_pinmux(0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_14: D7 (function 0) errata */
- scu_pinmux(0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_4: D8 (function 0) errata */
- scu_pinmux(0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_5: D9 (function 0) errata */
- scu_pinmux(0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_6: D10 (function 0) errata */
- scu_pinmux(0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_7: D11 (function 0) errata */
- scu_pinmux(0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_0: D12 (function 0) errata */
- scu_pinmux(0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_1: D13 (function 0) errata */
- scu_pinmux(0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_2: D14 (function 0) errata */
- scu_pinmux(0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_3: D15 (function 0) errata */
-#if 0
- scu_pinmux(0xD, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_2: D16 (function 0) errata */
- scu_pinmux(0xD, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_3: D17 (function 0) errata */
- scu_pinmux(0xD, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_4: D18 (function 0) errata */
- scu_pinmux(0xD, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_5: D19 (function 0) errata */
- scu_pinmux(0xD, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_6: D20 (function 0) errata */
- scu_pinmux(0xD, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_7: D21 (function 0) errata */
- scu_pinmux(0xD, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_8: D22 (function 0) errata */
- scu_pinmux(0xD, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_9: D23 (function 0) errata */
- scu_pinmux(0xE, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_5: D24 (function 0) errata */
- scu_pinmux(0xE, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_6: D25 (function 0) errata */
- scu_pinmux(0xE, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_7: D26 (function 0) errata */
- scu_pinmux(0xE, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_8: D27 (function 0) errata */
- scu_pinmux(0xE, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_9: D28 (function 0) errata */
- scu_pinmux(0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_10: D29 (function 0) errata */
- scu_pinmux(0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_11: D30 (function 0) errata */
- scu_pinmux(0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_12: D31 (function 0) errata */
-#endif
-
- /* ADDRESS LINES A0..A11 > A0..A11 */
- scu_pinmux(0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_9 - EXTBUS_A0 \97 External memory address line 0 */
- scu_pinmux(0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_10 - EXTBUS_A1 \97 External memory address line 1 */
- scu_pinmux(0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_11 - EXTBUS_A2 \97 External memory address line 2 */
- scu_pinmux(0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_12 - EXTBUS_A3 \97 External memory address line 3 */
- scu_pinmux(0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_13 - EXTBUS_A4 \97 External memory address line 4 */
- scu_pinmux(0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_0 - EXTBUS_A5 \97 External memory address line 5 */
- scu_pinmux(0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_1 - EXTBUS_A6 \97 External memory address line 6 */
- scu_pinmux(0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_2 - EXTBUS_A7 \97 External memory address line 7 */
- scu_pinmux(0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_8 - EXTBUS_A8 \97 External memory address line 8 */
- scu_pinmux(0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_7 - EXTBUS_A9 \97 External memory address line 9 */
- scu_pinmux(0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_6 - EXTBUS_A10 \97 External memory address line 10 */
- scu_pinmux(0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_2 - EXTBUS_A11 \97 External memory address line 11 */
- scu_pinmux(0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_1 - EXTBUS_A12 \97 External memory address line 12 */
- scu_pinmux(0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_0 - EXTBUS_A13 \97 External memory address line 13 */
- scu_pinmux(0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_8 - EXTBUS_A14 \97 External memory address line 14 */
- scu_pinmux(0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_7 - EXTBUS_A15 \97 External memory address line 15 */
- scu_pinmux(0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_16 - EXTBUS_A16 \97 External memory address line 16 */
- scu_pinmux(0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_15 - EXTBUS_A17 \97 External memory address line 17 */
- scu_pinmux(0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_0 - EXTBUS_A18 \97 External memory address line 18 */
- scu_pinmux(0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_1 - EXTBUS_A19 \97 External memory address line 19 */
- scu_pinmux(0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_2 - EXTBUS_A20 \97 External memory address line 20 */
- scu_pinmux(0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_3 - EXTBUS_A21 \97 External memory address line 21 */
- scu_pinmux(0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_4 - EXTBUS_A22 \97 External memory address line 22 */
- scu_pinmux(0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PA_4 - EXTBUS_A23 \97 External memory address line 23 */
-
- /* BYTE ENABLES */
- scu_pinmux(0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_4 - EXTBUS_BLS0 \97 LOW active Byte Lane select signal 0 */
- scu_pinmux(0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_6 - EXTBUS_BLS1 \97 LOW active Byte Lane select signal 1 */
- scu_pinmux(0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_13 - EXTBUS_BLS2 \97 LOW active Byte Lane select signal 2 */
- scu_pinmux(0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_10 - EXTBUS_BLS3 \97 LOW active Byte Lane select signal 3 */
-
- scu_pinmux(0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_9: EXTBUS_DYCS0 (function 0) > CS# errata */
- scu_pinmux(0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_6: WE (function 0) errata */
- scu_pinmux(0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_4: CAS (function 0) > CAS# errata */
- scu_pinmux(0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_5: RAS (function 0) > RAS# errata */
-
- LPC_SCU_CLK(0) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK0: EXTBUS_CLK0 (function 0, from datasheet) > CLK ds */
- LPC_SCU_CLK(1) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK1: EXTBUS_CLK1 (function 2, from datasheet) */
- LPC_SCU_CLK(2) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK2: EXTBUS_CLK2 (function 2, from datasheet) */
- LPC_SCU_CLK(3) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK3: EXTBUS_CLK3 (function 2, from datasheet) */
-
- scu_pinmux(0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_11: CKEOUT0 (function 0) > CKE errata */
- scu_pinmux(0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_12: DQMOUT0 (function 0) > DQM0 errata */
- scu_pinmux(0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_10: DQMOUT1 (function 0) > DQM1 errata */
- scu_pinmux(0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_0: DQMOUT2 (function 2, from datasheet) > DQM2 errata */
- scu_pinmux(0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_13: DQMOUT3 (function 3, from datasheet) > DQM3 errata */
-
- scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 ); //OE
- scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 ); //BLS0
- scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 ); //CS0
- scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 ); //WE
-
-#endif
-}
-
-void EMCFlashInit(void)
-{
- // Hitex board SST39VF3201B Flash
- // Read Cycle Time 70 nS minimum
- // Chip Enable Access Time 70 ns maximum
- // Address Access Time 70 ns max
- // Toe 35 ns max
- // CE/OE high to inactive output 16 ns
-
- /* Set up EMC Controller */
- LPC_EMC->STATICWAITRD0 = DELAYCYCLES(70)+1;
-
- LPC_EMC->STATICWAITPAG0 = DELAYCYCLES(70)+1;
-
-
- LPC_EMC->CONTROL = 0x01;
- LPC_EMC->STATICCONFIG0 = (1UL<<7) | (1UL);
- LPC_EMC->STATICWAITOEN0 = DELAYCYCLES(35)+1;
-
- /*Enable Buffer for External Flash*/
- LPC_EMC->STATICCONFIG0 |= 1<<19;
-}
-
-/* SDRAM refresh time to 16 clock num */
-#define EMC_SDRAM_REFRESH(freq,time) \
- (((uint64_t)((uint64_t)time * freq)/16000000000ull)+1)
-
-void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
-{
- // adjust the CCU delaye for EMI (default to zero)
- //LPC_SCU->EMCCLKDELAY = (CLK0_DELAY | (CLKE0_DELAY << 16));
- // Move all clock delays together
- LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY)
- | (CLK0_DELAY << 4)
- | (CLK0_DELAY << 8)
- | (CLK0_DELAY << 12));
-
- /* Initialize EMC to interface with SDRAM */
- LPC_EMC->CONTROL = 0x00000001; /* Enable the external memory controller */
- LPC_EMC->CONFIG = 0;
-
- LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14));
- LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14));
-
- LPC_EMC->DYNAMICRASCAS0 = (3 << 0) | (3 << 8); // aem
- LPC_EMC->DYNAMICRASCAS2 = (3 << 0) | (3 << 8); // aem
-
- LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
-
- LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
- LPC_EMC->DYNAMICRAS = 3;
- LPC_EMC->DYNAMICSREX = 5;
- LPC_EMC->DYNAMICAPR = 0;
- LPC_EMC->DYNAMICDAL = 4;
- LPC_EMC->DYNAMICWR = 1;
- LPC_EMC->DYNAMICRC = 5;
- LPC_EMC->DYNAMICRFC = 5;
- LPC_EMC->DYNAMICXSR = 5;
- LPC_EMC->DYNAMICRRD = 1;
- LPC_EMC->DYNAMICMRD = 1;
-
- LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
- emc_WaitUS(100);
-
- LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
-
- LPC_EMC->DYNAMICREFRESH = 2;
- emc_WaitUS(100);
-
- LPC_EMC->DYNAMICREFRESH = 50;
-
- LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
-
- if(u32DataBus == 0)
- {
- /* burst size 8 */
- *((volatile uint32_t *)(u32BaseAddr | ((3 | (3 << 4)) << (u32ColAddrBits + 1))));
- }
- else
- {
- /* burst size 4 */
- *((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2))));
- }
-
- LPC_EMC->DYNAMICCONTROL = 0; // EMC_CE_ENABLE | EMC_CS_ENABLE;
- LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
- LPC_EMC->DYNAMICCONFIG1 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
- LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
- LPC_EMC->DYNAMICCONFIG3 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
-}
-
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_evrt.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_evrt.c\r
-* @brief Contains all functions support for Event Router firmware\r
-* library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup EVRT\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_evrt.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup EVRT_Public_Functions\r
- * @{\r
- */\r
-\r
-/********************************************************************//**\r
- * @brief Initializes the EVRT peripheral.\r
- * @param[in] EVRTx EVRT peripheral selected, should be: LPC_EVRT\r
- * @return None\r
- *********************************************************************/\r
-void EVRT_Init (LPC_EVENTROUTER_Type *EVRTx)\r
-{\r
- uint8_t i=0;\r
-\r
- CHECK_PARAM(PARAM_EVRTx(EVRTx));\r
-\r
- // Clear all register to be default\r
- EVRTx->HILO = 0x0000;\r
- EVRTx->EDGE = 0x0000;\r
- EVRTx->CLR_EN = 0xFFFF;\r
- do\r
- {\r
- i++;\r
- EVRTx->CLR_STAT = 0xFFFFF;\r
- }while((EVRTx->STATUS != 0)&&(i<10));\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief De-initializes the EVRT peripheral registers to their\r
-* default reset values.\r
- * @param[in] EVRTx EVRT peripheral selected, should be: LPC_EVRT\r
- * @return None\r
- **********************************************************************/\r
-void EVRT_DeInit(LPC_EVENTROUTER_Type *EVRTx)\r
-{\r
- CHECK_PARAM(PARAM_EVRTx(EVRTx));\r
-\r
- EVRTx->CLR_EN = 0xFFFF;\r
- EVRTx->CLR_STAT = 0xFFFF;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Setting up the type of interrupt sources to EVRT\r
- * @param[in] EVRTx EVRT peripheral selected, should be: LPC_EVRT\r
- * @param[in] EVRT_Src EVRT source, should be:\r
- * - EVRT_SRC_WAKEUP0 :WAKEUP0 event\r
- * - EVRT_SRC_WAKEUP1 :WAKEUP1 event\r
- * - EVRT_SRC_WAKEUP2 :WAKEUP2 event\r
- * - EVRT_SRC_WAKEUP3 :WAKEUP3 event\r
- * - EVRT_SRC_ATIMER :Alarm timer eveny\r
- * - EVRT_SRC_RTC :RTC event\r
- * - EVRT_SRC_BOD :BOD event\r
- * - EVRT_SRC_WWDT :WWDT event\r
- * - EVRT_SRC_ETHERNET :ETHERNET event\r
- * - EVRT_SRC_USB0 :USB0 event\r
- * - EVRT_SRC_USB1 :USB1 event\r
- * - EVRT_SRC_CCAN :CCAN event\r
- * - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event\r
- * - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event\r
- * - EVRT_SRC_QEI :QEI event\r
- * - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event\r
- * - EVRT_SRC_RESET :RESET event\r
- * type Active type, should be:\r
- * - EVRT_SRC_ACTIVE_LOW_LEVEL :Active low level\r
- * - EVRT_SRC_ACTIVE_HIGH_LEVEL :Active high level\r
- * - EVRT_SRC_ACTIVE_FALLING_EDGE :Active falling edge\r
- * - EVRT_SRC_ACTIVE_RISING_EDGE :Active rising edge\r
- * @param[in] type EVRT source active type, should be:\r
- * - EVRT_SRC_ACTIVE_LOW_LEVEL :Active low level\r
- * - EVRT_SRC_ACTIVE_HIGH_LEVEL :Active high level\r
- * - EVRT_SRC_ACTIVE_FALLING_EDGE :Active falling edge\r
- * - EVRT_SRC_ACTIVE_RISING_EDGE :Active rising edge\r
- * @return None\r
- **********************************************************************/\r
-void EVRT_ConfigIntSrcActiveType(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type)\r
-{\r
- CHECK_PARAM(PARAM_EVRTx(EVRTx));\r
- CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src));\r
- CHECK_PARAM(PARAM_EVRT_SOURCE_ACTIVE_TYPE(type));\r
-\r
- switch (type)\r
- {\r
- case EVRT_SRC_ACTIVE_LOW_LEVEL:\r
- EVRTx->HILO &= ~(1<<(uint8_t)EVRT_Src);\r
- EVRTx->EDGE &= ~(1<<(uint8_t)EVRT_Src);\r
- break;\r
- case EVRT_SRC_ACTIVE_HIGH_LEVEL:\r
- EVRTx->HILO |= (1<<(uint8_t)EVRT_Src);\r
- EVRTx->EDGE &= ~(1<<(uint8_t)EVRT_Src);\r
- break;\r
- case EVRT_SRC_ACTIVE_FALLING_EDGE:\r
- EVRTx->HILO &= ~(1<<(uint8_t)EVRT_Src);\r
- EVRTx->EDGE |= (1<<(uint8_t)EVRT_Src);\r
- break;\r
- case EVRT_SRC_ACTIVE_RISING_EDGE:\r
- EVRTx->HILO |= (1<<(uint8_t)EVRT_Src);\r
- EVRTx->EDGE |= (1<<(uint8_t)EVRT_Src);\r
- break;\r
- default:\r
- break;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable or disable interrupt sources to EVRT\r
- * @param[in] EVRTx EVRT peripheral selected, should be LPC_EVRT\r
- * @param[in] EVRT_Src EVRT source, should be:\r
- * - EVRT_SRC_WAKEUP0 :WAKEUP0 event\r
- * - EVRT_SRC_WAKEUP1 :WAKEUP1 event\r
- * - EVRT_SRC_WAKEUP2 :WAKEUP2 event\r
- * - EVRT_SRC_WAKEUP3 :WAKEUP3 event\r
- * - EVRT_SRC_ATIMER :Alarm timer eveny\r
- * - EVRT_SRC_RTC :RTC event\r
- * - EVRT_SRC_BOD :BOD event\r
- * - EVRT_SRC_WWDT :WWDT event\r
- * - EVRT_SRC_ETHERNET :ETHERNET event\r
- * - EVRT_SRC_USB0 :USB0 event\r
- * - EVRT_SRC_USB1 :USB1 event\r
- * - EVRT_SRC_CCAN :CCAN event\r
- * - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event\r
- * - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event\r
- * - EVRT_SRC_QEI :QEI event\r
- * - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event\r
- * - EVRT_SRC_RESET :RESET event\r
- * @param[in] state ENABLE or DISABLE\r
- * @return None\r
- **********************************************************************/\r
-void EVRT_SetUpIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, FunctionalState state)\r
-{\r
- CHECK_PARAM(PARAM_EVRTx(EVRTx));\r
- CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src));\r
-\r
- if(state == ENABLE)\r
- EVRTx->SET_EN = (1<<(uint8_t)EVRT_Src);\r
- else\r
- EVRTx->CLR_EN = (1<<(uint8_t)EVRT_Src);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Check if a source is sending interrupt to EVRT\r
- * @param[in] EVRTx EVRT peripheral selected, should be LPC_EVRT\r
- * @param[in] EVRT_Src EVRT source, should be:\r
- * - EVRT_SRC_WAKEUP0 :WAKEUP0 event\r
- * - EVRT_SRC_WAKEUP1 :WAKEUP1 event\r
- * - EVRT_SRC_WAKEUP2 :WAKEUP2 event\r
- * - EVRT_SRC_WAKEUP3 :WAKEUP3 event\r
- * - EVRT_SRC_ATIMER :Alarm timer eveny\r
- * - EVRT_SRC_RTC :RTC event\r
- * - EVRT_SRC_BOD :BOD event\r
- * - EVRT_SRC_WWDT :WWDT event\r
- * - EVRT_SRC_ETHERNET :ETHERNET event\r
- * - EVRT_SRC_USB0 :USB0 event\r
- * - EVRT_SRC_USB1 :USB1 event\r
- * - EVRT_SRC_CCAN :CCAN event\r
- * - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event\r
- * - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event\r
- * - EVRT_SRC_QEI :QEI event\r
- * - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event\r
- * - EVRT_SRC_RESET :RESET event\r
- * @return TRUE or FALSE\r
- **********************************************************************/\r
-Bool EVRT_IsSourceInterrupting(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src)\r
-{\r
- CHECK_PARAM(PARAM_EVRTx(EVRTx));\r
- CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src));\r
-\r
- if(EVRTx->STATUS & (1<<(uint8_t)EVRT_Src))\r
- return TRUE;\r
- else return FALSE;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Clear pending interrupt EVRT source\r
- * @param[in] EVRTx EVRT peripheral selected, should be LPC_EVRT\r
- * @param[in] EVRT_Src EVRT source, should be:\r
- * - EVRT_SRC_WAKEUP0 :WAKEUP0 event\r
- * - EVRT_SRC_WAKEUP1 :WAKEUP1 event\r
- * - EVRT_SRC_WAKEUP2 :WAKEUP2 event\r
- * - EVRT_SRC_WAKEUP3 :WAKEUP3 event\r
- * - EVRT_SRC_ATIMER :Alarm timer eveny\r
- * - EVRT_SRC_RTC :RTC event\r
- * - EVRT_SRC_BOD :BOD event\r
- * - EVRT_SRC_WWDT :WWDT event\r
- * - EVRT_SRC_ETHERNET :ETHERNET event\r
- * - EVRT_SRC_USB0 :USB0 event\r
- * - EVRT_SRC_USB1 :USB1 event\r
- * - EVRT_SRC_CCAN :CCAN event\r
- * - EVRT_SRC_COMBINE_TIMER2 :Combined timer output 2 event\r
- * - EVRT_SRC_COMBINE_TIMER6 :Combined timer output 6 event\r
- * - EVRT_SRC_QEI :QEI event\r
- * - EVRT_SRC_COMBINE_TIMER14 :Combined timer output 14 event\r
- * - EVRT_SRC_RESET :RESET event\r
- * @return none\r
- **********************************************************************/\r
-void EVRT_ClrPendIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src)\r
-{\r
- CHECK_PARAM(PARAM_EVRTx(EVRTx));\r
- CHECK_PARAM(PARAM_EVRT_SOURCE(EVRT_Src));\r
-\r
- EVRTx->CLR_STAT = (1<<(uint8_t)EVRT_Src);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_gpdma.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_gpdma.c\r
-* @brief Contains all functions support for GPDMA firmware library\r
-* on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup GPDMA\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_gpdma.h"\r
-//#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-#ifdef _GPDMA\r
-\r
-/** GPDMA Mux definitions */\r
-#define DMAMUX_ADDRESS 0x4004311C\r
-\r
-/* Private Functions ----------------------------------------------------------- */\r
-/** @\r
- * @{\r
- */\r
-uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number);\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private Variables ---------------------------------------------------------- */\r
-/** @defgroup GPDMA_Private_Variables GPDMA Private Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Lookup Table of Connection Type matched with\r
- * Peripheral Data (FIFO) register base address\r
- */\r
-#ifdef __ICCARM__\r
-volatile const void *GPDMA_LUTPerAddr[] = {\r
- (&LPC_SPIFI->DAT), // SPIFI\r
- (&LPC_TIMER0->MR), // MAT0.0\r
- (&LPC_USART0->/*RBTHDLR.*/THR), // UART0 Tx\r
- ((uint32_t*)&LPC_TIMER0->MR + 1), // MAT0.1\r
- (&LPC_USART0->/*RBTHDLR.*/RBR), // UART0 Rx\r
- (&LPC_TIMER1->MR), // MAT1.0\r
- (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx\r
- ((uint32_t*)&LPC_TIMER1->MR + 1), // MAT1.1\r
- (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx\r
- (&LPC_TIMER2->MR), // MAT2.0\r
- (&LPC_USART2->/*RBTHDLR.*/THR), // UART2 Tx\r
- ((uint32_t*)&LPC_TIMER2->MR + 1), // MAT2.1\r
- (&LPC_USART2->/*RBTHDLR.*/RBR), // UART2 Rx\r
- (&LPC_TIMER3->MR), // MAT3.0\r
- (&LPC_USART3->/*RBTHDLR.*/THR), // UART3 Tx\r
- 0, // to be defined: SCT DMA request 0\r
- ((uint32_t*)&LPC_TIMER3->MR + 1), // MAT3.1\r
- (&LPC_USART3->/*RBTHDLR.*/RBR), // UART3 Rx\r
- 0, // to be defined: SCT DMA request 1\r
- (&LPC_SSP0->DR), // SSP0 Rx\r
- (&LPC_I2S0->TXFIFO), // I2S channel 0\r
- (&LPC_SSP0->DR), // SSP0 Tx\r
- (&LPC_I2S0->RXFIFO), // I2S channel 1\r
- (&LPC_SSP1->DR), // SSP1 Rx\r
- (&LPC_SSP1->DR), // SSP1 Tx\r
- (&LPC_ADC0->GDR), // ADC 0\r
- (&LPC_ADC1->GDR), // ADC 1\r
- (&LPC_DAC->CR) // DAC\r
-};\r
-#else\r
-const uint32_t GPDMA_LUTPerAddr[] = {\r
-// ((uint32_t)&LPC_SPIFI->DAT), // SPIFI\r
- ((uint32_t)0), // SPIFI\r
- ((uint32_t)&LPC_TIMER0->MR[0]), // MAT0.0\r
- ((uint32_t)&LPC_USART0->/*RBTHDLR.*/THR), // UART0 Tx\r
- ((uint32_t)&LPC_TIMER0->MR[1]), // MAT0.1\r
- ((uint32_t)&LPC_USART0->/*RBTHDLR.*/RBR), // UART0 Rx\r
- ((uint32_t)&LPC_TIMER1->MR[0]), // MAT1.0\r
- ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx\r
- ((uint32_t)&LPC_TIMER1->MR[1]), // MAT1.1\r
- ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx\r
- ((uint32_t)&LPC_TIMER2->MR[0]), // MAT2.0\r
- ((uint32_t)&LPC_USART2->/*RBTHDLR.*/THR), // UART2 Tx\r
- ((uint32_t)&LPC_TIMER2->MR[1]), // MAT2.1\r
- ((uint32_t)&LPC_USART2->/*RBTHDLR.*/RBR), // UART2 Rx\r
- ((uint32_t)&LPC_TIMER3->MR[0]), // MAT3.0\r
- ((uint32_t)&LPC_USART3->/*RBTHDLR.*/THR), // UART3 Tx\r
- 0, // to be defined: SCT DMA request 0\r
- ((uint32_t)&LPC_TIMER3->MR[1]), // MAT3.1\r
- ((uint32_t)&LPC_USART3->/*RBTHDLR.*/RBR), // UART3 Rx\r
- 0, // to be defined: SCT DMA request 1\r
- ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx\r
- ((uint32_t)&LPC_I2S0->TXFIFO), // I2S channel 0\r
- ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx\r
- ((uint32_t)&LPC_I2S0->RXFIFO), // I2S channel 1\r
- ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx\r
- ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx\r
- ((uint32_t)&LPC_ADC0->GDR), // ADC 0\r
- ((uint32_t)&LPC_ADC1->GDR), // ADC 1\r
- ((uint32_t)&LPC_DAC->CR) // DAC\r
-};\r
-#endif\r
-/**\r
- * @brief Lookup Table of GPDMA Channel Number matched with\r
- * GPDMA channel pointer\r
- */\r
-const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {\r
- LPC_GPDMACH0, // GPDMA Channel 0\r
- LPC_GPDMACH1, // GPDMA Channel 1\r
- LPC_GPDMACH2, // GPDMA Channel 2\r
- LPC_GPDMACH3, // GPDMA Channel 3\r
- LPC_GPDMACH4, // GPDMA Channel 4\r
- LPC_GPDMACH5, // GPDMA Channel 5\r
- LPC_GPDMACH6, // GPDMA Channel 6\r
- LPC_GPDMACH7, // GPDMA Channel 7\r
-};\r
-/**\r
- * @brief Optimized Peripheral Source and Destination burst size\r
- */\r
-const uint8_t GPDMA_LUTPerBurst[] = {\r
- GPDMA_BSIZE_4, // SPIFI\r
- GPDMA_BSIZE_1, // MAT0.0\r
- GPDMA_BSIZE_1, // UART0 Tx\r
- GPDMA_BSIZE_1, // MAT0.1\r
- GPDMA_BSIZE_1, // UART0 Rx\r
- GPDMA_BSIZE_1, // MAT1.0\r
- GPDMA_BSIZE_1, // UART1 Tx\r
- GPDMA_BSIZE_1, // MAT1.1\r
- GPDMA_BSIZE_1, // UART1 Rx\r
- GPDMA_BSIZE_1, // MAT2.0\r
- GPDMA_BSIZE_1, // UART2 Tx\r
- GPDMA_BSIZE_1, // MAT2.1\r
- GPDMA_BSIZE_1, // UART2 Rx\r
- GPDMA_BSIZE_1, // MAT3.0\r
- GPDMA_BSIZE_1, // UART3 Tx\r
- 0, // to be defined: SCT DMA request 0\r
- GPDMA_BSIZE_1, // MAT3.1\r
- GPDMA_BSIZE_1, // UART3 Rx\r
- 0, // to be defined: SCT DMA request 1\r
- GPDMA_BSIZE_4, // SSP0 Rx\r
- GPDMA_BSIZE_32, // I2S channel 0\r
- GPDMA_BSIZE_4, // SSP0 Tx\r
- GPDMA_BSIZE_32, // I2S channel 1\r
- GPDMA_BSIZE_4, // SSP1 Rx\r
- GPDMA_BSIZE_4, // SSP1 Tx\r
- GPDMA_BSIZE_4, // ADC 0\r
- GPDMA_BSIZE_4, // ADC 1\r
- GPDMA_BSIZE_1, // DAC\r
-};\r
-/**\r
- * @brief Optimized Peripheral Source and Destination transfer width\r
- */\r
-const uint8_t GPDMA_LUTPerWid[] = {\r
- GPDMA_WIDTH_WORD, // SPIFI\r
- GPDMA_WIDTH_WORD, // MAT0.0\r
- GPDMA_WIDTH_BYTE, // UART0 Tx\r
- GPDMA_WIDTH_WORD, // MAT0.1\r
- GPDMA_WIDTH_BYTE, // UART0 Rx\r
- GPDMA_WIDTH_WORD, // MAT1.0\r
- GPDMA_WIDTH_BYTE, // UART1 Tx\r
- GPDMA_WIDTH_WORD, // MAT1.1\r
- GPDMA_WIDTH_BYTE, // UART1 Rx\r
- GPDMA_WIDTH_WORD, // MAT2.0\r
- GPDMA_WIDTH_BYTE, // UART2 Tx\r
- GPDMA_WIDTH_WORD, // MAT2.1\r
- GPDMA_WIDTH_BYTE, // UART2 Rx\r
- GPDMA_WIDTH_WORD, // MAT3.0\r
- GPDMA_WIDTH_BYTE, // UART3 Tx\r
- 0, // to be defined: SCT DMA request 0\r
- GPDMA_WIDTH_WORD, // MAT3.1\r
- GPDMA_WIDTH_BYTE, // UART3 Rx\r
- 0, // to be defined: SCT DMA request 1\r
- GPDMA_WIDTH_BYTE, // SSP0 Rx\r
- GPDMA_WIDTH_WORD, // I2S channel 0\r
- GPDMA_WIDTH_BYTE, // SSP0 Tx\r
- GPDMA_WIDTH_WORD, // I2S channel 1\r
- GPDMA_WIDTH_BYTE, // SSP1 Rx\r
- GPDMA_WIDTH_BYTE, // SSP1 Tx\r
- GPDMA_WIDTH_WORD, // ADC 0\r
- GPDMA_WIDTH_WORD, // ADC 1\r
- GPDMA_WIDTH_WORD, // DAC\r
-};\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private Functions ----------------------------------------------------------- */\r
-/** @\r
- * @{\r
- */\r
-\r
-/********************************************************************//**\r
- * @brief Control which set of peripherals is connected to the\r
- * DMA controller\r
- * @param[in] gpdma_peripheral_connection_number GPDMA peripheral\r
- * connection number, should be:\r
- * - GPDMA_CONN_SPIFI :SPIFI\r
- * - GPDMA_CONN_MAT0_0 :Timer 0, match channel 0\r
- * - GPDMA_CONN_MAT0_1 :Timer 0, match channel 1\r
- * - GPDMA_CONN_MAT1_0 :Timer 1, match channel 0\r
- * - GPDMA_CONN_MAT1_1 :Timer 1, match channel 1\r
- * - GPDMA_CONN_MAT2_0 :Timer 2, match channel 0\r
- * - GPDMA_CONN_MAT2_1 :Timer 2, match channel 1\r
- * - GPDMA_CONN_MAT3_0 :Timer 3, match channel 0\r
- * - GPDMA_CONN_MAT3_1 :Timer 3, match channel 1\r
- * - GPDMA_CONN_UART0_Tx :USART 0 transmit\r
- * - GPDMA_CONN_UART0_Rx :USART 0 receive\r
- * - GPDMA_CONN_UART1_Tx :USART 1 transmit\r
- * - GPDMA_CONN_UART1_Rx :USART 1 receive\r
- * - GPDMA_CONN_UART2_Tx :USART 2 transmit\r
- * - GPDMA_CONN_UART2_Rx :USART 2 receive\r
- * - GPDMA_CONN_UART3_Tx :USART 3 transmit\r
- * - GPDMA_CONN_UART3_Rx :USART 3 receive\r
- * - GPDMA_CONN_SCT_0 :SCT output 0\r
- * - GPDMA_CONN_SCT_1 :SCT output 1\r
- * - GPDMA_CONN_I2S_Channel_0 :I2S channel 0\r
- * - GPDMA_CONN_I2S_Channel_1 :I2S channel 1\r
- * - GPDMA_CONN_SSP0_Tx :SSP0 transmit\r
- * - GPDMA_CONN_SSP0_Rx :SSP0 receive\r
- * - GPDMA_CONN_SSP1_Tx :SSP1 transmit\r
- * - GPDMA_CONN_SSP1_Rx :SSP1 receive\r
- * - GPDMA_CONN_ADC_0 :ADC0\r
- * - GPDMA_CONN_ADC_1 :ADC1\r
- * - GPDMA_CONN_DAC :DAC\r
- * @return channel number, could be in range: 0..16\r
- *********************************************************************/\r
-uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number)\r
-{\r
- uint32_t *dmamux_reg = (uint32_t*)DMAMUX_ADDRESS;\r
- uint8_t function, channel;\r
-\r
- switch(gpdma_peripheral_connection_number)\r
- {\r
- case GPDMA_CONN_SPIFI: function = 0; channel = 0; break;\r
- case GPDMA_CONN_MAT0_0: function = 0; channel = 1; break;\r
- case GPDMA_CONN_UART0_Tx: function = 1; channel = 1; break;\r
- case GPDMA_CONN_MAT0_1: function = 0; channel = 2; break;\r
- case GPDMA_CONN_UART0_Rx: function = 1; channel = 2; break;\r
- case GPDMA_CONN_MAT1_0: function = 0; channel = 3; break;\r
- case GPDMA_CONN_UART1_Tx: function = 1; channel = 3; break;\r
- case GPDMA_CONN_MAT1_1: function = 0; channel = 4; break;\r
- case GPDMA_CONN_UART1_Rx: function = 1; channel = 4; break;\r
- case GPDMA_CONN_MAT2_0: function = 0; channel = 5; break;\r
- case GPDMA_CONN_UART2_Tx: function = 1; channel = 5; break;\r
- case GPDMA_CONN_MAT2_1: function = 0; channel = 6; break;\r
- case GPDMA_CONN_UART2_Rx: function = 1; channel = 6; break;\r
- case GPDMA_CONN_MAT3_0: function = 0; channel = 7; break;\r
- case GPDMA_CONN_UART3_Tx: function = 1; channel = 7; break;\r
- case GPDMA_CONN_SCT_0: function = 2; channel = 7; break;\r
- case GPDMA_CONN_MAT3_1: function = 0; channel = 8; break;\r
- case GPDMA_CONN_UART3_Rx: function = 1; channel = 8; break;\r
- case GPDMA_CONN_SCT_1: function = 2; channel = 8; break;\r
- case GPDMA_CONN_SSP0_Rx: function = 0; channel = 9; break;\r
- case GPDMA_CONN_I2S_Channel_0:function = 1; channel = 9; break;\r
- case GPDMA_CONN_SSP0_Tx: function = 0; channel = 10; break;\r
- case GPDMA_CONN_I2S_Channel_1:function = 1; channel = 10; break;\r
- case GPDMA_CONN_SSP1_Rx: function = 0; channel = 11; break;\r
- case GPDMA_CONN_SSP1_Tx: function = 0; channel = 12; break;\r
- case GPDMA_CONN_ADC_0: function = 0; channel = 13; break;\r
- case GPDMA_CONN_ADC_1: function = 0; channel = 14; break;\r
- case GPDMA_CONN_DAC: function = 0; channel = 15; break;\r
- default: function = 3; channel = 15; break;\r
- }\r
- //Set select function to dmamux register\r
- *dmamux_reg &= ~(0x03<<(2*channel));\r
- *dmamux_reg |= (function<<(2*channel));\r
-\r
- return channel;\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup GPDMA_Public_Functions\r
- * @{\r
- */\r
-\r
-/********************************************************************//**\r
- * @brief Initialize GPDMA controller\r
- * @param[in] None\r
- * @return None\r
- *********************************************************************/\r
-void GPDMA_Init(void)\r
-{\r
- /* to be defined Enable GPDMA clock */\r
- // enabled default on reset\r
-\r
- // Reset all channel configuration register\r
- LPC_GPDMACH0->CConfig = 0;\r
- LPC_GPDMACH1->CConfig = 0;\r
- LPC_GPDMACH2->CConfig = 0;\r
- LPC_GPDMACH3->CConfig = 0;\r
- LPC_GPDMACH4->CConfig = 0;\r
- LPC_GPDMACH5->CConfig = 0;\r
- LPC_GPDMACH6->CConfig = 0;\r
- LPC_GPDMACH7->CConfig = 0;\r
-\r
- /* Clear all DMA interrupt and error flag */\r
- LPC_GPDMA->INTTCCLEAR = 0xFF;\r
- LPC_GPDMA->INTERRCLR = 0xFF;\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Setup GPDMA channel peripheral according to the specified\r
- * parameters in the GPDMAChannelConfig.\r
- * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type structure\r
- * that contains the configuration information for the specified\r
- * GPDMA channel peripheral.\r
- * @return Setup status, could be:\r
- * - ERROR :if selected channel is enabled before\r
- * - SUCCESS :if channel is configured successfully\r
- *********************************************************************/\r
-Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)\r
-{\r
- LPC_GPDMACH_TypeDef *pDMAch;\r
- uint8_t SrcPeripheral=0, DestPeripheral=0;\r
-\r
- if (LPC_GPDMA->ENBLDCHNS & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {\r
- // This channel is enabled, return ERROR, need to release this channel first\r
- return ERROR;\r
- }\r
-\r
- // Get Channel pointer\r
- pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];\r
-\r
- // Reset the Interrupt status\r
- LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);\r
- LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);\r
-\r
- // Clear DMA configure\r
- pDMAch->CControl = 0x00;\r
- pDMAch->CConfig = 0x00;\r
-\r
- /* Assign Linker List Item value */\r
- pDMAch->CLLI = GPDMAChannelConfig->DMALLI;\r
-\r
- /* Set value to Channel Control Registers */\r
- switch (GPDMAChannelConfig->TransferType)\r
- {\r
- // Memory to memory\r
- case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:\r
- // Assign physical source and destination address\r
- pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;\r
- pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;\r
- pDMAch->CControl\r
- = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \\r
- | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \\r
- | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \\r
- | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \\r
- | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \\r
- | GPDMA_DMACCxControl_SI \\r
- | GPDMA_DMACCxControl_DI \\r
- | GPDMA_DMACCxControl_I;\r
- break;\r
- // Memory to peripheral\r
- case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:\r
- // Assign physical source\r
- pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;\r
- // Assign peripheral destination address\r
- pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];\r
- pDMAch->CControl\r
- = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \\r
- | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \\r
- | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \\r
- | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \\r
- | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \\r
- | GPDMA_DMACCxControl_DestTransUseAHBMaster1 \\r
- | GPDMA_DMACCxControl_SI \\r
- | GPDMA_DMACCxControl_I;\r
- DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);\r
- break;\r
- // Peripheral to memory\r
- case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:\r
- // Assign peripheral source address\r
- pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];\r
- // Assign memory destination address\r
- pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;\r
- pDMAch->CControl\r
- = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \\r
- | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \\r
- | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \\r
- | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \\r
- | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \\r
- | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \\r
- | GPDMA_DMACCxControl_DI \\r
- | GPDMA_DMACCxControl_I;\r
- SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);\r
- break;\r
- // Peripheral to peripheral\r
- case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:\r
- // Assign peripheral source address\r
- pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];\r
- // Assign peripheral destination address\r
- pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];\r
- pDMAch->CControl\r
- = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \\r
- | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \\r
- | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \\r
- | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \\r
- | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \\r
- | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \\r
- | GPDMA_DMACCxControl_DestTransUseAHBMaster1 \\r
- | GPDMA_DMACCxControl_I;\r
- SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);\r
- DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);\r
- break;\r
-\r
- case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:\r
- case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:\r
- case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:\r
- case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:\r
- //to be defined\r
- // Do not support any more transfer type, return ERROR\r
- default:\r
- return ERROR;\r
- }\r
-\r
- /* Enable DMA channels, little endian */\r
- LPC_GPDMA->CONFIG = GPDMA_DMACConfig_E;\r
- while (!(LPC_GPDMA->CONFIG & GPDMA_DMACConfig_E));\r
-\r
- // Configure DMA Channel, enable Error Counter and Terminate counter\r
- pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \\r
- | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \\r
- | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) \\r
- | GPDMA_DMACCxConfig_DestPeripheral(DestPeripheral);\r
-\r
- return SUCCESS;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable DMA channel\r
- * @param[in] channelNum GPDMA channel, should be in range from 0 to 15\r
- * @param[in] NewState New State of this command, should be:\r
- * - ENABLE.\r
- * - DISABLE.\r
- * @return None\r
- **********************************************************************/\r
-void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)\r
-{\r
- LPC_GPDMACH_TypeDef *pDMAch;\r
-\r
- // Get Channel pointer\r
- pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];\r
-\r
- if (NewState == ENABLE) {\r
- pDMAch->CConfig |= GPDMA_DMACCxConfig_E;\r
- } else {\r
- pDMAch->CConfig &= ~GPDMA_DMACCxConfig_E;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Check if corresponding channel does have an active interrupt\r
- * request or not\r
- * @param[in] type type of status, should be:\r
- * - GPDMA_STAT_INT :GPDMA Interrupt Status\r
- * - GPDMA_STAT_INTTC :GPDMA Interrupt Terminal Count Request Status\r
- * - GPDMA_STAT_INTERR :GPDMA Interrupt Error Status\r
- * - GPDMA_STAT_RAWINTTC :GPDMA Raw Interrupt Terminal Count Status\r
- * - GPDMA_STAT_RAWINTERR :GPDMA Raw Error Interrupt Status\r
- * - GPDMA_STAT_ENABLED_CH :GPDMA Enabled Channel Status\r
- * @param[in] channel GPDMA channel, should be in range from 0 to 7\r
- * @return IntStatus status of DMA channel interrupt after masking\r
- * Should be:\r
- * - SET :the corresponding channel has no active interrupt request\r
- * - RESET :the corresponding channel does have an active interrupt request\r
- **********************************************************************/\r
-IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)\r
-{\r
- CHECK_PARAM(PARAM_GPDMA_STAT(type));\r
- CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));\r
-\r
- switch (type)\r
- {\r
- case GPDMA_STAT_INT: //check status of DMA channel interrupts\r
- if (LPC_GPDMA->INTSTAT & (GPDMA_DMACIntStat_Ch(channel)))\r
- return SET;\r
- return RESET;\r
- case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA\r
- if (LPC_GPDMA->INTTCSTAT & GPDMA_DMACIntTCStat_Ch(channel))\r
- return SET;\r
- return RESET;\r
- case GPDMA_STAT_INTERR: //check interrupt status for DMA channels\r
- if (LPC_GPDMA->INTERRSTAT & GPDMA_DMACIntTCClear_Ch(channel))\r
- return SET;\r
- return RESET;\r
- case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels\r
- if (LPC_GPDMA->RAWINTERRSTAT & GPDMA_DMACRawIntTCStat_Ch(channel))\r
- return SET;\r
- return RESET;\r
- case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels\r
- if (LPC_GPDMA->RAWINTTCSTAT & GPDMA_DMACRawIntErrStat_Ch(channel))\r
- return SET;\r
- return RESET;\r
- default: //check enable status for DMA channels\r
- if (LPC_GPDMA->ENBLDCHNS & GPDMA_DMACEnbldChns_Ch(channel))\r
- return SET;\r
- return RESET;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Clear one or more interrupt requests on DMA channels\r
- * @param[in] type type of interrupt request, should be:\r
- * - GPDMA_STATCLR_INTTC :GPDMA Interrupt Terminal Count Request Clear\r
- * - GPDMA_STATCLR_INTERR :GPDMA Interrupt Error Clear\r
- * @param[in] channel GPDMA channel, should be in range from 0 to 15\r
- * @return None\r
- **********************************************************************/\r
-void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)\r
-{\r
- CHECK_PARAM(PARAM_GPDMA_STATCLR(type));\r
- CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));\r
-\r
- if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel\r
- LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(channel);\r
- else // clear the error interrupt request\r
- LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(channel);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _GPDMA */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_gpio.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_gpio.c\r
-* @brief Contains all functions support for GPIO firmware library\r
-* on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup GPIO\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_gpio.h"\r
-#include "lpc_types.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _GPIO\r
-\r
-/* Private Functions ---------------------------------------------------------- */\r
-\r
-//static LPC_GPIOn_Type *GPIO_GetPointer(uint8_t portNum);\r
-//static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum);\r
-//static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum);\r
-\r
-#if 0\r
-/*********************************************************************//**\r
- * @brief Get pointer to GPIO peripheral due to GPIO port\r
- * @param[in] portNum Port Number value, should be in range from 0 to 4.\r
- * @return Pointer to GPIO peripheral\r
- **********************************************************************/\r
-static LPC_GPIOn_Type *GPIO_GetPointer(uint8_t portNum)\r
-{\r
- LPC_GPIOn_Type *pGPIO = NULL;\r
-\r
- switch (portNum)\r
- {\r
- case 0:\r
- pGPIO = LPC_GPIO0;\r
- break;\r
-\r
- case 1:\r
- pGPIO = LPC_GPIO1;\r
- break;\r
-\r
- case 2:\r
- pGPIO = LPC_GPIO2;\r
- break;\r
-\r
- case 3:\r
- pGPIO = LPC_GPIO3;\r
- break;\r
-\r
- case 4:\r
- pGPIO = LPC_GPIO4;\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- return pGPIO;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get pointer to FIO peripheral in halfword accessible style\r
- * due to FIO port\r
- * @param[in] portNum Port Number value, should be in range from 0 to 4.\r
- * @return Pointer to FIO peripheral\r
- **********************************************************************/\r
-static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum)\r
-{\r
- GPIO_HalfWord_TypeDef *pFIO = NULL;\r
-\r
- switch (portNum)\r
- {\r
- case 0:\r
- pFIO = GPIO0_HalfWord;\r
- break;\r
-\r
- case 1:\r
- pFIO = GPIO1_HalfWord;\r
- break;\r
-\r
- case 2:\r
- pFIO = GPIO2_HalfWord;\r
- break;\r
-\r
- case 3:\r
- pFIO = GPIO3_HalfWord;\r
- break;\r
-\r
- case 4:\r
- pFIO = GPIO4_HalfWord;\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- return pFIO;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get pointer to FIO peripheral in byte accessible style\r
- * due to FIO port\r
- * @param[in] portNum Port Number value, should be in range from 0 to 4.\r
- * @return Pointer to FIO peripheral\r
- **********************************************************************/\r
-static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum)\r
-{\r
- GPIO_Byte_TypeDef *pFIO = NULL;\r
-\r
- switch (portNum)\r
- {\r
- case 0:\r
- pFIO = GPIO0_Byte;\r
- break;\r
-\r
- case 1:\r
- pFIO = GPIO1_Byte;\r
- break;\r
-\r
- case 2:\r
- pFIO = GPIO2_Byte;\r
- break;\r
-\r
- case 3:\r
- pFIO = GPIO3_Byte;\r
- break;\r
-\r
- case 4:\r
- pFIO = GPIO4_Byte;\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- return pFIO;\r
-}\r
-#endif\r
-\r
-/* End of Private Functions --------------------------------------------------- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup GPIO_Public_Functions\r
- * @{\r
- */\r
-\r
-\r
-/* GPIO ------------------------------------------------------------------------------ */\r
-\r
-/*********************************************************************//**\r
- * @brief Set Direction for GPIO port.\r
- * @param[in] portNum Port Number value, should be in range from 0 to 4\r
- * @param[in] bitValue Value that contains all bits to set direction,\r
- * in range from 0 to 0xFFFFFFFF.\r
- * example: value 0x5 to set direction for bit 0 and bit 1.\r
- * @param[in] dir Direction value, should be:\r
- * - 0: Input.\r
- * - 1: Output.\r
- * @return None\r
- *\r
- * Note:\r
- * All remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- **********************************************************************/\r
-void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir)\r
-{\r
- if (dir)\r
- {\r
- LPC_GPIO_PORT->DIR[portNum] |= bitValue;\r
- } else\r
- {\r
- LPC_GPIO_PORT->DIR[portNum] &= ~bitValue;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set Value for bits that have output direction on GPIO port.\r
- * @param[in] portNum Port number value, should be in range from 0 to 4\r
- * @param[in] bitValue Value that contains all bits on GPIO to set, should\r
- * be in range from 0 to 0xFFFFFFFF.\r
- * example: value 0x5 to set bit 0 and bit 1.\r
- * @return None\r
- *\r
- * Note:\r
- * - For all bits that has been set as input direction, this function will\r
- * not effect.\r
- * - For all remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- **********************************************************************/\r
-void GPIO_SetValue(uint8_t portNum, uint32_t bitValue)\r
-{\r
- LPC_GPIO_PORT->SET[portNum] = bitValue;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Clear Value for bits that have output direction on GPIO port.\r
- * @param[in] portNum Port number value, should be in range from 0 to 4\r
- * @param[in] bitValue Value that contains all bits on GPIO to clear, should\r
- * be in range from 0 to 0xFFFFFFFF.\r
- * example: value 0x5 to clear bit 0 and bit 1.\r
- * @return None\r
- *\r
- * Note:\r
- * - For all bits that has been set as input direction, this function will\r
- * not effect.\r
- * - For all remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- **********************************************************************/\r
-void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue)\r
-{\r
- LPC_GPIO_PORT->CLR[portNum] = bitValue;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Read Current state on port pin that have input direction of GPIO\r
- * @param[in] portNum Port number to read value, in range from 0 to 4\r
- * @return Current value of GPIO port.\r
- *\r
- * Note: Return value contain state of each port pin (bit) on that GPIO regardless\r
- * its direction is input or output.\r
- **********************************************************************/\r
-uint32_t GPIO_ReadValue(uint8_t portNum)\r
-{\r
- return LPC_GPIO_PORT->PIN[portNum];\r
-}\r
-\r
-\r
-#ifdef GPIO_INT\r
-/*********************************************************************//**\r
- * @brief Enable GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13)\r
- * @param[in] portNum Port number to read value, should be: 0 or 2\r
- * @param[in] bitValue Value that contains all bits on GPIO to enable,\r
- * should be in range from 0 to 0xFFFFFFFF.\r
- * @param[in] edgeState state of edge, should be:\r
- * - 0: Rising edge\r
- * - 1: Falling edge\r
- * @return None\r
- **********************************************************************/\r
-void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState)\r
-{\r
- if((portNum == 0)&&(edgeState == 0))\r
- LPC_GPIOINT->IO0IntEnR = bitValue;\r
- else if ((portNum == 2)&&(edgeState == 0))\r
- LPC_GPIOINT->IO2IntEnR = bitValue;\r
- else if ((portNum == 0)&&(edgeState == 1))\r
- LPC_GPIOINT->IO0IntEnF = bitValue;\r
- else if ((portNum == 2)&&(edgeState == 1))\r
- LPC_GPIOINT->IO2IntEnF = bitValue;\r
- else\r
- //Error\r
- while(1);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get GPIO Interrupt Status (just used for P0.0-P0.30, P2.0-P2.13)\r
- * @param[in] portNum Port number to read value, should be: 0 or 2\r
- * @param[in] pinNum Pin number, should be: 0..30(with port 0) and 0..13\r
- * (with port 2)\r
- * @param[in] edgeState state of edge, should be:\r
- * - 0 :Rising edge\r
- * - 1 :Falling edge\r
- * @return Function status, could be:\r
- * - ENABLE :Interrupt has been generated due to a rising edge on P0.0\r
- * - DISABLE :A rising edge has not been detected on P0.0\r
- **********************************************************************/\r
-FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState)\r
-{\r
- if((portNum == 0) && (edgeState == 0))//Rising Edge\r
- return (((LPC_GPIOINT->IO0IntStatR)>>pinNum)& 0x1);\r
- else if ((portNum == 2) && (edgeState == 0))\r
- return (((LPC_GPIOINT->IO2IntStatR)>>pinNum)& 0x1);\r
- else if ((portNum == 0) && (edgeState == 1))//Falling Edge\r
- return (((LPC_GPIOINT->IO0IntStatF)>>pinNum)& 0x1);\r
- else if ((portNum == 2) && (edgeState == 1))\r
- return (((LPC_GPIOINT->IO2IntStatF)>>pinNum)& 0x1);\r
- else\r
- //Error\r
- while(1);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Clear GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13)\r
- * @param[in] portNum Port number to read value, should be: 0 or 2\r
- * @param[in] bitValue Value that contains all bits on GPIO to enable,\r
- * should be in range from 0 to 0xFFFFFFFF.\r
- * @return None\r
- **********************************************************************/\r
-void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue)\r
-{\r
- if(portNum == 0)\r
- LPC_GPIOINT->IO0IntClr = bitValue;\r
- else if (portNum == 2)\r
- LPC_GPIOINT->IO2IntClr = bitValue;\r
- else\r
- //Invalid portNum\r
- while(1);\r
-}\r
-#endif\r
-\r
-\r
-/* FIO word accessible ----------------------------------------------------------------- */\r
-/* Stub function for FIO (word-accessible) style */\r
-\r
-/**\r
- * @brief The same with GPIO_SetDir()\r
- */\r
-void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir)\r
-{\r
- GPIO_SetDir(portNum, bitValue, dir);\r
-}\r
-\r
-/**\r
- * @brief The same with GPIO_SetValue()\r
- */\r
-void FIO_SetValue(uint8_t portNum, uint32_t bitValue)\r
-{\r
- GPIO_SetValue(portNum, bitValue);\r
-}\r
-\r
-/**\r
- * @brief The same with GPIO_ClearValue()\r
- */\r
-void FIO_ClearValue(uint8_t portNum, uint32_t bitValue)\r
-{\r
- GPIO_ClearValue(portNum, bitValue);\r
-}\r
-\r
-/**\r
- * @brief The same with GPIO_ReadValue()\r
- */\r
-uint32_t FIO_ReadValue(uint8_t portNum)\r
-{\r
- return (GPIO_ReadValue(portNum));\r
-}\r
-\r
-\r
-#ifdef GPIO_INT\r
-/**\r
- * @brief The same with GPIO_IntCmd()\r
- */\r
-void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState)\r
-{\r
- GPIO_IntCmd(portNum, bitValue, edgeState);\r
-}\r
-\r
-/**\r
- * @brief The same with GPIO_GetIntStatus()\r
- */\r
-FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState)\r
-{\r
- return (GPIO_GetIntStatus(portNum, pinNum, edgeState));\r
-}\r
-\r
-/**\r
- * @brief The same with GPIO_ClearInt()\r
- */\r
-void FIO_ClearInt(uint8_t portNum, uint32_t bitValue)\r
-{\r
- GPIO_ClearInt(portNum, bitValue);\r
-}\r
-#endif\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set mask value for bits in FIO port\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] bitValue Value that contains all bits in to set, should be\r
- * in range from 0 to 0xFFFFFFFF.\r
- * @param[in] maskValue Mask value contains state value for each bit:\r
- * - 0 :not mask.\r
- * - 1 :mask.\r
- * @return None\r
- *\r
- * Note:\r
- * - All remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- * - After executing this function, in mask register, value '0' on each bit\r
- * enables an access to the corresponding physical pin via a read or write access,\r
- * while value '1' on bit (masked) that corresponding pin will not be changed\r
- * with write access and if read, will not be reflected in the updated pin.\r
- **********************************************************************/\r
-void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue)\r
-{\r
- if (maskValue)\r
- {\r
- LPC_GPIO_PORT->MASK[portNum] |= bitValue;\r
- } else\r
- {\r
- LPC_GPIO_PORT->MASK[portNum] &= ~bitValue;\r
- }\r
-}\r
-\r
-\r
-/* FIO halfword accessible ------------------------------------------------------------- */\r
-#if 0\r
-/*********************************************************************//**\r
- * @brief Set direction for FIO port in halfword accessible style\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)\r
- * @param[in] bitValue Value that contains all bits in to set direction,\r
- * in range from 0 to 0xFFFF.\r
- * @param[in] dir Direction value, should be:\r
- * - 0 :Input.\r
- * - 1 :Output.\r
- * @return None\r
- *\r
- * Note: All remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- **********************************************************************/\r
-void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir)\r
-{\r
- GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);\r
-\r
- if(pFIO != NULL)\r
- {\r
- // Output direction\r
- if (dir)\r
- {\r
- // Upper\r
- if(halfwordNum)\r
- {\r
- pFIO->FIODIRU |= bitValue;\r
- }\r
- // lower\r
- else\r
- {\r
- pFIO->FIODIRL |= bitValue;\r
- }\r
- }\r
- // Input direction\r
- else\r
- {\r
- // Upper\r
- if(halfwordNum)\r
- {\r
- pFIO->FIODIRU &= ~bitValue;\r
- }\r
- // lower\r
- else\r
- {\r
- pFIO->FIODIRL &= ~bitValue;\r
- }\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set mask value for bits in FIO port in halfword accessible style\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)\r
- * @param[in] bitValue Value that contains all bits in to set,\r
- * in range from 0 to 0xFFFF.\r
- * @param[in] maskValue Mask value contains state value for each bit:\r
- * - 0: not mask.\r
- * - 1: mask.\r
- * @return None\r
- *\r
- * Note:\r
- * - All remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- * - After executing this function, in mask register, value '0' on each bit\r
- * enables an access to the corresponding physical pin via a read or write access,\r
- * while value '1' on bit (masked) that corresponding pin will not be changed\r
- * with write access and if read, will not be reflected in the updated pin.\r
- **********************************************************************/\r
-void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue)\r
-{\r
- GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);\r
-\r
- if(pFIO != NULL)\r
- {\r
- // Mask\r
- if (maskValue)\r
- {\r
- // Upper\r
- if(halfwordNum)\r
- {\r
- pFIO->FIOMASKU |= bitValue;\r
- }\r
- // lower\r
- else\r
- {\r
- pFIO->FIOMASKL |= bitValue;\r
- }\r
- }\r
- // Un-mask\r
- else\r
- {\r
- // Upper\r
- if(halfwordNum)\r
- {\r
- pFIO->FIOMASKU &= ~bitValue;\r
- }\r
- // lower\r
- else\r
- {\r
- pFIO->FIOMASKL &= ~bitValue;\r
- }\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set bits for FIO port in halfword accessible style\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)\r
- * @param[in] bitValue Value that contains all bits in to set, should be\r
- * in range from 0 to 0xFFFF.\r
- * @return None\r
- *\r
- * Note:\r
- * - For all bits that has been set as input direction, this function will\r
- * not effect.\r
- * - For all remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- **********************************************************************/\r
-void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue)\r
-{\r
- GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);\r
-\r
- if(pFIO != NULL)\r
- {\r
- // Upper\r
- if(halfwordNum)\r
- {\r
- pFIO->FIOSETU = bitValue;\r
- }\r
- // lower\r
- else\r
- {\r
- pFIO->FIOSETL = bitValue;\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Clear bits for FIO port in halfword accessible style\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)\r
- * @param[in] bitValue Value that contains all bits in to clear, should be\r
- * in range from 0 to 0xFFFF.\r
- * @return None\r
- *\r
- * Note:\r
- * - For all bits that has been set as input direction, this function will\r
- * not effect.\r
- * - For all remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- **********************************************************************/\r
-void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue)\r
-{\r
- GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);\r
-\r
- if(pFIO != NULL)\r
- {\r
- // Upper\r
- if(halfwordNum)\r
- {\r
- pFIO->FIOCLRU = bitValue;\r
- }\r
- // lower\r
- else\r
- {\r
- pFIO->FIOCLRL = bitValue;\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Read Current state on port pin that have input direction of GPIO\r
- * in halfword accessible style.\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)\r
- * @return Current value of FIO port pin of specified halfword.\r
- * Note: Return value contain state of each port pin (bit) on that FIO regardless\r
- * its direction is input or output.\r
- **********************************************************************/\r
-uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum)\r
-{\r
- GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);\r
-\r
- if(pFIO != NULL)\r
- {\r
- // Upper\r
- if(halfwordNum)\r
- {\r
- return (pFIO->FIOPINU);\r
- }\r
- // lower\r
- else\r
- {\r
- return (pFIO->FIOPINL);\r
- }\r
- }\r
-\r
- return (0);\r
-}\r
-\r
-\r
-/* FIO Byte accessible ------------------------------------------------------------ */\r
-\r
-/*********************************************************************//**\r
- * @brief Set direction for FIO port in byte accessible style\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] byteNum Byte part number, should be in range from 0 to 3\r
- * @param[in] bitValue Value that contains all bits in to set direction,\r
- * in range from 0 to 0xFF.\r
- * @param[in] dir Direction value, should be:\r
- * - 0: Input.\r
- * - 1: Output.\r
- * @return None\r
- *\r
- * Note: All remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- **********************************************************************/\r
-void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir)\r
-{\r
- GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);\r
-\r
- if(pFIO != NULL)\r
- {\r
- // Output direction\r
- if (dir)\r
- {\r
- if (byteNum <= 3)\r
- {\r
- pFIO->FIODIR[byteNum] |= bitValue;\r
- }\r
- }\r
- // Input direction\r
- else\r
- {\r
- if (byteNum <= 3)\r
- {\r
- pFIO->FIODIR[byteNum] &= ~bitValue;\r
- }\r
- }\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set mask value for bits in FIO port in byte accessible style\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] byteNum Byte part number, should be in range from 0 to 3\r
- * @param[in] bitValue Value that contains all bits in to set mask, should\r
- * be in range from 0 to 0xFF.\r
- * @param[in] maskValue Mask value contains state value for each bit:\r
- * - 0: not mask.\r
- * - 1: mask.\r
- * @return None\r
- *\r
- * Note:\r
- * - All remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- * - After executing this function, in mask register, value '0' on each bit\r
- * enables an access to the corresponding physical pin via a read or write access,\r
- * while value '1' on bit (masked) that corresponding pin will not be changed\r
- * with write access and if read, will not be reflected in the updated pin.\r
- **********************************************************************/\r
-void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue)\r
-{\r
- GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);\r
-\r
- if(pFIO != NULL)\r
- {\r
- // Mask\r
- if (maskValue)\r
- {\r
- if (byteNum <= 3)\r
- {\r
- pFIO->FIOMASK[byteNum] |= bitValue;\r
- }\r
- }\r
- // Un-mask\r
- else {\r
- if (byteNum <= 3)\r
- {\r
- pFIO->FIOMASK[byteNum] &= ~bitValue;\r
- }\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set bits for FIO port in byte accessible style\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] byteNum Byte part number, should be in range from 0 to 3\r
- * @param[in] bitValue Value that contains all bits in to set, should\r
- * be in range from 0 to 0xFF.\r
- * @return None\r
- *\r
- * Note:\r
- * - For all bits that has been set as input direction, this function will\r
- * not effect.\r
- * - For all remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- **********************************************************************/\r
-void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue)\r
-{\r
- GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);\r
-\r
- if (pFIO != NULL) {\r
- if (byteNum <= 3)\r
- {\r
- pFIO->FIOSET[byteNum] = bitValue;\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Clear bits for FIO port in byte accessible style\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] byteNum Byte part number, should be in range from 0 to 3\r
- * @param[in] bitValue Value that contains all bits in to clear, should\r
- * be in range from 0 to 0xFF.\r
- * @return None\r
- *\r
- * Note:\r
- * - For all bits that has been set as input direction, this function will\r
- * not effect.\r
- * - For all remaining bits that are not activated in bitValue (value '0')\r
- * will not be effected by this function.\r
- **********************************************************************/\r
-void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue)\r
-{\r
- GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);\r
-\r
- if (pFIO != NULL)\r
- {\r
- if (byteNum <= 3)\r
- {\r
- pFIO->FIOCLR[byteNum] = bitValue;\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Read Current state on port pin that have input direction of GPIO\r
- * in byte accessible style.\r
- * @param[in] portNum Port number, in range from 0 to 4\r
- * @param[in] byteNum Byte part number, should be in range from 0 to 3\r
- * @return Current value of FIO port pin of specified byte part.\r
- * Note: Return value contain state of each port pin (bit) on that FIO regardless\r
- * its direction is input or output.\r
- **********************************************************************/\r
-uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum)\r
-{\r
- GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);\r
-\r
- if (pFIO != NULL)\r
- {\r
- if (byteNum <= 3)\r
- {\r
- return (pFIO->FIOPIN[byteNum]);\r
- }\r
- }\r
- return (0);\r
-}\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _GPIO */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_i2c.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_i2c.c\r
-* @brief Contains all functions support for I2C firmware library\r
-* on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup I2C\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_i2c.h"\r
-#include "lpc18xx_cgu.h"\r
-#include "lpc18xx_scu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _I2C\r
-\r
-\r
-/* Private Types -------------------------------------------------------------- */\r
-/** @defgroup I2C_Private_Types I2C Private Types\r
- * @{\r
- */\r
-#define SFSP2_3_CONFIGURE_I2C1_SDA (0x00000001 | MD_ZI | MD_EZI)\r
-#define SFSP2_4_CONFIGURE_I2C1_SCL (0x00000001 | MD_ZI | MD_EZI)\r
-#define SFSI2C0_CONFIGURE_STANDARD_FAST_MODE (1<<3 | 1<<11)\r
-#define SFSI2C0_CONFIGURE_FASTPLUS_HIGHSPEED_MODE (2<<1 | 1<<3 | 1<<7 | 1<<10 | 1<<11)\r
-\r
-/**\r
- * @brief I2C device configuration structure type\r
- */\r
-typedef struct\r
-{\r
- uint32_t txrx_setup; /* Transmission setup */\r
- int32_t dir; /* Current direction phase, 0 - write, 1 - read */\r
-} I2C_CFG_T;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private Variables ---------------------------------------------------------- */\r
-/**\r
- * @brief II2C driver data for I2C0, I2C1\r
- */\r
-static I2C_CFG_T i2cdat[3];\r
-\r
-static uint32_t I2C_MasterComplete[3];\r
-static uint32_t I2C_SlaveComplete[3];\r
-\r
-static uint32_t I2C_MonitorBufferIndex;\r
-\r
-/* Private Functions ---------------------------------------------------------- */\r
-\r
-/* Get I2C number */\r
-static int32_t I2C_getNum(LPC_I2Cn_Type *I2Cx);\r
-\r
-/* Generate a start condition on I2C bus (in master mode only) */\r
-static uint32_t I2C_Start (LPC_I2Cn_Type *I2Cx);\r
-\r
-/* Generate a stop condition on I2C bus (in master mode only) */\r
-static void I2C_Stop (LPC_I2Cn_Type *I2Cx);\r
-\r
-/* I2C send byte subroutine */\r
-static uint32_t I2C_SendByte (LPC_I2Cn_Type *I2Cx, uint8_t databyte);\r
-\r
-/* I2C get byte subroutine */\r
-static uint32_t I2C_GetByte (LPC_I2Cn_Type *I2Cx, uint8_t *retdat, Bool ack);\r
-\r
-/*--------------------------------------------------------------------------------*/\r
-/********************************************************************//**\r
- * @brief Convert from I2C peripheral to number\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return I2C number or error code, could be:\r
- * - 0 :I2C0\r
- * - 1 :I2C1\r
- * - (-1) :Error\r
- *********************************************************************/\r
-static int32_t I2C_getNum(LPC_I2Cn_Type *I2Cx){\r
- if (I2Cx == LPC_I2C0) {\r
- return (0);\r
- } else if (I2Cx == LPC_I2C1) {\r
- return (1);\r
- }\r
- return (-1);\r
-}\r
-\r
-\r
-/********************************************************************//**\r
- * @brief Generate a start condition on I2C bus (in master mode only)\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return value of I2C status register after generate a start condition\r
- *********************************************************************/\r
-static uint32_t I2C_Start (LPC_I2Cn_Type *I2Cx)\r
-{\r
- I2Cx->CONSET = I2C_I2CONSET_STA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
-\r
- // Wait for complete\r
- while (!(I2Cx->CONSET & I2C_I2CONSET_SI));\r
- I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
- return (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
-}\r
-\r
-\r
-/********************************************************************//**\r
- * @brief Generate a stop condition on I2C bus (in master mode only)\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return None\r
- *********************************************************************/\r
-static void I2C_Stop (LPC_I2Cn_Type *I2Cx)\r
-{\r
-\r
- /* Make sure start bit is not active */\r
- if (I2Cx->CONSET & I2C_I2CONSET_STA)\r
- {\r
- I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
- }\r
- I2Cx->CONSET = I2C_I2CONSET_STO;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
-}\r
-\r
-\r
-/********************************************************************//**\r
- * @brief Send a byte\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[in] databyte sent data\r
- * @return value of I2C status register after sending\r
- *********************************************************************/\r
-static uint32_t I2C_SendByte (LPC_I2Cn_Type *I2Cx, uint8_t databyte)\r
-{\r
- /* Make sure start bit is not active */\r
- if (I2Cx->CONSET & I2C_I2CONSET_STA)\r
- {\r
- I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
- }\r
- I2Cx->DAT = databyte & I2C_I2DAT_BITMASK;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
-\r
- while (!(I2Cx->CONSET & I2C_I2CONSET_SI));\r
- return (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
-}\r
-\r
-\r
-/********************************************************************//**\r
- * @brief Get a byte\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[out] retdat pointer to return data\r
- * @param[in] ack assert acknowledge or not, should be: TRUE/FALSE\r
- * @return value of I2C status register after sending\r
- *********************************************************************/\r
-static uint32_t I2C_GetByte (LPC_I2Cn_Type *I2Cx, uint8_t *retdat, Bool ack)\r
-{\r
- if (ack == TRUE)\r
- {\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- }\r
- else\r
- {\r
- I2Cx->CONCLR = I2C_I2CONCLR_AAC;\r
- }\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
-\r
- while (!(I2Cx->CONSET & I2C_I2CONSET_SI));\r
- *retdat = (uint8_t) (I2Cx->DAT & I2C_I2DAT_BITMASK);\r
- return (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
-}\r
-\r
-/* End of Private Functions --------------------------------------------------- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup I2C_Public_Functions\r
- * @{\r
- */\r
-\r
-/********************************************************************//**\r
- * @brief Initializes the I2Cx peripheral with specified parameter.\r
- * @param[in] I2Cx I2C peripheral selected, should be\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[in] clockrate Target clock rate value to initialized I2C\r
- * peripheral (Hz)\r
- * @return None\r
- *********************************************************************/\r
-void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate)\r
-{\r
- uint32_t tem;\r
-\r
- CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
-\r
- if (I2Cx==LPC_I2C0)\r
- {\r
- /* Set up clock for I2C0 module */\r
- //LPC_CGU->BASE_VPB1_CLK = (SRC_PL160M_0<<24) | (1<<11);\r
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB1);\r
- /* Select weather standard, fast, fast plus mode*/\r
- if(clockrate>=1000000)// Fast mode plus: 1MHz, high speed 3.4MHz\r
- LPC_SCU->SFSI2C0 = SFSI2C0_CONFIGURE_FASTPLUS_HIGHSPEED_MODE;\r
- else // standard 100KHz, fast 400KHz\r
- LPC_SCU->SFSI2C0 = SFSI2C0_CONFIGURE_STANDARD_FAST_MODE;\r
- }\r
- else if (I2Cx==LPC_I2C1)\r
- {\r
- /* Set up clock for I2C1 module */\r
- //LPC_CGU->BASE_VPB3_CLK = (SRC_PL160M_0<<24) | (1<<11);\r
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB3);\r
- /* Configure pin function for I2C1*/\r
- LPC_SCU->SFSP2_3 = SFSP2_3_CONFIGURE_I2C1_SDA; /* SDA */\r
- LPC_SCU->SFSP2_4 = SFSP2_4_CONFIGURE_I2C1_SCL; /* SCL */\r
- /* Check if I2C1 run fast mode*/\r
- if(clockrate != 400000)\r
- return;\r
- }\r
- else {\r
- // Up-Support this device\r
- return;\r
- }\r
-\r
- /* Set clock rate */\r
- if(clockrate<1000) //make sure SCLH,SCLL not exceed its 16bit value\r
- return;\r
- tem = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE) / clockrate;\r
- I2Cx->SCLH = (uint32_t)(tem / 2);\r
- I2Cx->SCLL = (uint32_t)(tem - I2Cx->SCLH);\r
- /* Set I2C operation to default */\r
- I2Cx->CONCLR = (I2C_I2CONCLR_AAC |I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_I2ENC);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief De-initializes the I2C peripheral registers to their\r
- * default reset values.\r
- * @param[in] I2Cx I2C peripheral selected, should be\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return None\r
- **********************************************************************/\r
-void I2C_DeInit(LPC_I2Cn_Type* I2Cx)\r
-{\r
- CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
-\r
- /* Disable I2C control */\r
- I2Cx->CONCLR = I2C_I2CONCLR_I2ENC;\r
-\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable or disable I2C peripheral's operation\r
- * @param[in] I2Cx I2C peripheral selected, should be\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[in] NewState New State of I2Cx peripheral's operation, should be:\r
- * - ENABLE :enable I2C operation\r
- * - DISABLE :disable I2C operation\r
- * @return none\r
- **********************************************************************/\r
-void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
- CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- I2Cx->CONSET = I2C_I2CONSET_I2EN;\r
- }\r
- else\r
- {\r
- I2Cx->CONCLR = I2C_I2CONCLR_I2ENC;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable interrupt for I2C peripheral\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[in] NewState New State of I2C peripheral interrupt in NVIC core\r
- * should be:\r
- * - ENABLE: enable interrupt for this I2C peripheral\r
- * - DISABLE: disable interrupt for this I2C peripheral\r
- * @return None\r
- **********************************************************************/\r
-void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState)\r
-{\r
- if (NewState)\r
- {\r
- if(I2Cx == LPC_I2C0)\r
- {\r
- NVIC_EnableIRQ(I2C0_IRQn);\r
- }\r
- else if (I2Cx == LPC_I2C1)\r
- {\r
- NVIC_EnableIRQ(I2C1_IRQn);\r
- }\r
- }\r
- else\r
- {\r
- if(I2Cx == LPC_I2C0)\r
- {\r
- NVIC_DisableIRQ(I2C0_IRQn);\r
- }\r
- else if (I2Cx == LPC_I2C1)\r
- {\r
- NVIC_DisableIRQ(I2C1_IRQn);\r
- }\r
- }\r
- return;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief General Master Interrupt handler for I2C peripheral\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return None\r
- **********************************************************************/\r
-void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx)\r
-{\r
- int32_t tmp;\r
- uint8_t returnCode;\r
- I2C_M_SETUP_Type *txrx_setup;\r
-\r
- tmp = I2C_getNum(I2Cx);\r
- txrx_setup = (I2C_M_SETUP_Type *) i2cdat[tmp].txrx_setup;\r
-\r
- returnCode = (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
- // Save current status\r
- txrx_setup->status = returnCode;\r
- // there's no relevant information\r
- if (returnCode == I2C_I2STAT_NO_INF){\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- return;\r
- }\r
-\r
- /* ----------------------------- TRANSMIT PHASE --------------------------*/\r
- if (i2cdat[tmp].dir == 0){\r
- switch (returnCode)\r
- {\r
- /* A start/repeat start condition has been transmitted -------------------*/\r
- case I2C_I2STAT_M_TX_START:\r
- case I2C_I2STAT_M_TX_RESTART:\r
- I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
- /*\r
- * If there's any transmit data, then start to\r
- * send SLA+W right now, otherwise check whether if there's\r
- * any receive data for next state.\r
- */\r
- if ((txrx_setup->tx_data != NULL) && (txrx_setup->tx_length != 0)){\r
- I2Cx->DAT = (txrx_setup->sl_addr7bit << 1);\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- } else {\r
- goto next_stage;\r
- }\r
- break;\r
-\r
- /* SLA+W has been transmitted, ACK has been received ----------------------*/\r
- case I2C_I2STAT_M_TX_SLAW_ACK:\r
- /* Data has been transmitted, ACK has been received */\r
- case I2C_I2STAT_M_TX_DAT_ACK:\r
- /* Send more data */\r
- if ((txrx_setup->tx_count < txrx_setup->tx_length) \\r
- && (txrx_setup->tx_data != NULL)){\r
- I2Cx->DAT = *(uint8_t *)(txrx_setup->tx_data + txrx_setup->tx_count);\r
- txrx_setup->tx_count++;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- }\r
- // no more data, switch to next stage\r
- else {\r
-next_stage:\r
- // change direction\r
- i2cdat[tmp].dir = 1;\r
- // Check if any data to receive\r
- if ((txrx_setup->rx_length != 0) && (txrx_setup->rx_data != NULL)){\r
- // check whether if we need to issue an repeat start\r
- if ((txrx_setup->tx_length != 0) && (txrx_setup->tx_data != NULL)){\r
- // Send out an repeat start command\r
- I2Cx->CONSET = I2C_I2CONSET_STA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC;\r
- }\r
- // Don't need issue an repeat start, just goto send SLA+R\r
- else {\r
- goto send_slar;\r
- }\r
- }\r
- // no more data send, the go to end stage now\r
- else {\r
- // success, goto end stage\r
- txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
- goto end_stage;\r
- }\r
- }\r
- break;\r
-\r
- /* SLA+W has been transmitted, NACK has been received ----------------------*/\r
- case I2C_I2STAT_M_TX_SLAW_NACK:\r
- /* Data has been transmitted, NACK has been received -----------------------*/\r
- case I2C_I2STAT_M_TX_DAT_NACK:\r
- // update status\r
- txrx_setup->status |= I2C_SETUP_STATUS_NOACKF;\r
- goto retry;\r
- /* Arbitration lost in SLA+R/W or Data bytes -------------------------------*/\r
- case I2C_I2STAT_M_TX_ARB_LOST:\r
- // update status\r
- txrx_setup->status |= I2C_SETUP_STATUS_ARBF;\r
- default:\r
- goto retry;\r
- }\r
- }\r
-\r
- /* ----------------------------- RECEIVE PHASE --------------------------*/\r
- else if (i2cdat[tmp].dir == 1){\r
- switch (returnCode){\r
- /* A start/repeat start condition has been transmitted ---------------------*/\r
- case I2C_I2STAT_M_RX_START:\r
- case I2C_I2STAT_M_RX_RESTART:\r
- I2Cx->CONCLR = I2C_I2CONCLR_STAC;\r
- /*\r
- * If there's any receive data, then start to\r
- * send SLA+R right now, otherwise check whether if there's\r
- * any receive data for end of state.\r
- */\r
- if ((txrx_setup->rx_data != NULL) && (txrx_setup->rx_length != 0)){\r
-send_slar:\r
- I2Cx->DAT = (txrx_setup->sl_addr7bit << 1) | 0x01;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- } else {\r
- // Success, goto end stage\r
- txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
- goto end_stage;\r
- }\r
- break;\r
-\r
- /* SLA+R has been transmitted, ACK has been received -----------------*/\r
- case I2C_I2STAT_M_RX_SLAR_ACK:\r
- if (txrx_setup->rx_count < (txrx_setup->rx_length - 1)) {\r
- /*Data will be received, ACK will be return*/\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- }\r
- else {\r
- /*Last data will be received, NACK will be return*/\r
- I2Cx->CONCLR = I2C_I2CONSET_AA;\r
- }\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Data has been received, ACK has been returned ----------------------*/\r
- case I2C_I2STAT_M_RX_DAT_ACK:\r
- // Note save data and increase counter first, then check later\r
- /* Save data */\r
- if ((txrx_setup->rx_data != NULL) && (txrx_setup->rx_count < txrx_setup->rx_length)){\r
- *(uint8_t *)(txrx_setup->rx_data + txrx_setup->rx_count) = (I2Cx->DAT & I2C_I2DAT_BITMASK);\r
- txrx_setup->rx_count++;\r
- }\r
- if (txrx_setup->rx_count < (txrx_setup->rx_length - 1)) {\r
- /*Data will be received, ACK will be return*/\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- }\r
- else {\r
- /*Last data will be received, NACK will be return*/\r
- I2Cx->CONCLR = I2C_I2CONSET_AA;\r
- }\r
-\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Data has been received, NACK has been return -------------------------*/\r
- case I2C_I2STAT_M_RX_DAT_NACK:\r
- /* Save the last data */\r
- if ((txrx_setup->rx_data != NULL) && (txrx_setup->rx_count < txrx_setup->rx_length)){\r
- *(uint8_t *)(txrx_setup->rx_data + txrx_setup->rx_count) = (I2Cx->DAT & I2C_I2DAT_BITMASK);\r
- txrx_setup->rx_count++;\r
- }\r
- // success, go to end stage\r
- txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
- goto end_stage;\r
-\r
- /* SLA+R has been transmitted, NACK has been received ------------------*/\r
- case I2C_I2STAT_M_RX_SLAR_NACK:\r
- // update status\r
- txrx_setup->status |= I2C_SETUP_STATUS_NOACKF;\r
- goto retry;\r
-\r
- /* Arbitration lost ----------------------------------------------------*/\r
- case I2C_I2STAT_M_RX_ARB_LOST:\r
- // update status\r
- txrx_setup->status |= I2C_SETUP_STATUS_ARBF;\r
- default:\r
-retry:\r
- // check if retransmission is available\r
- if (txrx_setup->retransmissions_count < txrx_setup->retransmissions_max){\r
- // Clear tx count\r
- txrx_setup->tx_count = 0;\r
- I2Cx->CONSET = I2C_I2CONSET_STA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC;\r
- txrx_setup->retransmissions_count++;\r
- }\r
- // End of stage\r
- else {\r
-end_stage:\r
- // Disable interrupt\r
- I2C_IntCmd(I2Cx, FALSE);\r
- // Send stop\r
- I2C_Stop(I2Cx);\r
-\r
- I2C_MasterComplete[tmp] = TRUE;\r
- }\r
- break;\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief General Slave Interrupt handler for I2C peripheral\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return None\r
- **********************************************************************/\r
-void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx)\r
-{\r
- int32_t tmp;\r
- uint8_t returnCode;\r
- I2C_S_SETUP_Type *txrx_setup;\r
- uint32_t timeout;\r
-\r
- tmp = I2C_getNum(I2Cx);\r
- txrx_setup = (I2C_S_SETUP_Type *) i2cdat[tmp].txrx_setup;\r
-\r
- returnCode = (I2Cx->STAT & I2C_STAT_CODE_BITMASK);\r
- // Save current status\r
- txrx_setup->status = returnCode;\r
- // there's no relevant information\r
- if (returnCode == I2C_I2STAT_NO_INF){\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- return;\r
- }\r
-\r
-\r
- switch (returnCode)\r
- {\r
-\r
- /* No status information */\r
- case I2C_I2STAT_NO_INF:\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Reading phase -------------------------------------------------------- */\r
- /* Own SLA+R has been received, ACK has been returned */\r
- case I2C_I2STAT_S_RX_SLAW_ACK:\r
- /* General call address has been received, ACK has been returned */\r
- case I2C_I2STAT_S_RX_GENCALL_ACK:\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Previously addressed with own SLA;\r
- * DATA byte has been received;\r
- * ACK has been returned */\r
- case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK:\r
- /* DATA has been received, ACK hasn been return */\r
- case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK:\r
- /*\r
- * All data bytes that over-flow the specified receive\r
- * data length, just ignore them.\r
- */\r
- if ((txrx_setup->rx_count < txrx_setup->rx_length) \\r
- && (txrx_setup->rx_data != NULL)){\r
- *(uint8_t *)(txrx_setup->rx_data + txrx_setup->rx_count) = (uint8_t)I2Cx->DAT;\r
- txrx_setup->rx_count++;\r
- }\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Previously addressed with own SLA;\r
- * DATA byte has been received;\r
- * NOT ACK has been returned */\r
- case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK:\r
- /* DATA has been received, NOT ACK has been returned */\r
- case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK:\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /*\r
- * Note that: Return code only let us know a stop condition mixed\r
- * with a repeat start condition in the same code value.\r
- * So we should provide a time-out. In case this is really a stop\r
- * condition, this will return back after time out condition. Otherwise,\r
- * next session that is slave receive data will be completed.\r
- */\r
-\r
- /* A Stop or a repeat start condition */\r
- case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX:\r
- // Temporally lock the interrupt for timeout condition\r
- I2C_IntCmd(I2Cx, FALSE);\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- // enable time out\r
- timeout = I2C_SLAVE_TIME_OUT;\r
- while(1){\r
- if (I2Cx->CONSET & I2C_I2CONSET_SI){\r
- // re-Enable interrupt\r
- I2C_IntCmd(I2Cx, TRUE);\r
- break;\r
- } else {\r
- timeout--;\r
- if (timeout == 0){\r
- // timeout occur, it's really a stop condition\r
- txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
- goto s_int_end;\r
- }\r
- }\r
- }\r
- break;\r
-\r
- /* Writing phase -------------------------------------------------------- */\r
- /* Own SLA+R has been received, ACK has been returned */\r
- case I2C_I2STAT_S_TX_SLAR_ACK:\r
- /* Data has been transmitted, ACK has been received */\r
- case I2C_I2STAT_S_TX_DAT_ACK:\r
- /*\r
- * All data bytes that over-flow the specified receive\r
- * data length, just ignore them.\r
- */\r
- if ((txrx_setup->tx_count < txrx_setup->tx_length) \\r
- && (txrx_setup->tx_data != NULL)){\r
- I2Cx->DAT = *(uint8_t *) (txrx_setup->tx_data + txrx_setup->tx_count);\r
- txrx_setup->tx_count++;\r
- }\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Data has been transmitted, NACK has been received,\r
- * that means there's no more data to send, exit now */\r
- /*\r
- * Note: Don't wait for stop event since in slave transmit mode,\r
- * since there no proof lets us know when a stop signal has been received\r
- * on slave side.\r
- */\r
- case I2C_I2STAT_S_TX_DAT_NACK:\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- txrx_setup->status |= I2C_SETUP_STATUS_DONE;\r
- goto s_int_end;\r
-\r
- // Other status must be captured\r
- default:\r
-s_int_end:\r
- // Disable interrupt\r
- I2C_IntCmd(I2Cx, FALSE);\r
- I2Cx->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;\r
- I2C_SlaveComplete[tmp] = TRUE;\r
- break;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Transmit and Receive data in master mode\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[in] TransferCfg Pointer to a I2C_M_SETUP_Type structure that\r
- * contains specified information about the configuration\r
- * for master transfer.\r
- * @param[in] Opt a I2C_TRANSFER_OPT_Type type that selected for interrupt\r
- * or polling mode.\r
- * @return Transmit/receive status, should be:\r
- * - SUCCESS\r
- * - ERROR\r
- *\r
- * Note:\r
- * - In case of using I2C to transmit data only, either transmit length set to 0\r
- * or transmit data pointer set to NULL.\r
- * - In case of using I2C to receive data only, either receive length set to 0\r
- * or receive data pointer set to NULL.\r
- * - In case of using I2C to transmit followed by receive data, transmit length,\r
- * transmit data pointer, receive length and receive data pointer should be set\r
- * corresponding.\r
- **********************************************************************/\r
-Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, \\r
- I2C_TRANSFER_OPT_Type Opt)\r
-{\r
- uint8_t *txdat;\r
- uint8_t *rxdat;\r
- uint32_t CodeStatus;\r
- uint8_t tmp;\r
-\r
- // reset all default state\r
- txdat = (uint8_t *) TransferCfg->tx_data;\r
- rxdat = (uint8_t *) TransferCfg->rx_data;\r
- // Reset I2C setup value to default state\r
- TransferCfg->tx_count = 0;\r
- TransferCfg->rx_count = 0;\r
- TransferCfg->status = 0;\r
-\r
- if (Opt == I2C_TRANSFER_POLLING){\r
-\r
- /* First Start condition -------------------------------------------------------------- */\r
- TransferCfg->retransmissions_count = 0;\r
-retry:\r
- // reset all default state\r
- txdat = (uint8_t *) TransferCfg->tx_data;\r
- rxdat = (uint8_t *) TransferCfg->rx_data;\r
- // Reset I2C setup value to default state\r
- TransferCfg->tx_count = 0;\r
- TransferCfg->rx_count = 0;\r
- CodeStatus = 0;\r
-\r
- // Start command\r
- CodeStatus = I2C_Start(I2Cx);\r
- if ((CodeStatus != I2C_I2STAT_M_TX_START) \\r
- && (CodeStatus != I2C_I2STAT_M_TX_RESTART)){\r
- TransferCfg->retransmissions_count++;\r
- if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
- // save status\r
- TransferCfg->status = CodeStatus;\r
- goto error;\r
- } else {\r
- goto retry;\r
- }\r
- }\r
-\r
- /* In case of sending data first --------------------------------------------------- */\r
- if ((TransferCfg->tx_length != 0) && (TransferCfg->tx_data != NULL)){\r
-\r
- /* Send slave address + WR direction bit = 0 ----------------------------------- */\r
- CodeStatus = I2C_SendByte(I2Cx, (TransferCfg->sl_addr7bit << 1));\r
- if (CodeStatus != I2C_I2STAT_M_TX_SLAW_ACK){\r
- TransferCfg->retransmissions_count++;\r
- if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
- // save status\r
- TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF;\r
- goto error;\r
- } else {\r
- goto retry;\r
- }\r
- }\r
-\r
- /* Send a number of data bytes ---------------------------------------- */\r
- while (TransferCfg->tx_count < TransferCfg->tx_length)\r
- {\r
- CodeStatus = I2C_SendByte(I2Cx, *txdat);\r
- if (CodeStatus != I2C_I2STAT_M_TX_DAT_ACK){\r
- TransferCfg->retransmissions_count++;\r
- if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
- // save status\r
- TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF;\r
- goto error;\r
- } else {\r
- goto retry;\r
- }\r
- }\r
-\r
- txdat++;\r
- TransferCfg->tx_count++;\r
- }\r
- }\r
-\r
- /* Second Start condition (Repeat Start) ------------------------------------------- */\r
- if ((TransferCfg->tx_length != 0) && (TransferCfg->tx_data != NULL) \\r
- && (TransferCfg->rx_length != 0) && (TransferCfg->rx_data != NULL)){\r
-\r
- CodeStatus = I2C_Start(I2Cx);\r
- if ((CodeStatus != I2C_I2STAT_M_RX_START) \\r
- && (CodeStatus != I2C_I2STAT_M_RX_RESTART)){\r
- TransferCfg->retransmissions_count++;\r
- if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
- // Update status\r
- TransferCfg->status = CodeStatus;\r
- goto error;\r
- } else {\r
- goto retry;\r
- }\r
- }\r
- }\r
-\r
- /* Then, start reading after sending data -------------------------------------- */\r
- if ((TransferCfg->rx_length != 0) && (TransferCfg->rx_data != NULL)){\r
- /* Send slave address + RD direction bit = 1 ----------------------------------- */\r
-\r
- CodeStatus = I2C_SendByte(I2Cx, ((TransferCfg->sl_addr7bit << 1) | 0x01));\r
- if (CodeStatus != I2C_I2STAT_M_RX_SLAR_ACK){\r
- TransferCfg->retransmissions_count++;\r
- if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
- // update status\r
- TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF;\r
- goto error;\r
- } else {\r
- goto retry;\r
- }\r
- }\r
-\r
- /* Receive a number of data bytes ------------------------------------------------- */\r
- while (TransferCfg->rx_count < TransferCfg->rx_length){\r
-\r
- /*\r
- * Note that: if data length is only one, the master should not\r
- * issue an ACK signal on bus after reading to avoid of next data frame\r
- * on slave side\r
- */\r
- if (TransferCfg->rx_count < (TransferCfg->rx_length - 1)){\r
- // Issue an ACK signal for next data frame\r
- CodeStatus = I2C_GetByte(I2Cx, &tmp, TRUE);\r
- if (CodeStatus != I2C_I2STAT_M_RX_DAT_ACK){\r
- TransferCfg->retransmissions_count++;\r
- if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
- // update status\r
- TransferCfg->status = CodeStatus;\r
- goto error;\r
- } else {\r
- goto retry;\r
- }\r
- }\r
- } else {\r
- // Do not issue an ACK signal\r
- CodeStatus = I2C_GetByte(I2Cx, &tmp, FALSE);\r
- if (CodeStatus != I2C_I2STAT_M_RX_DAT_NACK){\r
- TransferCfg->retransmissions_count++;\r
- if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){\r
- // update status\r
- TransferCfg->status = CodeStatus;\r
- goto error;\r
- } else {\r
- goto retry;\r
- }\r
- }\r
- }\r
- *rxdat++ = tmp;\r
- TransferCfg->rx_count++;\r
- }\r
- }\r
-\r
- /* Send STOP condition ------------------------------------------------- */\r
- I2C_Stop(I2Cx);\r
- return SUCCESS;\r
-\r
-error:\r
- // Send stop condition\r
- I2C_Stop(I2Cx);\r
- return ERROR;\r
- }\r
-\r
- else if (Opt == I2C_TRANSFER_INTERRUPT){\r
- // Setup tx_rx data, callback and interrupt handler\r
- tmp = I2C_getNum(I2Cx);\r
- i2cdat[tmp].txrx_setup = (uint32_t) TransferCfg;\r
- // Set direction phase, write first\r
- i2cdat[tmp].dir = 0;\r
-\r
- /* First Start condition -------------------------------------------------------------- */\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- I2Cx->CONSET = I2C_I2CONSET_STA;\r
- I2C_IntCmd(I2Cx, TRUE);\r
-\r
- return (SUCCESS);\r
- }\r
-\r
- return ERROR;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Receive and Transmit data in slave mode\r
- * @param[in] I2Cx I2C peripheral selected, should be\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[in] TransferCfg Pointer to a I2C_S_SETUP_Type structure that\r
- * contains specified information about the configuration for\r
- * master transfer.\r
- * @param[in] Opt I2C_TRANSFER_OPT_Type type that selected for interrupt\r
- * or polling mode.\r
- * @return Transmit/receive status, could be:\r
- * - SUCCESS\r
- * - ERRRO\r
- *\r
- * Note:\r
- * The mode of slave's operation depends on the command sent from master on\r
- * the I2C bus. If the master send a SLA+W command, this sub-routine will\r
- * use receive data length and receive data pointer. If the master send a SLA+R\r
- * command, this sub-routine will use transmit data length and transmit data\r
- * pointer.\r
- * If the master issue an repeat start command or a stop command, the slave will\r
- * enable an time out condition, during time out condition, if there's no activity\r
- * on I2C bus, the slave will exit, otherwise (i.e. the master send a SLA+R/W),\r
- * the slave then switch to relevant operation mode. The time out should be used\r
- * because the return status code can not show difference from stop and repeat\r
- * start command in slave operation.\r
- * In case of the expected data length from master is greater than data length\r
- * that slave can support:\r
- * - In case of reading operation (from master): slave will return I2C_I2DAT_IDLE_CHAR\r
- * value.\r
- * - In case of writing operation (from master): slave will ignore remain data from master.\r
- **********************************************************************/\r
-Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, \\r
- I2C_TRANSFER_OPT_Type Opt)\r
-{\r
- uint8_t *txdat;\r
- uint8_t *rxdat;\r
- uint32_t CodeStatus;\r
- uint32_t timeout;\r
- int32_t time_en;\r
- int32_t tmp;\r
-\r
- // reset all default state\r
- txdat = (uint8_t *) TransferCfg->tx_data;\r
- rxdat = (uint8_t *) TransferCfg->rx_data;\r
- // Reset I2C setup value to default state\r
- TransferCfg->tx_count = 0;\r
- TransferCfg->rx_count = 0;\r
- TransferCfg->status = 0;\r
-\r
-\r
- // Polling option\r
- if (Opt == I2C_TRANSFER_POLLING){\r
-\r
- /* Set AA bit to ACK command on I2C bus */\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- /* Clear SI bit to be ready ... */\r
- I2Cx->CONCLR = (I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC);\r
-\r
- time_en = 0;\r
- timeout = 0;\r
-\r
- while (1)\r
- {\r
- /* Check SI flag ready */\r
- if (I2Cx->CONSET & I2C_I2CONSET_SI)\r
- {\r
- time_en = 0;\r
-\r
- switch (CodeStatus = (I2Cx->STAT & I2C_STAT_CODE_BITMASK))\r
- {\r
-\r
- /* No status information */\r
- case I2C_I2STAT_NO_INF:\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Reading phase -------------------------------------------------------- */\r
- /* Own SLA+R has been received, ACK has been returned */\r
- case I2C_I2STAT_S_RX_SLAW_ACK:\r
- /* General call address has been received, ACK has been returned */\r
- case I2C_I2STAT_S_RX_GENCALL_ACK:\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Previously addressed with own SLA;\r
- * DATA byte has been received;\r
- * ACK has been returned */\r
- case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK:\r
- /* DATA has been received, ACK hasn been return */\r
- case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK:\r
- /*\r
- * All data bytes that over-flow the specified receive\r
- * data length, just ignore them.\r
- */\r
- if ((TransferCfg->rx_count < TransferCfg->rx_length) \\r
- && (TransferCfg->rx_data != NULL)){\r
- *rxdat++ = (uint8_t)I2Cx->DAT;\r
- TransferCfg->rx_count++;\r
- }\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Previously addressed with own SLA;\r
- * DATA byte has been received;\r
- * NOT ACK has been returned */\r
- case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK:\r
- /* DATA has been received, NOT ACK has been returned */\r
- case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK:\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /*\r
- * Note that: Return code only let us know a stop condition mixed\r
- * with a repeat start condition in the same code value.\r
- * So we should provide a time-out. In case this is really a stop\r
- * condition, this will return back after time out condition. Otherwise,\r
- * next session that is slave receive data will be completed.\r
- */\r
-\r
- /* A Stop or a repeat start condition */\r
- case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX:\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- // enable time out\r
- time_en = 1;\r
- timeout = 0;\r
- break;\r
-\r
- /* Writing phase -------------------------------------------------------- */\r
- /* Own SLA+R has been received, ACK has been returned */\r
- case I2C_I2STAT_S_TX_SLAR_ACK:\r
- /* Data has been transmitted, ACK has been received */\r
- case I2C_I2STAT_S_TX_DAT_ACK:\r
- /*\r
- * All data bytes that over-flow the specified receive\r
- * data length, just ignore them.\r
- */\r
- if ((TransferCfg->tx_count < TransferCfg->tx_length) \\r
- && (TransferCfg->tx_data != NULL)){\r
- I2Cx->DAT = *txdat++;\r
- TransferCfg->tx_count++;\r
- }\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- break;\r
-\r
- /* Data has been transmitted, NACK has been received,\r
- * that means there's no more data to send, exit now */\r
- /*\r
- * Note: Don't wait for stop event since in slave transmit mode,\r
- * since there no proof lets us know when a stop signal has been received\r
- * on slave side.\r
- */\r
- case I2C_I2STAT_S_TX_DAT_NACK:\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- // enable time out\r
- time_en = 1;\r
- timeout = 0;\r
- break;\r
-\r
- // Other status must be captured\r
- default:\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
- goto s_error;\r
- }\r
- } else if (time_en){\r
- if (timeout++ > I2C_SLAVE_TIME_OUT){\r
- // it's really a stop condition, goto end stage\r
- goto s_end_stage;\r
- }\r
- }\r
- }\r
-\r
-s_end_stage:\r
- /* Clear AA bit to disable ACK on I2C bus */\r
- I2Cx->CONCLR = I2C_I2CONCLR_AAC;\r
- // Check if there's no error during operation\r
- // Update status\r
- TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_DONE;\r
- return SUCCESS;\r
-\r
-s_error:\r
- /* Clear AA bit to disable ACK on I2C bus */\r
- I2Cx->CONCLR = I2C_I2CONCLR_AAC;\r
- // Update status\r
- TransferCfg->status = CodeStatus;\r
- return ERROR;\r
- }\r
-\r
- else if (Opt == I2C_TRANSFER_INTERRUPT){\r
- // Setup tx_rx data, callback and interrupt handler\r
- tmp = I2C_getNum(I2Cx);\r
- i2cdat[tmp].txrx_setup = (uint32_t) TransferCfg;\r
- // Set direction phase, read first\r
- i2cdat[tmp].dir = 1;\r
-\r
- // Enable AA\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;\r
- I2C_IntCmd(I2Cx, TRUE);\r
-\r
- return (SUCCESS);\r
- }\r
-\r
- return ERROR;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set Own slave address in I2C peripheral corresponding to\r
- * parameter specified in OwnSlaveAddrConfigStruct.\r
- * @param[in] I2Cx I2C peripheral selected, should be\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[in] OwnSlaveAddrConfigStruct Pointer to a I2C_OWNSLAVEADDR_CFG_Type\r
- * structure that contains the configuration information for the\r
- * specified I2C slave address.\r
- * @return None\r
- **********************************************************************/\r
-void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct)\r
-{\r
- uint32_t tmp;\r
- CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
- CHECK_PARAM(PARAM_I2C_SLAVEADDR_CH(OwnSlaveAddrConfigStruct->SlaveAddrChannel));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(OwnSlaveAddrConfigStruct->GeneralCallState));\r
-\r
- tmp = (((uint32_t)(OwnSlaveAddrConfigStruct->SlaveAddr_7bit << 1)) \\r
- | ((OwnSlaveAddrConfigStruct->GeneralCallState == ENABLE) ? 0x01 : 0x00))& I2C_I2ADR_BITMASK;\r
- switch (OwnSlaveAddrConfigStruct->SlaveAddrChannel)\r
- {\r
- case 0:\r
- I2Cx->ADR0 = tmp;\r
- I2Cx->MASK[0] = I2C_I2MASK_MASK((uint32_t) \\r
- (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));\r
- break;\r
- case 1:\r
- I2Cx->ADR1 = tmp;\r
- I2Cx->MASK[1] = I2C_I2MASK_MASK((uint32_t) \\r
- (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));\r
- break;\r
- case 2:\r
- I2Cx->ADR2 = tmp;\r
- I2Cx->MASK[2] = I2C_I2MASK_MASK((uint32_t) \\r
- (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));\r
- break;\r
- case 3:\r
- I2Cx->ADR3 = tmp;\r
- I2Cx->MASK[3] = I2C_I2MASK_MASK((uint32_t) \\r
- (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));\r
- break;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configures functionality in I2C monitor mode\r
- * @param[in] I2Cx I2C peripheral selected, should be\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[in] MonitorCfgType Monitor Configuration type, should be:\r
- * - I2C_MONITOR_CFG_SCL_OUTPUT :I2C module can 'stretch'\r
- * the clock line (hold it low) until it has had time to respond\r
- * to an I2C interrupt.\r
- * - I2C_MONITOR_CFG_MATCHALL :When this bit is set to '1'\r
- * and the I2C is in monitor mode, an interrupt will be generated\r
- * on ANY address received.\r
- * @param[in] NewState New State of this function, should be:\r
- * - ENABLE :Enable this function.\r
- * - DISABLE :Disable this function.\r
- * @return None\r
- **********************************************************************/\r
-void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
- CHECK_PARAM(PARAM_I2C_MONITOR_CFG(MonitorCfgType));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- I2Cx->MMCTRL |= MonitorCfgType;\r
- }\r
- else\r
- {\r
- I2Cx->MMCTRL &= (~MonitorCfgType) & I2C_I2MMCTRL_BITMASK;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable I2C monitor mode\r
- * @param[in] I2Cx I2C peripheral selected, should be\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @param[in] NewState New State of this function, should be:\r
- * - ENABLE :Enable monitor mode.\r
- * - DISABLE :Disable monitor mode.\r
- * @return None\r
- **********************************************************************/\r
-void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- I2Cx->MMCTRL |= I2C_I2MMCTRL_MM_ENA;\r
- I2Cx->CONSET = I2C_I2CONSET_AA;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;\r
- }\r
- else\r
- {\r
- I2Cx->MMCTRL &= (~I2C_I2MMCTRL_MM_ENA) & I2C_I2MMCTRL_BITMASK;\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_AAC;\r
- }\r
- I2C_MonitorBufferIndex = 0;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get data from I2C data buffer in monitor mode.\r
- * @param[in] I2Cx I2C peripheral selected, should be\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return None\r
- * Note: In monitor mode, the I2C module may lose the ability to stretch\r
- * the clock (stall the bus) if the ENA_SCL bit is not set. This means that\r
- * the processor will have a limited amount of time to read the contents of\r
- * the data received on the bus. If the processor reads the I2DAT shift\r
- * register, as it ordinarily would, it could have only one bit-time to\r
- * respond to the interrupt before the received data is overwritten by\r
- * new data.\r
- **********************************************************************/\r
-uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx)\r
-{\r
- CHECK_PARAM(PARAM_I2Cx(I2Cx));\r
- return ((uint8_t)(I2Cx->DATA_BUFFER));\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get data from I2C data buffer in monitor mode.\r
- * @param[in] I2Cx I2C peripheral selected, should be\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return None\r
- * Note: In monitor mode, the I2C module may lose the ability to stretch\r
- * the clock (stall the bus) if the ENA_SCL bit is not set. This means that\r
- * the processor will have a limited amount of time to read the contents of\r
- * the data received on the bus. If the processor reads the I2DAT shift\r
- * register, as it ordinarily would, it could have only one bit-time to\r
- * respond to the interrupt before the received data is overwritten by\r
- * new data.\r
- **********************************************************************/\r
-BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size)\r
-{\r
- BOOL_8 ret=FALSE;\r
-\r
- I2Cx->CONCLR = I2C_I2CONCLR_SIC;\r
-\r
- buffer[I2C_MonitorBufferIndex] = (uint8_t)(I2Cx->DATA_BUFFER);\r
- I2C_MonitorBufferIndex++;\r
- if(I2C_MonitorBufferIndex >= size)\r
- {\r
- ret = TRUE;\r
- }\r
- return ret;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get status of Master Transfer\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return Master transfer status, could be:\r
- * - TRUE :master transfer completed\r
- * - FALSE :master transfer have not completed yet\r
- **********************************************************************/\r
-uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx)\r
-{\r
- uint32_t retval, tmp;\r
- tmp = I2C_getNum(I2Cx);\r
- retval = I2C_MasterComplete[tmp];\r
- I2C_MasterComplete[tmp] = FALSE;\r
- return retval;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get status of Slave Transfer\r
- * @param[in] I2Cx I2C peripheral selected, should be:\r
- * - LPC_I2C0 :I2C0 peripheral\r
- * - LPC_I2C1 :I2C1 peripheral\r
- * @return Complete status, could be: TRUE/FALSE\r
- **********************************************************************/\r
-uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx)\r
-{\r
- uint32_t retval, tmp;\r
- tmp = I2C_getNum(I2Cx);\r
- retval = I2C_SlaveComplete[tmp];\r
- I2C_SlaveComplete[tmp] = FALSE;\r
- return retval;\r
-}\r
-\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _I2C */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_i2s.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_i2s.c\r
-* @brief Contains all functions support for I2S firmware library\r
-* on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup I2S\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_i2s.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _I2S\r
-\r
-/* Private Functions ---------------------------------------------------------- */\r
-\r
-static uint8_t i2s_GetWordWidth(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);\r
-static uint8_t i2s_GetChannel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);\r
-\r
-/********************************************************************//**\r
- * @brief Get I2S wordwidth value\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode is the I2S mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return The wordwidth value, should be: 8,16 or 32\r
- *********************************************************************/\r
-static uint8_t i2s_GetWordWidth(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {\r
- uint8_t value;\r
-\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if (TRMode == I2S_TX_MODE) {\r
- value = (I2Sx->DAO) & 0x03; /* get wordwidth bit */\r
- } else {\r
- value = (I2Sx->DAI) & 0x03; /* get wordwidth bit */\r
- }\r
- switch (value) {\r
- case I2S_WORDWIDTH_8:\r
- return 8;\r
- case I2S_WORDWIDTH_16:\r
- return 16;\r
- default:\r
- return 32;\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Get I2S channel value\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode is the I2S mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return The channel value, should be: 1(mono) or 2(stereo)\r
- *********************************************************************/\r
-static uint8_t i2s_GetChannel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {\r
- uint8_t value;\r
-\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if (TRMode == I2S_TX_MODE) {\r
- value = (I2Sx->DAO) & 0x04; /* get bit[2] */\r
- } else {\r
- value = (I2Sx->DAI) & 0x04; /* get bit[2] */\r
- }\r
- value >>= 2;\r
- if(value == I2S_MONO) return 1;\r
- return 2;\r
-}\r
-\r
-/* End of Private Functions --------------------------------------------------- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup I2S_Public_Functions\r
- * @{\r
- */\r
-\r
-/********************************************************************//**\r
- * @brief Initialize I2S\r
- * - Turn on power and clock\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @return none\r
- *********************************************************************/\r
-void I2S_Init(LPC_I2Sn_Type *I2Sx) {\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
-\r
- // Turn on power and clock\r
- //CGU_ConfigPPWR(CGU_PCONP_PCI2S, ENABLE);\r
- I2Sx->DAI = I2Sx->DAO = 0x00;\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Configuration I2S, setting:\r
- * - master/slave mode\r
- * - wordwidth value\r
- * - channel mode\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @param[in] ConfigStruct pointer to I2S_CFG_Type structure\r
- * which will be initialized.\r
- * @return none\r
- *********************************************************************/\r
-void I2S_Config(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct)\r
-{\r
- uint32_t bps, config;\r
-\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
-\r
- CHECK_PARAM(PARAM_I2S_WORDWIDTH(ConfigStruct->wordwidth));\r
- CHECK_PARAM(PARAM_I2S_CHANNEL(ConfigStruct->mono));\r
- CHECK_PARAM(PARAM_I2S_STOP(ConfigStruct->stop));\r
- CHECK_PARAM(PARAM_I2S_RESET(ConfigStruct->reset));\r
- CHECK_PARAM(PARAM_I2S_WS_SEL(ConfigStruct->ws_sel));\r
- CHECK_PARAM(PARAM_I2S_MUTE(ConfigStruct->mute));\r
-\r
- /* Setup clock */\r
- bps = (ConfigStruct->wordwidth +1)*8;\r
-\r
- /* Calculate audio config */\r
- config = (bps - 1)<<6 | (ConfigStruct->ws_sel)<<5 | (ConfigStruct->reset)<<4 |\r
- (ConfigStruct->stop)<<3 | (ConfigStruct->mono)<<2 | (ConfigStruct->wordwidth);\r
-\r
- if(TRMode == I2S_RX_MODE){\r
- I2Sx->DAI = config;\r
- }else{\r
- I2Sx->DAO = config;\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief DeInitial both I2S transmit or receive\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @return none\r
- *********************************************************************/\r
-void I2S_DeInit(LPC_I2Sn_Type *I2Sx) {\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
-\r
- // Turn off power and clock\r
- //CGU_ConfigPPWR(CGU_PCONP_PCI2S, DISABLE);\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Get I2S Buffer Level\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode Transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return current level of Transmit/Receive Buffer\r
- *********************************************************************/\r
-uint8_t I2S_GetLevel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode)\r
-{\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if(TRMode == I2S_TX_MODE)\r
- {\r
- return ((I2Sx->STATE >> 16) & 0xFF);\r
- }\r
- else\r
- {\r
- return ((I2Sx->STATE >> 8) & 0xFF);\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief I2S Start: clear all STOP,RESET and MUTE bit, ready to operate\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @return none\r
- *********************************************************************/\r
-void I2S_Start(LPC_I2Sn_Type *I2Sx)\r
-{\r
- //Clear STOP,RESET and MUTE bit\r
- I2Sx->DAO &= ~I2S_DAI_RESET;\r
- I2Sx->DAI &= ~I2S_DAI_RESET;\r
- I2Sx->DAO &= ~I2S_DAI_STOP;\r
- I2Sx->DAI &= ~I2S_DAI_STOP;\r
- I2Sx->DAO &= ~I2S_DAI_MUTE;\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief I2S Send data\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] BufferData pointer to uint32_t is the data will be send\r
- * @return none\r
- *********************************************************************/\r
-void I2S_Send(LPC_I2Sn_Type *I2Sx, uint32_t BufferData) {\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
-\r
- I2Sx->TXFIFO = BufferData;\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief I2S Receive Data\r
- * @param[in] I2Sx pointer to LPC_I2Sn_Type, should be: LPC_I2S\r
- * @return received value\r
- *********************************************************************/\r
-uint32_t I2S_Receive(LPC_I2Sn_Type* I2Sx) {\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
-\r
- return (I2Sx->RXFIFO);\r
-\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief I2S Pause\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return none\r
- *********************************************************************/\r
-void I2S_Pause(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if (TRMode == I2S_TX_MODE) //Transmit mode\r
- {\r
- I2Sx->DAO |= I2S_DAO_STOP;\r
- } else //Receive mode\r
- {\r
- I2Sx->DAI |= I2S_DAI_STOP;\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief I2S Mute\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return none\r
- *********************************************************************/\r
-void I2S_Mute(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if (TRMode == I2S_TX_MODE) //Transmit mode\r
- {\r
- I2Sx->DAO |= I2S_DAO_MUTE;\r
- } else //Receive mode\r
- {\r
- I2Sx->DAI |= I2S_DAI_MUTE;\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief I2S Stop\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return none\r
- *********************************************************************/\r
-void I2S_Stop(LPC_I2Sn_Type *I2Sx, uint8_t TRMode) {\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if (TRMode == I2S_TX_MODE) //Transmit mode\r
- {\r
- I2Sx->DAO &= ~I2S_DAO_MUTE;\r
- I2Sx->DAO |= I2S_DAO_STOP;\r
- I2Sx->DAO |= I2S_DAO_RESET;\r
- } else //Receive mode\r
- {\r
- I2Sx->DAI |= I2S_DAI_STOP;\r
- I2Sx->DAI |= I2S_DAI_RESET;\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Set frequency for I2S\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] Freq is the frequency for I2S will be set. It can range\r
- * from 16-96 kHz(16, 22.05, 32, 44.1, 48, 96kHz)\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return Status: ERROR or SUCCESS\r
- *********************************************************************/\r
-Status I2S_FreqConfig(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode) {\r
-\r
- /* Calculate bit rate\r
- * The formula is:\r
- * bit_rate = channel*wordwidth - 1\r
- * 48kHz sample rate for 16 bit stereo date requires\r
- * a bit rate of 48000*16*2=1536MHz (MCLK)\r
- */\r
- uint32_t i2sPclk;\r
- uint64_t divider;\r
- uint8_t bitrate, channel, wordwidth;\r
- uint32_t x, y;\r
- uint16_t dif;\r
- uint16_t error;\r
- uint16_t x_divide, y_divide;\r
- uint16_t ErrorOptimal = 0xFFFF;\r
- uint32_t N;\r
-\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PRAM_I2S_FREQ(Freq));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- //LPC_CGU->BASE_VPB1_CLK = 0x08<<24 | AUTO_BLOCK;\r
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB1);\r
- i2sPclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_I2S);\r
- if(TRMode == I2S_TX_MODE)\r
- {\r
- channel = i2s_GetChannel(I2Sx,I2S_TX_MODE);\r
- wordwidth = i2s_GetWordWidth(I2Sx,I2S_TX_MODE);\r
- }\r
- else\r
- {\r
- channel = i2s_GetChannel(I2Sx,I2S_RX_MODE);\r
- wordwidth = i2s_GetWordWidth(I2Sx,I2S_RX_MODE);\r
- }\r
- bitrate = 2 * wordwidth - 1;\r
-\r
- /* Calculate X and Y divider\r
- * The MCLK rate for the I2S transmitter is determined by the value\r
- * in the I2STXRATE/I2SRXRATE register. The required I2STXRATE/I2SRXRATE\r
- * setting depends on the desired audio sample rate desired, the format\r
- * (stereo/mono) used, and the data size.\r
- * The formula is:\r
- * I2S_MCLK = PCLK * (X/Y) / 2\r
- * We have:\r
- * I2S_MCLK = Freq * bit_rate * I2Sx->TXBITRATE;\r
- * So: (X/Y) = (Freq * bit_rate * I2Sx->TXBITRATE)/PCLK*2\r
- * We use a loop function to chose the most suitable X,Y value\r
- */\r
-\r
- /* divider is a fixed point number with 16 fractional bits */\r
- divider = ((uint64_t)(Freq *( bitrate+1) * 2)<<16) / i2sPclk;\r
-\r
- /* find N that make x/y <= 1 -> divider <= 2^16 */\r
- for(N=64;N>=0;N--){\r
- if((divider*N) < (1<<16)) break;\r
- }\r
-\r
- if(N == 0) return ERROR;\r
-\r
- divider *= N;\r
-\r
- for (y = 255; y > 0; y--) {\r
- x = y * divider;\r
- if(x & (0xFF000000)) continue;\r
- dif = x & 0xFFFF;\r
- if(dif>0x8000) error = 0x10000-dif;\r
- else error = dif;\r
- if (error == 0)\r
- {\r
- y_divide = y;\r
- break;\r
- }\r
- else if (error < ErrorOptimal)\r
- {\r
- ErrorOptimal = error;\r
- y_divide = y;\r
- }\r
- }\r
- x_divide = ((uint64_t)y_divide * Freq *( bitrate+1)* N * 2)/i2sPclk;\r
- if(x_divide >= 256) x_divide = 0xFF;\r
- if(x_divide == 0) x_divide = 1;\r
- if (TRMode == I2S_TX_MODE)// Transmitter\r
- {\r
- I2Sx->TXBITRATE = N;\r
- I2Sx->TXRATE = y_divide | (x_divide << 8);\r
- } else //Receiver\r
- {\r
- I2Sx->RXBITRATE = N;\r
- I2Sx->RXRATE = y_divide | (x_divide << 8);\r
- }\r
- return SUCCESS;\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief I2S set bitrate\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] bitrate value will be set, it can be calculate as follows:\r
- * bitrate = channel * wordwidth - 1\r
- * bitrate value should be in range: 0 .. 63\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return none\r
- *********************************************************************/\r
-void I2S_SetBitRate(LPC_I2Sn_Type *I2Sx, uint8_t bitrate, uint8_t TRMode)\r
-{\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_BITRATE(bitrate));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if(TRMode == I2S_TX_MODE)\r
- {\r
- I2Sx->TXBITRATE = bitrate;\r
- }\r
- else\r
- {\r
- I2Sx->RXBITRATE = bitrate;\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Configuration operating mode for I2S\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] ModeConfig pointer to I2S_MODEConf_Type will be used to\r
- * configure\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return none\r
- *********************************************************************/\r
-void I2S_ModeConfig(LPC_I2Sn_Type *I2Sx, I2S_MODEConf_Type* ModeConfig,\r
- uint8_t TRMode)\r
-{\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_CLKSEL(ModeConfig->clksel));\r
- CHECK_PARAM(PARAM_I2S_4PIN(ModeConfig->fpin));\r
- CHECK_PARAM(PARAM_I2S_MCLK(ModeConfig->mcena));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if (TRMode == I2S_TX_MODE) {\r
- I2Sx->TXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register\r
- if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {\r
- I2Sx->TXMODE |= 0x02;\r
- }\r
- if (ModeConfig->fpin == I2S_4PIN_ENABLE) {\r
- I2Sx->TXMODE |= (1 << 2);\r
- }\r
- if (ModeConfig->mcena == I2S_MCLK_ENABLE) {\r
- I2Sx->TXMODE |= (1 << 3);\r
- }\r
- } else {\r
- I2Sx->RXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register\r
- if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {\r
- I2Sx->RXMODE |= 0x02;\r
- }\r
- if (ModeConfig->fpin == I2S_4PIN_ENABLE) {\r
- I2Sx->RXMODE |= (1 << 2);\r
- }\r
- if (ModeConfig->mcena == I2S_MCLK_ENABLE) {\r
- I2Sx->RXMODE |= (1 << 3);\r
- }\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Configure DMA operation for I2S\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] DMAConfig pointer to I2S_DMAConf_Type will be used to configure\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return none\r
- *********************************************************************/\r
-void I2S_DMAConfig(LPC_I2Sn_Type *I2Sx, I2S_DMAConf_Type* DMAConfig,\r
- uint8_t TRMode)\r
-{\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_DMA(DMAConfig->DMAIndex));\r
- CHECK_PARAM(PARAM_I2S_DMA_DEPTH(DMAConfig->depth));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if (TRMode == I2S_RX_MODE) {\r
- if (DMAConfig->DMAIndex == I2S_DMA_1) {\r
- I2Sx->DMA1 = (DMAConfig->depth) << 8;\r
- } else {\r
- I2Sx->DMA2 = (DMAConfig->depth) << 8;\r
- }\r
- } else {\r
- if (DMAConfig->DMAIndex == I2S_DMA_1) {\r
- I2Sx->DMA1 = (DMAConfig->depth) << 16;\r
- } else {\r
- I2Sx->DMA2 = (DMAConfig->depth) << 16;\r
- }\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Enable/Disable DMA operation for I2S\r
- * @param[in] I2Sx: I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] DMAIndex chose what DMA is used, should be:\r
- * - I2S_DMA_1 = 0 :DMA1\r
- * - I2S_DMA_2 = 1 :DMA2\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @param[in] NewState is new state of DMA operation, should be:\r
- * - ENABLE\r
- * - DISABLE\r
- * @return none\r
- *********************************************************************/\r
-void I2S_DMACmd(LPC_I2Sn_Type *I2Sx, uint8_t DMAIndex, uint8_t TRMode,\r
- FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
- CHECK_PARAM(PARAM_I2S_DMA(DMAIndex));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
-\r
- if (TRMode == I2S_RX_MODE) {\r
- if (DMAIndex == I2S_DMA_1) {\r
- if (NewState == ENABLE)\r
- I2Sx->DMA1 |= 0x01;\r
- else\r
- I2Sx->DMA1 &= ~0x01;\r
- } else {\r
- if (NewState == ENABLE)\r
- I2Sx->DMA2 |= 0x01;\r
- else\r
- I2Sx->DMA2 &= ~0x01;\r
- }\r
- } else {\r
- if (DMAIndex == I2S_DMA_1) {\r
- if (NewState == ENABLE)\r
- I2Sx->DMA1 |= 0x02;\r
- else\r
- I2Sx->DMA1 &= ~0x02;\r
- } else {\r
- if (NewState == ENABLE)\r
- I2Sx->DMA2 |= 0x02;\r
- else\r
- I2Sx->DMA2 &= ~0x02;\r
- }\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Configure IRQ for I2S\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @param[in] level is the FIFO level that triggers IRQ request\r
- * @return none\r
- *********************************************************************/\r
-void I2S_IRQConfig(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, uint8_t level) {\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_I2S_TRX(TRMode));\r
- CHECK_PARAM(PARAM_I2S_IRQ_LEVEL(level));\r
-\r
- if (TRMode == I2S_RX_MODE) {\r
- I2Sx->IRQ |= (level << 8);\r
- } else {\r
- I2Sx->IRQ |= (level << 16);\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Enable/Disable IRQ for I2S\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @param[in] NewState is new state of DMA operation, should be:\r
- * - ENABLE\r
- * - DISABLE\r
- * @return none\r
- *********************************************************************/\r
-void I2S_IRQCmd(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, FunctionalState NewState) {\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (TRMode == I2S_RX_MODE) {\r
- if (NewState == ENABLE)\r
- I2Sx->IRQ |= 0x01;\r
- else\r
- I2Sx->IRQ &= ~0x01;\r
- //Enable DMA\r
-\r
- } else {\r
- if (NewState == ENABLE)\r
- I2Sx->IRQ |= 0x02;\r
- else\r
- I2Sx->IRQ &= ~0x02;\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Get I2S interrupt status\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return FunctionState should be:\r
- * - ENABLE :interrupt is enable\r
- * - DISABLE :interrupt is disable\r
- *********************************************************************/\r
-FunctionalState I2S_GetIRQStatus(LPC_I2Sn_Type *I2Sx,uint8_t TRMode)\r
-{\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- if(TRMode == I2S_TX_MODE)\r
- return (FunctionalState)((I2Sx->IRQ >> 1)&0x01);\r
- else\r
- return (FunctionalState)((I2Sx->IRQ)&0x01);\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Get I2S interrupt depth\r
- * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S\r
- * @param[in] TRMode is transmit/receive mode, should be:\r
- * - I2S_TX_MODE = 0 :transmit mode\r
- * - I2S_RX_MODE = 1 :receive mode\r
- * @return depth of FIFO level on which to create an irq request\r
- *********************************************************************/\r
-uint8_t I2S_GetIRQDepth(LPC_I2Sn_Type *I2Sx,uint8_t TRMode)\r
-{\r
- CHECK_PARAM(PARAM_I2Sx(I2Sx));\r
- if(TRMode == I2S_TX_MODE)\r
- return (((I2Sx->IRQ)>>16)&0xFF);\r
- else\r
- return (((I2Sx->IRQ)>>8)&0xFF);\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _I2S */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_lcd.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_lcd.c\r
-* @brief Contains all function support for LCD Driver\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup LCD\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h"\r
-#include "lpc18xx_lcd.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-#ifdef _LCD\r
-\r
-LCD_CURSOR_SIZE_OPT LCD_Cursor_Size = LCD_CURSOR_64x64;\r
-\r
-/* Private Functions ---------------------------------------------------------- */\r
-\r
-/*********************************************************************//**\r
- * @brief Init the LPC18xx LCD Controller\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] LCD_ConfigStruct point to LCD_CFG_Type that describe the LCD Panel\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Init(LPC_LCD_Type *LCDx, LCD_CFG_Type *LCD_ConfigStruct){\r
- uint32_t i, regValue, *pPal;\r
- uint32_t pcd;\r
- /* disable the display */\r
- LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE;\r
-\r
- /* Setting LCD_TIMH register */\r
- regValue= ( ((((LCD_ConfigStruct->screen_width/16)-1)&0x3F) << 2)\r
- | (( (LCD_ConfigStruct->HSync_pulse_width-1) &0xFF) << 8)\r
- | (( (LCD_ConfigStruct->horizontal_porch.front-1) &0xFF) << 16)\r
- | (( (LCD_ConfigStruct->horizontal_porch.back-1) &0xFF) << 24) );\r
-\r
- LCDx->TIMH = regValue;\r
-\r
- /* Setting LCD_TIMV register */\r
- regValue =((((LCD_ConfigStruct->screen_height-1) &0x3FF) << 0)\r
- | (((LCD_ConfigStruct->VSync_pulse_width-1) &0x03F) << 10)\r
- | (((LCD_ConfigStruct->vertical_porch.front-1) &0x0FF) << 16)\r
- | (((LCD_ConfigStruct->vertical_porch.back-1) &0x0FF) << 24) );\r
-\r
- LCDx->TIMV = regValue;\r
-\r
- /* Generate the clock and signal polarity control word */\r
- regValue = 0;\r
- regValue = (((LCD_ConfigStruct->ac_bias_frequency-1) & 0x1F) << 6);\r
-\r
- regValue |= (LCD_ConfigStruct->OE_pol & 1)<< 14;\r
-\r
- regValue |= (LCD_ConfigStruct->panel_clk_edge & 1)<< 13;\r
-\r
- regValue |= (LCD_ConfigStruct->HSync_pol & 1)<< 12;\r
-\r
- regValue |= (LCD_ConfigStruct->VSync_pol & 1)<< 11;\r
-\r
- /* Compute clocks per line based on panel type */\r
-\r
- switch(LCD_ConfigStruct->lcd_panel_type)\r
- {\r
- case LCD_MONO_4:\r
- regValue |= ((((LCD_ConfigStruct->screen_width / 4)-1) & 0x3FF) << 16);\r
- break;\r
- case LCD_MONO_8:\r
- regValue |= ((((LCD_ConfigStruct->screen_width / 8)-1) & 0x3FF) << 16);\r
- break;\r
- case LCD_CSTN:\r
- regValue |= (((((LCD_ConfigStruct->screen_width * 3)/8)-1) & 0x3FF) << 16);\r
- break;\r
- case LCD_TFT:\r
- default:\r
- regValue |= 1<<26 | (((LCD_ConfigStruct->screen_width-1) & 0x3FF) << 16);\r
- }\r
-\r
- /* panel clock divisor */\r
- pcd = LCD_ConfigStruct->pcd; // TODO: should be calculated from LCDDCLK\r
- pcd &= 0x3FF;\r
- regValue |= ((pcd>>5)<<27) | ((pcd)&0x1F);\r
-\r
- LCDx->POL = regValue;\r
-\r
- /* configure line end control */\r
- CHECK_PARAM(LCD_ConfigStruct->line_end_delay<=(1<<7));\r
- if(LCD_ConfigStruct->line_end_delay)\r
- LCDx->LE = (LCD_ConfigStruct->line_end_delay-1) | 1<<16;\r
- else\r
- LCDx->LE = 0;\r
-\r
- /* disable interrupts */\r
- LCDx->INTMSK = 0;\r
-\r
- /* set bits per pixel */\r
- regValue = LCD_ConfigStruct->bits_per_pixel << 1;\r
-\r
- /* set color format BGR or RGB */\r
- regValue |= LCD_ConfigStruct->color_format << 8;\r
-\r
- regValue |= LCD_ConfigStruct->lcd_panel_type << 4;\r
-\r
- if(LCD_ConfigStruct->dual_panel == 1)\r
- {\r
- regValue |= 1 << 7;\r
- }\r
- LCDx->CTRL = regValue;\r
- /* clear palette */\r
- pPal = (uint32_t*) (&(LCDx->PAL));\r
-\r
- for(i = 0; i < 128; i++)\r
- {\r
- *pPal = 0;\r
- pPal++;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Deinit LCD controller\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @return None\r
- **********************************************************************/\r
-void LCD_DeInit(LPC_LCD_Type *LCDx);\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Power the LCD Panel\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] OnOff Turn on/off LCD\r
- * - TRUE :Turn on\r
- * - FALSE :Turn off\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Power(LPC_LCD_Type *LCDx, FunctionalState OnOff){\r
-int i;\r
- if(OnOff){\r
- LPC_LCD->CTRL |= CLCDC_LCDCTRL_PWR;\r
- for(i=0;i<100000;i++);\r
- LPC_LCD->CTRL |= CLCDC_LCDCTRL_ENABLE;\r
- }else{\r
- LPC_LCD->CTRL &= ~CLCDC_LCDCTRL_PWR;\r
- for(i=0;i<100000;i++);\r
- LPC_LCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable the LCD Controller\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] EnDis Enable/disable status\r
- * - TRUE :Enable\r
- * - FALSE :Disable\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Enable(LPC_LCD_Type *LCDx, FunctionalState EnDis){\r
- if (EnDis)\r
- {\r
- LCDx->CTRL |= CLCDC_LCDCTRL_ENABLE;\r
- }\r
- else\r
- {\r
- LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set LCD Frame Buffer for Single Panel or Upper Panel Frame\r
- * Buffer for Dual Panel\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] buffer address of buffer\r
- * @return None\r
- **********************************************************************/\r
-void LCD_SetFrameBuffer(LPC_LCD_Type *LCDx, void* buffer){\r
- LCDx->UPBASE = (uint32_t)buffer;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set LCD Lower Panel Frame Buffer for Dual Panel\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] buffer address of buffer\r
- * @return None\r
- **********************************************************************/\r
-void LCD_SetLPFrameBuffer(LPC_LCD_Type *LCDx, void* buffer){\r
- LCDx->LPBASE = (uint32_t)buffer;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configure Cursor\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] cursor_size specify size of cursor\r
- * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels\r
- * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels\r
- * @param[in] sync cursor sync mode\r
- * - TRUE :cursor sync to the frame sync pulse\r
- * - FALSE :cursor async mode\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Cursor_Config(LPC_LCD_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, Bool sync){\r
- LCD_Cursor_Size = cursor_size;\r
- LCDx->CRSR_CFG = ((sync?1:0)<<1) | cursor_size;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Write Cursor Image into Internal Cursor Image Buffer\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] cursor_num specify number of cursor is going to be written\r
- * this param must < 4\r
- * @param[in] Image point to Cursor Image Buffer\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Cursor_WriteImage(LPC_LCD_Type *LCDx, uint8_t cursor_num, void* Image){\r
- int i,j;\r
- uint8_t *fifoptr, *crsr_ptr = (uint8_t *)Image;\r
-\r
- CHECK_PARAM(cursor_num<4);\r
- /* Check if Cursor Size was configured as 32x32 or 64x64*/\r
- if(LCD_Cursor_Size == LCD_CURSOR_32x32){\r
- i = cursor_num * 256;\r
- j = i + 256;\r
- }else{\r
- i = 0;\r
- j = 1024;\r
- }\r
- fifoptr = (uint8_t*)&(LCDx->CRSR_IMG[0]);\r
- /* Copy Cursor Image content to FIFO */\r
- for(; i < j; i++)\r
- {\r
- fifoptr[i] = *(uint8_t *)crsr_ptr;\r
- crsr_ptr++;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get Internal Cursor Image Buffer Address\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] cursor_num specify number of cursor is going to be written\r
- * this param must < 4\r
- * @return Cursor Image Buffer Address\r
- **********************************************************************/\r
-void* LCD_Cursor_GetImageBufferAddress(LPC_LCD_Type *LCDx, uint8_t cursor_num){\r
- CHECK_PARAM(cursor_num<4);\r
- return (void*)&(LCDx->CRSR_IMG[cursor_num*64]);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable Cursor\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] cursor_num specify number of cursor is going to be written\r
- * this param must < 4\r
- * @param[in] OnOff Turn on/off LCD\r
- * - TRUE :Enable\r
- * - FALSE :Disable\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Cursor_Enable(LPC_LCD_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff){\r
- CHECK_PARAM(cursor_num<4);\r
- if (OnOff)\r
- {\r
- LCDx->CRSR_CTRL = (cursor_num<<4) | 1;\r
- }\r
- else\r
- {\r
- LCDx->CRSR_CTRL = (cursor_num<<4);\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Load LCD Palette\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] palette point to palette address\r
- * @return None\r
- **********************************************************************/\r
-void LCD_LoadPalette(LPC_LCD_Type *LCDx, void* palette){\r
- LCD_PALETTE_ENTRY_Type pal_entry, *ptr_pal_entry;\r
- uint8_t i, *pal_ptr;\r
- /* This function supports loading of the color palette from\r
- the C file generated by the bmp2c utility. It expects the\r
- palette to be passed as an array of 32-bit BGR entries having\r
- the following format:\r
- 2:0 - Not used\r
- 7:3 - Blue\r
- 10:8 - Not used\r
- 15:11 - Green\r
- 18:16 - Not used\r
- 23:19 - Red\r
- 31:24 - Not used\r
- arg = pointer to input palette table address */\r
- ptr_pal_entry = &pal_entry;\r
- pal_ptr = (uint8_t *) palette;\r
-\r
- /* 256 entry in the palette table */\r
- for(i = 0; i < 256/2; i++)\r
- {\r
- pal_entry.Bl = (*pal_ptr++) >> 3; /* blue first */\r
- pal_entry.Gl = (*pal_ptr++) >> 3; /* get green */\r
- pal_entry.Rl = (*pal_ptr++) >> 3; /* get red */\r
- pal_ptr++; /* skip over the unused byte */\r
- /* do the most significant halfword of the palette */\r
- pal_entry.Bu = (*pal_ptr++) >> 3; /* blue first */\r
- pal_entry.Gu = (*pal_ptr++) >> 3; /* get green */\r
- pal_entry.Ru = (*pal_ptr++) >> 3; /* get red */\r
- pal_ptr++; /* skip over the unused byte */\r
-\r
- LCDx->PAL[i] = *(uint32_t *)ptr_pal_entry;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Load Cursor Palette\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] palette_color cursor palette 0 value\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Cursor_LoadPalette0(LPC_LCD_Type *LCDx, uint32_t palette_color){\r
- /* 7:0 - Red\r
- 15:8 - Green\r
- 23:16 - Blue\r
- 31:24 - Not used*/\r
- LCDx->CRSR_PAL0 = (uint32_t)palette_color;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Load Cursor Palette\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] palette_color cursor palette 1 value\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Cursor_LoadPalette1(LPC_LCD_Type *LCDx, uint32_t palette_color){\r
- /* 7:0 - Red\r
- 15:8 - Green\r
- 23:16 - Blue\r
- 31:24 - Not used*/\r
- LCDx->CRSR_PAL1 = (uint32_t)palette_color;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set Interrupt\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] Int LCD Interrupt Source, should be:\r
- * - LCD_INT_FUF :FIFO underflow\r
- * - LCD_INT_LNBU :LCD next base address update bit\r
- * - LCD_INT_VCOMP :Vertical compare bit\r
- * - LCD_INT_BER :AHB master error interrupt bit\r
- * @return None\r
- **********************************************************************/\r
-void LCD_SetInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int){\r
- LCDx->INTMSK |= Int;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Clear Interrupt\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] Int LCD Interrupt Source, should be:\r
- * - LCD_INT_FUF :FIFO underflow\r
- * - LCD_INT_LNBU :LCD next base address update bit\r
- * - LCD_INT_VCOMP :Vertical compare bit\r
- * - LCD_INT_BER :AHB master error interrupt bit\r
- * @return None\r
- **********************************************************************/\r
-void LCD_ClrInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int){\r
- LCDx->INTCLR |= Int;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get LCD Interrupt Status\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @return None\r
- **********************************************************************/\r
-LCD_INT_SRC LCD_GetInterrupt(LPC_LCD_Type *LCDx){\r
- return (LCD_INT_SRC)LCDx->INTRAW;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable Cursor Interrupt\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Cursor_SetInterrupt(LPC_LCD_Type *LCDx){\r
- LCDx->CRSR_INTMSK |= 1;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Clear Cursor Interrupt\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Cursor_ClrInterrupt(LPC_LCD_Type *LCDx){\r
- LCDx->CRSR_INTCLR |= 1;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set Cursor Position\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] x horizontal position\r
- * @param[in] y vertical position\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Cursor_SetPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y){\r
- LCDx->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set Cursor Clipping Position\r
- * @param[in] LCDx pointer to LCD Controller Reg Struct, should be: LPC_LCD\r
- * @param[in] x horizontal position, should be in range: 0..63\r
- * @param[in] y vertical position, should be in range: 0..63\r
- * @return None\r
- **********************************************************************/\r
-void LCD_Cursor_SetClip(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y){\r
- LCDx->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8);\r
-}\r
-#endif /* _LCD */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/***********************************************************************//**\r
- * @file lpc18xx_libcfg_default.c\r
- * @brief Library configuration source file (default),\r
- * used to build library without examples.\r
- * @version 2.0\r
- * @date 21. May. 2010\r
- * @author NXP MCU SW Application Team\r
- **************************************************************************\r
- * Software that is described herein is for illustrative purposes only\r
- * which provides customers with programming information regarding the\r
- * products. This software is supplied "AS IS" without any warranties.\r
- * NXP Semiconductors assumes no responsibility or liability for the\r
- * use of the software, conveys no license or title under any patent,\r
- * copyright, or mask work right to the product. NXP Semiconductors\r
- * reserves the right to make changes in the software without\r
- * notification. NXP Semiconductors also make no representation or\r
- * warranty that such application will be suitable for the specified\r
- * use without further testing or modification.\r
- **************************************************************************/\r
-\r
-/* Library group ----------------------------------------------------------- */\r
-/** @addtogroup LIBCFG_DEFAULT\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_libcfg_default.h"\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup LIBCFG_DEFAULT_Public_Functions\r
- * @{\r
- */\r
-\r
-#ifndef __BUILD_WITH_EXAMPLE__\r
-\r
-#ifdef DEBUG\r
-/*******************************************************************************\r
-* @brief Reports the name of the source file and the source line number\r
-* where the CHECK_PARAM error has occurred.\r
-* @param[in] file Pointer to the source file name\r
-* @param[in] line assert_param error line source number\r
-* @return None\r
-*******************************************************************************/\r
-void check_failed(uint8_t *file, uint32_t line)\r
-{\r
- /* User can add his own implementation to report the file name and line number,\r
- ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
-\r
- /* Infinite loop */\r
- while(1);\r
-}\r
-#endif /* DEBUG */\r
-\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_mcpwm.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_mcpwm.c\r
-* @brief Contains all functions support for Motor Control PWM firmware\r
-* library on LPC18XX\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup MCPWM\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_mcpwm.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-#ifdef _MCPWM\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup MCPWM_Public_Functions\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief Initializes the MCPWM peripheral\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @return None\r
- **********************************************************************/\r
-void MCPWM_Init(LPC_MCPWM_Type *MCPWMx)\r
-{\r
- /* Turn On MCPWM PCLK */\r
- //LPC_CGU->BASE_VPB1_CLK = (SRC_PL160M_0<<24) | (1<<11);\r
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_APB1);\r
-\r
- MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(0) | MCPWM_CAPCLR_CAP(1) | MCPWM_CAPCLR_CAP(2);\r
-\r
- MCPWMx->INTF_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \\r
- | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \\r
- | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);\r
-\r
- MCPWMx->INTEN_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \\r
- | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \\r
- | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configures each channel in MCPWM peripheral according to the\r
- * specified parameters in the MCPWM_CHANNEL_CFG_Type.\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] channelNum Channel number, should be: 0..2.\r
- * @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure\r
- * that contains the configuration information for the specified\r
- * MCPWM channel.\r
- * @return None\r
- **********************************************************************/\r
-void MCPWM_ConfigChannel(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,\r
- MCPWM_CHANNEL_CFG_Type * channelSetup)\r
-{\r
- if (channelNum <= 2)\r
- {\r
- if (channelNum == MCPWM_CHANNEL_0)\r
- {\r
- MCPWMx->TC[0] = channelSetup->channelTimercounterValue;\r
- MCPWMx->LIM[0] = channelSetup->channelPeriodValue;\r
- MCPWMx->MAT[0] = channelSetup->channelPulsewidthValue;\r
- }\r
- else if (channelNum == MCPWM_CHANNEL_1)\r
- {\r
- MCPWMx->TC[1] = channelSetup->channelTimercounterValue;\r
- MCPWMx->LIM[1] = channelSetup->channelPeriodValue;\r
- MCPWMx->MAT[1] = channelSetup->channelPulsewidthValue;\r
- }\r
- else if (channelNum == MCPWM_CHANNEL_2)\r
- {\r
- MCPWMx->TC[2] = channelSetup->channelTimercounterValue;\r
- MCPWMx->LIM[2] = channelSetup->channelPeriodValue;\r
- MCPWMx->MAT[2] = channelSetup->channelPulsewidthValue;\r
- }\r
- else\r
- {\r
- return;\r
- }\r
-\r
- if (channelSetup->channelType == MCPWM_CHANNEL_CENTER_MODE)\r
- {\r
- MCPWMx->CON_SET = MCPWM_CON_CENTER(channelNum);\r
- }\r
- else\r
- {\r
- MCPWMx->CON_CLR = MCPWM_CON_CENTER(channelNum);\r
- }\r
-\r
- if (channelSetup->channelPolarity == MCPWM_CHANNEL_PASSIVE_HI)\r
- {\r
- MCPWMx->CON_SET = MCPWM_CON_POLAR(channelNum);\r
- }\r
- else\r
- {\r
- MCPWMx->CON_CLR = MCPWM_CON_POLAR(channelNum);\r
- }\r
-\r
- if (channelSetup->channelDeadtimeEnable == ENABLE)\r
- {\r
- MCPWMx->CON_SET = MCPWM_CON_DTE(channelNum);\r
-\r
- MCPWMx->DT &= ~(MCPWM_DT(channelNum, 0x3FF));\r
-\r
- MCPWMx->DT |= MCPWM_DT(channelNum, channelSetup->channelDeadtimeValue);\r
- }\r
- else\r
- {\r
- MCPWMx->CON_CLR = MCPWM_CON_DTE(channelNum);\r
- }\r
-\r
- if (channelSetup->channelUpdateEnable == ENABLE)\r
- {\r
- MCPWMx->CON_CLR = MCPWM_CON_DISUP(channelNum);\r
- }\r
- else\r
- {\r
- MCPWMx->CON_SET = MCPWM_CON_DISUP(channelNum);\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Write to MCPWM shadow registers - Update the value for period\r
- * and pulse width in MCPWM peripheral.\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] channelNum Channel Number, should be: 0..2.\r
- * @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure\r
- * that contains the configuration information for the specified\r
- * MCPWM channel.\r
- * @return None\r
- **********************************************************************/\r
-void MCPWM_WriteToShadow(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,\r
- MCPWM_CHANNEL_CFG_Type *channelSetup)\r
-{\r
- if (channelNum == MCPWM_CHANNEL_0)\r
- {\r
- MCPWMx->LIM[0] = channelSetup->channelPeriodValue;\r
- MCPWMx->MAT[0] = channelSetup->channelPulsewidthValue;\r
- }\r
- else if (channelNum == MCPWM_CHANNEL_1)\r
- {\r
- MCPWMx->LIM[1] = channelSetup->channelPeriodValue;\r
- MCPWMx->MAT[1] = channelSetup->channelPulsewidthValue;\r
- }\r
- else if (channelNum == MCPWM_CHANNEL_2)\r
- {\r
- MCPWMx->LIM[2] = channelSetup->channelPeriodValue;\r
- MCPWMx->MAT[2] = channelSetup->channelPulsewidthValue;\r
- }\r
-}\r
-\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configures capture function in MCPWM peripheral\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] channelNum MCI (Motor Control Input pin) number, should be: 0..2\r
- * @param[in] captureConfig Pointer to a MCPWM_CAPTURE_CFG_Type structure\r
- * that contains the configuration information for the\r
- * specified MCPWM capture.\r
- * @return\r
- **********************************************************************/\r
-void MCPWM_ConfigCapture(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,\r
- MCPWM_CAPTURE_CFG_Type *captureConfig)\r
-{\r
- if ((channelNum <= MCPWM_CHANNEL_2))\r
- {\r
-\r
- if (captureConfig->captureFalling == ENABLE)\r
- {\r
- MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);\r
- }\r
- else\r
- {\r
- MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);\r
- }\r
-\r
- if (captureConfig->captureRising == ENABLE)\r
- {\r
- MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);\r
- }\r
- else\r
- {\r
- MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);\r
- }\r
-\r
- if (captureConfig->timerReset == ENABLE)\r
- {\r
- MCPWMx->CAPCON_SET = MCPWM_CAPCON_RT(captureConfig->captureChannel);\r
- }\r
- else\r
- {\r
- MCPWMx->CAPCON_CLR = MCPWM_CAPCON_RT(captureConfig->captureChannel);\r
- }\r
-\r
- if (captureConfig->hnfEnable == ENABLE)\r
- {\r
- MCPWMx->CAPCON_SET = MCPWM_CAPCON_HNFCAP(channelNum);\r
- }\r
- else\r
- {\r
- MCPWMx->CAPCON_CLR = MCPWM_CAPCON_HNFCAP(channelNum);\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Clears current captured value in specified capture channel\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] captureChannel Capture channel number, should be: 0..2\r
- * @return None\r
- **********************************************************************/\r
-void MCPWM_ClearCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel)\r
-{\r
- MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(captureChannel);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get current captured value in specified capture channel\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] captureChannel Capture channel number, should be: 0..2\r
- * @return None\r
- **********************************************************************/\r
-uint32_t MCPWM_GetCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel)\r
-{\r
- if (captureChannel == MCPWM_CHANNEL_0)\r
- {\r
- return (MCPWMx->CAP[0]);\r
- }\r
- else if (captureChannel == MCPWM_CHANNEL_1)\r
- {\r
- return (MCPWMx->CAP[1]);\r
- }\r
- else if (captureChannel == MCPWM_CHANNEL_2)\r
- {\r
- return (MCPWMx->CAP[2]);\r
- }\r
- return (0);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configures Count control in MCPWM peripheral\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] channelNum Channel number, should be: 0..2\r
- * @param[in] countMode Count mode, should be:\r
- * - ENABLE: Enables count mode.\r
- * - DISABLE: Disable count mode, the channel is in timer mode.\r
- * @param[in] countConfig Pointer to a MCPWM_COUNT_CFG_Type structure\r
- * that contains the configuration information for the\r
- * specified MCPWM count control.\r
- * @return None\r
- **********************************************************************/\r
-void MCPWM_CountConfig(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,\r
- uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig)\r
-{\r
- if ((channelNum <= 2))\r
- {\r
- if (countMode == ENABLE)\r
- {\r
- MCPWMx->CNTCON_SET = MCPWM_CNTCON_CNTR(channelNum);\r
-\r
- if (countConfig->countFalling == ENABLE)\r
- {\r
- MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);\r
- }\r
- else\r
- {\r
- MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);\r
- }\r
-\r
- if (countConfig->countRising == ENABLE)\r
- {\r
- MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);\r
- }\r
- else\r
- {\r
- MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);\r
- }\r
- }\r
- else\r
- {\r
- MCPWMx->CNTCON_CLR = MCPWM_CNTCON_CNTR(channelNum);\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Start MCPWM activity for each MCPWM channel\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] channel0 State of this command on channel 0:\r
- * - ENABLE: 'Start' command will effect on channel 0\r
- * - DISABLE: 'Start' command will not effect on channel 0\r
- * @param[in] channel1 State of this command on channel 1:\r
- * - ENABLE: 'Start' command will effect on channel 1\r
- * - DISABLE: 'Start' command will not effect on channel 1\r
- * @param[in] channel2 State of this command on channel 2:\r
- * - ENABLE: 'Start' command will effect on channel 2\r
- * - DISABLE: 'Start' command will not effect on channel 2\r
- * @return None\r
- **********************************************************************/\r
-void MCPWM_Start(LPC_MCPWM_Type *MCPWMx, uint32_t channel0,\r
- uint32_t channel1, uint32_t channel2)\r
-{\r
- uint32_t regVal = 0;\r
-\r
- regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \\r
- | (channel2 ? MCPWM_CON_RUN(2) : 0);\r
-\r
- MCPWMx->CON_SET = regVal;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Stop MCPWM activity for each MCPWM channel\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] channel0 State of this command on channel 0:\r
- * - ENABLE: 'Stop' command will effect on channel 0\r
- * - DISABLE: 'Stop' command will not effect on channel 0\r
- * @param[in] channel1 State of this command on channel 1:\r
- * - ENABLE: 'Stop' command will effect on channel 1\r
- * - DISABLE: 'Stop' command will not effect on channel 1\r
- * @param[in] channel2 State of this command on channel 2:\r
- * - ENABLE: 'Stop' command will effect on channel 2\r
- * - DISABLE: 'Stop' command will not effect on channel 2\r
- * @return None\r
- **********************************************************************/\r
-void MCPWM_Stop(LPC_MCPWM_Type *MCPWMx, uint32_t channel0,\r
- uint32_t channel1, uint32_t channel2)\r
-{\r
- uint32_t regVal = 0;\r
-\r
- regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \\r
- | (channel2 ? MCPWM_CON_RUN(2) : 0);\r
-\r
- MCPWMx->CON_CLR = regVal;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enables/Disables 3-phase AC motor mode on MCPWM peripheral\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] acMode State of this command, should be:\r
- * - ENABLE.\r
- * - DISABLE.\r
- * @return None\r
- **********************************************************************/\r
-void MCPWM_ACMode(LPC_MCPWM_Type *MCPWMx, uint32_t acMode)\r
-{\r
- if (acMode)\r
- {\r
- MCPWMx->CON_SET = MCPWM_CON_ACMODE;\r
- }\r
- else\r
- {\r
- MCPWMx->CON_CLR = MCPWM_CON_ACMODE;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enables/Disables 3-phase DC motor mode on MCPWM peripheral\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] dcMode State of this command, should be:\r
- * - ENABLE.\r
- * - DISABLE.\r
- * @param[in] outputInvered Polarity of the MCOB outputs for all 3 channels,\r
- * should be:\r
- * - ENABLE :The MCOB outputs have opposite polarity from the MCOA outputs.\r
- * - DISABLE :The MCOB outputs have the same basic polarity as the MCOA outputs.\r
- * @param[in] outputPattern A value contains bits that enables/disables the specified\r
- * output pins route to the internal MCOA0 signal, should be:\r
- * - MCPWM_PATENT_A0 :MCOA0 tracks internal MCOA0\r
- * - MCPWM_PATENT_B0 :MCOB0 tracks internal MCOA0\r
- * - MCPWM_PATENT_A1 :MCOA1 tracks internal MCOA0\r
- * - MCPWM_PATENT_B1 :MCOB1 tracks internal MCOA0\r
- * - MCPWM_PATENT_A2 :MCOA2 tracks internal MCOA0\r
- * - MCPWM_PATENT_B2 :MCOB2 tracks internal MCOA0\r
- * @return None\r
- *\r
- * Note: all these outputPatent values above can be ORed together for using as input parameter.\r
- **********************************************************************/\r
-void MCPWM_DCMode(LPC_MCPWM_Type *MCPWMx, uint32_t dcMode,\r
- uint32_t outputInvered, uint32_t outputPattern)\r
-{\r
- if (dcMode)\r
- {\r
- MCPWMx->CON_SET = MCPWM_CON_DCMODE;\r
- }\r
- else\r
- {\r
- MCPWMx->CON_CLR = MCPWM_CON_DCMODE;\r
- }\r
-\r
- if (outputInvered)\r
- {\r
- MCPWMx->CON_SET = MCPWM_CON_INVBDC;\r
- }\r
- else\r
- {\r
- MCPWMx->CON_CLR = MCPWM_CON_INVBDC;\r
- }\r
-\r
- MCPWMx->CCP = outputPattern;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configures the specified interrupt in MCPWM peripheral\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] ulIntType Interrupt type, should be:\r
- * - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0)\r
- * - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0)\r
- * - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0)\r
- * - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1)\r
- * - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1)\r
- * - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1)\r
- * - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2)\r
- * - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2)\r
- * - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2)\r
- * - MCPWM_INTFLAG_ABORT :Fast abort interrupt\r
- * @param[in] NewState New State of this command, should be:\r
- * - ENABLE.\r
- * - DISABLE.\r
- * @return None\r
- *\r
- * Note: all these ulIntType values above can be ORed together for using as input parameter.\r
- **********************************************************************/\r
-void MCPWM_IntConfig(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType, FunctionalState NewState)\r
-{\r
- if (NewState)\r
- {\r
- MCPWMx->INTEN_SET = ulIntType;\r
- }\r
- else\r
- {\r
- MCPWMx->INTEN_CLR = ulIntType;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Sets/Forces the specified interrupt for MCPWM peripheral\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] ulIntType Interrupt type, should be:\r
- * - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0)\r
- * - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0)\r
- * - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0)\r
- * - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1)\r
- * - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1)\r
- * - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1)\r
- * - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2)\r
- * - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2)\r
- * - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2)\r
- * - MCPWM_INTFLAG_ABORT :Fast abort interrupt\r
- * @return None\r
- * Note: all these ulIntType values above can be ORed together for using as input parameter.\r
- **********************************************************************/\r
-void MCPWM_IntSet(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType)\r
-{\r
- MCPWMx->INTF_SET = ulIntType;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Clear the specified interrupt pending for MCPWM peripheral\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] ulIntType Interrupt type, should be:\r
- * - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0)\r
- * - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0)\r
- * - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0)\r
- * - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1)\r
- * - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1)\r
- * - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1)\r
- * - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2)\r
- * - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2)\r
- * - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2)\r
- * - MCPWM_INTFLAG_ABORT :Fast abort interrupt\r
- * @return None\r
- * Note: all these ulIntType values above can be ORed together for using as input parameter.\r
- **********************************************************************/\r
-void MCPWM_IntClear(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType)\r
-{\r
- MCPWMx->INTF_CLR = ulIntType;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Check whether if the specified interrupt in MCPWM is set or not\r
- * @param[in] MCPWMx Motor Control PWM peripheral selected, should be: LPC_MCPWM\r
- * @param[in] ulIntType Interrupt type, should be:\r
- * - MCPWM_INTFLAG_LIM0 :Limit interrupt for channel (0)\r
- * - MCPWM_INTFLAG_MAT0 :Match interrupt for channel (0)\r
- * - MCPWM_INTFLAG_CAP0 :Capture interrupt for channel (0)\r
- * - MCPWM_INTFLAG_LIM1 :Limit interrupt for channel (1)\r
- * - MCPWM_INTFLAG_MAT1 :Match interrupt for channel (1)\r
- * - MCPWM_INTFLAG_CAP1 :Capture interrupt for channel (1)\r
- * - MCPWM_INTFLAG_LIM2 :Limit interrupt for channel (2)\r
- * - MCPWM_INTFLAG_MAT2 :Match interrupt for channel (2)\r
- * - MCPWM_INTFLAG_CAP2 :Capture interrupt for channel (2)\r
- * - MCPWM_INTFLAG_ABORT :Fast abort interrupt\r
- * @return None\r
- **********************************************************************/\r
-FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType)\r
-{\r
- return ((MCPWMx->INTF & ulIntType) ? SET : RESET);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _MCPWM */\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_nvic.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_nvic.c\r
-* @brief Contains all expansion functions support for NVIC firmware\r
-* library on LPC18XX. The main NVIC functions are defined in\r
-* core_cm3.h\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup NVIC\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_nvic.h"\r
-\r
-\r
-/* Private Macros ------------------------------------------------------------- */\r
-/** @addtogroup NVIC_Private_Macros\r
- * @{\r
- */\r
-\r
-/* Vector table offset bit mask */\r
-#define NVIC_VTOR_MASK 0x3FFFFF80\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup NVIC_Public_Functions\r
- * @{\r
- */\r
-\r
-/*****************************************************************************//**\r
- * @brief Set Vector Table Offset value\r
- * @param offset Offset value\r
- * @return None\r
- *******************************************************************************/\r
-void NVIC_SetVTOR(uint32_t offset)\r
-{\r
-// SCB->VTOR = (offset & NVIC_VTOR_MASK);\r
- SCB->VTOR = offset;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_pwr.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_pwr.c\r
-* @brief Contains all functions support for Power Control\r
-* firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup PWR\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc_types.h"\r
-#include "lpc18xx_scu.h"\r
-#include "lpc18xx_pwr.h"\r
-\r
-/*********************************************************************//**\r
- * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.\r
- * @param[in] None\r
- * @return None\r
- **********************************************************************/\r
-void PWR_Sleep(void)\r
-{\r
- //LPC_PMC->SLEEP0_MODE = 0x00;\r
- /* Sleep Mode*/\r
- __WFI();\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.\r
- * @param[in] None\r
- * @return None\r
- **********************************************************************/\r
-void PWR_DeepSleep(void)\r
-{\r
- /* Deep-Sleep Mode, set SLEEPDEEP bit */\r
- SCB->SCR = 0x4;\r
- LPC_PMC->PD0_SLEEP0_MODE = PWR_SLEEP_MODE_DEEP_SLEEP;\r
- /* Deep Sleep Mode*/\r
- __WFI();\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.\r
- * @param[in] None\r
- * @return None\r
- **********************************************************************/\r
-void PWR_PowerDown(void)\r
-{\r
- /* Deep-Sleep Mode, set SLEEPDEEP bit */\r
- SCB->SCR = 0x4;\r
- LPC_PMC->PD0_SLEEP0_MODE = PWR_SLEEP_MODE_POWER_DOWN;\r
- /* Power Down Mode*/\r
- __WFI();\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.\r
- * @param[in] None\r
- * @return None\r
- **********************************************************************/\r
-void PWR_DeepPowerDown(void)\r
-{\r
- /* Deep-Sleep Mode, set SLEEPDEEP bit */\r
- SCB->SCR = 0x4;\r
- LPC_PMC->PD0_SLEEP0_MODE = PWR_SLEEP_MODE_DEEP_POWER_DOWN;\r
- /* Deep Power Down Mode*/\r
- __WFI();\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_qei.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_pwr.c\r
-* @brief Contains all functions support for QEI firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup QEI\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_qei.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-#ifdef _QEI\r
-\r
-/* Private Types -------------------------------------------------------------- */\r
-/** @defgroup QEI_Private_Types QEI Private Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief QEI configuration union type definition\r
- */\r
-typedef union {\r
- QEI_CFG_Type bmQEIConfig;\r
- uint32_t ulQEIConfig;\r
-} QEI_CFGOPT_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-LPC_QEI_Type* QEI_GetPointer(uint8_t qeiId);\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup QEI_Public_Functions\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief Get the point to typedef of QEI component\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @return None\r
- **********************************************************************/\r
-LPC_QEI_Type* QEI_GetPointer(uint8_t qeiId)\r
-{\r
- LPC_QEI_Type* pQei = NULL;\r
-\r
- if(qeiId == 0)\r
- {\r
- pQei = LPC_QEI;\r
- }\r
-\r
- return pQei;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Resets value for each type of QEI value, such as velocity,\r
- * counter, position, etc..\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulResetType QEI Reset Type, should be one of the following:\r
- * - QEI_RESET_POS :Reset Position Counter\r
- * - QEI_RESET_POSOnIDX :Reset Position Counter on Index signal\r
- * - QEI_RESET_VEL :Reset Velocity\r
- * - QEI_RESET_IDX :Reset Index Counter\r
- * @return None\r
- **********************************************************************/\r
-void QEI_Reset(uint8_t qeiId, uint32_t ulResetType)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- pQei->CON = ulResetType;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Initializes the QEI peripheral according to the specified\r
-* parameters in the QEI_ConfigStruct.\r
-* @param[in] qeiId The Id of the expected QEI component, should be: 0\r
-* @param[in] QEI_ConfigStruct Pointer to a QEI_CFG_Type structure\r
-* that contains the configuration information for the\r
-* specified QEI peripheral\r
- * @return None\r
- **********************************************************************/\r
-void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- /* Set up clock and power for QEI module */\r
- // Already enabled by BASE_M3_CLK\r
-\r
- // Reset all remaining value in QEI peripheral\r
-\r
- pQei->MAXPOS = 0x00;\r
- pQei->CMPOS0 = 0x00;\r
- pQei->CMPOS1 = 0x00;\r
- pQei->CMPOS2 = 0x00;\r
- pQei->INXCMP0 = 0x00;\r
- pQei->VELCOMP = 0x00;\r
-\r
- pQei->LOAD = 0x00;\r
- pQei->CON = QEI_CON_RESP | QEI_CON_RESV | QEI_CON_RESI;\r
-\r
- pQei->FILTERPHA = 0x00;\r
- pQei->FILTERPHB = 0x00;\r
- pQei->FILTERINX = 0x00;\r
-\r
- // Disable all Interrupt\r
- pQei->IEC = QEI_IECLR_BITMASK;\r
-\r
- // Clear all Interrupt pending\r
- pQei->CLR = QEI_INTCLR_BITMASK;\r
-\r
- // Set QEI configuration value corresponding to its setting up value\r
- pQei->CONF = ((QEI_CFGOPT_Type *)QEI_ConfigStruct)->ulQEIConfig;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief De-Initalize QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @return None\r
- **********************************************************************/\r
-void QEI_DeInit(uint8_t qeiId)\r
-{\r
- /* Turn off clock and power for QEI module */\r
-\r
-}\r
-\r
-\r
-/*****************************************************************************//**\r
-* @brief Fills each QIE_InitStruct member with its default value:\r
-* - DirectionInvert = QEI_DIRINV_NONE\r
-* - SignalMode = QEI_SIGNALMODE_QUAD\r
-* - CaptureMode = QEI_CAPMODE_4X\r
-* - InvertIndex = QEI_INVINX_NONE\r
-* @param[in] QIE_InitStruct Pointer to a QEI_CFG_Type structure which will be\r
-* initialized.\r
-* @return None\r
-*******************************************************************************/\r
-void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct)\r
-{\r
- QIE_InitStruct->CaptureMode = QEI_CAPMODE_4X;\r
- QIE_InitStruct->DirectionInvert = QEI_DIRINV_NONE;\r
- QIE_InitStruct->InvertIndex = QEI_INVINX_NONE;\r
- QIE_InitStruct->SignalMode = QEI_SIGNALMODE_QUAD;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Check whether if specified flag status is set or not\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulFlagType Status Flag Type, should be one of the following:\r
- * - QEI_STATUS_DIR: Direction Status\r
- * @return New Status of this status flag (SET or RESET)\r
- **********************************************************************/\r
-FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- return ((pQei->STAT & ulFlagType) ? SET : RESET);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get current position value in QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @return Current position value of QEI peripheral\r
- **********************************************************************/\r
-uint32_t QEI_GetPosition(uint8_t qeiId)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- return (pQei->POS);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set max position value for QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulMaxPos Max position value to set\r
- * @return None\r
- **********************************************************************/\r
-void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- pQei->MAXPOS = ulMaxPos;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set position compare value for QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] bPosCompCh Compare Position channel, should be:\r
- * - QEI_COMPPOS_CH_0 :QEI compare position channel 0\r
- * - QEI_COMPPOS_CH_1 :QEI compare position channel 1\r
- * - QEI_COMPPOS_CH_2 :QEI compare position channel 2\r
- * @param[in] ulPosComp Compare Position value to set\r
- * @return None\r
- **********************************************************************/\r
-void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
- uint32_t *tmp;\r
-\r
- tmp = (uint32_t *) (&(pQei->CMPOS0) + bPosCompCh * 4);\r
- *tmp = ulPosComp;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get current index counter of QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @return Current value of QEI index counter\r
- **********************************************************************/\r
-uint32_t QEI_GetIndex(uint8_t qeiId)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- return (pQei->INXCNT);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set value for index compare in QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulIndexComp Compare Index Value to set\r
- * @return None\r
- **********************************************************************/\r
-void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- pQei->INXCMP0 = ulIndexComp;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set timer reload value for QEI peripheral. When the velocity timer is\r
- * over-flow, the value that set for Timer Reload register will be loaded\r
- * into the velocity timer for next period. The calculated velocity in RPM\r
- * therefore will be affect by this value.\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] QEIReloadStruct QEI reload structure\r
- * @return None\r
- **********************************************************************/\r
-void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
- uint64_t pclk;\r
-\r
- if (QEIReloadStruct->ReloadOption == QEI_TIMERRELOAD_TICKVAL)\r
- {\r
- pQei->LOAD = QEIReloadStruct->ReloadValue - 1;\r
- }\r
- else\r
- {\r
-#if 1\r
- pclk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE);\r
-\r
- pclk = (pclk /(1000000/QEIReloadStruct->ReloadValue)) - 1;\r
-\r
- pQei->LOAD = (uint32_t)pclk;\r
-#else\r
- ld = M3Frequency;\r
-\r
- if (ld/1000000 > 0)\r
- {\r
- ld /= 1000000;\r
- ld *= QEIReloadStruct->ReloadValue;\r
- ld -= 1;\r
- }\r
- else\r
- {\r
- ld *= QEIReloadStruct->ReloadValue;\r
- ld /= 1000000;\r
- ld -= 1;\r
- }\r
-\r
- pQei->LOAD = ld;\r
-#endif\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get current timer counter in QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @return Current timer counter in QEI peripheral\r
- **********************************************************************/\r
-uint32_t QEI_GetTimer(uint8_t qeiId)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- return (pQei->TIME);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get current velocity pulse counter in current time period\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @return Current velocity pulse counter value\r
- **********************************************************************/\r
-uint32_t QEI_GetVelocity(uint8_t qeiId)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- return (pQei->VEL);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get the most recently measured velocity of the QEI. When\r
- * the Velocity timer in QEI is over-flow, the current velocity\r
- * value will be loaded into Velocity Capture register.\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @return The most recently measured velocity value\r
- **********************************************************************/\r
-uint32_t QEI_GetVelocityCap(uint8_t qeiId)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- return (pQei->CAP);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set Velocity Compare value for QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulVelComp Compare Velocity value to set\r
- * @return None\r
- **********************************************************************/\r
-void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- pQei->VELCOMP = ulVelComp;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Set value of sampling count for the digital filter in\r
- * QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulSamplingPulse Value of sampling count to set\r
- * @return None\r
- **********************************************************************/\r
-void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- pQei->FILTERPHA = FilterVal.PHA_FilterVal;\r
- pQei->FILTERPHB = FilterVal.PHB_FilterVal;\r
- pQei->FILTERINX = FilterVal.INX_FilterVal;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Check whether if specified interrupt flag status in QEI\r
- * peripheral is set or not\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulIntType Interrupt Flag Status type, should be:\r
- * - QEI_INTFLAG_INX_Int : index pulse was detected interrupt\r
- * - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt\r
- * - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt\r
- * - QEI_INTFLAG_DIR_Int : Change of direction interrupt\r
- * - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt\r
- * - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt\r
- * - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt\r
- * - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt\r
- * - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt\r
- * - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt\r
- * @return New State of specified interrupt flag status (SET or RESET)\r
- **********************************************************************/\r
-FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- return((pQei->INTSTAT & ulIntType) ? SET : RESET);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable specified interrupt in QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulIntType Interrupt Flag Status type, should be:\r
- * - QEI_INTFLAG_INX_Int : index pulse was detected interrupt\r
- * - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt\r
- * - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt\r
- * - QEI_INTFLAG_DIR_Int : Change of direction interrupt\r
- * - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt\r
- * - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt\r
- * - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt\r
- * - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt\r
- * - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt\r
- * - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt\r
- * @param[in] NewState New function state, should be:\r
- * - DISABLE\r
- * - ENABLE\r
- * @return None\r
- **********************************************************************/\r
-void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- if (NewState == ENABLE)\r
- {\r
- pQei->IES = ulIntType;\r
- }\r
- else\r
- {\r
- pQei->IEC = ulIntType;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Sets (forces) specified interrupt in QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulIntType Interrupt Flag Status type, should be:\r
- * - QEI_INTFLAG_INX_Int : index pulse was detected interrupt\r
- * - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt\r
- * - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt\r
- * - QEI_INTFLAG_DIR_Int : Change of direction interrupt\r
- * - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt\r
- * - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt\r
- * - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt\r
- * - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt\r
- * - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt\r
- * - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt\r
- * @return None\r
- **********************************************************************/\r
-void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- pQei->SET = ulIntType;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Clear (force) specified interrupt (pending) in QEI peripheral\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulIntType Interrupt Flag Status type, should be:\r
- * - QEI_INTFLAG_INX_Int : index pulse was detected interrupt\r
- * - QEI_INTFLAG_TIM_Int : Velocity timer over flow interrupt\r
- * - QEI_INTFLAG_VELC_Int : Capture velocity is less than compare interrupt\r
- * - QEI_INTFLAG_DIR_Int : Change of direction interrupt\r
- * - QEI_INTFLAG_ERR_Int : An encoder phase error interrupt\r
- * - QEI_INTFLAG_ENCLK_Int : An encoder clock pulse was detected interrupt\r
- * - QEI_INTFLAG_POS0_Int : position 0 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_POS1_Int : position 1 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_POS2_Int : position 2 compare value is equal to the current position interrupt\r
- * - QEI_INTFLAG_REV_Int : Index compare value is equal to the current index count interrupt\r
- * - QEI_INTFLAG_POS0REV_Int : Combined position 0 and revolution count interrupt\r
- * - QEI_INTFLAG_POS1REV_Int : Combined position 1 and revolution count interrupt\r
- * - QEI_INTFLAG_POS2REV_Int : Combined position 2 and revolution count interrupt\r
- * @return None\r
- **********************************************************************/\r
-void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- pQei->CLR = ulIntType;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Calculates the actual velocity in RPM passed via velocity\r
- * capture value and Pulse Per Round (of the encoder) value\r
- * parameter input.\r
- * @param[in] qeiId The Id of the expected QEI component, should be: 0\r
- * @param[in] ulVelCapValue Velocity capture input value that can be\r
- * got from QEI_GetVelocityCap() function\r
- * @param[in] ulPPR Pulse per round of encoder\r
- * @return The actual value of velocity in RPM (Round per minute)\r
- **********************************************************************/\r
-uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR)\r
-{\r
- LPC_QEI_Type* pQei = QEI_GetPointer(qeiId);\r
-\r
- uint64_t rpm, clock, Load, edges;\r
-\r
- // Get current Clock rate for timer input\r
- clock = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE);\r
-\r
- // Get Timer load value (velocity capture period)\r
- Load = (uint64_t)(pQei->LOAD + 1);\r
-\r
- // Get Edge\r
- edges = (uint64_t)((pQei->CONF & QEI_CONF_CAPMODE) ? 4 : 2);\r
-\r
- // Calculate RPM\r
- rpm = ((clock * ulVelCapValue * 60) / (Load * ulPPR * edges));\r
-\r
- return (uint32_t)(rpm);\r
-}\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _QEI */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_rgu.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_rgu.c\r
-* @brief Contains all functions support for RGU firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup RGU\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_rgu.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _RGU\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup RGU_Public_Functions\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief Soft Reset a Signal\r
- * @param[in] ResetSignal indicates which signal will be reset, should be:\r
- * - RGU_SIG_CORE :Core\r
- * - RGU_SIG_PERIPH :Peripheral\r
- * - RGU_SIG_MASTER :Master\r
- * - RGU_SIG_WWDT :WWDT\r
- * - RGU_SIG_CREG :Configuration register block\r
- * - RGU_SIG_BUS :Buses\r
- * - RGU_SIG_SCU :System control unit\r
- * - RGU_SIG_PINMUX :Pin mux\r
- * - RGU_SIG_M3 :Cortex-M3 system\r
- * - RGU_SIG_LCD :LCD controller\r
- * - RGU_SIG_USB0 :USB0\r
- * - RGU_SIG_USB1 :USB1\r
- * - RGU_SIG_DMA :DMA\r
- * - RGU_SIG_SDIO :SDIO\r
- * - RGU_SIG_EMC :External memory controller\r
- * - RGU_SIG_ETHERNET :Ethernet\r
- * - RGU_SIG_AES :AES\r
- * - RGU_SIG_GPIO :GPIO\r
- * - RGU_SIG_TIMER0 :Timer 0\r
- * - RGU_SIG_TIMER1 :Timer 1\r
- * - RGU_SIG_TIMER2 :Timer 2\r
- * - RGU_SIG_TIMER3 :Timer 3\r
- * - RGU_SIG_RITIMER :Repetitive Interrupt Timer\r
- * - RGU_SIG_SCT :State Configurable Timer\r
- * - RGU_SIG_MOTOCONPWM:Motor Control PWM\r
- * - RGU_SIG_QEI :QEI\r
- * - RGU_SIG_ADC0 :ADC0\r
- * - RGU_SIG_ADC1 :ADC1\r
- * - RGU_SIG_DAC :DAC\r
- * - RGU_SIG_UART0 :UART0\r
- * - RGU_SIG_UART1 :UART1\r
- * - RGU_SIG_UART2 :UART2\r
- * - RGU_SIG_UART3 :UART3\r
- * - RGU_SIG_I2C0 :I2C0\r
- * - RGU_SIG_I2C1 :I2C1\r
- * - RGU_SIG_SSP0 :SSP0\r
- * - RGU_SIG_SSP1 :SSP1\r
- * - RGU_SIG_I2S :I2S\r
- * - RGU_SIG_SPIFI :SPIFI\r
- * - RGU_SIG_CAN :CAN\r
- * @return None\r
- **********************************************************************/\r
-void RGU_SoftReset(RGU_SIG ResetSignal)\r
-{\r
- if(ResetSignal < 32){\r
- LPC_RGU->RESET_CTRL0 = 1 << ResetSignal;\r
- LPC_RGU->RESET_CTRL0 = 0;\r
- }else{\r
- LPC_RGU->RESET_CTRL1 = 1 << (ResetSignal - 32);\r
- LPC_RGU->RESET_CTRL1 = 0;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get source cause of a signal\r
- * @param[in] ResetSignal reset signal, should be:\r
- * - RGU_SIG_CORE :Core\r
- * - RGU_SIG_PERIPH :Peripheral\r
- * - RGU_SIG_MASTER :Master\r
- * - RGU_SIG_WWDT :WWDT\r
- * - RGU_SIG_CREG :Configuration register block\r
- * - RGU_SIG_BUS :Buses\r
- * - RGU_SIG_SCU :System control unit\r
- * - RGU_SIG_PINMUX :Pin mux\r
- * - RGU_SIG_M3 :Cortex-M3 system\r
- * - RGU_SIG_LCD :LCD controller\r
- * - RGU_SIG_USB0 :USB0\r
- * - RGU_SIG_USB1 :USB1\r
- * - RGU_SIG_DMA :DMA\r
- * - RGU_SIG_SDIO :SDIO\r
- * - RGU_SIG_EMC :External memory controller\r
- * - RGU_SIG_ETHERNET :Ethernet\r
- * - RGU_SIG_AES :AES\r
- * - RGU_SIG_GPIO :GPIO\r
- * - RGU_SIG_TIMER0 :Timer 0\r
- * - RGU_SIG_TIMER1 :Timer 1\r
- * - RGU_SIG_TIMER2 :Timer 2\r
- * - RGU_SIG_TIMER3 :Timer 3\r
- * - RGU_SIG_RITIMER :Repetitive Interrupt Timer\r
- * - RGU_SIG_SCT :State Configurable Timer\r
- * - RGU_SIG_MOTOCONPWM:Motor Control PWM\r
- * - RGU_SIG_QEI :QEI\r
- * - RGU_SIG_ADC0 :ADC0\r
- * - RGU_SIG_ADC1 :ADC1\r
- * - RGU_SIG_DAC :DAC\r
- * - RGU_SIG_UART0 :UART0\r
- * - RGU_SIG_UART1 :UART1\r
- * - RGU_SIG_UART2 :UART2\r
- * - RGU_SIG_UART3 :UART3\r
- * - RGU_SIG_I2C0 :I2C0\r
- * - RGU_SIG_I2C1 :I2C1\r
- * - RGU_SIG_SSP0 :SSP0\r
- * - RGU_SIG_SSP1 :SSP1\r
- * - RGU_SIG_I2S :I2S\r
- * - RGU_SIG_SPIFI :SPIFI\r
- * - RGU_SIG_CAN :CAN\r
- * @return Source cause of reset, could be:\r
- * - RGU_SRC_NONE :No source\r
- * - RGU_SRC_SOFT :Software reset source\r
- * - RGU_SRC_EXT :External reset source\r
- * - RGU_SRC_CORE :Core reset source\r
- * - RGU_SRC_PERIPH :Peripheral reset source\r
- * - RGU_SRC_MASTER :Master reset source\r
- * - RGU_SRC_BOD :BOD reset source\r
- * - RGU_SRC_WWDT :WWDT reset source\r
- **********************************************************************/\r
-RGU_SRC RGU_GetSource(RGU_SIG ResetSignal)\r
-{\r
- uint32_t i, temp, registercache;\r
- if(ResetSignal < 16)\r
- temp = 3 & (LPC_RGU->RESET_STATUS0 >> ResetSignal);\r
- else if(ResetSignal < 32)\r
- temp = 3 & (LPC_RGU->RESET_STATUS1 >> (ResetSignal - 16));\r
- else if(ResetSignal < 48)\r
- temp = 3 & (LPC_RGU->RESET_STATUS2 >> (ResetSignal - 32));\r
- else\r
- temp = 3 & (LPC_RGU->RESET_STATUS3 >> (ResetSignal - 48));\r
-\r
- if(temp == 0) return RGU_SRC_NONE;\r
- else if(temp == 3) return RGU_SRC_SOFT;\r
- else if(temp == 1){\r
- registercache = (((uint32_t*)&LPC_RGU->RESET_EXT_STAT0)[ResetSignal]);\r
- for(i = 0; i < 6; i++){\r
- if(registercache & (1<<i)){\r
- return (RGU_SRC)(RGU_SRC_EXT + i);\r
- }\r
- }\r
- }\r
- return RGU_SRC_NONE;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get Current Status of Signal\r
- * @param[in] ResetSignal Reset Signal, should be:\r
- * - RGU_SIG_CORE :Core\r
- * - RGU_SIG_PERIPH :Peripheral\r
- * - RGU_SIG_MASTER :Master\r
- * - RGU_SIG_WWDT :WWDT\r
- * - RGU_SIG_CREG :Configuration register block\r
- * - RGU_SIG_BUS :Buses\r
- * - RGU_SIG_SCU :System control unit\r
- * - RGU_SIG_PINMUX :Pin mux\r
- * - RGU_SIG_M3 :Cortex-M3 system\r
- * - RGU_SIG_LCD :LCD controller\r
- * - RGU_SIG_USB0 :USB0\r
- * - RGU_SIG_USB1 :USB1\r
- * - RGU_SIG_DMA :DMA\r
- * - RGU_SIG_SDIO :SDIO\r
- * - RGU_SIG_EMC :External memory controller\r
- * - RGU_SIG_ETHERNET :Ethernet\r
- * - RGU_SIG_AES :AES\r
- * - RGU_SIG_GPIO :GPIO\r
- * - RGU_SIG_TIMER0 :Timer 0\r
- * - RGU_SIG_TIMER1 :Timer 1\r
- * - RGU_SIG_TIMER2 :Timer 2\r
- * - RGU_SIG_TIMER3 :Timer 3\r
- * - RGU_SIG_RITIMER :Repetitive Interrupt Timer\r
- * - RGU_SIG_SCT :State Configurable Timer\r
- * - RGU_SIG_MOTOCONPWM:Motor Control PWM\r
- * - RGU_SIG_QEI :QEI\r
- * - RGU_SIG_ADC0 :ADC0\r
- * - RGU_SIG_ADC1 :ADC1\r
- * - RGU_SIG_DAC :DAC\r
- * - RGU_SIG_UART0 :UART0\r
- * - RGU_SIG_UART1 :UART1\r
- * - RGU_SIG_UART2 :UART2\r
- * - RGU_SIG_UART3 :UART3\r
- * - RGU_SIG_I2C0 :I2C0\r
- * - RGU_SIG_I2C1 :I2C1\r
- * - RGU_SIG_SSP0 :SSP0\r
- * - RGU_SIG_SSP1 :SSP1\r
- * - RGU_SIG_I2S :I2S\r
- * - RGU_SIG_SPIFI :SPIFI\r
- * - RGU_SIG_CAN :CAN\r
- * @return Signal status, could be:\r
- * - TRUE :reset is active\r
- * - FALSE :reset is inactive\r
- **********************************************************************/\r
-Bool RGU_GetSignalStatus(RGU_SIG ResetSignal)\r
-{\r
- if(ResetSignal < 32)\r
- return (Bool)!(LPC_RGU->RESET_ACTIVE_STATUS0 | (1 << ResetSignal));\r
- else\r
- return (Bool)!(LPC_RGU->RESET_ACTIVE_STATUS1 | (1 << (ResetSignal - 32)));\r
-}\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _RGU */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_rit.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_rit.c\r
-* @brief Contains all functions support for RIT firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup RIT\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_rit.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-#ifdef _RIT\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup RIT_Public_Functions\r
- * @{\r
- */\r
-\r
-/******************************************************************************//*\r
- * @brief Initial for RIT\r
- * - Turn on power and clock\r
- * - Setup default register values\r
- * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT\r
- * @return None\r
- *******************************************************************************/\r
-void RIT_Init(LPC_RITIMER_Type *RITx)\r
-{\r
- CHECK_PARAM(PARAM_RITx(RITx));\r
- //CGU_ConfigPPWR (CGU_PCONP_PCRIT, ENABLE);\r
- //Set up default register values\r
- RITx->COMPVAL = 0xFFFFFFFF;\r
- RITx->MASK = 0x00000000;\r
- RITx->CTRL = 0x0C;\r
- RITx->COUNTER = 0x00000000;\r
- // Turn on power and clock\r
-\r
-}\r
-/******************************************************************************//*\r
- * @brief DeInitial for RIT\r
- * - Turn off power and clock\r
- * - ReSetup default register values\r
- * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT\r
- * @return None\r
- *******************************************************************************/\r
-void RIT_DeInit(LPC_RITIMER_Type *RITx)\r
-{\r
- CHECK_PARAM(PARAM_RITx(RITx));\r
-\r
- // Turn off power and clock\r
- //CGU_ConfigPPWR (CGU_PCONP_PCRIT, DISABLE);\r
- //ReSetup default register values\r
- RITx->COMPVAL = 0xFFFFFFFF;\r
- RITx->MASK = 0x00000000;\r
- RITx->CTRL = 0x0C;\r
- RITx->COUNTER = 0x00000000;\r
-}\r
-\r
-/******************************************************************************//*\r
- * @brief Set compare value, mask value and time counter value\r
- * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT\r
- * @param[in] time_interval timer interval value (ms)\r
- * @return None\r
- *******************************************************************************/\r
-\r
-void RIT_TimerConfig(LPC_RITIMER_Type *RITx, uint32_t time_interval)\r
-{\r
- uint32_t clock_rate, cmp_value;\r
- CHECK_PARAM(PARAM_RITx(RITx));\r
-\r
- // Get PCLK value of RIT\r
- clock_rate = /*CGU_GetPCLK(CGU_PCLKSEL_RIT)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE);\r
-\r
- /* calculate compare value for RIT to generate interrupt at\r
- * specified time interval\r
- * COMPVAL = (RIT_PCLK * time_interval)/1000\r
- * (with time_interval unit is millisecond)
- */\r
- cmp_value = (clock_rate /1000) * time_interval;\r
- RITx->COMPVAL = cmp_value;\r
-\r
- /* Set timer enable clear bit to clear timer to 0 whenever\r
- * counter value equals the contents of RICOMPVAL
- */\r
- RITx->CTRL |= (1<<1);\r
-}\r
-\r
-\r
-/******************************************************************************//*\r
- * @brief Enable/Disable Timer\r
- * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT\r
- * @param[in] NewState New State of this function\r
- * -ENABLE :Enable Timer\r
- * -DISABLE :Disable Timer\r
- * @return None\r
- *******************************************************************************/\r
-void RIT_Cmd(LPC_RITIMER_Type *RITx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_RITx(RITx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- //Enable or Disable Timer\r
- if(NewState==ENABLE)\r
- {\r
- RITx->CTRL |= RIT_CTRL_TEN;\r
- }\r
- else\r
- {\r
- RITx->CTRL &= ~RIT_CTRL_TEN;\r
- }\r
-}\r
-\r
-/******************************************************************************//*\r
- * @brief Timer Enable/Disable on debug\r
- * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT\r
- * @param[in] NewState New State of this function\r
- * -ENABLE :The timer is halted whenever a hardware break condition occurs\r
- * -DISABLE :Hardware break has no effect on the timer operation\r
- * @return None\r
- *******************************************************************************/\r
-void RIT_TimerDebugCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_RITx(RITx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- //Timer Enable/Disable on break\r
- if(NewState==ENABLE)\r
- {\r
- RITx->CTRL |= RIT_CTRL_ENBR;\r
- }\r
- else\r
- {\r
- RITx->CTRL &= ~RIT_CTRL_ENBR;\r
- }\r
-}\r
-/******************************************************************************//*\r
- * @brief Check whether interrupt flag is set or not\r
- * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT\r
- * @return Current interrupt status, could be\r
- * - SET\r
- * - RESET\r
- *******************************************************************************/\r
-IntStatus RIT_GetIntStatus(LPC_RITIMER_Type *RITx)\r
-{\r
- uint8_t result;\r
- CHECK_PARAM(PARAM_RITx(RITx));\r
- if((RITx->CTRL&RIT_CTRL_INTEN)==1) result= SET;\r
- else return RESET;\r
- //clear interrupt flag\r
- RITx->CTRL |= RIT_CTRL_INTEN;\r
- return (IntStatus)result;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _RIT */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_rtc.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_rtc.c\r
-* @brief Contains all functions support for RTC firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup RTC\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_rtc.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _RTC\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup RTC_Public_Functions\r
- * @{\r
- */\r
-\r
-/********************************************************************//**\r
- * @brief Initializes the RTC peripheral.\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @return None\r
- *********************************************************************/\r
-void RTC_Init (LPC_RTC_Type *RTCx)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
-\r
- // Configure clock to RTC\r
- LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Reset 32Khz oscillator\r
- LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k and release reset\r
- LPC_SCU->SFSCLK_0 = 1 | (0x3<<2); // function 1; CGU clk out, pull down\r
- LPC_CGU->BASE_OUT_CLK = (CGU_CLKSRC_32KHZ_OSC<<24) |(1<<11); // base clock out use 32KHz crystal and auto block\r
- do\r
- {\r
- /* Reset RTC clock*/\r
- RTCx->CCR = RTC_CCR_CTCRST | RTC_CCR_CCALEN;\r
- }\r
- while(RTCx->CCR!=(RTC_CCR_CTCRST | RTC_CCR_CCALEN));\r
- do\r
- {\r
- /* Finish resetting RTC clock*/\r
- RTCx->CCR = RTC_CCR_CCALEN;\r
- }\r
- while(RTCx->CCR != RTC_CCR_CCALEN);\r
- /* Clear counter increment and alarm interrupt */\r
- RTCx->ILR = RTC_IRL_RTCCIF | RTC_IRL_RTCALF;\r
- while(RTCx->ILR!=0);\r
- // Clear all register to be default\r
- RTCx->CIIR = 0x00;\r
- RTCx->AMR = 0xFF;\r
- RTCx->CALIBRATION = 0x00;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief De-initializes the RTC peripheral registers to their\r
-* default reset values.\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @return None\r
- **********************************************************************/\r
-void RTC_DeInit(LPC_RTC_Type *RTCx)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
-\r
- RTCx->CCR = 0x00;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Reset clock tick counter in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @return None\r
- **********************************************************************/\r
-void RTC_ResetClockTickCounter(LPC_RTC_Type *RTCx)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
-\r
- RTCx->CCR |= RTC_CCR_CTCRST;\r
- RTCx->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Start/Stop RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] NewState New State of this function, should be:\r
- * - ENABLE :The time counters are enabled\r
- * - DISABLE :The time counters are disabled\r
- * @return None\r
- **********************************************************************/\r
-void RTC_Cmd (LPC_RTC_Type *RTCx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- do\r
- {\r
- RTCx->CCR |= RTC_CCR_CLKEN;\r
- }\r
- while((RTCx->CCR&RTC_CCR_CLKEN)==0);\r
- }\r
- else\r
- {\r
- RTCx->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable Counter increment interrupt for each time type\r
- * in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] CntIncrIntType: Counter Increment Interrupt type,\r
- * an increment of this type value below will generates\r
- * an interrupt, should be:\r
- * - RTC_TIMETYPE_SECOND\r
- * - RTC_TIMETYPE_MINUTE\r
- * - RTC_TIMETYPE_HOUR\r
- * - RTC_TIMETYPE_DAYOFWEEK\r
- * - RTC_TIMETYPE_DAYOFMONTH\r
- * - RTC_TIMETYPE_DAYOFYEAR\r
- * - RTC_TIMETYPE_MONTH\r
- * - RTC_TIMETYPE_YEAR\r
- * @param[in] NewState New State of this function, should be:\r
- * - ENABLE: Counter Increment interrupt for this time type are enabled\r
- * - DISABLE: Counter Increment interrupt for this time type are disabled\r
- * @return None\r
- **********************************************************************/\r
-void RTC_CntIncrIntConfig (LPC_RTC_Type *RTCx, uint32_t CntIncrIntType, \\r
- FunctionalState NewState)\r
-{\r
- uint32_t tem;\r
-\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
- CHECK_PARAM(PARAM_RTC_TIMETYPE(CntIncrIntType));\r
-\r
- switch (CntIncrIntType)\r
- {\r
- case RTC_TIMETYPE_SECOND:\r
- tem = RTC_CIIR_IMSEC;\r
- break;\r
- case RTC_TIMETYPE_MINUTE:\r
- tem = RTC_CIIR_IMMIN;\r
- break;\r
- case RTC_TIMETYPE_HOUR:\r
- tem = RTC_CIIR_IMHOUR;\r
- break;\r
- case RTC_TIMETYPE_DAYOFWEEK:\r
- tem = RTC_CIIR_IMDOW;\r
- break;\r
- case RTC_TIMETYPE_DAYOFMONTH:\r
- tem = RTC_CIIR_IMDOM;\r
- break;\r
- case RTC_TIMETYPE_DAYOFYEAR:\r
- tem = RTC_CIIR_IMDOY;\r
- break;\r
- case RTC_TIMETYPE_MONTH:\r
- tem = RTC_CIIR_IMMON;\r
- break;\r
- case RTC_TIMETYPE_YEAR:\r
- tem = RTC_CIIR_IMYEAR;\r
- break;\r
- }\r
- if (NewState == ENABLE)\r
- {\r
- //do\r
- {\r
- RTCx->CIIR |= tem;\r
- }\r
- //while((RTCx->CIIR & tem)== 0);\r
- }\r
- else\r
- {\r
- //do\r
- {\r
- RTCx->CIIR &= (~tem) & RTC_CIIR_BITMASK;\r
- }\r
- //while(RTCx->CIIR & tem);\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable Alarm interrupt for each time type\r
- * in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] AlarmTimeType: Alarm Time Interrupt type,\r
- * an matching of this type value below with current time\r
- * in RTC will generates an interrupt, should be:\r
- * - RTC_TIMETYPE_SECOND\r
- * - RTC_TIMETYPE_MINUTE\r
- * - RTC_TIMETYPE_HOUR\r
- * - RTC_TIMETYPE_DAYOFWEEK\r
- * - RTC_TIMETYPE_DAYOFMONTH\r
- * - RTC_TIMETYPE_DAYOFYEAR\r
- * - RTC_TIMETYPE_MONTH\r
- * - RTC_TIMETYPE_YEAR\r
- * @param[in] NewState New State of this function, should be:\r
- * - ENABLE: Alarm interrupt for this time type are enabled\r
- * - DISABLE: Alarm interrupt for this time type are disabled\r
- * @return None\r
- **********************************************************************/\r
-void RTC_AlarmIntConfig (LPC_RTC_Type *RTCx, uint32_t AlarmTimeType, \\r
- FunctionalState NewState)\r
-{\r
- uint32_t tem;\r
-\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
- CHECK_PARAM(PARAM_RTC_TIMETYPE(AlarmTimeType));\r
-\r
- switch (AlarmTimeType)\r
- {\r
- case RTC_TIMETYPE_SECOND:\r
- tem = (RTC_AMR_AMRSEC);\r
- break;\r
- case RTC_TIMETYPE_MINUTE:\r
- tem = (RTC_AMR_AMRMIN);\r
- break;\r
- case RTC_TIMETYPE_HOUR:\r
- tem = (RTC_AMR_AMRHOUR);\r
- break;\r
- case RTC_TIMETYPE_DAYOFWEEK:\r
- tem = (RTC_AMR_AMRDOW);\r
- break;\r
- case RTC_TIMETYPE_DAYOFMONTH:\r
- tem = (RTC_AMR_AMRDOM);\r
- break;\r
- case RTC_TIMETYPE_DAYOFYEAR:\r
- tem = (RTC_AMR_AMRDOY);\r
- break;\r
- case RTC_TIMETYPE_MONTH:\r
- tem = (RTC_AMR_AMRMON);\r
- break;\r
- case RTC_TIMETYPE_YEAR:\r
- tem = (RTC_AMR_AMRYEAR);\r
- break;\r
- }\r
- if (NewState == ENABLE)\r
- {\r
- //do\r
- {\r
- RTCx->AMR &= (~tem) & RTC_AMR_BITMASK;\r
- }\r
- //while(RTCx->AMR & tem);\r
- }\r
- else\r
- {\r
- //do\r
- {\r
- RTCx->AMR |= (tem);\r
- }\r
- //while((RTCx->AMR & tem)== 0);\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set current time value for each time type in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] Timetype Time Type, should be:\r
- * - RTC_TIMETYPE_SECOND\r
- * - RTC_TIMETYPE_MINUTE\r
- * - RTC_TIMETYPE_HOUR\r
- * - RTC_TIMETYPE_DAYOFWEEK\r
- * - RTC_TIMETYPE_DAYOFMONTH\r
- * - RTC_TIMETYPE_DAYOFYEAR\r
- * - RTC_TIMETYPE_MONTH\r
- * - RTC_TIMETYPE_YEAR\r
- * @param[in] TimeValue Time value to set\r
- * @return None\r
- **********************************************************************/\r
-void RTC_SetTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t TimeValue)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_RTC_TIMETYPE(Timetype));\r
-\r
- switch ( Timetype)\r
- {\r
- case RTC_TIMETYPE_SECOND:\r
- CHECK_PARAM(TimeValue <= RTC_SECOND_MAX);\r
-\r
- RTCx->SEC = TimeValue & RTC_SEC_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_MINUTE:\r
- CHECK_PARAM(TimeValue <= RTC_MINUTE_MAX);\r
-\r
- RTCx->MIN = TimeValue & RTC_MIN_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_HOUR:\r
- CHECK_PARAM(TimeValue <= RTC_HOUR_MAX);\r
-\r
- RTCx->HRS = TimeValue & RTC_HOUR_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_DAYOFWEEK:\r
- CHECK_PARAM(TimeValue <= RTC_DAYOFWEEK_MAX);\r
-\r
- RTCx->DOW = TimeValue & RTC_DOW_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_DAYOFMONTH:\r
- CHECK_PARAM((TimeValue <= RTC_DAYOFMONTH_MAX) \\r
- && (TimeValue >= RTC_DAYOFMONTH_MIN));\r
-\r
- RTCx->DOM = TimeValue & RTC_DOM_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_DAYOFYEAR:\r
- CHECK_PARAM((TimeValue >= RTC_DAYOFYEAR_MIN) \\r
- && (TimeValue <= RTC_DAYOFYEAR_MAX));\r
-\r
- RTCx->DOY = TimeValue & RTC_DOY_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_MONTH:\r
- CHECK_PARAM((TimeValue >= RTC_MONTH_MIN) \\r
- && (TimeValue <= RTC_MONTH_MAX));\r
-\r
- RTCx->MONTH = TimeValue & RTC_MONTH_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_YEAR:\r
- CHECK_PARAM(TimeValue <= RTC_YEAR_MAX);\r
-\r
- RTCx->YEAR = TimeValue & RTC_YEAR_MASK;\r
- break;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Get current time value for each type time type\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] Timetype Time Type, should be:\r
- * - RTC_TIMETYPE_SECOND\r
- * - RTC_TIMETYPE_MINUTE\r
- * - RTC_TIMETYPE_HOUR\r
- * - RTC_TIMETYPE_DAYOFWEEK\r
- * - RTC_TIMETYPE_DAYOFMONTH\r
- * - RTC_TIMETYPE_DAYOFYEAR\r
- * - RTC_TIMETYPE_MONTH\r
- * - RTC_TIMETYPE_YEAR\r
- * @return Value of time according to specified time type\r
- **********************************************************************/\r
-uint32_t RTC_GetTime(LPC_RTC_Type *RTCx, uint32_t Timetype)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_RTC_TIMETYPE(Timetype));\r
-\r
- switch (Timetype)\r
- {\r
- case RTC_TIMETYPE_SECOND:\r
- return (RTCx->SEC & RTC_SEC_MASK);\r
- case RTC_TIMETYPE_MINUTE:\r
- return (RTCx->MIN & RTC_MIN_MASK);\r
- case RTC_TIMETYPE_HOUR:\r
- return (RTCx->HRS & RTC_HOUR_MASK);\r
- case RTC_TIMETYPE_DAYOFWEEK:\r
- return (RTCx->DOW & RTC_DOW_MASK);\r
- case RTC_TIMETYPE_DAYOFMONTH:\r
- return (RTCx->DOM & RTC_DOM_MASK);\r
- case RTC_TIMETYPE_DAYOFYEAR:\r
- return (RTCx->DOY & RTC_DOY_MASK);\r
- case RTC_TIMETYPE_MONTH:\r
- return (RTCx->MONTH & RTC_MONTH_MASK);\r
- case RTC_TIMETYPE_YEAR:\r
- return (RTCx->YEAR & RTC_YEAR_MASK);\r
- default:\r
- return (0);\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set full of time in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that\r
- * contains time value in full.\r
- * @return None\r
- **********************************************************************/\r
-void RTC_SetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
-\r
- RTCx->DOM = pFullTime->DOM & RTC_DOM_MASK;\r
- RTCx->DOW = pFullTime->DOW & RTC_DOW_MASK;\r
- RTCx->DOY = pFullTime->DOY & RTC_DOY_MASK;\r
- RTCx->HRS = pFullTime->HOUR & RTC_HOUR_MASK;\r
- RTCx->MIN = pFullTime->MIN & RTC_MIN_MASK;\r
- RTCx->SEC = pFullTime->SEC & RTC_SEC_MASK;\r
- RTCx->MONTH = pFullTime->MONTH & RTC_MONTH_MASK;\r
- RTCx->YEAR = pFullTime->YEAR & RTC_YEAR_MASK;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get full of time in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that\r
- * will be stored time in full.\r
- * @return None\r
- **********************************************************************/\r
-void RTC_GetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
-\r
- pFullTime->DOM = RTCx->DOM & RTC_DOM_MASK;\r
- pFullTime->DOW = RTCx->DOW & RTC_DOW_MASK;\r
- pFullTime->DOY = RTCx->DOY & RTC_DOY_MASK;\r
- pFullTime->HOUR = RTCx->HRS & RTC_HOUR_MASK;\r
- pFullTime->MIN = RTCx->MIN & RTC_MIN_MASK;\r
- pFullTime->SEC = RTCx->SEC & RTC_SEC_MASK;\r
- pFullTime->MONTH = RTCx->MONTH & RTC_MONTH_MASK;\r
- pFullTime->YEAR = RTCx->YEAR & RTC_YEAR_MASK;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set alarm time value for each time type\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] Timetype Time Type, should be:\r
- * - RTC_TIMETYPE_SECOND\r
- * - RTC_TIMETYPE_MINUTE\r
- * - RTC_TIMETYPE_HOUR\r
- * - RTC_TIMETYPE_DAYOFWEEK\r
- * - RTC_TIMETYPE_DAYOFMONTH\r
- * - RTC_TIMETYPE_DAYOFYEAR\r
- * - RTC_TIMETYPE_MONTH\r
- * - RTC_TIMETYPE_YEAR\r
- * @param[in] ALValue Alarm time value to set\r
- * @return None\r
- **********************************************************************/\r
-void RTC_SetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t ALValue)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
-\r
- switch (Timetype)\r
- {\r
- case RTC_TIMETYPE_SECOND:\r
- CHECK_PARAM(ALValue <= RTC_SECOND_MAX);\r
-\r
- RTCx->ASEC = ALValue & RTC_SEC_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_MINUTE:\r
- CHECK_PARAM(ALValue <= RTC_MINUTE_MAX);\r
-\r
- RTCx->AMIN = ALValue & RTC_MIN_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_HOUR:\r
- CHECK_PARAM(ALValue <= RTC_HOUR_MAX);\r
-\r
- RTCx->AHRS = ALValue & RTC_HOUR_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_DAYOFWEEK:\r
- CHECK_PARAM(ALValue <= RTC_DAYOFWEEK_MAX);\r
-\r
- RTCx->ADOW = ALValue & RTC_DOW_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_DAYOFMONTH:\r
- CHECK_PARAM((ALValue <= RTC_DAYOFMONTH_MAX) \\r
- && (ALValue >= RTC_DAYOFMONTH_MIN));\r
-\r
- RTCx->ADOM = ALValue & RTC_DOM_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_DAYOFYEAR:\r
- CHECK_PARAM((ALValue >= RTC_DAYOFYEAR_MIN) \\r
- && (ALValue <= RTC_DAYOFYEAR_MAX));\r
-\r
- RTCx->ADOY = ALValue & RTC_DOY_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_MONTH:\r
- CHECK_PARAM((ALValue >= RTC_MONTH_MIN) \\r
- && (ALValue <= RTC_MONTH_MAX));\r
-\r
- RTCx->AMON = ALValue & RTC_MONTH_MASK;\r
- break;\r
-\r
- case RTC_TIMETYPE_YEAR:\r
- CHECK_PARAM(ALValue <= RTC_YEAR_MAX);\r
-\r
- RTCx->AYRS = ALValue & RTC_YEAR_MASK;\r
- break;\r
- }\r
-}\r
-\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get alarm time value for each time type\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] Timetype Time Type, should be:\r
- * - RTC_TIMETYPE_SECOND\r
- * - RTC_TIMETYPE_MINUTE\r
- * - RTC_TIMETYPE_HOUR\r
- * - RTC_TIMETYPE_DAYOFWEEK\r
- * - RTC_TIMETYPE_DAYOFMONTH\r
- * - RTC_TIMETYPE_DAYOFYEAR\r
- * - RTC_TIMETYPE_MONTH\r
- * - RTC_TIMETYPE_YEAR\r
- * @return Value of Alarm time according to specified time type\r
- **********************************************************************/\r
-uint32_t RTC_GetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype)\r
-{\r
- switch (Timetype)\r
- {\r
- case RTC_TIMETYPE_SECOND:\r
- return (RTCx->ASEC & RTC_SEC_MASK);\r
- case RTC_TIMETYPE_MINUTE:\r
- return (RTCx->AMIN & RTC_MIN_MASK);\r
- case RTC_TIMETYPE_HOUR:\r
- return (RTCx->AHRS & RTC_HOUR_MASK);\r
- case RTC_TIMETYPE_DAYOFWEEK:\r
- return (RTCx->ADOW & RTC_DOW_MASK);\r
- case RTC_TIMETYPE_DAYOFMONTH:\r
- return (RTCx->ADOM & RTC_DOM_MASK);\r
- case RTC_TIMETYPE_DAYOFYEAR:\r
- return (RTCx->ADOY & RTC_DOY_MASK);\r
- case RTC_TIMETYPE_MONTH:\r
- return (RTCx->AMON & RTC_MONTH_MASK);\r
- case RTC_TIMETYPE_YEAR:\r
- return (RTCx->AYRS & RTC_YEAR_MASK);\r
- default:\r
- return (0);\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Set full of alarm time in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that\r
- * contains alarm time value in full.\r
- * @return None\r
- **********************************************************************/\r
-void RTC_SetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
-\r
- RTCx->ADOM = pFullTime->DOM & RTC_DOM_MASK;\r
- RTCx->ADOW = pFullTime->DOW & RTC_DOW_MASK;\r
- RTCx->ADOY = pFullTime->DOY & RTC_DOY_MASK;\r
- RTCx->AHRS = pFullTime->HOUR & RTC_HOUR_MASK;\r
- RTCx->AMIN = pFullTime->MIN & RTC_MIN_MASK;\r
- RTCx->ASEC = pFullTime->SEC & RTC_SEC_MASK;\r
- RTCx->AMON = pFullTime->MONTH & RTC_MONTH_MASK;\r
- RTCx->AYRS = pFullTime->YEAR & RTC_YEAR_MASK;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get full of alarm time in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that\r
- * will be stored alarm time in full.\r
- * @return None\r
- **********************************************************************/\r
-void RTC_GetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
-\r
- pFullTime->DOM = RTCx->ADOM & RTC_DOM_MASK;\r
- pFullTime->DOW = RTCx->ADOW & RTC_DOW_MASK;\r
- pFullTime->DOY = RTCx->ADOY & RTC_DOY_MASK;\r
- pFullTime->HOUR = RTCx->AHRS & RTC_HOUR_MASK;\r
- pFullTime->MIN = RTCx->AMIN & RTC_MIN_MASK;\r
- pFullTime->SEC = RTCx->ASEC & RTC_SEC_MASK;\r
- pFullTime->MONTH = RTCx->AMON & RTC_MONTH_MASK;\r
- pFullTime->YEAR = RTCx->AYRS & RTC_YEAR_MASK;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Check whether if specified Location interrupt in\r
- * RTC peripheral is set or not\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] IntType Interrupt location type, should be:\r
- * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.\r
- * - RTC_INT_ALARM: Alarm generated an interrupt.\r
- * @return New state of specified Location interrupt in RTC peripheral\r
- * - SET\r
- * - RESET\r
- **********************************************************************/\r
-IntStatus RTC_GetIntPending (LPC_RTC_Type *RTCx, uint32_t IntType)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_RTC_INT(IntType));\r
-\r
- return ((RTCx->ILR & IntType) ? SET : RESET);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Clear specified Location interrupt pending in\r
- * RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] IntType Interrupt location type, should be:\r
- * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending.\r
- * - RTC_INT_ALARM :Clear alarm interrupt pending\r
- * @return None\r
- **********************************************************************/\r
-void RTC_ClearIntPending (LPC_RTC_Type *RTCx, uint32_t IntType)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_RTC_INT(IntType));\r
-\r
- RTCx->ILR = IntType;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable calibration counter in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] NewState New State of this function, should be:\r
- * - ENABLE :The calibration counter is enabled and counting\r
- * - DISABLE :The calibration counter is disabled and reset to zero\r
- * @return None\r
- **********************************************************************/\r
-void RTC_CalibCounterCmd(LPC_RTC_Type *RTCx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- do\r
- {\r
- RTCx->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK;\r
- }while(RTCx->CCR&RTC_CCR_CCALEN);\r
- }\r
- else\r
- {\r
- RTCx->CCR |= RTC_CCR_CCALEN;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configures Calibration in RTC peripheral\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] CalibValue Calibration value, should be in range from\r
- * 0 to 131,072\r
- * @param[in] CalibDir Calibration Direction, should be:\r
- * - RTC_CALIB_DIR_FORWARD :Forward calibration\r
- * - RTC_CALIB_DIR_BACKWARD :Backward calibration\r
- * @return None\r
- **********************************************************************/\r
-void RTC_CalibConfig(LPC_RTC_Type *RTCx, uint32_t CalibValue, uint8_t CalibDir)\r
-{\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_RTC_CALIB_DIR(CalibDir));\r
- CHECK_PARAM(CalibValue < RTC_CALIBRATION_MAX);\r
-\r
- RTCx->CALIBRATION = ((CalibValue - 1) & RTC_CALIBRATION_CALVAL_MASK) \\r
- | ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Write value to General purpose registers\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] Channel General purpose registers Channel number,\r
- * should be in range from 0 to 63.\r
- * @param[in] Value Value to write\r
- * @return None\r
- * Note: These General purpose registers can be used to store important\r
- * information when the main power supply is off. The value in these\r
- * registers is not affected by chip reset.\r
- **********************************************************************/\r
-void RTC_WriteGPREG (LPC_RTC_Type *RTCx, uint8_t Channel, uint32_t Value)\r
-{\r
- uint32_t *preg;\r
-\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_RTC_GPREG_CH(Channel));\r
-\r
- preg = (uint32_t *)RTC_GPREG_BASE;\r
- preg += Channel;\r
- *preg = Value;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Read value from General purpose registers\r
- * @param[in] RTCx RTC peripheral selected, should be LPC_RTC\r
- * @param[in] Channel General purpose registers Channel number,\r
- * should be in range from 0 to 4.\r
- * @return Read Value\r
- * Note: These General purpose registers can be used to store important\r
- * information when the main power supply is off. The value in these\r
- * registers is not affected by chip reset.\r
- **********************************************************************/\r
-uint32_t RTC_ReadGPREG (LPC_RTC_Type *RTCx, uint8_t Channel)\r
-{\r
- uint32_t *preg;\r
- uint32_t value;\r
-\r
- CHECK_PARAM(PARAM_RTCx(RTCx));\r
- CHECK_PARAM(PARAM_RTC_GPREG_CH(Channel));\r
-\r
- preg = (uint32_t *)RTC_GPREG_BASE;\r
- preg += Channel;\r
- value = *preg;\r
- return (value);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _RTC */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_sct.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_sct.c\r
-* @brief Contains all functions support for SCT firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup SCT\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_sct.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _SCT\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup SCT_Public_Functions\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief Select 16/32 bit SCT counter\r
- * @param[in] value configuration value for SCT\r
- * - SCT_CONFIG_16BIT_COUNTER :16-bit counter\r
- * - SCT_CONFIG_32BIT_COUNTER :32-bit counter\r
- * @return None\r
- **********************************************************************/\r
-void SCT_Config(uint32_t value)\r
-{\r
- CHECK_PARAM(PARAM_SCT_CONFIG_COUNTER_TYPE(value));\r
-\r
- LPC_SCT->CONFIG = value;\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Setting SCT control\r
-* @param[in] value setting value\r
-* @param[in] ena Enable/disable status\r
-* - ENABLE\r
-* - DISABLE\r
-* @return None\r
-**********************************************************************/\r
-void SCT_ControlSet(uint32_t value, FunctionalState ena)\r
-{\r
- uint32_t tem;\r
-\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(ena));\r
-\r
- tem = LPC_SCT->CTRL_U;\r
-\r
- if(ena == ENABLE)\r
- {\r
- tem |= value;\r
- }\r
- else\r
- {\r
- tem &= (~value);\r
- }\r
-\r
- LPC_SCT->CTRL_U = tem;\r
-\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Set start mode for ADC\r
-* @param[in] outnum number of SCT output, should be: 0..15\r
-* @param[in] value solution value, should be\r
-* - SCT_RES_NOCHANGE :No change\r
-* - SCT_RES_SET_OUTPUT :Set output\r
-* - SCT_RES_CLEAR_OUTPUT :Clear output\r
-* - SCT_RES_TOGGLE_OUTPUT :Toggle output\r
-* @return None\r
-*********************************************************************/\r
-void SCT_ConflictResolutionSet(uint8_t outnum, uint8_t value)\r
-{\r
- uint32_t tem;\r
-\r
- CHECK_PARAM(PARAM_SCT_OUTPUT_NUM(outnum));\r
- CHECK_PARAM(PARAM_SCT_RES(value));\r
-\r
- tem = LPC_SCT->RES;\r
- tem &= ~(0x03 << (2*outnum));\r
- tem |= (value << (2*outnum));\r
- LPC_SCT->RES = tem;\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Clear SCT event generating interrupt request\r
-* @param[in] even_num SCT event number, should be: 0..15\r
-* @return None\r
-*********************************************************************/\r
-void SCT_EventFlagClear(uint8_t even_num)\r
-{\r
- CHECK_PARAM(PARAM_SCT_EVENT(even_num));\r
-\r
- LPC_SCT->EVFLAG = (1 << (even_num));\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _SCT */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_scu.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_scu.c\r
-* @brief Contains all functions support for SCU firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup SCU\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "LPC18xx.h" /* LPC18xx definitions */\r
-#include "lpc_types.h"\r
-#include "lpc18xx_scu.h"\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configure pin function\r
- * @param[in] port Port number, should be: 0..15\r
- * @param[in] pin Pin number, should be: 0..31\r
- * @param[in] mode Pin mode, should be:\r
- * - MD_PUP :Pull-up enabled\r
- * - MD_BUK :Plain input\r
- * - MD_PLN :Repeater mode\r
- * - MD_PDN :Pull-down enabled\r
- * @param[in] func Function mode, should be:\r
- * - FUNC0 :Function 0\r
- * - FUNC1 :Function 1\r
- * - FUNC2 :Function 2\r
- * - FUNC3 :Function 3\r
- * @return None\r
- **********************************************************************/\r
-void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func)\r
-{\r
- uint32_t * scu_base=(uint32_t*)(LPC_SCU_BASE);\r
- scu_base[(PORT_OFFSET*port+PIN_OFFSET*pin)/4]=mode+func;\r
-} /* scu_pinmux */\r
-\r
-/**\r
- * @}\r
- */\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_ssp.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_ssp.c\r
-* @brief Contains all functions support for SSP firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup SSP\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_ssp.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _SSP\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup SSP_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup SSP_Public_Functions\r
- * @{\r
- */\r
-\r
-/********************************************************************//**\r
- * @brief Initializes the SSPx peripheral according to the specified\r
- * parameters in the SSP_ConfigStruct.\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] SSP_ConfigStruct Pointer to a SSP_CFG_Type structure that\r
- * contains the configuration information for the specified\r
- * SSP peripheral.\r
- * @return None\r
- *********************************************************************/\r
-void SSP_Init(LPC_SSPn_Type *SSPx, SSP_CFG_Type *SSP_ConfigStruct)\r
-{\r
- uint32_t tmp;\r
- uint32_t prescale, cr0_div, cmp_clk, ssp_clk;\r
-\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
-\r
- if(SSPx == LPC_SSP0) {\r
- /* Set up clock and power for SSP0 module */\r
- //LPC_CGU->BASE_SSP0_CLK = (SRC_PL160M_0<<24) | (1<<11);\r
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_SSP0);\r
- } else if(SSPx == LPC_SSP1) {\r
- /* Set up clock and power for SSP1 module */\r
- //LPC_CGU->BASE_SSP1_CLK = (SRC_PL160M_0<<24) | (1<<11);\r
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_SSP1);\r
- } else {\r
- return;\r
- }\r
-\r
- /* Configure SSP, interrupt is disable, LoopBack mode is disable,\r
- * SSP is disable, Slave output is disable as default\r
- */\r
- tmp = ((SSP_ConfigStruct->CPHA) | (SSP_ConfigStruct->CPOL) \\r
- | (SSP_ConfigStruct->FrameFormat) | (SSP_ConfigStruct->Databit))\r
- & SSP_CR0_BITMASK;\r
- // write back to SSP control register\r
- SSPx->CR0 = tmp;\r
-\r
- tmp = SSP_ConfigStruct->Mode & SSP_CR1_BITMASK;\r
- // Write back to CR1\r
- SSPx->CR1 = tmp;\r
-\r
- // Set clock rate for SSP peripheral\r
- if(SSPx == LPC_SSP0)\r
- ssp_clk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_SSP0);\r
- else\r
- ssp_clk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_SSP1);\r
- cr0_div = 0;\r
- cmp_clk = 0xFFFFFFFF;\r
- prescale = 2;\r
- while (cmp_clk > SSP_ConfigStruct->ClockRate)\r
- {\r
- cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);\r
- if (cmp_clk > SSP_ConfigStruct->ClockRate)\r
- {\r
- cr0_div++;\r
- if (cr0_div > 0xFF)\r
- {\r
- cr0_div = 0;\r
- prescale += 2;\r
- }\r
- }\r
- }\r
-\r
- /* Write computed prescaler and divider back to register */\r
- SSPx->CR0 &= (~SSP_CR0_SCR(0xFF)) & SSP_CR0_BITMASK;\r
- SSPx->CR0 |= (SSP_CR0_SCR(cr0_div)) & SSP_CR0_BITMASK;\r
- SSPx->CPSR = prescale & SSP_CPSR_BITMASK;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief De-initializes the SSPx peripheral registers to their\r
- * default reset values.\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @return None\r
- **********************************************************************/\r
-void SSP_DeInit(LPC_SSPn_Type* SSPx)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
-\r
- /* Disable SSP operation*/\r
- SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;\r
-}\r
-\r
-/*****************************************************************************//**\r
- * @brief Get data size bit selected\r
- * @param[in] SSPx pointer to LPC_SSPn_Type structure, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @return Data size, could be:\r
- * - SSP_DATABIT_4 :4 bit transfer\r
- * - SSP_DATABIT_5 :5 bit transfer\r
- * ...\r
- * - SSP_DATABIT_16 :16 bit transfer\r
-*******************************************************************************/\r
-uint8_t SSP_GetDataSize(LPC_SSPn_Type* SSPx)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- return (SSPx->CR0 & (0xF));\r
-}\r
-\r
-/*****************************************************************************//**\r
- * @brief Fills each SSP_InitStruct member with its default value:\r
- * - CPHA = SSP_CPHA_FIRST\r
- * - CPOL = SSP_CPOL_HI\r
- * - ClockRate = 1000000\r
- * - Databit = SSP_DATABIT_8\r
- * - Mode = SSP_MASTER_MODE\r
- * - FrameFormat = SSP_FRAME_SSP\r
- * @param[in] SSP_InitStruct Pointer to a SSP_CFG_Type structure which will be\r
- * initialized.\r
- * @return None\r
- *******************************************************************************/\r
-void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct)\r
-{\r
- SSP_InitStruct->CPHA = SSP_CPHA_FIRST;\r
- SSP_InitStruct->CPOL = SSP_CPOL_HI;\r
- SSP_InitStruct->ClockRate = 100000;\r
- SSP_InitStruct->Databit = SSP_DATABIT_8;\r
- SSP_InitStruct->Mode = SSP_MASTER_MODE;\r
- SSP_InitStruct->FrameFormat = SSP_FRAME_SPI;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable or disable SSP peripheral's operation\r
- * @param[in] SSPx SSP peripheral, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] NewState New State of SSPx peripheral's operation, should be:\r
- * - ENABLE\r
- * - DISABLE\r
- * @return none\r
- **********************************************************************/\r
-void SSP_Cmd(LPC_SSPn_Type* SSPx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- SSPx->CR1 |= SSP_CR1_SSP_EN;\r
- }\r
- else\r
- {\r
- SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable or disable Loop Back mode function in SSP peripheral\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] NewState New State of Loop Back mode, should be:\r
- * - ENABLE\r
- * - DISABLE\r
- * @return None\r
- **********************************************************************/\r
-void SSP_LoopBackCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- SSPx->CR1 |= SSP_CR1_LBM_EN;\r
- }\r
- else\r
- {\r
- SSPx->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable or disable Slave Output function in SSP peripheral\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] NewState New State of Slave Output function, should be:\r
- * - ENABLE :Slave Output in normal operation\r
- * - DISABLE :Slave Output is disabled. This blocks\r
- * SSP controller from driving the transmit data line (MISO)\r
- * Note: This function is available when SSP peripheral in Slave mode\r
- * @return None\r
- **********************************************************************/\r
-void SSP_SlaveOutputCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- SSPx->CR1 &= (~SSP_CR1_SO_DISABLE) & SSP_CR1_BITMASK;\r
- }\r
- else\r
- {\r
- SSPx->CR1 |= SSP_CR1_SO_DISABLE;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Transmit a single data through SSPx peripheral\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] Data Data to transmit (must be 16 or 8-bit long, this\r
- * depend on SSP data bit number configured)\r
- * @return none\r
- **********************************************************************/\r
-void SSP_SendData(LPC_SSPn_Type* SSPx, uint16_t Data)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
-\r
- SSPx->DR = SSP_DR_BITMASK(Data);\r
-}\r
-\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Receive a single data from SSPx peripheral\r
- * @param[in] SSPx SSP peripheral selected, should be\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @return Data received (16-bit long)\r
- **********************************************************************/\r
-uint16_t SSP_ReceiveData(LPC_SSPn_Type* SSPx)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
-\r
- return ((uint16_t) (SSP_DR_BITMASK(SSPx->DR)));\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief SSP Read write data function\r
- * @param[in] SSPx Pointer to SSP peripheral, should be\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] dataCfg Pointer to a SSP_DATA_SETUP_Type structure that\r
- * contains specified information about transmit data\r
- * configuration.\r
- * @param[in] xfType Transfer type, should be:\r
- * - SSP_TRANSFER_POLLING :Polling mode\r
- * - SSP_TRANSFER_INTERRUPT :Interrupt mode\r
- * @return Actual Data length has been transferred in polling mode.\r
- * In interrupt mode, always return (0)\r
- * Return (-1) if error.\r
- * Note: This function can be used in both master and slave mode.\r
- ***********************************************************************/\r
-int32_t SSP_ReadWrite (LPC_SSPn_Type *SSPx, SSP_DATA_SETUP_Type *dataCfg, \\r
- SSP_TRANSFER_Type xfType)\r
-{\r
- uint8_t *rdata8;\r
- uint8_t *wdata8;\r
- uint16_t *rdata16;\r
- uint16_t *wdata16;\r
- uint32_t stat;\r
- uint32_t tmp;\r
- int32_t dataword;\r
-\r
- dataCfg->rx_cnt = 0;\r
- dataCfg->tx_cnt = 0;\r
- dataCfg->status = 0;\r
-\r
-\r
- /* Clear all remaining data in RX FIFO */\r
- while (SSPx->SR & SSP_SR_RNE){\r
- tmp = (uint32_t) SSP_ReceiveData(SSPx);\r
- }\r
-\r
- // Clear status\r
- SSPx->ICR = SSP_ICR_BITMASK;\r
- if(SSP_GetDataSize(SSPx)>8)\r
- dataword = 1;\r
- else dataword = 0;\r
-\r
- // Polling mode ----------------------------------------------------------------------\r
- if (xfType == SSP_TRANSFER_POLLING){\r
- if (dataword == 0){\r
- rdata8 = (uint8_t *)dataCfg->rx_data;\r
- wdata8 = (uint8_t *)dataCfg->tx_data;\r
- } else {\r
- rdata16 = (uint16_t *)dataCfg->rx_data;\r
- wdata16 = (uint16_t *)dataCfg->tx_data;\r
- }\r
- while ((dataCfg->tx_cnt < dataCfg->length) || (dataCfg->rx_cnt < dataCfg->length)){\r
- if ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt != dataCfg->length)){\r
- // Write data to buffer\r
- if(dataCfg->tx_data == NULL){\r
- if (dataword == 0){\r
- SSP_SendData(SSPx, 0xFF);\r
- dataCfg->tx_cnt++;\r
- } else {\r
- SSP_SendData(SSPx, 0xFFFF);\r
- dataCfg->tx_cnt += 2;\r
- }\r
- } else {\r
- if (dataword == 0){\r
- SSP_SendData(SSPx, *wdata8);\r
- wdata8++;\r
- dataCfg->tx_cnt++;\r
- } else {\r
- SSP_SendData(SSPx, *wdata16);\r
- wdata16++;\r
- dataCfg->tx_cnt += 2;\r
- }\r
- }\r
- }\r
-\r
- // Check overrun error\r
- if ((stat = SSPx->RIS) & SSP_RIS_ROR){\r
- // save status and return\r
- dataCfg->status = stat | SSP_STAT_ERROR;\r
- return (-1);\r
- }\r
-\r
- // Check for any data available in RX FIFO\r
- while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){\r
- // Read data from SSP data\r
- tmp = SSP_ReceiveData(SSPx);\r
-\r
- // Store data to destination\r
- if (dataCfg->rx_data != NULL)\r
- {\r
- if (dataword == 0){\r
- *(rdata8) = (uint8_t) tmp;\r
- rdata8++;\r
- } else {\r
- *(rdata16) = (uint16_t) tmp;\r
- rdata16++;\r
- }\r
- }\r
- // Increase counter\r
- if (dataword == 0){\r
- dataCfg->rx_cnt++;\r
- } else {\r
- dataCfg->rx_cnt += 2;\r
- }\r
- }\r
- }\r
-\r
- // save status\r
- dataCfg->status = SSP_STAT_DONE;\r
-\r
- if (dataCfg->tx_data != NULL){\r
- return dataCfg->tx_cnt;\r
- } else if (dataCfg->rx_data != NULL){\r
- return dataCfg->rx_cnt;\r
- } else {\r
- return (0);\r
- }\r
- }\r
-\r
- // Interrupt mode ----------------------------------------------------------------------\r
- else if (xfType == SSP_TRANSFER_INTERRUPT){\r
-\r
- while ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt < dataCfg->length)){\r
- // Write data to buffer\r
- if(dataCfg->tx_data == NULL){\r
- if (dataword == 0){\r
- SSP_SendData(SSPx, 0xFF);\r
- dataCfg->tx_cnt++;\r
- } else {\r
- SSP_SendData(SSPx, 0xFFFF);\r
- dataCfg->tx_cnt += 2;\r
- }\r
- } else {\r
- if (dataword == 0){\r
- SSP_SendData(SSPx, (*(uint8_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));\r
- dataCfg->tx_cnt++;\r
- } else {\r
- SSP_SendData(SSPx, (*(uint16_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));\r
- dataCfg->tx_cnt += 2;\r
- }\r
- }\r
-\r
- // Check error\r
- if ((stat = SSPx->RIS) & SSP_RIS_ROR){\r
- // save status and return\r
- dataCfg->status = stat | SSP_STAT_ERROR;\r
- return (-1);\r
- }\r
-\r
- // Check for any data available in RX FIFO\r
- while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){\r
- // Read data from SSP data\r
- tmp = SSP_ReceiveData(SSPx);\r
-\r
- // Store data to destination\r
- if (dataCfg->rx_data != NULL)\r
- {\r
- if (dataword == 0){\r
- *(uint8_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint8_t) tmp;\r
- } else {\r
- *(uint16_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint16_t) tmp;\r
- }\r
- }\r
- // Increase counter\r
- if (dataword == 0){\r
- dataCfg->rx_cnt++;\r
- } else {\r
- dataCfg->rx_cnt += 2;\r
- }\r
- }\r
- }\r
-\r
- // If there more data to sent or receive\r
- if ((dataCfg->rx_cnt != dataCfg->length) || (dataCfg->tx_cnt < dataCfg->length)){\r
- // Enable all interrupt\r
- SSPx->IMSC = SSP_IMSC_BITMASK;\r
- } else {\r
- // Save status\r
- dataCfg->status = SSP_STAT_DONE;\r
- }\r
- return (0);\r
- }\r
-\r
- return (-1);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Checks whether the specified SSP status flag is set or not\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] FlagType Type of flag to check status, should be:\r
- * - SSP_STAT_TXFIFO_EMPTY :TX FIFO is empty\r
- * - SSP_STAT_TXFIFO_NOTFULL :TX FIFO is not full\r
- * - SSP_STAT_RXFIFO_NOTEMPTY :RX FIFO is not empty\r
- * - SSP_STAT_RXFIFO_FULL :RX FIFO is full\r
- * - SSP_STAT_BUSY :SSP peripheral is busy\r
- * @return New State of specified SSP status flag\r
- **********************************************************************/\r
-FlagStatus SSP_GetStatus(LPC_SSPn_Type* SSPx, uint32_t FlagType)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- CHECK_PARAM(PARAM_SSP_STAT(FlagType));\r
-\r
- return ((SSPx->SR & FlagType) ? SET : RESET);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable or disable specified interrupt type in SSP peripheral\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] IntType Interrupt type in SSP peripheral, should be:\r
- * - SSP_INTCFG_ROR :Receive Overrun interrupt\r
- * - SSP_INTCFG_RT :Receive Time out interrupt\r
- * - SSP_INTCFG_RX :RX FIFO is at least half full interrupt\r
- * - SSP_INTCFG_TX :TX FIFO is at least half empty interrupt\r
- * @param[in] NewState New State of specified interrupt type, should be:\r
- * - ENABLE :Enable this interrupt type\r
- * - DISABLE :Disable this interrupt type\r
- * @return None\r
- **********************************************************************/\r
-void SSP_IntConfig(LPC_SSPn_Type *SSPx, uint32_t IntType, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- CHECK_PARAM(PARAM_SSP_INTCFG(IntType));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- SSPx->IMSC |= IntType;\r
- }\r
- else\r
- {\r
- SSPx->IMSC &= (~IntType) & SSP_IMSC_BITMASK;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Check whether the specified Raw interrupt status flag is\r
- * set or not\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] RawIntType Raw Interrupt Type, should be:\r
- * - SSP_INTSTAT_RAW_ROR :Receive Overrun interrupt\r
- * - SSP_INTSTAT_RAW_RT :Receive Time out interrupt\r
- * - SSP_INTSTAT_RAW_RX :RX FIFO is at least half full interrupt\r
- * - SSP_INTSTAT_RAW_TX :TX FIFO is at least half empty interrupt\r
- * @return New State of specified Raw interrupt status flag in SSP peripheral\r
- * Note: Enabling/Disabling specified interrupt in SSP peripheral does not\r
- * effect to Raw Interrupt Status flag.\r
- **********************************************************************/\r
-IntStatus SSP_GetRawIntStatus(LPC_SSPn_Type *SSPx, uint32_t RawIntType)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- CHECK_PARAM(PARAM_SSP_INTSTAT_RAW(RawIntType));\r
-\r
- return ((SSPx->RIS & RawIntType) ? SET : RESET);\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Check whether the specified interrupt status flag is\r
- * set or not\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] IntType Raw Interrupt Type, should be:\r
- * - SSP_INTSTAT_ROR :Receive Overrun interrupt\r
- * - SSP_INTSTAT_RT :Receive Time out interrupt\r
- * - SSP_INTSTAT_RX :RX FIFO is at least half full interrupt\r
- * - SSP_INTSTAT_TX :TX FIFO is at least half empty interrupt\r
- * @return New State of specified interrupt status flag in SSP peripheral\r
- * Note: Enabling/Disabling specified interrupt in SSP peripheral effects\r
- * to Interrupt Status flag.\r
- **********************************************************************/\r
-IntStatus SSP_GetIntStatus (LPC_SSPn_Type *SSPx, uint32_t IntType)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- CHECK_PARAM(PARAM_SSP_INTSTAT(IntType));\r
-\r
- return ((SSPx->MIS & IntType) ? SET :RESET);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Clear specified interrupt pending in SSP peripheral\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] IntType Interrupt pending to clear, should be:\r
- * - SSP_INTCLR_ROR :clears the "frame was received when\r
- * RxFIFO was full" interrupt.\r
- * - SSP_INTCLR_RT :clears the "Rx FIFO was not empty and\r
- * has not been read for a timeout period" interrupt.\r
- * @return None\r
- **********************************************************************/\r
-void SSP_ClearIntPending(LPC_SSPn_Type *SSPx, uint32_t IntType)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- CHECK_PARAM(PARAM_SSP_INTCLR(IntType));\r
-\r
- SSPx->ICR = IntType;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable DMA function for SSP peripheral\r
- * @param[in] SSPx SSP peripheral selected, should be:\r
- * - LPC_SSP0 :SSP0 peripheral\r
- * - LPC_SSP1 :SSP1 peripheral\r
- * @param[in] DMAMode Type of DMA, should be:\r
- * - SSP_DMA_TX :DMA for the transmit FIFO\r
- * - SSP_DMA_RX :DMA for the Receive FIFO\r
- * @param[in] NewState New State of DMA function on SSP peripheral,\r
- * should be:\r
- * - ENALBE :Enable this function\r
- * - DISABLE :Disable this function\r
- * @return None\r
- **********************************************************************/\r
-void SSP_DMACmd(LPC_SSPn_Type *SSPx, uint32_t DMAMode, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_SSPx(SSPx));\r
- CHECK_PARAM(PARAM_SSP_DMA(DMAMode));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- SSPx->DMACR |= DMAMode;\r
- }\r
- else\r
- {\r
- SSPx->DMACR &= (~DMAMode) & SSP_DMA_BITMASK;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _SSP */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_timer.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_timer.c\r
-* @brief Contains all functions support for Timer firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup TIMER\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_timer.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-#ifdef _TIM\r
-\r
-/* Private Functions ---------------------------------------------------------- */\r
-\r
-static uint32_t getPClock (uint32_t timernum);\r
-static uint32_t converUSecToVal (uint32_t timernum, uint32_t usec);\r
-static uint32_t converPtrToTimeNum (LPC_TIMERn_Type *TIMx);\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get peripheral clock of each timer controller\r
- * @param[in] timernum Timer number, should be: 0..3\r
- * @return Peripheral clock of timer\r
- **********************************************************************/\r
-extern uint32_t M3Frequency;\r
-static uint32_t getPClock (uint32_t timernum)\r
-{\r
- uint32_t clkdlycnt;\r
- switch (timernum)\r
- {\r
- case 0:\r
- clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER0)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER0);\r
- break;\r
-\r
- case 1:\r
- clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER1)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER1);\r
- break;\r
-\r
- case 2:\r
- clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER2)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER2);\r
- break;\r
-\r
- case 3:\r
- clkdlycnt = /*CGU_GetPCLK (CGU_PCLKSEL_TIMER3)*/ CGU_GetPCLKFrequency(CGU_PERIPHERAL_TIMER3);\r
- break;\r
- }\r
- return clkdlycnt;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Convert a time to a timer count value\r
- * @param[in] timernum Timer number, should be: 0..3\r
- * @param[in] usec Time in microseconds\r
- * @return The number of required clock ticks to give the time delay\r
- **********************************************************************/\r
-uint32_t converUSecToVal (uint32_t timernum, uint32_t usec)\r
-{\r
- uint64_t clkdlycnt;\r
-\r
- // Get Pclock of timer\r
- clkdlycnt = (uint64_t) getPClock(timernum);\r
-\r
- clkdlycnt = (clkdlycnt * usec) / 1000000;\r
- return (uint32_t) clkdlycnt;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Convert a timer register pointer to a timer number\r
- * @param[in] TIMx Pointer to LPC_TIMERn_Type, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @return The timer number (0 to 3) or -1 if register pointer is bad\r
- **********************************************************************/\r
-uint32_t converPtrToTimeNum (LPC_TIMERn_Type *TIMx)\r
-{\r
- uint32_t tnum = 0xFFFFFFFF;\r
-\r
- if (TIMx == LPC_TIMER0)\r
- {\r
- tnum = 0;\r
- }\r
- else if (TIMx == LPC_TIMER1)\r
- {\r
- tnum = 1;\r
- }\r
- else if (TIMx == LPC_TIMER2)\r
- {\r
- tnum = 2;\r
- }\r
- else if (TIMx == LPC_TIMER3)\r
- {\r
- tnum = 3;\r
- }\r
-\r
- return tnum;\r
-}\r
-\r
-/* End of Private Functions ---------------------------------------------------- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup TIM_Public_Functions\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
- * @brief Get Interrupt Status\r
- * @param[in] TIMx Timer selection, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] IntFlag: interrupt type, should be:\r
- * - TIM_MR0_INT :Interrupt for Match channel 0\r
- * - TIM_MR1_INT :Interrupt for Match channel 1\r
- * - TIM_MR2_INT :Interrupt for Match channel 2\r
- * - TIM_MR3_INT :Interrupt for Match channel 3\r
- * - TIM_CR0_INT :Interrupt for Capture channel 0\r
- * - TIM_CR1_INT :Interrupt for Capture channel 1\r
- * @return FlagStatus\r
- * - SET :interrupt\r
- * - RESET :no interrupt\r
- **********************************************************************/\r
-FlagStatus TIM_GetIntStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag)\r
-{\r
- uint8_t temp;\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));\r
- temp = (TIMx->IR)& TIM_IR_CLR(IntFlag);\r
- if (temp)\r
- return SET;\r
-\r
- return RESET;\r
-\r
-}\r
-/*********************************************************************//**\r
- * @brief Get Capture Interrupt Status\r
- * @param[in] TIMx Timer selection, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] IntFlag: interrupt type, should be:\r
- * - TIM_MR0_INT :Interrupt for Match channel 0\r
- * - TIM_MR1_INT :Interrupt for Match channel 1\r
- * - TIM_MR2_INT :Interrupt for Match channel 2\r
- * - TIM_MR3_INT :Interrupt for Match channel 3\r
- * - TIM_CR0_INT :Interrupt for Capture channel 0\r
- * - TIM_CR1_INT :Interrupt for Capture channel 1\r
- * @return FlagStatus\r
- * - SET :interrupt\r
- * - RESET :no interrupt\r
- **********************************************************************/\r
-FlagStatus TIM_GetIntCaptureStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag)\r
-{\r
- uint8_t temp;\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));\r
- temp = (TIMx->IR) & (1<<(4+IntFlag));\r
- if(temp)\r
- return SET;\r
- return RESET;\r
-}\r
-/*********************************************************************//**\r
- * @brief Clear Interrupt pending\r
- * @param[in] TIMx Timer selection, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] IntFlag: interrupt type, should be:\r
- * - TIM_MR0_INT :Interrupt for Match channel 0\r
- * - TIM_MR1_INT :Interrupt for Match channel 1\r
- * - TIM_MR2_INT :Interrupt for Match channel 2\r
- * - TIM_MR3_INT :Interrupt for Match channel 3\r
- * - TIM_CR0_INT :Interrupt for Capture channel 0\r
- * - TIM_CR1_INT :Interrupt for Capture channel 1\r
- * @return None\r
- **********************************************************************/\r
-void TIM_ClearIntPending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag)\r
-{\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));\r
- TIMx->IR = TIM_IR_CLR(IntFlag);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Clear Capture Interrupt pending\r
- * @param[in] TIMx Timer selection, should be\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] IntFlag interrupt type, should be:\r
- * - TIM_MR0_INT :Interrupt for Match channel 0\r
- * - TIM_MR1_INT :Interrupt for Match channel 1\r
- * - TIM_MR2_INT :Interrupt for Match channel 2\r
- * - TIM_MR3_INT :Interrupt for Match channel 3\r
- * - TIM_CR0_INT :Interrupt for Capture channel 0\r
- * - TIM_CR1_INT :Interrupt for Capture channel 1\r
- * @return None\r
- **********************************************************************/\r
-void TIM_ClearIntCapturePending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag)\r
-{\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));\r
- TIMx->IR = (1<<(4+IntFlag));\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Configuration for Timer at initial time\r
- * @param[in] TimerCounterMode timer counter mode, should be:\r
- * - TIM_TIMER_MODE :Timer mode\r
- * - TIM_COUNTER_RISING_MODE :Counter rising mode\r
- * - TIM_COUNTER_FALLING_MODE :Counter falling mode\r
- * - TIM_COUNTER_ANY_MODE :Counter on both edges\r
- * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type or\r
- * TIM_COUNTERCFG_Type\r
- * @return None\r
- **********************************************************************/\r
-void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct)\r
-{\r
- if (TimerCounterMode == TIM_TIMER_MODE )\r
- {\r
- TIM_TIMERCFG_Type * pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;\r
- pTimeCfg->PrescaleOption = TIM_PRESCALE_USVAL;\r
- pTimeCfg->PrescaleValue = 1;\r
- }\r
- else\r
- {\r
- TIM_COUNTERCFG_Type * pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;\r
- pCounterCfg->CountInputSelect = TIM_COUNTER_INCAP0;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Initial Timer/Counter device\r
- * Set Clock frequency for Timer\r
- * Set initial configuration for Timer\r
- * @param[in] TIMx Timer selection, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] TimerCounterMode Timer counter mode, should be:\r
- * - TIM_TIMER_MODE :Timer mode\r
- * - TIM_COUNTER_RISING_MODE :Counter rising mode\r
- * - TIM_COUNTER_FALLING_MODE :Counter falling mode\r
- * - TIM_COUNTER_ANY_MODE :Counter on both edges\r
- * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type\r
- * that contains the configuration information for the\r
- * specified Timer peripheral.\r
- * @return None\r
- **********************************************************************/\r
-void TIM_Init(LPC_TIMERn_Type *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct)\r
-{\r
- TIM_TIMERCFG_Type *pTimeCfg;\r
- TIM_COUNTERCFG_Type *pCounterCfg;\r
-\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- CHECK_PARAM(PARAM_TIM_MODE_OPT(TimerCounterMode));\r
-\r
- //set power\r
- if (TIMx== LPC_TIMER0)\r
- {\r
-\r
- }\r
- else if (TIMx== LPC_TIMER1)\r
- {\r
-\r
- }\r
-\r
- else if (TIMx== LPC_TIMER2)\r
- {\r
-\r
- }\r
- else if (TIMx== LPC_TIMER3)\r
- {\r
-\r
- }\r
-\r
- TIMx->CCR &= ~TIM_CTCR_MODE_MASK;\r
- TIMx->CCR |= TIM_TIMER_MODE;\r
-\r
- TIMx->TC =0;\r
- TIMx->PC =0;\r
- TIMx->PR =0;\r
- TIMx->TCR |= (1<<1); //Reset Counter\r
- TIMx->TCR &= ~(1<<1); //release reset\r
- if (TimerCounterMode == TIM_TIMER_MODE )\r
- {\r
- pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;\r
- if (pTimeCfg->PrescaleOption == TIM_PRESCALE_TICKVAL)\r
- {\r
- TIMx->PR = pTimeCfg->PrescaleValue -1 ;\r
- }\r
- else\r
- {\r
- TIMx->PR = converUSecToVal (converPtrToTimeNum(TIMx),pTimeCfg->PrescaleValue)-1;\r
- }\r
- }\r
- else\r
- {\r
-\r
- pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;\r
- TIMx->CCR &= ~TIM_CTCR_INPUT_MASK;\r
- if (pCounterCfg->CountInputSelect == TIM_COUNTER_INCAP1)\r
- TIMx->CCR |= _BIT(2);\r
- }\r
-\r
- // Clear interrupt pending\r
- TIMx->IR = 0xFFFFFFFF;\r
-\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Close Timer/Counter device\r
- * @param[in] TIMx Pointer to timer device, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @return None\r
- **********************************************************************/\r
-void TIM_DeInit (LPC_TIMERn_Type *TIMx)\r
-{\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- // Disable timer/counter\r
- TIMx->TCR = 0x00;\r
-\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Start/Stop Timer/Counter device\r
- * @param[in] TIMx Pointer to timer device, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] NewState\r
- * - ENABLE :Set timer enable\r
- * - DISABLE :Disable timer\r
- * @return None\r
- **********************************************************************/\r
-void TIM_Cmd(LPC_TIMERn_Type *TIMx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- if (NewState == ENABLE)\r
- {\r
- TIMx->TCR |= TIM_ENABLE;\r
- }\r
- else\r
- {\r
- TIMx->TCR &= ~TIM_ENABLE;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Reset Timer/Counter device,\r
- * Make TC and PC are synchronously reset on the next\r
- * positive edge of PCLK\r
- * @param[in] TIMx Pointer to timer device, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @return None\r
- **********************************************************************/\r
-void TIM_ResetCounter(LPC_TIMERn_Type *TIMx)\r
-{\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- TIMx->TCR |= TIM_RESET;\r
- TIMx->TCR &= ~TIM_RESET;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Configuration for Match register\r
- * @param[in] TIMx Pointer to timer device, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] TIM_MatchConfigStruct Pointer to TIM_MATCHCFG_Type\r
- * - MatchChannel : choose channel 0 or 1\r
- * - IntOnMatch : if SET, interrupt will be generated when MRxx match\r
- * the value in TC\r
- * - StopOnMatch : if SET, TC and PC will be stopped whenM Rxx match\r
- * the value in TC\r
- * - ResetOnMatch : if SET, Reset on MR0 when MRxx match\r
- * the value in TC\r
- * -ExtMatchOutputType: Select output for external match\r
- * + 0: Do nothing for external output pin if match\r
- * + 1: Force external output pin to low if match\r
- * + 2: Force external output pin to high if match\r
- * + 3: Toggle external output pin if match\r
- * MatchValue: Set the value to be compared with TC value\r
- * @return None\r
- **********************************************************************/\r
-void TIM_ConfigMatch(LPC_TIMERn_Type *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct)\r
-{\r
-\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- CHECK_PARAM(PARAM_TIM_EXTMATCH_OPT(TIM_MatchConfigStruct->ExtMatchOutputType));\r
-\r
- switch(TIM_MatchConfigStruct->MatchChannel)\r
- {\r
- case 0:\r
- TIMx->MR[0] = TIM_MatchConfigStruct->MatchValue;\r
- break;\r
- case 1:\r
- TIMx->MR[1] = TIM_MatchConfigStruct->MatchValue;\r
- break;\r
- case 2:\r
- TIMx->MR[2] = TIM_MatchConfigStruct->MatchValue;\r
- break;\r
- case 3:\r
- TIMx->MR[3] = TIM_MatchConfigStruct->MatchValue;\r
- break;\r
- default:\r
- //Error match value\r
- //Error loop\r
- while(1);\r
- }\r
- //interrupt on MRn\r
- TIMx->MCR &=~TIM_MCR_CHANNEL_MASKBIT(TIM_MatchConfigStruct->MatchChannel);\r
-\r
- if (TIM_MatchConfigStruct->IntOnMatch)\r
- TIMx->MCR |= TIM_INT_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);\r
-\r
- //reset on MRn\r
- if (TIM_MatchConfigStruct->ResetOnMatch)\r
- TIMx->MCR |= TIM_RESET_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);\r
-\r
- //stop on MRn\r
- if (TIM_MatchConfigStruct->StopOnMatch)\r
- TIMx->MCR |= TIM_STOP_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);\r
-\r
- // match output type\r
-\r
- TIMx->EMR &= ~TIM_EM_MASK(TIM_MatchConfigStruct->MatchChannel);\r
- TIMx->EMR |= TIM_EM_SET(TIM_MatchConfigStruct->MatchChannel,TIM_MatchConfigStruct->ExtMatchOutputType);\r
-}\r
-/*********************************************************************//**\r
- * @brief Update Match value\r
- * @param[in] TIMx Pointer to timer device, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] MatchChannel Match channel, should be: 0..3\r
- * @param[in] MatchValue updated match value\r
- * @return None\r
- **********************************************************************/\r
-void TIM_UpdateMatchValue(LPC_TIMERn_Type *TIMx,uint8_t MatchChannel, uint32_t MatchValue)\r
-{\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- switch(MatchChannel)\r
- {\r
- case 0:\r
- TIMx->MR[0] = MatchValue;\r
- break;\r
- case 1:\r
- TIMx->MR[1] = MatchValue;\r
- break;\r
- case 2:\r
- TIMx->MR[2] = MatchValue;\r
- break;\r
- case 3:\r
- TIMx->MR[3] = MatchValue;\r
- break;\r
- default:\r
- //Error Loop\r
- while(1);\r
- }\r
-\r
-}\r
-/*********************************************************************//**\r
- * @brief Configuration for Capture register\r
- * @param[in] TIMx Pointer to timer device, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] TIM_CaptureConfigStruct Pointer to TIM_CAPTURECFG_Type\r
- * @return None\r
- **********************************************************************/\r
-void TIM_ConfigCapture(LPC_TIMERn_Type *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct)\r
-{\r
-\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- TIMx->CCR &= ~TIM_CCR_CHANNEL_MASKBIT(TIM_CaptureConfigStruct->CaptureChannel);\r
-\r
- if (TIM_CaptureConfigStruct->RisingEdge)\r
- TIMx->CCR |= TIM_CAP_RISING(TIM_CaptureConfigStruct->CaptureChannel);\r
-\r
- if (TIM_CaptureConfigStruct->FallingEdge)\r
- TIMx->CCR |= TIM_CAP_FALLING(TIM_CaptureConfigStruct->CaptureChannel);\r
-\r
- if (TIM_CaptureConfigStruct->IntOnCaption)\r
- TIMx->CCR |= TIM_INT_ON_CAP(TIM_CaptureConfigStruct->CaptureChannel);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Read value of capture register in timer/counter device\r
- * @param[in] TIMx Pointer to timer/counter device, should be:\r
- * - LPC_TIM0 :TIMER0 peripheral\r
- * - LPC_TIM1 :TIMER1 peripheral\r
- * - LPC_TIM2 :TIMER2 peripheral\r
- * - LPC_TIM3 :TIMER3 peripheral\r
- * @param[in] CaptureChannel: capture channel number, should be:\r
- * - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn\r
- * - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn\r
- * - TIM_COUNTER_INCAP1: CAPn.2 input pin for TIMERn\r
- * - TIM_COUNTER_INCAP1: CAPn.3 input pin for TIMERn\r
- * @return Value of capture register\r
- **********************************************************************/\r
-uint32_t TIM_GetCaptureValue(LPC_TIMERn_Type *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel)\r
-{\r
- CHECK_PARAM(PARAM_TIMx(TIMx));\r
- CHECK_PARAM(PARAM_TIM_COUNTER_INPUT_OPT(CaptureChannel));\r
-\r
- switch(CaptureChannel){\r
- case 0: return TIMx->CR[0];\r
- case 1: return TIMx->CR[1];\r
- case 2: return TIMx->CR[2];\r
- case 3: return TIMx->CR[3];\r
- }\r
- return 0;\r
-}\r
-/*---------------Advanced TIMER functions -----------------------------------------*/\r
-/*********************************************************************//**\r
- * @brief Timer wait (microseconds)\r
- * @param[in] time number of microseconds waiting\r
- * @return None\r
- **********************************************************************/\r
-void TIM_Waitus(uint32_t time)\r
-{\r
- TIM_MATCHCFG_Type MatchConfigStruct;\r
- LPC_TIMER0->IR = 0xFFFFFFFF;\r
-\r
- MatchConfigStruct.MatchChannel = 0;\r
- MatchConfigStruct.IntOnMatch = ENABLE;\r
- MatchConfigStruct.ResetOnMatch = ENABLE;\r
- MatchConfigStruct.StopOnMatch = ENABLE;\r
- MatchConfigStruct.ExtMatchOutputType = 0;\r
- MatchConfigStruct.MatchValue = time;\r
-\r
- TIM_ConfigMatch(LPC_TIMER0, &MatchConfigStruct);\r
- TIM_Cmd(LPC_TIMER0,ENABLE);\r
- //wait until interrupt flag occur\r
- while(!(LPC_TIMER0->IR & 0x01));\r
- TIM_ResetCounter(LPC_TIMER0);\r
-}\r
-/*********************************************************************//**\r
- * @brief Timer wait (milliseconds)\r
- * @param[in] time number of millisecond waiting\r
- * @return None\r
- **********************************************************************/\r
-void TIM_Waitms(uint32_t time)\r
-{\r
- TIM_Waitus(time * 1000);\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _TIMER */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_uart.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_uart.c\r
-* @brief Contains all functions support for UART firmware library on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup UART\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_uart.h"\r
-#include "lpc18xx_cgu.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _UART\r
-\r
-/* Private Functions ---------------------------------------------------------- */\r
-\r
-static Status uart_set_divisors(LPC_USARTn_Type *UARTx, uint32_t baudrate);\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Determines best dividers to get a target clock rate\r
- * @param[in] UARTx Pointer to selected UART peripheral, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] baudrate Desired UART baud rate.\r
- * @return Error status, could be:\r
- * - SUCCESS\r
- * - ERROR\r
- **********************************************************************/\r
-static Status uart_set_divisors(LPC_USARTn_Type *UARTx, uint32_t baudrate)\r
-{\r
- Status errorStatus = ERROR;\r
-\r
- uint32_t uClk;\r
- uint32_t d, m, bestd, bestm, tmp;\r
- uint64_t best_divisor, divisor;\r
- uint32_t current_error, best_error;\r
- uint32_t recalcbaud;\r
-\r
- /* get UART block clock */\r
- //to be defined uClk = CGU_GetCLK(CGU_CLKTYPE_PER);\r
-#ifdef _UART0\r
- if(UARTx == LPC_USART0)\r
- {\r
- uClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_UART0);\r
- }\r
-#endif\r
-\r
-#ifdef _UART1\r
- if(((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- uClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_UART1);\r
- }\r
-#endif\r
-\r
-#ifdef _UART2\r
- if(UARTx == LPC_USART2)\r
- {\r
- uClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_UART2);\r
- }\r
-#endif\r
-\r
-#ifdef _UART3\r
- if(UARTx == LPC_USART3)\r
- {\r
- uClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_UART3);\r
- }\r
-#endif\r
-\r
- /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers\r
- * The formula is :\r
- * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)\r
- * It involves floating point calculations. That's the reason the formulae are adjusted with\r
- * Multiply and divide method.*/\r
- /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:\r
- * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */\r
- best_error = 0xFFFFFFFF; /* Worst case */\r
- bestd = 0;\r
- bestm = 0;\r
- best_divisor = 0;\r
- for (m = 1 ; m <= 15 ;m++)\r
- {\r
- for (d = 0 ; d < m ; d++)\r
- {\r
- divisor = ((uint64_t)uClk<<28)*m/(baudrate*(m+d));\r
- current_error = divisor & 0xFFFFFFFF;\r
-\r
- tmp = divisor>>32;\r
-\r
- /* Adjust error */\r
- if(current_error > ((uint32_t)1<<31)){\r
- current_error = -current_error;\r
- tmp++;\r
- }\r
-\r
- if(tmp<1 || tmp>65536) /* Out of range */\r
- continue;\r
-\r
- if( current_error < best_error){\r
- best_error = current_error;\r
- best_divisor = tmp;\r
- bestd = d;\r
- bestm = m;\r
- if(best_error == 0) break;\r
- }\r
- } /* end of inner for loop */\r
-\r
- if (best_error == 0)\r
- break;\r
- } /* end of outer for loop */\r
-\r
- if(best_divisor == 0) return ERROR; /* can not find best match */\r
-\r
- recalcbaud = (uClk>>4) * bestm/(best_divisor * (bestm + bestd));\r
-\r
- /* reuse best_error to evaluate baud error*/\r
- if(baudrate>recalcbaud) best_error = baudrate - recalcbaud;\r
- else best_error = recalcbaud -baudrate;\r
-\r
- best_error = best_error * 100 / baudrate;\r
-\r
- if (best_error < UART_ACCEPTED_BAUDRATE_ERROR)\r
- {\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->LCR |= UART_LCR_DLAB_EN;\r
- ((LPC_UART1_Type *)UARTx)->/*DLIER.*/DLM = UART_LOAD_DLM(best_divisor);\r
- ((LPC_UART1_Type *)UARTx)->/*RBTHDLR.*/DLL = UART_LOAD_DLL(best_divisor);\r
- /* Then reset DLAB bit */\r
- ((LPC_UART1_Type *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;\r
- ((LPC_UART1_Type *)UARTx)->FDR = (UART_FDR_MULVAL(bestm) \\r
- | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;\r
- }\r
- else\r
- {\r
- UARTx->LCR |= UART_LCR_DLAB_EN;\r
- UARTx->/*DLIER.*/DLM = UART_LOAD_DLM(best_divisor);\r
- UARTx->/*RBTHDLR.*/DLL = UART_LOAD_DLL(best_divisor);\r
- /* Then reset DLAB bit */\r
- UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;\r
- UARTx->FDR = (UART_FDR_MULVAL(bestm) \\r
- | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;\r
- }\r
- errorStatus = SUCCESS;\r
- }\r
-\r
- return errorStatus;\r
-}\r
-\r
-/* End of Private Functions ---------------------------------------------------- */\r
-\r
-\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup UART_Public_Functions\r
- * @{\r
- */\r
-/* UART Init/DeInit functions -------------------------------------------------*/\r
-/********************************************************************//**\r
- * @brief Initializes the UARTx peripheral according to the specified\r
- * parameters in the UART_ConfigStruct.\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure\r
- * that contains the configuration information for the\r
- * specified UART peripheral.\r
- * @return None\r
- *********************************************************************/\r
-void UART_Init(LPC_USARTn_Type *UARTx, UART_CFG_Type *UART_ConfigStruct)\r
-{\r
- uint32_t tmp;\r
-\r
- // For debug mode\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
- CHECK_PARAM(PARAM_UART_DATABIT(UART_ConfigStruct->Databits));\r
- CHECK_PARAM(PARAM_UART_STOPBIT(UART_ConfigStruct->Stopbits));\r
- CHECK_PARAM(PARAM_UART_PARITY(UART_ConfigStruct->Parity));\r
-\r
-#ifdef _UART0\r
- if(UARTx == LPC_USART0)\r
- {\r
- /* Set up peripheral clock for UART0 module */\r
- //LPC_CGU->BASE_UART0_CLK = (SRC_PL160M_0<<24) | (1<<11); // Use PLL1 and auto block\r
- CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART0);\r
- }\r
-#endif\r
-\r
-#ifdef _UART1\r
- if(((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- /* Set up peripheral clock for UART1 module */\r
- //LPC_CGU->BASE_UART1_CLK = (SRC_PL160M_0<<24) | (1<<11); // Use PLL1 and auto block\r
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_UART1);\r
- }\r
-#endif\r
-\r
-#ifdef _UART2\r
- if(UARTx == LPC_USART2)\r
- {\r
- /* Set up peripheral clock for UART2 module */\r
- //LPC_CGU->BASE_UART2_CLK = (SRC_PL160M_0<<24) | (1<<11); // Use PLL1 and auto block\r
- CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART2);\r
- }\r
-#endif\r
-\r
-#ifdef _UART3\r
- if(UARTx == LPC_USART3)\r
- {\r
- /* Set up peripheral clock for UART3 module */\r
- //LPC_CGU->BASE_UART3_CLK = (SRC_PL160M_0<<24) | (1<<11); // Use PLL1 and auto block\r
- CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART3);\r
- }\r
-#endif\r
-\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- /* FIFOs are empty */\r
- ((LPC_UART1_Type *)UARTx)->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN \\r
- | UART_FCR_RX_RS | UART_FCR_TX_RS);\r
- // Disable FIFO\r
- ((LPC_UART1_Type *)UARTx)->/*IIFCR.*/FCR = 0;\r
-\r
- // Dummy reading\r
- while (((LPC_UART1_Type *)UARTx)->LSR & UART_LSR_RDR)\r
- {\r
- tmp = ((LPC_UART1_Type *)UARTx)->/*RBTHDLR.*/RBR;\r
- }\r
-\r
- ((LPC_UART1_Type *)UARTx)->TER = UART1_TER_TXEN;\r
- // Wait for current transmit complete\r
- while (!(((LPC_UART1_Type *)UARTx)->LSR & UART_LSR_THRE));\r
- // Disable Tx\r
- ((LPC_UART1_Type *)UARTx)->TER = 0;\r
-\r
- // Disable interrupt\r
- ((LPC_UART1_Type *)UARTx)->/*DLIER.*/IER = 0;\r
- // Set LCR to default state\r
- ((LPC_UART1_Type *)UARTx)->LCR = 0;\r
- // Set ACR to default state\r
- ((LPC_UART1_Type *)UARTx)->ACR = 0;\r
- // Set Modem Control to default state\r
- ((LPC_UART1_Type *)UARTx)->MCR = 0;\r
- // Set RS485 control to default state\r
- ((LPC_UART1_Type *)UARTx)->RS485CTRL = 0;\r
- // Set RS485 delay timer to default state\r
- ((LPC_UART1_Type *)UARTx)->RS485DLY = 0;\r
- // Set RS485 addr match to default state\r
- ((LPC_UART1_Type *)UARTx)->RS485ADRMATCH = 0;\r
- //Dummy Reading to Clear Status\r
- tmp = ((LPC_UART1_Type *)UARTx)->MSR;\r
- tmp = ((LPC_UART1_Type *)UARTx)->LSR;\r
- }\r
- else\r
- {\r
- /* FIFOs are empty */\r
- UARTx->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);\r
- // Disable FIFO\r
- UARTx->/*IIFCR.*/FCR = 0;\r
-\r
- // Dummy reading\r
- while (UARTx->LSR & UART_LSR_RDR)\r
- {\r
- tmp = UARTx->/*RBTHDLR.*/RBR;\r
- }\r
-\r
- UARTx->TER = UART0_2_3_TER_TXEN;\r
- // Wait for current transmit complete\r
- while (!(UARTx->LSR & UART_LSR_THRE));\r
- // Disable Tx\r
- UARTx->TER = 0;\r
-\r
- // Disable interrupt\r
- UARTx->/*DLIER.*/IER = 0;\r
- // Set LCR to default state\r
- UARTx->LCR = 0;\r
- // Set ACR to default state\r
- UARTx->ACR = 0;\r
- // set HDEN to default state\r
- UARTx->HDEN = 0;\r
- // set SCICTRL to default state\r
- UARTx->SCICTRL = 0;\r
- // set SYNCCTRL to default state\r
- UARTx->SYNCCTRL =0;\r
- // Set RS485 control to default state\r
- UARTx->RS485CTRL = 0;\r
- // Set RS485 delay timer to default state\r
- UARTx->RS485DLY = 0;\r
- // Set RS485 addr match to default state\r
- UARTx->RS485ADRMATCH = 0;\r
- // Dummy reading\r
- tmp = UARTx->LSR;\r
- }\r
-\r
- if (UARTx == LPC_USART3)\r
- {\r
- // Set IrDA to default state\r
- UARTx->ICR = 0;\r
- }\r
-\r
- // Set Line Control register ----------------------------\r
-\r
- uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));\r
-\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- tmp = (((LPC_UART1_Type *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \\r
- & UART_LCR_BITMASK;\r
- }\r
- else\r
- {\r
- tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;\r
- }\r
-\r
- switch (UART_ConfigStruct->Databits){\r
- case UART_DATABIT_5:\r
- tmp |= UART_LCR_WLEN5;\r
- break;\r
- case UART_DATABIT_6:\r
- tmp |= UART_LCR_WLEN6;\r
- break;\r
- case UART_DATABIT_7:\r
- tmp |= UART_LCR_WLEN7;\r
- break;\r
- case UART_DATABIT_8:\r
- default:\r
- tmp |= UART_LCR_WLEN8;\r
- break;\r
- }\r
-\r
- if (UART_ConfigStruct->Parity == UART_PARITY_NONE)\r
- {\r
- // Do nothing...\r
- }\r
- else\r
- {\r
- tmp |= UART_LCR_PARITY_EN;\r
- switch (UART_ConfigStruct->Parity)\r
- {\r
- case UART_PARITY_ODD:\r
- tmp |= UART_LCR_PARITY_ODD;\r
- break;\r
-\r
- case UART_PARITY_EVEN:\r
- tmp |= UART_LCR_PARITY_EVEN;\r
- break;\r
-\r
- case UART_PARITY_SP_1:\r
- tmp |= UART_LCR_PARITY_F_1;\r
- break;\r
-\r
- case UART_PARITY_SP_0:\r
- tmp |= UART_LCR_PARITY_F_0;\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
-\r
- switch (UART_ConfigStruct->Stopbits){\r
- case UART_STOPBIT_2:\r
- tmp |= UART_LCR_STOPBIT_SEL;\r
- break;\r
- case UART_STOPBIT_1:\r
- default:\r
- // Do no thing\r
- break;\r
- }\r
-\r
-\r
- // Write back to LCR, configure FIFO and Disable Tx\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);\r
- }\r
- else\r
- {\r
- UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief De-initializes the UARTx peripheral registers to their\r
- * default reset values.\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @return None\r
- **********************************************************************/\r
-void UART_DeInit(LPC_USARTn_Type* UARTx)\r
-{\r
- // For debug mode\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
-\r
- UART_TxCmd(UARTx, DISABLE);\r
-\r
-#ifdef _UART0\r
- if (UARTx == LPC_USART0)\r
- {\r
- /* Set up peripheral clock for UART0 module */\r
- //LPC_CGU->BASE_UART0_CLK = (SRC_PL160M_1<<24) | (1<<11); // base SRC_PL160M_1 is not configured, so no clk out\r
- }\r
-#endif\r
-\r
-#ifdef _UART1\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- /* Set up peripheral clock for UART1 module */\r
- //LPC_CGU->BASE_UART1_CLK = (SRC_PL160M_1<<24) | (1<<11); // base SRC_PL160M_1 is not configured, so no clk out\r
- }\r
-#endif\r
-\r
-#ifdef _UART2\r
- if (UARTx == LPC_USART2)\r
- {\r
- /* Set up peripheral clock for UART2 module */\r
- //LPC_CGU->BASE_UART2_CLK = (SRC_PL160M_1<<24) | (1<<11); // base SRC_PL160M_1 is not configured, so no clk out\r
- }\r
-#endif\r
-\r
-#ifdef _UART3\r
- if (UARTx == LPC_USART3)\r
- {\r
- /* Set up peripheral clock for UART3 module */\r
- //LPC_CGU->BASE_UART3_CLK = (SRC_PL160M_1<<24) | (1<<11); // base SRC_PL160M_1 is not configured, so no clk out\r
- }\r
-#endif\r
-}\r
-\r
-/*****************************************************************************//**\r
- * @brief Fills each UART_InitStruct member with its default value:\r
- * - 9600 bps\r
- * - 8-bit data\r
- * - 1 Stopbit\r
- * - None Parity\r
- * @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure which will\r
- * be initialized.\r
- * @return None\r
- *******************************************************************************/\r
-void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct)\r
-{\r
- UART_InitStruct->Baud_rate = 9600;\r
- UART_InitStruct->Databits = UART_DATABIT_8;\r
- UART_InitStruct->Parity = UART_PARITY_NONE;\r
- UART_InitStruct->Stopbits = UART_STOPBIT_1;\r
-}\r
-\r
-/* UART Send/Recieve functions -------------------------------------------------*/\r
-/*********************************************************************//**\r
- * @brief Transmit a single data through UART peripheral\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] Data Data to transmit (must be 8-bit long)\r
- * @return None\r
- **********************************************************************/\r
-void UART_SendByte(LPC_USARTn_Type* UARTx, uint8_t Data)\r
-{\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
-\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT;\r
- }\r
- else\r
- {\r
- UARTx->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT;\r
- }\r
-\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Receive a single data from UART peripheral\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @return Data received\r
- **********************************************************************/\r
-uint8_t UART_ReceiveByte(LPC_USARTn_Type* UARTx)\r
-{\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
-\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- return (((LPC_UART1_Type *)UARTx)->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT);\r
- }\r
- else\r
- {\r
- return (UARTx->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT);\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Send a block of data via UART peripheral\r
- * @param[in] UARTx Selected UART peripheral used to send data, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] txbuf Pointer to Transmit buffer\r
- * @param[in] buflen Length of Transmit buffer\r
- * @param[in] flag Flag used in UART transfer, should be\r
- * - NONE_BLOCKING\r
- * - BLOCKING\r
- * @return Number of bytes sent.\r
- *\r
- * Note: when using UART in BLOCKING mode, a time-out condition is used\r
- * via defined symbol UART_BLOCKING_TIMEOUT.\r
- **********************************************************************/\r
-uint32_t UART_Send(LPC_USARTn_Type *UARTx, uint8_t *txbuf,\r
- uint32_t buflen, TRANSFER_BLOCK_Type flag)\r
-{\r
- uint32_t bToSend, bSent, timeOut, fifo_cnt;\r
- uint8_t *pChar = txbuf;\r
-\r
- bToSend = buflen;\r
-\r
- // blocking mode\r
- if (flag == BLOCKING) {\r
- bSent = 0;\r
- while (bToSend){\r
- timeOut = UART_BLOCKING_TIMEOUT;\r
- // Wait for THR empty with timeout\r
- while (!(UARTx->LSR & UART_LSR_THRE)) {\r
- if (timeOut == 0) break;\r
- timeOut--;\r
- }\r
- // Time out!\r
- if(timeOut == 0) break;\r
- fifo_cnt = UART_TX_FIFO_SIZE;\r
- while (fifo_cnt && bToSend){\r
- UART_SendByte(UARTx, (*pChar++));\r
- fifo_cnt--;\r
- bToSend--;\r
- bSent++;\r
- }\r
- }\r
- }\r
- // None blocking mode\r
- else {\r
- bSent = 0;\r
- while (bToSend) {\r
- if (!(UARTx->LSR & UART_LSR_THRE)){\r
- break;\r
- }\r
- fifo_cnt = UART_TX_FIFO_SIZE;\r
- while (fifo_cnt && bToSend) {\r
- UART_SendByte(UARTx, (*pChar++));\r
- bToSend--;\r
- fifo_cnt--;\r
- bSent++;\r
- }\r
- }\r
- }\r
- return bSent;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Receive a block of data via UART peripheral\r
- * @param[in] UARTx Selected UART peripheral used to send data,\r
- * should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[out] rxbuf Pointer to Received buffer\r
- * @param[in] buflen Length of Received buffer\r
- * @param[in] flag Flag mode, should be:\r
- * - NONE_BLOCKING\r
- * - BLOCKING\r
- * @return Number of bytes received\r
- *\r
- * Note: when using UART in BLOCKING mode, a time-out condition is used\r
- * via defined symbol UART_BLOCKING_TIMEOUT.\r
- **********************************************************************/\r
-uint32_t UART_Receive(LPC_USARTn_Type *UARTx, uint8_t *rxbuf, \\r
- uint32_t buflen, TRANSFER_BLOCK_Type flag)\r
-{\r
- uint32_t bToRecv, bRecv, timeOut;\r
- uint8_t *pChar = rxbuf;\r
-\r
- bToRecv = buflen;\r
-\r
- // Blocking mode\r
- if (flag == BLOCKING) {\r
- bRecv = 0;\r
- while (bToRecv){\r
- timeOut = UART_BLOCKING_TIMEOUT;\r
- while (!(UARTx->LSR & UART_LSR_RDR)){\r
- if (timeOut == 0) break;\r
- timeOut--;\r
- }\r
- // Time out!\r
- if(timeOut == 0) break;\r
- // Get data from the buffer\r
- (*pChar++) = UART_ReceiveByte(UARTx);\r
- bToRecv--;\r
- bRecv++;\r
- }\r
- }\r
- // None blocking mode\r
- else {\r
- bRecv = 0;\r
- while (bToRecv) {\r
- if (!(UARTx->LSR & UART_LSR_RDR)) {\r
- break;\r
- } else {\r
- (*pChar++) = UART_ReceiveByte(UARTx);\r
- bRecv++;\r
- bToRecv--;\r
- }\r
- }\r
- }\r
- return bRecv;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Force BREAK character on UART line, output pin UARTx TXD is\r
- forced to logic 0.\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @return None\r
- **********************************************************************/\r
-void UART_ForceBreak(LPC_USARTn_Type* UARTx)\r
-{\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
-\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->LCR |= UART_LCR_BREAK_EN;\r
- }\r
- else\r
- {\r
- UARTx->LCR |= UART_LCR_BREAK_EN;\r
- }\r
-}\r
-\r
-\r
-/********************************************************************//**\r
- * @brief Enable or disable specified UART interrupt.\r
- * @param[in] UARTx UART peripheral selected, should be\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] UARTIntCfg Specifies the interrupt flag,\r
- * should be one of the following:\r
- * - UART_INTCFG_RBR :RBR Interrupt enable\r
- * - UART_INTCFG_THRE :THR Interrupt enable\r
- * - UART_INTCFG_RLS :RX line status interrupt enable\r
- * - UART1_INTCFG_MS :Modem status interrupt enable (UART1 only)\r
- * - UART1_INTCFG_CTS :CTS1 signal transition interrupt enable (UART1 only)\r
- * - UART_INTCFG_ABEO :Enables the end of auto-baud interrupt\r
- * - UART_INTCFG_ABTO :Enables the auto-baud time-out interrupt\r
- * @param[in] NewState New state of specified UART interrupt type,\r
- * should be:\r
- * - ENALBE :Enable this UART interrupt type.\r
- * - DISALBE :Disable this UART interrupt type.\r
- * @return None\r
- *********************************************************************/\r
-void UART_IntConfig(LPC_USARTn_Type *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)\r
-{\r
- uint32_t tmp;\r
-\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- switch(UARTIntCfg){\r
- case UART_INTCFG_RBR:\r
- tmp = UART_IER_RBRINT_EN;\r
- break;\r
- case UART_INTCFG_THRE:\r
- tmp = UART_IER_THREINT_EN;\r
- break;\r
- case UART_INTCFG_RLS:\r
- tmp = UART_IER_RLSINT_EN;\r
- break;\r
- case UART1_INTCFG_MS:\r
- tmp = UART1_IER_MSINT_EN;\r
- break;\r
- case UART1_INTCFG_CTS:\r
- tmp = UART1_IER_CTSINT_EN;\r
- break;\r
- case UART_INTCFG_ABEO:\r
- tmp = UART_IER_ABEOINT_EN;\r
- break;\r
- case UART_INTCFG_ABTO:\r
- tmp = UART_IER_ABTOINT_EN;\r
- break;\r
- }\r
-\r
- if ((LPC_UART1_Type *) UARTx == LPC_UART1)\r
- {\r
- CHECK_PARAM((PARAM_UART_INTCFG(UARTIntCfg)) || (PARAM_UART1_INTCFG(UARTIntCfg)));\r
- }\r
- else\r
- {\r
- CHECK_PARAM(PARAM_UART_INTCFG(UARTIntCfg));\r
- }\r
-\r
- if (NewState == ENABLE)\r
- {\r
- if ((LPC_UART1_Type *) UARTx == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->/*DLIER.*/IER |= tmp;\r
- }\r
- else\r
- {\r
- UARTx->/*DLIER.*/IER |= tmp;\r
- }\r
- }\r
- else\r
- {\r
- if ((LPC_UART1_Type *) UARTx == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->/*DLIER.*/IER &= (~tmp) & UART1_IER_BITMASK;\r
- }\r
- else\r
- {\r
- UARTx->/*DLIER.*/IER &= (~tmp) & UART_IER_BITMASK;\r
- }\r
- }\r
-}\r
-\r
-\r
-/********************************************************************//**\r
- * @brief Get current value of Line Status register in UART peripheral.\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @return Current value of Line Status register in UART peripheral.\r
- * Note: The return value of this function must be ANDed with each member in\r
- * UART_LS_Type enumeration to determine current flag status\r
- * corresponding to each Line status type. Because some flags in\r
- * Line Status register will be cleared after reading, the next reading\r
- * Line Status register could not be correct. So this function used to\r
- * read Line status register in one time only, then the return value\r
- * used to check all flags.\r
- *********************************************************************/\r
-uint8_t UART_GetLineStatus(LPC_USARTn_Type* UARTx)\r
-{\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
-\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- return ((((LPC_UART1_Type *)LPC_UART1)->LSR) & UART_LSR_BITMASK);\r
- }\r
- else\r
- {\r
- return ((UARTx->LSR) & UART_LSR_BITMASK);\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Check whether if UART is busy or not\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @return RESET if UART is not busy, otherwise return SET.\r
- **********************************************************************/\r
-FlagStatus UART_CheckBusy(LPC_USARTn_Type *UARTx)\r
-{\r
- if (UARTx->LSR & UART_LSR_TEMT){\r
- return RESET;\r
- } else {\r
- return SET;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configure FIFO function on selected UART peripheral\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that\r
- * contains specified information about FIFO configuration\r
- * @return none\r
- **********************************************************************/\r
-void UART_FIFOConfig(LPC_USARTn_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg)\r
-{\r
- uint8_t tmp = 0;\r
-\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
- CHECK_PARAM(PARAM_UART_FIFO_LEVEL(FIFOCfg->FIFO_Level));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_DMAMode));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetRxBuf));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetTxBuf));\r
-\r
- tmp |= UART_FCR_FIFO_EN;\r
- switch (FIFOCfg->FIFO_Level){\r
- case UART_FIFO_TRGLEV0:\r
- tmp |= UART_FCR_TRG_LEV0;\r
- break;\r
- case UART_FIFO_TRGLEV1:\r
- tmp |= UART_FCR_TRG_LEV1;\r
- break;\r
- case UART_FIFO_TRGLEV2:\r
- tmp |= UART_FCR_TRG_LEV2;\r
- break;\r
- case UART_FIFO_TRGLEV3:\r
- default:\r
- tmp |= UART_FCR_TRG_LEV3;\r
- break;\r
- }\r
-\r
- if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)\r
- {\r
- tmp |= UART_FCR_TX_RS;\r
- }\r
- if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)\r
- {\r
- tmp |= UART_FCR_RX_RS;\r
- }\r
- if (FIFOCfg->FIFO_DMAMode == ENABLE)\r
- {\r
- tmp |= UART_FCR_DMAMODE_SEL;\r
- }\r
-\r
-\r
- //write to FIFO control register\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK;\r
- }\r
- else\r
- {\r
- UARTx->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK;\r
- }\r
-}\r
-\r
-/*****************************************************************************//**\r
- * @brief Fills each UART_FIFOInitStruct member with its default value:\r
- * - FIFO_DMAMode = DISABLE\r
- * - FIFO_Level = UART_FIFO_TRGLEV0\r
- * - FIFO_ResetRxBuf = ENABLE\r
- * - FIFO_ResetTxBuf = ENABLE\r
- * - FIFO_State = ENABLE\r
- *\r
- * @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure\r
- * which will be initialized.\r
- * @return None\r
- *******************************************************************************/\r
-void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)\r
-{\r
- UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;\r
- UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;\r
- UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;\r
- UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Start/Stop Auto Baudrate activity\r
- * @param[in] UARTx UART peripheral selected, should be\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that\r
- * contains specified information about UART auto baudrate configuration\r
- * @param[in] NewState New State of Auto baudrate activity, should be:\r
- * - ENABLE :Start this activity\r
- * - DISABLE :Stop this activity\r
- * Note: Auto-baudrate mode enable bit will be cleared once this mode\r
- * completed.\r
- * @return none\r
- **********************************************************************/\r
-void UART_ABCmd(LPC_USARTn_Type *UARTx, UART_AB_CFG_Type *ABConfigStruct, \\r
- FunctionalState NewState)\r
-{\r
- uint32_t tmp;\r
-\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- tmp = 0;\r
- if (NewState == ENABLE) {\r
- if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1){\r
- tmp |= UART_ACR_MODE;\r
- }\r
- if (ABConfigStruct->AutoRestart == ENABLE){\r
- tmp |= UART_ACR_AUTO_RESTART;\r
- }\r
- }\r
-\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- if (NewState == ENABLE)\r
- {\r
- // Clear DLL and DLM value\r
- ((LPC_UART1_Type *)UARTx)->LCR |= UART_LCR_DLAB_EN;\r
- ((LPC_UART1_Type *)UARTx)->DLL = 0;\r
- ((LPC_UART1_Type *)UARTx)->DLM = 0;\r
- ((LPC_UART1_Type *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;\r
- // FDR value must be reset to default value\r
- ((LPC_UART1_Type *)UARTx)->FDR = 0x10;\r
- ((LPC_UART1_Type *)UARTx)->ACR = UART_ACR_START | tmp;\r
- }\r
- else\r
- {\r
- ((LPC_UART1_Type *)UARTx)->ACR = 0;\r
- }\r
- }\r
- else\r
- {\r
- if (NewState == ENABLE)\r
- {\r
- // Clear DLL and DLM value\r
- UARTx->LCR |= UART_LCR_DLAB_EN;\r
- UARTx->DLL = 0;\r
- UARTx->DLM = 0;\r
- UARTx->LCR &= ~UART_LCR_DLAB_EN;\r
- // FDR value must be reset to default value\r
- UARTx->FDR = 0x10;\r
- UARTx->ACR = UART_ACR_START | tmp;\r
- }\r
- else\r
- {\r
- UARTx->ACR = 0;\r
- }\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable transmission on UART TxD pin\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] NewState New State of Tx transmission function, should be:\r
- * - ENABLE :Enable this function\r
- - DISABLE :Disable this function\r
- * @return none\r
- **********************************************************************/\r
-void UART_TxCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_UARTx(UARTx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->TER |= UART1_TER_TXEN;\r
- }\r
- else\r
- {\r
- UARTx->TER |= UART0_2_3_TER_TXEN;\r
- }\r
- }\r
- else\r
- {\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->TER &= (~UART1_TER_TXEN) & UART1_TER_BITMASK;\r
- }\r
- else\r
- {\r
- UARTx->TER &= (~UART0_2_3_TER_TXEN) & UART0_2_3_TER_BITMASK;\r
- }\r
- }\r
-}\r
-\r
-/* UART IrDA functions ---------------------------------------------------*/\r
-\r
-#ifdef _UART3\r
-\r
-/*********************************************************************//**\r
- * @brief Enable or disable inverting serial input function of IrDA\r
- * on UART peripheral.\r
- * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)\r
- * @param[in] NewState New state of inverting serial input, should be:\r
- * - ENABLE :Enable this function.\r
- * - DISABLE :Disable this function.\r
- * @return none\r
- **********************************************************************/\r
-void UART_IrDAInvtInputCmd(LPC_USARTn_Type* UARTx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_UART_IrDA(UARTx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- UARTx->ICR |= UART_ICR_IRDAINV;\r
- }\r
- else if (NewState == DISABLE)\r
- {\r
- UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Enable or disable IrDA function on UART peripheral.\r
- * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)\r
- * @param[in] NewState New state of IrDA function, should be:\r
- * - ENABLE :Enable this function.\r
- * - DISABLE :Disable this function.\r
- * @return none\r
- **********************************************************************/\r
-void UART_IrDACmd(LPC_USARTn_Type* UARTx, FunctionalState NewState)\r
-{\r
- CHECK_PARAM(PARAM_UART_IrDA(UARTx));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- if (NewState == ENABLE)\r
- {\r
- UARTx->ICR |= UART_ICR_IRDAEN;\r
- }\r
- else\r
- {\r
- UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configure Pulse divider for IrDA function on UART peripheral.\r
- * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)\r
- * @param[in] PulseDiv Pulse Divider value from Peripheral clock,\r
- * should be one of the following:\r
- * - UART_IrDA_PULSEDIV2 :Pulse width = 2 * Tpclk\r
- * - UART_IrDA_PULSEDIV4 :Pulse width = 4 * Tpclk\r
- * - UART_IrDA_PULSEDIV8 :Pulse width = 8 * Tpclk\r
- * - UART_IrDA_PULSEDIV16 :Pulse width = 16 * Tpclk\r
- * - UART_IrDA_PULSEDIV32 :Pulse width = 32 * Tpclk\r
- * - UART_IrDA_PULSEDIV64 :Pulse width = 64 * Tpclk\r
- * - UART_IrDA_PULSEDIV128 :Pulse width = 128 * Tpclk\r
- * - UART_IrDA_PULSEDIV256 :Pulse width = 256 * Tpclk\r
- * @return None\r
- **********************************************************************/\r
-void UART_IrDAPulseDivConfig(LPC_USARTn_Type *UARTx, UART_IrDA_PULSE_Type PulseDiv)\r
-{\r
- uint32_t tmp, tmp1;\r
- CHECK_PARAM(PARAM_UART_IrDA(UARTx));\r
- CHECK_PARAM(PARAM_UART_IrDA_PULSEDIV(PulseDiv));\r
-\r
- tmp1 = UART_ICR_PULSEDIV(PulseDiv);\r
- tmp = UARTx->ICR & (~UART_ICR_PULSEDIV(7));\r
- tmp |= tmp1 | UART_ICR_FIXPULSE_EN;\r
- UARTx->ICR = tmp & UART_ICR_BITMASK;\r
-}\r
-\r
-#endif\r
-\r
-\r
-/* UART1 FullModem function ---------------------------------------------*/\r
-\r
-#ifdef _UART1\r
-\r
-/*********************************************************************//**\r
- * @brief Force pin DTR/RTS corresponding to given state (Full modem mode)\r
- * @param[in] UARTx LPC_UART1 (only)\r
- * @param[in] Pin Pin that NewState will be applied to, should be:\r
- * - UART1_MODEM_PIN_DTR :DTR pin.\r
- * - UART1_MODEM_PIN_RTS :RTS pin.\r
- * @param[in] NewState New State of DTR/RTS pin, should be:\r
- * - INACTIVE :Force the pin to inactive signal.\r
- - ACTIVE :Force the pin to active signal.\r
- * @return none\r
- **********************************************************************/\r
-void UART_FullModemForcePinState(LPC_UART1_Type *UARTx, UART_MODEM_PIN_Type Pin, \\r
- UART1_SignalState NewState)\r
-{\r
- uint8_t tmp = 0;\r
-\r
- CHECK_PARAM(PARAM_UART1_MODEM(UARTx));\r
- CHECK_PARAM(PARAM_UART1_MODEM_PIN(Pin));\r
- CHECK_PARAM(PARAM_UART1_SIGNALSTATE(NewState));\r
-\r
- switch (Pin){\r
- case UART1_MODEM_PIN_DTR:\r
- tmp = UART1_MCR_DTR_CTRL;\r
- break;\r
- case UART1_MODEM_PIN_RTS:\r
- tmp = UART1_MCR_RTS_CTRL;\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- if (NewState == ACTIVE){\r
- UARTx->MCR |= tmp;\r
- } else {\r
- UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Configure Full Modem mode for UART peripheral\r
- * @param[in] UARTx LPC_UART1 (only)\r
- * @param[in] Mode Full Modem mode, should be:\r
- * - UART1_MODEM_MODE_LOOPBACK :Loop back mode.\r
- * - UART1_MODEM_MODE_AUTO_RTS :Auto-RTS mode.\r
- * - UART1_MODEM_MODE_AUTO_CTS :Auto-CTS mode.\r
- * @param[in] NewState New State of this mode, should be:\r
- * - ENABLE :Enable this mode.\r
- - DISABLE :Disable this mode.\r
- * @return none\r
- **********************************************************************/\r
-void UART_FullModemConfigMode(LPC_UART1_Type *UARTx, UART_MODEM_MODE_Type Mode, \\r
- FunctionalState NewState)\r
-{\r
- uint8_t tmp;\r
-\r
- CHECK_PARAM(PARAM_UART1_MODEM(UARTx));\r
- CHECK_PARAM(PARAM_UART1_MODEM_MODE(Mode));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));\r
-\r
- switch(Mode){\r
- case UART1_MODEM_MODE_LOOPBACK:\r
- tmp = UART1_MCR_LOOPB_EN;\r
- break;\r
- case UART1_MODEM_MODE_AUTO_RTS:\r
- tmp = UART1_MCR_AUTO_RTS_EN;\r
- break;\r
- case UART1_MODEM_MODE_AUTO_CTS:\r
- tmp = UART1_MCR_AUTO_CTS_EN;\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- if (NewState == ENABLE)\r
- {\r
- UARTx->MCR |= tmp;\r
- }\r
- else\r
- {\r
- UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;\r
- }\r
-}\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Get current status of modem status register\r
- * @param[in] UARTx LPC_UART1 (only)\r
- * @return Current value of modem status register\r
- * Note: The return value of this function must be ANDed with each member\r
- * UART_MODEM_STAT_type enumeration to determine current flag status\r
- * corresponding to each modem flag status. Because some flags in\r
- * modem status register will be cleared after reading, the next reading\r
- * modem register could not be correct. So this function used to\r
- * read modem status register in one time only, then the return value\r
- * used to check all flags.\r
- **********************************************************************/\r
-uint8_t UART_FullModemGetStatus(LPC_UART1_Type *UARTx)\r
-{\r
- CHECK_PARAM(PARAM_UART1_MODEM(UARTx));\r
- return ((UARTx->MSR) & UART1_MSR_BITMASK);\r
-}\r
-\r
-#endif /* _UART1 */\r
-/* UART RS485 functions --------------------------------------------------------------*/\r
-\r
-/*********************************************************************//**\r
-* @brief Configure UART peripheral in RS485 mode according to the specified\r
- * parameters in the RS485ConfigStruct.\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] RS485ConfigStruct Pointer to a UART_RS485_CTRLCFG_Type structure\r
- * that contains the configuration information for specified UART\r
- * in RS485 mode.\r
- * @return None\r
- **********************************************************************/\r
-void UART_RS485Config(LPC_USARTn_Type *UARTx, UART_RS485_CTRLCFG_Type *RS485ConfigStruct)\r
-{\r
- uint32_t tmp;\r
-\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoAddrDetect_State));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoDirCtrl_State));\r
- CHECK_PARAM(PARAM_UART_RS485_CFG_DELAYVALUE(RS485ConfigStruct->DelayValue));\r
- CHECK_PARAM(PARAM_SETSTATE(RS485ConfigStruct->DirCtrlPol_Level));\r
- CHECK_PARAM(PARAM_UART_RS485_DIRCTRL_PIN(RS485ConfigStruct->DirCtrlPin));\r
- CHECK_PARAM(PARAM_UART_RS485_CFG_MATCHADDRVALUE(RS485ConfigStruct->MatchAddrValue));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->NormalMultiDropMode_State));\r
- CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->Rx_State));\r
-\r
- tmp = 0;\r
- // If Auto Direction Control is enabled - This function is used in Master mode\r
- if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)\r
- {\r
- tmp |= UART_RS485CTRL_DCTRL_EN;\r
-\r
- // Set polar\r
- if (RS485ConfigStruct->DirCtrlPol_Level == SET)\r
- {\r
- tmp |= UART_RS485CTRL_OINV_1;\r
- }\r
-\r
- // Set pin according to\r
- if (RS485ConfigStruct->DirCtrlPin == UART_RS485_DIRCTRL_DTR)\r
- {\r
- tmp |= UART_RS485CTRL_SEL_DTR;\r
- }\r
-\r
- // Fill delay time\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->RS485DLY = RS485ConfigStruct->DelayValue & UART_RS485DLY_BITMASK;\r
- }\r
- else\r
- {\r
- UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART_RS485DLY_BITMASK;\r
- }\r
- }\r
-\r
- // MultiDrop mode is enable\r
- if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)\r
- {\r
- tmp |= UART_RS485CTRL_NMM_EN;\r
- }\r
-\r
- // Auto Address Detect function\r
- if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)\r
- {\r
- tmp |= UART_RS485CTRL_AADEN;\r
- // Fill Match Address\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->RS485ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART_RS485ADRMATCH_BITMASK;\r
- }\r
- else\r
- {\r
- UARTx->RS485ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART_RS485ADRMATCH_BITMASK;\r
- }\r
- }\r
-\r
-\r
- // Receiver is disable\r
- if (RS485ConfigStruct->Rx_State == DISABLE)\r
- {\r
- tmp |= UART_RS485CTRL_RX_DIS;\r
- }\r
-\r
- // write back to RS485 control register\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->RS485CTRL = tmp & UART_RS485CTRL_BITMASK;\r
- }\r
- else\r
- {\r
- UARTx->RS485CTRL = tmp & UART_RS485CTRL_BITMASK;\r
- }\r
-\r
- // Enable Parity function and leave parity in stick '0' parity as default\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- ((LPC_UART1_Type *)UARTx)->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN);\r
- }\r
- else\r
- {\r
- UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN);\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Enable/Disable receiver in RS485 module in UART\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] NewState New State of command, should be:\r
- * - ENABLE :Enable this function.\r
- * - DISABLE :Disable this function.\r
- * @return None\r
- **********************************************************************/\r
-void UART_RS485ReceiverCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState)\r
-{\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- if (NewState == ENABLE){\r
- ((LPC_UART1_Type *)UARTx)->RS485CTRL &= ~UART_RS485CTRL_RX_DIS;\r
- } else {\r
- ((LPC_UART1_Type *)UARTx)->RS485CTRL |= UART_RS485CTRL_RX_DIS;\r
- }\r
- }\r
- else\r
- {\r
- if (NewState == ENABLE){\r
- UARTx->RS485CTRL &= ~UART_RS485CTRL_RX_DIS;\r
- } else {\r
- UARTx->RS485CTRL |= UART_RS485CTRL_RX_DIS;\r
- }\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Send data on RS485 bus with specified parity stick value (9-bit mode).\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] pDatFrm Pointer to data frame.\r
- * @param[in] size Size of data.\r
- * @param[in] ParityStick Parity Stick value, should be 0 or 1.\r
- * @return None\r
- **********************************************************************/\r
-uint32_t UART_RS485Send(LPC_USARTn_Type *UARTx, uint8_t *pDatFrm, \\r
- uint32_t size, uint8_t ParityStick)\r
-{\r
- uint8_t tmp, save;\r
- uint32_t cnt;\r
- if (((LPC_UART1_Type *)UARTx) == LPC_UART1)\r
- {\r
- if (ParityStick){\r
- save = tmp = ((LPC_UART1_Type *)UARTx)->LCR & UART_LCR_BITMASK;\r
- tmp &= ~(UART_LCR_PARITY_EVEN);\r
- ((LPC_UART1_Type *)UARTx)->LCR = tmp;\r
- cnt = UART_Send((LPC_USARTn_Type *)UARTx, pDatFrm, size, BLOCKING);\r
- while (!(((LPC_UART1_Type *)UARTx)->LSR & UART_LSR_TEMT));\r
- ((LPC_UART1_Type *)UARTx)->LCR = save;\r
- } else {\r
- cnt = UART_Send((LPC_USARTn_Type *)UARTx, pDatFrm, size, BLOCKING);\r
- while (!(((LPC_UART1_Type *)UARTx)->LSR & UART_LSR_TEMT));\r
- }\r
- }\r
- else\r
- {\r
- if (ParityStick){\r
- save = tmp = UARTx->LCR & UART_LCR_BITMASK;\r
- tmp &= ~(UART_LCR_PARITY_EVEN);\r
- UARTx->LCR = tmp;\r
- cnt = UART_Send((LPC_USARTn_Type *)UARTx, pDatFrm, size, BLOCKING);\r
- while (!(UARTx->LSR & UART_LSR_TEMT));\r
- UARTx->LCR = save;\r
- } else {\r
- cnt = UART_Send((LPC_USARTn_Type *)UARTx, pDatFrm, size, BLOCKING);\r
- while (!(UARTx->LSR & UART_LSR_TEMT));\r
- }\r
- }\r
- return cnt;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Send Slave address frames on RS485 bus.\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] SlvAddr Slave Address.\r
- * @return None\r
- **********************************************************************/\r
-void UART_RS485SendSlvAddr(LPC_USARTn_Type *UARTx, uint8_t SlvAddr)\r
-{\r
- UART_RS485Send(UARTx, &SlvAddr, 1, 1);\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Send Data frames on RS485 bus.\r
- * @param[in] UARTx UART peripheral selected, should be:\r
- * - LPC_UART0 :UART0 peripheral\r
- * - LPC_UART1 :UART1 peripheral\r
- * - LPC_UART2 :UART2 peripheral\r
- * - LPC_UART3 :UART3 peripheral\r
- * @param[in] pData Pointer to data to be sent.\r
- * @param[in] size Size of data frame to be sent.\r
- * @return None\r
- **********************************************************************/\r
-uint32_t UART_RS485SendData(LPC_USARTn_Type *UARTx, uint8_t *pData, uint32_t size)\r
-{\r
- return (UART_RS485Send(UARTx, pData, size, 0));\r
-}\r
-\r
-\r
-#endif /* _UART */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-/* --------------------------------- End Of File ------------------------------ */\r
-\r
+++ /dev/null
-#include "lpc18xx_utils.h"\r
-#include "lpc18xx_timer.h"\r
-\r
-//timer init\r
-TIM_TIMERCFG_Type TIM_ConfigStruct;\r
-TIM_MATCHCFG_Type TIM_MatchConfigStruct;\r
-\r
-\r
-/*********************************************************************//**\r
- * @brief Main TIMER program body\r
- * @param[in] None\r
- * @return int\r
- **********************************************************************/\r
-int timer_delay_us( int cnt)\r
-{\r
-\r
- // Initialize timer 0, prescale count time of 1uS\r
- TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;\r
- TIM_ConfigStruct.PrescaleValue = 20;\r
-\r
- // use channel 0, MR0\r
- TIM_MatchConfigStruct.MatchChannel = 0;\r
- // Disable interrupt when MR0 matches the value in TC register\r
- TIM_MatchConfigStruct.IntOnMatch = TRUE;\r
- //Enable reset on MR0: TIMER will reset if MR0 matches it\r
- TIM_MatchConfigStruct.ResetOnMatch = TRUE;\r
- //Stop on MR0 if MR0 matches it\r
- TIM_MatchConfigStruct.StopOnMatch = TRUE;\r
-\r
- TIM_MatchConfigStruct.ExtMatchOutputType =TIM_EXTMATCH_NOTHING;\r
- \r
- TIM_MatchConfigStruct.MatchValue = cnt;\r
-\r
- // Set configuration for Tim_config and Tim_MatchConfig\r
- TIM_Init(LPC_TIMER0, TIM_TIMER_MODE,&TIM_ConfigStruct);\r
- TIM_ConfigMatch(LPC_TIMER0,&TIM_MatchConfigStruct);\r
- TIM_Cmd(LPC_TIMER0,ENABLE);\r
-\r
- while ( !(TIM_GetIntStatus(LPC_TIMER0,TIM_MR0_INT)));\r
- TIM_ClearIntPending(LPC_TIMER0,(TIM_INT_TYPE)0);\r
-\r
- return 0;\r
-}\r
-\r
-/*********************************************************************//**\r
- * @brief Main TIMER program body\r
- * @param[in] None\r
- * @return int\r
- **********************************************************************/\r
-int timer_delay_ms( int cnt)\r
-{\r
-\r
- // Initialize timer 0, prescale count time of 1uS\r
- TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;\r
- TIM_ConfigStruct.PrescaleValue = 1000;\r
-\r
- // use channel 0, MR0\r
- TIM_MatchConfigStruct.MatchChannel = 1;\r
- // Disable interrupt when MR0 matches the value in TC register\r
- TIM_MatchConfigStruct.IntOnMatch = TRUE;\r
- //Enable reset on MR0: TIMER will reset if MR0 matches it\r
- TIM_MatchConfigStruct.ResetOnMatch = TRUE;\r
- //Stop on MR0 if MR0 matches it\r
- TIM_MatchConfigStruct.StopOnMatch = TRUE;\r
-\r
- TIM_MatchConfigStruct.ExtMatchOutputType =TIM_EXTMATCH_NOTHING;\r
- \r
- TIM_MatchConfigStruct.MatchValue = cnt;\r
-\r
- // Set configuration for Tim_config and Tim_MatchConfig\r
- TIM_Init(LPC_TIMER1, TIM_TIMER_MODE,&TIM_ConfigStruct);\r
- TIM_ConfigMatch(LPC_TIMER1,&TIM_MatchConfigStruct);\r
- TIM_Cmd(LPC_TIMER1,ENABLE);\r
-\r
- while ( !(TIM_GetIntStatus(LPC_TIMER1,TIM_MR1_INT)));\r
- TIM_ClearIntPending(LPC_TIMER1,(TIM_INT_TYPE)1);\r
-\r
- return 0;\r
-}\r
+++ /dev/null
-/**********************************************************************\r
-* $Id$ lpc18xx_wwdt.c 2011-06-02\r
-*//**\r
-* @file lpc18xx_wwdt.c\r
-* @brief Contains all functions support for WDT firmware library\r
-* on LPC18xx\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-/* Peripheral group ----------------------------------------------------------- */\r
-/** @addtogroup WWDT\r
- * @{\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------- */\r
-#include "lpc18xx_wwdt.h"\r
-\r
-/* If this source file built with example, the LPC18xx FW library configuration\r
- * file in each example directory ("lpc18xx_libcfg.h") must be included,\r
- * otherwise the default FW library configuration file must be included instead\r
- */\r
-#ifdef __BUILD_WITH_EXAMPLE__\r
-#include "lpc18xx_libcfg.h"\r
-#else\r
-#include "lpc18xx_libcfg_default.h"\r
-#endif /* __BUILD_WITH_EXAMPLE__ */\r
-\r
-\r
-#ifdef _WWDT\r
-\r
-void WWDT_SetTimeOut(uint32_t timeout);\r
-\r
-/*********************************************************************//**\r
- * @brief Update WDT timeout value and feed\r
- * @param[in] timeout WDT timeout (us)\r
- * @return none\r
- **********************************************************************/\r
-void WWDT_SetTimeOut(uint32_t timeout)\r
-{\r
- uint32_t timeoutVal;\r
-\r
- timeoutVal = WDT_GET_FROM_USEC(timeout);\r
-\r
- if(timeoutVal < WWDT_TIMEOUT_MIN)\r
- {\r
- timeoutVal = WWDT_TIMEOUT_MIN;\r
- }\r
- else if (timeoutVal > WWDT_TIMEOUT_MAX)\r
- {\r
- timeoutVal = WWDT_TIMEOUT_MAX;\r
- }\r
-\r
- LPC_WWDT->TC = timeoutVal;\r
-}\r
-/* Public Functions ----------------------------------------------------------- */\r
-/** @addtogroup WDT_Public_Functions\r
- * @{\r
- */\r
-\r
-/*********************************************************************//**\r
-* @brief Initial for Watchdog function\r
-* @param[in] none\r
-* @return None\r
- **********************************************************************/\r
-void WWDT_Init(void)\r
-{\r
- LPC_WWDT->MOD = 0; // Clear time out and interrupt flags\r
- LPC_WWDT->TC = WWDT_TIMEOUT_MIN; // Reset time out\r
- LPC_WWDT->WARNINT= 0; // Reset warning value\r
- LPC_WWDT->WINDOW = WWDT_WINDOW_MAX; // Reset window value\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Update WDT timeout value and feed\r
- * @param[in] TimeOut TimeOut value to be updated, should be in range:\r
- * 2048 .. 134217728\r
- * @return None\r
- *********************************************************************/\r
-void WDT_UpdateTimeOut(uint32_t TimeOut)\r
-{\r
- /* check WDPROTECT,\r
- * if it is enable, wait until the counter is below the value of\r
- * WDWARNINT and WDWINDOW\r
- */\r
- if(LPC_WWDT->MOD & (1<<4))\r
- {\r
- while((LPC_WWDT->TV <(LPC_WWDT->WARNINT & WWDT_WDWARNINT_MASK))\\r
- &&(LPC_WWDT->TV <(LPC_WWDT->WINDOW & WWDT_WDTC_MASK)));\r
- }\r
-\r
- WWDT_SetTimeOut(TimeOut);\r
-}\r
-/********************************************************************//**\r
- * @brief After set WDTEN, call this function to start Watchdog\r
- * or reload the Watchdog timer\r
- * @param[in] None\r
- * @return None\r
- *********************************************************************/\r
-void WWDT_Feed (void)\r
-{\r
- LPC_WWDT->FEED = 0xAA;\r
-\r
- LPC_WWDT->FEED = 0x55;\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Update WDT timeout value and feed\r
- * @param[in] WarnTime time to generate watchdog warning interrupt(us)\r
- * should be in range: 2048 .. 8192\r
- * @return None\r
- *********************************************************************/\r
-void WWDT_SetWarning(uint32_t WarnTime)\r
-{\r
- uint32_t warnVal;\r
-\r
- warnVal = WDT_GET_FROM_USEC(WarnTime);\r
-\r
- if(warnVal <= WWDT_WARNINT_MIN)\r
- {\r
- warnVal = WWDT_WARNINT_MIN;\r
- }\r
- else if (warnVal >= WWDT_WARNINT_MAX)\r
- {\r
- warnVal = WWDT_WARNINT_MAX;\r
- }\r
-\r
- LPC_WWDT->WARNINT = warnVal;\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Update WDT timeout value and feed\r
- * @param[in] WindowedTime expected time to set watchdog window event(us)\r
- * @return none\r
- *********************************************************************/\r
-void WWDT_SetWindow(uint32_t WindowedTime)\r
-{\r
- uint32_t wndVal;\r
-\r
- wndVal = WDT_GET_FROM_USEC(WindowedTime);\r
-\r
- if(wndVal <= WWDT_WINDOW_MIN)\r
- {\r
- wndVal = WWDT_WINDOW_MIN;\r
- }\r
- else if (wndVal >= WWDT_WINDOW_MAX)\r
- {\r
- wndVal = WWDT_WINDOW_MAX;\r
- }\r
-\r
- LPC_WWDT->WINDOW = wndVal;\r
-}\r
-/*********************************************************************//**\r
-* @brief Enable/Disable WWDT activity\r
-* @param[in] None\r
-* @return None\r
- **********************************************************************/\r
-void WWDT_Configure(st_Wdt_Config wdtCfg)\r
-{\r
- WWDT_SetTimeOut(wdtCfg.wdtTmrConst);\r
-\r
- if(wdtCfg.wdtReset)\r
- {\r
- LPC_WWDT->MOD |= WWDT_WDMOD_WDRESET;\r
- }\r
- else\r
- {\r
- LPC_WWDT->MOD &= ~WWDT_WDMOD_WDRESET;\r
- }\r
-\r
- if(wdtCfg.wdtProtect)\r
- {\r
- LPC_WWDT->MOD |= WWDT_WDMOD_WDPROTECT;\r
- }\r
- else\r
- {\r
- LPC_WWDT->MOD &= ~WWDT_WDMOD_WDPROTECT;\r
- }\r
-}\r
-\r
-/*********************************************************************//**\r
-* @brief Enable WWDT activity\r
-* @param[in] None\r
-* @return None\r
- **********************************************************************/\r
-void WWDT_Start(void)\r
-{\r
- LPC_WWDT->MOD |= WWDT_WDMOD_WDEN;\r
- WWDT_Feed();\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Read WWDT status flag\r
- * @param[in] Status kind of status flag that you want to get, should be:\r
- * - WWDT_WARNINT_FLAG: watchdog interrupt flag\r
- * - WWDT_TIMEOUT_FLAG: watchdog time-out flag\r
- * @return Time out flag status of WDT\r
- *********************************************************************/\r
-FlagStatus WWDT_GetStatus (uint8_t Status)\r
-{\r
- if(Status == WWDT_WARNINT_FLAG)\r
- {\r
- return ((FlagStatus)(LPC_WWDT->MOD & (1<<3)));\r
- }\r
- else if (Status == WWDT_TIMEOUT_FLAG)\r
- {\r
- return ((FlagStatus)(LPC_WWDT->MOD & (1<<2)));\r
- }\r
- return (FlagStatus)RESET;\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Read WWDT status flag\r
- * @param[in] Status kind of status flag that you want to get, should be:\r
- * - WWDT_WARNINT_FLAG: watchdog interrupt flag\r
- * - WWDT_TIMEOUT_FLAG: watchdog time-out flag\r
- * @return Time out flag status of WDT\r
- *********************************************************************/\r
-void WWDT_ClearStatusFlag (uint8_t flag)\r
-{\r
- if(flag == WWDT_WARNINT_FLAG)\r
- {\r
- // Write 1 to this bit to clear itself\r
- LPC_WWDT->MOD |= WWDT_WDMOD_WDINT;\r
- }\r
- else if(flag == WWDT_TIMEOUT_FLAG)\r
- {\r
- // Write 0 to this bit to clear itself\r
- LPC_WWDT->MOD &= ~ WWDT_WDMOD_WDTOF;\r
- }\r
-}\r
-\r
-/********************************************************************//**\r
- * @brief Get the current value of WDT\r
- * @param[in] None\r
- * @return current value of WDT\r
- *********************************************************************/\r
-uint32_t WWDT_GetCurrentCount(void)\r
-{\r
- return LPC_WWDT->TV;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* _WWDT */\r
-/**\r
- * @}\r
- */\r
-\r
-/* --------------------------------- End Of File ------------------------------ */\r
+++ /dev/null
-/*\r
- * Modifications for use with Code Red's toolchain - 2011/11/24\r
- */\r
-/**********************************************************************\r
-* $Id$ system_LPC18xx.c 2011-06-02\r
-*//**\r
-* @file system_LPC18xx.c\r
-* @brief Cortex-M3 Device System Source File for NXP LPC18xx Series.\r
-* @version 1.0\r
-* @date 02. June. 2011\r
-* @author NXP MCU SW Application Team\r
-*\r
-* Copyright(C) 2011, NXP Semiconductor\r
-* All rights reserved.\r
-*\r
-***********************************************************************\r
-* Software that is described herein is for illustrative purposes only\r
-* which provides customers with programming information regarding the\r
-* products. This software is supplied "AS IS" without any warranties.\r
-* NXP Semiconductors assumes no responsibility or liability for the\r
-* use of the software, conveys no license or title under any patent,\r
-* copyright, or mask work right to the product. NXP Semiconductors\r
-* reserves the right to make changes in the software without\r
-* notification. NXP Semiconductors also make no representation or\r
-* warranty that such application will be suitable for the specified\r
-* use without further testing or modification.\r
-**********************************************************************/\r
-\r
-#include "LPC18xx.h"\r
-#include "lpc18xx_cgu.h"\r
-/*----------------------------------------------------------------------------\r
- Define clocks\r
- *----------------------------------------------------------------------------*/\r
-#define __IRC (12000000UL) /* IRC Oscillator frequency */\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-uint32_t SystemCoreClock = __IRC * 10UL; /*!< System Clock Frequency (Core Clock)*/\r
-\r
-#ifndef __CODE_RED\r
-extern uint32_t getPC(void);\r
-#endif\r
-\r
-/**\r
- * Initialize the system\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Setup the microcontroller system.\r
- * Initialize the System.\r
- */\r
-void SystemInit (void)\r
-{\r
-#ifdef __CODE_RED\r
- // CodeRed startup code will modify VTOR register to match\r
- // when code has been linked to run from.\r
-\r
- // Check whether we are running from external flash\r
- if (SCB->VTOR == 0x1C000000)\r
- /*Enable Buffer for External Flash*/\r
- LPC_EMC->STATICCONFIG0 |= 1<<19;\r
-\r
- // Call clock initialisation code\r
- CGU_Init();\r
-\r
-#else\r
- // Enable VTOR register to point to vector table\r
- SCB->VTOR = getPC() & 0xFFF00000;\r
- /*Enable Buffer for External Flash*/\r
- LPC_EMC->STATICCONFIG0 |= 1<<19;\r
-\r
-#endif\r
-\r
-}\r
--- /dev/null
+/*\r
+ * @brief Compilers's specific attributes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+*/\r
+\r
+\r
+\r
+/** @ingroup Group_Common\r
+ * @defgroup Group_FuncVarAttributes Function/Variable Attributes\r
+ * @brief Special function/variable attribute macros.\r
+ *\r
+ * This module contains macros for applying specific attributes to functions and variables to control various\r
+ * optimizer and code generation features of the compiler. Attributes may be placed in the function prototype\r
+ * or variable declaration in any order, and multiple attributes can be specified for a single item via a space\r
+ * separated list.\r
+ *\r
+ * On incompatible versions of GCC or on other compilers, these macros evaluate to nothing unless they are\r
+ * critical to the code's function and thus must throw a compile error when used.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __LPCUSBlib_FUNCATTR_H__\r
+#define __LPCUSBlib_FUNCATTR_H__\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_COMMON_H)\r
+ #error Do not include this file directly. Include LPCUSBlib/Common/Common.h instead to gain this functionality.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ #if (__GNUC__ >= 3) || defined(__DOXYGEN__)\r
+ /** Indicates to the compiler that the function can not ever return, so that any stack restoring or\r
+ * return code may be omitted by the compiler in the resulting binary.\r
+ */\r
+ #define ATTR_NO_RETURN __attribute__ ((noreturn))\r
+\r
+ /** Indicates that the function returns a value which should not be ignored by the user code. When\r
+ * applied, any ignored return value from calling the function will produce a compiler warning.\r
+ */\r
+ #define ATTR_WARN_UNUSED_RESULT __attribute__ ((warn_unused_result))\r
+\r
+ /** Indicates that the specified parameters of the function are pointers which should never be \c NULL.\r
+ * When applied as a 1-based comma separated list the compiler will emit a warning if the specified\r
+ * parameters are known at compiler time to be \c NULL at the point of calling the function.\r
+ */\r
+ #define ATTR_NON_NULL_PTR_ARG(...) __attribute__ ((nonnull (__VA_ARGS__)))\r
+\r
+ /** Removes any preamble or postamble from the function. When used, the function will not have any\r
+ * register or stack saving code. This should be used with caution, and when used the programmer\r
+ * is responsible for maintaining stack and register integrity.\r
+ */\r
+ #define ATTR_NAKED __attribute__ ((naked))\r
+\r
+ /** Prevents the compiler from considering a specified function for in-lining. When applied, the given\r
+ * function will not be in-lined under any circumstances.\r
+ */\r
+ #define ATTR_NO_INLINE __attribute__ ((noinline))\r
+\r
+ /** Forces the compiler to inline the specified function. When applied, the given function will be\r
+ * in-lined under all circumstances.\r
+ */\r
+ #define PRAGMA_ALWAYS_INLINE\r
+ #define ATTR_ALWAYS_INLINE __attribute__ ((always_inline))\r
+\r
+ /** Indicates that the specified function is pure, in that it has no side-effects other than global\r
+ * or parameter variable access.\r
+ */\r
+ #define ATTR_PURE __attribute__ ((pure))\r
+\r
+ /** Indicates that the specified function is constant, in that it has no side effects other than\r
+ * parameter access.\r
+ */\r
+ #define ATTR_CONST __attribute__ ((const))\r
+\r
+ /** Marks a given function as deprecated, which produces a warning if the function is called. */\r
+ #define ATTR_DEPRECATED __attribute__ ((deprecated))\r
+\r
+ /** Marks a function as a weak reference, which can be overridden by other functions with an\r
+ * identical name (in which case the weak reference is discarded at link time).\r
+ */\r
+ #define PRAGMA_WEAK(func,alias)\r
+ #define ATTR_WEAK __attribute__ ((weak))\r
+\r
+ /** Marks a function as an alias for another function.\r
+ *\r
+ * @param Func Name of the function which the given function name should alias.\r
+ */\r
+ #define ATTR_ALIAS(Func) __attribute__ ((alias( #Func )))\r
+ \r
+ /** Forces the compiler to not automatically zero the given global variable on startup, so that the\r
+ * current RAM contents is retained. Under most conditions this value will be random due to the\r
+ * behaviour of volatile memory once power is removed, but may be used in some specific circumstances,\r
+ * like the passing of values back after a system watchdog reset.\r
+ */\r
+ #define ATTR_NO_INIT __attribute__ ((section (".noinit")))\r
+ /** Indicates the minimum alignment in bytes for a variable or struct element.\r
+ *\r
+ * @param Bytes Minimum number of bytes the item should be aligned to.\r
+ */\r
+ #define PRAGMA_ALIGN_4096\r
+ #define PRAGMA_ALIGN_2048\r
+ #define PRAGMA_ALIGN_256\r
+ #define PRAGMA_ALIGN_128\r
+ #define PRAGMA_ALIGN_64\r
+ #define PRAGMA_ALIGN_48\r
+ #define PRAGMA_ALIGN_32\r
+ #define PRAGMA_ALIGN_4\r
+ #define ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))\r
+\r
+ #define ATTR_DEPRECATED __attribute__ ((deprecated))\r
+#if defined (__CC_ARM)\r
+ #define ATTR_ERROR(Message) //__attribute__ (( error(Message) ))\r
+#else\r
+ #define ATTR_ERROR(Message) __attribute__ (( error(Message) ))\r
+#endif\r
+ #define ATTR_WARNING(Message) __attribute__ (( warning(Message) ))\r
+ #define ATTR_IAR_PACKED\r
+ #define ATTR_PACKED __attribute__ ((packed))\r
+ #endif\r
+\r
+ #if defined(__ICCARM__)\r
+\r
+ /** Indicates to the compiler that the function can not ever return, so that any stack restoring or\r
+ * return code may be omitted by the compiler in the resulting binary.\r
+ */\r
+ #define ATTR_NO_RETURN \r
+\r
+ /** Indicates that the function returns a value which should not be ignored by the user code. When\r
+ * applied, any ignored return value from calling the function will produce a compiler warning.\r
+ */\r
+ #define ATTR_WARN_UNUSED_RESULT\r
+\r
+ /** Indicates that the specified parameters of the function are pointers which should never be \c NULL.\r
+ * When applied as a 1-based comma separated list the compiler will emit a warning if the specified\r
+ * parameters are known at compiler time to be \c NULL at the point of calling the function.\r
+ */\r
+ #define ATTR_NON_NULL_PTR_ARG(...)\r
+\r
+ /** Removes any preamble or postamble from the function. When used, the function will not have any\r
+ * register or stack saving code. This should be used with caution, and when used the programmer\r
+ * is responsible for maintaining stack and register integrity.\r
+ */\r
+ #define ATTR_NAKED __attribute__ ((naked))\r
+\r
+ /** Prevents the compiler from considering a specified function for in-lining. When applied, the given\r
+ * function will not be in-lined under any circumstances.\r
+ */\r
+ #define ATTR_NO_INLINE __attribute__ ((noinline))\r
+\r
+ /** Forces the compiler to inline the specified function. When applied, the given function will be\r
+ * in-lined under all circumstances.\r
+ */\r
+ #define PRAGMA_ALWAYS_INLINE _Pragma("inline=forced")\r
+ #define ATTR_ALWAYS_INLINE\r
+\r
+ /** Indicates that the specified function is pure, in that it has no side-effects other than global\r
+ * or parameter variable access.\r
+ */\r
+ #define ATTR_PURE __attribute__ ((pure))\r
+\r
+ /** Indicates that the specified function is constant, in that it has no side effects other than\r
+ * parameter access.\r
+ */\r
+ #define ATTR_CONST\r
+\r
+ /** Marks a given function as deprecated, which produces a warning if the function is called. */\r
+ #define ATTR_DEPRECATED// __attribute__ ((deprecated))\r
+\r
+ /** Marks a function as a weak reference, which can be overridden by other functions with an\r
+ * identical name (in which case the weak reference is discarded at link time).\r
+ */\r
+ #define _PPTOSTR_(x) #x\r
+ #define PRAGMA_WEAK(name, vector) _Pragma(_PPTOSTR_(weak name=vector))\r
+ #define ATTR_WEAK\r
+\r
+ /** Marks a function as an alias for another function.\r
+ *\r
+ * @param Func Name of the function which the given function name should alias.\r
+ */\r
+ #define ATTR_ALIAS(Func)\r
+ \r
+ /** Forces the compiler to not automatically zero the given global variable on startup, so that the\r
+ * current RAM contents is retained. Under most conditions this value will be random due to the\r
+ * behaviour of volatile memory once power is removed, but may be used in some specific circumstances,\r
+ * like the passing of values back after a system watchdog reset.\r
+ */\r
+ #define ATTR_NO_INIT __attribute__ ((section (".noinit")))\r
+ /** Indicates the minimum alignment in bytes for a variable or struct element.\r
+ *\r
+ * @param Bytes Minimum number of bytes the item should be aligned to.\r
+ */\r
+ #define PRAGMA_ALIGN_4096 _Pragma("data_alignment=4096")\r
+ #define PRAGMA_ALIGN_2048 _Pragma("data_alignment=2048")\r
+ #define PRAGMA_ALIGN_256 _Pragma("data_alignment=256")\r
+ #define PRAGMA_ALIGN_128 _Pragma("data_alignment=128")\r
+ #define PRAGMA_ALIGN_64 _Pragma("data_alignment=64")\r
+ #define PRAGMA_ALIGN_48 _Pragma("data_alignment=48")\r
+ #define PRAGMA_ALIGN_32 _Pragma("data_alignment=32")\r
+ #define PRAGMA_ALIGN_4 _Pragma("data_alignment=4")\r
+ #define ATTR_ALIGNED(Bytes)\r
+\r
+ //#define ATTR_DEPRECATED __attribute__ ((deprecated))\r
+\r
+ #define ATTR_ERROR(Message)// __attribute__ (( error(Message) ))\r
+\r
+ #define ATTR_WARNING(Message) // __attribute__ (( warning(Message) ))\r
+\r
+ #define ATTR_IAR_PACKED __packed\r
+\r
+ #define ATTR_PACKED\r
+\r
+ #endif\r
+\r
+ /** Places the function in one of the initialization sections, which execute before the main function\r
+ * of the application. Refer to the avr-libc manual for more information on the initialization sections.\r
+ *\r
+ * @param SectionIndex Initialization section number where the function should be placed.\r
+ */\r
+ #define ATTR_INIT_SECTION(SectionIndex) __attribute__ ((naked, section (".init" #SectionIndex )))\r
+\r
+ /** Marks a variable or struct element for packing into the smallest space available, omitting any\r
+ * alignment bytes usually added between fields to optimize field accesses.\r
+ */\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief LPCUSB library's common macros, definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+*/\r
+\r
+\r
+/** @defgroup Group_Common Common Utility Headers - LPCUSBlib/Common/Common.h\r
+ * @ingroup LPCUSBlib\r
+ * @brief Common library convenience headers, macros and functions.\r
+ *\r
+ * Common utility headers containing macros, functions, enums and types which are common to all\r
+ * aspects of the library.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Group_GlobalInt Global Interrupt Macros\r
+ * @brief Convenience macros for the management of interrupts globally within the device.\r
+ *\r
+ * Macros and functions to create and control global interrupts within the device.\r
+ */\r
+\r
+#ifndef __LPCUSBlib_COMMON_H__\r
+#define __LPCUSBlib_COMMON_H__\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_COMMON_H\r
+ \r
+ /* Includes: */\r
+ #include <stdint.h>\r
+ #include <stdbool.h>\r
+ #include <string.h>\r
+ #include <stddef.h>\r
+ \r
+ #if defined(USE_LUFA_CONFIG_HEADER)\r
+ #include "LUFAConfig.h"\r
+ #endif\r
+\r
+ #if 1 // TODO add control macros later\r
+ #include "../LPCUSBlibConfig.h"\r
+ #endif\r
+\r
+ #include "CompilerSpecific.h"\r
+ #include "Attributes.h"\r
+ \r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Architecture specific utility includes: */\r
+ #if defined(__DOXYGEN__)\r
+ /** Type define for an unsigned integer the same width as the selected architecture's machine register.\r
+ * This is distinct from the non-specific standard int data type, whose width is machine dependant but\r
+ * which may not reflect the actual machine register width on some targets (e.g. LPC).\r
+ */\r
+ typedef MACHINE_REG_t uint_reg_t; \r
+ #else\r
+ typedef uint32_t uint_reg_t;\r
+ #define ARCH_LITTLE_ENDIAN\r
+ #define PROGMEM const\r
+ #define pgm_read_byte(x) (*x)\r
+ #define memcmp_P(...) memcmp(__VA_ARGS__)\r
+ #define memcpy_P(...) memcpy(__VA_ARGS__)\r
+ #include "Endianness.h"\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** Macro for encasing other multi-statement macros. This should be used along with an opening brace\r
+ * before the start of any multi-statement macro, so that the macros contents as a whole are treated\r
+ * as a discrete block and not as a list of separate statements which may cause problems when used as\r
+ * a block (such as inline \c if statements).\r
+ */\r
+ #define MACROS do\r
+\r
+ /** Macro for encasing other multi-statement macros. This should be used along with a preceding closing\r
+ * brace at the end of any multi-statement macro, so that the macros contents as a whole are treated\r
+ * as a discrete block and not as a list of separate statements which may cause problems when used as\r
+ * a block (such as inline \c if statements).\r
+ */\r
+ #define MACROE while (0)\r
+\r
+ /** Convenience macro to determine the larger of two values.\r
+ *\r
+ * @note This macro should only be used with operands that do not have side effects from being evaluated\r
+ * multiple times.\r
+ *\r
+ * @param x First value to compare\r
+ * @param y First value to compare\r
+ *\r
+ * @return The larger of the two input parameters\r
+ */\r
+ #if !defined(MAX) || defined(__DOXYGEN__)\r
+ #define MAX(x, y) (((x) > (y)) ? (x) : (y))\r
+ #endif\r
+\r
+ /** Convenience macro to determine the smaller of two values.\r
+ *\r
+ * @note This macro should only be used with operands that do not have side effects from being evaluated\r
+ * multiple times.\r
+ *\r
+ * @param x First value to compare\r
+ * @param y First value to compare\r
+ *\r
+ * @return The smaller of the two input parameters\r
+ */\r
+ #if !defined(MIN) || defined(__DOXYGEN__)\r
+ #define MIN(x, y) (((x) < (y)) ? (x) : (y))\r
+ #endif\r
+ \r
+ #if !defined(STRINGIFY) || defined(__DOXYGEN__)\r
+ /** Converts the given input into a string, via the C Preprocessor. This macro puts literal quotation\r
+ * marks around the input, converting the source into a string literal.\r
+ *\r
+ * @param x Input to convert into a string literal.\r
+ *\r
+ * @return String version of the input.\r
+ */\r
+ #define STRINGIFY(x) #x\r
+\r
+ /** Converts the given input into a string after macro expansion, via the C Preprocessor. This macro puts\r
+ * literal quotation marks around the expanded input, converting the source into a string literal.\r
+ *\r
+ * @param x Input to expand and convert into a string literal.\r
+ *\r
+ * @return String version of the expanded input.\r
+ */\r
+ #define STRINGIFY_EXPANDED(x) STRINGIFY(x)\r
+ #endif\r
+\r
+ /* Inline Functions: */\r
+ /** Function to reverse the individual bits in a byte - i.e. bit 7 is moved to bit 0, bit 6 to bit 1,\r
+ * etc.\r
+ *\r
+ * @param Byte Byte of data whose bits are to be reversed.\r
+ */\r
+ static inline uint8_t BitReverse(uint8_t Byte) ATTR_WARN_UNUSED_RESULT ATTR_CONST;\r
+ static inline uint8_t BitReverse(uint8_t Byte)\r
+ {\r
+ Byte = (((Byte & 0xF0) >> 4) | ((Byte & 0x0F) << 4));\r
+ Byte = (((Byte & 0xCC) >> 2) | ((Byte & 0x33) << 2));\r
+ Byte = (((Byte & 0xAA) >> 1) | ((Byte & 0x55) << 1));\r
+\r
+ return Byte;\r
+ }\r
+\r
+ /** Function to perform a blocking delay for a specified number of milliseconds. The actual delay will be\r
+ * at a minimum the specified number of milliseconds, however due to loop overhead and internal calculations\r
+ * may be slightly higher.\r
+ *\r
+ * @param Milliseconds Number of milliseconds to delay\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline void Delay_MS(uint16_t Milliseconds) ATTR_ALWAYS_INLINE;\r
+ static inline void Delay_MS(uint16_t Milliseconds)\r
+ {\r
+ while (Milliseconds--)\r
+ {\r
+ volatile uint32_t i;\r
+\r
+ for (i = 0; i < (4 * 1000); i++) { /* This logic was tested. It gives app. 1 micro sec delay */\r
+ ;\r
+ }\r
+ }\r
+ }\r
+\r
+ /** Retrieves a mask which contains the current state of the global interrupts for the device. This\r
+ * value can be stored before altering the global interrupt enable state, before restoring the\r
+ * flag(s) back to their previous values after a critical section using @ref SetGlobalInterruptMask().\r
+ *\r
+ * @ingroup Group_GlobalInt\r
+ *\r
+ * @return Mask containing the current Global Interrupt Enable Mask bit(s).\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline uint_reg_t GetGlobalInterruptMask(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+ static inline uint_reg_t GetGlobalInterruptMask(void)\r
+ {\r
+ GCC_MEMORY_BARRIER();\r
+ // TODO #warning GetGlobalInterruptMask() is not implemented under ARCH_LPC.\r
+ return 0;\r
+ //GCC_MEMORY_BARRIER();\r
+ }\r
+\r
+ /** Sets the global interrupt enable state of the microcontroller to the mask passed into the function.\r
+ * This can be combined with @ref GetGlobalInterruptMask() to save and restore the Global Interrupt Enable\r
+ * Mask bit(s) of the device after a critical section has completed.\r
+ *\r
+ * @ingroup Group_GlobalInt\r
+ *\r
+ * @param GlobalIntState Global Interrupt Enable Mask value to use\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline void SetGlobalInterruptMask(const uint_reg_t GlobalIntState) ATTR_ALWAYS_INLINE;\r
+ static inline void SetGlobalInterruptMask(const uint_reg_t GlobalIntState)\r
+ {\r
+ GCC_MEMORY_BARRIER();\r
+ // TODO #warning SetGlobalInterruptMask() is not implemented under ARCH_LPC. \r
+ GCC_MEMORY_BARRIER();\r
+ }\r
+ \r
+ /** Enables global interrupt handling for the device, allowing interrupts to be handled.\r
+ *\r
+ * @ingroup Group_GlobalInt\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline void GlobalInterruptEnable(void) ATTR_ALWAYS_INLINE;\r
+ static inline void GlobalInterruptEnable(void)\r
+ {\r
+ GCC_MEMORY_BARRIER();\r
+ // TODO #warning GlobalInterruptEnable() is not implemented under ARCH_LPC.\r
+ GCC_MEMORY_BARRIER();\r
+ } \r
+\r
+ /** Disabled global interrupt handling for the device, preventing interrupts from being handled.\r
+ *\r
+ * @ingroup Group_GlobalInt\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline void GlobalInterruptDisable(void) ATTR_ALWAYS_INLINE;\r
+ static inline void GlobalInterruptDisable(void)\r
+ {\r
+ GCC_MEMORY_BARRIER();\r
+ // TODO #warning GlobalInterruptDisable() is not implemented under ARCH_LPC.\r
+ GCC_MEMORY_BARRIER();\r
+ }\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Special compiler's definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+*/\r
+\r
+\r
+\r
+/** @ingroup Group_Common\r
+ * @defgroup Group_CompilerSpecific Compiler Specific Definitions\r
+ * @brief Compiler specific definitions for code optimization and correctness.\r
+ *\r
+ * Compiler specific definitions to expose certain compiler features which may increase the level of code optimization\r
+ * for a specific compiler, or correct certain issues that may be present such as memory barriers for use in conjunction\r
+ * with atomic variable access. \r
+ *\r
+ * Where possible, on alternative compilers, these macros will either have no effect, or default to returning a sane value\r
+ * so that they can be used in existing code without the need for extra compiler checks in the user application code.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __LPCUSBlib_COMPILERSPEC_H__\r
+#define __LPCUSBlib_COMPILERSPEC_H__\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_COMMON_H)\r
+ #error Do not include this file directly. Include LPCUSBlib/Common/Common.h instead to gain this functionality.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ #if defined(__GNUC__) || defined(__DOXYGEN__)\r
+ /** Forces GCC to use pointer indirection (via the device's pointer register pairs) when accessing the given\r
+ * struct pointer. In some cases GCC will emit non-optimal assembly code when accessing a structure through\r
+ * a pointer, resulting in a larger binary. When this macro is used on a (non \c const) structure pointer before\r
+ * use, it will force GCC to use pointer indirection on the elements rather than direct store and load\r
+ * instructions.\r
+ *\r
+ * @param StructPtr Pointer to a structure which is to be forced into indirect access mode.\r
+ */\r
+ #define GCC_FORCE_POINTER_ACCESS(StructPtr) __asm__ __volatile__("" : "=b" (StructPtr) : "0" (StructPtr))\r
+\r
+ /** Forces GCC to create a memory barrier, ensuring that memory accesses are not reordered past the barrier point.\r
+ * This can be used before ordering-critical operations, to ensure that the compiler does not re-order the resulting\r
+ * assembly output in an unexpected manner on sections of code that are ordering-specific.\r
+ */\r
+ #define GCC_MEMORY_BARRIER() // FIXME __asm__ __volatile__("" ::: "memory");\r
+ \r
+ /** Evaluates to boolean true if the specified value can be determined at compile time to be a constant value\r
+ * when compiling under GCC.\r
+ *\r
+ * @param x Value to check compile time constantness of.\r
+ *\r
+ * @return Boolean true if the given value is known to be a compile time constant, false otherwise.\r
+ */\r
+ #define GCC_IS_COMPILE_CONST(x) __builtin_constant_p(x)\r
+ #else\r
+ #define GCC_FORCE_POINTER_ACCESS(StructPtr)\r
+ #define GCC_MEMORY_BARRIER()\r
+ #define GCC_IS_COMPILE_CONST(x) 0\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Endianness declaration\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+*/\r
+\r
+\r
+\r
+/** @ingroup Group_Endianness\r
+ * @defgroup Group_ByteSwapping Byte Reordering\r
+ * @brief Macros and functions for forced byte reordering.\r
+ */\r
+\r
+/** @ingroup Group_Endianness\r
+ * @defgroup Group_EndianConversion Endianness Conversion\r
+ * @brief Macros and functions for automatic endianness conversion.\r
+ */\r
+\r
+/** @ingroup Group_Common\r
+ * @defgroup Group_Endianness Endianness and Byte Ordering\r
+ * @brief Convenience macros and functions relating to byte (re-)ordering\r
+ *\r
+ * Common library convenience macros and functions relating to byte (re-)ordering.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __LPCUSBlib_ENDIANNESS_H__\r
+#define __LPCUSBlib_ENDIANNESS_H__\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_COMMON_H)\r
+ #error Do not include this file directly. Include LPCUSBlib/Common/Common.h instead to gain this functionality.\r
+ #endif\r
+ \r
+ #if !(defined(ARCH_BIG_ENDIAN) || defined(ARCH_LITTLE_ENDIAN))\r
+ #error ARCH_BIG_ENDIAN or ARCH_LITTLE_ENDIAN not set for the specified architecture.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** Swaps the byte ordering of a 16-bit value at compile-time. Do not use this macro for swapping byte orderings\r
+ * of dynamic values computed at runtime, use @ref SwapEndian_16() instead. The result of this macro can be used\r
+ * inside struct or other variable initializers outside of a function, something that is not possible with the\r
+ * inline function variant.\r
+ *\r
+ * @ingroup Group_ByteSwapping\r
+ *\r
+ * @param x 16-bit value whose byte ordering is to be swapped.\r
+ *\r
+ * @return Input value with the byte ordering reversed.\r
+ */\r
+ #define SWAPENDIAN_16(x) (uint16_t)((((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8))\r
+\r
+ /** Swaps the byte ordering of a 32-bit value at compile-time. Do not use this macro for swapping byte orderings\r
+ * of dynamic values computed at runtime- use @ref SwapEndian_32() instead. The result of this macro can be used\r
+ * inside struct or other variable initializers outside of a function, something that is not possible with the\r
+ * inline function variant.\r
+ *\r
+ * @ingroup Group_ByteSwapping\r
+ *\r
+ * @param x 32-bit value whose byte ordering is to be swapped.\r
+ *\r
+ * @return Input value with the byte ordering reversed.\r
+ */\r
+ #define SWAPENDIAN_32(x) (uint32_t)((((x) & 0xFF000000UL) >> 24UL) | (((x) & 0x00FF0000UL) >> 8UL) | \\r
+ (((x) & 0x0000FF00UL) << 8UL) | (((x) & 0x000000FFUL) << 24UL))\r
+\r
+ #if defined(ARCH_BIG_ENDIAN) && !defined(le16_to_cpu)\r
+ #define le16_to_cpu(x) SwapEndian_16(x)\r
+ #define le32_to_cpu(x) SwapEndian_32(x)\r
+ #define be16_to_cpu(x) (x)\r
+ #define be32_to_cpu(x) (x)\r
+ #define cpu_to_le16(x) SwapEndian_16(x)\r
+ #define cpu_to_le32(x) SwapEndian_32(x)\r
+ #define cpu_to_be16(x) (x)\r
+ #define cpu_to_be32(x) (x)\r
+ #define LE16_TO_CPU(x) SWAPENDIAN_16(x)\r
+ #define LE32_TO_CPU(x) SWAPENDIAN_32(x)\r
+ #define BE16_TO_CPU(x) (x)\r
+ #define BE32_TO_CPU(x) (x)\r
+ #define CPU_TO_LE16(x) SWAPENDIAN_16(x)\r
+ #define CPU_TO_LE32(x) SWAPENDIAN_32(x)\r
+ #define CPU_TO_BE16(x) (x)\r
+ #define CPU_TO_BE32(x) (x) \r
+ #elif !defined(le16_to_cpu)\r
+ /** \name Run-time endianness conversion */\r
+ //@{\r
+ \r
+ /** Performs a conversion between a Little Endian encoded 16-bit piece of data and the\r
+ * Endianness of the currently selected CPU architecture.\r
+ *\r
+ * On little endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for run-time conversion of data - for compile-time endianness\r
+ * conversion, use @ref LE16_TO_CPU instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define le16_to_cpu(x) (x)\r
+\r
+ /** Performs a conversion between a Little Endian encoded 32-bit piece of data and the\r
+ * Endianness of the currently selected CPU architecture.\r
+ *\r
+ * On little endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for run-time conversion of data - for compile-time endianness\r
+ * conversion, use @ref LE32_TO_CPU instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define le32_to_cpu(x) (x)\r
+\r
+ /** Performs a conversion between a Big Endian encoded 16-bit piece of data and the\r
+ * Endianness of the currently selected CPU architecture.\r
+ *\r
+ * On big endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for run-time conversion of data - for compile-time endianness\r
+ * conversion, use @ref BE16_TO_CPU instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define be16_to_cpu(x) SwapEndian_16(x)\r
+\r
+ /** Performs a conversion between a Big Endian encoded 32-bit piece of data and the\r
+ * Endianness of the currently selected CPU architecture.\r
+ *\r
+ * On big endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for run-time conversion of data - for compile-time endianness\r
+ * conversion, use @ref BE32_TO_CPU instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define be32_to_cpu(x) SwapEndian_32(x)\r
+\r
+ /** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it\r
+ * is in Little Endian format regardless of the currently selected CPU architecture.\r
+ *\r
+ * On little endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for run-time conversion of data - for compile-time endianness\r
+ * conversion, use @ref CPU_TO_LE16 instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define cpu_to_le16(x) (x)\r
+\r
+ /** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it\r
+ * is in Little Endian format regardless of the currently selected CPU architecture.\r
+ *\r
+ * On little endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for run-time conversion of data - for compile-time endianness\r
+ * conversion, use @ref CPU_TO_LE32 instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define cpu_to_le32(x) (x)\r
+\r
+ /** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it\r
+ * is in Big Endian format regardless of the currently selected CPU architecture.\r
+ *\r
+ * On big endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for run-time conversion of data - for compile-time endianness\r
+ * conversion, use @ref CPU_TO_BE16 instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define cpu_to_be16(x) SwapEndian_16(x)\r
+\r
+ /** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it\r
+ * is in Big Endian format regardless of the currently selected CPU architecture.\r
+ *\r
+ * On big endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for run-time conversion of data - for compile-time endianness\r
+ * conversion, use @ref CPU_TO_BE32 instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define cpu_to_be32(x) SwapEndian_32(x)\r
+\r
+ //@}\r
+\r
+ /** \name Compile-time endianness conversion */\r
+ //@{\r
+\r
+ /** Performs a conversion between a Little Endian encoded 16-bit piece of data and the\r
+ * Endianness of the currently selected CPU architecture.\r
+ *\r
+ * On little endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for compile-time conversion of data - for run time endianness\r
+ * conversion, use @ref le16_to_cpu instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define LE16_TO_CPU(x) (x)\r
+\r
+ /** Performs a conversion between a Little Endian encoded 32-bit piece of data and the\r
+ * Endianness of the currently selected CPU architecture.\r
+ *\r
+ * On little endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for compile-time conversion of data - for run time endianness\r
+ * conversion, use @ref le32_to_cpu instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define LE32_TO_CPU(x) (x)\r
+\r
+ /** Performs a conversion between a Big Endian encoded 16-bit piece of data and the\r
+ * Endianness of the currently selected CPU architecture.\r
+ *\r
+ * On big endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for compile-time conversion of data - for run-time endianness\r
+ * conversion, use @ref be16_to_cpu instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define BE16_TO_CPU(x) SWAPENDIAN_16(x)\r
+\r
+ /** Performs a conversion between a Big Endian encoded 32-bit piece of data and the\r
+ * Endianness of the currently selected CPU architecture.\r
+ *\r
+ * On big endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for compile-time conversion of data - for run-time endianness\r
+ * conversion, use @ref be32_to_cpu instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define BE32_TO_CPU(x) SWAPENDIAN_32(x)\r
+\r
+ /** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it\r
+ * is in Little Endian format regardless of the currently selected CPU architecture.\r
+ *\r
+ * On little endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for compile-time conversion of data - for run-time endianness\r
+ * conversion, use @ref cpu_to_le16 instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define CPU_TO_LE16(x) (x)\r
+\r
+ /** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it\r
+ * is in Little Endian format regardless of the currently selected CPU architecture.\r
+ *\r
+ * On little endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for compile-time conversion of data - for run-time endianness\r
+ * conversion, use @ref cpu_to_le32 instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define CPU_TO_LE32(x) (x)\r
+\r
+ /** Performs a conversion on a natively encoded 16-bit piece of data to ensure that it\r
+ * is in Big Endian format regardless of the currently selected CPU architecture.\r
+ *\r
+ * On big endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for compile-time conversion of data - for run-time endianness\r
+ * conversion, use @ref cpu_to_be16 instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define CPU_TO_BE16(x) SWAPENDIAN_16(x)\r
+\r
+ /** Performs a conversion on a natively encoded 32-bit piece of data to ensure that it\r
+ * is in Big Endian format regardless of the currently selected CPU architecture.\r
+ *\r
+ * On big endian architectures, this macro does nothing.\r
+ *\r
+ * @note This macro is designed for compile-time conversion of data - for run-time endianness\r
+ * conversion, use @ref cpu_to_be32 instead.\r
+ *\r
+ * @ingroup Group_EndianConversion\r
+ *\r
+ * @param x Data to perform the endianness conversion on.\r
+ *\r
+ * @return Endian corrected version of the input value.\r
+ */\r
+ #define CPU_TO_BE32(x) SWAPENDIAN_32(x)\r
+\r
+ //! @}\r
+ #endif\r
+\r
+ /* Inline Functions: */\r
+ /** Function to reverse the byte ordering of the individual bytes in a 16 bit value.\r
+ *\r
+ * @ingroup Group_ByteSwapping\r
+ *\r
+ * @param Word Word of data whose bytes are to be swapped.\r
+ */\r
+ static inline uint16_t SwapEndian_16(const uint16_t Word) ATTR_WARN_UNUSED_RESULT ATTR_CONST;\r
+ static inline uint16_t SwapEndian_16(const uint16_t Word)\r
+ {\r
+ if (GCC_IS_COMPILE_CONST(Word))\r
+ return SWAPENDIAN_16(Word);\r
+ \r
+ uint8_t Temp;\r
+\r
+ union\r
+ {\r
+ uint16_t Word;\r
+ uint8_t Bytes[2];\r
+ } Data;\r
+\r
+ Data.Word = Word;\r
+\r
+ Temp = Data.Bytes[0];\r
+ Data.Bytes[0] = Data.Bytes[1];\r
+ Data.Bytes[1] = Temp;\r
+\r
+ return Data.Word;\r
+ }\r
+\r
+ /** Function to reverse the byte ordering of the individual bytes in a 32 bit value.\r
+ *\r
+ * @ingroup Group_ByteSwapping\r
+ *\r
+ * @param DWord Double word of data whose bytes are to be swapped.\r
+ */\r
+ static inline uint32_t SwapEndian_32(const uint32_t DWord) ATTR_WARN_UNUSED_RESULT ATTR_CONST;\r
+ static inline uint32_t SwapEndian_32(const uint32_t DWord)\r
+ {\r
+ if (GCC_IS_COMPILE_CONST(DWord))\r
+ return SWAPENDIAN_32(DWord);\r
+\r
+ uint8_t Temp;\r
+\r
+ union\r
+ {\r
+ uint32_t DWord;\r
+ uint8_t Bytes[4];\r
+ } Data;\r
+\r
+ Data.DWord = DWord;\r
+\r
+ Temp = Data.Bytes[0];\r
+ Data.Bytes[0] = Data.Bytes[3];\r
+ Data.Bytes[3] = Temp;\r
+\r
+ Temp = Data.Bytes[1];\r
+ Data.Bytes[1] = Data.Bytes[2];\r
+ Data.Bytes[2] = Temp;\r
+\r
+ return Data.DWord;\r
+ }\r
+\r
+ /** Function to reverse the byte ordering of the individual bytes in a n byte value.\r
+ *\r
+ * @ingroup Group_ByteSwapping\r
+ *\r
+ * \param[in,out] Data Pointer to a number containing an even number of bytes to be reversed.\r
+ * @param Length Length of the data in bytes.\r
+ */\r
+ static inline void SwapEndian_n(void* const Data,\r
+ uint8_t Length) ATTR_NON_NULL_PTR_ARG(1);\r
+ static inline void SwapEndian_n(void* const Data,\r
+ uint8_t Length)\r
+ {\r
+ uint8_t* CurrDataPos = (uint8_t*)Data;\r
+\r
+ while (Length > 1)\r
+ {\r
+ uint8_t Temp = *CurrDataPos;\r
+ *CurrDataPos = *(CurrDataPos + Length - 1);\r
+ *(CurrDataPos + Length - 1) = Temp;\r
+\r
+ CurrDataPos++;\r
+ Length -= 2;\r
+ }\r
+ }\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * @brief Master include file for the library USB Audio 1.0 Class driver, for both host and device modes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassDrivers\r
+ * @defgroup Group_USBClassAudio Audio 1.0 Class Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Device/Audio.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/Audio.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Audio 1.0 Class Driver module. This module contains an internal implementation of the USB Audio 1.0 Class, for both\r
+ * Device and Host USB modes. User applications can use this class driver instead of implementing the Audio 1.0 class\r
+ * manually via the low-level nxpUSBlib APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Hosts or Devices using the USB Audio 1.0 Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _AUDIO_CLASS_H_\r
+#define _AUDIO_CLASS_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_USB_DRIVER\r
+ #define __INCLUDE_FROM_AUDIO_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../Core/USBMode.h"\r
+\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ #include "Device/AudioClassDevice.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ #include "Host/AudioClassHost.h"\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Master include file for the library USB CDC Class driver, for both host and device modes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassDrivers\r
+ * @defgroup Group_USBClassCDC CDC-ACM (Virtual Serial) Class Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Device/CDC.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/CDC.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * CDC Class Driver module. This module contains an internal implementation of the USB CDC-ACM class Virtual Serial\r
+ * Ports, for both Device and Host USB modes. User applications can use this class driver instead of implementing the\r
+ * CDC class manually via the low-level nxpUSBlib APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Hosts or Devices using the USB CDC Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _CDC_CLASS_H_\r
+#define _CDC_CLASS_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_USB_DRIVER\r
+ #define __INCLUDE_FROM_CDC_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../Core/USBMode.h"\r
+\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ #include "Device/CDCClassDevice.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ #include "Host/CDCClassHost.h"\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Common definitions and declarations for the library USB Audio 1.0 Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassAudio\r
+ * @defgroup Group_USBClassAudioCommon Common Class Definitions\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB\r
+ * Audio 1.0 Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _AUDIO_CLASS_COMMON_H_\r
+#define _AUDIO_CLASS_COMMON_H_\r
+\r
+ /* Includes: */\r
+ #include "../../Core/StdDescriptors.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_AUDIO_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Macros: */\r
+ /** @name Audio Channel Masks */\r
+ //@{\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_LEFT_FRONT (1 << 0)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_RIGHT_FRONT (1 << 1)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_CENTER_FRONT (1 << 2)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_LOW_FREQ_ENHANCE (1 << 3)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_LEFT_SURROUND (1 << 4)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_RIGHT_SURROUND (1 << 5)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_LEFT_OF_CENTER (1 << 6)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_RIGHT_OF_CENTER (1 << 7)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_SURROUND (1 << 8)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_SIDE_LEFT (1 << 9)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_SIDE_RIGHT (1 << 10)\r
+\r
+ /** Supported channel mask for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_CHANNEL_TOP (1 << 11)\r
+ //@}\r
+\r
+ /** @name Audio Feature Masks */\r
+ //@{\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_MUTE (1 << 0)\r
+\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_VOLUME (1 << 1)\r
+\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_BASS (1 << 2)\r
+\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_MID (1 << 3)\r
+\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_TREBLE (1 << 4)\r
+\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_GRAPHIC_EQUALIZER (1 << 5)\r
+\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_AUTOMATIC_GAIN (1 << 6)\r
+\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_DELAY (1 << 7)\r
+\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_BASS_BOOST (1 << 8)\r
+\r
+ /** Supported feature mask for an Audio class feature unit descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_FEATURE_BASS_LOUDNESS (1 << 9)\r
+ //@}\r
+\r
+ /** @name Audio Terminal Types */\r
+ //@{\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_UNDEFINED 0x0100\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_STREAMING 0x0101\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_VENDOR 0x01FF\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_IN_UNDEFINED 0x0200\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_IN_MIC 0x0201\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_IN_DESKTOP_MIC 0x0202\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_IN_PERSONAL_MIC 0x0203\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_IN_OMNIDIR_MIC 0x0204\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_IN_MIC_ARRAY 0x0205\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_IN_PROCESSING_MIC 0x0206\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_IN_OUT_UNDEFINED 0x0300\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_OUT_SPEAKER 0x0301\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_OUT_HEADPHONES 0x0302\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_OUT_HEAD_MOUNTED 0x0303\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_OUT_DESKTOP 0x0304\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_OUT_ROOM 0x0305\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_OUT_COMMUNICATION 0x0306\r
+\r
+ /** Terminal type constant for an Audio class terminal descriptor. See the Audio class specification for more details. */\r
+ #define AUDIO_TERMINAL_OUT_LOWFREQ 0x0307\r
+ //@}\r
+\r
+ /** Convenience macro to fill a 24-bit @ref USB_Audio_SampleFreq_t structure with the given sample rate as a 24-bit number.\r
+ *\r
+ * @param freq Required audio sampling frequency in HZ\r
+ */\r
+ #define AUDIO_SAMPLE_FREQ(freq) {.Byte1 = ((uint32_t)freq & 0xFF), .Byte2 = (((uint32_t)freq >> 8) & 0xFF), .Byte3 = (((uint32_t)freq >> 16) & 0xFF)}\r
+\r
+ /** Mask for the attributes parameter of an Audio class-specific Endpoint descriptor, indicating that the endpoint\r
+ * accepts only filled endpoint packets of audio samples.\r
+ */\r
+ #define AUDIO_EP_FULL_PACKETS_ONLY (1 << 7)\r
+\r
+ /** Mask for the attributes parameter of an Audio class-specific Endpoint descriptor, indicating that the endpoint\r
+ * will accept partially filled endpoint packets of audio samples.\r
+ */\r
+ #define AUDIO_EP_ACCEPTS_SMALL_PACKETS (0 << 7)\r
+\r
+ /** Mask for the attributes parameter of an Audio class-specific Endpoint descriptor, indicating that the endpoint\r
+ * allows for sampling frequency adjustments to be made via control requests directed at the endpoint.\r
+ */\r
+ #define AUDIO_EP_SAMPLE_FREQ_CONTROL (1 << 0)\r
+\r
+ /** Mask for the attributes parameter of an Audio class-specific Endpoint descriptor, indicating that the endpoint\r
+ * allows for pitch adjustments to be made via control requests directed at the endpoint.\r
+ */\r
+ #define AUDIO_EP_PITCH_CONTROL (1 << 1)\r
+ \r
+ /* Enums: */\r
+ /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the Audio\r
+ * device class.\r
+ */\r
+ enum Audio_Descriptor_ClassSubclassProtocol_t\r
+ {\r
+ AUDIO_CSCP_AudioClass = 0x01, /**< Descriptor Class value indicating that the device or\r
+ * interface belongs to the USB Audio 1.0 class.\r
+ */\r
+ AUDIO_CSCP_ControlSubclass = 0x01, /**< Descriptor Subclass value indicating that the device or\r
+ * interface belongs to the Audio Control subclass.\r
+ */\r
+ AUDIO_CSCP_ControlProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or\r
+ * interface belongs to the Audio Control protocol.\r
+ */\r
+ AUDIO_CSCP_AudioStreamingSubclass = 0x02, /**< Descriptor Subclass value indicating that the device or\r
+ * interface belongs to the MIDI Streaming subclass.\r
+ */\r
+ AUDIO_CSCP_MIDIStreamingSubclass = 0x03, /**< Descriptor Subclass value indicating that the device or\r
+ * interface belongs to the Audio streaming subclass.\r
+ */\r
+ AUDIO_CSCP_StreamingProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or\r
+ * interface belongs to the Streaming Audio protocol.\r
+ */\r
+ };\r
+ \r
+ /** Audio class specific interface description subtypes, for the Audio Control interface. */\r
+ enum Audio_CSInterface_AC_SubTypes_t\r
+ {\r
+ AUDIO_DSUBTYPE_CSInterface_Header = 0x01, /**< Audio class specific control interface header. */\r
+ AUDIO_DSUBTYPE_CSInterface_InputTerminal = 0x02, /**< Audio class specific control interface Input Terminal. */\r
+ AUDIO_DSUBTYPE_CSInterface_OutputTerminal = 0x03, /**< Audio class specific control interface Output Terminal. */\r
+ AUDIO_DSUBTYPE_CSInterface_Mixer = 0x04, /**< Audio class specific control interface Mixer Unit. */\r
+ AUDIO_DSUBTYPE_CSInterface_Selector = 0x05, /**< Audio class specific control interface Selector Unit. */\r
+ AUDIO_DSUBTYPE_CSInterface_Feature = 0x06, /**< Audio class specific control interface Feature Unit. */\r
+ AUDIO_DSUBTYPE_CSInterface_Processing = 0x07, /**< Audio class specific control interface Processing Unit. */\r
+ AUDIO_DSUBTYPE_CSInterface_Extension = 0x08, /**< Audio class specific control interface Extension Unit. */\r
+ };\r
+\r
+ /** Audio class specific interface description subtypes, for the Audio Streaming interface. */\r
+ enum Audio_CSInterface_AS_SubTypes_t\r
+ {\r
+ AUDIO_DSUBTYPE_CSInterface_General = 0x01, /**< Audio class specific streaming interface general descriptor. */\r
+ AUDIO_DSUBTYPE_CSInterface_FormatType = 0x02, /**< Audio class specific streaming interface format type descriptor. */\r
+ AUDIO_DSUBTYPE_CSInterface_FormatSpecific = 0x03, /**< Audio class specific streaming interface format information descriptor. */\r
+ };\r
+\r
+ /** Audio class specific endpoint description subtypes, for the Audio Streaming interface. */\r
+ enum Audio_CSEndpoint_SubTypes_t\r
+ {\r
+ AUDIO_DSUBTYPE_CSEndpoint_General = 0x01, /**< Audio class specific endpoint general descriptor. */\r
+ };\r
+\r
+ /** Enum for the Audio class specific control requests that can be issued by the USB bus host. */\r
+ enum Audio_ClassRequests_t\r
+ {\r
+ AUDIO_REQ_SetCurrent = 0x01, /**< Audio class-specific request to set the current value of a parameter within the device. */\r
+ AUDIO_REQ_SetMinimum = 0x02, /**< Audio class-specific request to set the minimum value of a parameter within the device. */\r
+ AUDIO_REQ_SetMaximum = 0x03, /**< Audio class-specific request to set the maximum value of a parameter within the device. */\r
+ AUDIO_REQ_SetResolution = 0x04, /**< Audio class-specific request to set the resolution value of a parameter within the device. */\r
+ AUDIO_REQ_SetMemory = 0x05, /**< Audio class-specific request to set the memory value of a parameter within the device. */\r
+ AUDIO_REQ_GetCurrent = 0x81, /**< Audio class-specific request to get the current value of a parameter within the device. */\r
+ AUDIO_REQ_GetMinimum = 0x82, /**< Audio class-specific request to get the minimum value of a parameter within the device. */\r
+ AUDIO_REQ_GetMaximum = 0x83, /**< Audio class-specific request to get the maximum value of a parameter within the device. */\r
+ AUDIO_REQ_GetResolution = 0x84, /**< Audio class-specific request to get the resolution value of a parameter within the device. */\r
+ AUDIO_REQ_GetMemory = 0x85, /**< Audio class-specific request to get the memory value of a parameter within the device. */\r
+ AUDIO_REQ_GetStatus = 0xFF, /**< Audio class-specific request to get the device status. */\r
+ };\r
+ \r
+ /** Enum for Audio class specific Endpoint control modifiers which can be set and retrieved by a USB host, if the corresponding\r
+ * endpoint control is indicated to be supported in the Endpoint's Audio-class specific endpoint descriptor.\r
+ */\r
+ enum Audio_EndpointControls_t\r
+ {\r
+ AUDIO_EPCONTROL_SamplingFreq = 0x01, /**< Sampling frequency adjustment of the endpoint. */\r
+ AUDIO_EPCONTROL_Pitch = 0x02, /**< Pitch adjustment of the endpoint. */\r
+ };\r
+\r
+ /* Type Defines: */\r
+ /** @brief Audio class-specific Input Terminal Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific input terminal descriptor. This indicates to the host that the device\r
+ * contains an input audio source, either from a physical terminal on the device, or a logical terminal (for example,\r
+ * a USB endpoint). See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_StdDescriptor_InputTerminal_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * must be @ref AUDIO_DSUBTYPE_CSInterface_InputTerminal.\r
+ */\r
+\r
+ uint8_t TerminalID; /**< ID value of this terminal unit - must be a unique value within the device. */\r
+ uint16_t TerminalType; /**< Type of terminal, a \c TERMINAL_* mask. */\r
+ uint8_t AssociatedOutputTerminal; /**< ID of associated output terminal, for physically grouped terminals\r
+ * such as the speaker and microphone of a phone handset.\r
+ */\r
+ uint8_t TotalChannels; /**< Total number of separate audio channels within this interface (right, left, etc.) */\r
+ uint16_t ChannelConfig; /**< \c CHANNEL_* masks indicating what channel layout is supported by this terminal. */\r
+\r
+ uint8_t ChannelStrIndex; /**< Index of a string descriptor describing this channel within the device. */\r
+ uint8_t TerminalStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_Audio_Descriptor_InputTerminal_t;\r
+\r
+ /** @brief Audio class-specific Input Terminal Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific input terminal descriptor. This indicates to the host that the device\r
+ * contains an input audio source, either from a physical terminal on the device, or a logical terminal (for example,\r
+ * a USB endpoint). See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_Descriptor_InputTerminal_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * must be @ref AUDIO_DSUBTYPE_CSInterface_InputTerminal.\r
+ */\r
+ uint8_t bTerminalID; /**< ID value of this terminal unit - must be a unique value within the device. */\r
+ uint16_t wTerminalType; /**< Type of terminal, a \c TERMINAL_* mask. */\r
+ uint8_t bAssocTerminal; /**< ID of associated output terminal, for physically grouped terminals\r
+ * such as the speaker and microphone of a phone handset.\r
+ */\r
+ uint8_t bNrChannels; /**< Total number of separate audio channels within this interface (right, left, etc.) */\r
+ uint16_t wChannelConfig; /**< \c CHANNEL_* masks indicating what channel layout is supported by this terminal. */\r
+\r
+ uint8_t iChannelNames; /**< Index of a string descriptor describing this channel within the device. */\r
+ uint8_t iTerminal; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_Audio_StdDescriptor_InputTerminal_t;\r
+\r
+ /** @brief Audio class-specific Output Terminal Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific output terminal descriptor. This indicates to the host that the device\r
+ * contains an output audio sink, either to a physical terminal on the device, or a logical terminal (for example,\r
+ * a USB endpoint). See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_StdDescriptor_OutputTerminal_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * must be @ref AUDIO_DSUBTYPE_CSInterface_OutputTerminal.\r
+ */\r
+\r
+ uint8_t TerminalID; /**< ID value of this terminal unit - must be a unique value within the device. */\r
+ uint16_t TerminalType; /**< Type of terminal, a \c TERMINAL_* mask. */\r
+ uint8_t AssociatedInputTerminal; /**< ID of associated input terminal, for physically grouped terminals\r
+ * such as the speaker and microphone of a phone handset.\r
+ */\r
+ uint8_t SourceID; /**< ID value of the unit this terminal's audio is sourced from. */\r
+\r
+ uint8_t TerminalStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_Audio_Descriptor_OutputTerminal_t;\r
+\r
+ /** @brief Audio class-specific Output Terminal Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific output terminal descriptor. This indicates to the host that the device\r
+ * contains an output audio sink, either to a physical terminal on the device, or a logical terminal (for example,\r
+ * a USB endpoint). See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_Descriptor_OutputTerminal_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * must be @ref AUDIO_DSUBTYPE_CSInterface_OutputTerminal.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * a value from the @ref Audio_CSInterface_AC_SubTypes_t enum.\r
+ */\r
+ uint8_t bTerminalID; /**< ID value of this terminal unit - must be a unique value within the device. */\r
+ uint16_t wTerminalType; /**< Type of terminal, a \c TERMINAL_* mask. */\r
+ uint8_t bAssocTerminal; /**< ID of associated input terminal, for physically grouped terminals\r
+ * such as the speaker and microphone of a phone handset.\r
+ */\r
+ uint8_t bSourceID; /**< ID value of the unit this terminal's audio is sourced from. */\r
+\r
+ uint8_t iTerminal; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_Audio_StdDescriptor_OutputTerminal_t;\r
+\r
+ /** @brief Audio class-specific Interface Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific interface descriptor. This follows a regular interface descriptor to\r
+ * supply extra information about the audio device's layout to the host. See the USB Audio specification for more\r
+ * details.\r
+ *\r
+ * @see @ref USB_Audio_StdDescriptor_Interface_AC_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.\r
+ */\r
+\r
+ uint16_t ACSpecification; /**< Binary coded decimal value, indicating the supported Audio Class specification version. */\r
+ uint16_t TotalLength; /**< Total length of the Audio class-specific descriptors, including this descriptor. */\r
+\r
+ uint8_t InCollection; /**< Total number of Audio Streaming interfaces linked to this Audio Control interface (must be 1). */\r
+ uint8_t InterfaceNumber; /**< Interface number of the associated Audio Streaming interface. */\r
+ } ATTR_PACKED USB_Audio_Descriptor_Interface_AC_t;\r
+\r
+ /** @brief Audio class-specific Interface Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific interface descriptor. This follows a regular interface descriptor to\r
+ * supply extra information about the audio device's layout to the host. See the USB Audio specification for more\r
+ * details.\r
+ *\r
+ * @see @ref USB_Audio_Descriptor_Interface_AC_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype;/**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.\r
+ */\r
+\r
+ uint16_t bcdADC; /**< Binary coded decimal value, indicating the supported Audio Class specification version. */\r
+ uint16_t wTotalLength; /**< Total length of the Audio class-specific descriptors, including this descriptor. */\r
+\r
+ uint8_t bInCollection; /**< Total number of Audio Streaming interfaces linked to this Audio Control interface (must be 1). */\r
+ uint8_t bInterfaceNumbers; /**< Interface number of the associated Audio Streaming interface. */\r
+ } ATTR_PACKED USB_Audio_StdDescriptor_Interface_AC_t;\r
+\r
+ /** @brief Audio class-specific Feature Unit Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific Feature Unit descriptor. This indicates to the host what features\r
+ * are present in the device's audio stream for basic control, such as per-channel volume. See the USB Audio\r
+ * specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_StdDescriptor_FeatureUnit_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * must be @ref AUDIO_DSUBTYPE_CSInterface_Feature.\r
+ */\r
+\r
+ uint8_t UnitID; /**< ID value of this feature unit - must be a unique value within the device. */\r
+ uint8_t SourceID; /**< Source ID value of the audio source input into this feature unit. */\r
+\r
+ uint8_t ControlSize; /**< Size of each element in the \c ChannelControls array. */\r
+ uint8_t ChannelControls[3]; /**< Feature masks for the control channel, and each separate audio channel. */\r
+\r
+ uint8_t FeatureUnitStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_Audio_Descriptor_FeatureUnit_t;\r
+\r
+ /** @brief Audio class-specific Feature Unit Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific Feature Unit descriptor. This indicates to the host what features\r
+ * are present in the device's audio stream for basic control, such as per-channel volume. See the USB Audio\r
+ * specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_Descriptor_FeatureUnit_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * must be @ref AUDIO_DSUBTYPE_CSInterface_Feature.\r
+ */\r
+\r
+ uint8_t bUnitID; /**< ID value of this feature unit - must be a unique value within the device. */\r
+ uint8_t bSourceID; /**< Source ID value of the audio source input into this feature unit. */\r
+\r
+ uint8_t bControlSize; /**< Size of each element in the \c ChannelControls array. */\r
+ uint8_t bmaControls[3]; /**< Feature masks for the control channel, and each separate audio channel. */\r
+\r
+ uint8_t iFeature; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_Audio_StdDescriptor_FeatureUnit_t;\r
+\r
+ /** @brief Audio class-specific Streaming Audio Interface Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific streaming interface descriptor. This indicates to the host\r
+ * how audio streams within the device are formatted. See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_StdDescriptor_Interface_AS_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.\r
+ */\r
+\r
+ uint8_t TerminalLink; /**< ID value of the output terminal this descriptor is describing. */\r
+\r
+ uint8_t FrameDelay; /**< Delay in frames resulting from the complete sample processing from input to output. */\r
+ uint16_t AudioFormat; /**< Format of the audio stream, see Audio Device Formats specification. */\r
+ } ATTR_PACKED USB_Audio_Descriptor_Interface_AS_t;\r
+\r
+ /** @brief Audio class-specific Streaming Audio Interface Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific streaming interface descriptor. This indicates to the host\r
+ * how audio streams within the device are formatted. See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_Descriptor_Interface_AS_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.\r
+ */\r
+\r
+ uint8_t bTerminalLink; /**< ID value of the output terminal this descriptor is describing. */\r
+\r
+ uint8_t bDelay; /**< Delay in frames resulting from the complete sample processing from input to output. */\r
+ uint16_t wFormatTag; /**< Format of the audio stream, see Audio Device Formats specification. */\r
+ } ATTR_PACKED USB_Audio_StdDescriptor_Interface_AS_t;\r
+\r
+ /** @brief Audio class-specific Format Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific audio format descriptor. This is used to give the host full details\r
+ * about the number of channels, the sample resolution, acceptable sample frequencies and encoding method used\r
+ * in the device's audio streams. See the USB Audio specification for more details.\r
+ *\r
+ * @note This descriptor <b>must</b> be followed by one or more @ref USB_Audio_SampleFreq_t elements containing\r
+ * the continuous or discrete sample frequencies.\r
+ *\r
+ * @see @ref USB_Audio_StdDescriptor_Format_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * must be @ref AUDIO_DSUBTYPE_CSInterface_FormatType.\r
+ */\r
+\r
+ uint8_t FormatType; /**< Format of the audio stream, see Audio Device Formats specification. */\r
+ uint8_t Channels; /**< Total number of discrete channels in the stream. */\r
+\r
+ uint8_t SubFrameSize; /**< Size in bytes of each channel's sample data in the stream. */\r
+ uint8_t BitResolution; /**< Bits of resolution of each channel's samples in the stream. */\r
+\r
+ uint8_t TotalDiscreteSampleRates; /**< Total number of discrete sample frequencies supported by the device. When\r
+ * zero, this must be followed by the lower and upper continuous sampling\r
+ * frequencies supported by the device; otherwise, this must be followed\r
+ * by the given number of discrete sampling frequencies supported.\r
+ */\r
+ } ATTR_PACKED USB_Audio_Descriptor_Format_t;\r
+\r
+ /** @brief 24-Bit Audio Frequency Structure.\r
+ *\r
+ * Type define for a 24bit audio sample frequency structure. As GCC does not contain a built in 24-bit datatype,\r
+ * this this structure is used to build up the value instead. Fill this structure with the @ref AUDIO_SAMPLE_FREQ() macro.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t Byte1; /**< Lowest 8 bits of the 24-bit value. */\r
+ uint8_t Byte2; /**< Middle 8 bits of the 24-bit value. */\r
+ uint8_t Byte3; /**< Upper 8 bits of the 24-bit value. */\r
+ } ATTR_PACKED USB_Audio_SampleFreq_t;\r
+\r
+ /** @brief Audio class-specific Format Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific audio format descriptor. This is used to give the host full details\r
+ * about the number of channels, the sample resolution, acceptable sample frequencies and encoding method used\r
+ * in the device's audio streams. See the USB Audio specification for more details.\r
+ *\r
+ * @note This descriptor <b>must</b> be followed by one or more 24-bit integer elements containing the continuous\r
+ * or discrete sample frequencies.\r
+ *\r
+ * @see @ref USB_Audio_Descriptor_Format_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * must be @ref AUDIO_DSUBTYPE_CSInterface_FormatType.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype;/**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * a value from the @ref Audio_CSInterface_AS_SubTypes_t enum.\r
+ */\r
+\r
+ uint8_t bFormatType; /**< Format of the audio stream, see Audio Device Formats specification. */\r
+ uint8_t bNrChannels; /**< Total number of discrete channels in the stream. */\r
+\r
+ uint8_t bSubFrameSize; /**< Size in bytes of each channel's sample data in the stream. */\r
+ uint8_t bBitResolution; /**< Bits of resolution of each channel's samples in the stream. */\r
+\r
+ uint8_t bSampleFrequencyType; /**< Total number of sample frequencies supported by the device. When\r
+ * zero, this must be followed by the lower and upper continuous sampling\r
+ * frequencies supported by the device; otherwise, this must be followed\r
+ * by the given number of discrete sampling frequencies supported.\r
+ */\r
+ } ATTR_PACKED USB_Audio_StdDescriptor_Format_t;\r
+\r
+ /** @brief Audio class-specific Streaming Endpoint Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific endpoint descriptor. This contains a regular endpoint\r
+ * descriptor with a few Audio-class-specific extensions. See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_StdDescriptor_StreamEndpoint_Std_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Endpoint_t Endpoint; /**< Standard endpoint descriptor describing the audio endpoint. */\r
+\r
+ uint8_t Refresh; /**< Always set to zero for Audio class devices. */\r
+ uint8_t SyncEndpointNumber; /**< Endpoint address to send synchronization information to, if needed (zero otherwise). */\r
+ } ATTR_PACKED USB_Audio_Descriptor_StreamEndpoint_Std_t;\r
+\r
+ /** @brief Audio class-specific Streaming Endpoint Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific endpoint descriptor. This contains a regular endpoint\r
+ * descriptor with a few Audio-class-specific extensions. See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_Descriptor_StreamEndpoint_Std_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a\r
+ * value given by the specific class.\r
+ */\r
+ uint8_t bEndpointAddress; /**< Logical address of the endpoint within the device for the current\r
+ * configuration, including direction mask.\r
+ */\r
+ uint8_t bmAttributes; /**< Endpoint attributes, comprised of a mask of the endpoint type (\c EP_TYPE_*)\r
+ * and attributes (\c ENDPOINT_ATTR_*) masks.\r
+ */\r
+ uint16_t wMaxPacketSize; /**< Size of the endpoint bank, in bytes. This indicates the maximum packet size\r
+ * that the endpoint can receive at a time.\r
+ */\r
+ uint8_t bInterval; /**< Polling interval in milliseconds for the endpoint if it is an INTERRUPT or\r
+ * ISOCHRONOUS type.\r
+ */\r
+\r
+ uint8_t bRefresh; /**< Always set to zero for Audio class devices. */\r
+ uint8_t bSynchAddress; /**< Endpoint address to send synchronization information to, if needed (zero otherwise). */\r
+ } ATTR_PACKED USB_Audio_StdDescriptor_StreamEndpoint_Std_t;\r
+\r
+ /** @brief Audio class-specific Extended Endpoint Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific extended endpoint descriptor. This contains extra information\r
+ * on the usage of endpoints used to stream audio in and out of the USB Audio device, and follows an Audio\r
+ * class-specific extended endpoint descriptor. See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_StdDescriptor_StreamEndpoint_Spc_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * a value from the @ref Audio_CSEndpoint_SubTypes_t enum.\r
+ */\r
+\r
+ uint8_t Attributes; /**< Audio class-specific endpoint attributes, such as @ref AUDIO_EP_FULL_PACKETS_ONLY. */\r
+\r
+ uint8_t LockDelayUnits; /**< Units used for the LockDelay field, see Audio class specification. */\r
+ uint16_t LockDelay; /**< Time required to internally lock endpoint's internal clock recovery circuitry. */\r
+ } ATTR_PACKED USB_Audio_Descriptor_StreamEndpoint_Spc_t;\r
+\r
+ /** @brief Audio class-specific Extended Endpoint Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific extended endpoint descriptor. This contains extra information\r
+ * on the usage of endpoints used to stream audio in and out of the USB Audio device, and follows an Audio\r
+ * class-specific extended endpoint descriptor. See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_Audio_Descriptor_StreamEndpoint_Spc_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors,\r
+ * a value from the @ref Audio_CSEndpoint_SubTypes_t enum.\r
+ */\r
+\r
+ uint8_t bmAttributes; /**< Audio class-specific endpoint attributes, such as @ref AUDIO_EP_FULL_PACKETS_ONLY. */\r
+\r
+ uint8_t bLockDelayUnits; /**< Units used for the LockDelay field, see Audio class specification. */\r
+ uint16_t wLockDelay; /**< Time required to internally lock endpoint's internal clock recovery circuitry. */\r
+ } ATTR_PACKED USB_Audio_StdDescriptor_StreamEndpoint_Spc_t;\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Common definitions and declarations for the library USB CDC Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassCDC\r
+ * @defgroup Group_USBClassCDCCommon Common Class Definitions\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB\r
+ * CDC Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _CDC_CLASS_COMMON_H_\r
+#define _CDC_CLASS_COMMON_H_\r
+\r
+ /* Includes: */\r
+ #include "../../Core/StdDescriptors.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_CDC_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Macros: */\r
+ /** @name Virtual Control Line Masks */\r
+ //@{\r
+ /** Mask for the DTR handshake line for use with the @ref CDC_REQ_SetControlLineState class-specific request\r
+ * from the host, to indicate that the DTR line state should be high.\r
+ */\r
+ #define CDC_CONTROL_LINE_OUT_DTR (1 << 0)\r
+\r
+ /** Mask for the RTS handshake line for use with the @ref CDC_REQ_SetControlLineState class-specific request\r
+ * from the host, to indicate that the RTS line state should be high.\r
+ */\r
+ #define CDC_CONTROL_LINE_OUT_RTS (1 << 1)\r
+\r
+ /** Mask for the DCD handshake line for use with the @ref CDC_NOTIF_SerialState class-specific notification\r
+ * from the device to the host, to indicate that the DCD line state is currently high.\r
+ */\r
+ #define CDC_CONTROL_LINE_IN_DCD (1 << 0)\r
+\r
+ /** Mask for the DSR handshake line for use with the @ref CDC_NOTIF_SerialState class-specific notification\r
+ * from the device to the host, to indicate that the DSR line state is currently high.\r
+ */\r
+ #define CDC_CONTROL_LINE_IN_DSR (1 << 1)\r
+\r
+ /** Mask for the BREAK handshake line for use with the @ref CDC_NOTIF_SerialState class-specific notification\r
+ * from the device to the host, to indicate that the BREAK line state is currently high.\r
+ */\r
+ #define CDC_CONTROL_LINE_IN_BREAK (1 << 2)\r
+\r
+ /** Mask for the RING handshake line for use with the @ref CDC_NOTIF_SerialState class-specific notification\r
+ * from the device to the host, to indicate that the RING line state is currently high.\r
+ */\r
+ #define CDC_CONTROL_LINE_IN_RING (1 << 3)\r
+\r
+ /** Mask for use with the @ref CDC_NOTIF_SerialState class-specific notification from the device to the host,\r
+ * to indicate that a framing error has occurred on the virtual serial port.\r
+ */\r
+ #define CDC_CONTROL_LINE_IN_FRAMEERROR (1 << 4)\r
+\r
+ /** Mask for use with the @ref CDC_NOTIF_SerialState class-specific notification from the device to the host,\r
+ * to indicate that a parity error has occurred on the virtual serial port.\r
+ */\r
+ #define CDC_CONTROL_LINE_IN_PARITYERROR (1 << 5)\r
+\r
+ /** Mask for use with the @ref CDC_NOTIF_SerialState class-specific notification from the device to the host,\r
+ * to indicate that a data overrun error has occurred on the virtual serial port.\r
+ */\r
+ #define CDC_CONTROL_LINE_IN_OVERRUNERROR (1 << 6)\r
+ //@}\r
+ \r
+ /** Macro to define a CDC class-specific functional descriptor. CDC functional descriptors have a\r
+ * uniform structure but variable sized data payloads, thus cannot be represented accurately by\r
+ * a single typedef struct. A macro is used instead so that functional descriptors can be created\r
+ * easily by specifying the size of the payload. This allows \c sizeof() to work correctly.\r
+ *\r
+ * @param DataSize Size in bytes of the CDC functional descriptor's data payload.\r
+ */\r
+ #define CDC_FUNCTIONAL_DESCRIPTOR(DataSize) \\r
+ struct \\r
+ { \\r
+ USB_Descriptor_Header_t Header; \\r
+ uint8_t SubType; \\r
+ uint8_t Data[DataSize]; \\r
+ }\r
+\r
+ /* Enums: */\r
+ /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the CDC\r
+ * device class.\r
+ */\r
+ enum CDC_Descriptor_ClassSubclassProtocol_t\r
+ {\r
+ CDC_CSCP_CDCClass = 0x02, /**< Descriptor Class value indicating that the device or interface\r
+ * belongs to the CDC class.\r
+ */\r
+ CDC_CSCP_NoSpecificSubclass = 0x00, /**< Descriptor Subclass value indicating that the device or interface\r
+ * belongs to no specific subclass of the CDC class.\r
+ */\r
+ CDC_CSCP_ACMSubclass = 0x02, /**< Descriptor Subclass value indicating that the device or interface\r
+ * belongs to the Abstract Control Model CDC subclass.\r
+ */\r
+ CDC_CSCP_ATCommandProtocol = 0x01, /**< Descriptor Protocol value indicating that the device or interface\r
+ * belongs to the AT Command protocol of the CDC class.\r
+ */\r
+ CDC_CSCP_NoSpecificProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or interface\r
+ * belongs to no specific protocol of the CDC class.\r
+ */\r
+ CDC_CSCP_VendorSpecificProtocol = 0xFF, /**< Descriptor Protocol value indicating that the device or interface\r
+ * belongs to a vendor-specific protocol of the CDC class.\r
+ */\r
+ CDC_CSCP_CDCDataClass = 0x0A, /**< Descriptor Class value indicating that the device or interface\r
+ * belongs to the CDC Data class.\r
+ */\r
+ CDC_CSCP_NoDataSubclass = 0x00, /**< Descriptor Subclass value indicating that the device or interface\r
+ * belongs to no specific subclass of the CDC data class.\r
+ */\r
+ CDC_CSCP_NoDataProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or interface\r
+ * belongs to no specific protocol of the CDC data class.\r
+ */\r
+ };\r
+ \r
+ /** Enum for the CDC class specific control requests that can be issued by the USB bus host. */\r
+ enum CDC_ClassRequests_t\r
+ {\r
+ CDC_REQ_SendEncapsulatedCommand = 0x00, /**< CDC class-specific request to send an encapsulated command to the device. */\r
+ CDC_REQ_GetEncapsulatedResponse = 0x01, /**< CDC class-specific request to retrieve an encapsulated command response from the device. */\r
+ CDC_REQ_SetLineEncoding = 0x20, /**< CDC class-specific request to set the current virtual serial port configuration settings. */\r
+ CDC_REQ_GetLineEncoding = 0x21, /**< CDC class-specific request to get the current virtual serial port configuration settings. */\r
+ CDC_REQ_SetControlLineState = 0x22, /**< CDC class-specific request to set the current virtual serial port handshake line states. */\r
+ CDC_REQ_SendBreak = 0x23, /**< CDC class-specific request to send a break to the receiver via the carrier channel. */\r
+ };\r
+\r
+ /** Enum for the CDC class specific notification requests that can be issued by a CDC device to a host. */\r
+ enum CDC_ClassNotifications_t\r
+ {\r
+ CDC_NOTIF_SerialState = 0x20, /**< Notification type constant for a change in the virtual serial port\r
+ * handshake line states, for use with a @ref USB_Request_Header_t\r
+ * notification structure when sent to the host via the CDC notification\r
+ * endpoint.\r
+ */\r
+ };\r
+\r
+ /** Enum for the CDC class specific interface descriptor subtypes. */\r
+ enum CDC_DescriptorSubtypes_t\r
+ {\r
+ CDC_DSUBTYPE_CSInterface_Header = 0x00, /**< CDC class-specific Header functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_CallManagement = 0x01, /**< CDC class-specific Call Management functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_ACM = 0x02, /**< CDC class-specific Abstract Control Model functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_DirectLine = 0x03, /**< CDC class-specific Direct Line functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_TelephoneRinger = 0x04, /**< CDC class-specific Telephone Ringer functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_TelephoneCall = 0x05, /**< CDC class-specific Telephone Call functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_Union = 0x06, /**< CDC class-specific Union functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_CountrySelection = 0x07, /**< CDC class-specific Country Selection functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_TelephoneOpModes = 0x08, /**< CDC class-specific Telephone Operation Modes functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_USBTerminal = 0x09, /**< CDC class-specific USB Terminal functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_NetworkChannel = 0x0A, /**< CDC class-specific Network Channel functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_ProtocolUnit = 0x0B, /**< CDC class-specific Protocol Unit functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_ExtensionUnit = 0x0C, /**< CDC class-specific Extension Unit functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_MultiChannel = 0x0D, /**< CDC class-specific Multi-Channel Management functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_CAPI = 0x0E, /**< CDC class-specific Common ISDN API functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_Ethernet = 0x0F, /**< CDC class-specific Ethernet functional descriptor. */\r
+ CDC_DSUBTYPE_CSInterface_ATM = 0x10, /**< CDC class-specific Asynchronous Transfer Mode functional descriptor. */\r
+ };\r
+\r
+ /** Enum for the possible line encoding formats of a virtual serial port. */\r
+ enum CDC_LineEncodingFormats_t\r
+ {\r
+ CDC_LINEENCODING_OneStopBit = 0, /**< Each frame contains one stop bit. */\r
+ CDC_LINEENCODING_OneAndAHalfStopBits = 1, /**< Each frame contains one and a half stop bits. */\r
+ CDC_LINEENCODING_TwoStopBits = 2, /**< Each frame contains two stop bits. */\r
+ };\r
+\r
+ /** Enum for the possible line encoding parity settings of a virtual serial port. */\r
+ enum CDC_LineEncodingParity_t\r
+ {\r
+ CDC_PARITY_None = 0, /**< No parity bit mode on each frame. */\r
+ CDC_PARITY_Odd = 1, /**< Odd parity bit mode on each frame. */\r
+ CDC_PARITY_Even = 2, /**< Even parity bit mode on each frame. */\r
+ CDC_PARITY_Mark = 3, /**< Mark parity bit mode on each frame. */\r
+ CDC_PARITY_Space = 4, /**< Space parity bit mode on each frame. */\r
+ };\r
+\r
+ /* Type Defines: */\r
+ /** @brief CDC class-specific Functional Header Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for a CDC class-specific functional header descriptor. This indicates to the host that the device\r
+ * contains one or more CDC functional data descriptors, which give the CDC interface's capabilities and configuration.\r
+ * See the CDC class specification for more details.\r
+ *\r
+ * @see @ref USB_CDC_StdDescriptor_FunctionalHeader_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between CDC class-specific descriptors,\r
+ * must be @ref CDC_DSUBTYPE_CSInterface_Header.\r
+ */\r
+ uint16_t CDCSpecification; /**< Version number of the CDC specification implemented by the device,\r
+ * encoded in BCD format.\r
+ */\r
+ } ATTR_PACKED USB_CDC_Descriptor_FunctionalHeader_t;\r
+\r
+ /** @brief CDC class-specific Functional Header Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a CDC class-specific functional header descriptor. This indicates to the host that the device\r
+ * contains one or more CDC functional data descriptors, which give the CDC interface's capabilities and configuration.\r
+ * See the CDC class specification for more details.\r
+ *\r
+ * @see @ref USB_CDC_Descriptor_FunctionalHeader_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bFunctionLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ uint8_t bDescriptorSubType; /**< Sub type value used to distinguish between CDC class-specific descriptors,\r
+ * must be @ref CDC_DSUBTYPE_CSInterface_Header.\r
+ */\r
+ uint16_t bcdCDC; /**< Version number of the CDC specification implemented by the device, encoded in BCD format. */\r
+ } ATTR_PACKED USB_CDC_StdDescriptor_FunctionalHeader_t;\r
+\r
+ /** @brief CDC class-specific Functional ACM Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for a CDC class-specific functional ACM descriptor. This indicates to the host that the CDC interface\r
+ * supports the CDC ACM subclass of the CDC specification. See the CDC class specification for more details.\r
+ *\r
+ * @see @ref USB_CDC_StdDescriptor_FunctionalACM_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between CDC class-specific descriptors,\r
+ * must be @ref CDC_DSUBTYPE_CSInterface_ACM.\r
+ */\r
+ uint8_t Capabilities; /**< Capabilities of the ACM interface, given as a bit mask. For most devices,\r
+ * this should be set to a fixed value of 0x06 - for other capabilities, refer\r
+ * to the CDC ACM specification.\r
+ */\r
+ } ATTR_PACKED USB_CDC_Descriptor_FunctionalACM_t;\r
+\r
+ /** @brief CDC class-specific Functional ACM Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a CDC class-specific functional ACM descriptor. This indicates to the host that the CDC interface\r
+ * supports the CDC ACM subclass of the CDC specification. See the CDC class specification for more details.\r
+ *\r
+ * @see @ref USB_CDC_Descriptor_FunctionalACM_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bFunctionLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ uint8_t bDescriptorSubType; /**< Sub type value used to distinguish between CDC class-specific descriptors,\r
+ * must be @ref CDC_DSUBTYPE_CSInterface_ACM.\r
+ */\r
+ uint8_t bmCapabilities; /**< Capabilities of the ACM interface, given as a bit mask. For most devices,\r
+ * this should be set to a fixed value of 0x06 - for other capabilities, refer\r
+ * to the CDC ACM specification.\r
+ */\r
+ } ATTR_PACKED USB_CDC_StdDescriptor_FunctionalACM_t;\r
+\r
+ /** @brief CDC class-specific Functional Union Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for a CDC class-specific functional Union descriptor. This indicates to the host that specific\r
+ * CDC control and data interfaces are related. See the CDC class specification for more details.\r
+ *\r
+ * @see @ref USB_CDC_StdDescriptor_FunctionalUnion_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between CDC class-specific descriptors,\r
+ * must be @ref CDC_DSUBTYPE_CSInterface_Union.\r
+ */\r
+ uint8_t MasterInterfaceNumber; /**< Interface number of the CDC Control interface. */\r
+ uint8_t SlaveInterfaceNumber; /**< Interface number of the CDC Data interface. */\r
+ } ATTR_PACKED USB_CDC_Descriptor_FunctionalUnion_t;\r
+\r
+ /** @brief CDC class-specific Functional Union Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a CDC class-specific functional Union descriptor. This indicates to the host that specific\r
+ * CDC control and data interfaces are related. See the CDC class specification for more details.\r
+ *\r
+ * @see @ref USB_CDC_Descriptor_FunctionalUnion_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bFunctionLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ uint8_t bDescriptorSubType; /**< Sub type value used to distinguish between CDC class-specific descriptors,\r
+ * must be @ref CDC_DSUBTYPE_CSInterface_Union.\r
+ */\r
+ uint8_t bMasterInterface; /**< Interface number of the CDC Control interface. */\r
+ uint8_t bSlaveInterface0; /**< Interface number of the CDC Data interface. */\r
+ } ATTR_PACKED USB_CDC_StdDescriptor_FunctionalUnion_t;\r
+ \r
+ /** @brief CDC Virtual Serial Port Line Encoding Settings Structure.\r
+ *\r
+ * Type define for a CDC Line Encoding structure, used to hold the various encoding parameters for a virtual\r
+ * serial port.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t BaudRateBPS; /**< Baud rate of the virtual serial port, in bits per second. */\r
+ uint8_t CharFormat; /**< Character format of the virtual serial port, a value from the\r
+ * @ref CDC_LineEncodingFormats_t enum.\r
+ */\r
+ uint8_t ParityType; /**< Parity setting of the virtual serial port, a value from the\r
+ * @ref CDC_LineEncodingParity_t enum.\r
+ */\r
+ uint8_t DataBits; /**< Bits of data per character of the virtual serial port. */\r
+ } ATTR_PACKED CDC_LineEncoding_t;\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Common definitions and declarations for the library USB HID Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassHID\r
+ * @defgroup Group_USBClassHIDCommon Common Class Definitions\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB\r
+ * HID Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _HID_CLASS_COMMON_H_\r
+#define _HID_CLASS_COMMON_H_\r
+\r
+ /* Includes: */\r
+ #include "../../Core/StdDescriptors.h"\r
+ #include "HIDParser.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_HID_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Macros: */\r
+ /** @name Keyboard Standard Report Modifier Masks */\r
+ //@{\r
+ /** Constant for a keyboard report modifier byte, indicating that the keyboard's left control key is currently pressed. */\r
+ #define HID_KEYBOARD_MODIFER_LEFTCTRL (1 << 0)\r
+\r
+ /** Constant for a keyboard report modifier byte, indicating that the keyboard's left shift key is currently pressed. */\r
+ #define HID_KEYBOARD_MODIFER_LEFTSHIFT (1 << 1)\r
+\r
+ /** Constant for a keyboard report modifier byte, indicating that the keyboard's left alt key is currently pressed. */\r
+ #define HID_KEYBOARD_MODIFER_LEFTALT (1 << 2)\r
+\r
+ /** Constant for a keyboard report modifier byte, indicating that the keyboard's left GUI key is currently pressed. */\r
+ #define HID_KEYBOARD_MODIFER_LEFTGUI (1 << 3)\r
+\r
+ /** Constant for a keyboard report modifier byte, indicating that the keyboard's right control key is currently pressed. */\r
+ #define HID_KEYBOARD_MODIFER_RIGHTCTRL (1 << 4)\r
+\r
+ /** Constant for a keyboard report modifier byte, indicating that the keyboard's right shift key is currently pressed. */\r
+ #define HID_KEYBOARD_MODIFER_RIGHTSHIFT (1 << 5)\r
+\r
+ /** Constant for a keyboard report modifier byte, indicating that the keyboard's right alt key is currently pressed. */\r
+ #define HID_KEYBOARD_MODIFER_RIGHTALT (1 << 6)\r
+\r
+ /** Constant for a keyboard report modifier byte, indicating that the keyboard's right GUI key is currently pressed. */\r
+ #define HID_KEYBOARD_MODIFER_RIGHTGUI (1 << 7)\r
+ //@}\r
+ \r
+ /** @name Keyboard Standard Report LED Masks */\r
+ //@{\r
+ /** Constant for a keyboard output report LED byte, indicating that the host's NUM LOCK mode is currently set. */\r
+ #define HID_KEYBOARD_LED_NUMLOCK (1 << 0)\r
+\r
+ /** Constant for a keyboard output report LED byte, indicating that the host's CAPS LOCK mode is currently set. */\r
+ #define HID_KEYBOARD_LED_CAPSLOCK (1 << 1)\r
+\r
+ /** Constant for a keyboard output report LED byte, indicating that the host's SCROLL LOCK mode is currently set. */\r
+ #define HID_KEYBOARD_LED_SCROLLLOCK (1 << 2)\r
+\r
+ /** Constant for a keyboard output report LED byte, indicating that the host's KATANA mode is currently set. */\r
+ #define HID_KEYBOARD_LED_KATANA (1 << 3)\r
+ //@}\r
+\r
+ /** @name Keyboard Standard Report Key Scan-codes */\r
+ //@{ \r
+ #define HID_KEYBOARD_SC_ERROR_ROLLOVER 0x01\r
+ #define HID_KEYBOARD_SC_POST_FAIL 0x02\r
+ #define HID_KEYBOARD_SC_ERROR_UNDEFINED 0x03\r
+ #define HID_KEYBOARD_SC_A 0x04\r
+ #define HID_KEYBOARD_SC_B 0x05\r
+ #define HID_KEYBOARD_SC_C 0x06\r
+ #define HID_KEYBOARD_SC_D 0x07\r
+ #define HID_KEYBOARD_SC_E 0x08\r
+ #define HID_KEYBOARD_SC_F 0x09\r
+ #define HID_KEYBOARD_SC_G 0x0A\r
+ #define HID_KEYBOARD_SC_H 0x0B\r
+ #define HID_KEYBOARD_SC_I 0x0C\r
+ #define HID_KEYBOARD_SC_J 0x0D\r
+ #define HID_KEYBOARD_SC_K 0x0E\r
+ #define HID_KEYBOARD_SC_L 0x0F\r
+ #define HID_KEYBOARD_SC_M 0x10\r
+ #define HID_KEYBOARD_SC_N 0x11\r
+ #define HID_KEYBOARD_SC_O 0x12\r
+ #define HID_KEYBOARD_SC_P 0x13\r
+ #define HID_KEYBOARD_SC_Q 0x14\r
+ #define HID_KEYBOARD_SC_R 0x15\r
+ #define HID_KEYBOARD_SC_S 0x16\r
+ #define HID_KEYBOARD_SC_T 0x17\r
+ #define HID_KEYBOARD_SC_U 0x18\r
+ #define HID_KEYBOARD_SC_V 0x19\r
+ #define HID_KEYBOARD_SC_W 0x1A\r
+ #define HID_KEYBOARD_SC_X 0x1B\r
+ #define HID_KEYBOARD_SC_Y 0x1C\r
+ #define HID_KEYBOARD_SC_Z 0x1D\r
+ #define HID_KEYBOARD_SC_1_AND_EXCLAMATION 0x1E\r
+ #define HID_KEYBOARD_SC_2_AND_AT 0x1F\r
+ #define HID_KEYBOARD_SC_3_AND_HASHMARK 0x20\r
+ #define HID_KEYBOARD_SC_4_AND_DOLLAR 0x21\r
+ #define HID_KEYBOARD_SC_5_AND_PERCENTAGE 0x22\r
+ #define HID_KEYBOARD_SC_6_AND_CARET 0x23\r
+ #define HID_KEYBOARD_SC_7_AND_AND_AMPERSAND 0x24\r
+ #define HID_KEYBOARD_SC_8_AND_ASTERISK 0x25\r
+ #define HID_KEYBOARD_SC_9_AND_OPENING_PARENTHESIS 0x26\r
+ #define HID_KEYBOARD_SC_0_AND_CLOSING_PARENTHESIS 0x27\r
+ #define HID_KEYBOARD_SC_ENTER 0x28\r
+ #define HID_KEYBOARD_SC_ESCAPE 0x29\r
+ #define HID_KEYBOARD_SC_BACKSPACE 0x2A\r
+ #define HID_KEYBOARD_SC_TAB 0x2B\r
+ #define HID_KEYBOARD_SC_SPACE 0x2C\r
+ #define HID_KEYBOARD_SC_MINUS_AND_UNDERSCORE 0x2D\r
+ #define HID_KEYBOARD_SC_EQUAL_AND_PLUS 0x2E\r
+ #define HID_KEYBOARD_SC_OPENING_BRACKET_AND_OPENING_BRACE 0x2F\r
+ #define HID_KEYBOARD_SC_CLOSING_BRACKET_AND_CLOSING_BRACE 0x30\r
+ #define HID_KEYBOARD_SC_BACKSLASH_AND_PIPE 0x31\r
+ #define HID_KEYBOARD_SC_NON_US_HASHMARK_AND_TILDE 0x32\r
+ #define HID_KEYBOARD_SC_SEMICOLON_AND_COLON 0x33\r
+ #define HID_KEYBOARD_SC_APOSTROPHE_AND_QUOTE 0x34\r
+ #define HID_KEYBOARD_SC_GRAVE_ACCENT_AND_TILDE 0x35\r
+ #define HID_KEYBOARD_SC_COMMA_AND_LESS_THAN_SIGN 0x36\r
+ #define HID_KEYBOARD_SC_DOT_AND_GREATER_THAN_SIGN 0x37\r
+ #define HID_KEYBOARD_SC_SLASH_AND_QUESTION_MARK 0x38\r
+ #define HID_KEYBOARD_SC_CAPS_LOCK 0x39\r
+ #define HID_KEYBOARD_SC_F1 0x3A\r
+ #define HID_KEYBOARD_SC_F2 0x3B\r
+ #define HID_KEYBOARD_SC_F3 0x3C\r
+ #define HID_KEYBOARD_SC_F4 0x3D\r
+ #define HID_KEYBOARD_SC_F5 0x3E\r
+ #define HID_KEYBOARD_SC_F6 0x3F\r
+ #define HID_KEYBOARD_SC_F7 0x40\r
+ #define HID_KEYBOARD_SC_F8 0x41\r
+ #define HID_KEYBOARD_SC_F9 0x42\r
+ #define HID_KEYBOARD_SC_F10 0x43\r
+ #define HID_KEYBOARD_SC_F11 0x44\r
+ #define HID_KEYBOARD_SC_F12 0x45\r
+ #define HID_KEYBOARD_SC_PRINT_SCREEN 0x46\r
+ #define HID_KEYBOARD_SC_SCROLL_LOCK 0x47\r
+ #define HID_KEYBOARD_SC_PAUSE 0x48\r
+ #define HID_KEYBOARD_SC_INSERT 0x49\r
+ #define HID_KEYBOARD_SC_HOME 0x4A\r
+ #define HID_KEYBOARD_SC_PAGE_UP 0x4B\r
+ #define HID_KEYBOARD_SC_DELETE 0x4C\r
+ #define HID_KEYBOARD_SC_END 0x4D\r
+ #define HID_KEYBOARD_SC_PAGE_DOWN 0x4E\r
+ #define HID_KEYBOARD_SC_RIGHT_ARROW 0x4F\r
+ #define HID_KEYBOARD_SC_LEFT_ARROW 0x50\r
+ #define HID_KEYBOARD_SC_DOWN_ARROW 0x51\r
+ #define HID_KEYBOARD_SC_UP_ARROW 0x52\r
+ #define HID_KEYBOARD_SC_NUM_LOCK 0x53\r
+ #define HID_KEYBOARD_SC_KEYPAD_SLASH 0x54\r
+ #define HID_KEYBOARD_SC_KEYPAD_ASTERISK 0x55\r
+ #define HID_KEYBOARD_SC_KEYPAD_MINUS 0x56\r
+ #define HID_KEYBOARD_SC_KEYPAD_PLUS 0x57\r
+ #define HID_KEYBOARD_SC_KEYPAD_ENTER 0x58\r
+ #define HID_KEYBOARD_SC_KEYPAD_1_AND_END 0x59\r
+ #define HID_KEYBOARD_SC_KEYPAD_2_AND_DOWN_ARROW 0x5A\r
+ #define HID_KEYBOARD_SC_KEYPAD_3_AND_PAGE_DOWN 0x5B\r
+ #define HID_KEYBOARD_SC_KEYPAD_4_AND_LEFT_ARROW 0x5C\r
+ #define HID_KEYBOARD_SC_KEYPAD_5 0x5D\r
+ #define HID_KEYBOARD_SC_KEYPAD_6_AND_RIGHT_ARROW 0x5E\r
+ #define HID_KEYBOARD_SC_KEYPAD_7_AND_HOME 0x5F\r
+ #define HID_KEYBOARD_SC_KEYPAD_8_AND_UP_ARROW 0x60\r
+ #define HID_KEYBOARD_SC_KEYPAD_9_AND_PAGE_UP 0x61\r
+ #define HID_KEYBOARD_SC_KEYPAD_0_AND_INSERT 0x62\r
+ #define HID_KEYBOARD_SC_KEYPAD_DOT_AND_DELETE 0x63\r
+ #define HID_KEYBOARD_SC_NON_US_BACKSLASH_AND_PIPE 0x64 \r
+ #define HID_KEYBOARD_SC_POWER 0x66\r
+ #define HID_KEYBOARD_SC_EQUAL_SIGN 0x67\r
+ #define HID_KEYBOARD_SC_F13 0x68\r
+ #define HID_KEYBOARD_SC_F14 0x69\r
+ #define HID_KEYBOARD_SC_F15 0x6A\r
+ #define HID_KEYBOARD_SC_F16 0x6B\r
+ #define HID_KEYBOARD_SC_F17 0x6C\r
+ #define HID_KEYBOARD_SC_F18 0x6D\r
+ #define HID_KEYBOARD_SC_F19 0x6E\r
+ #define HID_KEYBOARD_SC_F20 0x6F\r
+ #define HID_KEYBOARD_SC_F21 0x70\r
+ #define HID_KEYBOARD_SC_F22 0x71\r
+ #define HID_KEYBOARD_SC_F23 0x72\r
+ #define HID_KEYBOARD_SC_F24 0x73\r
+ #define HID_KEYBOARD_SC_EXECUTE 0x74\r
+ #define HID_KEYBOARD_SC_HELP 0x75\r
+ #define HID_KEYBOARD_SC_MANU 0x76\r
+ #define HID_KEYBOARD_SC_SELECT 0x77\r
+ #define HID_KEYBOARD_SC_STOP 0x78\r
+ #define HID_KEYBOARD_SC_AGAIN 0x79\r
+ #define HID_KEYBOARD_SC_UNDO 0x7A\r
+ #define HID_KEYBOARD_SC_CUT 0x7B\r
+ #define HID_KEYBOARD_SC_COPY 0x7C\r
+ #define HID_KEYBOARD_SC_PASTE 0x7D\r
+ #define HID_KEYBOARD_SC_FIND 0x7E\r
+ #define HID_KEYBOARD_SC_MUTE 0x7F\r
+ #define HID_KEYBOARD_SC_VOLUME_UP 0x80\r
+ #define HID_KEYBOARD_SC_VOLUME_DOWN 0x81\r
+ #define HID_KEYBOARD_SC_LOCKING_CAPS_LOCK 0x82\r
+ #define HID_KEYBOARD_SC_LOCKING_NUM_LOCK 0x83\r
+ #define HID_KEYBOARD_SC_LOCKING_SCROLL_LOCK 0x84\r
+ #define HID_KEYBOARD_SC_KEYPAD_COMMA 0x85\r
+ #define HID_KEYBOARD_SC_KEYPAD_EQUAL_SIGN 0x86\r
+ #define HID_KEYBOARD_SC_INTERNATIONAL1 0x87\r
+ #define HID_KEYBOARD_SC_INTERNATIONAL2 0x88\r
+ #define HID_KEYBOARD_SC_INTERNATIONAL3 0x89\r
+ #define HID_KEYBOARD_SC_INTERNATIONAL4 0x8A\r
+ #define HID_KEYBOARD_SC_INTERNATIONAL5 0x8B\r
+ #define HID_KEYBOARD_SC_INTERNATIONAL6 0x8C\r
+ #define HID_KEYBOARD_SC_INTERNATIONAL7 0x8D\r
+ #define HID_KEYBOARD_SC_INTERNATIONAL8 0x8E\r
+ #define HID_KEYBOARD_SC_INTERNATIONAL9 0x8F\r
+ #define HID_KEYBOARD_SC_LANG1 0x90\r
+ #define HID_KEYBOARD_SC_LANG2 0x91\r
+ #define HID_KEYBOARD_SC_LANG3 0x92\r
+ #define HID_KEYBOARD_SC_LANG4 0x93\r
+ #define HID_KEYBOARD_SC_LANG5 0x94\r
+ #define HID_KEYBOARD_SC_LANG6 0x95\r
+ #define HID_KEYBOARD_SC_LANG7 0x96\r
+ #define HID_KEYBOARD_SC_LANG8 0x97\r
+ #define HID_KEYBOARD_SC_LANG9 0x98\r
+ #define HID_KEYBOARD_SC_ALTERNATE_ERASE 0x99\r
+ #define HID_KEYBOARD_SC_SISREQ 0x9A\r
+ #define HID_KEYBOARD_SC_CANCEL 0x9B\r
+ #define HID_KEYBOARD_SC_CLEAR 0x9C\r
+ #define HID_KEYBOARD_SC_PRIOR 0x9D\r
+ #define HID_KEYBOARD_SC_RETURN 0x9E\r
+ #define HID_KEYBOARD_SC_SEPARATOR 0x9F\r
+ #define HID_KEYBOARD_SC_OUT 0xA0\r
+ #define HID_KEYBOARD_SC_OPER 0xA1\r
+ #define HID_KEYBOARD_SC_CLEAR_AND_AGAIN 0xA2\r
+ #define HID_KEYBOARD_SC_CRSEL_ANDPROPS 0xA3\r
+ #define HID_KEYBOARD_SC_EXSEL 0xA4\r
+ #define HID_KEYBOARD_SC_KEYPAD_00 0xB0\r
+ #define HID_KEYBOARD_SC_KEYPAD_000 0xB1\r
+ #define HID_KEYBOARD_SC_THOUSANDS_SEPARATOR 0xB2\r
+ #define HID_KEYBOARD_SC_DECIMAL_SEPARATOR 0xB3\r
+ #define HID_KEYBOARD_SC_CURRENCY_UNIT 0xB4\r
+ #define HID_KEYBOARD_SC_CURRENCY_SUB_UNIT 0xB5\r
+ #define HID_KEYBOARD_SC_KEYPAD_OPENING_PARENTHESIS 0xB6\r
+ #define HID_KEYBOARD_SC_KEYPAD_CLOSING_PARENTHESIS 0xB7\r
+ #define HID_KEYBOARD_SC_KEYPAD_OPENING_BRACE 0xB8\r
+ #define HID_KEYBOARD_SC_KEYPAD_CLOSING_BRACE 0xB9\r
+ #define HID_KEYBOARD_SC_KEYPAD_TAB 0xBA\r
+ #define HID_KEYBOARD_SC_KEYPAD_BACKSPACE 0xBB\r
+ #define HID_KEYBOARD_SC_KEYPAD_A 0xBC\r
+ #define HID_KEYBOARD_SC_KEYPAD_B 0xBD\r
+ #define HID_KEYBOARD_SC_KEYPAD_C 0xBE\r
+ #define HID_KEYBOARD_SC_KEYPAD_D 0xBF\r
+ #define HID_KEYBOARD_SC_KEYPAD_E 0xC0\r
+ #define HID_KEYBOARD_SC_KEYPAD_F 0xC1\r
+ #define HID_KEYBOARD_SC_KEYPAD_XOR 0xC2\r
+ #define HID_KEYBOARD_SC_KEYPAD_CARET 0xC3\r
+ #define HID_KEYBOARD_SC_KEYPAD_PERCENTAGE 0xC4\r
+ #define HID_KEYBOARD_SC_KEYPAD_LESS_THAN_SIGN 0xC5\r
+ #define HID_KEYBOARD_SC_KEYPAD_GREATER_THAN_SIGN 0xC6\r
+ #define HID_KEYBOARD_SC_KEYPAD_AMP 0xC7\r
+ #define HID_KEYBOARD_SC_KEYPAD_AMP_AMP 0xC8\r
+ #define HID_KEYBOARD_SC_KEYPAD_PIPE 0xC9\r
+ #define HID_KEYBOARD_SC_KEYPAD_PIPE_PIPE 0xCA\r
+ #define HID_KEYBOARD_SC_KEYPAD_COLON 0xCB\r
+ #define HID_KEYBOARD_SC_KEYPAD_HASHMARK 0xCC\r
+ #define HID_KEYBOARD_SC_KEYPAD_SPACE 0xCD\r
+ #define HID_KEYBOARD_SC_KEYPAD_AT 0xCE\r
+ #define HID_KEYBOARD_SC_KEYPAD_EXCLAMATION_SIGN 0xCF\r
+ #define HID_KEYBOARD_SC_KEYPAD_MEMORY_STORE 0xD0\r
+ #define HID_KEYBOARD_SC_KEYPAD_MEMORY_RECALL 0xD1\r
+ #define HID_KEYBOARD_SC_KEYPAD_MEMORY_CLEAR 0xD2\r
+ #define HID_KEYBOARD_SC_KEYPAD_MEMORY_ADD 0xD3\r
+ #define HID_KEYBOARD_SC_KEYPAD_MEMORY_SUBTRACT 0xD4\r
+ #define HID_KEYBOARD_SC_KEYPAD_MEMORY_MULTIPLY 0xD5\r
+ #define HID_KEYBOARD_SC_KEYPAD_MEMORY_DIVIDE 0xD6\r
+ #define HID_KEYBOARD_SC_KEYPAD_PLUS_AND_MINUS 0xD7\r
+ #define HID_KEYBOARD_SC_KEYPAD_CLEAR 0xD8\r
+ #define HID_KEYBOARD_SC_KEYPAD_CLEAR_ENTRY 0xD9\r
+ #define HID_KEYBOARD_SC_KEYPAD_BINARY 0xDA\r
+ #define HID_KEYBOARD_SC_KEYPAD_OCTAL 0xDB\r
+ #define HID_KEYBOARD_SC_KEYPAD_DECIMAL 0xDC\r
+ #define HID_KEYBOARD_SC_KEYPAD_HEXADECIMAL 0xDD\r
+ #define HID_KEYBOARD_SC_LEFT_CONTROL 0xE0\r
+ #define HID_KEYBOARD_SC_LEFT_SHIFT 0xE1\r
+ #define HID_KEYBOARD_SC_LEFT_ALT 0xE2\r
+ #define HID_KEYBOARD_SC_LEFT_GUI 0xE3\r
+ #define HID_KEYBOARD_SC_RIGHT_CONTROL 0xE4\r
+ #define HID_KEYBOARD_SC_RIGHT_SHIFT 0xE5\r
+ #define HID_KEYBOARD_SC_RIGHT_ALT 0xE6\r
+ #define HID_KEYBOARD_SC_RIGHT_GUI 0xE7\r
+ //@}\r
+\r
+ /** @name Common HID Device Report Descriptors */\r
+ //@{\r
+ /** \hideinitializer\r
+ * A list of HID report item array elements that describe a typical HID USB Joystick. The resulting report\r
+ * descriptor is structured according to the following layout:\r
+ *\r
+ * \code\r
+ * struct\r
+ * {\r
+ * intB_t X; // Signed X axis value\r
+ * intB_t Y; // Signed Y axis value\r
+ * int8_t Z; // Signed Z axis value\r
+ * // Additional axis elements here\r
+ * uintA_t Buttons; // Pressed buttons bitmask\r
+ * } Joystick_Report;\r
+ * \endcode\r
+ *\r
+ * Where \c uintA_t is a type large enough to hold one bit per button, and \c intB_t is a type large enough to hold the\r
+ * ranges of the signed \c MinAxisVal and \c MaxAxisVal values.\r
+ *\r
+ * @param NumAxis Number of axis in the joystick (8-bit)\r
+ * @param MinAxisVal Minimum logical axis value (16-bit).\r
+ * @param MaxAxisVal Maximum logical axis value (16-bit).\r
+ * @param MinPhysicalVal Minimum physical axis value, for movement resolution calculations (16-bit).\r
+ * @param MaxPhysicalVal Maximum physical axis value, for movement resolution calculations (16-bit).\r
+ * @param Buttons Total number of buttons in the device (8-bit).\r
+ */\r
+ #define HID_DESCRIPTOR_JOYSTICK(NumAxis, MinAxisVal, MaxAxisVal, MinPhysicalVal, MaxPhysicalVal, Buttons) \\r
+ HID_RI_USAGE_PAGE(8, 0x01), \\r
+ HID_RI_USAGE(8, 0x04), \\r
+ HID_RI_COLLECTION(8, 0x01), \\r
+ HID_RI_USAGE(8, 0x01), \\r
+ HID_RI_COLLECTION(8, 0x00), \\r
+ HID_RI_USAGE_MINIMUM(8, 0x30), \\r
+ HID_RI_USAGE_MAXIMUM(8, (0x30 + (NumAxis - 1))), \\r
+ HID_RI_LOGICAL_MINIMUM(16, MinAxisVal), \\r
+ HID_RI_LOGICAL_MAXIMUM(16, MaxAxisVal), \\r
+ HID_RI_PHYSICAL_MINIMUM(16, MinPhysicalVal), \\r
+ HID_RI_PHYSICAL_MAXIMUM(16, MaxPhysicalVal), \\r
+ HID_RI_REPORT_COUNT(8, NumAxis), \\r
+ HID_RI_REPORT_SIZE(8, ((((MinAxisVal >= -0xFF) && (MaxAxisVal <= 0xFF)) ? 8 : 16))), \\r
+ HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \\r
+ HID_RI_END_COLLECTION(0), \\r
+ HID_RI_USAGE_PAGE(8, 0x09), \\r
+ HID_RI_USAGE_MINIMUM(8, 0x01), \\r
+ HID_RI_USAGE_MAXIMUM(8, Buttons), \\r
+ HID_RI_LOGICAL_MINIMUM(8, 0x00), \\r
+ HID_RI_LOGICAL_MAXIMUM(8, 0x01), \\r
+ HID_RI_REPORT_SIZE(8, 0x01), \\r
+ HID_RI_REPORT_COUNT(8, Buttons), \\r
+ HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \\r
+ HID_RI_REPORT_SIZE(8, (8 - (Buttons % 8))), \\r
+ HID_RI_REPORT_COUNT(8, 0x01), \\r
+ HID_RI_INPUT(8, HID_IOF_CONSTANT), \\r
+ HID_RI_END_COLLECTION(0)\r
+\r
+ /** \hideinitializer\r
+ * A list of HID report item array elements that describe a typical HID USB keyboard. The resulting report descriptor\r
+ * is compatible with @ref USB_KeyboardReport_Data_t when \c MaxKeys is equal to 6. For other values, the report will\r
+ * be structured according to the following layout:\r
+ *\r
+ * \code\r
+ * struct\r
+ * {\r
+ * uint8_t Modifier; // Keyboard modifier byte indicating pressed modifier keys (HID_KEYBOARD_MODIFER_* masks)\r
+ * uint8_t Reserved; // Reserved for OEM use, always set to 0.\r
+ * uint8_t KeyCode[MaxKeys]; // Length determined by the number of keys that can be reported\r
+ * } Keyboard_Report;\r
+ * \endcode\r
+ *\r
+ * @param MaxKeys Number of simultaneous keys that can be reported at the one time (8-bit).\r
+ */\r
+ #define HID_DESCRIPTOR_KEYBOARD(MaxKeys) \\r
+ HID_RI_USAGE_PAGE(8, 0x01), \\r
+ HID_RI_USAGE(8, 0x06), \\r
+ HID_RI_COLLECTION(8, 0x01), \\r
+ HID_RI_USAGE_PAGE(8, 0x07), \\r
+ HID_RI_USAGE_MINIMUM(8, 0xE0), \\r
+ HID_RI_USAGE_MAXIMUM(8, 0xE7), \\r
+ HID_RI_LOGICAL_MINIMUM(8, 0x00), \\r
+ HID_RI_LOGICAL_MAXIMUM(8, 0x01), \\r
+ HID_RI_REPORT_SIZE(8, 0x01), \\r
+ HID_RI_REPORT_COUNT(8, 0x08), \\r
+ HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \\r
+ HID_RI_REPORT_COUNT(8, 0x01), \\r
+ HID_RI_REPORT_SIZE(8, 0x08), \\r
+ HID_RI_INPUT(8, HID_IOF_CONSTANT), \\r
+ HID_RI_USAGE_PAGE(8, 0x08), \\r
+ HID_RI_USAGE_MINIMUM(8, 0x01), \\r
+ HID_RI_USAGE_MAXIMUM(8, 0x05), \\r
+ HID_RI_REPORT_COUNT(8, 0x05), \\r
+ HID_RI_REPORT_SIZE(8, 0x01), \\r
+ HID_RI_OUTPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE | HID_IOF_NON_VOLATILE), \\r
+ HID_RI_REPORT_COUNT(8, 0x01), \\r
+ HID_RI_REPORT_SIZE(8, 0x03), \\r
+ HID_RI_OUTPUT(8, HID_IOF_CONSTANT), \\r
+ HID_RI_LOGICAL_MINIMUM(8, 0x00), \\r
+ HID_RI_LOGICAL_MAXIMUM(8, 0x65), \\r
+ HID_RI_USAGE_PAGE(8, 0x07), \\r
+ HID_RI_USAGE_MINIMUM(8, 0x00), \\r
+ HID_RI_USAGE_MAXIMUM(8, 0x65), \\r
+ HID_RI_REPORT_COUNT(8, MaxKeys), \\r
+ HID_RI_REPORT_SIZE(8, 0x08), \\r
+ HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_ARRAY | HID_IOF_ABSOLUTE), \\r
+ HID_RI_END_COLLECTION(0)\r
+\r
+ /** \hideinitializer\r
+ * A list of HID report item array elements that describe a typical HID USB mouse. The resulting report descriptor\r
+ * is compatible with @ref USB_MouseReport_Data_t if the \c MinAxisVal and \c MaxAxisVal values fit within a \c int8_t range\r
+ * and the number of Buttons is less than 8. For other values, the report is structured according to the following layout:\r
+ *\r
+ * \code\r
+ * struct\r
+ * {\r
+ * uintA_t Buttons; // Pressed buttons bitmask\r
+ * intB_t X; // X axis value\r
+ * intB_t Y; // Y axis value\r
+ * } Mouse_Report;\r
+ * \endcode\r
+ *\r
+ * Where \c intA_t is a type large enough to hold one bit per button, and \c intB_t is a type large enough to hold the\r
+ * ranges of the signed \c MinAxisVal and \c MaxAxisVal values.\r
+ *\r
+ * @param MinAxisVal Minimum X/Y logical axis value (16-bit).\r
+ * @param MaxAxisVal Maximum X/Y logical axis value (16-bit).\r
+ * @param MinPhysicalVal Minimum X/Y physical axis value, for movement resolution calculations (16-bit).\r
+ * @param MaxPhysicalVal Maximum X/Y physical axis value, for movement resolution calculations (16-bit).\r
+ * @param Buttons Total number of buttons in the device (8-bit).\r
+ * @param AbsoluteCoords Boolean true to use absolute X/Y coordinates (e.g. touchscreen).\r
+ */\r
+ #define HID_DESCRIPTOR_MOUSE(MinAxisVal, MaxAxisVal, MinPhysicalVal, MaxPhysicalVal, Buttons, AbsoluteCoords) \\r
+ HID_RI_USAGE_PAGE(8, 0x01), \\r
+ HID_RI_USAGE(8, 0x02), \\r
+ HID_RI_COLLECTION(8, 0x01), \\r
+ HID_RI_USAGE(8, 0x01), \\r
+ HID_RI_COLLECTION(8, 0x00), \\r
+ HID_RI_USAGE_PAGE(8, 0x09), \\r
+ HID_RI_USAGE_MINIMUM(8, 0x01), \\r
+ HID_RI_USAGE_MAXIMUM(8, Buttons), \\r
+ HID_RI_LOGICAL_MINIMUM(8, 0x00), \\r
+ HID_RI_LOGICAL_MAXIMUM(8, 0x01), \\r
+ HID_RI_REPORT_COUNT(8, Buttons), \\r
+ HID_RI_REPORT_SIZE(8, 0x01), \\r
+ HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \\r
+ HID_RI_REPORT_COUNT(8, 0x01), \\r
+ HID_RI_REPORT_SIZE(8, (8 - (Buttons % 8))), \\r
+ HID_RI_INPUT(8, HID_IOF_CONSTANT), \\r
+ HID_RI_USAGE_PAGE(8, 0x01), \\r
+ HID_RI_USAGE(8, 0x30), \\r
+ HID_RI_USAGE(8, 0x31), \\r
+ HID_RI_LOGICAL_MINIMUM(16, MinAxisVal), \\r
+ HID_RI_LOGICAL_MAXIMUM(16, MaxAxisVal), \\r
+ HID_RI_PHYSICAL_MINIMUM(16, MinPhysicalVal), \\r
+ HID_RI_PHYSICAL_MAXIMUM(16, MaxPhysicalVal), \\r
+ HID_RI_REPORT_COUNT(8, 0x02), \\r
+ HID_RI_REPORT_SIZE(8, ((((MinAxisVal >= -0xFF) && (MaxAxisVal <= 0xFF)) ? 8 : 16))), \\r
+ HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | (AbsoluteCoords ? HID_IOF_ABSOLUTE : HID_IOF_RELATIVE)), \\r
+ HID_RI_END_COLLECTION(0), \\r
+ HID_RI_END_COLLECTION(0)\r
+\r
+ /** \hideinitializer\r
+ * A list of HID report item array elements that describe a typical Vendor Defined byte array HID report descriptor,\r
+ * used for transporting arbitrary data between the USB host and device via HID reports. The resulting report should be\r
+ * a uint8_t byte array of the specified length in both Device to Host (IN) and Host to Device (OUT) directions.\r
+ *\r
+ * @param VendorPageNum Vendor Defined HID Usage Page index, ranging from 0x00 to 0xFF.\r
+ * @param CollectionUsage Vendor Usage for the encompassing report IN and OUT collection, ranging from 0x00 to 0xFF.\r
+ * @param DataINUsage Vendor Usage for the IN report data, ranging from 0x00 to 0xFF.\r
+ * @param DataOUTUsage Vendor Usage for the OUT report data, ranging from 0x00 to 0xFF. \r
+ * @param NumBytes Length of the data IN and OUT reports.\r
+ */\r
+ #define HID_DESCRIPTOR_VENDOR(VendorPageNum, CollectionUsage, DataINUsage, DataOUTUsage, NumBytes) \\r
+ HID_RI_USAGE_PAGE(16, (0xFF00 | VendorPageNum)), \\r
+ HID_RI_USAGE(8, CollectionUsage), \\r
+ HID_RI_COLLECTION(8, 0x01), \\r
+ HID_RI_USAGE(8, DataINUsage), \\r
+ HID_RI_LOGICAL_MINIMUM(8, 0x00), \\r
+ HID_RI_LOGICAL_MAXIMUM(8, 0xFF), \\r
+ HID_RI_REPORT_SIZE(8, 0x08), \\r
+ HID_RI_REPORT_COUNT(8, NumBytes), \\r
+ HID_RI_INPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE), \\r
+ HID_RI_USAGE(8, DataOUTUsage), \\r
+ HID_RI_LOGICAL_MINIMUM(8, 0x00), \\r
+ HID_RI_LOGICAL_MAXIMUM(8, 0xFF), \\r
+ HID_RI_REPORT_SIZE(8, 0x08), \\r
+ HID_RI_REPORT_COUNT(8, NumBytes), \\r
+ HID_RI_OUTPUT(8, HID_IOF_DATA | HID_IOF_VARIABLE | HID_IOF_ABSOLUTE | HID_IOF_NON_VOLATILE), \\r
+ HID_RI_END_COLLECTION(0)\r
+ //@}\r
+ \r
+ /* Type Defines: */\r
+ /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the HID\r
+ * device class.\r
+ */\r
+ enum HID_Descriptor_ClassSubclassProtocol_t\r
+ {\r
+ HID_CSCP_HIDClass = 0x03, /**< Descriptor Class value indicating that the device or interface\r
+ * belongs to the HID class.\r
+ */\r
+ HID_CSCP_NonBootSubclass = 0x00, /**< Descriptor Subclass value indicating that the device or interface\r
+ * does not implement a HID boot protocol.\r
+ */\r
+ HID_CSCP_BootSubclass = 0x01, /**< Descriptor Subclass value indicating that the device or interface\r
+ * implements a HID boot protocol.\r
+ */\r
+ HID_CSCP_NonBootProtocol = 0x00, /**< Descriptor Protocol value indicating that the device or interface\r
+ * does not belong to a HID boot protocol.\r
+ */\r
+ HID_CSCP_KeyboardBootProtocol = 0x01, /**< Descriptor Protocol value indicating that the device or interface\r
+ * belongs to the Keyboard HID boot protocol.\r
+ */\r
+ HID_CSCP_MouseBootProtocol = 0x02, /**< Descriptor Protocol value indicating that the device or interface\r
+ * belongs to the Mouse HID boot protocol.\r
+ */\r
+ };\r
+ \r
+ /** Enum for the HID class specific control requests that can be issued by the USB bus host. */\r
+ enum HID_ClassRequests_t\r
+ {\r
+ HID_REQ_GetReport = 0x01, /**< HID class-specific Request to get the current HID report from the device. */\r
+ HID_REQ_GetIdle = 0x02, /**< HID class-specific Request to get the current device idle count. */\r
+ HID_REQ_GetProtocol = 0x03, /**< HID class-specific Request to get the current HID report protocol mode. */\r
+ HID_REQ_SetReport = 0x09, /**< HID class-specific Request to set the current HID report to the device. */\r
+ HID_REQ_SetIdle = 0x0A, /**< HID class-specific Request to set the device's idle count. */\r
+ HID_REQ_SetProtocol = 0x0B, /**< HID class-specific Request to set the current HID report protocol mode. */\r
+ };\r
+\r
+ /** Enum for the HID class specific descriptor types. */\r
+ enum HID_DescriptorTypes_t\r
+ {\r
+ HID_DTYPE_HID = 0x21, /**< Descriptor header type value, to indicate a HID class HID descriptor. */\r
+ HID_DTYPE_Report = 0x22, /**< Descriptor header type value, to indicate a HID class HID report descriptor. */\r
+ };\r
+\r
+ /** Enum for the different types of HID reports. */\r
+ enum HID_ReportItemTypes_t\r
+ {\r
+ HID_REPORT_ITEM_In = 0, /**< Indicates that the item is an IN report type. */\r
+ HID_REPORT_ITEM_Out = 1, /**< Indicates that the item is an OUT report type. */\r
+ HID_REPORT_ITEM_Feature = 2, /**< Indicates that the item is a FEATURE report type. */\r
+ };\r
+\r
+ /** @brief HID class-specific HID Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID\r
+ * specification for details on the structure elements.\r
+ *\r
+ * @see @ref USB_HID_StdDescriptor_HID_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+\r
+ uint16_t HIDSpec; /**< BCD encoded version that the HID descriptor and device complies to. */\r
+ uint8_t CountryCode; /**< Country code of the localized device, or zero if universal. */\r
+\r
+ uint8_t TotalReportDescriptors; /**< Total number of HID report descriptors for the interface. */\r
+\r
+ uint8_t HIDReportType; /**< Type of HID report, set to @ref HID_DTYPE_Report. */\r
+ uint16_t HIDReportLength; /**< Length of the associated HID report descriptor, in bytes. */\r
+ } ATTR_PACKED USB_HID_Descriptor_HID_t;\r
+\r
+ /** @brief HID class-specific HID Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID\r
+ * specification for details on the structure elements.\r
+ *\r
+ * @see @ref USB_HID_Descriptor_HID_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint16_t bcdHID; /**< BCD encoded version that the HID descriptor and device complies to. */\r
+ uint8_t bCountryCode; /**< Country code of the localized device, or zero if universal. */\r
+\r
+ uint8_t bNumDescriptors; /**< Total number of HID report descriptors for the interface. */\r
+\r
+ uint8_t bDescriptorType2; /**< Type of HID report, set to @ref HID_DTYPE_Report. */\r
+ uint16_t wDescriptorLength; /**< Length of the associated HID report descriptor, in bytes. */\r
+ } ATTR_PACKED USB_HID_StdDescriptor_HID_t;\r
+\r
+ /** @brief Standard HID Boot Protocol Mouse Report.\r
+ *\r
+ * Type define for a standard Boot Protocol Mouse report\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t Button; /**< Button mask for currently pressed buttons in the mouse. */\r
+ int8_t X; /**< Current delta X movement of the mouse. */\r
+ int8_t Y; /**< Current delta Y movement on the mouse. */\r
+ } ATTR_PACKED USB_MouseReport_Data_t;\r
+\r
+ /** @brief Standard HID Boot Protocol Keyboard Report.\r
+ *\r
+ * Type define for a standard Boot Protocol Keyboard report\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t Modifier; /**< Keyboard modifier byte, indicating pressed modifier keys (a combination of\r
+ * \c HID_KEYBOARD_MODIFER_* masks).\r
+ */\r
+ uint8_t Reserved; /**< Reserved for OEM use, always set to 0. */\r
+ uint8_t KeyCode[6]; /**< Key codes of the currently pressed keys. */\r
+ } ATTR_PACKED USB_KeyboardReport_Data_t;\r
+\r
+ /** Type define for the data type used to store HID report descriptor elements. */\r
+ typedef uint8_t USB_Descriptor_HIDReport_Datatype_t;\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Human Interface Device (HID) Class report descriptor parser\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#define __INCLUDE_FROM_HID_DRIVER\r
+#include "HIDParser.h"\r
+\r
+uint8_t USB_ProcessHIDReport(const uint8_t* ReportData,\r
+ uint16_t ReportSize,\r
+ HID_ReportInfo_t* const ParserData)\r
+{\r
+ HID_StateTable_t StateTable[HID_STATETABLE_STACK_DEPTH];\r
+ HID_StateTable_t* CurrStateTable = &StateTable[0];\r
+ HID_CollectionPath_t* CurrCollectionPath = NULL;\r
+ HID_ReportSizeInfo_t* CurrReportIDInfo = &ParserData->ReportIDSizes[0];\r
+ uint16_t UsageList[HID_USAGE_STACK_DEPTH];\r
+ uint8_t UsageListSize = 0;\r
+ HID_MinMax_t UsageMinMax = {0, 0};\r
+\r
+ memset(ParserData, 0x00, sizeof(HID_ReportInfo_t));\r
+ memset(CurrStateTable, 0x00, sizeof(HID_StateTable_t));\r
+ memset(CurrReportIDInfo, 0x00, sizeof(HID_ReportSizeInfo_t));\r
+\r
+ ParserData->TotalDeviceReports = 1;\r
+\r
+ while (ReportSize)\r
+ {\r
+ uint8_t HIDReportItem = *ReportData;\r
+ uint32_t ReportItemData = 0;\r
+\r
+ ReportData++;\r
+ ReportSize--;\r
+\r
+ switch (HIDReportItem & HID_RI_DATA_SIZE_MASK)\r
+ {\r
+ case HID_RI_DATA_BITS_32:\r
+ ReportItemData = le32_to_cpu(*((uint32_t*)ReportData));\r
+ ReportSize -= 4;\r
+ ReportData += 4;\r
+ break;\r
+ case HID_RI_DATA_BITS_16:\r
+ ReportItemData = le16_to_cpu(*((uint16_t*)ReportData));\r
+ ReportSize -= 2;\r
+ ReportData += 2;\r
+ break;\r
+ case HID_RI_DATA_BITS_8:\r
+ ReportItemData = *((uint8_t*)ReportData);\r
+ ReportSize -= 1;\r
+ ReportData += 1;\r
+ break;\r
+ }\r
+\r
+ switch (HIDReportItem & (HID_RI_TYPE_MASK | HID_RI_TAG_MASK))\r
+ {\r
+ case HID_RI_PUSH(0):\r
+ if (CurrStateTable == &StateTable[HID_STATETABLE_STACK_DEPTH - 1])\r
+ return HID_PARSE_HIDStackOverflow;\r
+\r
+ memcpy((CurrStateTable + 1),\r
+ CurrStateTable,\r
+ sizeof(HID_ReportItem_t));\r
+\r
+ CurrStateTable++;\r
+ break;\r
+ case HID_RI_POP(0):\r
+ if (CurrStateTable == &StateTable[0])\r
+ return HID_PARSE_HIDStackUnderflow;\r
+\r
+ CurrStateTable--;\r
+ break;\r
+ case HID_RI_USAGE_PAGE(0):\r
+ if ((HIDReportItem & HID_RI_DATA_SIZE_MASK) == HID_RI_DATA_BITS_32)\r
+ CurrStateTable->Attributes.Usage.Page = (ReportItemData >> 16);\r
+ \r
+ CurrStateTable->Attributes.Usage.Page = ReportItemData;\r
+ break;\r
+ case HID_RI_LOGICAL_MINIMUM(0):\r
+ CurrStateTable->Attributes.Logical.Minimum = ReportItemData;\r
+ break;\r
+ case HID_RI_LOGICAL_MAXIMUM(0):\r
+ CurrStateTable->Attributes.Logical.Maximum = ReportItemData;\r
+ break;\r
+ case HID_RI_PHYSICAL_MINIMUM(0):\r
+ CurrStateTable->Attributes.Physical.Minimum = ReportItemData;\r
+ break;\r
+ case HID_RI_PHYSICAL_MAXIMUM(0):\r
+ CurrStateTable->Attributes.Physical.Maximum = ReportItemData;\r
+ break;\r
+ case HID_RI_UNIT_EXPONENT(0):\r
+ CurrStateTable->Attributes.Unit.Exponent = ReportItemData;\r
+ break;\r
+ case HID_RI_UNIT(0):\r
+ CurrStateTable->Attributes.Unit.Type = ReportItemData;\r
+ break;\r
+ case HID_RI_REPORT_SIZE(0):\r
+ CurrStateTable->Attributes.BitSize = ReportItemData;\r
+ break;\r
+ case HID_RI_REPORT_COUNT(0):\r
+ CurrStateTable->ReportCount = ReportItemData;\r
+ break;\r
+ case HID_RI_REPORT_ID(0):\r
+ CurrStateTable->ReportID = ReportItemData;\r
+\r
+ if (ParserData->UsingReportIDs)\r
+ {\r
+ CurrReportIDInfo = NULL;\r
+\r
+ for (uint8_t i = 0; i < ParserData->TotalDeviceReports; i++)\r
+ {\r
+ if (ParserData->ReportIDSizes[i].ReportID == CurrStateTable->ReportID)\r
+ {\r
+ CurrReportIDInfo = &ParserData->ReportIDSizes[i];\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (CurrReportIDInfo == NULL)\r
+ {\r
+ if (ParserData->TotalDeviceReports == HID_MAX_REPORT_IDS)\r
+ return HID_PARSE_InsufficientReportIDItems;\r
+\r
+ CurrReportIDInfo = &ParserData->ReportIDSizes[ParserData->TotalDeviceReports++];\r
+ memset(CurrReportIDInfo, 0x00, sizeof(HID_ReportSizeInfo_t));\r
+ }\r
+ }\r
+\r
+ ParserData->UsingReportIDs = true;\r
+\r
+ CurrReportIDInfo->ReportID = CurrStateTable->ReportID;\r
+ break;\r
+ case HID_RI_USAGE(0):\r
+ if (UsageListSize == HID_USAGE_STACK_DEPTH)\r
+ return HID_PARSE_UsageListOverflow;\r
+\r
+ UsageList[UsageListSize++] = ReportItemData;\r
+ break;\r
+ case HID_RI_USAGE_MINIMUM(0):\r
+ UsageMinMax.Minimum = ReportItemData;\r
+ break;\r
+ case HID_RI_USAGE_MAXIMUM(0):\r
+ UsageMinMax.Maximum = ReportItemData;\r
+ break;\r
+ case HID_RI_COLLECTION(0):\r
+ if (CurrCollectionPath == NULL)\r
+ {\r
+ CurrCollectionPath = &ParserData->CollectionPaths[0];\r
+ }\r
+ else\r
+ {\r
+ HID_CollectionPath_t* ParentCollectionPath = CurrCollectionPath;\r
+\r
+ CurrCollectionPath = &ParserData->CollectionPaths[1];\r
+\r
+ while (CurrCollectionPath->Parent != NULL)\r
+ {\r
+ if (CurrCollectionPath == &ParserData->CollectionPaths[HID_MAX_COLLECTIONS - 1])\r
+ return HID_PARSE_InsufficientCollectionPaths;\r
+\r
+ CurrCollectionPath++;\r
+ }\r
+\r
+ CurrCollectionPath->Parent = ParentCollectionPath;\r
+ }\r
+\r
+ CurrCollectionPath->Type = ReportItemData;\r
+ CurrCollectionPath->Usage.Page = CurrStateTable->Attributes.Usage.Page;\r
+\r
+ if (UsageListSize)\r
+ {\r
+ CurrCollectionPath->Usage.Usage = UsageList[0];\r
+\r
+ for (uint8_t i = 0; i < UsageListSize; i++)\r
+ UsageList[i] = UsageList[i + 1];\r
+\r
+ UsageListSize--;\r
+ }\r
+ else if (UsageMinMax.Minimum <= UsageMinMax.Maximum)\r
+ {\r
+ CurrCollectionPath->Usage.Usage = UsageMinMax.Minimum++;\r
+ }\r
+\r
+ break;\r
+ case HID_RI_END_COLLECTION(0):\r
+ if (CurrCollectionPath == NULL)\r
+ return HID_PARSE_UnexpectedEndCollection;\r
+\r
+ CurrCollectionPath = CurrCollectionPath->Parent;\r
+ break;\r
+ case HID_RI_INPUT(0):\r
+ case HID_RI_OUTPUT(0):\r
+ case HID_RI_FEATURE(0):\r
+ for (uint8_t ReportItemNum = 0; ReportItemNum < CurrStateTable->ReportCount; ReportItemNum++)\r
+ {\r
+ HID_ReportItem_t NewReportItem;\r
+\r
+ memcpy(&NewReportItem.Attributes,\r
+ &CurrStateTable->Attributes,\r
+ sizeof(HID_ReportItem_Attributes_t));\r
+\r
+ NewReportItem.ItemFlags = ReportItemData;\r
+ NewReportItem.CollectionPath = CurrCollectionPath;\r
+ NewReportItem.ReportID = CurrStateTable->ReportID;\r
+\r
+ if (UsageListSize)\r
+ {\r
+ NewReportItem.Attributes.Usage.Usage = UsageList[0];\r
+\r
+ for (uint8_t i = 0; i < UsageListSize; i++)\r
+ UsageList[i] = UsageList[i + 1];\r
+\r
+ UsageListSize--;\r
+ }\r
+ else if (UsageMinMax.Minimum <= UsageMinMax.Maximum)\r
+ {\r
+ NewReportItem.Attributes.Usage.Usage = UsageMinMax.Minimum++;\r
+ }\r
+\r
+ uint8_t ItemTypeTag = (HIDReportItem & (HID_RI_TYPE_MASK | HID_RI_TAG_MASK));\r
+\r
+ if (ItemTypeTag == HID_RI_INPUT(0))\r
+ NewReportItem.ItemType = HID_REPORT_ITEM_In;\r
+ else if (ItemTypeTag == HID_RI_OUTPUT(0))\r
+ NewReportItem.ItemType = HID_REPORT_ITEM_Out;\r
+ else\r
+ NewReportItem.ItemType = HID_REPORT_ITEM_Feature;\r
+\r
+ NewReportItem.BitOffset = CurrReportIDInfo->ReportSizeBits[NewReportItem.ItemType];\r
+\r
+ CurrReportIDInfo->ReportSizeBits[NewReportItem.ItemType] += CurrStateTable->Attributes.BitSize;\r
+\r
+ if (ParserData->LargestReportSizeBits < NewReportItem.BitOffset)\r
+ ParserData->LargestReportSizeBits = NewReportItem.BitOffset;\r
+\r
+ if (ParserData->TotalReportItems == HID_MAX_REPORTITEMS)\r
+ return HID_PARSE_InsufficientReportItems;\r
+\r
+ memcpy(&ParserData->ReportItems[ParserData->TotalReportItems],\r
+ &NewReportItem, sizeof(HID_ReportItem_t));\r
+\r
+ if (!(ReportItemData & HID_IOF_CONSTANT) && CALLBACK_HIDParser_FilterHIDReportItem(&NewReportItem))\r
+ ParserData->TotalReportItems++;\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+ if ((HIDReportItem & HID_RI_TYPE_MASK) == HID_RI_TYPE_MAIN)\r
+ {\r
+ UsageMinMax.Minimum = 0;\r
+ UsageMinMax.Maximum = 0;\r
+ UsageListSize = 0;\r
+ }\r
+ }\r
+\r
+ if (!(ParserData->TotalReportItems))\r
+ return HID_PARSE_NoUnfilteredReportItems;\r
+\r
+ return HID_PARSE_Successful;\r
+}\r
+\r
+bool USB_GetHIDReportItemInfo(const uint8_t* ReportData,\r
+ HID_ReportItem_t* const ReportItem)\r
+{\r
+ if (ReportItem == NULL)\r
+ return false;\r
+\r
+ uint16_t DataBitsRem = ReportItem->Attributes.BitSize;\r
+ uint16_t CurrentBit = ReportItem->BitOffset;\r
+ uint32_t BitMask = (1 << 0);\r
+\r
+ if (ReportItem->ReportID)\r
+ {\r
+ if (ReportItem->ReportID != ReportData[0])\r
+ return false;\r
+\r
+ ReportData++;\r
+ }\r
+\r
+ ReportItem->PreviousValue = ReportItem->Value;\r
+ ReportItem->Value = 0;\r
+\r
+ while (DataBitsRem--)\r
+ {\r
+ if (ReportData[CurrentBit / 8] & (1 << (CurrentBit % 8)))\r
+ ReportItem->Value |= BitMask;\r
+\r
+ CurrentBit++;\r
+ BitMask <<= 1;\r
+ }\r
+\r
+ return true;\r
+}\r
+\r
+void USB_SetHIDReportItemInfo(uint8_t* ReportData,\r
+ HID_ReportItem_t* const ReportItem)\r
+{\r
+ if (ReportItem == NULL)\r
+ return;\r
+\r
+ uint16_t DataBitsRem = ReportItem->Attributes.BitSize;\r
+ uint16_t CurrentBit = ReportItem->BitOffset;\r
+ uint32_t BitMask = (1 << 0);\r
+\r
+ if (ReportItem->ReportID)\r
+ {\r
+ ReportData[0] = ReportItem->ReportID;\r
+ ReportData++;\r
+ }\r
+\r
+ ReportItem->PreviousValue = ReportItem->Value;\r
+\r
+ while (DataBitsRem--)\r
+ {\r
+ if (ReportItem->Value & (1 << (CurrentBit % 8)))\r
+ ReportData[CurrentBit / 8] |= BitMask;\r
+\r
+ CurrentBit++;\r
+ BitMask <<= 1;\r
+ }\r
+}\r
+\r
+uint16_t USB_GetHIDReportSize(HID_ReportInfo_t* const ParserData,\r
+ const uint8_t ReportID,\r
+ const uint8_t ReportType)\r
+{\r
+ for (uint8_t i = 0; i < HID_MAX_REPORT_IDS; i++)\r
+ {\r
+ uint16_t ReportSizeBits = ParserData->ReportIDSizes[i].ReportSizeBits[ReportType];\r
+\r
+ if (ParserData->ReportIDSizes[i].ReportID == ReportID)\r
+ return (ReportSizeBits / 8) + ((ReportSizeBits % 8) ? 1 : 0);\r
+ }\r
+\r
+ return 0;\r
+}\r
--- /dev/null
+/*\r
+ * @brief USB Human Interface Device (HID) Class report descriptor parser\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_HIDParser HID Report Parser\r
+ * @brief USB Human Interface Device (HID) Class report descriptor parser.\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - nxpUSBlib/Drivers/USB/Class/Host/HIDParser.c <i>(Makefile source module name: NXPUSBLIB_SRC_USB)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Human Interface Device (HID) class report descriptor parser. This module implements a parser than is\r
+ * capable of processing a complete HID report descriptor, and outputting a flat structure containing the\r
+ * contents of the report in an a more friendly format. The parsed data may then be further processed and used\r
+ * within an application to process sent and received HID reports to and from an attached HID device.\r
+ *\r
+ * A HID report descriptor consists of a set of HID report items, which describe the function and layout\r
+ * of data exchanged between a HID device and a host, including both the physical encoding of each item\r
+ * (such as a button, key press or joystick axis) in the sent and received data packets - known as "reports" -\r
+ * as well as other information about each item such as the usages, data range, physical location and other\r
+ * characteristics. In this way a HID device can retain a high degree of flexibility in its capabilities, as it\r
+ * is not forced to comply with a given report layout or feature-set.\r
+ *\r
+ * This module also contains routines for the processing of data in an actual HID report, using the parsed report\r
+ * descriptor data as a guide for the encoding.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __HIDPARSER_H__\r
+#define __HIDPARSER_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../../Common/Common.h"\r
+\r
+ #include "HIDReportData.h"\r
+ #include "HIDClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Macros: */\r
+ #if !defined(HID_STATETABLE_STACK_DEPTH) || defined(__DOXYGEN__)\r
+ /** Constant indicating the maximum stack depth of the state table. A larger state table\r
+ * allows for more PUSH/POP report items to be nested, but consumes more memory. By default\r
+ * this is set to 2 levels (allowing non-nested PUSH items) but this can be overridden by\r
+ * defining \c HID_STATETABLE_STACK_DEPTH to another value in the user project makefile, passing the\r
+ * define to the compiler using the -D compiler switch.\r
+ */\r
+ #define HID_STATETABLE_STACK_DEPTH 2\r
+ #endif\r
+\r
+ #if !defined(HID_USAGE_STACK_DEPTH) || defined(__DOXYGEN__)\r
+ /** Constant indicating the maximum stack depth of the usage table. A larger usage table\r
+ * allows for more USAGE items to be indicated sequentially for REPORT COUNT entries of more than\r
+ * one, but requires more stack space. By default this is set to 8 levels (allowing for a report\r
+ * item with a count of 8) but this can be overridden by defining \c HID_USAGE_STACK_DEPTH to another\r
+ * value in the user project makefile, passing the define to the compiler using the -D compiler\r
+ * switch.\r
+ */\r
+ #define HID_USAGE_STACK_DEPTH 8\r
+ #endif\r
+\r
+ #if !defined(HID_MAX_COLLECTIONS) || defined(__DOXYGEN__)\r
+ /** Constant indicating the maximum number of COLLECTION items (nested or unnested) that can be\r
+ * processed in the report item descriptor. A large value allows for more COLLECTION items to be\r
+ * processed, but consumes more memory. By default this is set to 10 collections, but this can be\r
+ * overridden by defining \c HID_MAX_COLLECTIONS to another value in the user project makefile, passing\r
+ * the define to the compiler using the -D compiler switch.\r
+ */\r
+ #define HID_MAX_COLLECTIONS 10\r
+ #endif\r
+\r
+ #if !defined(HID_MAX_REPORTITEMS) || defined(__DOXYGEN__)\r
+ /** Constant indicating the maximum number of report items (IN, OUT or FEATURE) that can be processed\r
+ * in the report item descriptor and stored in the user HID Report Info structure. A large value allows\r
+ * for more report items to be stored, but consumes more memory. By default this is set to 20 items,\r
+ * but this can be overridden by defining \c HID_MAX_REPORTITEMS to another value in the user project\r
+ * makefile, and passing the define to the compiler using the -D compiler switch.\r
+ */\r
+ #define HID_MAX_REPORTITEMS 20\r
+ #endif\r
+\r
+ #if !defined(HID_MAX_REPORT_IDS) || defined(__DOXYGEN__)\r
+ /** Constant indicating the maximum number of unique report IDs that can be processed in the report item\r
+ * descriptor for the report size information array in the user HID Report Info structure. A large value\r
+ * allows for more report ID report sizes to be stored, but consumes more memory. By default this is set\r
+ * to 10 items, but this can be overridden by defining \c HID_MAX_REPORT_IDS to another value in the user project\r
+ * makefile, and passing the define to the compiler using the -D compiler switch. Note that IN, OUT and FEATURE\r
+ * items sharing the same report ID consume only one size item in the array.\r
+ */\r
+ #define HID_MAX_REPORT_IDS 10\r
+ #endif\r
+\r
+ /** Returns the value a given HID report item (once its value has been fetched via @ref USB_GetHIDReportItemInfo())\r
+ * left-aligned to the given data type. This allows for signed data to be interpreted correctly, by shifting the data\r
+ * leftwards until the data's sign bit is in the correct position.\r
+ *\r
+ * @param ReportItem HID Report Item whose retrieved value is to be aligned.\r
+ * @param Type Data type to align the HID report item's value to.\r
+ *\r
+ * @return Left-aligned data of the given report item's pre-retrieved value for the given datatype.\r
+ */\r
+ #define HID_ALIGN_DATA(ReportItem, Type) ((Type)(ReportItem->Value << ((8 * sizeof(Type)) - ReportItem->Attributes.BitSize)))\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Enums: */\r
+ /** Enum for the possible error codes in the return value of the @ref USB_ProcessHIDReport() function. */\r
+ enum HID_Parse_ErrorCodes_t\r
+ {\r
+ HID_PARSE_Successful = 0, /**< Successful parse of the HID report descriptor, no error. */\r
+ HID_PARSE_HIDStackOverflow = 1, /**< More than @ref HID_STATETABLE_STACK_DEPTH nested PUSHes in the report. */\r
+ HID_PARSE_HIDStackUnderflow = 2, /**< A POP was found when the state table stack was empty. */\r
+ HID_PARSE_InsufficientReportItems = 3, /**< More than @ref HID_MAX_REPORTITEMS report items in the report. */\r
+ HID_PARSE_UnexpectedEndCollection = 4, /**< An END COLLECTION item found without matching COLLECTION item. */\r
+ HID_PARSE_InsufficientCollectionPaths = 5, /**< More than @ref HID_MAX_COLLECTIONS collections in the report. */\r
+ HID_PARSE_UsageListOverflow = 6, /**< More than @ref HID_USAGE_STACK_DEPTH usages listed in a row. */\r
+ HID_PARSE_InsufficientReportIDItems = 7, /**< More than @ref HID_MAX_REPORT_IDS report IDs in the device. */\r
+ HID_PARSE_NoUnfilteredReportItems = 8, /**< All report items from the device were filtered by the filtering callback routine. */\r
+ };\r
+\r
+ /* Type Defines: */\r
+ /** @brief HID Parser Report Item Min/Max Structure.\r
+ *\r
+ * Type define for an attribute with both minimum and maximum values (e.g. Logical Min/Max).\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t Minimum; /**< Minimum value for the attribute. */\r
+ uint32_t Maximum; /**< Maximum value for the attribute. */\r
+ } HID_MinMax_t;\r
+\r
+ /** @brief HID Parser Report Item Unit Structure.\r
+ *\r
+ * Type define for the Unit attributes of a report item.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t Type; /**< Unit type (refer to HID specifications for details). */\r
+ uint8_t Exponent; /**< Unit exponent (refer to HID specifications for details). */\r
+ } HID_Unit_t;\r
+\r
+ /** @brief HID Parser Report Item Usage Structure.\r
+ *\r
+ * Type define for the Usage attributes of a report item.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t Page; /**< Usage page of the report item. */\r
+ uint16_t Usage; /**< Usage of the report item. */\r
+ } HID_Usage_t;\r
+\r
+ /** @brief HID Parser Report Item Collection Path Structure.\r
+ *\r
+ * Type define for a COLLECTION object. Contains the collection attributes and a reference to the\r
+ * parent collection if any.\r
+ */\r
+ typedef struct HID_CollectionPath\r
+ {\r
+ uint8_t Type; /**< Collection type (e.g. "Generic Desktop"). */\r
+ HID_Usage_t Usage; /**< Collection usage. */\r
+ struct HID_CollectionPath* Parent; /**< Reference to parent collection, or \c NULL if root collection. */\r
+ } HID_CollectionPath_t;\r
+\r
+ /** @brief HID Parser Report Item Attributes Structure.\r
+ *\r
+ * Type define for all the data attributes of a report item, except flags.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t BitSize; /**< Size in bits of the report item's data. */\r
+\r
+ HID_Usage_t Usage; /**< Usage of the report item. */\r
+ HID_Unit_t Unit; /**< Unit type and exponent of the report item. */\r
+ HID_MinMax_t Logical; /**< Logical minimum and maximum of the report item. */\r
+ HID_MinMax_t Physical; /**< Physical minimum and maximum of the report item. */\r
+ } HID_ReportItem_Attributes_t;\r
+\r
+ /** @brief HID Parser Report Item Details Structure.\r
+ *\r
+ * Type define for a report item (IN, OUT or FEATURE) layout attributes and other details.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t BitOffset; /**< Bit offset in the IN, OUT or FEATURE report of the item. */\r
+ uint8_t ItemType; /**< Report item type, a value in @ref HID_ReportItemTypes_t. */\r
+ uint16_t ItemFlags; /**< Item data flags, a mask of HID_IOF_* constants. */\r
+ uint8_t ReportID; /**< Report ID this item belongs to, or 0x00 if device has only one report */\r
+ HID_CollectionPath_t* CollectionPath; /**< Collection path of the item. */\r
+\r
+ HID_ReportItem_Attributes_t Attributes; /**< Report item attributes. */\r
+\r
+ uint32_t Value; /**< Current value of the report item - use @ref HID_ALIGN_DATA() when processing\r
+ * a retrieved value so that it is aligned to a specific type.\r
+ */\r
+ uint32_t PreviousValue; /**< Previous value of the report item. */\r
+ } HID_ReportItem_t;\r
+\r
+ /** @brief HID Parser Report Size Structure.\r
+ *\r
+ * Type define for a report item size information structure, to retain the size of a device's reports by ID.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t ReportID; /**< Report ID of the report within the HID interface. */\r
+ uint16_t ReportSizeBits[3]; /**< Total number of bits in each report type for the given Report ID,\r
+ * indexed by the @ref HID_ReportItemTypes_t enum.\r
+ */\r
+ } HID_ReportSizeInfo_t;\r
+\r
+ /** @brief HID Parser State Structure.\r
+ *\r
+ * Type define for a complete processed HID report, including all report item data and collections.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t TotalReportItems; /**< Total number of report items stored in the \c ReportItems array. */\r
+ HID_ReportItem_t ReportItems[HID_MAX_REPORTITEMS]; /**< Report items array, including all IN, OUT\r
+ * and FEATURE items.\r
+ */\r
+ HID_CollectionPath_t CollectionPaths[HID_MAX_COLLECTIONS]; /**< All collection items, referenced\r
+ * by the report items.\r
+ */\r
+ uint8_t TotalDeviceReports; /**< Number of reports within the HID interface */\r
+ HID_ReportSizeInfo_t ReportIDSizes[HID_MAX_REPORT_IDS]; /**< Report sizes for each report in the interface */\r
+ uint16_t LargestReportSizeBits; /**< Largest report that the attached device will generate, in bits */\r
+ bool UsingReportIDs; /**< Indicates if the device has at least one REPORT ID\r
+ * element in its HID report descriptor.\r
+ */\r
+ } HID_ReportInfo_t;\r
+\r
+ /* Function Prototypes: */\r
+ /** Function to process a given HID report returned from an attached device, and store it into a given\r
+ * @ref HID_ReportInfo_t structure.\r
+ *\r
+ * @param ReportData Buffer containing the device's HID report table.\r
+ * @param ReportSize Size in bytes of the HID report table.\r
+ * \param[out] ParserData Pointer to a @ref HID_ReportInfo_t instance for the parser output.\r
+ *\r
+ * @return A value in the @ref HID_Parse_ErrorCodes_t enum.\r
+ */\r
+ uint8_t USB_ProcessHIDReport(const uint8_t* ReportData,\r
+ uint16_t ReportSize,\r
+ HID_ReportInfo_t* const ParserData) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** Extracts the given report item's value out of the given HID report and places it into the Value\r
+ * member of the report item's @ref HID_ReportItem_t structure.\r
+ *\r
+ * When called on a report with an item that exists in that report, this copies the report item's \c Value\r
+ * to its \c PreviousValue element for easy checking to see if an item's value has changed before processing\r
+ * a report. If the given item does not exist in the report, the function does not modify the report item's\r
+ * data.\r
+ *\r
+ * @param ReportData Buffer containing an IN or FEATURE report from an attached device.\r
+ * \param[in,out] ReportItem Pointer to the report item of interest in a @ref HID_ReportInfo_t ReportItem array.\r
+ *\r
+ * \returns Boolean \c true if the item to retrieve was located in the given report, \c false otherwise.\r
+ */\r
+ bool USB_GetHIDReportItemInfo(const uint8_t* ReportData,\r
+ HID_ReportItem_t* const ReportItem) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** Retrieves the given report item's value out of the \c Value member of the report item's\r
+ * @ref HID_ReportItem_t structure and places it into the correct position in the HID report\r
+ * buffer. The report buffer is assumed to have the appropriate bits cleared before calling\r
+ * this function (i.e., the buffer should be explicitly cleared before report values are added).\r
+ *\r
+ * When called, this copies the report item's \c Value element to its \c PreviousValue element for easy\r
+ * checking to see if an item's value has changed before sending a report.\r
+ *\r
+ * If the device has multiple HID reports, the first byte in the report is set to the report ID of the given item.\r
+ *\r
+ * \param[out] ReportData Buffer holding the current OUT or FEATURE report data.\r
+ * @param ReportItem Pointer to the report item of interest in a @ref HID_ReportInfo_t ReportItem array.\r
+ */\r
+ void USB_SetHIDReportItemInfo(uint8_t* ReportData,\r
+ HID_ReportItem_t* const ReportItem) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** Retrieves the size of a given HID report in bytes from its Report ID.\r
+ *\r
+ * @param ParserData Pointer to a @ref HID_ReportInfo_t instance containing the parser output.\r
+ * @param ReportID Report ID of the report whose size is to be determined.\r
+ * @param ReportType Type of the report whose size is to be determined, a value from the\r
+ * @ref HID_ReportItemTypes_t enum.\r
+ *\r
+ * @return Size of the report in bytes, or \c 0 if the report does not exist.\r
+ */\r
+ uint16_t USB_GetHIDReportSize(HID_ReportInfo_t* const ParserData,\r
+ const uint8_t ReportID,\r
+ const uint8_t ReportType) ATTR_CONST ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** Callback routine for the HID Report Parser. This callback <b>must</b> be implemented by the user code when\r
+ * the parser is used, to determine what report IN, OUT and FEATURE item's information is stored into the user\r
+ * @ref HID_ReportInfo_t structure. This can be used to filter only those items the application will be using, so that\r
+ * no RAM is wasted storing the attributes for report items which will never be referenced by the application.\r
+ *\r
+ * Report item pointers passed to this callback function may be cached by the user application for later use\r
+ * when processing report items. This provides faster report processing in the user application than would\r
+ * a search of the entire parsed report item table for each received or sent report.\r
+ *\r
+ * @param CurrentItem Pointer to the current report item for user checking.\r
+ *\r
+ * @return Boolean \c true if the item should be stored into the @ref HID_ReportInfo_t structure, \c false if\r
+ * it should be ignored.\r
+ */\r
+ bool CALLBACK_HIDParser_FilterHIDReportItem(HID_ReportItem_t* const CurrentItem);\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Type Defines: */\r
+ typedef struct\r
+ {\r
+ HID_ReportItem_Attributes_t Attributes;\r
+ uint8_t ReportCount;\r
+ uint8_t ReportID;\r
+ } HID_StateTable_t;\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Constants for HID report item attributes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_HIDParser\r
+ * @defgroup Group_HIDReportItemConst HID Report Descriptor Item Constants\r
+ *\r
+ * General HID constant definitions for HID Report Descriptor elements.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __HIDREPORTDATA_H__\r
+#define __HIDREPORTDATA_H__\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Macros: */\r
+ #define HID_RI_DATA_SIZE_MASK 0x03\r
+ #define HID_RI_TYPE_MASK 0x0C\r
+ #define HID_RI_TAG_MASK 0xF0\r
+\r
+ #define HID_RI_TYPE_MAIN 0x00\r
+ #define HID_RI_TYPE_GLOBAL 0x04\r
+ #define HID_RI_TYPE_LOCAL 0x08\r
+\r
+ #define HID_RI_DATA_BITS_0 0x00\r
+ #define HID_RI_DATA_BITS_8 0x01\r
+ #define HID_RI_DATA_BITS_16 0x02\r
+ #define HID_RI_DATA_BITS_32 0x03\r
+ #define HID_RI_DATA_BITS(DataBits) HID_RI_DATA_BITS_ ## DataBits\r
+\r
+ #define _HID_RI_ENCODE_0(Data) \r
+ #define _HID_RI_ENCODE_8(Data) , (Data & 0xFF)\r
+ #define _HID_RI_ENCODE_16(Data) _HID_RI_ENCODE_8(Data) _HID_RI_ENCODE_8(Data >> 8)\r
+ #define _HID_RI_ENCODE_32(Data) _HID_RI_ENCODE_16(Data) _HID_RI_ENCODE_16(Data >> 16)\r
+ #define _HID_RI_ENCODE(DataBits, ...) _HID_RI_ENCODE_ ## DataBits(__VA_ARGS__)\r
+ \r
+ #define _HID_RI_ENTRY(Type, Tag, DataBits, ...) \\r
+ (Type | Tag | HID_RI_DATA_BITS(DataBits)) _HID_RI_ENCODE(DataBits, (__VA_ARGS__))\r
+ #endif\r
+ \r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** @name HID Input, Output and Feature Report Descriptor Item Flags */\r
+ //@{\r
+ #define HID_IOF_CONSTANT (1 << 0)\r
+ #define HID_IOF_DATA (0 << 0)\r
+ #define HID_IOF_VARIABLE (1 << 1)\r
+ #define HID_IOF_ARRAY (0 << 1)\r
+ #define HID_IOF_RELATIVE (1 << 2)\r
+ #define HID_IOF_ABSOLUTE (0 << 2)\r
+ #define HID_IOF_WRAP (1 << 3)\r
+ #define HID_IOF_NO_WRAP (0 << 3)\r
+ #define HID_IOF_NON_LINEAR (1 << 4)\r
+ #define HID_IOF_LINEAR (0 << 4)\r
+ #define HID_IOF_NO_PREFERRED_STATE (1 << 5)\r
+ #define HID_IOF_PREFERRED_STATE (0 << 5)\r
+ #define HID_IOF_NULLSTATE (1 << 6)\r
+ #define HID_IOF_NO_NULL_POSITION (0 << 6)\r
+ #define HID_IOF_VOLATILE (1 << 7)\r
+ #define HID_IOF_NON_VOLATILE (0 << 7)\r
+ #define HID_IOF_BUFFERED_BYTES (1 << 8)\r
+ #define HID_IOF_BITFIELD (0 << 8)\r
+ //@}\r
+ \r
+ /** @name HID Report Descriptor Item Macros */\r
+ //@{\r
+ #define HID_RI_INPUT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0x80, DataBits, __VA_ARGS__)\r
+ #define HID_RI_OUTPUT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0x90, DataBits, __VA_ARGS__)\r
+ #define HID_RI_COLLECTION(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0xA0, DataBits, __VA_ARGS__)\r
+ #define HID_RI_FEATURE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0xB0, DataBits, __VA_ARGS__)\r
+ #define HID_RI_END_COLLECTION(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_MAIN , 0xC0, DataBits, __VA_ARGS__)\r
+ #define HID_RI_USAGE_PAGE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x00, DataBits, __VA_ARGS__)\r
+ #define HID_RI_LOGICAL_MINIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x10, DataBits, __VA_ARGS__)\r
+ #define HID_RI_LOGICAL_MAXIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x20, DataBits, __VA_ARGS__)\r
+ #define HID_RI_PHYSICAL_MINIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x30, DataBits, __VA_ARGS__)\r
+ #define HID_RI_PHYSICAL_MAXIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x40, DataBits, __VA_ARGS__)\r
+ #define HID_RI_UNIT_EXPONENT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x50, DataBits, __VA_ARGS__)\r
+ #define HID_RI_UNIT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x60, DataBits, __VA_ARGS__)\r
+ #define HID_RI_REPORT_SIZE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x70, DataBits, __VA_ARGS__)\r
+ #define HID_RI_REPORT_ID(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x80, DataBits, __VA_ARGS__)\r
+ #define HID_RI_REPORT_COUNT(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0x90, DataBits, __VA_ARGS__)\r
+ #define HID_RI_PUSH(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0xA0, DataBits, __VA_ARGS__)\r
+ #define HID_RI_POP(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_GLOBAL, 0xB0, DataBits, __VA_ARGS__)\r
+ #define HID_RI_USAGE(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_LOCAL , 0x00, DataBits, __VA_ARGS__)\r
+ #define HID_RI_USAGE_MINIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_LOCAL , 0x10, DataBits, __VA_ARGS__)\r
+ #define HID_RI_USAGE_MAXIMUM(DataBits, ...) _HID_RI_ENTRY(HID_RI_TYPE_LOCAL , 0x20, DataBits, __VA_ARGS__)\r
+ //@}\r
+\r
+/** @} */\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief Common definitions and declarations for the library USB MIDI Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassMIDI\r
+ * @defgroup Group_USBClassMIDICommon Common Class Definitions\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB\r
+ * MIDI Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _MIDI_CLASS_COMMON_H_\r
+#define _MIDI_CLASS_COMMON_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_AUDIO_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../../Core/StdDescriptors.h"\r
+ #include "AudioClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_MIDI_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Macros: */\r
+ /** @name MIDI Command Values */\r
+ //@{\r
+ /** MIDI command for a note on (activation) event. */\r
+ #define MIDI_COMMAND_NOTE_ON 0x90\r
+\r
+ /** MIDI command for a note off (deactivation) event. */\r
+ #define MIDI_COMMAND_NOTE_OFF 0x80\r
+ //@}\r
+\r
+ /** Standard key press velocity value used for all note events. */\r
+ #define MIDI_STANDARD_VELOCITY 64\r
+\r
+ /** Convenience macro. MIDI channels are numbered from 1-10 (natural numbers) however the logical channel\r
+ * addresses are zero-indexed. This converts a natural MIDI channel number into the logical channel address.\r
+ *\r
+ * @param channel MIDI channel number to address.\r
+ */\r
+ #define MIDI_CHANNEL(channel) ((channel) - 1)\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible MIDI jack types in a MIDI device jack descriptor. */\r
+ enum MIDI_JackTypes_t\r
+ {\r
+ MIDI_JACKTYPE_Embedded = 0x01, /**< MIDI class descriptor jack type value for an embedded (logical) MIDI input or output jack. */\r
+ MIDI_JACKTYPE_External = 0x02, /**< MIDI class descriptor jack type value for an external (physical) MIDI input or output jack. */\r
+ };\r
+\r
+ /* Type Defines: */\r
+ /** @brief MIDI class-specific Streaming Interface Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific MIDI streaming interface descriptor. This indicates to the host\r
+ * how MIDI the specification compliance of the device and the total length of the Audio class-specific descriptors.\r
+ * See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_MIDI_StdDescriptor_AudioInterface_AS_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */\r
+\r
+ uint16_t AudioSpecification; /**< Binary coded decimal value, indicating the supported Audio Class\r
+ * specification version.\r
+ */\r
+ uint16_t TotalLength; /**< Total length of the Audio class-specific descriptors, including this descriptor. */\r
+ } ATTR_PACKED USB_MIDI_Descriptor_AudioInterface_AS_t;\r
+\r
+ /** @brief MIDI class-specific Streaming Interface Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific MIDI streaming interface descriptor. This indicates to the host\r
+ * how MIDI the specification compliance of the device and the total length of the Audio class-specific descriptors.\r
+ * See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_MIDI_Descriptor_AudioInterface_AS_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */\r
+\r
+ uint16_t bcdMSC; /**< Binary coded decimal value, indicating the supported MIDI Class specification version. */\r
+ uint16_t wTotalLength; /**< Total length of the Audio class-specific descriptors, including this descriptor. */\r
+ } ATTR_PACKED USB_MIDI_StdDescriptor_AudioInterface_AS_t;\r
+\r
+ /** @brief MIDI class-specific Input Jack Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific MIDI IN jack. This gives information to the host on a MIDI input, either\r
+ * a physical input jack, or a logical jack (receiving input data internally, or from the host via an endpoint).\r
+ *\r
+ * @see @ref USB_MIDI_StdDescriptor_InputJack_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */\r
+\r
+ uint8_t JackType; /**< Type of jack, one of the \c JACKTYPE_* mask values. */\r
+ uint8_t JackID; /**< ID value of this jack - must be a unique value within the device. */\r
+\r
+ uint8_t JackStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_MIDI_Descriptor_InputJack_t;\r
+\r
+ /** @brief MIDI class-specific Input Jack Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific MIDI IN jack. This gives information to the host on a MIDI input, either\r
+ * a physical input jack, or a logical jack (receiving input data internally, or from the host via an endpoint).\r
+ *\r
+ * @see @ref USB_MIDI_Descriptor_InputJack_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */\r
+\r
+ uint8_t bJackType; /**< Type of jack, one of the \c JACKTYPE_* mask values. */\r
+ uint8_t bJackID; /**< ID value of this jack - must be a unique value within the device. */\r
+\r
+ uint8_t iJack; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_MIDI_StdDescriptor_InputJack_t;\r
+\r
+ /** @brief MIDI class-specific Output Jack Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific MIDI OUT jack. This gives information to the host on a MIDI output, either\r
+ * a physical output jack, or a logical jack (sending output data internally, or to the host via an endpoint).\r
+ *\r
+ * @see @ref USB_MIDI_StdDescriptor_OutputJack_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */\r
+\r
+ uint8_t JackType; /**< Type of jack, one of the \c JACKTYPE_* mask values. */\r
+ uint8_t JackID; /**< ID value of this jack - must be a unique value within the device. */\r
+\r
+ uint8_t NumberOfPins; /**< Number of output channels within the jack, either physical or logical. */\r
+ uint8_t SourceJackID[1]; /**< ID of each output pin's source data jack. */\r
+ uint8_t SourcePinID[1]; /**< Pin number in the input jack of each output pin's source data. */\r
+\r
+ uint8_t JackStrIndex; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_MIDI_Descriptor_OutputJack_t;\r
+\r
+ /** @brief MIDI class-specific Output Jack Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific MIDI OUT jack. This gives information to the host on a MIDI output, either\r
+ * a physical output jack, or a logical jack (sending output data internally, or to the host via an endpoint).\r
+ *\r
+ * @see @ref USB_MIDI_Descriptor_OutputJack_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */\r
+\r
+ uint8_t bJackType; /**< Type of jack, one of the \c JACKTYPE_* mask values. */\r
+ uint8_t bJackID; /**< ID value of this jack - must be a unique value within the device. */\r
+\r
+ uint8_t bNrInputPins; /**< Number of output channels within the jack, either physical or logical. */\r
+ uint8_t baSourceID[1]; /**< ID of each output pin's source data jack. */\r
+ uint8_t baSourcePin[1]; /**< Pin number in the input jack of each output pin's source data. */\r
+\r
+ uint8_t iJack; /**< Index of a string descriptor describing this descriptor within the device. */\r
+ } ATTR_PACKED USB_MIDI_StdDescriptor_OutputJack_t;\r
+\r
+ /** @brief Audio class-specific Jack Endpoint Descriptor (nxpUSBlib naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific extended MIDI jack endpoint descriptor. This contains extra information\r
+ * on the usage of MIDI endpoints used to stream MIDI events in and out of the USB Audio device, and follows an Audio\r
+ * class-specific extended MIDI endpoint descriptor. See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_MIDI_StdDescriptor_Jack_Endpoint_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Regular descriptor header containing the descriptor's type and length. */\r
+ uint8_t Subtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */\r
+\r
+ uint8_t TotalEmbeddedJacks; /**< Total number of jacks inside this endpoint. */\r
+ uint8_t AssociatedJackID[1]; /**< IDs of each jack inside the endpoint. */\r
+ } ATTR_PACKED USB_MIDI_Descriptor_Jack_Endpoint_t;\r
+\r
+ /** @brief Audio class-specific Jack Endpoint Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for an Audio class-specific extended MIDI jack endpoint descriptor. This contains extra information\r
+ * on the usage of MIDI endpoints used to stream MIDI events in and out of the USB Audio device, and follows an Audio\r
+ * class-specific extended MIDI endpoint descriptor. See the USB Audio specification for more details.\r
+ *\r
+ * @see @ref USB_MIDI_Descriptor_Jack_Endpoint_t for the version of this type with non-standard nxpUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+\r
+ uint8_t bDescriptorSubtype; /**< Sub type value used to distinguish between audio class-specific descriptors. */\r
+\r
+ uint8_t bNumEmbMIDIJack; /**< Total number of jacks inside this endpoint. */\r
+ uint8_t bAssocJackID[1]; /**< IDs of each jack inside the endpoint. */\r
+ } ATTR_PACKED USB_MIDI_StdDescriptor_Jack_Endpoint_t;\r
+\r
+ /** @brief MIDI Class Driver Event Packet.\r
+ *\r
+ * Type define for a USB MIDI event packet, used to encapsulate sent and received MIDI messages from a USB MIDI interface.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ unsigned Command : 4; /**< Upper nibble of the MIDI command being sent or received in the event packet. */\r
+ unsigned CableNumber : 4; /**< Virtual cable number of the event being sent or received in the given MIDI interface. */\r
+\r
+ uint8_t Data1; /**< First byte of data in the MIDI event. */\r
+ uint8_t Data2; /**< Second byte of data in the MIDI event. */\r
+ uint8_t Data3; /**< Third byte of data in the MIDI event. */\r
+ } ATTR_PACKED MIDI_EventPacket_t;\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Common definitions and declarations for the library USB Mass Storage Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassMS\r
+ * @defgroup Group_USBClassMSCommon Common Class Definitions\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB\r
+ * Mass Storage Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _MS_CLASS_COMMON_H_\r
+#define _MS_CLASS_COMMON_H_\r
+\r
+ /* Includes: */\r
+ #include "../../Core/StdDescriptors.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_MS_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Macros: */\r
+ /** Magic signature for a Command Block Wrapper used in the Mass Storage Bulk-Only transport protocol. */\r
+ #define MS_CBW_SIGNATURE 0x43425355UL\r
+\r
+ /** Magic signature for a Command Status Wrapper used in the Mass Storage Bulk-Only transport protocol. */\r
+ #define MS_CSW_SIGNATURE 0x53425355UL\r
+\r
+ /** Mask for a Command Block Wrapper's flags attribute to specify a command with data sent from host-to-device. */\r
+ #define MS_COMMAND_DIR_DATA_OUT (0 << 7)\r
+\r
+ /** Mask for a Command Block Wrapper's flags attribute to specify a command with data sent from device-to-host. */\r
+ #define MS_COMMAND_DIR_DATA_IN (1 << 7)\r
+\r
+ /** @name SCSI Commands*/\r
+ //@{\r
+ /** SCSI Command Code for an INQUIRY command. */\r
+ #define SCSI_CMD_INQUIRY 0x12\r
+\r
+ /** SCSI Command Code for a REQUEST SENSE command. */\r
+ #define SCSI_CMD_REQUEST_SENSE 0x03\r
+\r
+ /** SCSI Command Code for a TEST UNIT READY command. */\r
+ #define SCSI_CMD_TEST_UNIT_READY 0x00\r
+\r
+ /** SCSI Command Code for a READ CAPACITY (10) command. */\r
+ #define SCSI_CMD_READ_CAPACITY_10 0x25\r
+\r
+ /** SCSI Command Code for a SEND DIAGNOSTIC command. */\r
+ #define SCSI_CMD_SEND_DIAGNOSTIC 0x1D\r
+\r
+ /** SCSI Command Code for a PREVENT ALLOW MEDIUM REMOVAL command. */\r
+ #define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E\r
+\r
+ /** SCSI Command Code for a WRITE (10) command. */\r
+ #define SCSI_CMD_WRITE_10 0x2A\r
+\r
+ /** SCSI Command Code for a READ (10) command. */\r
+ #define SCSI_CMD_READ_10 0x28\r
+\r
+ /** SCSI Command Code for a WRITE (6) command. */\r
+ #define SCSI_CMD_WRITE_6 0x0A\r
+\r
+ /** SCSI Command Code for a READ (6) command. */\r
+ #define SCSI_CMD_READ_6 0x08\r
+\r
+ /** SCSI Command Code for a VERIFY (10) command. */\r
+ #define SCSI_CMD_VERIFY_10 0x2F\r
+\r
+ /** SCSI Command Code for a MODE SENSE (6) command. */\r
+ #define SCSI_CMD_MODE_SENSE_6 0x1A\r
+\r
+ /** SCSI Command Code for a MODE SENSE (10) command. */\r
+ #define SCSI_CMD_MODE_SENSE_10 0x5A\r
+ //@}\r
+ \r
+ /** @name SCSI Sense Key Values */\r
+ //@{\r
+ /** SCSI Sense Code to indicate no error has occurred. */\r
+ #define SCSI_SENSE_KEY_GOOD 0x00\r
+\r
+ /** SCSI Sense Code to indicate that the device has recovered from an error. */\r
+ #define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01\r
+\r
+ /** SCSI Sense Code to indicate that the device is not ready for a new command. */\r
+ #define SCSI_SENSE_KEY_NOT_READY 0x02\r
+\r
+ /** SCSI Sense Code to indicate an error whilst accessing the medium. */\r
+ #define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03\r
+\r
+ /** SCSI Sense Code to indicate a hardware error has occurred. */\r
+ #define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04\r
+\r
+ /** SCSI Sense Code to indicate that an illegal request has been issued. */\r
+ #define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05\r
+\r
+ /** SCSI Sense Code to indicate that the unit requires attention from the host to indicate\r
+ * a reset event, medium removal or other condition.\r
+ */\r
+ #define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06\r
+\r
+ /** SCSI Sense Code to indicate that a write attempt on a protected block has been made. */\r
+ #define SCSI_SENSE_KEY_DATA_PROTECT 0x07\r
+\r
+ /** SCSI Sense Code to indicate an error while trying to write to a write-once medium. */\r
+ #define SCSI_SENSE_KEY_BLANK_CHECK 0x08\r
+\r
+ /** SCSI Sense Code to indicate a vendor specific error has occurred. */\r
+ #define SCSI_SENSE_KEY_VENDOR_SPECIFIC 0x09\r
+\r
+ /** SCSI Sense Code to indicate that an EXTENDED COPY command has aborted due to an error. */\r
+ #define SCSI_SENSE_KEY_COPY_ABORTED 0x0A\r
+\r
+ /** SCSI Sense Code to indicate that the device has aborted the issued command. */\r
+ #define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B\r
+\r
+ /** SCSI Sense Code to indicate an attempt to write past the end of a partition has been made. */\r
+ #define SCSI_SENSE_KEY_VOLUME_OVERFLOW 0x0D\r
+\r
+ /** SCSI Sense Code to indicate that the source data did not match the data read from the medium. */\r
+ #define SCSI_SENSE_KEY_MISCOMPARE 0x0E\r
+ //@}\r
+ \r
+ /** @name SCSI Additional Sense Codes */\r
+ //@{\r
+ /** SCSI Additional Sense Code to indicate no additional sense information is available. */\r
+ #define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION 0x00\r
+\r
+ /** SCSI Additional Sense Code to indicate that the logical unit (LUN) addressed is not ready. */\r
+ #define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY 0x04\r
+\r
+ /** SCSI Additional Sense Code to indicate an invalid field was encountered while processing the issued command. */\r
+ #define SCSI_ASENSE_INVALID_FIELD_IN_CDB 0x24\r
+\r
+ /** SCSI Additional Sense Code to indicate that a medium that was previously indicated as not ready has now\r
+ * become ready for use.\r
+ */\r
+ #define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE 0x28\r
+\r
+ /** SCSI Additional Sense Code to indicate that an attempt to write to a protected area was made. */\r
+ #define SCSI_ASENSE_WRITE_PROTECTED 0x27\r
+\r
+ /** SCSI Additional Sense Code to indicate an error whilst formatting the device medium. */\r
+ #define SCSI_ASENSE_FORMAT_ERROR 0x31\r
+\r
+ /** SCSI Additional Sense Code to indicate an invalid command was issued. */\r
+ #define SCSI_ASENSE_INVALID_COMMAND 0x20\r
+\r
+ /** SCSI Additional Sense Code to indicate a write to a block out outside of the medium's range was issued. */\r
+ #define SCSI_ASENSE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21\r
+\r
+ /** SCSI Additional Sense Code to indicate that no removable medium is inserted into the device. */\r
+ #define SCSI_ASENSE_MEDIUM_NOT_PRESENT 0x3A\r
+ //@}\r
+ \r
+ /** @name SCSI Additional Sense Key Code Qualifiers */\r
+ //@{\r
+ /** SCSI Additional Sense Qualifier Code to indicate no additional sense qualifier information is available. */\r
+ #define SCSI_ASENSEQ_NO_QUALIFIER 0x00\r
+\r
+ /** SCSI Additional Sense Qualifier Code to indicate that a medium format command failed to complete. */\r
+ #define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED 0x01\r
+\r
+ /** SCSI Additional Sense Qualifier Code to indicate that an initializing command must be issued before the issued\r
+ * command can be executed.\r
+ */\r
+ #define SCSI_ASENSEQ_INITIALIZING_COMMAND_REQUIRED 0x02\r
+\r
+ /** SCSI Additional Sense Qualifier Code to indicate that an operation is currently in progress. */\r
+ #define SCSI_ASENSEQ_OPERATION_IN_PROGRESS 0x07\r
+ //@}\r
+ \r
+ /* Enums: */\r
+ /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the Mass\r
+ * Storage device class.\r
+ */\r
+ enum MS_Descriptor_ClassSubclassProtocol_t\r
+ {\r
+ MS_CSCP_MassStorageClass = 0x08, /**< Descriptor Class value indicating that the device or interface\r
+ * belongs to the Mass Storage class.\r
+ */\r
+ MS_CSCP_SCSITransparentSubclass = 0x06, /**< Descriptor Subclass value indicating that the device or interface\r
+ * belongs to the SCSI Transparent Command Set subclass of the Mass\r
+ * storage class.\r
+ */\r
+ MS_CSCP_BulkOnlyTransportProtocol = 0x50, /**< Descriptor Protocol value indicating that the device or interface\r
+ * belongs to the Bulk Only Transport protocol of the Mass Storage class.\r
+ */\r
+ };\r
+ \r
+ /** Enum for the Mass Storage class specific control requests that can be issued by the USB bus host. */\r
+ enum MS_ClassRequests_t\r
+ {\r
+ MS_REQ_GetMaxLUN = 0xFE, /**< Mass Storage class-specific request to retrieve the total number of Logical\r
+ * Units (drives) in the SCSI device.\r
+ */\r
+ MS_REQ_MassStorageReset = 0xFF, /**< Mass Storage class-specific request to reset the Mass Storage interface,\r
+ * ready for the next command.\r
+ */\r
+ };\r
+\r
+ /** Enum for the possible command status wrapper return status codes. */\r
+ enum MS_CommandStatusCodes_t\r
+ {\r
+ MS_SCSI_COMMAND_Pass = 0, /**< Command completed with no error */\r
+ MS_SCSI_COMMAND_Fail = 1, /**< Command failed to complete - host may check the exact error via a\r
+ * SCSI REQUEST SENSE command.\r
+ */\r
+ MS_SCSI_COMMAND_PhaseError = 2, /**< Command failed due to being invalid in the current phase. */\r
+ };\r
+\r
+ /* Type Defines: */\r
+ /** @brief Mass Storage Class Command Block Wrapper.\r
+ *\r
+ * Type define for a Command Block Wrapper, used in the Mass Storage Bulk-Only Transport protocol.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t Signature; /**< Command block signature, must be @ref MS_CBW_SIGNATURE to indicate a valid Command Block. */\r
+ uint32_t Tag; /**< Unique command ID value, to associate a command block wrapper with its command status wrapper. */\r
+ uint32_t DataTransferLength; /**< Length of the optional data portion of the issued command, in bytes. */\r
+ uint8_t Flags; /**< Command block flags, indicating command data direction. */\r
+ uint8_t LUN; /**< Logical Unit number this command is issued to. */\r
+ uint8_t SCSICommandLength; /**< Length of the issued SCSI command within the SCSI command data array. */\r
+ uint8_t SCSICommandData[16]; /**< Issued SCSI command in the Command Block. */\r
+ } ATTR_PACKED MS_CommandBlockWrapper_t;\r
+\r
+ /** @brief Mass Storage Class Command Status Wrapper.\r
+ *\r
+ * Type define for a Command Status Wrapper, used in the Mass Storage Bulk-Only Transport protocol.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t Signature; /**< Status block signature, must be @ref MS_CSW_SIGNATURE to indicate a valid Command Status. */\r
+ uint32_t Tag; /**< Unique command ID value, to associate a command block wrapper with its command status wrapper. */\r
+ uint32_t DataTransferResidue; /**< Number of bytes of data not processed in the SCSI command. */\r
+ uint8_t Status; /**< Status code of the issued command - a value from the @ref MS_CommandStatusCodes_t enum. */\r
+ } ATTR_PACKED MS_CommandStatusWrapper_t;\r
+\r
+ /** @brief Mass Storage Class SCSI Sense Structure\r
+ *\r
+ * Type define for a SCSI Sense structure. Structures of this type are filled out by the\r
+ * device via the @ref MS_Host_RequestSense() function, indicating the current sense data of the\r
+ * device (giving explicit error codes for the last issued command). For details of the\r
+ * structure contents, refer to the SCSI specifications.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t ResponseCode;\r
+\r
+ uint8_t SegmentNumber;\r
+\r
+ unsigned SenseKey : 4;\r
+ unsigned Reserved : 1;\r
+ unsigned ILI : 1;\r
+ unsigned EOM : 1;\r
+ unsigned FileMark : 1;\r
+\r
+ uint8_t Information[4];\r
+ uint8_t AdditionalLength;\r
+ uint8_t CmdSpecificInformation[4];\r
+ uint8_t AdditionalSenseCode;\r
+ uint8_t AdditionalSenseQualifier;\r
+ uint8_t FieldReplaceableUnitCode;\r
+ uint8_t SenseKeySpecific[3];\r
+ } ATTR_PACKED SCSI_Request_Sense_Response_t;\r
+\r
+ /** @brief Mass Storage Class SCSI Inquiry Structure.\r
+ *\r
+ * Type define for a SCSI Inquiry structure. Structures of this type are filled out by the\r
+ * device via the @ref MS_Host_GetInquiryData() function, retrieving the attached device's\r
+ * information.\r
+ *\r
+ * For details of the structure contents, refer to the SCSI specifications.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ unsigned DeviceType : 5;\r
+ unsigned PeripheralQualifier : 3;\r
+\r
+ unsigned Reserved : 7;\r
+ unsigned Removable : 1;\r
+\r
+ uint8_t Version;\r
+\r
+ unsigned ResponseDataFormat : 4;\r
+ unsigned Reserved2 : 1;\r
+ unsigned NormACA : 1;\r
+ unsigned TrmTsk : 1;\r
+ unsigned AERC : 1;\r
+\r
+ uint8_t AdditionalLength;\r
+ uint8_t Reserved3[2];\r
+\r
+ unsigned SoftReset : 1;\r
+ unsigned CmdQue : 1;\r
+ unsigned Reserved4 : 1;\r
+ unsigned Linked : 1;\r
+ unsigned Sync : 1;\r
+ unsigned WideBus16Bit : 1;\r
+ unsigned WideBus32Bit : 1;\r
+ unsigned RelAddr : 1;\r
+\r
+ uint8_t VendorID[8];\r
+ uint8_t ProductID[16];\r
+ uint8_t RevisionID[4];\r
+ } ATTR_PACKED SCSI_Inquiry_Response_t;\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Common definitions and declarations for the library USB Printer Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassPrinter\r
+ * @defgroup Group_USBClassPrinterCommon Common Class Definitions\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB\r
+ * Printer Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _PRINTER_CLASS_COMMON_H_\r
+#define _PRINTER_CLASS_COMMON_H_\r
+\r
+ /* Includes: */\r
+ #include "../../Core/StdDescriptors.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_PRINTER_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Macros: */\r
+ /** @name Virtual Printer Status Line Masks */\r
+ //@{\r
+ /** Port status mask for a printer device, indicating that an error has *not* occurred. */\r
+ #define PRNT_PORTSTATUS_NOTERROR (1 << 3)\r
+\r
+ /** Port status mask for a printer device, indicating that the device is currently selected. */\r
+ #define PRNT_PORTSTATUS_SELECT (1 << 4)\r
+\r
+ /** Port status mask for a printer device, indicating that the device is currently out of paper. */\r
+ #define PRNT_PORTSTATUS_PAPEREMPTY (1 << 5)\r
+ //@}\r
+\r
+ /* Enums: */\r
+ /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the Printer\r
+ * device class.\r
+ */\r
+ enum PRNT_Descriptor_ClassSubclassProtocol_t\r
+ {\r
+ PRNT_CSCP_PrinterClass = 0x07, /**< Descriptor Class value indicating that the device or interface\r
+ * belongs to the Printer class.\r
+ */\r
+ PRNT_CSCP_PrinterSubclass = 0x01, /**< Descriptor Subclass value indicating that the device or interface\r
+ * belongs to the Printer subclass.\r
+ */\r
+ PRNT_CSCP_BidirectionalProtocol = 0x02, /**< Descriptor Protocol value indicating that the device or interface\r
+ * belongs to the Bidirectional protocol of the Printer class.\r
+ */\r
+ };\r
+ \r
+ /** Enum for the Printer class specific control requests that can be issued by the USB bus host. */\r
+ enum PRNT_ClassRequests_t\r
+ {\r
+ PRNT_REQ_GetDeviceID = 0x00, /**< Printer class-specific request to retrieve the Unicode ID\r
+ * string of the device, containing the device's name, manufacturer\r
+ * and supported printer languages.\r
+ */\r
+ PRNT_REQ_GetPortStatus = 0x01, /**< Printer class-specific request to get the current status of the\r
+ * virtual printer port, for device selection and ready states.\r
+ */\r
+ PRNT_REQ_SoftReset = 0x02, /**< Printer class-specific request to reset the device, ready for new\r
+ * printer commands.\r
+ */\r
+ }; \r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Common definitions and declarations for the library USB RNDIS Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassRNDIS\r
+ * @defgroup Group_USBClassRNDISCommon Common Class Definitions\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB\r
+ * RNDIS Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _RNDIS_CLASS_COMMON_H_\r
+#define _RNDIS_CLASS_COMMON_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_CDC_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../../Core/StdDescriptors.h"\r
+ #include "CDCClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_RNDIS_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Macros: */\r
+ /** Additional error code for RNDIS functions when a device returns a logical command failure. */\r
+ #define RNDIS_ERROR_LOGICAL_CMD_FAILED 0x80\r
+\r
+ /** Implemented RNDIS Version Major. */\r
+ #define REMOTE_NDIS_VERSION_MAJOR 0x01\r
+\r
+ /** Implemented RNDIS Version Minor. */\r
+ #define REMOTE_NDIS_VERSION_MINOR 0x00\r
+\r
+ /** @name RNDIS Message Values */\r
+ //@{\r
+ #define REMOTE_NDIS_PACKET_MSG 0x00000001UL\r
+ #define REMOTE_NDIS_INITIALIZE_MSG 0x00000002UL\r
+ #define REMOTE_NDIS_HALT_MSG 0x00000003UL\r
+ #define REMOTE_NDIS_QUERY_MSG 0x00000004UL\r
+ #define REMOTE_NDIS_SET_MSG 0x00000005UL\r
+ #define REMOTE_NDIS_RESET_MSG 0x00000006UL\r
+ #define REMOTE_NDIS_INDICATE_STATUS_MSG 0x00000007UL\r
+ #define REMOTE_NDIS_KEEPALIVE_MSG 0x00000008UL\r
+ //@}\r
+\r
+ /** @name RNDIS Response Values */\r
+ //@{\r
+ #define REMOTE_NDIS_INITIALIZE_CMPLT 0x80000002UL\r
+ #define REMOTE_NDIS_QUERY_CMPLT 0x80000004UL\r
+ #define REMOTE_NDIS_SET_CMPLT 0x80000005UL\r
+ #define REMOTE_NDIS_RESET_CMPLT 0x80000006UL\r
+ #define REMOTE_NDIS_KEEPALIVE_CMPLT 0x80000008UL\r
+ //@}\r
+\r
+ /** @name RNDIS Status Values */\r
+ //@{\r
+ #define REMOTE_NDIS_STATUS_SUCCESS 0x00000000UL\r
+ #define REMOTE_NDIS_STATUS_FAILURE 0xC0000001UL\r
+ #define REMOTE_NDIS_STATUS_INVALID_DATA 0xC0010015UL\r
+ #define REMOTE_NDIS_STATUS_NOT_SUPPORTED 0xC00000BBUL\r
+ #define REMOTE_NDIS_STATUS_MEDIA_CONNECT 0x4001000BUL\r
+ #define REMOTE_NDIS_STATUS_MEDIA_DISCONNECT 0x4001000CUL\r
+ //@}\r
+\r
+ /** @name RNDIS Media States */\r
+ //@{\r
+ #define REMOTE_NDIS_MEDIA_STATE_CONNECTED 0x00000000UL\r
+ #define REMOTE_NDIS_MEDIA_STATE_DISCONNECTED 0x00000001UL\r
+ //@}\r
+ \r
+ #define REMOTE_NDIS_MEDIUM_802_3 0x00000000UL\r
+\r
+ /** @name RNDIS Connection Types */\r
+ //@{\r
+ #define REMOTE_NDIS_DF_CONNECTIONLESS 0x00000001UL\r
+ #define REMOTE_NDIS_DF_CONNECTION_ORIENTED 0x00000002UL\r
+ //@}\r
+ \r
+ /** @name RNDIS Packet Types */\r
+ //@{\r
+ #define REMOTE_NDIS_PACKET_DIRECTED 0x00000001UL\r
+ #define REMOTE_NDIS_PACKET_MULTICAST 0x00000002UL\r
+ #define REMOTE_NDIS_PACKET_ALL_MULTICAST 0x00000004UL\r
+ #define REMOTE_NDIS_PACKET_BROADCAST 0x00000008UL\r
+ #define REMOTE_NDIS_PACKET_SOURCE_ROUTING 0x00000010UL\r
+ #define REMOTE_NDIS_PACKET_PROMISCUOUS 0x00000020UL\r
+ #define REMOTE_NDIS_PACKET_SMT 0x00000040UL\r
+ #define REMOTE_NDIS_PACKET_ALL_LOCAL 0x00000080UL\r
+ #define REMOTE_NDIS_PACKET_GROUP 0x00001000UL\r
+ #define REMOTE_NDIS_PACKET_ALL_FUNCTIONAL 0x00002000UL\r
+ #define REMOTE_NDIS_PACKET_FUNCTIONAL 0x00004000UL\r
+ #define REMOTE_NDIS_PACKET_MAC_FRAME 0x00008000UL\r
+ //@}\r
+ \r
+ /** @name RNDIS OID Values */\r
+ //@{\r
+ #define OID_GEN_SUPPORTED_LIST 0x00010101UL\r
+ #define OID_GEN_HARDWARE_STATUS 0x00010102UL\r
+ #define OID_GEN_MEDIA_SUPPORTED 0x00010103UL\r
+ #define OID_GEN_MEDIA_IN_USE 0x00010104UL\r
+ #define OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106UL\r
+ #define OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111UL\r
+ #define OID_GEN_LINK_SPEED 0x00010107UL\r
+ #define OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010AUL\r
+ #define OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010BUL\r
+ #define OID_GEN_VENDOR_ID 0x0001010CUL\r
+ #define OID_GEN_VENDOR_DESCRIPTION 0x0001010DUL\r
+ #define OID_GEN_CURRENT_PACKET_FILTER 0x0001010EUL\r
+ #define OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111UL\r
+ #define OID_GEN_MEDIA_CONNECT_STATUS 0x00010114UL\r
+ #define OID_GEN_PHYSICAL_MEDIUM 0x00010202UL\r
+ #define OID_GEN_XMIT_OK 0x00020101UL\r
+ #define OID_GEN_RCV_OK 0x00020102UL\r
+ #define OID_GEN_XMIT_ERROR 0x00020103UL\r
+ #define OID_GEN_RCV_ERROR 0x00020104UL\r
+ #define OID_GEN_RCV_NO_BUFFER 0x00020105UL\r
+ #define OID_802_3_PERMANENT_ADDRESS 0x01010101UL\r
+ #define OID_802_3_CURRENT_ADDRESS 0x01010102UL\r
+ #define OID_802_3_MULTICAST_LIST 0x01010103UL\r
+ #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104UL\r
+ #define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101UL\r
+ #define OID_802_3_XMIT_ONE_COLLISION 0x01020102UL\r
+ #define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103UL\r
+ //@}\r
+\r
+ /** Maximum size in bytes of a RNDIS control message which can be sent or received. */\r
+ #define RNDIS_MESSAGE_BUFFER_SIZE 128\r
+\r
+ /** Maximum size in bytes of an Ethernet frame according to the Ethernet standard. */\r
+ #define ETHERNET_FRAME_SIZE_MAX 1500\r
+\r
+ /* Enums: */\r
+ /** Enum for the RNDIS class specific control requests that can be issued by the USB bus host. */\r
+ enum RNDIS_ClassRequests_t\r
+ {\r
+ RNDIS_REQ_SendEncapsulatedCommand = 0x00, /**< RNDIS request to issue a host-to-device NDIS command. */\r
+ RNDIS_REQ_GetEncapsulatedResponse = 0x01, /**< RNDIS request to issue a device-to-host NDIS response. */\r
+ };\r
+\r
+ /** Enum for the possible NDIS adapter states. */\r
+ enum RNDIS_States_t\r
+ {\r
+ RNDIS_Uninitialized = 0, /**< Adapter currently uninitialized. */\r
+ RNDIS_Initialized = 1, /**< Adapter currently initialized but not ready for data transfers. */\r
+ RNDIS_Data_Initialized = 2, /**< Adapter currently initialized and ready for data transfers. */\r
+ };\r
+\r
+ /** Enum for the RNDIS class specific notification requests that can be issued by a RNDIS device to a host. */\r
+ enum RNDIS_ClassNotifications_t\r
+ {\r
+ RNDIS_NOTIF_ResponseAvailable = 0x01, /**< Notification request value for a RNDIS Response Available notification. */\r
+ };\r
+\r
+ /** Enum for the NDIS hardware states. */\r
+ enum NDIS_Hardware_Status_t\r
+ {\r
+ NDIS_HardwareStatus_Ready, /**< Hardware Ready to accept commands from the host. */\r
+ NDIS_HardwareStatus_Initializing, /**< Hardware busy initializing. */\r
+ NDIS_HardwareStatus_Reset, /**< Hardware reset. */\r
+ NDIS_HardwareStatus_Closing, /**< Hardware currently closing. */\r
+ NDIS_HardwareStatus_NotReady /**< Hardware not ready to accept commands from the host. */\r
+ };\r
+\r
+ /* Type Defines: */\r
+ /** @brief MAC Address Structure.\r
+ *\r
+ * Type define for a physical MAC address of a device on a network.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t Octets[6]; /**< Individual bytes of a MAC address */\r
+ } ATTR_PACKED MAC_Address_t;\r
+\r
+ /** @brief RNDIS Common Message Header Structure.\r
+ *\r
+ * Type define for a RNDIS message header, sent before RNDIS messages.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType; /**< RNDIS message type, a \c REMOTE_NDIS_*_MSG constant */\r
+ uint32_t MessageLength; /**< Total length of the RNDIS message, in bytes */\r
+ } ATTR_PACKED RNDIS_Message_Header_t;\r
+\r
+ /** @brief RNDIS Message Structure.\r
+ *\r
+ * Type define for a RNDIS packet message, used to encapsulate Ethernet packets sent to and from the adapter.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t DataOffset;\r
+ uint32_t DataLength;\r
+ uint32_t OOBDataOffset;\r
+ uint32_t OOBDataLength;\r
+ uint32_t NumOOBDataElements;\r
+ uint32_t PerPacketInfoOffset;\r
+ uint32_t PerPacketInfoLength;\r
+ uint32_t VcHandle;\r
+ uint32_t Reserved;\r
+ } ATTR_PACKED RNDIS_Packet_Message_t;\r
+\r
+ /** @brief RNDIS Initialization Message Structure.\r
+ *\r
+ * Type define for a RNDIS Initialize command message.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t RequestId;\r
+\r
+ uint32_t MajorVersion;\r
+ uint32_t MinorVersion;\r
+ uint32_t MaxTransferSize;\r
+ } ATTR_PACKED RNDIS_Initialize_Message_t;\r
+\r
+ /** @brief RNDIS Initialize Complete Message Structure.\r
+ *\r
+ * Type define for a RNDIS Initialize Complete response message.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t RequestId;\r
+ uint32_t Status;\r
+\r
+ uint32_t MajorVersion;\r
+ uint32_t MinorVersion;\r
+ uint32_t DeviceFlags;\r
+ uint32_t Medium;\r
+ uint32_t MaxPacketsPerTransfer;\r
+ uint32_t MaxTransferSize;\r
+ uint32_t PacketAlignmentFactor;\r
+ uint32_t AFListOffset;\r
+ uint32_t AFListSize;\r
+ } ATTR_PACKED RNDIS_Initialize_Complete_t;\r
+\r
+ /** @brief RNDIS Keep Alive Message Structure.\r
+ *\r
+ * Type define for a RNDIS Keep Alive command message.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t RequestId;\r
+ } ATTR_PACKED RNDIS_KeepAlive_Message_t;\r
+\r
+ /** @brief RNDIS Keep Alive Complete Message Structure.\r
+ *\r
+ * Type define for a RNDIS Keep Alive Complete response message.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t RequestId;\r
+ uint32_t Status;\r
+ } ATTR_PACKED RNDIS_KeepAlive_Complete_t;\r
+\r
+ /** @brief RNDIS Reset Complete Message Structure.\r
+ *\r
+ * Type define for a RNDIS Reset Complete response message.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t Status;\r
+\r
+ uint32_t AddressingReset;\r
+ } ATTR_PACKED RNDIS_Reset_Complete_t;\r
+\r
+ /** @brief RNDIS OID Property Set Message Structure.\r
+ *\r
+ * Type define for a RNDIS OID Property Set command message.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t RequestId;\r
+\r
+ uint32_t Oid;\r
+ uint32_t InformationBufferLength;\r
+ uint32_t InformationBufferOffset;\r
+ uint32_t DeviceVcHandle;\r
+ } ATTR_PACKED RNDIS_Set_Message_t;\r
+\r
+ /** @brief RNDIS OID Property Set Complete Message Structure.\r
+ *\r
+ * Type define for a RNDIS OID Property Set Complete response message.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t RequestId;\r
+ uint32_t Status;\r
+ } ATTR_PACKED RNDIS_Set_Complete_t;\r
+\r
+ /** @brief RNDIS OID Property Query Message Structure.\r
+ *\r
+ * Type define for a RNDIS OID Property Query command message.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t RequestId;\r
+\r
+ uint32_t Oid;\r
+ uint32_t InformationBufferLength;\r
+ uint32_t InformationBufferOffset;\r
+ uint32_t DeviceVcHandle;\r
+ } ATTR_PACKED RNDIS_Query_Message_t;\r
+\r
+ /** @brief RNDIS OID Property Query Complete Message Structure.\r
+ *\r
+ * Type define for a RNDIS OID Property Query Complete response message.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint32_t MessageType;\r
+ uint32_t MessageLength;\r
+ uint32_t RequestId;\r
+ uint32_t Status;\r
+\r
+ uint32_t InformationBufferLength;\r
+ uint32_t InformationBufferOffset;\r
+ } ATTR_PACKED RNDIS_Query_Complete_t;\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Common definitions and declarations for the library USB Still Image Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassSI\r
+ * @defgroup Group_USBClassSICommon Common Class Definitions\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Constants, Types and Enum definitions that are common to both Device and Host modes for the USB\r
+ * Still Image Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _SI_CLASS_COMMON_H_\r
+#define _SI_CLASS_COMMON_H_\r
+\r
+ /* Includes: */\r
+ #include "../../Core/StdDescriptors.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_SI_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Macros: */\r
+ /** Length in bytes of a given Unicode string's character length.\r
+ *\r
+ * @param Chars Total number of Unicode characters in the string.\r
+ *\r
+ * @return Number of bytes of the given unicode string.\r
+ */\r
+ #define UNICODE_STRING_LENGTH(Chars) ((Chars) << 1)\r
+\r
+ /** Used in the DataLength field of a PIMA container, to give the total container size in bytes for\r
+ * a command container.\r
+ *\r
+ * @param Params Number of parameters which are to be sent in the \c Param field of the container.\r
+ */\r
+ #define PIMA_COMMAND_SIZE(Params) ((sizeof(PIMA_Container_t) - 12) + ((Params) * sizeof(uint32_t)))\r
+\r
+ /** Used in the DataLength field of a PIMA container, to give the total container size in bytes for\r
+ * a data container.\r
+ *\r
+ * @param DataLen Length in bytes of the data in the container.\r
+ */\r
+ #define PIMA_DATA_SIZE(DataLen) ((sizeof(PIMA_Container_t) - 12) + (DataLen))\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible PIMA contains types. */\r
+ enum PIMA_Container_Types_t\r
+ {\r
+ PIMA_CONTAINER_Undefined = 0, /**< Undefined container type. */\r
+ PIMA_CONTAINER_CommandBlock = 1, /**< Command Block container type. */\r
+ PIMA_CONTAINER_DataBlock = 2, /**< Data Block container type. */\r
+ PIMA_CONTAINER_ResponseBlock = 3, /**< Response container type. */\r
+ PIMA_CONTAINER_EventBlock = 4, /**< Event Block container type. */\r
+ };\r
+\r
+ /* Enums: */\r
+ /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors relating to the\r
+ * Still Image device class.\r
+ */\r
+ enum SI_Descriptor_ClassSubclassProtocol_t\r
+ {\r
+ SI_CSCP_StillImageClass = 0x06, /**< Descriptor Class value indicating that the device or interface\r
+ * belongs to the Still Image class.\r
+ */\r
+ SI_CSCP_StillImageSubclass = 0x01, /**< Descriptor Subclass value indicating that the device or interface\r
+ * belongs to the Still Image subclass.\r
+ */\r
+ SI_CSCP_BulkOnlyProtocol = 0x01, /**< Descriptor Protocol value indicating that the device or interface\r
+ * belongs to the Bulk Only Transport protocol of the Still Image class.\r
+ */\r
+ };\r
+\r
+ /** Enums for the possible status codes of a returned Response Block from an attached PIMA compliant Still Image device. */\r
+ enum PIMA_ResponseCodes_t\r
+ {\r
+ PIMA_RESPONSE_OK = 1, /**< Response code indicating no error in the issued command. */\r
+ PIMA_RESPONSE_GeneralError = 2, /**< Response code indicating a general error while processing the\r
+ * issued command.\r
+ */\r
+ PIMA_RESPONSE_SessionNotOpen = 3, /**< Response code indicating that the sent command requires an open\r
+ * session before being issued.\r
+ */\r
+ PIMA_RESPONSE_InvalidTransaction = 4, /**< Response code indicating an invalid transaction occurred. */\r
+ PIMA_RESPONSE_OperationNotSupported = 5, /**< Response code indicating that the issued command is not supported\r
+ * by the attached device.\r
+ */\r
+ PIMA_RESPONSE_ParameterNotSupported = 6, /**< Response code indicating that one or more of the issued command's\r
+ * parameters are not supported by the device.\r
+ */\r
+ };\r
+\r
+ /* Type Defines: */\r
+ /** @brief PIMA Still Image Device Command/Response Container.\r
+ *\r
+ * Type define for a PIMA container, use to send commands and receive responses to and from an\r
+ * attached Still Image device.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t DataLength; /**< Length of the container and data, in bytes. */\r
+ uint16_t Type; /**< Container type, a value from the @ref PIMA_Container_Types_t enum. */\r
+ uint16_t Code; /**< Command, event or response code of the container. */\r
+ uint32_t TransactionID; /**< Unique container ID to link blocks together. */\r
+ uint32_t Params[3]; /**< Block parameters to be issued along with the block code (command blocks only). */\r
+ } ATTR_PACKED PIMA_Container_t;\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Device mode driver for the library USB Audio 1.0 Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassAudio\r
+ * @defgroup Group_USBClassAudioDevice Audio 1.0 Class Device Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - nxpUSBlib/Drivers/USB/Class/Device/Audio.c <i>(Makefile source module name: NXPUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Device Mode USB Class driver framework interface, for the Audio 1.0 USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _AUDIO_CLASS_DEVICE_H_\r
+#define _AUDIO_CLASS_DEVICE_H_\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/AudioClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_AUDIO_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Type Defines: */\r
+ /** @brief Audio Class Device Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made for each Audio interface\r
+ * within the user application, and passed to each of the Audio class driver functions as the\r
+ * \c AudioInterfaceInfo parameter. This stores each Audio interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ const struct\r
+ {\r
+ uint8_t ControlInterfaceNumber; /**< Index of the Audio Control interface within the device this\r
+ * structure controls.\r
+ */\r
+ uint8_t StreamingInterfaceNumber; /**< Index of the Audio Streaming interface within the device this\r
+ * structure controls.\r
+ */\r
+\r
+ uint8_t DataINEndpointNumber; /**< Endpoint number of the incoming Audio Streaming data, if available\r
+ * (zero if unused).\r
+ */\r
+ uint16_t DataINEndpointSize; /**< Size in bytes of the incoming Audio Streaming data endpoint, if available\r
+ * (zero if unused).\r
+ */\r
+\r
+ uint8_t DataOUTEndpointNumber; /**< Endpoint number of the outgoing Audio Streaming data, if available\r
+ * (zero if unused).\r
+ */\r
+ uint16_t DataOUTEndpointSize; /**< Size in bytes of the outgoing Audio Streaming data endpoint, if available\r
+ * (zero if unused).\r
+ */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.*/\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ bool InterfaceEnabled; /**< Set and cleared by the class driver to indicate if the host has enabled the streaming endpoints\r
+ * of the Audio Streaming interface.\r
+ */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * are reset to their defaults when the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_Audio_Device_t;\r
+\r
+ /* Function Prototypes: */\r
+\r
+ /**\r
+ * @brief Configures the endpoints of a given Audio interface, ready for use. This should be linked to the library\r
+ * @ref EVENT_USB_Device_ConfigurationChanged() event so that the endpoints are configured when the configuration containing the\r
+ * given Audio interface is selected.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @return Boolean \c true if the endpoints were successfully configured, \c false otherwise.\r
+ */\r
+ bool Audio_Device_ConfigureEndpoints(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Processes incoming control requests from the host, that are directed to the given Audio class interface. This should be\r
+ * linked to the library @ref EVENT_USB_Device_ControlRequest() event.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void Audio_Device_ProcessControlRequest(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+ \r
+ /**\r
+ * @brief Audio class driver callback for the setting and retrieval of streaming endpoint properties. This callback must be implemented\r
+ * in the user application to handle property manipulations on streaming audio endpoints.\r
+ *\r
+ * When the DataLength parameter is NULL, this callback should only indicate whether the specified operation is valid for\r
+ * the given endpoint index, and should return as fast as possible. When non-NULL, this value may be altered for GET operations\r
+ * to indicate the size of the retreived data.\r
+ *\r
+ * @note The length of the retrieved data stored into the Data buffer on GET operations should not exceed the initial value\r
+ * of the \c DataLength parameter.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @param EndpointProperty : Property of the endpoint to get or set, a value from @ref Audio_ClassRequests_t.\r
+ * @param EndpointAddress : Address of the streaming endpoint whose property is being referenced.\r
+ * @param EndpointControl : Parameter of the endpoint to get or set, a value from @ref Audio_EndpointControls_t.\r
+ * @param DataLength : For SET operations, the length of the parameter data to set. For GET operations, the maximum\r
+ * length of the retrieved data. When NULL, the function should return whether the given property\r
+ * and parameter is valid for the requested endpoint without reading or modifying the Data buffer.\r
+ * @param Data : Pointer to a location where the parameter data is stored for SET operations, or where\r
+ * the retrieved data is to be stored for GET operations.\r
+ * @return Boolean true if the property get/set was successful, false otherwise.\r
+ */\r
+ bool CALLBACK_Audio_Device_GetSetEndpointProperty(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo,\r
+ const uint8_t EndpointProperty,\r
+ const uint8_t EndpointAddress,\r
+ const uint8_t EndpointControl,\r
+ uint16_t* const DataLength,\r
+ uint8_t* Data);\r
+\r
+ /**\r
+ * @brief Audio class driver event for an Audio Stream start/stop change. This event fires each time the device receives a stream enable or\r
+ * disable control request from the host, to start and stop the audio stream. The current state of the stream can be determined by the\r
+ * State.InterfaceEnabled value inside the Audio interface structure passed as a parameter.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void EVENT_Audio_Device_StreamStartStop(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo);\r
+\r
+ /* Inline Functions: */\r
+ /**\r
+ * @brief General management task for a given Audio class interface, required for the correct operation of the interface. This should\r
+ * be called frequently in the main program loop, before the master USB management task @ref USB_USBTask().\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline void Audio_Device_USBTask(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void Audio_Device_USBTask(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ {\r
+ (void)AudioInterfaceInfo;\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the given audio interface is ready for a sample to be read from it, and selects the streaming\r
+ * OUT endpoint ready for reading.\r
+ *\r
+ * \pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @return Boolean \c true if the given Audio interface has a sample to be read, \c false otherwise.\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline bool Audio_Device_IsSampleReceived(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline bool Audio_Device_IsSampleReceived(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ {\r
+ if ((USB_DeviceState[AudioInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(AudioInterfaceInfo->State.InterfaceEnabled))\r
+ return false;\r
+\r
+ Endpoint_SelectEndpoint(AudioInterfaceInfo->Config.PortNumber, AudioInterfaceInfo->Config.DataOUTEndpointNumber);\r
+ return Endpoint_IsOUTReceived(AudioInterfaceInfo->Config.PortNumber);\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the given audio interface is ready to accept the next sample to be written to it, and selects\r
+ * the streaming IN endpoint ready for writing.\r
+ *\r
+ * \pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @return Boolean \c true if the given Audio interface is ready to accept the next sample, \c false otherwise.\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline bool Audio_Device_IsReadyForNextSample(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline bool Audio_Device_IsReadyForNextSample(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ {\r
+ if ((USB_DeviceState[AudioInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(AudioInterfaceInfo->State.InterfaceEnabled))\r
+ return false;\r
+\r
+ Endpoint_SelectEndpoint(AudioInterfaceInfo->Config.PortNumber, AudioInterfaceInfo->Config.DataINEndpointNumber);\r
+ return Endpoint_IsINReady(USB_DeviceState[AudioInterfaceInfo->Config.PortNumber]);\r
+ }\r
+\r
+ /**\r
+ * @brief Reads the next 8-bit audio sample from the current audio interface.\r
+ *\r
+ * \pre This should be preceded immediately by a call to the @ref Audio_Device_IsSampleReceived() function to ensure\r
+ * that the correct endpoint is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @return Signed 8-bit audio sample from the audio interface.\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline int8_t Audio_Device_ReadSample8(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline int8_t Audio_Device_ReadSample8(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ {\r
+ int8_t Sample;\r
+\r
+ (void)AudioInterfaceInfo;\r
+\r
+ Sample = Endpoint_Read_8(AudioInterfaceInfo->Config.PortNumber);\r
+\r
+ if (!(Endpoint_BytesInEndpoint(AudioInterfaceInfo->Config.PortNumber)))\r
+ Endpoint_ClearOUT(AudioInterfaceInfo->Config.PortNumber);\r
+\r
+ return Sample;\r
+ }\r
+\r
+ /**\r
+ * @brief Reads the next 16-bit audio sample from the current audio interface.\r
+ *\r
+ * \pre This should be preceded immediately by a call to the @ref Audio_Device_IsSampleReceived() function to ensure\r
+ * that the correct endpoint is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @return Signed 16-bit audio sample from the audio interface.\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline int16_t Audio_Device_ReadSample16(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline int16_t Audio_Device_ReadSample16(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ {\r
+ int16_t Sample;\r
+\r
+ (void)AudioInterfaceInfo;\r
+\r
+ Sample = (int16_t)Endpoint_Read_16_LE(AudioInterfaceInfo->Config.PortNumber);\r
+\r
+ if (!(Endpoint_BytesInEndpoint(AudioInterfaceInfo->Config.PortNumber)))\r
+ Endpoint_ClearOUT(AudioInterfaceInfo->Config.PortNumber);\r
+\r
+ return Sample;\r
+ }\r
+\r
+ /**\r
+ * @brief Reads the next 24-bit audio sample from the current audio interface.\r
+ *\r
+ * \pre This should be preceded immediately by a call to the @ref Audio_Device_IsSampleReceived() function to ensure\r
+ * that the correct endpoint is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @return Signed 24-bit audio sample from the audio interface.\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline int32_t Audio_Device_ReadSample24(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline int32_t Audio_Device_ReadSample24(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ {\r
+ int32_t Sample;\r
+\r
+ (void)AudioInterfaceInfo;\r
+\r
+ Sample = (((uint32_t)Endpoint_Read_8(AudioInterfaceInfo->Config.PortNumber) << 16) | Endpoint_Read_16_LE(AudioInterfaceInfo->Config.PortNumber));\r
+\r
+ if (!(Endpoint_BytesInEndpoint(AudioInterfaceInfo->Config.PortNumber)))\r
+ Endpoint_ClearOUT(AudioInterfaceInfo->Config.PortNumber);\r
+\r
+ return Sample;\r
+ }\r
+\r
+ /**\r
+ * @brief Writes the next 8-bit audio sample to the current audio interface.\r
+ *\r
+ * \pre This should be preceded immediately by a call to the @ref Audio_Device_IsReadyForNextSample() function to\r
+ * ensure that the correct endpoint is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @param Sample : Signed 8-bit audio sample.\r
+ * @return Nothing\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline void Audio_Device_WriteSample8(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo,\r
+ const int8_t Sample) ATTR_NON_NULL_PTR_ARG(1);\r
+ static inline void Audio_Device_WriteSample8(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo,\r
+ const int8_t Sample)\r
+ {\r
+ Endpoint_Write_8(AudioInterfaceInfo->Config.PortNumber, Sample);\r
+\r
+ if (Endpoint_BytesInEndpoint(AudioInterfaceInfo->Config.PortNumber) == AudioInterfaceInfo->Config.DataINEndpointSize)\r
+ Endpoint_ClearIN(AudioInterfaceInfo->Config.PortNumber);\r
+ }\r
+\r
+ /**\r
+ * @brief Writes the next 16-bit audio sample to the current audio interface.\r
+ *\r
+ * \pre This should be preceded immediately by a call to the @ref Audio_Device_IsReadyForNextSample() function to\r
+ * ensure that the correct endpoint is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @param Sample : Signed 16-bit audio sample.\r
+ * @return Nothing\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline void Audio_Device_WriteSample16(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo,\r
+ const int16_t Sample) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void Audio_Device_WriteSample16(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo,\r
+ const int16_t Sample)\r
+ {\r
+ Endpoint_Write_16_LE(AudioInterfaceInfo->Config.PortNumber, Sample);\r
+\r
+ if (Endpoint_BytesInEndpoint(AudioInterfaceInfo->Config.PortNumber) == AudioInterfaceInfo->Config.DataINEndpointSize)\r
+ Endpoint_ClearIN(AudioInterfaceInfo->Config.PortNumber);\r
+ }\r
+\r
+ /**\r
+ * @brief Writes the next 24-bit audio sample to the current audio interface.\r
+ *\r
+ * \pre This should be preceded immediately by a call to the @ref Audio_Device_IsReadyForNextSample() function to\r
+ * ensure that the correct endpoint is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @param Sample : Signed 24-bit audio sample.\r
+ * @return Nothing\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+ static inline void Audio_Device_WriteSample24(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo,\r
+ const int32_t Sample) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void Audio_Device_WriteSample24(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo,\r
+ const int32_t Sample)\r
+ {\r
+ Endpoint_Write_16_LE(AudioInterfaceInfo->Config.PortNumber, Sample);\r
+ Endpoint_Write_8(AudioInterfaceInfo->Config.PortNumber, Sample >> 16);\r
+\r
+ if (Endpoint_BytesInEndpoint(AudioInterfaceInfo->Config.PortNumber) == AudioInterfaceInfo->Config.DataINEndpointSize)\r
+ Endpoint_ClearIN(AudioInterfaceInfo->Config.PortNumber);\r
+ }\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_AUDIO_DEVICE_C)\r
+ void Audio_Device_Event_Stub(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo) ATTR_CONST;\r
+PRAGMA_WEAK(EVENT_Audio_Device_StreamStartStop,Audio_Device_Event_Stub) \r
+ void EVENT_Audio_Device_StreamStartStop(USB_ClassInfo_Audio_Device_t* const AudioInterfaceInfo)\r
+ ATTR_WEAK ATTR_NON_NULL_PTR_ARG(1) ATTR_ALIAS(Audio_Device_Event_Stub);\r
+ #endif\r
+\r
+ #endif \r
+ \r
+ \r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Device mode driver for the library USB CDC Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../Core/USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+\r
+#define __INCLUDE_FROM_CDC_DRIVER\r
+#define __INCLUDE_FROM_CDC_DEVICE_C\r
+#include "CDCClassDevice.h"\r
+\r
+void CDC_Device_ProcessControlRequest(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+{\r
+ if (!(Endpoint_IsSETUPReceived(CDCInterfaceInfo->Config.PortNumber)))\r
+ return;\r
+\r
+ if (USB_ControlRequest.wIndex != CDCInterfaceInfo->Config.ControlInterfaceNumber)\r
+ return;\r
+\r
+ switch (USB_ControlRequest.bRequest)\r
+ {\r
+ case CDC_REQ_GetLineEncoding:\r
+ if (USB_ControlRequest.bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE))\r
+ {\r
+ Endpoint_ClearSETUP(CDCInterfaceInfo->Config.PortNumber);\r
+\r
+ while (!(Endpoint_IsINReady(CDCInterfaceInfo->Config.PortNumber)));\r
+\r
+ Endpoint_Write_32_LE(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->State.LineEncoding.BaudRateBPS);\r
+ Endpoint_Write_8(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->State.LineEncoding.CharFormat);\r
+ Endpoint_Write_8(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->State.LineEncoding.ParityType);\r
+ Endpoint_Write_8(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->State.LineEncoding.DataBits);\r
+\r
+ Endpoint_ClearIN(CDCInterfaceInfo->Config.PortNumber);\r
+ Endpoint_ClearStatusStage(CDCInterfaceInfo->Config.PortNumber);\r
+ }\r
+\r
+ break;\r
+ case CDC_REQ_SetLineEncoding:\r
+ if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE))\r
+ {\r
+ Endpoint_ClearSETUP(CDCInterfaceInfo->Config.PortNumber);\r
+\r
+ while (!(Endpoint_IsOUTReceived(CDCInterfaceInfo->Config.PortNumber)));\r
+\r
+ CDCInterfaceInfo->State.LineEncoding.BaudRateBPS = Endpoint_Read_32_LE(CDCInterfaceInfo->Config.PortNumber);\r
+ CDCInterfaceInfo->State.LineEncoding.CharFormat = Endpoint_Read_8(CDCInterfaceInfo->Config.PortNumber);\r
+ CDCInterfaceInfo->State.LineEncoding.ParityType = Endpoint_Read_8(CDCInterfaceInfo->Config.PortNumber);\r
+ CDCInterfaceInfo->State.LineEncoding.DataBits = Endpoint_Read_8(CDCInterfaceInfo->Config.PortNumber);\r
+\r
+ Endpoint_ClearOUT(CDCInterfaceInfo->Config.PortNumber);\r
+ Endpoint_ClearStatusStage(CDCInterfaceInfo->Config.PortNumber);\r
+\r
+ EVENT_CDC_Device_LineEncodingChanged(CDCInterfaceInfo);\r
+ }\r
+\r
+ break;\r
+ case CDC_REQ_SetControlLineState:\r
+ if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE))\r
+ {\r
+ Endpoint_ClearSETUP(CDCInterfaceInfo->Config.PortNumber);\r
+ Endpoint_ClearStatusStage(CDCInterfaceInfo->Config.PortNumber);\r
+\r
+ CDCInterfaceInfo->State.ControlLineStates.HostToDevice = USB_ControlRequest.wValue;\r
+\r
+ EVENT_CDC_Device_ControLineStateChanged(CDCInterfaceInfo);\r
+ }\r
+\r
+ break;\r
+ case CDC_REQ_SendBreak:\r
+ if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_CLASS | REQREC_INTERFACE))\r
+ {\r
+ Endpoint_ClearSETUP(CDCInterfaceInfo->Config.PortNumber);\r
+ Endpoint_ClearStatusStage(CDCInterfaceInfo->Config.PortNumber);\r
+\r
+ EVENT_CDC_Device_BreakSent(CDCInterfaceInfo, (uint8_t)USB_ControlRequest.wValue);\r
+ }\r
+\r
+ break;\r
+ }\r
+}\r
+\r
+bool CDC_Device_ConfigureEndpoints(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+{\r
+ memset(&CDCInterfaceInfo->State, 0x00, sizeof(CDCInterfaceInfo->State));\r
+\r
+ for (uint8_t EndpointNum = 1; EndpointNum < ENDPOINT_TOTAL_ENDPOINTS(CDCInterfaceInfo->Config.PortNumber); EndpointNum++)\r
+ {\r
+ uint16_t Size;\r
+ uint8_t Type;\r
+ uint8_t Direction;\r
+ bool DoubleBanked;\r
+\r
+ if (EndpointNum == CDCInterfaceInfo->Config.DataINEndpointNumber)\r
+ {\r
+ Size = CDCInterfaceInfo->Config.DataINEndpointSize;\r
+ Direction = ENDPOINT_DIR_IN;\r
+ Type = EP_TYPE_BULK;\r
+ DoubleBanked = CDCInterfaceInfo->Config.DataINEndpointDoubleBank;\r
+ }\r
+ else if (EndpointNum == CDCInterfaceInfo->Config.DataOUTEndpointNumber)\r
+ {\r
+ Size = CDCInterfaceInfo->Config.DataOUTEndpointSize;\r
+ Direction = ENDPOINT_DIR_OUT;\r
+ Type = EP_TYPE_BULK;\r
+ DoubleBanked = CDCInterfaceInfo->Config.DataOUTEndpointDoubleBank;\r
+ }\r
+ else if (EndpointNum == CDCInterfaceInfo->Config.NotificationEndpointNumber)\r
+ {\r
+ Size = CDCInterfaceInfo->Config.NotificationEndpointSize;\r
+ Direction = ENDPOINT_DIR_IN;\r
+ Type = EP_TYPE_INTERRUPT;\r
+ DoubleBanked = CDCInterfaceInfo->Config.NotificationEndpointDoubleBank;\r
+ }\r
+ else\r
+ {\r
+ continue;\r
+ }\r
+\r
+ if (!(Endpoint_ConfigureEndpoint(CDCInterfaceInfo->Config.PortNumber, EndpointNum, Type, Direction, Size,\r
+ DoubleBanked ? ENDPOINT_BANK_DOUBLE : ENDPOINT_BANK_SINGLE)))\r
+ {\r
+ return false;\r
+ }\r
+ }\r
+\r
+ return true;\r
+}\r
+\r
+void CDC_Device_USBTask(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+{\r
+ if ((USB_DeviceState[CDCInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS))\r
+ return;\r
+\r
+ #if !defined(NO_CLASS_DRIVER_AUTOFLUSH)\r
+ CDC_Device_Flush(CDCInterfaceInfo);\r
+ #endif\r
+}\r
+\r
+uint8_t CDC_Device_SendString(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ const char* const String)\r
+{\r
+ if ((USB_DeviceState[CDCInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS))\r
+ return ENDPOINT_RWSTREAM_DeviceDisconnected;\r
+\r
+ Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->Config.DataINEndpointNumber);\r
+ Endpoint_Write_Stream_LE(CDCInterfaceInfo->Config.PortNumber, String, strlen(String), NULL);\r
+ Endpoint_ClearIN(CDCInterfaceInfo->Config.PortNumber);\r
+ return ENDPOINT_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t CDC_Device_SendData(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ const char* const Buffer,\r
+ const uint16_t Length)\r
+{\r
+ if ((USB_DeviceState[CDCInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS))\r
+ return ENDPOINT_RWSTREAM_DeviceDisconnected;\r
+\r
+ Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->Config.DataINEndpointNumber);\r
+ Endpoint_Write_Stream_LE(CDCInterfaceInfo->Config.PortNumber, Buffer, Length, NULL);\r
+ Endpoint_ClearIN(CDCInterfaceInfo->Config.PortNumber);\r
+ return ENDPOINT_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t CDC_Device_SendByte(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ const uint8_t Data)\r
+{\r
+ if ((USB_DeviceState[CDCInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS))\r
+ return ENDPOINT_RWSTREAM_DeviceDisconnected;\r
+\r
+ Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->Config.DataINEndpointNumber);\r
+\r
+ if (!(Endpoint_IsReadWriteAllowed(CDCInterfaceInfo->Config.PortNumber)))\r
+ {\r
+ Endpoint_ClearIN(CDCInterfaceInfo->Config.PortNumber);\r
+\r
+ uint8_t ErrorCode;\r
+\r
+ if ((ErrorCode = Endpoint_WaitUntilReady()) != ENDPOINT_READYWAIT_NoError)\r
+ return ErrorCode;\r
+ }\r
+\r
+ Endpoint_Write_8(CDCInterfaceInfo->Config.PortNumber, Data);\r
+ return ENDPOINT_READYWAIT_NoError;\r
+}\r
+\r
+uint8_t CDC_Device_Flush(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+{\r
+ if ((USB_DeviceState[CDCInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS))\r
+ return ENDPOINT_RWSTREAM_DeviceDisconnected;\r
+\r
+ uint8_t ErrorCode;\r
+\r
+ Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->Config.DataINEndpointNumber);\r
+\r
+ if (!(Endpoint_BytesInEndpoint(CDCInterfaceInfo->Config.PortNumber)))\r
+ return ENDPOINT_READYWAIT_NoError;\r
+\r
+ bool BankFull = !(Endpoint_IsReadWriteAllowed(CDCInterfaceInfo->Config.PortNumber));\r
+\r
+ Endpoint_ClearIN(CDCInterfaceInfo->Config.PortNumber);\r
+\r
+ if (BankFull)\r
+ {\r
+ if ((ErrorCode = Endpoint_WaitUntilReady()) != ENDPOINT_READYWAIT_NoError)\r
+ return ErrorCode;\r
+\r
+ Endpoint_ClearIN(CDCInterfaceInfo->Config.PortNumber);\r
+ }\r
+\r
+ return ENDPOINT_READYWAIT_NoError;\r
+}\r
+\r
+uint16_t CDC_Device_BytesReceived(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+{\r
+ if ((USB_DeviceState[CDCInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS))\r
+ return 0;\r
+\r
+ Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->Config.DataOUTEndpointNumber);\r
+\r
+ if (Endpoint_IsOUTReceived(CDCInterfaceInfo->Config.PortNumber))\r
+ {\r
+ if (!(Endpoint_BytesInEndpoint(CDCInterfaceInfo->Config.PortNumber)))\r
+ {\r
+ Endpoint_ClearOUT(CDCInterfaceInfo->Config.PortNumber);\r
+ return 0;\r
+ }\r
+ else\r
+ {\r
+ return Endpoint_BytesInEndpoint(CDCInterfaceInfo->Config.PortNumber);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return 0;\r
+ }\r
+}\r
+\r
+int16_t CDC_Device_ReceiveByte(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+{\r
+ if ((USB_DeviceState[CDCInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS))\r
+ return -1;\r
+\r
+ int16_t ReceivedByte = -1;\r
+\r
+ Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->Config.DataOUTEndpointNumber);\r
+\r
+ if (Endpoint_IsOUTReceived(CDCInterfaceInfo->Config.PortNumber))\r
+ {\r
+ if (Endpoint_BytesInEndpoint(CDCInterfaceInfo->Config.PortNumber)){\r
+ ReceivedByte = Endpoint_Read_8(CDCInterfaceInfo->Config.PortNumber);\r
+ //Endpoint_ClearOUT();\r
+ }\r
+\r
+ if (!(Endpoint_BytesInEndpoint(CDCInterfaceInfo->Config.PortNumber)))\r
+ Endpoint_ClearOUT(CDCInterfaceInfo->Config.PortNumber);\r
+ }\r
+\r
+ return ReceivedByte;\r
+}\r
+\r
+void CDC_Device_SendControlLineStateChange(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+{\r
+ if ((USB_DeviceState[CDCInterfaceInfo->Config.PortNumber] != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS))\r
+ return;\r
+\r
+ Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.PortNumber, CDCInterfaceInfo->Config.NotificationEndpointNumber);\r
+\r
+ USB_Request_Header_t Notification = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE),\r
+ .bRequest = CDC_NOTIF_SerialState,\r
+ .wValue = CPU_TO_LE16(0),\r
+ .wIndex = CPU_TO_LE16(0),\r
+ .wLength = CPU_TO_LE16(sizeof(CDCInterfaceInfo->State.ControlLineStates.DeviceToHost)),\r
+ };\r
+\r
+ Endpoint_Write_Stream_LE(CDCInterfaceInfo->Config.PortNumber, &Notification, sizeof(USB_Request_Header_t), NULL);\r
+ Endpoint_Write_Stream_LE(CDCInterfaceInfo->Config.PortNumber, &CDCInterfaceInfo->State.ControlLineStates.DeviceToHost,\r
+ sizeof(CDCInterfaceInfo->State.ControlLineStates.DeviceToHost),\r
+ NULL);\r
+ Endpoint_ClearIN(CDCInterfaceInfo->Config.PortNumber);\r
+}\r
+\r
+#if (defined(FDEV_SETUP_STREAM) && (!defined(__IAR_SYSTEMS_ICC__) || (_DLIB_FILE_DESCRIPTOR == 1)))\r
+void CDC_Device_CreateStream(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ FILE* const Stream)\r
+{\r
+ *Stream = (FILE)FDEV_SETUP_STREAM(CDC_Device_putchar, CDC_Device_getchar, _FDEV_SETUP_RW);\r
+ fdev_set_udata(Stream, CDCInterfaceInfo);\r
+}\r
+\r
+void CDC_Device_CreateBlockingStream(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ FILE* const Stream)\r
+{\r
+ *Stream = (FILE)FDEV_SETUP_STREAM(CDC_Device_putchar, CDC_Device_getchar_Blocking, _FDEV_SETUP_RW);\r
+ fdev_set_udata(Stream, CDCInterfaceInfo);\r
+}\r
+\r
+static int CDC_Device_putchar(char c,\r
+ FILE* Stream)\r
+{\r
+ return CDC_Device_SendByte((USB_ClassInfo_CDC_Device_t*)fdev_get_udata(Stream), c) ? _FDEV_ERR : 0;\r
+}\r
+\r
+static int CDC_Device_getchar(FILE* Stream)\r
+{\r
+ int16_t ReceivedByte = CDC_Device_ReceiveByte((USB_ClassInfo_CDC_Device_t*)fdev_get_udata(Stream));\r
+\r
+ if (ReceivedByte < 0)\r
+ return _FDEV_EOF;\r
+\r
+ return ReceivedByte;\r
+}\r
+\r
+static int CDC_Device_getchar_Blocking(FILE* Stream)\r
+{\r
+ int16_t ReceivedByte;\r
+\r
+ while ((ReceivedByte = CDC_Device_ReceiveByte((USB_ClassInfo_CDC_Device_t*)fdev_get_udata(Stream))) < 0)\r
+ {\r
+ if (USB_DeviceState[corenum] == DEVICE_STATE_Unattached)\r
+ return _FDEV_EOF;\r
+\r
+ CDC_Device_USBTask((USB_ClassInfo_CDC_Device_t*)fdev_get_udata(Stream));\r
+ USB_USBTask();\r
+ }\r
+\r
+ return ReceivedByte;\r
+}\r
+#endif\r
+\r
+void CDC_Device_Event_Stub(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+{\r
+\r
+}\r
+\r
+void CDC_Device_Event_Stub2(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, const uint8_t Duration)\r
+{\r
+}\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief Device mode driver for the library USB CDC Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassCDC\r
+ * @defgroup Group_USBClassCDCDevice CDC Class Device Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - nxpUSBlib/Drivers/USB/Class/Device/CDCClassDevice.c <i>(Makefile source module name: NXPUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Device Mode USB Class driver framework interface, for the CDC USB Class driver.\r
+ *\r
+ * @note There are several major drawbacks to the CDC-ACM standard USB class, however\r
+ * it is very standardized and thus usually available as a built-in driver on\r
+ * most platforms, and so is a better choice than a proprietary serial class.\r
+ *\r
+ * One major issue with CDC-ACM is that it requires two Interface descriptors,\r
+ * which will upset most hosts when part of a multi-function "Composite" USB\r
+ * device, as each interface will be loaded into a separate driver instance. To\r
+ * combat this, you should use the "Interface Association Descriptor" addendum to\r
+ * the USB standard which is available on most OSes when creating Composite devices.\r
+ *\r
+ * Another major oversight is that there is no mechanism for the host to notify the\r
+ * device that there is a data sink on the host side ready to accept data. This\r
+ * means that the device may try to send data while the host isn't listening, causing\r
+ * lengthy blocking timeouts in the transmission routines. To combat this, it is\r
+ * recommended that the virtual serial line DTR (Data Terminal Ready) be used where\r
+ * possible to determine if a host application is ready for data.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _CDC_CLASS_DEVICE_H_\r
+#define _CDC_CLASS_DEVICE_H_\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/CDCClassCommon.h"\r
+\r
+ #include <stdio.h>\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_CDC_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Type Defines: */\r
+ /** @brief CDC Class Device Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made for each CDC interface\r
+ * within the user application, and passed to each of the CDC class driver functions as the\r
+ * CDCInterfaceInfo parameter. This stores each CDC interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ const struct\r
+ {\r
+ uint8_t ControlInterfaceNumber; /**< Interface number of the CDC control interface within the device. */\r
+\r
+ uint8_t DataINEndpointNumber; /**< Endpoint number of the CDC interface's IN data endpoint. */\r
+ uint16_t DataINEndpointSize; /**< Size in bytes of the CDC interface's IN data endpoint. */\r
+ bool DataINEndpointDoubleBank; /**< Indicates if the CDC interface's IN data endpoint should use double banking. */\r
+\r
+ uint8_t DataOUTEndpointNumber; /**< Endpoint number of the CDC interface's OUT data endpoint. */\r
+ uint16_t DataOUTEndpointSize; /**< Size in bytes of the CDC interface's OUT data endpoint. */\r
+ bool DataOUTEndpointDoubleBank; /**< Indicates if the CDC interface's OUT data endpoint should use double banking. */\r
+\r
+ uint8_t NotificationEndpointNumber; /**< Endpoint number of the CDC interface's IN notification endpoint, if used. */\r
+ uint16_t NotificationEndpointSize; /**< Size in bytes of the CDC interface's IN notification endpoint, if used. */\r
+ bool NotificationEndpointDoubleBank; /**< Indicates if the CDC interface's notification endpoint should use double banking. */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.*/\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ struct\r
+ {\r
+ uint16_t HostToDevice; /**< Control line states from the host to device, as a set of \c CDC_CONTROL_LINE_OUT_*\r
+ * masks. This value is updated each time @ref CDC_Device_USBTask() is called.\r
+ */\r
+ uint16_t DeviceToHost; /**< Control line states from the device to host, as a set of \c CDC_CONTROL_LINE_IN_*\r
+ * masks - to notify the host of changes to these values, call the\r
+ * @ref CDC_Device_SendControlLineStateChange() function.\r
+ */\r
+ } ControlLineStates; /**< Current states of the virtual serial port's control lines between the device and host. */\r
+\r
+ CDC_LineEncoding_t LineEncoding; /** Line encoding used in the virtual serial port, for the device's information.\r
+ * This is generally only used if the virtual serial port data is to be\r
+ * reconstructed on a physical UART.\r
+ */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * are reset to their defaults when the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_CDC_Device_t;\r
+\r
+ /* Function Prototypes: */\r
+\r
+ /**\r
+ * @brief Configures the endpoints of a given CDC interface, ready for use. This should be linked to the library\r
+ * @ref EVENT_USB_Device_ConfigurationChanged() event so that the endpoints are configured when the configuration containing\r
+ * the given CDC interface is selected.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @return Boolean \c true if the endpoints were successfully configured, \c false otherwise.\r
+ */\r
+ bool CDC_Device_ConfigureEndpoints(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Processes incoming control requests from the host, that are directed to the given CDC class interface. This should be\r
+ * linked to the library @ref EVENT_USB_Device_ControlRequest() event.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void CDC_Device_ProcessControlRequest(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief General management task for a given CDC class interface, required for the correct operation of the interface. This should\r
+ * be called frequently in the main program loop, before the master USB management task @ref USB_USBTask().\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void CDC_Device_USBTask(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief CDC class driver event for a line encoding change on a CDC interface. This event fires each time the host requests a\r
+ * line encoding change (containing the serial parity, baud and other configuration information) and may be hooked in the\r
+ * user program by declaring a handler function with the same name and parameters listed here. The new line encoding\r
+ * settings are available in the LineEncoding structure inside the CDC interface structure passed as a parameter.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void EVENT_CDC_Device_LineEncodingChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief CDC class driver event for a control line state change on a CDC interface. This event fires each time the host requests a\r
+ * control line state change (containing the virtual serial control line states, such as DTR) and may be hooked in the\r
+ * user program by declaring a handler function with the same name and parameters listed here. The new control line states\r
+ * are available in the \c ControlLineStates.HostToDevice value inside the CDC interface structure passed as a parameter, set as\r
+ * a mask of \c CDC_CONTROL_LINE_OUT_* masks.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+ \r
+ void EVENT_CDC_Device_ControLineStateChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief CDC class driver event for a send break request sent to the device from the host. This is generally used to separate\r
+ * data or to indicate a special condition to the receiving device.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @param Duration : Duration of the break that has been sent by the host, in milliseconds.\r
+ * @return Nothing\r
+ */\r
+ void EVENT_CDC_Device_BreakSent(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ const uint8_t Duration) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Sends a given data buffer to the attached USB host, if connected. If a host is not connected when the function is\r
+ * called, the string is discarded. Bytes will be queued for transmission to the host until either the endpoint bank\r
+ * becomes full, or the @ref CDC_Device_Flush() function is called to flush the pending data to the host. This allows\r
+ * for multiple bytes to be packed into a single endpoint packet, increasing data throughput.\r
+ *\r
+ * \pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @param Buffer : Pointer to a buffer containing the data to send to the device.\r
+ * @param Length : Length of the data to send to the host.\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Device_SendData(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ const char* const Buffer,\r
+ const uint16_t Length) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /**\r
+ * @brief Sends a given null terminated string to the attached USB host, if connected. If a host is not connected when\r
+ * the function is called, the string is discarded. Bytes will be queued for transmission to the host until either\r
+ * the endpoint bank becomes full, or the @ref CDC_Device_Flush() function is called to flush the pending data to\r
+ * the host. This allows for multiple bytes to be packed into a single endpoint packet, increasing data throughput.\r
+ *\r
+ * \pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @param String : Pointer to the null terminated string to send to the host.\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Device_SendString(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ const char* const String) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /**\r
+ * @brief Sends a given byte to the attached USB host, if connected. If a host is not connected when the function is called, the\r
+ * byte is discarded. Bytes will be queued for transmission to the host until either the endpoint bank becomes full, or the\r
+ * @ref CDC_Device_Flush() function is called to flush the pending data to the host. This allows for multiple bytes to be\r
+ * packed into a single endpoint packet, increasing data throughput.\r
+ *\r
+ * \pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @param Data : Byte of data to send to the host.\r
+ * @return A value from the @ref Endpoint_WaitUntilReady_ErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Device_SendByte(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ const uint8_t Data) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Determines the number of bytes received by the CDC interface from the host, waiting to be read. This indicates the number\r
+ * of bytes in the OUT endpoint bank only, and thus the number of calls to @ref CDC_Device_ReceiveByte() which are guaranteed to\r
+ * succeed immediately. If multiple bytes are to be received, they should be buffered by the user application, as the endpoint\r
+ * bank will not be released back to the USB controller until all bytes are read.\r
+ *\r
+ * \pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @return Total number of buffered bytes received from the host.\r
+ */\r
+ uint16_t CDC_Device_BytesReceived(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Reads a byte of data from the host. If no data is waiting to be read of if a USB host is not connected, the function\r
+ * returns a negative value. The @ref CDC_Device_BytesReceived() function may be queried in advance to determine how many\r
+ * bytes are currently buffered in the CDC interface's data receive endpoint bank, and thus how many repeated calls to this\r
+ * function which are guaranteed to succeed.\r
+ *\r
+ * \pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @return Next received byte from the host, or a negative value if no data received.\r
+ */\r
+ int16_t CDC_Device_ReceiveByte(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Flushes any data waiting to be sent, ensuring that the send buffer is cleared.\r
+ *\r
+ * \pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @return A value from the @ref Endpoint_WaitUntilReady_ErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Device_Flush(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Sends a Serial Control Line State Change notification to the host. This should be called when the virtual serial\r
+ * control lines (DCD, DSR, etc.) have changed states, or to give BREAK notifications to the host. Line states persist\r
+ * until they are cleared via a second notification. This should be called each time the CDC class driver's\r
+ * \c ControlLineStates.DeviceToHost value is updated to push the new states to the USB host.\r
+ *\r
+ * \pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void CDC_Device_SendControlLineStateChange(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+ #if (!defined(__IAR_SYSTEMS_ICC__) || (_DLIB_FILE_DESCRIPTOR == 1))\r
+ /**\r
+ * @brief Creates a standard character stream for the given CDC Device instance so that it can be used with all the regular\r
+ * functions in the standard <stdio.h> library that accept a \c FILE stream as a destination (e.g. \c fprintf()). The created\r
+ * stream is bidirectional and can be used for both input and output functions.\r
+ *\r
+ * Reading data from this stream is non-blocking, i.e. in most instances, complete strings cannot be read in by a single\r
+ * fetch, as the endpoint will not be ready at some point in the transmission, aborting the transfer. However, this may\r
+ * be used when the read data is processed byte-per-bye (via \c getc()) or when the user application will implement its own\r
+ * line buffering.\r
+ *\r
+ * @note The created stream can be given as stdout if desired to direct the standard output from all <stdio.h> functions\r
+ * to the given CDC interface.\r
+ * \n\n\r
+ *\r
+ * @note This function is not available on all microcontroller architectures.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @param Stream : Pointer to a FILE structure where the created stream should be placed.\r
+ * @return Nothing\r
+ */\r
+ void CDC_Device_CreateStream(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ FILE* const Stream) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /**\r
+ * @brief Identical to @ref CDC_Device_CreateStream(), except that reads are blocking until the calling stream function terminates\r
+ * the transfer. While blocking, the USB and CDC service tasks are called repeatedly to maintain USB communications.\r
+ *\r
+ * @note This function is not available on all microcontroller architectures.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @param Stream : Pointer to a FILE structure where the created stream should be placed.\r
+ * @return Nothing\r
+ */\r
+ void CDC_Device_CreateBlockingStream(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ FILE* const Stream) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+ #endif /* IAR DLIB check */\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_CDC_DEVICE_C)\r
+ #if defined(FDEV_SETUP_STREAM)\r
+ static int CDC_Device_putchar(char c,\r
+ FILE* Stream) ATTR_NON_NULL_PTR_ARG(2);\r
+ static int CDC_Device_getchar(FILE* Stream) ATTR_NON_NULL_PTR_ARG(1);\r
+ static int CDC_Device_getchar_Blocking(FILE* Stream) ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+\r
+ void CDC_Device_Event_Stub(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo) ATTR_CONST;\r
+ void CDC_Device_Event_Stub2(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo, const uint8_t Duration) ATTR_CONST;\r
+\r
+PRAGMA_WEAK(EVENT_CDC_Device_LineEncodingChanged,CDC_Device_Event_Stub) \r
+ void EVENT_CDC_Device_LineEncodingChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+ ATTR_WEAK ATTR_NON_NULL_PTR_ARG(1) ATTR_ALIAS(CDC_Device_Event_Stub);\r
+PRAGMA_WEAK(EVENT_CDC_Device_ControLineStateChanged,CDC_Device_Event_Stub) \r
+ void EVENT_CDC_Device_ControLineStateChanged(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)\r
+ ATTR_WEAK ATTR_NON_NULL_PTR_ARG(1) ATTR_ALIAS(CDC_Device_Event_Stub);\r
+PRAGMA_WEAK(EVENT_CDC_Device_BreakSent,CDC_Device_Event_Stub2) \r
+ void EVENT_CDC_Device_BreakSent(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,\r
+ const uint8_t Duration) ATTR_WEAK ATTR_NON_NULL_PTR_ARG(1)\r
+ ATTR_ALIAS(CDC_Device_Event_Stub2);\r
+ #endif\r
+\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Device mode driver for the library USB HID Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassHID\r
+ * @defgroup Group_USBClassHIDDevice HID Class Device Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - nxpUSBlib/Drivers/USB/Class/Device/HID.c <i>(Makefile source module name: NXPUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Device Mode USB Class driver framework interface, for the HID USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _HID_CLASS_DEVICE_H_\r
+#define _HID_CLASS_DEVICE_H_\r
+\r
+/* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/HIDClassCommon.h"\r
+\r
+/* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+/* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_HID_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+/* Public Interface - May be used in end-application: */\r
+/* Type Defines: */\r
+/** @brief HID Class Device Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made for each HID interface\r
+ * within the user application, and passed to each of the HID class driver functions as the\r
+ * \c HIDInterfaceInfo parameter. This stores each HID interface's configuration and state information.\r
+ *\r
+ * @note Due to technical limitations, the HID device class driver does not utilize a separate OUT\r
+ * endpoint for host->device communications. Instead, the host->device data (if any) is sent to\r
+ * the device via the control endpoint.\r
+ */\r
+typedef struct {\r
+ const struct {\r
+ uint8_t InterfaceNumber; /**< Interface number of the HID interface within the device. */\r
+\r
+ uint8_t ReportINEndpointNumber; /**< Endpoint number of the HID interface's IN report endpoint. */\r
+ uint16_t ReportINEndpointSize; /**< Size in bytes of the HID interface's IN report endpoint. */\r
+ bool ReportINEndpointDoubleBank; /**< Indicates if the HID interface's IN report endpoint should use double banking. */\r
+\r
+ void *PrevReportINBuffer; /**< Pointer to a buffer where the previously created HID input report can be\r
+ * stored by the driver, for comparison purposes to detect report changes that\r
+ * must be sent immediately to the host. This should point to a buffer big enough\r
+ * to hold the largest HID input report sent from the HID interface. If this is set\r
+ * to \c NULL, it is up to the user to force transfers when needed in the\r
+ * @ref CALLBACK_HID_Device_CreateHIDReport() callback function.\r
+ *\r
+ * @note Due to the single buffer, the internal driver can only correctly compare\r
+ * subsequent reports with identical report IDs. In multiple report devices,\r
+ * this buffer should be set to \c NULL and the decision to send reports made\r
+ * by the user application instead.\r
+ */\r
+ uint8_t PrevReportINBufferSize; /**< Size in bytes of the given input report buffer. This is used to create a\r
+ * second buffer of the same size within the driver so that subsequent reports\r
+ * can be compared. If the user app is to determine when reports are to be sent\r
+ * exclusively (i.e. @ref PrevReportINBuffer is \c NULL) this value must still be\r
+ * set to the size of the largest report the device can issue to the host.\r
+ */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.*/\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+\r
+ struct {\r
+ bool UsingReportProtocol; /**< Indicates if the HID interface is set to Boot or Report protocol mode. */\r
+ uint16_t IdleCount; /**< Report idle period, in milliseconds, set by the host. */\r
+ uint16_t IdleMSRemaining; /**< Total number of milliseconds remaining before the idle period elapsed - this\r
+ * should be decremented by the user application if non-zero each millisecond. */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * are reset to their defaults when the interface is enumerated.\r
+ */\r
+\r
+} USB_ClassInfo_HID_Device_t;\r
+\r
+/* Function Prototypes: */\r
+/**\r
+ * @brief Configures the endpoints of a given HID interface, ready for use. This should be linked to the library\r
+ * @ref EVENT_USB_Device_ConfigurationChanged() event so that the endpoints are configured when the configuration\r
+ * containing the given HID interface is selected.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class configuration and state.\r
+ *\r
+ * @return Boolean \c true if the endpoints were successfully configured, \c false otherwise.\r
+ */\r
+bool HID_Device_ConfigureEndpoints(USB_ClassInfo_HID_Device_t *const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief Processes incoming control requests from the host, that are directed to the given HID class interface. This should be\r
+ * linked to the library @ref EVENT_USB_Device_ControlRequest() event.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+void HID_Device_ProcessControlRequest(USB_ClassInfo_HID_Device_t *const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief General management task for a given HID class interface, required for the correct operation of the interface. This should\r
+ * be called frequently in the main program loop, before the master USB management task @ref USB_USBTask().\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+void HID_Device_USBTask(USB_ClassInfo_HID_Device_t *const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief HID class driver callback for the user creation of a HID IN report. This callback may fire in response to either\r
+ * HID class control requests from the host, or by the normal HID endpoint polling procedure. Inside this callback the\r
+ * user is responsible for the creation of the next HID input report to be sent to the host.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class configuration and state.\r
+ * @param ReportID : If preset to a non-zero value, this is the report ID being requested by the host. If zero,\r
+ * this should be set to the report ID of the generated HID input report (if any). If multiple\r
+ * reports are not sent via the given HID interface, this parameter should be ignored.\r
+ * @param ReportType : Type of HID report to generate, either @ref HID_REPORT_ITEM_In or @ref HID_REPORT_ITEM_Feature.\r
+ * @param ReportData : Pointer to a buffer where the generated HID report should be stored.\r
+ * @param ReportSize : Number of bytes in the generated input report, or zero if no report is to be sent.\r
+ *\r
+ * @return Boolean \c true to force the sending of the report even if it is identical to the previous report and still within\r
+ * the idle period (useful for devices which report relative movement), \c false otherwise.\r
+ */\r
+bool CALLBACK_HID_Device_CreateHIDReport(USB_ClassInfo_HID_Device_t *const HIDInterfaceInfo,\r
+ uint8_t *const ReportID,\r
+ const uint8_t ReportType,\r
+ void *ReportData,\r
+ uint16_t *const ReportSize) ATTR_NON_NULL_PTR_ARG(1)\r
+ATTR_NON_NULL_PTR_ARG(2) ATTR_NON_NULL_PTR_ARG(4) ATTR_NON_NULL_PTR_ARG(5);\r
+\r
+/**\r
+ * @brief HID class driver callback for the user processing of a received HID OUT report. This callback may fire in response to\r
+ * either HID class control requests from the host, or by the normal HID endpoint polling procedure. Inside this callback\r
+ * the user is responsible for the processing of the received HID output report from the host.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class configuration and state.\r
+ * @param ReportID : Report ID of the received output report. If multiple reports are not received via the given HID\r
+ * interface, this parameter should be ignored.\r
+ * @param ReportType : Type of received HID report, either @ref HID_REPORT_ITEM_Out or @ref HID_REPORT_ITEM_Feature.\r
+ * @param ReportData : Pointer to a buffer where the received HID report is stored.\r
+ * @param ReportSize : Size in bytes of the received report from the host.\r
+ * @return Nothing\r
+ */\r
+void CALLBACK_HID_Device_ProcessHIDReport(USB_ClassInfo_HID_Device_t *const HIDInterfaceInfo,\r
+ const uint8_t ReportID,\r
+ const uint8_t ReportType,\r
+ const void *ReportData,\r
+ const uint16_t ReportSize) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(4);\r
+\r
+/* Inline Functions: */\r
+/**\r
+ * @brief Indicates that a millisecond of idle time has elapsed on the given HID interface, and the interface's idle count should be\r
+ * decremented. This should be called once per millisecond so that hardware key-repeats function correctly. It is recommended\r
+ * that this be called by the @ref EVENT_USB_Device_StartOfFrame() event, once SOF events have been enabled via\r
+ * @ref USB_Device_EnableSOFEvents().\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class configuration and state.\r
+ */\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void HID_Device_MillisecondElapsed(USB_ClassInfo_HID_Device_t *const HIDInterfaceInfo) ATTR_ALWAYS_INLINE\r
+ATTR_NON_NULL_PTR_ARG(1);\r
+static inline void HID_Device_MillisecondElapsed(USB_ClassInfo_HID_Device_t *const HIDInterfaceInfo)\r
+{\r
+ if (HIDInterfaceInfo->State.IdleMSRemaining) {\r
+ HIDInterfaceInfo->State.IdleMSRemaining--;\r
+ }\r
+}\r
+\r
+/* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Device mode driver for the library USB MIDI Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassMIDI\r
+ * @defgroup Group_USBClassMIDIDevice MIDI Class Device Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - nxpUSBlib/Drivers/USB/Class/Device/MIDI.c <i>(Makefile source module name: NXPUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Device Mode USB Class driver framework interface, for the MIDI USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _MIDI_CLASS_DEVICE_H_\r
+#define _MIDI_CLASS_DEVICE_H_\r
+\r
+/* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/MIDIClassCommon.h"\r
+\r
+/* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+/* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_MIDI_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+/* Public Interface - May be used in end-application: */\r
+/* Type Define: */\r
+/**\r
+ * @brief MIDI Class Device Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made for each MIDI interface\r
+ * within the user application, and passed to each of the MIDI class driver functions as the\r
+ * \c MIDIInterfaceInfo parameter. This stores each MIDI interface's configuration and state information.\r
+ */\r
+typedef struct {\r
+ const struct {\r
+ uint8_t StreamingInterfaceNumber; /**< Index of the Audio Streaming interface within the device this structure controls. */\r
+\r
+ uint8_t DataINEndpointNumber; /**< Endpoint number of the incoming MIDI IN data, if available (zero if unused). */\r
+ uint16_t DataINEndpointSize; /**< Size in bytes of the incoming MIDI IN data endpoint, if available (zero if unused). */\r
+ bool DataINEndpointDoubleBank; /**< Indicates if the MIDI interface's IN data endpoint should use double banking. */\r
+\r
+ uint8_t DataOUTEndpointNumber; /**< Endpoint number of the outgoing MIDI OUT data, if available (zero if unused). */\r
+ uint16_t DataOUTEndpointSize; /**< Size in bytes of the outgoing MIDI OUT data endpoint, if available (zero if unused). */\r
+ bool DataOUTEndpointDoubleBank; /**< Indicates if the MIDI interface's OUT data endpoint should use double banking. */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.*/\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+\r
+#if 0\r
+ struct {\r
+ // No state information for this class\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * are reset to their defaults when the interface is enumerated.\r
+ */\r
+\r
+#endif\r
+} USB_ClassInfo_MIDI_Device_t;\r
+\r
+/* Function Prototypes: */\r
+/**\r
+ * @brief Configures the endpoints of a given MIDI interface, ready for use. This should be linked to the library\r
+ * @ref EVENT_USB_Device_ConfigurationChanged() event so that the endpoints are configured when the configuration\r
+ * containing the given MIDI interface is selected.\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing a MIDI Class configuration and state.\r
+ *\r
+ * @return Boolean \c true if the endpoints were successfully configured, \c false otherwise.\r
+ */\r
+bool MIDI_Device_ConfigureEndpoints(USB_ClassInfo_MIDI_Device_t *const MIDIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief General management task for a given MIDI class interface, required for the correct operation of the interface. This should\r
+ * be called frequently in the main program loop, before the master USB management task @ref USB_USBTask().\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing a MIDI Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+void MIDI_Device_USBTask(USB_ClassInfo_MIDI_Device_t *const MIDIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief Sends a MIDI event packet to the host. If no host is connected, the event packet is discarded. Events are queued into the\r
+ * endpoint bank until either the endpoint bank is full, or @ref MIDI_Device_Flush() is called. This allows for multiple\r
+ * MIDI events to be packed into a single endpoint packet, increasing data throughput.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing a MIDI Class configuration and state.\r
+ * @param Event : Pointer to a populated @ref MIDI_EventPacket_t structure containing the MIDI event to send.\r
+ *\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+uint8_t MIDI_Device_SendEventPacket(USB_ClassInfo_MIDI_Device_t *const MIDIInterfaceInfo,\r
+ const MIDI_EventPacket_t *const Event) ATTR_NON_NULL_PTR_ARG(1)\r
+ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+/**\r
+ * @brief Flushes the MIDI send buffer, sending any queued MIDI events to the host. This should be called to override the\r
+ * @ref MIDI_Device_SendEventPacket() function's packing behaviour, to flush queued events.\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing a MIDI Class configuration and state.\r
+ *\r
+ * @return A value from the @ref Endpoint_WaitUntilReady_ErrorCodes_t enum.\r
+ */\r
+uint8_t MIDI_Device_Flush(USB_ClassInfo_MIDI_Device_t *const MIDIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief Receives a MIDI event packet from the host. Events are unpacked from the endpoint, thus if the endpoint bank contains\r
+ * multiple MIDI events from the host in the one packet, multiple calls to this function will return each individual event.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing a MIDI Class configuration and state.\r
+ * @param Event : Pointer to a USB_MIDI_EventPacket_t structure where the received MIDI event is to be placed.\r
+ *\r
+ * @return Boolean \c true if a MIDI event packet was received, \c false otherwise.\r
+ */\r
+bool MIDI_Device_ReceiveEventPacket(USB_ClassInfo_MIDI_Device_t *const MIDIInterfaceInfo,\r
+ MIDI_EventPacket_t *const Event) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+/* Inline Functions: */\r
+/**\r
+ * @brief Processes incoming control requests from the host, that are directed to the given MIDI class interface. This should be\r
+ * linked to the library @ref EVENT_USB_Device_ControlRequest() event.\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing a MIDI Class configuration and state.\r
+ */\r
+static inline void MIDI_Device_ProcessControlRequest(USB_ClassInfo_MIDI_Device_t *const MIDIInterfaceInfo)\r
+ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+static inline void MIDI_Device_ProcessControlRequest(USB_ClassInfo_MIDI_Device_t *const MIDIInterfaceInfo)\r
+{\r
+ (void) MIDIInterfaceInfo;\r
+}\r
+\r
+/* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Device mode driver for the library USB Mass Storage Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassMS\r
+ * @defgroup Group_USBClassMSDevice Mass Storage Class Device Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - nxpUSBlib/Drivers/USB/Class/Device/MassStorage.c <i>(Makefile source module name: NXPUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Device Mode USB Class driver framework interface, for the Mass Storage USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _MS_CLASS_DEVICE_H_\r
+#define _MS_CLASS_DEVICE_H_\r
+\r
+/* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/MassStorageClassCommon.h"\r
+\r
+/* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+/* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_MS_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+/* Public Interface - May be used in end-application: */\r
+/* Type Defines: */\r
+/**\r
+ * @brief Mass Storage Class Device Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made for each Mass Storage interface\r
+ * within the user application, and passed to each of the Mass Storage class driver functions as the\r
+ * \c MSInterfaceInfo parameter. This stores each Mass Storage interface's configuration and state information.\r
+ */\r
+typedef struct {\r
+ const struct {\r
+ uint8_t InterfaceNumber; /**< Interface number of the Mass Storage interface within the device. */\r
+\r
+ uint8_t DataINEndpointNumber; /**< Endpoint number of the Mass Storage interface's IN data endpoint. */\r
+ uint16_t DataINEndpointSize; /**< Size in bytes of the Mass Storage interface's IN data endpoint. */\r
+ bool DataINEndpointDoubleBank; /**< Indicates if the Mass Storage interface's IN data endpoint should use double banking. */\r
+\r
+ uint8_t DataOUTEndpointNumber; /**< Endpoint number of the Mass Storage interface's OUT data endpoint. */\r
+ uint16_t DataOUTEndpointSize; /**< Size in bytes of the Mass Storage interface's OUT data endpoint. */\r
+ bool DataOUTEndpointDoubleBank; /**< Indicates if the Mass Storage interface's OUT data endpoint should use double banking. */\r
+\r
+ uint8_t TotalLUNs; /**< Total number of logical drives in the Mass Storage interface. */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.*/\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+\r
+ struct {\r
+ MS_CommandBlockWrapper_t CommandBlock; /**< Mass Storage class command block structure, stores the received SCSI\r
+ * command from the host which is to be processed.\r
+ */\r
+ MS_CommandStatusWrapper_t CommandStatus; /**< Mass Storage class command status structure, set elements to indicate\r
+ * the issued command's success or failure to the host.\r
+ */\r
+ volatile bool IsMassStoreReset; /**< Flag indicating that the host has requested that the Mass Storage interface be reset\r
+ * and that all current Mass Storage operations should immediately abort.\r
+ */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * are reset to their defaults when the interface is enumerated.\r
+ */\r
+\r
+} USB_ClassInfo_MS_Device_t;\r
+\r
+/* Function Prototypes: */\r
+/**\r
+ * @brief Configures the endpoints of a given Mass Storage interface, ready for use. This should be linked to the library\r
+ * @ref EVENT_USB_Device_ConfigurationChanged() event so that the endpoints are configured when the configuration\r
+ * containing the given Mass Storage interface is selected.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a Mass Storage Class configuration and state.\r
+ *\r
+ * @return Boolean \c true if the endpoints were successfully configured, \c false otherwise.\r
+ */\r
+bool MS_Device_ConfigureEndpoints(USB_ClassInfo_MS_Device_t *const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief Processes incoming control requests from the host, that are directed to the given Mass Storage class interface. This should be\r
+ * linked to the library @ref EVENT_USB_Device_ControlRequest() event.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a Mass Storage Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+void MS_Device_ProcessControlRequest(USB_ClassInfo_MS_Device_t *const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief General management task for a given Mass Storage class interface, required for the correct operation of the interface. This should\r
+ * be called frequently in the main program loop, before the master USB management task @ref USB_USBTask().\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a Mass Storage configuration and state.\r
+ * @return Nothing\r
+ */\r
+void MS_Device_USBTask(USB_ClassInfo_MS_Device_t *const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief Mass Storage class driver callback for the user processing of a received SCSI command. This callback will fire each time the\r
+ * host sends a SCSI command which requires processing by the user application. Inside this callback the user is responsible\r
+ * for the processing of the received SCSI command from the host. The SCSI command is available in the CommandBlock structure\r
+ * inside the Mass Storage class state structure passed as a parameter to the callback function.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a Mass Storage Class configuration and state.\r
+ *\r
+ * @return Boolean \c true if the SCSI command was successfully processed, \c false otherwise.\r
+ */\r
+bool CALLBACK_MS_Device_SCSICommandReceived(USB_ClassInfo_MS_Device_t *const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+/* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_MASSSTORAGE_DEVICE_C)\r
+static void MS_Device_ReturnCommandStatus(USB_ClassInfo_MS_Device_t *const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+static bool MS_Device_ReadInCommandBlock(USB_ClassInfo_MS_Device_t *const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ #endif\r
+\r
+ #endif\r
+\r
+/* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Device mode driver for the library USB RNDIS Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassRNDIS\r
+ * @defgroup Group_USBClassRNDISDevice RNDIS Class Device Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - nxpUSBlib/Drivers/USB/Class/Device/RNDIS.c <i>(Makefile source module name: NXPUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Device Mode USB Class driver framework interface, for the RNDIS USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _RNDIS_CLASS_DEVICE_H_\r
+#define _RNDIS_CLASS_DEVICE_H_\r
+\r
+/* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/RNDISClassCommon.h"\r
+\r
+/* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+/* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_RNDIS_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+/* Public Interface - May be used in end-application: */\r
+/* Type Defines: */\r
+/**\r
+ * @brief RNDIS Class Device Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made for each RNDIS interface\r
+ * within the user application, and passed to each of the RNDIS class driver functions as the\r
+ * \c RNDISInterfaceInfo parameter. This stores each RNDIS interface's configuration and state information.\r
+ */\r
+typedef struct {\r
+ const struct {\r
+ uint8_t ControlInterfaceNumber; /**< Interface number of the RNDIS control interface within the device. */\r
+\r
+ uint8_t DataINEndpointNumber; /**< Endpoint number of the RNDIS interface's IN data endpoint. */\r
+ uint16_t DataINEndpointSize; /**< Size in bytes of the RNDIS interface's IN data endpoint. */\r
+ bool DataINEndpointDoubleBank; /**< Indicates if the RNDIS interface's IN data endpoint should use double banking. */\r
+\r
+ uint8_t DataOUTEndpointNumber; /**< Endpoint number of the RNDIS interface's OUT data endpoint. */\r
+ uint16_t DataOUTEndpointSize; /**< Size in bytes of the RNDIS interface's OUT data endpoint. */\r
+ bool DataOUTEndpointDoubleBank; /**< Indicates if the RNDIS interface's OUT data endpoint should use double banking. */\r
+\r
+ uint8_t NotificationEndpointNumber; /**< Endpoint number of the RNDIS interface's IN notification endpoint, if used. */\r
+ uint16_t NotificationEndpointSize; /**< Size in bytes of the RNDIS interface's IN notification endpoint, if used. */\r
+ bool NotificationEndpointDoubleBank; /**< Indicates if the RNDIS interface's notification endpoint should use double banking. */\r
+\r
+ char *AdapterVendorDescription; /**< String description of the adapter vendor. */\r
+ MAC_Address_t AdapterMACAddress; /**< MAC address of the adapter. */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.*/\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+\r
+ struct {\r
+ uint8_t RNDISMessageBuffer[RNDIS_MESSAGE_BUFFER_SIZE]; /**< Buffer to hold RNDIS messages to and from the host,\r
+ * managed by the class driver.\r
+ */\r
+ bool ResponseReady; /**< Internal flag indicating if a RNDIS message is waiting to be returned to the host. */\r
+ uint8_t CurrRNDISState; /**< Current RNDIS state of the adapter, a value from the @ref RNDIS_States_t enum. */\r
+ uint32_t CurrPacketFilter; /**< Current packet filter mode, used internally by the class driver. */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * are reset to their defaults when the interface is enumerated.\r
+ */\r
+\r
+} USB_ClassInfo_RNDIS_Device_t;\r
+\r
+/* Function Prototypes: */\r
+/**\r
+ * @brief Configures the endpoints of a given RNDIS interface, ready for use. This should be linked to the library\r
+ * @ref EVENT_USB_Device_ConfigurationChanged() event so that the endpoints are configured when the configuration\r
+ * containing the given RNDIS interface is selected.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing a RNDIS Class configuration and state.\r
+ *\r
+ * @return Boolean \c true if the endpoints were successfully configured, \c false otherwise.\r
+ */\r
+bool RNDIS_Device_ConfigureEndpoints(USB_ClassInfo_RNDIS_Device_t *const RNDISInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief Processes incoming control requests from the host, that are directed to the given RNDIS class interface. This should be\r
+ * linked to the library @ref EVENT_USB_Device_ControlRequest() event.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing a RNDIS Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+void RNDIS_Device_ProcessControlRequest(USB_ClassInfo_RNDIS_Device_t *const RNDISInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/** \r
+ * @brief General management task for a given RNDIS class interface, required for the correct operation of the interface. This should\r
+ * be called frequently in the main program loop, before the master USB management task @ref USB_USBTask().\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing a RNDIS Class configuration and state.\r
+ * @return Nothing\r
+ */\r
+void RNDIS_Device_USBTask(USB_ClassInfo_RNDIS_Device_t *const RNDISInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+/**\r
+ * @brief Determines if a packet is currently waiting for the device to read in and process.\r
+ *\r
+ * @pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class configuration and state.\r
+ *\r
+ * @return Boolean \c true if a packet is waiting to be read in by the host, \c false otherwise.\r
+ */\r
+bool RNDIS_Device_IsPacketReceived(USB_ClassInfo_RNDIS_Device_t *const RNDISInterfaceInfo);\r
+\r
+/**\r
+ * @brief Retrieves the next pending packet from the device, discarding the remainder of the RNDIS packet header to leave\r
+ * only the packet contents for processing by the device in the nominated buffer.\r
+ *\r
+ * @pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class configuration and state.\r
+ * @param Buffer : Pointer to a buffer where the packer data is to be written to.\r
+ * @param PacketLength : Pointer to where the length in bytes of the read packet is to be stored.\r
+ *\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+uint8_t RNDIS_Device_ReadPacket(USB_ClassInfo_RNDIS_Device_t *const RNDISInterfaceInfo,\r
+ void *Buffer,\r
+ uint16_t *const PacketLength);\r
+\r
+/**\r
+ * @brief Sends the given packet to the attached RNDIS device, after adding a RNDIS packet message header.\r
+ *\r
+ * @pre This function must only be called when the Device state machine is in the @ref DEVICE_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class configuration and state.\r
+ * @param Buffer : Pointer to a buffer where the packer data is to be read from.\r
+ * @param PacketLength : Length in bytes of the packet to send.\r
+ *\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+uint8_t RNDIS_Device_SendPacket(USB_ClassInfo_RNDIS_Device_t *const RNDISInterfaceInfo,\r
+ void *Buffer,\r
+ const uint16_t PacketLength);\r
+\r
+/* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+/* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_RNDIS_DEVICE_C)\r
+static void RNDIS_Device_ProcessRNDISControlMessage(USB_ClassInfo_RNDIS_Device_t *const RNDISInterfaceInfo)\r
+ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+static bool RNDIS_Device_ProcessNDISQuery(USB_ClassInfo_RNDIS_Device_t *const RNDISInterfaceInfo,\r
+ const uint32_t OId,\r
+ void *const QueryData,\r
+ const uint16_t QuerySize,\r
+ void *ResponseData,\r
+ uint16_t *const ResponseSize) ATTR_NON_NULL_PTR_ARG(1)\r
+ATTR_NON_NULL_PTR_ARG(5) ATTR_NON_NULL_PTR_ARG(6);\r
+\r
+static bool RNDIS_Device_ProcessNDISSet(USB_ClassInfo_RNDIS_Device_t *const RNDISInterfaceInfo,\r
+ const uint32_t OId,\r
+ const void *SetData,\r
+ const uint16_t SetSize) ATTR_NON_NULL_PTR_ARG(1)\r
+ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ #endif\r
+\r
+ #endif\r
+\r
+/* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Master include file for the library USB HID Class driver, for both host and device modes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassDrivers\r
+ * @defgroup Group_USBClassHID HID Class Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Device/HID.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/HID.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/HIDParser.c <i>(Makefile source module name: LPCUSBLIB_SRC_USB)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * HID Class Driver module. This module contains an internal implementation of the USB HID Class, for both Device\r
+ * and Host USB modes. User applications can use this class driver instead of implementing the HID class manually\r
+ * via the low-level nxpUSBlib APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Hosts or Devices using the USB HID Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _HID_CLASS_H_\r
+#define _HID_CLASS_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_USB_DRIVER\r
+ #define __INCLUDE_FROM_HID_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../Core/USBMode.h"\r
+\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ #include "Device/HIDClassDevice.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ #include "Host/HIDClassHost.h"\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Host mode driver for the library USB Audio 1.0 Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassAudio\r
+ * @defgroup Group_USBClassAudioHost Audio 1.0 Class Host Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/Audio.c <i>(Makefile source module name: LPCUSBlib_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Host Mode USB Class driver framework interface, for the Audio 1.0 USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __AUDIO_CLASS_HOST_H__\r
+#define __AUDIO_CLASS_HOST_H__\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/AudioClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_AUDIO_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Type Defines: */\r
+ /** @brief Audio Class Host Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made within the user application,\r
+ * and passed to each of the Audio class driver functions as the \c AudioInterfaceInfo parameter. This\r
+ * stores each Audio interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ struct\r
+ {\r
+ uint8_t DataINPipeNumber; /**< Pipe number of the Audio interface's IN data pipe. If this interface should not\r
+ * bind to an IN endpoint, this may be set to 0 to disable audio input streaming for\r
+ * this driver instance.\r
+ */\r
+ uint8_t DataOUTPipeNumber; /**< Pipe number of the Audio interface's OUT data pipe. If this interface should not\r
+ * bind to an OUT endpoint, this may be set to 0 to disable audio output streaming for\r
+ * this driver instance.\r
+ */\r
+ uint8_t PortNumber; /**< Port number that this interface is running. */ \r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ bool IsActive; /**< Indicates if the current interface instance is connected to an attached device, valid\r
+ * after @ref Audio_Host_ConfigurePipes() is called and the Host state machine is in the\r
+ * Configured state.\r
+ */\r
+ uint8_t ControlInterfaceNumber; /**< Interface index of the Audio Control interface within the attached device. */\r
+ uint8_t StreamingInterfaceNumber; /**< Interface index of the Audio Streaming interface within the attached device. */\r
+ \r
+ uint8_t EnabledStreamingAltIndex; /**< Alternative setting index of the Audio Streaming interface when the stream is enabled. */\r
+\r
+ uint16_t DataINPipeSize; /**< Size in bytes of the Audio interface's IN data pipe. */\r
+ uint16_t DataOUTPipeSize; /**< Size in bytes of the Audio interface's OUT data pipe. */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * <b>may</b> be set to initial values, but may also be ignored to default to sane values when\r
+ * the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_Audio_Host_t;\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible error codes returned by the @ref Audio_Host_ConfigurePipes() function. */\r
+ enum AUDIO_Host_EnumerationFailure_ErrorCodes_t\r
+ {\r
+ AUDIO_ENUMERROR_NoError = 0, /**< Configuration Descriptor was processed successfully. */\r
+ AUDIO_ENUMERROR_InvalidConfigDescriptor = 1, /**< The device returned an invalid Configuration Descriptor. */\r
+ AUDIO_ENUMERROR_NoCompatibleInterfaceFound = 2, /**< A compatible AUDIO interface was not found in the device's Configuration Descriptor. */\r
+ AUDIO_ENUMERROR_PipeConfigurationFailed = 3, /**< One or more pipes for the specified interface could not be configured correctly. */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** \r
+ * @brief Host interface configuration routine, to configure a given Audio host interface instance using the Configuration\r
+ * Descriptor read from an attached USB device. This function automatically updates the given Audio Host instance's\r
+ * state values and configures the pipes required to communicate with the interface if it is found within the\r
+ * device. This should be called once after the stack has enumerated the attached device, while the host state\r
+ * machine is in the Addressed state.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class host configuration and state.\r
+ * @param ConfigDescriptorSize : Length of the attached device's Configuration Descriptor.\r
+ * @param DeviceConfigDescriptor : Pointer to a buffer containing the attached device's Configuration Descriptor.\r
+ *\r
+ * @return A value from the @ref AUDIO_Host_EnumerationFailure_ErrorCodes_t enum.\r
+ */\r
+ uint8_t Audio_Host_ConfigurePipes(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo,\r
+ uint16_t ConfigDescriptorSize,\r
+ void* DeviceConfigDescriptor) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** \r
+ * @brief Starts or stops the audio streaming for the given configured Audio Host interface, allowing for audio samples to be\r
+ * send and/or received.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class host configuration and state.\r
+ * @param EnableStreaming : Boolean true to enable streaming of the specified interface, false to disable\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t Audio_Host_StartStopStreaming(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo,\r
+ const bool EnableStreaming) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Gets or sets the specified property of a streaming audio class endpoint that is bound to a pipe in the given\r
+ * class instance.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class host configuration and state.\r
+ * @param DataPipeIndex : Index of the data pipe whose bound endpoint is to be altered.\r
+ * @param EndpointProperty : Property of the endpoint to get or set, a value from @ref Audio_ClassRequests_t.\r
+ * @param EndpointControl : Parameter of the endpoint to get or set, a value from @ref Audio_EndpointControls_t.\r
+ * @param DataLength : For SET operations, the length of the parameter data to set. For GET operations, the maximum\r
+ * length of the retrieved data.\r
+ * @param Data : Pointer to a location where the parameter data is stored for SET operations, or where\r
+ * the retrieved data is to be stored for GET operations.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t Audio_Host_GetSetEndpointProperty(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo,\r
+ const uint8_t DataPipeIndex,\r
+ const uint8_t EndpointProperty,\r
+ const uint8_t EndpointControl,\r
+ const uint16_t DataLength,\r
+ void* const Data) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(6);\r
+\r
+ /* Inline Functions: */\r
+ /** @brief General management task for a given Audio host class interface, required for the correct operation of\r
+ * the interface. This should be called frequently in the main program loop, before the master USB management task\r
+ * @ref USB_USBTask().\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class host configuration and state.\r
+ * @return Nothing\r
+ */\r
+ static inline void Audio_Host_USBTask(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void Audio_Host_USBTask(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ {\r
+ (void)AudioInterfaceInfo;\r
+ }\r
+\r
+ /** @brief Determines if the given audio interface is ready for a sample to be read from it, and selects the streaming\r
+ * IN pipe ready for reading.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ *\r
+ * @return Boolean \c true if the given Audio interface has a sample to be read, \c false otherwise.\r
+ */\r
+ static inline bool Audio_Host_IsSampleReceived(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline bool Audio_Host_IsSampleReceived(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ {\r
+ uint8_t portnum = AudioInterfaceInfo->Config.PortNumber;\r
+ bool SampleReceived = false;\r
+\r
+ if ((USB_HostState[portnum] != HOST_STATE_Configured) || !(AudioInterfaceInfo->State.IsActive))\r
+ return false;\r
+\r
+ Pipe_SelectPipe(portnum,AudioInterfaceInfo->Config.DataINPipeNumber);\r
+ Pipe_Unfreeze();\r
+ SampleReceived = Pipe_IsINReceived(portnum);\r
+ Pipe_Freeze();\r
+\r
+ return SampleReceived;\r
+ }\r
+\r
+ /** @brief Determines if the given audio interface is ready to accept the next sample to be written to it, and selects\r
+ * the streaming OUT pipe ready for writing.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or\r
+ * the call will fail.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ *\r
+ * @return Boolean \c true if the given Audio interface is ready to accept the next sample, \c false otherwise.\r
+ */\r
+ static inline bool Audio_Host_IsReadyForNextSample(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline bool Audio_Host_IsReadyForNextSample(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ {\r
+ uint8_t portnum = AudioInterfaceInfo->Config.PortNumber;\r
+\r
+ if ((USB_HostState[portnum] != HOST_STATE_Configured) || !(AudioInterfaceInfo->State.IsActive))\r
+ return false;\r
+\r
+ Pipe_SelectPipe(portnum,AudioInterfaceInfo->Config.DataOUTPipeNumber);\r
+ return Pipe_IsOUTReady(portnum);\r
+ }\r
+\r
+ /** @brief Reads the next 8-bit audio sample from the current audio interface.\r
+ *\r
+ * @pre This should be preceded immediately by a call to the @ref Audio_Host_IsSampleReceived() function to ensure\r
+ * that the correct pipe is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ *\r
+ * @return Signed 8-bit audio sample from the audio interface.\r
+ */\r
+ static inline int8_t Audio_Host_ReadSample8(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline int8_t Audio_Host_ReadSample8(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ {\r
+ int8_t Sample;\r
+ uint8_t portnum = AudioInterfaceInfo->Config.PortNumber;\r
+\r
+ (void)AudioInterfaceInfo;\r
+\r
+ Sample = Pipe_Read_8(portnum);\r
+\r
+ if (!(Pipe_BytesInPipe(portnum)))\r
+ {\r
+ Pipe_Unfreeze();\r
+ Pipe_ClearIN(portnum);\r
+ Pipe_Freeze();\r
+ }\r
+\r
+ return Sample;\r
+ }\r
+\r
+ /** @brief Reads the next 16-bit audio sample from the current audio interface.\r
+ *\r
+ * @pre This should be preceded immediately by a call to the @ref Audio_Host_IsSampleReceived() function to ensure\r
+ * that the correct pipe is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ *\r
+ * @return Signed 16-bit audio sample from the audio interface.\r
+ */\r
+ static inline int16_t Audio_Host_ReadSample16(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline int16_t Audio_Host_ReadSample16(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ {\r
+ int16_t Sample;\r
+ uint8_t portnum = AudioInterfaceInfo->Config.PortNumber;\r
+ (void)AudioInterfaceInfo;\r
+\r
+ Sample = (int16_t)Pipe_Read_16_LE(portnum);\r
+\r
+ if (!(Pipe_BytesInPipe(portnum)))\r
+ {\r
+ Pipe_Unfreeze();\r
+ Pipe_ClearIN(portnum);\r
+ Pipe_Freeze();\r
+ }\r
+\r
+ return Sample;\r
+ }\r
+\r
+ /** @brief Reads the next 24-bit audio sample from the current audio interface.\r
+ *\r
+ * @pre This should be preceded immediately by a call to the @ref Audio_Host_IsSampleReceived() function to ensure\r
+ * that the correct pipe is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ *\r
+ * @return Signed 24-bit audio sample from the audio interface.\r
+ */\r
+ static inline int32_t Audio_Host_ReadSample24(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline int32_t Audio_Host_ReadSample24(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo)\r
+ {\r
+ int32_t Sample;\r
+ uint8_t portnum = AudioInterfaceInfo->Config.PortNumber;\r
+ (void)AudioInterfaceInfo;\r
+\r
+ Sample = (((uint32_t)Pipe_Read_8(portnum) << 16)\r
+ | Pipe_Read_16_LE(portnum));\r
+\r
+ if (!(Pipe_BytesInPipe(portnum)))\r
+ {\r
+ Pipe_Unfreeze();\r
+ Pipe_ClearIN(portnum);\r
+ Pipe_Freeze();\r
+ }\r
+\r
+ return Sample;\r
+ }\r
+\r
+ /** @brief Writes the next 8-bit audio sample to the current audio interface.\r
+ *\r
+ * @pre This should be preceded immediately by a call to the @ref Audio_Host_IsReadyForNextSample() function to\r
+ * ensure that the correct pipe is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @param Sample : Signed 8-bit audio sample.\r
+ * @return Nothing\r
+ */\r
+ static inline void Audio_Host_WriteSample8(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo,\r
+ const int8_t Sample) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void Audio_Host_WriteSample8(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo,\r
+ const int8_t Sample)\r
+ {\r
+ uint8_t portnum = AudioInterfaceInfo->Config.PortNumber;\r
+\r
+ (void)AudioInterfaceInfo;\r
+\r
+ Pipe_Write_8(portnum,Sample);\r
+\r
+ if (!(Pipe_IsReadWriteAllowed(portnum)))\r
+ {\r
+ Pipe_Unfreeze();\r
+ Pipe_ClearOUT(portnum);\r
+ Pipe_WaitUntilReady(portnum);\r
+ Pipe_Freeze();\r
+ }\r
+ }\r
+\r
+ /** @brief Writes the next 16-bit audio sample to the current audio interface.\r
+ *\r
+ * @pre This should be preceded immediately by a call to the @ref Audio_Host_IsReadyForNextSample() function to\r
+ * ensure that the correct pipe is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @param Sample : Signed 16-bit audio sample.\r
+ * @return Nothing\r
+ */\r
+ static inline void Audio_Host_WriteSample16(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo,\r
+ const int16_t Sample) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void Audio_Host_WriteSample16(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo,\r
+ const int16_t Sample)\r
+ {\r
+ uint8_t portnum = AudioInterfaceInfo->Config.PortNumber;\r
+\r
+ (void)AudioInterfaceInfo;\r
+ \r
+ Pipe_Write_16_LE(portnum,Sample);\r
+\r
+ if (!(Pipe_IsReadWriteAllowed(portnum)))\r
+ {\r
+ Pipe_Unfreeze();\r
+ Pipe_ClearOUT(portnum);\r
+ Pipe_WaitUntilReady(portnum);\r
+ Pipe_Freeze();\r
+ }\r
+ }\r
+\r
+ /** @brief Writes the next 24-bit audio sample to the current audio interface.\r
+ *\r
+ * @pre This should be preceded immediately by a call to the @ref Audio_Host_IsReadyForNextSample() function to\r
+ * ensure that the correct pipe is selected and ready for data.\r
+ *\r
+ * @param AudioInterfaceInfo : Pointer to a structure containing an Audio Class configuration and state.\r
+ * @param Sample : Signed 24-bit audio sample.\r
+ * @return Nothing\r
+ */\r
+ static inline void Audio_Host_WriteSample24(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo,\r
+ const int32_t Sample) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void Audio_Host_WriteSample24(USB_ClassInfo_Audio_Host_t* const AudioInterfaceInfo,\r
+ const int32_t Sample)\r
+ {\r
+ uint8_t portnum = AudioInterfaceInfo->Config.PortNumber;\r
+\r
+ (void)AudioInterfaceInfo;\r
+\r
+ Pipe_Write_16_LE(portnum,Sample);\r
+ Pipe_Write_8(portnum,Sample >> 16);\r
+\r
+ if (!(Pipe_IsReadWriteAllowed(portnum)))\r
+ {\r
+ Pipe_Unfreeze();\r
+ Pipe_ClearOUT(portnum);\r
+ Pipe_WaitUntilReady(portnum);\r
+ Pipe_Freeze();\r
+ }\r
+ }\r
+ \r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_AUDIO_HOST_C)\r
+ static uint8_t DCOMP_Audio_Host_NextAudioControlInterface(void* CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_Audio_Host_NextAudioStreamInterface(void* CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_Audio_Host_NextAudioInterfaceDataEndpoint(void* CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Host mode driver for the library USB CDC Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassCDC\r
+ * @defgroup Group_USBClassCDCHost CDC Class Host Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/CDC.c <i>(Makefile source module name: LPCUSBlib_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Host Mode USB Class driver framework interface, for the CDC USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __CDC_CLASS_HOST_H__\r
+#define __CDC_CLASS_HOST_H__\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/CDCClassCommon.h"\r
+\r
+ #include <stdio.h>\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_CDC_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Type Defines: */\r
+ /** @brief CDC Class Host Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made within the user application,\r
+ * and passed to each of the CDC class driver functions as the \c CDCInterfaceInfo parameter. This\r
+ * stores each CDC interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ const struct\r
+ {\r
+ uint8_t DataINPipeNumber; /**< Pipe number of the CDC interface's IN data pipe. */\r
+ bool DataINPipeDoubleBank; /**< Indicates if the CDC interface's IN data pipe should use double banking. */\r
+\r
+ uint8_t DataOUTPipeNumber; /**< Pipe number of the CDC interface's OUT data pipe. */\r
+ bool DataOUTPipeDoubleBank; /**< Indicates if the CDC interface's OUT data pipe should use double banking. */\r
+\r
+ uint8_t NotificationPipeNumber; /**< Pipe number of the CDC interface's IN notification endpoint, if used. */\r
+ bool NotificationPipeDoubleBank; /**< Indicates if the CDC interface's notification pipe should use double banking. */\r
+\r
+ uint8_t PortNumber; /**< Port number that this interface is running.\r
+ */\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ bool IsActive; /**< Indicates if the current interface instance is connected to an attached device, valid\r
+ * after @ref CDC_Host_ConfigurePipes() is called and the Host state machine is in the\r
+ * Configured state.\r
+ */\r
+ uint8_t ControlInterfaceNumber; /**< Interface index of the CDC-ACM control interface within the attached device. */\r
+\r
+ uint16_t DataINPipeSize; /**< Size in bytes of the CDC interface's IN data pipe. */\r
+ uint16_t DataOUTPipeSize; /**< Size in bytes of the CDC interface's OUT data pipe. */\r
+ uint16_t NotificationPipeSize; /**< Size in bytes of the CDC interface's IN notification pipe, if used. */\r
+\r
+ struct\r
+ {\r
+ uint8_t HostToDevice; /**< Control line states from the host to device, as a set of \c CDC_CONTROL_LINE_OUT_*\r
+ * masks - to notify the device of changes to these values, call the\r
+ * @ref CDC_Host_SendControlLineStateChange() function.\r
+ */\r
+ uint8_t DeviceToHost; /**< Control line states from the device to host, as a set of \c CDC_CONTROL_LINE_IN_*\r
+ * masks. This value is updated each time @ref CDC_Host_USBTask() is called.\r
+ */\r
+ } ControlLineStates; /**< Current states of the virtual serial port's control lines between the device and host. */\r
+\r
+ CDC_LineEncoding_t LineEncoding; /**< Line encoding used in the virtual serial port, for the device's information.\r
+ * This is generally only used if the virtual serial port data is to be\r
+ * reconstructed on a physical UART. When set by the host application, the\r
+ * @ref CDC_Host_SetLineEncoding() function must be called to push the changes\r
+ * to the device.\r
+ */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * <b>may</b> be set to initial values, but may also be ignored to default to sane values when\r
+ * the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_CDC_Host_t;\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible error codes returned by the @ref CDC_Host_ConfigurePipes() function. */\r
+ enum CDC_Host_EnumerationFailure_ErrorCodes_t\r
+ {\r
+ CDC_ENUMERROR_NoError = 0, /**< Configuration Descriptor was processed successfully. */\r
+ CDC_ENUMERROR_InvalidConfigDescriptor = 1, /**< The device returned an invalid Configuration Descriptor. */\r
+ CDC_ENUMERROR_NoCompatibleInterfaceFound = 2, /**< A compatible CDC interface was not found in the device's Configuration Descriptor. */\r
+ CDC_ENUMERROR_PipeConfigurationFailed = 3, /**< One or more pipes for the specified interface could not be configured correctly. */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** @brief General management task for a given CDC host class interface, required for the correct operation of the interface. This should\r
+ * be called frequently in the main program loop, before the master USB management task @ref USB_USBTask().\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing an CDC Class host configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void CDC_Host_USBTask(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Host interface configuration routine, to configure a given CDC host interface instance using the Configuration\r
+ * Descriptor read from an attached USB device. This function automatically updates the given CDC Host instance's\r
+ * state values and configures the pipes required to communicate with the interface if it is found within the device.\r
+ * This should be called once after the stack has enumerated the attached device, while the host state machine is in\r
+ * the Addressed state.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing an CDC Class host configuration and state.\r
+ * @param ConfigDescriptorSize : Length of the attached device's Configuration Descriptor.\r
+ * @param DeviceConfigDescriptor : Pointer to a buffer containing the attached device's Configuration Descriptor.\r
+ *\r
+ * @return A value from the @ref CDC_Host_EnumerationFailure_ErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Host_ConfigurePipes(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo,\r
+ uint16_t ConfigDescriptorSize,\r
+ void* DeviceConfigDescriptor) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Sets the line encoding for the attached device's virtual serial port. This should be called when the \c LineEncoding\r
+ * values of the interface have been changed to push the new settings to the USB device.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Host_SetLineEncoding(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Sends a Serial Control Line State Change notification to the device. This should be called when the virtual serial\r
+ * control lines (DTR, RTS, etc.) have changed states. Line states persist until they are cleared via a second\r
+ * notification. This should be called each time the CDC class driver's \c ControlLineStates.HostToDevice value is updated\r
+ * to push the new states to the USB device.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Host_SendControlLineStateChange(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Sends a Send Break request to the device. This is generally used to separate data or to indicate a special condition\r
+ * to the receiving device.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ * @param Duration : Duration of the break, in milliseconds.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Host_SendBreak(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo,\r
+ const uint8_t Duration) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Sends a given data buffer to the attached USB device, if connected. If a device is not connected when the function is\r
+ * called, the data will be discarded. Bytes will be queued for transmission to the device until either the pipe bank\r
+ * becomes full, or the @ref CDC_Host_Flush() function is called to flush the pending data to the device. This allows for\r
+ * multiple bytes to be packed into a single pipe packet, increasing data throughput.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ * @param Buffer : Pointer to a buffer containing the data to send to the device.\r
+ * @param Length : Length of the data to send to the device.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Host_SendData(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo,\r
+ const uint8_t* const Buffer,\r
+ const uint16_t Length);\r
+\r
+ /** @brief Sends a given null-terminated string to the attached USB device, if connected. If a device is not connected when the\r
+ * function is called, the string is discarded. Bytes will be queued for transmission to the device until either the pipe\r
+ * bank becomes full, or the @ref CDC_Host_Flush() function is called to flush the pending data to the device. This allows\r
+ * for multiple bytes to be packed into a single pipe packet, increasing data throughput.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ * @param String : Pointer to the null terminated string to send to the device.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Host_SendString(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo,\r
+ const char* const String) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Sends a given byte to the attached USB device, if connected. If a device is not connected when the function is called, the\r
+ * byte is discarded. Bytes will be queued for transmission to the device until either the pipe bank becomes full, or the\r
+ * @ref CDC_Host_Flush() function is called to flush the pending data to the host. This allows for multiple bytes to be\r
+ * packed into a single pipe packet, increasing data throughput.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ * @param Data : Byte of data to send to the device.\r
+ *\r
+ * @return A value from the @ref Pipe_WaitUntilReady_ErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Host_SendByte(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo,\r
+ const uint8_t Data) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Determines the number of bytes received by the CDC interface from the device, waiting to be read. This indicates the number\r
+ * of bytes in the IN pipe bank only, and thus the number of calls to @ref CDC_Host_ReceiveByte() which are guaranteed to succeed\r
+ * immediately. If multiple bytes are to be received, they should be buffered by the user application, as the pipe bank will not be\r
+ * released back to the USB controller until all bytes are read.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ *\r
+ * @return Total number of buffered bytes received from the device.\r
+ */\r
+ uint16_t CDC_Host_BytesReceived(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Reads a byte of data from the device. If no data is waiting to be read of if a USB device is not connected, the function\r
+ * returns a negative value. The @ref CDC_Host_BytesReceived() function may be queried in advance to determine how many bytes\r
+ * are currently buffered in the CDC interface's data receive pipe.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ *\r
+ * @return Next received byte from the device, or a negative value if no data received.\r
+ */\r
+ int16_t CDC_Host_ReceiveByte(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Flushes any data waiting to be sent, ensuring that the send buffer is cleared.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref Pipe_WaitUntilReady_ErrorCodes_t enum.\r
+ */\r
+ uint8_t CDC_Host_Flush(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ #if (!defined(__IAR_SYSTEMS_ICC__) || (_DLIB_FILE_DESCRIPTOR == 1))\r
+ /** @brief Creates a standard character stream for the given CDC Device instance so that it can be used with all the regular\r
+ * functions in the standard \c <stdio.h> library that accept a \c FILE stream as a destination (e.g. \c fprintf). The created\r
+ * stream is bidirectional and can be used for both input and output functions.\r
+ *\r
+ * Reading data from this stream is non-blocking, i.e. in most instances, complete strings cannot be read in by a single\r
+ * fetch, as the endpoint will not be ready at some point in the transmission, aborting the transfer. However, this may\r
+ * be used when the read data is processed byte-per-bye (via \c getc()) or when the user application will implement its own\r
+ * line buffering.\r
+ *\r
+ * @note The created stream can be given as stdout if desired to direct the standard output from all \c <stdio.h> functions\r
+ * to the given CDC interface.\r
+ * \n\n\r
+ *\r
+ * @note This function is not available on all microcontroller architectures.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @param Stream : Pointer to a FILE structure where the created stream should be placed.\r
+ * @return Nothing\r
+ */\r
+ void CDC_Host_CreateStream(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo,\r
+ FILE* const Stream);\r
+\r
+ /** @brief Identical to @ref CDC_Host_CreateStream(), except that reads are blocking until the calling stream function terminates\r
+ * the transfer. While blocking, the USB and CDC service tasks are called repeatedly to maintain USB communications.\r
+ *\r
+ * @note This function is not available on all microcontroller architectures.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class configuration and state.\r
+ * @param Stream : Pointer to a FILE structure where the created stream should be placed.\r
+ * @return Nothing\r
+ */\r
+ void CDC_Host_CreateBlockingStream(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo,\r
+ FILE* const Stream);\r
+ #endif /* IAR DLAB checking */\r
+\r
+ /** @brief CDC class driver event for a control line state change on a CDC host interface. This event fires each time the device notifies\r
+ * the host of a control line state change (containing the virtual serial control line states, such as DCD) and may be hooked in the\r
+ * user program by declaring a handler function with the same name and parameters listed here. The new control line states\r
+ * are available in the ControlLineStates.DeviceToHost value inside the CDC host interface structure passed as a parameter, set as\r
+ * a mask of \c CDC_CONTROL_LINE_IN_* masks.\r
+ *\r
+ * @param CDCInterfaceInfo : Pointer to a structure containing a CDC Class host configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void EVENT_CDC_Host_ControLineStateChanged(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_CDC_HOST_C)\r
+ #if defined(FDEV_SETUP_STREAM)\r
+ static int CDC_Host_putchar(char c,\r
+ FILE* Stream) ATTR_NON_NULL_PTR_ARG(2);\r
+ static int CDC_Host_getchar(FILE* Stream) ATTR_NON_NULL_PTR_ARG(1);\r
+ static int CDC_Host_getchar_Blocking(FILE* Stream) ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+\r
+ void CDC_Host_Event_Stub(void) ATTR_CONST;\r
+ \r
+ void EVENT_CDC_Host_ControLineStateChanged(USB_ClassInfo_CDC_Host_t* const CDCInterfaceInfo)\r
+ ATTR_WEAK ATTR_NON_NULL_PTR_ARG(1) ATTR_ALIAS(CDC_Host_Event_Stub);\r
+\r
+ static uint8_t DCOMP_CDC_Host_NextCDCControlInterface(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_CDC_Host_NextCDCDataInterface(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_CDC_Host_NextCDCInterfaceEndpoint(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Host mode driver for the library USB HID Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassHID\r
+ * @defgroup Group_USBClassHIDHost HID Class Host Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/HID.c <i>(Makefile source module name: LPCUSBlib_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Host Mode USB Class driver framework interface, for the HID USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __HID_CLASS_HOST_H__\r
+#define __HID_CLASS_HOST_H__\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/HIDClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_HID_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** Error code for some HID Host functions, indicating a logical (and not hardware) error. */\r
+ #define HID_ERROR_LOGICAL 0x80\r
+\r
+ /* Type Defines: */\r
+ /** @brief HID Class Host Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made within the user application,\r
+ * and passed to each of the HID class driver functions as the \c HIDInterfaceInfo parameter. This\r
+ * stores each HID interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ struct\r
+ {\r
+ uint8_t DataINPipeNumber; /**< Pipe number of the HID interface's IN data pipe. */\r
+ bool DataINPipeDoubleBank; /**< Indicates if the HID interface's IN data pipe should use double banking. */\r
+\r
+ uint8_t DataOUTPipeNumber; /**< Pipe number of the HID interface's OUT data pipe. */\r
+ bool DataOUTPipeDoubleBank; /**< Indicates if the HID interface's OUT data pipe should use double banking. */\r
+\r
+ uint8_t HIDInterfaceProtocol; /**< HID interface protocol value to match against if a specific\r
+ * boot subclass protocol is required, a protocol value from the\r
+ * @ref HID_Descriptor_ClassSubclassProtocol_t enum.\r
+ */\r
+ #if !defined(HID_HOST_BOOT_PROTOCOL_ONLY)\r
+ HID_ReportInfo_t* HIDParserData; /**< HID parser data to store the parsed HID report data, when boot protocol\r
+ * is not used.\r
+ *\r
+ * @note When the \c HID_HOST_BOOT_PROTOCOL_ONLY compile time token is defined,\r
+ * this method is unavailable.\r
+ */\r
+ #endif\r
+\r
+ uint8_t PortNumber; /**< Port number that this interface is running.\r
+ */\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ bool IsActive; /**< Indicates if the current interface instance is connected to an attached device, valid\r
+ * after @ref HID_Host_ConfigurePipes() is called and the Host state machine is in the\r
+ * Configured state.\r
+ */\r
+ uint8_t InterfaceNumber; /**< Interface index of the HID interface within the attached device. */\r
+\r
+ uint16_t DataINPipeSize; /**< Size in bytes of the HID interface's IN data pipe. */\r
+ uint16_t DataOUTPipeSize; /**< Size in bytes of the HID interface's OUT data pipe. */\r
+\r
+ bool SupportsBootProtocol; /**< Indicates if the current interface instance supports the HID Boot\r
+ * Protocol when enabled via @ref HID_Host_SetBootProtocol().\r
+ */\r
+ bool DeviceUsesOUTPipe; /**< Indicates if the current interface instance uses a separate OUT data pipe for\r
+ * OUT reports, or if OUT reports are sent via the control pipe instead.\r
+ */\r
+ bool UsingBootProtocol; /**< Indicates that the interface is currently initialized in Boot Protocol mode */\r
+ uint16_t HIDReportSize; /**< Size in bytes of the HID report descriptor in the device. */\r
+\r
+ uint8_t LargestReportSize; /**< Largest report the device will send, in bytes. */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * <b>may</b> be set to initial values, but may also be ignored to default to sane values when\r
+ * the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_HID_Host_t;\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible error codes returned by the @ref HID_Host_ConfigurePipes() function. */\r
+ enum HID_Host_EnumerationFailure_ErrorCodes_t\r
+ {\r
+ HID_ENUMERROR_NoError = 0, /**< Configuration Descriptor was processed successfully. */\r
+ HID_ENUMERROR_InvalidConfigDescriptor = 1, /**< The device returned an invalid Configuration Descriptor. */\r
+ HID_ENUMERROR_NoCompatibleInterfaceFound = 2, /**< A compatible HID interface was not found in the device's Configuration Descriptor. */\r
+ HID_ENUMERROR_PipeConfigurationFailed = 3, /**< One or more pipes for the specified interface could not be configured correctly. */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** @brief Host interface configuration routine, to configure a given HID host interface instance using the Configuration\r
+ * Descriptor read from an attached USB device. This function automatically updates the given HID Host instance's\r
+ * state values and configures the pipes required to communicate with the interface if it is found within the\r
+ * device. This should be called once after the stack has enumerated the attached device, while the host state\r
+ * machine is in the Addressed state.\r
+ *\r
+ * @note Once the device pipes are configured, the HID device's reporting protocol <b>must</b> be set via a call\r
+ * to either the @ref HID_Host_SetBootProtocol() or @ref HID_Host_SetReportProtocol() function.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class host configuration and state.\r
+ * @param ConfigDescriptorSize : Length of the attached device's Configuration Descriptor.\r
+ * @param DeviceConfigDescriptor : Pointer to a buffer containing the attached device's Configuration Descriptor.\r
+ *\r
+ * @return A value from the @ref HID_Host_EnumerationFailure_ErrorCodes_t enum.\r
+ */\r
+ uint8_t HID_Host_ConfigurePipes(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo,\r
+ uint16_t ConfigDescriptorSize,\r
+ void* DeviceConfigDescriptor) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+\r
+ /** @brief Receives a HID IN report from the attached HID device, when a report has been received on the HID IN Data pipe.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @note The destination buffer should be large enough to accommodate the largest report that the attached device\r
+ * can generate.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class host configuration and state.\r
+ * @param Buffer : Buffer to store the received report into.\r
+ *\r
+ * @return An error code from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t HID_Host_ReceiveReport(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo,\r
+ void* Buffer) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ #if !defined(HID_HOST_BOOT_PROTOCOL_ONLY)\r
+ /** @brief Receives a HID IN report from the attached device, by the report ID.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @note When the \c HID_HOST_BOOT_PROTOCOL_ONLY compile time token is defined, this method is unavailable.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class host configuration and state.\r
+ * @param ReportID : Report ID of the received report if ControlRequest is false, set by the to the Report ID to fetch.\r
+ * @param Buffer Buffer to store the received report into.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t HID_Host_ReceiveReportByID(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo,\r
+ const uint8_t ReportID,\r
+ void* Buffer) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+ #endif\r
+\r
+ /** @brief Sends an OUT or FEATURE report to the currently attached HID device, using the device's OUT pipe if available,\r
+ * or the device's Control pipe if not.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @note When the \c HID_HOST_BOOT_PROTOCOL_ONLY compile time token is defined, the ReportID parameter is removed\r
+ * from the parameter list of this function.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class host configuration and state.\r
+ * @param ReportID : Report ID of the report to send to the device, or 0 if the device does not use report IDs.\r
+ * @param ReportType : Type of report to issue to the device, either @ref HID_REPORT_ITEM_Out or @ref HID_REPORT_ITEM_Feature.\r
+ * @param Buffer : Buffer containing the report to send to the attached device.\r
+ * @param ReportSize : Report size in bytes to send to the attached device.\r
+ *\r
+ * @return An error code from the @ref USB_Host_SendControlErrorCodes_t enum if the DeviceUsesOUTPipe flag is set in\r
+ * the interface's state structure, a value from the @ref Pipe_Stream_RW_ErrorCodes_t enum otherwise.\r
+ */\r
+ uint8_t HID_Host_SendReportByID(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo,\r
+ #if !defined(HID_HOST_BOOT_PROTOCOL_ONLY)\r
+ const uint8_t ReportID,\r
+ #endif\r
+ const uint8_t ReportType,\r
+ void* Buffer,\r
+ const uint16_t ReportSize) ATTR_NON_NULL_PTR_ARG(1)\r
+ #if !defined(HID_HOST_BOOT_PROTOCOL_ONLY)\r
+ ATTR_NON_NULL_PTR_ARG(4);\r
+ #else\r
+ ATTR_NON_NULL_PTR_ARG(3);\r
+ #endif\r
+\r
+ /** @brief Determines if a HID IN report has been received from the attached device on the data IN pipe.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class host configuration and state.\r
+ *\r
+ * @return Boolean \c true if a report has been received, \c false otherwise.\r
+ */\r
+ bool HID_Host_IsReportReceived(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Switches the attached HID device's reporting protocol over to the Boot Report protocol mode, on supported devices.\r
+ *\r
+ * @note When the \c HID_HOST_BOOT_PROTOCOL_ONLY compile time token is defined, this method must still be called\r
+ * to explicitly place the attached device into boot protocol mode before use.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class host configuration and state.\r
+ *\r
+ * @return @ref HID_ERROR_LOGICAL if the device does not support Boot Protocol mode, a value from the\r
+ * @ref USB_Host_SendControlErrorCodes_t enum otherwise.\r
+ */\r
+ uint8_t HID_Host_SetBootProtocol(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Sets the idle period for the attached HID device to the specified interval. The HID idle period determines the rate\r
+ * at which the device should send a report, when no state changes have ocurred; i.e. on HID keyboards, this sets the\r
+ * hardware key repeat interval.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class host configuration and state.\r
+ * @param MS : Idle period as a multiple of four milliseconds, zero to disable hardware repeats\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t HID_Host_SetIdlePeriod(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo,\r
+ const uint16_t MS) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ #if !defined(HID_HOST_BOOT_PROTOCOL_ONLY)\r
+ /** @brief Switches the attached HID device's reporting protocol over to the standard Report protocol mode. This also retrieves\r
+ * and parses the device's HID report descriptor, so that the size of each report can be determined in advance.\r
+ *\r
+ * @note Whether this function is used or not, the @ref CALLBACK_HIDParser_FilterHIDReportItem() callback from the HID\r
+ * Report Parser this function references <b>must</b> be implemented in the user code.\r
+ * \n\n\r
+ *\r
+ * @note When the \c HID_HOST_BOOT_PROTOCOL_ONLY compile time token is defined, this method is unavailable.\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum if an error occurs while retrieving the HID\r
+ * Report descriptor or the setting of the Report protocol, @ref HID_ERROR_LOGICAL if the HID interface does\r
+ * not have a valid @ref HID_ReportInfo_t structure set in its configuration, a mask of @ref HID_ERROR_LOGICAL\r
+ * and a value from the @ref HID_Parse_ErrorCodes_t otherwise.\r
+ */\r
+ uint8_t HID_Host_SetReportProtocol(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+\r
+ /* Inline Functions: */\r
+ /** @brief General management task for a given Human Interface Class host class interface, required for the correct operation of\r
+ * the interface. This should be called frequently in the main program loop, before the master USB management task\r
+ * @ref USB_USBTask().\r
+ *\r
+ * @param HIDInterfaceInfo : Pointer to a structure containing a HID Class host configuration and state.\r
+ * @return Nothing\r
+ */\r
+ static inline void HID_Host_USBTask(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+ static inline void HID_Host_USBTask(USB_ClassInfo_HID_Host_t* const HIDInterfaceInfo)\r
+ {\r
+ (void)HIDInterfaceInfo;\r
+ }\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_HID_HOST_C)\r
+ static uint8_t DCOMP_HID_Host_NextHIDInterface(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_HID_Host_NextHIDDescriptor(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_HID_Host_NextHIDInterfaceEndpoint(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Host mode driver for the library USB MIDI Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassMIDI\r
+ * @defgroup Group_USBClassMIDIHost MIDI Class Host Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/MIDI.c <i>(Makefile source module name: LPCUSBlib_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Host Mode USB Class driver framework interface, for the MIDI USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __MIDI_CLASS_HOST_H__\r
+#define __MIDI_CLASS_HOST_H__\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/MIDIClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_MIDI_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Type Defines: */\r
+ /** @brief MIDI Class Host Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made within the user application,\r
+ * and passed to each of the MIDI class driver functions as the \c MIDIInterfaceInfo parameter. This\r
+ * stores each MIDI interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ const struct\r
+ {\r
+ uint8_t DataINPipeNumber; /**< Pipe number of the MIDI interface's streaming IN data pipe. */\r
+ bool DataINPipeDoubleBank; /**< Indicates if the MIDI interface's IN data pipe should use double banking. */\r
+\r
+ uint8_t DataOUTPipeNumber; /**< Pipe number of the MIDI interface's streaming OUT data pipe. */\r
+ bool DataOUTPipeDoubleBank; /**< Indicates if the MIDI interface's OUT data pipe should use double banking. */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.\r
+ */\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ bool IsActive; /**< Indicates if the current interface instance is connected to an attached device, valid\r
+ * after @ref MIDI_Host_ConfigurePipes() is called and the Host state machine is in the\r
+ * Configured state.\r
+ */\r
+ uint8_t InterfaceNumber; /**< Interface index of the MIDI interface within the attached device. */\r
+\r
+ uint16_t DataINPipeSize; /**< Size in bytes of the MIDI Streaming Data interface's IN data pipe. */\r
+ uint16_t DataOUTPipeSize; /**< Size in bytes of the MIDI Streaming Data interface's OUT data pipe. */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * <b>may</b> be set to initial values, but may also be ignored to default to sane values when\r
+ * the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_MIDI_Host_t;\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible error codes returned by the @ref MIDI_Host_ConfigurePipes() function. */\r
+ enum MIDI_Host_EnumerationFailure_ErrorCodes_t\r
+ {\r
+ MIDI_ENUMERROR_NoError = 0, /**< Configuration Descriptor was processed successfully. */\r
+ MIDI_ENUMERROR_InvalidConfigDescriptor = 1, /**< The device returned an invalid Configuration Descriptor. */\r
+ MIDI_ENUMERROR_NoCompatibleInterfaceFound = 2, /**< A compatible MIDI interface was not found in the device's Configuration Descriptor. */\r
+ MIDI_ENUMERROR_PipeConfigurationFailed = 3, /**< One or more pipes for the specified interface could not be configured correctly. */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** @brief Host interface configuration routine, to configure a given MIDI host interface instance using the Configuration\r
+ * Descriptor read from an attached USB device. This function automatically updates the given MIDI Host instance's\r
+ * state values and configures the pipes required to communicate with the interface if it is found within the device.\r
+ * This should be called once after the stack has enumerated the attached device, while the host state machine is in\r
+ * the Addressed state.\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing an MIDI Class host configuration and state.\r
+ * @param ConfigDescriptorSize : Length of the attached device's Configuration Descriptor.\r
+ * @param DeviceConfigDescriptor : Pointer to a buffer containing the attached device's Configuration Descriptor.\r
+ *\r
+ * @return A value from the @ref MIDI_Host_EnumerationFailure_ErrorCodes_t enum.\r
+ */\r
+ uint8_t MIDI_Host_ConfigurePipes(USB_ClassInfo_MIDI_Host_t* const MIDIInterfaceInfo,\r
+ uint16_t ConfigDescriptorSize,\r
+ void* DeviceConfigDescriptor) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief General management task for a given MIDI host class interface, required for the correct operation of the interface. This should\r
+ * be called frequently in the main program loop, before the master USB management task @ref USB_USBTask().\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing an MIDI Class host configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void MIDI_Host_USBTask(USB_ClassInfo_MIDI_Host_t* const MIDIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Sends a MIDI event packet to the device. If no device is connected, the event packet is discarded.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing a MIDI Class configuration and state.\r
+ * @param Event : Pointer to a populated USB_MIDI_EventPacket_t structure containing the MIDI event to send.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t MIDI_Host_SendEventPacket(USB_ClassInfo_MIDI_Host_t* const MIDIInterfaceInfo,\r
+ MIDI_EventPacket_t* const Event) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Flushes the MIDI send buffer, sending any queued MIDI events to the device. This should be called to override the\r
+ * @ref MIDI_Host_SendEventPacket() function's packing behaviour, to flush queued events. Events are queued into the\r
+ * pipe bank until either the pipe bank is full, or @ref MIDI_Host_Flush() is called. This allows for multiple MIDI\r
+ * events to be packed into a single pipe packet, increasing data throughput.\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing a MIDI Class configuration and state.\r
+ *\r
+ * @return A value from the @ref Pipe_WaitUntilReady_ErrorCodes_t enum.\r
+ */\r
+ uint8_t MIDI_Host_Flush(USB_ClassInfo_MIDI_Host_t* const MIDIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Receives a MIDI event packet from the device.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MIDIInterfaceInfo : Pointer to a structure containing a MIDI Class configuration and state.\r
+ * @param Event : Pointer to a USB_MIDI_EventPacket_t structure where the received MIDI event is to be placed.\r
+ *\r
+ * @return Boolean \c true if a MIDI event packet was received, \c false otherwise.\r
+ */\r
+ bool MIDI_Host_ReceiveEventPacket(USB_ClassInfo_MIDI_Host_t* const MIDIInterfaceInfo,\r
+ MIDI_EventPacket_t* const Event) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_MIDI_HOST_C)\r
+ static uint8_t DCOMP_MIDI_Host_NextMIDIStreamingInterface(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_MIDI_Host_NextMIDIStreamingDataEndpoint(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Host mode driver for the library USB Mass Storage Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassMS\r
+ * @defgroup Group_USBClassMassStorageHost Mass Storage Class Host Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/MassStorage.c <i>(Makefile source module name: LPCUSBlib_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Host Mode USB Class driver framework interface, for the Mass Storage USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __MS_CLASS_HOST_H__\r
+#define __MS_CLASS_HOST_H__\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/MassStorageClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_MS_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** Error code for some Mass Storage Host functions, indicating a logical (and not hardware) error. */\r
+ #define MS_ERROR_LOGICAL_CMD_FAILED 0x80\r
+\r
+ /* Type Defines: */\r
+ /** @brief Mass Storage Class Host Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made within the user application,\r
+ * and passed to each of the Mass Storage class driver functions as the \c MSInterfaceInfo parameter. This\r
+ * stores each Mass Storage interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ struct\r
+ {\r
+ uint8_t DataINPipeNumber; /**< Pipe number of the Mass Storage interface's IN data pipe. */\r
+ bool DataINPipeDoubleBank; /**< Indicates if the Mass Storage interface's IN data pipe should use double banking. */\r
+\r
+ uint8_t DataOUTPipeNumber; /**< Pipe number of the Mass Storage interface's OUT data pipe. */\r
+ bool DataOUTPipeDoubleBank; /**< Indicates if the Mass Storage interface's OUT data pipe should use double banking. */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.\r
+ */\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ bool IsActive; /**< Indicates if the current interface instance is connected to an attached device, valid\r
+ * after @ref MS_Host_ConfigurePipes() is called and the Host state machine is in the\r
+ * Configured state.\r
+ */\r
+ uint8_t InterfaceNumber; /**< Interface index of the Mass Storage interface within the attached device. */\r
+\r
+ uint16_t DataINPipeSize; /**< Size in bytes of the Mass Storage interface's IN data pipe. */\r
+ uint16_t DataOUTPipeSize; /**< Size in bytes of the Mass Storage interface's OUT data pipe. */\r
+\r
+ uint32_t TransactionTag; /**< Current transaction tag for data synchronizing of packets. */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * <b>may</b> be set to initial values, but may also be ignored to default to sane values when\r
+ * the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_MS_Host_t;\r
+\r
+ /** @brief SCSI Device LUN Capacity Structure.\r
+ *\r
+ * SCSI capacity structure, to hold the total capacity of the device in both the number\r
+ * of blocks in the current LUN, and the size of each block. This structure is filled by\r
+ * the device when the @ref MS_Host_ReadDeviceCapacity() function is called.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t Blocks; /**< Number of blocks in the addressed LUN of the device. */\r
+ uint32_t BlockSize; /**< Number of bytes in each block in the addressed LUN. */\r
+ } SCSI_Capacity_t;\r
+\r
+ /* Enums: */\r
+ enum MS_Host_EnumerationFailure_ErrorCodes_t\r
+ {\r
+ MS_ENUMERROR_NoError = 0, /**< Configuration Descriptor was processed successfully. */\r
+ MS_ENUMERROR_InvalidConfigDescriptor = 1, /**< The device returned an invalid Configuration Descriptor. */\r
+ MS_ENUMERROR_NoCompatibleInterfaceFound = 2, /**< A compatible Mass Storage interface was not found in the device's Configuration Descriptor. */\r
+ MS_ENUMERROR_PipeConfigurationFailed = 3, /**< One or more pipes for the specified interface could not be configured correctly. */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** @brief Host interface configuration routine, to configure a given Mass Storage host interface instance using the\r
+ * Configuration Descriptor read from an attached USB device. This function automatically updates the given Mass\r
+ * Storage Host instance's state values and configures the pipes required to communicate with the interface if it\r
+ * is found within the device. This should be called once after the stack has enumerated the attached device, while\r
+ * the host state machine is in the Addressed state.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing an MS Class host configuration and state.\r
+ * @param ConfigDescriptorSize : Length of the attached device's Configuration Descriptor.\r
+ * @param ConfigDescriptorData : Pointer to a buffer containing the attached device's Configuration Descriptor.\r
+ *\r
+ * @return A value from the @ref MS_Host_EnumerationFailure_ErrorCodes_t enum.\r
+ */\r
+ uint8_t MS_Host_ConfigurePipes(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ uint16_t ConfigDescriptorSize,\r
+ void* ConfigDescriptorData) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Sends a MASS STORAGE RESET control request to the attached device, resetting the Mass Storage Interface\r
+ * and readying it for the next Mass Storage command. This should be called after a failed SCSI request to \r
+ * ensure the attached Mass Storage device is ready to receive the next command.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a MS Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t MS_Host_ResetMSInterface(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Sends a GET MAX LUN control request to the attached device, retrieving the index of the highest LUN (Logical\r
+ * UNit, a logical drive) in the device. This value can then be used in the other functions of the Mass Storage\r
+ * Host mode Class driver to address a specific LUN within the device.\r
+ *\r
+ * @note Some devices do not support this request, and will STALL it when issued. To get around this,\r
+ * on unsupported devices the max LUN index will be reported as zero and no error will be returned\r
+ * if the device STALLs the request.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a MS Class host configuration and state.\r
+ * @param MaxLUNIndex : Pointer to a location where the highest LUN index value should be stored.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t MS_Host_GetMaxLUN(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ uint8_t* const MaxLUNIndex) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Retrieves the Mass Storage device's inquiry data for the specified LUN, indicating the device characteristics and\r
+ * properties.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a MS Class host configuration and state.\r
+ * @param LUNIndex : LUN index within the device the command is being issued to.\r
+ * @param InquiryData : Location where the read inquiry data should be stored.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum or @ref MS_ERROR_LOGICAL_CMD_FAILED.\r
+ */\r
+ uint8_t MS_Host_GetInquiryData(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ const uint8_t LUNIndex,\r
+ SCSI_Inquiry_Response_t* const InquiryData) ATTR_NON_NULL_PTR_ARG(1)\r
+ ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Sends a TEST UNIT READY command to the device, to determine if it is ready to accept other SCSI commands.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a MS Class host configuration and state.\r
+ * @param LUNIndex : LUN index within the device the command is being issued to.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum or @ref MS_ERROR_LOGICAL_CMD_FAILED if not ready.\r
+ */\r
+ uint8_t MS_Host_TestUnitReady(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ const uint8_t LUNIndex) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Retrieves the total capacity of the attached USB Mass Storage device, in blocks, and block size.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a MS Class host configuration and state.\r
+ * @param LUNIndex : LUN index within the device the command is being issued to.\r
+ * @param DeviceCapacity : Pointer to the location where the capacity information should be stored.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum or @ref MS_ERROR_LOGICAL_CMD_FAILED if not ready.\r
+ */\r
+ uint8_t MS_Host_ReadDeviceCapacity(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ const uint8_t LUNIndex,\r
+ SCSI_Capacity_t* const DeviceCapacity) ATTR_NON_NULL_PTR_ARG(1)\r
+ ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Retrieves the device sense data, indicating the current device state and error codes for the previously\r
+ * issued command.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a MS Class host configuration and state.\r
+ * @param LUNIndex : LUN index within the device the command is being issued to.\r
+ * @param SenseData : Pointer to the location where the sense information should be stored.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum or @ref MS_ERROR_LOGICAL_CMD_FAILED if not ready.\r
+ */\r
+ uint8_t MS_Host_RequestSense(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ const uint8_t LUNIndex,\r
+ SCSI_Request_Sense_Response_t* const SenseData) ATTR_NON_NULL_PTR_ARG(1)\r
+ ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Issues a PREVENT MEDIUM REMOVAL command, to logically (or, depending on the type of device, physically) lock\r
+ * the device from removal so that blocks of data on the medium can be read or altered.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a MS Class host configuration and state.\r
+ * @param LUNIndex : LUN index within the device the command is being issued to.\r
+ * @param PreventRemoval : Boolean \c true if the device should be locked from removal, \c false otherwise.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum or @ref MS_ERROR_LOGICAL_CMD_FAILED if not ready.\r
+ */\r
+ uint8_t MS_Host_PreventAllowMediumRemoval(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ const uint8_t LUNIndex,\r
+ const bool PreventRemoval) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Reads blocks of data from the attached Mass Storage device's medium.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a MS Class host configuration and state.\r
+ * @param LUNIndex : LUN index within the device the command is being issued to.\r
+ * @param BlockAddress : Starting block address within the device to read from.\r
+ * @param Blocks : Total number of blocks to read.\r
+ * @param BlockSize : Size in bytes of each block within the device.\r
+ * @param BlockBuffer : Pointer to where the read data from the device should be stored.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum or @ref MS_ERROR_LOGICAL_CMD_FAILED if not ready.\r
+ */\r
+ uint8_t MS_Host_ReadDeviceBlocks(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ const uint8_t LUNIndex,\r
+ const uint32_t BlockAddress,\r
+ const uint8_t Blocks,\r
+ const uint16_t BlockSize,\r
+ void* BlockBuffer) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(6);\r
+\r
+ /** @brief Writes blocks of data to the attached Mass Storage device's medium.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing a MS Class host configuration and state.\r
+ * @param LUNIndex : LUN index within the device the command is being issued to.\r
+ * @param BlockAddress : Starting block address within the device to write to.\r
+ * @param Blocks : Total number of blocks to read.\r
+ * @param BlockSize : Size in bytes of each block within the device.\r
+ * @param BlockBuffer : Pointer to where the data to write should be sourced from.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum or @ref MS_ERROR_LOGICAL_CMD_FAILED if not ready.\r
+ */\r
+ uint8_t MS_Host_WriteDeviceBlocks(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ const uint8_t LUNIndex,\r
+ const uint32_t BlockAddress,\r
+ const uint8_t Blocks,\r
+ const uint16_t BlockSize,\r
+ const void* BlockBuffer) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(6);\r
+\r
+ /* Inline Functions: */\r
+ /** @brief General management task for a given Mass Storage host class interface, required for the correct operation of\r
+ * the interface. This should be called frequently in the main program loop, before the master USB management task\r
+ * @ref USB_USBTask().\r
+ *\r
+ * @param MSInterfaceInfo : Pointer to a structure containing an Mass Storage Class host configuration and state.\r
+ * @return Nothing\r
+ */\r
+ static inline void MS_Host_USBTask(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void MS_Host_USBTask(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo)\r
+ {\r
+ (void)MSInterfaceInfo;\r
+ }\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Macros: */\r
+ #define MS_COMMAND_DATA_TIMEOUT_MS 10000\r
+\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_MASSSTORAGE_HOST_C)\r
+ static uint8_t MS_Host_SendCommand(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ MS_CommandBlockWrapper_t* const SCSICommandBlock,\r
+ const void* const BufferPtr) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+ static uint8_t MS_Host_WaitForDataReceived(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t MS_Host_SendReceiveData(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ MS_CommandBlockWrapper_t* const SCSICommandBlock,\r
+ void* BufferPtr) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+ static uint8_t MS_Host_GetReturnedStatus(USB_ClassInfo_MS_Host_t* const MSInterfaceInfo,\r
+ MS_CommandStatusWrapper_t* const SCSICommandStatus)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ static uint8_t DCOMP_MS_Host_NextMSInterface(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_MS_Host_NextMSInterfaceEndpoint(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Host mode driver for the library USB Printer Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassPrinter\r
+ * @defgroup Group_USBClassPrinterHost Printer Class Host Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/Printer.c <i>(Makefile source module name: LPCUSBlib_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Host Mode USB Class driver framework interface, for the Printer USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __PRINTER_CLASS_HOST_H__\r
+#define __PRINTER_CLASS_HOST_H__\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/PrinterClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_PRINTER_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Type Defines: */\r
+ /** @brief Printer Class Host Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made within the user application,\r
+ * and passed to each of the Printer class driver functions as the \c PRNTInterfaceInfo parameter. This\r
+ * stores each Printer interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ const struct\r
+ {\r
+ uint8_t DataINPipeNumber; /**< Pipe number of the Printer interface's IN data pipe. */\r
+ bool DataINPipeDoubleBank; /**< Indicates if the Printer interface's IN data pipe should use double banking. */\r
+\r
+ uint8_t DataOUTPipeNumber; /**< Pipe number of the Printer interface's OUT data pipe. */\r
+ bool DataOUTPipeDoubleBank; /**< Indicates if the Printer interface's OUT data pipe should use double banking. */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.\r
+ */\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ bool IsActive; /**< Indicates if the current interface instance is connected to an attached device, valid\r
+ * after @ref PRNT_Host_ConfigurePipes() is called and the Host state machine is in the\r
+ * Configured state.\r
+ */\r
+ uint8_t InterfaceNumber; /**< Interface index of the Printer interface within the attached device. */\r
+ uint8_t AlternateSetting; /**< Alternate setting within the Printer Interface in the attached device. */\r
+\r
+ uint16_t DataINPipeSize; /**< Size in bytes of the Printer interface's IN data pipe. */\r
+ uint16_t DataOUTPipeSize; /**< Size in bytes of the Printer interface's OUT data pipe. */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * <b>may</b> be set to initial values, but may also be ignored to default to sane values when\r
+ * the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_PRNT_Host_t;\r
+\r
+ /* Enums: */\r
+ enum PRNT_Host_EnumerationFailure_ErrorCodes_t\r
+ {\r
+ PRNT_ENUMERROR_NoError = 0, /**< Configuration Descriptor was processed successfully. */\r
+ PRNT_ENUMERROR_InvalidConfigDescriptor = 1, /**< The device returned an invalid Configuration Descriptor. */\r
+ PRNT_ENUMERROR_NoCompatibleInterfaceFound = 2, /**< A compatible Printer interface was not found in the device's Configuration Descriptor. */\r
+ PRNT_ENUMERROR_PipeConfigurationFailed = 3, /**< One or more pipes for the specified interface could not be configured correctly. */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** @brief Host interface configuration routine, to configure a given Printer host interface instance using the\r
+ * Configuration Descriptor read from an attached USB device. This function automatically updates the given Printer\r
+ * instance's state values and configures the pipes required to communicate with the interface if it is found within\r
+ * the device. This should be called once after the stack has enumerated the attached device, while the host state\r
+ * machine is in the Addressed state.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ * @param ConfigDescriptorSize : Length of the attached device's Configuration Descriptor.\r
+ * @param DeviceConfigDescriptor : Pointer to a buffer containing the attached device's Configuration Descriptor.\r
+ *\r
+ * @return A value from the @ref PRNT_Host_EnumerationFailure_ErrorCodes_t enum.\r
+ */\r
+ uint8_t PRNT_Host_ConfigurePipes(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo,\r
+ uint16_t ConfigDescriptorSize,\r
+ void* DeviceConfigDescriptor) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief General management task for a given Printer host class interface, required for the correct operation of\r
+ * the interface. This should be called frequently in the main program loop, before the master USB management task\r
+ * @ref USB_USBTask().\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ * @return Nothing\r
+ */\r
+ void PRNT_Host_USBTask(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Configures the printer to enable Bidirectional mode, if it is not already in this mode. This should be called\r
+ * once the connected device's configuration has been set, to ensure the printer is ready to accept commands.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t PRNT_Host_SetBidirectionalMode(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Retrieves the status of the virtual Printer port's inbound status lines. The result can then be masked against the\r
+ * \c PRNT_PORTSTATUS_* macros to determine the printer port's status.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ * @param PortStatus : Location where the retrieved port status should be stored.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t PRNT_Host_GetPortStatus(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo,\r
+ uint8_t* const PortStatus)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Soft-resets the attached printer, readying it for new commands.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum.\r
+ */\r
+ uint8_t PRNT_Host_SoftReset(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Flushes any data waiting to be sent, ensuring that the send buffer is cleared.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref Pipe_WaitUntilReady_ErrorCodes_t enum.\r
+ */\r
+ uint8_t PRNT_Host_Flush(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Sends the given null terminated string to the attached printer's input endpoint.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ * @param String : Pointer to a null terminated string to send.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t PRNT_Host_SendString(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo,\r
+ void* String) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Sends the given raw data stream to the attached printer's input endpoint. This should contain commands that the\r
+ * printer is able to understand - for example, PCL data. Not all printers accept all printer languages; see\r
+ * @ref PRNT_Host_GetDeviceID() for details on determining acceptable languages for an attached printer.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ * @param Buffer : Pointer to a buffer containing the raw command stream to send to the printer.\r
+ * @param Length : Size in bytes of the command stream to be sent.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t PRNT_Host_SendData(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo,\r
+ void* Buffer,\r
+ const uint16_t Length) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Sends a given byte to the attached USB device, if connected. If a device is not connected when the function is called, the\r
+ * byte is discarded. Bytes will be queued for transmission to the device until either the pipe bank becomes full, or the\r
+ * @ref PRNT_Host_Flush() function is called to flush the pending data to the host. This allows for multiple bytes to be\r
+ * packed into a single pipe packet, increasing data throughput.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ * @param Data : Byte of data to send to the device.\r
+ *\r
+ * @return A value from the @ref Pipe_WaitUntilReady_ErrorCodes_t enum.\r
+ */\r
+ uint8_t PRNT_Host_SendByte(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo,\r
+ const uint8_t Data) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Determines the number of bytes received by the printer interface from the device, waiting to be read. This indicates the number\r
+ * of bytes in the IN pipe bank only, and thus the number of calls to @ref PRNT_Host_ReceiveByte() which are guaranteed to succeed\r
+ * immediately. If multiple bytes are to be received, they should be buffered by the user application, as the pipe bank will not be\r
+ * released back to the USB controller until all bytes are read.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ *\r
+ * @return Total number of buffered bytes received from the device.\r
+ */\r
+ uint16_t PRNT_Host_BytesReceived(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo);\r
+\r
+ /** @brief Reads a byte of data from the device. If no data is waiting to be read of if a USB device is not connected, the function\r
+ * returns a negative value. The @ref PRNT_Host_BytesReceived() function may be queried in advance to determine how many bytes\r
+ * are currently buffered in the Printer interface's data receive pipe.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ *\r
+ * @return Next received byte from the device, or a negative value if no data received.\r
+ */\r
+ int16_t PRNT_Host_ReceiveByte(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo);\r
+\r
+ /** @brief Retrieves the attached printer device's ID string, formatted according to IEEE 1284. This string is sent as a\r
+ * Unicode string from the device and is automatically converted to an ASCII encoded C string by this function, thus\r
+ * the maximum reportable string length is two less than the size given (to accommodate the Unicode string length\r
+ * bytes which are removed).\r
+ *\r
+ * This string, when supported, contains the model, manufacturer and acceptable printer languages for the attached device.\r
+ *\r
+ * @param PRNTInterfaceInfo : Pointer to a structure containing a Printer Class host configuration and state.\r
+ * @param DeviceIDString : Pointer to a buffer where the Device ID string should be stored, in ASCII format.\r
+ * @param BufferSize : Size in bytes of the buffer allocated for the Device ID string.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t PRNT_Host_GetDeviceID(USB_ClassInfo_PRNT_Host_t* const PRNTInterfaceInfo,\r
+ char* const DeviceIDString,\r
+ const uint16_t BufferSize) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_PRINTER_HOST_C)\r
+ static uint8_t DCOMP_PRNT_Host_NextPRNTInterface(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_PRNT_Host_NextPRNTInterfaceEndpoint(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Host mode driver for the library USB RNDIS Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassRNDIS\r
+ * @defgroup Group_USBClassRNDISHost RNDIS Class Host Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/RNDIS.c <i>(Makefile source module name: LPCUSBlib_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Host Mode USB Class driver framework interface, for the Microsoft RNDIS Ethernet\r
+ * USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __RNDIS_CLASS_HOST_H__\r
+#define __RNDIS_CLASS_HOST_H__\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/RNDISClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_RNDIS_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Type Defines: */\r
+ /** @brief RNDIS Class Host Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made within the user application,\r
+ * and passed to each of the RNDIS class driver functions as the \c RNDISInterfaceInfo parameter. This\r
+ * stores each RNDIS interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ const struct\r
+ {\r
+ uint8_t DataINPipeNumber; /**< Pipe number of the RNDIS interface's IN data pipe. */\r
+ bool DataINPipeDoubleBank; /**< Indicates if the RNDIS interface's IN data pipe should use double banking. */\r
+\r
+ uint8_t DataOUTPipeNumber; /**< Pipe number of the RNDIS interface's OUT data pipe. */\r
+ bool DataOUTPipeDoubleBank; /**< Indicates if the RNDIS interface's OUT data pipe should use double banking. */\r
+\r
+ uint8_t NotificationPipeNumber; /**< Pipe number of the RNDIS interface's IN notification endpoint, if used. */\r
+ bool NotificationPipeDoubleBank; /**< Indicates if the RNDIS interface's notification pipe should use double banking. */\r
+\r
+ uint32_t HostMaxPacketSize; /**< Maximum size of a packet which can be buffered by the host. */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.\r
+ */\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ bool IsActive; /**< Indicates if the current interface instance is connected to an attached device, valid\r
+ * after @ref RNDIS_Host_ConfigurePipes() is called and the Host state machine is in the\r
+ * Configured state.\r
+ */\r
+ uint8_t ControlInterfaceNumber; /**< Interface index of the RNDIS control interface within the attached device. */\r
+\r
+ uint16_t DataINPipeSize; /**< Size in bytes of the RNDIS interface's IN data pipe. */\r
+ uint16_t DataOUTPipeSize; /**< Size in bytes of the RNDIS interface's OUT data pipe. */\r
+ uint16_t NotificationPipeSize; /**< Size in bytes of the RNDIS interface's IN notification pipe, if used. */\r
+\r
+ uint32_t DeviceMaxPacketSize; /**< Maximum size of a packet which can be buffered by the attached RNDIS device. */\r
+\r
+ uint32_t RequestID; /**< Request ID counter to give a unique ID for each command/response pair. */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * <b>may</b> be set to initial values, but may also be ignored to default to sane values when\r
+ * the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_RNDIS_Host_t;\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible error codes returned by the @ref RNDIS_Host_ConfigurePipes() function. */\r
+ enum RNDIS_Host_EnumerationFailure_ErrorCodes_t\r
+ {\r
+ RNDIS_ENUMERROR_NoError = 0, /**< Configuration Descriptor was processed successfully. */\r
+ RNDIS_ENUMERROR_InvalidConfigDescriptor = 1, /**< The device returned an invalid Configuration Descriptor. */\r
+ RNDIS_ENUMERROR_NoCompatibleInterfaceFound = 2, /**< A compatible RNDIS interface was not found in the device's Configuration Descriptor. */\r
+ RNDIS_ENUMERROR_PipeConfigurationFailed = 3, /**< One or more pipes for the specified interface could not be configured correctly. */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** @brief Host interface configuration routine, to configure a given RNDIS host interface instance using the Configuration\r
+ * Descriptor read from an attached USB device. This function automatically updates the given RNDIS Host instance's\r
+ * state values and configures the pipes required to communicate with the interface if it is found within the device.\r
+ * This should be called once after the stack has enumerated the attached device, while the host state machine is in\r
+ * the Addressed state.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class host configuration and state.\r
+ * @param ConfigDescriptorSize : Length of the attached device's Configuration Descriptor.\r
+ * @param DeviceConfigDescriptor : Pointer to a buffer containing the attached device's Configuration Descriptor.\r
+ *\r
+ * @return A value from the @ref RNDIS_Host_EnumerationFailure_ErrorCodes_t enum.\r
+ */\r
+ uint8_t RNDIS_Host_ConfigurePipes(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo,\r
+ uint16_t ConfigDescriptorSize,\r
+ void* DeviceConfigDescriptor) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Sends a RNDIS KEEPALIVE command to the device, to ensure that it does not enter standby mode after periods\r
+ * of long inactivity.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum or @ref RNDIS_ERROR_LOGICAL_CMD_FAILED if the device returned a\r
+ * logical command failure.\r
+ */\r
+ uint8_t RNDIS_Host_SendKeepAlive(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Initializes the attached RNDIS device's RNDIS interface. This should be called after the device's pipes have been\r
+ * configured via the call to @ref RNDIS_Host_ConfigurePipes().\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum or @ref RNDIS_ERROR_LOGICAL_CMD_FAILED if the\r
+ * device returned a logical command failure.\r
+ */\r
+ uint8_t RNDIS_Host_InitializeDevice(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Sets a given RNDIS property of an attached RNDIS device.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class host configuration and state.\r
+ * @param Oid : OID number of the parameter to set.\r
+ * @param Buffer : Pointer to where the property data is to be sourced from.\r
+ * @param Length : Length in bytes of the property data to sent to the device.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum or @ref RNDIS_ERROR_LOGICAL_CMD_FAILED if the\r
+ * device returned a logical command failure.\r
+ */\r
+ uint8_t RNDIS_Host_SetRNDISProperty(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo,\r
+ const uint32_t Oid,\r
+ void* Buffer,\r
+ const uint16_t Length) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Gets a given RNDIS property of an attached RNDIS device.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class host configuration and state.\r
+ * @param Oid : OID number of the parameter to get.\r
+ * @param Buffer : Pointer to where the property data is to be written to.\r
+ * @param MaxLength : Length in bytes of the destination buffer size.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum or @ref RNDIS_ERROR_LOGICAL_CMD_FAILED if the\r
+ * device returned a logical command failure.\r
+ */\r
+ uint8_t RNDIS_Host_QueryRNDISProperty(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo,\r
+ const uint32_t Oid,\r
+ void* Buffer,\r
+ const uint16_t MaxLength) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Determines if a packet is currently waiting for the host to read in and process.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class host configuration and state.\r
+ *\r
+ * @return Boolean \c true if a packet is waiting to be read in by the host, \c false otherwise.\r
+ */\r
+ bool RNDIS_Host_IsPacketReceived(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Retrieves the next pending packet from the device, discarding the remainder of the RNDIS packet header to leave\r
+ * only the packet contents for processing by the host in the nominated buffer.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class host configuration and state.\r
+ * @param Buffer : Pointer to a buffer where the packer data is to be written to.\r
+ * @param PacketLength : Pointer to where the length in bytes of the read packet is to be stored.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t RNDIS_Host_ReadPacket(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo,\r
+ void* Buffer,\r
+ uint16_t* const PacketLength) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2)\r
+ ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Sends the given packet to the attached RNDIS device, after adding a RNDIS packet message header.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class host configuration and state.\r
+ * @param Buffer : Pointer to a buffer where the packer data is to be read from.\r
+ * @param PacketLength : Length in bytes of the packet to send.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t RNDIS_Host_SendPacket(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo,\r
+ void* Buffer,\r
+ const uint16_t PacketLength) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /* Inline Functions: */\r
+ /** @brief General management task for a given RNDIS host class interface, required for the correct operation of the interface. This should\r
+ * be called frequently in the main program loop, before the master USB management task @ref USB_USBTask().\r
+ *\r
+ * @param RNDISInterfaceInfo : Pointer to a structure containing an RNDIS Class host configuration and state.\r
+ * @return Nothing\r
+ */\r
+ static inline void RNDIS_Host_USBTask(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void RNDIS_Host_USBTask(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo)\r
+ {\r
+ (void)RNDISInterfaceInfo;\r
+ }\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_RNDIS_HOST_C)\r
+ static uint8_t RNDIS_SendEncapsulatedCommand(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo,\r
+ void* Buffer,\r
+ const uint16_t Length) ATTR_NON_NULL_PTR_ARG(1)\r
+ ATTR_NON_NULL_PTR_ARG(2);\r
+ static uint8_t RNDIS_GetEncapsulatedResponse(USB_ClassInfo_RNDIS_Host_t* const RNDISInterfaceInfo,\r
+ void* Buffer,\r
+ const uint16_t Length) ATTR_NON_NULL_PTR_ARG(1)\r
+ ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ static uint8_t DCOMP_RNDIS_Host_NextRNDISControlInterface(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_RNDIS_Host_NextRNDISDataInterface(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_RNDIS_Host_NextRNDISInterfaceEndpoint(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Host mode driver for the library USB Still Image Class driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassSI\r
+ * @defgroup Group_USBClassStillImageHost Still Image Class Host Mode Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/StillImage.c <i>(Makefile source module name: LPCUSBlib_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Host Mode USB Class driver framework interface, for the Still Image USB Class driver.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __SI_CLASS_HOST_H__\r
+#define __SI_CLASS_HOST_H__\r
+\r
+ /* Includes: */\r
+ #include "../../USB.h"\r
+ #include "../Common/StillImageClassCommon.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_SI_DRIVER)\r
+ #error Do not include this file directly. Include LPCUSBlib/Drivers/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** Error code for some Still Image Host functions, indicating a logical (and not hardware) error. */\r
+ #define SI_ERROR_LOGICAL_CMD_FAILED 0x80\r
+\r
+ /* Type Defines: */\r
+ /** @brief Still Image Class Host Mode Configuration and State Structure.\r
+ *\r
+ * Class state structure. An instance of this structure should be made within the user application,\r
+ * and passed to each of the Still Image class driver functions as the \c SIInterfaceInfo parameter. This\r
+ * stores each Still Image interface's configuration and state information.\r
+ */\r
+ typedef struct\r
+ {\r
+ const struct\r
+ {\r
+ uint8_t DataINPipeNumber; /**< Pipe number of the Still Image interface's IN data pipe. */\r
+ bool DataINPipeDoubleBank; /**< Indicates if the Still Image interface's IN data pipe should use double banking. */\r
+\r
+ uint8_t DataOUTPipeNumber; /**< Pipe number of the Still Image interface's OUT data pipe. */\r
+ bool DataOUTPipeDoubleBank; /**< Indicates if the Still Image interface's OUT data pipe should use double banking. */\r
+\r
+ uint8_t EventsPipeNumber; /**< Pipe number of the Still Image interface's IN events endpoint, if used. */\r
+ bool EventsPipeDoubleBank; /**< Indicates if the Still Image interface's events data pipe should use double banking. */\r
+ uint8_t PortNumber; /**< Port number that this interface is running.\r
+ */\r
+ } Config; /**< Config data for the USB class interface within the device. All elements in this section\r
+ * <b>must</b> be set or the interface will fail to enumerate and operate correctly.\r
+ */\r
+ struct\r
+ {\r
+ bool IsActive; /**< Indicates if the current interface instance is connected to an attached device, valid\r
+ * after @ref SI_Host_ConfigurePipes() is called and the Host state machine is in the\r
+ * Configured state.\r
+ */\r
+ uint8_t InterfaceNumber; /**< Interface index of the Still Image interface within the attached device. */\r
+\r
+ uint16_t DataINPipeSize; /**< Size in bytes of the Still Image interface's IN data pipe. */\r
+ uint16_t DataOUTPipeSize; /**< Size in bytes of the Still Image interface's OUT data pipe. */\r
+ uint16_t EventsPipeSize; /**< Size in bytes of the Still Image interface's IN events pipe. */\r
+\r
+ bool IsSessionOpen; /**< Indicates if a PIMA session is currently open with the attached device. */\r
+ uint32_t TransactionID; /**< Transaction ID for the next transaction to send to the device. */\r
+ } State; /**< State data for the USB class interface within the device. All elements in this section\r
+ * <b>may</b> be set to initial values, but may also be ignored to default to sane values when\r
+ * the interface is enumerated.\r
+ */\r
+ } USB_ClassInfo_SI_Host_t;\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible error codes returned by the @ref SI_Host_ConfigurePipes() function. */\r
+ enum SI_Host_EnumerationFailure_ErrorCodes_t\r
+ {\r
+ SI_ENUMERROR_NoError = 0, /**< Configuration Descriptor was processed successfully. */\r
+ SI_ENUMERROR_InvalidConfigDescriptor = 1, /**< The device returned an invalid Configuration Descriptor. */\r
+ SI_ENUMERROR_NoCompatibleInterfaceFound = 2, /**< A compatible Still Image interface was not found in the device's\r
+ * Configuration Descriptor.\r
+ */\r
+ SI_ENUMERROR_PipeConfigurationFailed = 3, /**< One or more pipes for the specified interface could not be configured correctly. */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** @brief Host interface configuration routine, to configure a given Still Image host interface instance using the\r
+ * Configuration Descriptor read from an attached USB device. This function automatically updates the given Still\r
+ * Image Host instance's state values and configures the pipes required to communicate with the interface if it is\r
+ * found within the device. This should be called once after the stack has enumerated the attached device, while\r
+ * the host state machine is in the Addressed state.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ * @param ConfigDescriptorSize : Length of the attached device's Configuration Descriptor.\r
+ * @param ConfigDescriptorData : Pointer to a buffer containing the attached device's Configuration Descriptor.\r
+ *\r
+ * @return A value from the @ref SI_Host_EnumerationFailure_ErrorCodes_t enum.\r
+ */\r
+ uint8_t SI_Host_ConfigurePipes(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo,\r
+ uint16_t ConfigDescriptorSize,\r
+ void* ConfigDescriptorData) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Opens a new PIMA session with the attached device. This should be used before any session-orientated PIMA commands\r
+ * are issued to the device. Only one session can be open at the one time.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum, or @ref SI_ERROR_LOGICAL_CMD_FAILED if the device\r
+ * returned a logical command failure.\r
+ */\r
+ uint8_t SI_Host_OpenSession(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Closes an already opened PIMA session with the attached device. This should be used after all session-orientated\r
+ * PIMA commands have been issued to the device.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum, or @ref SI_ERROR_LOGICAL_CMD_FAILED if the device\r
+ * returned a logical command failure.\r
+ */\r
+ uint8_t SI_Host_CloseSession(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Sends a raw PIMA block header to the device, filling out the transaction ID automatically. This can be used to send\r
+ * arbitrary PIMA blocks to the device with or without parameters.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ * @param PIMAHeader : Pointer to a PIMA container structure that is to be sent.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t SI_Host_SendBlockHeader(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo,\r
+ PIMA_Container_t* const PIMAHeader) ATTR_NON_NULL_PTR_ARG(1)\r
+ ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Receives a raw PIMA block header from the device. This can be used to receive arbitrary PIMA blocks from the device with\r
+ * or without parameters.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ * @param PIMAHeader : Pointer to a PIMA container structure where the received block is to be stored.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t SI_Host_ReceiveBlockHeader(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo,\r
+ PIMA_Container_t* const PIMAHeader) ATTR_NON_NULL_PTR_ARG(1)\r
+ ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Sends a given PIMA command to the attached device, filling out the PIMA command header's Transaction ID automatically.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ * @param Operation : PIMA operation code to issue to the device.\r
+ * @param TotalParams : Total number of 32-bit parameters to send to the device in the issued command block.\r
+ * @param Params : Pointer to an array of 32-bit values containing the parameters to send in the command block.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum, or @ref SI_ERROR_LOGICAL_CMD_FAILED if the device\r
+ * returned a logical command failure.\r
+ */\r
+ uint8_t SI_Host_SendCommand(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo,\r
+ const uint16_t Operation,\r
+ const uint8_t TotalParams,\r
+ uint32_t* const Params) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Receives and checks a response block from the attached Still Image device, once a command has been issued and all data\r
+ * associated with the command has been transferred.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum, or @ref SI_ERROR_LOGICAL_CMD_FAILED if the device\r
+ * returned a logical command failure.\r
+ */\r
+ uint8_t SI_Host_ReceiveResponse(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Indicates if the device has issued a PIMA event block to the host via the asynchronous events pipe.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ *\r
+ * @return Boolean \c true if an event is waiting to be read, \c false otherwise.\r
+ */\r
+ bool SI_Host_IsEventReceived(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /** @brief Receives an asynchronous event block from the device via the asynchronous events pipe.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ * @param PIMAHeader : Pointer to a PIMA container structure where the event should be stored.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum, or @ref SI_ERROR_LOGICAL_CMD_FAILED if the device\r
+ * returned a logical command failure.\r
+ */\r
+ uint8_t SI_Host_ReceiveEventHeader(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo,\r
+ PIMA_Container_t* const PIMAHeader) ATTR_NON_NULL_PTR_ARG(1)\r
+ ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Sends arbitrary data to the attached device, for use in the data phase of PIMA commands which require data\r
+ * transfer beyond the regular PIMA command block parameters.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ * @param Buffer : Pointer to a buffer where the data to send has been stored.\r
+ * @param Bytes : Length in bytes of the data in the buffer to send to the attached device.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t SI_Host_SendData(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo,\r
+ void* Buffer,\r
+ const uint16_t Bytes) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Receives arbitrary data from the attached device, for use in the data phase of PIMA commands which require data\r
+ * transfer beyond the regular PIMA command block parameters.\r
+ *\r
+ * @pre This function must only be called when the Host state machine is in the @ref HOST_STATE_Configured state or the\r
+ * call will fail.\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ * @param Buffer : Pointer to a buffer where the received data is to be stored.\r
+ * @param Bytes : Length in bytes of the data to read.\r
+ *\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum.\r
+ */\r
+ uint8_t SI_Host_ReadData(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo,\r
+ void* Buffer,\r
+ const uint16_t Bytes) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /* Inline Functions: */\r
+ /** @brief General management task for a given Still Image host class interface, required for the correct operation of the\r
+ * interface. This should be called frequently in the main program loop, before the master USB management task\r
+ * @ref USB_USBTask().\r
+ *\r
+ * @param SIInterfaceInfo : Pointer to a structure containing a Still Image Class host configuration and state.\r
+ * @return Nothing\r
+ */\r
+ static inline void SI_Host_USBTask(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;\r
+ static inline void SI_Host_USBTask(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo)\r
+ {\r
+ (void)SIInterfaceInfo;\r
+ }\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Macros: */\r
+ #define SI_COMMAND_DATA_TIMEOUT_MS 10000\r
+\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_STILLIMAGE_HOST_C)\r
+ static uint8_t DCOMP_SI_Host_NextSIInterface(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ static uint8_t DCOMP_SI_Host_NextSIInterfaceEndpoint(void* const CurrentDescriptor)\r
+ ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(1);\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Master include file for the library USB MIDI Class driver, for both host and device modes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassDrivers\r
+ * @defgroup Group_USBClassMIDI MIDI Class Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Device/MIDI.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/MIDI.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * MIDI Class Driver module. This module contains an internal implementation of the USB MIDI Class, for both Device\r
+ * and Host USB modes. User applications can use this class driver instead of implementing the MIDI class manually\r
+ * via the low-level nxpUSBlib APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Hosts or Devices using the USB MIDI Class.\r
+ *\r
+ * @note The USB MIDI class is actually a special case of the regular Audio class, thus this module depends on\r
+ * structure definitions from the @ref Group_USBClassAudioDevice class driver module.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _MIDI_CLASS_H_\r
+#define _MIDI_CLASS_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_USB_DRIVER\r
+ #define __INCLUDE_FROM_MIDI_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../Core/USBMode.h"\r
+\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ #include "Device/MIDIClassDevice.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ #include "Host/MIDIClassHost.h"\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Master include file for the library USB Mass Storage Class driver, for both host and device modes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassDrivers\r
+ * @defgroup Group_USBClassMS Mass Storage Class Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Device/MassStorage.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/MassStorage.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Mass Storage Class Driver module. This module contains an internal implementation of the USB Mass Storage Class, for both\r
+ * Device and Host USB modes. User applications can use this class driver instead of implementing the Mass Storage class\r
+ * manually via the low-level nxpUSBlib APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Hosts or Devices using the USB Mass Storage Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _MS_CLASS_H_\r
+#define _MS_CLASS_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_USB_DRIVER\r
+ #define __INCLUDE_FROM_MS_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../Core/USBMode.h"\r
+\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ #include "Device/MassStorageClassDevice.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ #include "Host/MassStorageClassHost.h"\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Master include file for the library USB Printer Class driver, for both host and device modes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassDrivers\r
+ * @defgroup Group_USBClassPrinter Printer Class Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/Printer.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Printer Class Driver module. This module contains an internal implementation of the USB Printer Class, for the base\r
+ * USB Printer transport layer for USB Host mode only. Note that printers are free to implement whatever printer language\r
+ * they choose on top of this (e.g. Postscript), and so this driver exposes low level data transport functions only rather\r
+ * than high level raster or text functions. User applications can use this class driver instead of implementing the Printer\r
+ * class manually via the low-level nxpUSBlib APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB Printer Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _PRINTER_CLASS_H_\r
+#define _PRINTER_CLASS_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_USB_DRIVER\r
+ #define __INCLUDE_FROM_PRINTER_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../Core/USBMode.h"\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ #include "Host/PrinterClassHost.h"\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Master include file for the library USB RNDIS Class driver, for both host and device modes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassDrivers\r
+ * @defgroup Group_USBClassRNDIS RNDIS (Networking) Class Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Device/RNDIS.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/RNDIS.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * RNDIS Class Driver module. This module contains an internal implementation of the Microsoft USB RNDIS Networking\r
+ * Class, for both Device and Host USB modes. User applications can use this class driver instead of implementing the\r
+ * RNDIS class manually via the low-level nxpUSBlib APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Hosts using the USB RNDIS Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _RNDIS_CLASS_H_\r
+#define _RNDIS_CLASS_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_USB_DRIVER\r
+ #define __INCLUDE_FROM_RNDIS_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../Core/USBMode.h"\r
+\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ #include "Device/RNDISClassDevice.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ #include "Host/RNDISClassHost.h"\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Master include file for the library USB Still Image Class driver, for both host and device modes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USBClassDrivers\r
+ * @defgroup Group_USBClassSI Still Image Class Driver\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Class/Host/StillImage.c <i>(Makefile source module name: LPCUSBLIB_SRC_USBCLASS)</i>\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Still Image Class Driver module. This module contains an internal implementation of the USB Still Image Class,\r
+ * for USB Host mode only. User applications can use this class driver instead of implementing the Still Image class\r
+ * manually via the low-level nxpUSBlib APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB Still Image Class.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef _SI_CLASS_H_\r
+#define _SI_CLASS_H_\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_USB_DRIVER\r
+ #define __INCLUDE_FROM_SI_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../Core/USBMode.h"\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ #include "Host/StillImageClassHost.h"\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Configuration Descriptor definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "ConfigDescriptor.h"\r
+\r
+#if defined(USB_CAN_BE_HOST)\r
+uint8_t USB_Host_GetDeviceConfigDescriptor(const uint8_t corenum,\r
+ const uint8_t ConfigNumber,\r
+ uint16_t* const ConfigSizePtr,\r
+ void* const BufferPtr,\r
+ const uint16_t BufferSize)\r
+{\r
+ uint8_t ErrorCode;\r
+ uint8_t ConfigHeader[sizeof(USB_Descriptor_Configuration_Header_t)];\r
+ USB_Descriptor_Configuration_Header_t *pCfgHeader = (USB_Descriptor_Configuration_Header_t*)ConfigHeader;\r
+\r
+ USB_ControlRequest = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE),\r
+ .bRequest = REQ_GetDescriptor,\r
+ .wValue = ((DTYPE_Configuration << 8) | (ConfigNumber - 1)),\r
+ .wIndex = 0,\r
+ .wLength = sizeof(USB_Descriptor_Configuration_Header_t),\r
+ };\r
+\r
+ Pipe_SelectPipe(corenum,PIPE_CONTROLPIPE);\r
+\r
+ if ((ErrorCode = USB_Host_SendControlRequest(corenum,ConfigHeader)) != HOST_SENDCONTROL_Successful)\r
+ return ErrorCode;\r
+\r
+ *ConfigSizePtr = le16_to_cpu(pCfgHeader->TotalConfigurationSize);\r
+\r
+ if (*ConfigSizePtr > BufferSize)\r
+ return HOST_GETCONFIG_BuffOverflow;\r
+\r
+ USB_ControlRequest.wLength = *ConfigSizePtr;\r
+\r
+ if ((ErrorCode = USB_Host_SendControlRequest(corenum,BufferPtr)) != HOST_SENDCONTROL_Successful)\r
+ return ErrorCode;\r
+\r
+ if (DESCRIPTOR_TYPE(BufferPtr) != DTYPE_Configuration)\r
+ return HOST_GETCONFIG_InvalidData;\r
+\r
+ return HOST_GETCONFIG_Successful;\r
+}\r
+#endif\r
+\r
+void USB_GetNextDescriptorOfType(uint16_t* const BytesRem,\r
+ void** const CurrConfigLoc,\r
+ const uint8_t Type)\r
+{\r
+ while (*BytesRem)\r
+ {\r
+ USB_GetNextDescriptor(BytesRem, CurrConfigLoc);\r
+\r
+ if (DESCRIPTOR_TYPE(*CurrConfigLoc) == Type)\r
+ return;\r
+ }\r
+}\r
+\r
+void USB_GetNextDescriptorOfTypeBefore(uint16_t* const BytesRem,\r
+ void** const CurrConfigLoc,\r
+ const uint8_t Type,\r
+ const uint8_t BeforeType)\r
+{\r
+ while (*BytesRem)\r
+ {\r
+ USB_GetNextDescriptor(BytesRem, CurrConfigLoc);\r
+\r
+ if (DESCRIPTOR_TYPE(*CurrConfigLoc) == Type)\r
+ {\r
+ return;\r
+ }\r
+ else if (DESCRIPTOR_TYPE(*CurrConfigLoc) == BeforeType)\r
+ {\r
+ *BytesRem = 0;\r
+ return;\r
+ }\r
+ }\r
+}\r
+\r
+void USB_GetNextDescriptorOfTypeAfter(uint16_t* const BytesRem,\r
+ void** const CurrConfigLoc,\r
+ const uint8_t Type,\r
+ const uint8_t AfterType)\r
+{\r
+ USB_GetNextDescriptorOfType(BytesRem, CurrConfigLoc, AfterType);\r
+\r
+ if (*BytesRem)\r
+ USB_GetNextDescriptorOfType(BytesRem, CurrConfigLoc, Type);\r
+}\r
+\r
+uint8_t USB_GetNextDescriptorComp(uint16_t* const BytesRem,\r
+ void** const CurrConfigLoc,\r
+ ConfigComparatorPtr_t const ComparatorRoutine)\r
+{\r
+ uint8_t ErrorCode;\r
+\r
+ while (*BytesRem)\r
+ {\r
+ uint8_t* PrevDescLoc = *CurrConfigLoc;\r
+ uint16_t PrevBytesRem = *BytesRem;\r
+\r
+ USB_GetNextDescriptor(BytesRem, CurrConfigLoc);\r
+\r
+ if ((ErrorCode = ComparatorRoutine(*CurrConfigLoc)) != DESCRIPTOR_SEARCH_NotFound)\r
+ {\r
+ if (ErrorCode == DESCRIPTOR_SEARCH_Fail)\r
+ {\r
+ *CurrConfigLoc = PrevDescLoc;\r
+ *BytesRem = PrevBytesRem;\r
+ }\r
+\r
+ return ErrorCode;\r
+ }\r
+ }\r
+\r
+ return DESCRIPTOR_SEARCH_COMP_EndOfDescriptor;\r
+}\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Configuration Descriptor definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_ConfigDescriptorParser Configuration Descriptor Parser\r
+ * @brief USB Configuration Descriptor definitions.\r
+ *\r
+ * This section of the library gives a friendly API which can be used in host applications to easily\r
+ * parse an attached device's configuration descriptor so that endpoint, interface and other descriptor\r
+ * data can be extracted and used as needed.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __CONFIGDESCRIPTOR_H__\r
+#define __CONFIGDESCRIPTOR_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h" \r
+ #include "HostStandardReq.h"\r
+ #include "StdDescriptors.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** Casts a pointer to a descriptor inside the configuration descriptor into a pointer to the given\r
+ * descriptor type.\r
+ *\r
+ * Usage Example:\r
+ * \code\r
+ * uint8_t* CurrDescriptor = &ConfigDescriptor[0]; // Pointing to the configuration header\r
+ * USB_Descriptor_Configuration_Header_t* ConfigHeaderPtr = DESCRIPTOR_PCAST(CurrDescriptor,\r
+ * USB_Descriptor_Configuration_Header_t);\r
+ *\r
+ * // Can now access elements of the configuration header struct using the -> indirection operator\r
+ * \endcode\r
+ */\r
+ #define DESCRIPTOR_PCAST(DescriptorPtr, Type) ((Type*)(DescriptorPtr))\r
+\r
+ /** Casts a pointer to a descriptor inside the configuration descriptor into the given descriptor\r
+ * type (as an actual struct instance rather than a pointer to a struct).\r
+ *\r
+ * Usage Example:\r
+ * \code\r
+ * uint8_t* CurrDescriptor = &ConfigDescriptor[0]; // Pointing to the configuration header\r
+ * USB_Descriptor_Configuration_Header_t ConfigHeader = DESCRIPTOR_CAST(CurrDescriptor,\r
+ * USB_Descriptor_Configuration_Header_t);\r
+ *\r
+ * // Can now access elements of the configuration header struct using the . operator\r
+ * \endcode\r
+ */\r
+ #define DESCRIPTOR_CAST(DescriptorPtr, Type) (*DESCRIPTOR_PCAST(DescriptorPtr, Type))\r
+\r
+ /** Returns the descriptor's type, expressed as the 8-bit type value in the header of the descriptor.\r
+ * This value's meaning depends on the descriptor's placement in the descriptor, but standard type\r
+ * values can be accessed in the @ref USB_DescriptorTypes_t enum.\r
+ */\r
+ #define DESCRIPTOR_TYPE(DescriptorPtr) DESCRIPTOR_PCAST(DescriptorPtr, USB_Descriptor_Header_t)->Type\r
+\r
+ /** Returns the descriptor's size, expressed as the 8-bit value indicating the number of bytes. */\r
+ #define DESCRIPTOR_SIZE(DescriptorPtr) DESCRIPTOR_PCAST(DescriptorPtr, USB_Descriptor_Header_t)->Size\r
+\r
+ /* Type Defines: */\r
+ /** Type define for a Configuration Descriptor comparator function (function taking a pointer to an array\r
+ * of type void, returning a uint8_t value).\r
+ *\r
+ * \see @ref USB_GetNextDescriptorComp function for more details.\r
+ */\r
+ typedef uint8_t (* ConfigComparatorPtr_t)(void*);\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible return codes of the @ref USB_Host_GetDeviceConfigDescriptor() function. */\r
+ enum USB_Host_GetConfigDescriptor_ErrorCodes_t\r
+ {\r
+ HOST_GETCONFIG_Successful = 0, /**< No error occurred while retrieving the configuration descriptor. */\r
+ HOST_GETCONFIG_DeviceDisconnect = 1, /**< The attached device was disconnected while retrieving the configuration\r
+ * descriptor.\r
+ */\r
+ HOST_GETCONFIG_PipeError = 2, /**< An error occurred in the pipe while sending the request. */\r
+ HOST_GETCONFIG_SetupStalled = 3, /**< The attached device stalled the request to retrieve the configuration\r
+ * descriptor.\r
+ */\r
+ HOST_GETCONFIG_SoftwareTimeOut = 4, /**< The request or data transfer timed out. */\r
+ HOST_GETCONFIG_BuffOverflow = 5, /**< The device's configuration descriptor is too large to fit into the allocated\r
+ * buffer.\r
+ */\r
+ HOST_GETCONFIG_InvalidData = 6, /**< The device returned invalid configuration descriptor data. */\r
+ };\r
+\r
+ /** Enum for return values of a descriptor comparator function. */\r
+ enum DSearch_Return_ErrorCodes_t\r
+ {\r
+ DESCRIPTOR_SEARCH_Found = 0, /**< Current descriptor matches comparator criteria. */\r
+ DESCRIPTOR_SEARCH_Fail = 1, /**< No further descriptor could possibly match criteria, fail the search. */\r
+ DESCRIPTOR_SEARCH_NotFound = 2, /**< Current descriptor does not match comparator criteria. */\r
+ };\r
+\r
+ /** Enum for return values of @ref USB_GetNextDescriptorComp(). */\r
+ enum DSearch_Comp_Return_ErrorCodes_t\r
+ {\r
+ DESCRIPTOR_SEARCH_COMP_Found = 0, /**< Configuration descriptor now points to descriptor which matches\r
+ * search criteria of the given comparator function. */\r
+ DESCRIPTOR_SEARCH_COMP_Fail = 1, /**< Comparator function returned @ref DESCRIPTOR_SEARCH_Fail. */\r
+ DESCRIPTOR_SEARCH_COMP_EndOfDescriptor = 2, /**< End of configuration descriptor reached before match found. */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** @brief Retrieves the configuration descriptor data from an attached device via a standard request into a buffer,\r
+ * including validity and size checking to prevent a buffer overflow.\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param ConfigNumber : Device configuration descriptor number to fetch from the device (usually set to 1 for\r
+ * single configuration devices).\r
+ * @param ConfigSizePtr : Pointer to a location for storing the retrieved configuration descriptor size.\r
+ * @param BufferPtr : Pointer to the buffer for storing the configuration descriptor data.\r
+ * @param BufferSize : Size of the allocated buffer where the configuration descriptor is to be stored.\r
+ *\r
+ * @return A value from the @ref USB_Host_GetConfigDescriptor_ErrorCodes_t enum.\r
+ */\r
+ uint8_t USB_Host_GetDeviceConfigDescriptor(const uint8_t corenum,\r
+ const uint8_t ConfigNumber,\r
+ uint16_t* const ConfigSizePtr,\r
+ void* const BufferPtr,\r
+ const uint16_t BufferSize) ATTR_NON_NULL_PTR_ARG(3) ATTR_NON_NULL_PTR_ARG(4);\r
+\r
+ /** @brief Skips to the next sub-descriptor inside the configuration descriptor of the specified type value.\r
+ * The bytes remaining value is automatically decremented.\r
+ *\r
+ * @param BytesRem : Pointer to the number of bytes remaining of the configuration descriptor.\r
+ * @param CurrConfigLoc : Pointer to the current descriptor inside the configuration descriptor.\r
+ * @param Type : Descriptor type value to search for.\r
+ * @return Nothing\r
+ */\r
+ void USB_GetNextDescriptorOfType(uint16_t* const BytesRem,\r
+ void** const CurrConfigLoc,\r
+ const uint8_t Type)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Skips to the next sub-descriptor inside the configuration descriptor of the specified type value,\r
+ * which must come before a descriptor of the second given type value. If the BeforeType type\r
+ * descriptor is reached first, the number of bytes remaining to process is set to zero and the\r
+ * function exits. The bytes remaining value is automatically decremented.\r
+ *\r
+ * @param BytesRem : Pointer to the number of bytes remaining of the configuration descriptor.\r
+ * @param CurrConfigLoc : Pointer to the current descriptor inside the configuration descriptor.\r
+ * @param Type : Descriptor type value to search for.\r
+ * @param BeforeType : Descriptor type value which must not be reached before the given Type descriptor.\r
+ * @return Nothing\r
+ */\r
+ void USB_GetNextDescriptorOfTypeBefore(uint16_t* const BytesRem,\r
+ void** const CurrConfigLoc,\r
+ const uint8_t Type,\r
+ const uint8_t BeforeType)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Skips to the next sub-descriptor inside the configuration descriptor of the specified type value,\r
+ * which must come after a descriptor of the second given type value. The bytes remaining value is\r
+ * automatically decremented.\r
+ *\r
+ * @param BytesRem : Pointer to the number of bytes remaining of the configuration descriptor.\r
+ * @param CurrConfigLoc : Pointer to the current descriptor inside the configuration descriptor.\r
+ * @param Type : Descriptor type value to search for.\r
+ * @param AfterType : Descriptor type value which must be reached before the given Type descriptor.\r
+ * @return Nothing\r
+ */\r
+ void USB_GetNextDescriptorOfTypeAfter(uint16_t* const BytesRem,\r
+ void** const CurrConfigLoc,\r
+ const uint8_t Type,\r
+ const uint8_t AfterType)\r
+ ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Searches for the next descriptor in the given configuration descriptor using a pre-made comparator\r
+ * function. The routine updates the position and remaining configuration descriptor bytes values\r
+ * automatically. If a comparator routine fails a search, the descriptor pointer is retreated back\r
+ * so that the next descriptor search invocation will start from the descriptor which first caused the\r
+ * original search to fail. This behaviour allows for one comparator to be used immediately after another\r
+ * has failed, starting the second search from the descriptor which failed the first.\r
+ *\r
+ * Comparator functions should be standard functions which accept a pointer to the header of the current\r
+ * descriptor inside the configuration descriptor which is being compared, and should return a value from\r
+ * the @ref DSearch_Return_ErrorCodes_t enum as a uint8_t value.\r
+ *\r
+ * @note This function is available in USB Host mode only.\r
+ *\r
+ * @param BytesRem : Pointer to an int storing the remaining bytes in the configuration descriptor.\r
+ * @param CurrConfigLoc : Pointer to the current position in the configuration descriptor.\r
+ * @param ComparatorRoutine : Name of the comparator search function to use on the configuration descriptor.\r
+ *\r
+ * @return Value of one of the members of the @ref DSearch_Comp_Return_ErrorCodes_t enum.\r
+ *\r
+ * Usage Example:\r
+ * \code\r
+ * uint8_t EndpointSearcher(void* CurrentDescriptor); // Comparator Prototype\r
+ *\r
+ * uint8_t EndpointSearcher(void* CurrentDescriptor)\r
+ * {\r
+ * if (DESCRIPTOR_TYPE(CurrentDescriptor) == DTYPE_Endpoint)\r
+ * return DESCRIPTOR_SEARCH_Found;\r
+ * else\r
+ * return DESCRIPTOR_SEARCH_NotFound;\r
+ * }\r
+ *\r
+ * //...\r
+ * // After retrieving configuration descriptor:\r
+ * if (USB_Host_GetNextDescriptorComp(&BytesRemaining, &CurrentConfigLoc, EndpointSearcher) ==\r
+ * Descriptor_Search_Comp_Found)\r
+ * {\r
+ * // Do something with the endpoint descriptor\r
+ * }\r
+ * \endcode\r
+ */\r
+ uint8_t USB_GetNextDescriptorComp(uint16_t* const BytesRem,\r
+ void** const CurrConfigLoc,\r
+ ConfigComparatorPtr_t const ComparatorRoutine);\r
+\r
+ /* Inline Functions: */\r
+ /** @brief Skips over the current sub-descriptor inside the configuration descriptor, so that the pointer then\r
+ points to the next sub-descriptor. The bytes remaining value is automatically decremented.\r
+ *\r
+ * @param BytesRem : Pointer to the number of bytes remaining of the configuration descriptor.\r
+ * @param CurrConfigLoc : Pointer to the current descriptor inside the configuration descriptor.\r
+ */\r
+ static inline void USB_GetNextDescriptor(uint16_t* const BytesRem,\r
+ void** CurrConfigLoc) ATTR_NON_NULL_PTR_ARG(1) ATTR_NON_NULL_PTR_ARG(2);\r
+ static inline void USB_GetNextDescriptor(uint16_t* const BytesRem,\r
+ void** CurrConfigLoc)\r
+ {\r
+ uint16_t CurrDescriptorSize = DESCRIPTOR_CAST(*CurrConfigLoc, USB_Descriptor_Header_t).Size;\r
+ \r
+ if (*BytesRem < CurrDescriptorSize)\r
+ CurrDescriptorSize = *BytesRem;\r
+\r
+ *CurrConfigLoc = (void*)((uintptr_t)*CurrConfigLoc + CurrDescriptorSize);\r
+ *BytesRem -= CurrDescriptorSize;\r
+ }\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Declare common macros, variables that can be shared between\r
+ * DCD (Endpoint_LPCxxxx, Device_LPCxxxx) and (Endpoint_LPC, EndpointStream_LPC)\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_EndpointManagement\r
+ * @defgroup Group_EndpointCommon Endpoint Buffer for Writing and Reading\r
+ * @brief Endpoint Buffer for Writing and Reading.\r
+ *\r
+ * @{\r
+ */\r
+ \r
+#ifndef __ENDPOINT_COMMON_H__\r
+#define __ENDPOINT_COMMON_H__\r
+\r
+/* Includes: */\r
+#include "../HAL/HAL.h"\r
+\r
+/* Macros: */\r
+/** Size of share memory buffer that a device uses to communicate with host. */\r
+#define USB_DATA_BUFFER_TEM_LENGTH 512\r
+\r
+/* Global Variables: */\r
+/** Share memory buffer. */\r
+/* Control EP buffer */\r
+extern uint8_t usb_data_buffer[][USB_DATA_BUFFER_TEM_LENGTH];\r
+/* Non-Control EP IN buffer */\r
+extern uint8_t usb_data_buffer_IN[][USB_DATA_BUFFER_TEM_LENGTH];\r
+/* Non-Control EP OUT buffer */\r
+extern uint8_t usb_data_buffer_OUT[][USB_DATA_BUFFER_TEM_LENGTH];\r
+/* Control EP buffer size */\r
+extern volatile int32_t usb_data_buffer_size[];\r
+/* Non-Control EP OUT buffer index */\r
+extern volatile uint32_t usb_data_buffer_OUT_size[];\r
+/** Indexer rolling along the share memory buffer. Used to determine the offset\r
+ * of next read/write activities on share memory buffer or the total amount of data\r
+ * ready to be sent.\r
+ */\r
+extern volatile uint32_t usb_data_buffer_index[];\r
+extern volatile uint32_t usb_data_buffer_IN_index[];\r
+extern volatile uint32_t usb_data_buffer_OUT_index[];\r
+/** Store the current selected endpoint number, always the logical endpint number.\r
+ * Usually used as index of endpointhandle array.\r
+ */\r
+extern uint8_t endpointselected[];\r
+/** Array to store the physical endpoint number or the actual endpoint number that need\r
+ * to be configured for any USB transactions.\r
+ */\r
+extern uint8_t endpointhandle0[];\r
+extern uint8_t endpointhandle1[];\r
+\r
+#define endpointhandle(corenum) ((corenum) ? endpointhandle1 : endpointhandle0)\r
+#endif /* __ENDPOINT_COMMON_H__ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * @brief USB Device definitions for the LPC11Uxx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_Device\r
+ * @defgroup Group_Device_LPC11Uxx Device Management (LPC11Uxx, LPC1347)\r
+ * @brief USB Device definitions for the LPC1347 and LPC11Uxx microcontrollers.\r
+ *\r
+ * Architecture specific USB Device definitions for the LPC microcontrollers.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __USBDEVICE_LPC11UXX_H__\r
+#define __USBDEVICE_LPC11UXX_H__\r
+\r
+ #include "../../../../../Common/Common.h"\r
+ #include "../../USBController.h"\r
+ #include "../../StdDescriptors.h"\r
+ #include "../../USBInterrupt.h"\r
+ #include "../../Endpoint.h"\r
+ #include "../../HAL/HAL.h"\r
+\r
+ #if defined(USB_DEVICE_ROM_DRIVER)\r
+ #include "../USBRom/usbd_rom_api.h"\r
+ #endif\r
+\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ #if (defined(USE_RAM_DESCRIPTORS) && defined(USE_EEPROM_DESCRIPTORS))\r
+ #error USE_RAM_DESCRIPTORS and USE_EEPROM_DESCRIPTORS are mutually exclusive.\r
+ #endif\r
+\r
+ #if defined(USB_SERIES_4_AVR) || defined(USB_SERIES_6_AVR) || defined(USB_SERIES_7_AVR) || \\r
+ defined(__DOXYGEN__)\r
+\r
+ #define USB_DEVICE_OPT_LOWSPEED (1 << 0)\r
+ #endif\r
+\r
+ #define USB_DEVICE_OPT_FULLSPEED (0 << 0)\r
+\r
+ #if (!defined(NO_INTERNAL_SERIAL) && \\r
+ (defined(USB_SERIES_7_AVR) || defined(USB_SERIES_6_AVR) || defined(USB_SERIES_4_AVR) || \\r
+ (defined(USB_SERIES_2_AVR) && (!defined(__AVR_AT90USB82__) || defined(__AVR_AT90USB162__))) || \\r
+ defined(__DOXYGEN__)))\r
+\r
+ #define USE_INTERNAL_SERIAL 0xDC\r
+\r
+ #define INTERNAL_SERIAL_LENGTH_BITS 80\r
+\r
+ #define INTERNAL_SERIAL_START_ADDRESS 0x0E\r
+ #else\r
+ #define USE_INTERNAL_SERIAL NO_DESCRIPTOR\r
+\r
+ #define INTERNAL_SERIAL_LENGTH_BITS 0\r
+ #define INTERNAL_SERIAL_START_ADDRESS 0\r
+ #endif\r
+\r
+void USB_Device_SendRemoteWakeup(void);\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline uint16_t USB_Device_GetFrameNumber(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline uint16_t USB_Device_GetFrameNumber(void)\r
+{\r
+ return 0;\r
+}\r
+\r
+ #if !defined(NO_SOF_EVENTS)\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void USB_Device_EnableSOFEvents(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_EnableSOFEvents(void)\r
+{}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void USB_Device_DisableSOFEvents(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_DisableSOFEvents(void)\r
+{}\r
+\r
+ #endif\r
+\r
+ #if !defined(__DOXYGEN__)\r
+ #if defined(USB_DEVICE_OPT_LOWSPEED)\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void USB_Device_SetLowSpeed(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetLowSpeed(void)\r
+{\r
+ // UDCON |= (1 << LSM);\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void USB_Device_SetFullSpeed(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetFullSpeed(void)\r
+{\r
+ // UDCON &= ~(1 << LSM);\r
+}\r
+\r
+ #endif\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void USB_Device_SetDeviceAddress(uint8_t corenum, const uint8_t Address) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetDeviceAddress(uint8_t corenum, const uint8_t Address)\r
+{\r
+ HAL_SetDeviceAddress(Address);\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline bool USB_Device_IsAddressSet(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline bool USB_Device_IsAddressSet(void)\r
+{\r
+ return true; /* temporarily */\r
+}\r
+\r
+ #if (USE_INTERNAL_SERIAL != NO_DESCRIPTOR)\r
+static inline void USB_Device_GetSerialString(uint16_t *const UnicodeString) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+static inline void USB_Device_GetSerialString(uint16_t *const UnicodeString)\r
+{\r
+ uint_reg_t CurrentGlobalInt = GetGlobalInterruptMask();\r
+ GlobalInterruptDisable();\r
+\r
+ uint8_t SigReadAddress = INTERNAL_SERIAL_START_ADDRESS;\r
+\r
+ for (uint8_t SerialCharNum = 0; SerialCharNum < (INTERNAL_SERIAL_LENGTH_BITS / 4); SerialCharNum++) {\r
+ uint8_t SerialByte = boot_signature_byte_get(SigReadAddress);\r
+\r
+ if (SerialCharNum & 0x01) {\r
+ SerialByte >>= 4;\r
+ SigReadAddress++;\r
+ }\r
+\r
+ SerialByte &= 0x0F;\r
+\r
+ UnicodeString[SerialCharNum] = cpu_to_le16((SerialByte >= 10) ?\r
+ (('A' - 10) + SerialByte) : ('0' + SerialByte));\r
+ }\r
+\r
+ SetGlobalInterruptMask(CurrentGlobalInt);\r
+}\r
+\r
+ #endif\r
+\r
+ #endif\r
+\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Endpoint definitions for the LPC11Uxx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#if (defined(__LPC11U1X__) || defined(__LPC11U2X_3X__) || defined(__LPC1347__)) && defined(USB_CAN_BE_DEVICE)\r
+#include "../../Endpoint.h"\r
+\r
+#if defined(USB_DEVICE_ROM_DRIVER)\r
+\r
+PRAGMA_ALIGN_256\r
+uint8_t usb_RomDriver_buffer[ROMDRIVER_MEM_SIZE] ATTR_ALIGNED(256);\r
+PRAGMA_ALIGN_4\r
+uint8_t usb_RomDriver_MSC_buffer[ROMDRIVER_MSC_MEM_SIZE] ATTR_ALIGNED(4);\r
+PRAGMA_ALIGN_4\r
+uint8_t usb_RomDriver_CDC_buffer[ROMDRIVER_CDC_MEM_SIZE] ATTR_ALIGNED(4);\r
+/** Endpoint IN buffer, used for DMA operation */\r
+PRAGMA_ALIGN_4\r
+uint8_t UsbdCdc_EPIN_buffer[CDC_MAX_BULK_EP_SIZE] ATTR_ALIGNED(4);\r
+/** Endpoint OUT buffer, used for DMA operation */\r
+PRAGMA_ALIGN_4\r
+uint8_t UsbdCdc_EPOUT_buffer[CDC_MAX_BULK_EP_SIZE] ATTR_ALIGNED(4);\r
+PRAGMA_ALIGN_4\r
+uint8_t usb_RomDriver_HID_buffer[ROMDRIVER_HID_MEM_SIZE] ATTR_ALIGNED(4);\r
+\r
+#endif\r
+\r
+#define IsOutEndpoint(PhysicalEP) (!((PhysicalEP) & 1) )\r
+PRAGMA_ALIGN_256\r
+/*static*/ USB_CMD_STAT EndPointCmdStsList[USED_PHYSICAL_ENDPOINTS][2] __BSS(USBRAM_SECTION) ATTR_ALIGNED(256);/* 10 endpoints with 2 buffers each */\r
+PRAGMA_ALIGN_64\r
+static uint8_t SetupPackage[8] __BSS(USBRAM_SECTION) ATTR_ALIGNED(64);\r
+uint32_t EndpointMaxPacketSize[USED_PHYSICAL_ENDPOINTS];\r
+uint32_t Remain_length[ENDPOINT_DETAILS_MAXEP];\r
+bool shortpacket, epout_primed;\r
+uint16_t stream_total_packets;\r
+\r
+void HAL_Reset(void)\r
+{\r
+ LPC_USB->EPINUSE = 0;\r
+ LPC_USB->EPSKIP = 0xFFFFFFFF;\r
+ LPC_USB->EPBUFCFG = 0;\r
+\r
+ LPC_USB->DEVCMDSTAT |= USB_EN | USB_IntOnNAK_AO | USB_IntOnNAK_CO;\r
+ /* Clear all EP interrupts, device status, and SOF interrupts. */\r
+ LPC_USB->INTSTAT = 0xC00003FF;\r
+ /* Enable all ten(10) EPs interrupts including EP0, note: EP won't be\r
+ ready until it's configured/enabled when device sending SetEPStatus command\r
+ to the command engine. */\r
+ LPC_USB->INTEN = DEV_STAT_INT;\r
+\r
+ /* Initialize EP Command/Status List. */\r
+ LPC_USB->EPLISTSTART = (uint32_t) EndPointCmdStsList;\r
+ LPC_USB->DATABUFSTART = ((uint32_t) usb_data_buffer) & 0xFFC00000;\r
+\r
+ memset(EndPointCmdStsList, 0, sizeof(EndPointCmdStsList) );\r
+\r
+ HAL_SetDeviceAddress(0);\r
+\r
+ shortpacket = epout_primed = false;\r
+\r
+}\r
+\r
+bool Endpoint_ConfigureEndpointControl(const uint16_t Size)\r
+{\r
+ /* Endpoint Control OUT Buffer 0 */\r
+ EndPointCmdStsList[0][0].BufferAddrOffset = 0;\r
+ EndPointCmdStsList[0][0].NBytes = 0x200;\r
+ EndPointCmdStsList[0][0].Active = 0;\r
+\r
+ /* Setup Buffer */\r
+ EndPointCmdStsList[0][1].BufferAddrOffset = ( ((uint32_t) SetupPackage) >> 6) & 0xFFFF;\r
+\r
+ /* Endpoint Control IN Buffer 0 */\r
+ EndPointCmdStsList[1][0].BufferAddrOffset = 0;\r
+ EndPointCmdStsList[1][0].NBytes = 0;\r
+ EndPointCmdStsList[1][0].Active = 0;\r
+\r
+ LPC_USB->INTSTAT &= ~3;\r
+ LPC_USB->INTEN |= 3;\r
+\r
+ EndpointMaxPacketSize[0] = EndpointMaxPacketSize[1] = Size;\r
+\r
+ return true;\r
+}\r
+\r
+bool Endpoint_ConfigureEndpoint(uint8_t corenum, const uint8_t Number, const uint8_t Type,\r
+ const uint8_t Direction, const uint16_t Size, const uint8_t Banks)\r
+{\r
+ uint32_t PhyEP = 2 * Number + (Direction == ENDPOINT_DIR_OUT ? 0 : 1);\r
+\r
+ memset(EndPointCmdStsList[PhyEP], 0, sizeof(USB_CMD_STAT) * 2);\r
+ EndPointCmdStsList[PhyEP][0].NBytes = IsOutEndpoint(PhyEP) ? 0x200 : 0;\r
+\r
+ LPC_USB->INTSTAT &= ~(1 << PhyEP);\r
+ LPC_USB->INTEN |= (1 << PhyEP);\r
+\r
+ EndpointMaxPacketSize[PhyEP] = Size;\r
+ endpointhandle(corenum)[Number] = (Number == ENDPOINT_CONTROLEP) ? ENDPOINT_CONTROLEP : PhyEP;\r
+\r
+ return true;\r
+}\r
+\r
+void Endpoint_Streaming(uint8_t corenum, uint8_t *buffer, uint16_t packetsize,\r
+ uint16_t totalpackets, uint16_t dummypackets)\r
+{\r
+ uint8_t PhyEP = endpointhandle(corenum)[endpointselected[corenum]];\r
+ uint16_t i;\r
+\r
+ if (PhyEP & 1) {\r
+ for (i = 0; i < totalpackets; i++) {\r
+ while (!Endpoint_IsReadWriteAllowed(corenum)) ;\r
+ Endpoint_Write_Stream_LE(corenum,(void *) (buffer + i * packetsize), packetsize, NULL);\r
+ Endpoint_ClearIN(corenum);\r
+ }\r
+ for (i = 0; i < dummypackets; i++) {\r
+ while (!Endpoint_IsReadWriteAllowed(corenum)) ;\r
+ Endpoint_Write_Stream_LE(corenum,(void *) buffer, packetsize, NULL);\r
+ Endpoint_ClearIN(corenum);\r
+ }\r
+ }\r
+ else {\r
+ stream_total_packets = totalpackets + dummypackets;\r
+ for (i = 0; i < totalpackets; i++) {\r
+ DcdDataTransfer(PhyEP, (uint8_t *) (buffer + i * packetsize), packetsize);\r
+ Endpoint_ClearOUT(corenum);\r
+ while (!Endpoint_IsReadWriteAllowed(corenum)) ;\r
+ }\r
+ for (i = 0; i < dummypackets; i++) {\r
+ DcdDataTransfer(PhyEP, buffer, packetsize);\r
+ Endpoint_ClearOUT(corenum);\r
+ while (!Endpoint_IsReadWriteAllowed(corenum)) ;\r
+ }\r
+ stream_total_packets = 0;\r
+ }\r
+}\r
+\r
+void DcdDataTransfer(uint8_t EPNum, uint8_t *pData, uint32_t length)\r
+{\r
+ if (EPNum & 1) {\r
+ if (length >= EndpointMaxPacketSize[EPNum]) {\r
+ if ((length == EndpointMaxPacketSize[EPNum]) && (EPNum == 1)) {\r
+ shortpacket = true;\r
+ }\r
+ Remain_length[EPNum / 2] = length - EndpointMaxPacketSize[EPNum];\r
+ length = EndpointMaxPacketSize[EPNum];\r
+ }\r
+ else {\r
+ Remain_length[EPNum / 2] = 0;\r
+ }\r
+ EndPointCmdStsList[EPNum][0].NBytes = length;\r
+ }\r
+ EndPointCmdStsList[EPNum][0].BufferAddrOffset = ( ((uint32_t) pData) >> 6 ) & 0xFFFF;\r
+\r
+ EndPointCmdStsList[EPNum][0].Active = 1;\r
+}\r
+\r
+void Endpoint_GetSetupPackage(uint8_t corenum, uint8_t *pData)\r
+{\r
+ memcpy(pData, SetupPackage, 8);\r
+ /* Clear endpoint control stall flag if set */\r
+ EndPointCmdStsList[0][0].Stall = 0;\r
+ EndPointCmdStsList[1][0].Stall = 0;\r
+}\r
+\r
+void USB_IRQHandler(void)\r
+{\r
+ \r
+#if defined(USB_DEVICE_ROM_DRIVER)\r
+ UsbdRom_IrqHandler();\r
+#else \r
+ uint32_t IntStat = LPC_USB->INTSTAT; \r
+ uint32_t IntEn = LPC_USB->INTEN;\r
+ \r
+ IntStat &= IntEn; /* Get Interrupt Status and clear immediately. */\r
+ \r
+ if (IntStat == 0) {\r
+ return;\r
+ }\r
+\r
+ LPC_USB->INTSTAT = IntStat;\r
+\r
+ /* SOF Interrupt */\r
+ if (IntStat & FRAME_INT) {}\r
+\r
+ /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */\r
+ if (IntStat & DEV_STAT_INT) {\r
+ uint32_t DevCmdStat = LPC_USB->DEVCMDSTAT; /* Device Status */\r
+\r
+ if (DevCmdStat & USB_DRESET_C) { /* Reset */\r
+ LPC_USB->DEVCMDSTAT |= USB_DRESET_C;\r
+ HAL_Reset();\r
+ USB_DeviceState[0] = DEVICE_STATE_Default;\r
+ Endpoint_ConfigureEndpointControl(USB_Device_ControlEndpointSize);\r
+ }\r
+\r
+ if (DevCmdStat & USB_DCON_C) { /* Connect change */\r
+ LPC_USB->DEVCMDSTAT |= USB_DCON_C;\r
+ }\r
+\r
+ if (DevCmdStat & USB_DSUS_C) { /* Suspend/Resume */\r
+ LPC_USB->DEVCMDSTAT |= USB_DSUS_C;\r
+ if (DevCmdStat & USB_DSUS) { /* Suspend */\r
+ }\r
+ else { /* Resume */\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Endpoint's Interrupt */\r
+ if (IntStat & 0x3FF) { /* if any of the EP0 through EP9 is set, or bit 0 through 9 on disr */\r
+ uint32_t PhyEP;\r
+ for (PhyEP = 0; PhyEP < USED_PHYSICAL_ENDPOINTS; PhyEP++) /* Check All Endpoints */\r
+ if ( IntStat & (1 << PhyEP) ) {\r
+ if ( IsOutEndpoint(PhyEP) ) { /* OUT Endpoint */\r
+ if ( !Endpoint_IsSETUPReceived(0) ) {\r
+ if (EndPointCmdStsList[PhyEP][0].NBytes == 0x200) {\r
+ if (PhyEP == 0) {\r
+ DcdDataTransfer(PhyEP, usb_data_buffer[0], 512);\r
+ }\r
+ else if (stream_total_packets == 0) {\r
+ DcdDataTransfer(PhyEP, usb_data_buffer_OUT[0], 512);\r
+ }\r
+ if ((PhyEP == 0) || (stream_total_packets == 0)) {\r
+ epout_primed = true;\r
+ }\r
+ }\r
+ else {\r
+ if (epout_primed) {\r
+ epout_primed = false;\r
+ if (PhyEP == 0) {\r
+ usb_data_buffer_size[0] = (512 - EndPointCmdStsList[PhyEP][0].NBytes);\r
+ }\r
+ else {\r
+ usb_data_buffer_OUT_size[0] = (512 - EndPointCmdStsList[PhyEP][0].NBytes);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else { /* IN Endpoint */\r
+ if (Remain_length[PhyEP / 2] > 0) {\r
+ uint32_t i;\r
+ if (PhyEP == 1) { /* Control IN */\r
+ for (i = 0; i < Remain_length[PhyEP / 2]; i++)\r
+ usb_data_buffer[0][i] = usb_data_buffer[0][i + EndpointMaxPacketSize[PhyEP]];\r
+ DcdDataTransfer(PhyEP, usb_data_buffer[0], Remain_length[PhyEP / 2]);\r
+ }\r
+ else {\r
+ for (i = 0; i < Remain_length[PhyEP / 2]; i++)\r
+ usb_data_buffer_IN[0][i] = usb_data_buffer_IN[0][i + EndpointMaxPacketSize[PhyEP]];\r
+ DcdDataTransfer(PhyEP, usb_data_buffer_IN[0], Remain_length[PhyEP / 2]);\r
+ }\r
+ }\r
+ else {\r
+ if (PhyEP == 1) { /* Control IN */\r
+ if (shortpacket) {\r
+ shortpacket = false;\r
+ DcdDataTransfer(PhyEP, usb_data_buffer[0], 0);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+//#endif // defined(USB_DEVICE_ROM_DRIVER)\r
+\r
+#endif /*__LPC11UXX__ || __LPC1347__*/\r
--- /dev/null
+/*\r
+ * @brief USB Endpoint definitions for the LPC11Uxx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_EndpointRW\r
+ * @defgroup Group_EndpointRW_LPC11Uxx Endpoint Data Reading and Writing (LPC11Uxx, LPC1347)\r
+ * @brief Endpoint data read/write definitions for the LPC11Uxx and LPC1347 architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing from and to endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointPrimitiveRW\r
+ * @defgroup Group_EndpointPrimitiveRW_LPC11Uxx Read/Write of Primitive Data Types (LPC11Uxx, LPC1347)\r
+ * @brief Endpoint primitive read/write definitions for the LPC11Uxx and LPC1347 architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing of primitive data types\r
+ * from and to endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointPacketManagement\r
+ * @defgroup Group_EndpointPacketManagement_LPC11Uxx Endpoint Packet Management (LPC11Uxx, LPC1347)\r
+ * @brief Endpoint packet management definitions for the NXP LPC11Uxx and LPC1347 architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to packet management of endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointManagement\r
+ * @defgroup Group_EndpointManagement_LPC11Uxx Endpoint Management (LPC11Uxx, LPC1347)\r
+ * @brief Endpoint management definitions for the NXP LPC11Uxx and LPC1347 architecture.\r
+ *\r
+ * Functions, macros and enums related to endpoint management when in USB Device mode. This\r
+ * module contains the endpoint management macros, as well as endpoint interrupt and data\r
+ * send/receive functions for various data types.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __ENDPOINT_LPC11UXX_H__\r
+#define __ENDPOINT_LPC11UXX_H__\r
+\r
+ #include "../EndpointCommon.h"\r
+\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ #if !defined(__DOXYGEN__)\r
+\r
+ #define ENDPOINT_DETAILS_MAXEP 5\r
+ #define ENDPOINT_DETAILS_MAXEP0 ENDPOINT_DETAILS_MAXEP\r
+ #define ENDPOINT_DETAILS_MAXEP1 ENDPOINT_DETAILS_MAXEP\r
+ \r
+ #if defined(USB_DEVICE_ROM_DRIVER)\r
+\r
+typedef struct _ROM {\r
+ const unsigned p_usbd;\r
+ const unsigned p_clib;\r
+ const unsigned p_cand;\r
+ #ifdef PWRROMD_PRESENT\r
+ const PWRD *pPWRD;\r
+ #else\r
+ const unsigned p_pwrd;\r
+ #endif /* PWRROMD_PRESENT */\r
+ #ifdef DIVROMD_PRESENT\r
+ const LPC_ROM_DIV_STRUCT *pROMDiv;\r
+ #else\r
+ const unsigned p_dev1;\r
+ #endif /* DIVROMD_PRESENT */\r
+ const unsigned p_dev2;\r
+ const unsigned p_dev3;\r
+ const unsigned p_dev4;\r
+} ROM_FUNCTION_TABLE;\r
+\r
+ #define ROM_FUNCTION_TABLE_PTR_ADDR (0x1FFF1FF8UL)\r
+ #define ROM_USBD_PTR ((*(ROM_FUNCTION_TABLE * *) (ROM_FUNCTION_TABLE_PTR_ADDR))->p_usbd)\r
+\r
+ #define ROMDRIVER_USB0_BASE LPC_USB0_BASE\r
+ #define ROMDRIVER_USB1_BASE LPC_USB0_BASE\r
+ #define ROMDRIVER_MEM_SIZE 0x500\r
+extern uint8_t usb_RomDriver_buffer[ROMDRIVER_MEM_SIZE];\r
+\r
+ #define ROMDRIVER_MSC_MEM_SIZE 0x100\r
+extern uint8_t usb_RomDriver_MSC_buffer[ROMDRIVER_MSC_MEM_SIZE];\r
+\r
+ #define ROMDRIVER_CDC_MEM_SIZE 0x8\r
+extern uint8_t usb_RomDriver_CDC_buffer[ROMDRIVER_CDC_MEM_SIZE];\r
+\r
+ #if (USB_FORCED_FULLSPEED)\r
+ #define CDC_MAX_BULK_EP_SIZE 64\r
+ #else\r
+ #define CDC_MAX_BULK_EP_SIZE 512\r
+ #endif\r
+extern uint8_t UsbdCdc_EPIN_buffer[CDC_MAX_BULK_EP_SIZE];\r
+extern uint8_t UsbdCdc_EPOUT_buffer[CDC_MAX_BULK_EP_SIZE];\r
+\r
+ #define ROMDRIVER_HID_MEM_SIZE 0x8\r
+extern uint8_t usb_RomDriver_HID_buffer[ROMDRIVER_HID_MEM_SIZE];\r
+\r
+ #endif\r
+\r
+void Endpoint_ClearEndpoints(uint8_t corenum);\r
+\r
+bool Endpoint_ConfigureEndpoint_Prv(uint8_t corenum,\r
+ const uint8_t Number,\r
+ const uint8_t UECFG0XData,\r
+ const uint8_t UECFG1XData);\r
+\r
+ #endif\r
+ #define USED_PHYSICAL_ENDPOINTS (ENDPOINT_DETAILS_MAXEP * 2)/* This macro effect memory size of the DCD */\r
+\r
+ #define USB_EN (0x1 << 7) /* Device Enable */\r
+ #define USB_SETUP_RCVD (0x1 << 8) /* SETUP token received */\r
+ #define USB_PLL_ON (0x1 << 9) /* PLL is always ON */\r
+ #define USB_LPM (0x1 << 11) /* LPM is supported */\r
+ #define USB_IntOnNAK_AO (0x1 << 12) /* Device Interrupt on NAK BULK OUT */\r
+ #define USB_IntOnNAK_AI (0x1 << 13) /* Device Interrupt on NAK BULK IN */\r
+ #define USB_IntOnNAK_CO (0x1 << 14) /* Device Interrupt on NAK CTRL OUT */\r
+ #define USB_IntOnNAK_CI (0x1 << 15) /* Device Interrupt on NAK CTRL IN */\r
+ #define USB_DCON (0x1 << 16) /* Device connect */\r
+ #define USB_DSUS (0x1 << 17) /* Device Suspend */\r
+ #define USB_LPM_SUS (0x1 << 19) /* LPM suspend */\r
+ #define USB_REMOTE_WAKE (0x1 << 20) /* LPM Remote Wakeup */\r
+ #define USB_DCON_C (0x1 << 24) /* Device connection change */\r
+ #define USB_DSUS_C (0x1 << 25) /* Device SUSPEND change */\r
+ #define USB_DRESET_C (0x1 << 26) /* Device RESET */\r
+ #define USB_VBUS_DBOUNCE (0x1 << 28) /* Device VBUS detect */\r
+\r
+ #define EP0_INT (0x1 << 0)\r
+ #define EP1_INT (0x1 << 1)\r
+ #define EP2_INT (0x1 << 2)\r
+ #define EP3_INT (0x1 << 3)\r
+ #define EP4_INT (0x1 << 4)\r
+ #define EP5_INT (0x1 << 5)\r
+ #define EP6_INT (0x1 << 6)\r
+ #define EP7_INT (0x1 << 7)\r
+ #define EP8_INT (0x1 << 8)\r
+ #define EP9_INT (0x1 << 9)\r
+ #define FRAME_INT (0x1 << 30)\r
+ #define DEV_STAT_INT (0x80000000)\r
+\r
+ #define PKT_LNGTH_MASK 0x000003FF\r
+\r
+ #define ERR_NOERROR 0x00\r
+ #define ERR_PID_ENCODE 0x01\r
+ #define ERR_UNKNOWN_PID 0x02\r
+ #define ERR_UNEXPECT_PKT 0x03\r
+ #define ERR_TCRC 0x04\r
+ #define ERR_DCRC 0x05\r
+ #define ERR_TIMEOUT 0x06\r
+ #define ERR_BABBIE 0x07\r
+ #define ERR_EOF_PKT 0x08\r
+ #define ERR_TX_RX_NAK 0x09\r
+ #define ERR_SENT_STALL 0x0A\r
+ #define ERR_BUF_OVERRUN 0x0B\r
+ #define ERR_SENT_EPT_PKT 0x0C\r
+ #define ERR_BIT_STUFF 0x0D\r
+ #define ERR_SYNC 0x0E\r
+ #define ERR_TOGGLE_BIT 0x0F\r
+extern void WrCmdDat (uint32_t cmd, uint32_t val);\r
+\r
+extern void WrCmd (uint32_t cmd);\r
+\r
+void HAL11UXX_WriteEndPoint(uint8_t EPNum, uint8_t *pData, uint32_t cnt);\r
+\r
+void DcdDataTransfer(uint8_t EPNum, uint8_t *pData, uint32_t length);\r
+\r
+void Endpoint_Streaming(uint8_t corenum, uint8_t *buffer, uint16_t packetsize,\r
+ uint16_t totalpackets, uint16_t dummypackets);\r
+\r
+extern USB_CMD_STAT EndPointCmdStsList[10][2];\r
+\r
+/*static inline */ bool Endpoint_ConfigureEndpoint(uint8_t corenum,\r
+ const uint8_t Number,\r
+ const uint8_t Type,\r
+ const uint8_t Direction,\r
+ const uint16_t Size,\r
+ const uint8_t Banks) /*ATTR_ALWAYS_INLINE*/;\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber)\r
+{}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void Endpoint_EnableEndpoint(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_EnableEndpoint(void)\r
+{}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void Endpoint_DisableEndpoint(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_DisableEndpoint(void)\r
+{}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline bool Endpoint_IsEnabled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsEnabled(void)\r
+{\r
+ return true;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline uint8_t Endpoint_GetBusyBanks(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline uint8_t Endpoint_GetBusyBanks(void)\r
+{\r
+ return 0;\r
+}\r
+\r
+static inline void Endpoint_AbortPendingIN(void)\r
+{}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline bool Endpoint_IsConfigured(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsConfigured(void)\r
+{\r
+ // return ((UESTA0X & (1 << CFGOK)) ? true : false);\r
+ return true;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline uint8_t Endpoint_GetEndpointInterrupts(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline uint8_t Endpoint_GetEndpointInterrupts(void)\r
+{\r
+ return 0; // TODO not yet implemented\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber) ATTR_WARN_UNUSED_RESULT\r
+ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber)\r
+{\r
+ return (Endpoint_GetEndpointInterrupts() & (1 << EndpointNumber)) ? true : false;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum)\r
+{\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ return usb_data_buffer_size[corenum];\r
+ }\r
+ else {\r
+ return usb_data_buffer_OUT_size[corenum];\r
+ }\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline bool Endpoint_IsINReady(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsINReady(uint8_t corenum)\r
+{\r
+ uint32_t PhyEP =\r
+ (endpointselected[corenum] == ENDPOINT_CONTROLEP) ? (ENDPOINT_CONTROLEP + 1) : endpointhandle(corenum)[endpointselected[corenum]];\r
+ return EndPointCmdStsList[PhyEP][0].Active ? false : true;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline bool Endpoint_IsOUTReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsOUTReceived(uint8_t corenum)\r
+{\r
+ return /*EndPointCmdStsList[ endpointhandle(corenum)[endpointselected] ][0].Active == 0 &&*/\r
+ EndPointCmdStsList[endpointhandle(corenum)[endpointselected[corenum]]][0].NBytes != 0x200;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline bool Endpoint_IsSETUPReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsSETUPReceived(uint8_t corenum)\r
+{\r
+ return LPC_USB->DEVCMDSTAT & USB_SETUP_RCVD ? true : false;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void Endpoint_ClearSETUP(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearSETUP(uint8_t corenum)\r
+{\r
+ LPC_USB->DEVCMDSTAT |= USB_SETUP_RCVD;\r
+ usb_data_buffer_index[corenum] = 0;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void Endpoint_ClearIN(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearIN(uint8_t corenum)\r
+{\r
+ uint8_t PhyEP = (endpointselected[corenum] == ENDPOINT_CONTROLEP ? 1 : endpointhandle(corenum)[endpointselected[corenum]]);\r
+ if (PhyEP == 1) {\r
+ DcdDataTransfer(PhyEP, usb_data_buffer[corenum], usb_data_buffer_index[corenum]);\r
+ usb_data_buffer_index[corenum] = 0;\r
+ }\r
+ else {\r
+ DcdDataTransfer(PhyEP, usb_data_buffer_IN[corenum], usb_data_buffer_IN_index[corenum]);\r
+ usb_data_buffer_IN_index[corenum] = 0;\r
+ }\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void Endpoint_ClearOUT(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearOUT(uint8_t corenum)\r
+{\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ usb_data_buffer_index[corenum] = 0;\r
+ }\r
+ else {usb_data_buffer_OUT_index[corenum] = 0; }\r
+\r
+ EndPointCmdStsList[endpointhandle(corenum)[endpointselected[corenum]]][0].NBytes = 0x200;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void Endpoint_StallTransaction(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_StallTransaction(uint8_t corenum)\r
+{\r
+ EndPointCmdStsList[endpointhandle(corenum)[endpointselected[corenum]]][0].Stall = 1;\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ EndPointCmdStsList[1][0].Stall = 1;\r
+ }\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void Endpoint_ClearStall(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearStall(uint8_t corenum)\r
+{\r
+ EndPointCmdStsList[endpointhandle(corenum)[endpointselected[corenum]]][0].Stall = 0;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline bool Endpoint_IsStalled(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsStalled(uint8_t corenum)\r
+{\r
+ return EndPointCmdStsList[endpointhandle(corenum)[endpointselected[corenum]]][0].Stall ? true : false;\r
+}\r
+\r
+PRAGMA_ALWAYS_INLINE\r
+static inline void Endpoint_ResetDataToggle(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ResetDataToggle(uint8_t corenum)\r
+{\r
+ EndPointCmdStsList[endpointhandle(corenum)[endpointselected[corenum]]][0].ToogleReset = 1;\r
+}\r
+\r
+ #if (!defined(FIXED_CONTROL_ENDPOINT_SIZE) || defined(__DOXYGEN__))\r
+extern uint8_t USB_Device_ControlEndpointSize;\r
+ #else\r
+ #define USB_Device_ControlEndpointSize FIXED_CONTROL_ENDPOINT_SIZE\r
+ #endif\r
+\r
+void Endpoint_ClearStatusStage(uint8_t corenum);\r
+\r
+uint8_t Endpoint_WaitUntilReady(void);\r
+\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Device definitions for the LPC17xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_Device\r
+ * @defgroup Group_Device_LPC17xx Device Management (LPC17xx)\r
+ * @brief USB Device definitions for the LPC17xx microcontrollers.\r
+ *\r
+ * Architecture specific USB Device definitions for the LPC microcontrollers.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __USBDEVICE_LPC17XX_H__\r
+#define __USBDEVICE_LPC17XX_H__\r
+\r
+ #include "../../../../../Common/Common.h"\r
+ #include "../../USBController.h"\r
+ #include "../../StdDescriptors.h"\r
+ #include "../../USBInterrupt.h"\r
+ #include "../../HAL/HAL.h"\r
+ #include "../../Endpoint.h"\r
+\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ #if (defined(USE_RAM_DESCRIPTORS) && defined(USE_EEPROM_DESCRIPTORS))\r
+ #error USE_RAM_DESCRIPTORS and USE_EEPROM_DESCRIPTORS are mutually exclusive.\r
+ #endif\r
+\r
+ #if defined(__DOXYGEN__)\r
+ /** Mask for the Options parameter of the @ref USB_Init() function. This indicates that the\r
+ * USB interface should be initialized in low speed (1.5Mb/s) mode.\r
+ */\r
+ #define USB_DEVICE_OPT_LOWSPEED (1 << 0)\r
+ #endif\r
+ /** Mask for the Options parameter of the @ref USB_Init() function. This indicates that the\r
+ * USB interface should be initialized in full speed (12Mb/s) mode.\r
+ */\r
+ #define USB_DEVICE_OPT_FULLSPEED (0 << 0)\r
+\r
+ #if (!defined(NO_INTERNAL_SERIAL) && \\r
+ (defined(__DOXYGEN__)) )\r
+ /** String descriptor index for the device's unique serial number string descriptor within the device.\r
+ * This unique serial number is used by the host to associate resources to the device (such as drivers or COM port\r
+ * number allocations) to a device regardless of the port it is plugged in to on the host. Some microcontrollers contain\r
+ * a unique serial number internally, and setting the device descriptors serial number string index to this value\r
+ * will cause it to use the internal serial number.\r
+ *\r
+ * On unsupported devices, this will evaluate to @ref NO_DESCRIPTOR and so will force the host to create a pseudo-serial\r
+ * number for the device.\r
+ */\r
+ #define USE_INTERNAL_SERIAL 0xDC\r
+ /** Length of the device's unique internal serial number, in bits, if present on the selected microcontroller\r
+ * model.\r
+ */\r
+ #define INTERNAL_SERIAL_LENGTH_BITS 80\r
+ /** Start address of the internal serial number, in the appropriate address space, if present on the selected microcontroller\r
+ * model.\r
+ */\r
+ #define INTERNAL_SERIAL_START_ADDRESS 0x0E\r
+ #else\r
+ #define USE_INTERNAL_SERIAL NO_DESCRIPTOR\r
+\r
+ #define INTERNAL_SERIAL_LENGTH_BITS 0\r
+ #define INTERNAL_SERIAL_START_ADDRESS 0\r
+ #endif\r
+\r
+/** Sends a Remote Wakeup request to the host. This signals to the host that the device should\r
+ * be taken out of suspended mode, and communications should resume.\r
+ */\r
+void USB_Device_SendRemoteWakeup(void);\r
+\r
+//Move to Endpoint_LPC17xx\r
+/*static inline uint16_t USB_Device_GetFrameNumber(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline uint16_t USB_Device_GetFrameNumber(void)\r
+{\r
+ uint32_t val;\r
+\r
+ SIE_WriteCommand(CMD_RD_FRAME);\r
+ val = SIE_ReadCommandData(DAT_RD_FRAME);\r
+ val = val | (SIE_ReadCommandData(DAT_RD_FRAME) << 8);\r
+\r
+ return val;\r
+}*/\r
+\r
+ #if !defined(NO_SOF_EVENTS)\r
+/** Enables the device mode Start Of Frame events. When enabled, this causes the\r
+* @ref EVENT_USB_Device_StartOfFrame() event to fire once per millisecond, synchronized to the USB bus,\r
+* at the start of each USB frame when enumerated in device mode.\r
+*/\r
+static inline void USB_Device_EnableSOFEvents(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_EnableSOFEvents(void)\r
+{}\r
+\r
+/** Disables the device mode Start Of Frame events. When disabled, this stops the firing of the\r
+* @ref EVENT_USB_Device_StartOfFrame() event when enumerated in device mode.\r
+*/\r
+static inline void USB_Device_DisableSOFEvents(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_DisableSOFEvents(void)\r
+{}\r
+\r
+ #endif\r
+\r
+ #if !defined(__DOXYGEN__)\r
+ #if defined(USB_DEVICE_OPT_LOWSPEED)\r
+static inline void USB_Device_SetLowSpeed(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetLowSpeed(void)\r
+{}\r
+\r
+static inline void USB_Device_SetFullSpeed(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetFullSpeed(void)\r
+{}\r
+\r
+ #endif\r
+\r
+//Move to Endpoint_LPC17XX\r
+/*static inline void USB_Device_SetDeviceAddress(uint8_t corenum, const uint8_t Address) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetDeviceAddress(uint8_t corenum, const uint8_t Address)\r
+{\r
+ SIE_WriteCommandData(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | Address)); Don't wait for next\r
+ SIE_WriteCommandData(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | Address)); Setup Status Phase\r
+}*/\r
+\r
+static inline bool USB_Device_IsAddressSet(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline bool USB_Device_IsAddressSet(void)\r
+{\r
+ return true; /* TODO temporarily */\r
+}\r
+\r
+ #if (USE_INTERNAL_SERIAL != NO_DESCRIPTOR)\r
+static inline void USB_Device_GetSerialString(uint16_t *const UnicodeString) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+static inline void USB_Device_GetSerialString(uint16_t *const UnicodeString)\r
+{\r
+ uint_reg_t CurrentGlobalInt = GetGlobalInterruptMask();\r
+ GlobalInterruptDisable();\r
+\r
+ uint8_t SigReadAddress = INTERNAL_SERIAL_START_ADDRESS;\r
+\r
+ for (uint8_t SerialCharNum = 0; SerialCharNum < (INTERNAL_SERIAL_LENGTH_BITS / 4); SerialCharNum++) {\r
+ uint8_t SerialByte = boot_signature_byte_get(SigReadAddress);\r
+\r
+ if (SerialCharNum & 0x01) {\r
+ SerialByte >>= 4;\r
+ SigReadAddress++;\r
+ }\r
+\r
+ SerialByte &= 0x0F;\r
+\r
+ UnicodeString[SerialCharNum] = cpu_to_le16((SerialByte >= 10) ?\r
+ (('A' - 10) + SerialByte) : ('0' + SerialByte));\r
+ }\r
+\r
+ SetGlobalInterruptMask(CurrentGlobalInt);\r
+}\r
+\r
+ #endif\r
+\r
+ #endif\r
+\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Endpoint definitions for the LPC17xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#if (defined(__LPC175X_6X__) || defined(__LPC177X_8X__) || defined(__LPC407X_8X__)) && defined(USB_CAN_BE_DEVICE)\r
+#include "../../Endpoint.h"\r
+\r
+#define IsOutEndpoint(PhysicalEP) (!((PhysicalEP) & 1) )\r
+\r
+volatile bool SETUPReceived;\r
+volatile bool isOutReceived;\r
+volatile bool isInReady;\r
+\r
+PRAGMA_ALIGN_128\r
+uint32_t UDCA[32] __BSS(USBRAM_SECTION) ATTR_ALIGNED(128);\r
+DMADescriptor dmaDescriptor[USED_PHYSICAL_ENDPOINTS] __BSS(USBRAM_SECTION);\r
+static uint8_t SetupPackage[8] __BSS(USBRAM_SECTION);\r
+uint32_t DataInRemainCount, DataInRemainOffset;\r
+bool IsConfigured, shortpacket;\r
+uint8_t *ISO_Address;\r
+PRAGMA_ALIGN_4\r
+uint8_t iso_buffer[512] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+PRAGMA_WEAK(CALLBACK_HAL_GetISOBufferAddress, Dummy_EPGetISOAddress)\r
+uint32_t CALLBACK_HAL_GetISOBufferAddress(const uint32_t EPNum, uint32_t *last_packet_size) ATTR_WEAK ATTR_ALIAS(\r
+ Dummy_EPGetISOAddress);\r
+\r
+uint32_t BufferAddressIso[32] __BSS(USBRAM_SECTION);\r
+uint32_t SizeAudioTransfer;\r
+\r
+void SIE_WriteCommand(uint32_t cmd) {\r
+\r
+ USB_REG(0)->DevIntClr = CCEMTY_INT;\r
+ USB_REG(0)->CmdCode = cmd;\r
+ while ((USB_REG(0)->DevIntSt & CCEMTY_INT) == 0) ;\r
+}\r
+\r
+void SIE_WriteCommandData(uint32_t cmd, uint32_t val) {\r
+\r
+ USB_REG(0)->DevIntClr = CCEMTY_INT;\r
+ USB_REG(0)->CmdCode = cmd;\r
+ while ((USB_REG(0)->DevIntSt & CCEMTY_INT) == 0) ;\r
+ USB_REG(0)->DevIntClr = CCEMTY_INT;\r
+ USB_REG(0)->CmdCode = val;\r
+ while ((USB_REG(0)->DevIntSt & CCEMTY_INT) == 0) ;\r
+}\r
+\r
+uint32_t SIE_ReadCommandData(uint32_t cmd) {\r
+\r
+ USB_REG(0)->DevIntClr = CCEMTY_INT | CDFULL_INT;\r
+ USB_REG(0)->CmdCode = cmd;\r
+ while ((USB_REG(0)->DevIntSt & CDFULL_INT) == 0) ;\r
+ return USB_REG(0)->CmdData;\r
+}\r
+\r
+void HAL_Reset(uint8_t corenum)\r
+{\r
+ uint32_t n;\r
+\r
+ USB_REG(corenum)->EpInd = 0;\r
+ USB_REG(corenum)->MaxPSize = USB_Device_ControlEndpointSize;\r
+ USB_REG(corenum)->EpInd = 1;\r
+ USB_REG(corenum)->MaxPSize = USB_Device_ControlEndpointSize;\r
+ while ((USB_REG(corenum)->DevIntSt & EP_RLZED_INT) == 0) ;\r
+\r
+ /* Slave Register */\r
+ USB_REG(corenum)->EpIntEn = 0;\r
+ USB_REG(corenum)->DevIntEn = (DEV_STAT_INT | EP_SLOW_INT | ERR_INT);\r
+\r
+ USB_REG(corenum)->EpIntClr = 0xFFFFFFFF;\r
+ USB_REG(corenum)->DevIntClr = 0xFFFFFFFF;\r
+ USB_REG(corenum)->EpIntPri = 0;\r
+\r
+ /* DMA registers */\r
+ USB_REG(corenum)->EpDMADis = 0xFFFFFFFF;\r
+ USB_REG(corenum)->DMARClr = 0xFFFFFFFF;\r
+ USB_REG(corenum)->EoTIntClr = 0xFFFFFFFF;\r
+ USB_REG(corenum)->NDDRIntClr = 0xFFFFFFFF;\r
+ USB_REG(corenum)->SysErrIntClr = 0xFFFFFFFF;\r
+\r
+ USB_REG(corenum)->DMAIntEn = (EOT_INT | NDD_REQ_INT | SYS_ERR_INT );\r
+ USB_REG(corenum)->UDCAH = (uint32_t) UDCA;\r
+ for (n = 0; n < USED_PHYSICAL_ENDPOINTS; n++)\r
+ UDCA[n] = 0;\r
+ IsConfigured = false;\r
+ isOutReceived = false;\r
+ isInReady = true;\r
+ usb_data_buffer_size[corenum] = 0;\r
+ usb_data_buffer_index[corenum] = 0;\r
+\r
+ usb_data_buffer_OUT_size[corenum] = 0;\r
+ usb_data_buffer_OUT_index[corenum] = 0;\r
+ // uint32_t usb_data_buffer_IN_size = 0;\r
+ usb_data_buffer_IN_index[corenum] = 0;\r
+ // SIE_WriteCommandData(CMD_SET_MODE, DAT_WR_BYTE(0) );\r
+ // SIE_WriteCommandData(CMD_SET_MODE, DAT_WR_BYTE(INAK_IO | INAK_BO) ); /* Disable INAK_IO, INAK_BO */\r
+}\r
+\r
+void Endpoint_StallTransaction(uint8_t corenum)\r
+{\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ SIE_WriteCommandData(CMD_SET_EP_STAT(endpointhandle(corenum)[endpointselected[corenum]]), DAT_WR_BYTE(EP_STAT_CND_ST) );\r
+ }\r
+ else {\r
+ SIE_WriteCommandData(CMD_SET_EP_STAT(endpointhandle(corenum)[endpointselected[corenum]]), DAT_WR_BYTE(EP_STAT_ST) );\r
+ }\r
+}\r
+\r
+bool Endpoint_ConfigureEndpoint(uint8_t corenum, const uint8_t Number, const uint8_t Type,\r
+ const uint8_t Direction, const uint16_t Size, const uint8_t Banks)\r
+{\r
+ uint32_t PhyEP = 2 * Number + (Direction == ENDPOINT_DIR_OUT ? 0 : 1);\r
+\r
+ if ((!IsConfigured) && (PhyEP > 1)) {\r
+ IsConfigured = true;\r
+ SIE_WriteCommandData(CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));\r
+ }\r
+\r
+ USB_REG(corenum)->ReEp |= (1 << PhyEP); /* Realize endpoint */\r
+\r
+ USB_REG(corenum)->EpInd = PhyEP; /* Endpoint Index */\r
+ USB_REG(corenum)->MaxPSize = Size & 0x3ff; /* Max Packet Size */\r
+\r
+ while ((USB_REG(corenum)->DevIntSt & EP_RLZED_INT) == 0) ; /* TODO shouldd we wait for this */\r
+ USB_REG(corenum)->DevIntClr = EP_RLZED_INT;\r
+\r
+ if (Number == ENDPOINT_CONTROLEP) { /* Control endpoints have to uses slave mode */\r
+ USB_REG(corenum)->EpIntEn |= _BIT(PhyEP);\r
+ DataInRemainCount = 0;\r
+ DataInRemainOffset = 0;\r
+ }\r
+ else { /* all other endpoints use DMA mode */\r
+ memset(&dmaDescriptor[PhyEP], 0, sizeof(DMADescriptor));\r
+ dmaDescriptor[PhyEP].Isochronous = (Type == EP_TYPE_ISOCHRONOUS ? 1 : 0 );\r
+ dmaDescriptor[PhyEP].MaxPacketSize = Size;\r
+ dmaDescriptor[PhyEP].Retired = 1; /* inactive DD */\r
+\r
+ USB_REG(corenum)->EpDMAEn = _BIT(PhyEP);\r
+ }\r
+\r
+ SIE_WriteCommandData(CMD_SET_EP_STAT(PhyEP), DAT_WR_BYTE(0)); /*enable endpoint*/\r
+ SIE_WriteCommandData(CMD_SET_EP_STAT(PhyEP), DAT_WR_BYTE(0)); /* Reset Endpoint */\r
+\r
+ endpointhandle(corenum)[Number] = (Number == ENDPOINT_CONTROLEP) ? ENDPOINT_CONTROLEP : PhyEP;\r
+ return true;\r
+}\r
+\r
+void ReadControlEndpoint(uint8_t *pData)\r
+{\r
+ uint32_t cnt, n;\r
+\r
+ USB_REG(0)->Ctrl = CTRL_RD_EN;\r
+\r
+ do {\r
+ cnt = USB_REG(0)->RxPLen;\r
+ } while ((cnt & PKT_RDY) == 0);\r
+ cnt &= PKT_LNGTH_MASK;\r
+\r
+ for (n = 0; n < (cnt + 3) / 4; n++) {\r
+ *((uint32_t *) pData) = USB_REG(0)->RxData;\r
+ pData += 4;\r
+ }\r
+ USB_REG(0)->Ctrl = 0;\r
+\r
+ if ((cnt > 0) && (SETUPReceived == false)) {\r
+ isOutReceived = true;\r
+ }\r
+ usb_data_buffer_size[0] = cnt;\r
+\r
+ // SIE_WriteCommamd(CMD_SEL_EP(ENDPOINT_CONTROLEP));\r
+ // SIE_WriteCommamd(CMD_CLR_BUF);\r
+}\r
+\r
+void WriteControlEndpoint(uint8_t *pData, uint32_t cnt)\r
+{\r
+ uint32_t n;\r
+ uint32_t count;\r
+\r
+ isInReady = false;\r
+ if (cnt >= USB_Device_ControlEndpointSize) {\r
+ if (cnt == USB_Device_ControlEndpointSize) {\r
+ shortpacket = true;\r
+ }\r
+ count = USB_Device_ControlEndpointSize;\r
+ DataInRemainCount = cnt - USB_Device_ControlEndpointSize;\r
+ DataInRemainOffset += count;\r
+ }\r
+ else {\r
+ count = cnt;\r
+ DataInRemainCount = 0;\r
+ DataInRemainOffset = 0;\r
+ }\r
+ USB_REG(0)->Ctrl = CTRL_WR_EN;\r
+ USB_REG(0)->TxPLen = count;\r
+\r
+ for (n = 0; n < (count + 3) / 4; n++) {\r
+ USB_REG(0)->TxData = *((uint32_t *) pData);\r
+ pData += 4;\r
+ }\r
+\r
+ USB_REG(0)->Ctrl = 0;\r
+\r
+ SIE_WriteCommand(CMD_SEL_EP(ENDPOINT_CONTROLEP + 1));\r
+ SIE_WriteCommand(CMD_VALID_BUF);\r
+}\r
+\r
+void HAL17XX_SetDeviceAddress(uint8_t Address)\r
+{\r
+ SIE_WriteCommandData(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | Address)); /* Don't wait for next */\r
+ SIE_WriteCommandData(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | Address)); /* Setup Status Phase */\r
+}\r
+\r
+void HAL17XX_USBConnect(uint32_t con)\r
+{\r
+ SIE_WriteCommandData(CMD_SET_DEV_STAT, DAT_WR_BYTE(con ? DEV_CON : 0));\r
+}\r
+\r
+void Endpoint_GetSetupPackage(uint8_t corenum, uint8_t *pData)\r
+{\r
+ memcpy(pData, SetupPackage, 8);\r
+}\r
+\r
+void SlaveEndpointISR()\r
+{\r
+ uint32_t PhyEP;\r
+ for (PhyEP = 0; PhyEP < 2; PhyEP++) /* Check Control Endpoints */\r
+ if (USB_REG(0)->EpIntSt & _BIT(PhyEP)) {\r
+ USB_REG(0)->EpIntClr = _BIT(PhyEP); /*-- Clear Interrupt Endpoint --*/\r
+\r
+ if (PhyEP == ENDPOINT_CONTROLEP) { /* Control OUT Endpoint */\r
+ uint32_t SIEEndpointStatus;\r
+\r
+ while ((USB_REG(0)->DevIntSt & CDFULL_INT) == 0) ;\r
+ SIEEndpointStatus = USB_REG(0)->CmdData;\r
+\r
+ if (SIEEndpointStatus & EP_SEL_STP) { /* Setup Packet */\r
+ SETUPReceived = true;\r
+ ReadControlEndpoint(SetupPackage);\r
+ }\r
+ else {\r
+ ReadControlEndpoint(usb_data_buffer[0]);\r
+ }\r
+ }\r
+ else { /* IN Endpoint */\r
+ isInReady = true;\r
+ if (DataInRemainCount) {\r
+ WriteControlEndpoint((uint8_t *) (usb_data_buffer[0] + DataInRemainOffset), DataInRemainCount);\r
+ }\r
+ else {\r
+ if (shortpacket) {\r
+ shortpacket = false;\r
+ WriteControlEndpoint((uint8_t *) (usb_data_buffer[0] + DataInRemainOffset), DataInRemainCount);\r
+ DataInRemainOffset = 0;\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+void Endpoint_Streaming(uint8_t corenum, uint8_t *buffer, uint16_t packetsize,\r
+ uint16_t totalpackets, uint16_t dummypackets)\r
+{\r
+ uint8_t PhyEP = endpointhandle(corenum)[endpointselected[corenum]];\r
+ uint16_t i;\r
+ dummypackets = dummypackets;\r
+ if (PhyEP & 1) {\r
+ for (i = 0; i < totalpackets; i++) {\r
+ while (!Endpoint_IsReadWriteAllowed(corenum)) ;\r
+ Endpoint_Write_Stream_LE(corenum, (void *) (buffer + i * packetsize), packetsize, NULL);\r
+ Endpoint_ClearIN(corenum);\r
+ }\r
+ }\r
+ else {\r
+ for (i = 0; i < totalpackets; i++) {\r
+ DcdDataTransfer(PhyEP, usb_data_buffer_OUT[corenum], packetsize);\r
+ Endpoint_ClearOUT(corenum);\r
+ while (!Endpoint_IsReadWriteAllowed(corenum)) ;\r
+ Endpoint_Read_Stream_LE(corenum, (void *) (buffer + i * packetsize), packetsize, NULL);\r
+ }\r
+ }\r
+}\r
+\r
+void DcdDataTransfer(uint8_t PhyEP, uint8_t *pData, uint32_t cnt)\r
+{\r
+ dmaDescriptor[PhyEP].BufferStartAddr = pData;\r
+ if (dmaDescriptor[PhyEP].Isochronous == 1) {// iso endpoint\r
+ if (PhyEP & 1) {// IN DIRECTION\r
+ uint8_t BufferCount;\r
+ for (BufferCount = 0; BufferCount < cnt / 0xFF; BufferCount++)\r
+ BufferAddressIso[BufferCount] = 0xFF;\r
+ BufferAddressIso[BufferCount] = (cnt % 0xFF);\r
+ if (cnt % 0xFF != 0) {\r
+ dmaDescriptor[PhyEP].BufferLength = cnt / 0xFF + 1;\r
+ }\r
+ else {\r
+ dmaDescriptor[PhyEP].BufferLength = cnt / 0xFF;\r
+ }\r
+ }\r
+ else { // OUT DIRECTION\r
+ dmaDescriptor[PhyEP].BufferLength = 1;\r
+ }\r
+ dmaDescriptor[PhyEP].IsoBufferAddr = (uint32_t) BufferAddressIso;\r
+ dmaDescriptor[PhyEP].Isochronous = 1;\r
+ dmaDescriptor[PhyEP].MaxPacketSize = 0;\r
+ }\r
+ else {\r
+ dmaDescriptor[PhyEP].BufferLength = cnt;\r
+ }\r
+ dmaDescriptor[PhyEP].Retired = 0;\r
+ dmaDescriptor[PhyEP].Status = 0;\r
+ dmaDescriptor[PhyEP].IsoPacketValid = 0;\r
+ dmaDescriptor[PhyEP].LSByteExtracted = 0;\r
+ dmaDescriptor[PhyEP].MSByteExtracted = 0;\r
+ dmaDescriptor[PhyEP].PresentCount = 0;\r
+\r
+ UDCA[PhyEP] = (uint32_t) &dmaDescriptor[PhyEP];\r
+ USB_REG(0)->EpDMAEn = _BIT(PhyEP);\r
+}\r
+\r
+void DMAEndTransferISR()\r
+{\r
+ uint32_t PhyEP;\r
+ uint32_t EoTIntSt = USB_REG(0)->EoTIntSt;\r
+\r
+ for (PhyEP = 2; PhyEP < USED_PHYSICAL_ENDPOINTS; PhyEP++) /* Check All Endpoints */\r
+ if ( EoTIntSt & _BIT(PhyEP) ) {\r
+ if ( IsOutEndpoint(PhyEP) ) { /* OUT Endpoint */\r
+ uint32_t tem = usb_data_buffer_OUT_index[0]; //just to clear warning\r
+ if (dmaDescriptor[PhyEP].Isochronous == 1) {// iso endpoint\r
+ SizeAudioTransfer = (BufferAddressIso[0]) & 0xFFFF;\r
+ ISO_Address = (uint8_t *) CALLBACK_HAL_GetISOBufferAddress(PhyEP / 2, &SizeAudioTransfer);\r
+ DcdDataTransfer(PhyEP, ISO_Address, 512);\r
+ }\r
+ usb_data_buffer_OUT_size[0] += dmaDescriptor[PhyEP].PresentCount;\r
+ if ((usb_data_buffer_OUT_size[0] + tem + dmaDescriptor[PhyEP].MaxPacketSize) > 512) {\r
+ USB_REG(0)->DMAIntEn &= ~(1 << 1);\r
+ }\r
+ }\r
+ else { /* IN Endpoint */\r
+ /* Should be left blank */\r
+ }\r
+ }\r
+ USB_REG(0)->EoTIntClr = EoTIntSt;\r
+}\r
+\r
+void DMANewTransferRequestISR()\r
+{\r
+ uint32_t PhyEP;\r
+ uint32_t NDDRIntSt = USB_REG(0)->NDDRIntSt;\r
+\r
+ for (PhyEP = 2; PhyEP < USED_PHYSICAL_ENDPOINTS; PhyEP++) /* Check All Endpoints */\r
+ if ( NDDRIntSt & _BIT(PhyEP) ) {\r
+ if ( IsOutEndpoint(PhyEP) ) { /* OUT Endpoint */\r
+ if (dmaDescriptor[PhyEP].Isochronous == 1) {// iso endpoint\r
+ DcdDataTransfer(PhyEP, ISO_Address, 512);\r
+ }\r
+ else {\r
+ uint16_t MaxPS = dmaDescriptor[PhyEP].MaxPacketSize;\r
+ if (usb_data_buffer_OUT_size[0] == 0) {\r
+ usb_data_buffer_OUT_index[0] = 0;\r
+ DcdDataTransfer(PhyEP, usb_data_buffer_OUT[0], MaxPS);\r
+\r
+ }\r
+ else {\r
+ uint32_t tem = usb_data_buffer_OUT_index[0]; //just to clear warning\r
+ DcdDataTransfer(PhyEP, &usb_data_buffer_OUT[0][usb_data_buffer_OUT_size[0] + tem], MaxPS);\r
+ }\r
+ }\r
+ }\r
+ else { /* IN Endpoint */\r
+ if (dmaDescriptor[PhyEP].Isochronous == 1) {\r
+ ISO_Address = (uint8_t *) CALLBACK_HAL_GetISOBufferAddress(PhyEP / 2, &SizeAudioTransfer);\r
+ if (SizeAudioTransfer > 0) {\r
+ DcdDataTransfer(PhyEP, ISO_Address, SizeAudioTransfer);\r
+ }\r
+ else {\r
+ DcdDataTransfer(PhyEP, ISO_Address, 512);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ USB_REG(0)->NDDRIntClr = NDDRIntSt;\r
+}\r
+\r
+// void DMASysErrISR()\r
+// {\r
+// uint32_t PhyEP;\r
+// uint32_t SysErrIntSt = LPC_USB->USBSysErrIntSt;\r
+// for (PhyEP = 2; PhyEP < USED_PHYSICAL_ENDPOINTS; PhyEP++) /* Check All Endpoints */\r
+// {\r
+// if ( SysErrIntSt & _BIT(PhyEP) )\r
+// {\r
+// if ( IsOutEndpoint(PhyEP) ) /* OUT Endpoint */\r
+// {\r
+// }\r
+// else /* IN Endpoint */\r
+// {\r
+// }\r
+// }\r
+// }\r
+// LPC_USB->USBSysErrIntClr = SysErrIntSt;\r
+// }\r
+\r
+void DcdIrqHandler(uint8_t DeviceID)\r
+{\r
+ uint32_t DevIntSt, DMAIntSt;\r
+\r
+ DevIntSt = USB_REG(DeviceID)->DevIntEn; /* Device Interrupt Status */\r
+ DevIntSt &= USB_REG(DeviceID)->DevIntEn;\r
+ \r
+ USB_REG(DeviceID)->DevIntClr = DevIntSt;\r
+\r
+ /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */\r
+ if (DevIntSt & DEV_STAT_INT) {\r
+ uint32_t SIEDeviceStatus;\r
+ SIE_WriteCommand(CMD_GET_DEV_STAT);\r
+ SIEDeviceStatus = SIE_ReadCommandData(DAT_GET_DEV_STAT); /* Device Status */\r
+ if (SIEDeviceStatus & DEV_RST) { /* Reset */\r
+ HAL_Reset(DeviceID);\r
+ USB_DeviceState[DeviceID] = DEVICE_STATE_Default;\r
+ Endpoint_ConfigureEndpoint(DeviceID, ENDPOINT_CONTROLEP, 0, ENDPOINT_DIR_OUT, USB_Device_ControlEndpointSize, 0);\r
+ Endpoint_ConfigureEndpoint(DeviceID, ENDPOINT_CONTROLEP, 0, ENDPOINT_DIR_IN, USB_Device_ControlEndpointSize, 0);\r
+ }\r
+ if (SIEDeviceStatus & DEV_CON_CH) { /* Connect change */\r
+ }\r
+ if (SIEDeviceStatus & DEV_SUS_CH) { /* Suspend/Resume */\r
+ if (SIEDeviceStatus & DEV_SUS) { /* Suspend */\r
+ }\r
+ else { /* Resume */\r
+ }\r
+ }\r
+ }\r
+\r
+ if (DevIntSt & FRAME_INT) {}\r
+\r
+ if (DevIntSt & ERR_INT) {\r
+ volatile uint32_t SIEErrorStatus;\r
+ SIE_WriteCommand(CMD_RD_ERR_STAT);\r
+ SIEErrorStatus = SIE_ReadCommandData(DAT_RD_ERR_STAT);\r
+ }\r
+\r
+ /* SLAVE mode : Endpoint's Slow Interrupt */\r
+ if ( (DevIntSt & EP_SLOW_INT) || (DevIntSt & EP_FAST_INT) ) {\r
+ SlaveEndpointISR();\r
+ }\r
+\r
+ /* DMA mode */\r
+ DMAIntSt = LPC_USB->DMAIntSt;\r
+ DMAIntSt &= USB_REG(DeviceID)->DMAIntEn;\r
+\r
+ if (DMAIntSt & EOT_INT) { /* End of Transfer Interrupt */\r
+ DMAEndTransferISR();\r
+ }\r
+\r
+ if (DMAIntSt & NDD_REQ_INT) { /* New DD Request Interrupt */\r
+ DMANewTransferRequestISR();\r
+\r
+ }\r
+\r
+ if (DMAIntSt & SYS_ERR_INT) { /* System Error Interrupt */\r
+ // DMASysErrISR();\r
+ USB_REG(DeviceID)->SysErrIntClr = USB_REG(DeviceID)->SysErrIntSt;\r
+ }\r
+}\r
+\r
+uint32_t Dummy_EPGetISOAddress(uint32_t EPNum, uint32_t *last_packet_size)\r
+{\r
+ return (uint32_t) iso_buffer;\r
+}\r
+\r
+#endif /*__LPC17XX__ || __LPC40XX__*/\r
--- /dev/null
+/*\r
+ * @brief USB Endpoint definitions for the LPC17xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_EndpointRW\r
+ * @defgroup Group_EndpointRW_LPC17xx Endpoint Data Reading and Writing (LPC17xx)\r
+ * @brief Endpoint data read/write definitions for the LPC architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing from and to endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointPrimitiveRW\r
+ * @defgroup Group_EndpointPrimitiveRW_LPC17xx Read/Write of Primitive Data Types (LPC17xx)\r
+ * @brief Endpoint primitive read/write definitions for the LPC17xx architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing of primitive data types\r
+ * from and to endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointPacketManagement\r
+ * @defgroup Group_EndpointPacketManagement_LPC17xx Endpoint Packet Management (LPC17xx)\r
+ * @brief Endpoint packet management definitions for the NXP LPC17xx architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to packet management of endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointManagement\r
+ * @defgroup Group_EndpointManagement_LPC17xx Endpoint Management (LPC17xx)\r
+ * @brief Endpoint management definitions for the LPC17xx architecture.\r
+ *\r
+ * Functions, macros and enums related to endpoint management when in USB Device mode. This\r
+ * module contains the endpoint management macros, as well as endpoint interrupt and data\r
+ * send/receive functions for various data types.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __ENDPOINT_LPC17XX_H__\r
+#define __ENDPOINT_LPC17XX_H__\r
+\r
+ #include "../EndpointCommon.h"\r
+\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ #if !defined(__DOXYGEN__)\r
+\r
+ #define ENDPOINT_DETAILS_MAXEP 6 /* Maximum of supported endpoint */\r
+ #define USED_PHYSICAL_ENDPOINTS (ENDPOINT_DETAILS_MAXEP * 2) /* This macro effect memory size of the DCD */\r
+ #define ENDPOINT_DETAILS_MAXEP0 ENDPOINT_DETAILS_MAXEP\r
+ #define ENDPOINT_DETAILS_MAXEP1 ENDPOINT_DETAILS_MAXEP\r
+\r
+extern volatile bool SETUPReceived;\r
+extern DMADescriptor dmaDescriptor[USED_PHYSICAL_ENDPOINTS];\r
+\r
+void SIE_WriteCommandData (uint32_t cmd, uint32_t val);\r
+\r
+void SIE_WriteCommand (uint32_t cmd);\r
+\r
+extern volatile bool isOutReceived;\r
+extern volatile bool isInReady;\r
+\r
+void WriteControlEndpoint(uint8_t *pData, uint32_t cnt);\r
+\r
+void ReadControlEndpoint(uint8_t *pData);\r
+\r
+void DcdDataTransfer(uint8_t PhyEP, uint8_t *pData, uint32_t cnt);\r
+\r
+void Endpoint_Streaming(uint8_t corenum, uint8_t *buffer, uint16_t packetsize,\r
+ uint16_t totalpackets, uint16_t dummypackets);\r
+\r
+void Endpoint_ClearEndpoints(uint8_t corenum);\r
+\r
+bool Endpoint_ConfigureEndpoint_Prv(uint8_t corenum,\r
+ const uint8_t Number,\r
+ const uint8_t UECFG0XData,\r
+ const uint8_t UECFG1XData);\r
+\r
+ #endif\r
+ /** \r
+ * @brief Configures the specified endpoint number with the given endpoint type, direction, bank size\r
+ * and banking mode. Once configured, the endpoint may be read from or written to, depending\r
+ * on its direction.\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param Number : Endpoint number to configure. This must be more than 0 and less than\r
+ * @ref ENDPOINT_TOTAL_ENDPOINTS.\r
+ *\r
+ * @param Type : Type of endpoint to configure, a \c EP_TYPE_* mask. Not all endpoint types\r
+ * are available on Low Speed USB devices - refer to the USB 2.0 specification.\r
+ *\r
+ * @param Direction : Endpoint data direction, either @ref ENDPOINT_DIR_OUT or @ref ENDPOINT_DIR_IN.\r
+ * All endpoints (except Control type) are unidirectional - data may only be read\r
+ * from or written to the endpoint bank based on its direction, not both.\r
+ *\r
+ * @param Size : Size of the endpoint's bank, where packets are stored before they are transmitted\r
+ * to the USB host, or after they have been received from the USB host (depending on\r
+ * the endpoint's data direction). The bank size must indicate the maximum packet size\r
+ * that the endpoint can handle.\r
+ *\r
+ * @param Banks : Number of banks to use for the endpoint being configured, an \c ENDPOINT_BANK_* mask.\r
+ * More banks uses more USB DPRAM, but offers better performance. Isochronous type\r
+ * endpoints <b>must</b> have at least two banks.\r
+ * @return Boolean \c true if the configuration succeeded, \c false otherwise.\r
+ */\r
+/*static inline */ bool Endpoint_ConfigureEndpoint(uint8_t corenum,\r
+ const uint8_t Number,\r
+ const uint8_t Type,\r
+ const uint8_t Direction,\r
+ const uint16_t Size,\r
+ const uint8_t Banks) /*ATTR_ALWAYS_INLINE*/;\r
+\r
+static inline uint16_t USB_Device_GetFrameNumber(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline uint16_t USB_Device_GetFrameNumber(void)\r
+{\r
+ uint32_t val;\r
+\r
+ SIE_WriteCommand(CMD_RD_FRAME);\r
+ val = SIE_ReadCommandData(DAT_RD_FRAME);\r
+ val = val | (SIE_ReadCommandData(DAT_RD_FRAME) << 8);\r
+\r
+ return val;\r
+}\r
+\r
+static inline void USB_Device_SetDeviceAddress(uint8_t corenum, const uint8_t Address) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetDeviceAddress(uint8_t corenum, const uint8_t Address)\r
+{\r
+ SIE_WriteCommandData(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | Address));\r
+ SIE_WriteCommandData(CMD_SET_ADDR, DAT_WR_BYTE(DEV_EN | Address));\r
+}\r
+\r
+/**\r
+ * @brief Resets the endpoint bank FIFO. This clears all the endpoint banks and resets the USB controller's\r
+ * data In and Out pointers to the bank's contents.\r
+ *\r
+ * @param EndpointNumber : Endpoint number whose FIFO buffers are to be reset.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber)\r
+{}\r
+\r
+/**\r
+ * @brief Enables the currently selected endpoint so that data can be sent and received through it to\r
+ * and from a host.\r
+ *\r
+ * @note Endpoints must first be configured properly via @ref Endpoint_ConfigureEndpoint().\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_EnableEndpoint(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_EnableEndpoint(void)\r
+{}\r
+\r
+/**\r
+ * @brief Disables the currently selected endpoint so that data cannot be sent and received through it\r
+ * to and from a host.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_DisableEndpoint(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_DisableEndpoint(void)\r
+{}\r
+\r
+/**\r
+ * @brief Determines if the currently selected endpoint is enabled, but not necessarily configured\r
+ * @return Boolean \c true if the currently selected endpoint is enabled, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsEnabled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsEnabled(void)\r
+{\r
+ return true;\r
+}\r
+\r
+/**\r
+ * @brief Retrieves the number of busy banks in the currently selected endpoint, which have been queued for\r
+ * transmission via the @ref Endpoint_ClearIN() command, or are awaiting acknowledgement via the\r
+ * @ref Endpoint_ClearOUT() command.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ *\r
+ * @return Total number of busy banks in the selected endpoint.\r
+ */\r
+static inline uint8_t Endpoint_GetBusyBanks(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline uint8_t Endpoint_GetBusyBanks(void)\r
+{\r
+ return 0;\r
+}\r
+\r
+/** @brief Aborts all pending IN transactions on the currently selected endpoint, once the bank\r
+ * has been queued for transmission to the host via @ref Endpoint_ClearIN(). This function\r
+ * will terminate all queued transactions, resetting the endpoint banks ready for a new\r
+ * packet.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_AbortPendingIN(void)\r
+{}\r
+\r
+/**\r
+ * @brief Determines if the currently selected endpoint is configured.\r
+ *\r
+ * @return Boolean \c true if the currently selected endpoint has been configured, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsConfigured(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsConfigured(void)\r
+{\r
+ return true;\r
+}\r
+\r
+/**\r
+ * @brief Returns a mask indicating which INTERRUPT type endpoints have interrupted - i.e. their\r
+ * interrupt duration has elapsed. Which endpoints have interrupted can be determined by\r
+ * masking the return value against <tt>(1 << <i>{Endpoint Number}</i>)</tt>.\r
+ *\r
+ * @return Mask whose bits indicate which endpoints have interrupted.\r
+ */\r
+static inline uint8_t Endpoint_GetEndpointInterrupts(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline uint8_t Endpoint_GetEndpointInterrupts(void)\r
+{\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * @brief Determines if the specified endpoint number has interrupted (valid only for INTERRUPT type\r
+ * endpoints).\r
+ * @param EndpointNumber : Index of the endpoint whose interrupt flag should be tested\r
+ * @return Boolean \c true if the specified endpoint has interrupted, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber) ATTR_WARN_UNUSED_RESULT\r
+ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber)\r
+{\r
+ return (Endpoint_GetEndpointInterrupts() & (1 << EndpointNumber)) ? true : false;\r
+}\r
+\r
+/**\r
+ * @brief Indicates the number of bytes currently stored in the current endpoint's selected bank.\r
+ *\r
+ * @note The return width of this function may differ, depending on the maximum endpoint bank size\r
+ * of the selected LPC model.\r
+ * @ingroup Group_EndpointRW_LPC17xx\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Total number of bytes in the currently selected Endpoint's FIFO buffer\r
+ */\r
+static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum)\r
+{\r
+ if (endpointselected == ENDPOINT_CONTROLEP) {\r
+ return usb_data_buffer_size[corenum];\r
+ }\r
+ else {\r
+ // return (dmaDescriptor[ endpointhandle[endpointselected] ].PresentCount);\r
+ return usb_data_buffer_OUT_size[corenum];\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Determines if the selected IN endpoint is ready for a new packet to be sent to the host.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC17xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Boolean \c true if the current endpoint is ready for an IN packet, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsINReady(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsINReady(uint8_t corenum)\r
+{\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+\r
+ return isInReady;\r
+ }\r
+ else {\r
+ uint8_t SelEP_Data;\r
+ if (dmaDescriptor[endpointhandle(corenum)[endpointselected[corenum]]].Retired == true) {\r
+ SIE_WriteCommand(CMD_SEL_EP(endpointhandle(corenum)[endpointselected[corenum]]) );\r
+ SelEP_Data = SIE_ReadCommandData(DAT_SEL_EP(endpointhandle(corenum)[endpointselected[corenum]]) );\r
+ if ((SelEP_Data & 1) == 0) {\r
+ return true;\r
+ }\r
+ }\r
+ return false;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Determines if the selected OUT endpoint has received new packet from the host.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC17xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Boolean \c true if current endpoint is has received an OUT packet, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsOUTReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsOUTReceived(uint8_t corenum)\r
+{\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+\r
+ return isOutReceived;\r
+ }\r
+ else {\r
+ return (dmaDescriptor[endpointhandle(corenum)[endpointselected[corenum]]].Retired &&\r
+ (dmaDescriptor[endpointhandle(corenum)[endpointselected[corenum]]].Status == 2 ||\r
+ dmaDescriptor[endpointhandle(corenum)[endpointselected[corenum]]].Status == 3)\r
+ ) ? true : false;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Determines if the current CONTROL type endpoint has received a SETUP packet.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC17xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Boolean \c true if the selected endpoint has received a SETUP packet, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsSETUPReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsSETUPReceived(uint8_t corenum)\r
+{\r
+ return SETUPReceived;\r
+}\r
+\r
+/**\r
+ * @brief Clears a received SETUP packet on the currently selected CONTROL type endpoint, freeing up the\r
+ * endpoint for the next packet.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC17xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ * @note This is not applicable for non CONTROL type endpoints.\r
+ */\r
+static inline void Endpoint_ClearSETUP(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearSETUP(uint8_t corenum)\r
+{\r
+ SETUPReceived = FALSE;\r
+ usb_data_buffer_index[corenum] = 0;\r
+ usb_data_buffer_size[corenum] = 0;\r
+ SIE_WriteCommand(CMD_SEL_EP(ENDPOINT_CONTROLEP));\r
+ SIE_WriteCommand(CMD_CLR_BUF);\r
+}\r
+\r
+/**\r
+ * @brief Sends an IN packet to the host on the currently selected endpoint, freeing up the endpoint for the\r
+ * next packet and switching to the alternative endpoint bank if double banked.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC17xx\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_ClearIN(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearIN(uint8_t corenum)\r
+{\r
+ uint8_t PhyEP = (endpointselected[corenum] == ENDPOINT_CONTROLEP ? 1 : endpointhandle(corenum)[endpointselected[corenum]]);\r
+\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ WriteControlEndpoint(usb_data_buffer[corenum], usb_data_buffer_index[corenum]);\r
+ usb_data_buffer_index[corenum] = 0;\r
+ usb_data_buffer_size[corenum] = 0;\r
+ }\r
+ else {\r
+ DcdDataTransfer(PhyEP, usb_data_buffer_IN[corenum], usb_data_buffer_IN_index[corenum]);\r
+ LPC_USB->DMARSet = _BIT(PhyEP);\r
+ usb_data_buffer_IN_index[corenum] = 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Acknowledges an OUT packet to the host on the currently selected endpoint, freeing up the endpoint\r
+ * for the next packet and switching to the alternative endpoint bank if double banked.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC17xx\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_ClearOUT(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearOUT(uint8_t corenum)\r
+{\r
+ usb_data_buffer_index[corenum] = 0;\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) { /* Control only */\r
+ SIE_WriteCommand(CMD_SEL_EP(ENDPOINT_CONTROLEP));\r
+ SIE_WriteCommand(CMD_CLR_BUF);\r
+ isOutReceived = false;\r
+ }\r
+ else {\r
+ usb_data_buffer_OUT_index[corenum] = 0;\r
+ usb_data_buffer_OUT_size[corenum] = 0;\r
+ dmaDescriptor[endpointhandle(corenum)[endpointselected[corenum]]].Status = 0;\r
+ LPC_USB->DMAIntEn |= (1 << 1);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Stalls the current endpoint, indicating to the host that a logical problem occurred with the\r
+ * indicated endpoint and that the current transfer sequence should be aborted. This provides a\r
+ * way for devices to indicate invalid commands to the host so that the current transfer can be\r
+ * aborted and the host can begin its own recovery sequence.\r
+ *\r
+ * The currently selected endpoint remains stalled until either the @ref Endpoint_ClearStall() macro\r
+ * is called, or the host issues a CLEAR FEATURE request to the device for the currently selected\r
+ * endpoint.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC17xx\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+// static inline void Endpoint_StallTransaction(void) ATTR_ALWAYS_INLINE;\r
+void Endpoint_StallTransaction(uint8_t corenum);\r
+\r
+/**\r
+ * @brief Clears the STALL condition on the currently selected endpoint.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC17xx\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_ClearStall(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearStall(uint8_t corenum)\r
+{\r
+ uint8_t PhysicalEp = endpointhandle(corenum)[endpointselected[corenum]] + (endpointselected[corenum] == ENDPOINT_CONTROLEP ? 1 : 0);\r
+\r
+ HAL_DisableUSBInterrupt(corenum);\r
+ SIE_WriteCommandData(CMD_SET_EP_STAT(PhysicalEp), DAT_WR_BYTE(0));\r
+ HAL_EnableUSBInterrupt(corenum);\r
+}\r
+\r
+/**\r
+ * @brief Determines if the currently selected endpoint is stalled, false otherwise.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC17xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Boolean \c true if the currently selected endpoint is stalled, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsStalled(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsStalled(uint8_t corenum)\r
+{\r
+ bool isStalled;\r
+\r
+ HAL_DisableUSBInterrupt(corenum);\r
+ SIE_WriteCommand(CMD_SEL_EP(endpointhandle(corenum)[endpointselected[corenum]]) );\r
+ isStalled = SIE_ReadCommandData(DAT_SEL_EP(endpointhandle(corenum)[endpointselected[corenum]]) ) & EP_SEL_ST ? true : false;\r
+ HAL_EnableUSBInterrupt(corenum);\r
+\r
+ return isStalled; /* Device Status */\r
+}\r
+\r
+/** Resets the data toggle of the currently selected endpoint. */\r
+static inline void Endpoint_ResetDataToggle(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ResetDataToggle(uint8_t corenum)\r
+{}\r
+\r
+ #if (!defined(FIXED_CONTROL_ENDPOINT_SIZE) || defined(__DOXYGEN__))\r
+extern uint8_t USB_Device_ControlEndpointSize;\r
+ #else\r
+ #define USB_Device_ControlEndpointSize FIXED_CONTROL_ENDPOINT_SIZE\r
+ #endif\r
+\r
+/**\r
+ * @brief Completes the status stage of a control transfer on a CONTROL type endpoint automatically,\r
+ * with respect to the data direction. This is a convenience function which can be used to\r
+ * simplify user control request handling.\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+void Endpoint_ClearStatusStage(uint8_t corenum);\r
+\r
+uint8_t Endpoint_WaitUntilReady(void);\r
+\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Device definitions for the LPC18xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_Device\r
+ * @defgroup Group_Device_LPC18xx Device Definitions and General Functions (LPC18xx)\r
+ * @brief Device Definitions and General Functions for the LPC architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to usb device.\r
+ *\r
+ * @{\r
+ */\r
+ \r
+#ifndef __USBDEVICE_LPC18XX_H__\r
+#define __USBDEVICE_LPC18XX_H__\r
+\r
+/* Includes: */\r
+ #include "../../../../../Common/Common.h"\r
+ #include "../../USBController.h"\r
+ #include "../../StdDescriptors.h"\r
+ #include "../../USBInterrupt.h"\r
+ #include "../../HAL/HAL.h"\r
+\r
+ #if defined(USB_DEVICE_ROM_DRIVER)\r
+ #include "../USBRom/usbd_rom_api.h"\r
+ #endif\r
+\r
+/* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+/* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ #if (defined(USE_RAM_DESCRIPTORS) && defined(USE_EEPROM_DESCRIPTORS))\r
+ #error USE_RAM_DESCRIPTORS and USE_EEPROM_DESCRIPTORS are mutually exclusive.\r
+ #endif\r
+\r
+/* Public Interface - May be used in end-application: */\r
+/* Macros: */\r
+\r
+/** Mask for the Options parameter of the @ref USB_Init() function. This indicates that the\r
+ * USB interface should be initialized in full speed (12Mb/s) mode.\r
+ */\r
+ #define USB_DEVICE_OPT_FULLSPEED (0 << 0)\r
+\r
+ #if (!defined(NO_INTERNAL_SERIAL) && defined(__DOXYGEN__))\r
+/** String descriptor index for the device's unique serial number string descriptor within the device.\r
+ * This unique serial number is used by the host to associate resources to the device (such as drivers or COM port\r
+ * number allocations) to a device regardless of the port it is plugged in to on the host. Some microcontrollers contain\r
+ * a unique serial number internally, and setting the device descriptors serial number string index to this value\r
+ * will cause it to use the internal serial number.\r
+ *\r
+ * On unsupported devices, this will evaluate to @ref NO_DESCRIPTOR and so will force the host to create a pseudo-serial\r
+ * number for the device.\r
+ */\r
+ #define USE_INTERNAL_SERIAL 0xDC\r
+\r
+/** Length of the device's unique internal serial number, in bits, if present on the selected microcontroller\r
+ * model.\r
+ */\r
+ #define INTERNAL_SERIAL_LENGTH_BITS 80\r
+\r
+/** Start address of the internal serial number, in the appropriate address space, if present on the selected microcontroller\r
+ * model.\r
+ */\r
+ #define INTERNAL_SERIAL_START_ADDRESS 0x0E\r
+ #else\r
+ #define USE_INTERNAL_SERIAL NO_DESCRIPTOR\r
+\r
+ #define INTERNAL_SERIAL_LENGTH_BITS 0\r
+ #define INTERNAL_SERIAL_START_ADDRESS 0\r
+ #endif \r
+ \r
+/* Function Prototypes: */\r
+/**\r
+ * @brief Sends a Remote Wakeup request to the host. This signals to the host that the device should\r
+ * be taken out of suspended mode, and communications should resume.\r
+ *\r
+ * Typically, this is implemented so that HID devices (mice, keyboards, etc.) can wake up the\r
+ * host computer when the host has suspended all USB devices to enter a low power state.\r
+ *\r
+ * @note This macro should only be used if the device has indicated to the host that it\r
+ * supports the Remote Wakeup feature in the device descriptors, and should only be\r
+ * issued if the host is currently allowing remote wakeup events from the device (i.e.,\r
+ * the @ref USB_Device_RemoteWakeupEnabled flag is set). When the \c NO_DEVICE_REMOTE_WAKEUP\r
+ * compile time option is used, this macro is unavailable.\r
+ * \n\n\r
+ *\r
+ * @note The USB clock must be running for this function to operate. If the stack is initialized with\r
+ * the @ref USB_OPT_MANUAL_PLL option enabled, the user must ensure that the PLL is running\r
+ * before attempting to call this function.\r
+ *\r
+ * \see @ref Group_StdDescriptors for more information on the RMWAKEUP feature and device descriptors.\r
+ * @return Nothing.\r
+ */\r
+void USB_Device_SendRemoteWakeup(void);\r
+\r
+/* Inline Functions: */\r
+/**\r
+ * @brief Returns the current USB frame number, when in device mode. Every millisecond the USB bus is active (i.e. enumerated to a host)\r
+ * the frame number is incremented by one.\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Current frame number.\r
+ */\r
+static inline uint16_t USB_Device_GetFrameNumber(uint8_t corenum) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline uint16_t USB_Device_GetFrameNumber(uint8_t corenum)\r
+{\r
+ return USB_REG(corenum)->FRINDEX_D;\r
+}\r
+\r
+ #if !defined(NO_SOF_EVENTS)\r
+/**\r
+ * @brief Enables the device mode Start Of Frame events. When enabled, this causes the\r
+ * @ref EVENT_USB_Device_StartOfFrame() event to fire once per millisecond, synchronized to the USB bus,\r
+ * at the start of each USB frame when enumerated in device mode.\r
+ *\r
+ * @note Not available when the \c NO_SOF_EVENTS compile time token is defined.\r
+ * @return Nothing.\r
+ */\r
+static inline void USB_Device_EnableSOFEvents(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_EnableSOFEvents(void)\r
+{}\r
+\r
+/**\r
+ * @brief Disables the device mode Start Of Frame events. When disabled, this stops the firing of the\r
+ * @ref EVENT_USB_Device_StartOfFrame() event when enumerated in device mode.\r
+ *\r
+ * @note Not available when the \c NO_SOF_EVENTS compile time token is defined.\r
+ * @return Nothing.\r
+ */\r
+static inline void USB_Device_DisableSOFEvents(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_DisableSOFEvents(void)\r
+{}\r
+\r
+ #endif\r
+\r
+/* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+/* Inline Functions: */\r
+ #if defined(USB_DEVICE_OPT_LOWSPEED)\r
+static inline void USB_Device_SetLowSpeed(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetLowSpeed(void)\r
+{\r
+ // UDCON |= (1 << LSM);\r
+}\r
+\r
+static inline void USB_Device_SetFullSpeed(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetFullSpeed(void)\r
+{\r
+ // UDCON &= ~(1 << LSM);\r
+}\r
+\r
+ #endif\r
+\r
+/**\r
+ * @brief Set current USB device address.\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param Address : new USB device address.\r
+ * @return Nothing.\r
+ */\r
+static inline void USB_Device_SetDeviceAddress(uint8_t corenum, const uint8_t Address) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void USB_Device_SetDeviceAddress(uint8_t corenum, const uint8_t Address)\r
+{\r
+ USB_REG(corenum)->DEVICEADDR = USBDEV_ADDR(Address);\r
+ USB_REG(corenum)->DEVICEADDR |= USBDEV_ADDR_AD;\r
+}\r
+\r
+/**\r
+ * @brief Get status of USB address whether it is set or not.\r
+ * @return true if set\r
+ * otherwise false.\r
+ */\r
+static inline bool USB_Device_IsAddressSet(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline bool USB_Device_IsAddressSet(void)\r
+{\r
+ return true; /* temporarily */\r
+}\r
+\r
+ #if (USE_INTERNAL_SERIAL != NO_DESCRIPTOR)\r
+static inline void USB_Device_GetSerialString(uint16_t *const UnicodeString) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+static inline void USB_Device_GetSerialString(uint16_t *const UnicodeString)\r
+{\r
+ uint_reg_t CurrentGlobalInt = GetGlobalInterruptMask();\r
+ GlobalInterruptDisable();\r
+\r
+ uint8_t SigReadAddress = INTERNAL_SERIAL_START_ADDRESS;\r
+\r
+ for (uint8_t SerialCharNum = 0; SerialCharNum < (INTERNAL_SERIAL_LENGTH_BITS / 4); SerialCharNum++) {\r
+ uint8_t SerialByte = boot_signature_byte_get(SigReadAddress);\r
+\r
+ if (SerialCharNum & 0x01) {\r
+ SerialByte >>= 4;\r
+ SigReadAddress++;\r
+ }\r
+\r
+ SerialByte &= 0x0F;\r
+\r
+ UnicodeString[SerialCharNum] = cpu_to_le16((SerialByte >= 10) ?\r
+ (('A' - 10) + SerialByte) : ('0' + SerialByte));\r
+ }\r
+\r
+ SetGlobalInterruptMask(CurrentGlobalInt);\r
+}\r
+\r
+ #endif\r
+\r
+ #endif\r
+\r
+/* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Endpoint definitions for the LPC18xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#if (defined(__LPC18XX__) || defined(__LPC43XX__)) && defined(USB_CAN_BE_DEVICE)\r
+#include "../../Endpoint.h"\r
+#include <string.h>\r
+\r
+#if defined(USB_DEVICE_ROM_DRIVER)\r
+PRAGMA_ALIGN_2048\r
+uint8_t usb_RomDriver_buffer[ROMDRIVER_MEM_SIZE] ATTR_ALIGNED(2048) __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_4\r
+uint8_t usb_RomDriver_MSC_buffer[ROMDRIVER_MSC_MEM_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_4\r
+uint8_t usb_RomDriver_CDC_buffer[ROMDRIVER_CDC_MEM_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+/** Endpoint IN buffer, used for DMA operation */\r
+PRAGMA_ALIGN_4\r
+uint8_t UsbdCdc_EPIN_buffer[CDC_MAX_BULK_EP_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+/** Endpoint OUT buffer, used for DMA operation */\r
+PRAGMA_ALIGN_4\r
+uint8_t UsbdCdc_EPOUT_buffer[CDC_MAX_BULK_EP_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_4\r
+uint8_t usb_RomDriver_HID_buffer[ROMDRIVER_HID_MEM_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+\r
+#endif\r
+\r
+#define STREAM_TDs 16\r
+\r
+PRAGMA_ALIGN_2048\r
+volatile DeviceQueueHead dQueueHead0[USED_PHYSICAL_ENDPOINTS0] ATTR_ALIGNED(2048) __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_2048\r
+volatile DeviceQueueHead dQueueHead1[USED_PHYSICAL_ENDPOINTS1] ATTR_ALIGNED(2048) __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_32\r
+DeviceTransferDescriptor dTransferDescriptor0[USED_PHYSICAL_ENDPOINTS0] ATTR_ALIGNED(32) __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_32\r
+DeviceTransferDescriptor dTransferDescriptor1[USED_PHYSICAL_ENDPOINTS1] ATTR_ALIGNED(32) __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_32\r
+DeviceTransferDescriptor dStreamTD0[STREAM_TDs] ATTR_ALIGNED(32) __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_32\r
+DeviceTransferDescriptor dStreamTD1[STREAM_TDs] ATTR_ALIGNED(32) __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_4\r
+uint8_t iso_buffer[512] ATTR_ALIGNED(4);\r
+volatile DeviceQueueHead * const dQueueHead[LPC18_43_MAX_USB_CORE] = {dQueueHead0, dQueueHead1};\r
+DeviceTransferDescriptor * const dTransferDescriptor[LPC18_43_MAX_USB_CORE] = {dTransferDescriptor0, dTransferDescriptor1};\r
+DeviceTransferDescriptor * const dStreamTD_Tbl[LPC18_43_MAX_USB_CORE] = {dStreamTD0, dStreamTD1};\r
+\r
+typedef struct {\r
+ uint32_t stream_buffer_address,\r
+ stream_dummy_buffer_address,\r
+ stream_remain_packets,\r
+ stream_dummy_packets,\r
+ stream_packet_size,\r
+ stream_total_packets;\r
+} STREAM_VAR_t;\r
+\r
+static STREAM_VAR_t Stream_Variable[LPC18_43_MAX_USB_CORE];\r
+\r
+PRAGMA_WEAK(CALLBACK_HAL_GetISOBufferAddress, Dummy_EPGetISOAddress)\r
+uint32_t CALLBACK_HAL_GetISOBufferAddress(const uint32_t EPNum, uint32_t *last_packet_size) ATTR_WEAK ATTR_ALIAS(\r
+ Dummy_EPGetISOAddress);\r
+\r
+/* Device transfer completed event\r
+ * Event is required for using the device stack with any RTOS\r
+ */\r
+PRAGMA_WEAK(EVENT_USB_Device_TransferComplete,Dummy_EVENT_USB_Device_TransferComplete)\r
+void EVENT_USB_Device_TransferComplete(int logicalEP, int xfer_in) ATTR_WEAK ATTR_ALIAS(Dummy_EVENT_USB_Device_TransferComplete);\r
+\r
+void DcdInsertTD(uint32_t head, uint32_t newtd);\r
+\r
+void DcdPrepareTD(DeviceTransferDescriptor *pDTD, uint8_t *pData, uint32_t length, uint8_t IOC);\r
+\r
+void HAL_Reset(uint8_t corenum)\r
+{\r
+ uint32_t i;\r
+ IP_USBHS_001_T * USB_Reg;\r
+ USB_Reg = USB_REG(corenum);\r
+\r
+ /* disable all EPs */\r
+ USB_Reg->ENDPTCTRL[0] &= ~(ENDPTCTRL_RxEnable | ENDPTCTRL_TxEnable);\r
+ USB_Reg->ENDPTCTRL[1] &= ~(ENDPTCTRL_RxEnable | ENDPTCTRL_TxEnable);\r
+ USB_Reg->ENDPTCTRL[2] &= ~(ENDPTCTRL_RxEnable | ENDPTCTRL_TxEnable);\r
+ USB_Reg->ENDPTCTRL[3] &= ~(ENDPTCTRL_RxEnable | ENDPTCTRL_TxEnable);\r
+ if (corenum == 0) {\r
+ USB_Reg->ENDPTCTRL[4] &= ~(ENDPTCTRL_RxEnable | ENDPTCTRL_TxEnable);\r
+ USB_Reg->ENDPTCTRL[5] &= ~(ENDPTCTRL_RxEnable | ENDPTCTRL_TxEnable);\r
+ }\r
+\r
+ /* Clear all pending interrupts */\r
+ USB_Reg->ENDPTNAK = 0xFFFFFFFF;\r
+ USB_Reg->ENDPTNAKEN = 0;\r
+ USB_Reg->USBSTS_D = 0xFFFFFFFF;\r
+ USB_Reg->ENDPTSETUPSTAT = USB_Reg->ENDPTSETUPSTAT;\r
+ USB_Reg->ENDPTCOMPLETE = USB_Reg->ENDPTCOMPLETE;\r
+ while (USB_Reg->ENDPTPRIME) ; /* Wait until all bits are 0 */\r
+ USB_Reg->ENDPTFLUSH = 0xFFFFFFFF;\r
+ while (USB_Reg->ENDPTFLUSH) ; /* Wait until all bits are 0 */\r
+\r
+ /* Set the interrupt Threshold control interval to 0 */\r
+ USB_Reg->USBCMD_D &= ~0x00FF0000;\r
+\r
+ /* Configure the Endpoint List Address */\r
+ /* make sure it in on 64 byte boundary !!! */\r
+ /* init list address */\r
+ USB_Reg->ENDPOINTLISTADDR = (uint32_t) dQueueHead[corenum];\r
+\r
+ /* Enable interrupts: USB interrupt, error, port change, reset, suspend, NAK interrupt */\r
+ USB_Reg->USBINTR_D = USBINTR_D_UsbIntEnable | USBINTR_D_UsbErrorIntEnable |\r
+ USBINTR_D_PortChangeIntEnable | USBINTR_D_UsbResetEnable |\r
+ USBINTR_D_SuspendEnable | USBINTR_D_NAKEnable | USBINTR_D_SofReceivedEnable;\r
+\r
+ USB_Device_SetDeviceAddress(corenum, 0);\r
+\r
+ endpointselected[corenum] = 0;\r
+ for (i = 0; i < ENDPOINT_TOTAL_ENDPOINTS(corenum); i++)\r
+ endpointhandle(corenum)[i] = 0;\r
+\r
+ usb_data_buffer_size[corenum] = 0;\r
+ usb_data_buffer_index[corenum] = 0;\r
+\r
+ usb_data_buffer_OUT_size[corenum] = 0;\r
+ usb_data_buffer_OUT_index[corenum] = 0;\r
+\r
+ // usb_data_buffer_IN_size = 0;\r
+ usb_data_buffer_IN_index[corenum] = 0;\r
+ Stream_Variable[corenum].stream_total_packets = 0;\r
+}\r
+\r
+bool Endpoint_ConfigureEndpoint(uint8_t corenum, const uint8_t Number, const uint8_t Type,\r
+ const uint8_t Direction, const uint16_t Size, const uint8_t Banks)\r
+{\r
+ uint8_t * ISO_Address;\r
+ volatile DeviceQueueHead * pdQueueHead;\r
+ uint32_t PhyEP = 2 * Number + (Direction == ENDPOINT_DIR_OUT ? 0 : 1);\r
+ __IO uint32_t * pEndPointCtrl = &ENDPTCTRL_REG(corenum, Number);\r
+ uint32_t EndPtCtrl = *pEndPointCtrl;\r
+ \r
+ pdQueueHead = &(dQueueHead[corenum][PhyEP]);\r
+ memset((void *) pdQueueHead, 0, sizeof(DeviceQueueHead) );\r
+ \r
+ pdQueueHead->MaxPacketSize = Size & 0x3ff;\r
+ pdQueueHead->IntOnSetup = 1;\r
+ pdQueueHead->ZeroLengthTermination = 1;\r
+ pdQueueHead->overlay.NextTD = LINK_TERMINATE;\r
+\r
+ if (Direction == ENDPOINT_DIR_OUT) {\r
+ EndPtCtrl &= ~0x0000FFFF;\r
+ EndPtCtrl |= ((Type << 2) & ENDPTCTRL_RxType) | ENDPTCTRL_RxEnable | ENDPTCTRL_RxToggleReset;\r
+ if (Type == EP_TYPE_ISOCHRONOUS) {\r
+ uint32_t size = 0;\r
+ *pEndPointCtrl = (Type << 2); // TODO dummy to let DcdDataTransfer() knows iso transfer\r
+ ISO_Address = (uint8_t *) CALLBACK_HAL_GetISOBufferAddress(Number, &size);\r
+ DcdDataTransfer(corenum, PhyEP, ISO_Address, USB_DATA_BUFFER_TEM_LENGTH);\r
+ }\r
+ else {\r
+ USB_REG(corenum)->ENDPTNAKEN |= (1 << EP_Physical2BitPosition(PhyEP));\r
+ }\r
+ }\r
+ else { /* ENDPOINT_DIR_IN */\r
+ EndPtCtrl &= ~0xFFFF0000;\r
+ EndPtCtrl |= ((Type << 18) & ENDPTCTRL_TxType) | ENDPTCTRL_TxEnable | ENDPTCTRL_TxToggleReset;\r
+ if (Type == EP_TYPE_ISOCHRONOUS) {\r
+ uint32_t size = 0;\r
+ *pEndPointCtrl = (Type << 18); // TODO dummy to let DcdDataTransfer() knows iso transfer\r
+ ISO_Address = (uint8_t *) CALLBACK_HAL_GetISOBufferAddress(Number, &size);\r
+ DcdDataTransfer(corenum, PhyEP, ISO_Address, size);\r
+ }\r
+ }\r
+ *pEndPointCtrl = EndPtCtrl;\r
+\r
+ endpointhandle(corenum)[Number] = (Number == ENDPOINT_CONTROLEP) ? ENDPOINT_CONTROLEP : PhyEP;\r
+ return true;\r
+}\r
+\r
+void Endpoint_Streaming(uint8_t corenum, uint8_t *buffer, uint16_t packetsize,\r
+ uint16_t totalpackets, uint16_t dummypackets)\r
+{\r
+ uint8_t PhyEP = endpointhandle(corenum)[endpointselected[corenum]];\r
+ uint16_t i;\r
+ volatile DeviceQueueHead * pdQueueHead;\r
+#if 0\r
+ for (i = 0; i < totalpackets; i++) {\r
+ DcdDataTransfer(corenum, PhyEP, (uint8_t *) (buffer + i * packetsize), packetsize);\r
+ while (!(\r
+ (dQueueHead[PhyEP].overlay.NextTD & LINK_TERMINATE)\r
+ && (dQueueHead[PhyEP].overlay.Active == 0)\r
+ )\r
+ ) ;\r
+ }\r
+ for (i = 0; i < dummypackets; i++) {\r
+ DcdDataTransfer(corenum, PhyEP, buffer, packetsize);\r
+ while (!(\r
+ (dQueueHead[PhyEP].overlay.NextTD & LINK_TERMINATE)\r
+ && (dQueueHead[PhyEP].overlay.Active == 0)\r
+ )\r
+ ) ;\r
+ }\r
+#else\r
+ STREAM_VAR_t * current_stream = &Stream_Variable[corenum];\r
+ DeviceTransferDescriptor *dStreamTD = dStreamTD_Tbl[corenum];\r
+ uint16_t cnt = 0;\r
+ dummypackets = dummypackets;\r
+ while ( USB_REG(corenum)->ENDPTSTAT & _BIT(EP_Physical2BitPosition(PhyEP) ) ) { /* Endpoint is already primed */\r
+ }\r
+\r
+ for (i = 0; i < totalpackets; i++) {\r
+ uint8_t ioc;\r
+ if (i == STREAM_TDs) {\r
+ break;\r
+ }\r
+ if ((i == totalpackets - 1) || (i == STREAM_TDs - 1)) {\r
+ ioc = 1;\r
+ }\r
+ else {\r
+ ioc = 0;\r
+ }\r
+\r
+ DcdPrepareTD(&dStreamTD[i], (uint8_t *) (buffer + i * packetsize), packetsize, ioc);\r
+ if (i > 0) {\r
+ DcdInsertTD((uint32_t) dStreamTD, (uint32_t) &dStreamTD[i]);\r
+ }\r
+ cnt++;\r
+ }\r
+\r
+ if (STREAM_TDs < totalpackets) {\r
+ current_stream->stream_remain_packets = totalpackets - STREAM_TDs;\r
+ current_stream->stream_buffer_address = (uint32_t) buffer + STREAM_TDs * packetsize;\r
+ current_stream->stream_packet_size = packetsize;\r
+ }\r
+ else {\r
+ current_stream->stream_remain_packets = current_stream->stream_buffer_address = current_stream->stream_packet_size = 0;\r
+ }\r
+ current_stream->stream_total_packets = totalpackets;\r
+ pdQueueHead = &(dQueueHead[corenum][PhyEP]);\r
+ pdQueueHead->overlay.Halted = 0; /* this should be in USBInt */\r
+ pdQueueHead->overlay.Active = 0; /* this should be in USBInt */\r
+ pdQueueHead->overlay.NextTD = (uint32_t) dStreamTD;\r
+ pdQueueHead->TransferCount = totalpackets * packetsize;\r
+ pdQueueHead->IsOutReceived = 0;\r
+\r
+ USB_REG(corenum)->ENDPTPRIME |= _BIT(EP_Physical2BitPosition(PhyEP) );\r
+#endif\r
+}\r
+\r
+void DcdInsertTD(uint32_t head, uint32_t newtd)\r
+{\r
+ DeviceTransferDescriptor *pTD = (DeviceTransferDescriptor *) head;\r
+ while (!(pTD->NextTD & LINK_TERMINATE)) pTD = (DeviceTransferDescriptor *) pTD->NextTD;\r
+ pTD->NextTD = newtd;\r
+}\r
+\r
+void DcdPrepareTD(DeviceTransferDescriptor *pDTD, uint8_t *pData, uint32_t length, uint8_t IOC)\r
+{\r
+ /* Zero out the device transfer descriptors */\r
+ memset((void *) pDTD, 0, sizeof(DeviceTransferDescriptor));\r
+\r
+ pDTD->NextTD = LINK_TERMINATE;\r
+ pDTD->TotalBytes = length;\r
+ pDTD->IntOnComplete = IOC;\r
+ pDTD->Active = 1;\r
+ pDTD->BufferPage[0] = (uint32_t) pData;\r
+ pDTD->BufferPage[1] = ((uint32_t) pData + 0x1000) & 0xfffff000;\r
+ // pDTD->BufferPage[2] = ((uint32_t) pData + 0x2000) & 0xfffff000;\r
+ // pDTD->BufferPage[3] = ((uint32_t) pData + 0x3000) & 0xfffff000;\r
+ // pDTD->BufferPage[4] = ((uint32_t) pData + 0x4000) & 0xfffff000;\r
+}\r
+\r
+void DcdDataTransfer(uint8_t corenum, uint8_t PhyEP, uint8_t *pData, uint32_t length)\r
+{\r
+ DeviceTransferDescriptor * pDTD = (DeviceTransferDescriptor *) &dTransferDescriptor[corenum][PhyEP];\r
+ volatile DeviceQueueHead * pdQueueHead = &(dQueueHead[corenum][PhyEP]);\r
+ while ( USB_REG(corenum)->ENDPTSTAT & _BIT(EP_Physical2BitPosition(PhyEP) ) ) { /* Endpoint is already primed */\r
+ }\r
+\r
+ /* Zero out the device transfer descriptors */\r
+ memset((void *) pDTD, 0, sizeof(DeviceTransferDescriptor));\r
+\r
+ if (((ENDPTCTRL_REG(corenum, PhyEP / 2) >> 2) & EP_TYPE_MASK) == EP_TYPE_ISOCHRONOUS) { // iso out endpoint\r
+ uint32_t mult = (USB_DATA_BUFFER_TEM_LENGTH + 1024) / 1024;\r
+ pDTD->NextTD = LINK_TERMINATE;\r
+ pdQueueHead->Mult = mult;\r
+ }\r
+ else if (((ENDPTCTRL_REG(corenum, PhyEP / 2) >> 18) & EP_TYPE_MASK) == EP_TYPE_ISOCHRONOUS) {// iso in endpoint\r
+ uint32_t mult = (USB_DATA_BUFFER_TEM_LENGTH + 1024) / 1024;\r
+ pDTD->NextTD = LINK_TERMINATE;\r
+ pdQueueHead->Mult = mult;\r
+ }\r
+ else { // other endpoint types\r
+ pDTD->NextTD = LINK_TERMINATE; /* The next DTD pointer is INVALID */\r
+ }\r
+ pDTD->TotalBytes = length;\r
+ pDTD->IntOnComplete = 1;\r
+ pDTD->Active = 1;\r
+\r
+ pDTD->BufferPage[0] = (uint32_t) pData;\r
+ pDTD->BufferPage[1] = ((uint32_t) pData + 0x1000) & 0xfffff000;\r
+ pDTD->BufferPage[2] = ((uint32_t) pData + 0x2000) & 0xfffff000;\r
+ pDTD->BufferPage[3] = ((uint32_t) pData + 0x3000) & 0xfffff000;\r
+ pDTD->BufferPage[4] = ((uint32_t) pData + 0x4000) & 0xfffff000;\r
+\r
+ pdQueueHead->overlay.Halted = 0; /* this should be in USBInt */\r
+ pdQueueHead->overlay.Active = 0; /* this should be in USBInt */\r
+ pdQueueHead->overlay.NextTD = (uint32_t) &dTransferDescriptor[corenum][PhyEP];\r
+ pdQueueHead->TransferCount = length;\r
+\r
+ /* prime the endpoint for transmit */\r
+ USB_REG(corenum)->ENDPTPRIME |= _BIT(EP_Physical2BitPosition(PhyEP) );\r
+}\r
+\r
+void TransferCompleteISR(uint8_t corenum)\r
+{\r
+ uint8_t * ISO_Address;\r
+ IP_USBHS_001_T * USB_Reg = USB_REG(corenum);\r
+ STREAM_VAR_t * current_stream = &Stream_Variable[corenum];\r
+ uint32_t ENDPTCOMPLETE = USB_Reg->ENDPTCOMPLETE;\r
+ USB_Reg->ENDPTCOMPLETE = ENDPTCOMPLETE;\r
+ if (ENDPTCOMPLETE) {\r
+ uint8_t n;\r
+ for (n = 0; n < USED_PHYSICAL_ENDPOINTS(corenum) / 2; n++) { /* LOGICAL */\r
+ if ( ENDPTCOMPLETE & _BIT(n) ) {/* OUT */\r
+ if (((ENDPTCTRL_REG(corenum, n) >> 2) & EP_TYPE_MASK) == EP_TYPE_ISOCHRONOUS) { // iso out endpoint\r
+ uint32_t size = dQueueHead[corenum][2 * n].TransferCount;\r
+ size -= dQueueHead[corenum][2 * n].overlay.TotalBytes;\r
+ // copy to share buffer\r
+ ISO_Address = (uint8_t *) CALLBACK_HAL_GetISOBufferAddress(n, &size);\r
+ DcdDataTransfer(corenum, 2 * n, ISO_Address, USB_DATA_BUFFER_TEM_LENGTH);\r
+ }\r
+ else {\r
+ \r
+ uint32_t tem = dQueueHead[corenum][2 * n].overlay.TotalBytes;\r
+ dQueueHead[corenum][2 * n].TransferCount -= tem;\r
+\r
+ if (current_stream->stream_total_packets > 0) {\r
+ if (current_stream->stream_remain_packets > 0) {\r
+ uint32_t cnt = dQueueHead[corenum][2 * n].TransferCount;\r
+ Endpoint_Streaming(corenum,(uint8_t *) current_stream->stream_buffer_address,\r
+ current_stream->stream_packet_size,\r
+ current_stream->stream_remain_packets,\r
+ 0);\r
+ dQueueHead[corenum][2 * n].TransferCount = cnt;\r
+ }\r
+ else {\r
+ current_stream->stream_total_packets = 0;\r
+ dQueueHead[corenum][2 * n].IsOutReceived = 1;\r
+ }\r
+ }\r
+ else {\r
+ //stream_total_packets = 0;\r
+ dQueueHead[corenum][2 * n].IsOutReceived = 1;\r
+ }\r
+ if (n == 0) {\r
+ usb_data_buffer_size[corenum] = dQueueHead[corenum][2 * n].TransferCount;\r
+ }\r
+ else {\r
+ usb_data_buffer_OUT_size[corenum] = dQueueHead[corenum][2 * n].TransferCount;\r
+ }\r
+ }\r
+ EVENT_USB_Device_TransferComplete(n, 0);\r
+ }\r
+ if ( ENDPTCOMPLETE & _BIT( (n + 16) ) ) { /* IN */\r
+ if (((ENDPTCTRL_REG(corenum, n) >> 18) & EP_TYPE_MASK) == EP_TYPE_ISOCHRONOUS) { // iso in endpoint\r
+ uint32_t size;\r
+ ISO_Address = (uint8_t *) CALLBACK_HAL_GetISOBufferAddress(n, &size);\r
+ DcdDataTransfer(corenum, 2 * n + 1, ISO_Address, size);\r
+ }\r
+ else {\r
+ if (current_stream->stream_remain_packets > 0) {\r
+ uint32_t cnt = dQueueHead[corenum][2 * n].TransferCount;\r
+ Endpoint_Streaming(corenum, (uint8_t *) current_stream->stream_buffer_address,\r
+ current_stream->stream_packet_size,\r
+ current_stream->stream_remain_packets,\r
+ 0);\r
+ dQueueHead[corenum][2 * n].TransferCount = cnt;\r
+ }\r
+ else {\r
+ current_stream->stream_total_packets = 0;\r
+ }\r
+ }\r
+ EVENT_USB_Device_TransferComplete(n, 1);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+void Endpoint_GetSetupPackage(uint8_t corenum, uint8_t *pData)\r
+{\r
+ USB_Request_Header_t * ctrlrq = (USB_Request_Header_t *) pData;\r
+ volatile DeviceQueueHead* pdQueueHead = &(dQueueHead[corenum][0]);\r
+ memcpy(pData, (void *) pdQueueHead->SetupPackage, 8);\r
+ /* Below fix is to prevent Endpoint_Read_Control_Stream_LE()\r
+ * from getting wrong data*/\r
+\r
+ if (\r
+ (ctrlrq->wLength != 0)\r
+ ) {\r
+ pdQueueHead->IsOutReceived = 0;\r
+ }\r
+}\r
+\r
+void DcdIrqHandler(uint8_t corenum)\r
+{\r
+ uint32_t USBSTS_D;\r
+ IP_USBHS_001_T * USB_Reg = USB_REG(corenum);\r
+ uint32_t t = USB_Reg->USBINTR_D;\r
+\r
+ USBSTS_D = USB_Reg->USBSTS_D & t; /* Device Interrupt Status */\r
+ if (USBSTS_D == 0) {/* avoid to clear disabled interrupt source */\r
+ return;\r
+ }\r
+\r
+ USB_Reg->USBSTS_D = USBSTS_D; /* Acknowledge Interrupt */\r
+\r
+ /* Process Interrupt Sources */\r
+ if (USBSTS_D & USBSTS_D_UsbInt) {\r
+ if (USB_Reg->ENDPTSETUPSTAT) {\r
+ // memcpy(SetupPackage, dQueueHead[0].SetupPackage, 8);\r
+ /* Will be cleared by Endpoint_ClearSETUP */\r
+ }\r
+\r
+ if (USB_Reg->ENDPTCOMPLETE) {\r
+ TransferCompleteISR(corenum);\r
+ }\r
+ }\r
+\r
+ if (USBSTS_D & USBSTS_D_NAK) { /* NAK */\r
+ uint32_t ENDPTNAK = USB_Reg->ENDPTNAK;\r
+ uint32_t en = USB_Reg->ENDPTNAKEN;\r
+ ENDPTNAK &= en;\r
+ USB_Reg->ENDPTNAK = ENDPTNAK;\r
+\r
+ if (ENDPTNAK) { /* handle NAK interrupts */\r
+ uint8_t LogicalEP;\r
+ for (LogicalEP = 0; LogicalEP < USED_PHYSICAL_ENDPOINTS(corenum) / 2; LogicalEP++)\r
+ if (ENDPTNAK & _BIT(LogicalEP)) { /* Only OUT Endpoint is NAK enable */\r
+ uint8_t PhyEP = 2 * LogicalEP;\r
+ if ( !(USB_Reg->ENDPTSTAT & _BIT(LogicalEP)) ) {/* Is In ready */\r
+ /* Check read OUT flag */\r
+ if (!dQueueHead[corenum][PhyEP].IsOutReceived) {\r
+\r
+ if (PhyEP == 0) {\r
+ usb_data_buffer_size[corenum] = 0;\r
+ USB_Reg->ENDPTNAKEN &= ~(1 << 0);\r
+ DcdDataTransfer(corenum, PhyEP, usb_data_buffer[corenum], 512);\r
+ }\r
+ else {\r
+ if (Stream_Variable[corenum].stream_total_packets == 0) {\r
+ usb_data_buffer_OUT_size[corenum] = 0;\r
+ /* Clear NAK */\r
+ USB_Reg->ENDPTNAKEN &= ~(1 << LogicalEP);\r
+ DcdDataTransfer(corenum, PhyEP, usb_data_buffer_OUT[corenum], 512 /*512*/);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ if (USBSTS_D & USBSTS_D_SofReceived) { /* Start of Frame Interrupt */\r
+ EVENT_USB_Device_StartOfFrame();\r
+ }\r
+\r
+ if (USBSTS_D & USBSTS_D_ResetReceived) { /* Reset */\r
+ HAL_Reset(corenum);\r
+ USB_DeviceState[corenum] = DEVICE_STATE_Default;\r
+ Endpoint_ConfigureEndpoint(corenum,\r
+ ENDPOINT_CONTROLEP,\r
+ EP_TYPE_CONTROL,\r
+ ENDPOINT_DIR_OUT,\r
+ USB_Device_ControlEndpointSize,\r
+ 0);\r
+ Endpoint_ConfigureEndpoint(corenum, \r
+ ENDPOINT_CONTROLEP,\r
+ EP_TYPE_CONTROL,\r
+ ENDPOINT_DIR_IN,\r
+ USB_Device_ControlEndpointSize,\r
+ 0);\r
+ }\r
+\r
+ if (USBSTS_D & USBSTS_D_SuspendInt) { /* Suspend */\r
+\r
+ }\r
+\r
+ if (USBSTS_D & USBSTS_D_PortChangeDetect) { /* Resume */\r
+\r
+ }\r
+\r
+ if (USBSTS_D & USBSTS_D_UsbErrorInt) { /* Error Interrupt */\r
+ // while(1){}\r
+ }\r
+}\r
+\r
+uint32_t Dummy_EPGetISOAddress(uint32_t EPNum, uint32_t *last_packet_size)\r
+{\r
+ return (uint32_t) iso_buffer;\r
+}\r
+\r
+/*********************************************************************//**\r
+ * @brief Dummy USB device transfer complete event\r
+ * @param[in] logicalEP Logical endpoint number\r
+ * @param[in] xfer_in If this argument is 0 then xfer type is out, else in\r
+ * @note This event is required for running the stack with RTOS\r
+ * and so it should never be removed!\r
+ * @return None\r
+ **********************************************************************/\r
+void Dummy_EVENT_USB_Device_TransferComplete(int logicalEP, int xfer_in)\r
+{\r
+ /**\r
+ * This is a dummy function\r
+ * If xfer_in zero then the endpoint it OUT\r
+ * else ep is IN.\r
+ **/\r
+}\r
+// #endif\r
+\r
+#endif /*__LPC18XX__*/\r
--- /dev/null
+/*\r
+ * @brief USB Endpoint definitions for the LPC18xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_EndpointRW\r
+ * @defgroup Group_EndpointRW_LPC18xx Endpoint Data Reading and Writing (LPC18xx)\r
+ * @brief Endpoint data read/write definitions for the LPC architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing from and to endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointPrimitiveRW\r
+ * @defgroup Group_EndpointPrimitiveRW_LPC18xx Read/Write of Primitive Data Types (LPC18xx)\r
+ * @brief Endpoint primitive read/write definitions for the LPC18xx architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing of primitive data types\r
+ * from and to endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointPacketManagement\r
+ * @defgroup Group_EndpointPacketManagement_LPC18xx Endpoint Packet Management (LPC18xx)\r
+ * @brief Endpoint packet management definitions for the LPC18xx architecture.\r
+ *\r
+ * Functions, macros, variables, enums and types related to packet management of endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointManagement\r
+ * @defgroup Group_EndpointManagement_LPC18xx Endpoint Management (LPC18xx)\r
+ * @brief Endpoint management definitions for the LPC18xx architecture.\r
+ *\r
+ * Functions, macros and enums related to endpoint management when in USB Device mode. This\r
+ * module contains the endpoint management macros, as well as endpoint interrupt and data\r
+ * send/receive functions for various data types.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __ENDPOINT_LPC18XX_H__\r
+#define __ENDPOINT_LPC18XX_H__\r
+\r
+ #include "../EndpointCommon.h"\r
+\r
+/* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+extern "C" {\r
+ #endif\r
+\r
+/* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+/* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+/* Macros: */\r
+ #define ENDPOINT_DETAILS_MAXEP0 6\r
+ #define ENDPOINT_DETAILS_MAXEP1 4\r
+\r
+ #if defined(USB_DEVICE_ROM_DRIVER)\r
+/*==========================================================================*/\r
+/* USB ROM DRIVER DEFINITIONS */\r
+\r
+/* A table of pointers to the chip's main ROM functions contained in ROM is located at the\r
+ address contained at this location */\r
+typedef struct _ROM {\r
+ const unsigned p_otp;\r
+ const unsigned p_aes;\r
+ const unsigned p_pwd;\r
+ const unsigned p_clk;\r
+ const unsigned p_ipc;\r
+ const unsigned p_spifi;\r
+ const unsigned p_usbd;\r
+} ROM_FUNCTION_TABLE;\r
+\r
+/* A table of pointers to the USBD functions contained in ROM is located at the\r
+ address contained at this location */\r
+ #define ROM_FUNCTION_TABLE_PTR_ADDR (0x10400104UL)\r
+ #define ROM_USBD_PTR (((ROM_FUNCTION_TABLE *) (ROM_FUNCTION_TABLE_PTR_ADDR))->p_usbd)\r
+\r
+ #define ROMDRIVER_USB0_BASE LPC_USB0_BASE\r
+ #define ROMDRIVER_USB1_BASE LPC_USB1_BASE\r
+ #define ROMDRIVER_MEM_SIZE 0x1000\r
+extern uint8_t usb_RomDriver_buffer[ROMDRIVER_MEM_SIZE];\r
+\r
+ #define ROMDRIVER_MSC_MEM_SIZE 0x1000\r
+extern uint8_t usb_RomDriver_MSC_buffer[ROMDRIVER_MSC_MEM_SIZE];\r
+\r
+ #define ROMDRIVER_CDC_MEM_SIZE 0x800\r
+extern uint8_t usb_RomDriver_CDC_buffer[ROMDRIVER_CDC_MEM_SIZE];\r
+ #define ROMDRIVER_CDC_DATA_BUFFER_SIZE 640\r
+ #if (USB_FORCED_FULLSPEED)\r
+ #define CDC_MAX_BULK_EP_SIZE 64\r
+ #else\r
+ #define CDC_MAX_BULK_EP_SIZE 512\r
+ #endif\r
+extern uint8_t UsbdCdc_EPIN_buffer[CDC_MAX_BULK_EP_SIZE];\r
+extern uint8_t UsbdCdc_EPOUT_buffer[CDC_MAX_BULK_EP_SIZE];\r
+\r
+ #define ROMDRIVER_HID_MEM_SIZE 0x800\r
+extern uint8_t usb_RomDriver_HID_buffer[ROMDRIVER_HID_MEM_SIZE];\r
+/*==========================================================================*/\r
+ #endif\r
+\r
+/*==========================================================================*/\r
+/* DEVICE REGISTER DEFINITIONS */\r
+/*==========================================================================*/\r
+/*---------- USBCMD ----------*/\r
+ #define USBCMD_D_RunStop (1 << 0) /* Run or Stop */\r
+ #define USBCMD_D_Reset (1 << 1) /* Host Controller Reset */\r
+ #define USBCMD_D_SetupTripWire (1 << 13)\r
+ #define USBCMD_D_AddTDTripWire (1 << 14)\r
+ #define USBCMD_D_IntThreshold (0xff << 16)\r
+\r
+/*---------- USBSTS ----------*/\r
+ #define USBSTS_D_UsbInt 0x00000001UL /* USB Interrupt */\r
+ #define USBSTS_D_UsbErrorInt 0x00000002UL /* USB Error Interrupt */\r
+ #define USBSTS_D_PortChangeDetect 0x00000004UL /* Port Change Detect */\r
+ #define USBSTS_D_ResetReceived (1 << 6)\r
+ #define USBSTS_D_SofReceived (1 << 7)\r
+ #define USBSTS_D_SuspendInt (1 << 8)\r
+ #define USBSTS_D_NAK (1 << 16)\r
+\r
+/*---------- USBINTR ----------*/\r
+ #define USBINTR_D_UsbIntEnable (1 << 0)\r
+ #define USBINTR_D_UsbErrorIntEnable (1 << 1)\r
+ #define USBINTR_D_PortChangeIntEnable (1 << 2)\r
+ #define USBINTR_D_UsbResetEnable (1 << 6)\r
+ #define USBINTR_D_SofReceivedEnable (1 << 7)\r
+ #define USBINTR_D_SuspendEnable (1 << 8)\r
+ #define USBINTR_D_NAKEnable (1 << 16)\r
+\r
+/*---------- DEVICEADDR ----------*/\r
+ #define DEVICEADDR_AddressAdvance (1 << 24)\r
+ #define DEVICEADDR_DeviceAddr (0xff << 25)\r
+\r
+/*---------- ENDPTNAK ----------*/\r
+ #define ENDPTNAK_RX (0x3f)\r
+ #define ENDPTNAK_TX (0x3f << 16)\r
+\r
+/*---------- ENDPTNAKEN ----------*/\r
+ #define ENDPTNAKEN_RX (0x3f)\r
+ #define ENDPTNAKEN_TX (0x3f << 16)\r
+\r
+/*---------- PORTSC ----------*/\r
+ #define PORTSC_D_CurrentConnectStatus 0x00000001UL /* Current Connect Status */\r
+ #define PORTSC_D_ForcePortResume 0x00000040UL /* Force Port Resume */\r
+ #define PORTSC_D_PortSuspend 0x00000080UL /* Port Suspend */\r
+ #define PORTSC_D_PortReset 0x00000100UL /* Port Reset */\r
+ #define PORTSC_D_HighSpeedStatus 0x00000200UL /* Line Status */\r
+ #define PORTSC_D_PortIndicatorControl 0x0000C000UL /* Port Indicator Control */\r
+ #define PORTSC_D_PortTestControl 0x000F0000UL /* Port Test Control */\r
+ #define PORTSC_D_PhyClockDisable 0x00800000UL /* PHY Clock Disable - EHCI derivation */\r
+ #define PORTSC_D_PortForceFullspeedConnect 0x01000000UL /* Force Device on Fullspeed mode (disable chirp sequences) - EHCI derivation */\r
+ #define PORTSC_D_PortSpeed 0x0C000000UL /* Device Speed - EHCI derivation */\r
+\r
+/*---------- USBMODE_D ----------*/\r
+/*---------- ENDPSETUPSTAT ----------*/\r
+\r
+/*---------- ENDPTPRIME ----------*/\r
+ #define ENDPTPRIME_RX (0x3f)\r
+ #define ENDPTPRIME_TX (0x3f << 16)\r
+\r
+/*---------- ENDPTFLUSH ----------*/\r
+ #define ENDPTFLUSH_RX (0x3f)\r
+ #define ENDPTFLUSH_TX (0x3f << 16)\r
+\r
+/*---------- ENDPTSTAT ----------*/\r
+ #define ENDPTSTAT_RX (0x3f)\r
+ #define ENDPTSTAT_TX (0x3f << 16)\r
+\r
+/*---------- ENDPTCOMPLETE ----------*/\r
+ #define ENDPTCOMPLETE_RX (0x3f)\r
+ #define ENDPTCOMPLETE_TX (0x3f << 16)\r
+\r
+/*---------- ENDPTCTRL ----------*/\r
+ #define ENDPTCTRL_RxStall (1)\r
+ #define ENDPTCTRL_RxType (3 << 2)\r
+ #define ENDPTCTRL_RxToggleInhibit (1 << 5)\r
+ #define ENDPTCTRL_RxToggleReset (1 << 6)\r
+ #define ENDPTCTRL_RxEnable (1 << 7)\r
+\r
+ #define ENDPTCTRL_TxStall (1 << 16)\r
+ #define ENDPTCTRL_TxType (3 << 18)\r
+ #define ENDPTCTRL_TxToggleInhibit (1 << 21)\r
+ #define ENDPTCTRL_TxToggleReset (1 << 22)\r
+ #define ENDPTCTRL_TxEnable (1 << 23)\r
+ #define ENDPTCTRL_REG(corenum, LogicalAddr) ( ((__IO uint32_t *) &(USB_REG(corenum)->ENDPTCTRL[0]))[ \\r
+ LogicalAddr] )\r
+ #define EP_Physical2Logical(n) ((n) / 2)\r
+/* Total physical endpoints*/\r
+ #define USED_PHYSICAL_ENDPOINTS0 ENDPOINT_DETAILS_MAXEP0 * 2 /* This macro effect memory size of the DCD */\r
+ #define USED_PHYSICAL_ENDPOINTS1 ENDPOINT_DETAILS_MAXEP1 * 2 /* This macro effect memory size of the DCD */\r
+ #define USED_PHYSICAL_ENDPOINTS(corenum) ((corenum) ? USED_PHYSICAL_ENDPOINTS1 : USED_PHYSICAL_ENDPOINTS0) /* This macro effect memory size of the DCD */\r
+ #define EP_Physical2BitPosition(n) ( EP_Physical2Logical(n) + ((n) % 2 ? 16 : 0 ) )\r
+// #define LINK_TERMINATE 1\r
+\r
+/*---------- Device TD ----------*/\r
+typedef struct {\r
+ /*---------- Word 1 ----------*/\r
+ uint32_t NextTD;\r
+\r
+ /*---------- Word 2 ----------*/\r
+ uint32_t : 3;\r
+ __IO uint32_t TransactionErr : 1;\r
+ uint32_t : 1;\r
+ __IO uint32_t BufferErr : 1;\r
+ __IO uint32_t Halted : 1;\r
+ __IO uint32_t Active : 1;\r
+ uint32_t : 2;\r
+ uint32_t MultiplierOverride : 2;\r
+ uint32_t : 3;\r
+ __IO uint32_t IntOnComplete : 1;\r
+ __IO uint32_t TotalBytes : 15;\r
+ uint32_t : 0; /* force next member alinged on the next word */\r
+\r
+ /*---------- Word 3 - 7 ----------*/\r
+ uint32_t BufferPage[5];\r
+\r
+ uint32_t reserved;\r
+} DeviceTransferDescriptor, *PDeviceTransferDescriptor;\r
+\r
+/*---------- Device Qhd ----------*/\r
+typedef struct {\r
+ /*---------- Word 1: Capability/Characteristics ----------*/\r
+ uint32_t : 15;\r
+ __IO uint32_t IntOnSetup : 1;\r
+ uint32_t MaxPacketSize : 11;\r
+ uint32_t : 2;\r
+ __IO uint32_t ZeroLengthTermination : 1;\r
+ uint32_t Mult : 2;\r
+ uint32_t : 0;\r
+\r
+ /*---------- Word 2 ----------*/\r
+ uint32_t currentTD;\r
+\r
+ /*---------- Word 3 - 10 ----------*/\r
+ __IO DeviceTransferDescriptor overlay;\r
+\r
+ /*---------- Word 11-12 ----------*/\r
+ __IO uint8_t SetupPackage[8];\r
+\r
+ uint16_t TransferCount;\r
+ __IO uint16_t IsOutReceived; // === TODO: IsOutReceived should be refractor to QueueHead Status ===\r
+ uint16_t reserved[6];\r
+} DeviceQueueHead, *PDeviceQueueHead;\r
+\r
+extern volatile DeviceQueueHead * const dQueueHead[];\r
+extern DeviceTransferDescriptor * const dTransferDescriptor[];\r
+\r
+void DcdDataTransfer(uint8_t corenum, uint8_t EPNum, uint8_t *pData, uint32_t cnt);\r
+\r
+void Endpoint_Streaming(uint8_t corenum, uint8_t *buffer, uint16_t packetsize,\r
+ uint16_t totalpackets, uint16_t dummypackets);\r
+\r
+/* Inline Functions: */\r
+\r
+/* Function Prototypes: */\r
+void Endpoint_ClearEndpoints(uint8_t corenum);\r
+\r
+bool Endpoint_ConfigureEndpoint_Prv(uint8_t corenum,\r
+ const uint8_t Number,\r
+ const uint8_t UECFG0XData,\r
+ const uint8_t UECFG1XData);\r
+\r
+ #endif\r
+\r
+/* Inline Functions: */\r
+/**\r
+ * @brief Configures the specified endpoint number with the given endpoint type, direction, bank size\r
+ * and banking mode. Once configured, the endpoint may be read from or written to, depending\r
+ * on its direction.\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param Number : Endpoint number to configure. This must be more than 0 and less than @ref ENDPOINT_TOTAL_ENDPOINTS\r
+ * @param Type : Type of endpoint to configure, a \c EP_TYPE_* mask. Not all endpoint types\r
+ * are available on Low Speed USB devices - refer to the USB 2.0 specification.\r
+ * @param Direction : Endpoint data direction, either @ref ENDPOINT_DIR_OUT or @ref ENDPOINT_DIR_IN.\r
+ * All endpoints (except Control type) are unidirectional - data may only be read\r
+ * from or written to the endpoint bank based on its direction, not both.\r
+ * @param Size : Size of the endpoint's bank, where packets are stored before they are transmitted\r
+ * to the USB host, or after they have been received from the USB host (depending on\r
+ * the endpoint's data direction). The bank size must indicate the maximum packet size\r
+ * that the endpoint can handle.\r
+ * @param Banks : Number of banks to use for the endpoint being configured, an \c ENDPOINT_BANK_* mask.\r
+ * More banks uses more USB DPRAM, but offers better performance. Isochronous type\r
+ * endpoints <b>must</b> have at least two banks.\r
+ * @return Boolean \c true if the configuration succeeded, \c false otherwise.\r
+ */\r
+/*static inline */ bool Endpoint_ConfigureEndpoint(uint8_t corenum,\r
+ const uint8_t Number,\r
+ const uint8_t Type,\r
+ const uint8_t Direction,\r
+ const uint16_t Size,\r
+ const uint8_t Banks) /*ATTR_ALWAYS_INLINE*/;\r
+\r
+// static inline bool Endpoint_ConfigureEndpoint(const uint8_t Number,\r
+// const uint8_t Type,\r
+// const uint8_t Direction,\r
+// const uint16_t Size,\r
+// const uint8_t Banks)\r
+// {\r
+// endpointhandle[Number] = HAL17XX_ConfigureEndpoint(Number,Type,Direction,Size,Banks);\r
+// return true;\r
+// }\r
+\r
+/**\r
+ * @brief Resets the endpoint bank FIFO. This clears all the endpoint banks and resets the USB controller's\r
+ * data In and Out pointers to the bank's contents.\r
+ *\r
+ * @param EndpointNumber : Endpoint number whose FIFO buffers are to be reset.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ResetEndpoint(const uint8_t EndpointNumber)\r
+{}\r
+\r
+/**\r
+ * @brief Enables the currently selected endpoint so that data can be sent and received through it to\r
+ * and from a host.\r
+ *\r
+ * @note Endpoints must first be configured properly via @ref Endpoint_ConfigureEndpoint().\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_EnableEndpoint(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_EnableEndpoint(void)\r
+{}\r
+\r
+/**\r
+ * @brief Disables the currently selected endpoint so that data cannot be sent and received through it\r
+ * to and from a host.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_DisableEndpoint(void) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_DisableEndpoint(void)\r
+{}\r
+\r
+/**\r
+ * @brief Determines if the currently selected endpoint is enabled, but not necessarily configured\r
+ * @return Boolean \c true if the currently selected endpoint is enabled, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsEnabled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsEnabled(void)\r
+{\r
+ return true;\r
+}\r
+\r
+/**\r
+ * @brief Retrieves the number of busy banks in the currently selected endpoint, which have been queued for\r
+ * transmission via the @ref Endpoint_ClearIN() command, or are awaiting acknowledgement via the\r
+ * @ref Endpoint_ClearOUT() command.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ *\r
+ * @return Total number of busy banks in the selected endpoint.\r
+ */\r
+static inline uint8_t Endpoint_GetBusyBanks(void) ATTR_ALWAYS_INLINE ATTR_WARN_UNUSED_RESULT;\r
+\r
+static inline uint8_t Endpoint_GetBusyBanks(void)\r
+{\r
+ return 0;\r
+}\r
+\r
+/** @brief Aborts all pending IN transactions on the currently selected endpoint, once the bank\r
+ * has been queued for transmission to the host via @ref Endpoint_ClearIN(). This function\r
+ * will terminate all queued transactions, resetting the endpoint banks ready for a new\r
+ * packet.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_AbortPendingIN(void)\r
+{}\r
+\r
+/**\r
+ * @brief Determines if the currently selected endpoint is configured.\r
+ *\r
+ * @return Boolean \c true if the currently selected endpoint has been configured, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsConfigured(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsConfigured(void)\r
+{\r
+ // return ((UESTA0X & (1 << CFGOK)) ? true : false);\r
+ return true;\r
+}\r
+\r
+/**\r
+ * @brief Returns a mask indicating which INTERRUPT type endpoints have interrupted - i.e. their\r
+ * interrupt duration has elapsed. Which endpoints have interrupted can be determined by\r
+ * masking the return value against <tt>(1 << <i>{Endpoint Number}</i>)</tt>.\r
+ *\r
+ * @return Mask whose bits indicate which endpoints have interrupted.\r
+ */\r
+static inline uint8_t Endpoint_GetEndpointInterrupts(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline uint8_t Endpoint_GetEndpointInterrupts(void)\r
+{\r
+ return 0; // TODO not yet implemented\r
+}\r
+\r
+/**\r
+ * @brief Determines if the specified endpoint number has interrupted (valid only for INTERRUPT type\r
+ * endpoints).\r
+ * @param EndpointNumber : Index of the endpoint whose interrupt flag should be tested\r
+ * @return Boolean \c true if the specified endpoint has interrupted, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber) ATTR_WARN_UNUSED_RESULT\r
+ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_HasEndpointInterrupted(const uint8_t EndpointNumber)\r
+{\r
+ return (Endpoint_GetEndpointInterrupts() & (1 << EndpointNumber)) ? true : false;\r
+}\r
+\r
+/**\r
+ * @brief Indicates the number of bytes currently stored in the current endpoint's selected bank.\r
+ *\r
+ * @note The return width of this function may differ, depending on the maximum endpoint bank size\r
+ * of the selected LPC model.\r
+ *\r
+ * @ingroup Group_EndpointRW_LPC18xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Total number of bytes in the currently selected Endpoint's FIFO buffer\r
+ */\r
+static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline uint16_t Endpoint_BytesInEndpoint(uint8_t corenum)\r
+{\r
+ // return usb_data_buffer_index; // TODO not implemented yet\r
+ // uint8_t PhyEP = (endpointselected==ENDPOINT_CONTROLEP ? 1: endpointhandle[endpointselected]);\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ return usb_data_buffer_size[corenum];\r
+ }\r
+ else {\r
+ return usb_data_buffer_OUT_size[corenum];\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Determines if the selected IN endpoint is ready for a new packet to be sent to the host.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Boolean \c true if the current endpoint is ready for an IN packet, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsINReady(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsINReady(uint8_t corenum)\r
+{\r
+ uint8_t PhyEP = (endpointselected[corenum] == ENDPOINT_CONTROLEP ? 1 : endpointhandle(corenum)[endpointselected[corenum]]);\r
+ return (dQueueHead[corenum][PhyEP].overlay.NextTD & LINK_TERMINATE) &&\r
+ (dQueueHead[corenum][PhyEP].overlay.Active == 0);\r
+}\r
+\r
+/**\r
+ * @brief Determines if the selected OUT endpoint has received new packet from the host.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Boolean \c true if current endpoint is has received an OUT packet, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsOUTReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsOUTReceived(uint8_t corenum)\r
+{\r
+ // return (dQueueHead[ endpointhandle[endpointselected] ].overlay.NextTD == LINK_TERMINATE &&\r
+ // dQueueHead[ endpointhandle[endpointselected] ].overlay.Active == 0 );\r
+ return dQueueHead[corenum][endpointhandle(corenum)[endpointselected[corenum]]].IsOutReceived ? true : false; // TODO refractor IsOutReceived\r
+}\r
+\r
+/**\r
+ * @brief Determines if the current CONTROL type endpoint has received a SETUP packet.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Boolean \c true if the selected endpoint has received a SETUP packet, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsSETUPReceived(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsSETUPReceived(uint8_t corenum)\r
+{\r
+ return USB_REG(corenum)->ENDPTSETUPSTAT ? true : false;\r
+}\r
+\r
+/**\r
+ * @brief Clears a received SETUP packet on the currently selected CONTROL type endpoint, freeing up the\r
+ * endpoint for the next packet.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ * @note This is not applicable for non CONTROL type endpoints.\r
+ */\r
+static inline void Endpoint_ClearSETUP(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearSETUP(uint8_t corenum)\r
+{\r
+ IP_USBHS_001_T * USB_Reg = USB_REG(corenum);\r
+ USB_Reg->ENDPTSETUPSTAT = USB_Reg->ENDPTSETUPSTAT;\r
+ usb_data_buffer_index[corenum] = 0;\r
+ USB_Reg->ENDPTNAKEN |= (1 << 0);\r
+}\r
+\r
+/**\r
+ * @brief Sends an IN packet to the host on the currently selected endpoint, freeing up the endpoint for the\r
+ * next packet and switching to the alternative endpoint bank if double banked.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_ClearIN(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearIN(uint8_t corenum)\r
+{\r
+ uint8_t PhyEP = endpointselected[corenum] == ENDPOINT_CONTROLEP ? 1 : (endpointhandle(corenum)[endpointselected[corenum]]);\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ DcdDataTransfer(corenum, PhyEP, (uint8_t *)usb_data_buffer[corenum], usb_data_buffer_index[corenum]);\r
+ usb_data_buffer_index[corenum] = 0;\r
+ }\r
+ else {\r
+ DcdDataTransfer(corenum, PhyEP, usb_data_buffer_IN[corenum], usb_data_buffer_IN_index[corenum]);\r
+ usb_data_buffer_IN_index[corenum] = 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Acknowledges an OUT packet to the host on the currently selected endpoint, freeing up the endpoint\r
+ * for the next packet and switching to the alternative endpoint bank if double banked.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_ClearOUT(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearOUT(uint8_t corenum)\r
+{\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ usb_data_buffer_index[corenum] = 0;\r
+ dQueueHead[corenum][endpointhandle(corenum)[endpointselected[corenum]]].IsOutReceived = 0;\r
+ }\r
+ else {\r
+ usb_data_buffer_OUT_index[corenum] = 0;\r
+ dQueueHead[corenum][endpointhandle(corenum)[endpointselected[corenum]]].IsOutReceived = 0;\r
+ USB_REG(corenum)->ENDPTNAKEN |= (1 << endpointselected[corenum]);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Stalls the current endpoint, indicating to the host that a logical problem occurred with the\r
+ * indicated endpoint and that the current transfer sequence should be aborted. This provides a\r
+ * way for devices to indicate invalid commands to the host so that the current transfer can be\r
+ * aborted and the host can begin its own recovery sequence.\r
+ *\r
+ * The currently selected endpoint remains stalled until either the @ref Endpoint_ClearStall() macro\r
+ * is called, or the host issues a CLEAR FEATURE request to the device for the currently selected\r
+ * endpoint.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_StallTransaction(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_StallTransaction(uint8_t corenum)\r
+{\r
+ ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) |= ENDPTCTRL_RxStall | ENDPTCTRL_TxStall;\r
+}\r
+\r
+/**\r
+ * @brief Clears the STALL condition on the currently selected endpoint.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+static inline void Endpoint_ClearStall(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ClearStall(uint8_t corenum)\r
+{\r
+ // === TODO: Only clear stall correct endpoint ===\r
+ ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) &= ~(ENDPTCTRL_RxStall | ENDPTCTRL_TxStall);\r
+}\r
+\r
+/**\r
+ * @brief Determines if the currently selected endpoint is stalled, false otherwise.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement_LPC18xx\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Boolean \c true if the currently selected endpoint is stalled, \c false otherwise.\r
+ */\r
+static inline bool Endpoint_IsStalled(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+static inline bool Endpoint_IsStalled(uint8_t corenum)\r
+{\r
+ return ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) &\r
+ (ENDPTCTRL_RxStall | ENDPTCTRL_TxStall);\r
+}\r
+\r
+/** Resets the data toggle of the currently selected endpoint. */\r
+static inline void Endpoint_ResetDataToggle(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+static inline void Endpoint_ResetDataToggle(uint8_t corenum)\r
+{\r
+ ENDPTCTRL_REG(corenum, EP_Physical2Logical(endpointhandle(corenum)[endpointselected[corenum]]) ) |= ENDPTCTRL_RxToggleReset |\r
+ ENDPTCTRL_TxToggleReset;\r
+}\r
+\r
+/* External Variables: */\r
+/** Global indicating the maximum packet size of the default control endpoint located at address\r
+ * 0 in the device. This value is set to the value indicated in the device descriptor in the user\r
+ * project once the USB interface is initialized into device mode.\r
+ *\r
+ * If space is an issue, it is possible to fix this to a static value by defining the control\r
+ * endpoint size in the \c FIXED_CONTROL_ENDPOINT_SIZE token passed to the compiler in the makefile\r
+ * via the -D switch. When a fixed control endpoint size is used, the size is no longer dynamically\r
+ * read from the descriptors at runtime and instead fixed to the given value. When used, it is\r
+ * important that the descriptor control endpoint size value matches the size given as the\r
+ * \c FIXED_CONTROL_ENDPOINT_SIZE token - it is recommended that the \c FIXED_CONTROL_ENDPOINT_SIZE token\r
+ * be used in the device descriptors to ensure this.\r
+ *\r
+ * @note This variable should be treated as read-only in the user application, and never manually\r
+ * changed in value.\r
+ */\r
+ #if (!defined(FIXED_CONTROL_ENDPOINT_SIZE) || defined(__DOXYGEN__))\r
+extern uint8_t USB_Device_ControlEndpointSize;\r
+ #else\r
+ #define USB_Device_ControlEndpointSize FIXED_CONTROL_ENDPOINT_SIZE\r
+ #endif\r
+\r
+/* Function Prototypes: */\r
+/**\r
+ * @brief Completes the status stage of a control transfer on a CONTROL type endpoint automatically,\r
+ * with respect to the data direction. This is a convenience function which can be used to\r
+ * simplify user control request handling.\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+void Endpoint_ClearStatusStage(uint8_t corenum);\r
+\r
+/**\r
+ * @brief Spin-loops until the currently selected non-control endpoint is ready for the next packet of data\r
+ * to be read or written to it.\r
+ *\r
+ * @note This routine should not be called on CONTROL type endpoints.\r
+ *\r
+ * @ingroup Group_EndpointRW_LPC18xx\r
+ *\r
+ * @return A value from the @ref Endpoint_WaitUntilReady_ErrorCodes_t enum.\r
+ */\r
+uint8_t Endpoint_WaitUntilReady(void);\r
+\r
+/* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+}\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * @brief Error code returned by Boot ROM drivers/library functions\r
+ * @ingroup Common\r
+ *\r
+ * This file contains unified error codes to be used across driver,\r
+ * middleware, applications, hal and demo software.\r
+ *\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __LPC_ERROR_H__\r
+#define __LPC_ERROR_H__\r
+\r
+/** Error code returned by Boot ROM drivers/library functions\r
+*\r
+* Error codes are a 32-bit value with :\r
+* - The 16 MSB contains the peripheral code number\r
+* - The 16 LSB contains an error code number associated to that peripheral\r
+*\r
+*/\r
+typedef enum\r
+{\r
+ /**\b 0x00000000*/ LPC_OK=0, /**< enum value returned on Success */\r
+ /**\b 0xFFFFFFFF*/ ERR_FAILED = -1, /**< enum value returned on general failure */\r
+\r
+ /* ISP related errors */\r
+ ERR_ISP_BASE = 0x00000000,\r
+ /*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1,\r
+ /*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */\r
+ /*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */\r
+ /*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED,\r
+ /*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED,\r
+ /*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */\r
+ /*0x00000007*/ ERR_ISP_INVALID_SECTOR,\r
+ /*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK,\r
+ /*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,\r
+ /*0x0000000A*/ ERR_ISP_COMPARE_ERROR,\r
+ /*0x0000000B*/ ERR_ISP_BUSY, /* Flash programming hardware interface is busy */\r
+ /*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */\r
+ /*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */\r
+ /*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED,\r
+ /*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */\r
+ /*0x00000010*/ ERR_ISP_INVALID_CODE, /* Unlock code is invalid */\r
+ /*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE,\r
+ /*0x00000012*/ ERR_ISP_INVALID_STOP_BIT,\r
+ /*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED,\r
+\r
+ /* ROM API related errors */\r
+ ERR_API_BASE = 0x00010000,\r
+ /**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1, /**< Invalid parameters*/\r
+ /**\b 0x00010002*/ ERR_API_INVALID_PARAM1, /**< PARAM1 is invalid */\r
+ /**\b 0x00010003*/ ERR_API_INVALID_PARAM2, /**< PARAM2 is invalid */\r
+ /**\b 0x00010004*/ ERR_API_INVALID_PARAM3, /**< PARAM3 is invalid */\r
+ /**\b 0x00010005*/ ERR_API_MOD_INIT, /**< API is called before module init */\r
+\r
+ /* SPIFI API related errors */\r
+ ERR_SPIFI_BASE = 0x00020000,\r
+ /*0x00020001*/ ERR_SPIFI_DEVICE_ERROR =ERR_SPIFI_BASE+1,\r
+ /*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR,\r
+ /*0x00020003*/ ERR_SPIFI_TIMEOUT,\r
+ /*0x00020004*/ ERR_SPIFI_OPERAND_ERROR,\r
+ /*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM,\r
+ /*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT,\r
+ /*0x00020007*/ ERR_SPIFI_UNKNOWN_ID,\r
+ /*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE,\r
+ /*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG,\r
+\r
+ /* Security API related errors */\r
+ ERR_SEC_BASE = 0x00030000,\r
+ /*0x00030001*/ ERR_SEC_AES_WRONG_CMD=ERR_SEC_BASE+1,\r
+ /*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED,\r
+ /*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,\r
+\r
+\r
+ /* USB device stack related errors */\r
+ ERR_USBD_BASE = 0x00040000,\r
+ /**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1, /**< invalid request */\r
+ /**\b 0x00040002*/ ERR_USBD_UNHANDLED, /**< Callback did not process the event */\r
+ /**\b 0x00040003*/ ERR_USBD_STALL, /**< Stall the endpoint on which the call back is called */\r
+ /**\b 0x00040004*/ ERR_USBD_SEND_ZLP, /**< Send ZLP packet on the endpoint on which the call back is called */\r
+ /**\b 0x00040005*/ ERR_USBD_SEND_DATA, /**< Send data packet on the endpoint on which the call back is called */\r
+ /**\b 0x00040006*/ ERR_USBD_BAD_DESC, /**< Bad descriptor*/\r
+ /**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC,/**< Bad config descriptor*/\r
+ /**\b 0x00040009*/ ERR_USBD_BAD_INTF_DESC,/**< Bad interface descriptor*/\r
+ /**\b 0x0004000a*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/\r
+ /**\b 0x0004000b*/ ERR_USBD_BAD_MEM_BUF, /**< Bad alignment of buffer passed. */\r
+ /**\b 0x0004000c*/ ERR_USBD_TOO_MANY_CLASS_HDLR, /**< Too many class handlers. */\r
+\r
+ /* CGU related errors */\r
+ ERR_CGU_BASE = 0x00050000,\r
+ /*0x00050001*/ ERR_CGU_NOT_IMPL=ERR_CGU_BASE+1,\r
+ /*0x00050002*/ ERR_CGU_INVALID_PARAM,\r
+ /*0x00050003*/ ERR_CGU_INVALID_SLICE,\r
+ /*0x00050004*/ ERR_CGU_OUTPUT_GEN,\r
+ /*0x00050005*/ ERR_CGU_DIV_SRC,\r
+ /*0x00050006*/ ERR_CGU_DIV_VAL,\r
+ /*0x00050007*/ ERR_CGU_SRC\r
+\r
+} ErrorCode_t;\r
+\r
+\r
+\r
+//#define offsetof(s,m) (int)&(((s *)0)->m)\r
+#define COMPILE_TIME_ASSERT(pred) switch(0){case 0:case pred:;}\r
+\r
+#endif /* __LPC_ERROR_H__ */\r
--- /dev/null
+/*\r
+ * @brief Common definitions and declarations for the USB ROM based stack\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __USBD_H__\r
+#define __USBD_H__\r
+\r
+/** Common definitions and declarations for the USB stack.\r
+ * @addtogroup USBD_Core\r
+ * @{\r
+ */\r
+\r
+#include <stdint.h>\r
+\r
+#if defined(__GNUC__)\r
+/* As per http://gcc.gnu.org/onlinedocs/gcc/Attribute-Syntax.html#Attribute-Syntax,\r
+6.29 Attributes Syntax\r
+"An attribute specifier list may appear as part of a struct, union or\r
+enum specifier. It may go either immediately after the struct, union\r
+or enum keyword, or after the closing brace. The former syntax is\r
+preferred. Where attribute specifiers follow the closing brace, they\r
+are considered to relate to the structure, union or enumerated type\r
+defined, not to any enclosing declaration the type specifier appears\r
+in, and the type defined is not complete until after the attribute\r
+specifiers."\r
+So use POST_PACK immediately after struct keyword\r
+*/\r
+#define PRE_PACK\r
+#define POST_PACK __attribute__((__packed__))\r
+#define ALIGNED(n) __attribute__((aligned (n)))\r
+#elif defined(__arm)\r
+#define PRE_PACK __packed\r
+#define POST_PACK\r
+#define ALIGNED(n) __align(n)\r
+#elif defined(__ICCARM__)\r
+#define PRE_PACK __packed\r
+#define POST_PACK\r
+#endif\r
+\r
+/** Structure to pack lower and upper byte to form 16 bit word. */\r
+PRE_PACK struct POST_PACK _WB_T\r
+{\r
+ uint8_t L; /**< lower byte */\r
+ uint8_t H; /**< upper byte */\r
+};\r
+/** Structure to pack lower and upper byte to form 16 bit word.*/\r
+typedef struct _WB_T WB_T;\r
+\r
+/** Union of @ref _WB_T struct and 16 bit word.*/\r
+union __WORD_BYTE\r
+{\r
+ PRE_PACK uint16_t POST_PACK W; /**< data member to do 16 bit access */\r
+ WB_T WB; /**< data member to do 8 bit access */\r
+} ;\r
+/** Union of @ref _WB_T struct and 16 bit word.*/\r
+typedef union __WORD_BYTE WORD_BYTE;\r
+\r
+/** bmRequestType.Dir defines\r
+ * @{\r
+ */\r
+/** Request from host to device */\r
+#define REQUEST_HOST_TO_DEVICE 0\r
+/** Request from device to host */\r
+#define REQUEST_DEVICE_TO_HOST 1\r
+/** @} */\r
+\r
+/** bmRequestType.Type defines\r
+ * @{\r
+ */\r
+/** Standard Request */\r
+#define REQUEST_STANDARD 0\r
+/** Class Request */\r
+#define REQUEST_CLASS 1\r
+/** Vendor Request */\r
+#define REQUEST_VENDOR 2\r
+/** Reserved Request */\r
+#define REQUEST_RESERVED 3\r
+/** @} */\r
+\r
+/** bmRequestType.Recipient defines\r
+ * @{\r
+ */\r
+/** Request to device */\r
+#define REQUEST_TO_DEVICE 0\r
+/** Request to interface */\r
+#define REQUEST_TO_INTERFACE 1\r
+/** Request to endpoint */\r
+#define REQUEST_TO_ENDPOINT 2\r
+/** Request to other */\r
+#define REQUEST_TO_OTHER 3\r
+/** @} */\r
+\r
+/** Structure to define 8 bit USB request.*/\r
+PRE_PACK struct POST_PACK _BM_T\r
+{\r
+ uint8_t Recipient : 5; /**< Recipeint type. */\r
+ uint8_t Type : 2; /**< Request type. */\r
+ uint8_t Dir : 1; /**< Directtion type. */\r
+};\r
+/** Structure to define 8 bit USB request.*/\r
+typedef struct _BM_T BM_T;\r
+\r
+/** Union of @ref _BM_T struct and 8 bit byte.*/\r
+union _REQUEST_TYPE\r
+{\r
+// PRE_PACK uint8_t POST_PACK B; /**< byte wide access memeber */\r
+ uint8_t B;\r
+ BM_T BM; /**< bitfield structure access memeber */\r
+} ;\r
+/** Union of @ref _BM_T struct and 8 bit byte.*/\r
+typedef union _REQUEST_TYPE REQUEST_TYPE;\r
+\r
+/** USB Standard Request Codes\r
+ * @{\r
+ */\r
+/** GET_STATUS request */\r
+#define USB_REQUEST_GET_STATUS 0\r
+/** CLEAR_FEATURE request */\r
+#define USB_REQUEST_CLEAR_FEATURE 1\r
+/** SET_FEATURE request */\r
+#define USB_REQUEST_SET_FEATURE 3\r
+/** SET_ADDRESS request */\r
+#define USB_REQUEST_SET_ADDRESS 5\r
+/** GET_DESCRIPTOR request */\r
+#define USB_REQUEST_GET_DESCRIPTOR 6\r
+/** SET_DESCRIPTOR request */\r
+#define USB_REQUEST_SET_DESCRIPTOR 7\r
+/** GET_CONFIGURATION request */\r
+#define USB_REQUEST_GET_CONFIGURATION 8\r
+/** SET_CONFIGURATION request */\r
+#define USB_REQUEST_SET_CONFIGURATION 9\r
+/** GET_INTERFACE request */\r
+#define USB_REQUEST_GET_INTERFACE 10\r
+/** SET_INTERFACE request */\r
+#define USB_REQUEST_SET_INTERFACE 11\r
+/** SYNC_FRAME request */\r
+#define USB_REQUEST_SYNC_FRAME 12\r
+/** @} */\r
+\r
+/** USB GET_STATUS Bit Values\r
+ * @{\r
+ */\r
+/** SELF_POWERED status*/\r
+#define USB_GETSTATUS_SELF_POWERED 0x01\r
+/** REMOTE_WAKEUP capable status*/\r
+#define USB_GETSTATUS_REMOTE_WAKEUP 0x02\r
+/** ENDPOINT_STALL status*/\r
+#define USB_GETSTATUS_ENDPOINT_STALL 0x01\r
+/** @} */\r
+\r
+/** USB Standard Feature selectors\r
+ * @{\r
+ */\r
+/** ENDPOINT_STALL feature*/\r
+#define USB_FEATURE_ENDPOINT_STALL 0\r
+/** REMOTE_WAKEUP feature*/\r
+#define USB_FEATURE_REMOTE_WAKEUP 1\r
+/** TEST_MODE feature*/\r
+#define USB_FEATURE_TEST_MODE 2\r
+/** @} */\r
+\r
+/** USB Default Control Pipe Setup Packet*/\r
+PRE_PACK struct POST_PACK _USB_SETUP_PACKET\r
+{\r
+ REQUEST_TYPE bmRequestType; /**< This bitmapped field identifies the characteristics\r
+ of the specific request. \sa _BM_T.\r
+ */\r
+ uint8_t bRequest; /**< This field specifies the particular request. The\r
+ Type bits in the bmRequestType field modify the meaning\r
+ of this field. \sa USBD_REQUEST.\r
+ */\r
+ WORD_BYTE wValue; /**< Used to pass a parameter to the device, specific\r
+ to the request.\r
+ */\r
+ WORD_BYTE wIndex; /**< Used to pass a parameter to the device, specific\r
+ to the request. The wIndex field is often used in\r
+ requests to specify an endpoint or an interface.\r
+ */\r
+ uint16_t wLength; /**< This field specifies the length of the data\r
+ transferred during the second phase of the control\r
+ transfer.\r
+ */\r
+} ;\r
+/** USB Default Control Pipe Setup Packet*/\r
+typedef struct _USB_SETUP_PACKET USB_SETUP_PACKET;\r
+\r
+\r
+/** USB Descriptor Types\r
+ * @{\r
+ */\r
+/** Device descriptor type */\r
+#define USB_DEVICE_DESCRIPTOR_TYPE 1\r
+/** Configuration descriptor type */\r
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2\r
+/** String descriptor type */\r
+#define USB_STRING_DESCRIPTOR_TYPE 3\r
+/** Interface descriptor type */\r
+#define USB_INTERFACE_DESCRIPTOR_TYPE 4\r
+/** Endpoint descriptor type */\r
+#define USB_ENDPOINT_DESCRIPTOR_TYPE 5\r
+/** Device qualifier descriptor type */\r
+#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6\r
+/** Other speed configuration descriptor type */\r
+#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7\r
+/** Interface power descriptor type */\r
+#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8\r
+/** OTG descriptor type */\r
+#define USB_OTG_DESCRIPTOR_TYPE 9\r
+/** Debug descriptor type */\r
+#define USB_DEBUG_DESCRIPTOR_TYPE 10\r
+/** Interface association descriptor type */\r
+#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11\r
+/** @} */\r
+\r
+/** USB Device Classes\r
+ * @{\r
+ */\r
+/** Reserved device class */\r
+#define USB_DEVICE_CLASS_RESERVED 0x00\r
+/** Audio device class */\r
+#define USB_DEVICE_CLASS_AUDIO 0x01\r
+/** Communications device class */\r
+#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02\r
+/** Human interface device class */\r
+#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03\r
+/** monitor device class */\r
+#define USB_DEVICE_CLASS_MONITOR 0x04\r
+/** physical interface device class */\r
+#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05\r
+/** power device class */\r
+#define USB_DEVICE_CLASS_POWER 0x06\r
+/** Printer device class */\r
+#define USB_DEVICE_CLASS_PRINTER 0x07\r
+/** Storage device class */\r
+#define USB_DEVICE_CLASS_STORAGE 0x08\r
+/** Hub device class */\r
+#define USB_DEVICE_CLASS_HUB 0x09\r
+/** miscellaneous device class */\r
+#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF\r
+/** Application device class */\r
+#define USB_DEVICE_CLASS_APP 0xFE\r
+/** Vendor specific device class */\r
+#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF\r
+/** @} */\r
+\r
+/** bmAttributes in Configuration Descriptor\r
+ * @{\r
+ */\r
+/** Power field mask */\r
+#define USB_CONFIG_POWERED_MASK 0x40\r
+/** Bus powered */\r
+#define USB_CONFIG_BUS_POWERED 0x80\r
+/** Self powered */\r
+#define USB_CONFIG_SELF_POWERED 0xC0\r
+/** remote wakeup */\r
+#define USB_CONFIG_REMOTE_WAKEUP 0x20\r
+/** @} */\r
+\r
+/** bMaxPower in Configuration Descriptor */\r
+//#define USB_CONFIG_POWER_MA(mA) ((mA)/2)\r
+\r
+/** bEndpointAddress in Endpoint Descriptor\r
+ * @{\r
+ */\r
+/** Endopint address mask */\r
+#define USB_ENDPOINT_DIRECTION_MASK 0x80\r
+/** Macro to convert OUT endopint number to endpoint address value. */\r
+#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00)\r
+/** Macro to convert IN endopint number to endpoint address value. */\r
+#define USB_ENDPOINT_IN(addr) ((addr) | 0x80)\r
+/** @} */\r
+\r
+/** bmAttributes in Endpoint Descriptor\r
+ * @{\r
+ */\r
+/** Endopint type mask */\r
+#define USB_ENDPOINT_TYPE_MASK 0x03\r
+/** Control Endopint type */\r
+#define USB_ENDPOINT_TYPE_CONTROL 0x00\r
+/** isochronous Endopint type */\r
+#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01\r
+/** bulk Endopint type */\r
+#define USB_ENDPOINT_TYPE_BULK 0x02\r
+/** interrupt Endopint type */\r
+#define USB_ENDPOINT_TYPE_INTERRUPT 0x03\r
+/** Endopint sync type mask */\r
+#define USB_ENDPOINT_SYNC_MASK 0x0C\r
+/** no synchronization Endopint */\r
+#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00\r
+/** Asynchronous sync Endopint */\r
+#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04\r
+/** Adaptive sync Endopint */\r
+#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08\r
+/** Synchronous sync Endopint */\r
+#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C\r
+/** Endopint usage type mask */\r
+#define USB_ENDPOINT_USAGE_MASK 0x30\r
+/** Endopint data usage type */\r
+#define USB_ENDPOINT_USAGE_DATA 0x00\r
+/** Endopint feedback usage type */\r
+#define USB_ENDPOINT_USAGE_FEEDBACK 0x10\r
+/** Endopint implicit feedback usage type */\r
+#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20\r
+/** Endopint reserved usage type */\r
+#define USB_ENDPOINT_USAGE_RESERVED 0x30\r
+/** @} */\r
+\r
+/** Control endopint EP0's maximum packet size in high-speed mode.*/\r
+#define USB_ENDPOINT_0_HS_MAXP 64\r
+/** Control endopint EP0's maximum packet size in low-speed mode.*/\r
+#define USB_ENDPOINT_0_LS_MAXP 8\r
+/** Bulk endopint's maximum packet size in high-speed mode.*/\r
+#define USB_ENDPOINT_BULK_HS_MAXP 512\r
+\r
+/** USB Standard Device Descriptor */\r
+PRE_PACK struct POST_PACK _USB_DEVICE_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes. */\r
+ uint8_t bDescriptorType; /**< DEVICE Descriptor Type. */\r
+ uint16_t bcdUSB; /**< BUSB Specification Release Number in\r
+ Binary-Coded Decimal (i.e., 2.10 is 210H).\r
+ This field identifies the release of the USB\r
+ Specification with which the device and its\r
+ descriptors are compliant.\r
+ */\r
+ uint8_t bDeviceClass; /**< Class code (assigned by the USB-IF).\r
+ If this field is reset to zero, each interface\r
+ within a configuration specifies its own\r
+ class information and the various\r
+ interfaces operate independently.\n\r
+ If this field is set to a value between 1 and\r
+ FEH, the device supports different class\r
+ specifications on different interfaces and\r
+ the interfaces may not operate\r
+ independently. This value identifies the\r
+ class definition used for the aggregate\r
+ interfaces. \n\r
+ If this field is set to FFH, the device class\r
+ is vendor-specific.\r
+ */\r
+ uint8_t bDeviceSubClass; /**< Subclass code (assigned by the USB-IF).\r
+ These codes are qualified by the value of\r
+ the bDeviceClass field. \n\r
+ If the bDeviceClass field is reset to zero,\r
+ this field must also be reset to zero. \n\r
+ If the bDeviceClass field is not set to FFH,\r
+ all values are reserved for assignment by\r
+ the USB-IF.\r
+ */\r
+ uint8_t bDeviceProtocol; /**< Protocol code (assigned by the USB-IF).\r
+ These codes are qualified by the value of\r
+ the bDeviceClass and the\r
+ bDeviceSubClass fields. If a device\r
+ supports class-specific protocols on a\r
+ device basis as opposed to an interface\r
+ basis, this code identifies the protocols\r
+ that the device uses as defined by the\r
+ specification of the device class. \n\r
+ If this field is reset to zero, the device\r
+ does not use class-specific protocols on a\r
+ device basis. However, it may use classspecific\r
+ protocols on an interface basis. \n\r
+ If this field is set to FFH, the device uses a\r
+ vendor-specific protocol on a device basis.\r
+ */\r
+ uint8_t bMaxPacketSize0; /**< Maximum packet size for endpoint zero\r
+ (only 8, 16, 32, or 64 are valid). For HS devices\r
+ is fixed to 64.\r
+ */\r
+\r
+ uint16_t idVendor; /**< Vendor ID (assigned by the USB-IF). */\r
+ uint16_t idProduct; /**< Product ID (assigned by the manufacturer). */\r
+ uint16_t bcdDevice; /**< Device release number in binary-coded decimal. */\r
+ uint8_t iManufacturer; /**< Index of string descriptor describing manufacturer. */\r
+ uint8_t iProduct; /**< Index of string descriptor describing product. */\r
+ uint8_t iSerialNumber; /**< Index of string descriptor describing the device’s\r
+ serial number.\r
+ */\r
+ uint8_t bNumConfigurations; /**< Number of possible configurations. */\r
+} ;\r
+/** USB Standard Device Descriptor */\r
+typedef struct _USB_DEVICE_DESCRIPTOR USB_DEVICE_DESCRIPTOR;\r
+\r
+/** USB 2.0 Device Qualifier Descriptor */\r
+PRE_PACK struct POST_PACK _USB_DEVICE_QUALIFIER_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of descriptor */\r
+ uint8_t bDescriptorType; /**< Device Qualifier Type */\r
+ uint16_t bcdUSB; /**< USB specification version number (e.g., 0200H for V2.00) */\r
+ uint8_t bDeviceClass; /**< Class Code */\r
+ uint8_t bDeviceSubClass; /**< SubClass Code */\r
+ uint8_t bDeviceProtocol; /**< Protocol Code */\r
+ uint8_t bMaxPacketSize0; /**< Maximum packet size for other speed */\r
+ uint8_t bNumConfigurations; /**< Number of Other-speed Configurations */\r
+ uint8_t bReserved; /**< Reserved for future use, must be zero */\r
+} ;\r
+/** USB 2.0 Device Qualifier Descriptor */\r
+typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR USB_DEVICE_QUALIFIER_DESCRIPTOR;\r
+\r
+/** USB Standard Configuration Descriptor */\r
+PRE_PACK struct POST_PACK _USB_CONFIGURATION_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /**< CONFIGURATION Descriptor Type*/\r
+ uint16_t wTotalLength; /**< Total length of data returned for this\r
+ configuration. Includes the combined length\r
+ of all descriptors (configuration, interface,\r
+ endpoint, and class- or vendor-specific)\r
+ returned for this configuration.*/\r
+ uint8_t bNumInterfaces; /**< Number of interfaces supported by this configuration*/\r
+ uint8_t bConfigurationValue; /**< Value to use as an argument to the\r
+ SetConfiguration() request to select this\r
+ configuration. */\r
+ uint8_t iConfiguration; /**< Index of string descriptor describing this\r
+ configuration*/\r
+ uint8_t bmAttributes; /**< Configuration characteristics \n\r
+ D7: Reserved (set to one)\n\r
+ D6: Self-powered \n\r
+ D5: Remote Wakeup \n\r
+ D4...0: Reserved (reset to zero) \n\r
+ D7 is reserved and must be set to one for\r
+ historical reasons. \n\r
+ A device configuration that uses power from\r
+ the bus and a local source reports a non-zero\r
+ value in bMaxPower to indicate the amount of\r
+ bus power required and sets D6. The actual\r
+ power source at runtime may be determined\r
+ using the GetStatus(DEVICE) request (see\r
+ USB 2.0 spec Section 9.4.5). \n\r
+ If a device configuration supports remote\r
+ wakeup, D5 is set to one.*/\r
+ uint8_t bMaxPower; /**< Maximum power consumption of the USB\r
+ device from the bus in this specific\r
+ configuration when the device is fully\r
+ operational. Expressed in 2 mA units\r
+ (i.e., 50 = 100 mA). \n\r
+ Note: A device configuration reports whether\r
+ the configuration is bus-powered or selfpowered.\r
+ Device status reports whether the\r
+ device is currently self-powered. If a device is\r
+ disconnected from its external power source, it\r
+ updates device status to indicate that it is no\r
+ longer self-powered. \n\r
+ A device may not increase its power draw\r
+ from the bus, when it loses its external power\r
+ source, beyond the amount reported by its\r
+ configuration. \n\r
+ If a device can continue to operate when\r
+ disconnected from its external power source, it\r
+ continues to do so. If the device cannot\r
+ continue to operate, it fails operations it can\r
+ no longer support. The USB System Software\r
+ may determine the cause of the failure by\r
+ checking the status and noting the loss of the\r
+ device’s power source.*/\r
+} ;\r
+/** USB Standard Configuration Descriptor */\r
+typedef struct _USB_CONFIGURATION_DESCRIPTOR USB_CONFIGURATION_DESCRIPTOR;\r
+\r
+/** USB Standard Interface Descriptor */\r
+PRE_PACK struct POST_PACK _USB_INTERFACE_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes*/\r
+ uint8_t bDescriptorType; /**< INTERFACE Descriptor Type*/\r
+ uint8_t bInterfaceNumber; /**< Number of this interface. Zero-based\r
+ value identifying the index in the array of\r
+ concurrent interfaces supported by this\r
+ configuration.*/\r
+ uint8_t bAlternateSetting; /**< Value used to select this alternate setting\r
+ for the interface identified in the prior field*/\r
+ uint8_t bNumEndpoints; /**< Number of endpoints used by this\r
+ interface (excluding endpoint zero). If this\r
+ value is zero, this interface only uses the\r
+ Default Control Pipe.*/\r
+ uint8_t bInterfaceClass; /**< Class code (assigned by the USB-IF). \n\r
+ A value of zero is reserved for future\r
+ standardization. \n\r
+ If this field is set to FFH, the interface\r
+ class is vendor-specific. \n\r
+ All other values are reserved for\r
+ assignment by the USB-IF.*/\r
+ uint8_t bInterfaceSubClass; /**< Subclass code (assigned by the USB-IF). \n\r
+ These codes are qualified by the value of\r
+ the bInterfaceClass field. \n\r
+ If the bInterfaceClass field is reset to zero,\r
+ this field must also be reset to zero. \n\r
+ If the bInterfaceClass field is not set to\r
+ FFH, all values are reserved for\r
+ assignment by the USB-IF.*/\r
+ uint8_t bInterfaceProtocol; /**< Protocol code (assigned by the USB). \n\r
+ These codes are qualified by the value of\r
+ the bInterfaceClass and the\r
+ bInterfaceSubClass fields. If an interface\r
+ supports class-specific requests, this code\r
+ identifies the protocols that the device\r
+ uses as defined by the specification of the\r
+ device class. \n\r
+ If this field is reset to zero, the device\r
+ does not use a class-specific protocol on\r
+ this interface. \n\r
+ If this field is set to FFH, the device uses\r
+ a vendor-specific protocol for this\r
+ interface.*/\r
+ uint8_t iInterface; /**< Index of string descriptor describing this interface*/\r
+} ;\r
+/** USB Standard Interface Descriptor */\r
+typedef struct _USB_INTERFACE_DESCRIPTOR USB_INTERFACE_DESCRIPTOR;\r
+\r
+/** USB Standard Endpoint Descriptor */\r
+PRE_PACK struct POST_PACK _USB_ENDPOINT_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes*/\r
+ uint8_t bDescriptorType; /**< ENDPOINT Descriptor Type*/\r
+ uint8_t bEndpointAddress; /**< The address of the endpoint on the USB device\r
+ described by this descriptor. The address is\r
+ encoded as follows: \n\r
+ Bit 3...0: The endpoint number \n\r
+ Bit 6...4: Reserved, reset to zero \n\r
+ Bit 7: Direction, ignored for control endpoints\r
+ 0 = OUT endpoint\r
+ 1 = IN endpoint. \n \sa USBD_ENDPOINT_ADR_T*/\r
+ uint8_t bmAttributes; /**< This field describes the endpoint’s attributes when it is\r
+ configured using the bConfigurationValue. \n\r
+ Bits 1..0: Transfer Type\r
+ \li 00 = Control\r
+ \li 01 = Isochronous\r
+ \li 10 = Bulk\r
+ \li 11 = Interrupt \n\r
+ If not an isochronous endpoint, bits 5..2 are reserved\r
+ and must be set to zero. If isochronous, they are\r
+ defined as follows: \n\r
+ Bits 3..2: Synchronization Type\r
+ \li 00 = No Synchronization\r
+ \li 01 = Asynchronous\r
+ \li 10 = Adaptive\r
+ \li 11 = Synchronous \n\r
+ Bits 5..4: Usage Type\r
+ \li 00 = Data endpoint\r
+ \li 01 = Feedback endpoint\r
+ \li 10 = Implicit feedback Data endpoint\r
+ \li 11 = Reserved \n\r
+ Refer to Chapter 5 of USB 2.0 specification for more information. \n\r
+ All other bits are reserved and must be reset to zero.\r
+ Reserved bits must be ignored by the host.\r
+ \n \sa USBD_EP_ATTR_T*/\r
+ uint16_t wMaxPacketSize; /**< Maximum packet size this endpoint is capable of\r
+ sending or receiving when this configuration is\r
+ selected. \n\r
+ For isochronous endpoints, this value is used to\r
+ reserve the bus time in the schedule, required for the\r
+ per-(micro)frame data payloads. The pipe may, on an\r
+ ongoing basis, actually use less bandwidth than that\r
+ reserved. The device reports, if necessary, the actual\r
+ bandwidth used via its normal, non-USB defined\r
+ mechanisms. \n\r
+ For all endpoints, bits 10..0 specify the maximum\r
+ packet size (in bytes). \n\r
+ For high-speed isochronous and interrupt endpoints: \n\r
+ Bits 12..11 specify the number of additional transaction\r
+ opportunities per microframe: \n\r
+ \li 00 = None (1 transaction per microframe)\r
+ \li 01 = 1 additional (2 per microframe)\r
+ \li 10 = 2 additional (3 per microframe)\r
+ \li 11 = Reserved \n\r
+ Bits 15..13 are reserved and must be set to zero.*/\r
+ uint8_t bInterval; /**< Interval for polling endpoint for data transfers.\r
+ Expressed in frames or microframes depending on the\r
+ device operating speed (i.e., either 1 millisecond or\r
+ 125 µs units).\r
+ \li For full-/high-speed isochronous endpoints, this value\r
+ must be in the range from 1 to 16. The bInterval value\r
+ is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a\r
+ bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$).\r
+ \li For full-/low-speed interrupt endpoints, the value of\r
+ this field may be from 1 to 255.\r
+ \li For high-speed interrupt endpoints, the bInterval value\r
+ is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a\r
+ bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value\r
+ must be from 1 to 16.\r
+ \li For high-speed bulk/control OUT endpoints, the\r
+ bInterval must specify the maximum NAK rate of the\r
+ endpoint. A value of 0 indicates the endpoint never\r
+ NAKs. Other values indicate at most 1 NAK each\r
+ bInterval number of microframes. This value must be\r
+ in the range from 0 to 255. \n\r
+ Refer to Chapter 5 of USB 2.0 specification for more information.\r
+ */\r
+} ;\r
+/** USB Standard Endpoint Descriptor */\r
+typedef struct _USB_ENDPOINT_DESCRIPTOR USB_ENDPOINT_DESCRIPTOR;\r
+\r
+/** USB String Descriptor */\r
+PRE_PACK struct POST_PACK _USB_STRING_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes*/\r
+ uint8_t bDescriptorType; /**< STRING Descriptor Type*/\r
+ uint16_t bString/*[]*/; /**< UNICODE encoded string */\r
+} ;\r
+/** USB String Descriptor */\r
+typedef struct _USB_STRING_DESCRIPTOR USB_STRING_DESCRIPTOR;\r
+\r
+/** USB Common Descriptor */\r
+PRE_PACK struct POST_PACK _USB_COMMON_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes*/\r
+ uint8_t bDescriptorType; /**< Descriptor Type*/\r
+} ;\r
+/** USB Common Descriptor */\r
+typedef struct _USB_COMMON_DESCRIPTOR USB_COMMON_DESCRIPTOR;\r
+\r
+/** USB Other Speed Configuration */\r
+PRE_PACK struct POST_PACK _USB_OTHER_SPEED_CONFIGURATION\r
+{\r
+ uint8_t bLength; /**< Size of descriptor*/\r
+ uint8_t bDescriptorType; /**< Other_speed_Configuration Type*/\r
+ uint16_t wTotalLength; /**< Total length of data returned*/\r
+ uint8_t bNumInterfaces; /**< Number of interfaces supported by this speed configuration*/\r
+ uint8_t bConfigurationValue; /**< Value to use to select configuration*/\r
+ uint8_t IConfiguration; /**< Index of string descriptor*/\r
+ uint8_t bmAttributes; /**< Same as Configuration descriptor*/\r
+ uint8_t bMaxPower; /**< Same as Configuration descriptor*/\r
+} ;\r
+/** USB Other Speed Configuration */\r
+typedef struct _USB_OTHER_SPEED_CONFIGURATION USB_OTHER_SPEED_CONFIGURATION;\r
+\r
+/** @ingroup USBD_Core\r
+ * USB device stack/module handle.\r
+ */\r
+typedef void* USBD_HANDLE_T;\r
+\r
+#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF)\r
+#define B3VAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF),(((x) >> 16) & 0xFF)\r
+\r
+#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))\r
+#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))\r
+#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))\r
+#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))\r
+#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR))\r
+#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION))\r
+\r
+/** @}*/\r
+uint32_t CALLBACK_UsbdRom_Register_DeviceDescriptor(void);\r
+uint32_t CALLBACK_UsbdRom_Register_ConfigurationDescriptor(void);\r
+uint32_t CALLBACK_UsbdRom_Register_StringDescriptor(void);\r
+uint32_t CALLBACK_UsbdRom_Register_DeviceQualifierDescriptor(void);\r
+uint8_t CALLBACK_UsbdRom_Register_ConfigureEndpoint(void);\r
+#endif /* __USB_H__ */\r
--- /dev/null
+/***********************************************************************
+ * $Id: adc_def.h 8129 2011-09-26 22:49:26Z usb10131 $
+ *
+ * Project: LPC18xx Validation
+ *
+ * Description: USB ADC example project.
+ *
+ * Copyright(C) 2011, NXP Semiconductor
+ * All rights reserved.
+ *
+ ***********************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+#ifndef __AUDIO_H__
+#define __AUDIO_H__
+
+
+/* Audio Interface Subclass Codes */
+#define AUDIO_SUBCLASS_UNDEFINED 0x00
+#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01
+#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02
+#define AUDIO_SUBCLASS_MIDISTREAMING 0x03
+
+/* Audio Interface Protocol Codes */
+#define AUDIO_PROTOCOL_UNDEFINED 0x00
+
+
+/* Audio Descriptor Types */
+#define AUDIO_UNDEFINED_DESCRIPTOR_TYPE 0x20
+#define AUDIO_DEVICE_DESCRIPTOR_TYPE 0x21
+#define AUDIO_CONFIGURATION_DESCRIPTOR_TYPE 0x22
+#define AUDIO_STRING_DESCRIPTOR_TYPE 0x23
+#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24
+#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25
+
+
+/* Audio Control Interface Descriptor Subtypes */
+#define AUDIO_CONTROL_UNDEFINED 0x00
+#define AUDIO_CONTROL_HEADER 0x01
+#define AUDIO_CONTROL_INPUT_TERMINAL 0x02
+#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03
+#define AUDIO_CONTROL_MIXER_UNIT 0x04
+#define AUDIO_CONTROL_SELECTOR_UNIT 0x05
+#define AUDIO_CONTROL_FEATURE_UNIT 0x06
+#define AUDIO_CONTROL_PROCESSING_UNIT 0x07
+#define AUDIO_CONTROL_EXTENSION_UNIT 0x08
+
+/* Audio Streaming Interface Descriptor Subtypes */
+#define AUDIO_STREAMING_UNDEFINED 0x00
+#define AUDIO_STREAMING_GENERAL 0x01
+#define AUDIO_STREAMING_FORMAT_TYPE 0x02
+#define AUDIO_STREAMING_FORMAT_SPECIFIC 0x03
+
+/* Audio Endpoint Descriptor Subtypes */
+#define AUDIO_ENDPOINT_UNDEFINED 0x00
+#define AUDIO_ENDPOINT_GENERAL 0x01
+
+
+/* Audio Descriptor Sizes */
+#define AUDIO_CONTROL_INTERFACE_DESC_SZ(n) (0x08+(n))
+#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07
+#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C
+#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09
+#define AUDIO_MIXER_UNIT_DESC_SZ(p,n) (0x0A+(p)+(n))
+#define AUDIO_SELECTOR_UNIT_DESC_SZ(p) (0x06+(p))
+#define AUDIO_FEATURE_UNIT_DESC_SZ(ch,n) (0x07+((ch)+1)*(n))
+#define AUDIO_PROCESSING_UNIT_DESC_SZ(p,n,x) (0x0D+(p)+(n)+(x))
+#define AUDIO_EXTENSION_UNIT_DESC_SZ(p,n) (0x0D+(p)+(n))
+#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09
+#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07
+
+
+/* Audio Processing Unit Process Types */
+#define AUDIO_UNDEFINED_PROCESS 0x00
+#define AUDIO_UP_DOWN_MIX_PROCESS 0x01
+#define AUDIO_DOLBY_PROLOGIC_PROCESS 0x02
+#define AUDIO_3D_STEREO_PROCESS 0x03
+#define AUDIO_REVERBERATION_PROCESS 0x04
+#define AUDIO_CHORUS_PROCESS 0x05
+#define AUDIO_DYN_RANGE_COMP_PROCESS 0x06
+
+
+/* Audio Request Codes */
+#define AUDIO_REQUEST_UNDEFINED 0x00
+#define AUDIO_REQUEST_SET_CUR 0x01
+#define AUDIO_REQUEST_GET_CUR 0x81
+#define AUDIO_REQUEST_SET_MIN 0x02
+#define AUDIO_REQUEST_GET_MIN 0x82
+#define AUDIO_REQUEST_SET_MAX 0x03
+#define AUDIO_REQUEST_GET_MAX 0x83
+#define AUDIO_REQUEST_SET_RES 0x04
+#define AUDIO_REQUEST_GET_RES 0x84
+#define AUDIO_REQUEST_SET_MEM 0x05
+#define AUDIO_REQUEST_GET_MEM 0x85
+#define AUDIO_REQUEST_GET_STAT 0xFF
+
+
+/* Audio Control Selector Codes */
+#define AUDIO_CONTROL_UNDEFINED 0x00 /* Common Selector */
+
+/* Terminal Control Selectors */
+#define AUDIO_COPY_PROTECT_CONTROL 0x01
+
+/* Feature Unit Control Selectors */
+#define AUDIO_MUTE_CONTROL 0x01
+#define AUDIO_VOLUME_CONTROL 0x02
+#define AUDIO_BASS_CONTROL 0x03
+#define AUDIO_MID_CONTROL 0x04
+#define AUDIO_TREBLE_CONTROL 0x05
+#define AUDIO_GRAPHIC_EQUALIZER_CONTROL 0x06
+#define AUDIO_AUTOMATIC_GAIN_CONTROL 0x07
+#define AUDIO_DELAY_CONTROL 0x08
+#define AUDIO_BASS_BOOST_CONTROL 0x09
+#define AUDIO_LOUDNESS_CONTROL 0x0A
+
+/* Processing Unit Control Selectors: */
+#define AUDIO_ENABLE_CONTROL 0x01 /* Common Selector */
+#define AUDIO_MODE_SELECT_CONTROL 0x02 /* Common Selector */
+
+/* - Up/Down-mix Control Selectors */
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
+/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */
+
+/* - Dolby Prologic Control Selectors */
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
+/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */
+
+/* - 3D Stereo Extender Control Selectors */
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
+#define AUDIO_SPACIOUSNESS_CONTROL 0x02
+
+/* - Reverberation Control Selectors */
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
+#define AUDIO_REVERB_LEVEL_CONTROL 0x02
+#define AUDIO_REVERB_TIME_CONTROL 0x03
+#define AUDIO_REVERB_FEEDBACK_CONTROL 0x04
+
+/* - Chorus Control Selectors */
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
+#define AUDIO_CHORUS_LEVEL_CONTROL 0x02
+#define AUDIO_SHORUS_RATE_CONTROL 0x03
+#define AUDIO_CHORUS_DEPTH_CONTROL 0x04
+
+/* - Dynamic Range Compressor Control Selectors */
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
+#define AUDIO_COMPRESSION_RATE_CONTROL 0x02
+#define AUDIO_MAX_AMPL_CONTROL 0x03
+#define AUDIO_THRESHOLD_CONTROL 0x04
+#define AUDIO_ATTACK_TIME_CONTROL 0x05
+#define AUDIO_RELEASE_TIME_CONTROL 0x06
+
+/* Extension Unit Control Selectors */
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */
+
+/* Endpoint Control Selectors */
+#define AUDIO_SAMPLING_FREQ_CONTROL 0x01
+#define AUDIO_PITCH_CONTROL 0x02
+
+
+/* Audio Format Specific Control Selectors */
+
+/* MPEG Control Selectors */
+#define AUDIO_MPEG_CONTROL_UNDEFINED 0x00
+#define AUDIO_MPEG_DUAL_CHANNEL_CONTROL 0x01
+#define AUDIO_MPEG_SECOND_STEREO_CONTROL 0x02
+#define AUDIO_MPEG_MULTILINGUAL_CONTROL 0x03
+#define AUDIO_MPEG_DYN_RANGE_CONTROL 0x04
+#define AUDIO_MPEG_SCALING_CONTROL 0x05
+#define AUDIO_MPEG_HILO_SCALING_CONTROL 0x06
+
+/* AC-3 Control Selectors */
+#define AUDIO_AC3_CONTROL_UNDEFINED 0x00
+#define AUDIO_AC3_MODE_CONTROL 0x01
+#define AUDIO_AC3_DYN_RANGE_CONTROL 0x02
+#define AUDIO_AC3_SCALING_CONTROL 0x03
+#define AUDIO_AC3_HILO_SCALING_CONTROL 0x04
+
+
+/* Audio Format Types */
+#define AUDIO_FORMAT_TYPE_UNDEFINED 0x00
+#define AUDIO_FORMAT_TYPE_I 0x01
+#define AUDIO_FORMAT_TYPE_II 0x02
+#define AUDIO_FORMAT_TYPE_III 0x03
+
+
+/* Audio Format Type Descriptor Sizes */
+#define AUDIO_FORMAT_TYPE_I_DESC_SZ(n) (0x08+(n*3))
+#define AUDIO_FORMAT_TYPE_II_DESC_SZ(n) (0x09+(n*3))
+#define AUDIO_FORMAT_TYPE_III_DESC_SZ(n) (0x08+(n*3))
+#define AUDIO_FORMAT_MPEG_DESC_SIZE 0x09
+#define AUDIO_FORMAT_AC3_DESC_SIZE 0x0A
+
+
+/* Audio Data Format Codes */
+
+/* Audio Data Format Type I Codes */
+#define AUDIO_FORMAT_TYPE_I_UNDEFINED 0x0000
+#define AUDIO_FORMAT_PCM 0x0001
+#define AUDIO_FORMAT_PCM8 0x0002
+#define AUDIO_FORMAT_IEEE_FLOAT 0x0003
+#define AUDIO_FORMAT_ALAW 0x0004
+#define AUDIO_FORMAT_MULAW 0x0005
+
+/* Audio Data Format Type II Codes */
+#define AUDIO_FORMAT_TYPE_II_UNDEFINED 0x1000
+#define AUDIO_FORMAT_MPEG 0x1001
+#define AUDIO_FORMAT_AC3 0x1002
+
+/* Audio Data Format Type III Codes */
+#define AUDIO_FORMAT_TYPE_III_UNDEFINED 0x2000
+#define AUDIO_FORMAT_IEC1937_AC3 0x2001
+#define AUDIO_FORMAT_IEC1937_MPEG1_L1 0x2002
+#define AUDIO_FORMAT_IEC1937_MPEG1_L2_3 0x2003
+#define AUDIO_FORMAT_IEC1937_MPEG2_NOEXT 0x2003
+#define AUDIO_FORMAT_IEC1937_MPEG2_EXT 0x2004
+#define AUDIO_FORMAT_IEC1937_MPEG2_L1_LS 0x2005
+#define AUDIO_FORMAT_IEC1937_MPEG2_L2_3 0x2006
+
+
+/* Predefined Audio Channel Configuration Bits */
+#define AUDIO_CHANNEL_M 0x0000 /* Mono */
+#define AUDIO_CHANNEL_L 0x0001 /* Left Front */
+#define AUDIO_CHANNEL_R 0x0002 /* Right Front */
+#define AUDIO_CHANNEL_C 0x0004 /* Center Front */
+#define AUDIO_CHANNEL_LFE 0x0008 /* Low Freq. Enhance. */
+#define AUDIO_CHANNEL_LS 0x0010 /* Left Surround */
+#define AUDIO_CHANNEL_RS 0x0020 /* Right Surround */
+#define AUDIO_CHANNEL_LC 0x0040 /* Left of Center */
+#define AUDIO_CHANNEL_RC 0x0080 /* Right of Center */
+#define AUDIO_CHANNEL_S 0x0100 /* Surround */
+#define AUDIO_CHANNEL_SL 0x0200 /* Side Left */
+#define AUDIO_CHANNEL_SR 0x0400 /* Side Right */
+#define AUDIO_CHANNEL_T 0x0800 /* Top */
+
+
+/* Feature Unit Control Bits */
+#define AUDIO_CONTROL_MUTE 0x0001
+#define AUDIO_CONTROL_VOLUME 0x0002
+#define AUDIO_CONTROL_BASS 0x0004
+#define AUDIO_CONTROL_MID 0x0008
+#define AUDIO_CONTROL_TREBLE 0x0010
+#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020
+#define AUDIO_CONTROL_AUTOMATIC_GAIN 0x0040
+#define AUDIO_CONTROL_DEALY 0x0080
+#define AUDIO_CONTROL_BASS_BOOST 0x0100
+#define AUDIO_CONTROL_LOUDNESS 0x0200
+
+/* Processing Unit Control Bits: */
+#define AUDIO_CONTROL_ENABLE 0x0001 /* Common Bit */
+#define AUDIO_CONTROL_MODE_SELECT 0x0002 /* Common Bit */
+
+/* - Up/Down-mix Control Bits */
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
+/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */
+
+/* - Dolby Prologic Control Bits */
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
+/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */
+
+/* - 3D Stereo Extender Control Bits */
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
+#define AUDIO_CONTROL_SPACIOUSNESS 0x0002
+
+/* - Reverberation Control Bits */
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
+#define AUDIO_CONTROL_REVERB_TYPE 0x0002
+#define AUDIO_CONTROL_REVERB_LEVEL 0x0004
+#define AUDIO_CONTROL_REVERB_TIME 0x0008
+#define AUDIO_CONTROL_REVERB_FEEDBACK 0x0010
+
+/* - Chorus Control Bits */
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
+#define AUDIO_CONTROL_CHORUS_LEVEL 0x0002
+#define AUDIO_CONTROL_SHORUS_RATE 0x0004
+#define AUDIO_CONTROL_CHORUS_DEPTH 0x0008
+
+/* - Dynamic Range Compressor Control Bits */
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
+#define AUDIO_CONTROL_COMPRESSION_RATE 0x0002
+#define AUDIO_CONTROL_MAX_AMPL 0x0004
+#define AUDIO_CONTROL_THRESHOLD 0x0008
+#define AUDIO_CONTROL_ATTACK_TIME 0x0010
+#define AUDIO_CONTROL_RELEASE_TIME 0x0020
+
+/* Extension Unit Control Bits */
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */
+
+/* Endpoint Control Bits */
+#define AUDIO_CONTROL_SAMPLING_FREQ 0x01
+#define AUDIO_CONTROL_PITCH 0x02
+#define AUDIO_MAX_PACKETS_ONLY 0x80
+
+
+/* Audio Terminal Types */
+
+/* USB Terminal Types */
+#define AUDIO_TERMINAL_USB_UNDEFINED 0x0100
+#define AUDIO_TERMINAL_USB_STREAMING 0x0101
+#define AUDIO_TERMINAL_USB_VENDOR_SPECIFIC 0x01FF
+
+/* Input Terminal Types */
+#define AUDIO_TERMINAL_INPUT_UNDEFINED 0x0200
+#define AUDIO_TERMINAL_MICROPHONE 0x0201
+#define AUDIO_TERMINAL_DESKTOP_MICROPHONE 0x0202
+#define AUDIO_TERMINAL_PERSONAL_MICROPHONE 0x0203
+#define AUDIO_TERMINAL_OMNI_DIR_MICROPHONE 0x0204
+#define AUDIO_TERMINAL_MICROPHONE_ARRAY 0x0205
+#define AUDIO_TERMINAL_PROCESSING_MIC_ARRAY 0x0206
+
+/* Output Terminal Types */
+#define AUDIO_TERMINAL_OUTPUT_UNDEFINED 0x0300
+#define AUDIO_TERMINAL_SPEAKER 0x0301
+#define AUDIO_TERMINAL_HEADPHONES 0x0302
+#define AUDIO_TERMINAL_HEAD_MOUNTED_AUDIO 0x0303
+#define AUDIO_TERMINAL_DESKTOP_SPEAKER 0x0304
+#define AUDIO_TERMINAL_ROOM_SPEAKER 0x0305
+#define AUDIO_TERMINAL_COMMUNICATION_SPEAKER 0x0306
+#define AUDIO_TERMINAL_LOW_FREQ_SPEAKER 0x0307
+
+/* Bi-directional Terminal Types */
+#define AUDIO_TERMINAL_BIDIRECTIONAL_UNDEFINED 0x0400
+#define AUDIO_TERMINAL_HANDSET 0x0401
+#define AUDIO_TERMINAL_HEAD_MOUNTED_HANDSET 0x0402
+#define AUDIO_TERMINAL_SPEAKERPHONE 0x0403
+#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOSUPRESS 0x0404
+#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOCANCEL 0x0405
+
+/* Telephony Terminal Types */
+#define AUDIO_TERMINAL_TELEPHONY_UNDEFINED 0x0500
+#define AUDIO_TERMINAL_PHONE_LINE 0x0501
+#define AUDIO_TERMINAL_TELEPHONE 0x0502
+#define AUDIO_TERMINAL_DOWN_LINE_PHONE 0x0503
+
+/* External Terminal Types */
+#define AUDIO_TERMINAL_EXTERNAL_UNDEFINED 0x0600
+#define AUDIO_TERMINAL_ANALOG_CONNECTOR 0x0601
+#define AUDIO_TERMINAL_DIGITAL_AUDIO_INTERFACE 0x0602
+#define AUDIO_TERMINAL_LINE_CONNECTOR 0x0603
+#define AUDIO_TERMINAL_LEGACY_AUDIO_CONNECTOR 0x0604
+#define AUDIO_TERMINAL_SPDIF_INTERFACE 0x0605
+#define AUDIO_TERMINAL_1394_DA_STREAM 0x0606
+#define AUDIO_TERMINAL_1394_DA_STREAM_TRACK 0x0607
+
+/* Embedded Function Terminal Types */
+#define AUDIO_TERMINAL_EMBEDDED_UNDEFINED 0x0700
+#define AUDIO_TERMINAL_CALIBRATION_NOISE 0x0701
+#define AUDIO_TERMINAL_EQUALIZATION_NOISE 0x0702
+#define AUDIO_TERMINAL_CD_PLAYER 0x0703
+#define AUDIO_TERMINAL_DAT 0x0704
+#define AUDIO_TERMINAL_DCC 0x0705
+#define AUDIO_TERMINAL_MINI_DISK 0x0706
+#define AUDIO_TERMINAL_ANALOG_TAPE 0x0707
+#define AUDIO_TERMINAL_PHONOGRAPH 0x0708
+#define AUDIO_TERMINAL_VCR_AUDIO 0x0709
+#define AUDIO_TERMINAL_VIDEO_DISC_AUDIO 0x070A
+#define AUDIO_TERMINAL_DVD_AUDIO 0x070B
+#define AUDIO_TERMINAL_TV_TUNER_AUDIO 0x070C
+#define AUDIO_TERMINAL_SATELLITE_RECEIVER_AUDIO 0x070D
+#define AUDIO_TERMINAL_CABLE_TUNER_AUDIO 0x070E
+#define AUDIO_TERMINAL_DSS_AUDIO 0x070F
+#define AUDIO_TERMINAL_RADIO_RECEIVER 0x0710
+#define AUDIO_TERMINAL_RADIO_TRANSMITTER 0x0711
+#define AUDIO_TERMINAL_MULTI_TRACK_RECORDER 0x0712
+#define AUDIO_TERMINAL_SYNTHESIZER 0x0713
+
+
+#endif /* __AUDIO_H__ */
--- /dev/null
+/*
+ * @brief Audio device class ROM based application's specific functions supporting audio class layer
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#define __INCLUDE_FROM_USB_DRIVER
+#include "../../USBMode.h"
+
+#if defined(USB_CAN_BE_DEVICE)
+
+#if defined(USB_DEVICE_ROM_DRIVER) && !(defined(__LPC11U2X_3X__)||defined(__LPC13UXX__))
+#include "../../../Class/AudioClass.h"
+#include "usbd_adcuser.h"
+
+/** Internal definition */
+#define AUDIO_MAX_SAMPLE_FREQ 48000
+
+/* Volume definitions */
+#define VOLUME_MIN 0x0000
+#define VOLUME_MAX 0x003F
+#define VOLUME_RES 0x0001
+
+uint32_t ISO_packet_size = 0;
+
+/* Device Transfer Descriptor used in Custom ROM mode */
+DeviceTransferDescriptor Rom_dTD ATTR_ALIGNED(32);
+/* external Audio Sample Frequency variable */
+extern uint32_t CurrentAudioSampleFrequency;
+/* Current Volume */
+uint32_t curr_vol;
+static uint8_t ISOEndpointNumber;
+static uint8_t StreamInterfaceNumber;
+static uint8_t ControlInterfaceNumber;
+static uint8_t USBPort;
+
+extern uint32_t sample_buffer_size;
+
+extern uint32_t CALLBACK_HAL_GetISOBufferAddress(const uint32_t EPNum, uint32_t* last_packet_size);
+extern void Audio_Reset_Data_Buffer(void);
+extern void Audio_Init (uint32_t samplefreq);
+
+/* inline functions */
+static INLINE DeviceQueueHead* Usbd_GetEpQH(USB_CORE_CTRL_T* pCtrl, uint8_t ep)
+{
+ DeviceQueueHead* ep_QH = (DeviceQueueHead*)(*((uint32_t*)pCtrl->hw_data));
+ uint32_t ep_idx = (ep & 0x0F) << 1;
+
+ if(ep & 0x80)
+ ep_idx++;
+
+ return &ep_QH[ep_idx];
+}
+
+/** Get Transfer packet size */
+static INLINE uint32_t Usbd_GetTransferSize(USB_CORE_CTRL_T *pCtrl, uint8_t ep)
+{
+ DeviceQueueHead *ep_QH = Usbd_GetEpQH(pCtrl, ep);
+ return ep_QH->TransferCount - ep_QH->overlay.TotalBytes;
+}
+
+static void UsbdDcdDataTransfer(uint8_t EPNum, uint8_t *pData, uint32_t length)
+{
+ uint8_t PhyEP = (EPNum<<1) | (EPNum>>7); /* Rotate left without carry */
+ DeviceQueueHead* ep_QH = Usbd_GetEpQH((USB_CORE_CTRL_T*) UsbHandle, EPNum);
+ DeviceTransferDescriptor* pDTD = (DeviceTransferDescriptor*) &Rom_dTD;
+ IP_USBHS_001_T * USB_Reg;
+ USB_Reg = USB_REG(USBPort);
+
+ while ( USB_Reg->ENDPTSTAT & _BIT( EP_Physical2BitPosition(PhyEP) ) ) /* Endpoint is already primed */
+ {
+ }
+
+ /* Zero out the device transfer descriptors */
+ memset((void*)pDTD, 0, sizeof(DeviceTransferDescriptor));
+
+ if(((ENDPTCTRL_REG(USBPort, PhyEP/2)>>2)&EP_TYPE_MASK)==EP_TYPE_ISOCHRONOUS) // iso out endpoint
+ {
+ uint32_t mult = (USB_DATA_BUFFER_TEM_LENGTH + 1024) / 1024;
+ pDTD->NextTD = LINK_TERMINATE ;
+ ep_QH->Mult = mult;
+ }
+ else if(((ENDPTCTRL_REG(USBPort, PhyEP/2)>>18)&EP_TYPE_MASK)==EP_TYPE_ISOCHRONOUS)// iso in endpoint
+ {
+ uint32_t mult = (USB_DATA_BUFFER_TEM_LENGTH + 1024) / 1024;
+ pDTD->NextTD = LINK_TERMINATE;
+ ep_QH->Mult = mult;
+ }
+ else { // other endpoint types
+ pDTD->NextTD = LINK_TERMINATE; /* The next DTD pointer is INVALID */
+ }
+
+ pDTD->TotalBytes = length;
+ pDTD->IntOnComplete = 1;
+ pDTD->Active = 1;
+ pDTD->MultiplierOverride = 1;
+
+ pDTD->BufferPage[0] = (uint32_t) pData;
+ pDTD->BufferPage[1] = ((uint32_t) pData + 0x1000) & 0xfffff000;
+ pDTD->BufferPage[2] = ((uint32_t) pData + 0x2000) & 0xfffff000;
+ pDTD->BufferPage[3] = ((uint32_t) pData + 0x3000) & 0xfffff000;
+ pDTD->BufferPage[4] = ((uint32_t) pData + 0x4000) & 0xfffff000;
+
+ ep_QH->Mult = 1;
+ ep_QH->MaxPacketSize = 512;
+ ep_QH->overlay.NextTD = (uint32_t) pDTD;
+ ep_QH->TransferCount = length;
+
+ /* prime the endpoint for transmit */
+ USB_Reg->ENDPTPRIME |= _BIT( EP_Physical2BitPosition(PhyEP) ) ;
+}
+
+/** Initialize USBD ADC driver */
+void UsbdAdc_Init(USB_ClassInfo_Audio_Device_t* AudioInterface)
+{
+ uint32_t ep_indx;
+ USBD_API->hw->ForceFullSpeed(UsbHandle,1);
+
+ /* register ep0 handler */
+ USBD_API->core->RegisterClassHandler(UsbHandle, UsbdAdc_ep0_hdlr, NULL);
+
+ StreamInterfaceNumber = AudioInterface->Config.StreamingInterfaceNumber;
+ ControlInterfaceNumber = AudioInterface->Config.ControlInterfaceNumber;
+ USBPort = AudioInterface->Config.PortNumber;
+ /* register ISO OUT endpoint interrupt handler */
+ if(AudioInterface->Config.DataOUTEndpointNumber)
+ {
+ ISOEndpointNumber = AudioInterface->Config.DataOUTEndpointNumber;
+ ep_indx = ((ISOEndpointNumber & 0x0F) << 1);
+ USBD_API->core->RegisterEpHandler (UsbHandle, ep_indx, UsbdAdc_ISO_Hdlr, NULL);
+ }
+ else if(AudioInterface->Config.DataINEndpointNumber)
+ {
+ ISOEndpointNumber = AudioInterface->Config.DataINEndpointNumber;
+ ep_indx = ((ISOEndpointNumber & 0x0F) << 1) + 1;
+ USBD_API->core->RegisterEpHandler (UsbHandle, ep_indx, UsbdAdc_ISO_Hdlr, NULL);
+ }
+
+}
+
+/**----------------------------------------------------------------------------
+ ADC_IF_GetRequest: Audio Device Class Interface Get Request Callback
+ Called automatically on ADC Interface Get Request
+ *----------------------------------------------------------------------------*/
+ErrorCode_t ADC_IF_GetRequest (USB_CORE_CTRL_T* pCtrl)
+{
+
+ /*
+ Interface = SetupPacket.wIndex.WB.L;
+ EntityID = SetupPacket.wIndex.WB.H;
+ Request = SetupPacket.bRequest;
+ Value = SetupPacket.wValue.W;
+ ...
+ */
+ ErrorCode_t ret = ERR_USBD_INVALID_REQ;
+
+ if (pCtrl->SetupPacket.wIndex.W == 0x0200) {
+ /* Feature Unit: Interface = 0, ID = 2 */
+ if (pCtrl->SetupPacket.wValue.WB.L == 0) {
+ /* Master Channel */
+ switch (pCtrl->SetupPacket.wValue.WB.H) {
+ case AUDIO_MUTE_CONTROL:
+ if (pCtrl->SetupPacket.bRequest == AUDIO_REQUEST_GET_CUR) {
+ /*TODO: Get MUTE */
+ //pCtrl->EP0Buf[0] = (ADC_PLAY_MUTE)?1:0;
+ ret = LPC_OK;
+ }
+ break;
+ case AUDIO_VOLUME_CONTROL:
+ switch (pCtrl->SetupPacket.bRequest) {
+ case AUDIO_REQUEST_GET_CUR:
+ *((uint16_t *)pCtrl->EP0Buf) = curr_vol;
+ ret = LPC_OK;
+ break;
+ case AUDIO_REQUEST_GET_MIN:
+ *((uint16_t *)pCtrl->EP0Buf) = VOLUME_MIN;
+ ret = LPC_OK;
+ break;
+ case AUDIO_REQUEST_GET_MAX:
+ *((uint16_t *)pCtrl->EP0Buf) = VOLUME_MAX;
+ ret = LPC_OK;
+ break;
+ case AUDIO_REQUEST_GET_RES:
+ *((uint16_t *)pCtrl->EP0Buf) = VOLUME_RES;
+ ret = LPC_OK;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ return (ret); /* Not Supported */
+}
+
+
+/**----------------------------------------------------------------------------
+ ADC_IF_SetRequest: Audio Device Class Interface Set Request Callback
+ Called automatically on ADC Interface Set Request
+ *----------------------------------------------------------------------------*/
+ErrorCode_t ADC_IF_SetRequest (USB_CORE_CTRL_T* pCtrl)
+{
+
+/*
+ Interface = SetupPacket.wIndex.WB.L;
+ EntityID = SetupPacket.wIndex.WB.H;
+ Request = SetupPacket.bRequest;
+ Value = SetupPacket.wValue.W;
+ ...
+*/
+ ErrorCode_t ret = ERR_USBD_INVALID_REQ;
+ if (pCtrl->SetupPacket.wIndex.W == 0x0200) {
+ /* Feature Unit: Interface = 0, ID = 2 */
+ if ((pCtrl->SetupPacket.wValue.WB.L == 0) &&
+ (pCtrl->SetupPacket.bRequest == AUDIO_REQUEST_SET_CUR)) {
+ /* Master Channel */
+ switch (pCtrl->SetupPacket.wValue.WB.H) {
+ case AUDIO_MUTE_CONTROL:
+ if (pCtrl->EP0Buf[0])
+ { /*TODO: set MUTE here */
+ }else
+ { /*TODO: disable MUTE here */
+ }
+ ret = (LPC_OK);
+ break;
+ case AUDIO_VOLUME_CONTROL:
+ /*TODO: Set volume here */
+ curr_vol = *((uint16_t *)pCtrl->EP0Buf);
+ ret = (LPC_OK);
+ break;
+ }
+ }
+ }
+
+ return ret; /* Not Supported */
+}
+
+
+/**----------------------------------------------------------------------------
+ ADC_EP_GetRequest: Audio Device Class EndPoint Get Request Callback
+ Called automatically on ADC EndPoint Get Request
+ *----------------------------------------------------------------------------*/
+ErrorCode_t ADC_EP_GetRequest (USB_CORE_CTRL_T* pCtrl)
+{
+ /*
+ EndPoint = SetupPacket.wIndex.WB.L;
+ Request = SetupPacket.bRequest;
+ Value = SetupPacket.wValue.W;
+ ...
+ */
+ ErrorCode_t ret = ERR_USBD_INVALID_REQ;
+
+ if((pCtrl->SetupPacket.wIndex.W & 0x7F) == ISOEndpointNumber) {
+ /* Feature Unit: Interface = 0, ID = 2 */
+ if (pCtrl->SetupPacket.wValue.WB.L == 0) {
+ /* Master Channel */
+ if ((pCtrl->SetupPacket.wValue.WB.H == AUDIO_CONTROL_SAMPLING_FREQ) &&
+ (pCtrl->SetupPacket.bRequest == AUDIO_REQUEST_GET_CUR) ) {
+ pCtrl->EP0Buf[0] = (uint8_t)(CurrentAudioSampleFrequency & 0xFF);
+ pCtrl->EP0Buf[1] = (uint8_t)((CurrentAudioSampleFrequency >> 8) & 0xFF);
+ pCtrl->EP0Buf[2] = (uint8_t)((CurrentAudioSampleFrequency >> 16) & 0xFF);
+ ret = (LPC_OK);
+ }
+ }
+ }
+ return ret; /* Not Supported */
+}
+
+
+/**----------------------------------------------------------------------------
+ ADC_EP_SetRequest: Audio Device Class EndPoint Set Request Callback
+ Called automatically on ADC EndPoint Set Request
+ *----------------------------------------------------------------------------*/
+ErrorCode_t ADC_EP_SetRequest (USB_CORE_CTRL_T* pCtrl)
+{
+
+ /*
+ EndPoint = SetupPacket.wIndex.WB.L;
+ Request = SetupPacket.bRequest;
+ Value = SetupPacket.wValue.W;
+ ...
+ */
+ uint32_t rate;
+ ErrorCode_t ret = ERR_USBD_INVALID_REQ;
+
+ if((pCtrl->SetupPacket.wIndex.W & 0x7F) == ISOEndpointNumber) {
+ /* Feature Unit: Interface = 0, ID = 2 */
+ if (pCtrl->SetupPacket.wValue.WB.L == 0) {
+ /* Master Channel */
+ if (pCtrl->SetupPacket.wValue.WB.H == AUDIO_CONTROL_SAMPLING_FREQ) {
+ rate = pCtrl->EP0Buf[0] | (pCtrl->EP0Buf[1] << 8) | (pCtrl->EP0Buf[2] << 16);
+ if (pCtrl->SetupPacket.bRequest == AUDIO_REQUEST_SET_CUR) {
+ CurrentAudioSampleFrequency = rate;
+ if(CurrentAudioSampleFrequency <= AUDIO_MAX_SAMPLE_FREQ)
+ {
+ Audio_Init(CurrentAudioSampleFrequency);
+ ret = LPC_OK;
+ }
+ }
+ }
+ }
+ }
+ return (ret); /* Not Supported */
+}
+
+/**----------------------------------------------------------------------------
+ Override standard Interface Event
+ *----------------------------------------------------------------------------*/
+ErrorCode_t USB_Interface_Event (USBD_HANDLE_T hUsb)
+{
+ USB_CORE_CTRL_T* pCtrl = (USB_CORE_CTRL_T*)hUsb;
+ uint16_t wIndex = pCtrl->SetupPacket.wIndex.W;
+ uint16_t wValue = pCtrl->SetupPacket.wValue.W;
+
+ /* write code to enable/disable audo playback when interface
+ ALT setting is changed */
+ if (wIndex == StreamInterfaceNumber) {
+ if((wValue == 0x0001)){
+ UsbdAdc_start_xfr();
+ }else
+ {
+ UsbdAdc_stop_xfr();
+ }
+
+ }
+
+ return LPC_OK;
+}
+/** disable configure event in usbd_rom.c */
+ErrorCode_t USB_Configure_Event (USBD_HANDLE_T hUsb)
+{
+ return LPC_OK;
+}
+
+#if defined(__ICCARM__)
+/* Temp fix for IAR */
+uint32_t TransferDelayidx=0;
+volatile uint8_t Event_store[128];
+#endif
+
+/**----------------------------------------------------------------------------
+ Audio Class handler
+ *----------------------------------------------------------------------------*/
+ErrorCode_t UsbdAdc_ep0_hdlr(USBD_HANDLE_T hUsb, void* data, uint32_t event)
+{
+ USB_CORE_CTRL_T* pCtrl = (USB_CORE_CTRL_T*)hUsb;
+ ErrorCode_t ret = ERR_USBD_UNHANDLED;
+
+ #if defined(__ICCARM__)
+ /* Temp fix for IAR */
+ Event_store[TransferDelayidx] = event;
+ #endif
+
+ if (pCtrl->SetupPacket.bmRequestType.BM.Type == REQUEST_CLASS) {
+ switch (event) {
+ case USB_EVT_SETUP:
+ if ((pCtrl->SetupPacket.bmRequestType.BM.Recipient == REQUEST_TO_INTERFACE) &&
+ ((pCtrl->SetupPacket.wIndex.WB.L == ControlInterfaceNumber) || /* IF number correct? */
+ (pCtrl->SetupPacket.wIndex.WB.L == StreamInterfaceNumber)) ) {
+ switch (pCtrl->SetupPacket.bRequest) {
+ case AUDIO_REQUEST_GET_CUR:
+ case AUDIO_REQUEST_GET_MIN:
+ case AUDIO_REQUEST_GET_MAX:
+ case AUDIO_REQUEST_GET_RES:
+
+ ret = ADC_IF_GetRequest(pCtrl);
+ if (ret == LPC_OK) {
+ pCtrl->EP0Data.pData = pCtrl->EP0Buf; /* point to data to be sent */
+ USBD_API->core->DataInStage(pCtrl); /* send requested data */
+ }
+ break;
+ case AUDIO_REQUEST_SET_CUR:
+ // case AUDIO_REQUEST_SET_MIN:
+ // case AUDIO_REQUEST_SET_MAX:
+ // case AUDIO_REQUEST_SET_RES:
+ pCtrl->EP0Data.pData = pCtrl->EP0Buf; /* data to be received */
+
+ ret = LPC_OK;
+ break;
+ }
+ }
+ else if (pCtrl->SetupPacket.bmRequestType.BM.Recipient == REQUEST_TO_ENDPOINT) {
+ switch (pCtrl->SetupPacket.bRequest) {
+ case AUDIO_REQUEST_GET_CUR:
+ case AUDIO_REQUEST_GET_MIN:
+ case AUDIO_REQUEST_GET_MAX:
+ case AUDIO_REQUEST_GET_RES:
+ ret = ADC_EP_GetRequest(pCtrl);
+ if (ret == LPC_OK) {
+ pCtrl->EP0Data.pData = pCtrl->EP0Buf; /* point to data to be sent */
+ USBD_API->core->DataInStage(pCtrl); /* send requested data */
+ }
+ break;
+ case AUDIO_REQUEST_SET_CUR:
+ // case AUDIO_REQUEST_SET_MIN:
+ // case AUDIO_REQUEST_SET_MAX:
+ // case AUDIO_REQUEST_SET_RES:
+ pCtrl->EP0Data.pData = pCtrl->EP0Buf; /* data to be received */
+ ret = LPC_OK;
+ break;
+ }
+ }
+ break;
+ case USB_EVT_OUT:
+ if ((pCtrl->SetupPacket.bmRequestType.BM.Recipient == REQUEST_TO_INTERFACE) &&
+ ((pCtrl->SetupPacket.wIndex.WB.L == ControlInterfaceNumber) || /* IF number correct? */
+ (pCtrl->SetupPacket.wIndex.WB.L == StreamInterfaceNumber)) ) {
+ switch (pCtrl->SetupPacket.bRequest) {
+ case AUDIO_REQUEST_SET_CUR:
+ // case AUDIO_REQUEST_SET_MIN:
+ // case AUDIO_REQUEST_SET_MAX:
+ // case AUDIO_REQUEST_SET_RES:
+ ret = ADC_IF_SetRequest(pCtrl);
+ if (ret == LPC_OK) {
+ USBD_API->core->StatusInStage(pCtrl); /* send Acknowledge */
+ }
+ break;
+ }
+ } else if (pCtrl->SetupPacket.bmRequestType.BM.Recipient == REQUEST_TO_ENDPOINT) {
+ switch (pCtrl->SetupPacket.bRequest) {
+ case AUDIO_REQUEST_SET_CUR:
+ // case AUDIO_REQUEST_SET_MIN:
+ // case AUDIO_REQUEST_SET_MAX:
+ // case AUDIO_REQUEST_SET_RES:
+ ret = ADC_EP_SetRequest(pCtrl);
+ if (ret == LPC_OK) {
+ USBD_API->core->StatusInStage(pCtrl); /* send Acknowledge */
+ }
+ break;
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+ return ret;
+}
+
+/**----------------------------------------------------------------------------
+ Audio Start Transfer Callback
+ *----------------------------------------------------------------------------*/
+void UsbdAdc_start_xfr(void)
+{
+ ISO_packet_size = 0;
+ uint32_t ISO_buffer_address;
+ /* reset audio buffer */
+ Audio_Reset_Data_Buffer();
+ ISO_buffer_address = CALLBACK_HAL_GetISOBufferAddress(USB_ENDPOINT_IN(ISOEndpointNumber), &ISO_packet_size);
+ if(ISO_buffer_address != 0)
+ UsbdDcdDataTransfer(USB_ENDPOINT_IN(ISOEndpointNumber), (uint8_t*)ISO_buffer_address, ISO_packet_size);
+
+ ISO_buffer_address = CALLBACK_HAL_GetISOBufferAddress(ISOEndpointNumber, &ISO_packet_size);
+ if(ISO_buffer_address != 0)
+ UsbdDcdDataTransfer(ISOEndpointNumber, (uint8_t*)ISO_buffer_address, 512);
+}
+
+/**----------------------------------------------------------------------------
+ Audio Stop Transfer Callback
+ *----------------------------------------------------------------------------*/
+void UsbdAdc_stop_xfr(void)
+{
+ ISO_packet_size = 0;
+ /* reset audio buffer */
+ Audio_Reset_Data_Buffer();
+ USBD_API->hw->ResetEP(UsbHandle, ISOEndpointNumber);
+ USBD_API->hw->ResetEP(UsbHandle, USB_ENDPOINT_IN(ISOEndpointNumber));
+}
+
+
+/**----------------------------------------------------------------------------
+ Audio ISO handler
+ *----------------------------------------------------------------------------*/
+ErrorCode_t UsbdAdc_ISO_Hdlr (USBD_HANDLE_T hUsb, void* data, uint32_t event)
+{
+ uint32_t ISO_buffer_address;
+
+ if (event == USB_EVT_OUT) {
+ ISO_packet_size = Usbd_GetTransferSize((USB_CORE_CTRL_T *) hUsb, ISOEndpointNumber);
+ if (ISO_packet_size != 0) {
+ ISO_packet_size = ISO_packet_size;
+ }
+ /* Send DMA request */
+ ISO_buffer_address = CALLBACK_HAL_GetISOBufferAddress(ISOEndpointNumber, &ISO_packet_size);
+ UsbdDcdDataTransfer(ISOEndpointNumber, (uint8_t *) ISO_buffer_address, 512);
+ }
+
+ if (event == USB_EVT_IN)
+ {
+ /* Send DMA request */
+ ISO_buffer_address = CALLBACK_HAL_GetISOBufferAddress(USB_ENDPOINT_IN(ISOEndpointNumber), &ISO_packet_size);
+ UsbdDcdDataTransfer(USB_ENDPOINT_IN(ISOEndpointNumber), (uint8_t*)ISO_buffer_address, ISO_packet_size);
+ }
+
+ return LPC_OK;
+}
+
+#endif
+#endif
--- /dev/null
+/*
+ * @brief Audio device class ROM based application's specific functions supporting audio class layer
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ADC_USER_H__
+#define __ADC_USER_H__
+
+//#include "error.h"
+//#include "usbd.h"
+#include "usbd_adc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup Audio_Input_Device_ROM_Based_Audio_Device_Class ROM based class audio
+ * @ingroup Audio_Input_Device_ROM_Based
+ * @{
+ */
+
+
+/**
+ * @brief Initialize ROM based audio device class
+ * @return Nothing
+ */
+extern void UsbdAdc_Init(USB_ClassInfo_Audio_Device_t* AudioInterface);
+
+/**
+ * @brief Start streaming audio data
+ * @return Nothing
+ */
+extern void UsbdAdc_start_xfr(void);
+
+/**
+ * @brief Stop streaming audio data
+ * @return Nothing
+ */
+extern void UsbdAdc_stop_xfr(void);
+
+/**
+ * @brief Determind start or stop transfer audio data
+ * @param hUsb : Global USB ROM based handle variable
+ * @return ErrorCode_t : LPC_OK for success
+ */
+extern ErrorCode_t USB_Interface_Event (USBD_HANDLE_T hUsb);
+
+/**
+ * @brief Handle response to IN isochronous coming packets
+ * @param hUsb : Global USB ROM based handle variable
+ * @param data : Pointer point to buffer storing received data
+ * @param event : USB_EVT_IN only acceptable value
+ * @return ErrorCode_t : LPC_OK for success
+ */
+extern ErrorCode_t UsbdAdc_ISO_Hdlr (USBD_HANDLE_T hUsb, void* data, uint32_t event);
+
+/**
+ * @brief Handle response to standard requests (chapter9) from host
+ * @param hUsb : Global USB ROM based handle variable
+ * @param data : no used
+ * @param event : USB_EVT_OUT, USB_EVT_SETUP
+ * @return ErrorCode_t : LPC_OK for success, ERR_USBD_UNHANDLED otherwise
+ */
+extern ErrorCode_t UsbdAdc_ep0_hdlr(USBD_HANDLE_T hUsb, void* data, uint32_t event);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_USER_H__ */
--- /dev/null
+/*\r
+ * @brief Boot ROM drivers/library USB Communication Device Class Definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+#include "../../Device.h"\r
+#include "../../Endpoint.h"\r
+\r
+#if defined(USB_DEVICE_ROM_DRIVER)\r
+\r
+/** Internal definition */\r
+/* FIXME Abstract & make this size configurable */\r
+//#define ROMDRIVER_CDC_MEM_SIZE 0x800\r
+#define ROMDRIVER_CDC_DATA_BUFFER_SIZE 640\r
+#define CDC_EP_SIZE (CALLBACK_UsbdCdc_Register_DataOutEndpointSize())\r
+#if (USB_FORCED_FULLSPEED)\r
+ #define CDC_MAX_BULK_EP_SIZE 64\r
+#else\r
+ #define CDC_MAX_BULK_EP_SIZE 512\r
+#endif\r
+\r
+/** Circle Buffer Type */\r
+typedef struct {\r
+ uint8_t data[ROMDRIVER_CDC_DATA_BUFFER_SIZE];\r
+ volatile uint32_t rd_index;\r
+ volatile uint32_t wr_index;\r
+ volatile uint32_t count;\r
+} CDC_CIRCLE_BUFFER_T;\r
+\r
+//uint8_t usb_RomDriver_CDC_buffer[ROMDRIVER_CDC_MEM_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+CDC_LINE_CODING* UsbdCdcLineCoding;\r
+USBD_HANDLE_T UsbdCdcHdlr; //what is this for?\r
+\r
+/** Endpoint IN buffer, used for DMA operation */\r
+//uint8_t UsbdCdc_EPIN_buffer[CDC_MAX_BULK_EP_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+volatile uint32_t UsbdCdc_EPIN_buffer_count = 0;\r
+/** Endpoint OUT buffer, used for DMA operation */\r
+//uint8_t UsbdCdc_EPOUT_buffer[CDC_MAX_BULK_EP_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+volatile uint32_t UsbdCdc_EPOUT_buffer_index = 0;\r
+volatile uint32_t UsbdCdc_EPOUT_buffer_count = 0;\r
+\r
+CDC_CIRCLE_BUFFER_T UsbdCdc_OUT_buffer, UsbdCdc_IN_buffer;\r
+\r
+ErrorCode_t UsbdCdc_Bulk_OUT_Hdlr(USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+ErrorCode_t UsbdCdc_Bulk_IN_Hdlr(USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+void UsbdCdc_OUT_Buffer_Reset(void)\r
+{\r
+ UsbdCdc_OUT_buffer.rd_index = 0;\r
+ UsbdCdc_OUT_buffer.wr_index = 0;\r
+ UsbdCdc_OUT_buffer.count = 0;\r
+}\r
+\r
+void UsbdCdc_IN_Buffer_Reset(void)\r
+{\r
+ UsbdCdc_IN_buffer.rd_index = 0;\r
+ UsbdCdc_IN_buffer.wr_index = 0;\r
+ UsbdCdc_IN_buffer.count = 0;\r
+}\r
+\r
+PRAGMA_WEAK(EVENT_UsbdCdc_SetLineCode,EVENT_UsbdCdc_SetLineCode_Stub)\r
+void EVENT_UsbdCdc_SetLineCode(CDC_LINE_CODING* line_coding) ATTR_WEAK ATTR_ALIAS(EVENT_UsbdCdc_SetLineCode_Stub);\r
+\r
+/** Set Line Coding Handler */\r
+ErrorCode_t CALLBACK_UsbdCdc_SetLineCode(USBD_HANDLE_T hCDC, CDC_LINE_CODING* line_coding)\r
+{\r
+ memcpy(UsbdCdcLineCoding, line_coding, sizeof(CDC_LINE_CODING));\r
+ EVENT_UsbdCdc_SetLineCode(line_coding);\r
+ return LPC_OK;\r
+}\r
+\r
+/** Initialize USBD CDC driver */\r
+void UsbdCdc_Init(void)\r
+{\r
+ USBD_CDC_INIT_PARAM_T cdc_param;\r
+ uint32_t ep_indx;\r
+ memset((void*)&cdc_param, 0, sizeof(USBD_CDC_INIT_PARAM_T));\r
+ UsbdCdcLineCoding = (CDC_LINE_CODING*)CALLBACK_UsbdCdc_Register_LineCoding();\r
+\r
+ /* CDC paramas */\r
+ cdc_param.mem_base = (uint32_t)usb_RomDriver_CDC_buffer;\r
+ cdc_param.mem_size = (uint32_t)ROMDRIVER_CDC_MEM_SIZE;\r
+ cdc_param.cif_intf_desc = (uint8_t*)CALLBACK_UsbdCdc_Register_ControlInterfaceDescriptor();\r
+ cdc_param.dif_intf_desc = (uint8_t*)CALLBACK_UsbdCdc_Register_DataInterfaceDescriptor();\r
+ /* user defined functions */\r
+ cdc_param.SetLineCode = CALLBACK_UsbdCdc_SetLineCode;\r
+\r
+ /* register Bulk IN endpoint interrupt handler */\r
+ ep_indx = (((CALLBACK_UsbdCdc_Register_DataInEndpointNumber() & 0x0F) << 1) + 1);\r
+ USBD_API->core->RegisterEpHandler (UsbHandle, ep_indx, UsbdCdc_Bulk_IN_Hdlr, NULL);\r
+ \r
+ /* register Bulk OUT endpoint interrupt handler */\r
+ ep_indx = ((CALLBACK_UsbdCdc_Register_DataOutEndpointNumber() & 0x0F) << 1);\r
+ USBD_API->core->RegisterEpHandler (UsbHandle, ep_indx, UsbdCdc_Bulk_OUT_Hdlr, NULL);\r
+\r
+ UsbdCdc_OUT_Buffer_Reset();\r
+ UsbdCdc_IN_Buffer_Reset();\r
+ USBD_API->cdc->init(UsbHandle, &cdc_param, &UsbdCdcHdlr);\r
+}\r
+\r
+\r
+/** This is blocking send function */\r
+void UsbdCdc_SendData(uint8_t* buffer, uint32_t cnt)\r
+{\r
+ uint32_t buffer_index = 0;\r
+ //uint8_t EpAdd = USB_ENDPOINT_IN(CALLBACK_UsbdCdc_Register_DataInEndpointNumber());\r
+ while(cnt)\r
+ {\r
+ if(UsbdCdc_IN_buffer.count <= ROMDRIVER_CDC_DATA_BUFFER_SIZE)\r
+ {\r
+ UsbdCdc_IN_buffer.data[UsbdCdc_IN_buffer.wr_index] = buffer[buffer_index++];\r
+ UsbdCdc_IN_buffer.wr_index++;\r
+ UsbdCdc_IN_buffer.wr_index &= (ROMDRIVER_CDC_DATA_BUFFER_SIZE -1);\r
+ UsbdCdc_IN_buffer.count++;\r
+ cnt--;\r
+ }\r
+ }\r
+}\r
+\r
+/** Receive data to user buffer */\r
+uint32_t UsbdCdc_RecvData(uint8_t* buffer, uint32_t len)\r
+{\r
+ uint32_t avail_len, i;\r
+ if(UsbdCdc_OUT_buffer.count > len)\r
+ {\r
+ avail_len = len;\r
+ }else\r
+ {\r
+ avail_len = UsbdCdc_OUT_buffer.count;\r
+ }\r
+ for(i=0; i<avail_len;i++)\r
+ {\r
+ buffer[i] = UsbdCdc_OUT_buffer.data[UsbdCdc_OUT_buffer.rd_index];\r
+ UsbdCdc_OUT_buffer.rd_index++;\r
+ UsbdCdc_OUT_buffer.rd_index &= (ROMDRIVER_CDC_DATA_BUFFER_SIZE - 1);\r
+ UsbdCdc_OUT_buffer.count--;\r
+ }\r
+ return avail_len;\r
+}\r
+\r
+/** sync EP buffer(DMA) and CDC driver IO buffer */\r
+void UsbdCdc_IO_Buffer_Sync_Task(void)\r
+{\r
+ uint32_t avail_count, i;\r
+\r
+ /* Sync OUT EP task */\r
+ avail_count = ROMDRIVER_CDC_DATA_BUFFER_SIZE - UsbdCdc_OUT_buffer.count;\r
+ if(avail_count > UsbdCdc_EPOUT_buffer_count)\r
+ {\r
+ avail_count = UsbdCdc_EPOUT_buffer_count;\r
+ }\r
+ for(i=0; i<avail_count; i++)\r
+ {\r
+ uint8_t t = UsbdCdc_EPOUT_buffer[UsbdCdc_EPOUT_buffer_index];\r
+ UsbdCdc_OUT_buffer.data[UsbdCdc_OUT_buffer.wr_index] = t;\r
+ UsbdCdc_EPOUT_buffer_index++;\r
+\r
+ UsbdCdc_OUT_buffer.count++;\r
+ UsbdCdc_OUT_buffer.wr_index++;\r
+ UsbdCdc_OUT_buffer.wr_index &= (ROMDRIVER_CDC_DATA_BUFFER_SIZE - 1);\r
+ /* Sync 2 buffers must be implemented when all other tasks completed */\r
+ UsbdCdc_EPOUT_buffer_count--;\r
+ }\r
+\r
+ /* Sync IN EP task */\r
+ if(UsbdCdc_EPIN_buffer_count == 0){\r
+ if(UsbdCdc_IN_buffer.count > CDC_EP_SIZE)\r
+ {\r
+ avail_count = CDC_EP_SIZE;\r
+ }else\r
+ {\r
+ avail_count = UsbdCdc_IN_buffer.count;\r
+ }\r
+ \r
+ for(i=0; i<avail_count; i++)\r
+ {\r
+ UsbdCdc_EPIN_buffer[i] = UsbdCdc_IN_buffer.data[UsbdCdc_IN_buffer.rd_index];\r
+ UsbdCdc_IN_buffer.rd_index++;\r
+ UsbdCdc_IN_buffer.rd_index &= (ROMDRIVER_CDC_DATA_BUFFER_SIZE - 1);\r
+ UsbdCdc_IN_buffer.count --;\r
+ }\r
+ /* Sync 2 buffers must be implemented when all other tasks completed */\r
+ UsbdCdc_EPIN_buffer_count = avail_count;\r
+ }\r
+}\r
+\r
+ErrorCode_t UsbdCdc_Bulk_OUT_Hdlr(USBD_HANDLE_T hUsb, void* data, uint32_t event)\r
+{\r
+ uint8_t EpAdd = USB_ENDPOINT_OUT(CALLBACK_UsbdCdc_Register_DataOutEndpointNumber());\r
+ if (event == USB_EVT_OUT)\r
+ {\r
+ UsbdCdc_EPOUT_buffer_count = USBD_API->hw->ReadEP(UsbHandle, EpAdd, UsbdCdc_EPOUT_buffer);\r
+ }\r
+ else if(event == USB_EVT_OUT_NAK)\r
+ {\r
+ if(UsbdCdc_EPOUT_buffer_count == 0)\r
+ {\r
+ /* Reset EP OUT buffer */\r
+ UsbdCdc_EPOUT_buffer_index = 0;\r
+ /* Send DMA request */\r
+ USBD_API->hw->ReadReqEP(UsbHandle, EpAdd, UsbdCdc_EPOUT_buffer, CDC_EP_SIZE);\r
+ }\r
+ }\r
+ return LPC_OK;\r
+}\r
+\r
+ErrorCode_t UsbdCdc_Bulk_IN_Hdlr(USBD_HANDLE_T hUsb, void* data, uint32_t event)\r
+{\r
+ uint8_t EpAdd = USB_ENDPOINT_IN(CALLBACK_UsbdCdc_Register_DataInEndpointNumber());\r
+ \r
+ if (event == USB_EVT_IN)\r
+ {\r
+ USBD_API->hw->WriteEP(UsbHandle, EpAdd, UsbdCdc_EPIN_buffer,UsbdCdc_EPIN_buffer_count);\r
+ /* Clear EP buffer */\r
+ UsbdCdc_EPIN_buffer_count = 0;\r
+ }\r
+ return LPC_OK;\r
+}\r
+\r
+void UsbdCdc_EVENT_Stub(void* param)\r
+{\r
+\r
+}\r
+void EVENT_UsbdCdc_SetLineCode_Stub(CDC_LINE_CODING* line_coding)\r
+{\r
+\r
+}\r
+#endif /* USB_DEVICE_ROM_DRIVER */\r
+\r
+#endif /* USB_CAN_BE_DEVICE */\r
--- /dev/null
+/*\r
+ * @brief Boot ROM drivers/library USB Communication Device Class Definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CDC_H\r
+#define __CDC_H\r
+\r
+#include "usbd.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions based on usbcdc11.pdf (www.usb.org)\r
+ *---------------------------------------------------------------------------*/\r
+/* Communication device class specification version 1.10 */\r
+#define CDC_V1_10 0x0110\r
+\r
+/* Communication interface class code */\r
+/* (usbcdc11.pdf, 4.2, Table 15) */\r
+#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02\r
+\r
+/* Communication interface class subclass codes */\r
+/* (usbcdc11.pdf, 4.3, Table 16) */\r
+#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01\r
+#define CDC_ABSTRACT_CONTROL_MODEL 0x02\r
+#define CDC_TELEPHONE_CONTROL_MODEL 0x03\r
+#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04\r
+#define CDC_CAPI_CONTROL_MODEL 0x05\r
+#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06\r
+#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07\r
+\r
+/* Communication interface class control protocol codes */\r
+/* (usbcdc11.pdf, 4.4, Table 17) */\r
+#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01\r
+\r
+/* Data interface class code */\r
+/* (usbcdc11.pdf, 4.5, Table 18) */\r
+#define CDC_DATA_INTERFACE_CLASS 0x0A\r
+\r
+/* Data interface class protocol codes */\r
+/* (usbcdc11.pdf, 4.7, Table 19) */\r
+#define CDC_PROTOCOL_ISDN_BRI 0x30\r
+#define CDC_PROTOCOL_HDLC 0x31\r
+#define CDC_PROTOCOL_TRANSPARENT 0x32\r
+#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50\r
+#define CDC_PROTOCOL_Q921_DATA_LINK 0x51\r
+#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52\r
+#define CDC_PROTOCOL_V42 0x90\r
+#define CDC_PROTOCOL_EURO_ISDN 0x91\r
+#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92\r
+#define CDC_PROTOCOL_CAPI 0x93\r
+#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD\r
+#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE\r
+\r
+/* Type values for bDescriptorType field of functional descriptors */\r
+/* (usbcdc11.pdf, 5.2.3, Table 24) */\r
+#define CDC_CS_INTERFACE 0x24\r
+#define CDC_CS_ENDPOINT 0x25\r
+\r
+/* Type values for bDescriptorSubtype field of functional descriptors */\r
+/* (usbcdc11.pdf, 5.2.3, Table 25) */\r
+#define CDC_HEADER 0x00\r
+#define CDC_CALL_MANAGEMENT 0x01\r
+#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02\r
+#define CDC_DIRECT_LINE_MANAGEMENT 0x03\r
+#define CDC_TELEPHONE_RINGER 0x04\r
+#define CDC_REPORTING_CAPABILITIES 0x05\r
+#define CDC_UNION 0x06\r
+#define CDC_COUNTRY_SELECTION 0x07\r
+#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08\r
+#define CDC_USB_TERMINAL 0x09\r
+#define CDC_NETWORK_CHANNEL 0x0A\r
+#define CDC_PROTOCOL_UNIT 0x0B\r
+#define CDC_EXTENSION_UNIT 0x0C\r
+#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D\r
+#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E\r
+#define CDC_ETHERNET_NETWORKING 0x0F\r
+#define CDC_ATM_NETWORKING 0x10\r
+\r
+/* CDC class-specific request codes */\r
+/* (usbcdc11.pdf, 6.2, Table 46) */\r
+/* see Table 45 for info about the specific requests. */\r
+#define CDC_SEND_ENCAPSULATED_COMMAND 0x00\r
+#define CDC_GET_ENCAPSULATED_RESPONSE 0x01\r
+#define CDC_SET_COMM_FEATURE 0x02\r
+#define CDC_GET_COMM_FEATURE 0x03\r
+#define CDC_CLEAR_COMM_FEATURE 0x04\r
+#define CDC_SET_AUX_LINE_STATE 0x10\r
+#define CDC_SET_HOOK_STATE 0x11\r
+#define CDC_PULSE_SETUP 0x12\r
+#define CDC_SEND_PULSE 0x13\r
+#define CDC_SET_PULSE_TIME 0x14\r
+#define CDC_RING_AUX_JACK 0x15\r
+#define CDC_SET_LINE_CODING 0x20\r
+#define CDC_GET_LINE_CODING 0x21\r
+#define CDC_SET_CONTROL_LINE_STATE 0x22\r
+#define CDC_SEND_BREAK 0x23\r
+#define CDC_SET_RINGER_PARMS 0x30\r
+#define CDC_GET_RINGER_PARMS 0x31\r
+#define CDC_SET_OPERATION_PARMS 0x32\r
+#define CDC_GET_OPERATION_PARMS 0x33\r
+#define CDC_SET_LINE_PARMS 0x34\r
+#define CDC_GET_LINE_PARMS 0x35\r
+#define CDC_DIAL_DIGITS 0x36\r
+#define CDC_SET_UNIT_PARAMETER 0x37\r
+#define CDC_GET_UNIT_PARAMETER 0x38\r
+#define CDC_CLEAR_UNIT_PARAMETER 0x39\r
+#define CDC_GET_PROFILE 0x3A\r
+#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40\r
+#define CDC_SET_ETHERNET_PMP_FILTER 0x41\r
+#define CDC_GET_ETHERNET_PMP_FILTER 0x42\r
+#define CDC_SET_ETHERNET_PACKET_FILTER 0x43\r
+#define CDC_GET_ETHERNET_STATISTIC 0x44\r
+#define CDC_SET_ATM_DATA_FORMAT 0x50\r
+#define CDC_GET_ATM_DEVICE_STATISTICS 0x51\r
+#define CDC_SET_ATM_DEFAULT_VC 0x52\r
+#define CDC_GET_ATM_VC_STATISTICS 0x53\r
+\r
+/* Communication feature selector codes */\r
+/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */\r
+#define CDC_ABSTRACT_STATE 0x01\r
+#define CDC_COUNTRY_SETTING 0x02\r
+\r
+/* Feature Status returned for ABSTRACT_STATE Selector */\r
+/* (usbcdc11.pdf, 6.2.3, Table 48) */\r
+#define CDC_IDLE_SETTING (1 << 0)\r
+#define CDC_DATA_MULTPLEXED_STATE (1 << 1)\r
+\r
+\r
+/* Control signal bitmap values for the SetControlLineState request */\r
+/* (usbcdc11.pdf, 6.2.14, Table 51) */\r
+#define CDC_DTE_PRESENT (1 << 0)\r
+#define CDC_ACTIVATE_CARRIER (1 << 1)\r
+\r
+/* CDC class-specific notification codes */\r
+/* (usbcdc11.pdf, 6.3, Table 68) */\r
+/* see Table 67 for Info about class-specific notifications */\r
+#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00\r
+#define CDC_RESPONSE_AVAILABLE 0x01\r
+#define CDC_AUX_JACK_HOOK_STATE 0x08\r
+#define CDC_RING_DETECT 0x09\r
+#define CDC_NOTIFICATION_SERIAL_STATE 0x20\r
+#define CDC_CALL_STATE_CHANGE 0x28\r
+#define CDC_LINE_STATE_CHANGE 0x29\r
+#define CDC_CONNECTION_SPEED_CHANGE 0x2A\r
+\r
+/* UART state bitmap values (Serial state notification). */\r
+/* (usbcdc11.pdf, 6.3.5, Table 69) */\r
+#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */\r
+#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */\r
+#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */\r
+#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */\r
+#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */\r
+#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */\r
+#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Structures based on usbcdc11.pdf (www.usb.org)\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/* Header functional descriptor */\r
+/* (usbcdc11.pdf, 5.2.3.1) */\r
+/* This header must precede any list of class-specific descriptors. */\r
+PRE_PACK struct POST_PACK _CDC_HEADER_DESCRIPTOR{\r
+ uint8_t bFunctionLength; /* size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */\r
+ uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */\r
+ uint16_t bcdCDC; /* USB CDC specification release version */\r
+};\r
+typedef struct _CDC_HEADER_DESCRIPTOR CDC_HEADER_DESCRIPTOR;\r
+\r
+/* Call management functional descriptor */\r
+/* (usbcdc11.pdf, 5.2.3.2) */\r
+/* Describes the processing of calls for the communication class interface. */\r
+PRE_PACK struct POST_PACK _CDC_CALL_MANAGEMENT_DESCRIPTOR {\r
+ uint8_t bFunctionLength; /* size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */\r
+ uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */\r
+ uint8_t bmCapabilities; /* capabilities that this configuration supports */\r
+ uint8_t bDataInterface; /* interface number of the data class interface used for call management (optional) */\r
+};\r
+typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR CDC_CALL_MANAGEMENT_DESCRIPTOR;\r
+\r
+/* Abstract control management functional descriptor */\r
+/* (usbcdc11.pdf, 5.2.3.3) */\r
+/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */\r
+PRE_PACK struct POST_PACK _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR {\r
+ uint8_t bFunctionLength; /* size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */\r
+ uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */\r
+ uint8_t bmCapabilities; /* capabilities supported by this configuration */\r
+};\r
+typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR;\r
+\r
+/* Union functional descriptors */\r
+/* (usbcdc11.pdf, 5.2.3.8) */\r
+/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */\r
+PRE_PACK struct POST_PACK _CDC_UNION_DESCRIPTOR {\r
+ uint8_t bFunctionLength; /* size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */\r
+ uint8_t bDescriptorSubtype; /* union functional descriptor subtype */\r
+ uint8_t bMasterInterface; /* interface number designated as master */\r
+};\r
+typedef struct _CDC_UNION_DESCRIPTOR CDC_UNION_DESCRIPTOR;\r
+\r
+/* Union functional descriptors with one slave interface */\r
+/* (usbcdc11.pdf, 5.2.3.8) */\r
+PRE_PACK struct POST_PACK _CDC_UNION_1SLAVE_DESCRIPTOR {\r
+ CDC_UNION_DESCRIPTOR sUnion; /* Union functional descriptor */\r
+ uint8_t bSlaveInterfaces[1]; /* Slave interface 0 */\r
+};\r
+typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR CDC_UNION_1SLAVE_DESCRIPTOR;\r
+\r
+/* Line coding structure */\r
+/* Format of the data returned when a GetLineCoding request is received */\r
+/* (usbcdc11.pdf, 6.2.13) */\r
+PRE_PACK struct POST_PACK _CDC_LINE_CODING {\r
+ uint32_t dwDTERate; /* Data terminal rate in bits per second */\r
+ uint8_t bCharFormat; /* Number of stop bits */\r
+ uint8_t bParityType; /* Parity bit type */\r
+ uint8_t bDataBits; /* Number of data bits */\r
+};\r
+typedef struct _CDC_LINE_CODING CDC_LINE_CODING;\r
+\r
+/* Notification header */\r
+/* Data sent on the notification endpoint must follow this header. */\r
+/* see USB_SETUP_PACKET in file usb.h */\r
+typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER;\r
+\r
+uint32_t CALLBACK_UsbdCdc_Register_ControlInterfaceDescriptor(void);\r
+uint32_t CALLBACK_UsbdCdc_Register_DataInterfaceDescriptor(void);\r
+uint32_t CALLBACK_UsbdCdc_Register_LineCoding(void);\r
+uint8_t CALLBACK_UsbdCdc_Register_DataInEndpointNumber(void);\r
+uint8_t CALLBACK_UsbdCdc_Register_DataOutEndpointNumber(void);\r
+uint8_t CALLBACK_UsbdCdc_Register_NotificationEndpointNumber(void);\r
+\r
+uint32_t CALLBACK_UsbdCdc_Register_DataInEndpointSize(void);\r
+uint32_t CALLBACK_UsbdCdc_Register_DataOutEndpointSize(void);\r
+#endif /* __CDC_H */\r
+\r
--- /dev/null
+/*\r
+ * @brief Definition of functions exported by ROM based CDC function driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "usbd_cdc.h"\r
+\r
+#ifndef __CDCUSER_H__\r
+#define __CDCUSER_H__\r
+\r
+\r
+/** @ingroup Group_USBD_Class\r
+ * @defgroup USBD_CDC Communication Device Class (CDC) Function Driver\r
+ * @section Sec_CDCModDescription Module Description\r
+ * CDC Class Function Driver module. This module contains an internal implementation of the USB CDC Class.\r
+ * User applications can use this class driver instead of implementing the CDC class manually\r
+ * via the low-level USBD_HW and USBD_Core APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB CDC Class.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ We need a buffer for incomming data on USB port because USB receives\r
+ much faster than UART transmits\r
+ *---------------------------------------------------------------------------*/\r
+/* Buffer masks */\r
+#define CDC_BUF_SIZE (128) /* Output buffer in bytes (power 2) */\r
+ /* large enough for file transfer */\r
+#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul)\r
+\r
+/** @brief Communication Device Class function driver initilization parameter data structure.\r
+ * @ingroup USBD_CDC\r
+ *\r
+ * @details This data structure is used to pass initialization parameters to the \r
+ * Communication Device Class function driver's init function.\r
+ *\r
+ */\r
+typedef struct USBD_CDC_INIT_PARAM\r
+{\r
+ /* memory allocation params */\r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. @note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 4 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use. \r
+ @note The \em mem_size should be greater than the size \r
+ returned by USBD_CDC_API::GetMemSize() routine.*/\r
+ /** Pointer to the control interface descriptor within the descriptor\r
+ * array (\em high_speed_desc) passed to Init() through @ref USB_CORE_DESCS_T \r
+ * structure. The stack assumes both HS and FS use same BULK endpoints. \r
+ */\r
+ uint8_t* cif_intf_desc;\r
+ /** Pointer to the data interface descriptor within the descriptor\r
+ * array (\em high_speed_desc) passed to Init() through @ref USB_CORE_DESCS_T \r
+ * structure. The stack assumes both HS and FS use same BULK endpoints. \r
+ */\r
+ uint8_t* dif_intf_desc;\r
+\r
+ /* user defined functions */\r
+\r
+ /* required functions */\r
+ /** \r
+ * Communication Interface Class specific get request callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends CIC management element get requests. The setup packet data (\em pSetup)\r
+ * is passed to the callback so that application can extract the CIC request type\r
+ * and other associated data. By default the stack will ssign \em pBuffer pointer\r
+ * to \em EP0Buff allocated at init. The application code can directly write data \r
+ * into this buffer as long as data is less than 64 byte. If more data has to be sent \r
+ * then application code should update \em pBuffer pointer and length accordingly.\r
+ * \r
+ * \r
+ * @param hCdc Handle to CDC function driver. \r
+ * @param pSetup Pointer to setup packet recived from host. \r
+ * @param pBuffer Pointer to a pointer of data buffer containing request data. \r
+ * Pointer-to-pointer is used to implement zero-copy buffers.\r
+ * @param length Amount of data to be sent back to host.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * @retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CIC_GetRequest)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length); \r
+ \r
+ /** \r
+ * Communication Interface Class specific set request callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends a CIC management element requests. The setup packet data (\em pSetup)\r
+ * is passed to the callback so that application can extract the CIC request type\r
+ * and other associated data. If a set request has data associated, then this callback\r
+ * is called twice. \r
+ * (1) First when setup request is recived, at this time application code could update\r
+ * \em pBuffer pointer to point to the intended destination. The length param is set to 0\r
+ * so that application code knows this is first time. By default the stack will\r
+ * assign \em pBuffer pointer to \em EP0Buff allocated at init. Note, if data length is \r
+ * greater than 64 bytes and application code doesn't update \em pBuffer pointer the \r
+ * stack will send STALL condition to host.\r
+ * (2) Second when the data is recived from the host. This time the length param is set\r
+ * with number of data bytes recived.\r
+ * \r
+ * @param hCdc Handle to CDC function driver. \r
+ * @param pSetup Pointer to setup packet recived from host. \r
+ * @param pBuffer Pointer to a pointer of data buffer containing request data. \r
+ * Pointer-to-pointer is used to implement zero-copy buffers.\r
+ * @param length Amount of data copied to destination buffer.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * @retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CIC_SetRequest)( USBD_HANDLE_T hCdc, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);\r
+\r
+ /** \r
+ * Communication Device Class specific BULK IN endpoint handler.\r
+ *\r
+ * The application software should provide the BULK IN endpoint handler.\r
+ * Applications should transfer data depending on the communication protocol type set in descriptors. \r
+ * \n\r
+ * @note \r
+ * \r
+ * @param hUsb Handle to the USB device stack. \r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * @retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CDC_BulkIN_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+ /** \r
+ * Communication Device Class specific BULK OUT endpoint handler.\r
+ *\r
+ * The application software should provide the BULK OUT endpoint handler.\r
+ * Applications should transfer data depending on the communication protocol type set in descriptors. \r
+ * \n\r
+ * @note \r
+ * \r
+ * @param hUsb Handle to the USB device stack. \r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * @retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CDC_BulkOUT_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+ ErrorCode_t (*SendEncpsCmd) (USBD_HANDLE_T hCDC, uint8_t* buffer, uint16_t len);\r
+ ErrorCode_t (*GetEncpsResp) (USBD_HANDLE_T hCDC, uint8_t** buffer, uint16_t* len);\r
+ ErrorCode_t (*SetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t* buffer, uint16_t len);\r
+ ErrorCode_t (*GetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t** pBuffer, uint16_t* len);\r
+ ErrorCode_t (*ClrCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature);\r
+ ErrorCode_t (*SetCtrlLineState) (USBD_HANDLE_T hCDC, uint16_t state);\r
+ ErrorCode_t (*SendBreak) (USBD_HANDLE_T hCDC, uint16_t mstime);\r
+ ErrorCode_t (*SetLineCode) (USBD_HANDLE_T hCDC, CDC_LINE_CODING* line_coding);\r
+\r
+ /** \r
+ * Optional Communication Device Class specific INTERRUPT IN endpoint handler.\r
+ *\r
+ * The application software should provide the INT IN endpoint handler.\r
+ * Applications should transfer data depending on the communication protocol type set in descriptors. \r
+ * \n\r
+ * @note \r
+ * \r
+ * @param hUsb Handle to the USB device stack. \r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * @retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CDC_InterruptEP_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+ /** \r
+ * Optional user overridable function to replace the default CDC class handler.\r
+ *\r
+ * The application software could override the default EP0 class handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_CDC_API::Init().\r
+ * \n\r
+ * @note \r
+ * \r
+ * @param hUsb Handle to the USB device stack. \r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * @retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CDC_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+} USBD_CDC_INIT_PARAM_T;\r
+\r
+/** @brief CDC class API functions structure.\r
+ * @ingroup USBD_CDC\r
+ *\r
+ * This module exposes functions which interact directly with USB device controller hardware.\r
+ *\r
+ */\r
+typedef struct USBD_CDC_API\r
+{\r
+ /** @fn uint32_t GetMemSize(USBD_CDC_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the CDC function driver module.\r
+ * \r
+ * This function is called by application layer before calling pUsbApi->CDC->Init(), to allocate memory used \r
+ * by CDC function driver module. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller. \r
+ * @note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * @param param Structure containing CDC function driver module initialization parameters.\r
+ * @return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_CDC_INIT_PARAM_T* param);\r
+ \r
+ /** @fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param)\r
+ * Function to initialize CDC function driver module.\r
+ * \r
+ * This fuction is called by application layer to initialize CDC function driver module. \r
+ *\r
+ * @param hUsb Handle to the USB device stack. \r
+ * @param param Structure containing CDC function driver module initialization parameters.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success\r
+ * @retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte \r
+ * aligned or smaller than required. \r
+ * @retval ERR_API_INVALID_PARAM2 Either CDC_Write() or CDC_Read() or\r
+ * CDC_Verify() callbacks are not defined. \r
+ * @retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. \r
+ * @retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed. \r
+ */\r
+ ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param, USBD_HANDLE_T* phCDC);\r
+\r
+ /** @fn ErrorCode_t SendNotification(USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data)\r
+ * Function to initialize CDC function driver module.\r
+ * \r
+ * This fuction is called by application layer to initialize CDC function driver module. \r
+ *\r
+ * @param hUsb Handle to the USB device stack. \r
+ * @param param Structure containing CDC function driver module initialization parameters.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success\r
+ * @retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte \r
+ * aligned or smaller than required. \r
+ * @retval ERR_API_INVALID_PARAM2 Either CDC_Write() or CDC_Read() or\r
+ * CDC_Verify() callbacks are not defined. \r
+ * @retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. \r
+ * @retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed. \r
+ */\r
+ ErrorCode_t (*SendNotification)(USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data);\r
+\r
+} USBD_CDC_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+/** @cond ADVANCED_API */\r
+\r
+typedef struct _CDC_CTRL_T\r
+{\r
+ USB_CORE_CTRL_T* pUsbCtrl;\r
+ /* notification buffer */\r
+ uint8_t notice_buf[12];\r
+ CDC_LINE_CODING line_coding;\r
+ \r
+ uint8_t cif_num; /* control interface number */\r
+ uint8_t dif_num; /* data interface number */\r
+ uint8_t epin_num; /* BULK IN endpoint number */\r
+ uint8_t epout_num; /* BULK OUT endpoint number */\r
+ uint8_t epint_num; /* Interrupt IN endpoint number */\r
+\r
+ /* user defined functions */\r
+ ErrorCode_t (*SendEncpsCmd) (USBD_HANDLE_T hCDC, uint8_t* buffer, uint16_t len);\r
+ ErrorCode_t (*GetEncpsResp) (USBD_HANDLE_T hCDC, uint8_t** buffer, uint16_t* len);\r
+ ErrorCode_t (*SetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t* buffer, uint16_t len);\r
+ ErrorCode_t (*GetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t** pBuffer, uint16_t* len);\r
+ ErrorCode_t (*ClrCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature);\r
+ ErrorCode_t (*SetCtrlLineState) (USBD_HANDLE_T hCDC, uint16_t state);\r
+ ErrorCode_t (*SendBreak) (USBD_HANDLE_T hCDC, uint16_t state);\r
+ ErrorCode_t (*SetLineCode) (USBD_HANDLE_T hCDC, CDC_LINE_CODING* line_coding);\r
+\r
+ /* virtual functions */\r
+ ErrorCode_t (*CIC_GetRequest)( USBD_HANDLE_T hCdc, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length);\r
+ ErrorCode_t (*CIC_SetRequest)( USBD_HANDLE_T hCdc, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);\r
+\r
+}USB_CDC_CTRL_T;\r
+\r
+\r
+/** @endcond */\r
+\r
+void UsbdCdc_IO_Buffer_Sync_Task(void);\r
+void UsbdCdc_SendData(uint8_t* buffer, uint32_t cnt);\r
+uint32_t UsbdCdc_RecvData(uint8_t* buffer, uint32_t len);\r
+\r
+\r
+#endif /* __CDCUSER_H__ */\r
+\r
--- /dev/null
+/*\r
+ * @brief Definition of functions exported by core layer of ROM based USB device stack\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __MW_USBD_CORE_H__\r
+#define __MW_USBD_CORE_H__\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "lpc_types.h"\r
+\r
+/** @ingroup Group_USBD\r
+ * @defgroup USBD_Core USB Core Layer\r
+ * @section Sec_CoreModDescription Module Description\r
+ * The USB Core Layer implements the device abstraction defined in the <em> Universal Serial Bus Specification, </em>\r
+ * for applications to interact with the USB device interface on the device. The software in this layer responds to\r
+ * standard requests and returns standard descriptors. In current stack the Init() routine part of\r
+ * @ref USBD_HW_API_T structure initializes both hardware layer and core layer.\r
+ */\r
+\r
+\r
+/* function pointer types */\r
+\r
+/** @ingroup USBD_Core\r
+ * @typedef USB_CB_T\r
+ * @brief USB device stack's event callback function type.\r
+ *\r
+ * The USB device stack exposes several event triggers through callback to application layer. The\r
+ * application layer can register methods to be called when such USB event happens.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx Other error conditions.\r
+ *\r
+ */\r
+typedef ErrorCode_t (*USB_CB_T) (USBD_HANDLE_T hUsb);\r
+\r
+/** @ingroup USBD_Core\r
+ * @typedef USB_PARAM_CB_T\r
+ * @brief USB device stack's event callback function type.\r
+ *\r
+ * The USB device stack exposes several event triggers through callback to application layer. The\r
+ * application layer can register methods to be called when such USB event happens.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param param1 Extra information related to the event.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+typedef ErrorCode_t (*USB_PARAM_CB_T) (USBD_HANDLE_T hUsb, uint32_t param1);\r
+\r
+/** @ingroup USBD_Core\r
+ * @typedef USB_EP_HANDLER_T\r
+ * @brief USBD setup request and endpoint event handler type.\r
+ *\r
+ * The application layer should define the custom class's EP0 handler with function signature.\r
+ * The stack calls all the registered class handlers on any EP0 event before going through default\r
+ * handling of the event. This gives the class handlers to implement class specific request handlers\r
+ * and also to override the default stack handling for a particular event targeted to the interface.\r
+ * If an event is not handled by the callback the function should return ERR_USBD_UNHANDLED. For all\r
+ * other return codes the stack assumes that callback has taken care of the event and hence will not\r
+ * process the event any further and issues a STALL condition on EP0 indicating error to the host.\r
+ * \n\r
+ * For endpoint interrupt handler the return value is ignored by the stack.\r
+ * \n\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack.\r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+typedef ErrorCode_t (*USB_EP_HANDLER_T)(USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+\r
+/** @ingroup USBD_Core\r
+ * @brief USB descriptors data structure.\r
+ * @ingroup USBD_Core\r
+ *\r
+ * @details This structure is used as part of USB device stack initialisation\r
+ * parameter structure @ref USBD_API_INIT_PARAM_T. This structure contains\r
+ * pointers to various descriptor arrays needed by the stack. These descriptors\r
+ * are reported to USB host as part of enumerations process.\r
+ *\r
+ * @note All descriptor pointers assigned in this structure should be on 4 byte\r
+ * aligned address boundary.\r
+ */\r
+typedef struct _USB_CORE_DESCS_T\r
+{\r
+ uint8_t *device_desc; /**< Pointer to USB device descriptor */\r
+ uint8_t *string_desc; /**< Pointer to array of USB string descriptors */\r
+ uint8_t *full_speed_desc; /**< Pointer to USB device configuration descriptor\r
+ * when device is operating in full speed mode.\r
+ */\r
+ uint8_t *high_speed_desc; /**< Pointer to USB device configuration descriptor\r
+ * when device is operating in high speed mode. For\r
+ * full-speed only implementation this pointer should\r
+ * be same as full_speed_desc.\r
+ */\r
+ uint8_t *device_qualifier; /**< Pointer to USB device qualifier descriptor. For\r
+ * full-speed only implementation this pointer should\r
+ * be set to null (0).\r
+ */\r
+} USB_CORE_DESCS_T;\r
+\r
+/** @brief USB device stack initilization parameter data structure.\r
+ * @ingroup USBD_Core\r
+ *\r
+ * @details This data structure is used to pass initialization parameters to the\r
+ * USB device stack's init function.\r
+ *\r
+ */\r
+typedef struct USBD_API_INIT_PARAM\r
+{\r
+ uint32_t usb_reg_base; /**< USB device controller's base register address. */\r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. @note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 2048 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use.\r
+ @note The \em mem_size should be greater than the size\r
+ returned by USBD_HW_API::GetMemSize() routine.*/\r
+ uint8_t max_num_ep; /**< max number of endpoints supported by the USB device\r
+ controller instance (specified by \em usb_reg_base field)\r
+ to which this instance of stack is attached.\r
+ */\r
+\r
+ /* USB Device Events Callback Functions */\r
+ /** Event for USB interface reset. This event fires when the USB host requests that the device\r
+ * reset its interface. This event fires after the control endpoint has been automatically\r
+ * configured by the library.\r
+ * \n\r
+ * @note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will prevent the device from enumerating correctly or operate properly.\r
+ *\r
+ */\r
+ USB_CB_T USB_Reset_Event;\r
+\r
+ /** Event for USB suspend. This event fires when the USB host suspends the device by halting its\r
+ * transmission of Start Of Frame pulses to the device. This is generally hooked in order to move\r
+ * the device over to a low power state until the host wakes up the device.\r
+ * \n\r
+ * @note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will cause other system issues.\r
+ */\r
+ USB_CB_T USB_Suspend_Event;\r
+\r
+ /** Event for USB wake up or resume. This event fires when a the USB device interface is suspended\r
+ * and the host wakes up the device by supplying Start Of Frame pulses. This is generally\r
+ * hooked to pull the user application out of a low power state and back into normal operating\r
+ * mode.\r
+ * \n\r
+ * @note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will cause other system issues.\r
+ *\r
+ */\r
+ USB_CB_T USB_Resume_Event;\r
+\r
+ /** Reserved parameter should be set to zero. */\r
+ USB_CB_T reserved_sbz;\r
+\r
+ /** Event for USB Start Of Frame detection, when enabled. This event fires at the start of each USB\r
+ * frame, once per millisecond in full-speed mode or once per 125 microseconds in high-speed mode,\r
+ * and is synchronized to the USB bus.\r
+ *\r
+ * This event is time-critical; it is run once per millisecond (full-speed mode) and thus long handlers\r
+ * will significantly degrade device performance. This event should only be enabled when needed to\r
+ * reduce device wake-ups.\r
+ *\r
+ * @note This event is not normally active - it must be manually enabled and disabled via the USB interrupt\r
+ * register.\r
+ * \n\n\r
+ */\r
+ USB_CB_T USB_SOF_Event;\r
+\r
+ /** Event for remote wakeup configururation, when enabled. This event fires when the USB host\r
+ * request the device to configure itself for remote wake-up capability. The USB host sends\r
+ * this request to device which report remote wakeup capable in their device descriptors,\r
+ * before going to low-power state. The application layer should implement this callback if\r
+ * they have any special on board circuit to trigerr remote wake up event.\r
+ *\r
+ * This event is time-critical; it is run once per millisecond (full-speed mode) and thus long handlers\r
+ * will significantly degrade device performance.\r
+ *\r
+ * \n\n\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param param1 When 0 - Clear the wakeup configuration, 1 - Enable the wake-up configuration.\r
+ * @return The call back should return @ref ErrorCode_t type to indicate success or error condition.\r
+ */\r
+ USB_PARAM_CB_T USB_WakeUpCfg;\r
+\r
+ /** Reserved parameter should be set to zero. */\r
+ USB_PARAM_CB_T USB_Power_Event;\r
+\r
+ /** Event for error condition. This event fires when USB device controller detect\r
+ * an error condition in the system.\r
+ *\r
+ * \n\n\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param param1 USB device interrupt status register.\r
+ * @return The call back should return @ref ErrorCode_t type to indicate success or error condition.\r
+ */\r
+ USB_PARAM_CB_T USB_Error_Event;\r
+\r
+ /* USB Core Events Callback Functions */\r
+ /** Event for USB configuration number changed. This event fires when a the USB host changes the\r
+ * selected configuration number. On receiving configuration change request from host, the stack\r
+ * enables/configures the endpoints needed by the new configuration before calling this callback\r
+ * function.\r
+ * \n\r
+ * @note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will prevent the device from enumerating correctly or operate properly.\r
+ *\r
+ */\r
+ USB_CB_T USB_Configure_Event;\r
+\r
+ /** Event for USB interface setting changed. This event fires when a the USB host changes the\r
+ * interface setting to one of alternate interface settings. On receiving interface change\r
+ * request from host, the stack enables/configures the endpoints needed by the new alternate\r
+ * interface setting before calling this callback function.\r
+ * \n\r
+ * @note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will prevent the device from enumerating correctly or operate properly.\r
+ *\r
+ */\r
+ USB_CB_T USB_Interface_Event;\r
+\r
+ /** Event for USB feature changed. This event fires when a the USB host send set/clear feature\r
+ * request. The stack handles this request for USB_FEATURE_REMOTE_WAKEUP, USB_FEATURE_TEST_MODE\r
+ * and USB_FEATURE_ENDPOINT_STALL features only. On receiving feature request from host, the\r
+ * stack handle the request appropriately and then calls this callback function.\r
+ * \n\r
+ * @note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will prevent the device from enumerating correctly or operate properly.\r
+ *\r
+ */\r
+ USB_CB_T USB_Feature_Event;\r
+\r
+ /* cache and mmu translation functions */\r
+ /** Reserved parameter for future use. should be set to zero. */\r
+ uint32_t (* virt_to_phys)(void* vaddr);\r
+ /** Reserved parameter for future use. should be set to zero. */\r
+ void (* cache_flush)(uint32_t* start_adr, uint32_t* end_adr);\r
+\r
+} USBD_API_INIT_PARAM_T;\r
+\r
+\r
+/** @brief USBD stack Core API functions structure.\r
+ * @ingroup USBD_Core\r
+ *\r
+ * @details This module exposes functions which interact directly with USB device stack's core layer.\r
+ * The application layer uses this component when it has to implement custom class function driver or\r
+ * standard class function driver which is not part of the current USB device stack.\r
+ * The functions exposed by this interface are to register class specific EP0 handlers and corresponding\r
+ * utility functions to manipulate EP0 state machine of the stack. This interface also exposes\r
+ * function to register custom endpoint interrupt handler.\r
+ *\r
+ */\r
+typedef struct USBD_CORE_API\r
+{\r
+ /** @fn ErrorCode_t RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data)\r
+ * Function to register class specific EP0 event handler with USB device stack.\r
+ *\r
+ * The application layer uses this function when it has to register the custom class's EP0 handler.\r
+ * The stack calls all the registered class handlers on any EP0 event before going through default\r
+ * handling of the event. This gives the class handlers to implement class specific request handlers\r
+ * and also to override the default stack handling for a particular event targeted to the interface.\r
+ * Check USB_EP_HANDLER_T for more details on how the callback function should be implemented. Also\r
+ * application layer could use this function to register EP0 handler which responds to vendor specific\r
+ * requests.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param pfn Class specific EP0 handler function.\r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success\r
+ * @retval ERR_USBD_TOO_MANY_CLASS_HDLR(0x0004000c) The number of class handlers registered is\r
+ greater than the number of handlers allowed by the stack.\r
+ *\r
+ */\r
+ ErrorCode_t (*RegisterClassHandler)(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data);\r
+\r
+ /** @fn ErrorCode_t RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data)\r
+ * Function to register interrupt/event handler for the requested endpoint with USB device stack.\r
+ *\r
+ * The application layer uses this function to register the custom class's EP0 handler.\r
+ * The stack calls all the registered class handlers on any EP0 event before going through default\r
+ * handling of the event. This gives the class handlers to implement class specific request handlers\r
+ * and also to override the default stack handling for a particular event targeted to the interface.\r
+ * Check USB_EP_HANDLER_T for more details on how the callback function should be implemented.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param ep_index Class specific EP0 handler function.\r
+ * @param pfn Class specific EP0 handler function.\r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success\r
+ * @retval ERR_USBD_TOO_MANY_CLASS_HDLR(0x0004000c) Too many endpoint handlers.\r
+ *\r
+ */\r
+ ErrorCode_t (*RegisterEpHandler)(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data);\r
+\r
+ /** @fn void SetupStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in setup state.\r
+ *\r
+ * This function is called by USB stack and the application layer to\r
+ * set the EP0 state machine in setup state. This function will read\r
+ * the setup packet received from USB host into stack's buffer.\r
+ * \n\r
+ * @note This interface is provided to users to invoke this function in other\r
+ * scenarios which are not handle by current stack. In most user applications\r
+ * this function is not called directly.Also this function can be used by\r
+ * users who are selectively modifying the USB device stack's standard handlers\r
+ * through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @return Nothing.\r
+ */\r
+ void (*SetupStage )(USBD_HANDLE_T hUsb);\r
+\r
+ /** @fn void DataInStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in data_in state.\r
+ *\r
+ * This function is called by USB stack and the application layer to\r
+ * set the EP0 state machine in data_in state. This function will write\r
+ * the data present in EP0Data buffer to EP0 FIFO for tranmission to host.\r
+ * \n\r
+ * @note This interface is provided to users to invoke this function in other\r
+ * scenarios which are not handle by current stack. In most user applications\r
+ * this function is not called directly.Also this function can be used by\r
+ * users who are selectively modifying the USB device stack's standard handlers\r
+ * through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @return Nothing.\r
+ */\r
+ void (*DataInStage)(USBD_HANDLE_T hUsb);\r
+\r
+ /** @fn void DataOutStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in data_out state.\r
+ *\r
+ * This function is called by USB stack and the application layer to\r
+ * set the EP0 state machine in data_out state. This function will read\r
+ * the control data (EP0 out packets) received from USB host into EP0Data buffer.\r
+ * \n\r
+ * @note This interface is provided to users to invoke this function in other\r
+ * scenarios which are not handle by current stack. In most user applications\r
+ * this function is not called directly.Also this function can be used by\r
+ * users who are selectively modifying the USB device stack's standard handlers\r
+ * through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @return Nothing.\r
+ */\r
+ void (*DataOutStage)(USBD_HANDLE_T hUsb);\r
+\r
+ /** @fn void StatusInStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in status_in state.\r
+ *\r
+ * This function is called by USB stack and the application layer to\r
+ * set the EP0 state machine in status_in state. This function will send\r
+ * zero length IN packet on EP0 to host, indicating positive status.\r
+ * \n\r
+ * @note This interface is provided to users to invoke this function in other\r
+ * scenarios which are not handle by current stack. In most user applications\r
+ * this function is not called directly.Also this function can be used by\r
+ * users who are selectively modifying the USB device stack's standard handlers\r
+ * through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @return Nothing.\r
+ */\r
+ void (*StatusInStage)(USBD_HANDLE_T hUsb);\r
+ /** @fn void StatusOutStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in status_out state.\r
+ *\r
+ * This function is called by USB stack and the application layer to\r
+ * set the EP0 state machine in status_out state. This function will read\r
+ * the zero length OUT packet received from USB host on EP0.\r
+ * \n\r
+ * @note This interface is provided to users to invoke this function in other\r
+ * scenarios which are not handle by current stack. In most user applications\r
+ * this function is not called directly.Also this function can be used by\r
+ * users who are selectively modifying the USB device stack's standard handlers\r
+ * through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @return Nothing.\r
+ */\r
+ void (*StatusOutStage)(USBD_HANDLE_T hUsb);\r
+\r
+ /** @fn void StallEp0(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in stall state.\r
+ *\r
+ * This function is called by USB stack and the application layer to\r
+ * generate STALL signalling on EP0 endpoint. This function will also\r
+ * reset the EP0Data buffer.\r
+ * \n\r
+ * @note This interface is provided to users to invoke this function in other\r
+ * scenarios which are not handle by current stack. In most user applications\r
+ * this function is not called directly.Also this function can be used by\r
+ * users who are selectively modifying the USB device stack's standard handlers\r
+ * through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @return Nothing.\r
+ */\r
+ void (*StallEp0)(USBD_HANDLE_T hUsb);\r
+\r
+} USBD_CORE_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+\r
+ /** @cond ADVANCED_API */\r
+\r
+/* forward declaration */\r
+struct _USB_CORE_CTRL_T;\r
+typedef struct _USB_CORE_CTRL_T USB_CORE_CTRL_T;\r
+\r
+/* USB device Speed status defines */\r
+#define USB_FULL_SPEED 0\r
+#define USB_HIGH_SPEED 1\r
+\r
+/* USB Endpoint Data Structure */\r
+typedef struct _USB_EP_DATA\r
+{\r
+ uint8_t *pData;\r
+ uint16_t Count;\r
+} USB_EP_DATA;\r
+\r
+#define USB_MAX_IF_NUM 8\r
+#define USB_MAX_EP_NUM 6\r
+\r
+/* USB core controller data structure */\r
+struct _USB_CORE_CTRL_T\r
+{\r
+ /* overridable function pointers ~ c++ style virtual functions*/\r
+ USB_CB_T USB_EvtSetupHandler;\r
+ USB_CB_T USB_EvtOutHandler;\r
+ USB_PARAM_CB_T USB_ReqVendor;\r
+ USB_CB_T USB_ReqGetStatus;\r
+ USB_CB_T USB_ReqGetDescriptor;\r
+ USB_CB_T USB_ReqGetConfiguration;\r
+ USB_CB_T USB_ReqSetConfiguration;\r
+ USB_CB_T USB_ReqGetInterface;\r
+ USB_CB_T USB_ReqSetInterface;\r
+ USB_PARAM_CB_T USB_ReqSetClrFeature;\r
+\r
+ /* USB Device Events Callback Functions */\r
+ USB_CB_T USB_Reset_Event;\r
+ USB_CB_T USB_Suspend_Event;\r
+ USB_CB_T USB_Resume_Event;\r
+ USB_CB_T USB_SOF_Event;\r
+ USB_PARAM_CB_T USB_Power_Event;\r
+ USB_PARAM_CB_T USB_Error_Event;\r
+ USB_PARAM_CB_T USB_WakeUpCfg;\r
+\r
+ /* USB Core Events Callback Functions */\r
+ USB_CB_T USB_Configure_Event;\r
+ USB_CB_T USB_Interface_Event;\r
+ USB_CB_T USB_Feature_Event;\r
+\r
+ /* cache and mmu translation functions */\r
+ uint32_t (* virt_to_phys)(void* vaddr);\r
+ void (* cache_flush)(uint32_t* start_adr, uint32_t* end_adr);\r
+\r
+ /* event handlers for endpoints. */\r
+ USB_EP_HANDLER_T ep_event_hdlr[2 * USB_MAX_EP_NUM];\r
+ void* ep_hdlr_data[2 * USB_MAX_EP_NUM];\r
+\r
+ /* USB class handlers */\r
+ USB_EP_HANDLER_T ep0_hdlr_cb[USB_MAX_IF_NUM];\r
+ void* ep0_cb_data[USB_MAX_IF_NUM];\r
+ uint8_t num_ep0_hdlrs;\r
+ /* USB Core data Variables */\r
+ uint8_t max_num_ep; /* max number of endpoints supported by the HW */\r
+ uint8_t device_speed;\r
+ uint8_t num_interfaces;\r
+ uint8_t device_addr;\r
+ uint8_t config_value;\r
+ uint16_t device_status;\r
+ uint8_t *device_desc;\r
+ uint8_t *string_desc;\r
+ uint8_t *full_speed_desc;\r
+ uint8_t *high_speed_desc;\r
+ uint8_t *device_qualifier;\r
+ uint32_t ep_mask;\r
+ uint32_t ep_halt;\r
+ uint32_t ep_stall;\r
+ uint8_t alt_setting[USB_MAX_IF_NUM];\r
+ /* HW driver data pointer */\r
+ void* hw_data;\r
+\r
+ /* USB Endpoint 0 Data Info */\r
+ USB_EP_DATA EP0Data;\r
+\r
+ /* USB Endpoint 0 Buffer */\r
+ //ALIGNED(4)\r
+ uint8_t EP0Buf[64];\r
+\r
+ /* USB Setup Packet */\r
+ //ALIGNED(4)\r
+ USB_SETUP_PACKET SetupPacket;\r
+\r
+};\r
+\r
+\r
+static INLINE void USB_SetSpeedMode(USB_CORE_CTRL_T* pCtrl, uint8_t mode)\r
+{\r
+ pCtrl->device_speed = mode;\r
+}\r
+/** @endcond */\r
+\r
+#endif /* __MW_USBD_CORE_H__ */\r
--- /dev/null
+/*\r
+ * @brief Definition of DFU class descriptors and their bit defines\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "usbd.h"\r
+\r
+#ifndef __MW_USBD_DFU_H__\r
+#define __MW_USBD_DFU_H__\r
+\r
+\r
+/**\r
+ * If USB device is only DFU capable, DFU Interface number is always 0.\r
+ * if USB device is (DFU + Other Class (Audio/Mass Storage/HID), DFU\r
+ * Interface number should also be 0 in this implementation.\r
+ */\r
+#define USB_DFU_IF_NUM 0x0\r
+\r
+#define USB_DFU_DESCRIPTOR_TYPE 0x21\r
+#define USB_DFU_DESCRIPTOR_SIZE 9\r
+#define USB_DFU_SUBCLASS 0x01\r
+#define USB_DFU_XFER_SIZE 2048\r
+\r
+/* DFU class-specific requests (Section 3, DFU Rev 1.1) */\r
+#define USB_REQ_DFU_DETACH 0x00\r
+#define USB_REQ_DFU_DNLOAD 0x01\r
+#define USB_REQ_DFU_UPLOAD 0x02\r
+#define USB_REQ_DFU_GETSTATUS 0x03\r
+#define USB_REQ_DFU_CLRSTATUS 0x04\r
+#define USB_REQ_DFU_GETSTATE 0x05\r
+#define USB_REQ_DFU_ABORT 0x06\r
+\r
+#define DFU_STATUS_OK 0x00\r
+#define DFU_STATUS_errTARGET 0x01\r
+#define DFU_STATUS_errFILE 0x02\r
+#define DFU_STATUS_errWRITE 0x03\r
+#define DFU_STATUS_errERASE 0x04\r
+#define DFU_STATUS_errCHECK_ERASED 0x05\r
+#define DFU_STATUS_errPROG 0x06\r
+#define DFU_STATUS_errVERIFY 0x07\r
+#define DFU_STATUS_errADDRESS 0x08\r
+#define DFU_STATUS_errNOTDONE 0x09\r
+#define DFU_STATUS_errFIRMWARE 0x0a\r
+#define DFU_STATUS_errVENDOR 0x0b\r
+#define DFU_STATUS_errUSBR 0x0c\r
+#define DFU_STATUS_errPOR 0x0d\r
+#define DFU_STATUS_errUNKNOWN 0x0e\r
+#define DFU_STATUS_errSTALLEDPKT 0x0f\r
+\r
+enum dfu_state {\r
+ DFU_STATE_appIDLE = 0,\r
+ DFU_STATE_appDETACH = 1,\r
+ DFU_STATE_dfuIDLE = 2,\r
+ DFU_STATE_dfuDNLOAD_SYNC = 3,\r
+ DFU_STATE_dfuDNBUSY = 4,\r
+ DFU_STATE_dfuDNLOAD_IDLE = 5,\r
+ DFU_STATE_dfuMANIFEST_SYNC = 6,\r
+ DFU_STATE_dfuMANIFEST = 7,\r
+ DFU_STATE_dfuMANIFEST_WAIT_RST= 8,\r
+ DFU_STATE_dfuUPLOAD_IDLE = 9,\r
+ DFU_STATE_dfuERROR = 10\r
+};\r
+\r
+#define DFU_EP0_NONE 0\r
+#define DFU_EP0_UNHANDLED 1\r
+#define DFU_EP0_STALL 2\r
+#define DFU_EP0_ZLP 3\r
+#define DFU_EP0_DATA 4\r
+\r
+#define USB_DFU_CAN_DOWNLOAD (1 << 0)\r
+#define USB_DFU_CAN_UPLOAD (1 << 1)\r
+#define USB_DFU_MANIFEST_TOL (1 << 2)\r
+#define USB_DFU_WILL_DETACH (1 << 3)\r
+\r
+PRE_PACK struct POST_PACK _USB_DFU_FUNC_DESCRIPTOR {\r
+ uint8_t bLength;\r
+ uint8_t bDescriptorType;\r
+ uint8_t bmAttributes;\r
+ uint16_t wDetachTimeOut;\r
+ uint16_t wTransferSize;\r
+ uint16_t bcdDFUVersion;\r
+};\r
+typedef struct _USB_DFU_FUNC_DESCRIPTOR USB_DFU_FUNC_DESCRIPTOR;\r
+\r
+PRE_PACK struct POST_PACK _DFU_STATUS {\r
+ uint8_t bStatus;\r
+ uint8_t bwPollTimeout[3];\r
+ uint8_t bState;\r
+ uint8_t iString;\r
+};\r
+typedef struct _DFU_STATUS DFU_STATUS_T;\r
+\r
+#define DFU_FUNC_DESC_SIZE sizeof(USB_DFU_FUNC_DESCRIPTOR)\r
+#define DFU_GET_STATUS_SIZE 0x6\r
+\r
+\r
+#endif /* __MW_USBD_DFU_H__ */\r
--- /dev/null
+/*\r
+ * @brief Definition of functions exported by ROM based DFU function driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __DFUUSER_H__\r
+#define __DFUUSER_H__\r
+\r
+#include "usbd.h"\r
+#include "usbd_dfu.h"\r
+#include "usbd_core.h"\r
+\r
+\r
+/** @ingroup Group_USBD_Class\r
+ * @defgroup USBD_DFU Device Firmware Upgrade (DFU) Class Function Driver\r
+ * @section Sec_MSCModDescription Module Description\r
+ * DFU Class Function Driver module. This module contains an internal implementation of the USB DFU Class.\r
+ * User applications can use this class driver instead of implementing the DFU class manually\r
+ * via the low-level USBD_HW and USBD_Core APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB DFU Class.\r
+ */\r
+\r
+/** @brief USB descriptors data structure.\r
+ * @ingroup USBD_DFU\r
+ *\r
+ * @details This module exposes functions which interact directly with USB device stack's core layer.\r
+ * The application layer uses this component when it has to implement custom class function driver or\r
+ * standard class function driver which is not part of the current USB device stack.\r
+ * The functions exposed by this interface are to register class specific EP0 handlers and corresponding\r
+ * utility functions to manipulate EP0 state machine of the stack. This interface also exposes\r
+ * function to register custom endpoint interrupt handler.\r
+ *\r
+ */\r
+typedef struct USBD_DFU_INIT_PARAM\r
+{\r
+ /* memory allocation params */\r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. @note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 4 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use.\r
+ @note The \em mem_size should be greater than the size\r
+ returned by USBD_DFU_API::GetMemSize() routine.*/\r
+ /* DFU paramas */\r
+ uint16_t wTransferSize; /**< DFU transfer block size in number of bytes.\r
+ This value should match the value set in DFU descriptor\r
+ provided as part of the descriptor array\r
+ (\em high_speed_desc) passed to Init() through\r
+ @ref USB_CORE_DESCS_T structure. */\r
+\r
+ /** Pointer to the DFU interface descriptor within the descriptor\r
+ * array (\em high_speed_desc) passed to Init() through @ref USB_CORE_DESCS_T\r
+ * structure.\r
+ */\r
+ uint8_t* intf_desc;\r
+ /* user defined functions */\r
+ /**\r
+ * DFU Write callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a write command. For application using zero-copy buffer scheme\r
+ * this function is called for the first time with \em length parameter set to 0.\r
+ * The application code should update the buffer pointer.\r
+ *\r
+ * @param block_num Destination start address.\r
+ * @param src Pointer to a pointer to the source of data. Pointer-to-pointer\r
+ * is used to implement zero-copy buffers.\r
+ * @param bwPollTimeout Pointer to a 3 byte buffer which the callback implementer\r
+ * should fill with the amount of minimum time, in milliseconds, \r
+ * that the host should wait before sending a subsequent\r
+ * DFU_GETSTATUS request. \r
+ * @param length Number of bytes to be written.\r
+ * @return Returns DFU_STATUS_ values defined in mw_usbd_dfu.h.\r
+ *\r
+ */\r
+ uint8_t (*DFU_Write)( uint32_t block_num, uint8_t** src, uint32_t length, uint8_t* bwPollTimeout);\r
+\r
+ /**\r
+ * DFU Read callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a read command.\r
+ *\r
+ * @param block_num Destination start address.\r
+ * @param dst Pointer to a pointer to the source of data. Pointer-to-pointer\r
+ * is used to implement zero-copy buffers.\r
+ * @param length Amount of data copied to destination buffer.\r
+ * @return Returns DFU_STATUS_ values defined in mw_usbd_dfu.h.\r
+ *\r
+ */\r
+ uint32_t (*DFU_Read)( uint32_t block_num, uint8_t** dst, uint32_t length);\r
+\r
+ /**\r
+ * DFU done callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * after download is finished.\r
+ *\r
+ * @return Nothing.\r
+ *\r
+ */\r
+ void (*DFU_Done)(void);\r
+\r
+ /**\r
+ * DFU detach callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * after USB_REQ_DFU_DETACH is recieved. Applications which set USB_DFU_WILL_DETACH\r
+ * bit in DFU descriptor should define this function. As part of this function\r
+ * application can call Connect() routine to disconnect and then connect back with\r
+ * host. For application which rely on WinUSB based host application should use this\r
+ * feature since USB reset can be invoked only by kernel drivers on Windows host.\r
+ * By implementing this feature host doen't have to issue reset instead the device\r
+ * has to do it automatically by disconnect and connect procedure.\r
+ *\r
+ * @param hUsb Handle DFU control structure.\r
+ * @return Nothing.\r
+ *\r
+ */\r
+ void (*DFU_Detach)(USBD_HANDLE_T hUsb);\r
+\r
+ /**\r
+ * Optional user overridable function to replace the default DFU class handler.\r
+ *\r
+ * The application software could override the default EP0 class handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_DFU_API::Init().\r
+ * \n\r
+ * @note\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack.\r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*DFU_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+} USBD_DFU_INIT_PARAM_T;\r
+\r
+\r
+/** @brief DFU class API functions structure.\r
+ * @ingroup USBD_DFU\r
+ *\r
+ * This module exposes functions which interact directly with USB device controller hardware.\r
+ *\r
+ */\r
+typedef struct USBD_DFU_API\r
+{\r
+ /** @fn uint32_t GetMemSize(USBD_DFU_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the DFU function driver module.\r
+ *\r
+ * This function is called by application layer before calling pUsbApi->dfu->Init(), to allocate memory used\r
+ * by DFU function driver module. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller.\r
+ * @note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * @param param Structure containing DFU function driver module initialization parameters.\r
+ * @return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_DFU_INIT_PARAM_T* param);\r
+\r
+ /** @fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param)\r
+ * Function to initialize DFU function driver module.\r
+ *\r
+ * This function is called by application layer to initialize DFU function driver module.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param param Structure containing DFU function driver module initialization parameters.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success\r
+ * @retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte aligned or smaller than required.\r
+ * @retval ERR_API_INVALID_PARAM2 Either DFU_Write() or DFU_Done() or DFU_Read() callbacks are not defined.\r
+ * @retval ERR_USBD_BAD_DESC\r
+ * - USB_DFU_DESCRIPTOR_TYPE is not defined immediately after\r
+ * interface descriptor.\r
+ * - wTransferSize in descriptor doesn't match the value passed\r
+ * in param->wTransferSize.\r
+ * - DFU_Detach() is not defined while USB_DFU_WILL_DETACH is set\r
+ * in DFU descriptor.\r
+ * @retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed.\r
+ */\r
+ ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param, uint32_t init_state);\r
+\r
+} USBD_DFU_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+/** @cond ADVANCED_API */\r
+\r
+typedef struct _USBD_DFU_CTRL_T\r
+{\r
+ /*ALIGNED(4)*/ DFU_STATUS_T dfu_req_get_status;\r
+ uint8_t dfu_state;\r
+ uint8_t dfu_status;\r
+ uint8_t download_done;\r
+ uint8_t if_num; /* interface number */\r
+\r
+ uint8_t* xfr_buf;\r
+ USB_DFU_FUNC_DESCRIPTOR* dfu_desc;\r
+\r
+ USB_CORE_CTRL_T* pUsbCtrl;\r
+ /* user defined functions */\r
+ /* return DFU_STATUS_ values defined in mw_usbd_dfu.h */\r
+ uint8_t (*DFU_Write)( uint32_t block_num, uint8_t** src, uint32_t length, uint8_t* bwPollTimeout);\r
+ /* return\r
+ * DFU_STATUS_ : values defined in mw_usbd_dfu.h in case of errors\r
+ * 0 : If end of memory reached\r
+ * length : Amount of data copied to destination buffer\r
+ */\r
+ uint32_t (*DFU_Read)( uint32_t block_num, uint8_t** dst, uint32_t length);\r
+ /* callback called after download is finished */\r
+ void (*DFU_Done)(void);\r
+ /* callback called after USB_REQ_DFU_DETACH is recived */\r
+ void (*DFU_Detach)(USBD_HANDLE_T hUsb);\r
+\r
+} USBD_DFU_CTRL_T;\r
+\r
+\r
+/** @endcond */\r
+\r
+#endif /* __DFUUSER_H__ */\r
--- /dev/null
+/*\r
+ * @brief USB ROM based HID Class driver functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+#include "../../Device.h"\r
+#include "../../Endpoint.h"\r
+\r
+#if defined(USB_DEVICE_ROM_DRIVER)\r
+\r
+/* FIXME Abstract & make this size configurable */\r
+//#define ROMDRIVER_HID_MEM_SIZE 0x800\r
+//uint8_t usb_RomDriver_HID_buffer[ROMDRIVER_HID_MEM_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+uint8_t *reportinbuffer;\r
+uint32_t reportinsize;\r
+\r
+ErrorCode_t GetReport( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* plength);\r
+ErrorCode_t GetReport( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* plength)\r
+{\r
+ uint8_t report[reportinsize];\r
+\r
+ if(reportinbuffer == NULL)\r
+ return (LPC_OK);\r
+ memset(report, 0,reportinsize);\r
+ /* ReportID = SetupPacket.wValue.WB.L; */\r
+ switch (pSetup->wValue.WB.H) {\r
+ case HID_REPORT_INPUT:\r
+ if(CALLBACK_UsbdHid_IsReportChanged())\r
+ {\r
+ *pBuffer = reportinbuffer;\r
+ CALLBACK_UsbdHid_SetReportChange(false);\r
+ }\r
+ else\r
+ {\r
+ *pBuffer = report;\r
+ }\r
+ *plength = (uint16_t)reportinsize;\r
+ break;\r
+ case HID_REPORT_OUTPUT:\r
+ return (ERR_USBD_STALL); /* Not Supported */\r
+ case HID_REPORT_FEATURE:\r
+ return (ERR_USBD_STALL); /* Not Supported */\r
+ }\r
+ return (LPC_OK);\r
+}\r
+ErrorCode_t SetReport( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);\r
+ErrorCode_t SetReport( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length)\r
+{\r
+ /* we will reuse standard EP0Buf */\r
+ if (length == 0)\r
+ return LPC_OK;\r
+ /* ReportID = SetupPacket.wValue.WB.L; */\r
+ switch (pSetup->wValue.WB.H) {\r
+ case HID_REPORT_INPUT:\r
+ return (ERR_USBD_STALL); /* Not Supported */\r
+ case HID_REPORT_OUTPUT:\r
+ CALLBACK_UsbdHid_SetReport(pBuffer,(uint32_t)length);\r
+ break;\r
+ case HID_REPORT_FEATURE:\r
+ return (ERR_USBD_STALL); /* Not Supported */\r
+ }\r
+ return (LPC_OK);\r
+}\r
+ErrorCode_t EpInHdlr (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+ErrorCode_t EpInHdlr (USBD_HANDLE_T hUsb, void* data, uint32_t event)\r
+{\r
+ USB_HID_CTRL_T* pHidCtrl = (USB_HID_CTRL_T*)data;\r
+ uint8_t report[reportinsize];\r
+\r
+ if(reportinbuffer == NULL)\r
+ return (LPC_OK);\r
+ memset(report, 0,reportinsize);\r
+ switch (event) {\r
+ case USB_EVT_IN:\r
+ if(CALLBACK_UsbdHid_IsReportChanged())\r
+ {\r
+ USBD_API->hw->WriteEP(hUsb, pHidCtrl->epin_adr, reportinbuffer, reportinsize);\r
+ CALLBACK_UsbdHid_SetReportChange(false);\r
+ }\r
+ else\r
+ {\r
+ USBD_API->hw->WriteEP(hUsb, pHidCtrl->epin_adr, reportinbuffer, reportinsize);\r
+ }\r
+ break;\r
+ }\r
+ return LPC_OK;\r
+}\r
+void UsbdHid_Init(void)\r
+{\r
+ USBD_HID_INIT_PARAM_T hid_param;\r
+ USB_HID_REPORT_T reports_data;\r
+\r
+ memset((void*)&hid_param, 0, sizeof(USBD_HID_INIT_PARAM_T));\r
+ /* Init reports_data */\r
+ reports_data.len = (uint16_t)CALLBACK_UsbdHid_Register_ReportDescriptor(&reports_data.desc);\r
+ reports_data.idle_time = 0;\r
+ /* Init reports buffer */\r
+ reportinsize = CALLBACK_UsbdHid_Register_ReportInBuffer(&reportinbuffer);\r
+\r
+ /* HID paramas */\r
+ hid_param.mem_base = (uint32_t)usb_RomDriver_HID_buffer;\r
+ hid_param.mem_size = (uint32_t)ROMDRIVER_HID_MEM_SIZE;\r
+ hid_param.max_reports = 1; //TODO let user configures this number\r
+ hid_param.intf_desc = (uint8_t*)CALLBACK_UsbdHid_Register_InterfaceDescriptor();\r
+ hid_param.report_data = &reports_data;\r
+ /* user defined functions */\r
+ hid_param.HID_GetReport = GetReport;\r
+ hid_param.HID_SetReport = SetReport;\r
+ hid_param.HID_EpIn_Hdlr = EpInHdlr;\r
+\r
+ USBD_API->hid->init(UsbHandle, &hid_param);\r
+}\r
+\r
+#endif /* USB_DEVICE_ROM_DRIVER */\r
+\r
+#endif /* USB_CAN_BE_DEVICE */\r
--- /dev/null
+/*\r
+ * @brief Definition of USB ROM based HID class descriptors and their bit defines\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "usbd.h"\r
+\r
+#ifndef __HID_H__\r
+#define __HID_H__\r
+\r
+/** Common definitions and declarations for the library USB HID Class driver.\r
+ * @addtogroup USBD_HID\r
+ * @{\r
+ */\r
+\r
+\r
+/** HID Subclass Codes\r
+ * @{\r
+ */\r
+/** Descriptor Subclass value indicating that the device or interface does not implement a HID boot protocol. */\r
+#define HID_SUBCLASS_NONE 0x00\r
+/** Descriptor Subclass value indicating that the device or interface implements a HID boot protocol. */\r
+#define HID_SUBCLASS_BOOT 0x01\r
+/** @} */\r
+\r
+/** HID Protocol Codes\r
+ * @{\r
+ */\r
+/** Descriptor Protocol value indicating that the device or interface does not belong to a HID boot protocol. */\r
+#define HID_PROTOCOL_NONE 0x00\r
+/** Descriptor Protocol value indicating that the device or interface belongs to the Keyboard HID boot protocol. */\r
+#define HID_PROTOCOL_KEYBOARD 0x01\r
+/** Descriptor Protocol value indicating that the device or interface belongs to the Mouse HID boot protocol. */\r
+#define HID_PROTOCOL_MOUSE 0x02\r
+/** @} */\r
+\r
+\r
+\r
+/** Descriptor Types\r
+ * @{\r
+ */\r
+/** Descriptor header type value, to indicate a HID class HID descriptor. */\r
+#define HID_HID_DESCRIPTOR_TYPE 0x21\r
+/** Descriptor header type value, to indicate a HID class HID report descriptor. */\r
+#define HID_REPORT_DESCRIPTOR_TYPE 0x22\r
+/** Descriptor header type value, to indicate a HID class HID Physical descriptor. */\r
+#define HID_PHYSICAL_DESCRIPTOR_TYPE 0x23\r
+/** @} */\r
+\r
+\r
+/** @brief HID class-specific HID Descriptor.\r
+ *\r
+ * Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID\r
+ * specification for details on the structure elements.\r
+ *\r
+ */\r
+PRE_PACK struct POST_PACK _HID_DESCRIPTOR {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of HID descriptor. */\r
+ uint16_t bcdHID; /**< BCD encoded version that the HID descriptor and device complies to. */\r
+ uint8_t bCountryCode; /**< Country code of the localized device, or zero if universal. */\r
+ uint8_t bNumDescriptors; /**< Total number of HID report descriptors for the interface. */\r
+\r
+ PRE_PACK struct POST_PACK _HID_DESCRIPTOR_LIST {\r
+ uint8_t bDescriptorType; /**< Type of HID report. */\r
+ uint16_t wDescriptorLength; /**< Length of the associated HID report descriptor, in bytes. */\r
+ } DescriptorList[1]; /**< Array of one or more descriptors */\r
+} ;\r
+/** HID class-specific HID Descriptor. */\r
+typedef struct _HID_DESCRIPTOR HID_DESCRIPTOR;\r
+\r
+#define HID_DESC_SIZE (sizeof(HID_DESCRIPTOR))\r
+\r
+/** HID Request Codes\r
+ * @{\r
+ */\r
+#define HID_REQUEST_GET_REPORT 0x01\r
+#define HID_REQUEST_GET_IDLE 0x02\r
+#define HID_REQUEST_GET_PROTOCOL 0x03\r
+#define HID_REQUEST_SET_REPORT 0x09\r
+#define HID_REQUEST_SET_IDLE 0x0A\r
+#define HID_REQUEST_SET_PROTOCOL 0x0B\r
+/** @} */\r
+\r
+/** HID Report Types\r
+ * @{\r
+ */\r
+#define HID_REPORT_INPUT 0x01\r
+#define HID_REPORT_OUTPUT 0x02\r
+#define HID_REPORT_FEATURE 0x03\r
+/** @} */\r
+\r
+\r
+/** Usage Pages\r
+ * @{\r
+ */\r
+#define HID_USAGE_PAGE_UNDEFINED 0x00\r
+#define HID_USAGE_PAGE_GENERIC 0x01\r
+#define HID_USAGE_PAGE_SIMULATION 0x02\r
+#define HID_USAGE_PAGE_VR 0x03\r
+#define HID_USAGE_PAGE_SPORT 0x04\r
+#define HID_USAGE_PAGE_GAME 0x05\r
+#define HID_USAGE_PAGE_DEV_CONTROLS 0x06\r
+#define HID_USAGE_PAGE_KEYBOARD 0x07\r
+#define HID_USAGE_PAGE_LED 0x08\r
+#define HID_USAGE_PAGE_BUTTON 0x09\r
+#define HID_USAGE_PAGE_ORDINAL 0x0A\r
+#define HID_USAGE_PAGE_TELEPHONY 0x0B\r
+#define HID_USAGE_PAGE_CONSUMER 0x0C\r
+#define HID_USAGE_PAGE_DIGITIZER 0x0D\r
+#define HID_USAGE_PAGE_UNICODE 0x10\r
+#define HID_USAGE_PAGE_ALPHANUMERIC 0x14\r
+/** @} */\r
+\r
+\r
+/** Generic Desktop Page (0x01)\r
+ * @{\r
+ */\r
+#define HID_USAGE_GENERIC_POINTER 0x01\r
+#define HID_USAGE_GENERIC_MOUSE 0x02\r
+#define HID_USAGE_GENERIC_JOYSTICK 0x04\r
+#define HID_USAGE_GENERIC_GAMEPAD 0x05\r
+#define HID_USAGE_GENERIC_KEYBOARD 0x06\r
+#define HID_USAGE_GENERIC_KEYPAD 0x07\r
+#define HID_USAGE_GENERIC_X 0x30\r
+#define HID_USAGE_GENERIC_Y 0x31\r
+#define HID_USAGE_GENERIC_Z 0x32\r
+#define HID_USAGE_GENERIC_RX 0x33\r
+#define HID_USAGE_GENERIC_RY 0x34\r
+#define HID_USAGE_GENERIC_RZ 0x35\r
+#define HID_USAGE_GENERIC_SLIDER 0x36\r
+#define HID_USAGE_GENERIC_DIAL 0x37\r
+#define HID_USAGE_GENERIC_WHEEL 0x38\r
+#define HID_USAGE_GENERIC_HATSWITCH 0x39\r
+#define HID_USAGE_GENERIC_COUNTED_BUFFER 0x3A\r
+#define HID_USAGE_GENERIC_BYTE_COUNT 0x3B\r
+#define HID_USAGE_GENERIC_MOTION_WAKEUP 0x3C\r
+#define HID_USAGE_GENERIC_VX 0x40\r
+#define HID_USAGE_GENERIC_VY 0x41\r
+#define HID_USAGE_GENERIC_VZ 0x42\r
+#define HID_USAGE_GENERIC_VBRX 0x43\r
+#define HID_USAGE_GENERIC_VBRY 0x44\r
+#define HID_USAGE_GENERIC_VBRZ 0x45\r
+#define HID_USAGE_GENERIC_VNO 0x46\r
+#define HID_USAGE_GENERIC_SYSTEM_CTL 0x80\r
+#define HID_USAGE_GENERIC_SYSCTL_POWER 0x81\r
+#define HID_USAGE_GENERIC_SYSCTL_SLEEP 0x82\r
+#define HID_USAGE_GENERIC_SYSCTL_WAKE 0x83\r
+#define HID_USAGE_GENERIC_SYSCTL_CONTEXT_MENU 0x84\r
+#define HID_USAGE_GENERIC_SYSCTL_MAIN_MENU 0x85\r
+#define HID_USAGE_GENERIC_SYSCTL_APP_MENU 0x86\r
+#define HID_USAGE_GENERIC_SYSCTL_HELP_MENU 0x87\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_EXIT 0x88\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_SELECT 0x89\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_RIGHT 0x8A\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_LEFT 0x8B\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_UP 0x8C\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_DOWN 0x8D\r
+/** @} */\r
+\r
+/** Simulation Controls Page (0x02)\r
+ * @{\r
+ */\r
+#define HID_USAGE_SIMULATION_RUDDER 0xBA\r
+#define HID_USAGE_SIMULATION_THROTTLE 0xBB\r
+/** @} */\r
+\r
+/* Virtual Reality Controls Page (0x03) */\r
+/* ... */\r
+\r
+/* Sport Controls Page (0x04) */\r
+/* ... */\r
+\r
+/* Game Controls Page (0x05) */\r
+/* ... */\r
+\r
+/* Generic Device Controls Page (0x06) */\r
+/* ... */\r
+\r
+/** Keyboard/Keypad Page (0x07)\r
+ * @{\r
+ */\r
+/** Error "keys" */\r
+#define HID_USAGE_KEYBOARD_NOEVENT 0x00\r
+#define HID_USAGE_KEYBOARD_ROLLOVER 0x01\r
+#define HID_USAGE_KEYBOARD_POSTFAIL 0x02\r
+#define HID_USAGE_KEYBOARD_UNDEFINED 0x03\r
+\r
+/** Letters */\r
+#define HID_USAGE_KEYBOARD_aA 0x04\r
+#define HID_USAGE_KEYBOARD_zZ 0x1D\r
+\r
+/** Numbers */\r
+#define HID_USAGE_KEYBOARD_ONE 0x1E\r
+#define HID_USAGE_KEYBOARD_ZERO 0x27\r
+\r
+#define HID_USAGE_KEYBOARD_RETURN 0x28\r
+#define HID_USAGE_KEYBOARD_ESCAPE 0x29\r
+#define HID_USAGE_KEYBOARD_DELETE 0x2A\r
+\r
+/** Funtion keys */\r
+#define HID_USAGE_KEYBOARD_F1 0x3A\r
+#define HID_USAGE_KEYBOARD_F12 0x45\r
+\r
+#define HID_USAGE_KEYBOARD_PRINT_SCREEN 0x46\r
+\r
+/** Modifier Keys */\r
+#define HID_USAGE_KEYBOARD_LCTRL 0xE0\r
+#define HID_USAGE_KEYBOARD_LSHFT 0xE1\r
+#define HID_USAGE_KEYBOARD_LALT 0xE2\r
+#define HID_USAGE_KEYBOARD_LGUI 0xE3\r
+#define HID_USAGE_KEYBOARD_RCTRL 0xE4\r
+#define HID_USAGE_KEYBOARD_RSHFT 0xE5\r
+#define HID_USAGE_KEYBOARD_RALT 0xE6\r
+#define HID_USAGE_KEYBOARD_RGUI 0xE7\r
+#define HID_USAGE_KEYBOARD_SCROLL_LOCK 0x47\r
+#define HID_USAGE_KEYBOARD_NUM_LOCK 0x53\r
+#define HID_USAGE_KEYBOARD_CAPS_LOCK 0x39\r
+/** @} */\r
+\r
+/* ... */\r
+\r
+/** LED Page (0x08)\r
+ * @{\r
+ */\r
+#define HID_USAGE_LED_NUM_LOCK 0x01\r
+#define HID_USAGE_LED_CAPS_LOCK 0x02\r
+#define HID_USAGE_LED_SCROLL_LOCK 0x03\r
+#define HID_USAGE_LED_COMPOSE 0x04\r
+#define HID_USAGE_LED_KANA 0x05\r
+#define HID_USAGE_LED_POWER 0x06\r
+#define HID_USAGE_LED_SHIFT 0x07\r
+#define HID_USAGE_LED_DO_NOT_DISTURB 0x08\r
+#define HID_USAGE_LED_MUTE 0x09\r
+#define HID_USAGE_LED_TONE_ENABLE 0x0A\r
+#define HID_USAGE_LED_HIGH_CUT_FILTER 0x0B\r
+#define HID_USAGE_LED_LOW_CUT_FILTER 0x0C\r
+#define HID_USAGE_LED_EQUALIZER_ENABLE 0x0D\r
+#define HID_USAGE_LED_SOUND_FIELD_ON 0x0E\r
+#define HID_USAGE_LED_SURROUND_FIELD_ON 0x0F\r
+#define HID_USAGE_LED_REPEAT 0x10\r
+#define HID_USAGE_LED_STEREO 0x11\r
+#define HID_USAGE_LED_SAMPLING_RATE_DETECT 0x12\r
+#define HID_USAGE_LED_SPINNING 0x13\r
+#define HID_USAGE_LED_CAV 0x14\r
+#define HID_USAGE_LED_CLV 0x15\r
+#define HID_USAGE_LED_RECORDING_FORMAT_DET 0x16\r
+#define HID_USAGE_LED_OFF_HOOK 0x17\r
+#define HID_USAGE_LED_RING 0x18\r
+#define HID_USAGE_LED_MESSAGE_WAITING 0x19\r
+#define HID_USAGE_LED_DATA_MODE 0x1A\r
+#define HID_USAGE_LED_BATTERY_OPERATION 0x1B\r
+#define HID_USAGE_LED_BATTERY_OK 0x1C\r
+#define HID_USAGE_LED_BATTERY_LOW 0x1D\r
+#define HID_USAGE_LED_SPEAKER 0x1E\r
+#define HID_USAGE_LED_HEAD_SET 0x1F\r
+#define HID_USAGE_LED_HOLD 0x20\r
+#define HID_USAGE_LED_MICROPHONE 0x21\r
+#define HID_USAGE_LED_COVERAGE 0x22\r
+#define HID_USAGE_LED_NIGHT_MODE 0x23\r
+#define HID_USAGE_LED_SEND_CALLS 0x24\r
+#define HID_USAGE_LED_CALL_PICKUP 0x25\r
+#define HID_USAGE_LED_CONFERENCE 0x26\r
+#define HID_USAGE_LED_STAND_BY 0x27\r
+#define HID_USAGE_LED_CAMERA_ON 0x28\r
+#define HID_USAGE_LED_CAMERA_OFF 0x29\r
+#define HID_USAGE_LED_ON_LINE 0x2A\r
+#define HID_USAGE_LED_OFF_LINE 0x2B\r
+#define HID_USAGE_LED_BUSY 0x2C\r
+#define HID_USAGE_LED_READY 0x2D\r
+#define HID_USAGE_LED_PAPER_OUT 0x2E\r
+#define HID_USAGE_LED_PAPER_JAM 0x2F\r
+#define HID_USAGE_LED_REMOTE 0x30\r
+#define HID_USAGE_LED_FORWARD 0x31\r
+#define HID_USAGE_LED_REVERSE 0x32\r
+#define HID_USAGE_LED_STOP 0x33\r
+#define HID_USAGE_LED_REWIND 0x34\r
+#define HID_USAGE_LED_FAST_FORWARD 0x35\r
+#define HID_USAGE_LED_PLAY 0x36\r
+#define HID_USAGE_LED_PAUSE 0x37\r
+#define HID_USAGE_LED_RECORD 0x38\r
+#define HID_USAGE_LED_ERROR 0x39\r
+#define HID_USAGE_LED_SELECTED_INDICATOR 0x3A\r
+#define HID_USAGE_LED_IN_USE_INDICATOR 0x3B\r
+#define HID_USAGE_LED_MULTI_MODE_INDICATOR 0x3C\r
+#define HID_USAGE_LED_INDICATOR_ON 0x3D\r
+#define HID_USAGE_LED_INDICATOR_FLASH 0x3E\r
+#define HID_USAGE_LED_INDICATOR_SLOW_BLINK 0x3F\r
+#define HID_USAGE_LED_INDICATOR_FAST_BLINK 0x40\r
+#define HID_USAGE_LED_INDICATOR_OFF 0x41\r
+#define HID_USAGE_LED_FLASH_ON_TIME 0x42\r
+#define HID_USAGE_LED_SLOW_BLINK_ON_TIME 0x43\r
+#define HID_USAGE_LED_SLOW_BLINK_OFF_TIME 0x44\r
+#define HID_USAGE_LED_FAST_BLINK_ON_TIME 0x45\r
+#define HID_USAGE_LED_FAST_BLINK_OFF_TIME 0x46\r
+#define HID_USAGE_LED_INDICATOR_COLOR 0x47\r
+#define HID_USAGE_LED_RED 0x48\r
+#define HID_USAGE_LED_GREEN 0x49\r
+#define HID_USAGE_LED_AMBER 0x4A\r
+#define HID_USAGE_LED_GENERIC_INDICATOR 0x4B\r
+/** @} */\r
+\r
+/* Button Page (0x09)\r
+ */\r
+/* There is no need to label these usages. */\r
+\r
+/* Ordinal Page (0x0A)\r
+ */\r
+/* There is no need to label these usages. */\r
+\r
+/** Telephony Device Page (0x0B)\r
+ * @{\r
+ */\r
+#define HID_USAGE_TELEPHONY_PHONE 0x01\r
+#define HID_USAGE_TELEPHONY_ANSWERING_MACHINE 0x02\r
+#define HID_USAGE_TELEPHONY_MESSAGE_CONTROLS 0x03\r
+#define HID_USAGE_TELEPHONY_HANDSET 0x04\r
+#define HID_USAGE_TELEPHONY_HEADSET 0x05\r
+#define HID_USAGE_TELEPHONY_KEYPAD 0x06\r
+#define HID_USAGE_TELEPHONY_PROGRAMMABLE_BUTTON 0x07\r
+/** @} */\r
+/* ... */\r
+\r
+/** Consumer Page (0x0C)\r
+ * @{\r
+ */\r
+#define HID_USAGE_CONSUMER_CONTROL 0x01\r
+#define HID_USAGE_CONSUMER_FAST_FORWARD 0xB3\r
+#define HID_USAGE_CONSUMER_REWIND 0xB4\r
+#define HID_USAGE_CONSUMER_PLAY_PAUSE 0xCD\r
+#define HID_USAGE_CONSUMER_VOLUME_INCREMENT 0xE9\r
+#define HID_USAGE_CONSUMER_VOLUME_DECREMENT 0xEA\r
+/** @} */\r
+/* ... */\r
+\r
+/* and others ... */\r
+\r
+\r
+/** HID Report Item Macros\r
+ * @{\r
+ */\r
+/** Main Items */\r
+#define HID_Input(x) 0x81,x\r
+#define HID_Output(x) 0x91,x\r
+#define HID_Feature(x) 0xB1,x\r
+#define HID_Collection(x) 0xA1,x\r
+#define HID_EndCollection 0xC0\r
+\r
+/** Data (Input, Output, Feature) */\r
+#define HID_Data 0<<0\r
+#define HID_Constant 1<<0\r
+#define HID_Array 0<<1\r
+#define HID_Variable 1<<1\r
+#define HID_Absolute 0<<2\r
+#define HID_Relative 1<<2\r
+#define HID_NoWrap 0<<3\r
+#define HID_Wrap 1<<3\r
+#define HID_Linear 0<<4\r
+#define HID_NonLinear 1<<4\r
+#define HID_PreferredState 0<<5\r
+#define HID_NoPreferred 1<<5\r
+#define HID_NoNullPosition 0<<6\r
+#define HID_NullState 1<<6\r
+#define HID_NonVolatile 0<<7\r
+#define HID_Volatile 1<<7\r
+\r
+/** Collection Data */\r
+#define HID_Physical 0x00\r
+#define HID_Application 0x01\r
+#define HID_Logical 0x02\r
+#define HID_Report 0x03\r
+#define HID_NamedArray 0x04\r
+#define HID_UsageSwitch 0x05\r
+#define HID_UsageModifier 0x06\r
+\r
+/** Global Items */\r
+#define HID_UsagePage(x) 0x05,x\r
+#define HID_UsagePageVendor(x) 0x06,x,0xFF\r
+#define HID_LogicalMin(x) 0x15,x\r
+#define HID_LogicalMinS(x) 0x16,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_LogicalMinL(x) 0x17,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_LogicalMax(x) 0x25,x\r
+#define HID_LogicalMaxS(x) 0x26,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_LogicalMaxL(x) 0x27,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_PhysicalMin(x) 0x35,x\r
+#define HID_PhysicalMinS(x) 0x36,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_PhysicalMinL(x) 0x37,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_PhysicalMax(x) 0x45,x\r
+#define HID_PhysicalMaxS(x) 0x46,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_PhysicalMaxL(x) 0x47,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_UnitExponent(x) 0x55,x\r
+#define HID_Unit(x) 0x65,x\r
+#define HID_UnitS(x) 0x66,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_UnitL(x) 0x67,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_ReportSize(x) 0x75,x\r
+#define HID_ReportID(x) 0x85,x\r
+#define HID_ReportCount(x) 0x95,x\r
+#define HID_Push 0xA0\r
+#define HID_Pop 0xB0\r
+\r
+/** Local Items */\r
+#define HID_Usage(x) 0x09,x\r
+#define HID_UsageMin(x) 0x19,x\r
+#define HID_UsageMax(x) 0x29,x\r
+/** @} */\r
+uint32_t CALLBACK_UsbdHid_Register_InterfaceDescriptor(void);\r
+uint32_t CALLBACK_UsbdHid_Register_ReportDescriptor(uint8_t **dest);\r
+uint32_t CALLBACK_UsbdHid_Register_ReportInBuffer(uint8_t **dest);\r
+void CALLBACK_UsbdHid_SetReport(uint8_t **reportoutbuffer, uint32_t reportoutsize);\r
+void CALLBACK_UsbdHid_SetReportChange(bool newstate);\r
+bool CALLBACK_UsbdHid_IsReportChanged(void);\r
+\r
+/** @} */\r
+\r
+#endif /* __HID_H__ */\r
--- /dev/null
+/*\r
+ * @brief Definition of functions exported by ROM based HID function driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __HIDUSER_H__\r
+#define __HIDUSER_H__\r
+\r
+#include "usbd.h"\r
+#include "usbd_hid.h"\r
+#include "usbd_core.h"\r
+\r
+\r
+/** @ingroup Group_USBD_Class\r
+ * @defgroup USBD_HID HID Class Function Driver\r
+ * @section Sec_HIDModDescription Module Description\r
+ * HID Class Function Driver module. This module contains an internal implementation of the USB HID Class.\r
+ * User applications can use this class driver instead of implementing the HID class manually\r
+ * via the low-level HW and core APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB HID Class.\r
+ */\r
+\r
+/** @brief HID report descriptor data structure.\r
+ * @ingroup USBD_HID\r
+ *\r
+ * @details This structure is used as part of HID function driver initialization\r
+ * parameter structure @ref USBD_HID_INIT_PARAM_T. This structure contains\r
+ * details of a report type supported by the application. An application\r
+ * can support multiple report types as a single HID device. The application\r
+ * should define this report type data struture per report it supports and\r
+ * the array of reoprt types to USBD_HID_API::init() through @ref USBD_HID_INIT_PARAM_T\r
+ * structure.\r
+ *\r
+ * @note All descriptor pointers assigned in this structure should be on 4 byte\r
+ * aligned address boundary.\r
+ *\r
+ */\r
+typedef struct _HID_REPORT_T {\r
+ uint16_t len; /**< Size of the report descriptor in bytes. */\r
+ uint8_t idle_time; /**< This value is used by stack to respond to Set_Idle &\r
+ GET_Idle requests for the specified report ID. The value\r
+ of this field specified the rate at which duplicate reports\r
+ are generated for the specified Report ID. For example, a\r
+ device with two input reports could specify an idle rate of\r
+ 20 milliseconds for report ID 1 and 500 milliseconds for\r
+ report ID 2.\r
+ */\r
+ uint8_t __pad; /**< Padding space. */\r
+ uint8_t* desc; /**< Report descriptor. */\r
+} USB_HID_REPORT_T;\r
+\r
+/** @brief USB descriptors data structure.\r
+ * @ingroup USBD_HID\r
+ *\r
+ * @details This module exposes functions which interact directly with USB device stack's core layer.\r
+ * The application layer uses this component when it has to implement custom class function driver or\r
+ * standard class function driver which is not part of the current USB device stack.\r
+ * The functions exposed by this interface are to register class specific EP0 handlers and corresponding\r
+ * utility functions to manipulate EP0 state machine of the stack. This interface also exposes\r
+ * function to register custom endpoint interrupt handler.\r
+ *\r
+ */\r
+typedef struct USBD_HID_INIT_PARAM\r
+{\r
+ /* memory allocation params */\r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. @note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 4 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use.\r
+ @note The \em mem_size should be greater than the size\r
+ returned by USBD_HID_API::GetMemSize() routine.*/\r
+ /* HID paramas */\r
+ uint8_t max_reports; /**< Number of HID reports supported by this instance\r
+ of HID class driver.\r
+ */\r
+ uint8_t* intf_desc; /**< Pointer to the HID interface descriptor within the\r
+ descriptor array (\em high_speed_desc) passed to Init()\r
+ through @ref USB_CORE_DESCS_T structure.\r
+ */\r
+ USB_HID_REPORT_T* report_data; /**< Pointer to an array of HID report descriptor\r
+ data structure (@ref USB_HID_REPORT_T). The number\r
+ of elements in the array should be same a \em max_reports\r
+ value. The stack uses this array to respond to\r
+ requests recieved for various HID report descriptor\r
+ information. @note This array should be of global scope.\r
+ */\r
+\r
+ /* user defined functions */\r
+ /* required functions */\r
+ /**\r
+ * HID get report callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a HID_REQUEST_GET_REPORT request. The setup packet data (\em pSetup)\r
+ * is passed to the callback so that application can extract the report ID, report\r
+ * type and other information need to generate the report. @note HID reports are sent\r
+ * via interrupt IN endpoint also. This function is called only when report request\r
+ * is received on control endpoint. Application should implement \em HID_EpIn_Hdlr to\r
+ * send reports to host via interrupt IN endpoint.\r
+ *\r
+ *\r
+ * @param hHid Handle to HID function driver.\r
+ * @param pSetup Pointer to setup packet recived from host.\r
+ * @param pBuffer Pointer to a pointer of data buffer containing report data.\r
+ * Pointer-to-pointer is used to implement zero-copy buffers.\r
+ * @param length Amount of data copied to destination buffer.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*HID_GetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length);\r
+\r
+ /**\r
+ * HID set report callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a HID_REQUEST_SET_REPORT request. The setup packet data (\em pSetup)\r
+ * is passed to the callback so that application can extract the report ID, report\r
+ * type and other information need to modify the report. An application might choose\r
+ * to ignore input Set_Report requests as meaningless. Alternatively these reports\r
+ * could be used to reset the origin of a control (that is, current position should\r
+ * report zero).\r
+ *\r
+ * @param hHid Handle to HID function driver.\r
+ * @param pSetup Pointer to setup packet recived from host.\r
+ * @param pBuffer Pointer to a pointer of data buffer containing report data.\r
+ * Pointer-to-pointer is used to implement zero-copy buffers.\r
+ * @param length Amount of data copied to destination buffer.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*HID_SetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);\r
+\r
+ /* optional functions */\r
+\r
+ /**\r
+ * Optional callback function to handle HID_GetPhysDesc request.\r
+ *\r
+ * The application software could provide this callback HID_GetPhysDesc handler to\r
+ * handle get physical descriptor requests sent by the host. When host requests\r
+ * Physical Descriptor set 0, application should return a special descriptor\r
+ * identifying the number of descriptor sets and their sizes. A Get_Descriptor\r
+ * request with the Physical Index equal to 1 should return the first Physical\r
+ * Descriptor set. A device could possibly have alternate uses for its items.\r
+ * These can be enumerated by issuing subsequent Get_Descriptor requests while\r
+ * incrementing the Descriptor Index. A device should return the last descriptor\r
+ * set to requests with an index greater than the last number defined in the HID\r
+ * descriptor.\r
+ * @note Applications which don't have physical descriptor should set this data member\r
+ * to zero before calling the USBD_HID_API::Init().\r
+ * \n\r
+ *\r
+ * @param hHid Handle to HID function driver.\r
+ * @param pSetup Pointer to setup packet recived from host.\r
+ * @param pBuf Pointer to a pointer of data buffer containing physical descriptor\r
+ * data. If the physical descriptor is in USB accessable memory area\r
+ * application could just update the pointer or else it should copy\r
+ * the descriptor to the address pointed by this pointer.\r
+ * @param length Amount of data copied to destination buffer or descriptor length.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*HID_GetPhysDesc)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);\r
+\r
+ /**\r
+ * Optional callback function to handle HID_REQUEST_SET_IDLE request.\r
+ *\r
+ * The application software could provide this callback to handle HID_REQUEST_SET_IDLE\r
+ * requests sent by the host. This callback is provided to applications to adjust\r
+ * timers associated with various reports, which are sent to host over interrupt\r
+ * endpoint. The setup packet data (\em pSetup) is passed to the callback so that\r
+ * application can extract the report ID, report type and other information need\r
+ * to modify the report's idle time.\r
+ * @note Applications which don't send reports on Interrupt endpoint or don't\r
+ * have idle time between reports should set this data member to zero before\r
+ * calling the USBD_HID_API::Init().\r
+ * \n\r
+ *\r
+ * @param hHid Handle to HID function driver.\r
+ * @param pSetup Pointer to setup packet recived from host.\r
+ * @param idleTime Idle time to be set for the specified report.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*HID_SetIdle)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t idleTime);\r
+\r
+ /**\r
+ * Optional callback function to handle HID_REQUEST_SET_PROTOCOL request.\r
+ *\r
+ * The application software could provide this callback to handle HID_REQUEST_SET_PROTOCOL\r
+ * requests sent by the host. This callback is provided to applications to adjust\r
+ * modes of their code between boot mode and report mode.\r
+ * @note Applications which don't support protocol modes should set this data member\r
+ * to zero before calling the USBD_HID_API::Init().\r
+ * \n\r
+ *\r
+ * @param hHid Handle to HID function driver.\r
+ * @param pSetup Pointer to setup packet recived from host.\r
+ * @param protocol Protocol mode.\r
+ * 0 = Boot Protocol\r
+ * 1 = Report Protocol\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*HID_SetProtocol)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t protocol);\r
+\r
+ /**\r
+ * Optional Interrupt IN endpoint event handler.\r
+ *\r
+ * The application software could provide Interrupt IN endpoint event handler.\r
+ * Application which send reports to host on interrupt endpoint should provide\r
+ * an endpoint event handler through this data member. This data memeber is\r
+ * ignored if the interface descriptor \em intf_desc doesn't have any IN interrupt\r
+ * endpoint descriptor associated.\r
+ * \n\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param data Handle to HID function driver.\r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should return @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*HID_EpIn_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+ /**\r
+ * Optional Interrupt OUT endpoint event handler.\r
+ *\r
+ * The application software could provide Interrupt OUT endpoint event handler.\r
+ * Application which recieves reports from host on interrupt endpoint should provide\r
+ * an endpoint event handler through this data member. This data memeber is\r
+ * ignored if the interface descriptor \em intf_desc doesn't have any OUT interrupt\r
+ * endpoint descriptor associated.\r
+ * \n\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param data Handle to HID function driver.\r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should return @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*HID_EpOut_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+ /* user overridable function */\r
+ /**\r
+ * Optional user overridable function to replace the default HID_GetReportDesc handler.\r
+ *\r
+ * The application software could override the default HID_GetReportDesc handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_HID_API::Init() and also provide report data array\r
+ * \em report_data field.\r
+ * \n\r
+ * @note\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack.\r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*HID_GetReportDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);\r
+ /**\r
+ * Optional user overridable function to replace the default HID class handler.\r
+ *\r
+ * The application software could override the default EP0 class handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_HID_API::Init().\r
+ * \n\r
+ * @note\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack.\r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*HID_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+} USBD_HID_INIT_PARAM_T;\r
+\r
+/** @brief HID class API functions structure.\r
+ * @ingroup USBD_HID\r
+ *\r
+ * This structure contains pointers to all the function exposed by HID function driver module.\r
+ *\r
+ */\r
+typedef struct USBD_HID_API\r
+{\r
+ /** @fn uint32_t GetMemSize(USBD_HID_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the HID function driver module.\r
+ *\r
+ * This function is called by application layer before calling pUsbApi->hid->Init(), to allocate memory used\r
+ * by HID function driver module. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller.\r
+ * @note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * @param param Structure containing HID function driver module initialization parameters.\r
+ * @return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_HID_INIT_PARAM_T* param);\r
+\r
+ /** @fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param)\r
+ * Function to initialize HID function driver module.\r
+ *\r
+ * This function is called by application layer to initialize HID function driver\r
+ * module. On successful initialization the function returns a handle to HID\r
+ * function driver module in passed param structure.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param param Structure containing HID function driver module\r
+ * initialization parameters.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success\r
+ * @retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte\r
+ * aligned or smaller than required.\r
+ * @retval ERR_API_INVALID_PARAM2 Either HID_GetReport() or HID_SetReport()\r
+ * callback are not defined.\r
+ * @retval ERR_USBD_BAD_DESC HID_HID_DESCRIPTOR_TYPE is not defined\r
+ * immediately after interface descriptor.\r
+ * @retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed.\r
+ * @retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed.\r
+ */\r
+ ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param);\r
+\r
+} USBD_HID_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+/** @cond ADVANCED_API */\r
+\r
+typedef struct _HID_CTRL_T {\r
+ /* pointer to controller */\r
+ USB_CORE_CTRL_T* pUsbCtrl;\r
+ /* descriptor pointers */\r
+ uint8_t* hid_desc;\r
+ USB_HID_REPORT_T* report_data;\r
+\r
+ uint8_t protocol;\r
+ uint8_t if_num; /* interface number */\r
+ uint8_t epin_adr; /* IN interrupt endpoint */\r
+ uint8_t epout_adr; /* OUT interrupt endpoint */\r
+\r
+ /* user defined functions */\r
+ ErrorCode_t (*HID_GetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length);\r
+ ErrorCode_t (*HID_SetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);\r
+ ErrorCode_t (*HID_GetPhysDesc)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);\r
+ ErrorCode_t (*HID_SetIdle)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t idleTime);\r
+ ErrorCode_t (*HID_SetProtocol)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t protocol);\r
+\r
+ /* virtual overridable functions */\r
+ ErrorCode_t (*HID_GetReportDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);\r
+\r
+}USB_HID_CTRL_T;\r
+\r
+\r
+/** @endcond */\r
+\r
+#endif /* __HIDUSER_H__ */\r
--- /dev/null
+/*\r
+ * @brief USB ROM based hardware function prototypes\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "usbd_core.h"\r
+\r
+#ifndef __USBHW_H__\r
+#define __USBHW_H__\r
+\r
+\r
+/** @ingroup Group_USBD\r
+ * @defgroup USBD_HW USB Device Controller Driver\r
+ * @section Sec_HWModDescription Module Description\r
+ * The Device Controller Driver Layer implements the routines to deal directly with the hardware.\r
+ */\r
+\r
+/** @ingroup USBD_HW\r
+* USB Endpoint/class handler Callback Events.\r
+*\r
+*/\r
+enum USBD_EVENT_T {\r
+ USB_EVT_SETUP =1, /**< 1 Setup Packet received */\r
+ USB_EVT_OUT, /**< 2 OUT Packet received */\r
+ USB_EVT_IN, /**< 3 IN Packet sent */\r
+ USB_EVT_OUT_NAK, /**< 4 OUT Packet - Not Acknowledged */\r
+ USB_EVT_IN_NAK, /**< 5 IN Packet - Not Acknowledged */\r
+ USB_EVT_OUT_STALL, /**< 6 OUT Packet - Stalled */\r
+ USB_EVT_IN_STALL, /**< 7 IN Packet - Stalled */\r
+ USB_EVT_OUT_DMA_EOT, /**< 8 DMA OUT EP - End of Transfer */\r
+ USB_EVT_IN_DMA_EOT, /**< 9 DMA IN EP - End of Transfer */\r
+ USB_EVT_OUT_DMA_NDR, /**< 10 DMA OUT EP - New Descriptor Request */\r
+ USB_EVT_IN_DMA_NDR, /**< 11 DMA IN EP - New Descriptor Request */\r
+ USB_EVT_OUT_DMA_ERR, /**< 12 DMA OUT EP - Error */\r
+ USB_EVT_IN_DMA_ERR, /**< 13 DMA IN EP - Error */\r
+ USB_EVT_RESET, /**< 14 Reset event recieved */\r
+ USB_EVT_SOF, /**< 15 Start of Frame event */\r
+ USB_EVT_DEV_STATE, /**< 16 Device status events */\r
+ USB_EVT_DEV_ERROR, /**< 16 Device error events */\r
+};\r
+\r
+/**\r
+ * @brief Hardware API functions structure.\r
+ * @ingroup USBD_HW\r
+ *\r
+ * This module exposes functions which interact directly with USB device controller hardware.\r
+ *\r
+ */\r
+typedef struct USBD_HW_API\r
+{\r
+ /** @fn uint32_t GetMemSize(USBD_API_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the USB device stack's DCD and core layers.\r
+ *\r
+ * This fuction is called by application layer before calling pUsbApi->hw->Init(), to allocate memory used\r
+ * by DCD and core layers. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller.\r
+ * @note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * @param param Structure containing USB device stack initialization parameters.\r
+ * @return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_API_INIT_PARAM_T* param);\r
+\r
+ /** @fn ErrorCode_t Init(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param)\r
+ * Function to initialize USB device stack's DCD and core layers.\r
+ *\r
+ * This function is called by application layer to initialize USB hardware and core layers.\r
+ * On successful initialization the function returns a handle to USB device stack which should\r
+ * be passed to the rest of the functions.\r
+ *\r
+ * \param[in,out] phUsb Pointer to the USB device stack handle of type USBD_HANDLE_T.\r
+ * @param param Structure containing USB device stack initialization parameters.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK(0) On success\r
+ * @retval ERR_USBD_BAD_MEM_BUF(0x0004000b) When insufficient memory buffer is passed or memory\r
+ * is not aligned on 2048 boundary.\r
+ */\r
+ ErrorCode_t (*Init)(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param);\r
+\r
+ /** @fn void Connect(USBD_HANDLE_T hUsb, uint32_t con)\r
+ * Function to make USB device visible/invisible on the USB bus.\r
+ *\r
+ * This function is called after the USB initialization. This function uses the soft connect\r
+ * feature to make the device visible on the USB bus. This function is called only after the\r
+ * application is ready to handle the USB data. The enumeration process is started by the\r
+ * host after the device detection. The driver handles the enumeration process according to\r
+ * the USB descriptors passed in the USB initialization function.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param con States whether to connect (1) or to disconnect (0).\r
+ * @return Nothing.\r
+ */\r
+ void (*Connect)(USBD_HANDLE_T hUsb, uint32_t con);\r
+\r
+ /** @fn void ISR(USBD_HANDLE_T hUsb)\r
+ * Function to USB device controller interrupt events.\r
+ *\r
+ * When the user application is active the interrupt handlers are mapped in the user flash\r
+ * space. The user application must provide an interrupt handler for the USB interrupt and\r
+ * call this function in the interrupt handler routine. The driver interrupt handler takes\r
+ * appropriate action according to the data received on the USB bus.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @return Nothing.\r
+ */\r
+ void (*ISR)(USBD_HANDLE_T hUsb);\r
+\r
+ /** @fn void Reset(USBD_HANDLE_T hUsb)\r
+ * Function to Reset USB device stack and hardware controller.\r
+ *\r
+ * Reset USB device stack and hardware controller. Disables all endpoints except EP0.\r
+ * Clears all pending interrupts and resets endpoint transfer queues.\r
+ * This function is called internally by pUsbApi->hw->init() and from reset event.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @return Nothing.\r
+ */\r
+ void (*Reset)(USBD_HANDLE_T hUsb);\r
+\r
+ /** @fn void ForceFullSpeed(USBD_HANDLE_T hUsb, uint32_t cfg)\r
+ * Function to force high speed USB device to operate in full speed mode.\r
+ *\r
+ * This function is useful for testing the behaviour of current device when connected\r
+ * to a full speed only hosts.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param cfg When 1 - set force full-speed or\r
+ * 0 - clear force full-speed.\r
+ * @return Nothing.\r
+ */\r
+ void (*ForceFullSpeed )(USBD_HANDLE_T hUsb, uint32_t cfg);\r
+\r
+ /** @fn void WakeUpCfg(USBD_HANDLE_T hUsb, uint32_t cfg)\r
+ * Function to configure USB device controller to wakeup host on remote events.\r
+ *\r
+ * This function is called by application layer to configure the USB device controller\r
+ * to wakeup on remote events. It is recommended to call this function from users's\r
+ * USB_WakeUpCfg() callback routine registered with stack.\r
+ * @note User's USB_WakeUpCfg() is registered with stack by setting the USB_WakeUpCfg member \r
+ * of USBD_API_INIT_PARAM_T structure before calling pUsbApi->hw->Init() routine.\r
+ * Certain USB device controllers needed to keep some clocks always on to generate \r
+ * resume signaling through pUsbApi->hw->WakeUp(). This hook is provided to support \r
+ * such controllers. In most controllers cases this is an empty routine.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param cfg When 1 - Configure controller to wake on remote events or\r
+ * 0 - Configure controller not to wake on remote events.\r
+ * @return Nothing.\r
+ */\r
+ void (*WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg);\r
+\r
+ /** @fn void SetAddress(USBD_HANDLE_T hUsb, uint32_t adr)\r
+ * Function to set USB address assigned by host in device controller hardware.\r
+ *\r
+ * This function is called automatically when USB_REQUEST_SET_ADDRESS request is received\r
+ * by the stack from USB host.\r
+ * This interface is provided to users to invoke this function in other scenarios which are not\r
+ * handle by current stack. In most user applications this function is not called directly.\r
+ * Also this function can be used by users who are selectively modifying the USB device stack's\r
+ * standard handlers through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param adr USB bus Address to which the device controller should respond. Usually\r
+ * assigned by the USB host.\r
+ * @return Nothing.\r
+ */\r
+ void (*SetAddress)(USBD_HANDLE_T hUsb, uint32_t adr);\r
+\r
+ /** @fn void Configure(USBD_HANDLE_T hUsb, uint32_t cfg)\r
+ * Function to configure device controller hardware with selected configuration.\r
+ *\r
+ * This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received\r
+ * by the stack from USB host.\r
+ * This interface is provided to users to invoke this function in other scenarios which are not\r
+ * handle by current stack. In most user applications this function is not called directly.\r
+ * Also this function can be used by users who are selectively modifying the USB device stack's\r
+ * standard handlers through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param cfg Configuration index.\r
+ * @return Nothing.\r
+ */\r
+ void (*Configure)(USBD_HANDLE_T hUsb, uint32_t cfg);\r
+\r
+ /** @fn void ConfigEP(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD)\r
+ * Function to configure USB Endpoint according to descriptor.\r
+ *\r
+ * This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received\r
+ * by the stack from USB host. All the endpoints associated with the selected configuration\r
+ * are configured.\r
+ * This interface is provided to users to invoke this function in other scenarios which are not\r
+ * handle by current stack. In most user applications this function is not called directly.\r
+ * Also this function can be used by users who are selectively modifying the USB device stack's\r
+ * standard handlers through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param pEPD Endpoint descriptor structure defined in USB 2.0 specification.\r
+ * @return Nothing.\r
+ */\r
+ void (*ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD);\r
+\r
+ /** @fn void DirCtrlEP(USBD_HANDLE_T hUsb, uint32_t dir)\r
+ * Function to set firection for USB control endpoint EP0.\r
+ *\r
+ * This function is called automatically by the stack on need bassis.\r
+ * This interface is provided to users to invoke this function in other scenarios which are not\r
+ * handle by current stack. In most user applications this function is not called directly.\r
+ * Also this function can be used by users who are selectively modifying the USB device stack's\r
+ * standard handlers through callback interface exposed by the stack.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param cfg When 1 - Set EP0 in IN transfer mode\r
+ * 0 - Set EP0 in OUT transfer mode\r
+ * @return Nothing.\r
+ */\r
+ void (*DirCtrlEP)(USBD_HANDLE_T hUsb, uint32_t dir);\r
+\r
+ /** @fn void EnableEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to enable selected USB endpoint.\r
+ *\r
+ * This function enables interrupts on selected endpoint.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param EPNum Endpoint number as per USB specification.\r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * @return Nothing.\r
+ */\r
+ void (*EnableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** @fn void DisableEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to disable selected USB endpoint.\r
+ *\r
+ * This function disables interrupts on selected endpoint.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param EPNum Endpoint number as per USB specification.\r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * @return Nothing.\r
+ */\r
+ void (*DisableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** @fn void ResetEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to reset selected USB endpoint.\r
+ *\r
+ * This function flushes the endpoint buffers and resets data toggle logic.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param EPNum Endpoint number as per USB specification.\r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * @return Nothing.\r
+ */\r
+ void (*ResetEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** @fn void SetStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to STALL selected USB endpoint.\r
+ *\r
+ * Generates STALL signalling for requested endpoint.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param EPNum Endpoint number as per USB specification.\r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * @return Nothing.\r
+ */\r
+ void (*SetStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** @fn void ClrStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to clear STALL state for the requested endpoint.\r
+ *\r
+ * This function clears STALL state for the requested endpoint.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param EPNum Endpoint number as per USB specification.\r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * @return Nothing.\r
+ */\r
+ void (*ClrStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** @fn ErrorCode_t SetTestMode(USBD_HANDLE_T hUsb, uint8_t mode)\r
+ * Function to set high speed USB device controller in requested test mode.\r
+ *\r
+ * USB-IF requires the high speed device to be put in various test modes\r
+ * for electrical testing. This USB device stack calls this function whenever\r
+ * it receives USB_REQUEST_CLEAR_FEATURE request for USB_FEATURE_TEST_MODE.\r
+ * Users can put the device in test mode by directly calling this function.\r
+ * Returns ERR_USBD_INVALID_REQ when device controller is full-speed only.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param mode Test mode defined in USB 2.0 electrical testing specification.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK(0) - On success\r
+ * @retval ERR_USBD_INVALID_REQ(0x00040001) - Invalid test mode or\r
+ * Device controller is full-speed only.\r
+ */\r
+ ErrorCode_t (*SetTestMode)(USBD_HANDLE_T hUsb, uint8_t mode);\r
+\r
+ /** @fn uint32_t ReadEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData)\r
+ * Function to read data received on the requested endpoint.\r
+ *\r
+ * This function is called by USB stack and the application layer to read the data\r
+ * received on the requested endpoint.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param EPNum Endpoint number as per USB specification.\r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \param[in,out] pData Pointer to the data buffer where data is to be copied.\r
+ * @return Returns the number of bytes copied to the buffer.\r
+ */\r
+ uint32_t (*ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData);\r
+\r
+ /** @fn uint32_t ReadReqEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len)\r
+ * Function to queue read request on the specified endpoint.\r
+ *\r
+ * This function is called by USB stack and the application layer to queue a read request\r
+ * on the specified endpoint.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param EPNum Endpoint number as per USB specification.\r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \param[in,out] pData Pointer to the data buffer where data is to be copied. This buffer\r
+ * address should be accessible by USB DMA master.\r
+ * @param len Length of the buffer passed.\r
+ * @return Returns the length of the requested buffer.\r
+ */\r
+ uint32_t (*ReadReqEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len);\r
+\r
+ /** @fn uint32_t ReadSetupPkt(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t *pData)\r
+ * Function to read setup packet data received on the requested endpoint.\r
+ *\r
+ * This function is called by USB stack and the application layer to read setup packet data\r
+ * received on the requested endpoint.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param EPNum Endpoint number as per USB specification.\r
+ * ie. An EP0_IN is represented by 0x80 number.\r
+ * \param[in,out] pData Pointer to the data buffer where data is to be copied.\r
+ * @return Returns the number of bytes copied to the buffer.\r
+ */\r
+ uint32_t (*ReadSetupPkt)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t *pData);\r
+\r
+ /** @fn uint32_t WriteEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt)\r
+ * Function to write data to be sent on the requested endpoint.\r
+ *\r
+ * This function is called by USB stack and the application layer to send data\r
+ * on the requested endpoint.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param EPNum Endpoint number as per USB specification.\r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * @param pData Pointer to the data buffer from where data is to be copied.\r
+ * @param cnt Number of bytes to write.\r
+ * @return Returns the number of bytes written.\r
+ */\r
+ uint32_t (*WriteEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt);\r
+\r
+ /** @fn void WakeUp(USBD_HANDLE_T hUsb)\r
+ * Function to generate resume signaling on bus for remote host wakeup.\r
+ *\r
+ * This function is called by application layer to remotely wakeup host controller \r
+ * when system is in suspend state. Application should indicate this remote wakeup\r
+ * capability by setting USB_CONFIG_REMOTE_WAKEUP in bmAttributes of Configuration \r
+ * Descriptor. Also this routine will generate resume signalling only if host\r
+ * enables USB_FEATURE_REMOTE_WAKEUP by sending SET_FEATURE request before suspending\r
+ * the bus.\r
+ * \r
+ * @param hUsb Handle to the USB device stack. \r
+ * @return Nothing.\r
+ */\r
+ void (*WakeUp)(USBD_HANDLE_T hUsb);\r
+\r
+ /** @fn void EnableEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to enable/disable selected USB event.\r
+ *\r
+ * This function enables interrupts on selected endpoint.\r
+ * \r
+ * @param hUsb Handle to the USB device stack. \r
+ * @param EPNum Endpoint number corresponding to the eventas per USB specification. \r
+ * ie. An EP1_IN is represented by 0x81 number. For device events \r
+ * set this param to 0x0. \r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @param enable 1 - enable event, 0 - disable event.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK(0) - On success\r
+ * @retval ERR_USBD_INVALID_REQ(0x00040001) - Invalid event type.\r
+ */\r
+ ErrorCode_t (*EnableEvent)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, \r
+ uint32_t enable);\r
+\r
+} USBD_HW_API_T;\r
+\r
+\r
+\r
+\r
+#endif /* __USBHW_H__ */\r
--- /dev/null
+/*\r
+ * @brief USB ROM based MSC Class driver functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+#include "../../Device.h"\r
+#include "../../Endpoint.h"\r
+\r
+#if defined(USB_DEVICE_ROM_DRIVER)\r
+\r
+/* FIXME Abstract & make this size configurable */\r
+//#define ROMDRIVER_MSC_MEM_SIZE 0x1000\r
+//uint8_t usb_RomDriver_MSC_buffer[ROMDRIVER_MSC_MEM_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+\r
+void UsbdMsc_Init(void)\r
+{\r
+ USBD_MSC_INIT_PARAM_T msc_param =\r
+ {\r
+ /* mass storage paramas */\r
+ .InquiryStr = (uint8_t*) CALLBACK_UsbdMsc_Register_InquiryData(),\r
+\r
+ .BlockCount = CALLBACK_UsbdMsc_Register_BlockCount(),\r
+ .BlockSize = CALLBACK_UsbdMsc_Register_BlockSize(),\r
+ .MemorySize = CALLBACK_UsbdMsc_Register_MemorySize(),\r
+\r
+ .intf_desc = (uint8_t*) CALLBACK_UsbdMsc_Register_InterfaceDescriptor(),\r
+\r
+ /* user defined functions */\r
+ .MSC_Write = (void(*)(uint32_t,uint8_t**,uint32_t))CALLBACK_UsbdMsc_Register_MSCWrite(),\r
+ .MSC_Read = (void(*)(uint32_t,uint8_t**,uint32_t))CALLBACK_UsbdMsc_Register_MSCRead(),\r
+ .MSC_Verify = (ErrorCode_t(*)(uint32_t,uint8_t*,uint32_t))CALLBACK_UsbdMsc_Register_MSCVerify(),\r
+ .MSC_GetWriteBuf = (void(*)(uint32_t,uint8_t**,uint32_t))CALLBACK_UsbdMsc_Register_MSCGetWriteBuf(),\r
+\r
+ .mem_base = (uint32_t) usb_RomDriver_MSC_buffer,\r
+ .mem_size = ROMDRIVER_MSC_MEM_SIZE\r
+ };\r
+ USBD_API->msc->init(UsbHandle, &msc_param);\r
+}\r
+\r
+#endif /* USB_DEVICE_ROM_DRIVER */\r
+\r
+#endif /* USB_CAN_BE_DEVICE */\r
--- /dev/null
+/*\r
+ * @brief Definition of USB ROM based MSC class descriptors and their bit defines\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __MSC_H__\r
+#define __MSC_H__\r
+\r
+#include "usbd.h"\r
+\r
+ /*\r
+ * Definition of MSC class descriptors and their bit defines.\r
+ *\r
+ */\r
+/* MSC Subclass Codes */\r
+#define MSC_SUBCLASS_RBC 0x01\r
+#define MSC_SUBCLASS_SFF8020I_MMC2 0x02\r
+#define MSC_SUBCLASS_QIC157 0x03\r
+#define MSC_SUBCLASS_UFI 0x04\r
+#define MSC_SUBCLASS_SFF8070I 0x05\r
+#define MSC_SUBCLASS_SCSI 0x06\r
+\r
+/* MSC Protocol Codes */\r
+#define MSC_PROTOCOL_CBI_INT 0x00\r
+#define MSC_PROTOCOL_CBI_NOINT 0x01\r
+#define MSC_PROTOCOL_BULK_ONLY 0x50\r
+\r
+\r
+/* MSC Request Codes */\r
+#define MSC_REQUEST_RESET 0xFF\r
+#define MSC_REQUEST_GET_MAX_LUN 0xFE\r
+\r
+\r
+/* MSC Bulk-only Stage */\r
+#define MSC_BS_CBW 0 /* Command Block Wrapper */\r
+#define MSC_BS_DATA_OUT 1 /* Data Out Phase */\r
+#define MSC_BS_DATA_IN 2 /* Data In Phase */\r
+#define MSC_BS_DATA_IN_LAST 3 /* Data In Last Phase */\r
+#define MSC_BS_DATA_IN_LAST_STALL 4 /* Data In Last Phase with Stall */\r
+#define MSC_BS_CSW 5 /* Command Status Wrapper */\r
+#define MSC_BS_ERROR 6 /* Error */\r
+\r
+\r
+/* Bulk-only Command Block Wrapper */\r
+PRE_PACK struct POST_PACK _MSC_CBW\r
+{\r
+ uint32_t dSignature;\r
+ uint32_t dTag;\r
+ uint32_t dDataLength;\r
+ uint8_t bmFlags;\r
+ uint8_t bLUN;\r
+ uint8_t bCBLength;\r
+ uint8_t CB[16];\r
+} ;\r
+typedef struct _MSC_CBW MSC_CBW;\r
+\r
+/* Bulk-only Command Status Wrapper */\r
+PRE_PACK struct POST_PACK _MSC_CSW\r
+{\r
+ uint32_t dSignature;\r
+ uint32_t dTag;\r
+ uint32_t dDataResidue;\r
+ uint8_t bStatus;\r
+} ;\r
+typedef struct _MSC_CSW MSC_CSW;\r
+\r
+#define MSC_CBW_Signature 0x43425355\r
+#define MSC_CSW_Signature 0x53425355\r
+\r
+\r
+/* CSW Status Definitions */\r
+#define CSW_CMD_PASSED 0x00\r
+#define CSW_CMD_FAILED 0x01\r
+#define CSW_PHASE_ERROR 0x02\r
+\r
+\r
+/* SCSI Commands */\r
+#define SCSI_TEST_UNIT_READY 0x00\r
+#define SCSI_REQUEST_SENSE 0x03\r
+#define SCSI_FORMAT_UNIT 0x04\r
+#define SCSI_INQUIRY 0x12\r
+#define SCSI_MODE_SELECT6 0x15\r
+#define SCSI_MODE_SENSE6 0x1A\r
+#define SCSI_START_STOP_UNIT 0x1B\r
+#define SCSI_MEDIA_REMOVAL 0x1E\r
+#define SCSI_READ_FORMAT_CAPACITIES 0x23\r
+#define SCSI_READ_CAPACITY 0x25\r
+#define SCSI_READ10 0x28\r
+#define SCSI_WRITE10 0x2A\r
+#define SCSI_VERIFY10 0x2F\r
+#define SCSI_READ12 0xA8\r
+#define SCSI_WRITE12 0xAA\r
+#define SCSI_MODE_SELECT10 0x55\r
+#define SCSI_MODE_SENSE10 0x5A\r
+\r
+uint32_t CALLBACK_UsbdMsc_Register_InquiryData(void);\r
+uint32_t CALLBACK_UsbdMsc_Register_BlockCount(void);\r
+uint32_t CALLBACK_UsbdMsc_Register_BlockSize(void);\r
+uint32_t CALLBACK_UsbdMsc_Register_MemorySize(void);\r
+uint32_t CALLBACK_UsbdMsc_Register_InterfaceDescriptor(void);\r
+uint32_t CALLBACK_UsbdMsc_Register_MSCWrite(void);\r
+uint32_t CALLBACK_UsbdMsc_Register_MSCRead(void);\r
+uint32_t CALLBACK_UsbdMsc_Register_MSCVerify(void);\r
+uint32_t CALLBACK_UsbdMsc_Register_MSCGetWriteBuf(void);\r
+\r
+#endif /* __MSC_H__ */\r
--- /dev/null
+/*\r
+ * @brief Definition of functions exported by ROM based MSC function driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "usbd_msc.h"\r
+#include "usbd_core.h"\r
+\r
+#ifndef __MSCUSER_H__\r
+#define __MSCUSER_H__\r
+\r
+\r
+/** @ingroup Group_USBD_Class\r
+ * @defgroup USBD_MSC Mass Storage Class (MSC) Function Driver\r
+ * @section Sec_MSCModDescription Module Description\r
+ * MSC Class Function Driver module. This module contains an internal implementation of the USB MSC Class.\r
+ * User applications can use this class driver instead of implementing the MSC class manually\r
+ * via the low-level USBD_HW and USBD_Core APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB MSC Class.\r
+ */\r
+\r
+/** @brief Mass Storage class function driver initilization parameter data structure.\r
+ * @ingroup USBD_MSC\r
+ *\r
+ * @details This data structure is used to pass initialization parameters to the\r
+ * Mass Storage class function driver's init function.\r
+ *\r
+ */\r
+typedef struct USBD_MSC_INIT_PARAM\r
+{\r
+ /* memory allocation params */\r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. @note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 4 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use.\r
+ @note The \em mem_size should be greater than the size\r
+ returned by USBD_MSC_API::GetMemSize() routine.*/\r
+ /* mass storage paramas */\r
+ uint8_t* InquiryStr; /**< Pointer to the 28 character string. This string is\r
+ sent in response to the SCSI Inquiry command. @note The data\r
+ pointed by the pointer should be of global scope.\r
+ */\r
+ uint32_t BlockCount; /**< Number of blocks present in the mass storage device */\r
+ uint32_t BlockSize; /**< Block size in number of bytes */\r
+ uint32_t MemorySize; /**< Memory size in number of bytes */\r
+ /** Pointer to the interface descriptor within the descriptor\r
+ * array (\em high_speed_desc) passed to Init() through @ref USB_CORE_DESCS_T\r
+ * structure. The stack assumes both HS and FS use same BULK endpoints.\r
+ */\r
+ uint8_t* intf_desc;\r
+ /* user defined functions */\r
+\r
+ /**\r
+ * MSC Write callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a write command.\r
+ *\r
+ * @param offset Destination start address.\r
+ * @param src Pointer to a pointer to the source of data. Pointer-to-pointer\r
+ * is used to implement zero-copy buffers.\r
+ * @param length Number of bytes to be written.\r
+ * @return Nothing.\r
+ *\r
+ */\r
+ void (*MSC_Write)( uint32_t offset, uint8_t** src, uint32_t length);\r
+ /**\r
+ * MSC Read callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a read command.\r
+ *\r
+ * @param offset Source start address.\r
+ * @param dst Pointer to a pointer to the source of data. The MSC function drivers\r
+ * implemented in stack are written with zero-copy model. Meaning the stack doesn't make an\r
+ * extra copy of buffer before writing/reading data from USB hardware FIFO. Hence the\r
+ * parameter is pointer to a pointer containing address buffer (<em>uint8_t** dst</em>).\r
+ * So that the user application can update the buffer pointer instead of copying data to\r
+ * address pointed by the parameter. /note The updated buffer address should be accessable\r
+ * by USB DMA master. If user doesn't want to use zero-copy model, then the user should copy\r
+ * data to the address pointed by the passed buffer pointer parameter and shouldn't change\r
+ * the address value.\r
+ * @param length Number of bytes to be read.\r
+ * @return Nothing.\r
+ *\r
+ */\r
+ void (*MSC_Read)( uint32_t offset, uint8_t** dst, uint32_t length);\r
+ /**\r
+ * MSC Verify callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a verify command. The callback function should compare the buffer\r
+ * with the destination memory at the requested offset and\r
+ *\r
+ * @param offset Destination start address.\r
+ * @param buf Buffer containing the data sent by the host.\r
+ * @param length Number of bytes to verify.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK If data in the buffer matches the data at destination\r
+ * @retval ERR_FAILED Atleast one byte is different.\r
+ *\r
+ */\r
+ ErrorCode_t (*MSC_Verify)( uint32_t offset, uint8_t buf[], uint32_t length);\r
+ /**\r
+ * Optional callback function to optimize MSC_Write buffer transfer.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends SCSI_WRITE10/SCSI_WRITE12 command. The callback function should\r
+ * update the \em buff_adr pointer so that the stack transfers the data directly\r
+ * to the target buffer. /note The updated buffer address should be accessable\r
+ * by USB DMA master. If user doesn't want to use zero-copy model, then the user\r
+ * should not update the buffer pointer.\r
+ *\r
+ * @param offset Destination start address.\r
+ * \param[in,out] buf Buffer containing the data sent by the host.\r
+ * @param length Number of bytes to write.\r
+ * @return Nothing.\r
+ *\r
+ */\r
+ void (*MSC_GetWriteBuf)( uint32_t offset, uint8_t** buff_adr, uint32_t length);\r
+\r
+ /**\r
+ * Optional user overridable function to replace the default MSC class handler.\r
+ *\r
+ * The application software could override the default EP0 class handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_MSC_API::Init().\r
+ * \n\r
+ * @note\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param data Pointer to the data which will be passed when callback function is called by the stack.\r
+ * @param event Type of endpoint event. See @ref USBD_EVENT_T for more details.\r
+ * @return The call back should returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success.\r
+ * @retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * @retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*MSC_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+} USBD_MSC_INIT_PARAM_T;\r
+\r
+/** @brief MSC class API functions structure.\r
+ * @ingroup USBD_MSC\r
+ *\r
+ * This module exposes functions which interact directly with USB device controller hardware.\r
+ *\r
+ */\r
+typedef struct USBD_MSC_API\r
+{\r
+ /** @fn uint32_t GetMemSize(USBD_MSC_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the MSC function driver module.\r
+ *\r
+ * This function is called by application layer before calling pUsbApi->msc->Init(), to allocate memory used\r
+ * by MSC function driver module. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller.\r
+ * @note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * @param param Structure containing HID function driver module initialization parameters.\r
+ * @return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_MSC_INIT_PARAM_T* param);\r
+\r
+ /** @fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param)\r
+ * Function to initialize MSC function driver module.\r
+ *\r
+ * This fuction is called by application layer to initialize MSC function driver module.\r
+ *\r
+ * @param hUsb Handle to the USB device stack.\r
+ * @param param Structure containing HID function driver module initialization parameters.\r
+ * @return Returns @ref ErrorCode_t type to indicate success or error condition.\r
+ * @retval LPC_OK On success\r
+ * @retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte\r
+ * aligned or smaller than required.\r
+ * @retval ERR_API_INVALID_PARAM2 Either MSC_Write() or MSC_Read() or\r
+ * MSC_Verify() callbacks are not defined.\r
+ * @retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed.\r
+ * @retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed.\r
+ */\r
+ ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param);\r
+\r
+} USBD_MSC_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+/** @cond ADVANCED_API */\r
+\r
+typedef struct _MSC_CTRL_T\r
+{\r
+ /* If it's a USB HS, the max packet is 512, if it's USB FS,\r
+ the max packet is 64. Use 512 for both HS and FS. */\r
+ /*ALIGNED(4)*/ uint8_t BulkBuf[512]; /* Bulk In/Out Buffer */\r
+ /*ALIGNED(4)*/MSC_CBW CBW; /* Command Block Wrapper */\r
+ /*ALIGNED(4)*/MSC_CSW CSW; /* Command Status Wrapper */\r
+\r
+ USB_CORE_CTRL_T* pUsbCtrl;\r
+\r
+ uint32_t Offset; /* R/W Offset */\r
+ uint32_t Length; /* R/W Length */\r
+ uint32_t BulkLen; /* Bulk In/Out Length */\r
+ uint8_t* rx_buf;\r
+\r
+ uint8_t BulkStage; /* Bulk Stage */\r
+ uint8_t if_num; /* interface number */\r
+ uint8_t epin_num; /* BULK IN endpoint number */\r
+ uint8_t epout_num; /* BULK OUT endpoint number */\r
+ uint32_t MemOK; /* Memory OK */\r
+\r
+ uint8_t* InquiryStr;\r
+ uint32_t BlockCount;\r
+ uint32_t BlockSize;\r
+ uint32_t MemorySize;\r
+ /* user defined functions */\r
+ void (*MSC_Write)( uint32_t offset, uint8_t** src, uint32_t length);\r
+ void (*MSC_Read)( uint32_t offset, uint8_t** dst, uint32_t length);\r
+ ErrorCode_t (*MSC_Verify)( uint32_t offset, uint8_t src[], uint32_t length);\r
+ /* optional call back for MSC_Write optimization */\r
+ void (*MSC_GetWriteBuf)( uint32_t offset, uint8_t** buff_adr, uint32_t length);\r
+\r
+\r
+}USB_MSC_CTRL_T;\r
+\r
+\r
+/** @endcond */\r
+\r
+\r
+#endif /* __MSCUSER_H__ */\r
--- /dev/null
+/*\r
+ * @brief USB ROM based core driver functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+#include "../../Device.h"\r
+#include "../../Endpoint.h"\r
+\r
+#if defined(USB_DEVICE_ROM_DRIVER)\r
+USBD_HANDLE_T UsbHandle;\r
+/* FIXME Abstract & make this size configurable */\r
+//#define ROMDRIVER_MEM_SIZE 0x1000\r
+//uint8_t usb_RomDriver_buffer[ROMDRIVER_MEM_SIZE] ATTR_ALIGNED(2048) __BSS(USBRAM_SECTION);\r
+\r
+ErrorCode_t UsbdRom_Event_Stub (USBD_HANDLE_T hUsb);\r
+PRAGMA_WEAK(USB_Interface_Event,UsbdRom_Event_Stub)\r
+ErrorCode_t USB_Interface_Event (USBD_HANDLE_T hUsb) ATTR_WEAK ATTR_ALIAS(UsbdRom_Event_Stub);\r
+PRAGMA_WEAK(USB_Configure_Event,USB_Configure_Event_Stub)\r
+ErrorCode_t USB_Configure_Event (USBD_HANDLE_T hUsb) ATTR_WEAK ATTR_ALIAS(USB_Configure_Event_Stub);\r
+ErrorCode_t USB_Configure_Event_Stub (USBD_HANDLE_T hUsb)\r
+{\r
+ USB_CORE_CTRL_T* pCtrl = (USB_CORE_CTRL_T*)hUsb;\r
+ uint8_t epnum = CALLBACK_UsbdRom_Register_ConfigureEndpoint();\r
+\r
+ if((pCtrl->config_value)&&(epnum!=0))\r
+ {\r
+ USBD_API->hw->WriteEP(hUsb, (epnum + 0x80), usb_RomDriver_buffer, 1);//TODO: what is this for?\r
+ }\r
+ return LPC_OK;\r
+}\r
+void UsbdRom_Init(uint8_t corenum)\r
+{\r
+ ErrorCode_t ret;\r
+\r
+ USBD_API_INIT_PARAM_T usb_param =\r
+ {\r
+ .usb_reg_base = ROMDRIVER_USB0_BASE,\r
+ .max_num_ep = ENDPOINT_TOTAL_ENDPOINTS(corenum),\r
+ .mem_base = (uint32_t) usb_RomDriver_buffer,\r
+ .mem_size = ROMDRIVER_MEM_SIZE,\r
+ .USB_Configure_Event = USB_Configure_Event\r
+ };\r
+ USB_CORE_DESCS_T DeviceDes = {NULL};\r
+\r
+ if(corenum)\r
+ usb_param.usb_reg_base = ROMDRIVER_USB1_BASE;\r
+\r
+ /* add custom Interface Event */\r
+ if(USB_Interface_Event != UsbdRom_Event_Stub)\r
+ {\r
+ usb_param.USB_Interface_Event = USB_Interface_Event;\r
+ }\r
+ DeviceDes.device_desc = (uint8_t*)CALLBACK_UsbdRom_Register_DeviceDescriptor();\r
+ DeviceDes.high_speed_desc = (uint8_t*)CALLBACK_UsbdRom_Register_ConfigurationDescriptor();\r
+ DeviceDes.full_speed_desc = (uint8_t*)CALLBACK_UsbdRom_Register_ConfigurationDescriptor();\r
+ DeviceDes.string_desc = (uint8_t*)CALLBACK_UsbdRom_Register_StringDescriptor();\r
+ DeviceDes.device_qualifier = (uint8_t*)CALLBACK_UsbdRom_Register_DeviceQualifierDescriptor();\r
+\r
+ ret = USBD_API->hw->Init(&UsbHandle, &DeviceDes, &usb_param);\r
+\r
+ // trap failed initialization\r
+ while(ret != LPC_OK);\r
+}\r
+\r
+void UsbdRom_IrqHandler(void)\r
+{\r
+ USBD_API->hw->ISR(UsbHandle);\r
+}\r
+\r
+ErrorCode_t UsbdRom_Event_Stub (USBD_HANDLE_T hUsb)\r
+{\r
+ return LPC_OK;\r
+}\r
+#endif /* USB_DEVICE_ROM_DRIVER */\r
+\r
+#endif /* USB_CAN_BE_DEVICE */\r
--- /dev/null
+/*\r
+ * @brief Definition of functions exported by ROM based USB device stack\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __MW_USBD_ROM_API_H\r
+#define __MW_USBD_ROM_API_H\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "usbd_hw.h"\r
+#include "usbd_core.h"\r
+#include "usbd_mscuser.h"\r
+#include "usbd_dfuuser.h"\r
+#include "usbd_hiduser.h"\r
+#include "usbd_cdcuser.h"\r
+\r
+/** @brief Main USBD API functions structure.\r
+ * @ingroup Group_USBD\r
+ *\r
+ * This structure contains pointer to various USB Device stack's sub-module\r
+ * function tables. This structure is used as main entry point to access\r
+ * various methods (grouped in sub-modules) exposed by ROM based USB device\r
+ * stack.\r
+ *\r
+ */\r
+typedef struct USBD_API\r
+{\r
+ const USBD_HW_API_T* hw; /**< Pointer to function table which exposes functions\r
+ which interact directly with USB device stack's core\r
+ layer.*/\r
+ const USBD_CORE_API_T* core; /**< Pointer to function table which exposes functions\r
+ which interact directly with USB device controller\r
+ hardware.*/\r
+ const USBD_MSC_API_T* msc; /**< Pointer to function table which exposes functions\r
+ provided by MSC function driver module.\r
+ */\r
+ const USBD_DFU_API_T* dfu; /**< Pointer to function table which exposes functions\r
+ provided by DFU function driver module.\r
+ */\r
+ const USBD_HID_API_T* hid; /**< Pointer to function table which exposes functions\r
+ provided by HID function driver module.\r
+ */\r
+ const USBD_CDC_API_T* cdc; /**< Pointer to function table which exposes functions \r
+ provided by CDC-ACM function driver module.\r
+ */\r
+ const uint32_t* reserved6; /**< Reserved for future function driver module.\r
+ */\r
+ const uint32_t version; /**< Version identifier of USB ROM stack. The version is\r
+ defined as 0x0CHDMhCC where each nibble represnts version \r
+ number of the corresponding component.\r
+ CC - 7:0 - 8bit core version number\r
+ h - 11:8 - 4bit hardware interface version number\r
+ M - 15:12 - 4bit MSC class module version number\r
+ D - 19:16 - 4bit DFU class module version number\r
+ H - 23:20 - 4bit HID class module version number\r
+ C - 27:24 - 4bit CDC class module version number\r
+ H - 31:28 - 4bit reserved \r
+ */\r
+} USBD_API_T;\r
+\r
+\r
+#define USBD_API (((USBD_API_T*)(ROM_USBD_PTR)))\r
+\r
+extern USBD_HANDLE_T UsbHandle;\r
+\r
+/* USBD core functions */\r
+void UsbdRom_Init(uint8_t corenum);\r
+void UsbdRom_IrqHandler(void);\r
+/* USBD MSC functions */\r
+void UsbdMsc_Init(void);\r
+/* USBD HID functions */\r
+void UsbdHid_Init(void);\r
+/* USBD CDC functions */\r
+void UsbdCdc_Init(void);\r
+#endif /*__MW_USBD_ROM_API_H*/\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Device definitions for the LPC microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+\r
+#include "Device.h"\r
+\r
+void USB_Device_SendRemoteWakeup(void)\r
+{\r
+ // if (!(USB_Options & USB_OPT_MANUAL_PLL))\r
+ // {\r
+ // USB_PLL_On();\r
+ // while (!(USB_PLL_IsReady()));\r
+ // }\r
+ //\r
+ // USB_CLK_Unfreeze();\r
+ //\r
+ // UDCON |= (1 << RMWKUP);\r
+ // while (UDCON & (1 << RMWKUP));\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief Common USB Device definitions for all architectures\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_Device Device Management\r
+ * @brief USB Device management definitions for USB device mode.\r
+ *\r
+ * USB Device mode related definitions common to all architectures. This module contains definitions which\r
+ * are used when the USB controller is initialized in device mode.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __USBDEVICE_H__\r
+#define __USBDEVICE_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h" \r
+ #include "StdDescriptors.h"\r
+ #include "USBInterrupt.h"\r
+ #include "Endpoint.h"\r
+ \r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Enums: */\r
+ /** Enum for the various states of the USB Device state machine. Only some states are\r
+ * implemented in the nxpUSBlib library - other states are left to the user to implement.\r
+ *\r
+ * For information on each possible USB device state, refer to the USB 2.0 specification.\r
+ *\r
+ * \see @ref USB_DeviceState, which stores the current device state machine state.\r
+ */\r
+ enum USB_Device_States_t\r
+ {\r
+ DEVICE_STATE_Unattached = 0, /**< Internally implemented by the library. This state indicates\r
+ * that the device is not currently connected to a host.\r
+ */\r
+ DEVICE_STATE_Powered = 1, /**< Internally implemented by the library. This state indicates\r
+ * that the device is connected to a host, but enumeration has not\r
+ * yet begun.\r
+ */\r
+ DEVICE_STATE_Default = 2, /**< Internally implemented by the library. This state indicates\r
+ * that the device's USB bus has been reset by the host and it is\r
+ * now waiting for the host to begin the enumeration process.\r
+ */\r
+ DEVICE_STATE_Addressed = 3, /**< Internally implemented by the library. This state indicates\r
+ * that the device has been addressed by the USB Host, but is not\r
+ * yet configured.\r
+ */\r
+ DEVICE_STATE_Configured = 4, /**< May be implemented by the user project. This state indicates\r
+ * that the device has been enumerated by the host and is ready\r
+ * for USB communications to begin.\r
+ */\r
+ DEVICE_STATE_Suspended = 5, /**< May be implemented by the user project. This state indicates\r
+ * that the USB bus has been suspended by the host, and the device\r
+ * should power down to a minimal power level until the bus is\r
+ * resumed.\r
+ */\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /** @brief Function to retrieve a given descriptor's size and memory location from the given descriptor type value,\r
+ * index and language ID. This function MUST be overridden in the user application (added with full, identical\r
+ * prototype and name so that the library can call it to retrieve descriptor data.\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param wValue : The type of the descriptor to retrieve in the upper byte, and the index in the\r
+ * lower byte (when more than one descriptor of the given type exists, such as the\r
+ * case of string descriptors). The type may be one of the standard types defined\r
+ * in the DescriptorTypes_t enum, or may be a class-specific descriptor type value.\r
+ * @param wIndex : The language ID of the string to return if the \c wValue type indicates\r
+ * @ref DTYPE_String, otherwise zero for standard descriptors, or as defined in a\r
+ * class-specific standards.\r
+ * @param DescriptorAddress : Pointer to the descriptor in memory. This should be set by the routine to\r
+ * the address of the descriptor.\r
+ * @param MemoryAddressSpace : A value from the @ref USB_DescriptorMemorySpaces_t enum to indicate the memory\r
+ * space in which the descriptor is stored. This parameter does not exist when one\r
+ * of the \c USE_*_DESCRIPTORS compile time options is used, or on architectures which\r
+ * use a unified address space.\r
+ *\r
+ * @note By default, the library expects all descriptors to be located in flash memory via the \c PROGMEM attribute.\r
+ * If descriptors should be located in RAM or EEPROM instead (to speed up access in the case of RAM, or to\r
+ * allow the descriptors to be changed dynamically at runtime) either the \c USE_RAM_DESCRIPTORS or the\r
+ * \c USE_EEPROM_DESCRIPTORS tokens may be defined in the project makefile and passed to the compiler by the -D\r
+ * switch.\r
+ *\r
+ * @return Size in bytes of the descriptor if it exists, zero or @ref NO_DESCRIPTOR otherwise.\r
+ */\r
+ uint16_t CALLBACK_USB_GetDescriptor(uint8_t corenum, const uint16_t wValue,\r
+ const uint8_t wIndex,\r
+ const void** const DescriptorAddress\r
+ #if (defined(ARCH_HAS_MULTI_ADDRESS_SPACE) || defined(__DOXYGEN__)) && \\r
+ !(defined(USE_FLASH_DESCRIPTORS) || defined(USE_EEPROM_DESCRIPTORS) || defined(USE_RAM_DESCRIPTORS))\r
+ , uint8_t* MemoryAddressSpace\r
+ #endif\r
+ ) ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(4);\r
+\r
+ #if defined(__LPC18XX__) || defined(__LPC43XX__)\r
+ #include "DCD/LPC18XX/Device_LPC18xx.h"\r
+ #elif defined(__LPC175X_6X__) || defined(__LPC177X_8X__) || defined(__LPC407X_8X__)\r
+ #include "DCD/LPC17XX/Device_LPC17xx.h"\r
+ #elif defined(__LPC11U1X__) || defined(__LPC11U2X_3X__) || defined(__LPC1347__)\r
+ #include "DCD/LPC11UXX/Device_LPC11Uxx.h"\r
+ #endif\r
+ \r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB device standard request management\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+\r
+#define __INCLUDE_FROM_DEVICESTDREQ_C\r
+#include "DeviceStandardReq.h"\r
+\r
+uint8_t USB_Device_ConfigurationNumber;\r
+\r
+#if !defined(NO_DEVICE_SELF_POWER)\r
+bool USB_Device_CurrentlySelfPowered;\r
+#endif\r
+\r
+#if !defined(NO_DEVICE_REMOTE_WAKEUP)\r
+bool USB_Device_RemoteWakeupEnabled;\r
+#endif\r
+\r
+void USB_Device_ProcessControlRequest(uint8_t corenum)\r
+{\r
+// USB_ControlRequest.bmRequestType = Endpoint_Read_8();\r
+// USB_ControlRequest.bRequest = Endpoint_Read_8();\r
+// USB_ControlRequest.wValue = Endpoint_Read_16_LE();\r
+// USB_ControlRequest.wIndex = Endpoint_Read_16_LE();\r
+// USB_ControlRequest.wLength = Endpoint_Read_16_LE();\r
+\r
+ Endpoint_GetSetupPackage(corenum, (uint8_t*) &USB_ControlRequest);\r
+\r
+ EVENT_USB_Device_ControlRequest();\r
+\r
+ if (Endpoint_IsSETUPReceived(corenum))\r
+ {\r
+ uint8_t bmRequestType = USB_ControlRequest.bmRequestType;\r
+\r
+ switch (USB_ControlRequest.bRequest)\r
+ {\r
+ case REQ_GetStatus:\r
+ if ((bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE)) ||\r
+ (bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_ENDPOINT)))\r
+ {\r
+ USB_Device_GetStatus(corenum);\r
+ }\r
+\r
+ break;\r
+ case REQ_ClearFeature:\r
+ case REQ_SetFeature:\r
+ if ((bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_DEVICE)) ||\r
+ (bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_ENDPOINT)))\r
+ {\r
+ USB_Device_ClearSetFeature(corenum);\r
+ }\r
+\r
+ break;\r
+ case REQ_SetAddress:\r
+ if (bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_DEVICE))\r
+ USB_Device_SetAddress(corenum);\r
+\r
+ break;\r
+ case REQ_GetDescriptor:\r
+ if ((bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE)) ||\r
+ (bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_INTERFACE)))\r
+ {\r
+ USB_Device_GetDescriptor(corenum);\r
+ }\r
+\r
+ break;\r
+ case REQ_GetConfiguration:\r
+ if (bmRequestType == (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE))\r
+ USB_Device_GetConfiguration(corenum);\r
+\r
+ break;\r
+ case REQ_SetConfiguration:\r
+ if (bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_DEVICE))\r
+ USB_Device_SetConfiguration(corenum);\r
+\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (Endpoint_IsSETUPReceived(corenum))\r
+ {\r
+ Endpoint_ClearSETUP(corenum);\r
+ Endpoint_StallTransaction(corenum);\r
+ }\r
+}\r
+\r
+static void USB_Device_SetAddress(uint8_t corenum)\r
+{\r
+ uint8_t DeviceAddress = (USB_ControlRequest.wValue & 0x7F);\r
+ uint_reg_t CurrentGlobalInt = GetGlobalInterruptMask();\r
+ GlobalInterruptDisable();\r
+ \r
+ Endpoint_ClearSETUP(corenum);\r
+\r
+ Endpoint_ClearStatusStage(corenum);\r
+\r
+ while (!(Endpoint_IsINReady(corenum)));\r
+\r
+ USB_Device_SetDeviceAddress(corenum, DeviceAddress);\r
+ USB_DeviceState[corenum] = (DeviceAddress) ? DEVICE_STATE_Addressed : DEVICE_STATE_Default;\r
+ \r
+ SetGlobalInterruptMask(CurrentGlobalInt);\r
+}\r
+\r
+static void USB_Device_SetConfiguration(uint8_t corenum)\r
+{\r
+ #if defined(FIXED_NUM_CONFIGURATIONS)\r
+ if ((uint8_t)USB_ControlRequest.wValue > FIXED_NUM_CONFIGURATIONS)\r
+ return;\r
+ #else\r
+ USB_Descriptor_Device_t* DevDescriptorPtr;\r
+\r
+ #if defined(ARCH_HAS_MULTI_ADDRESS_SPACE)\r
+ #if defined(USE_FLASH_DESCRIPTORS)\r
+ #define MemoryAddressSpace MEMSPACE_FLASH\r
+ #elif defined(USE_EEPROM_DESCRIPTORS)\r
+ #define MemoryAddressSpace MEMSPACE_EEPROM\r
+ #elif defined(USE_RAM_DESCRIPTORS)\r
+ #define MemoryAddressSpace MEMSPACE_SRAM\r
+ #else\r
+ uint8_t MemoryAddressSpace;\r
+ #endif\r
+ #endif\r
+ \r
+ if (CALLBACK_USB_GetDescriptor(corenum, (DTYPE_Device << 8), 0, (void*)&DevDescriptorPtr\r
+ #if defined(ARCH_HAS_MULTI_ADDRESS_SPACE) && \\r
+ !(defined(USE_FLASH_DESCRIPTORS) || defined(USE_EEPROM_DESCRIPTORS) || defined(USE_RAM_DESCRIPTORS))\r
+ , &MemoryAddressSpace\r
+ #endif\r
+ ) == NO_DESCRIPTOR)\r
+ {\r
+ return;\r
+ }\r
+\r
+ #if defined(ARCH_HAS_MULTI_ADDRESS_SPACE)\r
+ if (MemoryAddressSpace == MEMSPACE_FLASH)\r
+ {\r
+ if (((uint8_t)USB_ControlRequest.wValue > pgm_read_byte(&DevDescriptorPtr->NumberOfConfigurations)))\r
+ return;\r
+ }\r
+ else if (MemoryAddressSpace == MEMSPACE_EEPROM)\r
+ {\r
+ if (((uint8_t)USB_ControlRequest.wValue > eeprom_read_byte(&DevDescriptorPtr->NumberOfConfigurations)))\r
+ return;\r
+ }\r
+ else\r
+ {\r
+ if ((uint8_t)USB_ControlRequest.wValue > DevDescriptorPtr->NumberOfConfigurations)\r
+ return;\r
+ }\r
+ #else\r
+ if ((uint8_t)USB_ControlRequest.wValue > DevDescriptorPtr->NumberOfConfigurations)\r
+ return; \r
+ #endif\r
+ #endif\r
+\r
+ Endpoint_ClearSETUP(corenum);\r
+\r
+ USB_Device_ConfigurationNumber = (uint8_t)USB_ControlRequest.wValue;\r
+\r
+ Endpoint_ClearStatusStage(corenum);\r
+\r
+ if (USB_Device_ConfigurationNumber)\r
+ USB_DeviceState[corenum] = DEVICE_STATE_Configured;\r
+ else\r
+ USB_DeviceState[corenum] = (USB_Device_IsAddressSet()) ? DEVICE_STATE_Configured : DEVICE_STATE_Powered;\r
+\r
+ EVENT_USB_Device_ConfigurationChanged();\r
+}\r
+\r
+static void USB_Device_GetConfiguration(uint8_t corenum)\r
+{\r
+ Endpoint_ClearSETUP(corenum);\r
+\r
+ Endpoint_Write_8(corenum, USB_Device_ConfigurationNumber);\r
+ Endpoint_ClearIN(corenum);\r
+\r
+ Endpoint_ClearStatusStage(corenum);\r
+}\r
+\r
+#if !defined(NO_INTERNAL_SERIAL) && (USE_INTERNAL_SERIAL != NO_DESCRIPTOR)\r
+static void USB_Device_GetInternalSerialDescriptor(uint8_t corenum)\r
+{\r
+ struct\r
+ {\r
+ USB_Descriptor_Header_t Header;\r
+ uint16_t UnicodeString[INTERNAL_SERIAL_LENGTH_BITS / 4];\r
+ } SignatureDescriptor;\r
+\r
+ SignatureDescriptor.Header.Type = DTYPE_String;\r
+ SignatureDescriptor.Header.Size = USB_STRING_LEN(INTERNAL_SERIAL_LENGTH_BITS / 4);\r
+ \r
+ USB_Device_GetSerialString(SignatureDescriptor.UnicodeString);\r
+\r
+ Endpoint_ClearSETUP(corenum);\r
+\r
+ Endpoint_Write_Control_Stream_LE(corenum, &SignatureDescriptor, sizeof(SignatureDescriptor));\r
+ Endpoint_ClearOUT(corenum);\r
+}\r
+#endif\r
+\r
+static void USB_Device_GetDescriptor(uint8_t corenum)\r
+{\r
+ const void* DescriptorPointer;\r
+ uint16_t DescriptorSize;\r
+\r
+ #if defined(ARCH_HAS_MULTI_ADDRESS_SPACE) && \\r
+ !(defined(USE_FLASH_DESCRIPTORS) || defined(USE_EEPROM_DESCRIPTORS) || defined(USE_RAM_DESCRIPTORS))\r
+ uint8_t DescriptorAddressSpace;\r
+ #endif\r
+\r
+ #if !defined(NO_INTERNAL_SERIAL) && (USE_INTERNAL_SERIAL != NO_DESCRIPTOR)\r
+ if (USB_ControlRequest.wValue == ((DTYPE_String << 8) | USE_INTERNAL_SERIAL))\r
+ {\r
+ USB_Device_GetInternalSerialDescriptor(corenum);\r
+ return;\r
+ }\r
+ #endif\r
+\r
+ if ((DescriptorSize = CALLBACK_USB_GetDescriptor(corenum, USB_ControlRequest.wValue, USB_ControlRequest.wIndex,\r
+ &DescriptorPointer\r
+ #if defined(ARCH_HAS_MULTI_ADDRESS_SPACE) && \\r
+ !(defined(USE_FLASH_DESCRIPTORS) || defined(USE_EEPROM_DESCRIPTORS) || defined(USE_RAM_DESCRIPTORS))\r
+ , &DescriptorAddressSpace\r
+ #endif\r
+ )) == NO_DESCRIPTOR)\r
+ {\r
+ return;\r
+ }\r
+\r
+ Endpoint_ClearSETUP(corenum);\r
+\r
+ #if defined(USE_RAM_DESCRIPTORS) || !defined(ARCH_HAS_MULTI_ADDRESS_SPACE)\r
+ Endpoint_Write_Control_Stream_LE(corenum, DescriptorPointer, DescriptorSize);\r
+ #elif defined(USE_EEPROM_DESCRIPTORS)\r
+ Endpoint_Write_Control_EStream_LE(DescriptorPointer, DescriptorSize);\r
+ #elif defined(USE_FLASH_DESCRIPTORS)\r
+ Endpoint_Write_Control_PStream_LE(DescriptorPointer, DescriptorSize);\r
+ #else\r
+ if (DescriptorAddressSpace == MEMSPACE_FLASH)\r
+ Endpoint_Write_Control_PStream_LE(DescriptorPointer, DescriptorSize);\r
+ else if (DescriptorAddressSpace == MEMSPACE_EEPROM)\r
+ Endpoint_Write_Control_EStream_LE(DescriptorPointer, DescriptorSize);\r
+ else\r
+ Endpoint_Write_Control_Stream_LE(corenum, DescriptorPointer, DescriptorSize);\r
+ #endif\r
+\r
+ Endpoint_ClearOUT(corenum);\r
+}\r
+\r
+static void USB_Device_GetStatus(uint8_t corenum)\r
+{\r
+ uint8_t CurrentStatus = 0;\r
+\r
+ switch (USB_ControlRequest.bmRequestType)\r
+ {\r
+ #if !defined(NO_DEVICE_SELF_POWER) || !defined(NO_DEVICE_REMOTE_WAKEUP)\r
+ case (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE):\r
+ #if !defined(NO_DEVICE_SELF_POWER)\r
+ if (USB_Device_CurrentlySelfPowered)\r
+ CurrentStatus |= FEATURE_SELFPOWERED_ENABLED;\r
+ #endif\r
+\r
+ #if !defined(NO_DEVICE_REMOTE_WAKEUP)\r
+ if (USB_Device_RemoteWakeupEnabled)\r
+ CurrentStatus |= FEATURE_REMOTE_WAKEUP_ENABLED;\r
+ #endif\r
+ break;\r
+ #endif\r
+ #if !defined(CONTROL_ONLY_DEVICE)\r
+ case (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_ENDPOINT):\r
+ Endpoint_SelectEndpoint(corenum, (uint8_t)USB_ControlRequest.wIndex & ENDPOINT_EPNUM_MASK);\r
+\r
+ CurrentStatus = Endpoint_IsStalled(corenum);\r
+\r
+ Endpoint_SelectEndpoint(corenum, ENDPOINT_CONTROLEP);\r
+\r
+ break;\r
+ #endif\r
+ default:\r
+ return;\r
+ }\r
+\r
+ Endpoint_ClearSETUP(corenum);\r
+\r
+ Endpoint_Write_16_LE(corenum, CurrentStatus);\r
+ Endpoint_ClearIN(corenum);\r
+\r
+ Endpoint_ClearStatusStage(corenum);\r
+}\r
+\r
+static void USB_Device_ClearSetFeature(uint8_t corenum)\r
+{\r
+ switch (USB_ControlRequest.bmRequestType & CONTROL_REQTYPE_RECIPIENT)\r
+ {\r
+ #if !defined(NO_DEVICE_REMOTE_WAKEUP)\r
+ case REQREC_DEVICE:\r
+ if ((uint8_t)USB_ControlRequest.wValue == FEATURE_SEL_DeviceRemoteWakeup)\r
+ USB_Device_RemoteWakeupEnabled = (USB_ControlRequest.bRequest == REQ_SetFeature);\r
+ else\r
+ return;\r
+\r
+ break;\r
+ #endif\r
+ #if !defined(CONTROL_ONLY_DEVICE)\r
+ case REQREC_ENDPOINT:\r
+ if ((uint8_t)USB_ControlRequest.wValue == FEATURE_SEL_EndpointHalt)\r
+ {\r
+ uint8_t EndpointIndex = ((uint8_t)USB_ControlRequest.wIndex & ENDPOINT_EPNUM_MASK);\r
+\r
+ if (EndpointIndex == ENDPOINT_CONTROLEP)\r
+ return;\r
+\r
+ Endpoint_SelectEndpoint(corenum, EndpointIndex);\r
+\r
+ if (Endpoint_IsEnabled())\r
+ {\r
+ if (USB_ControlRequest.bRequest == REQ_SetFeature)\r
+ {\r
+ Endpoint_StallTransaction(corenum);\r
+ }\r
+ else\r
+ {\r
+ Endpoint_ClearStall(corenum);\r
+ Endpoint_ResetEndpoint(EndpointIndex);\r
+ Endpoint_ResetDataToggle(corenum);\r
+ }\r
+ }\r
+ }\r
+\r
+ break;\r
+ #endif\r
+ default:\r
+ return;\r
+ }\r
+\r
+ Endpoint_SelectEndpoint(corenum, ENDPOINT_CONTROLEP);\r
+\r
+ Endpoint_ClearSETUP(corenum);\r
+\r
+ Endpoint_ClearStatusStage(corenum);\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief USB device standard request management\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+ \r
+#ifndef __DEVICESTDREQ_H__\r
+#define __DEVICESTDREQ_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h" \r
+ #include "StdDescriptors.h"\r
+ #include "Events.h"\r
+ #include "StdRequestType.h"\r
+ #include "USBTask.h"\r
+ #include "USBController.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Enums: */\r
+ #if defined(ARCH_HAS_MULTI_ADDRESS_SPACE) || defined(__DOXYGEN__)\r
+ /** Enum for the possible descriptor memory spaces, for the \c MemoryAddressSpace parameter of the\r
+ * @ref CALLBACK_USB_GetDescriptor() function. This can be used when none of the \c USE_*_DESCRIPTORS\r
+ * compile time options are used, to indicate in which memory space the descriptor is stored.\r
+ *\r
+ * @ingroup Group_Device\r
+ */\r
+ enum USB_DescriptorMemorySpaces_t\r
+ {\r
+ #if defined(ARCH_HAS_FLASH_ADDRESS_SPACE) || defined(__DOXYGEN__)\r
+ MEMSPACE_FLASH = 0, /**< Indicates the requested descriptor is located in FLASH memory. */\r
+ #endif\r
+ #if defined(ARCH_HAS_EEPROM_ADDRESS_SPACE) || defined(__DOXYGEN__)\r
+ MEMSPACE_EEPROM = 1, /**< Indicates the requested descriptor is located in EEPROM memory. */\r
+ #endif\r
+ MEMSPACE_RAM = 2, /**< Indicates the requested descriptor is located in RAM memory. */\r
+ };\r
+ #endif\r
+\r
+ /* Global Variables: */\r
+ /** Indicates the currently set configuration number of the device. USB devices may have several\r
+ * different configurations which the host can select between; this indicates the currently selected\r
+ * value, or 0 if no configuration has been selected.\r
+ *\r
+ * @note This variable should be treated as read-only in the user application, and never manually\r
+ * changed in value.\r
+ *\r
+ * @ingroup Group_Device\r
+ */\r
+ extern uint8_t USB_Device_ConfigurationNumber;\r
+\r
+ #if !defined(NO_DEVICE_REMOTE_WAKEUP)\r
+ /** Indicates if the host is currently allowing the device to issue remote wakeup events. If this\r
+ * flag is cleared, the device should not issue remote wakeup events to the host.\r
+ *\r
+ * @note This variable should be treated as read-only in the user application, and never manually\r
+ * changed in value.\r
+ * \n\n\r
+ *\r
+ * @note To reduce FLASH usage of the compiled applications where Remote Wakeup is not supported,\r
+ * this global and the underlying management code can be disabled by defining the\r
+ * \c NO_DEVICE_REMOTE_WAKEUP token in the project makefile and passing it to the compiler via\r
+ * the -D switch.\r
+ *\r
+ * @ingroup Group_Device\r
+ */\r
+ extern bool USB_Device_RemoteWakeupEnabled;\r
+ #endif\r
+\r
+ #if !defined(NO_DEVICE_SELF_POWER)\r
+ /** Indicates if the device is currently being powered by its own power supply, rather than being\r
+ * powered by the host's USB supply. This flag should remain cleared if the device does not\r
+ * support self powered mode, as indicated in the device descriptors.\r
+ *\r
+ * @ingroup Group_Device\r
+ */\r
+ extern bool USB_Device_CurrentlySelfPowered;\r
+ #endif\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ #if defined(USE_RAM_DESCRIPTORS) && defined(USE_EEPROM_DESCRIPTORS)\r
+ #error USE_RAM_DESCRIPTORS and USE_EEPROM_DESCRIPTORS are mutually exclusive.\r
+ #elif defined(USE_RAM_DESCRIPTORS) && defined(USE_FLASH_DESCRIPTORS)\r
+ #error USE_RAM_DESCRIPTORS and USE_FLASH_DESCRIPTORS are mutually exclusive.\r
+ #elif defined(USE_FLASH_DESCRIPTORS) && defined(USE_EEPROM_DESCRIPTORS)\r
+ #error USE_FLASH_DESCRIPTORS and USE_EEPROM_DESCRIPTORS are mutually exclusive.\r
+ #elif defined(USE_FLASH_DESCRIPTORS) && defined(USE_EEPROM_DESCRIPTORS) && defined(USE_RAM_DESCRIPTORS)\r
+ #error Only one of the USE_*_DESCRIPTORS modes should be selected.\r
+ #endif\r
+\r
+ /* Function Prototypes: */\r
+ void USB_Device_ProcessControlRequest(uint8_t corenum);\r
+\r
+ #if defined(__INCLUDE_FROM_DEVICESTDREQ_C)\r
+ static void USB_Device_SetAddress(uint8_t corenum);\r
+ static void USB_Device_SetConfiguration(uint8_t corenum);\r
+ static void USB_Device_GetConfiguration(uint8_t corenum);\r
+ static void USB_Device_GetDescriptor(uint8_t corenum);\r
+ static void USB_Device_GetStatus(uint8_t corenum);\r
+ static void USB_Device_ClearSetFeature(uint8_t corenum);\r
+\r
+ #if !defined(NO_INTERNAL_SERIAL) && (USE_INTERNAL_SERIAL != NO_DESCRIPTOR)\r
+ static void USB_Device_GetInternalSerialDescriptor(uint8_t corenum);\r
+ #endif\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief Endpoint declarations and functions for the LPC microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+#include "Endpoint.h"\r
+\r
+#if !defined(FIXED_CONTROL_ENDPOINT_SIZE)\r
+uint8_t USB_Device_ControlEndpointSize = ENDPOINT_CONTROLEP_DEFAULT_SIZE;\r
+#endif\r
+\r
+PRAGMA_ALIGN_64\r
+uint8_t usb_data_buffer[MAX_USB_CORE][USB_DATA_BUFFER_TEM_LENGTH] ATTR_ALIGNED(64) __BSS(USBRAM_SECTION);/* TODO 11uxx require buffer is 64 byte aligned */\r
+\r
+volatile int32_t usb_data_buffer_size[MAX_USB_CORE];\r
+volatile uint32_t usb_data_buffer_index[MAX_USB_CORE];\r
+uint8_t usb_data_buffer_OUT[MAX_USB_CORE][USB_DATA_BUFFER_TEM_LENGTH] ATTR_ALIGNED(64) __BSS(USBRAM_SECTION);/* TODO 11uxx require buffer is 64 byte aligned */\r
+volatile uint32_t usb_data_buffer_OUT_size[MAX_USB_CORE];\r
+volatile uint32_t usb_data_buffer_OUT_index[MAX_USB_CORE];\r
+uint8_t usb_data_buffer_IN[MAX_USB_CORE][USB_DATA_BUFFER_TEM_LENGTH] ATTR_ALIGNED(64) __BSS(USBRAM_SECTION); /* TODO 11uxx require buffer is 64 byte aligned */\r
+volatile uint32_t usb_data_buffer_IN_index[MAX_USB_CORE];\r
+\r
+uint8_t endpointselected[MAX_USB_CORE];\r
+uint8_t endpointhandle0[ENDPOINT_TOTAL_ENDPOINTS0];\r
+uint8_t endpointhandle1[ENDPOINT_TOTAL_ENDPOINTS1];\r
+\r
+bool Endpoint_ConfigureEndpoint_Prv(uint8_t corenum,\r
+ const uint8_t Number,\r
+ const uint8_t UECFG0XData,\r
+ const uint8_t UECFG1XData)\r
+{\r
+#if defined(CONTROL_ONLY_DEVICE) || defined(ORDERED_EP_CONFIG)\r
+ Endpoint_SelectEndpoint(corenum, Number);\r
+ Endpoint_EnableEndpoint();\r
+\r
+ // UECFG1X = 0;\r
+ // UECFG0X = UECFG0XData;\r
+ // UECFG1X = UECFG1XData;\r
+\r
+ return Endpoint_IsConfigured();\r
+#else\r
+ for (uint8_t EPNum = Number; EPNum < ENDPOINT_TOTAL_ENDPOINTS(corenum); EPNum++) {\r
+ // uint8_t UECFG0XTemp;\r
+ // uint8_t UECFG1XTemp;\r
+ // uint8_t UEIENXTemp;\r
+\r
+ Endpoint_SelectEndpoint(corenum, EPNum);\r
+\r
+ if (EPNum == Number) {\r
+ // UECFG0XTemp = UECFG0XData;\r
+ // UECFG1XTemp = UECFG1XData;\r
+ // UEIENXTemp = 0;\r
+ }\r
+ else {\r
+ // UECFG0XTemp = UECFG0X;\r
+ // UECFG1XTemp = UECFG1X;\r
+ // UEIENXTemp = UEIENX;\r
+ }\r
+\r
+ // if (!(UECFG1XTemp & (1 << ALLOC)))\r
+ // continue;\r
+\r
+ Endpoint_DisableEndpoint();\r
+ // UECFG1X &= ~(1 << ALLOC);\r
+\r
+ Endpoint_EnableEndpoint();\r
+ // UECFG0X = UECFG0XTemp;\r
+ // UECFG1X = UECFG1XTemp;\r
+ // UEIENX = UEIENXTemp;\r
+\r
+ if (!(Endpoint_IsConfigured())) {\r
+ return false;\r
+ }\r
+ }\r
+\r
+ Endpoint_SelectEndpoint(corenum, Number);\r
+ return true;\r
+#endif\r
+}\r
+\r
+void Endpoint_ClearEndpoints(uint8_t corenum)\r
+{\r
+ // UEINT = 0;\r
+\r
+ for (uint8_t EPNum = 0; EPNum < ENDPOINT_TOTAL_ENDPOINTS(corenum); EPNum++) {\r
+ Endpoint_SelectEndpoint(corenum, EPNum);\r
+ // UEIENX = 0;\r
+ // UEINTX = 0;\r
+ // UECFG1X = 0;\r
+ Endpoint_DisableEndpoint();\r
+ }\r
+}\r
+\r
+void Endpoint_ClearStatusStage(uint8_t corenum)\r
+{\r
+ if (USB_ControlRequest.bmRequestType & REQDIR_DEVICETOHOST) {\r
+ Endpoint_ClearOUT(corenum);\r
+ }\r
+ else {\r
+ Endpoint_ClearIN(corenum);\r
+ }\r
+}\r
+\r
+#if !defined(CONTROL_ONLY_DEVICE)\r
+uint8_t Endpoint_WaitUntilReady(void)\r
+{\r
+ return ENDPOINT_READYWAIT_NoError;\r
+}\r
+\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief USB Endpoint definitions for all architectures\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_EndpointManagement\r
+ * @defgroup Group_EndpointRW Endpoint Data Reading and Writing\r
+ * @brief Endpoint data read/write definitions.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing from and to endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointRW\r
+ * @defgroup Group_EndpointPrimitiveRW Read/Write of Primitive Data Types\r
+ * @brief Endpoint data primitive read/write definitions.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing of primitive data types\r
+ * from and to endpoints.\r
+ */\r
+\r
+/** @ingroup Group_EndpointManagement\r
+ * @defgroup Group_EndpointPacketManagement Endpoint Packet Management\r
+ * @brief USB Endpoint package management definitions.\r
+ *\r
+ * Functions, macros, variables, enums and types related to packet management of endpoints.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_EndpointManagement Endpoint Management\r
+ * @brief Endpoint management definitions.\r
+ *\r
+ * Functions, macros and enums related to endpoint management when in USB Device mode. This\r
+ * module contains the endpoint management macros, as well as endpoint interrupt and data\r
+ * send/receive functions for various data types.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __ENDPOINT_H__\r
+#define __ENDPOINT_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h"\r
+ #include "USBTask.h"\r
+ #include "USBInterrupt.h"\r
+ \r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** Endpoint number mask, for masking against endpoint addresses to retrieve the endpoint's\r
+ * numerical address in the device.\r
+ */\r
+ #define ENDPOINT_EPNUM_MASK 0x0F\r
+\r
+ /** Endpoint address for the default control endpoint, which always resides in address 0. This is\r
+ * defined for convenience to give more readable code when used with the endpoint macros.\r
+ */\r
+ #define ENDPOINT_CONTROLEP 0\r
+ \r
+ #if defined(__LPC18XX__) || defined(__LPC43XX__)\r
+ #include "DCD/LPC18XX/Endpoint_LPC18xx.h"\r
+ #elif defined(__LPC175X_6X__) || defined(__LPC177X_8X__) || defined(__LPC407X_8X__)\r
+ #include "DCD/LPC17XX/Endpoint_LPC17xx.h"\r
+ #elif defined(__LPC11U1X__) || defined(__LPC11U2X_3X__) || defined(__LPC1347__)\r
+ #include "DCD/LPC11UXX/Endpoint_LPC11Uxx.h"\r
+ #endif\r
+ \r
+\r
+ \r
+ /** Mask for the bank mode selection for the @ref Endpoint_ConfigureEndpoint() macro. This indicates\r
+ * that the endpoint should have one single bank, which requires less USB FIFO memory but results\r
+ * in slower transfers as only one USB device (the LPC or the host) can access the endpoint's\r
+ * bank at the one time.\r
+ */\r
+ #define ENDPOINT_BANK_SINGLE (0 << 1)\r
+ \r
+ /** Mask for the bank mode selection for the @ref Endpoint_ConfigureEndpoint() macro. This indicates\r
+ * that the endpoint should have two banks, which requires more USB FIFO memory but results\r
+ * in faster transfers as one USB device (the LPC or the host) can access one bank while the other\r
+ * accesses the second bank.\r
+ */\r
+ #define ENDPOINT_BANK_DOUBLE (1 << 1)\r
+ \r
+ #if (!defined(FIXED_CONTROL_ENDPOINT_SIZE) || defined(__DOXYGEN__))\r
+ /** Default size of the default control endpoint's bank, until altered by the control endpoint bank size\r
+ * value in the device descriptor. Not available if the \c FIXED_CONTROL_ENDPOINT_SIZE token is defined.\r
+ */\r
+ #define ENDPOINT_CONTROLEP_DEFAULT_SIZE 64\r
+ #endif\r
+ \r
+ /** Retrieves the maximum bank size in bytes of a given endpoint.\r
+ *\r
+ * @note This macro will only work correctly on endpoint indexes that are compile-time constants\r
+ * defined by the preprocessor.\r
+ *\r
+ * @param EPIndex Endpoint number, a value between 0 and (\ref ENDPOINT_TOTAL_ENDPOINTS - 1)\r
+ */\r
+ #define ENDPOINT_MAX_SIZE(EPIndex) 512\r
+ \r
+ #if !defined(CONTROL_ONLY_DEVICE) || defined(__DOXYGEN__)\r
+ /** Total number of endpoints (including the default control endpoint at address 0) which may\r
+ * be used in the device. Different USB LPC models support different amounts of endpoints,\r
+ * this value reflects the maximum number of endpoints for the currently selected LPC model.\r
+ */\r
+ #define ENDPOINT_TOTAL_ENDPOINTS0 ENDPOINT_DETAILS_MAXEP0\r
+ #define ENDPOINT_TOTAL_ENDPOINTS1 ENDPOINT_DETAILS_MAXEP1\r
+ #define ENDPOINT_TOTAL_ENDPOINTS(corenum) ((corenum) ? ENDPOINT_DETAILS_MAXEP1 : ENDPOINT_DETAILS_MAXEP0)\r
+ #else\r
+ #define ENDPOINT_TOTAL_ENDPOINTS 1\r
+ #endif\r
+ \r
+ /* Enums: */\r
+ /** Enum for the possible error return codes of the @ref Endpoint_WaitUntilReady() function.\r
+ *\r
+ * @ingroup Group_EndpointRW\r
+ */\r
+ enum Endpoint_WaitUntilReady_ErrorCodes_t {\r
+ ENDPOINT_READYWAIT_NoError = 0, /**< Endpoint is ready for next packet, no error. */\r
+ ENDPOINT_READYWAIT_EndpointStalled = 1, /**< The endpoint was stalled during the stream\r
+ * transfer by the host or device.\r
+ */\r
+ ENDPOINT_READYWAIT_DeviceDisconnected = 2, /**< Device was disconnected from the host while\r
+ * waiting for the endpoint to become ready.\r
+ */\r
+ ENDPOINT_READYWAIT_BusSuspended = 3, /**< The USB bus has been suspended by the host and\r
+ * no USB endpoint traffic can occur until the bus\r
+ * has resumed.\r
+ */\r
+ ENDPOINT_READYWAIT_Timeout = 4, /**< The host failed to accept or send the next packet\r
+ * within the software timeout period set by the\r
+ * @ref USB_STREAM_TIMEOUT_MS macro.\r
+ */\r
+ };\r
+ \r
+ /**\r
+ * @brief Get the endpoint address of the currently selected endpoint. This is typically used to save\r
+ * the currently selected endpoint number so that it can be restored after another endpoint has\r
+ * been manipulated.\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Index of the currently selected endpoint\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline uint8_t Endpoint_GetCurrentEndpoint(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Endpoint_GetCurrentEndpoint(uint8_t corenum)\r
+ {\r
+ return endpointselected[corenum];\r
+ }\r
+ \r
+ /**\r
+ * @brief Selects the given endpoint number. If the address from the device descriptors is used, the\r
+ * value should be masked with the @ref ENDPOINT_EPNUM_MASK constant to extract only the endpoint\r
+ * number (and discarding the endpoint direction bit).\r
+ *\r
+ * Any endpoint operations which do not require the endpoint number to be indicated will operate on\r
+ * the currently selected endpoint.\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param EndpointNumber : Endpoint number to select\r
+ * @return Nothing\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void Endpoint_SelectEndpoint(uint8_t corenum, const uint8_t EndpointNumber) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Endpoint_SelectEndpoint(uint8_t corenum, const uint8_t EndpointNumber)\r
+ {\r
+ endpointselected[corenum] = EndpointNumber;\r
+ // usb_data_buffer_index = 0;\r
+ }\r
+ \r
+ /**\r
+ * @brief Reads one byte from the currently selected endpoint's bank, for OUT direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Next byte in the currently selected endpoint's FIFO buffer\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline uint8_t Endpoint_Read_8(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Endpoint_Read_8(uint8_t corenum)\r
+ {\r
+ uint8_t tem;\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ tem = usb_data_buffer[corenum][usb_data_buffer_index[corenum]];\r
+ usb_data_buffer_index[corenum]++;\r
+ usb_data_buffer_size[corenum]--;\r
+ }\r
+ else {\r
+ tem = usb_data_buffer_OUT[corenum][usb_data_buffer_OUT_index[corenum]];\r
+ usb_data_buffer_OUT_index[corenum]++;\r
+ usb_data_buffer_OUT_size[corenum]--;\r
+ }\r
+ return tem;\r
+ }\r
+ \r
+ /**\r
+ * @brief Determines the currently selected endpoint's direction\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return The currently selected endpoint's direction, as a \c ENDPOINT_DIR_* mask.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline uint8_t Endpoint_GetEndpointDirection(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Endpoint_GetEndpointDirection(uint8_t corenum)\r
+ {\r
+ return (endpointhandle(corenum)[endpointselected[corenum]] % 2) ? ENDPOINT_DIR_IN : ENDPOINT_DIR_OUT;\r
+ }\r
+ \r
+ /**\r
+ * @brief Determines if the currently selected endpoint may be read from (if data is waiting in the endpoint\r
+ * bank and the endpoint is an OUT direction, or if the bank is not yet full if the endpoint is an IN\r
+ * direction). This function will return false if an error has occurred in the endpoint, if the endpoint\r
+ * is an OUT direction and no packet (or an empty packet) has been received, or if the endpoint is an IN\r
+ * direction and the endpoint bank is full.\r
+ *\r
+ * @ingroup Group_EndpointPacketManagement\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Boolean \c true if the currently selected endpoint may be read from or written to, depending\r
+ * on its direction.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline bool Endpoint_IsReadWriteAllowed(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Endpoint_IsReadWriteAllowed(uint8_t corenum)\r
+ {\r
+ return (Endpoint_GetEndpointDirection(corenum) == ENDPOINT_DIR_OUT) ? Endpoint_IsOUTReceived(corenum) : Endpoint_IsINReady(corenum);\r
+ }\r
+ \r
+ /**\r
+ * @brief Writes one byte to the currently selected endpoint's bank, for IN direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param Data : Data to write into the the currently selected endpoint's FIFO buffer\r
+ * @return Nothing\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void Endpoint_Write_8(uint8_t corenum, const uint8_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Endpoint_Write_8(uint8_t corenum, const uint8_t Data)\r
+ {\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ usb_data_buffer[corenum][usb_data_buffer_index[corenum]] = Data;\r
+ usb_data_buffer_index[corenum]++;\r
+ }\r
+ else {\r
+ usb_data_buffer_IN[corenum][usb_data_buffer_IN_index[corenum]] = Data;\r
+ usb_data_buffer_IN_index[corenum]++;\r
+ }\r
+ }\r
+ \r
+ /**\r
+ * @brief Discards one byte from the currently selected endpoint's bank, for OUT direction endpoints.\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void Endpoint_Discard_8(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Endpoint_Discard_8(uint8_t corenum)\r
+ {\r
+ volatile uint8_t dummy;\r
+ dummy = Endpoint_Read_8(corenum);\r
+ dummy = dummy;\r
+ }\r
+ \r
+ /**\r
+ * @brief Reads two bytes from the currently selected endpoint's bank in little endian format, for OUT\r
+ * direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Next two bytes in the currently selected endpoint's FIFO buffer.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline uint16_t Endpoint_Read_16_LE(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint16_t Endpoint_Read_16_LE(uint8_t corenum)\r
+ {\r
+ uint16_t tem = 0;\r
+ uint8_t tem1, tem2;\r
+\r
+ tem1 = Endpoint_Read_8(corenum);\r
+ tem2 = Endpoint_Read_8(corenum);\r
+ tem = (tem2 << 8) | tem1;\r
+ return tem;\r
+ }\r
+ \r
+ /**\r
+ * @brief Reads two bytes from the currently selected endpoint's bank in big endian format, for OUT\r
+ * direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Next two bytes in the currently selected endpoint's FIFO buffer.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline uint16_t Endpoint_Read_16_BE(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint16_t Endpoint_Read_16_BE(uint8_t corenum)\r
+ {\r
+ uint16_t tem = 0;\r
+ uint8_t tem1, tem2;\r
+\r
+ tem1 = Endpoint_Read_8(corenum);\r
+ tem2 = Endpoint_Read_8(corenum);\r
+ tem = (tem1 << 8) | tem2;\r
+ return tem;\r
+ }\r
+ \r
+ /**\r
+ * @brief Writes two bytes to the currently selected endpoint's bank in little endian format, for IN\r
+ * direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param Data : Data to write to the currently selected endpoint's FIFO buffer\r
+ * @return Nothing\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void Endpoint_Write_16_LE(uint8_t corenum, const uint16_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Endpoint_Write_16_LE(uint8_t corenum, const uint16_t Data)\r
+ {\r
+ Endpoint_Write_8(corenum, Data & 0xFF);\r
+ Endpoint_Write_8(corenum, (Data >> 8) & 0xFF);\r
+ }\r
+ \r
+ /**\r
+ * @brief Writes two bytes to the currently selected endpoint's bank in big endian format, for IN\r
+ * direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param Data : Data to write to the currently selected endpoint's FIFO buffer\r
+ * @return Nothing\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void Endpoint_Write_16_BE(uint8_t corenum, const uint16_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Endpoint_Write_16_BE(uint8_t corenum, const uint16_t Data)\r
+ {\r
+ Endpoint_Write_8(corenum, (Data >> 8) & 0xFF);\r
+ Endpoint_Write_8(corenum, Data & 0xFF);\r
+ }\r
+ \r
+ /**\r
+ * @brief Discards two bytes from the currently selected endpoint's bank, for OUT direction endpoints.\r
+ * @return Nothing\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void Endpoint_Discard_16(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Endpoint_Discard_16(uint8_t corenum)\r
+ {\r
+ uint8_t tem;\r
+ tem = Endpoint_Read_8(corenum);\r
+ tem = Endpoint_Read_8(corenum);\r
+ tem = tem;\r
+ }\r
+ \r
+ /**\r
+ * @brief Reads four bytes from the currently selected endpoint's bank in little endian format, for OUT\r
+ * direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Next four bytes in the currently selected endpoint's FIFO buffer.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline uint32_t Endpoint_Read_32_LE(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint32_t Endpoint_Read_32_LE(uint8_t corenum)\r
+ {\r
+ uint32_t tem = 0;\r
+ uint8_t tem1, tem2, tem3, tem4;\r
+\r
+ tem1 = Endpoint_Read_8(corenum);\r
+ tem2 = Endpoint_Read_8(corenum);\r
+ tem3 = Endpoint_Read_8(corenum);\r
+ tem4 = Endpoint_Read_8(corenum);\r
+ tem = (tem4 << 24) | (tem3 << 16) | (tem2 << 8) | tem1;\r
+ return tem;\r
+ }\r
+ \r
+ /**\r
+ * @brief Reads four bytes from the currently selected endpoint's bank in big endian format, for OUT\r
+ * direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Next four bytes in the currently selected endpoint's FIFO buffer.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline uint32_t Endpoint_Read_32_BE(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint32_t Endpoint_Read_32_BE(uint8_t corenum)\r
+ {\r
+ uint32_t tem = 0;\r
+ uint8_t tem1, tem2, tem3, tem4;\r
+\r
+ tem1 = Endpoint_Read_8(corenum);\r
+ tem2 = Endpoint_Read_8(corenum);\r
+ tem3 = Endpoint_Read_8(corenum);\r
+ tem4 = Endpoint_Read_8(corenum);\r
+ tem = (tem1 << 24) | (tem2 << 16) | (tem3 << 8) | tem4;\r
+ return tem;\r
+ }\r
+ \r
+ /**\r
+ * @brief Writes four bytes to the currently selected endpoint's bank in little endian format, for IN\r
+ * direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param Data : Data to write to the currently selected endpoint's FIFO buffer\r
+ * @return Nothing\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void Endpoint_Write_32_LE(uint8_t corenum, const uint32_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Endpoint_Write_32_LE(uint8_t corenum, const uint32_t Data)\r
+ {\r
+ Endpoint_Write_8(corenum, Data & 0xFF);\r
+ Endpoint_Write_8(corenum, (Data >> 8) & 0xFF);\r
+ Endpoint_Write_8(corenum, (Data >> 16) & 0xFF);\r
+ Endpoint_Write_8(corenum, (Data >> 24) & 0xFF);\r
+ }\r
+ \r
+ /**\r
+ * @brief Writes four bytes to the currently selected endpoint's bank in big endian format, for IN\r
+ * direction endpoints.\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @param Data : Data to write to the currently selected endpoint's FIFO buffer\r
+ * @return Nothing\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void Endpoint_Write_32_BE(uint8_t corenum, const uint32_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Endpoint_Write_32_BE(uint8_t corenum, const uint32_t Data)\r
+ {\r
+ Endpoint_Write_8(corenum, (Data >> 24) & 0xFF);\r
+ Endpoint_Write_8(corenum, (Data >> 16) & 0xFF);\r
+ Endpoint_Write_8(corenum, (Data >> 8) & 0xFF);\r
+ Endpoint_Write_8(corenum, Data & 0xFF);\r
+ }\r
+ \r
+ /**\r
+ * @brief Discards four bytes from the currently selected endpoint's bank, for OUT direction endpoints.\r
+ * @return Nothing\r
+ *\r
+ * @ingroup Group_EndpointPrimitiveRW\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void Endpoint_Discard_32(uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Endpoint_Discard_32(uint8_t corenum)\r
+ {\r
+ uint8_t tem;\r
+ tem = Endpoint_Read_8(corenum);\r
+ tem = Endpoint_Read_8(corenum);\r
+ tem = Endpoint_Read_8(corenum);\r
+ tem = Endpoint_Read_8(corenum);\r
+ tem = tem;\r
+ }\r
+ \r
+ void Endpoint_GetSetupPackage(uint8_t corenum, uint8_t *pData);\r
+\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Endpoint data stream transmission and reception management for the LPC microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+\r
+#include "EndpointStream.h"\r
+\r
+#if !defined(CONTROL_ONLY_DEVICE)\r
+uint8_t Endpoint_Discard_Stream(uint8_t corenum,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ uint32_t i;\r
+ for (i = 0; i < Length; i++)\r
+ Endpoint_Discard_8(corenum);\r
+ return ENDPOINT_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Endpoint_Null_Stream(uint8_t corenum,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ uint32_t i;\r
+\r
+ while ( !Endpoint_IsINReady(corenum) ) { /*-- Wait until ready --*/\r
+ Delay_MS(2);\r
+ }\r
+ for (i = 0; i < Length; i++)\r
+ Endpoint_Write_8(corenum, 0);\r
+ return ENDPOINT_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Endpoint_Write_Stream_LE(uint8_t corenum,\r
+ const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ uint16_t i;\r
+\r
+ while ( !Endpoint_IsINReady(corenum) ) { /*-- Wait until ready --*/\r
+ Delay_MS(2);\r
+ }\r
+ for (i = 0; i < Length; i++)\r
+ Endpoint_Write_8(corenum, ((uint8_t *) Buffer)[i]);\r
+\r
+ return ENDPOINT_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Endpoint_Write_Stream_BE(uint8_t corenum,\r
+ const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ uint16_t i;\r
+\r
+ for (i = 0; i < Length; i++)\r
+ Endpoint_Write_8(corenum, ((uint8_t *) Buffer)[Length - 1 - i]);\r
+ return ENDPOINT_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Endpoint_Read_Stream_LE(uint8_t corenum,\r
+ void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ uint16_t i;\r
+ if (endpointselected[corenum] == ENDPOINT_CONTROLEP) {\r
+ if (usb_data_buffer_size[corenum] == 0) {\r
+ return ENDPOINT_RWSTREAM_IncompleteTransfer;\r
+ }\r
+ }\r
+ else if (usb_data_buffer_OUT_size[corenum] == 0) {\r
+ return ENDPOINT_RWSTREAM_IncompleteTransfer;\r
+ }\r
+\r
+ for (i = 0; i < Length; i++) {\r
+ #if defined(__LPC175X_6X__) || defined(__LPC177X_8X__) || defined(__LPC407X_8X__)\r
+ if (endpointselected[corenum] != ENDPOINT_CONTROLEP) {\r
+ while (usb_data_buffer_OUT_size[corenum] == 0) ; /* Current Fix for LPC17xx, havent checked for others */\r
+ }\r
+ #endif\r
+ ((uint8_t *) Buffer)[i] = Endpoint_Read_8(corenum);\r
+ }\r
+ return ENDPOINT_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Endpoint_Read_Stream_BE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ return ENDPOINT_RWSTREAM_NoError;\r
+}\r
+\r
+#endif\r
+\r
+uint8_t Endpoint_Write_Control_Stream_LE(uint8_t corenum, const void *const Buffer,\r
+ uint16_t Length)\r
+{\r
+ Endpoint_Write_Stream_LE(corenum, (uint8_t *) Buffer, MIN(Length, USB_ControlRequest.wLength), NULL);\r
+ Endpoint_ClearIN(corenum);\r
+ // while (!(Endpoint_IsOUTReceived()))\r
+ // {\r
+ // }\r
+ return ENDPOINT_RWCSTREAM_NoError;\r
+}\r
+\r
+uint8_t Endpoint_Write_Control_Stream_BE(const void *const Buffer,\r
+ uint16_t Length)\r
+{\r
+ return ENDPOINT_RWCSTREAM_NoError;\r
+}\r
+\r
+uint8_t Endpoint_Read_Control_Stream_LE(uint8_t corenum, void *const Buffer,\r
+ uint16_t Length)\r
+{\r
+ while (!Endpoint_IsOUTReceived(corenum)) ; // FIXME: this safe checking is fine for LPC18xx\r
+ Endpoint_Read_Stream_LE(corenum, Buffer, Length, NULL); // but hangs LPC17xx --> comment out\r
+ Endpoint_ClearOUT(corenum);\r
+ return ENDPOINT_RWCSTREAM_NoError;\r
+}\r
+\r
+uint8_t Endpoint_Read_Control_Stream_BE(void *const Buffer,\r
+ uint16_t Length)\r
+{\r
+ return ENDPOINT_RWCSTREAM_NoError;\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief Endpoint data stream transmission and reception management\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_EndpointRW \r
+ * @defgroup Group_EndpointStreamRW Read/Write of Multi-Byte Streams\r
+ * @brief Endpoint data stream transmission and reception management.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing of data streams from\r
+ * and to endpoints.\r
+ *\r
+ * @{\r
+ */ \r
+\r
+#ifndef __ENDPOINT_STREAM_H__\r
+#define __ENDPOINT_STREAM_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Enums: */\r
+ /** Enum for the possible error return codes of the \c Endpoint_*_Stream_* functions. */\r
+ enum Endpoint_Stream_RW_ErrorCodes_t\r
+ {\r
+ ENDPOINT_RWSTREAM_NoError = 0, /**< Command completed successfully, no error. */\r
+ ENDPOINT_RWSTREAM_EndpointStalled = 1, /**< The endpoint was stalled during the stream\r
+ * transfer by the host or device.\r
+ */\r
+ ENDPOINT_RWSTREAM_DeviceDisconnected = 2, /**< Device was disconnected from the host during\r
+ * the transfer.\r
+ */\r
+ ENDPOINT_RWSTREAM_BusSuspended = 3, /**< The USB bus has been suspended by the host and\r
+ * no USB endpoint traffic can occur until the bus\r
+ * has resumed.\r
+ */\r
+ ENDPOINT_RWSTREAM_Timeout = 4, /**< The host failed to accept or send the next packet\r
+ * within the software timeout period set by the\r
+ * @ref USB_STREAM_TIMEOUT_MS macro.\r
+ */\r
+ ENDPOINT_RWSTREAM_IncompleteTransfer = 5, /**< Indicates that the endpoint bank became full or empty before\r
+ * the complete contents of the current stream could be\r
+ * transferred. The endpoint stream function should be called\r
+ * again to process the next chunk of data in the transfer.\r
+ */\r
+ };\r
+ \r
+ /** Enum for the possible error return codes of the \c Endpoint_*_Control_Stream_* functions. */\r
+ enum Endpoint_ControlStream_RW_ErrorCodes_t\r
+ {\r
+ ENDPOINT_RWCSTREAM_NoError = 0, /**< Command completed successfully, no error. */\r
+ ENDPOINT_RWCSTREAM_HostAborted = 1, /**< The aborted the transfer prematurely. */\r
+ ENDPOINT_RWCSTREAM_DeviceDisconnected = 2, /**< Device was disconnected from the host during\r
+ * the transfer.\r
+ */\r
+ ENDPOINT_RWCSTREAM_BusSuspended = 3, /**< The USB bus has been suspended by the host and\r
+ * no USB endpoint traffic can occur until the bus\r
+ * has resumed.\r
+ */\r
+ };\r
+\r
+ #include "../../../Common/Common.h"\r
+ #include "USBTask.h"\r
+ \r
+ /* Function Prototypes: */\r
+ /** \name Stream functions for null data */\r
+ //@{\r
+ /**\r
+ * @brief Reads and discards the given number of bytes from the currently selected endpoint's bank,\r
+ * discarding fully read packets from the host as needed. The last packet is not automatically\r
+ * discarded once the remaining bytes has been read; the user is responsible for manually\r
+ * discarding the last packet from the host via the @ref Endpoint_ClearOUT() macro.\r
+ *\r
+ * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once,\r
+ * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid\r
+ * storage location, the transfer will instead be performed as a series of chunks. Each time\r
+ * the endpoint bank becomes empty while there is still data to process (and after the current\r
+ * packet has been acknowledged) the BytesProcessed location will be updated with the total number\r
+ * of bytes processed in the stream, and the function will exit with an error code of\r
+ * @ref ENDPOINT_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed\r
+ * in the user code - to continue the transfer, call the function again with identical parameters\r
+ * and it will resume until the BytesProcessed value reaches the total transfer length.\r
+ *\r
+ * <b>Single Stream Transfer Example:</b>\r
+ * \code\r
+ * uint8_t ErrorCode;\r
+ *\r
+ * if ((ErrorCode = Endpoint_Discard_Stream(512, NULL)) != ENDPOINT_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * <b>Partial Stream Transfers Example:</b>\r
+ * \code\r
+ * uint8_t ErrorCode;\r
+ * uint16_t BytesProcessed;\r
+ *\r
+ * BytesProcessed = 0;\r
+ * while ((ErrorCode = Endpoint_Discard_Stream(512, &BytesProcessed)) == ENDPOINT_RWSTREAM_IncompleteTransfer)\r
+ * {\r
+ * // Stream not yet complete - do other actions here, abort if required\r
+ * }\r
+ *\r
+ * if (ErrorCode != ENDPOINT_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * @note This routine should not be used on CONTROL type endpoints.\r
+ *\r
+ * @param corenum ID Number of USB Core to be processed.\r
+ * @param Length Number of bytes to discard via the currently selected endpoint.\r
+ * @param BytesProcessed Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be read at once.\r
+ *\r
+ * @param Length : Number of bytes to discard via the currently selected endpoint\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, NULL if the entire stream should be read at once.\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Discard_Stream(uint8_t corenum,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed);\r
+\r
+ /**\r
+ * @brief Writes a given number of zeroed bytes to the currently selected endpoint's bank, sending\r
+ * full packets to the host as needed. The last packet is not automatically sent once the \r
+ * remaining bytes have been written; the user is responsible for manually sending the last\r
+ * packet to the host via the @ref Endpoint_ClearIN() macro.\r
+ *\r
+ * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once,\r
+ * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid\r
+ * storage location, the transfer will instead be performed as a series of chunks. Each time\r
+ * the endpoint bank becomes full while there is still data to process (and after the current\r
+ * packet transmission has been initiated) the BytesProcessed location will be updated with the\r
+ * total number of bytes processed in the stream, and the function will exit with an error code of\r
+ * @ref ENDPOINT_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed\r
+ * in the user code - to continue the transfer, call the function again with identical parameters\r
+ * and it will resume until the BytesProcessed value reaches the total transfer length.\r
+ *\r
+ * <b>Single Stream Transfer Example:</b>\r
+ * \code\r
+ * uint8_t ErrorCode;\r
+ *\r
+ * if ((ErrorCode = Endpoint_Null_Stream(512, NULL)) != ENDPOINT_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * <b>Partial Stream Transfers Example:</b>\r
+ * \code\r
+ * uint8_t ErrorCode;\r
+ * uint16_t BytesProcessed;\r
+ *\r
+ * BytesProcessed = 0;\r
+ * while ((ErrorCode = Endpoint_Null_Stream(512, &BytesProcessed)) == ENDPOINT_RWSTREAM_IncompleteTransfer)\r
+ * {\r
+ * // Stream not yet complete - do other actions here, abort if required\r
+ * }\r
+ *\r
+ * if (ErrorCode != ENDPOINT_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * @note This routine should not be used on CONTROL type endpoints.\r
+ *\r
+ * @param corenum ID Number of USB Core to be processed.\r
+ * @param Length Number of zero bytes to send via the currently selected endpoint.\r
+ * @param BytesProcessed Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be read at once.\r
+ *\r
+ * @param Length : Number of zero bytes to send via the currently selected endpoint\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, NULL if the entire stream should be read at once\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Null_Stream(uint8_t corenum,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed);\r
+\r
+ //@}\r
+\r
+ /** \name Stream functions for RAM source/destination data */\r
+ //@{\r
+ \r
+ /** @brief Writes the given number of bytes to the endpoint from the given buffer in little endian,\r
+ * sending full packets to the host as needed. The last packet filled is not automatically sent;\r
+ * the user is responsible for manually sending the last written packet to the host via the\r
+ * @ref Endpoint_ClearIN() macro.\r
+ *\r
+ * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once,\r
+ * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid\r
+ * storage location, the transfer will instead be performed as a series of chunks. Each time\r
+ * the endpoint bank becomes full while there is still data to process (and after the current\r
+ * packet transmission has been initiated) the BytesProcessed location will be updated with the\r
+ * total number of bytes processed in the stream, and the function will exit with an error code of\r
+ * @ref ENDPOINT_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed\r
+ * in the user code - to continue the transfer, call the function again with identical parameters\r
+ * and it will resume until the BytesProcessed value reaches the total transfer length.\r
+ *\r
+ * <b>Single Stream Transfer Example:</b>\r
+ * \code\r
+ * uint8_t DataStream[512];\r
+ * uint8_t ErrorCode;\r
+ *\r
+ * if ((ErrorCode = Endpoint_Write_Stream_LE(DataStream, sizeof(DataStream),\r
+ * NULL)) != ENDPOINT_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * <b>Partial Stream Transfers Example:</b>\r
+ * \code\r
+ * uint8_t DataStream[512];\r
+ * uint8_t ErrorCode;\r
+ * uint16_t BytesProcessed;\r
+ *\r
+ * BytesProcessed = 0;\r
+ * while ((ErrorCode = Endpoint_Write_Stream_LE(DataStream, sizeof(DataStream),\r
+ * &BytesProcessed)) == ENDPOINT_RWSTREAM_IncompleteTransfer)\r
+ * {\r
+ * // Stream not yet complete - do other actions here, abort if required\r
+ * }\r
+ *\r
+ * if (ErrorCode != ENDPOINT_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * @note This routine should not be used on CONTROL type endpoints.\r
+ *\r
+ * @param corenum ID Number of USB Core to be processed.\r
+ * @param Buffer Pointer to the source data buffer to read from.\r
+ * @param Length Number of bytes to read for the currently selected endpoint into the buffer.\r
+ * @param BytesProcessed Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be written at once.\r
+ *\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, NULL if the entire stream should be written at once\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_Stream_LE(uint8_t corenum,\r
+ const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /**\r
+ * @brief Writes the given number of bytes to the endpoint from the given buffer in big endian,\r
+ * sending full packets to the host as needed. The last packet filled is not automatically sent;\r
+ * the user is responsible for manually sending the last written packet to the host via the\r
+ * @ref Endpoint_ClearIN() macro.\r
+ *\r
+ * @note This routine should not be used on CONTROL type endpoints.\r
+ *\r
+ * @param corenum ID Number of USB Core to be processed.\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be written at once\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_Stream_BE(uint8_t corenum,\r
+ const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /**\r
+ * @brief Reads the given number of bytes from the endpoint from the given buffer in little endian,\r
+ * discarding fully read packets from the host as needed. The last packet is not automatically\r
+ * discarded once the remaining bytes has been read; the user is responsible for manually\r
+ * discarding the last packet from the host via the @ref Endpoint_ClearOUT() macro.\r
+ *\r
+ * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once,\r
+ * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid\r
+ * storage location, the transfer will instead be performed as a series of chunks. Each time\r
+ * the endpoint bank becomes empty while there is still data to process (and after the current\r
+ * packet has been acknowledged) the BytesProcessed location will be updated with the total number\r
+ * of bytes processed in the stream, and the function will exit with an error code of\r
+ * @ref ENDPOINT_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed\r
+ * in the user code - to continue the transfer, call the function again with identical parameters\r
+ * and it will resume until the BytesProcessed value reaches the total transfer length.\r
+ *\r
+ * <b>Single Stream Transfer Example:</b>\r
+ * \code\r
+ * uint8_t DataStream[512];\r
+ * uint8_t ErrorCode;\r
+ *\r
+ * if ((ErrorCode = Endpoint_Read_Stream_LE(DataStream, sizeof(DataStream),\r
+ * NULL)) != ENDPOINT_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * <b>Partial Stream Transfers Example:</b>\r
+ * \code\r
+ * uint8_t DataStream[512];\r
+ * uint8_t ErrorCode;\r
+ * uint16_t BytesProcessed;\r
+ *\r
+ * BytesProcessed = 0;\r
+ * while ((ErrorCode = Endpoint_Read_Stream_LE(DataStream, sizeof(DataStream),\r
+ * &BytesProcessed)) == ENDPOINT_RWSTREAM_IncompleteTransfer)\r
+ * {\r
+ * // Stream not yet complete - do other actions here, abort if required\r
+ * }\r
+ *\r
+ * if (ErrorCode != ENDPOINT_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * @note This routine should not be used on CONTROL type endpoints.\r
+ *\r
+ * @param corenum ID Number of USB Core to be processed.\r
+ * \param[out] Buffer Pointer to the destination data buffer to write to.\r
+ * @param Length Number of bytes to send via the currently selected endpoint.\r
+ * @param BytesProcessed Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be read at once.\r
+ *\r
+ * @param Buffer : Pointer to the destination data buffer to write to\r
+ * @param Length : Number of bytes to send via the currently selected endpoint\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, NULL if the entire stream should be written at once\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Read_Stream_LE(uint8_t corenum,\r
+ void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /**\r
+ * @brief Reads the given number of bytes from the endpoint from the given buffer in big endian,\r
+ * discarding fully read packets from the host as needed. The last packet is not automatically\r
+ * discarded once the remaining bytes has been read; the user is responsible for manually\r
+ * discarding the last packet from the host via the @ref Endpoint_ClearOUT() macro.\r
+ *\r
+ * @note This routine should not be used on CONTROL type endpoints.\r
+ *\r
+ * @param Buffer : Pointer to the destination data buffer to write to\r
+ * @param Length : Number of bytes to send via the currently selected endpoint\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be read at once\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Read_Stream_BE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Writes the given number of bytes to the CONTROL type endpoint from the given buffer in little endian,\r
+ * sending full packets to the host as needed. The host OUT acknowledgement is not automatically cleared\r
+ * in both failure and success states; the user is responsible for manually clearing the setup OUT to\r
+ * finalize the transfer via the @ref Endpoint_ClearOUT() macro.\r
+ *\r
+ * @note This function automatically clears the control transfer's status stage. Do not manually attempt\r
+ * to clear the status stage when using this routine in a control transaction.\r
+ * \n\n\r
+ *\r
+ * @note This routine should only be used on CONTROL type endpoints.\r
+ *\r
+ * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained\r
+ * together; i.e. the entire stream data must be read or written at the one time.\r
+ *\r
+ * @param corenum ID Number of USB Core to be processed.\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_Control_Stream_LE(uint8_t corenum, const void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /**\r
+ * @brief Writes the given number of bytes to the CONTROL type endpoint from the given buffer in big endian,\r
+ * sending full packets to the host as needed. The host OUT acknowledgement is not automatically cleared\r
+ * in both failure and success states; the user is responsible for manually clearing the setup OUT to\r
+ * finalize the transfer via the @ref Endpoint_ClearOUT() macro.\r
+ *\r
+ * @note This function automatically clears the control transfer's status stage. Do not manually attempt\r
+ * to clear the status stage when using this routine in a control transaction.\r
+ * \n\n\r
+ *\r
+ * @note This routine should only be used on CONTROL type endpoints.\r
+ *\r
+ * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained\r
+ * together; i.e. the entire stream data must be read or written at the one time.\r
+ *\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_Control_Stream_BE(const void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Reads the given number of bytes from the CONTROL endpoint from the given buffer in little endian,\r
+ * discarding fully read packets from the host as needed. The device IN acknowledgement is not\r
+ * automatically sent after success or failure states; the user is responsible for manually sending the\r
+ * setup IN to finalize the transfer via the @ref Endpoint_ClearIN() macro.\r
+ *\r
+ * @note This function automatically clears the control transfer's status stage. Do not manually attempt\r
+ * to clear the status stage when using this routine in a control transaction.\r
+ * \n\n\r
+ *\r
+ * @note This routine should only be used on CONTROL type endpoints.\r
+ *\r
+ * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained\r
+ * together; i.e. the entire stream data must be read or written at the one time.\r
+ *\r
+ * @param corenum ID Number of USB Core to be processed.\r
+ * @param Buffer : Pointer to the destination data buffer to write to\r
+ * @param Length : Number of bytes to send via the currently selected endpoint\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Read_Control_Stream_LE(uint8_t corenum, void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /**\r
+ * @brief Reads the given number of bytes from the CONTROL endpoint from the given buffer in big endian,\r
+ * discarding fully read packets from the host as needed. The device IN acknowledgement is not\r
+ * automatically sent after success or failure states; the user is responsible for manually sending the\r
+ * setup IN to finalize the transfer via the @ref Endpoint_ClearIN() macro.\r
+ *\r
+ * @note This function automatically clears the control transfer's status stage. Do not manually attempt\r
+ * to clear the status stage when using this routine in a control transaction.\r
+ * \n\n\r
+ *\r
+ * @note This routine should only be used on CONTROL type endpoints.\r
+ *\r
+ * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained\r
+ * together; i.e. the entire stream data must be read or written at the one time.\r
+ *\r
+ * @param Buffer : Pointer to the destination data buffer to write to\r
+ * @param Length : Number of bytes to send via the currently selected endpoint\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Read_Control_Stream_BE(void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(1);\r
+ //@}\r
+\r
+ /** \name Stream functions for EEPROM source/destination data */\r
+ //@{\r
+ /**\r
+ * @brief Endpoint Write EEPROM Stream Little Endian\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be written at once\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_EStream_LE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Write EEPROM Stream Big Endian\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be written at once\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_EStream_BE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Read EEPROM Stream Little Endian\r
+ * @param Buffer : Pointer to the destination data buffer to write to, located in EEPROM memory space\r
+ * @param Length : Number of bytes to send via the currently selected endpoint\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be read at once\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Read_EStream_LE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Read EEPROM Stream Big Endian\r
+ * @param Buffer : Pointer to the destination data buffer to write to, located in EEPROM memory space\r
+ * @param Length : Number of bytes to send via the currently selected endpoint\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be read at once\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Read_EStream_BE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Write Control EEPROM Stream Little Endian\r
+ *\r
+ * @note This function automatically clears the control transfer's status stage. Do not manually attempt\r
+ * to clear the status stage when using this routine in a control transaction.\r
+ * \n\n\r
+ *\r
+ * @note This routine should only be used on CONTROL type endpoints.\r
+ * \n\n\r
+ *\r
+ * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained\r
+ * together; i.e. the entire stream data must be read or written at the one time.\r
+ *\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_Control_EStream_LE(const void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Write Control EEPROM Stream Big Endian\r
+ *\r
+ * @note This function automatically clears the control transfer's status stage. Do not manually attempt\r
+ * to clear the status stage when using this routine in a control transaction.\r
+ * \n\n\r
+ *\r
+ * @note This routine should only be used on CONTROL type endpoints.\r
+ * \n\n\r
+ *\r
+ * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained\r
+ * together; i.e. the entire stream data must be read or written at the one time.\r
+ *\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_Control_EStream_BE(const void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Read Control EEPROM Stream Little Endian\r
+ *\r
+ * @note This function automatically clears the control transfer's status stage. Do not manually attempt\r
+ * to clear the status stage when using this routine in a control transaction.\r
+ * \n\n\r
+ *\r
+ * @note This routine should only be used on CONTROL type endpoints.\r
+ * \n\n\r
+ *\r
+ * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained\r
+ * together; i.e. the entire stream data must be read or written at the one time.\r
+ *\r
+ * @param Buffer : Pointer to the destination data buffer to write to\r
+ * @param Length : Number of bytes to send via the currently selected endpoint\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Read_Control_EStream_LE(void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Read Control EEPROM Stream Big Endian\r
+ *\r
+ * @note This function automatically clears the control transfer's status stage. Do not manually attempt\r
+ * to clear the status stage when using this routine in a control transaction.\r
+ * \n\n\r
+ *\r
+ * @note This routine should only be used on CONTROL type endpoints.\r
+ * \n\n\r
+ *\r
+ * \warning Unlike the standard stream read/write commands, the control stream commands cannot be chained\r
+ * together; i.e. the entire stream data must be read or written at the one time.\r
+ *\r
+ * @param Buffer : Pointer to the destination data buffer to write to\r
+ * @param Length : Number of bytes to send via the currently selected endpoint\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Read_Control_EStream_BE(void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(1);\r
+ //@}\r
+ /**\r
+ * @brief Endpoint Write PROGMEM Stream Little Endian\r
+ //@{\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, NULL if the entire stream should be written at once.\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_PStream_LE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Write PROGMEM Stream Big Endian\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes processed in the current\r
+ * transaction should be updated, \c NULL if the entire stream should be written at once.\r
+ * @return A value from the @ref Endpoint_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_PStream_BE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Write Control PROGMEM Stream Little Endian\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_Control_PStream_LE(const void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(1);\r
+\r
+ /**\r
+ * @brief Endpoint Write Control PROGMEM Stream Big Endian\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected endpoint into the buffer\r
+ * @return A value from the @ref Endpoint_ControlStream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Endpoint_Write_Control_PStream_BE(const void *const Buffer,\r
+ uint16_t Length) ATTR_NON_NULL_PTR_ARG(1);\r
+ //@}\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Event management definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+#define __INCLUDE_FROM_EVENTS_C\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "Events.h"\r
+\r
+void USB_Event_Stub(void)\r
+{\r
+\r
+}\r
+#if defined(__ICCARM__)\r
+void USB_Host_HostError_Event_Stub(const uint8_t ErrorCode)\r
+{\r
+\r
+}\r
+void USB_Host_DeviceEnumerationFailed_Event_Stub(const uint8_t ErrorCode,\r
+ const uint8_t SubErrorCode)\r
+{\r
+}\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief USB Event management definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_Events USB Events\r
+ * @brief USB Event management definitions.\r
+ *\r
+ * This module contains macros and functions relating to the management of library events, which are small\r
+ * pieces of code similar to ISRs which are run when a given condition is met. Each event can be fired from\r
+ * multiple places in the user or library code, which may or may not be inside an ISR, thus each handler\r
+ * should be written to be as small and fast as possible to prevent possible problems.\r
+ *\r
+ * Events can be hooked by the user application by declaring a handler function with the same name and parameters\r
+ * listed here. If an event with no user-associated handler is fired within the library, it by default maps to an\r
+ * internal empty stub function.\r
+ *\r
+ * Each event must only have one associated event handler, but can be raised by multiple sources by calling the\r
+ * event handler function (with any required event parameters).\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __USBEVENTS_H__\r
+#define __USBEVENTS_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Pseudo-Functions for Doxygen: */\r
+ #if !defined(__INCLUDE_FROM_EVENTS_C) || defined(__DOXYGEN__)\r
+ /** Event for USB mode pin level change. This event fires when the USB interface is set to dual role\r
+ * mode, and the UID pin level has changed to indicate a new mode (device or host). This event fires\r
+ * before the mode is switched to the newly indicated mode but after the @ref EVENT_USB_Device_Disconnect\r
+ * event has fired (if disconnected before the role change).\r
+ *\r
+ * @note This event only exists on microcontrollers that support dual role USB modes.\r
+ * \n\n\r
+ *\r
+ * @note This event does not exist if the \c USB_DEVICE_ONLY or \c USB_HOST_ONLY tokens have been supplied\r
+ * to the compiler (see @ref Group_USBManagement documentation).\r
+ */\r
+ void EVENT_USB_UIDChange(void);\r
+\r
+ /** Event for USB host error. This event fires when a hardware fault has occurred whilst the USB\r
+ * interface is in host mode.\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param ErrorCode : Error code indicating the failure reason, a value in @ref USB_Host_ErrorCodes_t.\r
+ *\r
+ * @note This event only exists on microcontrollers that supports USB host mode.\r
+ * \n\n\r
+ *\r
+ * @note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ */\r
+ void EVENT_USB_Host_HostError(const uint8_t corenum, const uint8_t ErrorCode);\r
+\r
+ /** Event for USB device attachment. This event fires when a the USB interface is in host mode, and\r
+ * a USB device has been connected to the USB interface. This is interrupt driven, thus fires before\r
+ * the standard @ref EVENT_USB_Device_Connect() event and so can be used to programmatically start the USB\r
+ * management task to reduce CPU consumption.\r
+ *\r
+ * @note This event only exists on microcontrollers that supports USB host mode.\r
+ * \n\n\r
+ *\r
+ * @note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ *\r
+ * @see @ref USB_USBTask() for more information on the USB management task and reducing CPU usage.\r
+ */\r
+ void EVENT_USB_Host_DeviceAttached(const uint8_t corenum);\r
+\r
+ /** Event for USB device removal. This event fires when a the USB interface is in host mode, and\r
+ * a USB device has been removed the USB interface whether or not it has been enumerated. This\r
+ * can be used to programmatically stop the USB management task to reduce CPU consumption.\r
+ *\r
+ * @note This event only exists on microcontrollers that supports USB host mode.\r
+ * \n\n\r
+ *\r
+ * @note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ *\r
+ * @see @ref USB_USBTask() for more information on the USB management task and reducing CPU usage.\r
+ */\r
+ void EVENT_USB_Host_DeviceUnattached(const uint8_t corenum);\r
+\r
+ /** Event for USB device enumeration failure. This event fires when a the USB interface is\r
+ * in host mode, and an attached USB device has failed to enumerate completely.\r
+ *\r
+ * @param corenum : USB port number\r
+ *\r
+ * @param ErrorCode Error code indicating the failure reason, a value in\r
+ * @ref USB_Host_EnumerationErrorCodes_t.\r
+ *\r
+ * @param SubErrorCode Sub error code indicating the reason for failure - for example, if the\r
+ * ErrorCode parameter indicates a control error, this will give the error\r
+ * code returned by the @ref USB_Host_SendControlRequest() function.\r
+ *\r
+ * @note This event only exists on microcontrollers that supports USB host mode.\r
+ * \n\n\r
+ *\r
+ * @note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ */\r
+ void EVENT_USB_Host_DeviceEnumerationFailed(const uint8_t corenum,\r
+ const uint8_t ErrorCode,\r
+ const uint8_t SubErrorCode);\r
+\r
+ /** Event for USB device enumeration completion. This event fires when a the USB interface is\r
+ * in host mode and an attached USB device has been completely enumerated and is ready to be\r
+ * controlled by the user application.\r
+ *\r
+ * This event is time-critical; exceeding OS-specific delays within this event handler (typically of around\r
+ * 1 second) when a transaction is waiting to be processed by the device will prevent break communications\r
+ * and cause the host to reset the USB bus.\r
+ */\r
+ void EVENT_USB_Host_DeviceEnumerationComplete(const uint8_t corenum);\r
+\r
+ /** Event for USB Start Of Frame detection, when enabled. This event fires at the start of each USB\r
+ * frame, once per millisecond, and is synchronized to the USB bus. This can be used as an accurate\r
+ * millisecond timer source when the USB bus is not suspended while in host mode.\r
+ *\r
+ * This event is time-critical; it is run once per millisecond and thus long handlers will significantly\r
+ * degrade device performance. This event should only be enabled when needed to reduce device wake-ups.\r
+ *\r
+ * @note This event is not normally active - it must be manually enabled and disabled via the\r
+ * @ref USB_Host_EnableSOFEvents() and @ref USB_Host_DisableSOFEvents() commands after enumeration of\r
+ * a USB device.\r
+ * \n\n\r
+ *\r
+ * @note This event does not exist if the \c USB_DEVICE_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ */\r
+ void EVENT_USB_Host_StartOfFrame(const uint8_t corenum);\r
+\r
+ /** Event for USB device connection. This event fires when the microcontroller is in USB Device mode\r
+ * and the device is connected to a USB host, beginning the enumeration process measured by a rising\r
+ * level on the microcontroller's VBUS sense pin.\r
+ *\r
+ * This event is time-critical; exceeding OS-specific delays within this event handler (typically of around\r
+ * two seconds) will prevent the device from enumerating correctly.\r
+ *\r
+ * @note For the microcontrollers with limited USB controller functionality, VBUS sensing is not available.\r
+ * this means that the current connection state is derived from the bus suspension and wake up events by default,\r
+ * which is not always accurate (host may suspend the bus while still connected). If the actual connection state\r
+ * needs to be determined, VBUS should be routed to an external pin, and the auto-detect behaviour turned off by\r
+ * passing the \c NO_LIMITED_CONTROLLER_CONNECT token to the compiler via the -D switch at compile time. The connection\r
+ * and disconnection events may be manually fired, and the @ref USB_DeviceState global changed manually.\r
+ * \n\n\r
+ *\r
+ * @note This event may fire multiple times during device enumeration on the microcontrollers with limited USB controllers\r
+ * if \c NO_LIMITED_CONTROLLER_CONNECT is not defined.\r
+ *\r
+ * @see @ref Group_USBManagement for more information on the USB management task and reducing CPU usage.\r
+ */\r
+ void EVENT_USB_Device_Connect(void);\r
+\r
+ /** Event for USB device disconnection. This event fires when the microcontroller is in USB Device mode and the device is\r
+ * disconnected from a host, measured by a falling level on the microcontroller's VBUS sense pin.\r
+ *\r
+ * @note For the microcontrollers with limited USB controllers, VBUS sense is not available to the USB controller.\r
+ * this means that the current connection state is derived from the bus suspension and wake up events by default,\r
+ * which is not always accurate (host may suspend the bus while still connected). If the actual connection state\r
+ * needs to be determined, VBUS should be routed to an external pin, and the auto-detect behaviour turned off by\r
+ * passing the \c NO_LIMITED_CONTROLLER_CONNECT token to the compiler via the -D switch at compile time. The connection\r
+ * and disconnection events may be manually fired, and the @ref USB_DeviceState global changed manually.\r
+ * \n\n\r
+ *\r
+ * @note This event may fire multiple times during device enumeration on the microcontrollers with limited USB controllers\r
+ * if \c NO_LIMITED_CONTROLLER_CONNECT is not defined.\r
+ *\r
+ * @see @ref Group_USBManagement for more information on the USB management task and reducing CPU usage.\r
+ */\r
+ void EVENT_USB_Device_Disconnect(void);\r
+\r
+ /** Event for control requests. This event fires when a the USB host issues a control request\r
+ * to the mandatory device control endpoint (of address 0). This may either be a standard \r
+ * request that the library may have a handler code for internally, or a class specific request\r
+ * issued to the device which must be handled appropriately. If a request is not processed in the\r
+ * user application via this event, it will be passed to the library for processing internally\r
+ * if a suitable handler exists.\r
+ *\r
+ * This event is time-critical; each packet within the request transaction must be acknowledged or\r
+ * sent within 50ms or the host will abort the transfer.\r
+ *\r
+ * The library internally handles all standard control requests with the exceptions of SYNC FRAME,\r
+ * SET DESCRIPTOR and SET INTERFACE. These and all other non-standard control requests will be left\r
+ * for the user to process via this event if desired. If not handled in the user application or by\r
+ * the library internally, unknown requests are automatically STALLed.\r
+ *\r
+ * @note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ * \n\n\r
+ *\r
+ * @note Requests should be handled in the same manner as described in the USB 2.0 Specification,\r
+ * or appropriate class specification. In all instances, the library has already read the\r
+ * request SETUP parameters into the @ref USB_ControlRequest structure which should then be used\r
+ * by the application to determine how to handle the issued request.\r
+ */\r
+ void EVENT_USB_Device_ControlRequest(void);\r
+\r
+ /** Event for USB configuration number changed. This event fires when a the USB host changes the\r
+ * selected configuration number while in device mode. This event should be hooked in device\r
+ * applications to create the endpoints and configure the device for the selected configuration.\r
+ *\r
+ * This event is time-critical; exceeding OS-specific delays within this event handler (typically of around\r
+ * one second) will prevent the device from enumerating correctly.\r
+ *\r
+ * This event fires after the value of @ref USB_Device_ConfigurationNumber has been changed.\r
+ *\r
+ * @note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ */\r
+ void EVENT_USB_Device_ConfigurationChanged(void);\r
+\r
+ /** Event for USB suspend. This event fires when a the USB host suspends the device by halting its\r
+ * transmission of Start Of Frame pulses to the device. This is generally hooked in order to move\r
+ * the device over to a low power state until the host wakes up the device. If the USB interface is\r
+ * enumerated with the @ref USB_OPT_AUTO_PLL option set, the library will automatically suspend the\r
+ * USB PLL before the event is fired to save power.\r
+ *\r
+ * @note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ * \n\n\r
+ *\r
+ * @note This event does not exist on the microcontrollers with limited USB VBUS sensing abilities\r
+ * when the \c NO_LIMITED_CONTROLLER_CONNECT compile time token is not set - see\r
+ * @ref EVENT_USB_Device_Disconnect.\r
+ *\r
+ * @see @ref EVENT_USB_Device_WakeUp() event for accompanying Wake Up event.\r
+ */\r
+ void EVENT_USB_Device_Suspend(void);\r
+\r
+ /** Event for USB wake up. This event fires when a the USB interface is suspended while in device\r
+ * mode, and the host wakes up the device by supplying Start Of Frame pulses. This is generally\r
+ * hooked to pull the user application out of a low power state and back into normal operating\r
+ * mode. If the USB interface is enumerated with the @ref USB_OPT_AUTO_PLL option set, the library\r
+ * will automatically restart the USB PLL before the event is fired.\r
+ *\r
+ * @note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ * \n\n\r
+ *\r
+ * @note This event does not exist on the microcontrollers with limited USB VBUS sensing abilities\r
+ * when the \c NO_LIMITED_CONTROLLER_CONNECT compile time token is not set - see\r
+ * @ref EVENT_USB_Device_Disconnect.\r
+ *\r
+ * @see @ref EVENT_USB_Device_Suspend() event for accompanying Suspend event.\r
+ */\r
+ void EVENT_USB_Device_WakeUp(void);\r
+\r
+ /** Event for USB interface reset. This event fires when the USB interface is in device mode, and\r
+ * a the USB host requests that the device reset its interface. This event fires after the control\r
+ * endpoint has been automatically configured by the library.\r
+ *\r
+ * This event is time-critical; exceeding OS-specific delays within this event handler (typically of around\r
+ * two seconds) will prevent the device from enumerating correctly.\r
+ *\r
+ * @note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ */\r
+ void EVENT_USB_Device_Reset(void);\r
+\r
+ /** Event for USB Start Of Frame detection, when enabled. This event fires at the start of each USB\r
+ * frame, once per millisecond, and is synchronized to the USB bus. This can be used as an accurate\r
+ * millisecond timer source when the USB bus is enumerated in device mode to a USB host.\r
+ *\r
+ * This event is time-critical; it is run once per millisecond and thus long handlers will significantly\r
+ * degrade device performance. This event should only be enabled when needed to reduce device wake-ups.\r
+ *\r
+ * \pre This event is not normally active - it must be manually enabled and disabled via the\r
+ * @ref USB_Device_EnableSOFEvents() and @ref USB_Device_DisableSOFEvents() commands after enumeration.\r
+ * \n\n\r
+ *\r
+ * @note This event does not exist if the \c USB_HOST_ONLY token is supplied to the compiler (see\r
+ * @ref Group_USBManagement documentation).\r
+ */\r
+ void EVENT_USB_Device_StartOfFrame(void);\r
+ #endif\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_EVENTS_C)\r
+ void USB_Event_Stub(void) ATTR_CONST;\r
+ #if defined(__ICCARM__)\r
+ void USB_Host_HostError_Event_Stub(const uint8_t ErrorCode);\r
+ void USB_Host_DeviceEnumerationFailed_Event_Stub(const uint8_t ErrorCode,\r
+ const uint8_t SubErrorCode);\r
+ #endif\r
+ #if defined(USB_CAN_BE_BOTH)\r
+PRAGMA_WEAK(EVENT_USB_UIDChange,USB_Event_Stub) \r
+ void EVENT_USB_UIDChange(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+PRAGMA_WEAK(EVENT_USB_Host_HostError,USB_Event_Stub) \r
+ #if !defined(__ICCARM__)\r
+ void EVENT_USB_Host_HostError(const uint8_t ErrorCode) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+ #endif\r
+PRAGMA_WEAK(EVENT_USB_Host_DeviceAttached,USB_Event_Stub) \r
+ void EVENT_USB_Host_DeviceAttached(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Host_DeviceUnattached,USB_Event_Stub) \r
+ void EVENT_USB_Host_DeviceUnattached(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Host_DeviceEnumerationComplete,USB_Event_Stub) \r
+ void EVENT_USB_Host_DeviceEnumerationComplete(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Host_DeviceEnumerationFailed,USB_Event_Stub) \r
+ #if !defined(__ICCARM__)\r
+ void EVENT_USB_Host_DeviceEnumerationFailed(const uint8_t ErrorCode,\r
+ const uint8_t SubErrorCode)\r
+ ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+ #endif\r
+PRAGMA_WEAK(EVENT_USB_Host_StartOfFrame,USB_Event_Stub) \r
+ void EVENT_USB_Host_StartOfFrame(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+PRAGMA_WEAK(EVENT_USB_Device_Connect,USB_Event_Stub) \r
+ void EVENT_USB_Device_Connect(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Device_Disconnect,USB_Event_Stub) \r
+ void EVENT_USB_Device_Disconnect(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Device_ControlRequest,USB_Event_Stub) \r
+ void EVENT_USB_Device_ControlRequest(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Device_ConfigurationChanged,USB_Event_Stub) \r
+ void EVENT_USB_Device_ConfigurationChanged(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Device_Suspend,USB_Event_Stub) \r
+ void EVENT_USB_Device_Suspend(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Device_WakeUp,USB_Event_Stub) \r
+ void EVENT_USB_Device_WakeUp(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Device_Reset,USB_Event_Stub) \r
+ void EVENT_USB_Device_Reset(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+PRAGMA_WEAK(EVENT_USB_Device_StartOfFrame,USB_Event_Stub) \r
+ void EVENT_USB_Device_StartOfFrame(void) ATTR_WEAK ATTR_ALIAS(USB_Event_Stub);\r
+ #endif\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief This file contains common macros, APIs for upper layer (DCD, HCD) call,\r
+ * relating to init/deinit USB core, enable/disable USB interrupt...\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+* @defgroup Group_HAL_LPC Hardware Abstraction Layer\r
+* @brief Hardware Abstraction Layer for LPC architecture\r
+* @{\r
+*/\r
+ \r
+#ifndef __LPC_HAL_H__\r
+#define __LPC_HAL_H__\r
+\r
+/* Macros: */\r
+/** These macros used to declare a variable in a defined section (ex: USB RAM section). */\r
+#ifdef __CODE_RED\r
+ #include <cr_section_macros.h>\r
+#endif\r
+/* Chip Includes: */\r
+#if defined(__LPC18XX__) || defined(__LPC43XX__)\r
+ #include "LPC18XX/HAL_LPC18xx.h"\r
+#elif defined(__LPC175X_6X__) || defined(__LPC177X_8X__) || defined(__LPC407X_8X__)\r
+ #include "LPC17XX/HAL_LPC17xx.h"\r
+#elif defined(__LPC11U1X__) || defined(__LPC11U2X_3X__) || defined(__LPC1347__)\r
+ #include "LPC11UXX/HAL_LPC11Uxx.h"\r
+#endif\r
+/* Function Prototypes: */\r
+/**\r
+ * @brief This function is called by void USB_Init(void) to do the initialization for chip's USB core.\r
+ * Normally, this function will do the following:\r
+ * - Configure USB pins\r
+ * - Setup USB core clock\r
+ * - Call HAL_RESET to setup needed USB operating registers, set device address 0 if running device mode\r
+ * @param corenum : USB port number\r
+ * @return Nothing\r
+ */\r
+void HAL_USBInit(uint8_t corenum);\r
+\r
+/**\r
+ * @brief This function usage is opposite to HAL_USBInit\r
+ * @param corenum : USB port number\r
+ * @param mode : USB mode\r
+ * @return Nothing\r
+ */\r
+void HAL_USBDeInit(uint8_t corenum, uint8_t mode);\r
+\r
+/**\r
+ * @brief This function used to enable USB interrupt\r
+ * @param corenum : USB port number\r
+ * @return Nothing\r
+ */\r
+void HAL_EnableUSBInterrupt(uint8_t corenum);\r
+\r
+/**\r
+ * @brief This function usage is opposite to HAL_EnableUSBInterrupt\r
+ * @param corenum : USB port number\r
+ * @return Nothing\r
+ */\r
+void HAL_DisableUSBInterrupt(uint8_t corenum);\r
+\r
+/** This function is used in device mode to pull up resistor on USB pin D+\r
+ * Normally, this function is called when every setup or initial are done.\r
+ */\r
+/**\r
+* @brief This function is used in device mode to pull up resistor on USB pin D+\r
+* Normally, this function is called when every setup or initial are done.\r
+* @param corenum : USB port number\r
+* @param con : connect or disconect\r
+* @return Nothing\r
+*/\r
+void HAL_USBConnect (uint8_t corenum, uint32_t con);\r
+\r
+/* Selected USB Port Number */\r
+extern uint8_t USBPortNum;\r
+#endif /*__LPC_HAL_H__*/\r
+/* --------------------------------- End Of File ------------------------------ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * @brief HAL USB functions for the LPC11Uxx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#if (defined(__LPC11U1X__) || defined(__LPC11U2X_3X__) || defined(__LPC1347__))\r
+\r
+#include "../HAL.h"\r
+#include "../../USBTask.h"\r
+\r
+void HAL_USBInit(uint8_t corenum)\r
+{\r
+ /* power UP USB Phy and USB PLL */\r
+ Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);\r
+ Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);\r
+ #if defined(__LPC1347__)\r
+ Chip_Clock_SetUSBPllSource(SYSCTL_PLLCLKSRC_SYSOSC);\r
+ #else\r
+ Chip_Clock_SetUSBPllSource(SYSCTL_PLLCLKSRC_MAINOSC);\r
+ #endif\r
+ //while (!(LPC_SYSCTL->USBPLLCLKUEN & 0x01));\r
+ Chip_Clock_SetupUSBPLL(3,1);\r
+ while (!Chip_Clock_IsUSBPLLLocked()) {}\r
+ Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);\r
+ \r
+/* Enable AHB clock to the USB block and USB RAM. */\r
+ LPC_SYSCTL->SYSAHBCLKCTRL |= ((0x1 << 14) | (0x1 << 27));\r
+ \r
+ LPC_USB->EPBUFCFG = 0x3FC;\r
+\r
+ /* configure usb_soft connect */\r
+ LPC_IOCON->PIO0[6] = 0x01;\r
+\r
+#if !defined(USB_DEVICE_ROM_DRIVER)\r
+ HAL_Reset();\r
+#endif\r
+}\r
+\r
+void HAL_USBDeInit(uint8_t corenum, uint8_t mode)\r
+{\r
+ NVIC_DisableIRQ(USB0_IRQn); /* disable USB interrupt */\r
+ LPC_SYSCTL->SYSAHBCLKCTRL &= ~((0x1 << 14) | (0x1 << 27)); /* disable USB clock */\r
+}\r
+\r
+void HAL_EnableUSBInterrupt(uint8_t corenum)\r
+{\r
+ NVIC_EnableIRQ(USB0_IRQn);\r
+}\r
+\r
+void HAL_DisableUSBInterrupt(uint8_t corenum)\r
+{\r
+ NVIC_DisableIRQ(USB0_IRQn);\r
+}\r
+\r
+void HAL_SetDeviceAddress(uint8_t Address)\r
+{\r
+#ifdef USB_CAN_BE_DEVICE\r
+ LPC_USB->DEVCMDSTAT &= ~0x7F;\r
+ LPC_USB->DEVCMDSTAT |= (USB_EN | Address);\r
+#endif\r
+}\r
+\r
+void HAL_USBConnect(uint8_t corenum, uint32_t con)\r
+{\r
+#ifdef USB_CAN_BE_DEVICE\r
+ if ( con ) {\r
+ LPC_USB->DEVCMDSTAT |= USB_DCON;\r
+ }\r
+ else {\r
+ LPC_USB->DEVCMDSTAT &= ~USB_DCON;\r
+ }\r
+#endif\r
+}\r
+\r
+#endif /*CHIP_LPC11UXX*/\r
--- /dev/null
+/*\r
+ * @brief HAL USB functions for the LPC11Uxx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __HAL_LPC11UXX_H__\r
+#define __HAL_LPC11UXX_H__\r
+#include "chip.h"\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+\r
+#include "../../USBMode.h"\r
+\r
+#define USBRAM_SECTION RAM2\r
+/** This macro is used to declare a variable in a defined section. */\r
+#if defined(__CC_ARM)\r
+ #define __BSS(x) __attribute__ ((section("usbram")))\r
+#endif\r
+#if defined(__ICCARM__)\r
+ #define __BSS(x) @ "USB_PACKET_MEMORY"\r
+#endif\r
+\r
+/* Terminated Link Mask of USB DMA. */\r
+#define LINK_TERMINATE 0x01\r
+\r
+typedef struct {\r
+ uint16_t BufferAddrOffset;\r
+\r
+ __IO uint16_t NBytes : 10;\r
+ uint16_t Type : 1;\r
+ uint16_t RateFeedback_Toogle : 1;\r
+ uint16_t ToogleReset : 1;\r
+ __IO uint16_t Stall : 1;\r
+ uint16_t Disabled : 1;\r
+ __IO uint16_t Active : 1;\r
+\r
+} /* __attribute__ ((packed)) */ USB_CMD_STAT;\r
+\r
+void HAL_Reset (void);\r
+\r
+void HAL_SetDeviceAddress (uint8_t Address);\r
+\r
+#endif // __HAL_LPC11UXX_H__\r
+\r
--- /dev/null
+/*\r
+ * @brief HAL USB functions for the LPC17xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#if defined(__LPC175X_6X__) || defined(__LPC177X_8X__) || defined(__LPC407X_8X__)\r
+\r
+#include "../HAL.h"\r
+#include "../../USBTask.h"\r
+\r
+void HAL_USBInit(uint8_t corenum)\r
+{\r
+ /* Enable PLL1 for 48MHz output */\r
+ Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);\r
+#if defined(__LPC175X_6X__)\r
+ while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLL1STS_LOCKED) == 0);\r
+#else\r
+ while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLLSTS_LOCKED) == 0);\r
+#endif\r
+\r
+ Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC1); /* P0.29 D1+, P0.30 D1- */\r
+ Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC1);\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ Chip_IOCON_PinMux(LPC_IOCON, 1, 19, IOCON_MODE_INACT, IOCON_FUNC2); /* USB_Power switch */\r
+#endif\r
+ \r
+#if defined(USB_CAN_BE_DEVICE)\r
+ Chip_IOCON_PinMux(LPC_IOCON, 2, 9, IOCON_MODE_INACT, IOCON_FUNC1); /* USB_SoftConnect */\r
+#endif\r
+ \r
+ LPC_SYSCTL->PCONP |= (1UL << 31); /* USB PCLK -> enable USB Per.*/\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+ LPC_USB->USBClkCtrl = 0x12; /* Dev, PortSel, AHB clock enable */\r
+ while ((LPC_USB->USBClkSt & 0x12) != 0x12) ;\r
+\r
+ HAL_Reset(corenum);\r
+#endif\r
+}\r
+\r
+void HAL_USBDeInit(uint8_t corenum, uint8_t mode)\r
+{\r
+ NVIC_DisableIRQ(USB_IRQn); /* disable USB interrupt */\r
+ LPC_SYSCTL->PCONP &= (~(1UL << 31)); /* disable USB Per. */ \r
+ Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC0); /* P0.29 D+, P0.30 D- reset to GPIO function */\r
+ Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC0);\r
+ /* Disable PLL1 to save power */\r
+ Chip_Clock_DisablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);\r
+}\r
+\r
+void HAL_EnableUSBInterrupt(uint8_t corenum)\r
+{\r
+ NVIC_EnableIRQ(USB_IRQn); /* enable USB interrupt */\r
+}\r
+\r
+void HAL_DisableUSBInterrupt(uint8_t corenum)\r
+{\r
+ NVIC_DisableIRQ(USB_IRQn); /* enable USB interrupt */\r
+}\r
+\r
+void HAL_USBConnect(uint8_t corenum, uint32_t con)\r
+{\r
+ if (USB_CurrentMode[corenum] == USB_MODE_Device) {\r
+#if defined(USB_CAN_BE_DEVICE)\r
+ HAL17XX_USBConnect(con);\r
+#endif\r
+ }\r
+}\r
+\r
+// TODO moving stuff to approriate places\r
+extern void DcdIrqHandler (uint8_t DeviceID);\r
+\r
+void USB_IRQHandler(void)\r
+{\r
+ if (USB_CurrentMode[0] == USB_MODE_Host) {\r
+ #if defined(USB_CAN_BE_HOST)\r
+ HcdIrqHandler(0);\r
+ #endif\r
+ }\r
+\r
+ if (USB_CurrentMode[0] == USB_MODE_Device) {\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ DcdIrqHandler(0);\r
+ #endif\r
+ }\r
+}\r
+\r
+#endif /*__LPC17XX__ || __LPC40XX__*/\r
--- /dev/null
+/*\r
+ * @brief HAL USB functions for the LPC17xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_HAL_LPC\r
+ * @defgroup Group_HAL_LPC17xx Hardware Abstraction Layer LPC17XX\r
+ * @{\r
+ */\r
+#ifndef __HAL_LPC17XX_H__\r
+#define __HAL_LPC17XX_H__\r
+\r
+#include "chip.h"\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#define USBRAM_SECTION RAM2\r
+\r
+#if defined(__LPC177X_8X__) || defined(__LPC407X_8X__)\r
+/** This macro is used to declare a variable in a defined section. */\r
+#if defined(__CC_ARM)\r
+ #define __BSS(x) __attribute__ ((section("usbram")))\r
+#endif\r
+#if defined(__ICCARM__)\r
+ #define __BSS(x) @ ".sram"\r
+#endif\r
+#else \r
+#if defined(__CC_ARM) || defined(__ICCARM__)\r
+ #define __BSS(x)\r
+#endif\r
+#endif\r
+\r
+#define USB_REG(CoreID) LPC_USB\r
+\r
+/**\r
+ * @brief Interrupt Handler (Host side).\r
+ * This handler is known as interrupt service routine of USB Host.\r
+ *\r
+ * @param HostID : Host ID\r
+ * @return Nothing.\r
+ */\r
+extern void HcdIrqHandler(uint8_t HostID);\r
+\r
+#ifdef USB_CAN_BE_DEVICE\r
+\r
+/* Device Interrupt Bit Definitions */\r
+#define FRAME_INT 0x00000001\r
+#define EP_FAST_INT 0x00000002\r
+#define EP_SLOW_INT 0x00000004\r
+#define DEV_STAT_INT 0x00000008\r
+#define CCEMTY_INT 0x00000010\r
+#define CDFULL_INT 0x00000020\r
+#define RxENDPKT_INT 0x00000040\r
+#define TxENDPKT_INT 0x00000080\r
+#define EP_RLZED_INT 0x00000100\r
+#define ERR_INT 0x00000200\r
+\r
+/* Rx & Tx Packet Length Definitions */\r
+#define PKT_LNGTH_MASK 0x000003FF\r
+#define PKT_DV 0x00000400\r
+#define PKT_RDY 0x00000800\r
+\r
+/* USB Control Definitions */\r
+#define CTRL_RD_EN 0x00000001\r
+#define CTRL_WR_EN 0x00000002\r
+\r
+/* Command Codes */\r
+#define CMD_SET_ADDR 0x00D00500\r
+#define CMD_CFG_DEV 0x00D80500\r
+#define CMD_SET_MODE 0x00F30500\r
+#define CMD_RD_FRAME 0x00F50500\r
+#define DAT_RD_FRAME 0x00F50200\r
+#define CMD_RD_TEST 0x00FD0500\r
+#define DAT_RD_TEST 0x00FD0200\r
+#define CMD_SET_DEV_STAT 0x00FE0500\r
+#define CMD_GET_DEV_STAT 0x00FE0500\r
+#define DAT_GET_DEV_STAT 0x00FE0200\r
+#define CMD_GET_ERR_CODE 0x00FF0500\r
+#define DAT_GET_ERR_CODE 0x00FF0200\r
+#define CMD_RD_ERR_STAT 0x00FB0500\r
+#define DAT_RD_ERR_STAT 0x00FB0200\r
+#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))\r
+#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))\r
+#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))\r
+#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))\r
+#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))\r
+#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))\r
+#define CMD_CLR_BUF 0x00F20500\r
+#define DAT_CLR_BUF 0x00F20200\r
+#define CMD_VALID_BUF 0x00FA0500\r
+\r
+/* Device Address Register Definitions */\r
+#define DEV_ADDR_MASK 0x7F\r
+#define DEV_EN 0x80\r
+\r
+/* Device Configure Register Definitions */\r
+#define CONF_DVICE 0x01\r
+\r
+/* Device Mode Register Definitions */\r
+#define AP_CLK 0x01\r
+#define INAK_CI 0x02\r
+#define INAK_CO 0x04\r
+#define INAK_II 0x08\r
+#define INAK_IO 0x10\r
+#define INAK_BI 0x20\r
+#define INAK_BO 0x40\r
+\r
+/* Device Status Register Definitions */\r
+#define DEV_CON 0x01\r
+#define DEV_CON_CH 0x02\r
+#define DEV_SUS 0x04\r
+#define DEV_SUS_CH 0x08\r
+#define DEV_RST 0x10\r
+\r
+/* Error Code Register Definitions */\r
+#define ERR_EC_MASK 0x0F\r
+#define ERR_EA 0x10\r
+\r
+/* Error Status Register Definitions */\r
+#define ERR_PID 0x01\r
+#define ERR_UEPKT 0x02\r
+#define ERR_DCRC 0x04\r
+#define ERR_TIMOUT 0x08\r
+#define ERR_EOP 0x10\r
+#define ERR_B_OVRN 0x20\r
+#define ERR_BTSTF 0x40\r
+#define ERR_TGL 0x80\r
+\r
+/* Endpoint Select Register Definitions */\r
+#define EP_SEL_F 0x01\r
+#define EP_SEL_ST 0x02\r
+#define EP_SEL_STP 0x04\r
+#define EP_SEL_PO 0x08\r
+#define EP_SEL_EPN 0x10\r
+#define EP_SEL_B_1_FULL 0x20\r
+#define EP_SEL_B_2_FULL 0x40\r
+\r
+/* Endpoint Status Register Definitions */\r
+#define EP_STAT_ST 0x01\r
+#define EP_STAT_DA 0x20\r
+#define EP_STAT_RF_MO 0x40\r
+#define EP_STAT_CND_ST 0x80\r
+\r
+/* Clear Buffer Register Definitions */\r
+#define CLR_BUF_PO 0x01\r
+\r
+/* DMA Interrupt Bit Definitions */\r
+#define EOT_INT 0x01\r
+#define NDD_REQ_INT 0x02\r
+#define SYS_ERR_INT 0x04\r
+\r
+void HAL_Reset (uint8_t corenum);\r
+\r
+/**\r
+ * @brief Set device address\r
+ * @param Address : Address to be set\r
+ * @return Nothing.\r
+ */\r
+void HAL_SetDeviceAddress (uint8_t Address);\r
+\r
+/**\r
+ * @brief Send connect SIE command\r
+ * @param con : connect or disconnect status\r
+ * @return Nothing.\r
+ */\r
+void HAL17XX_USBConnect (uint32_t con);\r
+\r
+/**\r
+ * @brief Read SIE command data\r
+ * @param cmd : command code\r
+ * @return Data.\r
+ */\r
+uint32_t SIE_ReadCommandData (uint32_t cmd);/* Device_LPC17xx */\r
+\r
+/*---------- DMA Descriptor ----------*/\r
+typedef struct {\r
+ /*---------- Word 0 ----------*/\r
+ uint32_t NextDD;\r
+\r
+ /*---------- Word 1 ----------*/\r
+ /* 1st half word */\r
+ uint16_t Mode : 2;\r
+ uint16_t NextDDValid : 1;\r
+ uint16_t : 1;\r
+ uint16_t Isochronous : 1;\r
+ uint16_t MaxPacketSize : 11;\r
+ /* 2nd half word */\r
+ __IO uint16_t BufferLength;\r
+\r
+ /*---------- Word 2 ----------*/\r
+ __IO uint8_t *BufferStartAddr;\r
+\r
+ /*---------- Word 3 ----------*/\r
+ /* 1st half word */\r
+ __IO uint16_t Retired : 1;\r
+ uint16_t Status : 4;\r
+ uint16_t IsoPacketValid : 1;\r
+ uint16_t LSByteExtracted : 1; /* ATLE mode */\r
+ uint16_t MSByteExtracted : 1; /* ATLE mode */\r
+ uint16_t MessageLengthPosition : 6;\r
+ uint16_t : 2;\r
+ /* 2st half word */\r
+ uint16_t PresentCount;\r
+\r
+ /*---------- Word 4 ----------*/\r
+ uint32_t IsoBufferAddr; /* Iso transfer exclusive */\r
+} DMADescriptor, *PDMADescriptor;\r
+#endif\r
+\r
+#endif // __HAL_LPC17XX_H__\r
+\r
+/**\r
+ * @}\r
+ */\r
--- /dev/null
+/*\r
+ * @brief HAL USB functions for the LPC18xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#if defined(__LPC18XX__) || defined(__LPC43XX__)\r
+\r
+#include "../HAL.h"\r
+#include "../../USBTask.h"\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+#include "../../Device.h"\r
+\r
+void HAL_USBConnect(uint8_t corenum, uint32_t con)\r
+{\r
+#if defined(USB_DEVICE_ROM_DRIVER)\r
+ if (con) {\r
+ USBD_API->hw->Connect(UsbHandle, 1);\r
+ }\r
+ else {\r
+ USBD_API->hw->Connect(UsbHandle, 0);\r
+ }\r
+#else\r
+ if (con) {\r
+ USB_REG(corenum)->USBCMD_D |= (1 << 0);\r
+ }\r
+ else {\r
+ USB_REG(corenum)->USBCMD_D &= ~(1 << 0);\r
+ }\r
+#endif\r
+}\r
+\r
+#endif\r
+\r
+IP_USBHS_001_T * const USB_REG_BASE_ADDR[LPC18_43_MAX_USB_CORE] = {LPC_USB0, LPC_USB1};\r
+\r
+/* Support for USB0 and USB1, 2 cores */\r
+static bool coreEnabled[2];\r
+\r
+void HAL_USBInit(uint8_t corenum)\r
+{\r
+ /* Just exit if already enabled */\r
+ if (!coreEnabled[corenum]) {\r
+ /* if other code is not enabled, the enable USB PLL */\r
+ if (!coreEnabled[1 - corenum]) {\r
+ /* Neither core is enabled, so enable USB PLL first */\r
+ Chip_Clock_EnablePLL(CGU_USB_PLL);\r
+\r
+ /* Wait for PLL lock */\r
+ while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED));\r
+ }\r
+\r
+ if (corenum == 0) {\r
+ /* For core 0, enable USB0 base clock */\r
+ Chip_Clock_EnableBaseClock(CLK_BASE_USB0);\r
+ Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1);\r
+\r
+ /* Turn on the phy */\r
+ Chip_CREG_EnableUSB0Phy(true);\r
+ }\r
+ else {\r
+ /* For core 1, enable USB1 base clock */\r
+ Chip_Clock_EnableBaseClock(CLK_BASE_USB1);\r
+ Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1);\r
+\r
+ /* Turn on the phy */\r
+ Chip_CREG_EnableUSB0Phy(true);\r
+#if defined(USB_CAN_BE_HOST)\r
+ /* enable USB1_DP and USB1_DN on chip FS phy */\r
+ if (corenum && USB_CurrentMode[corenum] == USB_MODE_Host)LPC_SCU->SFSUSB = 0x16;\r
+#endif\r
+#if defined(USB_CAN_BE_DEVICE)\r
+ /* enable USB1_DP and USB1_DN on chip FS phy */\r
+ if (corenum && USB_CurrentMode[corenum] == USB_MODE_Device)LPC_SCU->SFSUSB = 0x12;\r
+#endif\r
+ LPC_USB1->PORTSC1_D |= (1 << 24);\r
+ }\r
+\r
+ coreEnabled[corenum] = true;\r
+ }\r
+\r
+#if defined(USB_CAN_BE_DEVICE) && (!defined(USB_DEVICE_ROM_DRIVER))\r
+ /* reset the controller */\r
+ USB_REG(corenum)->USBCMD_D = USBCMD_D_Reset;\r
+ /* wait for reset to complete */\r
+ while (USB_REG(corenum)->USBCMD_D & USBCMD_D_Reset) ;\r
+\r
+ /* Program the controller to be the USB device controller */\r
+ USB_REG(corenum)->USBMODE_D = (0x2 << 0) /*| (1<<4)*//*| (1<<3)*/;\r
+ if (corenum == 0) {\r
+ /* set OTG transcever in proper state, device is present\r
+ on the port(CCS=1), port enable/disable status change(PES=1). */\r
+ LPC_USB0->OTGSC = (1 << 3) | (1 << 0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;\r
+ #if (USB_FORCED_FULLSPEED)\r
+ LPC_USB0->PORTSC1_D |= (1 << 24);\r
+ #endif\r
+ }\r
+ HAL_Reset(corenum);\r
+#endif\r
+}\r
+\r
+void HAL_USBDeInit(uint8_t corenum, uint8_t mode)\r
+{\r
+ HAL_DisableUSBInterrupt(corenum);\r
+ if (mode == USB_MODE_Device) {\r
+ #if defined(USB_CAN_BE_HOST)\r
+ USB_REG(corenum)->USBSTS_H = 0xFFFFFFFF; /* clear all current interrupts */\r
+ USB_REG(corenum)->PORTSC1_H &= ~(1 << 12); /* clear port power */\r
+ USB_REG(corenum)->USBMODE_H = (1 << 0); /* set USB mode reserve */\r
+ #endif\r
+ }\r
+ else if (mode == USB_MODE_Host) {\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ /* Clear all pending interrupts */\r
+ USB_REG(corenum)->USBSTS_D = 0xFFFFFFFF;\r
+ USB_REG(corenum)->ENDPTNAK = 0xFFFFFFFF;\r
+ USB_REG(corenum)->ENDPTNAKEN = 0;\r
+ USB_REG(corenum)->ENDPTSETUPSTAT = USB_REG(corenum)->ENDPTSETUPSTAT;\r
+ USB_REG(corenum)->ENDPTCOMPLETE = USB_REG(corenum)->ENDPTCOMPLETE;\r
+ while (USB_REG(corenum)->ENDPTPRIME) ; /* Wait until all bits are 0 */\r
+ USB_REG(corenum)->ENDPTFLUSH = 0xFFFFFFFF;\r
+ while (USB_REG(corenum)->ENDPTFLUSH) ; /* Wait until all bits are 0 */\r
+ #endif\r
+ }\r
+\r
+ /* Disable USB PHY if both USB cores are disabled */\r
+ if (coreEnabled[1 - corenum]) {\r
+ /* Turn off the phy (prior to PLL disabled) */\r
+ Chip_CREG_EnableUSB0Phy(false);\r
+ }\r
+\r
+ /* Power down USB clocking */\r
+ if (corenum == 0) {\r
+ Chip_Clock_Disable(CLK_MX_USB0);\r
+ Chip_Clock_DisableBaseClock(CLK_BASE_USB0);\r
+ }\r
+ else {\r
+ Chip_Clock_Disable(CLK_MX_USB1);\r
+ Chip_Clock_DisableBaseClock(CLK_BASE_USB1);\r
+ }\r
+\r
+ /* Disable USB PLL if both USB cores are disabled */\r
+ if (coreEnabled[1 - corenum]) {\r
+ /* Disable USB PLL */\r
+ Chip_Clock_DisablePLL(CGU_USB_PLL);\r
+ }\r
+\r
+ coreEnabled[corenum] = false;\r
+}\r
+\r
+void HAL_EnableUSBInterrupt(uint8_t corenum)\r
+{\r
+ NVIC_EnableIRQ((corenum) ? USB1_IRQn : USB0_IRQn); // enable USB interrupts\r
+}\r
+\r
+void HAL_DisableUSBInterrupt(uint8_t corenum)\r
+{\r
+ NVIC_DisableIRQ((corenum) ? USB1_IRQn : USB0_IRQn); // disable USB interrupts\r
+}\r
+\r
+void USB0_IRQHandler(void)\r
+{\r
+ if (USB_CurrentMode[0] == USB_MODE_Host) {\r
+ #ifdef USB_CAN_BE_HOST\r
+ HcdIrqHandler(0);\r
+ #endif\r
+ }\r
+ if (USB_CurrentMode[0] == USB_MODE_Device) {\r
+ #ifdef USB_CAN_BE_DEVICE\r
+ #ifdef USB_DEVICE_ROM_DRIVER\r
+ UsbdRom_IrqHandler();\r
+ #else\r
+ DcdIrqHandler(0);\r
+ #endif\r
+ #endif\r
+ }\r
+}\r
+\r
+void USB1_IRQHandler(void)\r
+{\r
+ if (USB_CurrentMode[1] == USB_MODE_Host) {\r
+ #ifdef USB_CAN_BE_HOST\r
+ HcdIrqHandler(1);\r
+ #endif\r
+ }\r
+ if (USB_CurrentMode[1] == USB_MODE_Device) {\r
+ #ifdef USB_CAN_BE_DEVICE\r
+ #ifdef USB_DEVICE_ROM_DRIVER\r
+ UsbdRom_IrqHandler();\r
+ #else\r
+ DcdIrqHandler(1);\r
+ #endif\r
+ #endif\r
+ }\r
+}\r
+\r
+#endif /*__LPC18XX__*/\r
--- /dev/null
+/*\r
+ * @brief HAL USB functions for the LPC18xx microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+ /** @ingroup Group_HAL_LPC\r
+ * @defgroup Group_HAL_LPC18xx Hardware Abstraction Layer LPC18XX\r
+ * @{\r
+ */\r
+\r
+#ifndef __HAL_LPC18XX_H__\r
+#define __HAL_LPC18XX_H__\r
+\r
+#include "chip.h"\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#define USBRAM_SECTION RAM2\r
+\r
+#if defined(__ICCARM__)\r
+ #define __BSS(x) @ ".ahb_sram1"\r
+#elif defined(__CC_ARM)\r
+ #define __BSS(x)\r
+#endif\r
+/* bit defines for DEVICEADDR register. */\r
+#define USBDEV_ADDR_AD (1 << 24)\r
+#define USBDEV_ADDR(n) (((n) & 0x7F) << 25)\r
+\r
+/* Max USB Core specially for LPC18xx/43xx series. */\r
+#define LPC18_43_MAX_USB_CORE 2\r
+\r
+/* This macro is used to get proper USB Register base address\r
+ * from specified USB core ID.\r
+ */\r
+#define USB_REG(CoreID) USB_REG_BASE_ADDR[CoreID]\r
+\r
+/* Terminated Link Mask of USB DMA. */\r
+#define LINK_TERMINATE 0x01\r
+\r
+/* Constant table stores base addresses of USB Register Structures. */\r
+extern IP_USBHS_001_T * const USB_REG_BASE_ADDR[];\r
+\r
+/**\r
+ * @brief Interrupt Handler (Host side).\r
+ * This handler is known as interrupt service routine of USB Host.\r
+ *\r
+ * @param HostID : Host ID\r
+ * @return Nothing.\r
+ */\r
+extern void HcdIrqHandler(uint8_t HostID);\r
+\r
+/**\r
+ * @brief Interrupt Handler (Device side).\r
+ * This handler is known as interrupt service routine of USB Device.\r
+ *\r
+ * @param corenum : ID Number of USB Core to be processed.\r
+ * @return Nothing.\r
+ */\r
+extern void DcdIrqHandler (uint8_t corenum);\r
+\r
+void HAL_Reset (uint8_t corenum);\r
+\r
+#endif // __HAL_LPC18XX_H__\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * @brief Enhanced Host Controller Interface\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/*=======================================================================*/\r
+/* I N C L U D E S */\r
+/*=======================================================================*/\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#if (defined(USB_CAN_BE_HOST) && defined(__LPC_EHCI__))\r
+\r
+#define __LPC_EHCI_C__\r
+#include "../../../../../Common/Common.h"\r
+#include "../../USBTask.h"\r
+#include "../HCD.h"\r
+#include "EHCI.h"\r
+\r
+// === TODO: Unify USBRAM Section ===\r
+PRAGMA_ALIGN_32\r
+EHCI_HOST_DATA_T ehci_data[MAX_USB_CORE] __BSS(USBRAM_SECTION);\r
+// EHCI_HOST_DATA_T ehci_data __BSS(USBRAM_SECTION);\r
+PRAGMA_ALIGN_4096\r
+NextLinkPointer PeriodFrameList0[FRAME_LIST_SIZE] ATTR_ALIGNED(4096) __BSS(USBRAM_SECTION); /* Period Frame List */\r
+PRAGMA_ALIGN_4096\r
+NextLinkPointer PeriodFrameList1[FRAME_LIST_SIZE] ATTR_ALIGNED(4096) __BSS(USBRAM_SECTION); /* Period Frame List */\r
+Pipe_Stream_Handle_T PipeStreaming[MAX_USB_CORE];\r
+/*=======================================================================*/\r
+/* G L O B A L F U N C T I O N S */\r
+/*=======================================================================*/\r
+HCD_STATUS HcdInitDriver(uint8_t HostID)\r
+{\r
+ EHciHostReset(HostID);\r
+ return EHciHostInit(HostID);\r
+}\r
+\r
+HCD_STATUS HcdDeInitDriver(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->USBSTS_H = 0xFFFFFFFF; /* clear all current interrupts */\r
+ USB_REG(HostID)->PORTSC1_H &= ~(1 << 12); /* clear port power */\r
+ USB_REG(HostID)->USBMODE_H = (1 << 0); /* set USB mode reserve */\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdRhPortEnable(uint8_t HostID)\r
+{\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdRhPortDisable(uint8_t HostID)\r
+{\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdRhPortReset(uint8_t HostID)\r
+{\r
+ HcdDelayMS(PORT_RESET_PERIOD_MS);\r
+\r
+ USB_REG(HostID)->PORTSC1_H &= ~EHC_PORTSC_PortEnable; /* Disable Port first */\r
+ USB_REG(HostID)->PORTSC1_H |= EHC_PORTSC_PortReset; /* Reset port */\r
+\r
+ /* should have time-out */\r
+ while (USB_REG(HostID)->PORTSC1_H & EHC_PORTSC_PortReset) {}\r
+\r
+ /* PortEnable is always set - Deviation from EHCI */\r
+\r
+ HcdDelayMS(PORT_RESET_PERIOD_MS);\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdClearEndpointHalt(uint32_t PipeHandle)// FIXME not implemented\r
+{\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+uint32_t HcdGetFrameNumber(uint8_t HostID)\r
+{\r
+ return USB_REG(HostID)->FRINDEX_H;\r
+}\r
+\r
+HCD_STATUS HcdGetDeviceSpeed(uint8_t HostID, HCD_USB_SPEED *DeviceSpeed)\r
+{\r
+ if ( USB_REG(HostID)->PORTSC1_H & EHC_PORTSC_CurrentConnectStatus) {/* If device is connected */\r
+ *DeviceSpeed = (HCD_USB_SPEED) ( (USB_REG(HostID)->PORTSC1_H & EHC_PORTSC_PortSpeed) >> 26 ); /* TODO magic number */\r
+ return HCD_STATUS_OK;\r
+ }\r
+ else {\r
+ return HCD_STATUS_DEVICE_DISCONNECTED;\r
+ }\r
+}\r
+\r
+HCD_STATUS HcdOpenPipe(uint8_t HostID,\r
+ uint8_t DeviceAddr,\r
+ HCD_USB_SPEED DeviceSpeed,\r
+ uint8_t EndpointNumber,\r
+ HCD_TRANSFER_TYPE TransferType,\r
+ HCD_TRANSFER_DIR TransferDir,\r
+ uint16_t MaxPacketSize,\r
+ uint8_t Interval,\r
+ uint8_t Mult,\r
+ uint8_t HSHubDevAddr,\r
+ uint8_t HSHubPortNum,\r
+ uint32_t *const pPipeHandle)\r
+{\r
+ uint32_t HeadIdx;\r
+\r
+#if !ISO_LIST_ENABLE\r
+ if ( TransferType == ISOCHRONOUS_TRANSFER ) {\r
+ ASSERT_STATUS_OK_MESSAGE(HCD_STATUS_TRANSFER_TYPE_NOT_SUPPORTED, "Please set ISO_LIST_ENABLE to YES");\r
+ }\r
+#endif\r
+\r
+#if !INTERRUPT_LIST_ENABLE\r
+ if ( TransferType == INTERRUPT_TRANSFER ) {\r
+ ASSERT_STATUS_OK_MESSAGE(HCD_STATUS_TRANSFER_TYPE_NOT_SUPPORTED, "Please set INTERRUPT_LIST_ENABLE to YES");\r
+ }\r
+#endif\r
+\r
+ /********************************* Parameters Verify *********************************/\r
+ ASSERT_STATUS_OK(OpenPipe_VerifyParameters(HostID, DeviceAddr, DeviceSpeed, EndpointNumber, TransferType,\r
+ TransferDir, MaxPacketSize, Interval, Mult) );\r
+\r
+ EndpointNumber &= 0xF; /* Endpoint number is in range 0-15 */\r
+ MaxPacketSize &= 0x3FF; /* Max Packet Size is in range 0-1024 */\r
+\r
+ switch (TransferType) { // TODO should unify more, perharps later\r
+ case CONTROL_TRANSFER:\r
+ case BULK_TRANSFER:\r
+ ASSERT_STATUS_OK(AllocQhd(HostID, DeviceAddr, DeviceSpeed, EndpointNumber, TransferType, TransferDir,\r
+ MaxPacketSize, Interval, Mult, HSHubDevAddr, HSHubPortNum, &HeadIdx) );\r
+ DisableAsyncSchedule(HostID);\r
+ InsertLinkPointer(&HcdAsyncHead(HostID)->Horizontal, &HcdQHD(HostID, HeadIdx)->Horizontal, QHD_TYPE);\r
+ EnableAsyncSchedule(HostID);\r
+ break;\r
+\r
+ case INTERRUPT_TRANSFER:\r
+ ASSERT_STATUS_OK(AllocQhd(HostID, DeviceAddr, DeviceSpeed, EndpointNumber, TransferType, TransferDir,\r
+ MaxPacketSize, Interval, Mult, HSHubDevAddr, HSHubPortNum, &HeadIdx) );\r
+ DisablePeriodSchedule(HostID);\r
+ InsertLinkPointer(&HcdIntHead(HostID)->Horizontal, &HcdQHD(HostID, HeadIdx)->Horizontal, QHD_TYPE);\r
+ EnablePeriodSchedule(HostID);\r
+ memset(&PipeStreaming[HostID], 0, sizeof(Pipe_Stream_Handle_T));\r
+ break;\r
+\r
+ case ISOCHRONOUS_TRANSFER:\r
+#ifndef __TEST__\r
+ if (( DeviceSpeed == HIGH_SPEED) || ( TransferDir == IN_TRANSFER) ) { /* TODO currently not support HS due to lack of device for testing */\r
+ ASSERT_STATUS_OK_MESSAGE(HCD_STATUS_TRANSFER_TYPE_NOT_SUPPORTED,\r
+ "Highspeed ISO and ISO IN is not supported yet, due to lack of testing");\r
+ }\r
+#endif\r
+ ASSERT_STATUS_OK(AllocQhd(HostID, DeviceAddr, DeviceSpeed, EndpointNumber, TransferType, TransferDir,\r
+ MaxPacketSize, Interval, Mult, HSHubDevAddr, HSHubPortNum, &HeadIdx) );\r
+ EnablePeriodSchedule(HostID);\r
+ break;\r
+ }\r
+\r
+ PipehandleCreate(pPipeHandle, HostID, TransferType, HeadIdx);\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdClosePipe(uint32_t PipeHandle)\r
+{\r
+ uint8_t HostID, HeadIdx;\r
+ HCD_TRANSFER_TYPE XferType;\r
+\r
+ ASSERT_STATUS_OK(HcdCancelTransfer(PipeHandle) );\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &XferType, &HeadIdx) );\r
+\r
+ switch (XferType) {\r
+ case CONTROL_TRANSFER:\r
+ case BULK_TRANSFER:\r
+ case INTERRUPT_TRANSFER:\r
+ RemoveQueueHead(HostID, HeadIdx);\r
+ USB_REG(HostID)->USBCMD_H |= EHC_USBCMD_IntAsyncAdvanceDoorbell; /* DoorBell Handshake: Queue Head will only be free in AsyncAdvanceIsr */\r
+ break;\r
+\r
+ case ISOCHRONOUS_TRANSFER:\r
+ FreeQhd(HostID, HeadIdx);\r
+ DisablePeriodSchedule(HostID);\r
+ break;\r
+ }\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdCancelTransfer(uint32_t PipeHandle)\r
+{\r
+ uint8_t HostID, HeadIdx;\r
+ HCD_TRANSFER_TYPE XferType;\r
+\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &XferType, &HeadIdx) );\r
+\r
+ DisableSchedule(HostID, (XferType == INTERRUPT_TRANSFER) || (XferType == ISOCHRONOUS_TRANSFER) ? 1 : 0);\r
+\r
+ if (XferType == ISOCHRONOUS_TRANSFER) { /* ISOCHRONOUS_TRANSFER */\r
+ uint32_t i;\r
+ for (i = 0; i < FRAME_LIST_SIZE; i++) { /*-- Foreach link in Period List Base --*/\r
+ NextLinkPointer *pNextPointer = &EHCI_FRAME_LIST(HostID)[i];\r
+\r
+ /*-- Foreach Itd/SItd in the link--*/\r
+ while ( isValidLink(pNextPointer->Link) && pNextPointer->Type != QHD_TYPE) {\r
+ if (pNextPointer->Type == ITD_TYPE) { /*-- Highspeed ISO --*/\r
+ PHCD_HS_ITD pItd = (PHCD_HS_ITD) Align32(pNextPointer->Link);\r
+\r
+ if (HeadIdx == pItd->IhdIdx) {\r
+ /*-- remove matched ITD --*/\r
+ pNextPointer->Link = pItd->Horizontal.Link;\r
+ FreeHsItd(pItd);\r
+ continue; /*-- skip advance pNextPointer due to TD removal --*/\r
+ }\r
+ }\r
+ else if (pNextPointer->Type == SITD_TYPE) { /*-- Split ISO --*/\r
+ PHCD_SITD pSItd = (PHCD_SITD) Align32(pNextPointer->Link);\r
+\r
+ if (HeadIdx == pSItd->IhdIdx) {\r
+ /*-- removed matched SITD --*/\r
+ pNextPointer->Link = pSItd->Horizontal.Link;\r
+ FreeSItd(pSItd);\r
+ continue; /*-- skip advance pNextPointer due to TD removal --*/\r
+ }\r
+ }\r
+ pNextPointer = (NextLinkPointer *) Align32(pNextPointer->Link);\r
+ }\r
+ }\r
+ }\r
+ else { /*-- Bulk / Control / Interrupt --*/\r
+ uint32_t TdLink = HcdQHD(HostID, HeadIdx)->FirstQtd;\r
+\r
+ /*-- Foreach Qtd in Qhd --*/ /*---------- Deactivate all queued TDs ----------*/\r
+ while ( isValidLink(TdLink) ) {\r
+ PHCD_QTD pQtd = (PHCD_QTD) Align32(TdLink);\r
+ TdLink = pQtd->NextQtd;\r
+\r
+ pQtd->Active = 0;\r
+ pQtd->IntOnComplete = 0;/* no interrupt scenario on this TD */\r
+ FreeQtd(pQtd);\r
+ }\r
+ HcdQHD(HostID, HeadIdx)->FirstQtd = LINK_TERMINATE;\r
+ }\r
+\r
+ EnableSchedule(HostID, (XferType == INTERRUPT_TRANSFER) || (XferType == ISOCHRONOUS_TRANSFER) ? 1 : 0);\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdControlTransfer(uint32_t PipeHandle,\r
+ const USB_Request_Header_t *const pDeviceRequest,\r
+ uint8_t *const buffer)\r
+{\r
+ uint8_t HostID, QhdIdx;\r
+ HCD_TRANSFER_TYPE XferType;\r
+ uint32_t SetupTdIdx, DataTdIdx, StatusTdIdx;\r
+ uint8_t direction;\r
+ uint32_t Datalength;\r
+\r
+ if ((pDeviceRequest == NULL) || (buffer == NULL)) {\r
+ ASSERT_STATUS_OK_MESSAGE(HCD_STATUS_PARAMETER_INVALID, "Device Request or Data Buffer is NULL");\r
+ }\r
+\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &XferType, &QhdIdx) );\r
+\r
+ Datalength = pDeviceRequest->wLength;\r
+ direction = pDeviceRequest->bmRequestType & 0x80;\r
+\r
+ /*---------- Setup Stage ----------*/\r
+ ASSERT_STATUS_OK(AllocQTD(HostID, &SetupTdIdx, (uint8_t *) pDeviceRequest, 8, SETUP_TRANSFER, 0, 0) ); /* Setup TD: DirectionPID=00 - DataToggle=10b (always DATA0) */\r
+\r
+ /*---------- Data Stage ----------*/\r
+ if (Datalength) {\r
+ ASSERT_STATUS_OK(AllocQTD(HostID, &DataTdIdx, buffer, Datalength, direction ? IN_TRANSFER : OUT_TRANSFER, 1, 0) );\r
+ }\r
+ else {\r
+ DataTdIdx = SetupTdIdx; /* Data TD is skipped */\r
+ }\r
+\r
+ /*---------- Status Stage ----------*/\r
+ ASSERT_STATUS_OK(AllocQTD(HostID, &StatusTdIdx, NULL, 0, direction ? OUT_TRANSFER : IN_TRANSFER, 1, 1) ); /* Status TD: Direction=opposite of data direction - DataToggle=11b (always DATA1) */\r
+\r
+ /* Hook TDs Together */\r
+ HcdQTD(HostID, SetupTdIdx)->NextQtd = (uint32_t) HcdQTD(HostID, DataTdIdx);\r
+ HcdQTD(HostID, DataTdIdx)->NextQtd = (uint32_t) HcdQTD(HostID, StatusTdIdx);\r
+\r
+ HcdQHD(HostID, QhdIdx)->status = (uint32_t) HCD_STATUS_TRANSFER_QUEUED;\r
+\r
+ /* Hook TDs to QHD */\r
+ HcdQHD(HostID, QhdIdx)->FirstQtd = Align32( (uint32_t) HcdQTD(HostID, SetupTdIdx) );\r
+ HcdQHD(HostID, QhdIdx)->Overlay.NextQtd = (uint32_t) HcdQTD(HostID, SetupTdIdx);\r
+\r
+ /* wait for semaphore compete TDs */\r
+ ASSERT_STATUS_OK(WaitForTransferComplete(HostID, QhdIdx) );\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdDataTransfer(uint32_t PipeHandle,\r
+ uint8_t *const buffer,\r
+ uint32_t const length,\r
+ uint16_t *const pActualTransferred)\r
+{\r
+ uint8_t HostID, HeadIdx;\r
+ HCD_TRANSFER_TYPE XferType;\r
+ uint32_t DataTdIdx;\r
+ uint32_t ExpectedLength;\r
+\r
+ if ((buffer == NULL) || (length == 0)) {\r
+ ASSERT_STATUS_OK_MESSAGE(HCD_STATUS_PARAMETER_INVALID, "Data Buffer is NULL or Transfer Length is 0");\r
+ }\r
+\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &XferType, &HeadIdx) );\r
+\r
+ ExpectedLength = (length != HCD_ENDPOINT_MAXPACKET_XFER_LEN) ? length : HcdQHD(HostID, HeadIdx)->MaxPackageSize;\r
+\r
+ HcdQHD(HostID, HeadIdx)->status = (uint32_t) HCD_STATUS_TRANSFER_QUEUED;\r
+\r
+ if (XferType == ISOCHRONOUS_TRANSFER) {\r
+ if ( HcdQHD(HostID, HeadIdx)->EndpointSpeed == HIGH_SPEED ) { /*-- Highspeed ISO --*/\r
+ ASSERT_STATUS_OK(QueueITDs(HostID, HeadIdx, buffer, ExpectedLength) );\r
+ }\r
+ else { /*-- Full/Low Speed ISO --*/\r
+ ASSERT_STATUS_OK(QueueSITDs(HostID, HeadIdx, buffer, ExpectedLength) );\r
+ }\r
+ }\r
+ else { /*-- Control / Bulk / Interrupt --*/\r
+ if(XferType == BULK_TRANSFER)\r
+ {\r
+ ASSERT_STATUS_OK( QueueQTDs(HostID, &DataTdIdx, buffer, ExpectedLength,\r
+ HcdQHD(HostID,HeadIdx)->Direction ? IN_TRANSFER : OUT_TRANSFER, 0) );\r
+ }\r
+ else\r
+ {\r
+ ASSERT_STATUS_OK(AllocQTD(HostID, &DataTdIdx, buffer, ExpectedLength,\r
+ HcdQHD(HostID, HeadIdx)->Direction ? IN_TRANSFER : OUT_TRANSFER, 0, 1) );\r
+ }\r
+ /*---------- Hook to Queue Head ----------*/\r
+ HcdQHD(HostID, HeadIdx)->FirstQtd = Align32( (uint32_t) HcdQTD(HostID, DataTdIdx) ); /* used as TD head to clean up TD chain when transfer done */\r
+ HcdQHD(HostID, HeadIdx)->Overlay.NextQtd = (uint32_t) HcdQTD(HostID, DataTdIdx);\r
+ }\r
+\r
+ HcdQHD(HostID, HeadIdx)->pActualTransferCount = pActualTransferred; /* TODO Actual Length get rid of this */\r
+ if (HcdQHD(HostID, HeadIdx)->pActualTransferCount) {\r
+ *(HcdQHD(HostID, HeadIdx)->pActualTransferCount) = ExpectedLength;\r
+ }\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdGetPipeStatus(uint32_t PipeHandle)/* TODO can be implemented based on overlay */\r
+{\r
+ uint8_t HostID, HeadIdx;\r
+ HCD_TRANSFER_TYPE XferType;\r
+\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &XferType, &HeadIdx) );\r
+\r
+ return (HCD_STATUS)HcdQHD(HostID, HeadIdx)->status;\r
+}\r
+\r
+static void FreeQhd(uint8_t HostID, uint8_t QhdIdx)\r
+{\r
+ HcdQHD(HostID, QhdIdx)->status = HCD_STATUS_STRUCTURE_IS_FREE;\r
+ HcdQHD(HostID, QhdIdx)->Horizontal.Link |= LINK_TERMINATE;\r
+ HcdQHD(HostID, QhdIdx)->inUse = 0;\r
+}\r
+\r
+static HCD_STATUS AllocQhd(uint8_t HostID,\r
+ uint8_t DeviceAddr,\r
+ HCD_USB_SPEED DeviceSpeed,\r
+ uint8_t EndpointNumber,\r
+ HCD_TRANSFER_TYPE TransferType,\r
+ HCD_TRANSFER_DIR TransferDir,\r
+ uint16_t MaxPacketSize,\r
+ uint8_t Interval,\r
+ uint8_t Mult,\r
+ uint8_t HSHubDevAddr,\r
+ uint8_t HSHubPortNum,\r
+ uint32_t *pQhdIdx)\r
+{\r
+ /* Looking for a free QHD */\r
+ for ( (*pQhdIdx) = 0; (*pQhdIdx) < HCD_MAX_QTD && HcdQHD(HostID, *pQhdIdx)->inUse; (*pQhdIdx)++) {}\r
+\r
+ if ((*pQhdIdx) == HCD_MAX_QTD ) {\r
+ return HCD_STATUS_NOT_ENOUGH_ENDPOINT;\r
+ }\r
+\r
+ memset(HcdQHD(HostID, *pQhdIdx), 0, sizeof(HCD_QHD) );\r
+\r
+ /* Init Data For Queue Head */\r
+ HcdQHD(HostID, *pQhdIdx)->inUse = 1;\r
+ HcdQHD(HostID, *pQhdIdx)->Direction = (TransferDir == IN_TRANSFER) ? 1 : 0; /* Control Endpoint should not use this parameter */\r
+ HcdQHD(HostID, *pQhdIdx)->Interval = Interval;\r
+ HcdQHD(HostID, *pQhdIdx)->status = HCD_STATUS_OK;\r
+ HcdQHD(HostID, *pQhdIdx)->FirstQtd = LINK_TERMINATE;\r
+\r
+ HcdQHD(HostID, *pQhdIdx)->Horizontal.Link = LINK_TERMINATE;\r
+ HcdQHD(HostID, *pQhdIdx)->DeviceAddress = DeviceAddr;\r
+\r
+ HcdQHD(HostID, *pQhdIdx)->InActiveOnNextTransaction = 0;\r
+ HcdQHD(HostID, *pQhdIdx)->EndpointNumber = EndpointNumber;\r
+ HcdQHD(HostID, *pQhdIdx)->EndpointSpeed = (uint32_t) DeviceSpeed;\r
+ HcdQHD(HostID, *pQhdIdx)->DataToggleControl = (TransferType == CONTROL_TRANSFER) ? 1 : 0;\r
+ HcdQHD(HostID, *pQhdIdx)->HeadReclamationFlag = 0;\r
+ HcdQHD(HostID, *pQhdIdx)->MaxPackageSize = MaxPacketSize;\r
+ HcdQHD(HostID,\r
+ *pQhdIdx)->ControlEndpointFlag = (DeviceSpeed != HIGH_SPEED && TransferType == CONTROL_TRANSFER) ? 1 : 0;\r
+ HcdQHD(HostID, *pQhdIdx)->NakCountReload = 0; /* infinite NAK/NYET */\r
+\r
+ /*-- Currently All interrupt endpoints will be served as 1 (micro)frame polling, thus Interval parameter is ignored --*/\r
+ /*-- For High Speed Interval should be used to compute the uFrameSMask --*/\r
+ HcdQHD(HostID,\r
+ *pQhdIdx)->uFrameSMask =\r
+ (TransferType == INTERRUPT_TRANSFER) ? (DeviceSpeed == HIGH_SPEED ? 0xFF : 0x01) : 0;\r
+ HcdQHD(HostID,\r
+ *pQhdIdx)->uFrameCMask = (DeviceSpeed != HIGH_SPEED && TransferType == INTERRUPT_TRANSFER) ? 0x1C : 0; /*-- Schedule Complete Split at uFrame2, uFrame3 and uFrame4 --*/\r
+ HcdQHD(HostID, *pQhdIdx)->HubAddress = HSHubDevAddr;\r
+ HcdQHD(HostID, *pQhdIdx)->PortNumber = HSHubPortNum;\r
+ HcdQHD(HostID, *pQhdIdx)->Mult = (DeviceSpeed == HIGH_SPEED ? Mult : 1);\r
+\r
+ HcdQHD(HostID, *pQhdIdx)->Overlay.NextQtd = LINK_TERMINATE;\r
+ HcdQHD(HostID, *pQhdIdx)->Overlay.AlterNextQtd = LINK_TERMINATE;\r
+ HcdQHD(HostID, *pQhdIdx)->FirstQtd = LINK_TERMINATE;\r
+\r
+ HcdQHD(HostID,\r
+ *pQhdIdx)->Overlay.PingState_Err =\r
+ (DeviceSpeed == HIGH_SPEED && TransferType != INTERRUPT_TRANSFER && TransferDir == OUT_TRANSFER) ? 1 : 0;\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static HCD_STATUS InsertLinkPointer(NextLinkPointer *pList, NextLinkPointer *pNew, uint8_t type)\r
+{\r
+ pNew->Link = pList->Link;\r
+ pList->Link = Align32( (uint32_t) pNew);\r
+ pList->Type = type;\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static HCD_STATUS RemoveQueueHead(uint8_t HostID, uint8_t QhdIdx)\r
+{\r
+ PHCD_QHD pQhd = IsInterruptQhd(HostID, QhdIdx) ? HcdIntHead(HostID) : HcdAsyncHead(HostID);\r
+ /*-- Foreach Qhd in async list --*/\r
+ while ( isValidLink(pQhd->Horizontal.Link) &&\r
+ Align32(pQhd->Horizontal.Link) != (uint32_t) HcdQHD(HostID, QhdIdx) &&\r
+ Align32(pQhd->Horizontal.Link) != (uint32_t) HcdAsyncHead(HostID) ) {\r
+ pQhd = (PHCD_QHD) Align32(pQhd->Horizontal.Link);\r
+ }\r
+ if ( Align32(pQhd->Horizontal.Link) != (uint32_t) HcdQHD(HostID, QhdIdx) ) {\r
+ return HCD_STATUS_PARAMETER_INVALID;\r
+ }\r
+\r
+ HcdQHD(HostID, QhdIdx)->status = (uint32_t) HCD_STATUS_TO_BE_REMOVED; /* Will be remove in AsyncAdvanceIsr - make use of IAAD */\r
+ pQhd->Horizontal.Link = HcdQHD(HostID, QhdIdx)->Horizontal.Link;\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+/*---------- Queue TD Routines ----------*/\r
+static void FreeQtd(PHCD_QTD pQtd)\r
+{\r
+ pQtd->NextQtd |= LINK_TERMINATE;\r
+ pQtd->inUse = 0;\r
+}\r
+\r
+/** Direction, DataToggle parameter only has meaning for control transfer, for other transfer use 0 for these paras */\r
+static HCD_STATUS AllocQTD(uint8_t HostID,\r
+ uint32_t *pTdIdx,\r
+ uint8_t *const BufferPointer,\r
+ uint32_t xferLen,\r
+ HCD_TRANSFER_DIR PIDCode,\r
+ uint8_t DataToggle,\r
+ uint8_t IOC)\r
+{\r
+ for ((*pTdIdx) = 0; (*pTdIdx) < HCD_MAX_QTD && HcdQTD(HostID, *pTdIdx)->inUse; (*pTdIdx)++) {}\r
+\r
+ if ((*pTdIdx) < HCD_MAX_QTD) {\r
+ uint8_t idx = 1;\r
+ uint32_t BytesInPage;\r
+\r
+ memset(HcdQTD(HostID, *pTdIdx), 0, sizeof(HCD_QTD));\r
+\r
+ HcdQTD(HostID, *pTdIdx)->NextQtd = 1;\r
+\r
+ HcdQTD(HostID, *pTdIdx)->AlterNextQtd = LINK_TERMINATE;\r
+ HcdQTD(HostID, *pTdIdx)->inUse = 1;\r
+\r
+ HcdQTD(HostID, *pTdIdx)->Active = 1;\r
+ HcdQTD(HostID, *pTdIdx)->PIDCode = (PIDCode == SETUP_TRANSFER) ? 2 : (PIDCode == IN_TRANSFER ? 1 : 0);\r
+ HcdQTD(HostID, *pTdIdx)->TotalBytesToTransfer = xferLen;\r
+ HcdQTD(HostID, *pTdIdx)->DataToggle = DataToggle;\r
+ HcdQTD(HostID, *pTdIdx)->IntOnComplete = IOC;\r
+\r
+ HcdQTD(HostID, *pTdIdx)->BufferPointer[0] = (uint32_t) BufferPointer;\r
+ BytesInPage = 0x1000 - Offset4k((uint32_t) BufferPointer);\r
+ xferLen -= MIN(xferLen, BytesInPage); /*-- Trim down xferlen to be multiple of 4k --*/\r
+\r
+ for (idx = 1; idx <= 4 && xferLen > 0; idx++) {\r
+ HcdQTD(HostID,\r
+ *pTdIdx)->BufferPointer[idx] = Align4k(HcdQTD(HostID, (*pTdIdx))->BufferPointer[idx - 1]) + 0x1000;\r
+ xferLen -= MIN(xferLen, 0x1000);\r
+ }\r
+ return HCD_STATUS_OK;\r
+ }\r
+ else {\r
+ return HCD_STATUS_NOT_ENOUGH_QTD;\r
+ }\r
+}\r
+\r
+static HCD_STATUS QueueQTDs (uint8_t HostID,\r
+ uint32_t* pTdIdx,\r
+ uint8_t* dataBuff,\r
+ uint32_t xferLen,\r
+ HCD_TRANSFER_DIR PIDCode,\r
+ uint8_t DataToggle)\r
+{\r
+ uint32_t TailTdIdx=0xFFFFFFFF;\r
+\r
+ while (xferLen > 0)\r
+ {\r
+ uint32_t TdLen;\r
+ uint32_t MaxTDLen = QTD_MAX_XFER_LENGTH - Offset4k((uint32_t)dataBuff);\r
+\r
+ if(PipeStreaming[HostID].PacketSize > 0)\r
+ TdLen = MIN(xferLen, PipeStreaming[HostID].PacketSize);\r
+ else\r
+ TdLen = MIN(xferLen, MaxTDLen);\r
+ xferLen -= TdLen;\r
+\r
+ if (TailTdIdx == 0xFFFFFFFF)\r
+ {\r
+ ASSERT_STATUS_OK ( AllocQTD(HostID, pTdIdx, dataBuff, TdLen, PIDCode, DataToggle, (xferLen==0) ? 1 : 0) );\r
+ TailTdIdx = *pTdIdx;\r
+ }\r
+ else\r
+ {\r
+ uint32_t NewTdIDx;\r
+ if(HCD_STATUS_OK == AllocQTD(HostID, &NewTdIDx, dataBuff, TdLen, PIDCode, DataToggle, (xferLen==0) ? 1 : 0))\r
+ {\r
+ HcdQTD(HostID,TailTdIdx)->NextQtd = Align32((uint32_t) HcdQTD(HostID,NewTdIDx));\r
+ TailTdIdx = NewTdIDx;\r
+ }\r
+ else\r
+ {\r
+ PipeStreaming[HostID].BufferAddress = (uint32_t)dataBuff;\r
+ PipeStreaming[HostID].RemainBytes = xferLen + TdLen;\r
+ PipeStreaming[HostID].DataToggle = DataToggle;\r
+ HcdQTD(HostID,HCD_MAX_QTD - 1)->IntOnComplete = 1;\r
+ break;\r
+ }\r
+ }\r
+ if(DataToggle == 1) DataToggle = 0;\r
+ else DataToggle = 1;\r
+ dataBuff += TdLen;\r
+ }\r
+ if(xferLen == 0)\r
+ {\r
+ memset(&PipeStreaming[HostID], 0, sizeof(Pipe_Stream_Handle_T));\r
+ }\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static void FreeHsItd(PHCD_HS_ITD pItd)\r
+{\r
+ pItd->Horizontal.Link |= LINK_TERMINATE;\r
+ pItd->inUse = 0;\r
+}\r
+\r
+HCD_STATUS AllocHsItd(uint8_t HostID,\r
+ uint32_t *pTdIdx,\r
+ uint8_t IhdIdx,\r
+ uint8_t *dataBuff,\r
+ uint32_t TDLen,\r
+ uint8_t XactPerITD,\r
+ uint8_t IntOnComplete)\r
+{\r
+ for ((*pTdIdx) = 0; (*pTdIdx) < HCD_MAX_HS_ITD && HcdHsITD(HostID, *pTdIdx)->inUse; (*pTdIdx)++) {}\r
+ if ((*pTdIdx) < HCD_MAX_HS_ITD) {\r
+ uint8_t i;\r
+ uint8_t XactStep = 8 / XactPerITD;\r
+ uint32_t MaxXactLen = HcdQHD(HostID, IhdIdx)->MaxPackageSize * HcdQHD(HostID, IhdIdx)->Mult;\r
+\r
+ memset(HcdHsITD(HostID, *pTdIdx), 0, sizeof(HCD_HS_ITD));\r
+\r
+ HcdHsITD(HostID, *pTdIdx)->inUse = 1;\r
+ HcdHsITD(HostID, *pTdIdx)->IhdIdx = IhdIdx;\r
+\r
+ HcdHsITD(HostID, *pTdIdx)->Horizontal.Link = LINK_TERMINATE;\r
+ for (i = 0; TDLen > 0 && i < 8; i += XactStep) {\r
+ uint32_t XactLen = MIN(TDLen, MaxXactLen);\r
+ TDLen -= XactLen;\r
+\r
+ HcdHsITD(HostID, *pTdIdx)->BufferPointer[i] = Align4k( (uint32_t) dataBuff);\r
+\r
+ HcdHsITD(HostID, *pTdIdx)->Transaction[i].Offset = ( (uint32_t) dataBuff ) & 4095;\r
+ HcdHsITD(HostID, *pTdIdx)->Transaction[i].PageSelect = i;\r
+ HcdHsITD(HostID, *pTdIdx)->Transaction[i].IntOnComplete = (IntOnComplete && TDLen == 0) ? 1 : 0;\r
+ HcdHsITD(HostID, *pTdIdx)->Transaction[i].Length = XactLen;\r
+ HcdHsITD(HostID, *pTdIdx)->Transaction[i].Active = 1;\r
+\r
+ dataBuff += XactLen;\r
+ }\r
+\r
+ HcdHsITD(HostID, *pTdIdx)->BufferPointer[0] |= (HcdQHD(HostID, IhdIdx)->EndpointNumber << 8) | HcdQHD(HostID,\r
+ IhdIdx)->\r
+ DeviceAddress;\r
+ HcdHsITD(HostID,\r
+ *pTdIdx)->BufferPointer[1] |=\r
+ (HcdQHD(HostID, IhdIdx)->Direction << 1) | HcdQHD(HostID, IhdIdx)->MaxPackageSize;\r
+ HcdHsITD(HostID, *pTdIdx)->BufferPointer[2] |= HcdQHD(HostID, IhdIdx)->Mult;\r
+\r
+ return HCD_STATUS_OK;\r
+ }\r
+ else {\r
+ return HCD_STATUS_NOT_ENOUGH_HS_ITD;\r
+ }\r
+}\r
+\r
+static HCD_STATUS QueueITDs(uint8_t HostID, uint8_t IhdIdx, uint8_t *dataBuff, uint32_t xferLen)\r
+{\r
+ uint32_t MaxTDLen;\r
+ uint32_t FrameIdx;\r
+\r
+#if 0 /* Maximum bandwidth (Interval = 1) regardless of Interval value */\r
+ uint8_t XactPerITD;\r
+ uint32_t FramePeriod;\r
+ if (HcdQHD(IhdIdx)->Interval < 4) { /*-- Period < 8 --*/\r
+ XactPerITD = 1 << ( 4 - HcdQHD(IhdIdx)->Interval ); /*-- Interval 1 => 8, 2 => 4, 3 => 2 --*/\r
+ FramePeriod = 1;\r
+ }\r
+ else {\r
+ XactPerITD = 1;\r
+ FramePeriod = 1 << ( HcdQHD(IhdIdx)->Interval - 4 ); /*-- Frame step 4 => 1, 5 => 2, 6 => 3 --*/\r
+ }\r
+#else\r
+ #define XactPerITD 8\r
+ #define FramePeriod 1\r
+#endif\r
+\r
+ MaxTDLen = XactPerITD * HcdQHD(HostID, IhdIdx)->MaxPackageSize * HcdQHD(HostID, IhdIdx)->Mult;\r
+ FrameIdx = USB_REG(HostID)->FRINDEX_H >> 3;\r
+\r
+ if (xferLen > MaxTDLen * FRAME_LIST_SIZE) { /*-- Data length overflow the Period FRAME LIST --*/\r
+ ASSERT_STATUS_OK_MESSAGE(\r
+ HCD_STATUS_DATA_OVERFLOW,\r
+ "ISO data length overflows the Period Frame List size, Please increase size by FRAMELIST_SIZE_BITS or reduce data length");\r
+ }\r
+\r
+ while (xferLen > 0) {\r
+ uint32_t TdIdx;\r
+ uint32_t TDLen;\r
+\r
+ TDLen = MIN(xferLen, MaxTDLen);\r
+ xferLen -= TDLen;\r
+\r
+ ASSERT_STATUS_OK(AllocHsItd(HostID, &TdIdx, IhdIdx, dataBuff, TDLen, XactPerITD, xferLen ? 0 : 1) );\r
+\r
+ FrameIdx = (FrameIdx + FramePeriod) % FRAME_LIST_SIZE;\r
+ /*-- Hook ITD to Period List Base --*/\r
+ InsertLinkPointer(&EHCI_FRAME_LIST(HostID)[FrameIdx], &HcdHsITD(HostID, TdIdx)->Horizontal, ITD_TYPE);\r
+ dataBuff += TDLen;\r
+ }\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static void FreeSItd(PHCD_SITD pSItd)\r
+{\r
+ pSItd->Horizontal.Link |= LINK_TERMINATE;\r
+ pSItd->inUse = 0;\r
+}\r
+\r
+static HCD_STATUS AllocSItd(uint8_t HostID,\r
+ uint32_t *pTdIdx,\r
+ uint8_t HeadIdx,\r
+ uint8_t *dataBuff,\r
+ uint32_t TDLen,\r
+ uint8_t IntOnComplete)\r
+{\r
+#define TCount_Pos 0\r
+#define TPos_Pos 3\r
+\r
+ for ((*pTdIdx) = 0; (*pTdIdx) < HCD_MAX_SITD && HcdSITD(HostID, *pTdIdx)->inUse; (*pTdIdx)++) {}\r
+\r
+ if ((*pTdIdx) < HCD_MAX_SITD) {\r
+ uint8_t TCount = TDLen / SPLIT_MAX_LEN_UFRAME + (TDLen % SPLIT_MAX_LEN_UFRAME ? 1 : 0); /*-- Number of Split Transactions --*/\r
+\r
+ memset(HcdSITD(HostID, *pTdIdx), 0, sizeof(HCD_SITD) );\r
+\r
+ HcdSITD(HostID, *pTdIdx)->inUse = 1;\r
+ HcdSITD(HostID, *pTdIdx)->IhdIdx = HeadIdx;\r
+\r
+ /*-- Word 1 --*/\r
+ HcdSITD(HostID, *pTdIdx)->Horizontal.Link = LINK_TERMINATE;\r
+ /*-- Word 2 --*/\r
+ HcdSITD(HostID, *pTdIdx)->DeviceAddress = HcdQHD(HostID, HeadIdx)->DeviceAddress;\r
+ HcdSITD(HostID, *pTdIdx)->EndpointNumber = HcdQHD(HostID, HeadIdx)->EndpointNumber;\r
+ HcdSITD(HostID, *pTdIdx)->HubAddress = HcdQHD(HostID, HeadIdx)->HubAddress;\r
+ HcdSITD(HostID, *pTdIdx)->PortNumber = HcdQHD(HostID, HeadIdx)->PortNumber;\r
+ HcdSITD(HostID, *pTdIdx)->Direction = HcdQHD(HostID, HeadIdx)->Direction;\r
+ /*-- Word 3 --*/\r
+ HcdSITD(HostID, *pTdIdx)->uFrameSMask = (1 << TCount) - 1;\r
+ HcdSITD(HostID, *pTdIdx)->uFrameCMask = 0;\r
+ /*-- Word 4 --*/\r
+ HcdSITD(HostID, *pTdIdx)->Active = 1;\r
+ HcdSITD(HostID, *pTdIdx)->TotalBytesToTransfer = TDLen;\r
+ HcdSITD(HostID, *pTdIdx)->IntOnComplete = IntOnComplete;\r
+ /*-- Word 5 --*/\r
+ HcdSITD(HostID, *pTdIdx)->BufferPointer[0] = (uint32_t) dataBuff;\r
+ /*-- Word 6 --*/\r
+ HcdSITD(HostID, *pTdIdx)->BufferPointer[1] = Align4k( ((uint32_t) dataBuff) + TDLen);\r
+\r
+ HcdSITD(HostID, *pTdIdx)->BufferPointer[1] |= TCount << TCount_Pos;\r
+ HcdSITD(HostID, *pTdIdx)->BufferPointer[1] |= (TCount > 1 ? 1 : 0 ) << TPos_Pos;/*-- TPosition - More than 1 split --> Begin Encoding, Otherwise All Encoding --*/\r
+\r
+ // HcdSITD(*pTdIdx)->TCount = NoSplits;\r
+ // HcdSITD(*pTdIdx)->TPosition = (NoSplits > 1) ? 1 : 0 ; /*-- TPosition - More than 1 split --> Begin Encoding, Otherwise All Encoding --*/\r
+\r
+ /*-- Word 7 --*/\r
+ HcdSITD(HostID, *pTdIdx)->BackPointer = LINK_TERMINATE;\r
+\r
+ return HCD_STATUS_OK;\r
+ }\r
+ else {\r
+ return HCD_STATUS_NOT_ENOUGH_SITD;\r
+ }\r
+}\r
+\r
+static HCD_STATUS QueueSITDs(uint8_t HostID, uint8_t HeadIdx, uint8_t *dataBuff, uint32_t xferLen)\r
+{\r
+ uint32_t FrameIdx;\r
+\r
+#if 0 /* Maximum bandwidth (Interval = 1) regardless of Interval value */\r
+ uint8_t XactPerITD;\r
+ uint32_t FramePeriod;\r
+ if (HcdQHD(IhdIdx)->Interval < 4) { /*-- Period < 8 --*/\r
+ FramePeriod = 1;\r
+ }\r
+ else {\r
+ FramePeriod = 1 << ( HcdQHD(IhdIdx)->Interval - 4 ); /*-- Frame step 4 => 1, 5 => 2, 6 => 3 --*/\r
+ }\r
+#else\r
+ #define FramePeriod 1\r
+#endif\r
+\r
+ if (xferLen > HcdQHD(HostID, HeadIdx)->MaxPackageSize * FRAME_LIST_SIZE) { /*-- Data length overflow the Period FRAME LIST --*/\r
+ ASSERT_STATUS_OK_MESSAGE(\r
+ HCD_STATUS_DATA_OVERFLOW,\r
+ "ISO data length overflows the Period Frame List size, Please increase size by FRAMELIST_SIZE_BITS or reduce data length");\r
+ }\r
+\r
+ FrameIdx = USB_REG(HostID)->FRINDEX_H >> 3;\r
+ while (xferLen) {\r
+ uint32_t TdIdx;\r
+ uint32_t TDLen;\r
+\r
+ TDLen = MIN(xferLen, HcdQHD(HostID, HeadIdx)->MaxPackageSize);\r
+ xferLen -= TDLen;\r
+\r
+ ASSERT_STATUS_OK(AllocSItd(HostID, &TdIdx, HeadIdx, dataBuff, TDLen, xferLen ? 0 : 1) );\r
+\r
+ FrameIdx = (FrameIdx + FramePeriod) % FRAME_LIST_SIZE;\r
+ /*-- Hook SITD to Period List Base --*/\r
+ InsertLinkPointer(&EHCI_FRAME_LIST(HostID)[FrameIdx], &HcdSITD(HostID, TdIdx)->Horizontal, SITD_TYPE);\r
+ dataBuff += TDLen;\r
+ }\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static HCD_STATUS WaitForTransferComplete(uint8_t HostID, uint8_t EdIdx)/* TODO indentical to OHCI now */\r
+{\r
+\r
+#ifndef __TEST__\r
+ while ( HcdQHD(HostID, EdIdx)->status == HCD_STATUS_TRANSFER_QUEUED ) {\r
+ /* Should have time-out but left blank intentionally for bug catcher */\r
+ }\r
+ return (HCD_STATUS) HcdQHD(HostID, EdIdx)->status;\r
+#else\r
+ return HCD_STATUS_OK;\r
+#endif\r
+\r
+}\r
+\r
+static HCD_STATUS PipehandleParse(uint32_t Pipehandle, uint8_t *pHostID, HCD_TRANSFER_TYPE *XferType, uint8_t *pIdx)\r
+{\r
+ Pipe_Handle_T *pHandle = (Pipe_Handle_T *) (&Pipehandle);\r
+\r
+ if ((pHandle->HostId >= MAX_USB_CORE) ||\r
+ ( pHandle->Idx >= HCD_MAX_QTD) ||\r
+ ( HcdQHD(pHandle->HostId, pHandle->Idx)->inUse == 0) ||\r
+ ( HcdQHD(pHandle->HostId, pHandle->Idx)->status == HCD_STATUS_TO_BE_REMOVED) ) {\r
+ return HCD_STATUS_PIPEHANDLE_INVALID;\r
+ }\r
+\r
+ if (pHostID) {\r
+ *pHostID = pHandle->HostId;\r
+ }\r
+ if (pIdx) {\r
+ *pIdx = pHandle->Idx;\r
+ }\r
+ if (XferType) {\r
+ *XferType = (HCD_TRANSFER_TYPE) pHandle->Type;\r
+ }\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static void PipehandleCreate(uint32_t *pPipeHandle, uint8_t HostID, HCD_TRANSFER_TYPE XferType, uint8_t idx)\r
+{\r
+ /*---------- HostID | PortNum | Type | Idx ----------*/\r
+ Pipe_Handle_T *pHandle = (Pipe_Handle_T *) pPipeHandle;\r
+\r
+ pHandle->HostId = HostID;\r
+ pHandle->PortNumber = 0;\r
+ pHandle->Type = (uint8_t) XferType;\r
+ pHandle->Idx = idx;\r
+}\r
+\r
+static __INLINE PHCD_QHD HcdAsyncHead(uint8_t HostID)\r
+{\r
+ return &(ehci_data[HostID].AsyncHeadQhd);\r
+ // return &(ehci_data.AsyncHeadQhd);\r
+}\r
+\r
+static __INLINE PHCD_QHD HcdIntHead(uint8_t HostID)\r
+{\r
+ return &(ehci_data[HostID].IntHeadQhd);\r
+ // return &(ehci_data.IntHeadQhd);\r
+}\r
+\r
+// === TODO: Deal with HostID later ===\r
+static __INLINE PHCD_QHD HcdQHD(uint8_t HostID, uint8_t idx)\r
+{\r
+ return &(ehci_data[HostID].qHDs[idx]);\r
+ // return &(ehci_data.qHDs[idx]);\r
+}\r
+\r
+static __INLINE PHCD_QTD HcdQTD(uint8_t HostID, uint8_t idx)\r
+{\r
+ return &(ehci_data[HostID].qTDs[idx]);\r
+ // return &(ehci_data.qTDs[idx]);\r
+}\r
+\r
+static __INLINE PHCD_SITD HcdSITD(uint8_t HostID, uint8_t idx)\r
+{\r
+ return &(ehci_data[HostID].siTDs[idx]);\r
+ // return &(ehci_data.siTDs[idx]);\r
+}\r
+\r
+static __INLINE PHCD_HS_ITD HcdHsITD(uint8_t HostID, uint8_t idx)\r
+{\r
+ return &(ehci_data[HostID].iTDs[idx]);\r
+ // return &(ehci_data.iTDs[idx]);\r
+}\r
+\r
+static __INLINE bool isValidLink(uint32_t link)\r
+{\r
+ return (link & LINK_TERMINATE) == 0;\r
+}\r
+\r
+static __INLINE bool IsInterruptQhd(uint8_t HostID, uint8_t QhdIdx)\r
+{\r
+ return HcdQHD(HostID, QhdIdx)->uFrameSMask;\r
+}\r
+\r
+void HcdIrqHandler(uint8_t HostID)\r
+{\r
+ uint32_t IntStatus;\r
+ uint32_t t = USB_REG(HostID)->USBINTR_H;\r
+ IntStatus = USB_REG(HostID)->USBSTS_H & t;\r
+\r
+ if (IntStatus == 0) {\r
+ return;\r
+ }\r
+\r
+ /* disable all interrupt for processing */\r
+ /* Acknowledge Interrrupt */\r
+ USB_REG(HostID)->USBSTS_H |= IntStatus;\r
+\r
+ /* Process Interrupt Sources */\r
+ if (IntStatus & EHC_USBSTS_PortChangeDetect) {\r
+ uint32_t PortSC = USB_REG(HostID)->PORTSC1_H;\r
+ if (PortSC & EHC_PORTSC_ConnectStatusChange) {\r
+ PortStatusChangeIsr(HostID, PortSC & EHC_PORTSC_CurrentConnectStatus);\r
+ USB_REG(HostID)->PORTSC1_H |= EHC_PORTSC_ConnectStatusChange; /* Clear PortSC Interrupt Status */\r
+ }\r
+ if (PortSC & EHC_PORTSC_PortEnableChange) {\r
+ USB_REG(HostID)->PORTSC1_H |= EHC_PORTSC_PortEnableChange; /* Clear PortSC Interrupt Status */\r
+ }\r
+ if (PortSC & EHC_PORTSC_OvercurrentChange) {\r
+ USB_REG(HostID)->PORTSC1_H |= EHC_PORTSC_OvercurrentChange; /* Clear PortSC Interrupt Status */\r
+ }\r
+ if (PortSC & EHC_PORTSC_ForcePortResume) {\r
+ USB_REG(HostID)->PORTSC1_H |= EHC_PORTSC_ForcePortResume; /* Clear PortSC Interrupt Status */\r
+ }\r
+ }\r
+\r
+ if (IntStatus & EHC_USBSTS_UsbAsyncInt) {\r
+ AsyncScheduleIsr(HostID);\r
+ }\r
+\r
+ if (IntStatus & EHC_USBSTS_UsbPeriodInt) {\r
+ PeriodScheduleIsr(HostID);\r
+ }\r
+\r
+ if (IntStatus & EHC_USBSTS_UsbErrorInt) {\r
+ UsbErrorIsr(HostID);\r
+ }\r
+\r
+ if (IntStatus & EHC_USBSTS_IntAsyncAdvance) {\r
+ AsyncAdvanceIsr(HostID);\r
+ }\r
+ /* Enable Interrupt */\r
+}\r
+\r
+static void RemoveCompletedQTD(uint8_t HostID, PHCD_QHD pQhd)\r
+{\r
+ PHCD_QTD pQtd;\r
+ uint32_t TdLink = pQhd->FirstQtd;\r
+ bool is_data_remain = false;\r
+\r
+ /*-- Foreach Qtd in Qhd --*/\r
+ while( (isValidLink(TdLink), pQtd = (PHCD_QTD) Align32(TdLink) ) &&\r
+ pQtd->Active == 0)\r
+ {\r
+ TdLink = pQtd->NextQtd;\r
+\r
+ if(pQhd->pActualTransferCount)\r
+ *(pQhd->pActualTransferCount) -= pQtd->TotalBytesToTransfer;\r
+\r
+ if (pQtd->IntOnComplete)\r
+ {\r
+ if(PipeStreaming[HostID].RemainBytes > 0)\r
+ is_data_remain = true;\r
+ else\r
+ pQhd->status = HCD_STATUS_OK;\r
+ }\r
+ if (pQtd->Halted /*|| pQtd->Babble || pQtd->BufferError || pQtd->TransactionError*/)\r
+ {\r
+ pQhd->status = HCD_STATUS_TRANSFER_Stall;\r
+ }\r
+ FreeQtd(pQtd);\r
+ }\r
+ pQhd->FirstQtd = TdLink;\r
+ if(is_data_remain)\r
+ {\r
+ uint32_t pQtd;\r
+ QueueQTDs(HostID, &pQtd,(uint8_t*)PipeStreaming[HostID].BufferAddress,\r
+ PipeStreaming[HostID].RemainBytes,\r
+ pQhd->Direction ? IN_TRANSFER : OUT_TRANSFER,\r
+ PipeStreaming[HostID].DataToggle);\r
+ pQhd->FirstQtd = Align32( (uint32_t) HcdQTD(HostID,pQtd) );\r
+ pQhd->Overlay.NextQtd = (uint32_t) HcdQTD(HostID,pQtd);\r
+ } \r
+}\r
+\r
+static void RemoveErrorQTD(PHCD_QHD pQhd)\r
+{\r
+ PHCD_QTD pQtd;\r
+ uint32_t TdLink = pQhd->FirstQtd;\r
+ bool errorfound = false;\r
+\r
+ /*-- Scan error Qtd in Qhd --*/\r
+ while ( (isValidLink(TdLink), pQtd = (PHCD_QTD) Align32(TdLink) ) &&\r
+ pQtd->Active == 0) {\r
+ TdLink = pQtd->NextQtd;\r
+\r
+ if (pQtd->Halted /*|| pQtd->Babble || pQtd->BufferError || pQtd->TransactionError*/) {\r
+ errorfound = true;\r
+ pQhd->status = HCD_STATUS_TRANSFER_Stall;\r
+ }\r
+ }\r
+ /*-- Remove error Qtd in Qhd --*/\r
+ if (errorfound) {\r
+ TdLink = pQhd->FirstQtd;\r
+ while (isValidLink(TdLink)) {\r
+ pQtd = (PHCD_QTD) Align32(TdLink);\r
+ TdLink = pQtd->NextQtd;\r
+ pQtd->Active = 0;\r
+ pQtd->IntOnComplete = 0;\r
+ FreeQtd(pQtd);\r
+ }\r
+ pQhd->FirstQtd = LINK_TERMINATE;\r
+ pQhd->Overlay.Halted = 0;\r
+ }\r
+}\r
+\r
+/*---------- Interrupt On Compete has occurred, however we have no clues on which QueueHead it happened. Also IOC TD may be advanced already So we will free all TD which is not Active (transferred already) ----------*/\r
+static void AsyncScheduleIsr(uint8_t HostID)\r
+{\r
+ PHCD_QHD pQhd = HcdAsyncHead(HostID);\r
+\r
+ /*-- Foreach Qhd in async list --*/\r
+ while ( isValidLink(pQhd->Horizontal.Link) &&\r
+ Align32(pQhd->Horizontal.Link) != (uint32_t) HcdAsyncHead(HostID) ) {\r
+ pQhd = (PHCD_QHD) Align32(pQhd->Horizontal.Link);\r
+ RemoveCompletedQTD(HostID,pQhd);\r
+ }\r
+}\r
+\r
+static void PeriodScheduleIsr(uint8_t HostID)\r
+{\r
+ uint32_t i;\r
+\r
+ /*ISOCHRONOUS*/\r
+ for (i = 0; i < FRAME_LIST_SIZE; i++) { /*-- Foreach link in Period List Base --*/\r
+ NextLinkPointer *pNextPointer = &EHCI_FRAME_LIST(HostID)[i];\r
+\r
+ /*-- Foreach Itd/SItd in the link--*/\r
+ while ( isValidLink(pNextPointer->Link) && pNextPointer->Type != QHD_TYPE ) {\r
+ if (pNextPointer->Type == ITD_TYPE) { /*-- Highspeed ISO --*/\r
+ PHCD_HS_ITD pItd = (PHCD_HS_ITD) Align32(pNextPointer->Link);\r
+\r
+ if ((pItd->Transaction[0].Active == 0) && (pItd->Transaction[1].Active == 0) &&\r
+ ( pItd->Transaction[2].Active == 0) && ( pItd->Transaction[3].Active == 0) &&\r
+ ( pItd->Transaction[4].Active == 0) && ( pItd->Transaction[5].Active == 0) &&\r
+ ( pItd->Transaction[6].Active == 0) && ( pItd->Transaction[7].Active == 0) ) {\r
+ if ((pItd->Transaction[0].IntOnComplete == 1) || (pItd->Transaction[1].IntOnComplete == 1) ||\r
+ ( pItd->Transaction[2].IntOnComplete == 1) || ( pItd->Transaction[3].IntOnComplete == 1) ||\r
+ ( pItd->Transaction[4].IntOnComplete == 1) || ( pItd->Transaction[5].IntOnComplete == 1) ||\r
+ ( pItd->Transaction[6].IntOnComplete == 1) || ( pItd->Transaction[7].IntOnComplete == 1) ) {\r
+ /*-- request complete, signal on Iso Head --*/\r
+ HcdQHD(HostID, pItd->IhdIdx)->status = HCD_STATUS_OK;\r
+ }\r
+ /*-- remove executed ITD --*/\r
+ pNextPointer->Link = pItd->Horizontal.Link;\r
+ FreeHsItd(pItd);\r
+ continue; /*-- skip advance pNextPointer due to TD removal --*/\r
+ }\r
+ }\r
+ else if (pNextPointer->Type == SITD_TYPE) { /*-- Split ISO --*/\r
+ PHCD_SITD pSItd = (PHCD_SITD) Align32(pNextPointer->Link);\r
+\r
+ if (pSItd->Active == 0) {\r
+ if (pSItd->IntOnComplete) {\r
+ /*-- request complete, signal on Iso Head --*/\r
+ HcdQHD(HostID, pSItd->IhdIdx)->status = HCD_STATUS_OK;\r
+ }\r
+\r
+ /*-- removed executed SITD --*/\r
+ pNextPointer->Link = pSItd->Horizontal.Link;\r
+ FreeSItd(pSItd);\r
+ continue; /*-- skip advance pNextPointer due to TD removal --*/\r
+ }\r
+ }\r
+\r
+ pNextPointer = (NextLinkPointer *) Align32(pNextPointer->Link);\r
+ }\r
+ }\r
+\r
+ /*INTERRUPT*/\r
+ {\r
+ PHCD_QHD pQhd = HcdIntHead(HostID);\r
+\r
+ /*-- Foreach Qhd in list --*/\r
+ while ( isValidLink(pQhd->Horizontal.Link) ) {\r
+ pQhd = (PHCD_QHD) Align32(pQhd->Horizontal.Link);\r
+ RemoveCompletedQTD(HostID,pQhd);\r
+ }\r
+ }\r
+}\r
+\r
+static void UsbErrorIsr(uint8_t HostID)\r
+{\r
+ PHCD_QHD pQhd = HcdAsyncHead(HostID);\r
+\r
+ /*-- Foreach Qhd in async list --*/\r
+ while ( isValidLink(pQhd->Horizontal.Link) &&\r
+ Align32(pQhd->Horizontal.Link) != (uint32_t) HcdAsyncHead(HostID) ) {\r
+ pQhd = (PHCD_QHD) Align32(pQhd->Horizontal.Link);\r
+ RemoveErrorQTD(pQhd);\r
+ }\r
+}\r
+\r
+static HCD_STATUS PortStatusChangeIsr(uint8_t HostID, uint32_t deviceConnect)\r
+{\r
+ if (deviceConnect) {/* Device Attached */\r
+ USB_Host_Enumerate(HostID);\r
+ }\r
+ else { /* Device detached */\r
+ USB_Host_DeEnumerate(HostID);\r
+ }\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static void AsyncAdvanceIsr(uint8_t HostID)\r
+{\r
+ uint32_t QhdIdx;\r
+\r
+ for (QhdIdx = 0; QhdIdx < HCD_MAX_QHD; QhdIdx++)\r
+ if ((HcdQHD(HostID, QhdIdx)->inUse == 1) && (HcdQHD(HostID, QhdIdx)->status == HCD_STATUS_TO_BE_REMOVED)) {\r
+ FreeQhd(HostID, QhdIdx);\r
+ }\r
+}\r
+\r
+static __INLINE HCD_STATUS EHciHostRun(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->USBCMD_H |= EHC_USBCMD_RunStop;\r
+ while (USB_REG(HostID)->USBSTS_H & EHC_USBSTS_HCHalted) {}\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS EHciHostStop(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->USBCMD_H &= ~EHC_USBCMD_RunStop;\r
+ while ( !(USB_REG(HostID)->USBSTS_H & EHC_USBSTS_HCHalted) ) {}\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS EHciHostReset(uint8_t HostID)\r
+{\r
+ if (USB_REG(HostID)->USBSTS_H & EHC_USBSTS_HCHalted) {\r
+ EHciHostStop(HostID);\r
+ }\r
+\r
+ USB_REG(HostID)->USBCMD_H |= EHC_USBCMD_HostReset;\r
+ while ( USB_REG(HostID)->USBCMD_H & EHC_USBCMD_HostReset ) {}\r
+\r
+ /* Program the controller to be the USB host controller, this can only be done after Reset */\r
+ USB_REG(HostID)->USBMODE_H = 0x23; // USBMODE_HostController | USBMODE_VBusPowerSelect_High;\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS EHciHostInit(uint8_t HostID)\r
+{\r
+ uint32_t idx;\r
+\r
+ /*---------- Host Data Structure Init ----------*/\r
+ // memset(&ehci_data[HostID], 0, sizeof(EHCI_HOST_DATA_T) );\r
+\r
+ /*---------- USBINT ----------*/\r
+ USB_REG(HostID)->USBINTR_H &= ~EHC_USBINTR_ALL; /* Disable All Interrupt */\r
+ USB_REG(HostID)->USBSTS_H &= ~EHC_USBINTR_ALL; /* Clear All Interrupt Status */\r
+ USB_REG(HostID)->USBINTR_H = EHC_USBINTR_UsbAsyncEnable | EHC_USBINTR_UsbPeriodEnable | /* Enable necessary interrupt source: Async Advance, System Error, Port Change, USB Error, USB Int */\r
+ EHC_USBINTR_PortChangeIntEnable | EHC_USBINTR_UsbErroIntEnable |\r
+ EHC_USBINTR_IntAsyncAdvanceEnable |\r
+ (INT_FRAME_ROLL_OVER_ENABLE ? EHC_USBINTR_FrameListRolloverEnable : 0);\r
+\r
+ /*---------- Asynchronous List ----------*/\r
+ /*-- Static Head Qhd with Halted/inactive --*/\r
+ HcdAsyncHead(HostID)->Horizontal.Link = Align32( (uint32_t) HcdAsyncHead(HostID) );\r
+ HcdAsyncHead(HostID)->Horizontal.Type = QHD_TYPE;\r
+ HcdAsyncHead(HostID)->HeadReclamationFlag = 1;\r
+ HcdAsyncHead(HostID)->Overlay.NextQtd = LINK_TERMINATE; /* Terminate Links */\r
+ HcdAsyncHead(HostID)->Overlay.AlterNextQtd = LINK_TERMINATE; /* Terminate Links */\r
+ HcdAsyncHead(HostID)->Overlay.Halted = 1;\r
+\r
+ USB_REG(HostID)->ASYNCLISTADDR = (uint32_t) HcdAsyncHead(HostID);\r
+\r
+ /*---------- Periodic List ----------*/\r
+ /*-- Static Interrupt Qhd (1 ms) --*/\r
+ HcdIntHead(HostID)->Horizontal.Link = LINK_TERMINATE;\r
+ HcdIntHead(HostID)->Overlay.NextQtd = LINK_TERMINATE; /* Terminate Links */\r
+ HcdIntHead(HostID)->Overlay.AlterNextQtd = LINK_TERMINATE; /* Terminate Links */\r
+ HcdIntHead(HostID)->Overlay.Halted = 1;\r
+ HcdIntHead(HostID)->uFrameSMask = 1;\r
+\r
+ for (idx = 0; idx < FRAME_LIST_SIZE; idx++) { /* Attach 1 ms Interrupt Qhd to Period Frame List */\r
+ EHCI_FRAME_LIST(HostID)[idx].Link = Align32( (uint32_t) HcdIntHead(HostID) );\r
+ EHCI_FRAME_LIST(HostID)[idx].Type = QHD_TYPE;\r
+ }\r
+\r
+ USB_REG(HostID)->PERIODICLISTBASE = Align4k( (uint32_t) EHCI_FRAME_LIST(HostID) );\r
+\r
+ /*---------- USBCMD ----------*/\r
+ USB_REG(HostID)->USBCMD_H = EHC_USBCMD_AsynScheduleEnable |\r
+ ((FRAMELIST_SIZE_BITS % 4) << 2) | ((FRAMELIST_SIZE_BITS / 4) << 15);\r
+\r
+ /*---------- CONFIGFLAG ----------*/\r
+ /* LPC18xx doesn't has CONFIGFLAG register */\r
+\r
+ /*---------- Power On RhPort ----------*/\r
+ USB_REG(HostID)->PORTSC1_H |= EHC_PORTSC_PortPowerControl;\r
+\r
+ EHciHostRun(HostID);/* Run The HC */\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE void DisableSchedule(uint8_t HostID, uint8_t isPeriod)\r
+{\r
+ uint32_t statusMask = isPeriod ? EHC_USBSTS_PeriodScheduleStatus : EHC_USBSTS_AsyncScheduleStatus;\r
+ uint32_t cmdMask = isPeriod ? EHC_USBCMD_PeriodScheduleEnable : EHC_USBCMD_AsynScheduleEnable;\r
+\r
+ if (USB_REG(HostID)->USBSTS_H & statusMask) {\r
+ USB_REG(HostID)->USBCMD_H &= ~cmdMask;\r
+ while (USB_REG(HostID)->USBSTS_H & statusMask) {} /* TODO Should have time-out */\r
+ }\r
+}\r
+\r
+static __INLINE void EnableSchedule(uint8_t HostID, uint8_t isPeriod)\r
+{\r
+ uint32_t statusMask = isPeriod ? EHC_USBSTS_PeriodScheduleStatus : EHC_USBSTS_AsyncScheduleStatus;\r
+ uint32_t cmdMask = isPeriod ? EHC_USBCMD_PeriodScheduleEnable : EHC_USBCMD_AsynScheduleEnable;\r
+\r
+ if (!(USB_REG(HostID)->USBSTS_H & statusMask)) {\r
+ USB_REG(HostID)->USBCMD_H |= cmdMask;\r
+ while (!(USB_REG(HostID)->USBSTS_H & statusMask)) {}/* TODO Should have time-out */\r
+ }\r
+}\r
+\r
+static void DisableAsyncSchedule(uint8_t HostID)\r
+{\r
+ DisableSchedule(HostID, 0);\r
+}\r
+\r
+static void EnableAsyncSchedule(uint8_t HostID)\r
+{\r
+ EnableSchedule(HostID, 0);\r
+}\r
+\r
+static void DisablePeriodSchedule(uint8_t HostID)\r
+{\r
+ DisableSchedule(HostID, 1);\r
+}\r
+\r
+static void EnablePeriodSchedule(uint8_t HostID)\r
+{\r
+ EnableSchedule(HostID, 1);\r
+}\r
+\r
+void HcdSetStreamPacketSize(uint32_t PipeHandle, uint16_t packetsize)\r
+{\r
+ uint8_t HostID = 0, HeadIdx;\r
+ HCD_TRANSFER_TYPE XferType;\r
+\r
+ PipehandleParse(PipeHandle, &HostID, &XferType, &HeadIdx);\r
+\r
+ PipeStreaming[HostID].PacketSize = packetsize;\r
+}\r
+\r
+#endif // __LPC_EHCI__\r
--- /dev/null
+/*\r
+ * @brief Enhanced Host Controller Interface\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+/** @ingroup Group_HCD\r
+ * @defgroup Host_EHCI Enhanced Host Controller Interface Driver\r
+ * @{\r
+ */\r
+#ifndef __LPC_EHCI_H__\r
+#define __LPC_EHCI_H__\r
+\r
+#ifndef __LPC_EHCI_C__ // TODO INCLUDE FROM EHCI.C\r
+ #error "EHCI.h is private header and can only be included by EHCI.c, try to include HCD.h instead"\r
+#endif\r
+\r
+#ifdef __TEST__ // suppress static/inline for Testing purpose\r
+ #define static\r
+ #define inline\r
+#endif\r
+\r
+/*=======================================================================*/\r
+/* EHCI C O N F I G U R A T I O N */\r
+/*=======================================================================*/\r
+#define HCD_MAX_QHD HCD_MAX_ENDPOINT /* USBD_USB_HC_EHCI */\r
+//#define HCD_MAX_QTD (HCD_MAX_ENDPOINT+3) /* USBD_USB_HC_EHCI */\r
+#define HCD_MAX_QTD 8 /* USBD_USB_HC_EHCI */\r
+#define HCD_MAX_HS_ITD 4 /* USBD_USB_HC_EHCI */\r
+#define HCD_MAX_SITD 16 /* USBD_USB_HC_EHCI */\r
+\r
+#define FRAMELIST_SIZE_BITS 5 /* (0:1024) - (1:512) - (2:256) - (3:128) - (4:64) - (5:32) - (6:16) - (7:8) */\r
+#define FRAME_LIST_SIZE (1024 >> FRAMELIST_SIZE_BITS)\r
+\r
+/**********************/\r
+/* USBCMD Register */\r
+/**********************/\r
+#define INT_THRESHOLD_CTRL 0x00080000UL/* Max Int Interval = 8 uframes */\r
+#define ASYNC_SCHEDULE_PARK_MODE_ENABLE NO\r
+#define ASYNC_SCHEDULE_PARK_MODE_COUNT 0\r
+\r
+/****************************/\r
+/* USBSTS Register */\r
+/****************************/\r
+\r
+/**************************************************/\r
+/* USBINTR Register */\r
+/**************************************************/\r
+#define INT_SOF_RECEIVED_ENABLE NO\r
+// #define INT_ASYNC_ADVANCE_ENABLE Must be YES\r
+// #define INT_SYSTEM_ERR_ENABLE Must be YES\r
+#define INT_FRAME_ROLL_OVER_ENABLE NO\r
+// #define INT_PORT_CHANGE_ENABLE Must be YES\r
+// #define INT_USB_ERR_ENABLE Must be YES\r
+// #define INT_USB_ENABLE Must be YES (NO for NXP chips in favor of UAI, UPI)\r
+// #define INT_USB_ASYNC_INT_ENABLE Must be YES\r
+// #define INT_USB_PERIOD_INT_ENABLE Must be YES\r
+\r
+/********************************************/\r
+/* PORTSC Register */\r
+/********************************************/\r
+#define PORT_WAKE_OVER_CURRENT NO\r
+#define PORT_WAKE_ON_DISCONNECT NO\r
+#define PORT_WAKE_ON_CONNECT NO\r
+#define PORT_INDICATOR NO\r
+\r
+/*==========================================================================*/\r
+/* EHCI LOCAL DECLARATIONS */\r
+/*==========================================================================*/\r
+\r
+/*==========================================================================*/\r
+/* EHCI REGISTERS */\r
+/*==========================================================================*/\r
+/* Bit field definition for USBMODE_H */\r
+#define USBMODE_DeviceController (2)\r
+#define USBMODE_HostController (3)\r
+#define USBMODE_VBusPowerSelect_High (1 << 5)\r
+\r
+/* Bit field definition for register UsbCmd */\r
+#define EHC_USBCMD_RunStop 0x00000001UL /* Run or Stop */\r
+#define EHC_USBCMD_HostReset 0x00000002UL /* Host Controller Reset */\r
+#define EHC_USBCMD_FrameListSize 0x0000000CUL /* Frame List Size */\r
+#define EHC_USBCMD_PeriodScheduleEnable 0x00000010UL /* Periodic Schedule Enable */\r
+#define EHC_USBCMD_AsynScheduleEnable 0x00000020UL /* Asynchronous Schedule Enable */\r
+#define EHC_USBCMD_IntAsyncAdvanceDoorbell 0x00000040UL /* Interrupt on Async Advance Doorbell */\r
+#define EHC_USBCMD_LightReset 0x00000080UL /* Light Host Controller Reset */\r
+#define EHC_USBCMD_AsyncScheduleParkCount 0x00000300UL /* Asynchronous Schedule Park Mode Count */\r
+#define EHC_USBCMD_AsyncScheduleParkEnable 0x00000800UL /* Asynchronous Schedule Park Mode Enable */\r
+#define EHC_USBCMD_FrameListSizeBit2 0x00008000UL /* Frame List Size bit 2 - EHCI derivation */\r
+#define EHC_USBCMD_InterruptThresholdControl 0x00FF0000UL /* Interrupt Threshold control */\r
+\r
+/* Bit field definition for register UsbStatus */\r
+#define EHC_USBSTS_UsbInt 0x00000001UL /* USB Interrupt */\r
+#define EHC_USBSTS_UsbErrorInt 0x00000002UL /* USB Error Interrupt */\r
+#define EHC_USBSTS_PortChangeDetect 0x00000004UL /* Port Change Detect */\r
+#define EHC_USBSTS_FrameListRollover 0x00000008UL /* Frame List Rollover */\r
+#define EHC_USBSTS_HostSystemError 0x00000010UL /* Host System Error */\r
+#define EHC_USBSTS_IntAsyncAdvance 0x00000020UL /* Interrupt on Async Advance */\r
+#define EHC_USBSTS_SofRecieveInt 0x00000080UL /* SOF - EHCI derivation */\r
+#define EHC_USBSTS_HCHalted 0x00001000UL /* HCHalted */\r
+#define EHC_USBSTS_Reclamation 0x00002000UL /* Reclamation */\r
+#define EHC_USBSTS_PeriodScheduleStatus 0x00004000UL /* Periodic Schedule Status */\r
+#define EHC_USBSTS_AsyncScheduleStatus 0x00008000UL /* Asynchronous Schedule Status */\r
+#define EHC_USBSTS_UsbAsyncInt 0x00040000UL /* USB Asynchronous Interrupt - EHCI derivation */\r
+#define EHC_USBSTS_UsbPeriodInt 0x00080000UL /* USB Period Interrupt - EHCI derivation */\r
+\r
+/* Bit field definition for register UsbIntr */\r
+#define EHC_USBINTR_UsbIntEnable 0x00000001UL /* USB Interrupt Enable */\r
+#define EHC_USBINTR_UsbErroIntEnable 0x00000002UL /* USB Error Interrupt Enable */\r
+#define EHC_USBINTR_PortChangeIntEnable 0x00000004UL /* Port Change Interrupt Enable */\r
+#define EHC_USBINTR_FrameListRolloverEnable 0x00000008UL /* Frame List Rollover Enable */\r
+#define EHC_USBINTR_HostSystemErrorEnable 0x00000010UL /* Host System Error Enable */\r
+#define EHC_USBINTR_IntAsyncAdvanceEnable 0x00000020UL /* Interrupt on Async Advance Enable */\r
+#define EHC_USBINTR_SofRecieveEnable 0x00000080UL /* SOF - EHCI derivation */\r
+#define EHC_USBINTR_UsbAsyncEnable 0x00040000UL /* USB Asynchronous Interrupt - EHCI derivation */\r
+#define EHC_USBINTR_UsbPeriodEnable 0x00080000UL /* USB Period Interrupt - EHCI derivation */\r
+#define EHC_USBINTR_ALL 0x000C00BFUL /* All Interrupt */\r
+\r
+/* Bit field definition for register FrIndex */\r
+#define EHC_FRINDEX_MASK 0x000003FFUL /* Frame Index */\r
+#define EHC_UFRAME_MASK 0x00000007UL /* u-Frame Index */\r
+#define EHC_MFRAME_MASK 0x00001FF8UL /* m-Frame Index */\r
+\r
+/* Bit field definition for register PortSC */\r
+#define EHC_PORTSC_CurrentConnectStatus 0x00000001UL /* Current Connect Status */\r
+#define EHC_PORTSC_ConnectStatusChange 0x00000002UL /* Connect Status Change */\r
+#define EHC_PORTSC_PortEnable 0x00000004UL /* Port Enabled Status */\r
+#define EHC_PORTSC_PortEnableChange 0x00000008UL /* Port Enabled/Disabled Change */\r
+#define EHC_PORTSC_OvercurrentActive 0x00000010UL /* Over-current Status */\r
+#define EHC_PORTSC_OvercurrentChange 0x00000020UL /* Over-current Change */\r
+#define EHC_PORTSC_ForcePortResume 0x00000040UL /* Force Port Resume */\r
+#define EHC_PORTSC_PortSuspend 0x00000080UL /* Port Suspend */\r
+#define EHC_PORTSC_PortReset 0x00000100UL /* Port Reset */\r
+#define EHC_PORTSC_LineStatus 0x00000C00UL /* Line Status */\r
+#define EHC_PORTSC_PortPowerControl 0x00001000UL /* Port Power Status */\r
+#define EHC_PORTSC_PortOwner 0x00002000UL /* Port Owner Status */\r
+#define EHC_PORTSC_PortIndicatorControl 0x0000C000UL /* Port Indicator Control */\r
+#define EHC_PORTSC_PortTestControl 0x000F0000UL /* Port Test Control */\r
+#define EHC_PORTSC_WakeonConnectEnable 0x00100000UL /* Wake on Connect Enable */\r
+#define EHC_PORTSC_WakeonDisconnectEnable 0x00200000UL /* Wake on Disconnect Enable */\r
+#define EHC_PORTSC_WakeonOvercurrentEnable 0x00400000UL /* Wake on Over-Current Enable */\r
+#define EHC_PORTSC_PhyClockDisable 0x00800000UL /* PHY Clock Disable - EHCI derivation */\r
+#define EHC_PORTSC_PortForceFullspeedConnect 0x01000000UL /* Force Device on Fullspeed mode (disable chirp sequences) - EHCI derivation */\r
+#define EHC_PORTSC_PortSpeed 0x0C000000UL /* Device Speed - EHCI derivation */\r
+\r
+/* Definitions for Frame List Element Pointer */\r
+#define QTD_MAX_XFER_LENGTH 0x5000\r
+#define FRAMELIST_ALIGNMENT 4096 /* Frame List Alignment */\r
+//#define LINK_TERMINATE 0x01\r
+#define SPLIT_MAX_LEN_UFRAME 188\r
+\r
+/*=======================================================================*/\r
+/* E H C I S T R U C T U R E S */\r
+/*=======================================================================*/\r
+\r
+/* Memory for EHCI Structures, docs for more information */\r
+\r
+typedef union un_EHCD_Link {\r
+ uint32_t Link;\r
+ struct {\r
+ uint32_t Terminate : 1;\r
+ uint32_t Type : 2;\r
+ };\r
+\r
+} NextLinkPointer;\r
+\r
+typedef struct st_EHCD_QTD {\r
+ /*---------- Word 1 ----------*/\r
+ uint32_t NextQtd;\r
+\r
+ /*---------- Word 2 ----------*/\r
+ /*-- Take advantage of this to store HCD information --*/\r
+ union {\r
+ uint32_t AlterNextQtd;\r
+ struct {\r
+ uint32_t Terminate : 1;\r
+ uint32_t : 4;\r
+\r
+ // === TODO: used reserved space, need to move to other place ===\r
+ /*-- HCD Area --*/\r
+ uint32_t inUse : 1;\r
+ uint32_t : 0;\r
+ };\r
+\r
+ };\r
+\r
+ /*---------- Word 3 ----------*/\r
+ /* Status [7:0] */\r
+ __IO uint32_t PingState_Err : 1;\r
+ __IO uint32_t SplitXstate : 1;\r
+ __IO uint32_t MissedUframe : 1;\r
+ __IO uint32_t TransactionError : 1;\r
+ __IO uint32_t Babble : 1;\r
+ __IO uint32_t BufferError : 1;\r
+ __IO uint32_t Halted : 1;\r
+ __IO uint32_t Active : 1;\r
+\r
+ uint32_t PIDCode : 2;\r
+ __IO uint32_t ErrorCounter : 2;\r
+ __IO uint32_t CurrentPage : 3;\r
+ uint32_t IntOnComplete : 1;\r
+ __IO uint32_t TotalBytesToTransfer : 15;\r
+ __IO uint32_t DataToggle : 1;\r
+ uint32_t : 0;/* Force next member on next storage unit */\r
+ /*---------- End Word 3 ----------*/\r
+\r
+ /*---------- Buffer Pointer Word 4-7 ----------*/\r
+ uint32_t BufferPointer[5];\r
+} HCD_QTD, *PHCD_QTD; // TODO: because QTD is used to declare overlay in HCD_QHD, we cannot put aligned 32 here ATTR_ALIGNED(32)\r
+\r
+typedef struct st_EHCD_QHD {\r
+ /*---------- Word 1 ----------*/\r
+ NextLinkPointer Horizontal;\r
+\r
+ /*---------- Word 2 ----------*/\r
+ uint32_t DeviceAddress : 7;\r
+ uint32_t InActiveOnNextTransaction : 1;\r
+ uint32_t EndpointNumber : 4;\r
+ uint32_t EndpointSpeed : 2;\r
+ uint32_t DataToggleControl : 1;\r
+ uint32_t HeadReclamationFlag : 1;\r
+ uint32_t MaxPackageSize : 11;\r
+ uint32_t ControlEndpointFlag : 1;\r
+ uint32_t NakCountReload : 4;\r
+ uint32_t : 0;/* Force next member on next storage unit */\r
+ /*---------- End Word 2 ----------*/\r
+\r
+ /*---------- Word 3 ----------*/\r
+ uint32_t uFrameSMask : 8;\r
+ uint32_t uFrameCMask : 8;\r
+ uint32_t HubAddress : 7;\r
+ uint32_t PortNumber : 7;\r
+ uint32_t Mult : 2;\r
+ uint32_t : 0;/* Force next member on next storage unit */\r
+ /*---------- End Word 3 ----------*/\r
+\r
+ /*---------- Word 4 ----------*/\r
+ __IO uint32_t CurrentQtd;\r
+\r
+ /*---------- Overlay Area ----------*/\r
+ __IO HCD_QTD Overlay;\r
+\r
+ /*---------- HCD Area : 16 Bytes----------*/\r
+ uint32_t inUse : 1;\r
+ uint32_t Direction : 2;\r
+ uint32_t Interval : 5;\r
+ uint32_t ListIndex : 20;/* not support full period list */\r
+ uint32_t : 0;/* Force next member on next storage unit */\r
+\r
+ __IO uint32_t status; // TODO will remove __IO after remove all HcdQHD function\r
+ uint32_t FirstQtd; /* used as TD head to clean up TD chain when transfer done */\r
+ uint16_t *pActualTransferCount; /* total transferred bytes of a usb request */\r
+} ATTR_ALIGNED (32) HCD_QHD, *PHCD_QHD;\r
+\r
+typedef struct st_EHCD_ITD {\r
+ /*---------- Word 1 ----------*/\r
+ NextLinkPointer Horizontal;\r
+\r
+ /*---------- Word 2-9 ----------*/\r
+ struct {\r
+ __IO uint32_t Offset : 12;\r
+ __IO uint32_t PageSelect : 3;\r
+ uint32_t IntOnComplete : 1;\r
+ __IO uint32_t Length : 12;\r
+ /*-- status [31:28] --*/\r
+ __IO uint32_t Error : 1;\r
+ __IO uint32_t Babble : 1;\r
+ __IO uint32_t BufferError : 1;\r
+ __IO uint32_t Active : 1;\r
+ } Transaction[8];\r
+\r
+ /*---------- Word 10-16 ----------*/\r
+ uint32_t BufferPointer[7];\r
+\r
+ // FIXME: refractor to save memory HCD Area\r
+ /*---------- HCD Area ----------*/\r
+ uint32_t inUse;\r
+ uint32_t IhdIdx;\r
+ uint32_t reserved[6];\r
+} ATTR_ALIGNED (32) HCD_HS_ITD, *PHCD_HS_ITD;\r
+\r
+typedef struct st_EHCD_SITD {\r
+ NextLinkPointer Horizontal;\r
+\r
+ /*---------- Word 2: static endpoint ----------*/\r
+ uint32_t DeviceAddress : 7;\r
+ uint32_t : 1;\r
+ uint32_t EndpointNumber : 4;\r
+ uint32_t : 4;\r
+ uint32_t HubAddress : 7;\r
+ uint32_t : 1;\r
+ uint32_t PortNumber : 7;\r
+ uint32_t Direction : 1;\r
+ uint32_t : 0;/* Force next member on next storage unit */\r
+ /*---------- End Word 2 ----------*/\r
+\r
+ /*---------- Word 3: Slipt Mask ----------*/\r
+ uint8_t uFrameSMask;\r
+ uint8_t uFrameCMask;\r
+ uint16_t reserved; /* Force next member on next storage unit */\r
+ /*---------- End Word 3 ----------*/\r
+\r
+ /*---------- Word 4: ----------*/\r
+ /* Status [7:0] */\r
+ __IO uint32_t : 1;\r
+ __IO uint32_t SplitXstate : 1;\r
+ __IO uint32_t MissedUframe : 1;\r
+ __IO uint32_t TransactionError : 1;\r
+ __IO uint32_t Babble : 1;\r
+ __IO uint32_t BufferError : 1;\r
+ __IO uint32_t ERR : 1;\r
+ __IO uint32_t Active : 1;\r
+\r
+ __IO uint32_t uFrameCProgMask : 8;\r
+ __IO uint32_t TotalBytesToTransfer : 10;\r
+ __IO uint32_t : 4;\r
+ __IO uint32_t PageSelect : 1;\r
+ uint32_t IntOnComplete : 1;\r
+ uint32_t : 0;\r
+ /*---------- End Word 4 ----------*/\r
+\r
+ /*---------- Word 5-6 ----------*/\r
+ uint32_t BufferPointer[2]; /*-- in BufferPointer[1] TP: Transaction Position - T-Count: Transaction Count --*/\r
+\r
+ // union{\r
+ // uint32_t BufferPointer1;\r
+ // struct {\r
+ // __IO uint32_t TCount : 3;\r
+ // __IO uint32_t TPosition : 2;\r
+ // };\r
+ // };\r
+\r
+ /*---------- Word 7 ----------*/\r
+ uint32_t BackPointer;\r
+\r
+ /*-- HCD ARERA 4 bytes --*/\r
+ uint8_t inUse;\r
+ uint8_t IhdIdx;\r
+ uint8_t reserved2[2];\r
+} ATTR_ALIGNED (32) HCD_SITD, *PHCD_SITD;\r
+\r
+typedef struct st_EHCI_HOST_DATA {\r
+ HCD_HS_ITD iTDs[HCD_MAX_HS_ITD]; /* Iso Transfer Descriptor */\r
+ HCD_QHD AsyncHeadQhd; /* Serve as H-Queue Head in Async Schedule */\r
+ HCD_QHD IntHeadQhd; /* Serve as Static 1ms Interrupt Heads */\r
+ HCD_QHD qHDs[HCD_MAX_QHD]; /* Queue Head */\r
+ HCD_QTD qTDs[HCD_MAX_QTD]; /* Queue Transfer Descriptor (Queue Element) */\r
+ HCD_SITD siTDs[HCD_MAX_SITD]; /* Split Iso Transfer Descriptor */\r
+} EHCI_HOST_DATA_T;\r
+\r
+typedef enum {\r
+ ITD_TYPE = 0,\r
+ QHD_TYPE,\r
+ SITD_TYPE,\r
+ FSTN_TYPE\r
+} TD_TYPE;\r
+\r
+typedef struct st_PipeHandle {\r
+ uint8_t Idx;\r
+ uint8_t Type;\r
+ uint8_t PortNumber;\r
+ uint8_t HostId;\r
+} Pipe_Handle_T;\r
+\r
+typedef struct st_PipeStreamHandle {\r
+ uint32_t BufferAddress;\r
+ uint32_t RemainBytes;\r
+ uint16_t PacketSize;\r
+ uint8_t DataToggle;\r
+} Pipe_Stream_Handle_T;\r
+\r
+/*=======================================================================*/\r
+/* LOCAL S Y M B O L D E C L A R A T I O N S */\r
+/*=======================================================================*/\r
+extern EHCI_HOST_DATA_T ehci_data[MAX_USB_CORE];\r
+// extern EHCI_HOST_DATA_T ehci_data;\r
+extern NextLinkPointer PeriodFrameList0[FRAME_LIST_SIZE]; /* Period Frame List */\r
+extern NextLinkPointer PeriodFrameList1[FRAME_LIST_SIZE]; /* Period Frame List */\r
+#define EHCI_FRAME_LIST(HostID) ((HostID) ? PeriodFrameList1 : PeriodFrameList0 )\r
+\r
+/*=======================================================================*/\r
+/* G L O B A L S Y M B O L D E C L A R A T I O N S */\r
+/*=======================================================================*/\r
+void USB_Host_Enumerate (uint8_t HostID);\r
+\r
+void USB_Host_DeEnumerate(uint8_t HostID);\r
+\r
+/*=======================================================================*/\r
+/* L O C A L F U N C T I O N P R O T O T Y P E S */\r
+/*=======================================================================*/\r
+/********************************* HOST API *********************************/\r
+static INLINE HCD_STATUS EHciHostInit(uint8_t HostID);\r
+\r
+static INLINE HCD_STATUS EHciHostRun(uint8_t HostID);\r
+\r
+static INLINE HCD_STATUS EHciHostStop(uint8_t HostID);\r
+\r
+static INLINE HCD_STATUS EHciHostReset(uint8_t HostID);\r
+\r
+static void DisableAsyncSchedule(uint8_t HostID);\r
+\r
+static void EnableAsyncSchedule(uint8_t HostID);\r
+\r
+#if !defined(__ICCARM__)\r
+static void DisablePeriodSchedule(uint8_t HostID) __attribute__ ((unused)); // TODO temporarily suppress unused warnnings for DisablePeriodSchedule & EnablePeriodSchedule\r
+\r
+static void EnablePeriodSchedule(uint8_t HostID) __attribute__ ((unused)); // TODO temporarily suppress unused warnnings for DisablePeriodSchedule & EnablePeriodSchedule\r
+\r
+#else\r
+static void DisablePeriodSchedule(uint8_t HostID); // TODO temporarily suppress unused warnnings for DisablePeriodSchedule & EnablePeriodSchedule\r
+\r
+static void EnablePeriodSchedule(uint8_t HostID); // TODO temporarily suppress unused warnnings for DisablePeriodSchedule & EnablePeriodSchedule\r
+\r
+#endif\r
+static INLINE void DisableSchedule(uint8_t HostID, uint8_t isPeriod);\r
+\r
+static INLINE void EnableSchedule(uint8_t HostID, uint8_t isPeriod);\r
+\r
+/********************************* HELPER *********************************/\r
+static INLINE PHCD_QHD HcdAsyncHead(uint8_t HostID);\r
+\r
+static INLINE PHCD_QHD HcdIntHead(uint8_t HostID);\r
+\r
+static INLINE PHCD_QHD HcdQHD(uint8_t HostID, uint8_t idx);\r
+\r
+static INLINE PHCD_QTD HcdQTD(uint8_t HostID, uint8_t idx);\r
+\r
+static INLINE PHCD_HS_ITD HcdHsITD(uint8_t HostID, uint8_t idx);\r
+\r
+static INLINE PHCD_SITD HcdSITD(uint8_t HostID, uint8_t idx);\r
+\r
+static INLINE bool isValidLink(uint32_t link);\r
+\r
+static INLINE bool IsInterruptQhd (uint8_t HostID, uint8_t QhdIdx);\r
+\r
+/********************************* Queue Head & Queue TD *********************************/\r
+static void FreeQhd(uint8_t HostID, uint8_t QhdIdx);\r
+\r
+static HCD_STATUS AllocQhd(uint8_t HostID,\r
+ uint8_t DeviceAddr,\r
+ HCD_USB_SPEED DeviceSpeed,\r
+ uint8_t EndpointNumber,\r
+ HCD_TRANSFER_TYPE TransferType,\r
+ HCD_TRANSFER_DIR TransferDir,\r
+ uint16_t MaxPacketSize,\r
+ uint8_t Interval,\r
+ uint8_t Mult,\r
+ uint8_t HSHubDevAddr,\r
+ uint8_t HSHubPortNum,\r
+ uint32_t *pQhdIdx);\r
+\r
+static HCD_STATUS InsertLinkPointer(NextLinkPointer *pList, NextLinkPointer *pNew, uint8_t type);\r
+\r
+static HCD_STATUS RemoveQueueHead(uint8_t HostID, uint8_t QhdIdx);\r
+\r
+static void FreeQtd(PHCD_QTD pQtd);\r
+\r
+static HCD_STATUS AllocQTD (uint8_t HostID,\r
+ uint32_t *pTdIdx,\r
+ uint8_t *const BufferPointer,\r
+ uint32_t xferLen,\r
+ HCD_TRANSFER_DIR PIDCode,\r
+ uint8_t DataToggle,\r
+ uint8_t IOC);\r
+\r
+static HCD_STATUS QueueQTDs (uint8_t HostID,\r
+ uint32_t* pTdIdx,\r
+ uint8_t* dataBuff,\r
+ uint32_t xferLen,\r
+ HCD_TRANSFER_DIR PIDCode,\r
+ uint8_t DataToggle);\r
+\r
+/********************************* ISO Head & ISO TD & Split ISO *********************************/\r
+static void FreeHsItd(PHCD_HS_ITD pItd);\r
+\r
+static HCD_STATUS AllocHsItd(uint8_t HostID,\r
+ uint32_t *pTdIdx,\r
+ uint8_t IhdIdx,\r
+ uint8_t *dataBuff,\r
+ uint32_t TDLen,\r
+ uint8_t XactPerITD,\r
+ uint8_t IntOnComplete);\r
+\r
+static HCD_STATUS QueueITDs(uint8_t HostID, uint8_t IhdIdx, uint8_t *dataBuff, uint32_t xferLen);\r
+\r
+static void FreeSItd(PHCD_SITD pSItd);\r
+\r
+static HCD_STATUS AllocSItd(uint8_t HostID,\r
+ uint32_t *TdIdx,\r
+ uint8_t HeadIdx,\r
+ uint8_t *dataBuff,\r
+ uint32_t TDLen,\r
+ uint8_t IntOnComplete);\r
+\r
+static HCD_STATUS QueueSITDs(uint8_t HostID, uint8_t HeadIdx, uint8_t *dataBuff, uint32_t xferLen);\r
+\r
+/********************************* Transfer Routines *********************************/\r
+static HCD_STATUS WaitForTransferComplete(uint8_t HostID, uint8_t EpIdx);\r
+\r
+static HCD_STATUS PipehandleParse(uint32_t Pipehandle, uint8_t *pHostID, HCD_TRANSFER_TYPE *XferType, uint8_t *pIdx);\r
+\r
+static void PipehandleCreate(uint32_t *pPipeHandle, uint8_t HostID, HCD_TRANSFER_TYPE XferType, uint8_t idx);\r
+\r
+/********************************* Interrupt Service Routines *********************************/\r
+static void AsyncScheduleIsr(uint8_t HostID);\r
+\r
+static void PeriodScheduleIsr(uint8_t HostID);\r
+\r
+static HCD_STATUS PortStatusChangeIsr(uint8_t HostID, uint32_t deviceConnect);\r
+\r
+static void AsyncAdvanceIsr(uint8_t HostID);\r
+\r
+static void UsbErrorIsr(uint8_t HostID);\r
+\r
+#endif\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * @brief Host Controller Driver functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../USBMode.h"\r
+\r
+#ifdef USB_CAN_BE_HOST\r
+\r
+#if !defined(__LPC_OHCI__) && !defined(__LPC_EHCI__)\r
+ #error "Either __LPC_OHCI__ or __LPC_EHCI__ must be defined"\r
+#endif\r
+\r
+#include "../USBTask.h"\r
+\r
+\r
+#ifdef LPCUSBlib_DEBUG\r
+void assert_status_ok_message(HCD_STATUS status,\r
+ char const *mess,\r
+ char const *func,\r
+ char const *file,\r
+ uint32_t const line)\r
+{\r
+ if (HCD_STATUS_OK != status) {\r
+ hcd_printf("%s\r\n", func);\r
+ hcd_printf("\t%s: %d\r\n", file, line);\r
+ hcd_printf("\tEvaluated HCD_STATUS = %d\r\n", (uint32_t) status);\r
+ if (mess != NULL) {\r
+ hcd_printf("\t%s\r\n", mess);\r
+ }\r
+ }\r
+}\r
+\r
+#endif\r
+\r
+void HcdDelayUS(uint32_t delay)\r
+{\r
+ volatile uint32_t i;\r
+\r
+ for (i = 0; i < (4 * delay); i++) /* This logic was tested. It gives app. 1 micro sec delay */\r
+ ;\r
+}\r
+\r
+void HcdDelayMS(uint32_t delay)\r
+{\r
+ volatile uint32_t i;\r
+\r
+ for (i = 0; i < delay; i++)\r
+ HcdDelayUS(1000);\r
+}\r
+\r
+HCD_STATUS OpenPipe_VerifyParameters(uint8_t HostID,\r
+ uint8_t DeviceAddr,\r
+ HCD_USB_SPEED DeviceSpeed,\r
+ uint8_t EndpointNumber,\r
+ HCD_TRANSFER_TYPE TransferType,\r
+ HCD_TRANSFER_DIR TransferDir,\r
+ uint16_t MaxPacketSize,\r
+ uint8_t Interval,\r
+ uint8_t Mult)\r
+{\r
+ if ((HostID >= MAX_USB_CORE) ||\r
+ ( DeviceAddr > 127) ||\r
+ ( DeviceSpeed > HIGH_SPEED) ||\r
+ (EndpointNumber & 0x70) ||\r
+ ( TransferType > INTERRUPT_TRANSFER) ||\r
+ ( TransferDir > OUT_TRANSFER) ) {\r
+ ASSERT_STATUS_OK(HCD_STATUS_PARAMETER_INVALID);\r
+ }\r
+\r
+ /* XXX by USB specs Low speed device should not have packet size > 8, but many market devices does */\r
+ if ((DeviceSpeed == LOW_SPEED) && ((TransferType == BULK_TRANSFER) || (TransferType == ISOCHRONOUS_TRANSFER)) ) {\r
+ ASSERT_STATUS_OK(HCD_STATUS_PARAMETER_INVALID);\r
+ }\r
+\r
+ switch (TransferType) {\r
+ case CONTROL_TRANSFER:\r
+ if (MaxPacketSize > 64) {\r
+ ASSERT_STATUS_OK(HCD_STATUS_PARAMETER_INVALID);\r
+ }\r
+ break;\r
+\r
+ case BULK_TRANSFER:\r
+ if (((DeviceSpeed == FULL_SPEED) && (MaxPacketSize > 64)) ||\r
+ ((DeviceSpeed == HIGH_SPEED) && (MaxPacketSize > 512)) ) {\r
+ ASSERT_STATUS_OK(HCD_STATUS_PARAMETER_INVALID);\r
+ }\r
+ break;\r
+\r
+ case INTERRUPT_TRANSFER:\r
+ if ((Interval == 0) ||\r
+ ((DeviceSpeed == FULL_SPEED) && (MaxPacketSize > 64)) ||\r
+ ((DeviceSpeed == HIGH_SPEED) && ((MaxPacketSize > 1024) || (Interval > 16) || (Mult == 0))) ) {\r
+ ASSERT_STATUS_OK(HCD_STATUS_PARAMETER_INVALID);\r
+ }\r
+ break;\r
+\r
+ case ISOCHRONOUS_TRANSFER:\r
+ if ((Interval == 0) || (Interval > 16) ||\r
+ ((DeviceSpeed == FULL_SPEED) && (MaxPacketSize > 1023)) ||\r
+ ((DeviceSpeed == HIGH_SPEED) && ((MaxPacketSize > 1024) || (Mult == 0))) ) {\r
+ ASSERT_STATUS_OK(HCD_STATUS_PARAMETER_INVALID);\r
+ }\r
+ break;\r
+ }\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief Host Controller Driver functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_Host\r
+ * @defgroup Group_HCD Host Controller Drivers\r
+ * @{\r
+ */\r
+#ifndef __LPC_HCD_H__\r
+#define __LPC_HCD_H__\r
+\r
+#include "../../../../Common/Common.h"\r
+#include "../StdRequestType.h" // FIXME should be USBTask.h instead\r
+#include "../HAL/HAL.h"\r
+#include <string.h>\r
+#include <stdio.h>\r
+\r
+/** Used with \ref HcdDataTransfer() to set maximum endpoint size for transfer length\r
+ */\r
+#define HCD_ENDPOINT_MAXPACKET_XFER_LEN 0xFFEEFFEE\r
+\r
+/** Similar to boolean type\r
+ */\r
+#define YES 1\r
+\r
+/** Similar to boolean type\r
+ */\r
+#define NO 0\r
+\r
+/** Maximum number of endpoints/pipes that a single USB host core can support\r
+ */\r
+#define HCD_MAX_ENDPOINT 8\r
+\r
+/** Pre-defined counter value for reseting USB host core\r
+ */\r
+#define HC_RESET_TIMEOUT 10\r
+\r
+/** Pre-defined counter value for transferring\r
+ */\r
+#define TRANSFER_TIMEOUT_MS 1000\r
+\r
+/** Pre-defined counter value for reseting USB port\r
+ */\r
+#define PORT_RESET_PERIOD_MS 100\r
+\r
+/* Control / Bulk transfer is always enabled */\r
+/** Flag to enable processing for interrupt transfer\r
+ * Select \ref YES to enable or \ref NO if disable\r
+ */\r
+#define INTERRUPT_LIST_ENABLE YES\r
+\r
+/** Flag to enable processing for isochronous transfer\r
+ * Select \ref YES to enable or \ref NO if disable\r
+ */\r
+#define ISO_LIST_ENABLE YES\r
+\r
+/** Declare labels for all USB transfer types\r
+ */\r
+typedef enum {\r
+ CONTROL_TRANSFER,\r
+ ISOCHRONOUS_TRANSFER,\r
+ BULK_TRANSFER,\r
+ INTERRUPT_TRANSFER\r
+} HCD_TRANSFER_TYPE;\r
+\r
+/** Declare labels for all USB transfer direction\r
+ */\r
+typedef enum {\r
+ SETUP_TRANSFER,\r
+ IN_TRANSFER,\r
+ OUT_TRANSFER\r
+} HCD_TRANSFER_DIR;\r
+\r
+/** Declare labels for supported USB transfer speeds\r
+ */\r
+typedef enum {\r
+ FULL_SPEED = 0,\r
+ LOW_SPEED,\r
+ HIGH_SPEED\r
+} HCD_USB_SPEED;\r
+\r
+/** Declare status/completion code for host processing\r
+ */\r
+typedef enum {\r
+ HCD_STATUS_OK = 0, /**< Transfer/process completion normal*/\r
+\r
+ HCD_STATUS_TRANSFER_CRC, /**< Transfer/process completion fail: CRC error */\r
+ HCD_STATUS_TRANSFER_BitStuffing, /**< Transfer/process completion fail: bit stuffing error */\r
+ HCD_STATUS_TRANSFER_DataToggleMismatch, /**< Transfer/process completion fail: data toggle error */\r
+ HCD_STATUS_TRANSFER_Stall, /**< Transfer/process completion fail: endpoint stall */\r
+ HCD_STATUS_TRANSFER_DeviceNotResponding,/**< Transfer/process completion fail: connected device hung or ... */\r
+\r
+ HCD_STATUS_TRANSFER_PIDCheckFailure, /**< Transfer/process completion fail: PID error */\r
+ HCD_STATUS_TRANSFER_UnexpectedPID, /**< Transfer/process completion fail: PID error */\r
+ HCD_STATUS_TRANSFER_DataOverrun, /**< Transfer/process completion fail: data over run */\r
+ HCD_STATUS_TRANSFER_DataUnderrun, /**< Transfer/process completion fail: data under run */\r
+ HCD_STATUS_TRANSFER_CC_Reserved1, /**< Transfer/process completion fail: Reserved */\r
+\r
+ HCD_STATUS_TRANSFER_CC_Reserved2, /**< Transfer/process completion fail: Reserved */\r
+ HCD_STATUS_TRANSFER_BufferOverrun, /**< Transfer/process completion fail: buffer over run */\r
+ HCD_STATUS_TRANSFER_BufferUnderrun, /**< Transfer/process completion fail: buffer under run */\r
+ HCD_STATUS_TRANSFER_NotAccessed, /**< Transfer/process completion fail: Reserved */\r
+ HCD_STATUS_TRANSFER_Reserved, /**< Transfer/process completion fail: Reserved */\r
+\r
+ HCD_STATUS_STRUCTURE_IS_FREE, /**< USB transfer status: USB data structure is free to use */\r
+ HCD_STATUS_TO_BE_REMOVED, /**< USB transfer status: USB data structure need to be freed */\r
+ HCD_STATUS_TRANSFER_QUEUED, /**< USB transfer status: transfer descriptor has been set up and queued */\r
+ HCD_STATUS_TRANSFER_COMPLETED, /**< USB transfer status: transfer descriptor finished */\r
+ HCD_STATUS_TRANSFER_ERROR, /**< USB transfer status: transfer descriptor finished with error */\r
+\r
+ HCD_STATUS_NOT_ENOUGH_MEMORY, /**< USB transfer set up status: not enough memory */\r
+ HCD_STATUS_NOT_ENOUGH_ENDPOINT, /**< USB transfer set up status: not enough endpoint */\r
+ HCD_STATUS_NOT_ENOUGH_GTD, /**< USB transfer set up status: not enough general transfer descriptor (OHCI)*/\r
+ HCD_STATUS_NOT_ENOUGH_ITD, /**< USB transfer set up status: not enough isochronous transfer descriptor */\r
+ HCD_STATUS_NOT_ENOUGH_QTD, /**< USB transfer set up status: not enough queue transfer descrptor (EHCI) */\r
+\r
+ HCD_STATUS_NOT_ENOUGH_HS_ITD, /**< USB transfer set up status: not enough high speed isochronous trsfer descriptor */\r
+ HCD_STATUS_NOT_ENOUGH_SITD, /**< USB transfer set up status: not enough split isochronous transfer descriptor */\r
+ HCD_STATUS_DATA_OVERFLOW, /**< USB transfer set up status: data over flow */\r
+ HCD_STATUS_DEVICE_DISCONNECTED, /**< USB transfer set up status: device disconnected */\r
+ HCD_STATUS_TRANSFER_TYPE_NOT_SUPPORTED, /**< USB transfer set up status: transfer is not supported */\r
+\r
+ HCD_STATUS_PIPEHANDLE_INVALID, /**< USB transfer set up status: pipe handle information is not valid */\r
+ HCD_STATUS_PARAMETER_INVALID /**< USB transfer set up status: wrong supply parameters */\r
+} HCD_STATUS;\r
+\r
+/**\r
+ * @brief Initiate host driver\r
+ *\r
+ * @param HostID : USB port number\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdInitDriver (uint8_t HostID);\r
+\r
+/**\r
+ * @brief De-initiate host driver\r
+ *\r
+ * @param HostID : USB port number\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdDeInitDriver(uint8_t HostID);\r
+\r
+/**\r
+ * @brief Interrupt service routine for host mode\r
+ * This function must be called in chip's USB interrupt routine\r
+ *\r
+ * @param HostID : USB port number\r
+ * @return nothing\r
+ */\r
+void HcdIrqHandler(uint8_t HostID);\r
+\r
+/**\r
+ * @brief Perform USB bus reset\r
+ *\r
+ * @param HostID : USB port number\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdRhPortReset(uint8_t HostID);\r
+\r
+/**\r
+ * @brief Turn on 5V USB VBUS\r
+ *\r
+ * @param HostID : USB port number\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdRhPortEnable(uint8_t HostID);\r
+\r
+/**\r
+ * @brief Turn off 5V USB VBUS\r
+ *\r
+ * @param HostID : USB port number\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdRhPortDisable(uint8_t HostID);\r
+\r
+/**\r
+ * @brief Get operation speed of connected device\r
+ *\r
+ * @param HostID : USB port number\r
+ * @param DeviceSpeed : return device speed through pointer of type \ref HCD_USB_SPEED\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdGetDeviceSpeed(uint8_t HostID, HCD_USB_SPEED *DeviceSpeed);\r
+\r
+/**\r
+ * @brief Get current frame number\r
+ *\r
+ * @param HostID : USB port number\r
+ * @return frame number\r
+ */\r
+uint32_t HcdGetFrameNumber(uint8_t HostID);\r
+\r
+/**\r
+ * @brief Setup a pipe to connect to device's logical endpoint\r
+ *\r
+ * @param HostID : USB port number\r
+ * @param DeviceAddr : address of connected device\r
+ * @param DeviceSpeed : speed of connected device in format \ref HCD_USB_SPEED\r
+ * @param EndpointNo : connected logical endpoint number\r
+ * @param TransferType : transfer type of this link in format \ref HCD_TRANSFER_TYPE\r
+ * @param TransferDir : direction of this link in format \ref HCD_TRANSFER_DIR\r
+ * @param MaxPacketSize: maximum size of connected endpoint\r
+ * @param Interval : polling frequency for this transfer type, only apply for period transfer\r
+ * @param Mult : used for isochronous transfer to determine number of packets sent in one transaction\r
+ * @param HSHubDevAddr : currently not use this parameter\r
+ * @param HSHubPortNum : currently not use this parameter\r
+ * @param PipeHandle : pointer to return pipe handle information\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdOpenPipe(uint8_t HostID,\r
+ uint8_t DeviceAddr,\r
+ HCD_USB_SPEED DeviceSpeed,\r
+ uint8_t EndpointNo,\r
+ HCD_TRANSFER_TYPE TransferType,\r
+ HCD_TRANSFER_DIR TransferDir,\r
+ uint16_t MaxPacketSize,\r
+ uint8_t Interval,\r
+ uint8_t Mult,\r
+ uint8_t HSHubDevAddr,\r
+ uint8_t HSHubPortNum,\r
+ uint32_t *const PipeHandle);\r
+\r
+/**\r
+ * @brief Delete the link between USB host and device's logical endpoint\r
+ *\r
+ * @param PipeHandle : encoded pipe handle information\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdClosePipe(uint32_t PipeHandle);\r
+\r
+/**\r
+ * @brief Cancel a processing transfer\r
+ *\r
+ * @param PipeHandle : encoded pipe handle information\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdCancelTransfer(uint32_t PipeHandle);\r
+\r
+/**\r
+ * @brief Clear stall status for connected endpoint\r
+ *\r
+ * @param PipeHandle : encoded pipe handle information\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdClearEndpointHalt(uint32_t PipeHandle);\r
+\r
+/**\r
+ * @brief Perform a control transfer\r
+ *\r
+ * @param PipeHandle : encoded pipe handle information\r
+ * @param pDeviceRequest: pointer to \ref USB_Request_Header_t structure\r
+ * @param buffer : pointer to share buffer used in data phase\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdControlTransfer(uint32_t PipeHandle,\r
+ const USB_Request_Header_t *const pDeviceRequest,\r
+ uint8_t *const buffer);\r
+\r
+/**\r
+ * @brief Perform a non-control transfer\r
+ *\r
+ * @param PipeHandle : encoded pipe handle information\r
+ * @param buffer : pointer to transferred data buffer\r
+ * @param length : size of this transfer\r
+ * @param pActualTransferred: return actual transfer bytes through pointer\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdDataTransfer(uint32_t PipeHandle,\r
+ uint8_t *const buffer,\r
+ uint32_t const length,\r
+ uint16_t *const pActualTransferred);\r
+\r
+/**\r
+ * @brief Get current pipe status\r
+ *\r
+ * @param PipeHandle : encoded pipe handle information\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS HcdGetPipeStatus(uint32_t PipeHandle);\r
+\r
+/**\r
+ * @brief Set size of each packet in a continuous data transfer\r
+ *\r
+ * @param PipeHandle : encoded pipe handle information\r
+ * @param packetsize : packet size\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+void HcdSetStreamPacketSize(uint32_t PipeHandle, uint16_t packetsize);\r
+\r
+#ifdef LPCUSBlib_DEBUG\r
+ #define hcd_printf printf\r
+void assert_status_ok_message(HCD_STATUS status,\r
+ char const *mess,\r
+ char const *func,\r
+ char const *file,\r
+ uint32_t const line);\r
+\r
+#else\r
+ #define hcd_printf(...)\r
+ #define assert_status_ok_message(...)\r
+#endif\r
+\r
+#define ASSERT_STATUS_OK_MESSAGE(sts, message) \\r
+ do { \\r
+ HCD_STATUS status = (sts); \\r
+ assert_status_ok_message(status, message, __func__, __FILE__, __LINE__); \\r
+ if (HCD_STATUS_OK != status) { \\r
+ return status; \\r
+ } \\r
+ } while (0)\r
+\r
+#define ASSERT_STATUS_OK(sts) ASSERT_STATUS_OK_MESSAGE(sts, NULL)\r
+\r
+#if defined(__LPC_OHCI_C__) || defined(__LPC_EHCI_C__)\r
+\r
+void HcdDelayUS (uint32_t delay);\r
+\r
+void HcdDelayMS (uint32_t delay);\r
+\r
+/**\r
+ * @brief Verify if input parameters are supported\r
+ *\r
+ * @param HostID : USB port number\r
+ * @param DeviceAddr : address of connected device\r
+ * @param DeviceSpeed : speed of connected device in format \ref HCD_USB_SPEED\r
+ * @param EndpointNumber: connected logical endpoint number\r
+ * @param TransferType : transfer type of this link in format \ref HCD_TRANSFER_TYPE\r
+ * @param TransferDir : direction of this link in format \ref HCD_TRANSFER_DIR\r
+ * @param MaxPacketSize: maximum size of connected endpoint\r
+ * @param Interval : polling frequency for this transfer type, only apply for period transfer\r
+ * @param Mult : used for isochronous transfer to determine number of packets sent in one transaction\r
+ * @return \ref HCD_STATUS code\r
+ */\r
+HCD_STATUS OpenPipe_VerifyParameters(uint8_t HostID,\r
+ uint8_t DeviceAddr,\r
+ HCD_USB_SPEED DeviceSpeed,\r
+ uint8_t EndpointNumber,\r
+ HCD_TRANSFER_TYPE TransferType,\r
+ HCD_TRANSFER_DIR TransferDir,\r
+ uint16_t MaxPacketSize,\r
+ uint8_t Interval,\r
+ uint8_t Mult);\r
+\r
+/**\r
+ * @brief Modify an address to a desired alignment\r
+ *\r
+ * @param Value : input address\r
+ * @return output aligned address\r
+ */\r
+static INLINE uint32_t Align32(uint32_t Value)\r
+{\r
+ return Value & 0xFFFFFFE0UL; /* Bit 31 .. 5 */\r
+}\r
+\r
+/**\r
+ * @brief Modify an address to a desired alignment\r
+ *\r
+ * @param alignment : alignment desired value\r
+ * @param Value : input address\r
+ * @return output aligned address\r
+ */\r
+static INLINE uint32_t Aligned(uint32_t alignment, uint32_t Value)\r
+{\r
+ return Value & (~(alignment - 1));\r
+}\r
+\r
+/**\r
+ * @brief Modify an address to desired alignment\r
+ *\r
+ * @param Value : input address\r
+ * @return output aligned address\r
+ */\r
+static INLINE uint32_t Align4k(uint32_t Value)\r
+{\r
+ return Value & 0xFFFFF000; /* Bit 31 .. 5 */\r
+}\r
+\r
+/**\r
+ * @brief Modify an address to desired offset\r
+ *\r
+ * @param Value : input address\r
+ * @return output offset address\r
+ */\r
+static INLINE uint32_t Offset4k(uint32_t Value)\r
+{\r
+ return Value & 0xFFF;\r
+}\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * @brief Open Host Controller Interface\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/*=======================================================================*/\r
+/* I N C L U D E S */\r
+/*=======================================================================*/\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "../../USBMode.h"\r
+\r
+#if (defined(USB_CAN_BE_HOST) && defined(__LPC_OHCI__))\r
+\r
+#define __LPC_OHCI_C__\r
+#include "../../../../../Common/Common.h"\r
+#include "../../USBTask.h"\r
+#include "../HCD.h"\r
+#include "OHCI.h"\r
+\r
+PRAGMA_ALIGN_256\r
+OHCI_HOST_DATA_T ohci_data[MAX_USB_CORE] __BSS(USBRAM_SECTION) ATTR_ALIGNED(256);\r
+\r
+/*=======================================================================*/\r
+/* G L O B A L S Y M B O L D E C L A R A T I O N S */\r
+/*=======================================================================*/\r
+void USB_Host_Enumerate (uint8_t HostID);\r
+\r
+void USB_Host_DeEnumerate(uint8_t HostID);\r
+\r
+/*********************************************************************\r
+ * IMPLEMENTATION\r
+ **********************************************************************/\r
+HCD_STATUS HcdGetDeviceSpeed(uint8_t HostID, HCD_USB_SPEED *DeviceSpeed)\r
+{\r
+ if ( USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_CurrentConnectStatus) { /* If device is connected */\r
+ *DeviceSpeed =\r
+ ( USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_LowSpeedDeviceAttached) ? LOW_SPEED : FULL_SPEED;\r
+ return HCD_STATUS_OK;\r
+ }\r
+ else {\r
+ return HCD_STATUS_DEVICE_DISCONNECTED;\r
+ }\r
+}\r
+\r
+uint32_t HcdGetFrameNumber(uint8_t HostID)\r
+{\r
+ return ohci_data[HostID].hcca.HccaFrameNumber;\r
+}\r
+\r
+HCD_STATUS HcdRhPortReset(uint8_t HostID)\r
+{\r
+ HcdDelayMS(400);// TODO delay should be on Host_LPC\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_PortResetStatus; /* SetPortReset */\r
+ /* should have time-out */\r
+ while ( USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_PortResetStatus) {}\r
+\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_PortResetStatusChange;/* Clear Port Reset Status Change */\r
+\r
+ HcdDelayMS(400);// TODO delay should be on Host_LPC\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdRhPortEnable(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_PowerEnableStatus;/* SetPortEnable */\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdRhPortDisable(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_CurrentConnectStatus; /* ClearPortEnable */\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdInitDriver(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->OTGClkCtrl = 0x00000019; /* enable Host clock, OTG clock and AHB clock */\r
+ while ((USB_REG(HostID)->OTGClkSt & 0x00000019) != 0x00000019) ;\r
+#if defined(__LPC175X_6X__)\r
+ USB_REG(HostID)->StCtrl = 0x3; /* ??? */\r
+#elif defined(__LPC177X_8X__) || defined(__LPC407X_8X__)\r
+ USB_REG(HostID)->StCtrl = 0x1; /* Port 1 is host */\r
+#endif\r
+ OHciHostReset(HostID); /* Software Reset */\r
+ return OHciHostInit(HostID);\r
+}\r
+\r
+HCD_STATUS HcdDeInitDriver(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->StCtrl = 0;\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdOpenPipe(uint8_t HostID,\r
+ uint8_t DeviceAddr,\r
+ HCD_USB_SPEED DeviceSpeed,\r
+ uint8_t EndpointNumber,\r
+ HCD_TRANSFER_TYPE TransferType,\r
+ HCD_TRANSFER_DIR TransferDir,\r
+ uint16_t MaxPacketSize,\r
+ uint8_t Interval,\r
+ uint8_t Mult,\r
+ uint8_t HSHubDevAddr,\r
+ uint8_t HSHubPortNum,\r
+ uint32_t *const PipeHandle)\r
+{\r
+ uint32_t EdIdx;\r
+ uint8_t ListIdx;\r
+\r
+ (void) Mult; (void) HSHubDevAddr; (void) HSHubPortNum; /* Disable compiler warnings */\r
+\r
+#if !ISO_LIST_ENABLE\r
+ if ( TransferType == ISOCHRONOUS_TRANSFER ) {\r
+ ASSERT_STATUS_OK_MESSAGE(HCD_STATUS_TRANSFER_TYPE_NOT_SUPPORTED, "Please set ISO_LIST_ENABLE to YES");\r
+ }\r
+#endif\r
+\r
+#if !INTERRUPT_LIST_ENABLE\r
+ if ( TransferType == INTERRUPT_TRANSFER ) {\r
+ ASSERT_STATUS_OK_MESSAGE(HCD_STATUS_TRANSFER_TYPE_NOT_SUPPORTED, "Please set INTERRUPT_LIST_ENABLE to YES");\r
+ }\r
+#endif\r
+\r
+ /********************************* Parameters Verify *********************************/\r
+ ASSERT_STATUS_OK(OpenPipe_VerifyParameters(HostID, DeviceAddr, DeviceSpeed, EndpointNumber, TransferType,\r
+ TransferDir, MaxPacketSize, Interval, 0) );\r
+\r
+ EndpointNumber &= 0xF; /* Endpoint number is in range 0-15 */\r
+ MaxPacketSize &= 0x3FF; /* Max Packet Size is in range 0-1024 */\r
+\r
+ switch (TransferType) {\r
+ case CONTROL_TRANSFER:\r
+ ListIdx = CONTROL_LIST_HEAD;\r
+ break;\r
+\r
+ case BULK_TRANSFER:\r
+ ListIdx = BULK_LIST_HEAD;\r
+ break;\r
+\r
+ case INTERRUPT_TRANSFER:\r
+ // ListIdx = FindInterruptTransferListIndex(Interval);\r
+ ListIdx = INTERRUPT_1ms_LIST_HEAD;\r
+ break;\r
+\r
+ case ISOCHRONOUS_TRANSFER:\r
+ ListIdx = ISO_LIST_HEAD;\r
+ break;\r
+ default : // just to clear warning\r
+ ListIdx = 0xFF;\r
+ break;\r
+ }\r
+ \r
+ if(ListIdx == 0xFF) return HCD_STATUS_PARAMETER_INVALID;\r
+\r
+ ASSERT_STATUS_OK(AllocEd(DeviceAddr, DeviceSpeed, EndpointNumber, TransferType, TransferDir, MaxPacketSize,\r
+ Interval, &EdIdx) );\r
+\r
+ /* Add new ED to the EDs List */\r
+ HcdED(EdIdx)->ListIndex = ListIdx;\r
+ InsertEndpoint(HostID, EdIdx, ListIdx);\r
+\r
+ PipehandleCreate(PipeHandle, HostID, EdIdx);\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdCancelTransfer(uint32_t PipeHandle)\r
+{\r
+ uint8_t HostID, EdIdx;\r
+\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &EdIdx) );\r
+\r
+ HcdED(EdIdx)->hcED.Skip = 1;\r
+\r
+ /* Clear SOF and wait for the next frame */\r
+ USB_REG(HostID)->InterruptStatus = HC_INTERRUPT_StartofFrame;\r
+ while ( !(USB_REG(HostID)->InterruptStatus & HC_INTERRUPT_StartofFrame) )/* TODO Should have timeout */\r
+\r
+ /* ISO TD & General TD have the same offset for nextTD, we can use GTD as pointer to travel on TD list */\r
+ while ( Align16(HcdED(EdIdx)->hcED.HeadP.HeadTD) != Align16(HcdED(EdIdx)->hcED.TailP) ) {\r
+ uint32_t HeadTD = Align16(HcdED(EdIdx)->hcED.HeadP.HeadTD);\r
+ if ( IsIsoEndpoint(EdIdx) ) {\r
+ HcdED(EdIdx)->hcED.HeadP.HeadTD = ((PHCD_IsoTransferDescriptor) HeadTD)->NextTD;\r
+ FreeItd( (PHCD_IsoTransferDescriptor) HeadTD);\r
+ }\r
+ else {\r
+ HcdED(EdIdx)->hcED.HeadP.HeadTD = ((PHCD_GeneralTransferDescriptor) HeadTD)->hcGTD.NextTD;\r
+ FreeGtd((PHCD_GeneralTransferDescriptor) HeadTD);\r
+ }\r
+ }\r
+ HcdED(EdIdx)->hcED.HeadP.HeadTD = Align16(HcdED(EdIdx)->hcED.TailP);/*-- Toggle Carry/Halted are also set to 0 --*/\r
+ HcdED(EdIdx)->hcED.HeadP.ToggleCarry = 0;\r
+\r
+ HcdED(EdIdx)->hcED.Skip = 0;\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdClosePipe(uint32_t PipeHandle)\r
+{\r
+ uint8_t HostID, EdIdx;\r
+\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &EdIdx) );\r
+\r
+ ASSERT_STATUS_OK(HcdCancelTransfer(PipeHandle) );\r
+\r
+ HcdED(EdIdx)->hcED.Skip = 1;/* no need for delay, it is already delayed in cancel transfer */\r
+ RemoveEndpoint(HostID, EdIdx);\r
+\r
+ FreeED(EdIdx);\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdClearEndpointHalt(uint32_t PipeHandle)\r
+{\r
+ uint8_t HostID, EdIdx;\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &EdIdx) );\r
+ /* TODO should we call HcdCancelTrnasfer ? */\r
+ HcdED(EdIdx)->hcED.HeadP.Halted = 0;\r
+ HcdED(EdIdx)->hcED.HeadP.ToggleCarry = 0;\r
+\r
+ HcdED(EdIdx)->status = HCD_STATUS_OK;\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdControlTransfer(uint32_t PipeHandle,\r
+ const USB_Request_Header_t *const pDeviceRequest,\r
+ uint8_t *const buffer)\r
+{\r
+ uint8_t HostID, EdIdx;\r
+\r
+ if ((pDeviceRequest == NULL) || (buffer == NULL)) {\r
+ ASSERT_STATUS_OK_MESSAGE(HCD_STATUS_PARAMETER_INVALID, "Device Request or Data Buffer is NULL");\r
+ }\r
+\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &EdIdx) );\r
+\r
+ /************************************************************************/\r
+ /* Setup Stage */\r
+ /************************************************************************/\r
+ ASSERT_STATUS_OK(QueueOneGTD(EdIdx, (uint8_t *) pDeviceRequest, 8, 0, 2, 0) ); /* Setup TD: DirectionPID=00 - DataToggle=10b (always DATA0) */\r
+\r
+ /************************************************************************/\r
+ /* Data Stage */\r
+ /************************************************************************/\r
+ if (pDeviceRequest->wLength) { /* Could have problem if the wLength is larger than pipe size */\r
+ ASSERT_STATUS_OK(QueueOneGTD(EdIdx, buffer, pDeviceRequest->wLength,\r
+ (pDeviceRequest->bmRequestType & 0x80) ? 2 : 1, 3, 0) ); /* DataToggle=11b (always DATA1) */\r
+ }\r
+ /************************************************************************/\r
+ /* Status Stage */\r
+ /************************************************************************/\r
+ ASSERT_STATUS_OK(QueueOneGTD(EdIdx, NULL, 0, (pDeviceRequest->bmRequestType & 0x80) ? 1 : 2, 3, 1) ); /* Status TD: Direction=opposite of data direction - DataToggle=11b (always DATA1) */\r
+\r
+ /* set control list filled */\r
+ USB_REG(HostID)->CommandStatus |= HC_COMMAND_STATUS_ControlListFilled;\r
+\r
+ HcdED(EdIdx)->status = HCD_STATUS_TRANSFER_QUEUED;\r
+\r
+ /* wait for semaphore compete TDs */\r
+ ASSERT_STATUS_OK(WaitForTransferComplete(EdIdx) );\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static HCD_STATUS QueueOneITD(uint32_t EdIdx, uint8_t *dataBuff, uint32_t TDLen, uint16_t StartingFrame)\r
+{\r
+ uint32_t i;\r
+ PHCD_IsoTransferDescriptor pItd = (PHCD_IsoTransferDescriptor) Align16(HcdED(EdIdx)->hcED.TailP);\r
+\r
+ pItd->StartingFrame = StartingFrame;\r
+ pItd->FrameCount =\r
+ (TDLen / HcdED(EdIdx)->hcED.MaxPackageSize) + (TDLen % HcdED(EdIdx)->hcED.MaxPackageSize ? 1 : 0) - 1;\r
+ pItd->BufferPage0 = Align4k( (uint32_t) dataBuff);\r
+ pItd->BufferEnd = (uint32_t) (dataBuff + TDLen - 1);\r
+\r
+ for (i = 0; TDLen > 0 && i < 8; i++) {\r
+ uint32_t XactLen = MIN(TDLen, HcdED(EdIdx)->hcED.MaxPackageSize);\r
+\r
+ pItd->OffsetPSW[i] =\r
+ (HCD_STATUS_TRANSFER_NotAccessed <<\r
+ 12) | (Align4k((uint32_t) dataBuff) != Align4k(pItd->BufferPage0) ? _BIT(12) : 0) |\r
+ Offset4k((uint32_t) dataBuff); /*-- FIXME take into cross page account later 15-12: ConditionCode, 11-0: offset --*/\r
+\r
+ TDLen -= XactLen;\r
+ dataBuff += XactLen;\r
+ }\r
+\r
+ /* Create a new place holder TD & link setup TD to the new place holder */\r
+ ASSERT_STATUS_OK(AllocItdForEd(EdIdx) );\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static HCD_STATUS QueueITDs(uint32_t EdIdx, uint8_t *dataBuff, uint32_t xferLen)\r
+{\r
+ uint32_t FrameIdx;\r
+ uint32_t MaxDataSize;\r
+\r
+#if 0 /* Maximum bandwidth (Interval = 1) regardless of Interval value */\r
+ uint8_t MaxXactPerITD, FramePeriod;\r
+ if (HcdED(EdIdx)->Interval < 4) { /*-- Period < 8 --*/\r
+ MaxXactPerITD = 1 << ( 4 - HcdED(EdIdx)->Interval ); /*-- Interval 1 => 8, 2 => 4, 3 => 2 --*/\r
+ FramePeriod = 1;\r
+ }\r
+ else {\r
+ MaxXactPerITD = 1;\r
+ FramePeriod = 1 << ( HcdED(EdIdx)->Interval - 4 ); /*-- Frame step 4 => 1, 5 => 2, 6 => 3 --*/\r
+ }\r
+#else\r
+ #define MaxXactPerITD 8\r
+ #define FramePeriod 1\r
+#endif\r
+\r
+ MaxDataSize = MaxXactPerITD * HcdED(EdIdx)->hcED.MaxPackageSize;\r
+ FrameIdx = HcdGetFrameNumber(0) + 1; /* FIXME dual controller */\r
+\r
+ while (xferLen > 0) {\r
+ uint16_t TdLen;\r
+ uint32_t MaxTDLen = TD_MAX_XFER_LENGTH - Offset4k((uint32_t) dataBuff);\r
+ MaxTDLen = MIN(MaxDataSize, MaxTDLen);\r
+\r
+ TdLen = MIN(xferLen, MaxTDLen);\r
+ xferLen -= TdLen;\r
+\r
+ /*---------- Fill data to Place hodler TD ----------*/\r
+ ASSERT_STATUS_OK(QueueOneITD(EdIdx, dataBuff, TdLen, FrameIdx) );\r
+\r
+ FrameIdx = (FrameIdx + FramePeriod) % (1 << 16);\r
+ dataBuff += TdLen;\r
+ }\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdDataTransfer(uint32_t PipeHandle,\r
+ uint8_t *const buffer,\r
+ uint32_t const length,\r
+ uint16_t *const pActualTransferred)\r
+{\r
+ uint8_t HostID, EdIdx;\r
+ uint32_t ExpectedLength;\r
+\r
+ if ((buffer == NULL) || (length == 0)) {\r
+ ASSERT_STATUS_OK_MESSAGE(HCD_STATUS_PARAMETER_INVALID, "Data Buffer is NULL or Transfer Length is 0");\r
+ }\r
+\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &EdIdx) );\r
+ ASSERT_STATUS_OK(HcdED(EdIdx)->hcED.HeadP.Halted ? HCD_STATUS_TRANSFER_Stall : HCD_STATUS_OK);\r
+\r
+ ExpectedLength = (length != HCD_ENDPOINT_MAXPACKET_XFER_LEN) ? length : HcdED(EdIdx)->hcED.MaxPackageSize;\r
+\r
+ if ( IsIsoEndpoint(EdIdx) ) { /* Iso Transfer */\r
+ ASSERT_STATUS_OK(QueueITDs(EdIdx, buffer, ExpectedLength) );\r
+ }\r
+ else {\r
+ ASSERT_STATUS_OK(QueueGTDs(EdIdx, buffer, ExpectedLength, 0) );\r
+ if (HcdED(EdIdx)->ListIndex == BULK_LIST_HEAD) {\r
+ USB_REG(HostID)->CommandStatus |= HC_COMMAND_STATUS_BulkListFilled;\r
+ }\r
+ }\r
+\r
+ HcdED(EdIdx)->status = HCD_STATUS_TRANSFER_QUEUED;\r
+ HcdED(EdIdx)->pActualTransferCount = pActualTransferred;/* TODO refractor Actual length transfer */\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+HCD_STATUS HcdGetPipeStatus(uint32_t PipeHandle)\r
+{\r
+ uint8_t HostID, EdIdx;\r
+\r
+ ASSERT_STATUS_OK(PipehandleParse(PipeHandle, &HostID, &EdIdx) );\r
+\r
+ return (HCD_STATUS)HcdED(EdIdx)->status;\r
+}\r
+\r
+static void OHciRhStatusChangeIsr(uint8_t HostID, uint32_t deviceConnect)\r
+{\r
+ if (deviceConnect) {/* Device Attached */\r
+ USB_Host_Enumerate(HostID);\r
+ }\r
+ else { /* Device detached */\r
+ USB_Host_DeEnumerate(HostID);\r
+ }\r
+}\r
+\r
+static void ProcessDoneQueue(uint8_t HostID, uint32_t donehead)\r
+{\r
+ PHC_GTD pCurTD = (PHC_GTD) donehead;\r
+ PHC_GTD pTDList = NULL;\r
+\r
+ /* do nothing if done queue is empty */\r
+ if (!donehead) {\r
+ return;\r
+ }\r
+\r
+ /* reverse done queue order */\r
+ do {\r
+ uint32_t nextTD = pCurTD->NextTD;\r
+ pCurTD->NextTD = (uint32_t) pTDList;\r
+ pTDList = pCurTD;\r
+ pCurTD = (PHC_GTD) nextTD;\r
+ } while (pCurTD);\r
+\r
+ while (pTDList != NULL) {\r
+ uint32_t EdIdx;\r
+\r
+ pCurTD = pTDList;\r
+ pTDList = (PHC_GTD) pTDList->NextTD;\r
+\r
+ /* TODO Cannot determine EdIdx because GTD and ITD have different offsets for EdIdx */\r
+ if ( ((uint32_t) pCurTD) <= ((uint32_t) HcdITD(MAX_ITD - 1)) ) { /* ISO TD address range */\r
+ PHCD_IsoTransferDescriptor pItd = (PHCD_IsoTransferDescriptor) pCurTD;\r
+ EdIdx = pItd->EdIdx;\r
+ }\r
+ else { /* GTD */\r
+ PHCD_GeneralTransferDescriptor pGtd = (PHCD_GeneralTransferDescriptor) pCurTD;\r
+ EdIdx = pGtd->EdIdx;\r
+\r
+ if (pGtd->hcGTD.CurrentBufferPointer) {\r
+ pGtd->TransferCount -=\r
+ ( Align4k( ((uint32_t) pGtd->hcGTD.BufferEnd) ^\r
+ ((uint32_t) pGtd->hcGTD.CurrentBufferPointer) ) ? 0x00001000 : 0 ) +\r
+ Offset4k((uint32_t) pGtd->hcGTD.BufferEnd) - Offset4k(\r
+ (uint32_t) pGtd->hcGTD.CurrentBufferPointer) + 1;\r
+ }\r
+ if (HcdED(EdIdx)->pActualTransferCount) {\r
+ *(HcdED(EdIdx)->pActualTransferCount) = pGtd->TransferCount;/* increase usb request transfer count */\r
+\r
+ }\r
+ }\r
+\r
+ if (pCurTD->DelayInterrupt != TD_NoInterruptOnComplete) { /* Update ED status if Interrupt on Complete is set */\r
+ HcdED(EdIdx)->status = pCurTD->ConditionCode;\r
+ }\r
+\r
+ if ( pCurTD->ConditionCode ) { /* also update ED status if TD complete with error */\r
+ HcdED(EdIdx)->status =\r
+ (HcdED(EdIdx)->hcED.HeadP.Halted == 1) ? HCD_STATUS_TRANSFER_Stall : pCurTD->ConditionCode;\r
+ HcdED(EdIdx)->hcED.HeadP.Halted = 0;\r
+ hcd_printf("Error on Endpoint 0x%X has HCD_STATUS code %d\r\n",\r
+ HcdED(EdIdx)->hcED.FunctionAddr | (HcdED(EdIdx)->hcED.Direction == 2 ? 0x80 : 0x00),\r
+ pCurTD->ConditionCode);\r
+ }\r
+\r
+ /* remove completed TD from usb request list, if request list is now empty complete usb request */\r
+ if (IsIsoEndpoint(EdIdx)) {\r
+ FreeItd( (PHCD_IsoTransferDescriptor) pCurTD);\r
+ }\r
+ else {\r
+ FreeGtd( (PHCD_GeneralTransferDescriptor) pCurTD);\r
+ }\r
+\r
+ /* Post Semaphore to signal TDs are transfer */\r
+ }\r
+}\r
+\r
+#if SCHEDULING_OVRERRUN_INTERRUPT\r
+static void OHciSchedulingOverrunIsr(uint8_t HostID)\r
+{}\r
+\r
+#endif\r
+\r
+#if SOF_INTERRUPT\r
+static void OHciStartofFrameIsr(uint8_t HostID)\r
+{}\r
+\r
+#endif\r
+\r
+#if RESUME_DETECT_INTERRUPT\r
+static void OHciResumeDetectedIsr(uint8_t HostID)\r
+{}\r
+\r
+#endif\r
+\r
+#if UNRECOVERABLE_ERROR_INTERRUPT\r
+static void OHciUnrecoverableErrorIsr(uint8_t HostID)\r
+{}\r
+\r
+#endif\r
+\r
+#if FRAMENUMBER_OVERFLOW_INTERRUPT\r
+static void OHciFramenumberOverflowIsr(uint8_t HostID)\r
+{}\r
+\r
+#endif\r
+\r
+#if OWNERSHIP_CHANGE_INTERRUPT\r
+static void OHciOwnershipChangeIsr(uint8_t HostID)\r
+{}\r
+\r
+#endif\r
+\r
+void HcdIrqHandler(uint8_t HostID)\r
+{\r
+ uint32_t IntStatus;\r
+\r
+ IntStatus = USB_REG(HostID)->InterruptStatus;\r
+ /* Clear status after read immediately.\r
+ Then it will be able to record a new status. */\r
+ USB_REG(HostID)->InterruptStatus = IntStatus;/* Clear HcInterruptStatus */\r
+ IntStatus &= USB_REG(HostID)->InterruptEnable;\r
+ if (IntStatus == 0) {\r
+ return;\r
+ }\r
+\r
+ /* disable all interrupt for processing */\r
+ USB_REG(HostID)->InterruptDisable = HC_INTERRUPT_MasterInterruptEnable;\r
+\r
+ /* Process RootHub Status Change */\r
+ if (IntStatus & HC_INTERRUPT_RootHubStatusChange) {\r
+ for(;USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_StatusChangeMask;){\r
+ /* only 1 port/host --> skip to get the number of ports */\r
+ if (USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_ConnectStatusChange) {\r
+ if (USB_REG(HostID)->RhStatus & HC_RH_STATUS_DeviceRemoteWakeupEnable) { /* means a remote wakeup event */\r
+\r
+ }\r
+ else {}\r
+\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_ConnectStatusChange; /* clear CSC bit */\r
+ OHciRhStatusChangeIsr(HostID, USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_CurrentConnectStatus);\r
+ }\r
+\r
+ if (USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_PortEnableStatusChange) {\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_PortEnableStatusChange; /* clear PESC */\r
+ }\r
+\r
+ if (USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_PortSuspendStatusChange) {\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_PortSuspendStatusChange; /* clear PSSC */\r
+ }\r
+\r
+ if (USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_OverCurrentIndicatorChange) { /* Over-current handler to avoid physical damage */\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_OverCurrentIndicatorChange; /* clear OCIC */\r
+ }\r
+\r
+ if (USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_PortResetStatusChange) {\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_PortResetStatusChange; /* clear PRSC */\r
+ }\r
+ }\r
+ }\r
+\r
+ if (IntStatus & HC_INTERRUPT_WritebackDoneHead) {\r
+ ProcessDoneQueue(HostID, Align16(ohci_data[HostID].hcca.HccaDoneHead) );\r
+ }\r
+\r
+#if SCHEDULING_OVRERRUN_INTERRUPT\r
+ if (USB_REG(HostID)->HcInterruptStatus & HC_INTERRUPT_SchedulingOverrun) {\r
+ OHciSchedulingOverrunIsr(HostID);\r
+ }\r
+#endif\r
+\r
+#if SOF_INTERRUPT\r
+ if (USB_REG(HostID)->HcInterruptStatus & HC_INTERRUPT_StartofFrame) {\r
+ OHciStartofFrameIsr(HostID);\r
+ }\r
+#endif\r
+\r
+#if RESUME_DETECT_INTERRUPT\r
+ if (USB_REG(HostID)->HcInterruptStatus & HC_INTERRUPT_ResumeDetected) {\r
+ OHciResumeDetectedIsr(HostID);\r
+ }\r
+#endif\r
+\r
+#if UNRECOVERABLE_ERROR_INTERRUPT\r
+ if (USB_REG(HostID)->HcInterruptStatus & HC_INTERRUPT_UnrecoverableError) {\r
+ OHciUnrecoverableErrorIsr(HostID);\r
+ }\r
+#endif\r
+\r
+#if FRAMENUMBER_OVERFLOW_INTERRUPT\r
+ if (USB_REG(HostID)->HcInterruptStatus & HC_INTERRUPT_FrameNumberOverflow) {\r
+ OHciFramenumberOverflowIsr(HostID);\r
+ }\r
+#endif\r
+\r
+#if OWNERSHIP_CHANGE_INTERRUPT\r
+ if (USB_REG(HostID)->HcInterruptStatus & HC_INTERRUPT_OwnershipChange) {\r
+ OHciOwnershipChangeIsr(HostID);\r
+ }\r
+#endif\r
+ USB_REG(HostID)->InterruptEnable = HC_INTERRUPT_MasterInterruptEnable;\r
+ \r
+}\r
+\r
+static HCD_STATUS QueueOneGTD(uint32_t EdIdx,\r
+ uint8_t *const CurrentBufferPointer,\r
+ uint32_t xferLen,\r
+ uint8_t DirectionPID,\r
+ uint8_t DataToggle,\r
+ uint8_t IOC)\r
+{\r
+ PHCD_GeneralTransferDescriptor TailP;\r
+\r
+ TailP = ( (PHCD_GeneralTransferDescriptor) HcdED(EdIdx)->hcED.TailP );\r
+ TailP->hcGTD.DirectionPID = DirectionPID;\r
+ TailP->hcGTD.DataToggle = DataToggle;\r
+ TailP->hcGTD.CurrentBufferPointer = CurrentBufferPointer;\r
+ TailP->hcGTD.BufferEnd = (xferLen) ? (CurrentBufferPointer + xferLen - 1) : NULL;\r
+ TailP->TransferCount = xferLen;\r
+ if (!IOC) {\r
+ TailP->hcGTD.DelayInterrupt = TD_NoInterruptOnComplete; /* Delay Interrupt with */\r
+ }\r
+\r
+ /* Create a new place holder TD & link setup TD to the new place holder */\r
+ ASSERT_STATUS_OK(AllocGtdForEd(EdIdx) );\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static HCD_STATUS QueueGTDs(uint32_t EdIdx, uint8_t *dataBuff, uint32_t xferLen, uint8_t Direction)\r
+{\r
+ while (xferLen > 0) {\r
+ uint16_t TdLen;\r
+ uint32_t MaxTDLen = TD_MAX_XFER_LENGTH - Offset4k((uint32_t) dataBuff);\r
+\r
+ TdLen = MIN(xferLen, MaxTDLen);\r
+ xferLen -= TdLen;\r
+\r
+ ASSERT_STATUS_OK(QueueOneGTD(EdIdx, dataBuff, TdLen, Direction, 0, (xferLen ? 0 : 1)) );\r
+ dataBuff += TdLen;\r
+ }\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static HCD_STATUS WaitForTransferComplete(uint8_t EdIdx)\r
+{\r
+#ifndef __TEST__\r
+ while ( HcdED(EdIdx)->status == HCD_STATUS_TRANSFER_QUEUED ) {}\r
+ return (HCD_STATUS) HcdED(EdIdx)->status;\r
+#else\r
+ return HCD_STATUS_OK;\r
+#endif\r
+}\r
+\r
+static __INLINE HCD_STATUS InsertEndpoint(uint8_t HostID, uint32_t EdIdx, uint8_t ListIndex)\r
+{\r
+ PHC_ED list_head;\r
+ list_head = &(ohci_data[HostID].staticEDs[ListIndex]);\r
+\r
+ HcdED(EdIdx)->hcED.NextED = list_head->NextED;\r
+ list_head->NextED = (uint32_t) HcdED(EdIdx);\r
+\r
+ // if ( IsInterruptEndpoint(EdIdx) )\r
+ // {\r
+ // OHCI_HOST_DATA->staticEDs[ListIndex].TailP += HcdED(EdIdx)->hcED.MaxPackageSize; /* increase the bandwidth for the found list */\r
+ // }\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS RemoveEndpoint(uint8_t HostID, uint32_t EdIdx)\r
+{\r
+ PHCD_EndpointDescriptor prevED;\r
+\r
+ prevED = (PHCD_EndpointDescriptor) & (ohci_data[HostID].staticEDs[HcdED(EdIdx)->ListIndex]);\r
+ while (prevED->hcED.NextED != (uint32_t) HcdED(EdIdx) ) {\r
+ prevED = (PHCD_EndpointDescriptor) (prevED->hcED.NextED);\r
+ }\r
+\r
+ // if ( IsInterruptEndpoint(EdIdx) )\r
+ // {\r
+ // OHCI_HOST_DATA->staticEDs[HcdED(EdIdx)->ListIndex].TailP -= HcdED(EdIdx)->hcED.MaxPackageSize; /* decrease the bandwidth for the removed list */\r
+ // }\r
+ prevED->hcED.NextED = HcdED(EdIdx)->hcED.NextED;\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+#if 0 /* We dont need to manage bandwidth this hard */\r
+\r
+__INLINE uint8_t FindInterruptTransferListIndex(uint8_t HostID, uint8_t Interval)\r
+{\r
+ uint8_t ListLeastBandwidth;\r
+ uint8_t ListEnd;\r
+ uint8_t ListIdx = INTERRUPT_32ms_LIST_HEAD;\r
+\r
+ /* Find the correct interval list with right power of 2, i.e: 1,2,4,8,16,32 ms */\r
+ while ( (ListIdx >= Interval) && (ListIdx >>= 1) ) {}\r
+ ListEnd = ListIdx << 1;\r
+\r
+ /* Find the least bandwidth in the same interval */\r
+ /* Note: For Interrupt Static ED (0 to 62), TailP is used to store the accumulated bandwidth of the list */\r
+ for (ListLeastBandwidth = ListIdx; ListIdx <= ListEnd; ListIdx++ )\r
+ if ( ohci_data[HostID].staticEDs[ListIdx].TailP < ohci_data[HostID].staticEDs[ListLeastBandwidth].TailP ) {\r
+ ListLeastBandwidth = ListIdx;\r
+ }\r
+ return ListLeastBandwidth;\r
+}\r
+\r
+static __INLINE void BuildPeriodicStaticEdTree(uint8_t HostID)\r
+{\r
+#if INTERRUPT_LIST_ENABLE\r
+ /* Build full binary tree for interrupt list */\r
+ uint32_t idx, count;\r
+ uint32_t Balance[16] = {0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF};\r
+\r
+ /* build static tree for 1 -> 16 ms */\r
+ OHCI_HOST_DATA->staticEDs[0].NextED = 0;\r
+ for (idx = 1; idx < INTERRUPT_32ms_LIST_HEAD; idx++)\r
+ OHCI_HOST_DATA->staticEDs[idx].NextED = (uint32_t) &(OHCI_HOST_DATA->staticEDs[(idx - 1) / 2]);\r
+ /* create 32ms EDs which will be assigned to HccaInterruptTable */\r
+ for (count = 0, idx = INTERRUPT_32ms_LIST_HEAD; count < 32; count++, idx++)\r
+ OHCI_HOST_DATA->staticEDs[idx].NextED =\r
+ (uint32_t) &(OHCI_HOST_DATA->staticEDs[Balance[count & 0xF] + INTERRUPT_16ms_LIST_HEAD]);\r
+ /* Hook to HCCA interrupt Table */\r
+ for (idx = 0; idx < 32; idx++)\r
+ OHCI_HOST_DATA->hcca.HccaIntTable[idx] = (uint32_t) &(OHCI_HOST_DATA->staticEDs[idx + INTERRUPT_32ms_LIST_HEAD]);\r
+ OHCI_HOST_DATA->staticEDs[INTERRUPT_1ms_LIST_HEAD].NextED = (uint32_t) &(OHCI_HOST_DATA->staticEDs[ISO_LIST_HEAD]);\r
+#elif ISO_LIST_ENABLE\r
+ for (idx = 0; idx < 32; idx++)\r
+ OHCI_HOST_DATA->hcca.HccaIntTable[idx] = (uint32_t) &(OHCI_HOST_DATA->staticEDs[ISO_LIST_HEAD]);\r
+\r
+#endif\r
+}\r
+\r
+#else\r
+\r
+static __INLINE void BuildPeriodicStaticEdTree(uint8_t HostID)\r
+{\r
+ /* Treat all interrupt interval as 1ms (maximum rate) */\r
+ uint32_t idx;\r
+ for (idx = 0; idx < 32; idx++)\r
+ ohci_data[HostID].hcca.HccaIntTable[idx] = (uint32_t) &(ohci_data[HostID].staticEDs[INTERRUPT_1ms_LIST_HEAD]);\r
+ /* ISO_LIST_HEAD is an alias for INTERRUPT_1ms_LIST_HEAD */\r
+}\r
+\r
+#endif\r
+\r
+static __INLINE uint32_t Align16(uint32_t Value)\r
+{\r
+ return Value & 0xFFFFFFF0UL; /* Bit 31 .. 4 */\r
+}\r
+\r
+static __INLINE PHCD_EndpointDescriptor HcdED(uint8_t idx)\r
+{\r
+ return &(ohci_data[0 /*HostID*/].EDs[idx]);\r
+}\r
+\r
+static __INLINE PHCD_GeneralTransferDescriptor HcdGTD(uint8_t idx)\r
+{\r
+ return &(ohci_data[0 /*HostID*/].gTDs[idx]);\r
+}\r
+\r
+static __INLINE PHCD_IsoTransferDescriptor HcdITD(uint8_t idx)\r
+{\r
+#if ISO_LIST_ENABLE\r
+ return &(ohci_data[0 /*HostID*/].iTDs[idx]);\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+static __INLINE Bool IsIsoEndpoint(uint8_t EdIdx)\r
+{\r
+ return (HcdED(EdIdx)->hcED.Format ==0 ? FALSE : TRUE);\r
+}\r
+\r
+#if 0 // just to clear warning\r
+static __INLINE Bool IsInterruptEndpoint(uint8_t EdIdx)\r
+{\r
+ return (HcdED(EdIdx)->ListIndex < CONTROL_LIST_HEAD) && !IsIsoEndpoint(EdIdx);\r
+}\r
+#endif\r
+\r
+static void PipehandleCreate(uint32_t *pPipeHandle, uint8_t HostID, uint8_t EdIdx)\r
+{\r
+ *pPipeHandle = ((uint32_t) (HostID << 8)) + EdIdx;\r
+}\r
+\r
+static HCD_STATUS PipehandleParse(uint32_t Pipehandle, uint8_t *HostID, uint8_t *EdIdx)\r
+{\r
+ *HostID = Pipehandle >> 8;\r
+ *EdIdx = Pipehandle & 0xFF;\r
+ if ((*HostID >= MAX_USB_CORE) || (*EdIdx >= MAX_ED) || (HcdED(*EdIdx)->inUse == 0)) {\r
+ return HCD_STATUS_PIPEHANDLE_INVALID;\r
+ }\r
+ else {\r
+ return HCD_STATUS_OK;\r
+ }\r
+}\r
+\r
+static __INLINE HCD_STATUS AllocEd(uint8_t DeviceAddr,\r
+ HCD_USB_SPEED DeviceSpeed,\r
+ uint8_t EndpointNumber,\r
+ HCD_TRANSFER_TYPE TransferType,\r
+ HCD_TRANSFER_DIR TransferDir,\r
+ uint16_t MaxPacketSize,\r
+ uint8_t Interval,\r
+ uint32_t *pEdIdx)\r
+{\r
+ /* Looking for free EDs */\r
+ for ((*pEdIdx) = 0; ((*pEdIdx) < MAX_ED) && HcdED((*pEdIdx))->inUse; (*pEdIdx)++) {}\r
+ if ((*pEdIdx) >= MAX_ED) {\r
+ return HCD_STATUS_NOT_ENOUGH_ENDPOINT;\r
+ }\r
+\r
+ /* Init Data for new ED */\r
+ memset(HcdED(*pEdIdx), 0, sizeof(HCD_EndpointDescriptor) );\r
+\r
+ HcdED((*pEdIdx))->inUse = 1;\r
+\r
+ HcdED((*pEdIdx))->hcED.FunctionAddr = DeviceAddr;\r
+ HcdED((*pEdIdx))->hcED.EndpointNumber = EndpointNumber; /* Endpoint number only has 4 bits */\r
+ HcdED((*pEdIdx))->hcED.Direction = (TransferType == CONTROL_TRANSFER) ? 0 : ((TransferDir == OUT_TRANSFER) ? 1 : 2 );\r
+ HcdED((*pEdIdx))->hcED.Speed = (DeviceSpeed == FULL_SPEED) ? 0 : 1;\r
+ HcdED((*pEdIdx))->hcED.Skip = 0;\r
+ HcdED((*pEdIdx))->hcED.Format = (TransferType == ISOCHRONOUS_TRANSFER) ? 1 : 0;\r
+ HcdED((*pEdIdx))->hcED.MaxPackageSize = MaxPacketSize;\r
+ HcdED((*pEdIdx))->Interval = Interval;\r
+\r
+ /* Allocate Place Holder TD as suggested by OHCI 5.2.8 */\r
+ if (TransferType != ISOCHRONOUS_TRANSFER) {\r
+ ASSERT_STATUS_OK(AllocGtdForEd(*pEdIdx) );\r
+ }\r
+ else {\r
+ ASSERT_STATUS_OK(AllocItdForEd(*pEdIdx) );\r
+ }\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static HCD_STATUS AllocGtdForEd(uint8_t EdIdx)\r
+{\r
+ uint32_t GtdIdx;\r
+\r
+ /* Allocate new GTD */\r
+ for (GtdIdx = 0; (GtdIdx < MAX_GTD) && HcdGTD(GtdIdx)->inUse; GtdIdx++) {}\r
+\r
+ if (GtdIdx < MAX_GTD) {\r
+ /*************** Control (word 0) ****************/\r
+ /* Buffer rounding: R = 1b (yes) */\r
+ /* Direction/PID: DP = 00b (SETUP) */\r
+ /* Delay Interrupt: DI = 000b (interrupt) */\r
+ /* Data Toggle: DT = 00b (from ED) */\r
+ /* Error Count: EC = 00b */\r
+ /* Condition Code: CC = 1110b (not accessed) */\r
+ /****************************************************/\r
+ memset(HcdGTD(GtdIdx), 0, sizeof(HCD_GeneralTransferDescriptor));\r
+\r
+ HcdGTD(GtdIdx)->inUse = 1;\r
+ HcdGTD(GtdIdx)->EdIdx = EdIdx;\r
+\r
+ HcdGTD(GtdIdx)->hcGTD.BufferRounding = 1;\r
+ HcdGTD(GtdIdx)->hcGTD.ConditionCode = (uint32_t) HCD_STATUS_TRANSFER_NotAccessed;\r
+\r
+ /* link new GTD to the Endpoint */\r
+ if (HcdED(EdIdx)->hcED.TailP) { /* already have place holder */\r
+ ( (PHCD_GeneralTransferDescriptor) HcdED(EdIdx)->hcED.TailP )->hcGTD.NextTD = (uint32_t) HcdGTD(GtdIdx);\r
+ }\r
+ else { /* have no dummy TD attached to the ED */\r
+ HcdED(EdIdx)->hcED.HeadP.HeadTD = ((uint32_t) HcdGTD(GtdIdx));\r
+ }\r
+ HcdED(EdIdx)->hcED.TailP = (uint32_t) HcdGTD(GtdIdx);\r
+\r
+ return HCD_STATUS_OK;\r
+ }\r
+ else {\r
+ return HCD_STATUS_NOT_ENOUGH_GTD;\r
+ }\r
+\r
+}\r
+\r
+static HCD_STATUS AllocItdForEd(uint8_t EdIdx)\r
+{\r
+ uint32_t ItdIdx;\r
+\r
+ for (ItdIdx = 0; (ItdIdx < MAX_ITD) && HcdITD(ItdIdx)->inUse; ItdIdx++) {}\r
+\r
+ if (ItdIdx < MAX_ITD) {\r
+ memset(HcdITD(ItdIdx), 0, sizeof(HCD_IsoTransferDescriptor) );\r
+ HcdITD(ItdIdx)->inUse = 1;\r
+ HcdITD(ItdIdx)->EdIdx = EdIdx;\r
+\r
+ HcdITD(ItdIdx)->ConditionCode = (uint32_t) HCD_STATUS_TRANSFER_NotAccessed;\r
+\r
+ /* link new ITD to the Endpoint */\r
+ if (HcdED(EdIdx)->hcED.TailP) { /* already have place holder */\r
+ ( (PHCD_IsoTransferDescriptor) HcdED(EdIdx)->hcED.TailP )->NextTD = (uint32_t) HcdITD(ItdIdx);\r
+ }\r
+ else { /* have no dummy TD attached to the ED */\r
+ HcdED(EdIdx)->hcED.HeadP.HeadTD = ((uint32_t) HcdITD(ItdIdx));\r
+ }\r
+ HcdED(EdIdx)->hcED.TailP = (uint32_t) HcdITD(ItdIdx);\r
+\r
+ return HCD_STATUS_OK;\r
+ }\r
+ else {\r
+ return HCD_STATUS_NOT_ENOUGH_ITD;\r
+ }\r
+}\r
+\r
+static __INLINE HCD_STATUS FreeED(uint8_t EdIdx)\r
+{\r
+ /* Remove Place holder TD */\r
+ if ( IsIsoEndpoint(EdIdx) ) {\r
+ FreeItd( (PHCD_IsoTransferDescriptor) HcdED(EdIdx)->hcED.TailP);\r
+ }\r
+ else {\r
+ FreeGtd( (PHCD_GeneralTransferDescriptor) HcdED(EdIdx)->hcED.TailP);\r
+ }\r
+\r
+ HcdED(EdIdx)->status = HCD_STATUS_TRANSFER_NotAccessed;\r
+ HcdED(EdIdx)->inUse = 0;\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS FreeGtd(PHCD_GeneralTransferDescriptor pGtd)\r
+{\r
+ pGtd->inUse = 0;\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS FreeItd(PHCD_IsoTransferDescriptor pItd)\r
+{\r
+ pItd->inUse = 0;\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS OHciHostInit(uint8_t HostID)\r
+{\r
+ uint32_t idx,tem;\r
+\r
+ if ( sizeof(OHCI_HOST_DATA_T) > 0x4000 ) { /* Host data exceed 16 KB */\r
+ ASSERT_STATUS_OK(HCD_STATUS_NOT_ENOUGH_MEMORY);\r
+ }\r
+\r
+ memset(&ohci_data[HostID], 0, sizeof(OHCI_HOST_DATA_T));\r
+ /* Skip writing 1s to HcHCCA, assume it is 256 aligned */\r
+\r
+ /* set skip bit for all static EDs */\r
+ for (idx = 0; idx < MAX_STATIC_ED; idx++)\r
+ ohci_data[HostID].staticEDs[idx].Skip = 1;\r
+\r
+ /* Periodic List Initialization */\r
+ BuildPeriodicStaticEdTree(HostID);\r
+\r
+ /* Initialize OHCI registers */\r
+ USB_REG(HostID)->Control = 0;\r
+ OHciHostOperational(HostID);/* have to turn HC to operational mode before setting up below registers*/\r
+\r
+ USB_REG(HostID)->FmInterval = HC_FMINTERVAL_DEFAULT;\r
+ USB_REG(HostID)->PeriodicStart = PERIODIC_START;\r
+\r
+ USB_REG(HostID)->ControlHeadED = (uint32_t) &(ohci_data[HostID].staticEDs[CONTROL_LIST_HEAD]);\r
+ USB_REG(HostID)->BulkHeadED = (uint32_t) &(ohci_data[HostID].staticEDs[BULK_LIST_HEAD]);\r
+\r
+ USB_REG(HostID)->HCCA = (uint32_t) &(ohci_data[HostID].hcca); /* Hook Hcca */\r
+\r
+ /* Set up HcControl */\r
+ USB_REG(HostID)->Control |= CONTROL_BULK_SERVICE_RATIO |\r
+ (INTERRUPT_ROUTING ? HC_CONTROL_InterruptRouting : 0) |\r
+ (REMOTE_WAKEUP_CONNECTED ? HC_CONTROL_RemoteWakeupConnected : 0) |\r
+ (REMOTE_WAKEUP_ENABLE ? HC_CONTROL_RemoteWakeupEnable : 0) |\r
+ HC_CONTROL_ControlListEnable | HC_CONTROL_BulkListEnable |\r
+ (ISO_LIST_ENABLE ? (HC_CONTROL_PeriodListEnable | HC_CONTROL_IsochronousEnable) :\r
+ (INTERRUPT_LIST_ENABLE ? HC_CONTROL_PeriodListEnable : 0));\r
+\r
+ /* Set Global Power */\r
+ USB_REG(HostID)->RhStatus = HC_RH_STATUS_LocalPowerStatusChange;\r
+\r
+ // HcInterrupt Registers Init\r
+ tem = USB_REG(HostID)->InterruptStatus; // just to clear warning\r
+ USB_REG(HostID)->InterruptStatus |= tem; /* Clear Interrupt Status */\r
+ USB_REG(HostID)->InterruptDisable = HC_INTERRUPT_ALL;/* Disable all interrupts */\r
+ /* Enable necessary Interrupts */\r
+ USB_REG(HostID)->InterruptEnable = HC_INTERRUPT_MasterInterruptEnable | HC_INTERRUPT_WritebackDoneHead |\r
+ HC_INTERRUPT_RootHubStatusChange |\r
+ (SCHEDULING_OVRERRUN_INTERRUPT ? HC_INTERRUPT_SchedulingOverrun : 0 ) |\r
+ (SOF_INTERRUPT ? HC_INTERRUPT_StartofFrame : 0) |\r
+ (RESUME_DETECT_INTERRUPT ? HC_INTERRUPT_ResumeDetected : 0) |\r
+ (UNRECOVERABLE_ERROR_INTERRUPT ? HC_INTERRUPT_UnrecoverableError : 0) |\r
+ (FRAMENUMBER_OVERFLOW_INTERRUPT ? HC_INTERRUPT_FrameNumberOverflow : 0) |\r
+ (OWNERSHIP_CHANGE_INTERRUPT ? HC_INTERRUPT_OwnershipChange : 0 );\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS OHciHostReset(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->CommandStatus = HC_COMMAND_STATUS_HostControllerReset;\r
+ while ( USB_REG(HostID)->CommandStatus & HC_COMMAND_STATUS_HostControllerReset) {} /* FIXME Wait indefinitely (may need a time-out here) */\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS OHciHostOperational(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->Control =\r
+ (USB_REG(HostID)->Control & (~HC_CONTROL_HostControllerFunctionalState)) | (HC_HOST_OPERATIONAL << 6);\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+#if 0 // just to clear warning\r
+static __INLINE HCD_STATUS OHciHostSuspend(uint8_t HostID)\r
+{\r
+ USB_REG(HostID)->Control =\r
+ (USB_REG(HostID)->Control & (~HC_CONTROL_HostControllerFunctionalState)) | (HC_HOST_SUSPEND << 6);\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS OHciRhPortPowerOn(uint8_t HostID, uint8_t uPortNumber)\r
+{\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_PortPowerStatus; /* SetPortPower */\r
+ HcdDelayMS(2 * ( (USB_REG(HostID)->RhDescriptorA & HC_RH_DESCRIPTORA_PowerOnToPowerGoodTime) >> 24 ) ); /* FIXME need to delay here POTPGT */\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS OHciRhPortPowerOff(uint8_t HostID, uint8_t uPortNumber)\r
+{\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_LowSpeedDeviceAttached; /* ClearPortPower */\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS OHciRhPortSuspend(uint8_t HostID, uint8_t uPortNumber)\r
+{\r
+ if ( USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_CurrentConnectStatus) { /* If device is connected */\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_PortSuspendStatus;/* SetPortSuspend */\r
+ }\r
+ HcdDelayMS(3); /* FIXME 3ms for device to suspend */\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+\r
+static __INLINE HCD_STATUS OHciRhPortResume(uint8_t HostID, uint8_t uPortNumber)\r
+{\r
+ if ( USB_REG(HostID)->RhPortStatus1 & HC_RH_PORT_STATUS_CurrentConnectStatus) { /* If port is currently suspended */\r
+ USB_REG(HostID)->RhPortStatus1 = HC_RH_PORT_STATUS_PortOverCurrentIndicator; /* ClearSuspendStatus */\r
+ }\r
+ HcdDelayMS(20); /* FIXME 20ms for device to resume */\r
+\r
+ return HCD_STATUS_OK;\r
+}\r
+#endif\r
+\r
+void HcdSetStreamPacketSize(uint32_t PipeHandle, uint16_t packetsize)\r
+{\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief Open Host Controller Interface\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+/** @ingroup Group_HCD\r
+ * @defgroup Host_OHCI Open Host Controller Interface Driver\r
+ * @{\r
+ */\r
+ \r
+#ifndef __LPC_OHCI_H__\r
+#define __LPC_OHCI_H__\r
+\r
+#ifndef __LPC_OHCI_C__ // TODO INCLUDE FROM OHCI.C\r
+ #error OHCI.h is private header and can only be included by OHCI.c, try to include HCD.h instead\r
+#endif\r
+\r
+#ifdef __TEST__ // suppress static/inline for Testing purpose\r
+ #define static\r
+ #define inline\r
+#endif\r
+\r
+#define MAX_ED HCD_MAX_ENDPOINT\r
+#define MAX_GTD (MAX_ED + 3)\r
+#define MAX_STATIC_ED 3 /* Serve as list head, fixed, not configurable */\r
+\r
+#if ISO_LIST_ENABLE\r
+ #define MAX_ITD 4\r
+#else\r
+ #define MAX_ITD 0\r
+#endif\r
+\r
+#define CONTROL_BULK_SERVICE_RATIO 3 /* Control Bulk transfer ratio 0 = 1:1 - 1 = 2:1 - 2 = 3:1 - 3 = 4:1 */\r
+#define INTERRUPT_ROUTING 0 /* Host interrupt routing 0 = IRQ - 1 = SMI */\r
+#define REMOTE_WAKEUP_CONNECTED NO /* Remote wakeup connected */\r
+#define REMOTE_WAKEUP_ENABLE NO /* Remote wakeup enable */\r
+\r
+#define SCHEDULING_OVRERRUN_INTERRUPT NO\r
+\r
+#define SOF_INTERRUPT NO\r
+#define RESUME_DETECT_INTERRUPT NO\r
+#define UNRECOVERABLE_ERROR_INTERRUPT NO\r
+#define FRAMENUMBER_OVERFLOW_INTERRUPT NO\r
+\r
+#define OWNERSHIP_CHANGE_INTERRUPT NO\r
+\r
+#define FRAME_INTERVAL 0x2EDF /* Reset default value */\r
+#define HC_FMINTERVAL_DEFAULT ((((6 * (FRAME_INTERVAL - 210)) / 7) << 16) | FRAME_INTERVAL)\r
+\r
+#define PERIODIC_START 0x00002A27UL /* 10% off from FRAME_INTERVAL */\r
+\r
+#define PORT_POWER_SWITCHING NO\r
+#define PER_PORT_POWER_SWITCHING NO\r
+#define PER_PORT_OVER_CURRENT_REPORT NO\r
+#define OVER_CURRENT_PROTECTION NO\r
+\r
+#define INTERRUPT_1ms_LIST_HEAD 0\r
+#define INTERRUPT_2ms_LIST_HEAD 1\r
+#define INTERRUPT_4ms_LIST_HEAD 3\r
+#define INTERRUPT_8ms_LIST_HEAD 7\r
+#define INTERRUPT_16ms_LIST_HEAD 15\r
+#define INTERRUPT_32ms_LIST_HEAD 31\r
+#define ISO_LIST_HEAD (MAX_STATIC_ED - 3)\r
+#define CONTROL_LIST_HEAD (MAX_STATIC_ED - 2)\r
+#define BULK_LIST_HEAD (MAX_STATIC_ED - 1)\r
+#define TD_MAX_XFER_LENGTH 0x2000\r
+\r
+#define TD_NoInterruptOnComplete (7)\r
+\r
+#define HC_REVISION 0x000000FFUL\r
+\r
+#define HC_FM_REMAIN 0x00003FFFUL /* Frame remaining */\r
+\r
+#define HC_FM_NUMBER 0x0000FFFFUL /* Frame Number */\r
+\r
+#define HC_CONTROL_ControlBulkServiceRatio 0x00000003UL /* Control/Bulk ratio */\r
+#define HC_CONTROL_PeriodListEnable 0x00000004UL /* Periodic List Enable */\r
+#define HC_CONTROL_IsochronousEnable 0x00000008UL /* Isochronous Enable */\r
+#define HC_CONTROL_ControlListEnable 0x00000010UL /* Control List Enable */\r
+#define HC_CONTROL_BulkListEnable 0x00000020UL /* Bulk List Enable */\r
+#define HC_CONTROL_HostControllerFunctionalState 0x000000C0UL /* Host Controller Functional State */\r
+#define HC_CONTROL_InterruptRouting 0x00000100UL /* Interrupt Routing */\r
+#define HC_CONTROL_RemoteWakeupConnected 0x00000200UL /* Remote Wakeup Connected */\r
+#define HC_CONTROL_RemoteWakeupEnable 0x00000400UL /* Remote Wakeup Enable */\r
+\r
+#define HC_HOST_RESET 0x00000000UL /* Reset state */\r
+#define HC_HOST_RESUME 0X00000001UL /* Resume state */\r
+#define HC_HOST_OPERATIONAL 0x00000002UL /* Operational state */\r
+#define HC_HOST_SUSPEND 0x00000003UL /* Suspend state */\r
+\r
+#define HC_COMMAND_STATUS_HostControllerReset 0x00000001UL /* Host Controller Reset */\r
+#define HC_COMMAND_STATUS_ControlListFilled 0x00000002UL /* Control List Filled */\r
+#define HC_COMMAND_STATUS_BulkListFilled 0x00000004UL /* Bulk List Filled */\r
+\r
+#define HC_INTERRUPT_SchedulingOverrun 0x00000001UL /* Scheduling Overrun */\r
+#define HC_INTERRUPT_WritebackDoneHead 0x00000002UL /* Writeback DoneHead */\r
+#define HC_INTERRUPT_StartofFrame 0x00000004UL /* Start of Frame */\r
+#define HC_INTERRUPT_ResumeDetected 0x00000008UL /* Resume Detect */\r
+#define HC_INTERRUPT_UnrecoverableError 0x00000010UL /* Unrecoverable error */\r
+#define HC_INTERRUPT_FrameNumberOverflow 0x00000020UL /* Frame Number Overflow */\r
+#define HC_INTERRUPT_RootHubStatusChange 0x00000040UL /* Root Hub Status Change */\r
+#define HC_INTERRUPT_OwnershipChange 0x40000000UL /* Ownership Change */\r
+#define HC_INTERRUPT_MasterInterruptEnable 0x80000000UL /* Master Interrupt Enable */\r
+#define HC_INTERRUPT_ALL 0xC000007FUL /* All interrupts */\r
+\r
+#define HC_RH_DESCRIPTORA_NumberDownstreamPorts 0x000000FFUL /* Number of downstream ports */\r
+#define HC_RH_DESCRIPTORA_PowerSwitchingMode 0x00000100UL /* Power Switching Mode */\r
+#define HC_RH_DESCRIPTORA_NoPowerSwitching 0x00000200UL /* No Power Switching */\r
+#define HC_RH_DESCRIPTORA_OverCurrentProtectionMode 0x00000800UL /* OverCurrent Protection Mode */\r
+#define HC_RH_DESCRIPTORA_NoOverCurrentProtection 0x00001000UL /* No OverCurrent Protection */\r
+#define HC_RH_DESCRIPTORA_PowerOnToPowerGoodTime 0xFF000000UL /* Power On To Power Good Time */\r
+\r
+#define HC_RH_DESCRIPTORB_PortPowerControlMask 0xFFFF0000UL /* Port Power Control Mask */\r
+#define HC_RH_DESCRIPTORB_DeviceRemovable 0x0000FFFFUL /* Device Removable */\r
+\r
+#define HC_RH_STATUS_LocalPowerStatus 0x00000001UL /* R: Local Power Status - W: Clear Global Power */\r
+#define HC_RH_STATUS_LocalPowerStatusChange 0x00010000UL /* R: Local Power Status Change - W: Set Global Power */\r
+#define HC_RH_STATUS_DeviceRemoteWakeupEnable 0x00008000UL /* W: Set Remote Wakeup Enable */\r
+\r
+#define HC_RH_PORT_STATUS_CurrentConnectStatus 0x00000001UL /* R: Current Connect Status - W: Clear Port Enable */\r
+#define HC_RH_PORT_STATUS_PowerEnableStatus 0x00000002UL /* R: Port Enable Status - W: Set Port Enable */\r
+#define HC_RH_PORT_STATUS_PortSuspendStatus 0x00000004UL /* R: Port Suspend Status - W: Set Port Suspend */\r
+#define HC_RH_PORT_STATUS_PortOverCurrentIndicator 0x00000008UL /* R: Port OverCurrent Indicator- W: Clear Suspend Status */\r
+#define HC_RH_PORT_STATUS_PortResetStatus 0x00000010UL /* R: Port Reset Status - W: Set Port Reset */\r
+#define HC_RH_PORT_STATUS_PortPowerStatus 0x00000100UL /* R: Port Power Status - W: Set Port Power */\r
+#define HC_RH_PORT_STATUS_LowSpeedDeviceAttached 0x00000200UL /* R: Low Speed Device Attached - W: Clear Port Power */\r
+\r
+#define HC_RH_PORT_STATUS_ConnectStatusChange 0x00010000UL /* Connect Status Change */\r
+#define HC_RH_PORT_STATUS_PortEnableStatusChange 0x00020000UL /* Port Enable Status Change */\r
+#define HC_RH_PORT_STATUS_PortSuspendStatusChange 0x00040000UL /* Port Suspend Status Change */\r
+#define HC_RH_PORT_STATUS_OverCurrentIndicatorChange 0x00080000UL /* OverCurrent Indicator Change */\r
+#define HC_RH_PORT_STATUS_PortResetStatusChange 0x00100000UL /* Port Reset Status Change */\r
+#define HC_RH_PORT_STATUS_StatusChangeMask (HC_RH_PORT_STATUS_ConnectStatusChange | \\r
+ HC_RH_PORT_STATUS_PortEnableStatusChange | \\r
+ HC_RH_PORT_STATUS_PortSuspendStatusChange | \\r
+ HC_RH_PORT_STATUS_OverCurrentIndicatorChange | \\r
+ HC_RH_PORT_STATUS_PortResetStatusChange)\r
+\r
+typedef struct st_HC_HCCA {\r
+ __O uint32_t HccaIntTable[32];\r
+ __I uint16_t HccaFrameNumber;\r
+ __I uint16_t HccaPad1;\r
+ __I uint32_t HccaDoneHead;\r
+ __I uint8_t HccaReserved[116];\r
+} ATTR_ALIGNED (256) HC_HCCA;\r
+\r
+typedef struct st_HC_ED { // 16 byte align\r
+ /*---------- Word 1 ----------*/\r
+ uint32_t FunctionAddr : 7;\r
+ uint32_t EndpointNumber : 4;\r
+ uint32_t Direction : 2;\r
+ uint32_t Speed : 1;\r
+ uint32_t Skip : 1;\r
+ uint32_t Format : 1;\r
+ uint32_t MaxPackageSize : 11;\r
+ uint32_t : 0;/* Force next member on next storage unit */\r
+ /*---------- End Word 1 ----------*/\r
+\r
+ /*---------- Word 2 ----------*/\r
+ uint32_t TailP; // only 28 bits - 16B align\r
+\r
+ /*---------- Word 3 ----------*/\r
+ union {\r
+ uint32_t HeadTD;\r
+ struct {\r
+ uint32_t Halted : 1;\r
+ uint32_t ToggleCarry : 1;\r
+ uint32_t : 30;\r
+ };\r
+\r
+ } HeadP;/* TODO remove this name */\r
+\r
+ /*---------- Word 4 ----------*/\r
+ uint32_t NextED;// only 28 bits - 16B align\r
+} ATTR_ALIGNED (16) HC_ED, *PHC_ED;\r
+\r
+typedef struct st_HCD_EndpointDescriptor { // 32 byte align\r
+ HC_ED hcED;\r
+\r
+ /*---------- Word 1 ----------*/\r
+ uint32_t inUse : 1;\r
+ uint32_t ListIndex : 7; // 0: Interrupt/ISO, 1: Control, 2: bulk\r
+ uint32_t Interval : 8; /* Used by ISO, High speed Bulk/Control maximum NAK */\r
+ uint32_t : 0; /* Force next member on next storage unit */\r
+ /*---------- End Word 1 ----------*/\r
+\r
+ __IO uint32_t status; // TODO status is updated by ISR --> is non-caching\r
+ uint16_t *pActualTransferCount; /* total transferred bytes of a usb request */\r
+\r
+ uint32_t reserved;\r
+} HCD_EndpointDescriptor, *PHCD_EndpointDescriptor;\r
+\r
+typedef struct st_HC_GTD { // 16 byte align\r
+ /*---------- Word 1 ----------*/\r
+ uint32_t : 18;\r
+ uint32_t BufferRounding : 1;\r
+ uint32_t DirectionPID : 2;\r
+ uint32_t DelayInterrupt : 3;\r
+ __IO uint32_t DataToggle : 2;\r
+ __IO uint32_t ErrorCount : 2;\r
+ __IO uint32_t ConditionCode : 4;\r
+ uint32_t : 0; /* Force next member on next storage unit */\r
+ /*---------- End Word 1 ----------*/\r
+\r
+ /*---------- Word 2 ----------*/\r
+ __IO uint8_t *CurrentBufferPointer;\r
+\r
+ /*---------- Word 3 ----------*/\r
+ __IO uint32_t NextTD; // only 28 bits - 16B align\r
+\r
+ /*---------- Word 4 ----------*/\r
+ uint8_t *BufferEnd;\r
+} ATTR_ALIGNED (16) HC_GTD, *PHC_GTD; /* TODO merge into HCD_GeneralTransferDescriptor */\r
+\r
+typedef struct st_HCD_GeneralTransferDescriptor { // 32 byte align\r
+ HC_GTD hcGTD;\r
+\r
+ /*---------- Word 1 ----------*/\r
+ uint32_t inUse : 1;\r
+ uint32_t : 0; /* Force next member on next storage unit */\r
+ /*---------- End Word 1 ----------*/\r
+\r
+ uint16_t EdIdx;\r
+ uint16_t TransferCount;\r
+\r
+ uint32_t reserved2;\r
+ uint32_t reserved3;\r
+} HCD_GeneralTransferDescriptor, *PHCD_GeneralTransferDescriptor;\r
+\r
+typedef struct st_HCD_IsoTransferDescriptor { // 64 byte align\r
+ /*---------- Word 1 ----------*/\r
+ uint32_t StartingFrame : 16;\r
+ uint32_t : 5;\r
+ uint32_t DelayInterrupt : 3;\r
+ uint32_t FrameCount : 3;\r
+ uint32_t : 1;\r
+ __IO uint32_t ConditionCode : 4;\r
+ uint32_t : 0; /* Force next member on next storage unit */\r
+ /*---------- End Word 1 ----------*/\r
+\r
+ /*---------- Word 2 ----------*/\r
+ uint32_t BufferPage0; // only 20 bits - 4KB align\r
+\r
+ /*---------- Word 3 ----------*/\r
+ __IO uint32_t NextTD; // only 27 bits - 32B align\r
+\r
+ /*---------- Word 4 ----------*/\r
+ uint32_t BufferEnd;\r
+\r
+ /*---------- Word 5-8 ----------*/\r
+ __IO uint16_t OffsetPSW[8];\r
+\r
+ /*---------- HCD AREA ----------*/\r
+ /*---------- Word 9 ----------*/\r
+ uint32_t inUse : 1;\r
+ uint32_t : 0; /* Force next member on next storage unit */\r
+ /*---------- End Word 9 ----------*/\r
+\r
+ /*---------- Word 10 ----------*/\r
+ uint16_t EdIdx;\r
+ uint16_t reserved3;\r
+ /*---------- End Word 10 ----------*/\r
+\r
+ uint32_t reserved2[6];\r
+} ATTR_ALIGNED (32) HCD_IsoTransferDescriptor, *PHCD_IsoTransferDescriptor;\r
+\r
+typedef struct st_OHCI_HOST {\r
+ HC_HCCA hcca;\r
+ uint32_t host_reserved1;\r
+#if ISO_LIST_ENABLE\r
+ HCD_IsoTransferDescriptor iTDs[MAX_ITD];\r
+#endif\r
+ HCD_GeneralTransferDescriptor gTDs[MAX_GTD];\r
+ HCD_EndpointDescriptor EDs[MAX_ED];\r
+ HC_ED staticEDs[MAX_STATIC_ED];\r
+} OHCI_HOST_DATA_T;\r
+\r
+// #define OHCI_DATA(HostID) ((OHCI_HOST_DATA_T*) HCD_RAM_ADDR_BASE)\r
+extern OHCI_HOST_DATA_T ohci_data[MAX_USB_CORE];\r
+\r
+static INLINE HCD_STATUS OHciHostInit(uint8_t HostID);\r
+\r
+static INLINE HCD_STATUS OHciHostReset(uint8_t HostID);\r
+\r
+static INLINE HCD_STATUS OHciHostOperational(uint8_t HostID);\r
+\r
+#if 0 // just to clear warning\r
+static INLINE HCD_STATUS OHciHostSuspend(uint8_t HostID);\r
+\r
+static INLINE HCD_STATUS OHciRhPortPowerOn(uint8_t HostID, uint8_t uPortNumber);\r
+\r
+static INLINE HCD_STATUS OHciRhPortPowerOff(uint8_t HostID, uint8_t uPortNumber);\r
+\r
+static INLINE HCD_STATUS OHciRhPortSuspend(uint8_t HostID, uint8_t uPortNumber);\r
+\r
+static INLINE HCD_STATUS OHciRhPortResume(uint8_t HostID, uint8_t uPortNumber);\r
+\r
+static INLINE Bool IsInterruptEndpoint (uint8_t EdIdx);\r
+\r
+#endif\r
+\r
+static INLINE uint32_t Align16 (uint32_t Value);\r
+\r
+static INLINE PHCD_EndpointDescriptor HcdED(uint8_t idx);\r
+\r
+static INLINE PHCD_GeneralTransferDescriptor HcdGTD(uint8_t idx);\r
+\r
+static INLINE PHCD_IsoTransferDescriptor HcdITD(uint8_t idx);\r
+\r
+static INLINE Bool IsIsoEndpoint(uint8_t EdIdx);\r
+\r
+static void PipehandleCreate(uint32_t *pPipeHandle, uint8_t HostID, uint8_t idx);\r
+\r
+static HCD_STATUS PipehandleParse(uint32_t Pipehandle, uint8_t *HostID, uint8_t *EdIdx);\r
+\r
+static INLINE void BuildPeriodicStaticEdTree(uint8_t HostID);\r
+\r
+static INLINE HCD_STATUS AllocEd(uint8_t DeviceAddr,\r
+ HCD_USB_SPEED DeviceSpeed,\r
+ uint8_t EndpointNumber,\r
+ HCD_TRANSFER_TYPE TransferType,\r
+ HCD_TRANSFER_DIR TransferDir,\r
+ uint16_t MaxPacketSize,\r
+ uint8_t Interval,\r
+ uint32_t *pEdIdx);\r
+\r
+static INLINE HCD_STATUS AllocGtdForEd(uint8_t EdIdx);\r
+\r
+static INLINE HCD_STATUS AllocItdForEd(uint8_t EdIdx);\r
+\r
+static INLINE HCD_STATUS FreeED(uint8_t EdIdx);\r
+\r
+static INLINE HCD_STATUS FreeGtd(PHCD_GeneralTransferDescriptor pGtd);\r
+\r
+static INLINE HCD_STATUS FreeItd(PHCD_IsoTransferDescriptor pItd);\r
+\r
+static INLINE HCD_STATUS InsertEndpoint(uint8_t HostID, uint32_t EdIdx, uint8_t ListIndex);\r
+\r
+static INLINE HCD_STATUS RemoveEndpoint(uint8_t HostID, uint32_t EdIdx);\r
+\r
+/*static INLINE uint8_t FindInterruptTransferListIndex(uint8_t HostID, uint8_t Interval);*/\r
+static HCD_STATUS QueueOneGTD (uint32_t EdIdx,\r
+ uint8_t *const CurrentBufferPointer,\r
+ uint32_t xferLen,\r
+ uint8_t DirectionPID,\r
+ uint8_t DataToggle,\r
+ uint8_t IOC);\r
+\r
+static HCD_STATUS QueueGTDs (uint32_t EdIdx, uint8_t *dataBuff, uint32_t xferLen, uint8_t Direction);\r
+\r
+static HCD_STATUS WaitForTransferComplete(uint8_t EdIdx);\r
+\r
+#endif /*defined(__LPC_OHCI__)*/\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * @brief USB Host definitions for the LPC microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_HOST)\r
+\r
+#define __INCLUDE_FROM_HOST_C\r
+#include "Host.h"\r
+\r
+//static uint8_t CurrentHostID = 0;\r
+uint8_t USB_Host_ControlPipeSize[MAX_USB_CORE];\r
+\r
+void USB_Host_SetDeviceSpeed(uint8_t hostid, HCD_USB_SPEED speed);\r
+\r
+HCD_USB_SPEED USB_Host_GetDeviceSpeed(uint8_t hostid);\r
+\r
+void USB_Host_ProcessNextHostState(uint8_t corenum)\r
+{\r
+ uint8_t ErrorCode = HOST_ENUMERROR_NoError;\r
+ uint8_t SubErrorCode = HOST_ENUMERROR_NoError;\r
+\r
+ static uint16_t WaitMSRemaining;\r
+ static uint8_t PostWaitState;\r
+\r
+ switch (USB_HostState[corenum]) {\r
+ case HOST_STATE_WaitForDevice:\r
+ if (WaitMSRemaining) {\r
+ if ((SubErrorCode = USB_Host_WaitMS(1)) != HOST_WAITERROR_Successful) {\r
+ USB_HostState[corenum] = PostWaitState;\r
+ ErrorCode = HOST_ENUMERROR_WaitStage;\r
+ break;\r
+ }\r
+\r
+ if (!(--WaitMSRemaining)) {\r
+ USB_HostState[corenum] = PostWaitState;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case HOST_STATE_Powered:\r
+ WaitMSRemaining = HOST_DEVICE_SETTLE_DELAY_MS;\r
+\r
+ USB_HostState[corenum] = HOST_STATE_Powered_WaitForDeviceSettle;\r
+ break;\r
+\r
+ case HOST_STATE_Powered_WaitForDeviceSettle:\r
+ if (WaitMSRemaining--) {\r
+ Delay_MS(1);\r
+ break;\r
+ }\r
+ else {\r
+ USB_Host_VBUS_Manual_Off();\r
+\r
+ USB_OTGPAD_On();\r
+ USB_Host_VBUS_Auto_Enable();\r
+ USB_Host_VBUS_Auto_On();\r
+\r
+ USB_HostState[corenum] = HOST_STATE_Powered_WaitForConnect;\r
+ }\r
+ break;\r
+\r
+ case HOST_STATE_Powered_WaitForConnect:\r
+ HOST_TASK_NONBLOCK_WAIT(corenum, 100, HOST_STATE_Powered_DoReset);\r
+ break;\r
+\r
+ case HOST_STATE_Powered_DoReset: {\r
+ HCD_USB_SPEED DeviceSpeed;\r
+ HcdRhPortReset(corenum);\r
+ HcdGetDeviceSpeed(corenum,&DeviceSpeed); // skip checking status\r
+ USB_Host_SetDeviceSpeed(corenum, DeviceSpeed);\r
+ HOST_TASK_NONBLOCK_WAIT(corenum, 200, HOST_STATE_Powered_ConfigPipe);\r
+ }\r
+ break;\r
+\r
+ case HOST_STATE_Powered_ConfigPipe:\r
+ if (!Pipe_ConfigurePipe(corenum, PIPE_CONTROLPIPE, EP_TYPE_CONTROL,\r
+ PIPE_TOKEN_SETUP, ENDPOINT_CONTROLEP,\r
+ PIPE_CONTROLPIPE_DEFAULT_SIZE, PIPE_BANK_SINGLE) ) {\r
+ ErrorCode = HOST_ENUMERROR_PipeConfigError;\r
+ SubErrorCode = 0;\r
+ break;\r
+ }\r
+\r
+ USB_HostState[corenum] = HOST_STATE_Default;\r
+ break;\r
+\r
+ case HOST_STATE_Default: {\r
+ USB_Descriptor_Device_t DevDescriptor;\r
+ USB_ControlRequest = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE),\r
+ .bRequest = REQ_GetDescriptor,\r
+ .wValue = (DTYPE_Device << 8),\r
+ .wIndex = 0,\r
+ .wLength = 8,\r
+ };\r
+\r
+ if ((SubErrorCode = USB_Host_SendControlRequest(corenum, &DevDescriptor)) != HOST_SENDCONTROL_Successful) {\r
+ ErrorCode = HOST_ENUMERROR_ControlError;\r
+ break;\r
+ }\r
+\r
+ USB_Host_ControlPipeSize[corenum] = DevDescriptor.Endpoint0Size;\r
+\r
+ Pipe_ClosePipe(corenum, PIPE_CONTROLPIPE);\r
+ HcdRhPortReset(corenum);\r
+\r
+ HOST_TASK_NONBLOCK_WAIT(corenum, 200, HOST_STATE_Default_PostReset);\r
+ }\r
+ break;\r
+\r
+ case HOST_STATE_Default_PostReset:\r
+ if (!Pipe_ConfigurePipe(corenum, PIPE_CONTROLPIPE, EP_TYPE_CONTROL,\r
+ PIPE_TOKEN_SETUP, ENDPOINT_CONTROLEP,\r
+ USB_Host_ControlPipeSize[corenum], PIPE_BANK_SINGLE) ) {\r
+ ErrorCode = HOST_ENUMERROR_PipeConfigError;\r
+ SubErrorCode = 0;\r
+ break;\r
+ }\r
+\r
+ USB_ControlRequest = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_DEVICE),\r
+ .bRequest = REQ_SetAddress,\r
+ .wValue = USB_HOST_DEVICEADDRESS,\r
+ .wIndex = 0,\r
+ .wLength = 0,\r
+ };\r
+\r
+ if ((SubErrorCode = USB_Host_SendControlRequest(corenum, NULL)) != HOST_SENDCONTROL_Successful) {\r
+ ErrorCode = HOST_ENUMERROR_ControlError;\r
+ break;\r
+ }\r
+\r
+ Pipe_ClosePipe(corenum, PIPE_CONTROLPIPE);\r
+ HOST_TASK_NONBLOCK_WAIT(corenum, 100, HOST_STATE_Default_PostAddressSet);\r
+ break;\r
+\r
+ case HOST_STATE_Default_PostAddressSet:\r
+ Pipe_ConfigurePipe(corenum, PIPE_CONTROLPIPE, EP_TYPE_CONTROL,\r
+ PIPE_TOKEN_SETUP, ENDPOINT_CONTROLEP,\r
+ USB_Host_ControlPipeSize[corenum], PIPE_BANK_SINGLE);\r
+\r
+ USB_Host_SetDeviceAddress(USB_HOST_DEVICEADDRESS);\r
+\r
+ USB_HostState[corenum] = HOST_STATE_Addressed;\r
+\r
+ EVENT_USB_Host_DeviceEnumerationComplete(corenum);\r
+ break;\r
+ }\r
+\r
+ if ((ErrorCode != HOST_ENUMERROR_NoError) && (USB_HostState[corenum] != HOST_STATE_Unattached)) {\r
+ EVENT_USB_Host_DeviceEnumerationFailed(corenum, ErrorCode, SubErrorCode);\r
+\r
+ USB_Host_VBUS_Auto_Off();\r
+\r
+ EVENT_USB_Host_DeviceUnattached(corenum);\r
+\r
+ USB_ResetInterface(corenum, USB_MODE_Host);\r
+ }\r
+}\r
+\r
+uint8_t USB_Host_WaitMS(uint8_t MS)\r
+{\r
+ return HOST_WAITERROR_Successful;\r
+}\r
+\r
+void USB_Host_Enumerate(uint8_t HostId) /* Part of Interrupt Service Routine */\r
+{\r
+ // CurrentHostID = HostId;\r
+ // hostselected = HostId;\r
+ EVENT_USB_Host_DeviceAttached(HostId);\r
+ USB_HostState[HostId] = HOST_STATE_Powered;\r
+}\r
+\r
+void USB_Host_DeEnumerate(uint8_t HostId) /* Part of Interrupt Service Routine */\r
+{\r
+ uint8_t i;\r
+\r
+ Pipe_ClosePipe(HostId, PIPE_CONTROLPIPE); // FIXME close only relevant pipes , take long time in ISR\r
+ for (i = PIPE_CONTROLPIPE + 1; i < PIPE_TOTAL_PIPES; i++)\r
+ if (PipeInfo[HostId][i].PipeHandle != 0) {\r
+ Pipe_ClosePipe(HostId, i);\r
+ }\r
+\r
+ EVENT_USB_Host_DeviceUnattached(HostId);\r
+ USB_HostState[HostId] = HOST_STATE_Unattached;\r
+}\r
+\r
+void USB_Host_SetActiveHost(uint8_t hostid)\r
+{\r
+ hostselected = hostid;\r
+}\r
+\r
+uint8_t USB_Host_GetActiveHost(void)\r
+{\r
+ return hostselected;\r
+}\r
+\r
+void USB_Host_SetDeviceSpeed(uint8_t hostid, HCD_USB_SPEED speed)\r
+{\r
+ hostportspeed[hostid] = speed;\r
+}\r
+\r
+HCD_USB_SPEED USB_Host_GetDeviceSpeed(uint8_t hostid)\r
+{\r
+ if (hostid <= 1) {\r
+ return hostportspeed[hostid];\r
+ }\r
+ else {return LOW_SPEED; }\r
+}\r
+\r
+uint16_t USB_Host_GetFrameNumber(void)\r
+{\r
+ return HcdGetFrameNumber(USB_Host_GetActiveHost());\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief Common USB Host definitions for all architectures\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_Host Host Management\r
+ * @brief USB Host management definitions for USB host mode.\r
+ *\r
+ * USB Host mode related macros and enums. This module contains macros and enums which are used when\r
+ * the USB controller is initialized in host mode.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __USBHOST_H__\r
+#define __USBHOST_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h" \r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Enums: */\r
+ /** Enum for the various states of the USB Host state machine.\r
+ *\r
+ * For information on each possible USB host state, refer to the USB 2.0 specification.\r
+ * Several of the USB host states are broken up further into multiple smaller sub-states,\r
+ * so that they can be internally implemented inside the library in an efficient manner.\r
+ *\r
+ * @see @ref USB_HostState, which stores the current host state machine state.\r
+ */\r
+ enum USB_Host_States_t\r
+ {\r
+ HOST_STATE_WaitForDevice = 0, /**< This state indicates that the stack is waiting for an interval\r
+ * to elapse before continuing with the next step of the device\r
+ * enumeration process.\r
+ */\r
+ HOST_STATE_Unattached = 1, /**< This state indicates that the host state machine is waiting for\r
+ * a device to be attached so that it can start the enumeration process.\r
+ */\r
+ HOST_STATE_Powered = 2, /**< This state indicates that a device has been attached, and the\r
+ * library's internals are being configured to begin the enumeration\r
+ * process.\r
+ */\r
+ HOST_STATE_Powered_WaitForDeviceSettle = 3, /**< This state indicates that the stack is waiting for the initial\r
+ * settling period to elapse before beginning the enumeration process.\r
+ */\r
+ HOST_STATE_Powered_WaitForConnect = 4, /**< This state indicates that the stack is waiting for a connection event\r
+ * from the USB controller to indicate a valid USB device has been attached\r
+ * to the bus and is ready to be enumerated.\r
+ */\r
+ HOST_STATE_Powered_DoReset = 5, /**< This state indicates that a valid USB device has been attached, and that\r
+ * it will now be reset to ensure it is ready for enumeration.\r
+ */\r
+ HOST_STATE_Powered_ConfigPipe = 6, /**< This state indicates that the attached device is currently powered and\r
+ * reset, and that the control pipe is now being configured by the stack.\r
+ */\r
+ HOST_STATE_Default = 7, /**< This state indicates that the stack is currently retrieving the control\r
+ * endpoint's size from the device, so that the control pipe can be altered\r
+ * to match.\r
+ */\r
+ HOST_STATE_Default_PostReset = 8, /**< This state indicates that the control pipe is being reconfigured to match\r
+ * the retrieved control endpoint size from the device, and the device's USB\r
+ * bus address is being set.\r
+ */\r
+ HOST_STATE_Default_PostAddressSet = 9, /**< This state indicates that the device's address has now been set, and the\r
+ * stack is has now completed the device enumeration process. This state causes \r
+ * the stack to change the current USB device address to that set for the\r
+ * connected device, before progressing to the @ref HOST_STATE_Addressed state\r
+ * ready for use in the user application.\r
+ */\r
+ HOST_STATE_Addressed = 10, /**< Indicates that the device has been enumerated and addressed, and is now waiting\r
+ * for the user application to configure the device ready for use. \r
+ */\r
+ HOST_STATE_Configured = 11, /**< Indicates that the device has been configured into a valid device configuration,\r
+ * ready for general use by the user application. \r
+ */\r
+ };\r
+\r
+ #include "StdDescriptors.h"\r
+ #include "Pipe.h"\r
+ #include "USBInterrupt.h"\r
+ \r
+ /* Macros: */\r
+ /** Indicates the fixed USB device address which any attached device is enumerated to when in\r
+ * host mode. As only one USB device may be attached to the LPC in host mode at any one time\r
+ * and that the address used is not important (other than the fact that it is non-zero), a\r
+ * fixed value is specified by the library.\r
+ */\r
+ #define USB_HOST_DEVICEADDRESS 1\r
+\r
+ #if !defined(USB_HOST_TIMEOUT_MS) || defined(__DOXYGEN__)\r
+ /** Constant for the maximum software timeout period of sent USB control transactions to an attached\r
+ * device. If a device fails to respond to a sent control request within this period, the\r
+ * library will return a timeout error code.\r
+ *\r
+ * This value may be overridden in the user project makefile as the value of the\r
+ * @ref USB_HOST_TIMEOUT_MS token, and passed to the compiler using the -D switch.\r
+ */\r
+ #define USB_HOST_TIMEOUT_MS 1000\r
+ #endif\r
+\r
+ #if !defined(HOST_DEVICE_SETTLE_DELAY_MS) || defined(__DOXYGEN__)\r
+ /** Constant for the delay in milliseconds after a device is connected before the library\r
+ * will start the enumeration process. Some devices require a delay of up to 5 seconds\r
+ * after connection before the enumeration process can start or incorrect operation will\r
+ * occur.\r
+ *\r
+ * The default delay value may be overridden in the user project makefile by defining the\r
+ * \c HOST_DEVICE_SETTLE_DELAY_MS token to the required delay in milliseconds, and passed to the\r
+ * compiler using the -D switch.\r
+ */\r
+ #define HOST_DEVICE_SETTLE_DELAY_MS 1000\r
+ #endif\r
+\r
+ /** Enum for the error codes for the @ref EVENT_USB_Host_HostError() event.\r
+ *\r
+ * @see @ref Group_Events for more information on this event.\r
+ */\r
+ enum USB_Host_ErrorCodes_t {\r
+ HOST_ERROR_VBusVoltageDip = 0, /**< VBUS voltage dipped to an unacceptable level. This\r
+ * error may be the result of an attached device drawing\r
+ * too much current from the VBUS line, or due to the\r
+ * LPC's power source being unable to supply sufficient\r
+ * current.\r
+ */\r
+ };\r
+\r
+ /** Enum for the error codes for the @ref EVENT_USB_Host_DeviceEnumerationFailed() event.\r
+ *\r
+ * @see @ref Group_Events for more information on this event.\r
+ */\r
+ enum USB_Host_EnumerationErrorCodes_t {\r
+ HOST_ENUMERROR_NoError = 0, /**< No error occurred. Used internally, this is not a valid\r
+ * ErrorCode parameter value for the @ref EVENT_USB_Host_DeviceEnumerationFailed()\r
+ * event.\r
+ */\r
+ HOST_ENUMERROR_WaitStage = 1, /**< One of the delays between enumeration steps failed\r
+ * to complete successfully, due to a timeout or other\r
+ * error.\r
+ */\r
+ HOST_ENUMERROR_NoDeviceDetected = 2, /**< No device was detected, despite the USB data lines\r
+ * indicating the attachment of a device.\r
+ */\r
+ HOST_ENUMERROR_ControlError = 3, /**< One of the enumeration control requests failed to\r
+ * complete successfully.\r
+ */\r
+ HOST_ENUMERROR_PipeConfigError = 4, /**< The default control pipe (address 0) failed to\r
+ * configure correctly.\r
+ */\r
+ };\r
+\r
+ /**\r
+ * @brief Get current active host core number\r
+ * @return Active USB host core number\r
+ */\r
+ uint8_t USB_Host_GetActiveHost(void);\r
+\r
+ /** Array stores pre-set size of control pipe of all available USB cores\r
+ */\r
+ extern uint8_t USB_Host_ControlPipeSize[MAX_USB_CORE];\r
+\r
+ /* Inline Functions: */\r
+ #if !defined(NO_SOF_EVENTS)\r
+\r
+ /**\r
+ * @brief Enables the host mode Start Of Frame events. When enabled, this causes the\r
+ * @ref EVENT_USB_Host_StartOfFrame() event to fire once per millisecond, synchronized to the USB bus,\r
+ * at the start of each USB frame when a device is enumerated while in host mode.\r
+ *\r
+ * @note Not available when the \c NO_SOF_EVENTS compile time token is defined.\r
+ * @return Nothing\r
+ */\r
+ static inline void USB_Host_EnableSOFEvents(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_EnableSOFEvents(void)\r
+ {}\r
+\r
+ /**\r
+ * @brief Disables the host mode Start Of Frame events. When disabled, this stops the firing of the\r
+ * @ref EVENT_USB_Host_StartOfFrame() event when enumerated in host mode.\r
+ *\r
+ * @note Not available when the NO_SOF_EVENTS compile time token is defined.\r
+ * @return Nothing\r
+ */\r
+ static inline void USB_Host_DisableSOFEvents(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_DisableSOFEvents(void)\r
+ {}\r
+\r
+ #endif\r
+\r
+ /**\r
+ * @brief Resets the USB bus, including the endpoints in any attached device and pipes on the LPC host.\r
+ * USB bus resets leave the default control pipe configured (if already configured).\r
+ *\r
+ * If the USB bus has been suspended prior to issuing a bus reset, the attached device will be\r
+ * woken up automatically and the bus resumed after the reset has been correctly issued.\r
+ * @return Nothing\r
+ */\r
+ static inline void USB_Host_ResetBus(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_ResetBus(void)\r
+ {}\r
+\r
+ /**\r
+ * @brief Determines if a previously issued bus reset (via the @ref USB_Host_ResetBus() macro) has\r
+ * completed.\r
+ * @return Boolean \c true if no bus reset is currently being sent, \c false otherwise.\r
+ */\r
+ static inline bool USB_Host_IsBusResetComplete(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool USB_Host_IsBusResetComplete(void)\r
+ {\r
+ return true;\r
+ }\r
+\r
+ /**\r
+ * @brief Resumes USB communications with an attached and enumerated device, by resuming the transmission\r
+ * of the 1MS Start Of Frame messages to the device. When resumed, USB communications between the\r
+ * host and attached device may occur.\r
+ * @return Nothing\r
+ */\r
+ static inline void USB_Host_ResumeBus(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_ResumeBus(void)\r
+ {}\r
+\r
+ /**\r
+ * @brief Suspends the USB bus, preventing any communications from occurring between the host and attached\r
+ * device until the bus has been resumed. This stops the transmission of the 1MS Start Of Frame\r
+ * messages to the device.\r
+ * @return Nothing\r
+ */\r
+ static inline void USB_Host_SuspendBus(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_SuspendBus(void)\r
+ {}\r
+\r
+ /**\r
+ * @brief Determines if the USB bus has been suspended via the use of the @ref USB_Host_SuspendBus() macro,\r
+ * false otherwise. While suspended, no USB communications can occur until the bus is resumed,\r
+ * except for the Remote Wakeup event from the device if supported.\r
+ *\r
+ * @return Boolean \c true if the bus is currently suspended, \c false otherwise.\r
+ */\r
+ static inline bool USB_Host_IsBusSuspended(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool USB_Host_IsBusSuspended(void)\r
+ {\r
+ return false;\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the attached device is currently enumerated in Full Speed mode (12Mb/s), or\r
+ * false if the attached device is enumerated in Low Speed mode (1.5Mb/s).\r
+ *\r
+ * @return Boolean \c true if the attached device is enumerated in Full Speed mode, \c false otherwise.\r
+ */\r
+ static inline bool USB_Host_IsDeviceFullSpeed(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool USB_Host_IsDeviceFullSpeed(void)\r
+ {\r
+ return true; // implement later when needed\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the attached device is currently issuing a Remote Wakeup request, requesting\r
+ * that the host resume the USB bus and wake up the device, false otherwise.\r
+ *\r
+ * @return Boolean \c true if the attached device has sent a Remote Wakeup request, \c false otherwise.\r
+ */\r
+ static inline bool USB_Host_IsRemoteWakeupSent(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool USB_Host_IsRemoteWakeupSent(void)\r
+ {\r
+ return false;\r
+ }\r
+\r
+ /** Clears the flag indicating that a Remote Wakeup request has been issued by an attached device. */\r
+ static inline void USB_Host_ClearRemoteWakeupSent(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_ClearRemoteWakeupSent(void)\r
+ {}\r
+\r
+ /** Accepts a Remote Wakeup request from an attached device. This must be issued in response to\r
+ * a device's Remote Wakeup request within 2ms for the request to be accepted and the bus to\r
+ * be resumed.\r
+ */\r
+ static inline void USB_Host_ResumeFromWakeupRequest(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_ResumeFromWakeupRequest(void)\r
+ {}\r
+\r
+ /**\r
+ * @brief Determines if a resume from Remote Wakeup request is currently being sent to an attached\r
+ * device.\r
+ *\r
+ * @return Boolean \c true if no resume request is currently being sent, \c false otherwise.\r
+ */\r
+ static inline bool USB_Host_IsResumeFromWakeupRequestSent(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool USB_Host_IsResumeFromWakeupRequestSent(void)\r
+ {\r
+ return false;\r
+ }\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Macros: */\r
+ static inline void USB_Host_HostMode_On(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_HostMode_On(void)\r
+ {}\r
+\r
+ static inline void USB_Host_HostMode_Off(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_HostMode_Off(void)\r
+ {}\r
+\r
+ static inline void USB_Host_VBUS_Auto_Enable(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_VBUS_Auto_Enable(void)\r
+ {}\r
+\r
+ static inline void USB_Host_VBUS_Manual_Enable(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_VBUS_Manual_Enable(void)\r
+ {}\r
+\r
+ static inline void USB_Host_VBUS_Auto_On(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_VBUS_Auto_On(void)\r
+ {}\r
+\r
+ static inline void USB_Host_VBUS_Manual_On(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_VBUS_Manual_On(void)\r
+ {}\r
+\r
+ static inline void USB_Host_VBUS_Auto_Off(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_VBUS_Auto_Off(void)\r
+ {}\r
+\r
+ static inline void USB_Host_VBUS_Manual_Off(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_VBUS_Manual_Off(void)\r
+ {}\r
+\r
+ static inline void USB_Host_SetDeviceAddress(const uint8_t Address) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Host_SetDeviceAddress(const uint8_t Address)\r
+ {}\r
+\r
+ /* Enums: */\r
+ /** Enum defines error codes returned by \ref USB_Host_WaitMS()\r
+ */\r
+ enum USB_Host_WaitMSErrorCodes_t {\r
+ HOST_WAITERROR_Successful = 0,\r
+ HOST_WAITERROR_DeviceDisconnect = 1,\r
+ HOST_WAITERROR_PipeError = 2,\r
+ HOST_WAITERROR_SetupStalled = 3,\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ /**\r
+ * @brief Perform enumeration process\r
+ *\r
+ * @param corenum: active USB port number\r
+ * @return Nothing\r
+ */\r
+ void USB_Host_ProcessNextHostState(uint8_t corenum);\r
+\r
+ /**\r
+ * @brief A delay function use in host\r
+ * @note This function currently is not inplemented\r
+ * @return always return HOST_WAITERROR_Successful \ref USB_Host_WaitMSErrorCodes_t\r
+ */\r
+ uint8_t USB_Host_WaitMS(uint8_t MS);\r
+\r
+ /**\r
+ * @brief Returns the current USB frame number, when in host mode. Every millisecond the USB bus is active (i.e. not suspended)\r
+ * the frame number is incremented by one.\r
+ * @return Current frame number on active USB port\r
+ */\r
+ uint16_t USB_Host_GetFrameNumber(void);\r
+\r
+ #if defined(__INCLUDE_FROM_HOST_C)\r
+ // static void USB_Host_ResetDevice(void);\r
+ #endif\r
+ #endif\r
+\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB host standard request management\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_HOST)\r
+\r
+#define __INCLUDE_FROM_HOSTSTDREQ_C\r
+#include "HostStandardReq.h"\r
+\r
+uint8_t USB_Host_ConfigurationNumber;\r
+\r
+#if 1\r
+\r
+uint8_t USB_Host_SendControlRequest(const uint8_t corenum, void* const BufferPtr)\r
+{\r
+ uint8_t* DataStream = (uint8_t*)BufferPtr;\r
+ uint16_t DataLen = USB_ControlRequest.wLength;\r
+ uint8_t ret;\r
+\r
+ if ((USB_ControlRequest.bmRequestType & CONTROL_REQTYPE_DIRECTION) == REQDIR_HOSTTODEVICE)\r
+ {\r
+ Pipe_Write_Stream_LE(corenum, BufferPtr, DataLen, NULL);\r
+ }\r
+\r
+ ret = (uint8_t)HcdControlTransfer(PipeInfo[corenum][pipeselected[corenum]].PipeHandle, &USB_ControlRequest,\r
+ PipeInfo[corenum][pipeselected[corenum]].Buffer);\r
+\r
+ if(ret == (uint8_t)HOST_SENDCONTROL_Successful)\r
+ {\r
+ if ((USB_ControlRequest.bmRequestType & CONTROL_REQTYPE_DIRECTION) == REQDIR_DEVICETOHOST)\r
+ {\r
+ PipeInfo[corenum][pipeselected[corenum]].ByteTransfered = USB_ControlRequest.wLength;\r
+ while(DataLen)\r
+ {\r
+ *(DataStream++) = Pipe_Read_8(corenum);\r
+ DataLen--;\r
+ }\r
+ /* Pipe_Read_Stream_LE(BufferPtr, DataLen, NULL); cannot use read stream as it call HcdDataTransfer*/\r
+ }\r
+ PipeInfo[corenum][pipeselected[corenum]].StartIdx = PipeInfo[corenum][pipeselected[corenum]].ByteTransfered = 0; /* Clear Control Pipe */\r
+ return HOST_SENDCONTROL_Successful;\r
+ }\r
+ else\r
+ {\r
+ return HOST_SENDCONTROL_PipeError;\r
+ }\r
+}\r
+\r
+#else // The following code is deprecated\r
+uint8_t USB_Host_SendControlRequest(void* const BufferPtr)\r
+{\r
+ uint8_t* DataStream = (uint8_t*)BufferPtr;\r
+ bool BusSuspended = USB_Host_IsBusSuspended();\r
+ uint8_t ReturnStatus = HOST_SENDCONTROL_Successful;\r
+ uint16_t DataLen = USB_ControlRequest.wLength;\r
+\r
+ USB_Host_ResumeBus();\r
+\r
+ if ((ReturnStatus = USB_Host_WaitMS(1)) != HOST_WAITERROR_Successful)\r
+ goto End_Of_Control_Send;\r
+\r
+ Pipe_SetPipeToken(PIPE_TOKEN_SETUP);\r
+ Pipe_ClearError();\r
+\r
+ Pipe_Unfreeze();\r
+\r
+ Pipe_Write_8(USB_ControlRequest.bmRequestType);\r
+ Pipe_Write_8(USB_ControlRequest.bRequest);\r
+ Pipe_Write_16_LE(USB_ControlRequest.wValue);\r
+ Pipe_Write_16_LE(USB_ControlRequest.wIndex);\r
+ Pipe_Write_16_LE(USB_ControlRequest.wLength);\r
+\r
+ Pipe_ClearSETUP();\r
+\r
+ if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_SetupSent)) != HOST_SENDCONTROL_Successful)\r
+ goto End_Of_Control_Send;\r
+\r
+ Pipe_Freeze();\r
+\r
+ if ((ReturnStatus = USB_Host_WaitMS(1)) != HOST_WAITERROR_Successful)\r
+ goto End_Of_Control_Send;\r
+\r
+ if ((USB_ControlRequest.bmRequestType & CONTROL_REQTYPE_DIRECTION) == REQDIR_DEVICETOHOST)\r
+ {\r
+ Pipe_SetPipeToken(PIPE_TOKEN_IN);\r
+\r
+ if (DataStream != NULL)\r
+ {\r
+ while (DataLen)\r
+ {\r
+ Pipe_Unfreeze();\r
+\r
+ if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_InReceived)) != HOST_SENDCONTROL_Successful)\r
+ goto End_Of_Control_Send;\r
+\r
+ if (!(Pipe_BytesInPipe()))\r
+ DataLen = 0;\r
+\r
+ while (Pipe_BytesInPipe() && DataLen)\r
+ {\r
+ *(DataStream++) = Pipe_Read_8();\r
+ DataLen--;\r
+ }\r
+\r
+ Pipe_Freeze();\r
+ Pipe_ClearIN();\r
+ }\r
+ }\r
+\r
+ Pipe_SetPipeToken(PIPE_TOKEN_OUT);\r
+ Pipe_Unfreeze();\r
+\r
+ if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_OutReady)) != HOST_SENDCONTROL_Successful)\r
+ goto End_Of_Control_Send;\r
+\r
+ Pipe_ClearOUT();\r
+\r
+ if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_OutReady)) != HOST_SENDCONTROL_Successful)\r
+ goto End_Of_Control_Send;\r
+ }\r
+ else\r
+ {\r
+ if (DataStream != NULL)\r
+ {\r
+ Pipe_SetPipeToken(PIPE_TOKEN_OUT);\r
+ Pipe_Unfreeze();\r
+\r
+ while (DataLen)\r
+ {\r
+ if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_OutReady)) != HOST_SENDCONTROL_Successful)\r
+ goto End_Of_Control_Send;\r
+\r
+ while (DataLen && (Pipe_BytesInPipe() < USB_Host_ControlPipeSize))\r
+ {\r
+ Pipe_Write_8(*(DataStream++));\r
+ DataLen--;\r
+ }\r
+\r
+ Pipe_ClearOUT();\r
+ }\r
+\r
+ if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_OutReady)) != HOST_SENDCONTROL_Successful)\r
+ goto End_Of_Control_Send;\r
+\r
+ Pipe_Freeze();\r
+ }\r
+\r
+ Pipe_SetPipeToken(PIPE_TOKEN_IN);\r
+ Pipe_Unfreeze();\r
+\r
+ if ((ReturnStatus = USB_Host_WaitForIOS(USB_HOST_WAITFOR_InReceived)) != HOST_SENDCONTROL_Successful)\r
+ goto End_Of_Control_Send;\r
+\r
+ Pipe_ClearIN();\r
+ }\r
+\r
+End_Of_Control_Send:\r
+ Pipe_Freeze();\r
+\r
+ if (BusSuspended)\r
+ USB_Host_SuspendBus();\r
+\r
+ Pipe_ResetPipe(PIPE_CONTROLPIPE);\r
+\r
+ return ReturnStatus;\r
+}\r
+\r
+static uint8_t USB_Host_WaitForIOS(const uint8_t WaitType)\r
+{\r
+ #if (USB_HOST_TIMEOUT_MS < 0xFF)\r
+ uint8_t TimeoutCounter = USB_HOST_TIMEOUT_MS;\r
+ #else\r
+ uint16_t TimeoutCounter = USB_HOST_TIMEOUT_MS;\r
+ #endif\r
+\r
+ while (!(((WaitType == USB_HOST_WAITFOR_SetupSent) && Pipe_IsSETUPSent()) ||\r
+ ((WaitType == USB_HOST_WAITFOR_InReceived) && Pipe_IsINReceived()) ||\r
+ ((WaitType == USB_HOST_WAITFOR_OutReady) && Pipe_IsOUTReady())))\r
+ {\r
+ uint8_t ErrorCode;\r
+\r
+ if ((ErrorCode = USB_Host_WaitMS(1)) != HOST_WAITERROR_Successful)\r
+ return ErrorCode;\r
+\r
+ if (!(TimeoutCounter--))\r
+ return HOST_SENDCONTROL_SoftwareTimeOut;\r
+ }\r
+\r
+ return HOST_SENDCONTROL_Successful;\r
+}\r
+#endif\r
+\r
+uint8_t USB_Host_SetDeviceConfiguration(const uint8_t corenum, const uint8_t ConfigNumber)\r
+{\r
+ uint8_t ErrorCode;\r
+\r
+ USB_ControlRequest = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_DEVICE),\r
+ .bRequest = REQ_SetConfiguration,\r
+ .wValue = ConfigNumber,\r
+ .wIndex = 0,\r
+ .wLength = 0,\r
+ };\r
+\r
+ Pipe_SelectPipe(corenum, PIPE_CONTROLPIPE);\r
+ \r
+ if ((ErrorCode = USB_Host_SendControlRequest(corenum, NULL)) == HOST_SENDCONTROL_Successful)\r
+ {\r
+ USB_Host_ConfigurationNumber = ConfigNumber;\r
+ USB_HostState[corenum] = (ConfigNumber) ? HOST_STATE_Configured : HOST_STATE_Addressed;\r
+ }\r
+\r
+ return ErrorCode;\r
+}\r
+\r
+uint8_t USB_Host_GetDeviceDescriptor(const uint8_t corenum, void* const DeviceDescriptorPtr)\r
+{\r
+ USB_ControlRequest = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE),\r
+ .bRequest = REQ_GetDescriptor,\r
+ .wValue = (DTYPE_Device << 8),\r
+ .wIndex = 0,\r
+ .wLength = sizeof(USB_Descriptor_Device_t),\r
+ };\r
+\r
+ Pipe_SelectPipe(corenum, PIPE_CONTROLPIPE);\r
+\r
+ return USB_Host_SendControlRequest(corenum,DeviceDescriptorPtr);\r
+}\r
+\r
+uint8_t USB_Host_GetDeviceStringDescriptor(const uint8_t corenum,\r
+ const uint8_t Index,\r
+ void* const Buffer,\r
+ const uint8_t BufferLength)\r
+{\r
+ USB_ControlRequest = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE),\r
+ .bRequest = REQ_GetDescriptor,\r
+ .wValue = (DTYPE_String << 8) | Index,\r
+ .wIndex = 0,\r
+ .wLength = BufferLength,\r
+ };\r
+\r
+ Pipe_SelectPipe(corenum, PIPE_CONTROLPIPE);\r
+\r
+ return USB_Host_SendControlRequest(corenum,Buffer);\r
+}\r
+\r
+uint8_t USB_Host_GetDeviceStatus(const uint8_t corenum, uint8_t* const FeatureStatus)\r
+{\r
+ USB_ControlRequest = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_STANDARD | REQREC_DEVICE),\r
+ .bRequest = REQ_GetStatus,\r
+ .wValue = 0,\r
+ .wIndex = 0,\r
+ .wLength = 0,\r
+ };\r
+\r
+ Pipe_SelectPipe(corenum, PIPE_CONTROLPIPE);\r
+\r
+ return USB_Host_SendControlRequest(corenum, FeatureStatus);\r
+}\r
+\r
+uint8_t USB_Host_ClearEndpointStall(const uint8_t corenum, const uint8_t EndpointAddress)\r
+{\r
+ USB_ControlRequest = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_ENDPOINT),\r
+ .bRequest = REQ_ClearFeature,\r
+ .wValue = FEATURE_SEL_EndpointHalt,\r
+ .wIndex = EndpointAddress,\r
+ .wLength = 0,\r
+ };\r
+\r
+ Pipe_SelectPipe(corenum, PIPE_CONTROLPIPE);\r
+\r
+ return USB_Host_SendControlRequest(corenum,NULL);\r
+}\r
+\r
+uint8_t USB_Host_SetInterfaceAltSetting(const uint8_t corenum,\r
+ const uint8_t InterfaceIndex,\r
+ const uint8_t AltSetting)\r
+{\r
+ USB_ControlRequest = (USB_Request_Header_t)\r
+ {\r
+ .bmRequestType = (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_INTERFACE),\r
+ .bRequest = REQ_SetInterface,\r
+ .wValue = AltSetting,\r
+ .wIndex = InterfaceIndex,\r
+ .wLength = 0,\r
+ };\r
+\r
+ Pipe_SelectPipe(corenum, PIPE_CONTROLPIPE);\r
+\r
+ return USB_Host_SendControlRequest(corenum,NULL);\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief USB host standard request management\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __HOSTSTDREQ_H__\r
+#define __HOSTSTDREQ_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h"\r
+ #include "StdRequestType.h"\r
+ #include "USBController.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ #if !defined(USB_HOST_TIMEOUT_MS) || defined(__DOXYGEN__)\r
+ /** Constant for the maximum software timeout period of sent USB control transactions to an attached\r
+ * device. If a device fails to respond to a sent control request within this period, the\r
+ * library will return a timeout error code.\r
+ *\r
+ * This value may be overridden in the user project makefile as the value of the\r
+ * @ref USB_HOST_TIMEOUT_MS token, and passed to the compiler using the -D switch.\r
+ */\r
+ #define USB_HOST_TIMEOUT_MS 1000\r
+ #endif\r
+ \r
+ /* Enums: */\r
+ /** Enum for the @ref USB_Host_SendControlRequest() return code, indicating the reason for the error\r
+ * if the transfer of the request is unsuccessful.\r
+ *\r
+ * @ingroup Group_PipeControlReq\r
+ */\r
+ enum USB_Host_SendControlErrorCodes_t\r
+ {\r
+ HOST_SENDCONTROL_Successful = 0, /**< No error occurred in the request transfer. */\r
+ HOST_SENDCONTROL_DeviceDisconnected = 1, /**< The attached device was disconnected during the\r
+ * request transfer.\r
+ */\r
+ HOST_SENDCONTROL_PipeError = 2, /**< An error occurred in the pipe while sending the request. */\r
+ HOST_SENDCONTROL_SetupStalled = 3, /**< The attached device stalled the request, usually\r
+ * indicating that the request is unsupported on the device.\r
+ */\r
+ HOST_SENDCONTROL_SoftwareTimeOut = 4, /**< The request or data transfer timed out. */\r
+ };\r
+\r
+ /* Global Variables: */\r
+ /** Indicates the currently set configuration number of the attached device. This indicates the currently\r
+ * selected configuration value if one has been set sucessfully, or 0 if no configuration has been selected.\r
+ *\r
+ * To set a device configuration, call the @ref USB_Host_SetDeviceConfiguration() function.\r
+ *\r
+ * @note This variable should be treated as read-only in the user application, and never manually\r
+ * changed in value.\r
+ *\r
+ * @ingroup Group_Host\r
+ */\r
+ extern uint8_t USB_Host_ConfigurationNumber;\r
+ \r
+ /* Function Prototypes: */\r
+ /** @brief Sends the request stored in the @ref USB_ControlRequest global structure to the attached device,\r
+ * and transfers the data stored in the buffer to the device, or from the device to the buffer\r
+ * as requested. The transfer is made on the currently selected pipe.\r
+ *\r
+ * @ingroup Group_PipeControlReq\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param BufferPtr : Pointer to the start of the data buffer if the request has a data stage, or\r
+ * \c NULL if the request transfers no data to or from the device.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum to indicate the result.\r
+ */\r
+ uint8_t USB_Host_SendControlRequest(const uint8_t corenum, void* const BufferPtr);\r
+\r
+ /** @brief Sends a SET CONFIGURATION standard request to the attached device, with the given configuration index.\r
+ *\r
+ * This routine will automatically update the @ref USB_HostState and @ref USB_Host_ConfigurationNumber\r
+ * state variables according to the given function parameters and the result of the request.\r
+ *\r
+ * @note After this routine returns, the control pipe will be selected.\r
+ *\r
+ * @ingroup Group_PipeControlReq\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param ConfigNumber : Configuration index to send to the device.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum to indicate the result.\r
+ */\r
+ uint8_t USB_Host_SetDeviceConfiguration(const uint8_t corenum, const uint8_t ConfigNumber);\r
+\r
+ /** @brief Sends a GET DESCRIPTOR standard request to the attached device, requesting the device descriptor.\r
+ * This can be used to easily retrieve information about the device such as its VID, PID and power\r
+ * requirements.\r
+ *\r
+ * @note After this routine returns, the control pipe will be selected.\r
+ *\r
+ * @ingroup Group_PipeControlReq\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param DeviceDescriptorPtr : Pointer to the destination device descriptor structure where\r
+ * the read data is to be stored.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum to indicate the result.\r
+ */\r
+ uint8_t USB_Host_GetDeviceDescriptor(const uint8_t corenum, void* const DeviceDescriptorPtr) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Sends a GET DESCRIPTOR standard request to the attached device, requesting the string descriptor\r
+ * of the specified index. This can be used to easily retrieve string descriptors from the device by\r
+ * index, after the index is obtained from the Device or Configuration descriptors.\r
+ *\r
+ * @note After this routine returns, the control pipe will be selected.\r
+ *\r
+ * @ingroup Group_PipeControlReq\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Index : Index of the string index to retrieve.\r
+ * @param Buffer : Pointer to the destination buffer where the retrieved string descriptor is\r
+ * to be stored.\r
+ * @param BufferLength : Maximum size of the string descriptor which can be stored into the buffer.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum to indicate the result.\r
+ */\r
+ uint8_t USB_Host_GetDeviceStringDescriptor(const uint8_t corenum,\r
+ const uint8_t Index,\r
+ void* const Buffer,\r
+ const uint8_t BufferLength) ATTR_NON_NULL_PTR_ARG(3);\r
+\r
+ /** @brief Retrieves the current feature status of the attached device, via a GET STATUS standard request. The\r
+ * retrieved feature status can then be examined by masking the retrieved value with the various\r
+ * FEATURE_* masks for bus/self power information and remote wakeup support.\r
+ *\r
+ * @note After this routine returns, the control pipe will be selected.\r
+ *\r
+ * @ingroup Group_PipeControlReq\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param FeatureStatus : Location where the retrieved feature status should be stored.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum to indicate the result.\r
+ */\r
+ uint8_t USB_Host_GetDeviceStatus(const uint8_t corenum, uint8_t* const FeatureStatus) ATTR_NON_NULL_PTR_ARG(2);\r
+\r
+ /** @brief Clears a stall condition on the given pipe, via a CLEAR FEATURE standard request to the attached device.\r
+ *\r
+ * @note After this routine returns, the control pipe will be selected.\r
+ *\r
+ * @ingroup Group_PipeControlReq\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param EndpointAddress : Address of the endpoint to clear, including the endpoint's direction.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum to indicate the result.\r
+ */\r
+ uint8_t USB_Host_ClearEndpointStall(const uint8_t corenum, const uint8_t EndpointAddress);\r
+\r
+ /** @brief Selects a given alternative setting for the specified interface, via a SET INTERFACE standard request to\r
+ * the attached device.\r
+ *\r
+ * @note After this routine returns, the control pipe will be selected.\r
+ *\r
+ * @ingroup Group_PipeControlReq\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param InterfaceIndex : Index of the interface whose alternative setting is to be altered.\r
+ * @param AltSetting : Index of the interface's alternative setting which is to be selected.\r
+ *\r
+ * @return A value from the @ref USB_Host_SendControlErrorCodes_t enum to indicate the result.\r
+ */\r
+ uint8_t USB_Host_SetInterfaceAltSetting(const uint8_t corenum,\r
+ const uint8_t InterfaceIndex,\r
+ const uint8_t AltSetting);\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Enums: */\r
+ enum USB_WaitForTypes_t\r
+ {\r
+ USB_HOST_WAITFOR_SetupSent,\r
+ USB_HOST_WAITFOR_InReceived,\r
+ USB_HOST_WAITFOR_OutReady,\r
+ };\r
+\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_HOSTSTDREQ_C)\r
+ // static uint8_t USB_Host_WaitForIOS(const uint8_t WaitType); Deprecated\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief Common USB OTG definitions for all architectures\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_OTG USB On The Go (OTG) Management\r
+ * @brief USB OTG management definitions.\r
+ *\r
+ * This module contains macros for embedded USB hosts with dual role On The Go capabilities, for managing role\r
+ * exchange. OTG is a way for two USB dual role devices to talk to one another directly without fixed device/host\r
+ * roles.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __USBOTG_H__\r
+#define __USBOTG_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h" \r
+ \r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Architecture Includes: */\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Pipe definitions for the LPC microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_HOST)\r
+\r
+#include "Pipe.h"\r
+\r
+uint8_t pipeselected[MAX_USB_CORE];\r
+USB_Pipe_Data_t PipeInfo[MAX_USB_CORE][PIPE_TOTAL_PIPES];\r
+\r
+HCD_USB_SPEED hostportspeed[MAX_USB_CORE];\r
+uint8_t hostselected;\r
+\r
+bool Pipe_ConfigurePipe(const uint8_t corenum,\r
+ const uint8_t Number,\r
+ const uint8_t Type,\r
+ const uint8_t Token,\r
+ const uint8_t EndpointNumber,\r
+ const uint16_t Size,\r
+ const uint8_t Banks)\r
+{\r
+ if ( HCD_STATUS_OK == HcdOpenPipe(corenum, /* HostID */\r
+ (( Type == EP_TYPE_CONTROL) &&\r
+ ( USB_HostState[corenum] <\r
+ HOST_STATE_Default_PostAddressSet) ) ? 0 : USB_HOST_DEVICEADDRESS, /* FIXME DeviceAddr */\r
+ hostportspeed[corenum], /* DeviceSpeed */\r
+ EndpointNumber, /* EndpointNo */\r
+ (HCD_TRANSFER_TYPE) Type, /* TransferType */\r
+ (HCD_TRANSFER_DIR) Token, /* TransferDir */\r
+ Size, /* MaxPacketSize */\r
+ 1, /* Interval */\r
+ 1, /* Mult */\r
+ 0, /* HSHubDevAddr */\r
+ 0, /* HSHubPortNum */\r
+ &PipeInfo[corenum][Number].PipeHandle /* PipeHandle */)\r
+ ) {\r
+ PipeInfo[corenum][Number].ByteTransfered = PipeInfo[corenum][Number].StartIdx = 0;\r
+ PipeInfo[corenum][Number].BufferSize = (Type == EP_TYPE_BULK || Type == EP_TYPE_CONTROL) ? PIPE_MAX_SIZE : Size;/* XXX Some devices could have configuration descriptor > 235 bytes (eps speaker, webcame). If not deal with those, not need to have such large pipe size for control */\r
+ PipeInfo[corenum][Number].Buffer = USB_Memory_Alloc(PipeInfo[corenum][Number].BufferSize,0);\r
+ PipeInfo[corenum][Number].EndponitAddress = EndpointNumber;\r
+ if (PipeInfo[corenum][Number].Buffer == NULL) {\r
+ return false;\r
+ }\r
+\r
+ return true;\r
+ }\r
+ else {\r
+ return false;\r
+ }\r
+}\r
+\r
+void Pipe_ClosePipe(const uint8_t corenum, uint8_t pipenum)\r
+{\r
+ if (pipenum < PIPE_TOTAL_PIPES) {\r
+ HcdClosePipe(PipeInfo[corenum][pipenum].PipeHandle);\r
+ PipeInfo[corenum][pipenum].PipeHandle = 0;\r
+ USB_Memory_Free(PipeInfo[corenum][pipenum].Buffer);\r
+ PipeInfo[corenum][pipenum].Buffer = NULL;\r
+ PipeInfo[corenum][pipenum].BufferSize = 0;\r
+ }\r
+}\r
+\r
+void Pipe_ClearPipes(void)\r
+{}\r
+\r
+bool Pipe_IsEndpointBound(const uint8_t EndpointAddress)\r
+{\r
+ return false;\r
+}\r
+\r
+uint8_t Pipe_WaitUntilReady(const uint8_t corenum)\r
+{\r
+ /* #if (USB_STREAM_TIMEOUT_MS < 0xFF)\r
+ uint8_t TimeoutMSRem = USB_STREAM_TIMEOUT_MS;\r
+ #else\r
+ uint16_t TimeoutMSRem = USB_STREAM_TIMEOUT_MS;\r
+ #endif\r
+\r
+ uint16_t PreviousFrameNumber = USB_Host_GetFrameNumber();*/\r
+\r
+ for (;; ) {\r
+ if (Pipe_IsReadWriteAllowed(corenum)) {\r
+ return PIPE_READYWAIT_NoError;\r
+ }\r
+\r
+ if (Pipe_IsStalled(corenum)) {\r
+ return PIPE_READYWAIT_PipeStalled;\r
+ }\r
+ else if (USB_HostState[corenum] == HOST_STATE_Unattached) {\r
+ return PIPE_READYWAIT_DeviceDisconnected;\r
+ }\r
+\r
+ /*TODO no timeout yet */\r
+ /* uint16_t CurrentFrameNumber = USB_Host_GetFrameNumber();\r
+\r
+ if (CurrentFrameNumber != PreviousFrameNumber)\r
+ {\r
+ PreviousFrameNumber = CurrentFrameNumber;\r
+\r
+ if (!(TimeoutMSRem--))\r
+ return PIPE_READYWAIT_Timeout;\r
+ }*/\r
+ }\r
+}\r
+\r
+bool Pipe_IsINReceived(const uint8_t corenum)\r
+{\r
+ if (HCD_STATUS_OK != HcdGetPipeStatus(PipeInfo[corenum][pipeselected[corenum]].PipeHandle)) {\r
+ return false;\r
+ }\r
+\r
+ if (Pipe_BytesInPipe(corenum)) {\r
+ return true;\r
+ }\r
+ else { /* Empty Pipe */\r
+ HcdDataTransfer(PipeInfo[corenum][pipeselected[corenum]].PipeHandle,\r
+ PipeInfo[corenum][pipeselected[corenum]].Buffer,\r
+ HCD_ENDPOINT_MAXPACKET_XFER_LEN,\r
+ &PipeInfo[corenum][pipeselected[corenum]].ByteTransfered);\r
+ return false;\r
+ }\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief Common USB Pipe definitions for all architectures\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_PipeManagement\r
+ * @defgroup Group_PipeRW Pipe Data Reading and Writing\r
+ * @brief Pipe data read/write definitions.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing from and to pipes.\r
+ */\r
+\r
+/** @ingroup Group_PipeRW\r
+ * @defgroup Group_PipePrimitiveRW Read/Write of Primitive Data Types\r
+ * @brief Pipe data primitive read/write definitions.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing of primitive data types\r
+ * from and to pipes.\r
+ */\r
+\r
+/** @ingroup Group_PipeManagement\r
+ * @defgroup Group_PipePacketManagement Pipe Packet Management\r
+ * @brief Pipe packet management definitions.\r
+ *\r
+ * Functions, macros, variables, enums and types related to packet management of pipes.\r
+ */\r
+\r
+/** @ingroup Group_PipeManagement\r
+ * @defgroup Group_PipeControlReq Pipe Control Request Management\r
+ * @brief Pipe control request definitions.\r
+ *\r
+ * Module for host mode request processing. This module allows for the transmission of standard, class and\r
+ * vendor control requests to the default control endpoint of an attached device while in host mode.\r
+ *\r
+ * @see Chapter 9 of the USB 2.0 specification.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_PipeManagement Pipe Management\r
+ * @brief Pipe management definitions.\r
+ *\r
+ * This module contains functions, macros and enums related to pipe management when in USB Host mode. This\r
+ * module contains the pipe management macros, as well as pipe interrupt and data send/receive functions\r
+ * for various data types.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __PIPE_H__\r
+#define __PIPE_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** Pipe address for the default control pipe, which always resides in address 0. This is\r
+ * defined for convenience to give more readable code when used with the pipe macros.\r
+ */\r
+ #define PIPE_CONTROLPIPE 0\r
+\r
+ /** Pipe number mask, for masking against pipe addresses to retrieve the pipe's numerical address\r
+ * in the device.\r
+ */\r
+ #define PIPE_PIPENUM_MASK 0x0F\r
+\r
+ /** Endpoint number mask, for masking against endpoint addresses to retrieve the endpoint's\r
+ * numerical address in the attached device.\r
+ */\r
+ #define PIPE_EPNUM_MASK 0x0F\r
+\r
+ /** Endpoint direction mask, for masking against endpoint addresses to retrieve the endpoint's\r
+ * direction for comparing with the \c ENDPOINT_DESCRIPTOR_DIR_* masks.\r
+ */\r
+ #define PIPE_EPDIR_MASK 0x80\r
+\r
+ #include "USBTask.h"\r
+ #include "HCD/HCD.h"\r
+ #include "USBMemory.h" // FIXME move later\r
+ #include <stdbool.h>\r
+ \r
+ /* Macros: */\r
+ /** \name Pipe Error Flag Masks */\r
+ // @{\r
+ /** Mask for @ref Pipe_GetErrorFlags(), indicating that an overflow error occurred in the pipe on the received data. */\r
+ #define PIPE_ERRORFLAG_OVERFLOW (1 << 6)\r
+\r
+ /** Mask for @ref Pipe_GetErrorFlags(), indicating that an underflow error occurred in the pipe on the received data. */\r
+ #define PIPE_ERRORFLAG_UNDERFLOW (1 << 5)\r
+\r
+ /** Mask for @ref Pipe_GetErrorFlags(), indicating that a CRC error occurred in the pipe on the received data. */\r
+ #define PIPE_ERRORFLAG_CRC16 (1 << 4)\r
+\r
+ /** Mask for @ref Pipe_GetErrorFlags(), indicating that a hardware timeout error occurred in the pipe. */\r
+ #define PIPE_ERRORFLAG_TIMEOUT (1 << 3)\r
+\r
+ /** Mask for @ref Pipe_GetErrorFlags(), indicating that a hardware PID error occurred in the pipe. */\r
+ #define PIPE_ERRORFLAG_PID (1 << 2)\r
+\r
+ /** Mask for @ref Pipe_GetErrorFlags(), indicating that a hardware data PID error occurred in the pipe. */\r
+ #define PIPE_ERRORFLAG_DATAPID (1 << 1)\r
+\r
+ /** Mask for @ref Pipe_GetErrorFlags(), indicating that a hardware data toggle error occurred in the pipe. */\r
+ #define PIPE_ERRORFLAG_DATATGL (1 << 0)\r
+ //@}\r
+\r
+ /** \name Pipe Token Masks */\r
+ //@{\r
+ /** Token mask for @ref Pipe_ConfigurePipe(). This sets the pipe as a SETUP token (for CONTROL type pipes),\r
+ * which will trigger a control request on the attached device when data is written to the pipe.\r
+ */\r
+ #define PIPE_TOKEN_SETUP (0)\r
+\r
+ /** Token mask for @ref Pipe_ConfigurePipe(). This sets the pipe as a IN token (for non-CONTROL type pipes),\r
+ * indicating that the pipe data will flow from device to host.\r
+ */\r
+ #define PIPE_TOKEN_IN (1)\r
+\r
+ /** Token mask for @ref Pipe_ConfigurePipe(). This sets the pipe as a OUT token (for non-CONTROL type pipes),\r
+ * indicating that the pipe data will flow from host to device.\r
+ */\r
+ #define PIPE_TOKEN_OUT (2)\r
+ //@}\r
+ \r
+ /** \name Pipe Bank Mode Masks */\r
+ //@{\r
+ /** Mask for the bank mode selection for the @ref Pipe_ConfigurePipe() macro. This indicates that the pipe\r
+ * should have one single bank, which requires less USB FIFO memory but results in slower transfers as\r
+ * only one USB device (the LPC or the attached device) can access the pipe's bank at the one time.\r
+ */\r
+ #define PIPE_BANK_SINGLE (0 << 1)\r
+\r
+ /** Mask for the bank mode selection for the @ref Pipe_ConfigurePipe() macro. This indicates that the pipe\r
+ * should have two banks, which requires more USB FIFO memory but results in faster transfers as one\r
+ * USB device (the LPC or the attached device) can access one bank while the other accesses the second\r
+ * bank.\r
+ */\r
+ #define PIPE_BANK_DOUBLE (1 << 1)\r
+ //@}\r
+\r
+ /** Default size of the default control pipe's bank, until altered by the Endpoint0Size value\r
+ * in the device descriptor of the attached device.\r
+ */\r
+ #define PIPE_CONTROLPIPE_DEFAULT_SIZE 8\r
+\r
+ /** Total number of pipes (including the default control pipe at address 0) which may be used in\r
+ * the device. Different USB LPC models support different amounts of pipes, this value reflects\r
+ * the maximum number of pipes for the currently selected LPC model.\r
+ */\r
+ #define PIPE_TOTAL_PIPES HCD_MAX_ENDPOINT\r
+\r
+ /** Size in bytes of the largest pipe bank size possible in the device. Not all banks on each LPC\r
+ * model supports the largest bank size possible on the device; different pipe numbers support\r
+ * different maximum bank sizes. This value reflects the largest possible bank of any pipe on the\r
+ * currently selected USB LPC model.\r
+ */\r
+ #define PIPE_MAX_SIZE 512\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible error return codes of the @ref Pipe_WaitUntilReady() function.\r
+ *\r
+ * @ingroup Group_PipeRW\r
+ */\r
+ enum Pipe_WaitUntilReady_ErrorCodes_t {\r
+ PIPE_READYWAIT_NoError = 0, /**< Pipe ready for next packet, no error. */\r
+ PIPE_READYWAIT_PipeStalled = 1, /**< The device stalled the pipe while waiting. */\r
+ PIPE_READYWAIT_DeviceDisconnected = 2, /**< Device was disconnected from the host while waiting. */\r
+ PIPE_READYWAIT_Timeout = 3, /**< The device failed to accept or send the next packet\r
+ * within the software timeout period set by the\r
+ * @ref USB_STREAM_TIMEOUT_MS macro.\r
+ */\r
+ };\r
+\r
+ /** Structure stores necessary information to control a pipe\r
+ */\r
+ typedef struct {\r
+ uint32_t PipeHandle; /**< Encode chip's USB port number, index to specific transfer array */\r
+ uint8_t *Buffer; /**< Pointer to share memory space between this pipe and USB module */\r
+ uint16_t BufferSize; /**< Size of the share memory */\r
+ uint16_t StartIdx; /**< Indexer inside share buffer */\r
+ uint16_t ByteTransfered; /**< Number of bytes transfer */\r
+ uint8_t EndponitAddress; /**< Logical address of connected endpoint */\r
+ } USB_Pipe_Data_t;\r
+\r
+ /** Current active USB module number\r
+ */\r
+ extern uint8_t hostselected;\r
+\r
+ /** USB speed of connected devices\r
+ */\r
+ extern HCD_USB_SPEED hostportspeed[];\r
+\r
+ /** Array stores current active pipe number of each USB module\r
+ */\r
+ extern uint8_t pipeselected[MAX_USB_CORE];\r
+\r
+ /** Array stores all pipes \ref USB_Pipe_Data_t information available of all USB modules\r
+ */\r
+ extern USB_Pipe_Data_t PipeInfo[MAX_USB_CORE][PIPE_TOTAL_PIPES];\r
+\r
+ /* Inline Functions: */\r
+ /**\r
+ * @brief Indicates the number of bytes currently stored in the current pipes's selected bank.\r
+ *\r
+ * @note The return width of this function may differ, depending on the maximum pipe bank size\r
+ * of the selected LPC model.\r
+ *\r
+ * @ingroup Group_PipeRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Total number of bytes in the currently selected pipe's FIFO buffer\r
+ */\r
+ static inline uint16_t Pipe_BytesInPipe(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint16_t Pipe_BytesInPipe(const uint8_t corenum)\r
+ {\r
+ return PipeInfo[corenum][pipeselected[corenum]].ByteTransfered - PipeInfo[corenum][pipeselected[corenum]].StartIdx;\r
+ }\r
+\r
+ /**\r
+ * @brief Returns the pipe address of the currently selected pipe. This is typically used to save the\r
+ * currently selected pipe number so that it can be restored after another pipe has been manipulated.\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Index of the currently selected pipe\r
+ */\r
+ static inline uint8_t Pipe_GetCurrentPipe(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Pipe_GetCurrentPipe(const uint8_t corenum)\r
+ {\r
+ return pipeselected[corenum];\r
+ }\r
+\r
+ /**\r
+ * @brief Selects the given pipe number. Any pipe operations which do not require the pipe number to be\r
+ * indicated will operate on the currently selected pipe.\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param PipeNumber : Index of the pipe to select\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_SelectPipe(const uint8_t corenum, const uint8_t PipeNumber) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_SelectPipe(const uint8_t corenum, const uint8_t PipeNumber)\r
+ {\r
+ pipeselected[corenum] = PipeNumber;\r
+ }\r
+\r
+ /**\r
+ * @brief Resets the desired pipe, including the pipe banks and flags\r
+ * @param corenum : USB port number\r
+ * @param PipeNumber : Index of the pipe to reset\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_ResetPipe(const uint8_t corenum, const uint8_t PipeNumber) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_ResetPipe(const uint8_t corenum, const uint8_t PipeNumber)\r
+ {\r
+ PipeInfo[corenum][pipeselected[corenum]].StartIdx = PipeInfo[corenum][pipeselected[corenum]].ByteTransfered = 0;\r
+ }\r
+\r
+ /** Enables the currently selected pipe so that data can be sent and received through it to and from\r
+ * an attached device.\r
+ *\r
+ * \pre The currently selected pipe must first be configured properly via @ref Pipe_ConfigurePipe().\r
+ */\r
+ static inline void Pipe_EnablePipe(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_EnablePipe(void)\r
+ {\r
+ // TODO implement later\r
+ }\r
+\r
+ /** Disables the currently selected pipe so that data cannot be sent and received through it to and\r
+ * from an attached device.\r
+ */\r
+ static inline void Pipe_DisablePipe(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_DisablePipe(void)\r
+ {\r
+ // TODO implement later\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the currently selected pipe is enabled, but not necessarily configured\r
+ * @return Boolean \c true if the currently selected pipe is enabled, \c false otherwise.\r
+ */\r
+ static inline bool Pipe_IsEnabled(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_IsEnabled(void)\r
+ {\r
+ // TODO implement later\r
+ return true;\r
+ }\r
+\r
+ /**\r
+ * @brief Gets the current pipe token, indicating the pipe's data direction and type\r
+ * @param corenum : USB port number\r
+ * @return The current pipe token, as a \c PIPE_TOKEN_* mask.\r
+ */\r
+ static inline uint8_t Pipe_GetPipeToken(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Pipe_GetPipeToken(const uint8_t corenum)\r
+ {\r
+ return (PipeInfo[corenum][pipeselected[corenum]].EndponitAddress &\r
+ PIPE_EPDIR_MASK) ? PIPE_TOKEN_IN : PIPE_TOKEN_OUT;\r
+ }\r
+\r
+ /**\r
+ * @brief Sets the token for the currently selected pipe to one of the tokens specified by the \c PIPE_TOKEN_*\r
+ * masks. This can be used on CONTROL type pipes, to allow for bidirectional transfer of data during\r
+ * control requests, or on regular pipes to allow for half-duplex bidirectional data transfer to devices\r
+ * which have two endpoints of opposite direction sharing the same endpoint address within the device.\r
+ *\r
+ * @param Token : New pipe token to set the selected pipe to, as a \c PIPE_TOKEN_* mask.\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_SetPipeToken(const uint8_t Token) ATTR_DEPRECATED ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_SetPipeToken(const uint8_t Token)\r
+ {}\r
+\r
+ /** Configures the currently selected pipe to allow for an unlimited number of IN requests. */\r
+ static inline void Pipe_SetInfiniteINRequests(void) ATTR_DEPRECATED ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_SetInfiniteINRequests(void)\r
+ {}\r
+\r
+ /**\r
+ * @brief Configures the currently selected pipe to only allow the specified number of IN requests to be\r
+ * accepted by the pipe before it is automatically frozen.\r
+ *\r
+ * @param TotalINRequests : Total number of IN requests that the pipe may receive before freezing\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_SetFiniteINRequests(const uint8_t TotalINRequests) ATTR_DEPRECATED ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_SetFiniteINRequests(const uint8_t TotalINRequests)\r
+ {}\r
+\r
+ /**\r
+ * @brief Determines if the currently selected pipe is configured.\r
+ * @param corenum : USB port number\r
+ * @return Boolean \c true if the selected pipe is configured, \c false otherwise.\r
+ */\r
+ static inline bool Pipe_IsConfigured(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_IsConfigured(const uint8_t corenum)\r
+ {\r
+ return PipeInfo[corenum][pipeselected[corenum]].Buffer != NULL; // TODO implement using status later\r
+ }\r
+\r
+ /**\r
+ * @brief Retrieves the endpoint address of the endpoint within the attached device that the currently selected\r
+ * pipe is bound to.\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return address the currently selected pipe is bound to.\r
+ */\r
+ static inline uint8_t Pipe_GetBoundEndpointAddress(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Pipe_GetBoundEndpointAddress(const uint8_t corenum)\r
+ {\r
+ return PipeInfo[corenum][pipeselected[corenum]].EndponitAddress;\r
+ }\r
+\r
+ /**\r
+ * @brief Sets the period between interrupts for an INTERRUPT type pipe to a specified number of milliseconds\r
+ * @param Milliseconds : Number of milliseconds between each pipe poll.\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_SetInterruptPeriod(const uint8_t Milliseconds) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_SetInterruptPeriod(const uint8_t Milliseconds)\r
+ {\r
+ // TODO implement later\r
+ }\r
+\r
+ /**\r
+ * @brief Returns a mask indicating which pipe's interrupt periods have elapsed, indicating that the pipe should\r
+ * be serviced.\r
+ * @return Mask whose bits indicate which pipes have interrupted.\r
+ */\r
+ static inline uint8_t Pipe_GetPipeInterrupts(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Pipe_GetPipeInterrupts(void)\r
+ {\r
+ return 0; // TODO implement later\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the specified pipe number has interrupted (valid only for INTERRUPT type\r
+ * pipes).\r
+ *\r
+ * @param PipeNumber : Index of the pipe whose interrupt flag should be tested\r
+ * @return Boolean \c true if the specified pipe has interrupted, \c false otherwise.\r
+ */\r
+ static inline bool Pipe_HasPipeInterrupted(const uint8_t PipeNumber) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_HasPipeInterrupted(const uint8_t PipeNumber)\r
+ {\r
+ return false; // TODO implement later\r
+ }\r
+\r
+ /** Unfreezes the selected pipe, allowing it to communicate with an attached device. */\r
+ static inline void Pipe_Unfreeze(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Unfreeze(void)\r
+ {\r
+ // TODO implement later\r
+ }\r
+\r
+ /** Freezes the selected pipe, preventing it from communicating with an attached device. */\r
+ static inline void Pipe_Freeze(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Freeze(void)\r
+ {\r
+ // TODO implement later\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the currently selected pipe is frozen, and not able to accept data.\r
+ * @return Boolean \c true if the currently selected pipe is frozen, \c false otherwise.\r
+ */\r
+ static inline bool Pipe_IsFrozen(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_IsFrozen(void)\r
+ {\r
+ return false; // TODO implement later\r
+ }\r
+\r
+ /** Clears the error flags for the currently selected pipe. */\r
+ static inline void Pipe_ClearError(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_ClearError(void)\r
+ {\r
+ // TODO implement later\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the master pipe error flag is set for the currently selected pipe, indicating that\r
+ * some sort of hardware error has occurred on the pipe.\r
+ *\r
+ * \see @ref Pipe_GetErrorFlags() macro for information on retrieving the exact error flag.\r
+ *\r
+ * @return Boolean \c true if an error has occurred on the selected pipe, \c false otherwise.\r
+ */\r
+ static inline bool Pipe_IsError(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_IsError(void)\r
+ {\r
+ return false; // TODO implement later\r
+ }\r
+\r
+ /**\r
+ * @brief Gets a mask of the hardware error flags which have occurred on the currently selected pipe. This\r
+ * value can then be masked against the \c PIPE_ERRORFLAG_* masks to determine what error has occurred.\r
+ *\r
+ * @return Mask comprising of \c PIPE_ERRORFLAG_* bits indicating what error has occurred on the selected pipe.\r
+ */\r
+ static inline uint8_t Pipe_GetErrorFlags(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Pipe_GetErrorFlags(void)\r
+ {\r
+ return 0; // TODO implement later\r
+ }\r
+\r
+ /**\r
+ * @brief Retrieves the number of busy banks in the currently selected pipe, which have been queued for\r
+ * transmission via the @ref Pipe_ClearOUT() command, or are awaiting acknowledgement via the\r
+ * @ref Pipe_ClearIN() command.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ *\r
+ * @return Total number of busy banks in the selected pipe.\r
+ */\r
+ static inline uint8_t Pipe_GetBusyBanks(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Pipe_GetBusyBanks(void)\r
+ {\r
+ return 0; // TODO implement later\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if a packet has been received on the currently selected IN pipe from the attached device.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Boolean \c true if the current pipe has received an IN packet, \c false otherwise.\r
+ */\r
+ // static inline bool Pipe_IsINReceived(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+ bool Pipe_IsINReceived(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT;\r
+\r
+ /**\r
+ * @brief Determines if the currently selected OUT pipe is ready to send an OUT packet to the attached device.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Boolean \c true if the current pipe is ready for an OUT packet, \c false otherwise.\r
+ */\r
+ static inline bool Pipe_IsOUTReady(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_IsOUTReady(const uint8_t corenum)\r
+ {\r
+ return (HcdGetPipeStatus(PipeInfo[corenum][pipeselected[corenum]].PipeHandle) == HCD_STATUS_OK)\r
+ && (PipeInfo[corenum][pipeselected[corenum]].ByteTransfered <\r
+ PipeInfo[corenum][pipeselected[corenum]].BufferSize);\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the currently selected pipe may be read from (if data is waiting in the pipe\r
+ * bank and the pipe is an IN direction, or if the bank is not yet full if the pipe is an OUT\r
+ * direction). This function will return false if an error has occurred in the pipe, or if the pipe\r
+ * is an IN direction and no packet (or an empty packet) has been received, or if the pipe is an OUT\r
+ * direction and the pipe bank is full.\r
+ *\r
+ * @note This function is not valid on CONTROL type pipes.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Boolean \c true if the currently selected pipe may be read from or written to, depending\r
+ * on its direction.\r
+ */\r
+ static inline bool Pipe_IsReadWriteAllowed(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_IsReadWriteAllowed(const uint8_t corenum)\r
+ {\r
+ if (Pipe_GetPipeToken(corenum) == PIPE_TOKEN_IN) {\r
+ return (HCD_STATUS_OK == HcdGetPipeStatus(PipeInfo[corenum][pipeselected[corenum]].PipeHandle)) &&\r
+ Pipe_BytesInPipe(corenum);\r
+ }\r
+ else {\r
+ return Pipe_IsOUTReady(corenum);\r
+ }\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if pipe's status is OK\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ *\r
+ * @return Boolean \c true if the current pipe's status is OK , \c false otherwise.\r
+ */\r
+ static inline bool Pipe_IsStatusOK(uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+ static inline bool Pipe_IsStatusOK(uint8_t corenum)\r
+ {\r
+ return (HCD_STATUS_OK == HcdGetPipeStatus(PipeInfo[corenum][pipeselected[corenum]].PipeHandle));\r
+ }\r
+ \r
+ /**\r
+ * @brief Determines if no SETUP request is currently being sent to the attached device on the selected\r
+ * CONTROL type pipe.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ *\r
+ * @return Boolean \c true if the current pipe is ready for a SETUP packet, \c false otherwise.\r
+ */\r
+ static inline bool Pipe_IsSETUPSent(void) ATTR_DEPRECATED ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_IsSETUPSent(void)\r
+ {\r
+ return true;\r
+ }\r
+\r
+ /** Sends the currently selected CONTROL type pipe's contents to the device as a SETUP packet.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ */\r
+ static inline void Pipe_ClearSETUP(void) ATTR_DEPRECATED ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_ClearSETUP(void)\r
+ {}\r
+\r
+ /** Acknowledges the reception of a setup IN request from the attached device on the currently selected\r
+ * pipe, freeing the bank ready for the next packet.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ * @param corenum : USB port number\r
+ */\r
+ static inline void Pipe_ClearIN(const uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_ClearIN(const uint8_t corenum)\r
+ {\r
+ PipeInfo[corenum][pipeselected[corenum]].StartIdx = PipeInfo[corenum][pipeselected[corenum]].ByteTransfered = 0;\r
+ }\r
+\r
+ /** Sends the currently selected pipe's contents to the device as an OUT packet on the selected pipe, freeing\r
+ * the bank ready for the next packet.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ * @param corenum : USB port number\r
+ */\r
+ static inline void Pipe_ClearOUT(const uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_ClearOUT(const uint8_t corenum)\r
+ {\r
+ HcdDataTransfer(PipeInfo[corenum][pipeselected[corenum]].PipeHandle,\r
+ PipeInfo[corenum][pipeselected[corenum]].Buffer,\r
+ PipeInfo[corenum][pipeselected[corenum]].ByteTransfered,\r
+ NULL /* FIXME &PipeInfo[pipeselected].ByteTransfered*/);\r
+ PipeInfo[corenum][pipeselected[corenum]].StartIdx = PipeInfo[corenum][pipeselected[corenum]].ByteTransfered = 0;\r
+ }\r
+\r
+ /**\r
+ * @brief Determines if the device sent a NAK (Negative Acknowledge) in response to the last sent packet on\r
+ * the currently selected pipe. This occurs when the host sends a packet to the device, but the device\r
+ * is not currently ready to handle the packet (i.e. its endpoint banks are full). Once a NAK has been\r
+ * received, it must be cleared using @ref Pipe_ClearNAKReceived() before the previous (or any other) packet\r
+ * can be re-sent.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ *\r
+ * @return Boolean \c true if an NAK has been received on the current pipe, \c false otherwise.\r
+ */\r
+ static inline bool Pipe_IsNAKReceived(void) ATTR_DEPRECATED ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_IsNAKReceived(void)\r
+ {\r
+ return false;\r
+ }\r
+\r
+ /** Clears the NAK condition on the currently selected pipe.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ *\r
+ * \see @ref Pipe_IsNAKReceived() for more details.\r
+ */\r
+ static inline void Pipe_ClearNAKReceived(void) ATTR_DEPRECATED ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_ClearNAKReceived(void)\r
+ {}\r
+\r
+ /**\r
+ * @brief Determines if the currently selected pipe has had the STALL condition set by the attached device.\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Boolean \c true if the current pipe has been stalled by the attached device, \c false otherwise.\r
+ */\r
+ static inline bool Pipe_IsStalled(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool Pipe_IsStalled(const uint8_t corenum)\r
+ {\r
+ return HcdGetPipeStatus(PipeInfo[corenum][pipeselected[corenum]].PipeHandle) == HCD_STATUS_TRANSFER_Stall;\r
+ }\r
+\r
+ /** Clears the STALL condition detection flag on the currently selected pipe, but does not clear the\r
+ * STALL condition itself (this must be done via a ClearFeature control request to the device).\r
+ *\r
+ * @ingroup Group_PipePacketManagement\r
+ * @param corenum : USB port number\r
+ */\r
+ static inline void Pipe_ClearStall(const uint8_t corenum) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_ClearStall(const uint8_t corenum)\r
+ {\r
+ HcdClearEndpointHalt(PipeInfo[corenum][pipeselected[corenum]].PipeHandle);\r
+ }\r
+\r
+ /**\r
+ * @brief Reads one byte from the currently selected pipe's bank, for OUT direction pipes\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Next byte in the currently selected pipe's FIFO buffer\r
+ */\r
+ static inline uint8_t Pipe_Read_8(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Pipe_Read_8(const uint8_t corenum)\r
+ {\r
+ if (PipeInfo[corenum][pipeselected[corenum]].StartIdx < PipeInfo[corenum][pipeselected[corenum]].ByteTransfered ) {\r
+ uint8_t temp =\r
+ PipeInfo[corenum][pipeselected[corenum]].Buffer[PipeInfo[corenum][pipeselected[corenum]].StartIdx];\r
+ PipeInfo[corenum][pipeselected[corenum]].StartIdx++;\r
+ return temp;\r
+ }\r
+ else {\r
+ return 0;\r
+ }\r
+ }\r
+\r
+ /**\r
+ * @brief Writes one byte to the currently selected pipe's bank, for IN direction pipes\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Data : Data to write into the the currently selected pipe's FIFO buffer\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_Write_8(const uint8_t corenum, const uint8_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Write_8(const uint8_t corenum, const uint8_t Data)\r
+ {\r
+ if (PipeInfo[corenum][pipeselected[corenum]].ByteTransfered <\r
+ PipeInfo[corenum][pipeselected[corenum]].BufferSize) {\r
+ PipeInfo[corenum][pipeselected[corenum]].Buffer[PipeInfo[corenum][pipeselected[corenum]].ByteTransfered] = Data;\r
+ PipeInfo[corenum][pipeselected[corenum]].ByteTransfered++;\r
+ }\r
+ }\r
+\r
+ /** Discards one byte from the currently selected pipe's bank, for OUT direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ */\r
+ static inline void Pipe_Discard_8(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Discard_8(void)\r
+ {}\r
+\r
+ /**\r
+ * @brief Reads two bytes from the currently selected pipe's bank in little endian format, for OUT\r
+ * direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Next two bytes in the currently selected pipe's FIFO buffer.\r
+ */\r
+ static inline uint16_t Pipe_Read_16_LE(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint16_t Pipe_Read_16_LE(const uint8_t corenum)\r
+ {\r
+ uint16_t tem = 0;\r
+ uint8_t tem1, tem2;\r
+\r
+ tem1 = Pipe_Read_8(corenum);\r
+ tem2 = Pipe_Read_8(corenum);\r
+ tem = (tem2 << 8) | tem1;\r
+ return tem;\r
+ }\r
+\r
+ /**\r
+ * @brief Reads two bytes from the currently selected pipe's bank in big endian format, for OUT\r
+ * direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Next two bytes in the currently selected pipe's FIFO buffer.\r
+ */\r
+ static inline uint16_t Pipe_Read_16_BE(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint16_t Pipe_Read_16_BE(const uint8_t corenum)\r
+ {\r
+ uint16_t tem = 0;\r
+ uint8_t tem1, tem2;\r
+\r
+ tem1 = Pipe_Read_8(corenum);\r
+ tem2 = Pipe_Read_8(corenum);\r
+ tem = (tem1 << 8) | tem2;\r
+ return tem;\r
+ }\r
+\r
+ /**\r
+ * @brief Writes two bytes to the currently selected pipe's bank in little endian format, for IN\r
+ * direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Data : Data to write to the currently selected pipe's FIFO buffer\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_Write_16_LE(const uint8_t corenum, const uint16_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Write_16_LE(const uint8_t corenum, const uint16_t Data)\r
+ {\r
+ Pipe_Write_8(corenum, Data & 0xFF);\r
+ Pipe_Write_8(corenum, (Data >> 8) & 0xFF);\r
+ }\r
+\r
+ /**\r
+ * @brief Writes two bytes to the currently selected pipe's bank in big endian format, for IN\r
+ * direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Data : Data to write to the currently selected pipe's FIFO buffer.\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_Write_16_BE(const uint8_t corenum, const uint16_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Write_16_BE(const uint8_t corenum, const uint16_t Data)\r
+ {\r
+ Pipe_Write_8(corenum, (Data >> 8) & 0xFF);\r
+ Pipe_Write_8(corenum, Data & 0xFF);\r
+ }\r
+\r
+ /** Discards two bytes from the currently selected pipe's bank, for OUT direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ */\r
+ static inline void Pipe_Discard_16(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Discard_16(void)\r
+ {}\r
+\r
+ /**\r
+ * @brief Reads four bytes from the currently selected pipe's bank in little endian format, for OUT\r
+ * direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Next four bytes in the currently selected pipe's FIFO buffer.\r
+ */\r
+ static inline uint32_t Pipe_Read_32_LE(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint32_t Pipe_Read_32_LE(const uint8_t corenum)\r
+ {\r
+ uint32_t tem = 0;\r
+ uint8_t tem1, tem2, tem3, tem4;\r
+\r
+ tem1 = Pipe_Read_8(corenum);\r
+ tem2 = Pipe_Read_8(corenum);\r
+ tem3 = Pipe_Read_8(corenum);\r
+ tem4 = Pipe_Read_8(corenum);\r
+ tem = (tem4 << 24) | (tem3 << 16) | (tem2 << 8) | tem1;\r
+ return tem;\r
+ }\r
+\r
+ /**\r
+ * @brief Reads four bytes from the currently selected pipe's bank in big endian format, for OUT\r
+ * direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @return Next four bytes in the currently selected pipe's FIFO buffer.\r
+ */\r
+ static inline uint32_t Pipe_Read_32_BE(const uint8_t corenum) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint32_t Pipe_Read_32_BE(const uint8_t corenum)\r
+ {\r
+ uint32_t tem = 0;\r
+ uint8_t tem1, tem2, tem3, tem4;\r
+\r
+ tem1 = Pipe_Read_8(corenum);\r
+ tem2 = Pipe_Read_8(corenum);\r
+ tem3 = Pipe_Read_8(corenum);\r
+ tem4 = Pipe_Read_8(corenum);\r
+ tem = (tem1 << 24) | (tem2 << 16) | (tem3 << 8) | tem4;\r
+ return tem;\r
+ }\r
+\r
+ /**\r
+ * @brief Writes four bytes to the currently selected pipe's bank in little endian format, for IN\r
+ * direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Data : Data to write to the currently selected pipe's FIFO buffer.\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_Write_32_LE(const uint8_t corenum, const uint32_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Write_32_LE(const uint8_t corenum, const uint32_t Data)\r
+ {\r
+ Pipe_Write_8(corenum, Data & 0xFF);\r
+ Pipe_Write_8(corenum, (Data >> 8) & 0xFF);\r
+ Pipe_Write_8(corenum, (Data >> 16) & 0xFF);\r
+ Pipe_Write_8(corenum, (Data >> 24) & 0xFF);\r
+ }\r
+\r
+ /**\r
+ * @brief Writes four bytes to the currently selected pipe's bank in big endian format, for IN\r
+ * direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Data : Data to write to the currently selected pipe's FIFO buffer\r
+ * @return Nothing\r
+ */\r
+ static inline void Pipe_Write_32_BE(const uint8_t corenum, const uint32_t Data) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Write_32_BE(const uint8_t corenum, const uint32_t Data)\r
+ {\r
+ Pipe_Write_8(corenum, (Data >> 24) & 0xFF);\r
+ Pipe_Write_8(corenum, (Data >> 16) & 0xFF);\r
+ Pipe_Write_8(corenum, (Data >> 8) & 0xFF);\r
+ Pipe_Write_8(corenum, Data & 0xFF);\r
+ }\r
+\r
+ /** Discards four bytes from the currently selected pipe's bank, for OUT direction pipes.\r
+ *\r
+ * @ingroup Group_PipePrimitiveRW\r
+ */\r
+ static inline void Pipe_Discard_32(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void Pipe_Discard_32(void)\r
+ {}\r
+\r
+ /* External Variables: */\r
+ /** Global indicating the maximum packet size of the default control pipe located at address\r
+ * 0 in the device. This value is set to the value indicated in the attached device's device\r
+ * descriptor once the USB interface is initialized into host mode and a device is attached\r
+ * to the USB bus.\r
+ *\r
+ * @note This variable should be treated as read-only in the user application, and never manually\r
+ * changed in value.\r
+ */\r
+\r
+ /* Function Prototypes: */\r
+ /**\r
+ * @brief Configures the specified pipe number with the given pipe type, token, target endpoint number in the\r
+ * attached device, bank size and banking mode.\r
+ *\r
+ * A newly configured pipe is frozen by default, and must be unfrozen before use via the @ref Pipe_Unfreeze()\r
+ * before being used. Pipes should be kept frozen unless waiting for data from a device while in IN mode, or\r
+ * sending data to the device in OUT mode. IN type pipes are also automatically configured to accept infinite\r
+ * numbers of IN requests without automatic freezing - this can be overridden by a call to\r
+ * @ref Pipe_SetFiniteINRequests().\r
+ * @param corenum : USB port number\r
+ * @param Number : Pipe number to configure. This must be more than 0 and less than @ref PIPE_TOTAL_PIPES.\r
+ * @param Type : Type of pipe to configure, an \c EP_TYPE_* mask. Not all pipe types are available on Low\r
+ * Speed USB devices - refer to the USB 2.0 specification.\r
+ * @param Token : Pipe data token, either @ref PIPE_TOKEN_SETUP, @ref PIPE_TOKEN_OUT or @ref PIPE_TOKEN_IN.\r
+ * All pipes (except Control type) are unidirectional - data may only be read from or\r
+ * written to the pipe bank based on its direction, not both.\r
+ * @param EndpointNumber : Endpoint index within the attached device that the pipe should interface to.\r
+ * @param Size : Size of the pipe's bank, where packets are stored before they are transmitted to\r
+ * the USB device, or after they have been received from the USB device (depending on\r
+ * the pipe's data direction). The bank size must indicate the maximum packet size that\r
+ * the pipe can handle.\r
+ * @param Banks : Number of banks to use for the pipe being configured, a \c PIPE_BANK_* mask. More banks\r
+ * uses more USB DPRAM, but offers better performance. Isochronous type pipes <b>must</b>\r
+ * have at least two banks.\r
+ * @note When the \c ORDERED_EP_CONFIG compile time option is used, Pipes <b>must</b> be configured in ascending order,\r
+ * or bank corruption will occur.\r
+ * \n\n\r
+ *\r
+ * @note Certain microcontroller model's pipes may have different maximum packet sizes based on the pipe's\r
+ * index - refer to the chosen microcontroller's datasheet to determine the maximum bank size for each pipe.\r
+ * \n\n\r
+ *\r
+ * @note The default control pipe should not be manually configured by the user application, as it is\r
+ * automatically configured by the library internally.\r
+ * \n\n\r
+ *\r
+ * @note This routine will automatically select the specified pipe upon success. Upon failure, the pipe which\r
+ * failed to reconfigure correctly will be selected.\r
+ *\r
+ * @return Boolean \c true if the configuration succeeded, \c false otherwise.\r
+ */\r
+ bool Pipe_ConfigurePipe(const uint8_t corenum,\r
+ const uint8_t Number,\r
+ const uint8_t Type,\r
+ const uint8_t Token,\r
+ const uint8_t EndpointNumber,\r
+ const uint16_t Size,\r
+ const uint8_t Banks);\r
+\r
+ void Pipe_ClosePipe(const uint8_t corenum, uint8_t pipenum);\r
+\r
+ /**\r
+ * @brief Spin-loops until the currently selected non-control pipe is ready for the next packed of data to be read\r
+ * or written to it, aborting in the case of an error condition (such as a timeout or device disconnect).\r
+ *\r
+ * @ingroup Group_PipeRW\r
+ *\r
+ * @return A value from the @ref Pipe_WaitUntilReady_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_WaitUntilReady(const uint8_t corenum);\r
+\r
+ /**\r
+ * @brief Determines if a pipe has been bound to the given device endpoint address. If a pipe which is bound to the given\r
+ * endpoint is found, it is automatically selected.\r
+ *\r
+ * @param EndpointAddress : EndpointAddress Address and direction mask of the endpoint within the attached device to check\r
+ * @return Boolean \c true if a pipe bound to the given endpoint address of the specified direction is found,\r
+ * \c false otherwise.\r
+ */\r
+ bool Pipe_IsEndpointBound(const uint8_t EndpointAddress) ATTR_WARN_UNUSED_RESULT;\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Macros: */\r
+ #if !defined(ENDPOINT_CONTROLEP)\r
+ #define ENDPOINT_CONTROLEP 0\r
+ #endif\r
+\r
+ /* Inline Functions: */\r
+ static inline uint8_t Pipe_BytesToEPSizeMask(const uint16_t Bytes) ATTR_WARN_UNUSED_RESULT ATTR_CONST\r
+ ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t Pipe_BytesToEPSizeMask(const uint16_t Bytes)\r
+ {\r
+ return 0; // implement later\r
+ }\r
+\r
+ /* Function Prototypes: */\r
+ void Pipe_ClearPipes(void);\r
+\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Pipe data stream transmission and reception management for the LPC microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBMode.h"\r
+\r
+#if defined(USB_CAN_BE_HOST)\r
+\r
+#include "PipeStream.h"\r
+\r
+uint8_t Pipe_Discard_Stream(const uint8_t corenum,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ uint8_t ErrorCode;\r
+ uint16_t BytesInTransfer = 0;\r
+\r
+ // Pipe_SetPipeToken(PIPE_TOKEN_IN);\r
+ ErrorCode = Pipe_WaitUntilReady(corenum);\r
+ if (ErrorCode) {\r
+ return ErrorCode;\r
+ }\r
+\r
+ if (BytesProcessed != NULL) {\r
+ Length -= *BytesProcessed;\r
+ }\r
+\r
+ while (Length) {\r
+ if (!(Pipe_IsReadWriteAllowed(corenum))) {\r
+ Pipe_ClearIN(corenum);\r
+\r
+ if (BytesProcessed != NULL) {\r
+ *BytesProcessed += BytesInTransfer;\r
+ return PIPE_RWSTREAM_IncompleteTransfer;\r
+ }\r
+ ErrorCode = Pipe_WaitUntilReady(corenum);\r
+ if (ErrorCode) {\r
+ return ErrorCode;\r
+ }\r
+ }\r
+ else {\r
+ Pipe_Discard_8();\r
+\r
+ Length--;\r
+ BytesInTransfer++;\r
+ }\r
+ }\r
+\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Null_Stream(const uint8_t corenum,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ if (BytesProcessed != NULL) {\r
+ Length -= *BytesProcessed;\r
+ }\r
+\r
+ while (Length) {\r
+ Pipe_Write_8(corenum, 0);\r
+ Length--;\r
+ }\r
+\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Write_Stream_LE(const uint8_t corenum,\r
+ const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ uint8_t *DataStream = (uint8_t *) Buffer;\r
+ if (BytesProcessed != NULL) {\r
+ Length -= *BytesProcessed;\r
+ DataStream += *BytesProcessed;\r
+ }\r
+\r
+ while (Length) {\r
+ Pipe_Write_8(corenum, *DataStream);\r
+ DataStream++;\r
+ Length--;\r
+ }\r
+\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Read_Stream_LE(const uint8_t corenum,\r
+ void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) /* TODO Blocking due to Pipe_WaitUntilReady */\r
+{\r
+ uint8_t *DataStream = (uint8_t *) Buffer;\r
+ uint8_t ErrorCode;\r
+\r
+ ErrorCode = Pipe_WaitUntilReady(corenum);\r
+ if (ErrorCode) {\r
+ return ErrorCode;\r
+ }\r
+\r
+ if (BytesProcessed != NULL) {\r
+ Length -= *BytesProcessed;\r
+ DataStream += *BytesProcessed;\r
+ }\r
+\r
+ while (Length) {\r
+ if (Pipe_IsReadWriteAllowed(corenum)) {\r
+ *DataStream = Pipe_Read_8(corenum);\r
+ DataStream++;\r
+ Length--;\r
+ }\r
+ else {\r
+ Pipe_ClearIN(corenum);\r
+ HcdDataTransfer(PipeInfo[corenum][pipeselected[corenum]].PipeHandle,\r
+ PipeInfo[corenum][pipeselected[corenum]].Buffer,\r
+ MIN(Length, PipeInfo[corenum][pipeselected[corenum]].BufferSize),\r
+ &PipeInfo[corenum][pipeselected[corenum]].ByteTransfered);\r
+ ErrorCode = Pipe_WaitUntilReady(corenum);\r
+ if (ErrorCode) {\r
+ return ErrorCode;\r
+ }\r
+ }\r
+ }\r
+\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Write_Stream_BE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Read_Stream_BE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Write_PStream_LE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Write_PStream_BE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Write_EStream_LE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Write_EStream_BE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Read_EStream_LE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Read_EStream_BE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed)\r
+{\r
+ return PIPE_RWSTREAM_NoError;\r
+}\r
+\r
+uint8_t Pipe_Streaming(uint8_t corenum, uint8_t* const buffer, uint32_t const transferlength, uint16_t const packetsize)\r
+{\r
+ uint32_t pipehdl = PipeInfo[corenum][pipeselected[corenum]].PipeHandle;\r
+ if (HCD_STATUS_OK == HcdGetPipeStatus(pipehdl))\r
+ {\r
+ HcdSetStreamPacketSize(pipehdl,packetsize);\r
+ HcdDataTransfer(pipehdl,buffer,transferlength,&PipeInfo[corenum][pipeselected[corenum]].ByteTransfered);\r
+ return PIPE_RWSTREAM_NoError;\r
+ }\r
+ else return PIPE_RWSTREAM_IncompleteTransfer;\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief Pipe data stream transmission and reception management\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_PipeRW \r
+ * @defgroup Group_PipeStreamRW Read/Write of Multi-Byte Streams\r
+ * @brief Pipe data stream transmission and reception management.\r
+ *\r
+ * Functions, macros, variables, enums and types related to data reading and writing of data streams from\r
+ * and to pipes.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __PIPE_STREAM_H__\r
+#define __PIPE_STREAM_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h"\r
+ \r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+ \r
+ /* Public Interface - May be used in end-application: */\r
+ /* Enums: */\r
+ /** Enum for the possible error return codes of the Pipe_*_Stream_* functions. */\r
+ enum Pipe_Stream_RW_ErrorCodes_t\r
+ {\r
+ PIPE_RWSTREAM_NoError = 0, /**< Command completed successfully, no error. */\r
+ PIPE_RWSTREAM_PipeStalled = 1, /**< The device stalled the pipe during the transfer. */ \r
+ PIPE_RWSTREAM_DeviceDisconnected = 2, /**< Device was disconnected from the host during\r
+ * the transfer.\r
+ */ \r
+ PIPE_RWSTREAM_Timeout = 3, /**< The device failed to accept or send the next packet\r
+ * within the software timeout period set by the\r
+ * @ref USB_STREAM_TIMEOUT_MS macro.\r
+ */\r
+ PIPE_RWSTREAM_IncompleteTransfer = 4, /**< Indicates that the pipe bank became full/empty before the\r
+ * complete contents of the stream could be transferred.\r
+ */\r
+ };\r
+\r
+ #include "USBTask.h"\r
+ /* Function Prototypes: */\r
+ /** \name Stream functions for null data */\r
+ //@{\r
+ /**\r
+ * @brief Reads and discards the given number of bytes from the pipe, discarding fully read packets from the host\r
+ * as needed. The last packet is not automatically discarded once the remaining bytes has been read; the\r
+ * user is responsible for manually discarding the last packet from the device via the @ref Pipe_ClearIN() macro.\r
+ *\r
+ * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once, failing or\r
+ * succeeding as a single unit. If the BytesProcessed parameter points to a valid storage location, the transfer\r
+ * will instead be performed as a series of chunks. Each time the pipe bank becomes empty while there is still data\r
+ * to process (and after the current packet has been acknowledged) the BytesProcessed location will be updated with\r
+ * the total number of bytes processed in the stream, and the function will exit with an error code of\r
+ * @ref PIPE_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed in the user code - to\r
+ * continue the transfer, call the function again with identical parameters and it will resume until the BytesProcessed\r
+ * value reaches the total transfer length.\r
+ *\r
+ * <b>Single Stream Transfer Example:</b>\r
+ * \code\r
+ * uint8_t ErrorCode;\r
+ *\r
+ * if ((ErrorCode = Pipe_Discard_Stream(512, NULL)) != PIPE_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * <b>Partial Stream Transfers Example:</b>\r
+ * \code\r
+ * uint8_t ErrorCode;\r
+ * uint16_t BytesProcessed;\r
+ *\r
+ * BytesProcessed = 0;\r
+ * while ((ErrorCode = Pipe_Discard_Stream(512, &BytesProcessed)) == PIPE_RWSTREAM_IncompleteTransfer)\r
+ * {\r
+ * // Stream not yet complete - do other actions here, abort if required\r
+ * }\r
+ *\r
+ * if (ErrorCode != PIPE_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * @note The pipe token is set automatically, thus this can be used on bi-directional pipes directly without\r
+ * having to explicitly change the data direction with a call to @ref Pipe_SetPipeToken().\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Length : Number of bytes to discard via the currently selected pipe\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be processed at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+\r
+ */\r
+ uint8_t Pipe_Discard_Stream(const uint8_t corenum,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) /*ATTR_DEPRECATED*/;\r
+\r
+ /**\r
+ * @brief Writes a given number of zeroed bytes to the pipe, sending full pipe packets from the host to the device\r
+ * as needed. The last packet is not automatically sent once the remaining bytes has been written; the\r
+ * user is responsible for manually discarding the last packet from the device via the @ref Pipe_ClearOUT() macro.\r
+ *\r
+ * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once, failing or\r
+ * succeeding as a single unit. If the BytesProcessed parameter points to a valid storage location, the transfer\r
+ * will instead be performed as a series of chunks. Each time the pipe bank becomes full while there is still data\r
+ * to process (and after the current packet transmission has been initiated) the BytesProcessed location will be\r
+ * updated with the total number of bytes processed in the stream, and the function will exit with an error code of\r
+ * @ref PIPE_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed in the user code - to\r
+ * continue the transfer, call the function again with identical parameters and it will resume until the BytesProcessed\r
+ * value reaches the total transfer length.\r
+ *\r
+ * <b>Single Stream Transfer Example:</b>\r
+ * \code\r
+ * uint8_t ErrorCode;\r
+ *\r
+ * if ((ErrorCode = Pipe_Null_Stream(512, NULL)) != PIPE_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * <b>Partial Stream Transfers Example:</b>\r
+ * \code\r
+ * uint8_t ErrorCode;\r
+ * uint16_t BytesProcessed;\r
+ *\r
+ * BytesProcessed = 0;\r
+ * while ((ErrorCode = Pipe_Null_Stream(512, &BytesProcessed)) == PIPE_RWSTREAM_IncompleteTransfer)\r
+ * {\r
+ * // Stream not yet complete - do other actions here, abort if required\r
+ * }\r
+ *\r
+ * if (ErrorCode != PIPE_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * @note The pipe token is set automatically, thus this can be used on bi-directional pipes directly without\r
+ * having to explicitly change the data direction with a call to @ref Pipe_SetPipeToken().\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Length : Number of zero bytes to write via the currently selected pipe\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be processed at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Null_Stream(const uint8_t corenum,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed);\r
+\r
+ //@}\r
+\r
+ /** \name Stream functions for RAM source/destination data */\r
+ //@{\r
+ /**\r
+ * @brief Writes the given number of bytes to the pipe from the given buffer in little endian,\r
+ * sending full packets to the device as needed. The last packet filled is not automatically sent;\r
+ * the user is responsible for manually sending the last written packet to the host via the\r
+ * @ref Pipe_ClearOUT() macro. Between each USB packet, the given stream callback function is\r
+ * executed repeatedly until the next packet is ready, allowing for early aborts of stream transfers.\r
+ *\r
+ * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once,\r
+ * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid\r
+ * storage location, the transfer will instead be performed as a series of chunks. Each time\r
+ * the pipe bank becomes full while there is still data to process (and after the current\r
+ * packet transmission has been initiated) the BytesProcessed location will be updated with the\r
+ * total number of bytes processed in the stream, and the function will exit with an error code of\r
+ * @ref PIPE_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed\r
+ * in the user code - to continue the transfer, call the function again with identical parameters\r
+ * and it will resume until the BytesProcessed value reaches the total transfer length.\r
+ *\r
+ * <b>Single Stream Transfer Example:</b>\r
+ * \code\r
+ * uint8_t DataStream[512];\r
+ * uint8_t ErrorCode;\r
+ *\r
+ * if ((ErrorCode = Pipe_Write_Stream_LE(DataStream, sizeof(DataStream),\r
+ * NULL)) != PIPE_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * <b>Partial Stream Transfers Example:</b>\r
+ * \code\r
+ * uint8_t DataStream[512];\r
+ * uint8_t ErrorCode;\r
+ * uint16_t BytesProcessed;\r
+ *\r
+ * BytesProcessed = 0;\r
+ * while ((ErrorCode = Pipe_Write_Stream_LE(DataStream, sizeof(DataStream),\r
+ * &BytesProcessed)) == PIPE_RWSTREAM_IncompleteTransfer)\r
+ * {\r
+ * // Stream not yet complete - do other actions here, abort if required\r
+ * }\r
+ *\r
+ * if (ErrorCode != PIPE_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * @note The pipe token is set automatically, thus this can be used on bi-directional pipes directly without\r
+ * having to explicitly change the data direction with a call to @ref Pipe_SetPipeToken().\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected pipe into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be written at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Write_Stream_LE(const uint8_t corenum,\r
+ const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed);\r
+\r
+ /**\r
+ * @brief Writes the given number of bytes to the pipe from the given buffer in big endian,\r
+ * sending full packets to the device as needed. The last packet filled is not automatically sent;\r
+ * the user is responsible for manually sending the last written packet to the host via the\r
+ * @ref Pipe_ClearOUT() macro. Between each USB packet, the given stream callback function is\r
+ * executed repeatedly until the next packet is ready, allowing for early aborts of stream transfers.\r
+ *\r
+ * @note The pipe token is set automatically, thus this can be used on bi-directional pipes directly without\r
+ * having to explicitly change the data direction with a call to @ref Pipe_SetPipeToken().\r
+ *\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected pipe into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be written at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Write_Stream_BE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1) ATTR_ERROR(\r
+ "Function is not implemented yet");\r
+\r
+ /**\r
+ * @brief Reads the given number of bytes from the pipe into the given buffer in little endian,\r
+ * sending full packets to the device as needed. The last packet filled is not automatically sent;\r
+ * the user is responsible for manually sending the last written packet to the host via the\r
+ * @ref Pipe_ClearIN() macro. Between each USB packet, the given stream callback function is\r
+ * executed repeatedly until the next packet is ready, allowing for early aborts of stream transfers.\r
+ *\r
+ * If the BytesProcessed parameter is \c NULL, the entire stream transfer is attempted at once,\r
+ * failing or succeeding as a single unit. If the BytesProcessed parameter points to a valid\r
+ * storage location, the transfer will instead be performed as a series of chunks. Each time\r
+ * the pipe bank becomes empty while there is still data to process (and after the current\r
+ * packet has been acknowledged) the BytesProcessed location will be updated with the total number\r
+ * of bytes processed in the stream, and the function will exit with an error code of\r
+ * @ref PIPE_RWSTREAM_IncompleteTransfer. This allows for any abort checking to be performed\r
+ * in the user code - to continue the transfer, call the function again with identical parameters\r
+ * and it will resume until the BytesProcessed value reaches the total transfer length.\r
+ *\r
+ * <b>Single Stream Transfer Example:</b>\r
+ * \code\r
+ * uint8_t DataStream[512];\r
+ * uint8_t ErrorCode;\r
+ *\r
+ * if ((ErrorCode = Pipe_Read_Stream_LE(DataStream, sizeof(DataStream),\r
+ * NULL)) != PIPE_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * <b>Partial Stream Transfers Example:</b>\r
+ * \code\r
+ * uint8_t DataStream[512];\r
+ * uint8_t ErrorCode;\r
+ * uint16_t BytesProcessed;\r
+ *\r
+ * BytesProcessed = 0;\r
+ * while ((ErrorCode = Pipe_Read_Stream_LE(DataStream, sizeof(DataStream),\r
+ * &BytesProcessed)) == PIPE_RWSTREAM_IncompleteTransfer)\r
+ * {\r
+ * // Stream not yet complete - do other actions here, abort if required\r
+ * }\r
+ *\r
+ * if (ErrorCode != PIPE_RWSTREAM_NoError)\r
+ * {\r
+ * // Stream failed to complete - check ErrorCode here\r
+ * }\r
+ * \endcode\r
+ *\r
+ * @note The pipe token is set automatically, thus this can be used on bi-directional pipes directly without\r
+ * having to explicitly change the data direction with a call to @ref Pipe_SetPipeToken().\r
+ *\r
+ * @param corenum : USB port number\r
+ * @param Buffer : Pointer to the source data buffer to write to\r
+ * @param Length : Number of bytes to read for the currently selected pipe to read from\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be read at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Read_Stream_LE(const uint8_t corenum,\r
+ void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed);\r
+\r
+ /**\r
+ * @brief Reads the given number of bytes from the pipe into the given buffer in big endian,\r
+ * sending full packets to the device as needed. The last packet filled is not automatically sent;\r
+ * the user is responsible for manually sending the last written packet to the host via the\r
+ * @ref Pipe_ClearIN() macro. Between each USB packet, the given stream callback function is\r
+ * executed repeatedly until the next packet is ready, allowing for early aborts of stream transfers.\r
+ *\r
+ * @note The pipe token is set automatically, thus this can be used on bi-directional pipes directly without\r
+ * having to explicitly change the data direction with a call to @ref Pipe_SetPipeToken().\r
+ *\r
+ * @param Buffer : Pointer to the source data buffer to write to\r
+ * @param Length : Number of bytes to read for the currently selected pipe to read from\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be read at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Read_Stream_BE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1) ATTR_ERROR(\r
+ "Function is not implemented yet");\r
+ //@}\r
+\r
+ /** \name Stream functions for EEPROM source/destination data */\r
+ //@{\r
+ /**\r
+ * @brief Pipe Write EEPROM Stream Little Endian\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected pipe into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be written at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Write_EStream_LE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1) ATTR_ERROR(\r
+ "Function is not implemented yet");\r
+\r
+ /**\r
+ * @brief Pipe Write EEPROM Stream Big Endian\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected pipe into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be written at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Write_EStream_BE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1) ATTR_ERROR(\r
+ "Function is not implemented yet");\r
+\r
+ /**\r
+ * @brief Pipe Read EEPROM Stream Little Endian\r
+ * @param Buffer : Pointer to the source data buffer to write to\r
+ * @param Length : Number of bytes to read for the currently selected pipe to read from\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be read at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Read_EStream_LE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1) ATTR_ERROR(\r
+ "Function is not implemented yet");\r
+\r
+ /**\r
+ * @brief Pipe Read EEPROM Stream Big Endian\r
+ * @param Buffer : Pointer to the source data buffer to write to\r
+ * @param Length : Number of bytes to read for the currently selected pipe to read from\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be read at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Read_EStream_BE(void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1) ATTR_ERROR(\r
+ "Function is not implemented yet");\r
+\r
+ //@}\r
+\r
+ /** \name Stream functions for PROGMEM source/destination data */\r
+ //@{\r
+ /**\r
+ * @brief Pipe Write FLASH Stream Little Endian\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected pipe into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be written at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Write_PStream_LE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1) ATTR_ERROR(\r
+ "Function is not implemented yet");\r
+\r
+ /**\r
+ * @brief Pipe Write FLASH Stream Big Endian\r
+ * @param Buffer : Pointer to the source data buffer to read from\r
+ * @param Length : Number of bytes to read for the currently selected pipe into the buffer\r
+ * @param BytesProcessed : Pointer to a location where the total number of bytes already processed should\r
+ * updated, \c NULL if the entire stream should be written at once.\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Write_PStream_BE(const void *const Buffer,\r
+ uint16_t Length,\r
+ uint16_t *const BytesProcessed) ATTR_NON_NULL_PTR_ARG(1) ATTR_ERROR(\r
+ "Function is not implemented yet");\r
+ \r
+ /**\r
+ * @brief Transfer a stream of data to/from USB bus\r
+ * @param corenum : streaming USB core number\r
+ * @param buffer : Pointer to the data buffer to read from or write to\r
+ * @param transferlength : Number of bytes to transfer\r
+ * @param packetsize : Size in byte of each packet in stream\r
+ * @return A value from the @ref Pipe_Stream_RW_ErrorCodes_t enum\r
+ */\r
+ uint8_t Pipe_Streaming(uint8_t corenum, uint8_t* const buffer, uint32_t const transferlength, uint16_t const packetsize);\r
+ \r
+ //@}\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+ \r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief Common standard USB Descriptor definitions for all architectures\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_StdDescriptors USB Descriptors\r
+ * @brief Standard USB Descriptor definitions.\r
+ *\r
+ * Standard USB device descriptor defines and retrieval routines, for USB devices. This module contains\r
+ * structures and macros for the easy creation of standard USB descriptors in USB device projects.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __USBDESCRIPTORS_H__\r
+#define __USBDESCRIPTORS_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h"\r
+ #include "Events.h"\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+\r
+ /** Utility macro used in the formation of descriptors\r
+ */\r
+ #define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF)\r
+\r
+ /** Indicates that a given descriptor does not exist in the device. This can be used inside descriptors\r
+ * for string descriptor indexes, or may be use as a return value for GetDescriptor when the specified\r
+ * descriptor does not exist.\r
+ */\r
+ #define NO_DESCRIPTOR 0\r
+\r
+ /** Macro to calculate the power value for the configuration descriptor, from a given number of milliamperes.\r
+ *\r
+ * @param mA Maximum number of milliamps the device consumes when the given configuration is selected.\r
+ */\r
+ #define USB_CONFIG_POWER_MA(mA) ((mA) >> 1)\r
+\r
+ /** Macro to calculate the Unicode length of a string with a given number of Unicode characters.\r
+ * Should be used in string descriptor's headers for giving the string descriptor's byte length.\r
+ *\r
+ * @param UnicodeChars Number of Unicode characters in the string text.\r
+ */\r
+ #define USB_STRING_LEN(UnicodeChars) (sizeof(USB_Descriptor_Header_t) + ((UnicodeChars) << 1))\r
+\r
+ /** Macro to encode a given four digit floating point version number (e.g. 01.23) into Binary Coded\r
+ * Decimal format for descriptor fields requiring BCD encoding, such as the USB version number in the\r
+ * standard device descriptor.\r
+ *\r
+ * @note This value is automatically converted into Little Endian, suitable for direct use inside device\r
+ * descriptors on all architectures without endianness conversion macros.\r
+ *\r
+ * @param x Version number to encode as a 16-bit little-endian number, as a floating point number.\r
+ */\r
+ #define VERSION_BCD(x) CPU_TO_LE16((((VERSION_TENS(x) << 4) | VERSION_ONES(x)) << 8) | \\r
+ ((VERSION_TENTHS(x) << 4) | VERSION_HUNDREDTHS(x)))\r
+\r
+ /** String language ID for the English language. Should be used in @ref USB_Descriptor_String_t descriptors\r
+ * to indicate that the English language is supported by the device in its string descriptors.\r
+ */\r
+ #define LANGUAGE_ID_ENG 0x0409\r
+\r
+ /** \name USB Configuration Descriptor Attribute Masks */\r
+ //@{\r
+ /** Can be masked with other configuration descriptor attributes for a @ref USB_Descriptor_Configuration_Header_t\r
+ * descriptor's ConfigAttributes value to indicate that the specified configuration can draw its power\r
+ * from the host's VBUS line.\r
+ */\r
+ #define USB_CONFIG_ATTR_BUSPOWERED 0x80\r
+\r
+ /** Can be masked with other configuration descriptor attributes for a @ref USB_Descriptor_Configuration_Header_t\r
+ * descriptor's ConfigAttributes value to indicate that the specified configuration can draw its power\r
+ * from the device's own power source.\r
+ */\r
+ #define USB_CONFIG_ATTR_SELFPOWERED 0x40\r
+\r
+ /** Can be masked with other configuration descriptor attributes for a @ref USB_Descriptor_Configuration_Header_t\r
+ * descriptor's ConfigAttributes value to indicate that the specified configuration supports the\r
+ * remote wakeup feature of the USB standard, allowing a suspended USB device to wake up the host upon\r
+ * request.\r
+ */\r
+ #define USB_CONFIG_ATTR_REMOTEWAKEUP 0x20\r
+ //@}\r
+ \r
+ /** \name Endpoint Descriptor Attribute Masks */\r
+ //@{\r
+ /** Can be masked with other endpoint descriptor attributes for a @ref USB_Descriptor_Endpoint_t descriptor's\r
+ * Attributes value to indicate that the specified endpoint is not synchronized.\r
+ *\r
+ * @see The USB specification for more details on the possible Endpoint attributes.\r
+ */\r
+ #define ENDPOINT_ATTR_NO_SYNC (0 << 2)\r
+\r
+ /** Can be masked with other endpoint descriptor attributes for a @ref USB_Descriptor_Endpoint_t descriptor's\r
+ * Attributes value to indicate that the specified endpoint is asynchronous.\r
+ *\r
+ * @see The USB specification for more details on the possible Endpoint attributes.\r
+ */\r
+ #define ENDPOINT_ATTR_ASYNC (1 << 2)\r
+\r
+ /** Can be masked with other endpoint descriptor attributes for a @ref USB_Descriptor_Endpoint_t descriptor's\r
+ * Attributes value to indicate that the specified endpoint is adaptive.\r
+ *\r
+ * @see The USB specification for more details on the possible Endpoint attributes.\r
+ */\r
+ #define ENDPOINT_ATTR_ADAPTIVE (2 << 2)\r
+\r
+ /** Can be masked with other endpoint descriptor attributes for a @ref USB_Descriptor_Endpoint_t descriptor's\r
+ * Attributes value to indicate that the specified endpoint is synchronized.\r
+ *\r
+ * @see The USB specification for more details on the possible Endpoint attributes.\r
+ */\r
+ #define ENDPOINT_ATTR_SYNC (3 << 2)\r
+ //@}\r
+ \r
+ /** \name Endpoint Descriptor Usage Masks */\r
+ //@{\r
+ /** Can be masked with other endpoint descriptor attributes for a @ref USB_Descriptor_Endpoint_t descriptor's\r
+ * Attributes value to indicate that the specified endpoint is used for data transfers.\r
+ *\r
+ * @see The USB specification for more details on the possible Endpoint usage attributes.\r
+ */\r
+ #define ENDPOINT_USAGE_DATA (0 << 4)\r
+\r
+ /** Can be masked with other endpoint descriptor attributes for a @ref USB_Descriptor_Endpoint_t descriptor's\r
+ * Attributes value to indicate that the specified endpoint is used for feedback.\r
+ *\r
+ * @see The USB specification for more details on the possible Endpoint usage attributes.\r
+ */\r
+ #define ENDPOINT_USAGE_FEEDBACK (1 << 4)\r
+\r
+ /** Can be masked with other endpoint descriptor attributes for a @ref USB_Descriptor_Endpoint_t descriptor's\r
+ * Attributes value to indicate that the specified endpoint is used for implicit feedback.\r
+ *\r
+ * @see The USB specification for more details on the possible Endpoint usage attributes.\r
+ */\r
+ #define ENDPOINT_USAGE_IMPLICIT_FEEDBACK (2 << 4)\r
+ //@}\r
+ \r
+ /* Enums: */\r
+ /** Enum for the possible standard descriptor types, as given in each descriptor's header. */\r
+ enum USB_DescriptorTypes_t\r
+ {\r
+ DTYPE_Device = 0x01, /**< Indicates that the descriptor is a device descriptor. */\r
+ DTYPE_Configuration = 0x02, /**< Indicates that the descriptor is a configuration descriptor. */\r
+ DTYPE_String = 0x03, /**< Indicates that the descriptor is a string descriptor. */\r
+ DTYPE_Interface = 0x04, /**< Indicates that the descriptor is an interface descriptor. */\r
+ DTYPE_Endpoint = 0x05, /**< Indicates that the descriptor is an endpoint descriptor. */\r
+ DTYPE_DeviceQualifier = 0x06, /**< Indicates that the descriptor is a device qualifier descriptor. */\r
+ DTYPE_Other = 0x07, /**< Indicates that the descriptor is of other type. */\r
+ DTYPE_InterfacePower = 0x08, /**< Indicates that the descriptor is an interface power descriptor. */\r
+ DTYPE_InterfaceAssociation = 0x0B, /**< Indicates that the descriptor is an interface association descriptor. */\r
+ DTYPE_CSInterface = 0x24, /**< Indicates that the descriptor is a class specific interface descriptor. */\r
+ DTYPE_CSEndpoint = 0x25, /**< Indicates that the descriptor is a class specific endpoint descriptor. */\r
+ };\r
+\r
+ /** Enum for possible Class, Subclass and Protocol values of device and interface descriptors. */\r
+ enum USB_Descriptor_ClassSubclassProtocol_t\r
+ {\r
+ USB_CSCP_NoDeviceClass = 0x00, /**< Descriptor Class value indicating that the device does not belong\r
+ * to a particular class at the device level.\r
+ */\r
+ USB_CSCP_NoDeviceSubclass = 0x00, /**< Descriptor Subclass value indicating that the device does not belong\r
+ * to a particular subclass at the device level.\r
+ */\r
+ USB_CSCP_NoDeviceProtocol = 0x00, /**< Descriptor Protocol value indicating that the device does not belong\r
+ * to a particular protocol at the device level.\r
+ */\r
+ USB_CSCP_VendorSpecificClass = 0xFF, /**< Descriptor Class value indicating that the device/interface belongs\r
+ * to a vendor specific class.\r
+ */\r
+ USB_CSCP_VendorSpecificSubclass = 0xFF, /**< Descriptor Subclass value indicating that the device/interface belongs\r
+ * to a vendor specific subclass.\r
+ */\r
+ USB_CSCP_VendorSpecificProtocol = 0xFF, /**< Descriptor Protocol value indicating that the device/interface belongs\r
+ * to a vendor specific protocol.\r
+ */\r
+ USB_CSCP_IADDeviceClass = 0xEF, /**< Descriptor Class value indicating that the device belongs to the\r
+ * Interface Association Descriptor class.\r
+ */\r
+ USB_CSCP_IADDeviceSubclass = 0x02, /**< Descriptor Subclass value indicating that the device belongs to the\r
+ * Interface Association Descriptor subclass.\r
+ */\r
+ USB_CSCP_IADDeviceProtocol = 0x01, /**< Descriptor Protocol value indicating that the device belongs to the\r
+ * Interface Association Descriptor protocol.\r
+ */\r
+ };\r
+\r
+ /* Type Defines: */\r
+ /** @brief Standard USB Descriptor Header (LPCUSBlib naming conventions).\r
+ *\r
+ * Type define for all descriptors' standard header, indicating the descriptor's length and type. This structure\r
+ * uses LPCUSBlib-specific element names to make each element's purpose clearer.\r
+ *\r
+ * @see @ref USB_StdDescriptor_Header_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t Size; /**< Size of the descriptor, in bytes. */\r
+ uint8_t Type; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ } ATTR_PACKED USB_Descriptor_Header_t;\r
+\r
+ /** @brief Standard USB Descriptor Header (USB-IF naming conventions).\r
+ *\r
+ * Type define for all descriptors' standard header, indicating the descriptor's length and type. This structure\r
+ * uses the relevant standard's given element names to ensure compatibility with the standard.\r
+ *\r
+ * @see @ref USB_Descriptor_Header_t for the version of this type with non-standard LPCUSBlib specific element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ } ATTR_PACKED USB_StdDescriptor_Header_t;\r
+\r
+ /** @brief Standard USB Device Descriptor (LPCUSBlib naming conventions).\r
+ *\r
+ * Type define for a standard Device Descriptor. This structure uses LPCUSBlib-specific element names to make each\r
+ * element's purpose clearer.\r
+ *\r
+ * @see @ref USB_StdDescriptor_Device_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */\r
+\r
+ uint16_t USBSpecification; /**< BCD of the supported USB specification. */\r
+ uint8_t Class; /**< USB device class. */\r
+ uint8_t SubClass; /**< USB device subclass. */\r
+ uint8_t Protocol; /**< USB device protocol. */\r
+\r
+ uint8_t Endpoint0Size; /**< Size of the control (address 0) endpoint's bank in bytes. */\r
+\r
+ uint16_t VendorID; /**< Vendor ID for the USB product. */\r
+ uint16_t ProductID; /**< Unique product ID for the USB product. */\r
+ uint16_t ReleaseNumber; /**< Product release (version) number. */\r
+\r
+ uint8_t ManufacturerStrIndex; /**< String index for the manufacturer's name. The\r
+ * host will request this string via a separate\r
+ * control request for the string descriptor.\r
+ *\r
+ * @note If no string supplied, use @ref NO_DESCRIPTOR.\r
+ */\r
+ uint8_t ProductStrIndex; /**< String index for the product name/details.\r
+ *\r
+ * @see ManufacturerStrIndex structure entry.\r
+ */\r
+ uint8_t SerialNumStrIndex; /**< String index for the product's globally unique hexadecimal\r
+ * serial number, in uppercase Unicode ASCII.\r
+ *\r
+ * @note On some microcontroller models, there is an embedded serial number\r
+ * in the chip which can be used for the device serial number.\r
+ * To use this serial number, set this to USE_INTERNAL_SERIAL.\r
+ * On unsupported devices, this will evaluate to 0 and will cause\r
+ * the host to generate a pseudo-unique value for the device upon\r
+ * insertion.\r
+ *\r
+ * @see ManufacturerStrIndex structure entry.\r
+ */\r
+ uint8_t NumberOfConfigurations; /**< Total number of configurations supported by\r
+ * the device.\r
+ */\r
+ } ATTR_PACKED USB_Descriptor_Device_t;\r
+\r
+ /** @brief Standard USB Device Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a standard Device Descriptor. This structure uses the relevant standard's given element names\r
+ * to ensure compatibility with the standard.\r
+ *\r
+ * @see @ref USB_Descriptor_Device_t for the version of this type with non-standard LPCUSBlib specific element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ uint16_t bcdUSB; /**< BCD of the supported USB specification. */\r
+ uint8_t bDeviceClass; /**< USB device class. */\r
+ uint8_t bDeviceSubClass; /**< USB device subclass. */\r
+ uint8_t bDeviceProtocol; /**< USB device protocol. */\r
+ uint8_t bMaxPacketSize0; /**< Size of the control (address 0) endpoint's bank in bytes. */\r
+ uint16_t idVendor; /**< Vendor ID for the USB product. */\r
+ uint16_t idProduct; /**< Unique product ID for the USB product. */\r
+ uint16_t bcdDevice; /**< Product release (version) number. */\r
+ uint8_t iManufacturer; /**< String index for the manufacturer's name. The\r
+ * host will request this string via a separate\r
+ * control request for the string descriptor.\r
+ *\r
+ * @note If no string supplied, use @ref NO_DESCRIPTOR.\r
+ */\r
+ uint8_t iProduct; /**< String index for the product name/details.\r
+ *\r
+ * @see ManufacturerStrIndex structure entry.\r
+ */\r
+ uint8_t iSerialNumber; /**< String index for the product's globally unique hexadecimal\r
+ * serial number, in uppercase Unicode ASCII.\r
+ *\r
+ * @note On some microcontroller models, there is an embedded serial number\r
+ * in the chip which can be used for the device serial number.\r
+ * To use this serial number, set this to USE_INTERNAL_SERIAL.\r
+ * On unsupported devices, this will evaluate to 0 and will cause\r
+ * the host to generate a pseudo-unique value for the device upon\r
+ * insertion.\r
+ *\r
+ * @see ManufacturerStrIndex structure entry.\r
+ */\r
+ uint8_t bNumConfigurations; /**< Total number of configurations supported by\r
+ * the device.\r
+ */\r
+ } ATTR_PACKED USB_StdDescriptor_Device_t;\r
+\r
+ /** @brief Standard USB Device Qualifier Descriptor (LPCUSBlib naming conventions).\r
+ *\r
+ * Type define for a standard Device Qualifier Descriptor. This structure uses LPCUSBlib-specific element names\r
+ * to make each element's purpose clearer.\r
+ *\r
+ * @see @ref USB_StdDescriptor_DeviceQualifier_t for the version of this type with standard element names.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */\r
+\r
+ uint16_t USBSpecification; /**< BCD of the supported USB specification. */\r
+ uint8_t Class; /**< USB device class. */\r
+ uint8_t SubClass; /**< USB device subclass. */\r
+ uint8_t Protocol; /**< USB device protocol. */\r
+\r
+ uint8_t Endpoint0Size; /**< Size of the control (address 0) endpoint's bank in bytes. */\r
+ uint8_t NumberOfConfigurations; /**< Total number of configurations supported by\r
+ * the device.\r
+ */\r
+ uint8_t Reserved; /**< Reserved for future use, must be 0. */\r
+ } ATTR_PACKED USB_Descriptor_DeviceQualifier_t;\r
+\r
+ /** @brief Standard USB Device Qualifier Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a standard Device Qualifier Descriptor. This structure uses the relevant standard's given element names\r
+ * to ensure compatibility with the standard.\r
+ *\r
+ * @see @ref USB_Descriptor_DeviceQualifier_t for the version of this type with non-standard LPCUSBlib specific element names.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ uint16_t bcdUSB; /**< BCD of the supported USB specification. */\r
+ uint8_t bDeviceClass; /**< USB device class. */\r
+ uint8_t bDeviceSubClass; /**< USB device subclass. */\r
+ uint8_t bDeviceProtocol; /**< USB device protocol. */\r
+ uint8_t bMaxPacketSize0; /**< Size of the control (address 0) endpoint's bank in bytes. */\r
+ uint8_t bNumConfigurations; /**< Total number of configurations supported by\r
+ * the device.\r
+ */\r
+ uint8_t bReserved; /**< Reserved for future use, must be 0. */\r
+ } ATTR_PACKED USB_StdDescriptor_DeviceQualifier_t;\r
+\r
+ /** @brief Standard USB Configuration Descriptor (LPCUSBlib naming conventions).\r
+ *\r
+ * Type define for a standard Configuration Descriptor header. This structure uses LPCUSBlib-specific element names\r
+ * to make each element's purpose clearer.\r
+ *\r
+ * @see @ref USB_StdDescriptor_Configuration_Header_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */\r
+\r
+ uint16_t TotalConfigurationSize; /**< Size of the configuration descriptor header,\r
+ * and all sub descriptors inside the configuration.\r
+ */\r
+ uint8_t TotalInterfaces; /**< Total number of interfaces in the configuration. */\r
+\r
+ uint8_t ConfigurationNumber; /**< Configuration index of the current configuration. */\r
+ uint8_t ConfigurationStrIndex; /**< Index of a string descriptor describing the configuration. */\r
+\r
+ uint8_t ConfigAttributes; /**< Configuration attributes, comprised of a mask of zero or\r
+ * more USB_CONFIG_ATTR_* masks.\r
+ */\r
+\r
+ uint8_t MaxPowerConsumption; /**< Maximum power consumption of the device while in the\r
+ * current configuration, calculated by the @ref USB_CONFIG_POWER_MA()\r
+ * macro.\r
+ */\r
+ } ATTR_PACKED USB_Descriptor_Configuration_Header_t;\r
+\r
+ /** @brief Standard USB Configuration Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a standard Configuration Descriptor header. This structure uses the relevant standard's given element names\r
+ * to ensure compatibility with the standard.\r
+ *\r
+ * @see @ref USB_Descriptor_Device_t for the version of this type with non-standard LPCUSBlib specific element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ uint16_t wTotalLength; /**< Size of the configuration descriptor header,\r
+ * and all sub descriptors inside the configuration.\r
+ */\r
+ uint8_t bNumInterfaces; /**< Total number of interfaces in the configuration. */\r
+ uint8_t bConfigurationValue; /**< Configuration index of the current configuration. */\r
+ uint8_t iConfiguration; /**< Index of a string descriptor describing the configuration. */\r
+ uint8_t bmAttributes; /**< Configuration attributes, comprised of a mask of zero or\r
+ * more USB_CONFIG_ATTR_* masks.\r
+ */\r
+ uint8_t bMaxPower; /**< Maximum power consumption of the device while in the\r
+ * current configuration, calculated by the @ref USB_CONFIG_POWER_MA()\r
+ * macro.\r
+ */\r
+ } ATTR_PACKED USB_StdDescriptor_Configuration_Header_t;\r
+\r
+ /** @brief Standard USB Interface Descriptor (LPCUSBlib naming conventions).\r
+ *\r
+ * Type define for a standard Interface Descriptor. This structure uses LPCUSBlib-specific element names\r
+ * to make each element's purpose clearer.\r
+ *\r
+ * @see @ref USB_StdDescriptor_Interface_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */\r
+\r
+ uint8_t InterfaceNumber; /**< Index of the interface in the current configuration. */\r
+ uint8_t AlternateSetting; /**< Alternate setting for the interface number. The same\r
+ * interface number can have multiple alternate settings\r
+ * with different endpoint configurations, which can be\r
+ * selected by the host.\r
+ */\r
+ uint8_t TotalEndpoints; /**< Total number of endpoints in the interface. */\r
+\r
+ uint8_t Class; /**< Interface class ID. */\r
+ uint8_t SubClass; /**< Interface subclass ID. */\r
+ uint8_t Protocol; /**< Interface protocol ID. */\r
+\r
+ uint8_t InterfaceStrIndex; /**< Index of the string descriptor describing the interface. */\r
+ } ATTR_PACKED USB_Descriptor_Interface_t;\r
+\r
+ /** @brief Standard USB Interface Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a standard Interface Descriptor. This structure uses the relevant standard's given element names\r
+ * to ensure compatibility with the standard.\r
+ *\r
+ * @see @ref USB_Descriptor_Interface_t for the version of this type with non-standard LPCUSBlib specific element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ uint8_t bInterfaceNumber; /**< Index of the interface in the current configuration. */\r
+ uint8_t bAlternateSetting; /**< Alternate setting for the interface number. The same\r
+ * interface number can have multiple alternate settings\r
+ * with different endpoint configurations, which can be\r
+ * selected by the host.\r
+ */\r
+ uint8_t bNumEndpoints; /**< Total number of endpoints in the interface. */\r
+ uint8_t bInterfaceClass; /**< Interface class ID. */\r
+ uint8_t bInterfaceSubClass; /**< Interface subclass ID. */\r
+ uint8_t bInterfaceProtocol; /**< Interface protocol ID. */\r
+ uint8_t iInterface; /**< Index of the string descriptor describing the\r
+ * interface.\r
+ */\r
+ } ATTR_PACKED USB_StdDescriptor_Interface_t;\r
+\r
+ /** @brief Standard USB Interface Association Descriptor (LPCUSBlib naming conventions).\r
+ *\r
+ * Type define for a standard Interface Association Descriptor. This structure uses LPCUSBlib-specific element names\r
+ * to make each element's purpose clearer.\r
+ *\r
+ * This descriptor has been added as a supplement to the USB2.0 standard, in the ECN located at\r
+ * <a>http://www.usb.org/developers/docs/InterfaceAssociationDescriptor_ecn.pdf</a>. It allows composite\r
+ * devices with multiple interfaces related to the same function to have the multiple interfaces bound\r
+ * together at the point of enumeration, loading one generic driver for all the interfaces in the single\r
+ * function. Read the ECN for more information.\r
+ *\r
+ * @see @ref USB_StdDescriptor_Interface_Association_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */\r
+\r
+ uint8_t FirstInterfaceIndex; /**< Index of the first associated interface. */\r
+ uint8_t TotalInterfaces; /**< Total number of associated interfaces. */\r
+\r
+ uint8_t Class; /**< Interface class ID. */\r
+ uint8_t SubClass; /**< Interface subclass ID. */\r
+ uint8_t Protocol; /**< Interface protocol ID. */\r
+\r
+ uint8_t IADStrIndex; /**< Index of the string descriptor describing the\r
+ * interface association.\r
+ */\r
+ } ATTR_PACKED USB_Descriptor_Interface_Association_t;\r
+\r
+ /** @brief Standard USB Interface Association Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a standard Interface Association Descriptor. This structure uses the relevant standard's given\r
+ * element names to ensure compatibility with the standard.\r
+ *\r
+ * This descriptor has been added as a supplement to the USB2.0 standard, in the ECN located at\r
+ * <a>http://www.usb.org/developers/docs/InterfaceAssociationDescriptor_ecn.pdf</a>. It allows composite\r
+ * devices with multiple interfaces related to the same function to have the multiple interfaces bound\r
+ * together at the point of enumeration, loading one generic driver for all the interfaces in the single\r
+ * function. Read the ECN for more information.\r
+ *\r
+ * @see @ref USB_Descriptor_Interface_Association_t for the version of this type with non-standard LPCUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a value\r
+ * given by the specific class.\r
+ */\r
+ uint8_t bFirstInterface; /**< Index of the first associated interface. */\r
+ uint8_t bInterfaceCount; /**< Total number of associated interfaces. */\r
+ uint8_t bFunctionClass; /**< Interface class ID. */\r
+ uint8_t bFunctionSubClass; /**< Interface subclass ID. */\r
+ uint8_t bFunctionProtocol; /**< Interface protocol ID. */\r
+ uint8_t iFunction; /**< Index of the string descriptor describing the\r
+ * interface association.\r
+ */\r
+ } ATTR_PACKED USB_StdDescriptor_Interface_Association_t;\r
+\r
+ /** @brief Standard USB Endpoint Descriptor (LPCUSBlib naming conventions).\r
+ *\r
+ * Type define for a standard Endpoint Descriptor. This structure uses LPCUSBlib-specific element names\r
+ * to make each element's purpose clearer.\r
+ *\r
+ * @see @ref USB_StdDescriptor_Endpoint_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */\r
+\r
+ uint8_t EndpointAddress; /**< Logical address of the endpoint within the device for the current\r
+ * configuration, including direction mask.\r
+ */\r
+ uint8_t Attributes; /**< Endpoint attributes, comprised of a mask of the endpoint type (EP_TYPE_*)\r
+ * and attributes (ENDPOINT_ATTR_*) masks.\r
+ */\r
+ uint16_t EndpointSize; /**< Size of the endpoint bank, in bytes. This indicates the maximum packet\r
+ * size that the endpoint can receive at a time.\r
+ */\r
+ uint8_t PollingIntervalMS; /**< Polling interval in milliseconds for the endpoint if it is an INTERRUPT\r
+ * or ISOCHRONOUS type.\r
+ */\r
+ } ATTR_PACKED USB_Descriptor_Endpoint_t;\r
+\r
+ /** @brief Standard USB Endpoint Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a standard Endpoint Descriptor. This structure uses the relevant standard's given\r
+ * element names to ensure compatibility with the standard.\r
+ *\r
+ * @see @ref USB_Descriptor_Endpoint_t for the version of this type with non-standard LPCUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t or a\r
+ * value given by the specific class.\r
+ */\r
+ uint8_t bEndpointAddress; /**< Logical address of the endpoint within the device for the current\r
+ * configuration, including direction mask.\r
+ */\r
+ uint8_t bmAttributes; /**< Endpoint attributes, comprised of a mask of the endpoint type (EP_TYPE_*)\r
+ * and attributes (ENDPOINT_ATTR_*) masks.\r
+ */\r
+ uint16_t wMaxPacketSize; /**< Size of the endpoint bank, in bytes. This indicates the maximum packet size\r
+ * that the endpoint can receive at a time.\r
+ */\r
+ uint8_t bInterval; /**< Polling interval in milliseconds for the endpoint if it is an INTERRUPT or\r
+ * ISOCHRONOUS type.\r
+ */\r
+ } ATTR_PACKED USB_StdDescriptor_Endpoint_t;\r
+\r
+ /** @brief Standard USB String Descriptor (LPCUSBlib naming conventions).\r
+ *\r
+ * Type define for a standard string descriptor. Unlike other standard descriptors, the length\r
+ * of the descriptor for placement in the descriptor header must be determined by the @ref USB_STRING_LEN()\r
+ * macro rather than by the size of the descriptor structure, as the length is not fixed.\r
+ *\r
+ * This structure should also be used for string index 0, which contains the supported language IDs for\r
+ * the device as an array.\r
+ *\r
+ * This structure uses LPCUSBlib-specific element names to make each element's purpose clearer.\r
+ *\r
+ * @see @ref USB_StdDescriptor_String_t for the version of this type with standard element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ USB_Descriptor_Header_t Header; /**< Descriptor header, including type and size. */\r
+\r
+ uint16_t UnicodeString[]; /**< String data, as unicode characters (alternatively,\r
+ * string language IDs). If normal ASCII characters are\r
+ * to be used, they must be added as an array of characters\r
+ * rather than a normal C string so that they are widened to\r
+ * Unicode size.\r
+ *\r
+ * Under GCC, strings prefixed with the "L" character (before\r
+ * the opening string quotation mark) are considered to be\r
+ * Unicode strings, and may be used instead of an explicit\r
+ * array of ASCII characters on little endian devices with\r
+ * UTF-16-LE \c wchar_t encoding.\r
+ */\r
+ } ATTR_PACKED USB_Descriptor_String_t;\r
+\r
+ /** @brief Standard USB String Descriptor (USB-IF naming conventions).\r
+ *\r
+ * Type define for a standard string descriptor. Unlike other standard descriptors, the length\r
+ * of the descriptor for placement in the descriptor header must be determined by the @ref USB_STRING_LEN()\r
+ * macro rather than by the size of the descriptor structure, as the length is not fixed.\r
+ *\r
+ * This structure should also be used for string index 0, which contains the supported language IDs for\r
+ * the device as an array.\r
+ *\r
+ * This structure uses the relevant standard's given element names to ensure compatibility with the standard.\r
+ *\r
+ * @see @ref USB_Descriptor_String_t for the version of this type with with non-standard LPCUSBlib specific\r
+ * element names.\r
+ *\r
+ * @note Regardless of CPU architecture, these values should be stored as little endian.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of the descriptor, either a value in @ref USB_DescriptorTypes_t\r
+ * or a value given by the specific class.\r
+ */\r
+ uint16_t bString[]; /**< String data, as unicode characters (alternatively, string language IDs).\r
+ * If normal ASCII characters are to be used, they must be added as an array\r
+ * of characters rather than a normal C string so that they are widened to\r
+ * Unicode size.\r
+ *\r
+ * Under GCC, strings prefixed with the "L" character (before the opening string\r
+ * quotation mark) are considered to be Unicode strings, and may be used instead\r
+ * of an explicit array of ASCII characters.\r
+ */\r
+ } ATTR_PACKED USB_StdDescriptor_String_t;\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Macros: */\r
+ #define VERSION_TENS(x) (int)((x) / 10)\r
+ #define VERSION_ONES(x) (int)((x) - (10 * VERSION_TENS(x)))\r
+ #define VERSION_TENTHS(x) (int)(((x) - (int)(x)) * 10)\r
+ #define VERSION_HUNDREDTHS(x) (int)((((x) - (int)(x)) * 100) - (10 * VERSION_TENTHS(x)))\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB control endpoint request definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_StdRequest Standard USB Requests\r
+ * @brief USB control endpoint request definitions.\r
+ *\r
+ * This module contains definitions for the various control request parameters, so that the request\r
+ * details (such as data direction, request recipient, etc.) can be extracted via masking.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __STDREQTYPE_H__\r
+#define __STDREQTYPE_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h" \r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** Mask for the request type parameter, to indicate the direction of the request data (Host to Device\r
+ * or Device to Host). The result of this mask should then be compared to the request direction masks.\r
+ *\r
+ * @see REQDIR_* macros for masks indicating the request data direction.\r
+ */\r
+ #define CONTROL_REQTYPE_DIRECTION 0x80\r
+\r
+ /** Mask for the request type parameter, to indicate the type of request (Device, Class or Vendor\r
+ * Specific). The result of this mask should then be compared to the request type masks.\r
+ *\r
+ * @see REQTYPE_* macros for masks indicating the request type.\r
+ */\r
+ #define CONTROL_REQTYPE_TYPE 0x60\r
+\r
+ /** Mask for the request type parameter, to indicate the recipient of the request (Device, Interface\r
+ * Endpoint or Other). The result of this mask should then be compared to the request recipient\r
+ * masks.\r
+ *\r
+ * @see REQREC_* macros for masks indicating the request recipient.\r
+ */\r
+ #define CONTROL_REQTYPE_RECIPIENT 0x1F\r
+\r
+ /** \name Control Request Data Direction Masks */\r
+ //@{\r
+ /** Request data direction mask, indicating that the request data will flow from host to device.\r
+ *\r
+ * @see @ref CONTROL_REQTYPE_DIRECTION macro.\r
+ */\r
+ #define REQDIR_HOSTTODEVICE (0 << 7)\r
+\r
+ /** Request data direction mask, indicating that the request data will flow from device to host.\r
+ *\r
+ * @see @ref CONTROL_REQTYPE_DIRECTION macro.\r
+ */\r
+ #define REQDIR_DEVICETOHOST (1 << 7)\r
+ //@}\r
+\r
+ /** \name Control Request Type Masks */\r
+ //@{\r
+ /** Request type mask, indicating that the request is a standard request.\r
+ *\r
+ * @see @ref CONTROL_REQTYPE_TYPE macro.\r
+ */\r
+ #define REQTYPE_STANDARD (0 << 5)\r
+\r
+ /** Request type mask, indicating that the request is a class-specific request.\r
+ *\r
+ * @see @ref CONTROL_REQTYPE_TYPE macro.\r
+ */\r
+ #define REQTYPE_CLASS (1 << 5)\r
+\r
+ /** Request type mask, indicating that the request is a vendor specific request.\r
+ *\r
+ * @see @ref CONTROL_REQTYPE_TYPE macro.\r
+ */\r
+ #define REQTYPE_VENDOR (2 << 5)\r
+ //@}\r
+\r
+ /** \name Control Request Recipient Masks */\r
+ //@{\r
+ /** Request recipient mask, indicating that the request is to be issued to the device as a whole.\r
+ *\r
+ * @see @ref CONTROL_REQTYPE_RECIPIENT macro.\r
+ */\r
+ #define REQREC_DEVICE (0 << 0)\r
+\r
+ /** Request recipient mask, indicating that the request is to be issued to an interface in the\r
+ * currently selected configuration.\r
+ *\r
+ * @see @ref CONTROL_REQTYPE_RECIPIENT macro.\r
+ */\r
+ #define REQREC_INTERFACE (1 << 0)\r
+\r
+ /** Request recipient mask, indicating that the request is to be issued to an endpoint in the\r
+ * currently selected configuration.\r
+ *\r
+ * @see @ref CONTROL_REQTYPE_RECIPIENT macro.\r
+ */\r
+ #define REQREC_ENDPOINT (2 << 0)\r
+\r
+ /** Request recipient mask, indicating that the request is to be issued to an unspecified element\r
+ * in the currently selected configuration.\r
+ *\r
+ * @see @ref CONTROL_REQTYPE_RECIPIENT macro.\r
+ */\r
+ #define REQREC_OTHER (3 << 0)\r
+ //@}\r
+\r
+ /* Type Defines: */\r
+ /** @brief Standard USB Control Request\r
+ *\r
+ * Type define for a standard USB control request.\r
+ *\r
+ * @see The USB 2.0 specification for more information on standard control requests.\r
+ */\r
+ typedef ATTR_IAR_PACKED struct\r
+ {\r
+ uint8_t bmRequestType; /**< Type of the request. */\r
+ uint8_t bRequest; /**< Request command code. */\r
+ uint16_t wValue; /**< wValue parameter of the request. */\r
+ uint16_t wIndex; /**< wIndex parameter of the request. */\r
+ uint16_t wLength; /**< Length of the data to transfer in bytes. */\r
+ } ATTR_PACKED USB_Request_Header_t;\r
+\r
+ /* Enums: */\r
+ /** Enumeration for the various standard request commands. These commands are applicable when the\r
+ * request type is @ref REQTYPE_STANDARD (with the exception of @ref REQ_GetDescriptor, which is always\r
+ * handled regardless of the request type value).\r
+ *\r
+ * @see Chapter 9 of the USB 2.0 Specification.\r
+ */\r
+ enum USB_Control_Request_t\r
+ {\r
+ REQ_GetStatus = 0, /**< Implemented in the library for device and endpoint recipients. Passed\r
+ * to the user application for other recipients via the\r
+ * @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_ClearFeature = 1, /**< Implemented in the library for device and endpoint recipients. Passed\r
+ * to the user application for other recipients via the\r
+ * @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_SetFeature = 3, /**< Implemented in the library for device and endpoint recipients. Passed\r
+ * to the user application for other recipients via the\r
+ * @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_SetAddress = 5, /**< Implemented in the library for the device recipient. Passed\r
+ * to the user application for other recipients via the\r
+ * @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_GetDescriptor = 6, /**< Implemented in the library for device and interface recipients. Passed to the\r
+ * user application for other recipients via the\r
+ * @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_SetDescriptor = 7, /**< Not implemented in the library, passed to the user application\r
+ * via the @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_GetConfiguration = 8, /**< Implemented in the library for the device recipient. Passed\r
+ * to the user application for other recipients via the\r
+ * @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_SetConfiguration = 9, /**< Implemented in the library for the device recipient. Passed\r
+ * to the user application for other recipients via the\r
+ * @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_GetInterface = 10, /**< Not implemented in the library, passed to the user application\r
+ * via the @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_SetInterface = 11, /**< Not implemented in the library, passed to the user application\r
+ * via the @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ REQ_SynchFrame = 12, /**< Not implemented in the library, passed to the user application\r
+ * via the @ref EVENT_USB_Device_ControlRequest() event when received in\r
+ * device mode. */\r
+ };\r
+ \r
+ /** Feature Selector values for Set Feature and Clear Feature standard control requests directed to the device, interface\r
+ * and endpoint recipients.\r
+ */\r
+ enum USB_Feature_Selectors_t\r
+ {\r
+ FEATURE_SEL_EndpointHalt = 0x00, /**< Feature selector for Clear Feature or Set Feature commands. When\r
+ * used in a Set Feature or Clear Feature request this indicates that an\r
+ * endpoint (whose address is given elsewhere in the request) should have\r
+ * its stall condition changed.\r
+ */\r
+ FEATURE_SEL_DeviceRemoteWakeup = 0x01, /**< Feature selector for Device level Remote Wakeup enable set or clear.\r
+ * This feature can be controlled by the host on devices which indicate\r
+ * remote wakeup support in their descriptors to selectively disable or\r
+ * enable remote wakeup.\r
+ */\r
+ FEATURE_SEL_TestMode = 0x02, /**< Feature selector for Test Mode features, used to test the USB controller\r
+ * to check for incorrect operation.\r
+ */\r
+ };\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Macros: */\r
+ #define FEATURE_SELFPOWERED_ENABLED (1 << 0)\r
+ #define FEATURE_REMOTE_WAKEUP_ENABLED (1 << 1)\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB Controller definitions for the LPC microcontrollers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#define __INCLUDE_FROM_USB_CONTROLLER_C\r
+#include "USBController.h"\r
+\r
+volatile uint8_t USB_CurrentMode[MAX_USB_CORE];\r
+volatile bool Mem_IsInitialized = false;\r
+\r
+\r
+void USB_Init(uint8_t corenum, uint8_t mode)\r
+{\r
+#if defined(USB_CAN_BE_HOST) \r
+ if (mode == USB_MODE_Host && Mem_IsInitialized == false)\r
+ {\r
+ USB_Memory_Init(USBRAM_BUFFER_SIZE);\r
+ Mem_IsInitialized = true;\r
+ }\r
+#endif\r
+ USB_CurrentMode[corenum] = mode;\r
+ HAL_USBInit(corenum);\r
+ USB_ResetInterface(corenum, mode);\r
+ USB_IsInitialized = true;\r
+}\r
+\r
+void USB_Disable(uint8_t corenum, uint8_t mode)\r
+{\r
+ USB_IsInitialized = false;\r
+ if (mode == USB_MODE_Device) {\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ HAL_USBConnect(corenum, 0);\r
+ HAL_USBDeInit(corenum, mode);\r
+ #endif\r
+ }\r
+ if (mode == USB_MODE_Host) {\r
+ #if defined(USB_CAN_BE_HOST)\r
+\r
+ #if defined(USB_MULTI_PORTS)\r
+ uint8_t i;\r
+ for (i = 0; i < MAX_USB_CORE; i++) {\r
+ HcdDeInitDriver(i);\r
+ HAL_USBDeInit(i, mode);\r
+ }\r
+ #else\r
+ HcdDeInitDriver(corenum);\r
+ HAL_USBDeInit(corenum, mode);\r
+ #endif\r
+\r
+ #endif\r
+ }\r
+}\r
+\r
+void USB_ResetInterface(uint8_t corenum, uint8_t mode)\r
+{\r
+ if (mode == USB_MODE_Device) {\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ USB_Init_Device(corenum);\r
+ #endif\r
+ }\r
+ else if (mode == USB_MODE_Host) {\r
+ #if defined(USB_CAN_BE_HOST)\r
+ USB_Init_Host(corenum);\r
+ #endif\r
+ }\r
+}\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+static void USB_Init_Device(uint8_t corenum)\r
+{\r
+ USB_DeviceState[corenum] = DEVICE_STATE_Unattached;\r
+ USB_Device_ConfigurationNumber = 0;\r
+\r
+ #if !defined(NO_DEVICE_REMOTE_WAKEUP)\r
+ USB_Device_RemoteWakeupEnabled = false;\r
+ #endif\r
+\r
+ #if !defined(NO_DEVICE_SELF_POWER)\r
+ USB_Device_CurrentlySelfPowered = false;\r
+ #endif\r
+\r
+ #if defined(USB_DEVICE_ROM_DRIVER)\r
+ UsbdRom_Init(corenum);\r
+ #else\r
+ Endpoint_ConfigureEndpoint(corenum, ENDPOINT_CONTROLEP, EP_TYPE_CONTROL,\r
+ ENDPOINT_DIR_OUT, USB_Device_ControlEndpointSize,\r
+ ENDPOINT_BANK_SINGLE);\r
+ #endif\r
+ HAL_EnableUSBInterrupt(corenum);\r
+ HAL_USBConnect(corenum, 1);\r
+}\r
+\r
+#endif\r
+\r
+#if defined(USB_CAN_BE_HOST)\r
+static void USB_Init_Host(uint8_t corenum)\r
+{\r
+ // uint8_t i;\r
+\r
+ // for(i=0;i<PIPE_TOTAL_PIPES;i++) PipeInfo[i].PipeHandle=0;\r
+\r
+ pipeselected[corenum] = PIPE_CONTROLPIPE;\r
+\r
+ USB_HostState[corenum] = HOST_STATE_Unattached;\r
+ USB_Host_ControlPipeSize[corenum] = PIPE_CONTROLPIPE_DEFAULT_SIZE;\r
+\r
+ if (HcdInitDriver(corenum) == HCD_STATUS_OK) {\r
+ USB_IsInitialized = true;\r
+ HAL_EnableUSBInterrupt(corenum);\r
+ }\r
+ else {\r
+ USB_IsInitialized = false;\r
+ HcdDeInitDriver(corenum);\r
+ }\r
+\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief Common USB Controller definitions for all architectures\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_USBManagement USB Interface Management\r
+ * @brief USB Controller definitions for general USB controller management.\r
+ *\r
+ * Functions, macros, variables, enums and types related to the setup and management of the USB interface.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __USBCONTROLLER_H__\r
+#define __USBCONTROLLER_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h" \r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks and Defines: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Defines: */\r
+ /** \name Endpoint Direction Masks */\r
+ //@{\r
+ /** Endpoint direction mask, for masking against endpoint addresses to retrieve the endpoint's\r
+ * direction for comparing with the \c ENDPOINT_DIR_* masks.\r
+ */\r
+ #define ENDPOINT_DIR_MASK 0x80\r
+\r
+ /** Endpoint address direction mask for an OUT direction (Host to Device) endpoint. This may be ORed with\r
+ * the index of the address within a device to obtain the full endpoint address.\r
+ */\r
+ #define ENDPOINT_DIR_OUT 0x00\r
+\r
+ /** Endpoint address direction mask for an IN direction (Device to Host) endpoint. This may be ORed with\r
+ * the index of the address within a device to obtain the full endpoint address.\r
+ */\r
+ #define ENDPOINT_DIR_IN 0x80\r
+ //@}\r
+\r
+ /** \name Endpoint/Pipe Type Masks */\r
+ //@{\r
+ /** Mask for determining the type of an endpoint from an endpoint descriptor. This should then be compared\r
+ * with the \c EP_TYPE_* masks to determine the exact type of the endpoint.\r
+ */\r
+ #define EP_TYPE_MASK 0x03\r
+\r
+ /** Mask for a CONTROL type endpoint or pipe.\r
+ *\r
+ * @note See @ref Group_EndpointManagement and @ref Group_PipeManagement for endpoint/pipe functions.\r
+ */\r
+ #define EP_TYPE_CONTROL 0x00\r
+\r
+ /** Mask for an ISOCHRONOUS type endpoint or pipe.\r
+ *\r
+ * @note See @ref Group_EndpointManagement and @ref Group_PipeManagement for endpoint/pipe functions.\r
+ */\r
+ #define EP_TYPE_ISOCHRONOUS 0x01\r
+\r
+ /** Mask for a BULK type endpoint or pipe.\r
+ *\r
+ * @note See @ref Group_EndpointManagement and @ref Group_PipeManagement for endpoint/pipe functions.\r
+ */\r
+ #define EP_TYPE_BULK 0x02\r
+\r
+ /** Mask for an INTERRUPT type endpoint or pipe.\r
+ *\r
+ * @note See @ref Group_EndpointManagement and @ref Group_PipeManagement for endpoint/pipe functions.\r
+ */\r
+ #define EP_TYPE_INTERRUPT 0x03\r
+ //@}\r
+\r
+ #include "Events.h"\r
+ #include "USBTask.h"\r
+ #include "USBInterrupt.h"\r
+ \r
+ #if defined(USB_CAN_BE_HOST) || defined(__DOXYGEN__)\r
+ #include "Host.h"\r
+ #include "OTG.h"\r
+ #include "Pipe.h"\r
+ #include "HostStandardReq.h"\r
+ #include "PipeStream.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_DEVICE) || defined(__DOXYGEN__)\r
+ #include "Device.h"\r
+ #include "Endpoint.h"\r
+ #include "DeviceStandardReq.h"\r
+ #include "EndpointStream.h"\r
+ #endif\r
+ \r
+ /* Public Interface - May be used in end-application: */\r
+ /* Macros: */\r
+ /** @name USB Controller Option Masks */\r
+ //@{\r
+ /** Regulator disable option mask for @ref USB_Init(). This indicates that the internal 3.3V USB data pad\r
+ * regulator should be disabled and the LPC's VCC level used for the data pads.\r
+ *\r
+ * @note See USB LPC data sheet for more information on the internal pad regulator.\r
+ */\r
+ #define USB_OPT_REG_DISABLED (1 << 1)\r
+\r
+ /** Regulator enable option mask for @ref USB_Init(). This indicates that the internal 3.3V USB data pad\r
+ * regulator should be enabled to regulate the data pin voltages from the VBUS level down to a level within\r
+ * the range allowable by the USB standard.\r
+ *\r
+ * @note See USB LPC data sheet for more information on the internal pad regulator.\r
+ */\r
+ #define USB_OPT_REG_ENABLED (0 << 1)\r
+\r
+ /** Manual PLL control option mask for @ref USB_Init(). This indicates to the library that the user application\r
+ * will take full responsibility for controlling the LPC's PLL (used to generate the high frequency clock\r
+ * that the USB controller requires) and ensuring that it is locked at the correct frequency for USB operations.\r
+ */\r
+ #define USB_OPT_MANUAL_PLL (1 << 2)\r
+\r
+ /** Automatic PLL control option mask for @ref USB_Init(). This indicates to the library that the library should\r
+ * take full responsibility for controlling the LPC's PLL (used to generate the high frequency clock\r
+ * that the USB controller requires) and ensuring that it is locked at the correct frequency for USB operations.\r
+ */\r
+ #define USB_OPT_AUTO_PLL (0 << 2)\r
+ //@}\r
+ \r
+ #if !defined(USB_STREAM_TIMEOUT_MS) || defined(__DOXYGEN__)\r
+ /** Constant for the maximum software timeout period of the USB data stream transfer functions\r
+ * (both control and standard) when in either device or host mode. If the next packet of a stream\r
+ * is not received or acknowledged within this time period, the stream function will fail.\r
+ *\r
+ * This value may be overridden in the user project makefile as the value of the\r
+ * @ref USB_STREAM_TIMEOUT_MS token, and passed to the compiler using the -D switch.\r
+ */\r
+ #define USB_STREAM_TIMEOUT_MS 100\r
+ #endif\r
+\r
+ /* Inline Functions: */\r
+ #if defined(USB_SERIES_4_AVR) || defined(USB_SERIES_6_AVR) || defined(USB_SERIES_7_AVR) || \\r
+ defined(__DOXYGEN__)\r
+ /**\r
+ * @brief Determines if the VBUS line is currently high (i.e. the USB host is supplying power).\r
+ *\r
+ * @note This function is not available on some AVR models which do not support hardware VBUS monitoring.\r
+ *\r
+ * @return Boolean \c true if the VBUS line is currently detecting power from a host, \c false otherwise.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline bool USB_VBUS_GetStatus(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool USB_VBUS_GetStatus(void)\r
+ {\r
+ return (USBSTA & (1 << VBUS)) ? true : false;\r
+ }\r
+\r
+ #endif\r
+\r
+ /** Detaches the device from the USB bus. This has the effect of removing the device from any\r
+ * attached host, ceasing USB communications. If no host is present, this prevents any host from\r
+ * enumerating the device once attached until @ref USB_Attach() is called.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_Detach(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Detach(void)\r
+ {}\r
+\r
+ /** Attaches the device to the USB bus. This announces the device's presence to any attached\r
+ * USB host, starting the enumeration process. If no host is present, attaching the device\r
+ * will allow for enumeration once a host is connected to the device.\r
+ *\r
+ * This is inexplicably also required for proper operation while in host mode, to enable the\r
+ * attachment of a device to the host. This is despite the bit being located in the device-mode\r
+ * register and despite the datasheet making no mention of its requirement in host mode.\r
+ */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_Attach(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Attach(void)\r
+ {}\r
+\r
+ /* Function Prototypes: */\r
+ /** Main function to initialize and start the USB interface. Once active, the USB interface will\r
+ * allow for device connection to a host when in device mode, or for device enumeration while in\r
+ * host mode.\r
+ *\r
+ * As the USB library relies on interrupts for the device and host mode enumeration processes,\r
+ * the user must enable global interrupts before or shortly after this function is called. In\r
+ * device mode, interrupts must be enabled within 500ms of this function being called to ensure\r
+ * that the host does not time out whilst enumerating the device. In host mode, interrupts may be\r
+ * enabled at the application's leisure however enumeration will not begin of an attached device\r
+ * until after this has occurred.\r
+ *\r
+ * Calling this function when the USB interface is already initialized will cause a complete USB\r
+ * interface reset and re-enumeration.\r
+ *\r
+ * \see @ref Group_Device for the \c USB_DEVICE_OPT_* masks.\r
+ */\r
+ void USB_Init(uint8_t corenum, uint8_t mode);\r
+\r
+ /** Shuts down the USB interface. This turns off the USB interface after deallocating all USB FIFO\r
+ * memory, endpoints and pipes. When turned off, no USB functionality can be used until the interface\r
+ * is restarted with the @ref USB_Init() function.\r
+ */\r
+ void USB_Disable(uint8_t corenum, uint8_t mode);\r
+\r
+ /** Resets the interface, when already initialized. This will re-enumerate the device if already connected\r
+ * to a host, or re-enumerate an already attached device when in host mode.\r
+ */\r
+ void USB_ResetInterface(uint8_t corenum, uint8_t mode);\r
+\r
+ /* Global Variables: */\r
+ extern volatile uint8_t USB_CurrentMode[];\r
+ // #if (!defined(USB_HOST_ONLY) && !defined(USB_DEVICE_ONLY)) || defined(__DOXYGEN__)\r
+ /** Indicates the mode that the USB interface is currently initialized to, a value from the\r
+ * @ref USB_Modes_t enum.\r
+ *\r
+ * @note This variable should be treated as read-only in the user application, and never manually\r
+ * changed in value.\r
+ *\r
+ * @note When the controller is initialized into UID auto-detection mode, this variable will hold the\r
+ * currently selected USB mode (i.e. @ref USB_MODE_Device or @ref USB_MODE_Host). If the controller\r
+ * is fixed into a specific mode (either through the \c USB_DEVICE_ONLY or \c USB_HOST_ONLY compile time\r
+ * options, or a limitation of the USB controller in the chosen device model) this will evaluate to\r
+ * a constant of the appropriate value and will never evaluate to @ref USB_MODE_None even when the\r
+ * USB interface is not initialized.\r
+ */\r
+ // extern volatile uint8_t USB_CurrentMode[];\r
+ // #elif defined(USB_HOST_ONLY)\r
+ // #define USB_CurrentMode[0] USB_MODE_Host\r
+ // #elif defined(USB_DEVICE_ONLY)\r
+ // #define USB_CurrentMode[0] USB_MODE_Device\r
+ // #endif\r
+\r
+ #if !defined(USE_STATIC_OPTIONS) || defined(__DOXYGEN__)\r
+ /** Indicates the current USB options that the USB interface was initialized with when @ref USB_Init()\r
+ * was called. This value will be one of the \c USB_MODE_* masks defined elsewhere in this module.\r
+ *\r
+ * @note This variable should be treated as read-only in the user application, and never manually\r
+ * changed in value.\r
+ */\r
+ extern volatile uint8_t USB_Options;\r
+ #elif defined(USE_STATIC_OPTIONS)\r
+ #define USB_Options USE_STATIC_OPTIONS\r
+ #endif\r
+\r
+ /* Enums: */\r
+ /** Enum for the possible USB controller modes, for initialization via @ref USB_Init() and indication back to the\r
+ * user application via @ref USB_CurrentMode.\r
+ */\r
+ enum USB_Modes_t {\r
+ USB_MODE_None = 0, /**< Indicates that the controller is currently not initialized in any specific USB mode. */\r
+ USB_MODE_Device = 1, /**< Indicates that the controller is currently initialized in USB Device mode. */\r
+ USB_MODE_Host = 2, /**< Indicates that the controller is currently initialized in USB Host mode. */\r
+ USB_MODE_UID = 3, /**< Indicates that the controller should determine the USB mode from the UID pin of the\r
+ * USB connector.\r
+ */\r
+ };\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_USB_CONTROLLER_C)\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ static void USB_Init_Device(uint8_t corenum);\r
+\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ static void USB_Init_Host(uint8_t corenum);\r
+\r
+ #endif\r
+ #endif\r
+\r
+ /* Inline Functions: */\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_PLL_On(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_PLL_On(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_PLL_Off(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_PLL_Off(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline bool USB_PLL_IsReady(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline bool USB_PLL_IsReady(void)\r
+ {\r
+ return true; // implement later if needed\r
+ }\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_REG_On(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_REG_On(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_REG_Off(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_REG_Off(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_OTGPAD_On(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_OTGPAD_On(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_OTGPAD_Off(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_OTGPAD_Off(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_CLK_Freeze(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_CLK_Freeze(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_CLK_Unfreeze(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_CLK_Unfreeze(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_Controller_Enable(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Controller_Enable(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_Controller_Disable(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Controller_Disable(void)\r
+ {}\r
+\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline void USB_Controller_Reset(void) ATTR_ALWAYS_INLINE;\r
+\r
+ static inline void USB_Controller_Reset(void)\r
+ {}\r
+\r
+ #if defined(USB_CAN_BE_BOTH)\r
+ PRAGMA_ALWAYS_INLINE\r
+ static inline uint8_t USB_GetUSBModeFromUID(void) ATTR_WARN_UNUSED_RESULT ATTR_ALWAYS_INLINE;\r
+\r
+ static inline uint8_t USB_GetUSBModeFromUID(void)\r
+ {\r
+ // if (USBSTA & (1 << ID))\r
+ // return USB_MODE_Device;\r
+ // else\r
+ // return USB_MODE_Host;\r
+ return 0;\r
+ }\r
+\r
+ #endif\r
+\r
+ #endif\r
+\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
+\r
--- /dev/null
+/*\r
+ * @brief USB controller interrupt service routine management\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+\r
+#ifndef __USBINTERRUPT_H__\r
+#define __USBINTERRUPT_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h" \r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Architecture Includes: */\r
+\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief Memory management for host mode\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBMode.h"\r
+\r
+#ifdef USB_CAN_BE_HOST\r
+\r
+#include "../../../Common/Common.h"\r
+#include "USBTask.h"\r
+#include "HAL/HAL.h"\r
+#include "USBMemory.h"\r
+\r
+/************************************************************************/\r
+/* LOCAL SYMBOL DECLARATIION */\r
+/************************************************************************/\r
+#define TEST_NEW_ALLOC 0\r
+\r
+#if TEST_NEW_ALLOC\r
+\r
+typedef struct MemBlockInfo_t {\r
+ uint32_t size :15; // memory size of this block\r
+ uint32_t type :2; // indicate whether this memory block is free, pad or used\r
+ uint32_t next :15; // offset (from head address) to the next block\r
+} sMemBlockInfo, *PMemBlockInfo;\r
+\r
+typedef enum\r
+{\r
+ MEM_FREE = 0,\r
+ MEM_PAD,\r
+ MEM_USED,\r
+}enMemBlockType;\r
+\r
+#else\r
+\r
+typedef struct MemBlockInfo_t {\r
+ uint32_t size :15; // memory size of this block\r
+ uint32_t isFree :1; // indicate whether this memory block is free or used\r
+ uint32_t next :16; // offset (from head address) to the next block\r
+} sMemBlockInfo, *PMemBlockInfo;\r
+\r
+#endif\r
+/************************************************************************/\r
+/* LOCAL DEFINE */\r
+/************************************************************************/\r
+#define ALIGN_FOUR_BYTES (4) // FIXME only m3 is 1 byte alignment\r
+\r
+/* FIXME the following dynamic allocation is temporarly */\r
+\r
+#define HEADER_SIZE (sizeof(sMemBlockInfo))\r
+#define HEADER_POINTER(x) ((uint8_t *)x - sizeof(sMemBlockInfo))\r
+#define NEXT_BLOCK(x) ((PMemBlockInfo) ( ((x)->next==0) ? 0 : ((uint32_t)head +(x)->next) ))\r
+#define LINK_TO_THIS_BLOCK(x) (((uint32_t)(x))-((uint32_t)head))\r
+\r
+PRAGMA_ALIGN_4\r
+static uint8_t USB_Mem_Buffer[USBRAM_BUFFER_SIZE] ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+\r
+void USB_Memory_Init(uint32_t Memory_Pool_Size)\r
+{\r
+ PMemBlockInfo head = (PMemBlockInfo) USB_Mem_Buffer;\r
+\r
+ head->next = 0;\r
+ head->size = (Memory_Pool_Size & 0xfffffffc) - HEADER_SIZE ;// align memory size\r
+#if TEST_NEW_ALLOC\r
+ head->type = MEM_FREE;\r
+#else\r
+ head->isFree = 1;\r
+#endif\r
+}\r
+\r
+uint8_t* USB_Memory_Alloc(uint32_t size, uint32_t num_aligned_bytes)\r
+{\r
+ PMemBlockInfo freeBlock=NULL, newBlock, blk_ptr = NULL;\r
+ PMemBlockInfo head = (PMemBlockInfo) USB_Mem_Buffer;\r
+\r
+#if TEST_NEW_ALLOC\r
+ for (blk_ptr = head; blk_ptr != NULL; blk_ptr = NEXT_BLOCK(blk_ptr)) // 1st-fit technique\r
+ {\r
+ if (((blk_ptr->type == MEM_FREE)||(blk_ptr->type == MEM_PAD)) && (blk_ptr->size >= size))\r
+ {\r
+ /* Filter by requested size */\r
+ if (blk_ptr->size <= HEADER_SIZE + size) // where (blk_size=size | blk_size=size+HEAD) then allocate whole block & do not create freeBlock\r
+ {\r
+ blk_ptr->next = 0;\r
+ blk_ptr->type = MEM_USED;\r
+ } else {\r
+ /* Locate empty block at end of found block */\r
+ freeBlock = (PMemBlockInfo) (((uint32_t) blk_ptr) + size + HEADER_SIZE);\r
+ freeBlock->next = blk_ptr->next;\r
+ freeBlock->size = blk_ptr->size - (HEADER_SIZE + size);\r
+ freeBlock->type = blk_ptr->type;\r
+\r
+ /* Locate new block at start of found block */\r
+ blk_ptr->size = size;\r
+ blk_ptr->next = LINK_TO_THIS_BLOCK(freeBlock);\r
+ blk_ptr->type = MEM_USED;\r
+ }\r
+ /* Filter by requested alignment*/\r
+ if(num_aligned_bytes > 0)\r
+ {\r
+ uint32_t pad_size = (((uint32_t)blk_ptr) + HEADER_SIZE) % num_aligned_bytes;\r
+ if(pad_size == 0) break; //block found\r
+ else //not fit alignment\r
+ if(blk_ptr->next != 0) //break if this is the last block in chain\r
+ {\r
+ uint32_t padBlkSize;\r
+\r
+ if((num_aligned_bytes - pad_size) >= HEADER_SIZE)\r
+ padBlkSize = num_aligned_bytes - pad_size - HEADER_SIZE;\r
+ else\r
+ padBlkSize = 2*num_aligned_bytes - pad_size - HEADER_SIZE;\r
+\r
+ if(padBlkSize > freeBlock->size) //not enough space to create new pad\r
+ {\r
+ blk_ptr->next = freeBlock->next;\r
+ blk_ptr->size = freeBlock->size + HEADER_SIZE + size;\r
+ blk_ptr->type = MEM_PAD;\r
+ }\r
+ else //there is space for new pad\r
+ {\r
+ newBlock = (PMemBlockInfo) (((uint32_t) blk_ptr) + HEADER_SIZE + padBlkSize);\r
+ newBlock->next = freeBlock->next;\r
+ newBlock->type = freeBlock->type;\r
+ newBlock->size = freeBlock->size + HEADER_SIZE + size - padBlkSize;\r
+\r
+ blk_ptr->size = padBlkSize;\r
+ blk_ptr->next = LINK_TO_THIS_BLOCK(newBlock);\r
+ blk_ptr->type = MEM_PAD;\r
+ }\r
+ }\r
+ }\r
+ else if(blk_ptr->type == MEM_USED) break;\r
+ }\r
+ }\r
+\r
+ if (blk_ptr == NULL) {\r
+ return ((uint8_t *) NULL);\r
+ }\r
+\r
+ return (((uint8_t *) blk_ptr) + HEADER_SIZE); \r
+\r
+#else\r
+ /* Align the requested size by 4 bytes */\r
+ if ((size % ALIGN_FOUR_BYTES) != 0) {\r
+ size = (((size >> 2) << 2) + ALIGN_FOUR_BYTES);\r
+ }\r
+\r
+ for (freeBlock = head; freeBlock != NULL; freeBlock = NEXT_BLOCK(freeBlock)) // 1st-fit technique\r
+ {\r
+ if ((freeBlock->isFree == 1) && (freeBlock->size >= size))\r
+ {\r
+ blk_ptr = freeBlock;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (blk_ptr == NULL) {\r
+ return ((uint8_t *) NULL);\r
+ }\r
+\r
+ if (blk_ptr->size <= HEADER_SIZE + size) // where (blk_size=size | blk_size=size+HEAD) then allocate whole block & do not create freeBlock\r
+ {\r
+ newBlock = blk_ptr;\r
+ //newBlock->size = blk_ptr->size;\r
+ //newBlock->next = blk_ptr->next;\r
+ newBlock->isFree = 0;\r
+ } else {\r
+ /* Locate empty block at end of found block */\r
+ freeBlock = (PMemBlockInfo) (((uint8_t *) blk_ptr) + size + HEADER_SIZE);\r
+ freeBlock->next = blk_ptr->next;\r
+ freeBlock->size = blk_ptr->size - (HEADER_SIZE + size);\r
+ freeBlock->isFree = 1;\r
+\r
+ /* Locate new block at start of found block */\r
+ newBlock = blk_ptr;\r
+ newBlock->size = size;\r
+ newBlock->next = LINK_TO_THIS_BLOCK(freeBlock);\r
+ newBlock->isFree = 0;\r
+ }\r
+\r
+ return (((uint8_t *) newBlock) + HEADER_SIZE);\r
+#endif\r
+}\r
+\r
+void USB_Memory_Free(uint8_t *ptr)\r
+{\r
+ PMemBlockInfo prev;\r
+ PMemBlockInfo head = (PMemBlockInfo) USB_Mem_Buffer;\r
+ PMemBlockInfo blk_ptr;\r
+\r
+ if (ptr == NULL)\r
+ {\r
+ return;\r
+ }\r
+\r
+ blk_ptr = (PMemBlockInfo) HEADER_POINTER(ptr);\r
+ \r
+#if TEST_NEW_ALLOC\r
+ \r
+ bool being_pad = false;\r
+ if (blk_ptr->next != 0) // merge with next free block\r
+ {\r
+ if ((NEXT_BLOCK(blk_ptr)->type == MEM_FREE)||(NEXT_BLOCK(blk_ptr)->type == MEM_PAD))\r
+ {\r
+ blk_ptr->size = blk_ptr->size + NEXT_BLOCK(blk_ptr)->size + HEADER_SIZE;\r
+ blk_ptr->next = NEXT_BLOCK(blk_ptr)->next;\r
+ blk_ptr->type = NEXT_BLOCK(blk_ptr)->type;\r
+ }\r
+ else being_pad = true;\r
+ }\r
+\r
+ for (prev = head; prev != NULL; prev = NEXT_BLOCK(prev)) // merge with previous free block\r
+ {\r
+ if (NEXT_BLOCK(prev) == blk_ptr)\r
+ {\r
+ if ((prev->type == MEM_FREE)||(prev->type == MEM_PAD))\r
+ {\r
+ prev->size = prev->size + blk_ptr->size + HEADER_SIZE;\r
+ prev->next = blk_ptr->next;\r
+ }\r
+ else if(being_pad == true) // prev&next blocks are used\r
+ blk_ptr->type = MEM_PAD;\r
+\r
+ break;\r
+ }\r
+ } \r
+\r
+#else\r
+ if (blk_ptr->next != 0) // merge with next free block\r
+ {\r
+ if (NEXT_BLOCK(blk_ptr)->isFree == 1)\r
+ {\r
+ blk_ptr->size = blk_ptr->size + NEXT_BLOCK(blk_ptr)->size + HEADER_SIZE;\r
+ blk_ptr->next = NEXT_BLOCK(blk_ptr)->next;\r
+ }\r
+ }\r
+\r
+ for (prev = head; prev != NULL; prev = NEXT_BLOCK(prev)) // merge with previous free block\r
+ {\r
+ if (NEXT_BLOCK(prev) == blk_ptr)\r
+ {\r
+ if (prev->isFree == 1)\r
+ {\r
+ prev->size = prev->size + blk_ptr->size + HEADER_SIZE;\r
+ prev->next = blk_ptr->next;\r
+ blk_ptr = prev;\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ blk_ptr->isFree = 1;\r
+\r
+#endif\r
+ return;\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * @brief Memory management for host mode\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __USBMEMORY_H__\r
+#define __USBMEMORY_H__\r
+\r
+/* Includes: */\r
+#include "lpc_types.h"\r
+#include "../../../Common/Common.h"\r
+\r
+/* Function Prototypes: */\r
+void USB_Memory_Init(uint32_t Memory_Pool_Size);\r
+uint8_t* USB_Memory_Alloc(uint32_t size, uint32_t num_aligned_bytes);\r
+void USB_Memory_Free(uint8_t *ptr);\r
+\r
+#endif /* __USBMEMORY_H__ */\r
--- /dev/null
+/*\r
+ * @brief USB mode and feature support definitions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @ingroup Group_USB\r
+ * @defgroup Group_USBMode USB Mode Tokens\r
+ * @brief USB mode and feature support definitions.\r
+ *\r
+ * This file defines macros indicating the type of USB controller the library is being compiled for, and its\r
+ * capabilities. These macros may then be referenced in the user application to selectively enable or disable\r
+ * code sections depending on if they are defined or not.\r
+ *\r
+ * After the inclusion of the master USB driver header, one or more of the following tokens may be defined, to\r
+ * allow the user code to conditionally enable or disable code based on the USB controller family and allowable\r
+ * USB modes. These tokens may be tested against to eliminate code relating to a USB mode which is not enabled for\r
+ * the given compilation.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef __USBMODE_H__\r
+#define __USBMODE_H__\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include /software/LPCUSBLib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ #include "../../../LPCUSBlibConfig.h"\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ #if defined(__DOXYGEN__)\r
+\r
+ /** Indicates that the target microcontroller and compilation settings allow for the\r
+ * target to be configured in USB Device mode when defined.\r
+ */\r
+ #define USB_CAN_BE_DEVICE\r
+\r
+ /** Indicates that the target microcontroller and compilation settings allow for the\r
+ * target to be configured in USB Host mode when defined.\r
+ */\r
+ #define USB_CAN_BE_HOST\r
+\r
+ /** Indicates that the target microcontroller and compilation settings allow for the\r
+ * target to be configured in either USB Device or Host mode when defined.\r
+ */\r
+ #define USB_CAN_BE_BOTH\r
+ #else\r
+ /* Macros: */\r
+ #if (defined(__LPC175X_6X__))||(defined(__LPC177X_8X__))||(defined(__LPC407X_8X__))\r
+ #define USB_CAN_BE_HOST\r
+ #define __LPC_OHCI__\r
+ #define USB_CAN_BE_DEVICE\r
+\r
+ #define MAX_USB_CORE 1\r
+\r
+ #elif (defined (__LPC18XX__)||defined(__LPC43XX__))\r
+ #define USB_CAN_BE_HOST\r
+ #define __LPC_EHCI__\r
+ #define USB_CAN_BE_DEVICE\r
+\r
+ #if (USE_USB_ROM_STACK)\r
+ #define USB_DEVICE_ROM_DRIVER\r
+ #endif\r
+\r
+ #define MAX_USB_CORE 2\r
+\r
+ #elif (defined(__LPC11U1X__) || defined(__LPC11U2X_3X__) || defined(__LPC1347__))\r
+ #define USB_CAN_BE_DEVICE\r
+\r
+ #if ((USE_USB_ROM_STACK) && (defined(__LPC11U2X_3X__) || defined(__LPC1347__)))\r
+ #define USB_DEVICE_ROM_DRIVER\r
+ #endif\r
+\r
+ #define MAX_USB_CORE 1\r
+\r
+ #endif\r
+\r
+ #if (defined(USB_CAN_BE_DEVICE) && defined(USB_CAN_BE_HOST))\r
+ #define USB_CAN_BE_BOTH\r
+ #endif\r
+\r
+ #if defined(USB_HOST_ONLY)\r
+ #if !defined(USB_CAN_BE_HOST)\r
+ #error USB_HOST_ONLY is not available for the currently selected microcontroller model.\r
+ #else\r
+ #undef USB_CAN_BE_DEVICE\r
+ #undef USB_CAN_BE_BOTH\r
+ #endif\r
+ #endif\r
+\r
+ #if defined(USB_DEVICE_ONLY)\r
+ #if !defined(USB_CAN_BE_DEVICE)\r
+ #error USB_DEVICE_ONLY is not available for the currently selected microcontroller model.\r
+ #else\r
+ #undef USB_CAN_BE_HOST\r
+ #undef USB_CAN_BE_BOTH\r
+ #endif\r
+ #endif\r
+ \r
+ #if (defined(USB_HOST_ONLY) && defined(USB_DEVICE_ONLY))\r
+ #error USB_HOST_ONLY and USB_DEVICE_ONLY are mutually exclusive.\r
+ #endif\r
+\r
+ #if (!defined(USB_CAN_BE_DEVICE) && !defined(USB_CAN_BE_HOST))\r
+ #error The currently selected device or architecture is not supported under the USB component of the library.\r
+ #endif\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * @brief Main USB service task management\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+#define __INCLUDE_FROM_USBTASK_C\r
+#define __INCLUDE_FROM_USB_DRIVER\r
+#include "USBTask.h"\r
+\r
+volatile bool USB_IsInitialized;\r
+\r
+/* This structure must be 4 bytes aligned */\r
+PRAGMA_ALIGN_4\r
+USB_Request_Header_t USB_ControlRequest ATTR_ALIGNED(4) __BSS(USBRAM_SECTION);\r
+\r
+#if defined(USB_CAN_BE_HOST) && !defined(HOST_STATE_AS_GPIOR)\r
+volatile uint8_t USB_HostState[MAX_USB_CORE];\r
+#endif\r
+\r
+#if defined(USB_CAN_BE_DEVICE) && !defined(DEVICE_STATE_AS_GPIOR)\r
+volatile uint8_t USB_DeviceState[MAX_USB_CORE];\r
+#endif\r
+\r
+void USB_USBTask(uint8_t corenum, uint8_t mode)\r
+{\r
+ #if defined(USB_HOST_ONLY)\r
+ USB_HostTask(corenum);\r
+ #elif defined(USB_DEVICE_ONLY)\r
+ USB_DeviceTask(corenum);\r
+ #else\r
+ if (mode == USB_MODE_Device)\r
+ USB_DeviceTask(corenum);\r
+ else if (mode == USB_MODE_Host)\r
+ USB_HostTask(corenum);\r
+ #endif\r
+}\r
+\r
+#if defined(USB_CAN_BE_DEVICE)\r
+static void USB_DeviceTask(uint8_t corenum)\r
+{\r
+ if (USB_DeviceState[corenum] != DEVICE_STATE_Unattached)\r
+ {\r
+ uint8_t PrevEndpoint = Endpoint_GetCurrentEndpoint(corenum);\r
+\r
+ Endpoint_SelectEndpoint(corenum, ENDPOINT_CONTROLEP);\r
+\r
+ if (Endpoint_IsSETUPReceived(corenum))\r
+ USB_Device_ProcessControlRequest(corenum);\r
+\r
+ Endpoint_SelectEndpoint(corenum, PrevEndpoint);\r
+ }\r
+}\r
+#endif\r
+\r
+#if defined(USB_CAN_BE_HOST)\r
+static void USB_HostTask(uint8_t corenum)\r
+{\r
+\r
+ uint8_t PrevPipe;\r
+\r
+ PrevPipe = Pipe_GetCurrentPipe(corenum);\r
+ Pipe_SelectPipe(corenum,PIPE_CONTROLPIPE);\r
+ USB_Host_ProcessNextHostState(corenum);\r
+ Pipe_SelectPipe(corenum,PrevPipe);\r
+}\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief Main USB service task management\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+\r
+#ifndef __USBTASK_H__\r
+#define __USBTASK_H__\r
+\r
+ /* Includes: */\r
+ #include "../../../Common/Common.h"\r
+ #include "USBMode.h" \r
+ #include "USBController.h"\r
+ #include "Events.h"\r
+ #include "StdRequestType.h"\r
+ #include "StdDescriptors.h"\r
+\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ #include "DeviceStandardReq.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_HOST)\r
+ #include "HostStandardReq.h"\r
+ #endif\r
+\r
+ /* Enable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ extern "C" {\r
+ #endif\r
+\r
+ /* Preprocessor Checks: */\r
+ #if !defined(__INCLUDE_FROM_USB_DRIVER)\r
+ #error Do not include this file directly. Include lpcroot/libraries/LPCUSBlib/Drivers/USB/USB.h instead.\r
+ #endif\r
+\r
+ /* Public Interface - May be used in end-application: */\r
+ /* Global Variables: */\r
+ /** Indicates if the USB interface is currently initialized but not necessarily connected to a host\r
+ * or device (i.e. if @ref USB_Init() has been run). If this is false, all other library globals related\r
+ * to the USB driver are invalid.\r
+ *\r
+ * @note This variable should be treated as read-only in the user application, and never manually\r
+ * changed in value.\r
+ *\r
+ * @ingroup Group_USBManagement\r
+ */\r
+ extern volatile bool USB_IsInitialized;\r
+\r
+ /** Structure containing the last received Control request when in Device mode (for use in user-applications\r
+ * inside of the @ref EVENT_USB_Device_ControlRequest() event, or for filling up with a control request to \r
+ * issue when in Host mode before calling @ref USB_Host_SendControlRequest().\r
+ *\r
+ * @note The contents of this structure is automatically endian-corrected for the current CPU architecture.\r
+ *\r
+ * @ingroup Group_USBManagement\r
+ */\r
+ extern USB_Request_Header_t USB_ControlRequest;\r
+\r
+ #if defined(USB_CAN_BE_HOST) || defined(__DOXYGEN__)\r
+ #if !defined(HOST_STATE_AS_GPIOR) || defined(__DOXYGEN__)\r
+ /** Indicates the current host state machine state. When in host mode, this indicates the state\r
+ * via one of the values of the @ref USB_Host_States_t enum values.\r
+ *\r
+ * This value should not be altered by the user application as it is handled automatically by the\r
+ * library.\r
+ *\r
+ * To reduce program size and speed up checks of this global on the LPC architecture, it can be\r
+ * placed into one of the LPC's \c GPIOR hardware registers instead of RAM by defining the\r
+ * \c HOST_STATE_AS_GPIOR token to a value between 0 and 2 in the project makefile and passing it to\r
+ * the compiler via the -D switch. When defined, the corresponding GPIOR register should not be used\r
+ * in the user application except implicitly via the library APIs.\r
+ *\r
+ * @note This global is only present if the user application can be a USB host.\r
+ *\r
+ * @see @ref USB_Host_States_t for a list of possible device states.\r
+ *\r
+ * @ingroup Group_Host\r
+ */\r
+ extern volatile uint8_t USB_HostState[MAX_USB_CORE];\r
+ #else\r
+ #define _GET_HOST_GPIOR_NAME2(y) GPIOR ## y\r
+ #define _GET_HOST_GPIOR_NAME(x) _GET_HOST_GPIOR_NAME2(x)\r
+ #define USB_HostState _GET_HOST_GPIOR_NAME(HOST_STATE_AS_GPIOR)\r
+ #endif\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_DEVICE) || defined(__DOXYGEN__)\r
+ #if !defined(DEVICE_STATE_AS_GPIOR) || defined(__DOXYGEN__)\r
+ /** Indicates the current device state machine state. When in device mode, this indicates the state\r
+ * via one of the values of the @ref USB_Device_States_t enum values.\r
+ *\r
+ * This value should not be altered by the user application as it is handled automatically by the\r
+ * library. The only exception to this rule is if the NO_LIMITED_CONTROLLER_CONNECT token is used\r
+ * (see @ref EVENT_USB_Device_Connect() and @ref EVENT_USB_Device_Disconnect() events).\r
+ *\r
+ * To reduce program size and speed up checks of this global on the LPC architecture, it can be\r
+ * placed into one of the LPC's \c GPIOR hardware registers instead of RAM by defining the\r
+ * \c DEVICE_STATE_AS_GPIOR token to a value between 0 and 2 in the project makefile and passing it to\r
+ * the compiler via the -D switch. When defined, the corresponding GPIOR register should not be used\r
+ * in the user application except implicitly via the library APIs.\r
+ *\r
+ * @note This global is only present if the user application can be a USB device.\r
+ * \n\n\r
+ *\r
+ * @note This variable should be treated as read-only in the user application, and never manually\r
+ * changed in value except in the circumstances outlined above.\r
+ *\r
+ * @see @ref USB_Device_States_t for a list of possible device states.\r
+ *\r
+ * @ingroup Group_Device\r
+ */\r
+ extern volatile uint8_t USB_DeviceState[];\r
+ #else\r
+ #define _GET_DEVICE_GPIOR_NAME2(y) GPIOR ## y\r
+ #define _GET_DEVICE_GPIOR_NAME(x) _GET_DEVICE_GPIOR_NAME2(x)\r
+ #define USB_DeviceState[0] _GET_DEVICE_GPIOR_NAME(DEVICE_STATE_AS_GPIOR)\r
+ #define USB_DeviceState[1] _GET_DEVICE_GPIOR_NAME(DEVICE_STATE_AS_GPIOR)\r
+ #endif\r
+ #endif\r
+\r
+ /* Function Prototypes: */\r
+ /** This is the main USB management task. The USB driver requires this task to be executed\r
+ * continuously when the USB system is active (device attached in host mode, or attached to a host\r
+ * in device mode) in order to manage USB communications. This task may be executed inside an RTOS,\r
+ * fast timer ISR or the main user application loop.\r
+ *\r
+ * The USB task must be serviced within 30ms while in device mode, or within 1ms while in host mode.\r
+ * The task may be serviced at all times, or (for minimum CPU consumption):\r
+ *\r
+ * - In device mode, it may be disabled at start-up, enabled on the firing of the @ref EVENT_USB_Device_Connect()\r
+ * event and disabled again on the firing of the @ref EVENT_USB_Device_Disconnect() event.\r
+ *\r
+ * - In host mode, it may be disabled at start-up, enabled on the firing of the @ref EVENT_USB_Host_DeviceAttached()\r
+ * event and disabled again on the firing of the @ref EVENT_USB_Host_DeviceEnumerationComplete() or\r
+ * @ref EVENT_USB_Host_DeviceEnumerationFailed() events.\r
+ *\r
+ * If in device mode (only), the control endpoint can instead be managed via interrupts entirely by the library\r
+ * by defining the INTERRUPT_CONTROL_ENDPOINT token and passing it to the compiler via the -D switch.\r
+ *\r
+ * @see @ref Group_Events for more information on the USB events.\r
+ *\r
+ * @ingroup Group_USBManagement\r
+ */\r
+ void USB_USBTask(uint8_t corenum, uint8_t mode);\r
+\r
+ /* Private Interface - For use in library only: */\r
+ #if !defined(__DOXYGEN__)\r
+ /* Function Prototypes: */\r
+ #if defined(__INCLUDE_FROM_USBTASK_C)\r
+ #if defined(USB_CAN_BE_HOST)\r
+ static void USB_HostTask(uint8_t corenum);\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_DEVICE)\r
+ static void USB_DeviceTask(uint8_t corenum);\r
+ #endif\r
+ #endif\r
+\r
+ /* Macros: */\r
+ #define HOST_TASK_NONBLOCK_WAIT(CoreID, Duration, NextState) MACROS{ USB_HostState[(CoreID)] = HOST_STATE_WaitForDevice; \\r
+ WaitMSRemaining = (Duration); \\r
+ PostWaitState = (NextState); }MACROE\r
+ #endif\r
+\r
+ /* Disable C linkage for C++ Compilers: */\r
+ #if defined(__cplusplus)\r
+ }\r
+ #endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief Master include file for the library USB functionality\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * Copyright(C) Dean Camera, 2011, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+/** @defgroup Group_USB USB Core - software/LPCUSBLib/Drivers/USB/USB.h\r
+ * @ingroup LPCUSBlib\r
+ *\r
+ * @section Sec_Dependencies Module Source Dependencies\r
+ * The following files must be built with any user project that uses this module:\r
+ * - LPCUSBlib/Drivers/USB/Core/ConfigDescriptor.c\r
+ * - LPCUSBlib/Drivers/USB/Core/DeviceStandardReq.c\r
+ * - LPCUSBlib/Drivers/USB/Core/Events.c\r
+ * - LPCUSBlib/Drivers/USB/Core/HostStandardReq.c\r
+ * - LPCUSBlib/Drivers/USB/Core/USBTask.c\r
+ * - LPCUSBlib/Drivers/USB/Core/Device.c\r
+ * - LPCUSBlib/Drivers/USB/Core/Endpoint.c\r
+ * - LPCUSBlib/Drivers/USB/Core/EndpointStream.c\r
+ * - LPCUSBlib/Drivers/USB/Core/Host.c\r
+ * - LPCUSBlib/Drivers/USB/Core/Pipe.c\r
+ * - LPCUSBlib/Drivers/USB/Core/PipeStream.c\r
+ * - LPCUSBlib/Drivers/USB/Core/USBController.c\r
+ * - LPCUSBlib/Drivers/USB/Class/Common/HIDParser.c\r
+ *\r
+ * @section Sec_ModDescription Module Description\r
+ * Driver and framework for the USB controller of the selected architecture and microcontroller model. This module\r
+ * consists of many submodules, and is designed to provide an easy way to configure and control USB host, device\r
+ * or OTG mode USB applications.\r
+ *\r
+ * The USB stack requires the sole control over the USB controller in the microcontroller only; i.e. it does not\r
+ * require any additional timers or other peripherals to operate. This ensures that the USB stack requires as few\r
+ * resources as possible.\r
+ *\r
+ * The USB stack can be used in Device Mode for connections to USB Hosts (see @ref Group_Device), in Host mode for\r
+ * hosting of other USB devices (see @ref Group_Host), or as a dual role device which can either act as a USB host\r
+ * or device depending on what peripheral is connected (see @ref Group_OTG). Both modes also require a common set\r
+ * of USB management functions found @ref Group_USBManagement.\r
+ */\r
+\r
+/** @defgroup Group_USBClassDrivers USB Class Drivers\r
+ * @ingroup LPCUSBlib\r
+ *\r
+ * Drivers for both host and device mode of the standard USB classes, for rapid application development.\r
+ * Class drivers give a framework which sits on top of the low level library API, allowing for standard\r
+ * USB classes to be implemented in a project with minimal user code. These drivers can be used in\r
+ * conjunction with the library low level APIs to implement interfaces both via the class drivers and via\r
+ * the standard library APIs.\r
+ *\r
+ * Multiple device mode class drivers can be used within a project, including multiple instances of the\r
+ * same class driver. In this way, USB Hosts and Devices can be made quickly using the internal class drivers\r
+ * so that more time and effort can be put into the end application instead of the USB protocol.\r
+ *\r
+ * The available class drivers and their modes are listed below.\r
+ *\r
+ * <table>\r
+ * <tr>\r
+ * <th width="100px">USB Class</th>\r
+ * <th width="90px">Device Mode</th>\r
+ * <th width="90px">Host Mode</th>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Audio</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>CDC</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>HID</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>MIDI</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Mass Storage</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Printer</td>\r
+ * <td bgcolor="#EE0000">No</td>\r
+* <td bgcolor="#00EE00">Yes</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>RNDIS</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * </tr>\r
+ * <tr>\r
+ * <td>Still Image</td>\r
+ * <td bgcolor="#EE0000">No</td>\r
+ * <td bgcolor="#00EE00">Yes</td>\r
+ * </tr>\r
+ * </table>\r
+ *\r
+ *\r
+ * @section Sec_UsingClassDrivers Using the Class Drivers\r
+ * To make the Class drivers easy to integrate into a user application, they all implement a standardized\r
+ * design with similarly named/used function, enums, defines and types. The two different modes are implemented\r
+ * slightly differently, and thus will be explained separately. For information on a specific class driver, read\r
+ * the class driver's module documentation.\r
+ *\r
+ * @subsection Sec_ClassDriverDevice Device Mode Class Drivers\r
+ * Implementing a Device Mode Class Driver in a user application requires a number of steps to be followed. Firstly,\r
+ * the module configuration and state structure must be added to the project source. These structures are named in a\r
+ * similar manner between classes, that of <tt>USB_ClassInfo_<i>{Class Name}</i>_Device_t</tt>, and are used to hold the\r
+ * complete state and configuration for each class instance. Multiple class instances is where the power of the class\r
+ * drivers lie; multiple interfaces of the same class simply require more instances of the Class Driver's \c USB_ClassInfo_*\r
+ * structure.\r
+ *\r
+ * Inside the ClassInfo structure lies two sections, a \c Config section, and a \c State section. The \c Config\r
+ * section contains the instance's configuration parameters, and <b>must have all fields set by the user application</b>\r
+ * before the class driver is used. Each Device mode Class driver typically contains a set of configuration parameters\r
+ * for the endpoint size/number of the associated logical USB interface, plus any class-specific configuration parameters.\r
+ *\r
+ * The \c State section of the \c USB_ClassInfo_* structures are designed to be controlled by the Class Drivers only for\r
+ * maintaining the Class Driver instance's state, and should not normally be set by the user application.\r
+ *\r
+ * The following is an example of a properly initialized instance of the Audio Class Driver structure:\r
+ *\r
+ * \code\r
+ * USB_ClassInfo_Audio_Device_t My_Audio_Interface =\r
+ * {\r
+ * .Config =\r
+ * {\r
+ * .StreamingInterfaceNumber = 1,\r
+ *\r
+ * .DataINEndpointNumber = 1,\r
+ * .DataINEndpointSize = 256,\r
+ * },\r
+ * };\r
+ * \endcode\r
+ *\r
+ * @note The class driver's configuration parameters should match those used in the device's descriptors that are\r
+ * sent to the host.\r
+ *\r
+ * To initialize the Class driver instance, the driver's <tt><i>{Class Name}</i>_Device_ConfigureEndpoints()</tt> function\r
+ * should be called in response to the @ref EVENT_USB_Device_ConfigurationChanged() event. This function will return a\r
+ * boolean true value if the driver successfully initialized the instance. Like all the class driver functions, this function\r
+ * takes in the address of the specific instance you wish to initialize - in this manner, multiple separate instances of\r
+ * the same class type can be initialized like this:\r
+ *\r
+ * \code\r
+ * void EVENT_USB_Device_ConfigurationChanged(void)\r
+ * {\r
+ * LEDs_SetAllLEDs(LEDMASK_USB_READY);\r
+ *\r
+ * if (!(Audio_Device_ConfigureEndpoints(&My_Audio_Interface)))\r
+ * LEDs_SetAllLEDs(LEDMASK_USB_ERROR);\r
+ * }\r
+ * \endcode\r
+ *\r
+ * Once initialized, it is important to maintain the class driver's state by repeatedly calling the Class Driver's\r
+ * <tt><i>{Class Name}</i>_Device_USBTask()</tt> function in the main program loop. The exact implementation of this\r
+ * function varies between class drivers, and can be used for any internal class driver purpose to maintain each\r
+ * instance. Again, this function uses the address of the instance to operate on, and thus needs to be called for each\r
+ * separate instance, just like the main USB maintenance routine @ref USB_USBTask():\r
+ *\r
+ * \code\r
+ * int main(void)\r
+ * {\r
+ * SetupHardware();\r
+ *\r
+ * LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY);\r
+ *\r
+ * for (;;)\r
+ * {\r
+ * Create_And_Process_Samples();\r
+ *\r
+ * Audio_Device_USBTask(&My_Audio_Interface);\r
+ * USB_USBTask();\r
+ * }\r
+ * }\r
+ * \endcode\r
+ *\r
+ * The final standardized Device Class Driver function is the Control Request handler function\r
+ * <tt><i>{Class Name}</i>_Device_ProcessControlRequest()</tt>, which should be called when the\r
+ * @ref EVENT_USB_Device_ControlRequest() event fires. This function should also be called for\r
+ * each class driver instance, using the address of the instance to operate on as the function's\r
+ * parameter. The request handler will abort if it is determined that the current request is not\r
+ * targeted at the given class driver instance, thus these methods can safely be called\r
+ * one-after-another in the event handler with no form of error checking:\r
+ *\r
+ * \code\r
+ * void EVENT_USB_Device_ControlRequest(void)\r
+ * {\r
+ * Audio_Device_ProcessControlRequest(&My_Audio_Interface);\r
+ * }\r
+ * \endcode\r
+ *\r
+ * Each class driver may also define a set of callback functions (which are prefixed by \c CALLBACK_*\r
+ * in the function's name) which <b>must</b> also be added to the user application - refer to each\r
+ * individual class driver's documentation for mandatory callbacks. In addition, each class driver may\r
+ * also define a set of events (identifiable by their prefix of \c EVENT_* in the function's name), which\r
+ * the user application <b>may</b> choose to implement, or ignore if not needed.\r
+ *\r
+ * The individual Device Mode Class Driver documentation contains more information on the non-standardized,\r
+ * class-specific functions which the user application can then use on the driver instances, such as data\r
+ * read and write routines. See each driver's individual documentation for more information on the\r
+ * class-specific functions.\r
+ *\r
+ * @subsection Sec_ClassDriverHost Host Mode Class Drivers\r
+ * Implementing a Host Mode Class Driver in a user application requires a number of steps to be followed. Firstly,\r
+ * the module configuration and state structure must be added to the project source. These structures are named in a\r
+ * similar manner between classes, that of <tt>USB_ClassInfo_<b>{Class Name}</b>_Host_t</tt>, and are used to hold the\r
+ * complete state and configuration for each class instance. Multiple class instances is where the power of the class\r
+ * drivers lie; multiple interfaces of the same class simply require more instances of the Class Driver's \c USB_ClassInfo_*\r
+ * structure.\r
+ *\r
+ * Inside the \c USB_ClassInfo_* structure lies two sections, a \c Config section, and a \c State section. The \c Config\r
+ * section contains the instance's configuration parameters, and <b>must have all fields set by the user application</b>\r
+ * before the class driver is used. Each Device mode Class driver typically contains a set of configuration parameters\r
+ * for the endpoint size/number of the associated logical USB interface, plus any class-specific configuration parameters.\r
+ *\r
+ * The \c State section of the \c USB_ClassInfo_* structures are designed to be controlled by the Class Drivers only for\r
+ * maintaining the Class Driver instance's state, and should not normally be set by the user application.\r
+ *\r
+ * The following is an example of a properly initialized instance of the MIDI Class Driver structure:\r
+ *\r
+ * \code\r
+ * USB_ClassInfo_MIDI_Host_t My_MIDI_Interface =\r
+ * {\r
+ * .Config =\r
+ * {\r
+ * .DataINPipeNumber = 1,\r
+ * .DataINPipeDoubleBank = false,\r
+ *\r
+ * .DataOUTPipeNumber = 2,\r
+ * .DataOUTPipeDoubleBank = false,\r
+ * },\r
+ * };\r
+ * \endcode\r
+ *\r
+ * To initialize the Class driver instance, the driver's <tt><b>{Class Name}</b>_Host_ConfigurePipes()</tt> function\r
+ * should be called in response to the host state machine entering the @ref HOST_STATE_Addressed state. This function\r
+ * will return an error code from the class driver's <tt><b>{Class Name}</b>_EnumerationFailure_ErrorCodes_t</tt> enum\r
+ * to indicate if the driver successfully initialized the instance and bound it to an interface in the attached device.\r
+ * Like all the class driver functions, this function takes in the address of the specific instance you wish to initialize -\r
+ * in this manner, multiple separate instances of the same class type can be initialized. A fragment of a Class Driver\r
+ * based Host mode application may look like the following:\r
+ *\r
+ * \code\r
+ * switch (USB_HostState)\r
+ * {\r
+ * case HOST_STATE_Addressed:\r
+ * LEDs_SetAllLEDs(LEDMASK_USB_ENUMERATING);\r
+ *\r
+ * uint16_t ConfigDescriptorSize;\r
+ * uint8_t ConfigDescriptorData[512];\r
+ *\r
+ * if (USB_Host_GetDeviceConfigDescriptor(1, &ConfigDescriptorSize, ConfigDescriptorData,\r
+ * sizeof(ConfigDescriptorData)) != HOST_GETCONFIG_Successful)\r
+ * {\r
+ * LEDs_SetAllLEDs(LEDMASK_USB_ERROR);\r
+ * USB_HostState = HOST_STATE_WaitForDeviceRemoval;\r
+ * break;\r
+ * }\r
+ *\r
+ * if (MIDI_Host_ConfigurePipes(&My_MIDI_Interface,\r
+ * ConfigDescriptorSize, ConfigDescriptorData) != MIDI_ENUMERROR_NoError)\r
+ * {\r
+ * LEDs_SetAllLEDs(LEDMASK_USB_ERROR);\r
+ * USB_HostState = HOST_STATE_WaitForDeviceRemoval;\r
+ * break;\r
+ * }\r
+ *\r
+ * // Other state handler code here\r
+ * \endcode\r
+ *\r
+ * Note that the function also required the device's configuration descriptor so that it can determine which interface\r
+ * in the device to bind to - this can be retrieved as shown in the above fragment using the\r
+ * @ref USB_Host_GetDeviceConfigDescriptor() function. If the device does not implement the interface the class driver\r
+ * is looking for, if all the matching interfaces are already bound to class driver instances or if an error occurs while\r
+ * binding to a device interface (for example, a device endpoint bank larger that the maximum supported bank size is used)\r
+ * the configuration will fail.\r
+ *\r
+ * Once initialized, it is important to maintain the class driver's state by repeatedly calling the Class Driver's\r
+ * <tt><b>{Class Name}</b>_Host_USBTask()</tt> function in the main program loop. The exact implementation of this\r
+ * function varies between class drivers, and can be used for any internal class driver purpose to maintain each\r
+ * instance. Again, this function uses the address of the instance to operate on, and thus needs to be called for each\r
+ * separate instance, just like the main USB maintenance routine @ref USB_USBTask():\r
+ *\r
+ * \code\r
+ * int main(void)\r
+ * {\r
+ * SetupHardware();\r
+ *\r
+ * LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY);\r
+ *\r
+ * for (;;)\r
+ * {\r
+ * switch (USB_HostState)\r
+ * {\r
+ * // Host state machine handling here\r
+ * }\r
+ *\r
+ * MIDI_Host_USBTask(&My_Audio_Interface);\r
+ * USB_USBTask();\r
+ * }\r
+ * }\r
+ * \endcode\r
+ *\r
+ * Each class driver may also define a set of callback functions (which are prefixed by \c CALLBACK_*\r
+ * in the function's name) which <b>must</b> also be added to the user application - refer to each\r
+ * individual class driver's documentation for mandatory callbacks. In addition, each class driver may\r
+ * also define a set of events (identifiable by their prefix of \c EVENT_* in the function's name), which\r
+ * the user application <b>may</b> choose to implement, or ignore if not needed.\r
+ *\r
+ * The individual Host Mode Class Driver documentation contains more information on the non-standardized,\r
+ * class-specific functions which the user application can then use on the driver instances, such as data\r
+ * read and write routines. See each driver's individual documentation for more information on the\r
+ * class-specific functions.\r
+ */\r
+\r
+#ifndef __USB_H__\r
+#define __USB_H__\r
+\r
+ /* Macros: */\r
+ #define __INCLUDE_FROM_USB_DRIVER\r
+\r
+ /* Includes: */\r
+ #include "../../Common/Common.h"\r
+ #include "Core/USBMode.h"\r
+\r
+ /* Includes: */\r
+ #include "Core/USBTask.h"\r
+ #include "Core/Events.h"\r
+ #include "Core/StdDescriptors.h"\r
+ #include "Core/ConfigDescriptor.h"\r
+ #include "Core/USBController.h"\r
+ #include "Core/USBInterrupt.h"\r
+\r
+ #if defined(USB_CAN_BE_HOST) || defined(__DOXYGEN__)\r
+ #include "Core/Host.h"\r
+ #include "Core/Pipe.h"\r
+ #include "Core/HostStandardReq.h"\r
+ #include "Core/PipeStream.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_DEVICE) || defined(__DOXYGEN__)\r
+ #include "Core/Device.h"\r
+ #include "Core/Endpoint.h"\r
+ #include "Core/DeviceStandardReq.h"\r
+ #include "Core/EndpointStream.h"\r
+ #endif\r
+\r
+ #if defined(USB_CAN_BE_BOTH) || defined(__DOXYGEN__)\r
+ #include "Core/OTG.h"\r
+ #endif\r
+\r
+ #include "Class/AudioClass.h"\r
+ #include "Class/CDCClass.h"\r
+ #include "Class/HIDClass.h"\r
+ #include "Class/MassStorageClass.h"\r
+ #include "Class/MIDIClass.h"\r
+ #include "Class/PrinterClass.h"\r
+ #include "Class/RNDISClass.h"\r
+ #include "Class/StillImageClass.h"\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * @brief LPCUSB library's configurations\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+ \r
+/** @defgroup USB_Config USB Configuration\r
+ * @ingroup LPCUSBlib\r
+* @{\r
+*/\r
+\r
+#ifndef LPCUSBLIB_CONFIG_H_\r
+#define LPCUSBLIB_CONFIG_H_\r
+\r
+/** Define NXPUSBLIB_DEBUG to allow the library prints out diagnostic messages */\r
+//#define NXPUSBLIB_DEBUG\r
+\r
+/** Available configuration number in a device */\r
+#define FIXED_NUM_CONFIGURATIONS 1\r
+\r
+/** Control endpoint max packet size */\r
+#define FIXED_CONTROL_ENDPOINT_SIZE 64\r
+\r
+//#define __TEST__ /* Test development */\r
+\r
+/** Size of share memory that a device uses to store data transfer to/ receive from host\r
+ * or a host uses to store data transfer to/ receive from device.\r
+ */\r
+#define USBRAM_BUFFER_SIZE (4*1024)\r
+\r
+/** This option effects only on high speed parts that need to test full speed activities */\r
+#define USB_FORCED_FULLSPEED 0\r
+\r
+/** Define USE_USB_ROM_STACK = 1 to use MCU's internal ROM stack, 0 if otherwise */\r
+#define USE_USB_ROM_STACK 0\r
+\r
+#endif /* NXPUSBLIB_CONFIG_H_ */\r
+\r
+/**\r
+* @}\r
+*/\r
--- /dev/null
+Copyright(C) NXP Semiconductors, 2012\r
+All rights reserved.\r
+\r
+Software that is described herein is for illustrative purposes only\r
+which provides customers with programming information regarding the\r
+LPC products. This software is supplied "AS IS" without any warranties of\r
+any kind, and NXP Semiconductors and its licensor disclaim any and \r
+all warranties, express or implied, including all implied warranties of \r
+merchantability, fitness for a particular purpose and non-infringement of \r
+intellectual property rights. NXP Semiconductors assumes no responsibility\r
+or liability for the use of the software, conveys no license or rights under any\r
+patent, copyright, mask work right, or any other intellectual property rights in \r
+or to any products. NXP Semiconductors reserves the right to make changes\r
+in the software without notification. NXP Semiconductors also makes no \r
+representation or warranty that such application will be suitable for the\r
+specified use without further testing or modification.\r
+\r
+Permission to use, copy, modify, and distribute this software and its \r
+documentation is hereby granted, under NXP Semiconductors' and its \r
+licensor's relevant copyrights in the software, without fee, provided that it \r
+is used in conjunction with NXP Semiconductors microcontrollers. This \r
+copyright, permission, and disclaimer notice must appear in all copies of \r
+this code.
\ No newline at end of file
--- /dev/null
+== LPCUSBlib software package == (http://www.lpcware.com/content/project/LPCUSBlib)\r
+\r
+Top level directories:\r
+\r
+applications/examples\r
+A collection of several example applications based on host/device mode and USB class\r
+\r
+applications/projects\r
+A collection of custom applications using the LPCUSBlib, BSP, and CDL libraries\r
+\r
+libraries/BSP - Board Support Package\r
+includes common code in bsp.c and bsp.h and a separate set of files for each support board\r
+\r
+libraries/CDL - Common Driver Library\r
+includes CMSIS and driver library files for multiple MCUs\r
+\r
+libraries/LPCUSBlib - NXP's USB library\r
+USB class and driver software for NXP USB controllers\r
+\r
+\r
+==========================================================================================\r
+Build instructions\r
+\r
+\r
+LPCXpresso 4 IDE (Code Red)\r
+\r
+\r
+1. Start up the IDE\r
+2. Choose a workspace folder\r
+3. Click File->Import->General->Existing Projects into Workspace->Next\r
+4. Browse to the base of your LPCUSBlib release (the location of this file)\r
+5. Click Finish\r
+\r
+At this point the Project Explorer should show the following projects:\r
+\r
+BSP (Board Support Package)\r
+CDL (Common Driver Library)\r
+Example_<app name> (Example applications)\r
+LPCUSBlib (NXP's USB library)\r
+Project_<proj name> (Miscellaneous projects)\r
+\r
+6. Right click on BSP->Build Configurations->Set Active and select your development board\r
+7. Right click on CDL->Build Configurations->Set Active and select your MCU\r
+8. Right click on LPCUSBlib->Build Configurations->Set Active and select your MCU\r
+9. Right click on Example_<app name>->Build Configurations->Set Active and select your MCU\r
+10. Right click on Example_<app name>->Properties->C/C++ Build->MCU Settings and select your MCU\r
+11. Right click on Example_<app name>->Build Project\r
+\r
+ \r
+\r
+\r
+tips:\r
+\r
+To reset the IDE to its default look and feel, right click on the Develop box in the upper right hand corner of the tool and select Reset\r
+\r
+\r
+-----------------------------------------------------------------------\r
+uVision 4 (Keil)\r
+\r
+1. Start up the IDE\r
+2. Open the workspace at Demos\keil_workspace.uvmpw\r
+3. Click Projects->Batch Build...\r
+4. Select your board and MCU in the 6 projects. \r
+\r
+To build a mass storage device example for the MCB1700 click DelectAll and select:\r
+ BSP = MCB1700\r
+ CDL = LPC17xx\r
+ Example_MassStorageDevice = MCB1700\r
+ LPCUSBlib_Device = LPC17xx_Device\r
+5. Click Build
\ No newline at end of file
--- /dev/null
+# Doxyfile 1.8.0\r
+\r
+# This file describes the settings to be used by the documentation system\r
+# doxygen (www.doxygen.org) for a project\r
+#\r
+# All text after a hash (#) is considered a comment and will be ignored\r
+# The format is:\r
+# TAG = value [value, ...]\r
+# For lists items can also be appended using:\r
+# TAG += value [value, ...]\r
+# Values that contain spaces should be placed between quotes (" ")\r
+\r
+#---------------------------------------------------------------------------\r
+# Project related configuration options\r
+#---------------------------------------------------------------------------\r
+\r
+# This tag specifies the encoding used for all characters in the config file \r
+# that follow. The default is UTF-8 which is also the encoding used for all \r
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the \r
+# iconv built into libc) for the transcoding. See \r
+# http://www.gnu.org/software/libiconv for the list of possible encodings.\r
+\r
+DOXYFILE_ENCODING = UTF-8\r
+\r
+# The PROJECT_NAME tag is a single word (or sequence of words) that should \r
+# identify the project. Note that if you do not use Doxywizard you need \r
+# to put quotes around the project name if it contains spaces.\r
+\r
+PROJECT_NAME = LPCUSBlib\r
+\r
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. \r
+# This could be handy for archiving the generated documentation or \r
+# if some version control system is used.\r
+\r
+PROJECT_NUMBER = v0.95\r
+\r
+# Using the PROJECT_BRIEF tag one can provide an optional one line description \r
+# for a project that appears at the top of each page and should give viewer \r
+# a quick idea about the purpose of the project. Keep the description short.\r
+\r
+PROJECT_BRIEF = "A USB software library for NXP Cortex microcontrollers"\r
+\r
+# With the PROJECT_LOGO tag one can specify an logo or icon that is \r
+# included in the documentation. The maximum height of the logo should not \r
+# exceed 55 pixels and the maximum width should not exceed 200 pixels. \r
+# Doxygen will copy the logo to the output directory.\r
+\r
+PROJECT_LOGO = "C:/Projects/LPCware.com/LPCUSBlib v0.93/UsersManual/LPCUSBlib_thumb_small.png"\r
+\r
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) \r
+# base path where the generated documentation will be put. \r
+# If a relative path is entered, it will be relative to the location \r
+# where doxygen was started. If left blank the current directory will be used.\r
+\r
+OUTPUT_DIRECTORY = ./Documentation/\r
+\r
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create \r
+# 4096 sub-directories (in 2 levels) under the output directory of each output \r
+# format and will distribute the generated files over these directories. \r
+# Enabling this option can be useful when feeding doxygen a huge amount of \r
+# source files, where putting all generated files in the same directory would \r
+# otherwise cause performance problems for the file system.\r
+\r
+CREATE_SUBDIRS = NO\r
+\r
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all \r
+# documentation generated by doxygen is written. Doxygen will use this \r
+# information to generate all constant output in the proper language. \r
+# The default language is English, other supported languages are: \r
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, \r
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, \r
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English \r
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, \r
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, \r
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.\r
+\r
+OUTPUT_LANGUAGE = English\r
+\r
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will \r
+# include brief member descriptions after the members that are listed in \r
+# the file and class documentation (similar to JavaDoc). \r
+# Set to NO to disable this.\r
+\r
+BRIEF_MEMBER_DESC = YES\r
+\r
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend \r
+# the brief description of a member or function before the detailed description. \r
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the \r
+# brief descriptions will be completely suppressed.\r
+\r
+REPEAT_BRIEF = NO\r
+\r
+# This tag implements a quasi-intelligent brief description abbreviator \r
+# that is used to form the text in various listings. Each string \r
+# in this list, if found as the leading text of the brief description, will be \r
+# stripped from the text and the result after processing the whole list, is \r
+# used as the annotated text. Otherwise, the brief description is used as-is. \r
+# If left blank, the following values are used ("$name" is automatically \r
+# replaced with the name of the entity): "The $name class" "The $name widget" \r
+# "The $name file" "is" "provides" "specifies" "contains" \r
+# "represents" "a" "an" "the"\r
+\r
+ABBREVIATE_BRIEF = "The $name class" \\r
+ "The $name widget" \\r
+ "The $name file" \\r
+ is \\r
+ provides \\r
+ specifies \\r
+ contains \\r
+ represents \\r
+ a \\r
+ an \\r
+ the\r
+\r
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then \r
+# Doxygen will generate a detailed section even if there is only a brief \r
+# description.\r
+\r
+ALWAYS_DETAILED_SEC = NO\r
+\r
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all \r
+# inherited members of a class in the documentation of that class as if those \r
+# members were ordinary class members. Constructors, destructors and assignment \r
+# operators of the base classes will not be shown.\r
+\r
+INLINE_INHERITED_MEMB = NO\r
+\r
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full \r
+# path before files name in the file list and in the header files. If set \r
+# to NO the shortest path that makes the file name unique will be used.\r
+\r
+FULL_PATH_NAMES = YES\r
+\r
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag \r
+# can be used to strip a user-defined part of the path. Stripping is \r
+# only done if one of the specified strings matches the left-hand part of \r
+# the path. The tag can be used to show relative paths in the file list. \r
+# If left blank the directory from which doxygen is run is used as the \r
+# path to strip.\r
+\r
+STRIP_FROM_PATH = C:\Projects\LPCware.com\r
+\r
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of \r
+# the path mentioned in the documentation of a class, which tells \r
+# the reader which header file to include in order to use a class. \r
+# If left blank only the name of the header file containing the class \r
+# definition is used. Otherwise one should specify the include paths that \r
+# are normally passed to the compiler using the -I flag.\r
+\r
+STRIP_FROM_INC_PATH = C:\Projects\LPCware.com\r
+\r
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter \r
+# (but less readable) file names. This can be useful if your file system \r
+# doesn't support long names like on DOS, Mac, or CD-ROM.\r
+\r
+SHORT_NAMES = NO\r
+\r
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen \r
+# will interpret the first line (until the first dot) of a JavaDoc-style \r
+# comment as the brief description. If set to NO, the JavaDoc \r
+# comments will behave just like regular Qt-style comments \r
+# (thus requiring an explicit @brief command for a brief description.)\r
+\r
+JAVADOC_AUTOBRIEF = NO\r
+\r
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will \r
+# interpret the first line (until the first dot) of a Qt-style \r
+# comment as the brief description. If set to NO, the comments \r
+# will behave just like regular Qt-style comments (thus requiring \r
+# an explicit \brief command for a brief description.)\r
+\r
+QT_AUTOBRIEF = NO\r
+\r
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen \r
+# treat a multi-line C++ special comment block (i.e. a block of //! or /// \r
+# comments) as a brief description. This used to be the default behaviour. \r
+# The new default is to treat a multi-line C++ comment block as a detailed \r
+# description. Set this tag to YES if you prefer the old behaviour instead.\r
+\r
+MULTILINE_CPP_IS_BRIEF = NO\r
+\r
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented \r
+# member inherits the documentation from any documented member that it \r
+# re-implements.\r
+\r
+INHERIT_DOCS = YES\r
+\r
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce \r
+# a new page for each member. If set to NO, the documentation of a member will \r
+# be part of the file/class/namespace that contains it.\r
+\r
+SEPARATE_MEMBER_PAGES = NO\r
+\r
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. \r
+# Doxygen uses this value to replace tabs by spaces in code fragments.\r
+\r
+TAB_SIZE = 4\r
+\r
+# This tag can be used to specify a number of aliases that acts \r
+# as commands in the documentation. An alias has the form "name=value". \r
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to \r
+# put the command \sideeffect (or @sideeffect) in the documentation, which \r
+# will result in a user-defined paragraph with heading "Side Effects:". \r
+# You can put \n's in the value part of an alias to insert newlines.\r
+\r
+ALIASES = \r
+\r
+# This tag can be used to specify a number of word-keyword mappings (TCL only). \r
+# A mapping has the form "name=value". For example adding \r
+# "class=itcl::class" will allow you to use the command class in the \r
+# itcl::class meaning.\r
+\r
+TCL_SUBST = \r
+\r
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C \r
+# sources only. Doxygen will then generate output that is more tailored for C. \r
+# For instance, some of the names that are used will be different. The list \r
+# of all members will be omitted, etc.\r
+\r
+OPTIMIZE_OUTPUT_FOR_C = YES\r
+\r
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java \r
+# sources only. Doxygen will then generate output that is more tailored for \r
+# Java. For instance, namespaces will be presented as packages, qualified \r
+# scopes will look different, etc.\r
+\r
+OPTIMIZE_OUTPUT_JAVA = NO\r
+\r
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran \r
+# sources only. Doxygen will then generate output that is more tailored for \r
+# Fortran.\r
+\r
+OPTIMIZE_FOR_FORTRAN = NO\r
+\r
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL \r
+# sources. Doxygen will then generate output that is tailored for \r
+# VHDL.\r
+\r
+OPTIMIZE_OUTPUT_VHDL = NO\r
+\r
+# Doxygen selects the parser to use depending on the extension of the files it \r
+# parses. With this tag you can assign which parser to use for a given extension. \r
+# Doxygen has a built-in mapping, but you can override or extend it using this \r
+# tag. The format is ext=language, where ext is a file extension, and language \r
+# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, \r
+# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make \r
+# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C \r
+# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions \r
+# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.\r
+\r
+EXTENSION_MAPPING = \r
+\r
+# If MARKDOWN_SUPPORT is enabled (the default) then doxygen pre-processes all \r
+# comments according to the Markdown format, which allows for more readable \r
+# documentation. See http://daringfireball.net/projects/markdown/ for details. \r
+# The output of markdown processing is further processed by doxygen, so you \r
+# can mix doxygen, HTML, and XML commands with Markdown formatting. \r
+# Disable only in case of backward compatibilities issues.\r
+\r
+MARKDOWN_SUPPORT = YES\r
+\r
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want \r
+# to include (a tag file for) the STL sources as input, then you should \r
+# set this tag to YES in order to let doxygen match functions declarations and \r
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. \r
+# func(std::string) {}). This also makes the inheritance and collaboration \r
+# diagrams that involve STL classes more complete and accurate.\r
+\r
+BUILTIN_STL_SUPPORT = NO\r
+\r
+# If you use Microsoft's C++/CLI language, you should set this option to YES to \r
+# enable parsing support.\r
+\r
+CPP_CLI_SUPPORT = NO\r
+\r
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. \r
+# Doxygen will parse them like normal C++ but will assume all classes use public \r
+# instead of private inheritance when no explicit protection keyword is present.\r
+\r
+SIP_SUPPORT = NO\r
+\r
+# For Microsoft's IDL there are propget and propput attributes to indicate getter \r
+# and setter methods for a property. Setting this option to YES (the default) \r
+# will make doxygen replace the get and set methods by a property in the \r
+# documentation. This will only work if the methods are indeed getting or \r
+# setting a simple type. If this is not the case, or you want to show the \r
+# methods anyway, you should set this option to NO.\r
+\r
+IDL_PROPERTY_SUPPORT = YES\r
+\r
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC \r
+# tag is set to YES, then doxygen will reuse the documentation of the first \r
+# member in the group (if any) for the other members of the group. By default \r
+# all members of a group must be documented explicitly.\r
+\r
+DISTRIBUTE_GROUP_DOC = NO\r
+\r
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of \r
+# the same type (for instance a group of public functions) to be put as a \r
+# subgroup of that type (e.g. under the Public Functions section). Set it to \r
+# NO to prevent subgrouping. Alternatively, this can be done per class using \r
+# the \nosubgrouping command.\r
+\r
+SUBGROUPING = YES\r
+\r
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and \r
+# unions are shown inside the group in which they are included (e.g. using \r
+# @ingroup) instead of on a separate page (for HTML and Man pages) or \r
+# section (for LaTeX and RTF).\r
+\r
+INLINE_GROUPED_CLASSES = NO\r
+\r
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and \r
+# unions with only public data fields will be shown inline in the documentation \r
+# of the scope in which they are defined (i.e. file, namespace, or group \r
+# documentation), provided this scope is documented. If set to NO (the default), \r
+# structs, classes, and unions are shown on a separate page (for HTML and Man \r
+# pages) or section (for LaTeX and RTF).\r
+\r
+INLINE_SIMPLE_STRUCTS = NO\r
+\r
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum \r
+# is documented as struct, union, or enum with the name of the typedef. So \r
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct \r
+# with name TypeT. When disabled the typedef will appear as a member of a file, \r
+# namespace, or class. And the struct will be named TypeS. This can typically \r
+# be useful for C code in case the coding convention dictates that all compound \r
+# types are typedef'ed and only the typedef is referenced, never the tag name.\r
+\r
+TYPEDEF_HIDES_STRUCT = YES\r
+\r
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to \r
+# determine which symbols to keep in memory and which to flush to disk. \r
+# When the cache is full, less often used symbols will be written to disk. \r
+# For small to medium size projects (<1000 input files) the default value is \r
+# probably good enough. For larger projects a too small cache size can cause \r
+# doxygen to be busy swapping symbols to and from disk most of the time \r
+# causing a significant performance penalty. \r
+# If the system has enough physical memory increasing the cache will improve the \r
+# performance by keeping more symbols in memory. Note that the value works on \r
+# a logarithmic scale so increasing the size by one will roughly double the \r
+# memory usage. The cache size is given by this formula: \r
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, \r
+# corresponding to a cache size of 2^16 = 65536 symbols.\r
+\r
+SYMBOL_CACHE_SIZE = 1\r
+\r
+# Similar to the SYMBOL_CACHE_SIZE the size of the symbol lookup cache can be \r
+# set using LOOKUP_CACHE_SIZE. This cache is used to resolve symbols given \r
+# their name and scope. Since this can be an expensive process and often the \r
+# same symbol appear multiple times in the code, doxygen keeps a cache of \r
+# pre-resolved symbols. If the cache is too small doxygen will become slower. \r
+# If the cache is too large, memory is wasted. The cache size is given by this \r
+# formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range is 0..9, the default is 0, \r
+# corresponding to a cache size of 2^16 = 65536 symbols.\r
+\r
+LOOKUP_CACHE_SIZE = 0\r
+\r
+#---------------------------------------------------------------------------\r
+# Build related configuration options\r
+#---------------------------------------------------------------------------\r
+\r
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in \r
+# documentation are documented, even if no documentation was available. \r
+# Private class members and static file members will be hidden unless \r
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES\r
+\r
+EXTRACT_ALL = YES\r
+\r
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class \r
+# will be included in the documentation.\r
+\r
+EXTRACT_PRIVATE = YES\r
+\r
+# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\r
+# scope will be included in the documentation.\r
+\r
+EXTRACT_PACKAGE = NO\r
+\r
+# If the EXTRACT_STATIC tag is set to YES all static members of a file \r
+# will be included in the documentation.\r
+\r
+EXTRACT_STATIC = YES\r
+\r
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) \r
+# defined locally in source files will be included in the documentation. \r
+# If set to NO only classes defined in header files are included.\r
+\r
+EXTRACT_LOCAL_CLASSES = YES\r
+\r
+# This flag is only useful for Objective-C code. When set to YES local \r
+# methods, which are defined in the implementation section but not in \r
+# the interface are included in the documentation. \r
+# If set to NO (the default) only methods in the interface are included.\r
+\r
+EXTRACT_LOCAL_METHODS = NO\r
+\r
+# If this flag is set to YES, the members of anonymous namespaces will be \r
+# extracted and appear in the documentation as a namespace called \r
+# 'anonymous_namespace{file}', where file will be replaced with the base \r
+# name of the file that contains the anonymous namespace. By default \r
+# anonymous namespaces are hidden.\r
+\r
+EXTRACT_ANON_NSPACES = NO\r
+\r
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all \r
+# undocumented members of documented classes, files or namespaces. \r
+# If set to NO (the default) these members will be included in the \r
+# various overviews, but no documentation section is generated. \r
+# This option has no effect if EXTRACT_ALL is enabled.\r
+\r
+HIDE_UNDOC_MEMBERS = NO\r
+\r
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all \r
+# undocumented classes that are normally visible in the class hierarchy. \r
+# If set to NO (the default) these classes will be included in the various \r
+# overviews. This option has no effect if EXTRACT_ALL is enabled.\r
+\r
+HIDE_UNDOC_CLASSES = NO\r
+\r
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all \r
+# friend (class|struct|union) declarations. \r
+# If set to NO (the default) these declarations will be included in the \r
+# documentation.\r
+\r
+HIDE_FRIEND_COMPOUNDS = NO\r
+\r
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any \r
+# documentation blocks found inside the body of a function. \r
+# If set to NO (the default) these blocks will be appended to the \r
+# function's detailed documentation block.\r
+\r
+HIDE_IN_BODY_DOCS = NO\r
+\r
+# The INTERNAL_DOCS tag determines if documentation \r
+# that is typed after a \internal command is included. If the tag is set \r
+# to NO (the default) then the documentation will be excluded. \r
+# Set it to YES to include the internal documentation.\r
+\r
+INTERNAL_DOCS = NO\r
+\r
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate \r
+# file names in lower-case letters. If set to YES upper-case letters are also \r
+# allowed. This is useful if you have classes or files whose names only differ \r
+# in case and if your file system supports case sensitive file names. Windows \r
+# and Mac users are advised to set this option to NO.\r
+\r
+CASE_SENSE_NAMES = NO\r
+\r
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen \r
+# will show members with their full class and namespace scopes in the \r
+# documentation. If set to YES the scope will be hidden.\r
+\r
+HIDE_SCOPE_NAMES = NO\r
+\r
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen \r
+# will put a list of the files that are included by a file in the documentation \r
+# of that file.\r
+\r
+SHOW_INCLUDE_FILES = YES\r
+\r
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen \r
+# will list include files with double quotes in the documentation \r
+# rather than with sharp brackets.\r
+\r
+FORCE_LOCAL_INCLUDES = NO\r
+\r
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] \r
+# is inserted in the documentation for inline members.\r
+\r
+INLINE_INFO = YES\r
+\r
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen \r
+# will sort the (detailed) documentation of file and class members \r
+# alphabetically by member name. If set to NO the members will appear in \r
+# declaration order.\r
+\r
+SORT_MEMBER_DOCS = YES\r
+\r
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the \r
+# brief documentation of file, namespace and class members alphabetically \r
+# by member name. If set to NO (the default) the members will appear in \r
+# declaration order.\r
+\r
+SORT_BRIEF_DOCS = NO\r
+\r
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen \r
+# will sort the (brief and detailed) documentation of class members so that \r
+# constructors and destructors are listed first. If set to NO (the default) \r
+# the constructors will appear in the respective orders defined by \r
+# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. \r
+# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO \r
+# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.\r
+\r
+SORT_MEMBERS_CTORS_1ST = NO\r
+\r
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the \r
+# hierarchy of group names into alphabetical order. If set to NO (the default) \r
+# the group names will appear in their defined order.\r
+\r
+SORT_GROUP_NAMES = YES\r
+\r
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be \r
+# sorted by fully-qualified names, including namespaces. If set to \r
+# NO (the default), the class list will be sorted only by class name, \r
+# not including the namespace part. \r
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. \r
+# Note: This option applies only to the class list, not to the \r
+# alphabetical list.\r
+\r
+SORT_BY_SCOPE_NAME = NO\r
+\r
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to \r
+# do proper type resolution of all parameters of a function it will reject a \r
+# match between the prototype and the implementation of a member function even \r
+# if there is only one candidate or it is obvious which candidate to choose \r
+# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen \r
+# will still accept a match between prototype and implementation in such cases.\r
+\r
+STRICT_PROTO_MATCHING = NO\r
+\r
+# The GENERATE_TODOLIST tag can be used to enable (YES) or \r
+# disable (NO) the todo list. This list is created by putting \todo \r
+# commands in the documentation.\r
+\r
+GENERATE_TODOLIST = NO\r
+\r
+# The GENERATE_TESTLIST tag can be used to enable (YES) or \r
+# disable (NO) the test list. This list is created by putting \test \r
+# commands in the documentation.\r
+\r
+GENERATE_TESTLIST = NO\r
+\r
+# The GENERATE_BUGLIST tag can be used to enable (YES) or \r
+# disable (NO) the bug list. This list is created by putting \bug \r
+# commands in the documentation.\r
+\r
+GENERATE_BUGLIST = NO\r
+\r
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or \r
+# disable (NO) the deprecated list. This list is created by putting \r
+# \deprecated commands in the documentation.\r
+\r
+GENERATE_DEPRECATEDLIST= YES\r
+\r
+# The ENABLED_SECTIONS tag can be used to enable conditional \r
+# documentation sections, marked by \if sectionname ... \endif.\r
+\r
+ENABLED_SECTIONS = \r
+\r
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines \r
+# the initial value of a variable or macro consists of for it to appear in \r
+# the documentation. If the initializer consists of more lines than specified \r
+# here it will be hidden. Use a value of 0 to hide initializers completely. \r
+# The appearance of the initializer of individual variables and macros in the \r
+# documentation can be controlled using \showinitializer or \hideinitializer \r
+# command in the documentation regardless of this setting.\r
+\r
+MAX_INITIALIZER_LINES = 15\r
+\r
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated \r
+# at the bottom of the documentation of classes and structs. If set to YES the \r
+# list will mention the files that were used to generate the documentation.\r
+\r
+SHOW_USED_FILES = YES\r
+\r
+# If the sources in your project are distributed over multiple directories \r
+# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy \r
+# in the documentation. The default is NO.\r
+\r
+SHOW_DIRECTORIES = YES\r
+\r
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page. \r
+# This will remove the Files entry from the Quick Index and from the \r
+# Folder Tree View (if specified). The default is YES.\r
+\r
+SHOW_FILES = YES\r
+\r
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the \r
+# Namespaces page. This will remove the Namespaces entry from the Quick Index \r
+# and from the Folder Tree View (if specified). The default is YES.\r
+\r
+SHOW_NAMESPACES = YES\r
+\r
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that \r
+# doxygen should invoke to get the current version for each file (typically from \r
+# the version control system). Doxygen will invoke the program by executing (via \r
+# popen()) the command <command> <input-file>, where <command> is the value of \r
+# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file \r
+# provided by doxygen. Whatever the program writes to standard output \r
+# is used as the file version. See the manual for examples.\r
+\r
+FILE_VERSION_FILTER = \r
+\r
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed \r
+# by doxygen. The layout file controls the global structure of the generated \r
+# output files in an output format independent way. The create the layout file \r
+# that represents doxygen's defaults, run doxygen with the -l option. \r
+# You can optionally specify a file name after the option, if omitted \r
+# DoxygenLayout.xml will be used as the name of the layout file.\r
+\r
+LAYOUT_FILE = \r
+\r
+# The CITE_BIB_FILES tag can be used to specify one or more bib files \r
+# containing the references data. This must be a list of .bib files. The \r
+# .bib extension is automatically appended if omitted. Using this command \r
+# requires the bibtex tool to be installed. See also \r
+# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style \r
+# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this \r
+# feature you need bibtex and perl available in the search path.\r
+\r
+CITE_BIB_FILES = \r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to warning and progress messages\r
+#---------------------------------------------------------------------------\r
+\r
+# The QUIET tag can be used to turn on/off the messages that are generated \r
+# by doxygen. Possible values are YES and NO. If left blank NO is used.\r
+\r
+QUIET = YES\r
+\r
+# The WARNINGS tag can be used to turn on/off the warning messages that are \r
+# generated by doxygen. Possible values are YES and NO. If left blank \r
+# NO is used.\r
+\r
+WARNINGS = YES\r
+\r
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings \r
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will \r
+# automatically be disabled.\r
+\r
+WARN_IF_UNDOCUMENTED = YES\r
+\r
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for \r
+# potential errors in the documentation, such as not documenting some \r
+# parameters in a documented function, or documenting parameters that \r
+# don't exist or using markup commands wrongly.\r
+\r
+WARN_IF_DOC_ERROR = YES\r
+\r
+# The WARN_NO_PARAMDOC option can be enabled to get warnings for \r
+# functions that are documented, but have no documentation for their parameters \r
+# or return value. If set to NO (the default) doxygen will only warn about \r
+# wrong or incomplete parameter documentation, but not about the absence of \r
+# documentation.\r
+\r
+WARN_NO_PARAMDOC = YES\r
+\r
+# The WARN_FORMAT tag determines the format of the warning messages that \r
+# doxygen can produce. The string should contain the $file, $line, and $text \r
+# tags, which will be replaced by the file and line number from which the \r
+# warning originated and the warning text. Optionally the format may contain \r
+# $version, which will be replaced by the version of the file (if it could \r
+# be obtained via FILE_VERSION_FILTER)\r
+\r
+WARN_FORMAT = "$file:$line: $text"\r
+\r
+# The WARN_LOGFILE tag can be used to specify a file to which warning \r
+# and error messages should be written. If left blank the output is written \r
+# to stderr.\r
+\r
+WARN_LOGFILE = \r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the input files\r
+#---------------------------------------------------------------------------\r
+\r
+# The INPUT tag can be used to specify the files and/or directories that contain \r
+# documented source files. You may enter file names like "myfile.cpp" or \r
+# directories like "/usr/src/myproject". Separate the files or directories \r
+# with spaces.\r
+\r
+INPUT = . \\r
+ ..\libraries\BSP \\r
+ ..\libraries\LPCUSBlib \\r
+ ..\applications \\r
+ ..\\r
+\r
+# This tag can be used to specify the character encoding of the source files \r
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is \r
+# also the default input encoding. Doxygen uses libiconv (or the iconv built \r
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for \r
+# the list of possible encodings.\r
+\r
+INPUT_ENCODING = UTF-8\r
+\r
+# If the value of the INPUT tag contains directories, you can use the \r
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp \r
+# and *.h) to filter out the source-files in the directories. If left \r
+# blank the following patterns are tested: \r
+# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh \r
+# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py \r
+# *.f90 *.f *.for *.vhd *.vhdl\r
+\r
+FILE_PATTERNS = *.h \\r
+ *.txt \\r
+ *.s \\r
+ *.c\r
+\r
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories \r
+# should be searched for input files as well. Possible values are YES and NO. \r
+# If left blank NO is used.\r
+\r
+RECURSIVE = YES\r
+\r
+# The EXCLUDE tag can be used to specify files and/or directories that should be \r
+# excluded from the INPUT source files. This way you can easily exclude a \r
+# subdirectory from a directory tree whose root is specified with the INPUT tag. \r
+# Note that relative paths are relative to the directory from which doxygen is \r
+# run.\r
+\r
+EXCLUDE = Documentation/ \\r
+ License.txt\r
+\r
+# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or \r
+# directories that are symbolic links (a Unix file system feature) are excluded \r
+# from the input.\r
+\r
+EXCLUDE_SYMLINKS = NO\r
+\r
+# If the value of the INPUT tag contains directories, you can use the \r
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude \r
+# certain files from those directories. Note that the wildcards are matched \r
+# against the file with absolute path, so to exclude all test directories \r
+# for example use the pattern */test/*\r
+\r
+EXCLUDE_PATTERNS = \r
+\r
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names \r
+# (namespaces, classes, functions, etc.) that should be excluded from the \r
+# output. The symbol name can be a fully qualified name, a word, or if the \r
+# wildcard * is used, a substring. Examples: ANamespace, AClass, \r
+# AClass::ANamespace, ANamespace::*Test\r
+\r
+EXCLUDE_SYMBOLS = _* \\r
+ __*\r
+\r
+# The EXAMPLE_PATH tag can be used to specify one or more files or \r
+# directories that contain example code fragments that are included (see \r
+# the \include command).\r
+\r
+EXAMPLE_PATH = ../\r
+\r
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the \r
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp \r
+# and *.h) to filter out the source-files in the directories. If left \r
+# blank all files are included.\r
+\r
+EXAMPLE_PATTERNS = *\r
+\r
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be \r
+# searched for input files to be used with the \include or \dontinclude \r
+# commands irrespective of the value of the RECURSIVE tag. \r
+# Possible values are YES and NO. If left blank NO is used.\r
+\r
+EXAMPLE_RECURSIVE = NO\r
+\r
+# The IMAGE_PATH tag can be used to specify one or more files or \r
+# directories that contain image that are included in the documentation (see \r
+# the \image command).\r
+\r
+IMAGE_PATH = ./\r
+\r
+# The INPUT_FILTER tag can be used to specify a program that doxygen should \r
+# invoke to filter for each input file. Doxygen will invoke the filter program \r
+# by executing (via popen()) the command <filter> <input-file>, where <filter> \r
+# is the value of the INPUT_FILTER tag, and <input-file> is the name of an \r
+# input file. Doxygen will then use the output that the filter program writes \r
+# to standard output. If FILTER_PATTERNS is specified, this tag will be \r
+# ignored.\r
+\r
+INPUT_FILTER = \r
+\r
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern \r
+# basis. Doxygen will compare the file name with each pattern and apply the \r
+# filter if there is a match. The filters are a list of the form: \r
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further \r
+# info on how filters are used. If FILTER_PATTERNS is empty or if \r
+# non of the patterns match the file name, INPUT_FILTER is applied.\r
+\r
+FILTER_PATTERNS = \r
+\r
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using \r
+# INPUT_FILTER) will be used to filter the input files when producing source \r
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).\r
+\r
+FILTER_SOURCE_FILES = NO\r
+\r
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file \r
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any) \r
+# and it is also possible to disable source filtering for a specific pattern \r
+# using *.ext= (so without naming a filter). This option only has effect when \r
+# FILTER_SOURCE_FILES is enabled.\r
+\r
+FILTER_SOURCE_PATTERNS = \r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to source browsing\r
+#---------------------------------------------------------------------------\r
+\r
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will \r
+# be generated. Documented entities will be cross-referenced with these sources. \r
+# Note: To get rid of all source code in the generated output, make sure also \r
+# VERBATIM_HEADERS is set to NO.\r
+\r
+SOURCE_BROWSER = NO\r
+\r
+# Setting the INLINE_SOURCES tag to YES will include the body \r
+# of functions and classes directly in the documentation.\r
+\r
+INLINE_SOURCES = NO\r
+\r
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct \r
+# doxygen to hide any special comment blocks from generated source code \r
+# fragments. Normal C and C++ comments will always remain visible.\r
+\r
+STRIP_CODE_COMMENTS = YES\r
+\r
+# If the REFERENCED_BY_RELATION tag is set to YES \r
+# then for each documented function all documented \r
+# functions referencing it will be listed.\r
+\r
+REFERENCED_BY_RELATION = NO\r
+\r
+# If the REFERENCES_RELATION tag is set to YES \r
+# then for each documented function all documented entities \r
+# called/used by that function will be listed.\r
+\r
+REFERENCES_RELATION = NO\r
+\r
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) \r
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from \r
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will \r
+# link to the source code. Otherwise they will link to the documentation.\r
+\r
+REFERENCES_LINK_SOURCE = NO\r
+\r
+# If the USE_HTAGS tag is set to YES then the references to source code \r
+# will point to the HTML generated by the htags(1) tool instead of doxygen \r
+# built-in source browser. The htags tool is part of GNU's global source \r
+# tagging system (see http://www.gnu.org/software/global/global.html). You \r
+# will need version 4.8.6 or higher.\r
+\r
+USE_HTAGS = NO\r
+\r
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen \r
+# will generate a verbatim copy of the header file for each class for \r
+# which an include is specified. Set to NO to disable this.\r
+\r
+VERBATIM_HEADERS = NO\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the alphabetical class index\r
+#---------------------------------------------------------------------------\r
+\r
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index \r
+# of all compounds will be generated. Enable this if the project \r
+# contains a lot of classes, structs, unions or interfaces.\r
+\r
+ALPHABETICAL_INDEX = YES\r
+\r
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then \r
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns \r
+# in which this list will be split (can be a number in the range [1..20])\r
+\r
+COLS_IN_ALPHA_INDEX = 5\r
+\r
+# In case all classes in a project start with a common prefix, all \r
+# classes will be put under the same header in the alphabetical index. \r
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that \r
+# should be ignored while generating the index headers.\r
+\r
+IGNORE_PREFIX = \r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the HTML output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will \r
+# generate HTML output.\r
+\r
+GENERATE_HTML = YES\r
+\r
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `html' will be used as the default path.\r
+\r
+HTML_OUTPUT = html\r
+\r
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for \r
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank \r
+# doxygen will generate files with .html extension.\r
+\r
+HTML_FILE_EXTENSION = .html\r
+\r
+# The HTML_HEADER tag can be used to specify a personal HTML header for \r
+# each generated HTML page. If it is left blank doxygen will generate a \r
+# standard header. Note that when using a custom header you are responsible \r
+# for the proper inclusion of any scripts and style sheets that doxygen \r
+# needs, which is dependent on the configuration options used. \r
+# It is advised to generate a default header using "doxygen -w html \r
+# header.html footer.html stylesheet.css YourConfigFile" and then modify \r
+# that header. Note that the header is subject to change so you typically \r
+# have to redo this when upgrading to a newer version of doxygen or when \r
+# changing the value of configuration settings such as GENERATE_TREEVIEW!\r
+\r
+HTML_HEADER = \r
+\r
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for \r
+# each generated HTML page. If it is left blank doxygen will generate a \r
+# standard footer.\r
+\r
+HTML_FOOTER = ./footer.htm\r
+\r
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading \r
+# style sheet that is used by each HTML page. It can be used to \r
+# fine-tune the look of the HTML output. If the tag is left blank doxygen \r
+# will generate a default style sheet. Note that doxygen will try to copy \r
+# the style sheet file to the HTML output directory, so don't put your own \r
+# style sheet in the HTML output directory as well, or it will be erased!\r
+\r
+HTML_STYLESHEET = \r
+\r
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or \r
+# other source files which should be copied to the HTML output directory. Note \r
+# that these files will be copied to the base HTML output directory. Use the \r
+# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these \r
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that \r
+# the files will be copied as-is; there are no commands or markers available.\r
+\r
+HTML_EXTRA_FILES = \r
+\r
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. \r
+# Doxygen will adjust the colors in the style sheet and background images \r
+# according to this color. Hue is specified as an angle on a colorwheel, \r
+# see http://en.wikipedia.org/wiki/Hue for more information. \r
+# For instance the value 0 represents red, 60 is yellow, 120 is green, \r
+# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. \r
+# The allowed range is 0 to 359.\r
+\r
+HTML_COLORSTYLE_HUE = 221\r
+\r
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of \r
+# the colors in the HTML output. For a value of 0 the output will use \r
+# grayscales only. A value of 255 will produce the most vivid colors.\r
+\r
+HTML_COLORSTYLE_SAT = 120\r
+\r
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to \r
+# the luminance component of the colors in the HTML output. Values below \r
+# 100 gradually make the output lighter, whereas values above 100 make \r
+# the output darker. The value divided by 100 is the actual gamma applied, \r
+# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, \r
+# and 100 does not change the gamma.\r
+\r
+HTML_COLORSTYLE_GAMMA = 80\r
+\r
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML \r
+# page will contain the date and time when the page was generated. Setting \r
+# this to NO can help when comparing the output of multiple runs.\r
+\r
+HTML_TIMESTAMP = NO\r
+\r
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, \r
+# files or namespaces will be aligned in HTML using tables. If set to \r
+# NO a bullet list will be used.\r
+\r
+HTML_ALIGN_MEMBERS = YES\r
+\r
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML \r
+# documentation will contain sections that can be hidden and shown after the \r
+# page has loaded. For this to work a browser that supports \r
+# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox \r
+# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).\r
+\r
+HTML_DYNAMIC_SECTIONS = YES\r
+\r
+# If the GENERATE_DOCSET tag is set to YES, additional index files \r
+# will be generated that can be used as input for Apple's Xcode 3 \r
+# integrated development environment, introduced with OSX 10.5 (Leopard). \r
+# To create a documentation set, doxygen will generate a Makefile in the \r
+# HTML output directory. Running make will produce the docset in that \r
+# directory and running "make install" will install the docset in \r
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find \r
+# it at startup. \r
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html \r
+# for more information.\r
+\r
+GENERATE_DOCSET = NO\r
+\r
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the \r
+# feed. A documentation feed provides an umbrella under which multiple \r
+# documentation sets from a single provider (such as a company or product suite) \r
+# can be grouped.\r
+\r
+DOCSET_FEEDNAME = "Doxygen generated docs"\r
+\r
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that \r
+# should uniquely identify the documentation set bundle. This should be a \r
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen \r
+# will append .docset to the name.\r
+\r
+DOCSET_BUNDLE_ID = org.doxygen.Project\r
+\r
+# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify \r
+# the documentation publisher. This should be a reverse domain-name style \r
+# string, e.g. com.mycompany.MyDocSet.documentation.\r
+\r
+DOCSET_PUBLISHER_ID = com.lufa-lib.library.documentation\r
+\r
+# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.\r
+\r
+DOCSET_PUBLISHER_NAME = DeanCamera\r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files \r
+# will be generated that can be used as input for tools like the \r
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) \r
+# of the generated HTML documentation.\r
+\r
+GENERATE_HTMLHELP = NO\r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can \r
+# be used to specify the file name of the resulting .chm file. You \r
+# can add a path in front of the file if the result should not be \r
+# written to the html output directory.\r
+\r
+CHM_FILE = ../LUFA.chm\r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can \r
+# be used to specify the location (absolute path including file name) of \r
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run \r
+# the HTML help compiler on the generated index.hhp.\r
+\r
+HHC_LOCATION = \r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag \r
+# controls if a separate .chi index file is generated (YES) or that \r
+# it should be included in the master .chm file (NO).\r
+\r
+GENERATE_CHI = NO\r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING \r
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file \r
+# content.\r
+\r
+CHM_INDEX_ENCODING = \r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag \r
+# controls whether a binary table of contents is generated (YES) or a \r
+# normal table of contents (NO) in the .chm file.\r
+\r
+BINARY_TOC = NO\r
+\r
+# The TOC_EXPAND flag can be set to YES to add extra items for group members \r
+# to the contents of the HTML help documentation and to the tree view.\r
+\r
+TOC_EXPAND = YES\r
+\r
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and \r
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated \r
+# that can be used as input for Qt's qhelpgenerator to generate a \r
+# Qt Compressed Help (.qch) of the generated HTML documentation.\r
+\r
+GENERATE_QHP = NO\r
+\r
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can \r
+# be used to specify the file name of the resulting .qch file. \r
+# The path specified is relative to the HTML output folder.\r
+\r
+QCH_FILE = \r
+\r
+# The QHP_NAMESPACE tag specifies the namespace to use when generating \r
+# Qt Help Project output. For more information please see \r
+# http://doc.trolltech.com/qthelpproject.html#namespace\r
+\r
+QHP_NAMESPACE = org.doxygen.Project\r
+\r
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating \r
+# Qt Help Project output. For more information please see \r
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders\r
+\r
+QHP_VIRTUAL_FOLDER = doc\r
+\r
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to \r
+# add. For more information please see \r
+# http://doc.trolltech.com/qthelpproject.html#custom-filters\r
+\r
+QHP_CUST_FILTER_NAME = \r
+\r
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the \r
+# custom filter to add. For more information please see \r
+# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters"> \r
+# Qt Help Project / Custom Filters</a>.\r
+\r
+QHP_CUST_FILTER_ATTRS = \r
+\r
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this \r
+# project's \r
+# filter section matches. \r
+# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes"> \r
+# Qt Help Project / Filter Attributes</a>.\r
+\r
+QHP_SECT_FILTER_ATTRS = \r
+\r
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can \r
+# be used to specify the location of Qt's qhelpgenerator. \r
+# If non-empty doxygen will try to run qhelpgenerator on the generated \r
+# .qhp file.\r
+\r
+QHG_LOCATION = \r
+\r
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files \r
+# will be generated, which together with the HTML files, form an Eclipse help \r
+# plugin. To install this plugin and make it available under the help contents \r
+# menu in Eclipse, the contents of the directory containing the HTML and XML \r
+# files needs to be copied into the plugins directory of eclipse. The name of \r
+# the directory within the plugins directory should be the same as \r
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before \r
+# the help appears.\r
+\r
+GENERATE_ECLIPSEHELP = NO\r
+\r
+# A unique identifier for the eclipse help plugin. When installing the plugin \r
+# the directory name containing the HTML and XML files should also have \r
+# this name.\r
+\r
+ECLIPSE_DOC_ID = org.doxygen.Project\r
+\r
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) \r
+# at top of each HTML page. The value NO (the default) enables the index and \r
+# the value YES disables it. Since the tabs have the same information as the \r
+# navigation tree you can set this option to NO if you already set \r
+# GENERATE_TREEVIEW to YES.\r
+\r
+DISABLE_INDEX = NO\r
+\r
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index \r
+# structure should be generated to display hierarchical information. \r
+# If the tag value is set to YES, a side panel will be generated \r
+# containing a tree-like index structure (just like the one that \r
+# is generated for HTML Help). For this to work a browser that supports \r
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). \r
+# Windows users are probably better off using the HTML help feature. \r
+# Since the tree basically has the same information as the tab index you \r
+# could consider to set DISABLE_INDEX to NO when enabling this option.\r
+\r
+GENERATE_TREEVIEW = YES\r
+\r
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values \r
+# (range [0,1..20]) that doxygen will group on one line in the generated HTML \r
+# documentation. Note that a value of 0 will completely suppress the enum \r
+# values from appearing in the overview section.\r
+\r
+ENUM_VALUES_PER_LINE = 1\r
+\r
+# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, \r
+# and Class Hierarchy pages using a tree view instead of an ordered list.\r
+\r
+USE_INLINE_TREES = YES\r
+\r
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be \r
+# used to set the initial width (in pixels) of the frame in which the tree \r
+# is shown.\r
+\r
+TREEVIEW_WIDTH = 300\r
+\r
+# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open \r
+# links to external symbols imported via tag files in a separate window.\r
+\r
+EXT_LINKS_IN_WINDOW = NO\r
+\r
+# Use this tag to change the font size of Latex formulas included \r
+# as images in the HTML documentation. The default is 10. Note that \r
+# when you change the font size after a successful doxygen run you need \r
+# to manually remove any form_*.png images from the HTML output directory \r
+# to force them to be regenerated.\r
+\r
+FORMULA_FONTSIZE = 10\r
+\r
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images \r
+# generated for formulas are transparent PNGs. Transparent PNGs are \r
+# not supported properly for IE 6.0, but are supported on all modern browsers. \r
+# Note that when changing this option you need to delete any form_*.png files \r
+# in the HTML output before the changes have effect.\r
+\r
+FORMULA_TRANSPARENT = YES\r
+\r
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax \r
+# (see http://www.mathjax.org) which uses client side Javascript for the \r
+# rendering instead of using prerendered bitmaps. Use this if you do not \r
+# have LaTeX installed or if you want to formulas look prettier in the HTML \r
+# output. When enabled you may also need to install MathJax separately and \r
+# configure the path to it using the MATHJAX_RELPATH option.\r
+\r
+USE_MATHJAX = NO\r
+\r
+# When MathJax is enabled you need to specify the location relative to the \r
+# HTML output directory using the MATHJAX_RELPATH option. The destination \r
+# directory should contain the MathJax.js script. For instance, if the mathjax \r
+# directory is located at the same level as the HTML output directory, then \r
+# MATHJAX_RELPATH should be ../mathjax. The default value points to \r
+# the MathJax Content Delivery Network so you can quickly see the result without \r
+# installing MathJax. However, it is strongly recommended to install a local \r
+# copy of MathJax from http://www.mathjax.org before deployment.\r
+\r
+MATHJAX_RELPATH = http://www.mathjax.org/mathjax\r
+\r
+# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension \r
+# names that should be enabled during MathJax rendering.\r
+\r
+MATHJAX_EXTENSIONS = \r
+\r
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box \r
+# for the HTML output. The underlying search engine uses javascript \r
+# and DHTML and should work on any modern browser. Note that when using \r
+# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets \r
+# (GENERATE_DOCSET) there is already a search function so this one should \r
+# typically be disabled. For large projects the javascript based search engine \r
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.\r
+\r
+SEARCHENGINE = YES\r
+\r
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be \r
+# implemented using a PHP enabled web server instead of at the web client \r
+# using Javascript. Doxygen will generate the search PHP script and index \r
+# file to put on the web server. The advantage of the server \r
+# based approach is that it scales better to large projects and allows \r
+# full text search. The disadvantages are that it is more difficult to setup \r
+# and does not have live searching capabilities.\r
+\r
+SERVER_BASED_SEARCH = NO\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the LaTeX output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will \r
+# generate Latex output.\r
+\r
+GENERATE_LATEX = NO\r
+\r
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `latex' will be used as the default path.\r
+\r
+LATEX_OUTPUT = latex\r
+\r
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be \r
+# invoked. If left blank `latex' will be used as the default command name. \r
+# Note that when enabling USE_PDFLATEX this option is only used for \r
+# generating bitmaps for formulas in the HTML output, but not in the \r
+# Makefile that is written to the output directory.\r
+\r
+LATEX_CMD_NAME = latex\r
+\r
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to \r
+# generate index for LaTeX. If left blank `makeindex' will be used as the \r
+# default command name.\r
+\r
+MAKEINDEX_CMD_NAME = makeindex\r
+\r
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact \r
+# LaTeX documents. This may be useful for small projects and may help to \r
+# save some trees in general.\r
+\r
+COMPACT_LATEX = NO\r
+\r
+# The PAPER_TYPE tag can be used to set the paper type that is used \r
+# by the printer. Possible values are: a4, letter, legal and \r
+# executive. If left blank a4wide will be used.\r
+\r
+PAPER_TYPE = a4wide\r
+\r
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX \r
+# packages that should be included in the LaTeX output.\r
+\r
+EXTRA_PACKAGES = \r
+\r
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for \r
+# the generated latex document. The header should contain everything until \r
+# the first chapter. If it is left blank doxygen will generate a \r
+# standard header. Notice: only use this tag if you know what you are doing!\r
+\r
+LATEX_HEADER = \r
+\r
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for \r
+# the generated latex document. The footer should contain everything after \r
+# the last chapter. If it is left blank doxygen will generate a \r
+# standard footer. Notice: only use this tag if you know what you are doing!\r
+\r
+LATEX_FOOTER = \r
+\r
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated \r
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will \r
+# contain links (just like the HTML output) instead of page references \r
+# This makes the output suitable for online browsing using a pdf viewer.\r
+\r
+PDF_HYPERLINKS = YES\r
+\r
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of \r
+# plain latex in the generated Makefile. Set this option to YES to get a \r
+# higher quality PDF documentation.\r
+\r
+USE_PDFLATEX = YES\r
+\r
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. \r
+# command to the generated LaTeX files. This will instruct LaTeX to keep \r
+# running if errors occur, instead of asking the user for help. \r
+# This option is also used when generating formulas in HTML.\r
+\r
+LATEX_BATCHMODE = NO\r
+\r
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not \r
+# include the index chapters (such as File Index, Compound Index, etc.) \r
+# in the output.\r
+\r
+LATEX_HIDE_INDICES = NO\r
+\r
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include \r
+# source code with syntax highlighting in the LaTeX output. \r
+# Note that which sources are shown also depends on other settings \r
+# such as SOURCE_BROWSER.\r
+\r
+LATEX_SOURCE_CODE = NO\r
+\r
+# The LATEX_BIB_STYLE tag can be used to specify the style to use for the \r
+# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See \r
+# http://en.wikipedia.org/wiki/BibTeX for more info.\r
+\r
+LATEX_BIB_STYLE = plain\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the RTF output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output \r
+# The RTF output is optimized for Word 97 and may not look very pretty with \r
+# other RTF readers or editors.\r
+\r
+GENERATE_RTF = NO\r
+\r
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `rtf' will be used as the default path.\r
+\r
+RTF_OUTPUT = rtf\r
+\r
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact \r
+# RTF documents. This may be useful for small projects and may help to \r
+# save some trees in general.\r
+\r
+COMPACT_RTF = NO\r
+\r
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated \r
+# will contain hyperlink fields. The RTF file will \r
+# contain links (just like the HTML output) instead of page references. \r
+# This makes the output suitable for online browsing using WORD or other \r
+# programs which support those fields. \r
+# Note: wordpad (write) and others do not support links.\r
+\r
+RTF_HYPERLINKS = NO\r
+\r
+# Load style sheet definitions from file. Syntax is similar to doxygen's \r
+# config file, i.e. a series of assignments. You only have to provide \r
+# replacements, missing definitions are set to their default value.\r
+\r
+RTF_STYLESHEET_FILE = \r
+\r
+# Set optional variables used in the generation of an rtf document. \r
+# Syntax is similar to doxygen's config file.\r
+\r
+RTF_EXTENSIONS_FILE = \r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the man page output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will \r
+# generate man pages\r
+\r
+GENERATE_MAN = NO\r
+\r
+# The MAN_OUTPUT tag is used to specify where the man pages will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `man' will be used as the default path.\r
+\r
+MAN_OUTPUT = man\r
+\r
+# The MAN_EXTENSION tag determines the extension that is added to \r
+# the generated man pages (default is the subroutine's section .3)\r
+\r
+MAN_EXTENSION = .3\r
+\r
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output, \r
+# then it will generate one additional man file for each entity \r
+# documented in the real man page(s). These additional files \r
+# only source the real man page, but without them the man command \r
+# would be unable to find the correct page. The default is NO.\r
+\r
+MAN_LINKS = NO\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the XML output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_XML tag is set to YES Doxygen will \r
+# generate an XML file that captures the structure of \r
+# the code including all documentation.\r
+\r
+GENERATE_XML = NO\r
+\r
+# The XML_OUTPUT tag is used to specify where the XML pages will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `xml' will be used as the default path.\r
+\r
+XML_OUTPUT = xml\r
+\r
+# The XML_SCHEMA tag can be used to specify an XML schema, \r
+# which can be used by a validating XML parser to check the \r
+# syntax of the XML files.\r
+\r
+XML_SCHEMA = \r
+\r
+# The XML_DTD tag can be used to specify an XML DTD, \r
+# which can be used by a validating XML parser to check the \r
+# syntax of the XML files.\r
+\r
+XML_DTD = \r
+\r
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will \r
+# dump the program listings (including syntax highlighting \r
+# and cross-referencing information) to the XML output. Note that \r
+# enabling this will significantly increase the size of the XML output.\r
+\r
+XML_PROGRAMLISTING = YES\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options for the AutoGen Definitions output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will \r
+# generate an AutoGen Definitions (see autogen.sf.net) file \r
+# that captures the structure of the code including all \r
+# documentation. Note that this feature is still experimental \r
+# and incomplete at the moment.\r
+\r
+GENERATE_AUTOGEN_DEF = NO\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the Perl module output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will \r
+# generate a Perl module file that captures the structure of \r
+# the code including all documentation. Note that this \r
+# feature is still experimental and incomplete at the \r
+# moment.\r
+\r
+GENERATE_PERLMOD = NO\r
+\r
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate \r
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able \r
+# to generate PDF and DVI output from the Perl module output.\r
+\r
+PERLMOD_LATEX = NO\r
+\r
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be \r
+# nicely formatted so it can be parsed by a human reader. This is useful \r
+# if you want to understand what is going on. On the other hand, if this \r
+# tag is set to NO the size of the Perl module output will be much smaller \r
+# and Perl will parse it just the same.\r
+\r
+PERLMOD_PRETTY = YES\r
+\r
+# The names of the make variables in the generated doxyrules.make file \r
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. \r
+# This is useful so different doxyrules.make files included by the same \r
+# Makefile don't overwrite each other's variables.\r
+\r
+PERLMOD_MAKEVAR_PREFIX = \r
+\r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the preprocessor\r
+#---------------------------------------------------------------------------\r
+\r
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will \r
+# evaluate all C-preprocessor directives found in the sources and include \r
+# files.\r
+\r
+ENABLE_PREPROCESSING = YES\r
+\r
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro \r
+# names in the source code. If set to NO (the default) only conditional \r
+# compilation will be performed. Macro expansion can be done in a controlled \r
+# way by setting EXPAND_ONLY_PREDEF to YES.\r
+\r
+MACRO_EXPANSION = YES\r
+\r
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES \r
+# then the macro expansion is limited to the macros specified with the \r
+# PREDEFINED and EXPAND_AS_DEFINED tags.\r
+\r
+EXPAND_ONLY_PREDEF = YES\r
+\r
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files \r
+# pointed to by INCLUDE_PATH will be searched when a #include is found.\r
+\r
+SEARCH_INCLUDES = YES\r
+\r
+# The INCLUDE_PATH tag can be used to specify one or more directories that \r
+# contain include files that are not input files but should be processed by \r
+# the preprocessor.\r
+\r
+INCLUDE_PATH = \r
+\r
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard \r
+# patterns (like *.h and *.hpp) to filter out the header-files in the \r
+# directories. If left blank, the patterns specified with FILE_PATTERNS will \r
+# be used.\r
+\r
+INCLUDE_FILE_PATTERNS = \r
+\r
+# The PREDEFINED tag can be used to specify one or more macro names that \r
+# are defined before the preprocessor is started (similar to the -D option of \r
+# gcc). The argument of the tag is a list of macros of the form: name \r
+# or name=definition (no spaces). If the definition and the = are \r
+# omitted =1 is assumed. To prevent a macro definition from being \r
+# undefined via #undef or recursively expanded use the := operator \r
+# instead of the = operator.\r
+\r
+PREDEFINED = __DOXYGEN__ \\r
+ PROGMEM \\r
+ EEMEM \\r
+ ATTR_PACKED\r
+\r
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then \r
+# this tag can be used to specify a list of macro names that should be expanded. \r
+# The macro definition that is found in the sources will be used. \r
+# Use the PREDEFINED tag if you want to use a different macro definition that \r
+# overrules the definition found in the source code.\r
+\r
+EXPAND_AS_DEFINED = \r
+\r
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then \r
+# doxygen's preprocessor will remove all references to function-like macros \r
+# that are alone on a line, have an all uppercase name, and do not end with a \r
+# semicolon, because these will confuse the parser if not removed.\r
+\r
+SKIP_FUNCTION_MACROS = YES\r
+\r
+#---------------------------------------------------------------------------\r
+# Configuration::additions related to external references\r
+#---------------------------------------------------------------------------\r
+\r
+# The TAGFILES option can be used to specify one or more tagfiles. For each \r
+# tag file the location of the external documentation should be added. The \r
+# format of a tag file without this location is as follows: \r
+# TAGFILES = file1 file2 ... \r
+# Adding location for the tag files is done as follows: \r
+# TAGFILES = file1=loc1 "file2 = loc2" ... \r
+# where "loc1" and "loc2" can be relative or absolute paths \r
+# or URLs. Note that each tag file must have a unique name (where the name does \r
+# NOT include the path). If a tag file is not located in the directory in which \r
+# doxygen is run, you must also specify the path to the tagfile here.\r
+\r
+TAGFILES = \r
+\r
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create \r
+# a tag file that is based on the input files it reads.\r
+\r
+GENERATE_TAGFILE = Documentation/LPCUSBlib.tag\r
+\r
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed \r
+# in the class index. If set to NO only the inherited external classes \r
+# will be listed.\r
+\r
+ALLEXTERNALS = NO\r
+\r
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed \r
+# in the modules index. If set to NO, only the current project's groups will \r
+# be listed.\r
+\r
+EXTERNAL_GROUPS = NO\r
+\r
+# The PERL_PATH should be the absolute path and name of the perl script \r
+# interpreter (i.e. the result of `which perl').\r
+\r
+PERL_PATH = /usr/bin/perl\r
+\r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the dot tool\r
+#---------------------------------------------------------------------------\r
+\r
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will \r
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base \r
+# or super classes. Setting the tag to NO turns the diagrams off. Note that \r
+# this option also works with HAVE_DOT disabled, but it is recommended to \r
+# install and use dot, since it yields more powerful graphs.\r
+\r
+CLASS_DIAGRAMS = NO\r
+\r
+# You can define message sequence charts within doxygen comments using the \msc \r
+# command. Doxygen will then run the mscgen tool (see \r
+# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the \r
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where \r
+# the mscgen tool resides. If left empty the tool is assumed to be found in the \r
+# default search path.\r
+\r
+MSCGEN_PATH = \r
+\r
+# If set to YES, the inheritance and collaboration graphs will hide \r
+# inheritance and usage relations if the target is undocumented \r
+# or is not a class.\r
+\r
+HIDE_UNDOC_RELATIONS = YES\r
+\r
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is \r
+# available from the path. This tool is part of Graphviz, a graph visualization \r
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section \r
+# have no effect if this option is set to NO (the default)\r
+\r
+HAVE_DOT = NO\r
+\r
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is \r
+# allowed to run in parallel. When set to 0 (the default) doxygen will \r
+# base this on the number of processors available in the system. You can set it \r
+# explicitly to a value larger than 0 to get control over the balance \r
+# between CPU load and processing speed.\r
+\r
+DOT_NUM_THREADS = 0\r
+\r
+# By default doxygen will use the Helvetica font for all dot files that \r
+# doxygen generates. When you want a differently looking font you can specify \r
+# the font name using DOT_FONTNAME. You need to make sure dot is able to find \r
+# the font, which can be done by putting it in a standard location or by setting \r
+# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the \r
+# directory containing the font.\r
+\r
+DOT_FONTNAME = FreeSans\r
+\r
+# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. \r
+# The default size is 10pt.\r
+\r
+DOT_FONTSIZE = 10\r
+\r
+# By default doxygen will tell dot to use the Helvetica font. \r
+# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to \r
+# set the path where dot can find it.\r
+\r
+DOT_FONTPATH = \r
+\r
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen \r
+# will generate a graph for each documented class showing the direct and \r
+# indirect inheritance relations. Setting this tag to YES will force the \r
+# CLASS_DIAGRAMS tag to NO.\r
+\r
+CLASS_GRAPH = NO\r
+\r
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen \r
+# will generate a graph for each documented class showing the direct and \r
+# indirect implementation dependencies (inheritance, containment, and \r
+# class references variables) of the class with other documented classes.\r
+\r
+COLLABORATION_GRAPH = NO\r
+\r
+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen \r
+# will generate a graph for groups, showing the direct groups dependencies\r
+\r
+GROUP_GRAPHS = YES\r
+\r
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and \r
+# collaboration diagrams in a style similar to the OMG's Unified Modeling \r
+# Language.\r
+\r
+UML_LOOK = NO\r
+\r
+# If the UML_LOOK tag is enabled, the fields and methods are shown inside \r
+# the class node. If there are many fields or methods and many nodes the \r
+# graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS \r
+# threshold limits the number of items for each type to make the size more \r
+# managable. Set this to 0 for no limit. Note that the threshold may be \r
+# exceeded by 50% before the limit is enforced.\r
+\r
+UML_LIMIT_NUM_FIELDS = 10\r
+\r
+# If set to YES, the inheritance and collaboration graphs will show the \r
+# relations between templates and their instances.\r
+\r
+TEMPLATE_RELATIONS = NO\r
+\r
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT \r
+# tags are set to YES then doxygen will generate a graph for each documented \r
+# file showing the direct and indirect include dependencies of the file with \r
+# other documented files.\r
+\r
+INCLUDE_GRAPH = YES\r
+\r
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and \r
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each \r
+# documented header file showing the documented files that directly or \r
+# indirectly include this file.\r
+\r
+INCLUDED_BY_GRAPH = YES\r
+\r
+# If the CALL_GRAPH and HAVE_DOT options are set to YES then \r
+# doxygen will generate a call dependency graph for every global function \r
+# or class method. Note that enabling this option will significantly increase \r
+# the time of a run. So in most cases it will be better to enable call graphs \r
+# for selected functions only using the \callgraph command.\r
+\r
+CALL_GRAPH = NO\r
+\r
+# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then \r
+# doxygen will generate a caller dependency graph for every global function \r
+# or class method. Note that enabling this option will significantly increase \r
+# the time of a run. So in most cases it will be better to enable caller \r
+# graphs for selected functions only using the \callergraph command.\r
+\r
+CALLER_GRAPH = NO\r
+\r
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen \r
+# will generate a graphical hierarchy of all classes instead of a textual one.\r
+\r
+GRAPHICAL_HIERARCHY = NO\r
+\r
+# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES \r
+# then doxygen will show the dependencies a directory has on other directories \r
+# in a graphical way. The dependency relations are determined by the #include \r
+# relations between the files in the directories.\r
+\r
+DIRECTORY_GRAPH = YES\r
+\r
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images \r
+# generated by dot. Possible values are svg, png, jpg, or gif. \r
+# If left blank png will be used. If you choose svg you need to set \r
+# HTML_FILE_EXTENSION to xhtml in order to make the SVG files \r
+# visible in IE 9+ (other browsers do not have this requirement).\r
+\r
+DOT_IMAGE_FORMAT = png\r
+\r
+# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to \r
+# enable generation of interactive SVG images that allow zooming and panning. \r
+# Note that this requires a modern browser other than Internet Explorer. \r
+# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you \r
+# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files \r
+# visible. Older versions of IE do not have SVG support.\r
+\r
+INTERACTIVE_SVG = NO\r
+\r
+# The tag DOT_PATH can be used to specify the path where the dot tool can be \r
+# found. If left blank, it is assumed the dot tool can be found in the path.\r
+\r
+DOT_PATH = \r
+\r
+# The DOTFILE_DIRS tag can be used to specify one or more directories that \r
+# contain dot files that are included in the documentation (see the \r
+# \dotfile command).\r
+\r
+DOTFILE_DIRS = \r
+\r
+# The MSCFILE_DIRS tag can be used to specify one or more directories that \r
+# contain msc files that are included in the documentation (see the \r
+# \mscfile command).\r
+\r
+MSCFILE_DIRS = \r
+\r
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of \r
+# nodes that will be shown in the graph. If the number of nodes in a graph \r
+# becomes larger than this value, doxygen will truncate the graph, which is \r
+# visualized by representing a node as a red box. Note that doxygen if the \r
+# number of direct children of the root node in a graph is already larger than \r
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note \r
+# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.\r
+\r
+DOT_GRAPH_MAX_NODES = 15\r
+\r
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the \r
+# graphs generated by dot. A depth value of 3 means that only nodes reachable \r
+# from the root by following a path via at most 3 edges will be shown. Nodes \r
+# that lay further from the root node will be omitted. Note that setting this \r
+# option to 1 or 2 may greatly reduce the computation time needed for large \r
+# code bases. Also note that the size of a graph can be further restricted by \r
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.\r
+\r
+MAX_DOT_GRAPH_DEPTH = 2\r
+\r
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent \r
+# background. This is disabled by default, because dot on Windows does not \r
+# seem to support this out of the box. Warning: Depending on the platform used, \r
+# enabling this option may lead to badly anti-aliased labels on the edges of \r
+# a graph (i.e. they become hard to read).\r
+\r
+DOT_TRANSPARENT = YES\r
+\r
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output \r
+# files in one run (i.e. multiple -o and -T options on the command line). This \r
+# makes dot run faster, but since only newer versions of dot (>1.8.10) \r
+# support this, this feature is disabled by default.\r
+\r
+DOT_MULTI_TARGETS = NO\r
+\r
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will \r
+# generate a legend page explaining the meaning of the various boxes and \r
+# arrows in the dot generated graphs.\r
+\r
+GENERATE_LEGEND = YES\r
+\r
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will \r
+# remove the intermediate dot files that are used to generate \r
+# the various graphs.\r
+\r
+DOT_CLEANUP = YES\r
--- /dev/null
+/** \file\r
+*\r
+* This file contains special DoxyGen information for the generation of the main page and other special\r
+* documentation pages. It is not a project source file.\r
+*/\r
+\r
+/**\r
+* \mainpage\r
+*\r
+*\r
+<b>\r
+<p>LPCUSBlib is a full featured, open-source USB library designed\r
+to run on all USB capable LPC microcontrollers from NXP.</p>\r
+</b>\r
+<p>The library includes support for</p>\r
+<ul>\r
+<li>USB 2.0</li>\r
+<li>Host and device modes</li>\r
+<li>Low, full and high speed transfer rates</li>\r
+<li>Control, bulk, interrupt, and isochronous transfer types</li>\r
+</ul>\r
+<p> </p>\r
+<div style="text-align: center;"><a\r
+href="http://www.lpcware.com/content/project/LPCUSBlib/get-it">Visit\r
+http://www.lpcware.com/content/project/LPCUSBlib to get the\r
+latest version of LPCUSBlib</a></div>\r
+<p> </p>\r
+ *\r
+ */\r
+\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r
+<html>\r
+ <head>\r
+\r
+ <meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">\r
+ </head>\r
+ <body>\r
+ <div style="text-align: center; color: rgb(255, 102, 0);">LPCUSBlib\r
+ – USB software for your LPC world<br>\r
+ </div>\r
+ </body>\r
+</html>\r
--- /dev/null
+/*\r
+ * @brief LPCUSB library version constants\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+/** @defgroup USB_Version Version of LPC USB library\r
+ * @ingroup LPCUSBlib\r
+ * @{\r
+ */\r
+#ifndef __LPCUSBlib_VERSION_H__\r
+#define __LPCUSBlib_VERSION_H__\r
+\r
+ #define LPCUSBlib_VERSION_INTEGER 0x000000\r
+\r
+ #define LPCUSBlib_VERSION_STRING "XXXXXX"\r
+\r
+#endif\r
+/**\r
+* @}\r
+*/\r
+\r
--- /dev/null
+/*\r
+ * @brief Common board API functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __BOARD_API_H_\r
+#define __BOARD_API_H_\r
+\r
+#include "lpc_types.h"\r
+#include <stdio.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup BOARD_COMMON_API BOARD: Common board functions\r
+ * @ingroup BOARD_Common\r
+ * This file contains common board definitions that are shared across\r
+ * boards and devices. All of these functions do not need to be\r
+ * impemented for a specific board, but if they are implemented, they\r
+ * should use this API standard.\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set up and initialize all required blocks and functions related to the board hardware.\r
+ * @return None\r
+ */\r
+void Board_Init(void);\r
+\r
+/**\r
+ * @brief Initializes board UART for output, required for printf redirection\r
+ * @return None\r
+ */\r
+void Board_Debug_Init(void);\r
+\r
+/**\r
+ * @brief Sends a single character on the UART, required for printf redirection\r
+ * @param ch : character to send\r
+ * @return None\r
+ */\r
+void Board_UARTPutChar(char ch);\r
+\r
+/**\r
+ * @brief Get a single character from the UART, required for scanf input\r
+ * @return EOF if not character was received, or character value\r
+ */\r
+int Board_UARTGetChar(void);\r
+\r
+/**\r
+ * @brief Prints a string to the UART\r
+ * @param str : Terminated string to output\r
+ * @return None\r
+ */\r
+void Board_UARTPutSTR(char *str);\r
+\r
+/**\r
+ * @brief Sets the state of a board LED to on or off\r
+ * @param LEDNumber : LED number to set state for\r
+ * @param State : true for on, false for off\r
+ * @return None\r
+ */\r
+void Board_LED_Set(uint8_t LEDNumber, bool State);\r
+\r
+/**\r
+ * @brief Returns the current state of a board LED\r
+ * @param LEDNumber : LED number to set state for\r
+ * @return true if the LED is on, otherwise false\r
+ */\r
+bool Board_LED_Test(uint8_t LEDNumber);\r
+\r
+/**\r
+ * @brief Toggles the current state of a board LED\r
+ * @param LEDNumber : LED number to change state for\r
+ * @return None\r
+ */\r
+STATIC INLINE void Board_LED_Toggle(uint8_t LEDNumber)\r
+{\r
+ Board_LED_Set(LEDNumber, !Board_LED_Test(LEDNumber));\r
+}\r
+\r
+/**\r
+ * @brief Current system clock rate, mainly used for sysTick\r
+ */\r
+extern uint32_t SystemCoreClock;\r
+\r
+/**\r
+ * @brief Update system core clock rate, should be called if the\r
+ * system has a clock rate change\r
+ * @return None\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
+/**\r
+ * @brief Turn on Board LCD Backlight\r
+ * @param Intensity : Backlight intensity (0 = off, >=1 = on)\r
+ * @return None\r
+ * @note On boards where a GPIO is used to control backlight on/off state, a '0' or '1'\r
+ * value will turn off or on the backlight. On some boards, a non-0 value will\r
+ * control backlight intensity via a PWN. For PWM systems, the intensity value\r
+ * is a percentage value between 0 and 100%.\r
+ */\r
+void Board_SetLCDBacklight(uint8_t Intensity);\r
+\r
+/**\r
+ * @brief Function prototype for a MS delay function. Board layers or example code may\r
+ * define this function as needed.\r
+ */\r
+typedef void (*p_msDelay_func_t)(uint32_t);\r
+\r
+/* The DEBUG* functions are selected based on system configuration.\r
+ Code that uses the DEBUG* functions will have their I/O routed to\r
+ the UART, semihosting, or nowhere. */\r
+#if defined(DEBUG_ENABLE)\r
+#if defined(DEBUG_SEMIHOSTING)\r
+#define DEBUGINIT()\r
+#define DEBUGOUT(...) printf(__VA_ARGS__)\r
+#define DEBUGSTR(str) printf(str)\r
+#define DEBUGIN() (int) EOF\r
+\r
+#else\r
+#define DEBUGINIT() Board_Debug_Init()\r
+#define DEBUGOUT(...) printf(__VA_ARGS__)\r
+#define DEBUGSTR(str) Board_UARTPutSTR(str)\r
+#define DEBUGIN() Board_UARTGetChar()\r
+#endif /* defined(DEBUG_SEMIHOSTING) */\r
+\r
+#else\r
+#define DEBUGINIT()\r
+#define DEBUGOUT(...)\r
+#define DEBUGSTR(str)\r
+#define DEBUGIN() (int) EOF\r
+#endif /* defined(DEBUG_ENABLE) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __BOARD_API_H_ */\r
--- /dev/null
+/*\r
+ * @brief Common PHY functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __LPC_PHY_H_\r
+#define __LPC_PHY_H_\r
+\r
+#include "board.h"\r
+#include "chip.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup BOARD_PHY BOARD: Board specific PHY drivers\r
+ * @ingroup BOARD_Common\r
+ * The simple PHY function API provides simple non-blocking PHY status\r
+ * monitoring and initialization support for various Ethernet PHYs.\r
+ * To initialize the PHY, call lpc_phy_init() once. lpc_phy_init() requires\r
+ * several standard functions from the MAC driver for interfacing to the\r
+ * PHY via a MII link (Chip_ENET_StartMIIWrite(), Chip_ENET_IsMIIBusy(),\r
+ * Chip_ENET_StartMIIRead(), and Chip_ENET_ReadMIIData()).\r
+ *\r
+ * Once initialized, just preiodically call the lpcPHYStsPoll() function\r
+ * from the background loop or a thread and monitor the returned status\r
+ * to determine if the PHY state has changed and the current PHY state.\r
+ * @{\r
+ */\r
+#define PHY_LINK_ERROR (1 << 0) /*!< PHY status bit for link error */\r
+#define PHY_LINK_BUSY (1 << 1) /*!< PHY status bit for MII link busy */\r
+#define PHY_LINK_CHANGED (1 << 2) /*!< PHY status bit for changed state (not persistent) */\r
+#define PHY_LINK_CONNECTED (1 << 3) /*!< PHY status bit for connected state */\r
+#define PHY_LINK_SPEED100 (1 << 4) /*!< PHY status bit for 100Mbps mode */\r
+#define PHY_LINK_FULLDUPLX (1 << 5) /*!< PHY status bit for full duplex mode */\r
+\r
+/**\r
+ * @brief Phy status update state machine\r
+ * @return An Or'ed value of PHY_LINK_* statuses\r
+ * @note This function can be called at any rate and will poll the the PHY status. Multiple\r
+ * calls may be needed to determine PHY status.\r
+ */\r
+uint32_t lpcPHYStsPoll(void);\r
+\r
+/**\r
+ * @brief Initialize the PHY\r
+ * @param rmii : Initializes PHY for RMII mode if true, MII if false\r
+ * @param pDelayMsFunc : Delay function (in mS) used for this driver\r
+ * @return PHY_LINK_ERROR or 0 on success\r
+ * @note This function initializes the PHY. It will block until complete. It will not\r
+ * wait for the PHY to detect a connected cable and remain busy. Use lpcPHYStsPoll to\r
+ * detect cable insertion.\r
+ */\r
+uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __LPC_PHY_H_ */\r
--- /dev/null
+/*\r
+ * @brief UDA1380 Audio Codec header\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __UDA1380_H_\r
+#define __UDA1380_H_\r
+\r
+/** @defgroup BOARD_COMMON_UDA1380 BOARD: UDA1380 Audio codec interface module\r
+ * UDA1380 Audio codec interface module, the module registers are accessed\r
+ * using I2C. The board which uses this module must define #UDA1380_I2C_BUS to #I2C0\r
+ * , #I2C1, etc, based on which I2C bus is connected to UDA1380. All the\r
+ * functions in this modules assumes that the I2C interrupt for #UDA1380_I2C_BUS\r
+ * is enabled and ::Chip_I2C_MasterStateHandler(#UDA1380_I2C_BUS) is called from the\r
+ * ISR. If the functions are to be used in polling mode the caller must replace\r
+ * the event handler to Chip_I2C_EventHandlerPolling(), by using API\r
+ * Chip_I2C_SetMasterEventHandler(). A macro #I2CDEV_UDA1380_ADDR must be defined\r
+ * to the appropriate slave address of UDA1380 audio codec.\r
+ * @ingroup BOARD_Common\r
+ * @{\r
+ */\r
+\r
+/* UDA1380 Registers */\r
+#define UDA_EVALM_CLK 0x00\r
+#define UDA_BUS_CTRL 0x01\r
+#define UDA_POWER_CTRL 0x02\r
+#define UDA_ANALOG_CTRL 0x03\r
+#define UDA_HPAMP_CTRL 0x04\r
+#define UDA_MASTER_VOL_CTRL 0x10\r
+#define UDA_MIXER_VOL_CTRL 0x11\r
+#define UDA_MODE_CTRL 0x12\r
+#define UDA_MUTE_CTRL 0x13\r
+#define UDA_MIXER_FILTER_CTRL 0x14\r
+#define UDA_DEC_VOL_CTRL 0x20\r
+#define UDA_PGA_CTRL 0x21\r
+#define UDA_ADC_CTRL 0x22\r
+#define UDA_AGC_CTRL 0x23\r
+#define UDA_TOTAL_REG 0x24\r
+\r
+/** Evalutation mode and clock setting register bits */\r
+#define EVCLK_EV2 (1 << 15)\r
+#define EVCLK_EV1 (1 << 14)\r
+#define EVCLK_EV0 (1 << 13)\r
+#define EVCLK_EN_ADC (1 << 11)\r
+#define EVCLK_EN_DEC (1 << 10)\r
+#define EVCLK_EN_DAC (1 << 9)\r
+#define EVCLK_EN_INT (1 << 8)\r
+#define EVCLK_ADC_CLK (1 << 5)\r
+#define EVCLK_DAC_CLK (1 << 4)\r
+#define EVCLK_SYS_DIV1 (1 << 3)\r
+#define EVCLK_SYS_DIV0 (1 << 2)\r
+#define EVCLK_PLL1 (1 << 1)\r
+#define EVCLK_PLL0 (1 << 0)\r
+\r
+/** UDA1380 register default values */\r
+#define UDA1380_REG_EVALCLK_DEFAULT_VALUE (0xF << 8 | 0x3 << 4 | 1 << 1)\r
+#define UDA1380_REG_I2S_DEFAULT_VALUE 0x0000\r
+\r
+#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F)\r
+#define UDA1380_REG_ANAMIX_DEFAULT_VALUE 0x0000\r
+#define UDA1380_REG_HEADAMP_DEFAULT_VALUE ( 1 << 9 | 2)\r
+\r
+#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE 0x0000\r
+#define UDA1380_REG_MIXVOL_DEFAULT_VALUE 0x0000\r
+#define UDA1380_REG_MODEBBT_DEFAULT_VALUE 0x0000\r
+#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE (2 << 8 | 2)\r
+#define UDA1380_REG_MIXSDO_DEFAULT_VALUE 0x0000\r
+\r
+#define UDA1380_REG_DECVOL_DEFAULT_VALUE 0xE4E4 /* Decrease Volume -28dB */\r
+#define UDA1380_REG_PGA_DEFAULT_VALUE 0x0000\r
+#define UDA1380_REG_ADC_DEFAULT_VALUE 0x0001 /* Apply 0bB VGA Gain, enable DC Filter */\r
+#define UDA1380_REG_AGC_DEFAULT_VALUE 0x0000\r
+\r
+#define UDA1380_REG_L3_DEFAULT_VALUE 0x0000\r
+\r
+/* UDA1380 Audio input selection */\r
+#define UDA1380_LINE_IN 0 /**< LINE_IN_L in left stream, LINE_IN_R in Right stream */\r
+#define UDA1380_MIC_IN_L (1 << 2) /**< MIC audio in Left stream, Line_IN_R in Right stream */\r
+#define UDA1380_MIC_IN_LR (3 << 2) /**< MIC audio in Left & Right stream */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * @def UDA1380_U8(val)\r
+ * Convert a 16 bit register value to 2 x 8 bit values that could be written\r
+ * to the I2C bus in an efficient way.\r
+ */\r
+#define UDA1380_U8(val) (((val) >> 8) & 0xFF), ((val) & 0xFF)\r
+\r
+/**\r
+ * @brief Write a 16-bit value to UDA Register\r
+ * @param reg : Register to which @a val be written\r
+ * @param val : 16-Bit value to be written\r
+ * @return Nothing\r
+ */\r
+void UDA1380_REG_Write(uint8_t reg, uint16_t val);\r
+\r
+/**\r
+ * @brief Read a 16-bit value from UDA1380 codec register\r
+ * @param reg : Register from which the value to be read\r
+ * @return Returns the value read from the register\r
+ */\r
+uint16_t UDA1380_REG_Read(uint8_t reg);\r
+\r
+/**\r
+ * @brief Writes a value to a UDA register, read back and verify the value\r
+ * @param reg : Register to which the value be written\r
+ * @param val : Value to be written\r
+ * @return 1 On success, 0 on failure\r
+ */\r
+int UDA1380_REG_WriteVerify(uint8_t reg, uint16_t val);\r
+\r
+/**\r
+ * @brief Write multiple value to UDA1380 registers\r
+ * @param buff : Pointer to buffer (See note section)\r
+ * @param len : Number of bytes in buff\r
+ * @return 1 on Success, 0 on failure\r
+ * @note buff[0] must be the address of the register to which\r
+ * the first data i.e, buff[1], buff[2] be written, the next bytes\r
+ * buff[3], buff[4] be written to register buff[0]+1 and so on.\r
+ */\r
+int UDA1380_REG_WriteMult(const uint8_t *buff, int len);\r
+\r
+/**\r
+ * @brief Verify values in multiple UDA1380 registers\r
+ * @param reg : Starting register from which data be read\r
+ * @param value : Pointer to memory which contains values to be compared\r
+ * @param buff : Pointer to memory to which data be read\r
+ * @param len : Length of bytes in value @a buff\r
+ * @return 1 on Success & Data is valid, 0 on Failure\r
+ */\r
+int UDA1380_REG_VerifyMult(uint8_t reg, const uint8_t *value, uint8_t *buff, int len);\r
+\r
+/**\r
+ * @brief Initialize UDA1380 to its default state\r
+ * @param input : Audio input source (Must be one of #UDA1380_LINE_IN\r
+ * or #UDA1380_MIC_IN_L or #UDA1380_MIC_IN_LR)\r
+ * @return 1 on Success and 0 on failure\r
+ */\r
+int UDA1380_Init(int input);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __UDA1380_H_ */\r
--- /dev/null
+/*\r
+ * @brief NGX Xplorer 1830/4330 board file\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __BOARD_H_\r
+#define __BOARD_H_\r
+\r
+#include "board_ngx_xplorer_18304330.h"\r
+\r
+#endif /* __BOARD_H_ */\r
--- /dev/null
+/*\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "board.h"\r
+#include "string.h"\r
+\r
+//#include "lpc_phy_smsc87x0.c"\r
+//#include "retarget.c"\r
+\r
+/** @ingroup BOARD_NGX_XPLORER_18304330\r
+ * @{\r
+ */\r
+\r
+void Board_UART_Init(LPC_USART_T *pUART)\r
+{\r
+ if (pUART == LPC_USART0) {\r
+ Chip_SCU_PinMuxSet(0x6, 4, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC2)); /* P6.5 : UART0_TXD */\r
+ Chip_SCU_PinMuxSet(0x6, 5, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2));/* P6.4 : UART0_RXD */\r
+ }\r
+ else if (pUART == LPC_UART1) {\r
+ Chip_SCU_PinMuxSet(0x1, 13, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC2)); /* P1.13 : UART1_TXD */\r
+ Chip_SCU_PinMuxSet(0x1, 14, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)); /* P1.14 : UART1_RX */\r
+ }\r
+}\r
+\r
+/* Initialize debug output via UART for board */\r
+void Board_Debug_Init(void)\r
+{\r
+#if defined(DEBUG_UART)\r
+ Board_UART_Init(DEBUG_UART);\r
+\r
+ Chip_UART_Init(DEBUG_UART);\r
+ Chip_UART_SetBaud(DEBUG_UART, 115200);\r
+ Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1);\r
+\r
+ /* Enable UART Transmit */\r
+ Chip_UART_TxCmd(DEBUG_UART, ENABLE);\r
+#endif\r
+}\r
+\r
+/* Sends a character on the UART */\r
+void Board_UARTPutChar(char ch)\r
+{\r
+#if defined(DEBUG_UART)\r
+ while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {}\r
+#endif\r
+}\r
+\r
+/* Gets a character from the UART, returns EOF if no character is ready */\r
+int Board_UARTGetChar(void)\r
+{\r
+#if defined(DEBUG_UART)\r
+ uint8_t data;\r
+\r
+ if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) {\r
+ return (int) data;\r
+ }\r
+#endif\r
+ return EOF;\r
+}\r
+\r
+/* Outputs a string on the debug UART */\r
+void Board_UARTPutSTR(char *str)\r
+{\r
+#if defined(DEBUG_UART)\r
+ while (*str != '\0') {\r
+ Board_UARTPutChar(*str++);\r
+ }\r
+#endif\r
+}\r
+\r
+static void Board_LED_Init()\r
+{\r
+ /* P2.12 : LED D2 as output */\r
+ Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 1, 12, true);\r
+\r
+ /* P2.11 : LED D3 as output */\r
+ Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 1, 11, true);\r
+\r
+ /* Set initial states to off (true to disable) */\r
+ Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 1, 12, (bool) true);\r
+ Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 1, 11, (bool) true);\r
+}\r
+\r
+void Board_LED_Set(uint8_t LEDNumber, bool On)\r
+{\r
+ if (LEDNumber == 0) {\r
+ Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 1, 12, (bool) !On);\r
+ }\r
+ else if (LEDNumber == 1) {\r
+ Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 1, 11, (bool) !On);\r
+ }\r
+}\r
+\r
+bool Board_LED_Test(uint8_t LEDNumber)\r
+{\r
+ if (LEDNumber == 0) {\r
+ return (bool) !Chip_GPIO_ReadPortBit(LPC_GPIO_PORT, 1, 12);\r
+ }\r
+ else if (LEDNumber == 1) {\r
+ return (bool) !Chip_GPIO_ReadPortBit(LPC_GPIO_PORT, 1, 11);\r
+ }\r
+\r
+ return false;\r
+}\r
+\r
+void Board_Buttons_Init(void) // FIXME not functional ATM\r
+{\r
+ Chip_SCU_PinMuxSet(0x2, 7, (SCU_MODE_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)); // P2_7 as GPIO0[7]\r
+ Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, BUTTONS_BUTTON1_GPIO_PORT_NUM, (1 << BUTTONS_BUTTON1_GPIO_BIT_NUM), false); // input\r
+}\r
+\r
+uint32_t Buttons_GetStatus(void)\r
+{\r
+ uint8_t ret = NO_BUTTON_PRESSED;\r
+ if (Chip_GPIO_ReadPortBit(LPC_GPIO_PORT, BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) {\r
+ ret |= BUTTONS_BUTTON1;\r
+ }\r
+ return ret;\r
+}\r
+\r
+void Board_Joystick_Init(void)\r
+{}\r
+\r
+uint8_t Joystick_GetStatus(void)\r
+{\r
+ return NO_BUTTON_PRESSED;\r
+}\r
+\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+/* Update system core clock rate, should be called if the system has\r
+ a clock rate change */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ /* CPU core speed */\r
+ SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);\r
+}\r
+\r
+/* Returns the MAC address assigned to this board */\r
+void Board_ENET_GetMacADDR(uint8_t *mcaddr)\r
+{\r
+ uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56};\r
+\r
+ memcpy(mcaddr, boardmac, 6);\r
+}\r
+\r
+/* Set up and initialize all required blocks and functions related to the\r
+ board hardware */\r
+void Board_Init(void)\r
+{\r
+ /* Sets up DEBUG UART */\r
+ DEBUGINIT();\r
+\r
+ /* Updates SystemCoreClock global var with current clock speed */\r
+ SystemCoreClockUpdate();\r
+\r
+ /* Initializes GPIO */\r
+ Chip_GPIO_Init(LPC_GPIO_PORT);\r
+\r
+ /* Setup GPIOs for USB demos */\r
+ Chip_SCU_PinMuxSet(0x2, 6, (SCU_MODE_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)); /* P2_6 USB1_PWR_EN, USB1 VBus function */\r
+ Chip_SCU_PinMuxSet(0x2, 5, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)); /* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */\r
+ Chip_SCU_PinMuxSet(0x1, 7, (SCU_MODE_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)); /* P1_7 USB0_PWR_EN, USB0 VBus function Xplorer */\r
+ Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 5, 6, true); /* GPIO5[6] = USB1_PWR_EN */\r
+ Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 5, 6, true); /* GPIO5[6] output high */\r
+\r
+ /* Initialize LEDs */\r
+ Board_LED_Init();\r
+}\r
+\r
+void Board_I2C_Init(I2C_ID_T id)\r
+{\r
+ if (id == I2C1) {\r
+ /* Configure pin function for I2C1*/\r
+ Chip_SCU_PinMuxSet(0x2, 3, (SCU_MODE_ZIF_DIS | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1)); /* P2.3 : I2C1_SDA */\r
+ Chip_SCU_PinMuxSet(0x2, 4, (SCU_MODE_ZIF_DIS | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1)); /* P2.4 : I2C1_SCL */\r
+ }\r
+ else {\r
+ Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);\r
+ }\r
+}\r
+\r
+#ifndef CORE_M0\r
+/* PIN0 Interrupt not available in M0 core */\r
+void GPIO0_IRQHandler(void)\r
+{\r
+ static bool On;\r
+\r
+ if (Chip_GPIO_IntGetStatus(LPC_GPIO_PIN_INT, 0, 0, 0)) {\r
+ Chip_GPIO_IntClear(LPC_GPIO_PIN_INT, 0, 0);\r
+ On = (bool) !On;\r
+ Board_LED_Set(1, On);\r
+ }\r
+}\r
+\r
+void Board_GPIO_Int_Init()\r
+{\r
+ Chip_SCU_PinMuxSet(0xF, 9, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)); /* PF.9 : POTI button */\r
+ Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 7, 23, false); /* PF.9 -> GPIO7[23] : input */\r
+ Chip_SCU_GPIOIntPinSel(0, 7, 23);\r
+ Chip_GPIO_IntCmd(LPC_GPIO_PIN_INT, 0, 0, GPIOPININT_FALLING_EDGE); /* Configure GPIO0[7] to interrupt pin (SW2 switch) */\r
+\r
+ NVIC_EnableIRQ(PIN_INT0_IRQn); /* enable GPIO interrupt 0 */\r
+}\r
+\r
+#endif\r
+\r
+void Board_SDMMC_Init(void)\r
+{\r
+ Chip_SCU_PinMuxSet(0x1, 9, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.9 connected to SDIO_D0 */\r
+ Chip_SCU_PinMuxSet(0x1, 10, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.10 connected to SDIO_D1 */\r
+ Chip_SCU_PinMuxSet(0x1, 11, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.11 connected to SDIO_D2 */\r
+ Chip_SCU_PinMuxSet(0x1, 12, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.12 connected to SDIO_D3 */\r
+\r
+ Chip_SCU_ClockPinMuxSet(2, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC4)); /* CLK2 connected to SDIO_CLK */\r
+ Chip_SCU_PinMuxSet(0x1, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC7)); /* P1.6 connected to SDIO_CMD */\r
+}\r
+\r
+void Board_SSP_Init(LPC_SSP_T *pSSP)\r
+{\r
+ if (pSSP == LPC_SSP1) {\r
+ /* Set up clock and power for SSP1 module */\r
+ /* Configure SSP1 pins*/\r
+ /* SCLK comes out pin CLK0 */\r
+ Chip_SCU_ClockPinMuxSet(0, (SCU_PINIO_FAST | SCU_MODE_FUNC6)); /* CLK0 connected to CLK SCU_MODE_FUNC6=SSP1 CLK1 */\r
+ Chip_SCU_PinMuxSet(0x1, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC5)); /* P1.5 connected to nCS SCU_MODE_FUNC5=SSP1 SSEL1 */\r
+ Chip_SCU_PinMuxSet(0x1, 3, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC5));/* P1.3 connected to SO SCU_MODE_FUNC5=SSP1 MISO1 */\r
+ Chip_SCU_PinMuxSet(0x1, 4, (SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC5));/* P1.4 connected to nSI SCU_MODE_FUNC5=SSP1 MOSI1 */\r
+ }\r
+ else {\r
+ return;\r
+ }\r
+}\r
+\r
+static void delay(uint32_t i) {\r
+ while (i--) {}\r
+}\r
+\r
+/* Initialize Audio Codec */\r
+static Status Board_Audio_CodecInit(int micIn)\r
+{\r
+ /* Reset UDA1380 on board NGX Xplorer */\r
+ Chip_SCU_PinMuxSet(0x2, 10, (SCU_MODE_MODE_INACT | SCU_MODE_FUNC0));\r
+ Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, 0, 14, true);\r
+ Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 0, 14, true);\r
+ // delay 1us\r
+ delay(100000);\r
+ Chip_GPIO_WritePortBit(LPC_GPIO_PORT, 0, 14, false);\r
+ delay(100000);\r
+\r
+ if (!UDA1380_Init(UDA1380_MIC_IN_LR & - (micIn != 0))) {\r
+ return ERROR;\r
+ }\r
+\r
+ return SUCCESS;\r
+}\r
+\r
+/* Board Audio initialization */\r
+void Board_Audio_Init(LPC_I2S_T *pI2S, int micIn)\r
+{\r
+ Chip_I2S_Audio_Format_T I2S_Config;\r
+\r
+ I2S_Config.SampleRate = 48000;\r
+ I2S_Config.ChannelNumber = 2; /* 1 is mono, 2 is stereo */\r
+ I2S_Config.WordWidth = 16; /* 8, 16 or 32 bits */\r
+ Chip_I2S_Init(pI2S);\r
+ Chip_I2S_Config(pI2S, I2S_TX_MODE, &I2S_Config);\r
+\r
+ /* Init UDA1380 CODEC */\r
+ while (Board_Audio_CodecInit(micIn) != SUCCESS) {}\r
+}\r
+\r
+/* FIXME Should we remove this function? */\r
+void Serial_CreateStream(void *Stream)\r
+{}\r
+\r
+/**\r
+ * @}\r
+ */\r
--- /dev/null
+/*\r
+ * @brief NGX Xplorer 1830/4330 board file\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __BOARD_NGX_XPLORER_18304330_H_\r
+#define __BOARD_NGX_XPLORER_18304330_H_\r
+\r
+#include "chip.h"\r
+#include "board_api.h"\r
+#include "lpc_phy.h"\r
+#include "uda1380.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup BOARD_NGX_XPLORER_18304330 LPC1830 and LPC4330 NGX Xplorer board support functions\r
+ * @ingroup BOARDS_18XX_43XX\r
+ * @{\r
+ */\r
+\r
+/** @defgroup BOARD_NGX_XPLORER_1830_OPTIONS BOARD: LPC1830 NGX Xplorer board builds options\r
+ * This board has options that configure its operation at build-time.<br>\r
+ *\r
+ * For more information on driver options see<br>\r
+ * @ref LPCOPEN_DESIGN_ARPPROACH<br>\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BOARD_NGX_XPLORER_4330_OPTIONS BOARD: LPC4330 NGX Xplorer board builds options\r
+ * This board has options that configure its operation at build-time.<br>\r
+ *\r
+ * For more information on driver options see<br>\r
+ * @ref LPCOPEN_DESIGN_ARPPROACH<br>\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define BOARD_NGX_XPLORER_18304330\r
+\r
+#define I2CDEV_UDA1380_ADDR (0x34 >> 1)\r
+#define UDA1380_I2C_BUS I2C0\r
+\r
+/* For USBLIB examples */\r
+#define LEDS_LED1 0x01\r
+#define LEDS_LED2 0x02\r
+#define LEDS_LED3 0x04\r
+#define LEDS_LED4 0x08\r
+#define LEDS_NO_LEDS 0x00\r
+#define BUTTONS_BUTTON1 0x01\r
+#define JOY_UP 0x01\r
+#define JOY_DOWN 0x02\r
+#define JOY_LEFT 0x04\r
+#define JOY_RIGHT 0x08\r
+#define JOY_PRESS 0x10\r
+#define NO_BUTTON_PRESSED 0x00\r
+\r
+/*Define if use SDCARD for Mass Storage Example*/\r
+//#define CFG_SDCARD\r
+\r
+#define BUTTONS_BUTTON1_GPIO_PORT_NUM 0\r
+#define BUTTONS_BUTTON1_GPIO_BIT_NUM 7\r
+#define LED1_GPIO_PORT_NUM 1\r
+#define LED1_GPIO_BIT_NUM 11\r
+#define LED2_GPIO_PORT_NUM 1\r
+#define LED2_GPIO_BIT_NUM 12\r
+\r
+/**\r
+ * @brief Sets up board specific I2C interface\r
+ * @param id : I2C Peripheral ID (I2C0, I2C1)\r
+ * @return Nothing\r
+ */\r
+void Board_I2C_Init(I2C_ID_T id);\r
+\r
+/**\r
+ * @brief Sets up I2C Fast Plus mode\r
+ * @param id : Must always be I2C0\r
+ * @return Nothing\r
+ * @note This function must be called before calling\r
+ * Chip_I2C_SetClockRate() to set clock rates above\r
+ * normal range 100KHz to 400KHz. Only I2C0 supports\r
+ * this mode.\r
+ */\r
+STATIC INLINE void Board_I2C_EnableFastPlus(I2C_ID_T id)\r
+{\r
+ Chip_SCU_I2C0PinConfig(I2C0_FAST_MODE_PLUS);\r
+}\r
+\r
+/**\r
+ * @brief Disable I2C Fast Plus mode and enables default mode\r
+ * @param id : Must always be I2C0\r
+ * @return Nothing\r
+ * @sa Board_I2C_EnableFastPlus()\r
+ */\r
+STATIC INLINE void Board_I2C_DisableFastPlus(I2C_ID_T id)\r
+{\r
+ Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes board specific GPIO Interrupt\r
+ * @return Nothing\r
+ */\r
+void Board_GPIO_Int_Init(void);\r
+\r
+/**\r
+ * @brief Initialize pin muxing for SSP interface\r
+ * @param pSSP : Pointer to SSP interface to initialize\r
+ * @return Nothing\r
+ */\r
+void Board_SSP_Init(LPC_SSP_T *pSSP);\r
+\r
+/**\r
+ * @brief Returns the MAC address assigned to this board\r
+ * @param mcaddr : Pointer to 6-byte character array to populate with MAC address\r
+ * @return Nothing\r
+ */\r
+void Board_ENET_GetMacADDR(uint8_t *mcaddr);\r
+\r
+/**\r
+ * @brief Initialize pin muxing for a UART\r
+ * @param pUART : Pointer to UART register block for UART pins to init\r
+ * @return Nothing\r
+ */\r
+void Board_UART_Init(LPC_USART_T *pUART);\r
+\r
+/**\r
+ * @brief Initialize pin muxing for SDMMC interface\r
+ * @return Nothing\r
+ */\r
+void Board_SDMMC_Init(void);\r
+\r
+/**\r
+ * @brief Initialize button(s) interface on board\r
+ * @return Nothing\r
+ */\r
+void Board_Buttons_Init(void);\r
+\r
+/**\r
+ * @brief Initialize joystick interface on board\r
+ * @return Nothing\r
+ */\r
+void Board_Joystick_Init(void);\r
+\r
+/**\r
+ * @brief Returns joystick states on board\r
+ * @return Returns a JOY_* value, ir JOY_PRESS or JOY_UP\r
+ */\r
+uint8_t Joystick_GetStatus(void);\r
+\r
+/**\r
+ * @brief Returns button(s) state on board\r
+ * @return Returns BUTTONS_BUTTON1 if button1 is pressed\r
+ */\r
+uint32_t Buttons_GetStatus (void);\r
+\r
+/**\r
+ * @brief Initialize I2S interface for the board and UDA1380\r
+ * @param pI2S : Pointer to I2S register interface used on this board\r
+ * @param micIn : If 1 MIC will be used as input, if 0 LINE_IN will be used\r
+ * @return Nothing\r
+ */\r
+void Board_Audio_Init(LPC_I2S_T *pI2S, int micIn);\r
+\r
+/**\r
+ * @brief FIXME\r
+ * @param Stream : FIXME\r
+ * @return Nothing\r
+ */\r
+void Serial_CreateStream(void *Stream);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __BOARD_NGX_XPLORER_18304330_H_ */\r
--- /dev/null
+/*\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SYS_CONFIG_H_\r
+#define __SYS_CONFIG_H_\r
+\r
+/** @ingroup BOARD_NGX_XPLORER_1830_OPTIONS\r
+ * @{\r
+ */\r
+\r
+/* Build for 18xx chip family */\r
+#define CHIP_LPC18XX\r
+\r
+/* Build for RMII interface */\r
+#define USE_RMII\r
+\r
+/* Un-comment DEBUG_ENABLE for IO support via the UART */\r
+// #define DEBUG_ENABLE\r
+\r
+/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support\r
+ via semihosting */\r
+// #define DEBUG_SEMIHOSTING\r
+\r
+/* Board UART used for debug output */\r
+#define DEBUG_UART LPC_USART0 /* No port on Xplorer */\r
+\r
+/* Crystal frequency into device */\r
+#define CRYSTAL_MAIN_FREQ_IN 12000000\r
+\r
+/* Crystal frequency into device for RTC/32K input */\r
+#define CRYSTAL_32K_FREQ_IN 32768\r
+\r
+/* Frequency on external clock in pin */\r
+#define EXTERNAL_CLKIN_FREQ_IN 0\r
+\r
+/* Default CPU clock frequency */\r
+#define MAX_CLOCK_FREQ (180000000)\r
+\r
+/* Audio and USB default PLL rates (configured in SystemInit()) */\r
+#define CGU_AUDIO_PLL_RATE (0)\r
+#define CGU_USB_PLL_RATE (480000000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __SYS_CONFIG_H_ */\r
--- /dev/null
+/*\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "board.h"\r
+\r
+/** @defgroup BOARD_NGX_XPLORER_18304330_SYSINIT LPC1830 and LPC4330 NGX Xplorer board System Init code\r
+ * @ingroup BOARD_NGX_XPLORER_18304330\r
+ * The System initialization code is called prior to the application and\r
+ * initializes the board for run-time operation. Board initialization\r
+ * for the NGX Xplorer boards includes clock setup and default pin muxing\r
+ * configuration.\r
+ *\r
+ * With the exception of stack space, no RW memory is used for this call.\r
+ *\r
+ * LPC1830 and LPC4330 NGX Xplorer setup<BR>\r
+ * Clocking:<BR>\r
+ * All base clocks enabled by default (Save power by disabling un-needed clocks)<BR>\r
+ * CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)<BR>\r
+ * SPIFI FLASH clock setup for fastest speed<BR>\r
+ * CGU Dividers A, C, D and E are used for the LCD, USB, and SPIFI.\r
+ * Pin muxing:<BR>\r
+ * Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)<BR>\r
+ * Memory:<BR>\r
+ * There is no memory setup for this board.\r
+ * @{\r
+ */\r
+\r
+#ifndef CORE_M0\r
+/* SCR pin definitions for pin muxing */\r
+typedef struct {\r
+ uint8_t pingrp; /* Pin group */\r
+ uint8_t pinnum; /* Pin number */\r
+ uint16_t modefunc; /* Pin mode and function for SCU */\r
+} PINMUX_GRP_T;\r
+\r
+/* Structure for initial base clock states */\r
+struct CLK_BASE_STATES {\r
+ CHIP_CGU_BASE_CLK_T clk; /* Base clock */\r
+ CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */\r
+ bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */\r
+ bool powerdn; /* Set to true if the base clock is initially powered down */\r
+};\r
+\r
+/* Initial base clock states are mostly on */\r
+STATIC const struct CLK_BASE_STATES InitClkStates[] = {\r
+ {CLK_BASE_SAFE, CLKIN_IRC, true, false},\r
+ {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_USB0, CLKIN_USBPLL, true, true},\r
+#if defined(CHIP_LPC43XX)\r
+ {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_VADC, CLKIN_MAINPLL, true, true},\r
+#endif\r
+ {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},\r
+#if defined(USE_RMII)\r
+ {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},\r
+#else\r
+ {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},\r
+#endif\r
+ {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},\r
+ {CLK_BASE_OUT, CLKINPUT_PD, true, false},\r
+ {CLK_BASE_APLL, CLKINPUT_PD, true, false},\r
+ {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},\r
+ {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false},\r
+\r
+ /* Clocks derived from dividers */\r
+ {CLK_BASE_LCD, CLKIN_IDIVC, true, false},\r
+ {CLK_BASE_USB1, CLKIN_IDIVD, true, true}\r
+};\r
+\r
+/* SPIFI high speed pin mode setup */\r
+STATIC const PINMUX_GRP_T spifipinmuxing[] = {\r
+ {0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI CLK */\r
+ {0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D3 */\r
+ {0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D2 */\r
+ {0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D1 */\r
+ {0x3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D0 */\r
+ {0x3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)} /* SPIFI CS/SSEL */\r
+};\r
+\r
+/* USB PLL pre-initialized setup values for 480MHz output rate */\r
+static const CGU_USBAUDIO_PLL_SETUP_T usbPLLSetup = {\r
+ 0x0000601D, /* Default control with main osc input, PLL disabled */\r
+ 0x06167FFA, /* M-divider value for 480MHz output from 12MHz input */\r
+ 0x00000000, /* N-divider value */\r
+ 0x00000000 /* Not applicable for USB PLL */\r
+};\r
+\r
+/* Audio PLL pre-initialized setup values for FIXME output rate */\r
+// static const CGU_USBAUDIO_PLL_SETUP_T audioPLLSetup = {\r
+// 0x0000601D, /* Default control with main osc input, PLL disabled */\r
+// 0x06167FFA, /* M-divider value for FIXME output from 12MHz input */\r
+// 0x00000000, /* N-divider value */\r
+// 0x00000000 /* FIXME */\r
+// };\r
+\r
+/* Setup system clocking */\r
+STATIC void SystemSetupClocking(void)\r
+{\r
+ int i;\r
+\r
+ /* Switch main system clocking to crystal */\r
+ Chip_Clock_EnableCrystal();\r
+ Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);\r
+\r
+ /* Setup PLL for 100MHz and switch main system clocking */\r
+ Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);\r
+ Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);\r
+\r
+ /* Setup PLL for maximum clock */\r
+ Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);\r
+\r
+ /* Setup system base clocks and initial states. This won't enable and\r
+ disable individual clocks, but sets up the base clock sources for\r
+ each individual peripheral clock. */\r
+ for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {\r
+ Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,\r
+ InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);\r
+ }\r
+\r
+ /* Reset and enable 32Khz oscillator */\r
+ LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));\r
+ LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);\r
+\r
+ /* SPIFI pin setup is done prior to setting up system clocking */\r
+ for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {\r
+ Chip_SCU_PinMuxSet(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,\r
+ spifipinmuxing[i].modefunc);\r
+ }\r
+\r
+ /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.\r
+ Divide rate is based on CPU speed and speed of SPI FLASH part. */\r
+#if (MAX_CLOCK_FREQ > 180000000)\r
+ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);\r
+#else\r
+ Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);\r
+#endif\r
+ Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);\r
+\r
+ /* Attach main PLL clock to divider C with a divider of 2 */\r
+ Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);\r
+\r
+ /* Setup default USB PLL state for a 480MHz output and attach */\r
+ Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);\r
+\r
+ /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are\r
+ chained to make a divide by 8 function. Connect the output of\r
+ divider D to the USB1 base clock. */\r
+ Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);\r
+ Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);\r
+ Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);\r
+\r
+ /* Setup default audio PLL state for a FIXME output */\r
+ // Chip_Clock_SetupPLL(CGU_AUDIO_PLL, &audioPLLSetup); // FIXME\r
+}\r
+\r
+STATIC const PINMUX_GRP_T pinmuxing[] = {\r
+ /* RMII pin group */\r
+ {0x1, 15,\r
+ (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},\r
+ {0x0, 0,\r
+ (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},\r
+ {0x1, 16,\r
+ (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},\r
+ {0x0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},\r
+ {0x1, 19,\r
+ (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},\r
+ {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},\r
+ {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},\r
+ {0x1, 17,\r
+ (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},\r
+ {0x2, 0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_MODE_PULLUP | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},\r
+ /* Board LEDs */\r
+ {0x2, 11, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC0)},\r
+ {0x2, 12, (SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC0)},\r
+ /* I2S */\r
+ {0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},\r
+ {0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},\r
+ {0x7, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},\r
+ {0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},\r
+ {0x7, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},\r
+ {0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},\r
+};\r
+\r
+/* Sets up system pin muxing */\r
+STATIC void SystemSetupMuxing(void)\r
+{\r
+ int i;\r
+\r
+ /* Setup system level pin muxing */\r
+ for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {\r
+ Chip_SCU_PinMuxSet(pinmuxing[i].pingrp, pinmuxing[i].pinnum,\r
+ pinmuxing[i].modefunc);\r
+ }\r
+}\r
+\r
+/* Nothing to do for the Xplorer board */\r
+STATIC void SystemSetupMemory(void)\r
+{}\r
+\r
+#endif\r
+\r
+/**\r
+ * @brief Setup the system\r
+ * @return none\r
+ * SystemInit() is called prior to the application and sets up system\r
+ * clocking, memory, and any resources needed prior to the application\r
+ * starting.\r
+ */\r
+void SystemInit(void)\r
+{\r
+#if defined(CORE_M3) || defined(CORE_M4)\r
+ unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;\r
+\r
+#if defined(__IAR_SYSTEMS_ICC__)\r
+ extern void *__vector_table;\r
+\r
+ *pSCB_VTOR = (unsigned int) &__vector_table;\r
+#elif defined(__CODE_RED)\r
+ extern void *g_pfnVectors;\r
+\r
+ *pSCB_VTOR = (unsigned int) &g_pfnVectors;\r
+#elif defined(__ARMCC_VERSION)\r
+ extern void *__Vectors;\r
+\r
+ *pSCB_VTOR = (unsigned int) &__Vectors;\r
+#endif\r
+\r
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1\r
+ fpuInit();\r
+#endif\r
+\r
+ /* Setup system clocking and memory. This is done early to allow the\r
+ application and tools to clear memory and use scatter loading to\r
+ external memory. */\r
+ SystemSetupClocking();\r
+ SystemSetupMuxing();\r
+ SystemSetupMemory();\r
+#endif\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx A/D conversion driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __ADC_18XX_43XX_H_\r
+#define __ADC_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup ADC_18XX_43XX CHIP: LPC18xx/43xx A/D conversion driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/** The channels on one ADC peripheral*/\r
+typedef enum CHIP_ADC_CHANNEL {\r
+ ADC_CH0 = 0, /**< ADC channel 0 */\r
+ ADC_CH1, /**< ADC channel 1 */\r
+ ADC_CH2, /**< ADC channel 2 */\r
+ ADC_CH3, /**< ADC channel 3 */\r
+ ADC_CH4, /**< ADC channel 4 */\r
+ ADC_CH5, /**< ADC channel 5 */\r
+ ADC_CH6, /**< ADC channel 6 */\r
+ ADC_CH7, /**< ADC channel 7 */\r
+} CHIP_ADC_CHANNEL_T;\r
+\r
+/** The number of bits of accuracy of the result in the LS bits of ADDR*/\r
+typedef enum CHIP_ADC_RESOLUTION {\r
+ ADC_10BITS = 0, /**< ADC 10 bits */\r
+ ADC_9BITS, /**< ADC 9 bits */\r
+ ADC_8BITS, /**< ADC 8 bits */\r
+ ADC_7BITS, /**< ADC 7 bits */\r
+ ADC_6BITS, /**< ADC 6 bits */\r
+ ADC_5BITS, /**< ADC 5 bits */\r
+ ADC_4BITS, /**< ADC 4 bits */\r
+ ADC_3BITS, /**< ADC 3 bits */\r
+} CHIP_ADC_RESOLUTION_T;\r
+\r
+/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */\r
+typedef enum CHIP_ADC_EDGE_CFG {\r
+ ADC_TRIGGERMODE_RISING = 0, /**< Trigger event: rising edge */\r
+ ADC_TRIGGERMODE_FALLING, /**< Trigger event: falling edge */\r
+} CHIP_ADC_EDGE_CFG_T;\r
+\r
+/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */\r
+typedef enum CHIP_ADC_START_MODE {\r
+ ADC_NO_START = 0,\r
+ ADC_START_NOW, /*!< Start conversion now */\r
+ ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */\r
+ ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */\r
+ ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */\r
+ ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */\r
+ ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */\r
+} CHIP_ADC_START_MODE_T;\r
+\r
+/** Clock setup structure for ADC controller passed to the initialize function */\r
+typedef struct {\r
+ uint32_t adcRate; /*!< ADC rate */\r
+ uint8_t bitsAccuracy; /*!< ADC bit accuracy */\r
+ bool burstMode; /*!< ADC Burt Mode */\r
+} ADC_Clock_Setup_T;\r
+\r
+/**\r
+ * @brief Read the ADC value from a channel\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param channel : ADC channel to read\r
+ * @param data : Pointer to where to put data\r
+ * @return SUCCESS or ERROR if no conversion is ready\r
+ */\r
+STATIC INLINE Status Chip_ADC_Read_Value(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)\r
+{\r
+ return IP_ADC_Get_Val(pADC, channel, data);\r
+}\r
+\r
+/**\r
+ * @brief Read the ADC channel status\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param channel : ADC channel to read\r
+ * @param StatusType : Status type of ADC_DR_*\r
+ * @return SET or RESET\r
+ */\r
+STATIC INLINE FlagStatus Chip_ADC_Read_Status(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType)\r
+{\r
+ return IP_ADC_GetStatus(pADC, channel, StatusType);\r
+}\r
+\r
+/**\r
+ * @brief Enable/Disable interrupt for ADC channel\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param channel : ADC channel to read\r
+ * @param NewState : New state, ENABLE or DISABLE\r
+ * @return SET or RESET\r
+ */\r
+STATIC INLINE void Chip_ADC_Channel_Int_Cmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState)\r
+{\r
+ IP_ADC_Int_Enable(pADC, channel, NewState);\r
+}\r
+\r
+/**\r
+ * @brief Enable/Disable global interrupt for ADC channel\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param NewState : New state, ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ADC_Global_Int_Cmd(LPC_ADC_T *pADC, FunctionalState NewState)\r
+{\r
+ IP_ADC_Int_Enable(pADC, 8, NewState);\r
+}\r
+\r
+/**\r
+ * @brief Shutdown ADC\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_ADC_DeInit(LPC_ADC_T *pADC);\r
+\r
+/**\r
+ * @brief Initialize the ADC peripheral and the ADC setup structure to default value\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param ADCSetup : ADC setup structure to be set\r
+ * @return Nothing\r
+ * @note Default setting for ADC is 400kHz - 10bits\r
+ */\r
+void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_Clock_Setup_T *ADCSetup);\r
+\r
+/**\r
+ * @brief Select the mode starting the AD conversion\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param mode : Stating mode, should be :\r
+ * - ADC_NO_START : Must be set for Burst mode\r
+ * - ADC_START_NOW : Start conversion now\r
+ * - ADC_START_ON_CTOUT15 : Start conversion when the edge selected by bit 27 occurs on CTOUT_15\r
+ * - ADC_START_ON_CTOUT8 : Start conversion when the edge selected by bit 27 occurs on CTOUT_8\r
+ * - ADC_START_ON_ADCTRIG0 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0\r
+ * - ADC_START_ON_ADCTRIG1 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1\r
+ * - ADC_START_ON_MCOA2 : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2\r
+ * @param EdgeOption : Stating Edge Condition, should be :\r
+ * - ADC_TRIGGERMODE_RISING : Trigger event on rising edge\r
+ * - ADC_TRIGGERMODE_FALLING : Trigger event on falling edge\r
+ * @return Nothing\r
+ */\r
+void Chip_ADC_Set_StartMode(LPC_ADC_T *pADC, CHIP_ADC_START_MODE_T mode, CHIP_ADC_EDGE_CFG_T EdgeOption);\r
+\r
+/**\r
+ * @brief Set the ADC Sample rate\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param ADCSetup : ADC setup structure to be modified\r
+ * @param rate : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.\r
+ * @return Nothing\r
+ */\r
+void Chip_ADC_Set_SampleRate(LPC_ADC_T *pADC, ADC_Clock_Setup_T *ADCSetup, uint32_t rate);\r
+\r
+/**\r
+ * @brief Set the ADC accuracy bits\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param ADCSetup : ADC setup structure to be modified\r
+ * @param resolution : The resolution, should be ADC_10BITS -> ADC_3BITS\r
+ * @return Nothing\r
+ */\r
+void Chip_ADC_Set_Resolution(LPC_ADC_T *pADC, ADC_Clock_Setup_T *ADCSetup, CHIP_ADC_RESOLUTION_T resolution);\r
+\r
+/**\r
+ * @brief Enable or disable the ADC channel on ADC peripheral\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param channel : Channel to be enable or disable\r
+ * @param NewState : New state, should be:\r
+ * - ENABLE\r
+ * - DISABLE\r
+ * @return Nothing\r
+ */\r
+void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_T *pADC, CHIP_ADC_CHANNEL_T channel, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Enable burst mode\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param NewState : New state, should be:\r
+ * - ENABLE\r
+ * - DISABLE\r
+ * @return Nothing\r
+ */\r
+void Chip_ADC_Burst_Cmd(LPC_ADC_T *pADC, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Read the ADC value and convert it to 8bits value\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param channel: selected channel\r
+ * @param data : Storage for data\r
+ * @return Status : ERROR or SUCCESS\r
+ */\r
+Status Chip_ADC_Read_Byte(LPC_ADC_T *pADC, CHIP_ADC_CHANNEL_T channel, uint8_t *data);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __ADC_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx AES Engine driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __AES_18XX_43XX_H_\r
+#define __AES_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup AES_18XX_43XX CHIP: LPC18xx/43xx AES Engine driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief AES Engine operation mode\r
+ */\r
+typedef enum CHIP_AES_OP_MODE {\r
+ CHIP_AES_API_CMD_ENCODE_ECB, /*!< ECB Encode mode */\r
+ CHIP_AES_API_CMD_DECODE_ECB, /*!< ECB Decode mode */\r
+ CHIP_AES_API_CMD_ENCODE_CBC, /*!< CBC Encode mode */\r
+ CHIP_AES_API_CMD_DECODE_CBC, /*!< CBC Decode mode */\r
+} CHIP_AES_OP_MODE_T;\r
+\r
+/**\r
+ * @brief Initialize the AES Engine function\r
+ * @return None\r
+ * This function will initialise all the AES Engine driver function pointers\r
+ * and call the AES Engine Initialisation function.\r
+ */\r
+void Chip_AES_Init(void);\r
+\r
+/**\r
+ * @brief Set operation mode in AES Engine\r
+ * @param AesMode : AES Operation Mode\r
+ * @return Status\r
+ */\r
+uint32_t Chip_AES_SetMode(CHIP_AES_OP_MODE_T AesMode);\r
+\r
+/**\r
+ * @brief Load 128-bit AES user key in AES Engine\r
+ * @param keyNum: 0 - Load AES 128-bit user key 1, else load user key2\r
+ * @return None\r
+ */\r
+void Chip_AES_LoadKey(uint32_t keyNum);\r
+\r
+/**\r
+ * @brief Load randomly generated key in AES engine\r
+ * @return None\r
+ * To update the RNG and load a new random number,\r
+ * the API call Chip_OTP_GenRand should be used\r
+ */\r
+void Chip_AES_LoadKeyRNG(void);\r
+\r
+/**\r
+ * @brief Load 128-bit AES software defined user key in AES Engine\r
+ * @param pKey : Pointer to 16 byte user key\r
+ * @return None\r
+ */\r
+void Chip_AES_LoadKeySW(uint8_t *pKey);\r
+\r
+/**\r
+ * @brief Load 128-bit AES initialization vector in AES Engine\r
+ * @param pVector : Pointer to 16 byte Initialisation vector\r
+ * @return None\r
+ */\r
+void Chip_AES_LoadIV_SW(uint8_t *pVector);\r
+\r
+/**\r
+ * @brief Load IC specific 128-bit AES initialization vector in AES Engine\r
+ * @return None\r
+ * This loads 128-bit AES IC specific initialization vector,\r
+ * which is used to decrypt a boot image\r
+ */\r
+void Chip_AES_LoadIV_IC(void);\r
+\r
+/**\r
+ * @brief Operate AES Engine\r
+ * @param pDatOut : Pointer to output data stream\r
+ * @param pDatIn : Pointer to input data stream\r
+ * @param Size : Size of the data stream (128-bit)\r
+ * @return Status\r
+ * This function performs the AES operation after the AES mode\r
+ * has been set using Chip_AES_SetMode and the appropriate keys\r
+ * and init vectors have been loaded\r
+ */\r
+uint32_t Chip_AES_Operate(uint8_t *pDatOut, uint8_t *pDatIn, uint32_t Size);\r
+\r
+/**\r
+ * @brief Program 128-bit AES Key in OTP\r
+ * @param KeyNum : Key Number (Select 0 or 1)\r
+ * @param pKey : Pointer to AES Key (16 bytes required)\r
+ * @return Status\r
+ * When calling the aes_ProgramKey2 function, ensure that VPP = 2.7 V to 3.6 V.\r
+ */\r
+uint32_t Chip_AES_ProgramKey(uint32_t KeyNum, uint8_t *pKey);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __AES_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx ATimer chip driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __ATIMER_18XX_43XX_H_\r
+#define __ATIMER_18XX_43XX_H_\r
+\r
+/** @defgroup ATIMER_18XX_43XX CHIP: LPC18xx/43xx ATimer Driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize Alarm Timer\r
+ * @param pATIMER : The base of ATIMER peripheral on the chip\r
+ * @param PresetValue : Count of 1 to 1024s for Alarm\r
+ * @return None\r
+ */\r
+void Chip_ATIMER_Init(LPC_ATIMER_T *pATIMER, uint32_t PresetValue);\r
+\r
+/**\r
+ * @brief Close ATIMER device\r
+ * @param pATIMER : The base of ATIMER peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_ATIMER_DeInit(LPC_ATIMER_T *pATIMER)\r
+{\r
+ IP_ATIMER_DeInit(pATIMER);\r
+}\r
+\r
+/**\r
+ * @brief Enable ATIMER Interrupt\r
+ * @param pATIMER : The base of ATIMER peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_ATIMER_IntEnable(LPC_ATIMER_T *pATIMER)\r
+{\r
+ IP_ATIMER_IntEnable(pATIMER);\r
+}\r
+\r
+/**\r
+ * @brief Disable ATIMER Interrupt\r
+ * @param pATIMER : The base of ATIMER peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_ATIMER_IntDisable(LPC_ATIMER_T *pATIMER)\r
+{\r
+ IP_ATIMER_IntDisable(pATIMER);\r
+}\r
+\r
+/**\r
+ * @brief Clear ATIMER Interrupt Status\r
+ * @param pATIMER : The base of ATIMER peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_ATIMER_ClearIntStatus(LPC_ATIMER_T *pATIMER)\r
+{\r
+ IP_ATIMER_ClearIntStatus(pATIMER);\r
+}\r
+\r
+/**\r
+ * @brief Set ATIMER Interrupt Status\r
+ * @param pATIMER : The base of ATIMER peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_ATIMER_SetIntStatus(LPC_ATIMER_T *pATIMER)\r
+{\r
+ IP_ATIMER_SetIntStatus(pATIMER);\r
+}\r
+\r
+/**\r
+ * @brief Update Preset value\r
+ * @param pATIMER : The base of ATIMER peripheral on the chip\r
+ * @param PresetValue : updated preset value\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ATIMER_UpdatePresetValue(LPC_ATIMER_T *pATIMER, uint32_t PresetValue)\r
+{\r
+ IP_ATIMER_UpdatePresetValue(pATIMER, PresetValue);\r
+}\r
+\r
+/**\r
+ * @brief Read value of preset register\r
+ * @param pATIMER : The base of ATIMER peripheral on the chip\r
+ * @return Value of capture register\r
+ */\r
+STATIC INLINE uint32_t Chip_ATIMER_GetPresetValue(LPC_ATIMER_T *pATIMER)\r
+{\r
+ return IP_ATIMER_GetPresetValue(pATIMER);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ #endif /* __ATIMER_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx CCAN driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CCAN_18XX_43XX_H_\r
+#define __CCAN_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#define CCAN_SEG1_DEFAULT_VAL 5\r
+#define CCAN_SEG2_DEFAULT_VAL 4\r
+#define CCAN_SJW_DEFAULT_VAL 0\r
+\r
+/** @defgroup CCAN_18XX_43XX CHIP: LPC18xx/43xx CCAN driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable/Disable CCAN Interrupts\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param NewState : New state, ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_CCAN_IntEnable(LPC_CCAN_T *pCCAN, FunctionalState NewState)\r
+{\r
+ IP_CCAN_IntEnable(pCCAN, (IP_CCAN_INT_T) (CCAN_MODULE_INT | CCAN_STATUS_CHANGE_INT | CCAN_ERR_INT), NewState);\r
+}\r
+\r
+/**\r
+ * @brief Get the source ID of an interrupt\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @return Interrupt source ID\r
+ */\r
+STATIC INLINE uint32_t Chip_CCAN_GetIntID(LPC_CCAN_T *pCCAN)\r
+{\r
+ return IP_CCAN_Get_IntID(pCCAN);\r
+}\r
+\r
+/**\r
+ * @brief Get the CCAN status register\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @return CCAN status register\r
+ */\r
+STATIC INLINE uint32_t Chip_CCAN_GetStatus(LPC_CCAN_T *pCCAN)\r
+{\r
+ return IP_CCAN_GetStatus(pCCAN);\r
+}\r
+\r
+/**\r
+ * @brief Get a message object in message RAM into the message buffer\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param msg_num : The number of message object in message RAM to be get\r
+ * @param msg_buf : Pointer of the message buffer\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_CCAN_GetMsgObject(LPC_CCAN_T *pCCAN, uint8_t msg_num, message_object *msg_buf)\r
+{\r
+ IP_CCAN_GetMsgObject(LPC_C_CAN0, IF2, msg_num, msg_buf);\r
+}\r
+\r
+/**\r
+ * @brief Initialize the CCAN peripheral, free all message object in RAM\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_CCAN_Init(LPC_CCAN_T *pCCAN);\r
+\r
+/**\r
+ * @brief De-initialize the CCAN peripheral\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_CCAN_DeInit(LPC_CCAN_T *pCCAN);\r
+\r
+/**\r
+ * @brief Select bit rate for CCAN bus\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param bitRate : Bit rate to be set\r
+ * @return Nothing\r
+ */\r
+void Chip_CCAN_SetBitRate(LPC_CCAN_T *pCCAN, uint32_t bitRate);\r
+\r
+/**\r
+ * @brief Clear the status of CCAN bus\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param status : Status to be cleared\r
+ * @return Nothing\r
+ */\r
+void Chip_CCAN_ClearStatus(LPC_CCAN_T *pCCAN, IP_CCAN_STATUS_T status);\r
+\r
+/**\r
+ * @brief Clear the pending interrupt\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param msg_num : Message number\r
+ * @param TRxMode : Select transmit or receive interrupt to be cleared\r
+ * @return Nothing\r
+ */\r
+void Chip_CCAN_ClearIntPend(LPC_CCAN_T *pCCAN, uint8_t msg_num, uint8_t TRxMode);\r
+\r
+/**\r
+ * @brief Send a message\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param RemoteEnable: Enable/Disable passives transmit by using remote frame\r
+ * @param msg_ptr : Message to be transmitted\r
+ * @return Nothing\r
+ */\r
+void Chip_CCAN_Send (LPC_CCAN_T *pCCAN, uint32_t RemoteEnable, message_object *msg_ptr);\r
+\r
+/**\r
+ * @brief Register a message ID for receiving\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param rev_id : Received message ID\r
+ * @return Nothing\r
+ */\r
+void Chip_CCAN_AddReceiveID(LPC_CCAN_T *pCCAN, uint32_t rev_id);\r
+\r
+/**\r
+ * @brief Remove a registered message ID from receiving\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param rev_id : Received message ID to be removed\r
+ * @return Nothing\r
+ */\r
+void Chip_CCAN_DeleteReceiveID(LPC_CCAN_T *pCCAN, uint32_t rev_id);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CCAN_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief CGU/CCU registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CGUCCU_18XX_43XX_H_\r
+#define __CGUCCU_18XX_43XX_H_\r
+\r
+#include "cmsis.h"\r
+#include "chip_clocks.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @ingroup CLOCK_18XX_43XX\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * Audio or USB PLL selection\r
+ */\r
+typedef enum CHIP_CGU_USB_AUDIO_PLL {\r
+ CGU_USB_PLL,\r
+ CGU_AUDIO_PLL\r
+} CHIP_CGU_USB_AUDIO_PLL_T;\r
+\r
+/**\r
+ * PLL register block\r
+ */\r
+typedef struct {\r
+ __I uint32_t PLL_STAT; /*!< PLL status register */\r
+ __IO uint32_t PLL_CTRL; /*!< PLL control register */\r
+ __IO uint32_t PLL_MDIV; /*!< PLL M-divider register */\r
+ __IO uint32_t PLL_NP_DIV; /*!< PLL N/P-divider register */\r
+} CGU_PLL_REG_T;\r
+\r
+/**\r
+ * @brief LPC18XX/43XX CGU register block structure\r
+ */\r
+typedef struct { /*!< (@ 0x40050000) CGU Structure */\r
+ __I uint32_t RESERVED0[5];\r
+ __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */\r
+ __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */\r
+ CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /*!< (@ 0x4005001C) USB and audio PLL blocks */\r
+ __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */\r
+ __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */\r
+ __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */\r
+ __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */\r
+ __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /*!< (@ 0x4005005C) Start of base clock registers */\r
+} LPC_CGU_T;\r
+\r
+/**\r
+ * @brief CCU clock config/status register pair\r
+ */\r
+typedef struct {\r
+ __IO uint32_t CFG; /*!< CCU clock configuration register */\r
+ __I uint32_t STAT; /*!< CCU clock status register */\r
+} CCU_CFGSTAT_T;\r
+\r
+/**\r
+ * @brief CCU1 register block structure\r
+ */\r
+typedef struct { /*!< (@ 0x40051000) CCU1 Structure */\r
+ __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */\r
+ __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */\r
+ __I uint32_t RESERVED0[62];\r
+ CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /*!< (@ 0x40051100) Start of CCU1 clock registers */\r
+} LPC_CCU1_T;\r
+\r
+/**\r
+ * @brief CCU2 register block structure\r
+ */\r
+typedef struct { /*!< (@ 0x40052000) CCU2 Structure */\r
+ __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */\r
+ __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */\r
+ __I uint32_t RESERVED0[62];\r
+ CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /*!< (@ 0x40052100) Start of CCU2 clock registers */\r
+} LPC_CCU2_T;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CGUCCU_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief Chip inclusion selector file\r
+ *\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CHIP_H_\r
+#define __CHIP_H_\r
+\r
+#include "sys_config.h"\r
+\r
+#if defined(CHIP_LPC18XX)\r
+#include "chip_lpc18xx.h"\r
+\r
+#elif defined(CHIP_LPC43XX)\r
+#include "chip_lpc43xx.h"\r
+\r
+#else\r
+#error CHIP_LPC18XX or CHIP_LPC43XX must be defined\r
+#endif\r
+\r
+#endif /* __CHIP_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx chip clock list used by CGU and CCU drivers\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CHIP_CLOCKS_H_\r
+#define __CHIP_CLOCKS_H_\r
+\r
+#include "sys_config.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @ingroup CLOCK_18XX_43XX\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief CGU clock input list\r
+ * These are possible input clocks for the CGU and can come\r
+ * from both external (crystal) and internal (PLL) sources. These\r
+ * clock inputs can be routed to the base clocks (@ref CHIP_CGU_BASE_CLK_T).\r
+ */\r
+typedef enum CHIP_CGU_CLKIN {\r
+ CLKIN_32K, /*!< External 32KHz input */\r
+ CLKIN_IRC, /*!< Internal IRC (12MHz) input */\r
+ CLKIN_ENET_RX, /*!< External ENET_RX pin input */\r
+ CLKIN_ENET_TX, /*!< External ENET_TX pin input */\r
+ CLKIN_CLKIN, /*!< External GPCLKIN pin input */\r
+ CLKIN_RESERVED1,\r
+ CLKIN_CRYSTAL, /*!< External (main) crystal pin input */\r
+ CLKIN_USBPLL, /*!< Internal USB PLL input */\r
+ CLKIN_AUDIOPLL, /*!< Internal Audio PLL input */\r
+ CLKIN_MAINPLL, /*!< Internal Main PLL input */\r
+ CLKIN_RESERVED2,\r
+ CLKIN_RESERVED3,\r
+ CLKIN_IDIVA, /*!< Internal divider A input */\r
+ CLKIN_IDIVB, /*!< Internal divider B input */\r
+ CLKIN_IDIVC, /*!< Internal divider C input */\r
+ CLKIN_IDIVD, /*!< Internal divider D input */\r
+ CLKIN_IDIVE, /*!< Internal divider E input */\r
+ CLKINPUT_PD /*!< External 32KHz input */\r
+} CHIP_CGU_CLKIN_T;\r
+\r
+/**\r
+ * @brief CGU base clocks\r
+ * CGU base clocks are clocks that are associated with a single input clock\r
+ * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH\r
+ * clock can be configured to use the CLKIN_MAINPLL input clock, which will in\r
+ * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and\r
+ * CLK_PERIPH_SGPIO periphral clocks.\r
+ */\r
+typedef enum CHIP_CGU_BASE_CLK {\r
+ CLK_BASE_SAFE, /*!< Base clock for WDT oscillator, IRC input only */\r
+ CLK_BASE_USB0, /*!< Base USB clock for USB0, USB PLL input only */\r
+#if defined(CHIP_LPC43XX)\r
+ CLK_BASE_PERIPH, /*!< Base clock for SGPIO */\r
+#else\r
+ CLK_BASE_RESERVED1,\r
+#endif\r
+ CLK_BASE_USB1, /*!< Base USB clock for USB1 */\r
+ CLK_BASE_MX, /*!< Base clock for CPU core */\r
+ CLK_BASE_SPIFI, /*!< Base clock for SPIFI */\r
+#if defined(CHIP_LPC43XX)\r
+ CLK_BASE_SPI, /*!< Base clock for SPI */\r
+#else\r
+ CLK_BASE_RESERVED2,\r
+#endif\r
+ CLK_BASE_PHY_RX, /*!< Base clock for PHY RX */\r
+ CLK_BASE_PHY_TX, /*!< Base clock for PHY TX */\r
+ CLK_BASE_APB1, /*!< Base clock for APB1 group */\r
+ CLK_BASE_APB3, /*!< Base clock for APB3 group */\r
+ CLK_BASE_LCD, /*!< Base clock for LCD pixel clock */\r
+#if defined(CHIP_LPC43XX)\r
+ CLK_BASE_VADC, /*!< Base clock for VADC */\r
+#else\r
+ CLK_BASE_RESERVED3,\r
+#endif\r
+ CLK_BASE_SDIO, /*!< Base clock for SDIO */\r
+ CLK_BASE_SSP0, /*!< Base clock for SSP0 */\r
+ CLK_BASE_SSP1, /*!< Base clock for SSP1 */\r
+ CLK_BASE_UART0, /*!< Base clock for UART0 */\r
+ CLK_BASE_UART1, /*!< Base clock for UART1 */\r
+ CLK_BASE_UART2, /*!< Base clock for UART2 */\r
+ CLK_BASE_UART3, /*!< Base clock for UART3 */\r
+ CLK_BASE_OUT, /*!< Base clock for CLKOUT pin */\r
+ CLK_BASE_RESERVED4,\r
+ CLK_BASE_RESERVED5,\r
+ CLK_BASE_RESERVED6,\r
+ CLK_BASE_RESERVED7,\r
+ CLK_BASE_APLL, /*!< Base clock for audio PLL */\r
+ CLK_BASE_CGU_OUT0, /*!< Base clock for CGUOUT0 pin */\r
+ CLK_BASE_CGU_OUT1, /*!< Base clock for CGUOUT1 pin */\r
+ CLK_BASE_LAST,\r
+ CLK_BASE_NONE = CLK_BASE_LAST\r
+} CHIP_CGU_BASE_CLK_T;\r
+\r
+/**\r
+ * @brief CGU dividers\r
+ * CGU dividers provide an extra clock state where a specific clock can be\r
+ * divided before being routed to a peripheral group. A divider accepts an\r
+ * input clock and then divides it. To use the divided clock for a base clock\r
+ * group, use the divider as the input clock for the base clock (for example,\r
+ * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).\r
+ */\r
+typedef enum CHIP_CGU_IDIV {\r
+ CLK_IDIV_A, /*!< CGU clock divider A */\r
+ CLK_IDIV_B, /*!< CGU clock divider B */\r
+ CLK_IDIV_C, /*!< CGU clock divider A */\r
+ CLK_IDIV_D, /*!< CGU clock divider D */\r
+ CLK_IDIV_E, /*!< CGU clock divider E */\r
+ CLK_IDIV_LAST\r
+} CHIP_CGU_IDIV_T;\r
+\r
+/**\r
+ * @brief Peripheral clocks\r
+ * Peripheral clocks are individual clocks routed to peripherals. Although\r
+ * multiple peripherals may share a same base clock, each peripheral's clock\r
+ * can be enabled or disabled individually. Some peripheral clocks also have\r
+ * additional dividers associated with them.\r
+ */\r
+typedef enum CHIP_CCU_CLK {\r
+ /* CCU1 clocks */\r
+ CLK_APB3_BUS, /*!< APB3 bus clock from base clock CLK_BASE_APB3 */\r
+ CLK_APB3_I2C1, /*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */\r
+ CLK_APB3_DAC, /*!< DAC peripheral clock from base clock CLK_BASE_APB3 */\r
+ CLK_APB3_ADC0, /*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */\r
+ CLK_APB3_ADC1, /*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */\r
+ CLK_APB3_CAN0, /*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */\r
+ CLK_APB1_BUS = 32, /*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */\r
+ CLK_APB1_MOTOCON, /*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */\r
+ CLK_APB1_I2C0, /*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */\r
+ CLK_APB1_I2S, /*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */\r
+ CLK_APB1_CAN1, /*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */\r
+ CLK_SPIFI = 64, /*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */\r
+ CLK_MX_BUS = 96, /*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */\r
+ CLK_MX_SPIFI, /*!< SPIFI register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_GPIO, /*!< GPIO register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_LCD, /*!< LCD register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_ETHERNET, /*!< ETHERNET register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_USB0, /*!< USB0 register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_EMC, /*!< EMC clock from base clock CLK_BASE_MX */\r
+ CLK_MX_SDIO, /*!< SDIO register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_DMA, /*!< DMA register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_MXCORE, /*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */\r
+ RESERVED_ALIGN = CLK_MX_MXCORE + 3,\r
+ CLK_MX_SCT, /*!< SCT register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_USB1, /*!< USB1 register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_EMC_DIV, /*!< ENC divider clock from base clock CLK_BASE_MX */\r
+ CLK_MX_FLASHA, /*!< FLASHA bank clock from base clock CLK_BASE_MX */\r
+ CLK_MX_FLASHB, /*!< FLASHB bank clock from base clock CLK_BASE_MX */\r
+#if defined(CHIP_LPC43XX)\r
+ CLK_M4_M0APP, /*!< M0 app CPU core clock from base clock CLK_BASE_MX */\r
+ CLK_MX_VADC, /*!< VADC clock from base clock CLK_BASE_MX */\r
+#else\r
+ CLK_RESERVED1,\r
+ CLK_RESERVED2,\r
+#endif\r
+ CLK_MX_EEPROM, /*!< EEPROM clock from base clock CLK_BASE_MX */\r
+ CLK_MX_WWDT = 128, /*!< WWDT register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_UART0, /*!< UART0 register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_UART1, /*!< UART1 register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_SSP0, /*!< SSP0 register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_TIMER0, /*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */\r
+ CLK_MX_TIMER1, /*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */\r
+ CLK_MX_SCU, /*!< SCU register/perigheral clock from base clock CLK_BASE_MX */\r
+ CLK_MX_CREG, /*!< CREG clock from base clock CLK_BASE_MX */\r
+ CLK_MX_RITIMER = 160, /*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */\r
+ CLK_MX_UART2, /*!< UART3 register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_UART3, /*!< UART4 register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_TIMER2, /*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */\r
+ CLK_MX_TIMER3, /*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */\r
+ CLK_MX_SSP1, /*!< SSP1 register clock from base clock CLK_BASE_MX */\r
+ CLK_MX_QEI, /*!< QEI register/perigheral clock from base clock CLK_BASE_MX */\r
+#if defined(CHIP_LPC43XX)\r
+ CLK_PERIPH_BUS = 192, /*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */\r
+ CLK_RESERVED3,\r
+ CLK_PERIPH_CORE, /*!< Peripheral core clock from base clock CLK_BASE_PERIPH */\r
+ CLK_PERIPH_SGPIO, /*!< SGPIO clock from base clock CLK_BASE_PERIPH */\r
+#else\r
+ CLK_RESERVED3 = 192,\r
+ CLK_RESERVED3A,\r
+ CLK_RESERVED4,\r
+ CLK_RESERVED5,\r
+#endif\r
+ CLK_USB0 = 224, /*!< USB0 clock from base clock CLK_BASE_USB0 */\r
+ CLK_USB1 = 256, /*!< USB1 clock from base clock CLK_BASE_USB1 */\r
+#if defined(CHIP_LPC43XX)\r
+ CLK_SPI = 288, /*!< SPI clock from base clock CLK_BASE_SPI */\r
+ CLK_VADC, /*!< VADC clock from base clock CLK_BASE_VADC */\r
+#else\r
+ CLK_RESERVED7 = 320,\r
+ CLK_RESERVED8,\r
+#endif\r
+ CLK_CCU1_LAST,\r
+\r
+ /* CCU2 clocks */\r
+ CLK_CCU2_START,\r
+ CLK_APLL = CLK_CCU2_START, /*!< Audio PLL clock from base clock CLK_BASE_APLL */\r
+ RESERVED_ALIGNB = CLK_CCU2_START + 31,\r
+ CLK_APB2_UART3, /*!< UART3 clock from base clock CLK_BASE_UART3 */\r
+ RESERVED_ALIGNC = CLK_CCU2_START + 63,\r
+ CLK_APB2_UART2, /*!< UART2 clock from base clock CLK_BASE_UART2 */\r
+ RESERVED_ALIGND = CLK_CCU2_START + 95,\r
+ CLK_APB0_UART1, /*!< UART1 clock from base clock CLK_BASE_UART1 */\r
+ RESERVED_ALIGNE = CLK_CCU2_START + 127,\r
+ CLK_APB0_UART0, /*!< UART0 clock from base clock CLK_BASE_UART0 */\r
+ RESERVED_ALIGNF = CLK_CCU2_START + 159,\r
+ CLK_APB2_SSP1, /*!< SSP1 clock from base clock CLK_BASE_SSP1 */\r
+ RESERVED_ALIGNG = CLK_CCU2_START + 191,\r
+ CLK_APB0_SSP0, /*!< SSP0 clock from base clock CLK_BASE_SSP0 */\r
+ RESERVED_ALIGNH = CLK_CCU2_START + 223,\r
+ CLK_APB2_SDIO, /*!< SDIO clock from base clock CLK_BASE_SDIO */\r
+ CLK_CCU2_LAST\r
+} CHIP_CCU_CLK_T;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CHIP_CLOCKS_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx basic chip inclusion file\r
+ *\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CHIP_LPC18XX_H_\r
+#define __CHIP_LPC18XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include "lpc_types.h"\r
+#include "sys_config.h"\r
+\r
+#ifndef CORE_M3\r
+#error CORE_M3 is not defined for the LPC18xx architecture\r
+#error CORE_M3 should be defined as part of your compiler define list\r
+#endif\r
+\r
+#ifndef CHIP_LPC18XX\r
+#error The LPC18XX Chip include path is used for this build, but\r
+#error CHIP_LPC18XX is not defined!\r
+#endif\r
+\r
+/** @defgroup IP_LPC18XX_FILES CHIP: LPC18XX Chip layer required IP layer drivers\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * This is a list of the IP drivers required for the LPC18XX device family.<br>\r
+ * (adc_001.c, adc_001.h) @ref IP_ADC_001<br>\r
+ * (atimer_001.c, atimer_001.h) @ref IP_ATIMER_001<br>\r
+ * (ccan_001.c, ccan_001.h) @ref IP_CCAN_001<br>\r
+ * (dac_001.c, dac_001.h) @ref IP_DAC_001<br>\r
+ * (emc_001.c, emc_001.h) @ref IP_EMC_001<br>\r
+ * (enet_001.c, enet_001.h) @ref IP_ENET_001<br>\r
+ * (gima_001.h) @ref IP_GIMA_001<br>\r
+ * (gpdma_001.c, gpdma_001.h) @ref IP_GPDMA_001<br>\r
+ * (gpiogrpint_001.c, gpiogrpint_001.h) @ref IP_GPIOGRPINT_001<br>\r
+ * (gpiopinint_001.c, gpiopinint_001.h) @ref IP_GPIOPININT_001<br>\r
+ * (gpio_001.h) @ref IP_GPIO_001<br>\r
+ * (i2c_001.c, i2c_001.h) @ref IP_I2C_001<br>\r
+ * (i2s_001.c, i2s_001.h) @ref IP_I2S_001<br>\r
+ * (lcd_001.c, lcd_001.h) @ref IP_LCD_001<br>\r
+ * (mcpwm_001.h) @ref IP_MCPWM_001<br>\r
+ * (pmc_001.h) @ref IP_PMC_001<br>\r
+ * (qei_001.h) @ref IP_QEI_001<br>\r
+ * (regfile_001.h) @ref IP_REGFILE_001<br>\r
+ * (ritimer_001.c, ritimer_001.h) @ref IP_RITIMER_001<br>\r
+ * (rtc_001.c, rtc_001.h) @ref IP_RTC_001<br>\r
+ * (sct_001.c, sct_001.h) @ref IP_SCT_001<br>\r
+ * (sdmmc_001.c, sdmmc_001.h) @ref IP_SDMMC_001<br>\r
+ * (ssp_001.c, ssp_001.h) @ref IP_SSP_001<br>\r
+ * (timer_001.c, timer_001.h) @ref IP_TIMER_001<br>\r
+ * (usart_001.c, usart_001.h) @ref IP_USART_001<br>\r
+ * (usbhs_001.h) @ref IP_USBHS_001<br>\r
+ * (wwdt_001.c, wwdt_001.h) @ref IP_WWDT_001<br>\r
+ * (eeprom_002.c, eeprom_002.h) @ref IP_EEPROM_002<br>\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#include "adc_001.h"\r
+#include "atimer_001.h"\r
+#include "ccan_001.h"\r
+#include "dac_001.h"\r
+#include "emc_001.h"\r
+#include "enet_001.h"\r
+#include "gima_001.h"\r
+#include "gpdma_001.h"\r
+#include "gpiogrpint_001.h"\r
+#include "gpiopinint_001.h"\r
+#include "gpio_001.h"\r
+#include "i2c_001.h"\r
+#include "i2s_001.h"\r
+#include "lcd_001.h"\r
+#include "mcpwm_001.h"\r
+#include "pmc_001.h"\r
+#include "qei_001.h"\r
+#include "regfile_001.h"\r
+#include "ritimer_001.h"\r
+#include "rtc_001.h"\r
+#include "sct_001.h"\r
+#include "sdmmc_001.h"\r
+#include "ssp_001.h"\r
+#include "timer_001.h"\r
+#include "usart_001.h"\r
+#include "usbhs_001.h"\r
+#include "wwdt_001.h"\r
+#include "rgu_18xx_43xx.h"\r
+#include "cguccu_18xx_43xx.h"\r
+#include "eeprom_002.h"\r
+\r
+/** @defgroup PERIPH_18XX_BASE CHIP: LPC18xx Peripheral addresses and register set declarations\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+#define LPC_SCT_BASE 0x40000000\r
+#define LPC_GPDMA_BASE 0x40002000\r
+#define LPC_SDMMC_BASE 0x40004000\r
+#define LPC_EMC_BASE 0x40005000\r
+#define LPC_USB0_BASE 0x40006000\r
+#define LPC_USB1_BASE 0x40007000\r
+#define LPC_LCD_BASE 0x40008000\r
+#define LPC_ETHERNET_BASE 0x40010000\r
+#define LPC_ATIMER_BASE 0x40040000\r
+#define LPC_REGFILE_BASE 0x40041000\r
+#define LPC_PMC_BASE 0x40042000\r
+#define LPC_CREG_BASE 0x40043000\r
+#define LPC_EVRT_BASE 0x40044000\r
+#define LPC_OTP_BASE 0x40045000\r
+#define LPC_RTC_BASE 0x40046000\r
+#define LPC_CGU_BASE 0x40050000\r
+#define LPC_CCU1_BASE 0x40051000\r
+#define LPC_CCU2_BASE 0x40052000\r
+#define LPC_RGU_BASE 0x40053000\r
+#define LPC_WWDT_BASE 0x40080000\r
+#define LPC_USART0_BASE 0x40081000\r
+#define LPC_USART2_BASE 0x400C1000\r
+#define LPC_USART3_BASE 0x400C2000\r
+#define LPC_UART1_BASE 0x40082000\r
+#define LPC_SSP0_BASE 0x40083000\r
+#define LPC_SSP1_BASE 0x400C5000\r
+#define LPC_TIMER0_BASE 0x40084000\r
+#define LPC_TIMER1_BASE 0x40085000\r
+#define LPC_TIMER2_BASE 0x400C3000\r
+#define LPC_TIMER3_BASE 0x400C4000\r
+#define LPC_SCU_BASE 0x40086000\r
+#define LPC_GPIO_PIN_INT_BASE 0x40087000\r
+#define LPC_GPIO_GROUP_INT0_BASE 0x40088000\r
+#define LPC_GPIO_GROUP_INT1_BASE 0x40089000\r
+#define LPC_MCPWM_BASE 0x400A0000\r
+#define LPC_I2C0_BASE 0x400A1000\r
+#define LPC_I2C1_BASE 0x400E0000\r
+#define LPC_I2S0_BASE 0x400A2000\r
+#define LPC_I2S1_BASE 0x400A3000\r
+#define LPC_C_CAN1_BASE 0x400A4000\r
+#define LPC_RITIMER_BASE 0x400C0000\r
+#define LPC_QEI_BASE 0x400C6000\r
+#define LPC_GIMA_BASE 0x400C7000\r
+#define LPC_DAC_BASE 0x400E1000\r
+#define LPC_C_CAN0_BASE 0x400E2000\r
+#define LPC_ADC0_BASE 0x400E3000\r
+#define LPC_ADC1_BASE 0x400E4000\r
+#define LPC_GPIO_PORT_BASE 0x400F4000\r
+#define LPC_SPI_BASE 0x40100000\r
+#define LPC_SGPIO_BASE 0x40101000\r
+#define LPC_EEPROM_BASE 0x4000E000\r
+\r
+/* Normalize types */\r
+typedef IP_SCT_001_T LPC_SCT_T;\r
+typedef IP_GPDMA_001_T LPC_GPDMA_T;\r
+typedef IP_SDMMC_001_T LPC_SDMMC_T;\r
+typedef IP_EMC_001_T LPC_EMC_T;\r
+typedef IP_USBHS_001_T LPC_USBHS_T;\r
+typedef IP_ENET_001_T LPC_ENET_T;\r
+typedef IP_ATIMER_001_T LPC_ATIMER_T;\r
+typedef IP_REGFILE_001_T LPC_REGFILE_T;\r
+typedef IP_PMC_001_T LPC_PMC_T;\r
+typedef IP_RTC_001_T LPC_RTC_T;\r
+typedef IP_WWDT_001_T LPC_WWDT_T;\r
+typedef IP_USART_001_T LPC_USART_T;\r
+typedef IP_SSP_001_T LPC_SSP_T;\r
+typedef IP_TIMER_001_T LPC_TIMER_T;\r
+typedef IP_GPIOPININT_001_T LPC_GPIOPININT_T;\r
+typedef IP_MCPWM_001_T LPC_MCPWM_T;\r
+typedef IP_I2C_001_T LPC_I2C_T;\r
+typedef IP_I2S_001_T LPC_I2S_T;\r
+typedef IP_CCAN_001_T LPC_CCAN_T;\r
+typedef IP_RITIMER_001_T LPC_RITIMER_T;\r
+typedef IP_QEI_001_T LPC_QEI_T;\r
+typedef IP_GIMA_001_T LPC_GIMA_T;\r
+typedef IP_DAC_001_T LPC_DAC_T;\r
+typedef IP_ADC_001_T LPC_ADC_T;\r
+typedef IP_GPIO_001_T LPC_GPIO_T;\r
+typedef IP_LCD_001_T LPC_LCD_T;\r
+typedef IP_EEPROM_002_T LPC_EEPROM_T;\r
+\r
+#define LPC_SCT ((IP_SCT_001_T *) LPC_SCT_BASE)\r
+#define LPC_GPDMA ((IP_GPDMA_001_T *) LPC_GPDMA_BASE)\r
+#define LPC_SDMMC ((IP_SDMMC_001_T *) LPC_SDMMC_BASE)\r
+#define LPC_EMC ((IP_EMC_001_T *) LPC_EMC_BASE)\r
+#define LPC_USB0 ((IP_USBHS_001_T *) LPC_USB0_BASE)\r
+#define LPC_USB1 ((IP_USBHS_001_T *) LPC_USB1_BASE)\r
+#define LPC_LCD ((IP_LCD_001_T *) LPC_LCD_BASE)\r
+#define LPC_ETHERNET ((IP_ENET_001_T *) LPC_ETHERNET_BASE)\r
+#define LPC_ATIMER ((IP_ATIMER_001_T *) LPC_ATIMER_BASE)\r
+#define LPC_REGFILE ((IP_REGFILE_001_T *) LPC_REGFILE_BASE)\r
+#define LPC_PMC ((IP_PMC_001_T *) LPC_PMC_BASE)\r
+#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)\r
+#define LPC_RTC ((IP_RTC_001_T *) LPC_RTC_BASE)\r
+#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)\r
+#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)\r
+#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)\r
+#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)\r
+#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)\r
+#define LPC_WWDT ((IP_WWDT_001_T *) LPC_WWDT_BASE)\r
+#define LPC_USART0 ((IP_USART_001_T *) LPC_USART0_BASE)\r
+#define LPC_USART2 ((IP_USART_001_T *) LPC_USART2_BASE)\r
+#define LPC_USART3 ((IP_USART_001_T *) LPC_USART3_BASE)\r
+#define LPC_UART1 ((IP_USART_001_T *) LPC_UART1_BASE)\r
+#define LPC_SSP0 ((IP_SSP_001_T *) LPC_SSP0_BASE)\r
+#define LPC_SSP1 ((IP_SSP_001_T *) LPC_SSP1_BASE)\r
+#define LPC_TIMER0 ((IP_TIMER_001_T *) LPC_TIMER0_BASE)\r
+#define LPC_TIMER1 ((IP_TIMER_001_T *) LPC_TIMER1_BASE)\r
+#define LPC_TIMER2 ((IP_TIMER_001_T *) LPC_TIMER2_BASE)\r
+#define LPC_TIMER3 ((IP_TIMER_001_T *) LPC_TIMER3_BASE)\r
+#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)\r
+#define LPC_GPIO_PIN_INT ((IP_GPIOPININT_001_T *) LPC_GPIO_PIN_INT_BASE)\r
+#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT0_BASE)\r
+#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT1_BASE)\r
+#define LPC_MCPWM ((IP_MCPWM_001_T *) LPC_MCPWM_BASE)\r
+#define LPC_I2C0 ((IP_I2C_001_T *) LPC_I2C0_BASE)\r
+#define LPC_I2C1 ((IP_I2C_001_T *) LPC_I2C1_BASE)\r
+#define LPC_I2S0 ((IP_I2S_001_T *) LPC_I2S0_BASE)\r
+#define LPC_I2S1 ((IP_I2S_001_T *) LPC_I2S1_BASE)\r
+#define LPC_C_CAN1 ((IP_CCAN_001_T *) LPC_C_CAN1_BASE)\r
+#define LPC_RITIMER ((IP_RITIMER_001_T *) LPC_RITIMER_BASE)\r
+#define LPC_QEI ((IP_QEI_001_T *) LPC_QEI_BASE)\r
+#define LPC_GIMA ((IP_GIMA_001_T *) LPC_GIMA_BASE)\r
+#define LPC_DAC ((IP_DAC_001_T *) LPC_DAC_BASE)\r
+#define LPC_C_CAN0 ((IP_CCAN_001_T *) LPC_C_CAN0_BASE)\r
+#define LPC_ADC0 ((IP_ADC_001_T *) LPC_ADC0_BASE)\r
+#define LPC_ADC1 ((IP_ADC_001_T *) LPC_ADC1_BASE)\r
+#define LPC_GPIO_PORT ((IP_GPIO_001_T *) LPC_GPIO_PORT_BASE)\r
+#define LPC_EEPROM ((IP_EEPROM_002_T *) LPC_EEPROM_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "clock_18xx_43xx.h"\r
+#include "gpio_18xx_43xx.h"\r
+#include "uart_18xx_43xx.h"\r
+#include "gpdma_18xx_43xx.h"\r
+#include "enet_18xx_43xx.h"\r
+#include "i2c_18xx_43xx.h"\r
+#include "i2s_18xx_43xx.h"\r
+#include "ssp_18xx_43xx.h"\r
+#include "rtc_18xx_43xx.h"\r
+#include "evrt_18xx_43xx.h"\r
+#include "atimer_18xx_43xx.h"\r
+#include "wwdt_18xx_43xx.h"\r
+#include "ritimer_18xx_43xx.h"\r
+#include "emc_18xx_43xx.h"\r
+#include "lcd_18xx_43xx.h"\r
+#include "adc_18xx_43xx.h"\r
+#include "dac_18xx_43xx.h"\r
+#include "sdif_18xx_43xx.h"\r
+#include "sdmmc_18xx_43xx.h"\r
+#include "timer_18xx_43xx.h"\r
+#include "creg_18xx_43xx.h"\r
+#include "scu_18xx_43xx.h"\r
+#include "sct_18xx_43xx.h"\r
+#include "ccan_18xx_43xx.h"\r
+#include "pmc_18xx_43xx.h"\r
+#include "otp_18xx_43xx.h"\r
+#include "aes_18xx_43xx.h"\r
+#include "eeprom_18xx_43xx.h"\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CHIP_LPC18XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC43xx basic chip inclusion file\r
+ *\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CHIP_LPC43XX_H_\r
+#define __CHIP_LPC43XX_H_\r
+\r
+#include "lpc_types.h"\r
+#include "sys_config.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#if !defined(CORE_M4) && !defined(CORE_M0)\r
+#error CORE_M4 or CORE_M0 is not defined for the LPC43xx architecture\r
+#error CORE_M4 or CORE_M0 should be defined as part of your compiler define list\r
+#endif\r
+\r
+#ifndef CHIP_LPC43XX\r
+#error The LPC43XX Chip include path is used for this build, but\r
+#error CHIP_LPC43XX is not defined!\r
+#endif\r
+\r
+/** @defgroup IP_LPC43XX_FILES CHIP: LPC43XX Chip layer required IP layer drivers\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * This is a list of the IP drivers required for the LPC43XX device family.<br>\r
+ * (adc_001.c, adc_001.h) @ref IP_ADC_001<br>\r
+ * (atimer_001.c, atimer_001.h) @ref IP_ATIMER_001<br>\r
+ * (ccan_001.c, ccan_001.h) @ref IP_CCAN_001<br>\r
+ * (dac_001.c, dac_001.h) @ref IP_DAC_001<br>\r
+ * (emc_001.c, emc_001.h) @ref IP_EMC_001<br>\r
+ * (enet_001.c, enet_001.h) @ref IP_ENET_001<br>\r
+ * (gima_001.h) @ref IP_GIMA_001<br>\r
+ * (gpdma_001.c, gpdma_001.h) @ref IP_GPDMA_001<br>\r
+ * (gpiogrpint_001.c, gpiogrpint_001.h) @ref IP_GPIOGRPINT_001<br>\r
+ * (gpiopinint_001.c, gpiopinint_001.h) @ref IP_GPIOPININT_001<br>\r
+ * (gpio_001.h) @ref IP_GPIO_001<br>\r
+ * (i2c_001.c, i2c_001.h) @ref IP_I2C_001<br>\r
+ * (i2s_001.c, i2s_001.h) @ref IP_I2S_001<br>\r
+ * (lcd_001.c, lcd_001.h) @ref IP_LCD_001<br>\r
+ * (mcpwm_001.h) @ref IP_MCPWM_001<br>\r
+ * (pmc_001.h) @ref IP_PMC_001<br>\r
+ * (qei_001.h) @ref IP_QEI_001<br>\r
+ * (regfile_001.h) @ref IP_REGFILE_001<br>\r
+ * (ritimer_001.c, ritimer_001.h) @ref IP_RITIMER_001<br>\r
+ * (rtc_001.c, rtc_001.h) @ref IP_RTC_001<br>\r
+ * (sct_001.c, sct_001.h) @ref IP_SCT_001<br>\r
+ * (sdmmc_001.c, sdmmc_001.h) @ref IP_SDMMC_001<br>\r
+ * (sgpio_001.h) @ref IP_SGPIO_001<br>\r
+ * (spi_001.h) @ref IP_SPI_001<br>\r
+ * (ssp_001.c, ssp_001.h) @ref IP_SSP_001<br>\r
+ * (timer_001.c, timer_001.h) @ref IP_TIMER_001<br>\r
+ * (usart_001.c, usart_001.h) @ref IP_USART_001<br>\r
+ * (usbhs_001.h) @ref IP_USBHS_001<br>\r
+ * (wwdt_001.c, wwdt_001.h) @ref IP_WWDT_001<br>\r
+ * (eeprom_002.c, eeprom_002.h) @ref IP_EEPROM_002<br>\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+#include "adc_001.h"\r
+#include "atimer_001.h"\r
+#include "ccan_001.h"\r
+#include "dac_001.h"\r
+#include "emc_001.h"\r
+#include "enet_001.h"\r
+#include "gima_001.h"\r
+#include "gpdma_001.h"\r
+#include "gpiogrpint_001.h"\r
+#include "gpiopinint_001.h"\r
+#include "gpio_001.h"\r
+#include "i2c_001.h"\r
+#include "i2s_001.h"\r
+#include "lcd_001.h"\r
+#include "mcpwm_001.h"\r
+#include "pmc_001.h"\r
+#include "qei_001.h"\r
+#include "regfile_001.h"\r
+#include "ritimer_001.h"\r
+#include "rtc_001.h"\r
+#include "sct_001.h"\r
+#include "sdmmc_001.h"\r
+#include "sgpio_001.h"\r
+#include "spi_001.h"\r
+#include "ssp_001.h"\r
+#include "timer_001.h"\r
+#include "usart_001.h"\r
+#include "usbhs_001.h"\r
+#include "wwdt_001.h"\r
+#include "rgu_18xx_43xx.h"\r
+#include "cguccu_18xx_43xx.h"\r
+#include "eeprom_002.h"\r
+\r
+/** @defgroup PERIPH_43XX_BASE CHIP: LPC43xx Peripheral addresses and register set declarations\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+#define LPC_SCT_BASE 0x40000000\r
+#define LPC_GPDMA_BASE 0x40002000\r
+#define LPC_SDMMC_BASE 0x40004000\r
+#define LPC_EMC_BASE 0x40005000\r
+#define LPC_USB0_BASE 0x40006000\r
+#define LPC_USB1_BASE 0x40007000\r
+#define LPC_LCD_BASE 0x40008000\r
+#define LPC_ETHERNET_BASE 0x40010000\r
+#define LPC_ATIMER_BASE 0x40040000\r
+#define LPC_REGFILE_BASE 0x40041000\r
+#define LPC_PMC_BASE 0x40042000\r
+#define LPC_CREG_BASE 0x40043000\r
+#define LPC_EVRT_BASE 0x40044000\r
+#define LPC_RTC_BASE 0x40046000\r
+#define LPC_CGU_BASE 0x40050000\r
+#define LPC_CCU1_BASE 0x40051000\r
+#define LPC_CCU2_BASE 0x40052000\r
+#define LPC_RGU_BASE 0x40053000\r
+#define LPC_WWDT_BASE 0x40080000\r
+#define LPC_USART0_BASE 0x40081000\r
+#define LPC_USART2_BASE 0x400C1000\r
+#define LPC_USART3_BASE 0x400C2000\r
+#define LPC_UART1_BASE 0x40082000\r
+#define LPC_SSP0_BASE 0x40083000\r
+#define LPC_SSP1_BASE 0x400C5000\r
+#define LPC_TIMER0_BASE 0x40084000\r
+#define LPC_TIMER1_BASE 0x40085000\r
+#define LPC_TIMER2_BASE 0x400C3000\r
+#define LPC_TIMER3_BASE 0x400C4000\r
+#define LPC_SCU_BASE 0x40086000\r
+#define LPC_GPIO_PIN_INT_BASE 0x40087000\r
+#define LPC_GPIO_GROUP_INT0_BASE 0x40088000\r
+#define LPC_GPIO_GROUP_INT1_BASE 0x40089000\r
+#define LPC_MCPWM_BASE 0x400A0000\r
+#define LPC_I2C0_BASE 0x400A1000\r
+#define LPC_I2C1_BASE 0x400E0000\r
+#define LPC_I2S0_BASE 0x400A2000\r
+#define LPC_I2S1_BASE 0x400A3000\r
+#define LPC_C_CAN1_BASE 0x400A4000\r
+#define LPC_RITIMER_BASE 0x400C0000\r
+#define LPC_QEI_BASE 0x400C6000\r
+#define LPC_GIMA_BASE 0x400C7000\r
+#define LPC_DAC_BASE 0x400E1000\r
+#define LPC_C_CAN0_BASE 0x400E2000\r
+#define LPC_ADC0_BASE 0x400E3000\r
+#define LPC_ADC1_BASE 0x400E4000\r
+#define LPC_GPIO_PORT_BASE 0x400F4000\r
+#define LPC_SPI_BASE 0x40100000\r
+#define LPC_SGPIO_BASE 0x40101000\r
+#define LPC_EEPROM_BASE 0x4000E000\r
+\r
+/* Normalize types */\r
+typedef IP_SCT_001_T LPC_SCT_T;\r
+typedef IP_GPDMA_001_T LPC_GPDMA_T;\r
+typedef IP_SDMMC_001_T LPC_SDMMC_T;\r
+typedef IP_EMC_001_T LPC_EMC_T;\r
+typedef IP_USBHS_001_T LPC_USBHS_T;\r
+typedef IP_ENET_001_T LPC_ENET_T;\r
+typedef IP_ATIMER_001_T LPC_ATIMER_T;\r
+typedef IP_REGFILE_001_T LPC_REGFILE_T;\r
+typedef IP_PMC_001_T LPC_PMC_T;\r
+typedef IP_RTC_001_T LPC_RTC_T;\r
+typedef IP_WWDT_001_T LPC_WWDT_T;\r
+typedef IP_USART_001_T LPC_USART_T;\r
+typedef IP_SSP_001_T LPC_SSP_T;\r
+typedef IP_TIMER_001_T LPC_TIMER_T;\r
+typedef IP_GPIOPININT_001_T LPC_GPIOPININT_T;\r
+typedef IP_MCPWM_001_T LPC_MCPWM_T;\r
+typedef IP_I2C_001_T LPC_I2C_T;\r
+typedef IP_I2S_001_T LPC_I2S_T;\r
+typedef IP_CCAN_001_T LPC_CCAN_T;\r
+typedef IP_RITIMER_001_T LPC_RITIMER_T;\r
+typedef IP_QEI_001_T LPC_QEI_T;\r
+typedef IP_GIMA_001_T LPC_GIMA_T;\r
+typedef IP_DAC_001_T LPC_DAC_T;\r
+typedef IP_ADC_001_T LPC_ADC_T;\r
+typedef IP_GPIO_001_T LPC_GPIO_T;\r
+typedef IP_SPI_001_T LPC_SPI_T;\r
+typedef IP_SGPIO_001_T LPC_SGPIO_T;\r
+typedef IP_LCD_001_T LPC_LCD_T;\r
+typedef IP_EEPROM_002_T LPC_EEPROM_T;\r
+\r
+#define LPC_SCT ((IP_SCT_001_T *) LPC_SCT_BASE)\r
+#define LPC_GPDMA ((IP_GPDMA_001_T *) LPC_GPDMA_BASE)\r
+#define LPC_SDMMC ((IP_SDMMC_001_T *) LPC_SDMMC_BASE)\r
+#define LPC_EMC ((IP_EMC_001_T *) LPC_EMC_BASE)\r
+#define LPC_USB0 ((IP_USBHS_001_T *) LPC_USB0_BASE)\r
+#define LPC_USB1 ((IP_USBHS_001_T *) LPC_USB1_BASE)\r
+#define LPC_LCD ((IP_LCD_001_T *) LPC_LCD_BASE)\r
+#define LPC_ETHERNET ((IP_ENET_001_T *) LPC_ETHERNET_BASE)\r
+#define LPC_ATIMER ((IP_ATIMER_001_T *) LPC_ATIMER_BASE)\r
+#define LPC_REGFILE ((IP_REGFILE_001_T *) LPC_REGFILE_BASE)\r
+#define LPC_PMC ((IP_PMC_001_T *) LPC_PMC_BASE)\r
+#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)\r
+#define LPC_RTC ((IP_RTC_001_T *) LPC_RTC_BASE)\r
+#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)\r
+#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)\r
+#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)\r
+#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)\r
+#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)\r
+#define LPC_WWDT ((IP_WWDT_001_T *) LPC_WWDT_BASE)\r
+#define LPC_USART0 ((IP_USART_001_T *) LPC_USART0_BASE)\r
+#define LPC_USART2 ((IP_USART_001_T *) LPC_USART2_BASE)\r
+#define LPC_USART3 ((IP_USART_001_T *) LPC_USART3_BASE)\r
+#define LPC_UART1 ((IP_USART_001_T *) LPC_UART1_BASE)\r
+#define LPC_SSP0 ((IP_SSP_001_T *) LPC_SSP0_BASE)\r
+#define LPC_SSP1 ((IP_SSP_001_T *) LPC_SSP1_BASE)\r
+#define LPC_TIMER0 ((IP_TIMER_001_T *) LPC_TIMER0_BASE)\r
+#define LPC_TIMER1 ((IP_TIMER_001_T *) LPC_TIMER1_BASE)\r
+#define LPC_TIMER2 ((IP_TIMER_001_T *) LPC_TIMER2_BASE)\r
+#define LPC_TIMER3 ((IP_TIMER_001_T *) LPC_TIMER3_BASE)\r
+#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)\r
+#define LPC_GPIO_PIN_INT ((IP_GPIOPININT_001_T *) LPC_GPIO_PIN_INT_BASE)\r
+#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT0_BASE)\r
+#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_001_T *) LPC_GPIO_GROUP_INT1_BASE)\r
+#define LPC_MCPWM ((IP_MCPWM_001_T *) LPC_MCPWM_BASE)\r
+#define LPC_I2C0 ((IP_I2C_001_T *) LPC_I2C0_BASE)\r
+#define LPC_I2C1 ((IP_I2C_001_T *) LPC_I2C1_BASE)\r
+#define LPC_I2S0 ((IP_I2S_001_T *) LPC_I2S0_BASE)\r
+#define LPC_I2S1 ((IP_I2S_001_T *) LPC_I2S1_BASE)\r
+#define LPC_C_CAN1 ((IP_CCAN_001_T *) LPC_C_CAN1_BASE)\r
+#define LPC_RITIMER ((IP_RITIMER_001_T *) LPC_RITIMER_BASE)\r
+#define LPC_QEI ((IP_QEI_001_T *) LPC_QEI_BASE)\r
+#define LPC_GIMA ((IP_GIMA_001_T *) LPC_GIMA_BASE)\r
+#define LPC_DAC ((IP_DAC_001_T *) LPC_DAC_BASE)\r
+#define LPC_C_CAN0 ((IP_CCAN_001_T *) LPC_C_CAN0_BASE)\r
+#define LPC_ADC0 ((IP_ADC_001_T *) LPC_ADC0_BASE)\r
+#define LPC_ADC1 ((IP_ADC_001_T *) LPC_ADC1_BASE)\r
+#define LPC_GPIO_PORT ((IP_GPIO_001_T *) LPC_GPIO_PORT_BASE)\r
+#define LPC_SPI ((IP_SPI_001_T *) LPC_SPI_BASE)\r
+#define LPC_SGPIO ((IP_SGPIO_001_T *) LPC_SGPIO_BASE)\r
+#define LPC_EEPROM ((IP_EEPROM_002_T *) LPC_EEPROM_BASE)\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "clock_18xx_43xx.h"\r
+#include "gpio_18xx_43xx.h"\r
+#include "scu_18xx_43xx.h"\r
+#include "sct_18xx_43xx.h"\r
+#include "uart_18xx_43xx.h"\r
+#include "gpdma_18xx_43xx.h"\r
+#include "enet_18xx_43xx.h"\r
+#include "rgu_18xx_43xx.h"\r
+#include "i2c_18xx_43xx.h"\r
+#include "i2s_18xx_43xx.h"\r
+#include "ssp_18xx_43xx.h"\r
+#include "rtc_18xx_43xx.h"\r
+#include "evrt_18xx_43xx.h"\r
+#include "atimer_18xx_43xx.h"\r
+#include "wwdt_18xx_43xx.h"\r
+#include "ritimer_18xx_43xx.h"\r
+#include "emc_18xx_43xx.h"\r
+#include "lcd_18xx_43xx.h"\r
+#include "adc_18xx_43xx.h"\r
+#include "dac_18xx_43xx.h"\r
+#include "timer_18xx_43xx.h"\r
+#include "sdif_18xx_43xx.h"\r
+#include "sdmmc_18xx_43xx.h"\r
+#include "fpu_init.h"\r
+#include "creg_18xx_43xx.h"\r
+#include "ccan_18xx_43xx.h"\r
+#include "pmc_18xx_43xx.h"\r
+#include "otp_18xx_43xx.h"\r
+#include "aes_18xx_43xx.h"\r
+#include "eeprom_18xx_43xx.h"\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CHIP_LPC43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx clock driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licenser disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "chip.h"\r
+\r
+/*****************************************************************************\r
+ * Private types/enumerations/variables\r
+ ****************************************************************************/\r
+\r
+/* Maps a peripheral clock to it's base clock */\r
+typedef struct {\r
+ CHIP_CCU_CLK_T clkstart;\r
+ CHIP_CCU_CLK_T clkend;\r
+ CHIP_CGU_BASE_CLK_T clkbase;\r
+} CLK_PERIPH_TO_BASE_T;\r
+static const CLK_PERIPH_TO_BASE_T periph_to_base[] = {\r
+ {CLK_APB3_BUS, CLK_APB3_CAN0, CLK_BASE_APB3},\r
+ {CLK_APB1_BUS, CLK_APB1_CAN1, CLK_BASE_APB1},\r
+ {CLK_SPIFI, CLK_SPIFI, CLK_BASE_SPIFI},\r
+ {CLK_MX_BUS, CLK_MX_QEI, CLK_BASE_MX},\r
+#if 0\r
+#if defined(CHIP_LPC43XX)\r
+ {CLK_PERIPH_BUS, CLK_PERIPH_SGPIO, CLK_BASE_PERIPH},\r
+#endif\r
+ {CLK_USB0, CLK_USB0, CLK_BASE_USB0},\r
+ {CLK_USB1, CLK_USB1, CLK_BASE_USB1},\r
+#if defined(CHIP_LPC43XX)\r
+ {CLK_SPI, CLK_SPI, CLK_BASE_SPI},\r
+ {CLK_VADC, CLK_VADC, CLK_BASE_VADC},\r
+#endif\r
+ {CLK_APLL, CLK_APLL, CLK_BASE_APLL},\r
+ {CLK_APB2_UART3, CLK_APB2_UART3, CLK_BASE_UART3},\r
+ {CLK_APB2_UART2, CLK_APB2_UART2, CLK_BASE_UART2},\r
+ {CLK_APB2_UART1, CLK_APB2_UART1, CLK_BASE_UART1},\r
+ {CLK_APB2_UART0, CLK_APB2_UART0, CLK_BASE_UART0},\r
+ {CLK_APB2_SSP1, CLK_APB2_SSP1, CLK_BASE_SSP1},\r
+ {CLK_APB2_SSP0, CLK_APB2_SSP0, CLK_BASE_SSP0},\r
+ {CLK_APB2_SDIO, CLK_APB2_SDIO, CLK_BASE_SDIO},\r
+ {CLK_CCU2_LAST, CLK_CCU2_LAST, CLK_BASE_NONE}\r
+#endif\r
+};\r
+\r
+/*****************************************************************************\r
+ * Public types/enumerations/variables\r
+ ****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Private functions\r
+ ****************************************************************************/\r
+\r
+/* Test PLL input values for a specific frequency range */\r
+static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t TestMult, uint32_t MinHz, uint32_t MaxHz)\r
+{\r
+ uint32_t TestHz = TestMult * InputHz;\r
+\r
+ if ((TestHz < MinHz) || (TestHz > MAX_CLOCK_FREQ) || (TestHz > MaxHz)) {\r
+ TestHz = 0;\r
+ }\r
+\r
+ return TestHz;\r
+}\r
+\r
+/* Returns clock rate out of a divider */\r
+static uint32_t Chip_Clock_GetDivRate(CHIP_CGU_CLKIN_T clock, CHIP_CGU_IDIV_T divider)\r
+{\r
+ CHIP_CGU_CLKIN_T input;\r
+ uint32_t div;\r
+\r
+ input = Chip_Clock_GetDividerSource(divider);\r
+ div = Chip_Clock_GetDividerDivisor(divider);\r
+ return Chip_Clock_GetClockInputHz(input) / (div + 1);\r
+}\r
+\r
+/* Finds the base clock for the peripheral clock */\r
+static CHIP_CGU_BASE_CLK_T Chip_Clock_FindBaseClock(CHIP_CCU_CLK_T clk)\r
+{\r
+ CHIP_CGU_BASE_CLK_T baseclk = CLK_BASE_NONE;\r
+ int i = 0;\r
+\r
+ while ((baseclk == CLK_BASE_NONE) && (periph_to_base[i].clkbase != baseclk)) {\r
+ if ((clk >= periph_to_base[i].clkstart) && (clk <= periph_to_base[i].clkend)) {\r
+ baseclk = periph_to_base[i].clkbase;\r
+ }\r
+ else {\r
+ i++;\r
+ }\r
+ }\r
+\r
+ return baseclk;\r
+}\r
+\r
+/*****************************************************************************\r
+ * Public functions\r
+ ****************************************************************************/\r
+\r
+/* Enables the crystal oscillator */\r
+void Chip_Clock_EnableCrystal(void)\r
+{\r
+ uint32_t OldCrystalConfig = LPC_CGU->XTAL_OSC_CTRL;\r
+\r
+ /* Clear bypass mode */\r
+ OldCrystalConfig &= (~2);\r
+ if (OldCrystalConfig != LPC_CGU->XTAL_OSC_CTRL) {\r
+ LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;\r
+ }\r
+\r
+ /* Enable crystal oscillator */\r
+ OldCrystalConfig &= (~1);\r
+ if (CRYSTAL_MAIN_FREQ_IN >= 20000000) {\r
+ OldCrystalConfig |= 4; /* Set high frequency mode */\r
+\r
+ }\r
+ LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;\r
+}\r
+\r
+/* Disables the crystal oscillator */\r
+void Chip_Clock_DisableCrystal(void)\r
+{\r
+ /* Disable crystal oscillator */\r
+ LPC_CGU->XTAL_OSC_CTRL &= (~1);\r
+}\r
+\r
+/* Configures the main PLL */\r
+uint32_t Chip_Clock_SetupMainPLLHz(CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz)\r
+{\r
+ uint32_t freqin = Chip_Clock_GetClockInputHz(Input);\r
+ uint32_t Mult, LastMult, MultEnd;\r
+ uint32_t freqout, freqout2;\r
+\r
+ if (DesiredHz != 0xFFFFFFFF) {\r
+ /* Test DesiredHz rounded down */\r
+ Mult = DesiredHz / freqin;\r
+ freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);\r
+\r
+ /* Test DesiredHz rounded up */\r
+ Mult++;\r
+ freqout2 = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);\r
+\r
+ if (freqout && !freqout2) { /* rounding up is no good? set first multiplier */\r
+ Mult--;\r
+ return Chip_Clock_SetupMainPLLMult(Input, Mult);\r
+ }\r
+ if (!freqout && freqout2) { /* didn't work until rounded up? set 2nd multiplier */\r
+ return Chip_Clock_SetupMainPLLMult(Input, Mult);\r
+ }\r
+\r
+ if (freqout && freqout2) { /* either multiplier okay? choose closer one */\r
+ if ((DesiredHz - freqout) > (freqout2 - DesiredHz)) {\r
+ Mult--;\r
+ return Chip_Clock_SetupMainPLLMult(Input, Mult);\r
+ }\r
+ else {\r
+ return Chip_Clock_SetupMainPLLMult(Input, Mult);\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Neither multiplier okay? Try to start at MinHz and increment.\r
+ This should find the highest multiplier that is still good */\r
+ Mult = MinHz / freqin;\r
+ MultEnd = MaxHz / freqin;\r
+ LastMult = 0;\r
+ while (1) {\r
+ freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz);\r
+\r
+ if (freqout) {\r
+ LastMult = Mult;\r
+ }\r
+\r
+ if (Mult >= MultEnd) {\r
+ break;\r
+ }\r
+ Mult++;\r
+ }\r
+\r
+ if (LastMult) {\r
+ return Chip_Clock_SetupMainPLLMult(Input, LastMult);\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/* Directly set the PLL multipler */\r
+uint32_t Chip_Clock_SetupMainPLLMult(CHIP_CGU_CLKIN_T Input, uint32_t mult)\r
+{\r
+ uint32_t freq = Chip_Clock_GetClockInputHz(Input);\r
+ uint32_t msel = 0, nsel = 0, psel = 0, pval = 1;\r
+ uint32_t PLLReg = LPC_CGU->PLL1_CTRL;\r
+\r
+ freq *= mult;\r
+ msel = mult - 1;\r
+\r
+ PLLReg &= ~(0x1F << 24);/* clear input source bits */\r
+ PLLReg |= Input << 24; /* set input source bits to parameter */\r
+\r
+ /* Clear other PLL input bits */\r
+ PLLReg &= ~((1 << 6) | /* FBSEL */\r
+ (1 << 1) | /* BYPASS */\r
+ (1 << 7) | /* DIRECT */\r
+ (0x03 << 8) | (0xFF << 16) | (0x03 << 12)); /* PSEL, MSEL, NSEL- divider ratios */\r
+\r
+ if (freq < 156000000) {\r
+ /* psel is encoded such that 0=1, 1=2, 2=4, 3=8 */\r
+ while ((2 * (pval) * freq) < 156000000) {\r
+ psel++;\r
+ pval *= 2;\r
+ }\r
+\r
+ PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 6); /* dividers + FBSEL */\r
+ }\r
+ else if (freq < 320000000) {\r
+ PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 7) | (1 << 6); /* dividers + DIRECT + FBSEL */\r
+ }\r
+ else {\r
+ Chip_Clock_DisableMainPLL();\r
+ return 0;\r
+ }\r
+ LPC_CGU->PLL1_CTRL = PLLReg & ~(1 << 0);\r
+\r
+ return freq;\r
+}\r
+\r
+/* Returns the frequency of the main PLL */\r
+uint32_t Chip_Clock_GetMainPLLHz(void)\r
+{\r
+ uint32_t PLLReg = LPC_CGU->PLL1_CTRL;\r
+ uint32_t freq = Chip_Clock_GetClockInputHz((CHIP_CGU_CLKIN_T) ((PLLReg >> 24) & 0xF));\r
+ uint32_t msel, nsel, psel, direct, fbsel;\r
+ uint32_t m, n, p;\r
+ const uint8_t ptab[] = {1, 2, 4, 8};\r
+\r
+ /* No lock? */\r
+ if (!(LPC_CGU->PLL1_STAT & 1)) {\r
+ return 0;\r
+ }\r
+\r
+ msel = (PLLReg >> 16) & 0xFF;\r
+ nsel = (PLLReg >> 12) & 0x3;\r
+ psel = (PLLReg >> 8) & 0x3;\r
+ direct = (PLLReg >> 7) & 0x1;\r
+ fbsel = (PLLReg >> 6) & 0x1;\r
+\r
+ m = msel + 1;\r
+ n = nsel + 1;\r
+ p = ptab[psel];\r
+\r
+ if (direct || fbsel) {\r
+ return m * (freq / n);\r
+ }\r
+\r
+ return (m / (2 * p)) * (freq / n);\r
+}\r
+\r
+/* Disables the main PLL */\r
+void Chip_Clock_DisableMainPLL(void)\r
+{\r
+ /* power down main PLL */\r
+ LPC_CGU->PLL1_CTRL |= 1;\r
+}\r
+\r
+/* Disables the main PLL */\r
+void Chip_Clock_EnableMainPLL(void)\r
+{\r
+ /* power down main PLL */\r
+ LPC_CGU->PLL1_CTRL &= ~1;\r
+}\r
+\r
+/* Returns the lock status of the main PLL */\r
+bool Chip_Clock_MainPLLLocked(void)\r
+{\r
+ /* Return true if locked */\r
+ return (bool) (LPC_CGU->PLL1_STAT & 1);\r
+}\r
+\r
+/* Sets up a CGU clock divider and it's input clock */\r
+void Chip_Clock_SetDivider(CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor)\r
+{\r
+ uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];\r
+\r
+ Divisor--;\r
+\r
+ if (Input != CLKINPUT_PD) {\r
+ /* Mask off bits that need to changes */\r
+ reg &= ~((0x1F << 24) | 1 | (0xF << 2));\r
+\r
+ /* Enable autoblocking, clear PD, and set clock source & divisor */\r
+ LPC_CGU->IDIV_CTRL[Divider] = reg | (1 << 11) | (Input << 24) | (Divisor << 2);\r
+ }\r
+ else {\r
+ LPC_CGU->IDIV_CTRL[Divider] = reg | 1; /* Power down this divider */\r
+ }\r
+}\r
+\r
+/* Gets a CGU clock divider source */\r
+CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource(CHIP_CGU_IDIV_T Divider)\r
+{\r
+ uint32_t reg = LPC_CGU->IDIV_CTRL[Divider];\r
+\r
+ if (reg & 1) { /* divider is powered down */\r
+ return CLKINPUT_PD;\r
+ }\r
+\r
+ return (CHIP_CGU_CLKIN_T) ((reg >> 24) & 0x1F);\r
+}\r
+\r
+/* Gets a CGU clock divider divisor */\r
+uint32_t Chip_Clock_GetDividerDivisor(CHIP_CGU_IDIV_T Divider)\r
+{\r
+ return (CHIP_CGU_CLKIN_T) ((LPC_CGU->IDIV_CTRL[Divider] >> 2) & 0xF);\r
+}\r
+\r
+/* Returns the frequency of the specified input clock source */\r
+uint32_t Chip_Clock_GetClockInputHz(CHIP_CGU_CLKIN_T input)\r
+{\r
+ uint32_t rate = 0;\r
+\r
+ switch (input) {\r
+ case CLKIN_32K:\r
+ rate = CRYSTAL_32K_FREQ_IN;\r
+ break;\r
+\r
+ case CLKIN_IRC:\r
+ rate = CGU_IRC_FREQ;\r
+ break;\r
+\r
+ case CLKIN_ENET_RX:\r
+#if defined(USE_RMII)\r
+ /* In RMII mode, this clock is not attached */\r
+#else\r
+ /* MII mode requires 25MHz clock */\r
+ rate = 25000000;\r
+#endif\r
+ break;\r
+\r
+ case CLKIN_ENET_TX:\r
+#if defined(USE_RMII)\r
+ /* MII mode requires 50MHz clock */\r
+ rate = 50000000;\r
+#else\r
+ /* MII mode requires 25MHz clock */\r
+ rate = 25000000;\r
+#endif\r
+ break;\r
+\r
+ case CLKIN_CLKIN:\r
+#if defined(EXTERNAL_CLKIN_FREQ_IN)\r
+ rate = EXTERNAL_CLKIN_FREQ_IN;\r
+#else\r
+ /* Assume no clock in if a rate wasn't defined */\r
+#endif\r
+ break;\r
+\r
+ case CLKIN_CRYSTAL:\r
+ rate = CRYSTAL_MAIN_FREQ_IN;\r
+ break;\r
+\r
+ case CLKIN_USBPLL:\r
+ rate = CGU_USB_PLL_RATE;\r
+ break;\r
+\r
+ case CLKIN_AUDIOPLL:\r
+ rate = CGU_AUDIO_PLL_RATE;\r
+ break;\r
+\r
+ case CLKIN_MAINPLL:\r
+ rate = Chip_Clock_GetMainPLLHz();\r
+ break;\r
+\r
+ case CLKIN_IDIVA:\r
+ rate = Chip_Clock_GetDivRate(input, CLK_IDIV_A);\r
+ break;\r
+\r
+ case CLKIN_IDIVB:\r
+ rate = Chip_Clock_GetDivRate(input, CLK_IDIV_B);\r
+ break;\r
+\r
+ case CLKIN_IDIVC:\r
+ rate = Chip_Clock_GetDivRate(input, CLK_IDIV_C);\r
+ break;\r
+\r
+ case CLKIN_IDIVD:\r
+ rate = Chip_Clock_GetDivRate(input, CLK_IDIV_D);\r
+ break;\r
+\r
+ case CLKIN_IDIVE:\r
+ rate = Chip_Clock_GetDivRate(input, CLK_IDIV_E);\r
+ break;\r
+\r
+ case CLKINPUT_PD:\r
+ rate = 0;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return rate;\r
+}\r
+\r
+/* Returns the frequency of the specified base clock source */\r
+uint32_t Chip_Clock_GetBaseClocktHz(CHIP_CGU_BASE_CLK_T clock)\r
+{\r
+ return Chip_Clock_GetClockInputHz(Chip_Clock_GetBaseClock(clock));\r
+}\r
+\r
+/* Sets a CGU Base Clock clock source */\r
+void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn)\r
+{\r
+ uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];\r
+\r
+ if (BaseClock < CLK_BASE_NONE) {\r
+ if (Input != CLKINPUT_PD) {\r
+ /* Mask off fields we plan to update */\r
+ reg &= ~((0x1F << 24) | 1 | (1 << 11));\r
+\r
+ if (autoblocken) {\r
+ reg |= (1 << 11);\r
+ }\r
+ if (powerdn) {\r
+ reg |= (1 << 0);\r
+ }\r
+\r
+ /* Set clock source */\r
+ reg |= (Input << 24);\r
+\r
+ LPC_CGU->BASE_CLK[BaseClock] = reg;\r
+ }\r
+ }\r
+ else {\r
+ LPC_CGU->BASE_CLK[BaseClock] = reg | 1; /* Power down this base clock */\r
+ }\r
+}\r
+\r
+/* Reads CGU Base Clock clock source information */\r
+void Chip_Clock_GetBaseClockOpts(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken,\r
+ bool *powerdn)\r
+{\r
+ uint32_t reg = LPC_CGU->BASE_CLK[BaseClock];\r
+ CHIP_CGU_CLKIN_T ClkIn = (CHIP_CGU_CLKIN_T) ((reg >> 24) & 0x1F );\r
+\r
+ if (BaseClock < CLK_BASE_NONE) {\r
+ /* Get settings */\r
+ *Input = ClkIn;\r
+ *autoblocken = (reg & (1 << 11)) ? true : false;\r
+ *powerdn = (reg & (1 << 0)) ? true : false;\r
+ }\r
+ else {\r
+ *Input = CLKINPUT_PD;\r
+ *powerdn = true;\r
+ *autoblocken = true;\r
+ }\r
+}\r
+\r
+/*Enables a base clock source */\r
+void Chip_Clock_EnableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock)\r
+{\r
+ if (BaseClock < CLK_BASE_NONE) {\r
+ LPC_CGU->BASE_CLK[BaseClock] &= ~1;\r
+ }\r
+}\r
+\r
+/* Disables a base clock source */\r
+void Chip_Clock_DisableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock)\r
+{\r
+ if (BaseClock < CLK_BASE_NONE) {\r
+ LPC_CGU->BASE_CLK[BaseClock] |= 1;\r
+ }\r
+}\r
+\r
+/* Returns base clock enable state */\r
+bool Chip_Clock_IsBaseClockEnabled(CHIP_CGU_BASE_CLK_T BaseClock)\r
+{\r
+ bool enabled;\r
+\r
+ if (BaseClock < CLK_BASE_NONE) {\r
+ enabled = (bool) ((LPC_CGU->BASE_CLK[BaseClock] & 1) == 0);\r
+ }\r
+ else {\r
+ enabled = false;\r
+ }\r
+\r
+ return enabled;\r
+}\r
+\r
+/* Gets a CGU Base Clock clock source */\r
+CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock)\r
+{\r
+ uint32_t reg;\r
+\r
+ if (BaseClock >= CLK_BASE_NONE) {\r
+ return CLKINPUT_PD;\r
+ }\r
+\r
+ reg = LPC_CGU->BASE_CLK[BaseClock];\r
+\r
+ /* base clock is powered down? */\r
+ if (reg & 1) {\r
+ return CLKINPUT_PD;\r
+ }\r
+\r
+ return (CHIP_CGU_CLKIN_T) ((reg >> 24) & 0x1F);\r
+}\r
+\r
+/* Enables a peripheral clock and sets clock states */\r
+void Chip_Clock_EnableOpts(CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div)\r
+{\r
+ uint32_t reg = 1;\r
+\r
+ if (autoen) {\r
+ reg |= (1 << 1);\r
+ }\r
+ if (wakeupen) {\r
+ reg |= (1 << 2);\r
+ }\r
+\r
+ /* Not all clocks support a divider, but we won't check that here. Only\r
+ dividers of 1 and 2 are allowed. Assume 1 if not 2 */\r
+ if (div == 2) {\r
+ reg |= (1 << 5);\r
+ }\r
+\r
+ /* Setup peripheral clock and start running */\r
+ if (clk >= CLK_CCU2_START) {\r
+ LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG = reg;\r
+ }\r
+ else {\r
+ LPC_CCU1->CLKCCU[clk].CFG = reg;\r
+ }\r
+}\r
+\r
+/* Enables a peripheral clock */\r
+void Chip_Clock_Enable(CHIP_CCU_CLK_T clk)\r
+{\r
+ /* Start peripheral clock running */\r
+ if (clk >= CLK_CCU2_START) {\r
+ LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG |= 1;\r
+ }\r
+ else {\r
+ LPC_CCU1->CLKCCU[clk].CFG |= 1;\r
+ }\r
+}\r
+\r
+/* Disables a peripheral clock */\r
+void Chip_Clock_Disable(CHIP_CCU_CLK_T clk)\r
+{\r
+ /* Stop peripheral clock */\r
+ if (clk >= CLK_CCU2_START) {\r
+ LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG &= ~1;\r
+ }\r
+ else {\r
+ LPC_CCU1->CLKCCU[clk].CFG &= ~1;\r
+ }\r
+}\r
+\r
+/**\r
+ * Disable all branch output clocks with wake up mechanism enabled.\r
+ * Only the clocks with wake up mechanism enabled will be disabled &\r
+ * power down sequence started\r
+ */\r
+void Chip_Clock_StartPowerDown(void)\r
+{\r
+ /* Set Power Down bit */\r
+ LPC_CCU1->PM = 1;\r
+ LPC_CCU2->PM = 1;\r
+}\r
+\r
+/**\r
+ * Enable all branch output clocks after the wake up event.\r
+ * Only the clocks with wake up mechanism enabled will be enabled\r
+ */\r
+void Chip_Clock_ClearPowerDown(void)\r
+{\r
+ /* Clear Power Down bit */\r
+ LPC_CCU1->PM = 0;\r
+ LPC_CCU2->PM = 0;\r
+}\r
+\r
+/* Returns a peripheral clock rate */\r
+uint32_t Chip_Clock_GetRate(CHIP_CCU_CLK_T clk)\r
+{\r
+ CHIP_CGU_BASE_CLK_T baseclk;\r
+ uint32_t reg, div, rate;\r
+\r
+ /* Get CCU config register for clock */\r
+ if (clk >= CLK_CCU2_START) {\r
+ reg = LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG;\r
+ }\r
+ else {\r
+ reg = LPC_CCU1->CLKCCU[clk].CFG;\r
+ }\r
+\r
+ /* Is the clock enabled? */\r
+ if (reg & 1) {\r
+ /* Get base clock for this peripheral clock */\r
+ baseclk = Chip_Clock_FindBaseClock(clk);\r
+\r
+ /* Get base clock rate */\r
+ rate = Chip_Clock_GetBaseClocktHz(baseclk);\r
+\r
+ /* Get divider for this clock */\r
+ if (((reg >> 5) & 0x7) == 0) {\r
+ div = 1;\r
+ }\r
+ else {\r
+ div = 2;/* No other dividers supported */\r
+\r
+ }\r
+ rate = rate / div;\r
+ }\r
+ else {\r
+ rate = 0;\r
+ }\r
+\r
+ return rate;\r
+}\r
+\r
+/* Sets up the audio or USB PLL */\r
+void Chip_Clock_SetupPLL(CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum,\r
+ const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup)\r
+{\r
+ uint32_t reg = pPLLSetup->ctrl | (Input << 24);\r
+ /* Setup from passed values */\r
+ LPC_CGU->PLL[pllnum].PLL_CTRL = reg;\r
+ LPC_CGU->PLL[pllnum].PLL_MDIV = pPLLSetup->mdiv;\r
+ LPC_CGU->PLL[pllnum].PLL_NP_DIV = pPLLSetup->ndiv;\r
+\r
+ /* Fractional divider is for audio PLL only */\r
+ if (pllnum == pllnum) {\r
+ LPC_CGU->PLL0AUDIO_FRAC = pPLLSetup->fract;\r
+ }\r
+}\r
+\r
+/* Enables the audio or USB PLL */\r
+void Chip_Clock_EnablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum)\r
+{\r
+ LPC_CGU->PLL[pllnum].PLL_CTRL &= ~1;\r
+}\r
+\r
+/* Disables the audio or USB PLL */\r
+void Chip_Clock_DisablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum)\r
+{\r
+ LPC_CGU->PLL[pllnum].PLL_CTRL |= 1;\r
+}\r
+\r
+/* Returns the PLL status */\r
+uint32_t Chip_Clock_GetPLLStatus(CHIP_CGU_USB_AUDIO_PLL_T pllnum)\r
+{\r
+ return LPC_CGU->PLL[pllnum].PLL_STAT;\r
+}\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx clock driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licenser disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CLOCK_18XX_43XX_H_\r
+#define __CLOCK_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup CLOCK_18XX_43XX CHIP: LPC18xx/43xx Clock Driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CLOCK_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Clock Driver driver options\r
+ * @ingroup CLOCK_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS\r
+ * The clock driver has options that configure it's operation at build-time.<br>\r
+ *\r
+ * <b>MAX_CLOCK_FREQ</b><br>\r
+ * This define, when set, identifies the running CPU clock rate of the system\r
+ * (change this to alter running CPU speed).<br>\r
+ * When this is not defined, The maximum clock rate for the CPU is used.<br>\r
+ *\r
+ * <b>CRYSTAL_MAIN_FREQ_IN</b><br>\r
+ * This define is the external crystal frequency used for the main oscillator.<br>\r
+ *\r
+ * <b>EXTCLKIN_FREQ_IN</b><br>\r
+ * This define is rate of the input clock signal on the CLKIN input of the device\r
+ * (on some parts only).<br>\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Internal oscillator frequency */\r
+#define CGU_IRC_FREQ (12000000)\r
+\r
+#ifndef MAX_CLOCK_FREQ\r
+#if defined(CHIP_LPC43XX)\r
+#define MAX_CLOCK_FREQ (204000000)\r
+#else\r
+#define MAX_CLOCK_FREQ (180000000)\r
+#endif\r
+#endif /* MAX_CLOCK_FREQ */\r
+\r
+/**\r
+ * @brief Enables the crystal oscillator\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_EnableCrystal(void);\r
+\r
+/**\r
+ * @brief Disables the crystal oscillator\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_DisableCrystal(void);\r
+\r
+/**\r
+ * @brief Configures the main PLL\r
+ * @param Input : Which clock input to use as the PLL input\r
+ * @param MinHz : Minimum allowable PLL output frequency\r
+ * @param DesiredHz : Desired PLL output frequency\r
+ * @param MaxHz : Maximum allowable PLL output frequency\r
+ * @return Frequency of the PLL in Hz\r
+ * Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz\r
+ * and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if\r
+ * the PLL is locked.\r
+ */\r
+uint32_t Chip_Clock_SetupMainPLLHz(CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz);\r
+\r
+/**\r
+ * @brief Directly set the PLL multipler\r
+ * @param Input : Which clock input to use as the PLL input\r
+ * @param mult : How many times to multiply the input clock\r
+ * @return Frequency of the PLL in Hz\r
+ */\r
+uint32_t Chip_Clock_SetupMainPLLMult(CHIP_CGU_CLKIN_T Input, uint32_t mult);\r
+\r
+/**\r
+ * @brief Returns the frequency of the main PLL\r
+ * @return Frequency of the PLL in Hz\r
+ * Returns zero if the main PLL is not running.\r
+ */\r
+uint32_t Chip_Clock_GetMainPLLHz(void);\r
+\r
+/**\r
+ * @brief Disables the main PLL\r
+ * @return none\r
+ * Make sure the main PLL is not needed to clock the part before disabling it.\r
+ * Saves power if the main PLL is not needed.\r
+ */\r
+void Chip_Clock_DisableMainPLL(void);\r
+\r
+/**\r
+ * @brief Enbles the main PLL\r
+ * @return none\r
+ * Make sure the main PLL is enabled.\r
+ */\r
+void Chip_Clock_EnableMainPLL(void);\r
+\r
+/**\r
+ * @brief Returns the lock status of the main PLL\r
+ * @return true if the PLL is locked, otherwise false\r
+ * The main PLL should be locked prior to using it as a clock input for a base clock.\r
+ */\r
+bool Chip_Clock_MainPLLLocked(void);\r
+\r
+/**\r
+ * @brief Sets up a CGU clock divider and it's input clock\r
+ * @param Divider : CHIP_CGU_IDIV_T value indicating which divider to configure\r
+ * @param Input : CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider\r
+ * @param Divisor : value to divide Input clock by\r
+ * @return Nothing\r
+ * Maximum divider on A = 4, B/C/D = 16, E = 256.\r
+ * See the user manual for allowable combinations for input clock.\r
+ */\r
+void Chip_Clock_SetDivider(CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor);\r
+\r
+/**\r
+ * @brief Gets a CGU clock divider source\r
+ * @param Divider : CHIP_CGU_IDIV_T value indicating which divider to get the source of\r
+ * @return CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD\r
+ */\r
+CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource(CHIP_CGU_IDIV_T Divider);\r
+\r
+/**\r
+ * @brief Gets a CGU clock divider divisor\r
+ * @param Divider : CHIP_CGU_IDIV_T value indicating which divider to get the source of\r
+ * @return the divider value for the divider\r
+ */\r
+uint32_t Chip_Clock_GetDividerDivisor(CHIP_CGU_IDIV_T Divider);\r
+\r
+/**\r
+ * @brief Returns the frequency of the specified input clock source\r
+ * @param input : Which clock input to return the frequency of\r
+ * @return Frequency of input source in Hz\r
+ * This function returns an ideal frequency and not the actual frequency. Returns\r
+ * zero if the clock source is disabled.\r
+ */\r
+uint32_t Chip_Clock_GetClockInputHz(CHIP_CGU_CLKIN_T input);\r
+\r
+/**\r
+ * @brief Returns the frequency of the specified base clock source\r
+ * @param clock : which base clock to return the frequency of.\r
+ * @return Frequency of base source in Hz\r
+ * This function returns an ideal frequency and not the actual frequency. Returns\r
+ * zero if the clock source is disabled.\r
+ */\r
+uint32_t Chip_Clock_GetBaseClocktHz(CHIP_CGU_BASE_CLK_T clock);\r
+\r
+/**\r
+ * @brief Sets a CGU Base Clock clock source\r
+ * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to set\r
+ * @param Input : CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock\r
+ * @param autoblocken : Enables autoblocking during frequency change if true\r
+ * @param powerdn : The clock base is setup, but powered down if true\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn);\r
+\r
+/**\r
+ * @brief Get CGU Base Clock clock source information\r
+ * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to get\r
+ * @param Input : Pointer to CHIP_CGU_CLKIN_T value of the base clock\r
+ * @param autoblocken : Pointer to autoblocking value of the base clock\r
+ * @param powerdn : Pointer to power down flag\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_GetBaseClockOpts(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken,\r
+ bool *powerdn);\r
+\r
+/**\r
+ * @brief Gets a CGU Base Clock clock source\r
+ * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for\r
+ * @return CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD\r
+ */\r
+CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock);\r
+\r
+/**\r
+ * @brief Enables a base clock source\r
+ * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to enable\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_EnableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock);\r
+\r
+/**\r
+ * @brief Disables a base clock source\r
+ * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to disable\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_DisableBaseClock(CHIP_CGU_BASE_CLK_T BaseClock);\r
+\r
+/**\r
+ * @brief Returns base clock enable state\r
+ * @param BaseClock : CHIP_CGU_BASE_CLK_T value indicating which base clock to check\r
+ * @return true if the base clock is enabled, false if disabled\r
+ */\r
+bool Chip_Clock_IsBaseClockEnabled(CHIP_CGU_BASE_CLK_T BaseClock);\r
+\r
+/**\r
+ * @brief Enables a peripheral clock and sets clock states\r
+ * @param clk : CHIP_CCU_CLK_T value indicating which clock to enable\r
+ * @param autoen : true to enable autoblocking on a clock rate change, false to disable\r
+ * @param wakeupen : true to enable wakeup mechanism, false to disable\r
+ * @param div : Divider for the clock, must be 1 for most clocks, 2 supported on others\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_EnableOpts(CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div);\r
+\r
+/**\r
+ * @brief Enables a peripheral clock\r
+ * @param clk : CHIP_CCU_CLK_T value indicating which clock to enable\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_Enable(CHIP_CCU_CLK_T clk);\r
+\r
+/**\r
+ * @brief Disables a peripheral clock\r
+ * @param clk : CHIP_CCU_CLK_T value indicating which clock to disable\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_Disable(CHIP_CCU_CLK_T clk);\r
+\r
+/**\r
+ * @brief Returns a peripheral clock rate\r
+ * @param clk : CHIP_CCU_CLK_T value indicating which clock to get rate for\r
+ * @return 0 if the clock is disabled, or the rate of the clock\r
+ */\r
+uint32_t Chip_Clock_GetRate(CHIP_CCU_CLK_T clk);\r
+\r
+/**\r
+ * @brief Start the power down sequence by disabling the branch output\r
+ * clocks with wake up mechanism (Only the clocks which\r
+ * wake up mechanism bit enabled will be disabled)\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_StartPowerDown(void);\r
+\r
+/**\r
+ * @brief Clear the power down mode bit & proceed normal operation of branch output\r
+ * clocks (Only the clocks which wake up mechanism bit enabled will be\r
+ * enabled after the wake up event)\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_ClearPowerDown(void);\r
+\r
+/**\r
+ * Structure for setting up the USB or audio PLL\r
+ */\r
+typedef struct {\r
+ uint32_t ctrl; /* Default control word for PLL */\r
+ uint32_t mdiv; /* Default M-divider value for PLL */\r
+ uint32_t ndiv; /* Default NP-divider value for PLL */\r
+ uint32_t fract; /* Default fractional value for audio PLL only */\r
+} CGU_USBAUDIO_PLL_SETUP_T;\r
+\r
+/**\r
+ * @brief Sets up the audio or USB PLL\r
+ * @param Input : Input clock\r
+ * @param pllnum : PLL identifier\r
+ * @param pPLLSetup : Pointer to PLL setup structure\r
+ * @return Nothing\r
+ * Sets up the PLL with the passed structure values.\r
+ */\r
+void Chip_Clock_SetupPLL(CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum,\r
+ const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup);\r
+\r
+/**\r
+ * @brief Enables the audio or USB PLL\r
+ * @param pllnum : PLL identifier\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_EnablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum);\r
+\r
+/**\r
+ * @brief Disables the audio or USB PLL\r
+ * @param pllnum : PLL identifier\r
+ * @return Nothing\r
+ */\r
+void Chip_Clock_DisablePLL(CHIP_CGU_USB_AUDIO_PLL_T pllnum);\r
+\r
+#define CGU_PLL_LOCKED (1 << 0) /* PLL locked status */\r
+#define CGU_PLL_FR (1 << 1) /* PLL free running indicator status */\r
+\r
+/**\r
+ * @brief Returns the PLL status\r
+ * @param pllnum : PLL identifier\r
+ * @return An OR'ed value of CGU_PLL_LOCKED or CGU_PLL_FR\r
+ */\r
+uint32_t Chip_Clock_GetPLLStatus(CHIP_CGU_USB_AUDIO_PLL_T pllnum);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CLOCK_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief Basic CMSIS include file\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CMSIS_H_\r
+#define __CMSIS_H_\r
+\r
+#include "lpc_types.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup CMSIS_18XX_43XX CHIP: LPC18xx/43xx CMSIS include file\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+#if defined(__ARMCC_VERSION)\r
+// Kill warning "#pragma push with no matching #pragma pop"\r
+ #pragma diag_suppress 2525\r
+ #pragma push\r
+ #pragma anon_unions\r
+#elif defined(__CWCC__)\r
+ #pragma push\r
+ #pragma cpp_extensions on\r
+#elif defined(__GNUC__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined(__IAR_SYSTEMS_ICC__)\r
+// #pragma push // FIXME not usable for IAR\r
+ #pragma language=extended\r
+#else\r
+ #error Not supported compiler type\r
+#endif\r
+\r
+#if defined(CORE_M4)\r
+/** @defgroup CMSIS_43XX CHIP: LPC43xx Cortex CMSIS definitions\r
+ * @{\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */\r
+#define __MPU_PRESENT 1 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#ifdef CHIP_LPC43XX\r
+#define __FPU_PRESENT 1 /*!< FPU present or not */\r
+#else\r
+#define __FPU_PRESENT 0 /*!< FPU present or not */\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers\r
+ * @{\r
+ */\r
+\r
+typedef enum {\r
+ /* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */\r
+ Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */\r
+ NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
+ HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */\r
+ MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */\r
+ BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */\r
+ UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */\r
+ SVCall_IRQn = -5,/*!< 11 System Service Call via SVC instruction */\r
+ DebugMonitor_IRQn = -4,/*!< 12 Debug Monitor */\r
+ PendSV_IRQn = -2,/*!< 14 Pendable request for system service */\r
+ SysTick_IRQn = -1,/*!< 15 System Tick Timer */\r
+\r
+ /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */\r
+ DAC_IRQn = 0,/*!< 0 DAC */\r
+ M0CORE_IRQn = 1,/*!< 1 M0a */\r
+ DMA_IRQn = 2,/*!< 2 DMA */\r
+ RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */\r
+ RESERVED2_IRQn = 4,\r
+ ETHERNET_IRQn = 5,/*!< 5 ETHERNET */\r
+ SDIO_IRQn = 6,/*!< 6 SDIO */\r
+ LCD_IRQn = 7,/*!< 7 LCD */\r
+ USB0_IRQn = 8,/*!< 8 USB0 */\r
+ USB1_IRQn = 9,/*!< 9 USB1 */\r
+ SCT_IRQn = 10,/*!< 10 SCT */\r
+ RITIMER_IRQn = 11,/*!< 11 RITIMER */\r
+ TIMER0_IRQn = 12,/*!< 12 TIMER0 */\r
+ TIMER1_IRQn = 13,/*!< 13 TIMER1 */\r
+ TIMER2_IRQn = 14,/*!< 14 TIMER2 */\r
+ TIMER3_IRQn = 15,/*!< 15 TIMER3 */\r
+ MCPWM_IRQn = 16,/*!< 16 MCPWM */\r
+ ADC0_IRQn = 17,/*!< 17 ADC0 */\r
+ I2C0_IRQn = 18,/*!< 18 I2C0 */\r
+ I2C1_IRQn = 19,/*!< 19 I2C1 */\r
+ SPI_INT_IRQn = 20,/*!< 20 SPI_INT */\r
+ ADC1_IRQn = 21,/*!< 21 ADC1 */\r
+ SSP0_IRQn = 22,/*!< 22 SSP0 */\r
+ SSP1_IRQn = 23,/*!< 23 SSP1 */\r
+ USART0_IRQn = 24,/*!< 24 USART0 */\r
+ UART1_IRQn = 25,/*!< 25 UART1 */\r
+ USART2_IRQn = 26,/*!< 26 USART2 */\r
+ USART3_IRQn = 27,/*!< 27 USART3 */\r
+ I2S0_IRQn = 28,/*!< 28 I2S0 */\r
+ I2S1_IRQn = 29,/*!< 29 I2S1 */\r
+ RESERVED4_IRQn = 30,\r
+ SGPIO_INT_IRQn = 31,/*!< 31 SGPIO_IINT */\r
+ PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */\r
+ PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */\r
+ PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */\r
+ PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */\r
+ PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */\r
+ PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */\r
+ PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */\r
+ PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */\r
+ GINT0_IRQn = 40,/*!< 40 GINT0 */\r
+ GINT1_IRQn = 41,/*!< 41 GINT1 */\r
+ EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */\r
+ C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */\r
+ RESERVED6_IRQn = 44,\r
+ RESERVED7_IRQn = 45,/*!< 45 VADC */\r
+ ATIMER_IRQn = 46,/*!< 46 ATIMER */\r
+ RTC_IRQn = 47,/*!< 47 RTC */\r
+ RESERVED8_IRQn = 48,\r
+ WWDT_IRQn = 49,/*!< 49 WWDT */\r
+ RESERVED9_IRQn = 50,\r
+ C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */\r
+ QEI_IRQn = 52,/*!< 52 QEI */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */\r
+\r
+#elif defined(CORE_M3)\r
+/** @defgroup CMSIS_18XX CHIP: LPC18xx Cortex CMSIS definitions\r
+ * @{\r
+ */\r
+\r
+#define __MPU_PRESENT 1 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 0 /*!< FPU present or not */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers\r
+ * @{\r
+ */\r
+\r
+typedef enum {\r
+ /* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */\r
+ Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */\r
+ NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
+ HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */\r
+ MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */\r
+ BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */\r
+ UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */\r
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
+\r
+ /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */\r
+ DAC_IRQn = 0,/*!< 0 DAC */\r
+ RESERVED0_IRQn = 1,\r
+ DMA_IRQn = 2,/*!< 2 DMA */\r
+ RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */\r
+ RESERVED2_IRQn = 4,\r
+ ETHERNET_IRQn = 5,/*!< 5 ETHERNET */\r
+ SDIO_IRQn = 6,/*!< 6 SDIO */\r
+ LCD_IRQn = 7,/*!< 7 LCD */\r
+ USB0_IRQn = 8,/*!< 8 USB0 */\r
+ USB1_IRQn = 9,/*!< 9 USB1 */\r
+ SCT_IRQn = 10,/*!< 10 SCT */\r
+ RITIMER_IRQn = 11,/*!< 11 RITIMER */\r
+ TIMER0_IRQn = 12,/*!< 12 TIMER0 */\r
+ TIMER1_IRQn = 13,/*!< 13 TIMER1 */\r
+ TIMER2_IRQn = 14,/*!< 14 TIMER2 */\r
+ TIMER3_IRQn = 15,/*!< 15 TIMER3 */\r
+ MCPWM_IRQn = 16,/*!< 16 MCPWM */\r
+ ADC0_IRQn = 17,/*!< 17 ADC0 */\r
+ I2C0_IRQn = 18,/*!< 18 I2C0 */\r
+ I2C1_IRQn = 19,/*!< 19 I2C1 */\r
+ RESERVED3_IRQn = 20,\r
+ ADC1_IRQn = 21,/*!< 21 ADC1 */\r
+ SSP0_IRQn = 22,/*!< 22 SSP0 */\r
+ SSP1_IRQn = 23,/*!< 23 SSP1 */\r
+ USART0_IRQn = 24,/*!< 24 USART0 */\r
+ UART1_IRQn = 25,/*!< 25 UART1 */\r
+ USART2_IRQn = 26,/*!< 26 USART2 */\r
+ USART3_IRQn = 27,/*!< 27 USART3 */\r
+ I2S0_IRQn = 28,/*!< 28 I2S0 */\r
+ I2S1_IRQn = 29,/*!< 29 I2S1 */\r
+ RESERVED4_IRQn = 30,\r
+ RESERVED5_IRQn = 31,\r
+ PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */\r
+ PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */\r
+ PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */\r
+ PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */\r
+ PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */\r
+ PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */\r
+ PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */\r
+ PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */\r
+ GINT0_IRQn = 40,/*!< 40 GINT0 */\r
+ GINT1_IRQn = 41,/*!< 41 GINT1 */\r
+ EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */\r
+ C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */\r
+ RESERVED6_IRQn = 44,\r
+ RESERVED7_IRQn = 45,/*!< 45 VADC */\r
+ ATIMER_IRQn = 46,/*!< 46 ATIMER */\r
+ RTC_IRQn = 47,/*!< 47 RTC */\r
+ RESERVED8_IRQn = 48,\r
+ WWDT_IRQn = 49,/*!< 49 WWDT */\r
+ RESERVED9_IRQn = 50,\r
+ C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */\r
+ QEI_IRQn = 52,/*!< 52 QEI */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */\r
+\r
+#elif defined(CORE_M0)\r
+/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions\r
+ * @{\r
+ */\r
+\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 0 /*!< FPU present or not */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers\r
+ * @{\r
+ */\r
+\r
+typedef enum {\r
+ /* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */\r
+ Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */\r
+ NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
+ HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */\r
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
+\r
+ /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */\r
+ DAC_IRQn = 0,/*!< 0 DAC */\r
+ M0_M4CORE_IRQn = 1,/*!< 1 M0a */\r
+ DMA_IRQn = 2,/*!< 2 DMA */\r
+ RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */\r
+ FLASHEEPROM_IRQn = 4,/*!< 4 ORed Flash EEPROM Bank A, B, EEPROM */\r
+ ETHERNET_IRQn = 5,/*!< 5 ETHERNET */\r
+ SDIO_IRQn = 6,/*!< 6 SDIO */\r
+ LCD_IRQn = 7,/*!< 7 LCD */\r
+ USB0_IRQn = 8,/*!< 8 USB0 */\r
+ USB1_IRQn = 9,/*!< 9 USB1 */\r
+ SCT_IRQn = 10,/*!< 10 SCT */\r
+ RITIMER_IRQn = 11,/*!< 11 ORed RITIMER, WDT */\r
+ TIMER0_IRQn = 12,/*!< 12 TIMER0 */\r
+ GINT1_IRQn = 13,/*!< 13 GINT1 */\r
+ PIN_INT4_IRQn = 14,/*!< 14 GPIO 4 */\r
+ TIMER3_IRQn = 15,/*!< 15 TIMER3 */\r
+ MCPWM_IRQn = 16,/*!< 16 MCPWM */\r
+ ADC0_IRQn = 17,/*!< 17 ADC0 */\r
+ I2C0_IRQn = 18,/*!< 18 ORed I2C0, I2C1 */\r
+ SGPIO_INT_IRQn = 19,/*!< 19 SGPIO */\r
+ SPI_INT_IRQn = 20,/*!< 20 SPI_INT */\r
+ ADC1_IRQn = 21,/*!< 21 ADC1 */\r
+ SSP0_IRQn = 22,/*!< 22 ORed SSP0, SSP1 */\r
+ EVENTROUTER_IRQn = 23,/*!< 23 EVENTROUTER */\r
+ USART0_IRQn = 24,/*!< 24 USART0 */\r
+ UART1_IRQn = 25,/*!< 25 UART1 */\r
+ USART2_IRQn = 26,/*!< 26 USART2 */\r
+ USART3_IRQn = 27,/*!< 27 USART3 */\r
+ I2S0_IRQn = 28,/*!< 28 ORed I2S0, I2S1 */\r
+ C_CAN0_IRQn = 29,/*!< 29 C_CAN0 */\r
+ I2S1_IRQn = 29,/*!< 29 I2S1 */\r
+ RESERVED2_IRQn = 30,\r
+ RESERVED3_IRQn = 31,\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm0.h" /*!< Cortex-M4 processor and core peripherals */\r
+#else\r
+#error Please #define CORE_M0, CORE_M3, or CORE_M4\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CMSIS_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18XX/43XX CREG control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CREG_18XX_43XX_H_\r
+#define __CREG_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief CREG Register Block\r
+ */\r
+typedef struct { /*!< CREG Structure */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t CREG0; /*!< Chip configuration register 32 kHz oscillator output and BOD control register. */\r
+ __I uint32_t RESERVED1[62];\r
+ __IO uint32_t MXMEMMAP; /*!< ARM Cortex-M3/M4 memory mapping */\r
+#if defined(CHIP_LPC18XX)\r
+ __I uint32_t RESERVED2[5];\r
+#else\r
+ __I uint32_t RESERVED2;\r
+ __I uint32_t CREG1; /*!< Configuration Register 1 */\r
+ __I uint32_t CREG2; /*!< Configuration Register 2 */\r
+ __I uint32_t CREG3; /*!< Configuration Register 3 */\r
+ __I uint32_t CREG4; /*!< Configuration Register 4 */\r
+#endif\r
+ __IO uint32_t CREG5; /*!< Chip configuration register 5. Controls JTAG access. */\r
+ __IO uint32_t DMAMUX; /*!< DMA muxing control */\r
+ __IO uint32_t FLASHCFGA; /*!< Flash accelerator configuration register for flash bank A */\r
+ __IO uint32_t FLASHCFGB; /*!< Flash accelerator configuration register for flash bank B */\r
+ __IO uint32_t ETBCFG; /*!< ETB RAM configuration */\r
+ __IO uint32_t CREG6; /*!< Chip configuration register 6. */\r
+#if defined(CHIP_LPC18XX)\r
+ __I uint32_t RESERVED4[52];\r
+#else\r
+ __IO uint32_t M4TXEVENT; /*!< M4 IPC event register */\r
+ __I uint32_t RESERVED4[51];\r
+#endif\r
+ __I uint32_t CHIPID; /*!< Part ID */\r
+#if defined(CHIP_LPC18XX)\r
+ __I uint32_t RESERVED5[191];\r
+#else\r
+ __I uint32_t RESERVED5[127];\r
+ __IO uint32_t M0TXEVENT; /*!< M0 IPC Event register */\r
+ __IO uint32_t M0APPMEMMAP; /*!< ARM Cortex M0 memory mapping */\r
+ __I uint32_t RESERVED6[62];\r
+#endif\r
+ __IO uint32_t USB0FLADJ; /*!< USB0 frame length adjust register */\r
+ __I uint32_t RESERVED7[63];\r
+ __IO uint32_t USB1FLADJ; /*!< USB1 frame length adjust register */\r
+} LPC_CREG_T;\r
+\r
+/**\r
+ * @brief Identifies whether on-chip flash is present\r
+ * @return true if on chip flash is available, otherwise false\r
+ */\r
+STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void)\r
+{\r
+ return LPC_CREG->CHIPID != 0x3284E02B;\r
+}\r
+\r
+/**\r
+ * @brief Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts.\r
+ * @param Hz : Current frequency in Hz of the CPU\r
+ * @return Nothing\r
+ * This function should be called with the higher frequency before the clock frequency is\r
+ * increased and it should be called with the new lower value after the clock frequency is\r
+ * decreased.\r
+ */\r
+STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz)\r
+{\r
+ uint32_t FAValue = Hz / 21510000;\r
+\r
+ LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);\r
+ LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);\r
+}\r
+\r
+/**\r
+ * @brief Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts\r
+ * @param Enable : true to enable PHY, false to disable\r
+ * @return Nothing\r
+ * The USB0 PLL & clock should be configured before calling this function. This function\r
+ * should be called before the USB0 registers are accessed.\r
+ */\r
+STATIC INLINE void Chip_CREG_EnableUSB0Phy(bool Enable)\r
+{\r
+ if (Enable) {\r
+ LPC_CREG->CREG0 &= ~(1 << 5);\r
+ }\r
+ else {\r
+ LPC_CREG->CREG0 |= (1 << 5);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the BOD and Reset on LPC18xx/LPC43xx parts.\r
+ * @param BODVL : Brown-Out Detect voltage level (0-3)\r
+ * @param BORVL : Brown-Out Reset voltage level (0-3)\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)\r
+{\r
+ LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);\r
+}\r
+\r
+#if (defined(CHIP_LPC43XX) && defined(LPC_CREG))\r
+/**\r
+ * @brief Configures base address of image to be run in the Cortex M0 Core.\r
+ * @param memaddr : Address of the image (must be aligned to 4K)\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)\r
+{\r
+ LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;\r
+}\r
+\r
+/**\r
+ * @brief Clear M4 IPC Event\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_CREG_ClearM4Event(void)\r
+{\r
+ LPC_CREG->M4TXEVENT = 0;\r
+}\r
+\r
+/**\r
+ * @brief Clear M0 IPC Event\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_CREG_ClearM0Event(void)\r
+{\r
+ LPC_CREG->M0TXEVENT = 0;\r
+}\r
+\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CREG_18XX_43XX_H_ */\r
--- /dev/null
+/*
+ * @brief LPC18xx/43xx D/A conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __DAC_18XX_43XX_H_
+#define __DAC_18XX_43XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup DAC_18XX_43XX CHIP: LPC18xx/43xx D/A conversion driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+
+// FIXME LPC_DAC_T *pDAC argument not needed for 18xx/43xx CHIP driver
+
+/**
+ * @brief Initial DAC configuration
+ * - Maximum current is 700 uA
+ * - Value to AOUT is 0
+ * @param pDAC : pointer to LPC_DAC_T
+ * @return Nothing
+ */
+void Chip_DAC_Init(LPC_DAC_T *pDAC);
+
+/**
+ * @brief Shutdown DAC
+ * @param pDAC : pointer to LPC_DAC_T
+ * @return Nothing
+ */
+void Chip_DAC_DeInit(LPC_DAC_T *pDAC);
+
+/**
+ * @brief Update value to DAC buffer
+ * @param pDAC : pointer to LPC_DAC_T
+ * @param dac_value : value 10 bit to be converted to output
+ * @return Nothing
+ */
+STATIC INLINE void Chip_DAC_UpdateValue(LPC_DAC_T *pDAC, uint32_t dac_value)
+{
+ IP_DAC_UpdateValue(pDAC, dac_value);
+}
+
+/**
+ * @brief Set maximum update rate for DAC
+ * @param pDAC : pointer to LPC_DAC_T
+ * @param bias : Using Bias value, should be:
+ * - 0 is 1MHz
+ * - 1 is 400kHz
+ * @return Nothing
+ */
+STATIC INLINE void Chip_DAC_SetBias(LPC_DAC_T *pDAC, uint32_t bias)
+{
+ IP_DAC_SetBias(pDAC, bias);
+}
+
+/**
+ * @brief Enables the DMA operation and controls DMA timer
+ * @param pDAC : pointer to the DAC peripheral block
+ * @param dacFlags : An Or'ed value of the following DAC values:
+ * - DAC_DBLBUF_ENA :enable/disable DACR double buffering feature
+ * - DAC_CNT_ENA :enable/disable timer out counter
+ * - DAC_DMA_ENA :enable/disable DMA access
+ * @return Nothing
+ * @note Pass an Or'ed value of the DAC flags to enable those options.
+ */
+STATIC INLINE void Chip_DAC_ConfigDAConverterControl(IP_DAC_001_T *pDAC, uint32_t dacFlags)
+{
+ IP_DAC_ConfigDAConverterControl(pDAC, dacFlags);
+}
+
+/**
+ * @brief Set reload value for interrupt/DMA counter
+ * @param pDAC : pointer to LPC_DAC_T
+ * @param time_out : time out to reload for interrupt/DMA counter
+ * @return Nothing
+ */
+STATIC INLINE void Chip_DAC_SetDMATimeOut(LPC_DAC_T *pDAC, uint32_t time_out)
+{
+ IP_DAC_SetDMATimeOut(pDAC, time_out);
+}
+
+/**
+ * @brief Get status for interrupt/DMA time out
+ * @param pDAC : pointer to LPC_DAC_T
+ * @return interrupt/DMA time out status, should be SET or RESET
+ */
+STATIC INLINE IntStatus Chip_DAC_GetIntStatus(LPC_DAC_T *pDAC)
+{
+ return IP_DAC_GetIntStatus(pDAC);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_18XX_43XX_H_ */
--- /dev/null
+/*
+ * @brief LPC18xx/40xx EEPROM driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef EEPROM_18XX_43XX_H_
+#define EEPROM_18XX_43XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup EEPROM_18XX_43XX CHIP: LPC18xx/40xx EEPROM Driver
+ * @ingroup CHIP_18XX_43XX_Drivers
+ * @{
+ */
+/** EEPROM start address */
+#define EEPROM_START (0x20040000)
+/** EEPROM byes per page */
+#define EEPROM_PAGE_SIZE (128)
+/**The number of EEPROM pages. The last page is not writable.*/
+#define EEPROM_PAGE_NUM (128)
+/** Get the eeprom address */
+#define EEPROM_ADDRESS(page, offset) (EEPROM_START + (EEPROM_PAGE_SIZE * (page)) + offset)
+
+/**
+ * @brief Initializes EEPROM
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @return Nothing
+ */
+void Chip_EEPROM_Init(LPC_EEPROM_T *pEEPROM);
+
+/**
+ * @brief De-initializes EEPROM
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_DeInit(LPC_EEPROM_T *pEEPROM)
+{
+ IP_EEPROM_DeInit(pEEPROM);
+}
+
+/**
+ * @brief Set Auto program mode
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @param mode : Auto Program Mode (One of EEPROM_AUTOPROG_* value)
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_SetAutoProg(LPC_EEPROM_T *pEEPROM, uint32_t mode)
+{
+ IP_EEPROM_SetAutoProg(pEEPROM, mode);
+}
+
+/**
+ * @brief Set EEPROM Read Wait State
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @param ws : Wait State value
+ * @return Nothing\r
+ * @note Bits 7:0 represents wait state for Read Phase 2 and \r
+ * Bits 15:8 represents wait state for Read Phase1
+ */
+STATIC INLINE void Chip_EEPROM_SetReadWaitState(LPC_EEPROM_T *pEEPROM, uint32_t ws)
+{
+ IP_EEPROM_SetReadWaitState(pEEPROM, ws);
+}
+
+/**
+ * @brief Set EEPROM wait state
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @param ws : Wait State value
+ * @return Nothing\r
+ * @note Bits 7:0 represents wait state for Phase 3,\r
+ * Bits 15:8 represents wait state for Phase2, and\r
+ * Bits 23:16 represents wait state for Phase1
+ */
+STATIC INLINE void Chip_EEPROM_SetWaitState(LPC_EEPROM_T *pEEPROM, uint32_t ws)
+{
+ IP_EEPROM_SetWaitState(pEEPROM, ws);
+}
+
+/**
+ * @brief Select an EEPROM command
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @param cmd : EEPROM command
+ * @return Nothing
+ * @note The cmd is OR-ed bits value of EEPROM_CMD_*
+ */
+STATIC INLINE void Chip_EEPROM_SetCmd(LPC_EEPROM_T *pEEPROM, uint32_t cmd)
+{
+ IP_EEPROM_SetCmd(pEEPROM, cmd);
+}
+
+/**
+ * @brief Erase/Program an EEPROM page
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_EraseProgramPage(LPC_EEPROM_T *pEEPROM)
+{
+ IP_EEPROM_EraseProgramPage(pEEPROM);
+}
+
+/**
+ * @brief Wait for interrupt occurs
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @param mask : Expected interrupt
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_WaitForIntStatus(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
+{
+ IP_EEPROM_WaitForIntStatus(pEEPROM, mask);
+}
+
+/**
+ * @brief Put EEPROM device in power down mode
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_EnablePowerDown(LPC_EEPROM_T *pEEPROM)
+{
+ IP_EEPROM_EnablePowerDown(pEEPROM);
+}
+
+/**
+ * @brief Bring EEPROM device out of power down mode
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_DisablePowerDown(LPC_EEPROM_T *pEEPROM)
+{
+ IP_EEPROM_DisablePowerDown(pEEPROM);
+}
+
+/**
+ * @brief Enable EEPROM interrupt
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_EnableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask)
+{
+ IP_EEPROM_EnableInt(pEEPROM, mask);
+}
+
+/**
+ * @brief Disable EEPROM interrupt
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_DisableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask)
+{
+ IP_EEPROM_DisableInt(pEEPROM, mask);
+}
+
+/**
+ * @brief Get the value of the EEPROM interrupt enable register
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @return OR-ed bits value of EEPROM_INT_*
+ */
+STATIC INLINE uint32_t Chip_EEPROM_GetIntEnable(LPC_EEPROM_T *pEEPROM)
+{
+ return IP_EEPROM_GetIntEnable(pEEPROM);
+}
+
+/**
+ * @brief Get EEPROM interrupt status
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @return OR-ed bits value of EEPROM_INT_*
+ */
+STATIC INLINE uint32_t Chip_EEPROM_GetIntStatus(LPC_EEPROM_T *pEEPROM)
+{
+ return IP_EEPROM_GetIntStatus(pEEPROM);
+}
+
+/**
+ * @brief Set EEPROM interrupt status
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_SetIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
+{
+ IP_EEPROM_SetIntStatus(pEEPROM, mask);
+}
+
+/**
+ * @brief Clear EEPROM interrupt status
+ * @param pEEPROM : Pointer to EEPROM peripheral block structure
+ * @param mask : Interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return Nothing
+ */
+STATIC INLINE void Chip_EEPROM_ClearIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
+{
+ IP_EEPROM_ClearIntStatus(pEEPROM, mask);
+}
+
+/**
+ * @}
+ */
+
+ #ifdef __cplusplus
+}
+#endif
+
+#endif /* EEPROM_18XX_43XX_H_ */
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx EMC driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __EMC_18XX_43XX_H_\r
+#define __EMC_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup EMC_18XX_43XX CHIP: LPC18xx/43xx EMC Driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ * The EMC interface clocks must be enabled outside this driver prior to\r
+ * calling any function of this driver with the\r
+ * Chip_Clock_EnableOpts(CLK_MX_EMC_DIV) and Chip_Clock_Enable(CLK_MX_EMC)\r
+ * functions.\r
+ */\r
+\r
+/**\r
+ * Dynamic Chip Select Address\r
+ */\r
+#define EMC_ADDRESS_DYCS0 (0x28000000)\r
+#define EMC_ADDRESS_DYCS1 (0x30000000)\r
+#define EMC_ADDRESS_DYCS2 (0x60000000)\r
+#define EMC_ADDRESS_DYCS3 (0x70000000)\r
+\r
+/**\r
+ * Static Chip Select Address\r
+ */\r
+#define EMC_ADDRESS_CS0 (0x1C000000)\r
+#define EMC_ADDRESS_CS1 (0x1D000000)\r
+#define EMC_ADDRESS_CS2 (0x1E000000)\r
+#define EMC_ADDRESS_CS3 (0x1F000000)\r
+\r
+/**\r
+ * @brief Dyanmic memory setup\r
+ * @param Dynamic_Config : Pointer to dynamic memory setup data\r
+ * @return None\r
+ */\r
+void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_T *Dynamic_Config);\r
+\r
+/**\r
+ * @brief Static memory setup\r
+ * @param Static_Config : Pointer to static memory setup data\r
+ * @return None\r
+ */\r
+void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_T *Static_Config);\r
+\r
+/**\r
+ * @brief Enable Dynamic Memory Controller\r
+ * @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_EMC_Dynamic_Enable(uint8_t Enable)\r
+{\r
+ IP_EMC_Dynamic_Enable(LPC_EMC, Enable);\r
+}\r
+\r
+/**\r
+ * @brief Mirror CS1 to CS0 and DYCS0\r
+ * @param Enable : 1 = Mirror, 0 = Normal Memory Map\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_EMC_Mirror(uint8_t Enable)\r
+{\r
+ IP_EMC_Mirror(LPC_EMC, Enable);\r
+}\r
+\r
+/**\r
+ * @brief Enable EMC\r
+ * @param Enable : 1 = Enable, 0 = Disable\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_EMC_Enable(uint8_t Enable)\r
+{\r
+ IP_EMC_Enable(LPC_EMC, Enable);\r
+}\r
+\r
+/**\r
+ * @brief Set EMC LowPower Mode\r
+ * @param Enable : 1 = Enable, 0 = Disable\r
+ * @return None\r
+ * @note This function should only be called when the memory\r
+ * controller is not busy (bit 0 of the status register is not set).\r
+ */\r
+STATIC INLINE void Chip_EMC_LowPowerMode(uint8_t Enable)\r
+{\r
+ IP_EMC_LowPowerMode(LPC_EMC, Enable);\r
+}\r
+\r
+/**\r
+ * @brief Initialize EMC\r
+ * @param Enable : 1 = Enable, 0 = Disable\r
+ * @param EndianMode : Endian Mode, 0 = Little, 1 = Big\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_EMC_Init(uint32_t Enable, uint32_t EndianMode)\r
+{\r
+ IP_EMC_Init(LPC_EMC, Enable, 0, EndianMode);\r
+}\r
+\r
+/**\r
+ * @brief Set Static Memory Extended Wait in Clock\r
+ * @param Wait16Clks : Number of '16 clock' delay cycles\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks)\r
+{\r
+ IP_EMC_SetStaticExtendedWait(LPC_EMC, Wait16Clks);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __EMC_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx ethernet driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "chip.h"\r
+\r
+/*****************************************************************************\r
+ * Private types/enumerations/variables\r
+ ****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Public types/enumerations/variables\r
+ ****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Private functions\r
+ ****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Public functions\r
+ ****************************************************************************/\r
+\r
+/* Basic Ethernet interface initialization */\r
+void Chip_ENET_Init(LPC_ENET_T *pENET)\r
+{\r
+ LPC_CREG->CREG6 &= ~0x7;\r
+\r
+ /* Enable ethernet clock */\r
+ Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);\r
+\r
+ /* PHY TX/RX base clock routing is setup as part of SystemInit() */\r
+\r
+#if defined(USE_RMII)\r
+ LPC_CREG->CREG6 |= 0x4;\r
+#endif\r
+\r
+ /* Reset ethernet and wait for reset to complete */\r
+ Chip_RGU_TriggerReset(RGU_ETHERNET_RST);\r
+ while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {}\r
+\r
+ /* Reset ethernet peripheral */\r
+ Chip_ENET_Reset(pENET);\r
+\r
+ /* Setup MII link divider to /102 and PHY address 1 */\r
+ Chip_ENET_SetupMII(pENET, 4, 1);\r
+\r
+ IP_ENET_Init(pENET);\r
+}\r
+\r
+/* Ethernet interface shutdown */\r
+void Chip_ENET_DeInit(LPC_ENET_T *pENET)\r
+{\r
+ IP_ENET_DeInit(pENET);\r
+ Chip_Clock_Disable(CLK_MX_ETHERNET);\r
+}\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx ethernet driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __ENET_18XX_43XX_H_\r
+#define __ENET_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup ENET_18XX_43XX CHIP: LPC18xx/43xx Ethernet driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ENET_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Ethernet driver build options\r
+ * @ingroup ENET_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS\r
+ * The ethernet driver has options that configure it's operation at build-time.<br>\r
+ *\r
+ * <b>USE_RMII</b><br>\r
+ * When defined, the driver will be built for RMII operation.<br>\r
+ * When not defined, the driver will be built for MII operation.<br>\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Resets the ethernet interface\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Nothing\r
+ * @note Resets the ethernet interface. This should be called prior to\r
+ * Chip_ENET_Init with a small delay after this call.\r
+ */\r
+STATIC INLINE void Chip_ENET_Reset(LPC_ENET_T *pENET)\r
+{\r
+ IP_ENET_Reset(pENET);\r
+}\r
+\r
+/**\r
+ * @brief Sets the address of the interface\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @param macAddr : Pointer to the 6 bytes used for the MAC address\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_SetADDR(LPC_ENET_T *pENET, const uint8_t *macAddr)\r
+{\r
+ IP_ENET_SetADDR(pENET, macAddr);\r
+}\r
+\r
+/**\r
+ * @brief Sets up the PHY link clock divider and PHY address\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @param div : Divider index, not a divider value, see user manual\r
+ * @param addr : PHY address, used with MII read and write\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr)\r
+{\r
+ IP_ENET_SetupMII(pENET, div, addr);\r
+}\r
+\r
+/**\r
+ * @brief Starts a PHY write via the MII\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @param reg : PHY register to write\r
+ * @param data : Data to write to PHY register\r
+ * @return Nothing\r
+ * @note Start a PHY write operation. Does not block, requires calling\r
+ * IP_ENET_IsMIIBusy to determine when write is complete.\r
+ */\r
+STATIC INLINE void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data)\r
+{\r
+ IP_ENET_StartMIIWrite(pENET, reg, data);\r
+}\r
+\r
+/**\r
+ * @brief Starts a PHY read via the MII\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @param reg : PHY register to read\r
+ * @return Nothing\r
+ * @note Start a PHY read operation. Does not block, requires calling\r
+ * IP_ENET_IsMIIBusy to determine when read is complete and calling\r
+ * IP_ENET_ReadMIIData to get the data.\r
+ */\r
+STATIC INLINE void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg)\r
+{\r
+ IP_ENET_StartMIIRead(pENET, reg);\r
+}\r
+\r
+/**\r
+ * @brief Returns MII link (PHY) busy status\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Returns true if busy, otherwise false\r
+ */\r
+STATIC INLINE bool Chip_ENET_IsMIIBusy(LPC_ENET_T *pENET)\r
+{\r
+ return IP_ENET_IsMIIBusy(pENET);\r
+}\r
+\r
+/**\r
+ * @brief Returns the value read from the PHY\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Read value from PHY\r
+ */\r
+STATIC INLINE uint16_t Chip_ENET_ReadMIIData(LPC_ENET_T *pENET)\r
+{\r
+ return IP_ENET_ReadMIIData(pENET);\r
+}\r
+\r
+/**\r
+ * @brief Enables ethernet transmit\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_TXEnable(LPC_ENET_T *pENET)\r
+{\r
+ IP_ENET_TXEnable(pENET);\r
+}\r
+\r
+/**\r
+ * @brief Disables ethernet transmit\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_TXDisable(LPC_ENET_T *pENET)\r
+{\r
+ IP_ENET_TXDisable(pENET);\r
+}\r
+\r
+/**\r
+ * @brief Enables ethernet packet reception\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_RXEnable(LPC_ENET_T *pENET)\r
+{\r
+ IP_ENET_RXEnable(pENET);\r
+}\r
+\r
+/**\r
+ * @brief Disables ethernet packet reception\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_RXDisable(LPC_ENET_T *pENET)\r
+{\r
+ IP_ENET_RXDisable(pENET);\r
+}\r
+\r
+/**\r
+ * @brief Sets full or half duplex for the interface\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @param full : true to selected full duplex, false for half\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_SetDuplex(LPC_ENET_T *pENET, bool full)\r
+{\r
+ IP_ENET_SetDuplex(pENET, full);\r
+}\r
+\r
+/**\r
+ * @brief Sets speed for the interface\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @param speed100 : true to select 100Mbps mode, false for 10Mbps\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_SetSpeed(LPC_ENET_T *pENET, bool speed100)\r
+{\r
+ IP_ENET_SetSpeed(pENET, speed100);\r
+}\r
+\r
+/**\r
+ * @brief Configures the initial ethernet descriptors\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @param pTXDescs : Pointer to TX descriptor list\r
+ * @param pRXDescs : Pointer to RX descriptor list\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_InitDescriptors(LPC_ENET_T *pENET,\r
+ IP_ENET_001_ENHTXDESC_T *pTXDescs, IP_ENET_001_ENHRXDESC_T *pRXDescs)\r
+{\r
+ IP_ENET_InitDescriptors(pENET, pTXDescs, pRXDescs);\r
+}\r
+\r
+/**\r
+ * @brief Starts receive polling of RX descriptors\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_RXStart(LPC_ENET_T *pENET)\r
+{\r
+ IP_ENET_RXStart(pENET);\r
+}\r
+\r
+/**\r
+ * @brief Starts transmit polling of TX descriptors\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_ENET_TXStart(LPC_ENET_T *pENET)\r
+{\r
+ IP_ENET_TXStart(pENET);\r
+}\r
+\r
+/**\r
+ * @brief Initialize ethernet interface\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Nothing\r
+ * @note Performs basic initialization of the ethernet interface in a default\r
+ * state. This is enough to place the interface in a usable state, but\r
+ * may require more setup outside this function.\r
+ */\r
+void Chip_ENET_Init(LPC_ENET_T *pENET);\r
+\r
+/**\r
+ * @brief De-initialize the ethernet interface\r
+ * @param pENET : The base of ENET peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_ENET_DeInit(LPC_ENET_T *pENET);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __ENET_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx event router driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __EVRT_18XX_43XX_H_\r
+#define __EVRT_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup EVRT_18XX_43XX CHIP: LPC18xx/43xx Event router driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Event Router register structure\r
+ */\r
+typedef struct { /*!< EVENTROUTER Structure */\r
+ __IO uint32_t HILO; /*!< Level configuration register */\r
+ __IO uint32_t EDGE; /*!< Edge configuration */\r
+ __I uint32_t RESERVED0[1012];\r
+ __O uint32_t CLR_EN; /*!< Event clear enable register */\r
+ __O uint32_t SET_EN; /*!< Event set enable register */\r
+ __I uint32_t STATUS; /*!< Status register */\r
+ __I uint32_t ENABLE; /*!< Enable register */\r
+ __O uint32_t CLR_STAT; /*!< Clear register */\r
+ __O uint32_t SET_STAT; /*!< Set register */\r
+} LPC_EVRT_T;\r
+\r
+/**\r
+ * @brief EVRT input sources\r
+ */\r
+typedef enum CHIP_EVRT_SRC {\r
+ EVRT_SRC_WAKEUP0, /*!< WAKEUP0 event router source */\r
+ EVRT_SRC_WAKEUP1, /*!< WAKEUP1 event router source */\r
+ EVRT_SRC_WAKEUP2, /*!< WAKEUP2 event router source */\r
+ EVRT_SRC_WAKEUP3, /*!< WAKEUP3 event router source */\r
+ EVRT_SRC_ATIMER, /*!< Alarm timer event router source */\r
+ EVRT_SRC_RTC, /*!< RTC event router source */\r
+ EVRT_SRC_BOD1, /*!< BOD event router source */\r
+ EVRT_SRC_WWDT, /*!< WWDT event router source */\r
+ EVRT_SRC_ETHERNET, /*!< Ethernet event router source */\r
+ EVRT_SRC_USB0, /*!< USB0 event router source */\r
+ EVRT_SRC_USB1, /*!< USB1 event router source */\r
+ EVRT_SRC_SDIO, /*!< Reserved */\r
+ EVRT_SRC_CCAN, /*!< C_CAN event router source */\r
+ EVRT_SRC_COMBINE_TIMER2, /*!< Combined timer 2 event router source */\r
+ EVRT_SRC_COMBINE_TIMER6, /*!< Combined timer 6 event router source */\r
+ EVRT_SRC_QEI, /*!< QEI event router source */\r
+ EVRT_SRC_COMBINE_TIMER14, /*!< Combined timer 14 event router source */\r
+ EVRT_SRC_RESERVED1, /*!< Reserved */\r
+ EVRT_SRC_RESERVED2, /*!< Reserved */\r
+ EVRT_SRC_RESET /*!< Reset event router source */\r
+} CHIP_EVRT_SRC_T;\r
+\r
+/**\r
+ * @brief Macro for checking for a valid EVRT source\r
+ */\r
+#define PARAM_EVRT_SOURCE(n) ((n == EVRT_SRC_WAKEUP0) || (n == EVRT_SRC_WAKEUP1) \\r
+ || (n == EVRT_SRC_WAKEUP2) || (n == EVRT_SRC_WAKEUP3) \\r
+ || (n == EVRT_SRC_ATIMER) || (n == EVRT_SRC_RTC) \\r
+ || (n == EVRT_SRC_BOD1) || (n == EVRT_SRC_WWDT) \\r
+ || (n == EVRT_SRC_ETHERNET) || (n == EVRT_SRC_USB0) \\r
+ || (n == EVRT_SRC_USB1) || (n == EVRT_SRC_CCAN) || (n == EVRT_SRC_SDIO) \\r
+ || (n == EVRT_SRC_COMBINE_TIMER2) || (n == EVRT_SRC_COMBINE_TIMER6) \\r
+ || (n == EVRT_SRC_QEI) || (n == EVRT_SRC_COMBINE_TIMER14) \\r
+ || (n == EVRT_SRC_RESET)) \\r
+\r
+/**\r
+ * @brief EVRT input state detecting type\r
+ */\r
+typedef enum CHIP_EVRT_SRC_ACTIVE {\r
+ EVRT_SRC_ACTIVE_LOW_LEVEL, /*!< Active low level */\r
+ EVRT_SRC_ACTIVE_HIGH_LEVEL, /*!< Active high level */\r
+ EVRT_SRC_ACTIVE_FALLING_EDGE, /*!< Active falling edge */\r
+ EVRT_SRC_ACTIVE_RISING_EDGE /*!< Active rising edge */\r
+} CHIP_EVRT_SRC_ACTIVE_T;\r
+\r
+/**\r
+ * @brief Macro for checking for a valid EVRT state type\r
+ */\r
+#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n == EVRT_SRC_ACTIVE_LOW_LEVEL) || (n == EVRT_SRC_ACTIVE_HIGH_LEVEL) \\r
+ || (n == EVRT_SRC_ACTIVE_FALLING_EDGE) || (n == EVRT_SRC_ACTIVE_RISING_EDGE))\r
+\r
+/**\r
+ * @brief Initialize the EVRT\r
+ * @return Nothing\r
+ */\r
+void Chip_EVRT_Init (void);\r
+\r
+/**\r
+ * @brief Set up the type of interrupt type for a source to EVRT\r
+ * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type\r
+ * @param type : EVRT type, should be one of CHIP_EVRT_SRC_ACTIVE_T type\r
+ * @return Nothing\r
+ */\r
+void Chip_EVRT_ConfigIntSrcActiveType(CHIP_EVRT_SRC_T EVRT_Src, CHIP_EVRT_SRC_ACTIVE_T type);\r
+\r
+/**\r
+ * @brief Check if a source is sending interrupt to EVRT\r
+ * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type\r
+ * @return true if the interrupt from the source is pending, otherwise false\r
+ */\r
+IntStatus Chip_EVRT_IsSourceInterrupting(CHIP_EVRT_SRC_T EVRT_Src);\r
+\r
+/**\r
+ * @brief Enable or disable interrupt sources to EVRT\r
+ * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type\r
+ * @param state : ENABLE or DISABLE to enable or disable event router source\r
+ * @return Nothing\r
+ */\r
+void Chip_EVRT_SetUpIntSrc(CHIP_EVRT_SRC_T EVRT_Src, FunctionalState state);\r
+\r
+/**\r
+ * @brief De-initializes the EVRT peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_EVRT_DeInit(void)\r
+{\r
+ LPC_EVRT->CLR_EN = 0xFFFF;\r
+ LPC_EVRT->CLR_STAT = 0xFFFF;\r
+}\r
+\r
+/**\r
+ * @brief Clear pending interrupt EVRT source\r
+ * @param EVRT_Src : EVRT source, should be one of CHIP_EVRT_SRC_T type\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_EVRT_ClrPendIntSrc(CHIP_EVRT_SRC_T EVRT_Src)\r
+{\r
+ LPC_EVRT->CLR_STAT = (1 << (uint8_t) EVRT_Src);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __EVRT_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx DMA driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __GPDMA_18XX_43XX_H_\r
+#define __GPDMA_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup GPDMA_18XX_43XX CHIP: LPC18xx/43xx General Purpose DMA driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Number of channels on GPDMA\r
+ */\r
+#define GPDMA_NUMBER_CHANNELS 8\r
+\r
+/**\r
+ * @brief GPDMA request connections\r
+ */\r
+#define GPDMA_CONN_MEMORY ((0UL)) /**< MEMORY */\r
+#define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */\r
+#define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */\r
+#define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */\r
+#define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */\r
+#define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */\r
+#define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */\r
+#define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */\r
+#define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */\r
+#define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */\r
+#define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */\r
+#define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */\r
+#define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */\r
+#define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */\r
+#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */\r
+#define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/\r
+#define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */\r
+#define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */\r
+#define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/\r
+#define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */\r
+#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL)) /**< I2S channel 0 */\r
+#define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */\r
+#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL)) /**< I2S channel 1 */\r
+#define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */\r
+#define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */\r
+#define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */\r
+#define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */\r
+#define GPDMA_CONN_DAC ((27UL)) /**< DAC */\r
+#define GPDMA_CONN_I2S_Tx_Channel_1 ((28UL)) /**< I2S channel 0 */\r
+#define GPDMA_CONN_I2S_Rx_Channel_0 ((29UL)) /**< I2S channel 0 */\r
+\r
+/**\r
+ * @brief GPDMA Burst size in Source and Destination definitions\r
+ */\r
+#define GPDMA_BSIZE_1 ((0UL)) /*!< Burst size = 1 */\r
+#define GPDMA_BSIZE_4 ((1UL)) /*!< Burst size = 4 */\r
+#define GPDMA_BSIZE_8 ((2UL)) /*!< Burst size = 8 */\r
+#define GPDMA_BSIZE_16 ((3UL)) /*!< Burst size = 16 */\r
+#define GPDMA_BSIZE_32 ((4UL)) /*!< Burst size = 32 */\r
+#define GPDMA_BSIZE_64 ((5UL)) /*!< Burst size = 64 */\r
+#define GPDMA_BSIZE_128 ((6UL)) /*!< Burst size = 128 */\r
+#define GPDMA_BSIZE_256 ((7UL)) /*!< Burst size = 256 */\r
+\r
+/**\r
+ * @brief Width in Source transfer width and Destination transfer width definitions\r
+ */\r
+#define GPDMA_WIDTH_BYTE ((0UL)) /*!< Width = 1 byte */\r
+#define GPDMA_WIDTH_HALFWORD ((1UL)) /*!< Width = 2 bytes */\r
+#define GPDMA_WIDTH_WORD ((2UL)) /*!< Width = 4 bytes */\r
+\r
+/**\r
+ * @brief Flow control definitions\r
+ */\r
+#define DMA_CONTROLLER 0 /*!< Flow control is DMA controller*/\r
+#define SRC_PER_CONTROLLER 1 /*!< Flow control is Source peripheral controller*/\r
+#define DST_PER_CONTROLLER 2 /*!< Flow control is Destination peripheral controller*/\r
+\r
+/**\r
+ * @brief DMA channel handle structure\r
+ */\r
+typedef struct {\r
+ FunctionalState ChannelStatus; /*!< DMA channel status */\r
+} DMA_ChannelHandle_t;\r
+\r
+/**\r
+ * @brief Transfer Descriptor structure typedef\r
+ */\r
+typedef struct DMA_TransferDescriptor {\r
+ uint32_t src; /*!< Source address */\r
+ uint32_t dst; /*!< Destination address */\r
+ uint32_t lli; /*!< Pointer to next descriptor structure */\r
+ uint32_t ctrl; /*!< Control word that has transfer size, type etc. */\r
+} DMA_TransferDescriptor_t;\r
+\r
+/**\r
+ * @brief Read the status from different registers according to the type\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param type : Status mode, should be:\r
+ * - GPDMA_STAT_INT : GPDMA Interrupt Status\r
+ * - GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status\r
+ * - GPDMA_STAT_INTERR : GPDMA Interrupt Error Status\r
+ * - GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status\r
+ * - GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status\r
+ * - GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status\r
+ * @param channel : The GPDMA channel : 0 - 7\r
+ * @return SET is interrupt is pending or RESET if not pending\r
+ */\r
+STATIC INLINE IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, IP_GPDMA_STATUS_T type, uint8_t channel)\r
+{\r
+ return IP_GPDMA_IntGetStatus(pGPDMA, type, channel);\r
+}\r
+\r
+/**\r
+ * @brief Clear the Interrupt Flag from different registers according to the type\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param type : Flag mode, should be:\r
+ * - GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request\r
+ * - GPDMA_STATCLR_INTERR : GPDMA Interrupt Error\r
+ * @param channel : The GPDMA channel : 0 - 7\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, IP_GPDMA_STATECLEAR_T type, uint8_t channel)\r
+{\r
+ IP_GPDMA_ClearIntPending(pGPDMA, type, channel);\r
+}\r
+\r
+/**\r
+ * @brief Enable or Disable the GPDMA Channel\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param channelNum : The GPDMA channel : 0 - 7\r
+ * @param NewState : ENABLE to enable GPDMA or DISABLE to disable GPDMA\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState)\r
+{\r
+ IP_GPDMA_ChannelCmd(pGPDMA, channelNum, NewState);\r
+}\r
+\r
+/**\r
+ * @brief Initialize the GPDMA\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA);\r
+\r
+/**\r
+ * @brief Shutdown the GPDMA\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA);\r
+\r
+/**\r
+ * @brief Stop a stream DMA transfer\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param ChannelNum : Channel Number to be closed\r
+ * @return Nothing\r
+ */\r
+void Chip_DMA_Stop(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);\r
+\r
+/**\r
+ * @brief The GPDMA stream interrupt status checking\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param ChannelNum : Channel Number to be checked on interruption\r
+ * @return Status:\r
+ * - SUCCESS : DMA transfer success\r
+ * - ERROR : DMA transfer failed\r
+ */\r
+Status Chip_DMA_Interrupt(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);\r
+\r
+/**\r
+ * @brief Get a free GPDMA channel for one DMA connection\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param PeripheralConnection_ID : Some chip fix each peripheral DMA connection on a specified channel ( have not used in 18xx/43xx )\r
+ * @return The channel number which is selected\r
+ */\r
+uint8_t Chip_DMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA, uint32_t PeripheralConnection_ID);\r
+\r
+/**\r
+ * @brief Do a DMA transfer M2M, M2P,P2M or P2P\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param ChannelNum : Channel used for transfer\r
+ * @param src : Address of Memory or PeripheralConnection_ID which is the source\r
+ * @param dst : Address of Memory or PeripheralConnection_ID which is the destination\r
+ * @param TransferType: Select the transfer controller and the type of transfer. Should be:\r
+ * - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA\r
+ * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA\r
+ * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA\r
+ * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA\r
+ * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL\r
+ * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL\r
+ * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL\r
+ * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL\r
+ * @param Size : The number of DMA transfers\r
+ * @return ERROR on error, SUCCESS on success\r
+ */\r
+Status Chip_DMA_Transfer(LPC_GPDMA_T *pGPDMA,\r
+ uint8_t ChannelNum,\r
+ uint32_t src,\r
+ uint32_t dst,\r
+ IP_GPDMA_FLOW_CONTROL_T TransferType,\r
+ uint32_t Size);\r
+\r
+/**\r
+ * @brief Do a DMA transfer using linked list of descriptors\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param ChannelNum : Channel used for transfer *must be obtained using Chip_DMA_GetFreeChannel()*\r
+ * @param DMADescriptor : First node in the linked list of descriptors\r
+ * @param TransferType : Select the transfer controller and the type of transfer. (See, #IP_GPDMA_FLOW_CONTROL_T)\r
+ * @return ERROR on error, SUCCESS on success\r
+ */\r
+Status Chip_DMA_SGTransfer(LPC_GPDMA_T *pGPDMA,\r
+ uint8_t ChannelNum,\r
+ const DMA_TransferDescriptor_t *DMADescriptor,\r
+ IP_GPDMA_FLOW_CONTROL_T TransferType);\r
+\r
+/**\r
+ * @brief Prepare a single DMA descriptor\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param DMADescriptor : DMA Descriptor to be initialized\r
+ * @param src : Address of Memory or one of @link #GPDMA_CONN_MEMORY\r
+ * PeripheralConnection_ID @endlink, which is the source\r
+ * @param dst : Address of Memory or one of @link #GPDMA_CONN_MEMORY\r
+ * PeripheralConnection_ID @endlink, which is the destination\r
+ * @param Size : The number of DMA transfers\r
+ * @param TransferType : Select the transfer controller and the type of transfer. (See, #IP_GPDMA_FLOW_CONTROL_T)\r
+ * @param NextDescriptor : Pointer to next descriptor (0 if no more descriptors available)\r
+ * @return ERROR on error, SUCCESS on success\r
+ */\r
+Status Chip_DMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA,\r
+ DMA_TransferDescriptor_t *DMADescriptor,\r
+ uint32_t src,\r
+ uint32_t dst,\r
+ uint32_t Size,\r
+ IP_GPDMA_FLOW_CONTROL_T TransferType,\r
+ const DMA_TransferDescriptor_t *NextDescriptor);\r
+\r
+/**\r
+ * @brief Initialize channel configuration strucutre\r
+ * @param pGPDMA : The base of GPDMA on the chip\r
+ * @param GPDMACfg : Pointer to configuration structure to be initialized\r
+ * @param ChannelNum : Channel used for transfer *must be obtained using Chip_DMA_GetFreeChannel()*\r
+ * @param src : Address of Memory or one of @link #GPDMA_CONN_MEMORY\r
+ * PeripheralConnection_ID @endlink, which is the source\r
+ * @param dst : Address of Memory or one of @link #GPDMA_CONN_MEMORY\r
+ * PeripheralConnection_ID @endlink, which is the destination\r
+ * @param Size : The number of DMA transfers\r
+ * @param TransferType : Select the transfer controller and the type of transfer. (See, #IP_GPDMA_FLOW_CONTROL_T)\r
+ * @return ERROR on error, SUCCESS on success\r
+ */\r
+int Chip_DMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA,\r
+ GPDMA_Channel_CFG_T *GPDMACfg,\r
+ uint8_t ChannelNum,\r
+ uint32_t src,\r
+ uint32_t dst,\r
+ uint32_t Size,\r
+ IP_GPDMA_FLOW_CONTROL_T TransferType);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __GPDMA_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx GPIO driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __GPIO_18XX_43XX_H_\r
+#define __GPIO_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup GPIO_18XX_43XX CHIP: LPC18xx/43xx GPIO Driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize GPIO block\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)\r
+{\r
+ IP_GPIO_Init(pGPIO);\r
+}\r
+\r
+/**\r
+ * @brief Set a GPIO port/bit state\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param port : GPIO port to set\r
+ * @param bit : GPIO bit to set\r
+ * @param setting : true for high, false for low\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)\r
+{\r
+ IP_GPIO_WritePortBit(pGPIO, port, bit, setting);\r
+}\r
+\r
+/**\r
+ * @brief Seta GPIO direction\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param port : GPIO port to set\r
+ * @param bit : GPIO bit to set\r
+ * @param setting : true for output, false for input\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)\r
+{\r
+ IP_GPIO_WriteDirBit(pGPIO, port, bit, setting);\r
+}\r
+\r
+/**\r
+ * @brief Read a GPIO state\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param port : GPIO port to read\r
+ * @param bit : GPIO bit to read\r
+ * @return true of the GPIO is high, false if low\r
+ */\r
+STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)\r
+{\r
+ return IP_GPIO_ReadPortBit(pGPIO, port, bit);\r
+}\r
+\r
+/**\r
+ * @brief Read a GPIO direction (out or in)\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param port : GPIO port to read\r
+ * @param bit : GPIO bit to read\r
+ * @return true of the GPIO is an output, false if input\r
+ */\r
+STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)\r
+{\r
+ return IP_GPIO_ReadDirBit(pGPIO, port, bit);\r
+}\r
+\r
+/**\r
+ * @brief Enable GPIO Interrupt\r
+ * @param pGPIOPinInt : The base of GPIO pin interrupt peripheral on the chip\r
+ * @param portNum : GPIO port number interrupt, should be: 0 to 7\r
+ * @param bitValue : GPIO bit to enable (Not used)\r
+ * @param intMode : Interrupt mode, should be:\r
+ * 0: Rising edge interrupt mode\r
+ * 1: Falling edge interrupt mode\r
+ * 2: Active-High interrupt mode\r
+ * 3: Active-Low interrupt mode\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_GPIO_IntCmd(LPC_GPIOPININT_T* pGPIOPinInt, uint8_t portNum, uint8_t bitValue, IP_GPIOPININT_MODE_T intMode)\r
+{\r
+ IP_GPIOPININT_IntCmd(pGPIOPinInt, portNum, intMode);\r
+}\r
+\r
+/**\r
+ * @brief Get GPIO Interrupt Status\r
+ * @param pGPIOPinInt : The base of GPIO pin interrupt peripheral on the chip\r
+ * @param portNum : GPIO port number interrupt, should be: 0 to 7\r
+ * @param pinNum : GPIO pin to check (Not used)\r
+ * @param intMode : Interrupt mode (Not used)\r
+ * @return true if interrupt is pending, otherwise false\r
+ */\r
+STATIC INLINE bool Chip_GPIO_IntGetStatus(LPC_GPIOPININT_T* pGPIOPinInt, uint8_t portNum, uint8_t pinNum, uint8_t intMode)\r
+{\r
+ return IP_GPIOPININT_IntGetStatus(pGPIOPinInt, portNum);\r
+}\r
+\r
+/**\r
+ * @brief Clear GPIO Interrupt (Edge interrupt cases only)\r
+ * @param pGPIOPinInt : The base of GPIO pin interrupt peripheral on the chip\r
+ * @param portNum : GPIO port number interrupt, should be: 0 to 7\r
+ * @param bitValue : GPIO bit to clear (Not used)\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_GPIO_IntClear(LPC_GPIOPININT_T* pGPIOPinInt, uint8_t portNum, uint8_t bitValue)\r
+{\r
+ IP_GPIOPININT_IntClear(pGPIOPinInt, portNum);\r
+}\r
+\r
+/**\r
+ * @brief GPIO Group Interrupt Pin Initialization\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @param PortComb : GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality)\r
+ * @param PortTrigger : GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered)\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_GPIOGP_IntInit(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger)\r
+{\r
+ IP_GPIOGP_IntInit(pGPIOGPINT, PortComb, PortTrigger);\r
+}\r
+\r
+/**\r
+ * @brief GPIO Group Interrupt Pin Add to Group\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @param PortNum : GPIO port number, should be 0 to 7\r
+ * @param PinNum : GPIO pin number, should be 0 to 31\r
+ * @param ActiveMode : GPIO active mode, should be 0 (active LOW) and 1 (active HIGH)\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_T *pGPIOGPINT,\r
+ uint8_t PortNum,\r
+ uint8_t PinNum,\r
+ bool ActiveMode)\r
+{\r
+ IP_GPIOGP_IntPinAdd(pGPIOGPINT, PortNum, PinNum, ActiveMode);\r
+}\r
+\r
+/**\r
+ * @brief GPIO Group Interrupt Pin Remove from Group\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @param PortNum : GPIO port number, should be 0 to 7\r
+ * @param PinNum : GPIO pin number, should be 0 to 31\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum)\r
+{\r
+ IP_GPIOGP_IntPinRemove(pGPIOGPINT, PortNum, PinNum);\r
+}\r
+\r
+/**\r
+ * @brief Get GPIO Group Interrupt Get Status\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @return true if interrupt is pending, otherwise false\r
+ */\r
+STATIC INLINE bool Chip_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_T *pGPIOGPINT)\r
+{\r
+ return IP_GPIOGP_IntGetStatus(pGPIOGPINT);\r
+}\r
+\r
+/**\r
+ * @brief Clear GPIO Group Interrupt\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_GPIOGP_IntClear(IP_GPIOGROUPINT_001_T *pGPIOGPINT)\r
+{\r
+ IP_GPIOGP_IntClear(pGPIOGPINT);\r
+}\r
+\r
+/**\r
+ * @brief Set Direction for a GPIO port\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param portNum : Port Number\r
+ * @param bitValue : GPIO bit to set\r
+ * @param out : Direction value, 0 = input, !0 = output\r
+ * @return None\r
+ * @note Bits set to '0' are not altered.\r
+ */\r
+void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out);\r
+\r
+/**\r
+ * @brief Set Direction for a GPIO port\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param portNum : Port Number\r
+ * @param bitValue : GPIO bit to set\r
+ * @param out : Direction value, 0 = input, !0 = output\r
+ * @return None\r
+ * @note Bits set to '0' are not altered.\r
+ */\r
+STATIC INLINE void Chip_FIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)\r
+{\r
+ /* Same with Chip_GPIO_SetDir() */\r
+ Chip_GPIO_SetDir(pGPIO, portNum, bitValue, out);\r
+}\r
+\r
+/**\r
+ * @brief Set a GPIO port/bit to the high state\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param portNum : Port number\r
+ * @param bitValue : Bit(s) in the port to set high\r
+ * @return None\r
+ * @note Any bit set as a '0' will not have it's state changed. This only\r
+ * applies to ports configured as an output.\r
+ */\r
+STATIC INLINE void Chip_FIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)\r
+{\r
+ /* Same with GPIO_SetValue() */\r
+ pGPIO->SET[portNum] = bitValue;\r
+}\r
+\r
+/**\r
+ * @brief Set a GPIO port/bit to the low state\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param portNum : Port number\r
+ * @param bitValue : Bit(s) in the port to set low\r
+ * @return None\r
+ * @note Any bit set as a '0' will not have it's state changed. This only\r
+ * applies to ports configured as an output.\r
+ */\r
+STATIC INLINE void Chip_FIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)\r
+{\r
+ /* Same with GPIO_ClearValue() */\r
+ pGPIO->CLR[portNum] = bitValue;\r
+}\r
+\r
+/**\r
+ * @brief Read current bit states for the selected port\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param portNum : Port number to read\r
+ * @return Current value of GPIO port\r
+ * @note The current states of the bits for the port are read, regardless of\r
+ * whether the GPIO port bits are input or output.\r
+ */\r
+STATIC INLINE uint32_t Chip_FIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)\r
+{\r
+ /* Same with GPIO_ReadValue() */\r
+ return pGPIO->PIN[portNum];\r
+}\r
+\r
+/**\r
+ * @brief Set a GPIO port/bit to the high state\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param portNum : Port number\r
+ * @param bitValue : Bit(s) in the port to set high\r
+ * @return None\r
+ * @note Any bit set as a '0' will not have it's state changed. This only\r
+ * applies to ports configured as an output.\r
+ */\r
+STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)\r
+{\r
+ pGPIO->SET[portNum] = bitValue;\r
+}\r
+\r
+/**\r
+ * @brief Set a GPIO port/bit to the low state\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param portNum : Port number\r
+ * @param bitValue : Bit(s) in the port to set low\r
+ * @return None\r
+ * @note Any bit set as a '0' will not have it's state changed. This only\r
+ * applies to ports configured as an output.\r
+ */\r
+STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)\r
+{\r
+ pGPIO->CLR[portNum] = bitValue;\r
+}\r
+\r
+/**\r
+ * @brief Read current bit states for the selected port\r
+ * @param pGPIO : The base of GPIO peripheral on the chip\r
+ * @param portNum : Port number to read\r
+ * @return Current value of GPIO port\r
+ * @note The current states of the bits for the port are read, regardless of\r
+ * whether the GPIO port bits are input or output.\r
+ */\r
+STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)\r
+{\r
+ return pGPIO->PIN[portNum];\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __GPIO_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx I2C driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __I2C_18XX_43XX_H_\r
+#define __I2C_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup I2C_18XX_43XX CHIP: LPC18xx/43xx I2C Driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief I2C interface IDs\r
+ * @note\r
+ * All Chip functions will take this as the first parameter,\r
+ * I2C_NUM_INTERFACE must never be used for calling any Chip\r
+ * functions, it is only used to find the number of interfaces\r
+ * available in the Chip.\r
+ */\r
+typedef enum I2C_ID {\r
+ I2C0, /**< ID I2C0 */\r
+ I2C1, /**< ID I2C1 */\r
+ I2C_NUM_INTERFACE /**< Number of I2C interfaces in the chip */\r
+} I2C_ID_T;\r
+\r
+/**\r
+ * @brief I2C master events\r
+ */\r
+typedef enum {\r
+ I2C_EVENT_WAIT = 1, /**< I2C Wait event */\r
+ I2C_EVENT_DONE, /**< Done event that wakes up Wait event */\r
+ I2C_EVENT_LOCK, /**< Re-entrency lock event for I2C transfer */\r
+ I2C_EVENT_UNLOCK, /**< Re-entrency unlock event for I2C transfer */\r
+ I2C_EVENT_SLAVE_RX, /**< Slave receive event */\r
+ I2C_EVENT_SLAVE_TX, /**< Slave transmit event */\r
+} I2C_EVENT_T;\r
+\r
+/**\r
+ * @brief Event handler function type\r
+ */\r
+typedef void (*I2C_EVENTHANDLER_T)(I2C_ID_T, I2C_EVENT_T);\r
+\r
+/**\r
+ * @brief Initializes the LPC_I2C peripheral with specified parameter.\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @return Nothing\r
+ */\r
+void Chip_I2C_Init(I2C_ID_T id);\r
+\r
+/**\r
+ * @brief De-initializes the I2C peripheral registers to their default reset values\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @return Nothing\r
+ */\r
+void Chip_I2C_DeInit(I2C_ID_T id);\r
+\r
+/**\r
+ * @brief Set up clock rate for LPC_I2C peripheral.\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @param clockrate : Target clock rate value to initialized I2C peripheral (Hz)\r
+ * @return Nothing\r
+ * @note\r
+ * Parameter @a clockrate for I2C0 should be from 1000 up to 1000000\r
+ * (1 KHz to 1 MHz), as I2C0 support Fast Mode Plus. I2C1 @a clockrate\r
+ * should be within the range of 1000 to 400000 (1 KHz to 400 KHz). If\r
+ * the frequency is above 400KHz (Fast Plus Mode) Board_I2C_EnableFastPlus()\r
+ * must be called prior to calling this function (Only I2C0 supports frequency\r
+ * above 400 KHz).\r
+ */\r
+void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate);\r
+\r
+/**\r
+ * @brief Get current clock rate for LPC_I2C peripheral.\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @return The current I2C peripheral clock rate\r
+ */\r
+uint32_t Chip_I2C_GetClockRate(I2C_ID_T id);\r
+\r
+/**\r
+ * @brief Transmit and Receive data in master mode\r
+ * @param id : I2C peripheral selected (I2C0, I2C1 etc)\r
+ * @param xfer : Pointer to a I2C_XFER_T structure see notes below\r
+ * @return\r
+ * Any of #I2C_STATUS_T values, xfer->txSz will have number of bytes\r
+ * not sent due to error, xfer->rxSz will have the number of bytes yet\r
+ * to be received.\r
+ * @note\r
+ * The parameter @a xfer should have its member @a slaveAddr initialized\r
+ * to the 7-Bit slave address to which the master will do the xfer, Bit0\r
+ * to bit6 should have the address and Bit8 is ignored. During the transfer\r
+ * no code (like event handler) must change the content of the memory\r
+ * pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be\r
+ * initialized to the memory from which the I2C must pick the data to be\r
+ * transfered to slave and the number of bytes to send respectively, similarly\r
+ * @a rxBuff and @a rxSz must have pointer to memroy where data received\r
+ * from slave be stored and the number of data to get from slave respectilvely.\r
+ */\r
+int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer);\r
+\r
+/**\r
+ * @brief Transmit data to I2C slave using I2C Master mode\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 .. etc)\r
+ * @param slaveAddr : Slave address to which the data be written\r
+ * @param buff : Pointer to buffer having the array of data\r
+ * @param len : Number of bytes to be transfered from @a buff\r
+ * @return Number of bytes successfully transfered\r
+ */\r
+int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len);\r
+\r
+/**\r
+ * @brief Transfer a command to slave and receive data from slave after a repeated start\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @param slaveAddr : Slave address of the I2C device\r
+ * @param cmd : Command (Address/Register) to be written\r
+ * @param buff : Pointer to memory that will hold the data received\r
+ * @param len : Number of bytes to receive\r
+ * @return Number of bytes successfully received\r
+ */\r
+int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len);\r
+\r
+/**\r
+ * @brief Get pointer to current function handling the events\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @return Pointer to function handing events of I2C\r
+ */\r
+I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id);\r
+\r
+/**\r
+ * @brief Set function that must handle I2C events\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @param event : Pointer to function that will handle the event\r
+ * (Should not be NULL)\r
+ * @return 1 when successful, 0 when a transfer is on going with its own event handler\r
+ */\r
+int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event);\r
+\r
+/**\r
+ * @brief Set function that must handle I2C events\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @param slaveAddr : Slave address from which data be read\r
+ * @param buff : Pointer to memory where data read be stored\r
+ * @param len : Number of bytes to read from slave\r
+ * @return Number of bytes read successfully\r
+ */\r
+int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len);\r
+\r
+/**\r
+ * @brief Default event handler for polling operation\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @param event : Event ID of the event that called the function\r
+ * @return Nothing\r
+ */\r
+void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event);\r
+\r
+/**\r
+ * @brief Default event handler for interrupt base operation\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @param event : Event ID of the event that called the function\r
+ * @return Nothing\r
+ */\r
+void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event);\r
+\r
+/**\r
+ * @brief I2C Master transfer state change handler\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @return Nothing\r
+ * @note Usually called from the appropriate Interrupt handler\r
+ */\r
+void Chip_I2C_MasterStateHandler(I2C_ID_T id);\r
+\r
+/**\r
+ * @brief Disable I2C peripheral's operation\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @return Nothing\r
+ */\r
+void Chip_I2C_Disable(I2C_ID_T id);\r
+\r
+/**\r
+ * @brief Checks if master xfer in progress\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @return 1 if master xfer in progress 0 otherwise\r
+ * @note\r
+ * This API is generally used in interrupt handler\r
+ * of the application to decide whether to call\r
+ * master state handler or to call slave state handler\r
+ */\r
+int Chip_I2C_IsMasterActive(I2C_ID_T id);\r
+\r
+/**\r
+ * @brief Setup a slave I2C device\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @param sid : I2C Slave peripheral ID (I2C_SLAVE_0, I2C_SLAVE_1 etc)\r
+ * @param xfer : Pointer to transfer structure (see note below for more info)\r
+ * @param event : Event handler for slave transfers\r
+ * @param addrMask : Address mask to use along with slave address (see notes below for more info)\r
+ * @return Nothing\r
+ * @note\r
+ * Parameter @a xfer should point to a valid I2C_XFER_T structure object\r
+ * and must have @a slaveAddr initialized with 7bit Slave address (From Bit1 to Bit7),\r
+ * Bit0 when set enables general call handling, @a slaveAddr along with @a addrMask will\r
+ * be used to match the slave address. @a rxBuff and @a txBuff must point to valid buffers\r
+ * where slave can receive or send the data from, size of which will be provided by\r
+ * @a rxSz and @a txSz respectively. Function pointed to by @a event will be called\r
+ * for the following events #I2C_EVENT_SLAVE_RX (One byte of data received successfully\r
+ * from the master and stored inside memory pointed by xfer->rxBuff, incremented\r
+ * the pointer and decremented the @a xfer->rxSz), #I2C_EVENT_SLAVE_TX (One byte of\r
+ * data from xfer->txBuff was sent to master successfully, incremented the pointer\r
+ * and decremented xfer->txSz), #I2C_EVENT_DONE (Master is done doing its transfers\r
+ * with the slave).<br>\r
+ * <br>Bit-0 of the parameter @a addrMask is reserved and should always be 0. Any bit (BIT1\r
+ * to BIT7) set in @a addrMask will make the corresponding bit in *xfer->slaveAddr* as\r
+ * don't care. Thit is, if *xfer->slaveAddr* is (0x10 << 1) and @a addrMask is (0x03 << 1) then\r
+ * 0x10, 0x11, 0x12, 0x13 will all be considered as valid slave addresses for the registered\r
+ * slave. Upon receving any event *xfer->slaveAddr* (BIT1 to BIT7) will hold the actual\r
+ * address which was received from master.<br>\r
+ * <br><b>General Call Handling</b><br>\r
+ * Slave can receive data from master using general call address (0x00). General call\r
+ * handling must be setup as given below\r
+ * - Call Chip_I2C_SlaveSetup() with argument @a sid as I2C_SLAVE_GENERAL\r
+ * - xfer->slaveAddr ignored, argument @a addrMask ignored\r
+ * - function provided by @a event will registered to be called when slave received data using addr 0x00\r
+ * - xfer->rxBuff and xfer->rxSz should be valid in argument @a xfer\r
+ * - To handle General Call only (No other slaves are configured)\r
+ * - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)\r
+ * - setup @a xfer with slaveAddr member set to 0, @a event is ignored hence can be NULL\r
+ * - provide @a addrMask (typically 0, if not you better be knowing what you are doing)\r
+ * - To handler General Call when other slave is active\r
+ * - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)\r
+ * - setup @a xfer with slaveAddr member set to 7-Bit Slave address [from Bit1 to 7]\r
+ * - Set Bit0 of @a xfer->slaveAddr as 1\r
+ * - Provide appropriate @a addrMask\r
+ * - Argument @a event must point to function, that handles events from actual slaveAddress and not the GC\r
+ * @warning\r
+ * If the slave has only one byte in its txBuff, once that byte is transfered to master the event handler\r
+ * will be called for event #I2C_EVENT_DONE. If the master attempts to read more bytes in the same transfer\r
+ * then the slave hardware will send 0xFF to master till the end of transfer, event handler will not be\r
+ * called to notify this. For more info see section below<br>\r
+ * <br><b> Last data handling in slave </b><br>\r
+ * If the user wants to implement a slave which will read a byte from a specific location over and over\r
+ * again whenever master reads the slave. If the user initializes the xfer->txBuff as the location to read\r
+ * the byte from and xfer->txSz as 1, then say, if master reads one byte; slave will send the byte read from\r
+ * xfer->txBuff and will call the event handler with #I2C_EVENT_DONE. If the master attempts to read another\r
+ * byte instead of sending the byte read from xfer->txBuff the slave hardware will send 0xFF and no event will\r
+ * occur. To handle this issue, slave should set xfer->txSz to 2, in which case when master reads the byte\r
+ * event handler will be called with #I2C_EVENT_SLAVE_TX, in which the slave implementation can reset the buffer\r
+ * and size back to original location (i.e, xfer->txBuff--, xfer->txSz++), if the master reads another byte\r
+ * in the same transfer, byte read from xfer->txBuff will be sent and #I2C_EVENT_SLAVE_TX will be called again, and\r
+ * the process repeats.\r
+ */\r
+void Chip_I2C_SlaveSetup(I2C_ID_T id,\r
+ I2C_SLAVE_ID sid,\r
+ I2C_XFER_T *xfer,\r
+ I2C_EVENTHANDLER_T event,\r
+ uint8_t addrMask);\r
+\r
+/**\r
+ * @brief I2C Slave event handler\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @return Nothing\r
+ */\r
+void Chip_I2C_SlaveStateHandler(I2C_ID_T id);\r
+\r
+/**\r
+ * @brief I2C peripheral state change checking\r
+ * @param id : I2C peripheral ID (I2C0, I2C1 ... etc)\r
+ * @return 1 if I2C peripheral @a id has changed its state,\r
+ * 0 if there is no state change\r
+ * @note This function must be used by the application when\r
+ * the polling has to be done based on state change.\r
+ */\r
+int Chip_I2C_IsStateChanged(I2C_ID_T id);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ #ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __I2C_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx I2S driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __I2S_18XX_43XX_H_\r
+#define __I2S_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup I2S_18XX_43XX CHIP: LPC18xx/43xx I2S driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+#define I2S_DMA_REQUEST_NUMBER_1 IP_I2S_DMA_REQUEST_NUMBER_1\r
+#define I2S_DMA_REQUEST_NUMBER_2 IP_I2S_DMA_REQUEST_NUMBER_2\r
+\r
+/**\r
+ * @brief I2S Audio Format Structure\r
+ */\r
+typedef struct {\r
+ uint32_t SampleRate; /*!< Sample Rate */\r
+ uint8_t ChannelNumber; /*!< Channel Number - 1 is mono, 2 is stereo */\r
+ uint8_t WordWidth; /*!< Word Width - 8, 16 or 32 bits */\r
+} Chip_I2S_Audio_Format_T;\r
+\r
+/**\r
+ * @brief Initialize for I2S\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_I2S_Init(LPC_I2S_T *pI2S);\r
+\r
+/**\r
+ * @brief Shutdown I2S\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @return Nothing\r
+ * @note Reset all relative registers (DMA, transmit/receive control, interrupt) to default value\r
+ */\r
+void Chip_I2S_DeInit(LPC_I2S_T *pI2S);\r
+\r
+/**\r
+ * @brief Send a 32-bit data to TXFIFO for transmition\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param data : Data to be transmited\r
+ * @return Nothing\r
+ * @note The function writes to TXFIFO without checking any condition.\r
+ */\r
+STATIC INLINE void Chip_I2S_Send(LPC_I2S_T *pI2S, uint32_t data)\r
+{\r
+ IP_I2S_Send(pI2S, data);\r
+}\r
+\r
+/**\r
+ * @brief Get received data from RXFIFO\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @return Data received in RXFIFO\r
+ * @note The function reads from RXFIFO without checking any condition.\r
+ */\r
+STATIC INLINE uint32_t Chip_I2S_Receive(LPC_I2S_T *pI2S)\r
+{\r
+ return IP_I2S_Receive(pI2S);\r
+}\r
+\r
+/**\r
+ * @brief Start the I2S\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_I2S_Start(LPC_I2S_T *pI2S, uint8_t TRMode)\r
+{\r
+ IP_I2S_Start(pI2S, TRMode);\r
+}\r
+\r
+/**\r
+ * @brief Disables accesses on FIFOs, places the transmit channel in mute mode\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_I2S_Pause(LPC_I2S_T *pI2S, uint8_t TRMode)\r
+{\r
+ IP_I2S_Pause(pI2S, TRMode);\r
+}\r
+\r
+/**\r
+ * @brief Mute the Transmit channel\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @return Nothing\r
+ * @note The data output from I2S transmit channel is always zeroes\r
+ */\r
+STATIC INLINE void Chip_I2S_EnableMute(LPC_I2S_T *pI2S)\r
+{\r
+ IP_I2S_EnableMute(pI2S);\r
+}\r
+\r
+/**\r
+ * @brief Un-Mute the I2S channel\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_I2S_DisableMute(LPC_I2S_T *pI2S)\r
+{\r
+ IP_I2S_DisableMute(pI2S);\r
+}\r
+\r
+/**\r
+ * @brief Stop I2S asynchronously\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @return Nothing\r
+ * @note Pause, resets the transmit channel and FIFO asynchronously\r
+ */\r
+STATIC INLINE void Chip_I2S_Stop(LPC_I2S_T *pI2S, uint8_t TRMode)\r
+{\r
+ IP_I2S_Stop(pI2S, TRMode);\r
+}\r
+\r
+/**\r
+ * @brief Set the I2S operating modes\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param clksel : Clock source selection for the receive bit clock divider\r
+ * @param fpin : Receive 4-pin mode selection\r
+ * @param mcena : Enable for the RX_MCLK output\r
+ * @return Nothing\r
+ * @note In addition to master and slave modes, which are independently configurable for\r
+ * the transmitter and the receiver, several different clock sources are possible,\r
+ * including variations that share the clock and/or WS between the transmitter and\r
+ * receiver. It also allows using I2S with fewer pins, typically four.\r
+ */\r
+STATIC INLINE void Chip_I2S_ModeConfig(LPC_I2S_T *pI2S,\r
+ uint8_t TRMode,\r
+ uint32_t clksel,\r
+ uint32_t fpin,\r
+ uint32_t mcena)\r
+{\r
+ IP_I2S_ModeConfig(pI2S, TRMode, clksel, fpin, mcena);\r
+}\r
+\r
+/**\r
+ * @brief Get the current level of the Transmit/Receive FIFO\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @return Current level of the Transmit/Receive FIFO\r
+ */\r
+STATIC INLINE uint8_t Chip_I2S_GetLevel(LPC_I2S_T *pI2S, uint8_t TRMode)\r
+{\r
+ return IP_I2S_GetLevel(pI2S, TRMode);\r
+}\r
+\r
+/**\r
+ * @brief Configure I2S for Audio Format input\r
+ * @param pI2S : The base I2S peripheral on the chip\r
+ * @param TRMode : Mode Rx/Tx\r
+ * @param audio_format : Audio Format\r
+ * @return SUCCESS or ERROR\r
+ */\r
+Status Chip_I2S_Config(LPC_I2S_T *pI2S, uint8_t TRMode, Chip_I2S_Audio_Format_T *audio_format);\r
+\r
+/**\r
+ * @brief Enable/Disable Interrupt with a specific FIFO depth\r
+ * @param pI2S : The base I2S peripheral on the chip\r
+ * @param TRMode : Mode Rx/Tx\r
+ * @param NewState : ENABLE or DISABLE interrupt\r
+ * @param FIFO_Depth : FIFO level creating an irq request\r
+ * @return Nothing\r
+ */\r
+void Chip_I2S_Int_Cmd(LPC_I2S_T *pI2S, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth);\r
+\r
+/**\r
+ * @brief Enable/Disable DMA with a specific FIFO depth\r
+ * @param pI2S : The base I2S peripheral on the chip\r
+ * @param TRMode : Mode Rx/Tx\r
+ * @param DMANum : Should be\r
+ * - IP_I2S_DMA_REQUEST_NUMBER_1 : Using DMA1\r
+ * - IP_I2S_DMA_REQUEST_NUMBER_2 : Using DMA2\r
+ * @param NewState : ENABLE or DISABLE interrupt\r
+ * @param FIFO_Depth : FIFO level creating an irq request\r
+ * @return Nothing\r
+ */\r
+void Chip_I2S_DMA_Cmd(LPC_I2S_T *pI2S, uint8_t TRMode, uint8_t DMANum, FunctionalState NewState, uint8_t FIFO_Depth);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __I2S_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx LCD chip driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __LCD_18XX_43XX_H_\r
+#define __LCD_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup LCD_18XX_43XX CHIP: LPC18xx/43xx LCD driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the LCD controller\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param LCD_ConfigStruct : Pointer to LCD configuration\r
+ * @return LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error\r
+ */\r
+void Chip_LCD_Init(LPC_LCD_T *pLCD, LCD_Config_T *LCD_ConfigStruct);\r
+\r
+/**\r
+ * @brief Shutdown the LCD controller\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_LCD_DeInit(LPC_LCD_T *pLCD);\r
+\r
+/**\r
+ * @brief Power-on the LCD Panel (power pin)\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_PowerOn(LPC_LCD_T *pLCD)\r
+{\r
+ IP_LCD_PowerOn(pLCD);\r
+}\r
+\r
+/**\r
+ * @brief Power-off the LCD Panel (power pin)\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_PowerOff(LPC_LCD_T *pLCD)\r
+{\r
+ IP_LCD_PowerOff(pLCD);\r
+}\r
+\r
+/**\r
+ * @brief Enable/Disable the LCD Controller\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_Enable(LPC_LCD_T *pLCD)\r
+{\r
+ IP_LCD_Enable(pLCD);\r
+}\r
+\r
+/**\r
+ * @brief Enable/Disable the LCD Controller\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_Disable(LPC_LCD_T *pLCD)\r
+{\r
+ IP_LCD_Disable(pLCD);\r
+}\r
+\r
+/**\r
+ * @brief Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame\r
+ * Buffer for Dual Panel\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param buffer : address of buffer\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_SetUPFrameBuffer(LPC_LCD_T *pLCD, void *buffer)\r
+{\r
+ IP_LCD_SetUPFrameBuffer(pLCD, buffer);\r
+}\r
+\r
+/**\r
+ * @brief Set LCD Lower Panel Frame Buffer for Dual Panel\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param buffer : address of buffer\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_SetLPFrameBuffer(LPC_LCD_T *pLCD, void *buffer)\r
+{\r
+ IP_LCD_SetLPFrameBuffer(pLCD, buffer);\r
+}\r
+\r
+/**\r
+ * @brief Configure Cursor\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param cursor_size : specify size of cursor\r
+ * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels\r
+ * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels\r
+ * @param sync : cursor sync mode\r
+ * - TRUE :cursor sync to the frame sync pulse\r
+ * - FALSE :cursor async mode\r
+ * @return None\r
+ */\r
+void Chip_LCD_Cursor_Config(LPC_LCD_T *pLCD, IP_LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync);\r
+\r
+/**\r
+ * @brief Enable Cursor\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param cursor_num : specify number of cursor is going to be written\r
+ * this param must < 4\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_Cursor_Enable(LPC_LCD_T *pLCD, uint8_t cursor_num)\r
+{\r
+ IP_LCD_Cursor_Enable(pLCD, cursor_num);\r
+}\r
+\r
+/**\r
+ * @brief Disable Cursor\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param cursor_num : specify number of cursor is going to be written\r
+ * this param must < 4\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_Cursor_Disable(LPC_LCD_T *pLCD, uint8_t cursor_num)\r
+{\r
+ IP_LCD_Cursor_Disable(pLCD, cursor_num);\r
+}\r
+\r
+/**\r
+ * @brief Load Cursor Palette\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param palette_color : cursor palette 0 value\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_Cursor_LoadPalette0(LPC_LCD_T *pLCD, uint32_t palette_color)\r
+{\r
+ IP_LCD_Cursor_LoadPalette0(pLCD, palette_color);\r
+}\r
+\r
+/**\r
+ * @brief Load Cursor Palette\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param palette_color : cursor palette 1 value\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_Cursor_LoadPalette1(LPC_LCD_T *pLCD, uint32_t palette_color)\r
+{\r
+ IP_LCD_Cursor_LoadPalette1(pLCD, palette_color);\r
+}\r
+\r
+/**\r
+ * @brief Set Cursor Position\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param x : horizontal position\r
+ * @param y : vertical position\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_Cursor_SetPos(LPC_LCD_T *pLCD, uint16_t x, uint16_t y)\r
+{\r
+ IP_LCD_Cursor_SetPos(pLCD, x, y);\r
+}\r
+\r
+/**\r
+ * @brief Set Cursor Clipping Position\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param x : horizontal position, should be in range: 0..63\r
+ * @param y : vertical position, should be in range: 0..63\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_Cursor_SetClip(LPC_LCD_T *pLCD, uint16_t x, uint16_t y)\r
+{\r
+ IP_LCD_Cursor_SetClip(pLCD, x, y);\r
+}\r
+\r
+/**\r
+ * @brief Enable Controller Interrupt\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param ints : OR'ed interrupt bits to enable\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_EnableInts(LPC_LCD_T *pLCD, uint32_t ints)\r
+{\r
+ IP_LCD_EnableInts(pLCD, ints);\r
+}\r
+\r
+/**\r
+ * @brief Disable Controller Interrupt\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param ints : OR'ed interrupt bits to disable\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_DisableInts(LPC_LCD_T *pLCD, uint32_t ints)\r
+{\r
+ IP_LCD_DisableInts(pLCD, ints);\r
+}\r
+\r
+/**\r
+ * @brief Clear Controller Interrupt\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param ints : OR'ed interrupt bits to clear\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_LCD_ClearInts(LPC_LCD_T *pLCD, uint32_t ints)\r
+{\r
+ IP_LCD_ClearInts(pLCD, ints);\r
+}\r
+\r
+/**\r
+ * @brief Write Cursor Image into Internal Cursor Image Buffer\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param cursor_num : Cursor index\r
+ * @param Image : Pointer to image data\r
+ * @return None\r
+ */\r
+void Chip_LCD_Cursor_WriteImage(LPC_LCD_T *pLCD, uint8_t cursor_num, void *Image);\r
+\r
+/**\r
+ * @brief Load LCD Palette\r
+ * @param pLCD : The base of LCD peripheral on the chip\r
+ * @param palette : Address of palette table to load\r
+ * @return None\r
+ */\r
+void Chip_LCD_LoadPalette(LPC_LCD_T *pLCD, void *palette);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __LCD_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx OTP Controller driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __OTP_18XX_43XX_H_\r
+#define __OTP_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup OTP_18XX_43XX CHIP: LPC18xx/43xx OTP Controller driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief OTP Register block\r
+ */\r
+typedef struct {\r
+ __IO uint32_t OTP0_0; /*!< (@ 0x40045000) OTP content */\r
+ __IO uint32_t OTP0_1; /*!< (@ 0x40045004) OTP content */\r
+ __IO uint32_t OTP0_2; /*!< (@ 0x40045008) OTP content */\r
+ __IO uint32_t OTP0_3; /*!< (@ 0x4004500C) OTP content */\r
+ __IO uint32_t OTP1_0; /*!< (@ 0x40045010) OTP content */\r
+ __IO uint32_t OTP1_1; /*!< (@ 0x40045014) OTP content */\r
+ __IO uint32_t OTP1_2; /*!< (@ 0x40045018) OTP content */\r
+ __IO uint32_t OTP1_3; /*!< (@ 0x4004501C) OTP content */\r
+ __IO uint32_t OTP2_0; /*!< (@ 0x40045020) OTP content */\r
+ __IO uint32_t OTP2_1; /*!< (@ 0x40045024) OTP content */\r
+ __IO uint32_t OTP2_2; /*!< (@ 0x40045028) OTP content */\r
+ __IO uint32_t OTP2_3; /*!< (@ 0x4004502C) OTP content */\r
+ uint32_t RESERVED0[4];\r
+ __IO uint32_t UNIQUE_KEY0; /*!< (@ 0x40045040) Unique Key bit 31..0. R/W locked at default */\r
+ __IO uint32_t UNIQUE_KEY1; /*!< (@ 0x40045044) Unique Key bit 63..32. R/W locked at default */\r
+ __IO uint32_t UNIQUE_KEY2; /*!< (@ 0x40045048) Unique Key bit 95..64. R/W locked at default */\r
+ __IO uint32_t UNIQUE_KEY3; /*!< (@ 0x4004504C) Unique Key bit 127..96. R/W locked at default */\r
+ __IO uint32_t RANDOM_NUM0; /*!< (@ 0x40045050) Random number bit 31..0. R/W locked at default */\r
+ __IO uint32_t RANDOM_NUM1; /*!< (@ 0x40045054) Random number bit 63..32. R/W locked at default */\r
+ __IO uint32_t RANDOM_NUM2; /*!< (@ 0x40045058) Random number bit 95..64. R/W locked at default */\r
+ __IO uint32_t RANDOM_NUM3; /*!< (@ 0x4004505C) Random number bit 127..96. R/W locked at default */\r
+ __IO uint32_t USER_KEY0; /*!< (@ 0x40045060) User Key bit 31..0. R locked at default */\r
+ __IO uint32_t USER_KEY1; /*!< (@ 0x40045064) User Key bit 63..32. R locked at default */\r
+ __IO uint32_t USER_KEY2; /*!< (@ 0x40045068) User Key bit 95..64. R locked at default */\r
+ __IO uint32_t USER_KEY3; /*!< (@ 0x4004506C) User Key bit 127..96. R locked at default */\r
+ uint32_t RESERVED1[4];\r
+ __IO uint32_t WRTMASK; /*!< (@ 0x40045080) Masks APB write to fuses */\r
+ __O uint32_t STATUS; /*!< (@ 0x40045084) Indicates write status of fuses */\r
+ uint32_t RESERVED2[2];\r
+ __IO uint32_t PROGRAM; /*!< (@ 0x40045090) Enables write of Shuffled AES value to OTP1c */\r
+ __IO uint32_t AES_SSEL; /*!< (@ 0x40045094) Controls selecting source for SKey output to AES Engine */\r
+ __IO uint32_t SHUFFLE_CTRL; /*!< (@ 0x40045098) Shuffle block control */\r
+ uint32_t RESERVED3;\r
+ __IO uint32_t OTP0_WR_LOCK; /*!< (@ 0x400450A0) Locks write access to itself and OTP0 write access */\r
+ __IO uint32_t OTP0_RD_LOCK; /*!< (@ 0x400450A4) Locks write access to itself and OTP0 read access */\r
+ __IO uint32_t OTP1_WR_LOCK; /*!< (@ 0x400450A8) Locks write access to itself and OTP1 write access */\r
+ __IO uint32_t OTP1_RD_LOCK; /*!< (@ 0x400450AC) Locks write access to itself and OTP1 read access */\r
+ __IO uint32_t OTP2_WR_LOCK; /*!< (@ 0x400450B0) Locks write access to itself and OTP2 write access */\r
+ __IO uint32_t OTP2_RD_LOCK; /*!< (@ 0x400450B4) Locks write access to itself and OTP2 read access */\r
+ __IO uint32_t RESERVED4[2];\r
+ __IO uint32_t UNIQUE_KEY_WR_LOCK; /*!< (@ 0x400450C0) Locks write access to itself and Unique Key write access */\r
+ __IO uint32_t UNIQUE_KEY_RD_LOCK; /*!< (@ 0x400450C4) */\r
+ __IO uint32_t RANDOM_NUM_WR_LOCK; /*!< (@ 0x400450C8) */\r
+ __IO uint32_t RANDOM_NUM_RD_LOCK; /*!< (@ 0x400450CC) */\r
+ __IO uint32_t RESERVED5; /*!< (@ 0x400450D0) */\r
+ __IO uint32_t USER_KEY_RD_LOCK; /*!< (@ 0x400450D4) */\r
+} LPC_OTP_T;\r
+\r
+/**\r
+ * @brief OTP Boot Source selection used in Chip driver\r
+ */\r
+typedef enum CHIP_OTP_BOOT_SRC {\r
+ CHIP_OTP_BOOTSRC_PINS, /*!< Boot source - External pins */\r
+ CHIP_OTP_BOOTSRC_UART0, /*!< Boot source - UART0 */\r
+ CHIP_OTP_BOOTSRC_SPIFI, /*!< Boot source - EMC 8-bit memory */\r
+ CHIP_OTP_BOOTSRC_EMC8, /*!< Boot source - EMC 16-bit memory */\r
+ CHIP_OTP_BOOTSRC_EMC16, /*!< Boot source - EMC 32-bit memory */\r
+ CHIP_OTP_BOOTSRC_EMC32, /*!< Boot source - EMC 32-bit memory */\r
+ CHIP_OTP_BOOTSRC_USB0, /*!< Boot source - DFU USB0 boot */\r
+ CHIP_OTP_BOOTSRC_USB1, /*!< Boot source - DFU USB1 boot */\r
+ CHIP_OTP_BOOTSRC_SPI, /*!< Boot source - SPI boot */\r
+ CHIP_OTP_BOOTSRC_UART3 /*!< Boot source - UART3 */\r
+} CHIP_OTP_BOOT_SRC_T;\r
+\r
+/**\r
+ * @brief Initialize for OTP Controller functions\r
+ * @return Status of Otp_Init function\r
+ * This function will initialise all the OTP driver function pointers\r
+ * and call the ROM OTP Initialisation function.\r
+ */\r
+uint32_t Chip_OTP_Init(void);\r
+\r
+/**\r
+ * @brief Program boot source in OTP Controller\r
+ * @param BootSrc : Boot Source enum value\r
+ * @return Status\r
+ */\r
+uint32_t Chip_OTP_ProgBootSrc(CHIP_OTP_BOOT_SRC_T BootSrc);\r
+\r
+/**\r
+ * @brief Program the JTAG bit in OTP Controller\r
+ * @return Status\r
+ */\r
+uint32_t Chip_OTP_ProgJTAGDis(void);\r
+\r
+/**\r
+ * @brief Program USB ID in OTP Controller\r
+ * @param ProductID : USB Product ID\r
+ * @param VendorID : USB Vendor ID\r
+ * @return Status\r
+ */\r
+uint32_t Chip_OTP_ProgUSBID(uint32_t ProductID, uint32_t VendorID);\r
+\r
+/**\r
+ * @brief Program OTP GP Word memory\r
+ * @param WordNum : Word Number (Select word 0 or word 1 or word 2)\r
+ * @param Data : Data value\r
+ * @param Mask : Mask value\r
+ * @return Status\r
+ * This function available in devices which are not AES capable\r
+ */\r
+uint32_t Chip_OTP_ProgGPWord(uint32_t WordNum, uint32_t Data, uint32_t Mask);\r
+\r
+/**\r
+ * @brief Program AES Key\r
+ * @param KeyNum : Key Number (Select 0 or 1)\r
+ * @param key : Pointer to AES Key (16 bytes required)\r
+ * @return Status\r
+ * This function available in devices which are AES capable\r
+ */\r
+uint32_t Chip_OTP_ProgKey(uint32_t KeyNum, uint8_t *key);\r
+\r
+/**\r
+ * @brief Generate Random Number using HW Random Number Generator\r
+ * @return Random Number value\r
+ */\r
+uint32_t Chip_OTP_GenRand(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __OTP_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx Power Management Controller driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __PMC_18XX_43XX_H_\r
+#define __PMC_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup PMC_18XX_43XX CHIP: LPC18xx/43xx Power Management Controller driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/*\r
+ * @brief PMC power states\r
+ */\r
+typedef enum CHIP_PMC_PWR_STATE {\r
+ PMC_DeepSleep = PMC_PWR_DEEP_SLEEP_MODE, /*!< Deep sleep state */\r
+ PMC_PowerDown = PMC_PWR_POWER_DOWN_MODE, /*!< Power Down state */\r
+ PMC_DeepPowerDown = PMC_PWR_DEEP_POWER_DOWN_MODE, /*!< Power Down state */\r
+} CHIP_PMC_PWR_STATE_T;\r
+\r
+/**\r
+ * @brief Set to sleep power state\r
+ * @return Nothing\r
+ */\r
+void Chip_PMC_Sleep(void);\r
+\r
+/**\r
+ * @brief Set to sleep power mode\r
+ * @param PwrState : Power State as specified in /a CHIP_PMC_PWR_STATE_T enum\r
+ * @return Nothing\r
+ */\r
+void Chip_PMC_Set_PwrState(CHIP_PMC_PWR_STATE_T PwrState);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __PMC_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx Reset Generator Unit driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#include "chip.h"\r
+\r
+/*****************************************************************************\r
+ * Private types/enumerations/variables\r
+ ****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Public types/enumerations/variables\r
+ ****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Private functions\r
+ ****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Public functions\r
+ ****************************************************************************/\r
+\r
+/* Trigger a peripheral reset for the selected peripheral */\r
+void Chip_RGU_TriggerReset(CHIP_RGU_RST_T ResetNumber)\r
+{\r
+ volatile uint32_t *p;\r
+\r
+ /* To trigger reset- write RESET_CTRLx with a 1 bit */\r
+ p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);\r
+\r
+ /* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */\r
+ p += ResetNumber / 32;\r
+\r
+ /* On the LPC18xx and LPC43xx, most of the reset bits automatically clear\r
+ after 1 clock cycle, so set the bit and return */\r
+ *p = (1 << (ResetNumber % 32));\r
+}\r
+\r
+/* Clears reset for the selected peripheral */\r
+void Chip_RGU_ClearReset(CHIP_RGU_RST_T ResetNumber)\r
+{\r
+ volatile uint32_t *p;\r
+\r
+ /* To trigger reset- write RESET_CTRLx with a 1 bit */\r
+ p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0);\r
+\r
+ /* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */\r
+ p += ResetNumber / 32;\r
+\r
+ /* On the LPC18xx and LPC43xx, most of the reset bits automatically clear\r
+ after 1 clock cycle, so set the bit and return */\r
+ *p = 0;\r
+}\r
+\r
+/* Checks the reset status of a peripheral */\r
+bool Chip_RGU_InReset(CHIP_RGU_RST_T ResetNumber)\r
+{\r
+ volatile uint32_t *read;\r
+\r
+ read = (volatile uint32_t *) &(LPC_RGU->RESET_ACTIVE_STATUS0);\r
+ read += ResetNumber / 32;\r
+\r
+ /* Reset not asserted if bit is set */\r
+ return (bool) ((*read & (1 << (ResetNumber % 32))) == 0);\r
+}\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx Reset Generator Unit driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __RGU_18XX_43XX_H_\r
+#define __RGU_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup RGU_18XX_43XX CHIP: LPC18xx/43xx Reset Generator Unit (RGU) driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief RGU reset enumerations\r
+ */\r
+typedef enum CHIP_RGU_RST {\r
+ RGU_CORE_RST,\r
+ RGU_PERIPH_RST,\r
+ RGU_MASTER_RST,\r
+ RGU_WWDT_RST = 4,\r
+ RGU_CREG_RST,\r
+ RGU_BUS_RST = 8,\r
+ RGU_SCU_RST,\r
+ RGU_M3_RST = 13,\r
+ RGU_LCD_RST = 16,\r
+ RGU_USB0_RST,\r
+ RGU_USB1_RST,\r
+ RGU_DMA_RST,\r
+ RGU_SDIO_RST,\r
+ RGU_EMC_RST,\r
+ RGU_ETHERNET_RST,\r
+ RGU_FLASHA_RST = 25,\r
+ RGU_EEPROM_RST = 27,\r
+ RGU_GPIO_RST,\r
+ RGU_FLASHB_RST,\r
+ RGU_TIMER0_RST = 32,\r
+ RGU_TIMER1_RST,\r
+ RGU_TIMER2_RST,\r
+ RGU_TIMER3_RST,\r
+ RGU_RITIMER_RST,\r
+ RGU_SCT_RST,\r
+ RGU_MOTOCONPWM_RST,\r
+ RGU_QEI_RST,\r
+ RGU_ADC0_RST,\r
+ RGU_ADC1_RST,\r
+ RGU_DAC_RST,\r
+ RGU_UART0_RST = 44,\r
+ RGU_UART1_RST,\r
+ RGU_UART2_RST,\r
+ RGU_UART3_RST,\r
+ RGU_I2C0_RST,\r
+ RGU_I2C1_RST,\r
+ RGU_SSP0_RST,\r
+ RGU_SSP1_RST,\r
+ RGU_I2S_RST,\r
+ RGU_SPIFI_RST,\r
+ RGU_CAN1_RST,\r
+ RGU_CAN0_RST,\r
+#ifdef CHIP_LPC43XX\r
+ RGU_M0APP_RST,\r
+ RGU_SGPIO_RST,\r
+ RGU_SPI_RST,\r
+#endif\r
+ RGU_LAST_RST = 63,\r
+} CHIP_RGU_RST_T;\r
+\r
+/**\r
+ * @brief RGU register structure\r
+ */\r
+typedef struct { /*!< RGU Structure */\r
+ __I uint32_t RESERVED0[64];\r
+ __O uint32_t RESET_CTRL0; /*!< Reset control register 0 */\r
+ __O uint32_t RESET_CTRL1; /*!< Reset control register 1 */\r
+ __I uint32_t RESERVED1[2];\r
+ __IO uint32_t RESET_STATUS0; /*!< Reset status register 0 */\r
+ __IO uint32_t RESET_STATUS1; /*!< Reset status register 1 */\r
+ __IO uint32_t RESET_STATUS2; /*!< Reset status register 2 */\r
+ __IO uint32_t RESET_STATUS3; /*!< Reset status register 3 */\r
+ __I uint32_t RESERVED2[12];\r
+ __I uint32_t RESET_ACTIVE_STATUS0; /*!< Reset active status register 0 */\r
+ __I uint32_t RESET_ACTIVE_STATUS1; /*!< Reset active status register 1 */\r
+ __I uint32_t RESERVED3[170];\r
+ __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/*!< Reset external status registers */\r
+} LPC_RGU_T;\r
+\r
+/**\r
+ * @brief Trigger a peripheral reset for the selected peripheral\r
+ * @param ResetNumber : Peripheral reset number to trigger\r
+ * @return Nothing\r
+ */\r
+void Chip_RGU_TriggerReset(CHIP_RGU_RST_T ResetNumber);\r
+\r
+/**\r
+ * @brief Checks the reset status of a peripheral\r
+ * @param ResetNumber : Peripheral reset number to trigger\r
+ * @return true if the periperal is still being reset\r
+ */\r
+bool Chip_RGU_InReset(CHIP_RGU_RST_T ResetNumber);\r
+\r
+/**\r
+ * @brief Clears reset for the selected peripheral\r
+ * @param ResetNumber : Peripheral reset number to trigger\r
+ * @return Nothing\r
+ * Almost all peripherals will auto clear the reset bit. Only a few peripherals\r
+ * like the Cortex M0 Core in LPC43xx will not auto clear the reset and require\r
+ * this function to clear the reset bit.\r
+ */\r
+void Chip_RGU_ClearReset(CHIP_RGU_RST_T ResetNumber);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __RGU_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx RITimer chip driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __RITIMER_18XX_43XX_H_\r
+#define __RITIMER_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup RIT_18XX_43XX CHIP: LPC18xx/43xx RIT driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the RIT\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @return None\r
+ */\r
+void Chip_RIT_Init(LPC_RITIMER_T *pRITimer);\r
+\r
+/**\r
+ * @brief Shutdown the RIT\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @return None\r
+ */\r
+void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer);\r
+\r
+/**\r
+ * @brief Enable Timer\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RIT_Enable(LPC_RITIMER_T *pRITimer)\r
+{\r
+ IP_RIT_Enable(pRITimer);\r
+}\r
+\r
+/**\r
+ * @brief Disable Timer\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RIT_Disable(LPC_RITIMER_T *pRITimer)\r
+{\r
+ IP_RIT_Disable(pRITimer);\r
+}\r
+\r
+/**\r
+ * @brief Enable timer debug\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RIT_TimerDebugEnable(LPC_RITIMER_T *pRITimer)\r
+{\r
+ IP_RIT_TimerDebugEnable(pRITimer);\r
+}\r
+\r
+/**\r
+ * @brief Disable timer debug\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RIT_TimerDebugDisable(LPC_RITIMER_T *pRITimer)\r
+{\r
+ IP_RIT_TimerDebugDisable(pRITimer);\r
+}\r
+\r
+/**\r
+ * @brief Check whether interrupt flag is set or not\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @return Current interrupt status, either ET or UNSET\r
+ */\r
+STATIC INLINE IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer)\r
+{\r
+ return IP_RIT_GetIntStatus(pRITimer);\r
+}\r
+\r
+/**\r
+ * @brief Set a tick value for the interrupt to time out\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @param val : value (in ticks) of the interrupt to be set\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RIT_SetCOMPVAL(LPC_RITIMER_T *pRITimer, uint32_t val)\r
+{\r
+ IP_RIT_SetCOMPVAL(pRITimer, val);\r
+}\r
+\r
+/**\r
+ * @brief Enables or clears the RIT or interrupt\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @param val : RIT to be set, one or more RIT_CTRL_* values\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RIT_EnableCTRL(LPC_RITIMER_T *pRITimer, uint32_t val)\r
+{\r
+ IP_RIT_EnableCTRL(pRITimer, val);\r
+}\r
+\r
+/**\r
+ * @brief Clears the RIT interrupt\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RIT_ClearInt(LPC_RITIMER_T *pRITimer)\r
+{\r
+ IP_RIT_EnableCTRL(pRITimer, RIT_CTRL_INT);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current RIT Counter value\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @return the current timer counter value\r
+ */\r
+STATIC INLINE uint32_t Chip_RIT_GetCounter(LPC_RITIMER_T *pRITimer)\r
+{\r
+ return IP_RIT_GetCounter(pRITimer);\r
+}\r
+\r
+/**\r
+ * @brief Set timer interval value\r
+ * @param pRITimer : RITimer peripheral selected\r
+ * @param time_interval : timer interval value (ms)\r
+ * @return None\r
+ */\r
+void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __RITIMER_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx RTC driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __RTC_18XX_43XX_H_\r
+#define __RTC_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup RTC_18XX_43XX CHIP: LPC18xx/43xx RTC driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @return None\r
+ */\r
+void Chip_RTC_Init(LPC_RTC_T *pRTC);\r
+\r
+/**\r
+ * @brief De-initialize the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_DeInit(LPC_RTC_T *pRTC)\r
+{\r
+ IP_RTC_DeInit(LPC_RTC);\r
+}\r
+\r
+/**\r
+ * @brief Reset clock tick counter in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_ResetClockTickCounter(LPC_RTC_T *pRTC)\r
+{\r
+ IP_RTC_ResetClockTickCounter(LPC_RTC);\r
+}\r
+\r
+/**\r
+ * @brief Start/Stop RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param NewState : New State of this function, should be:\r
+ * - ENABLE :The time counters are enabled\r
+ * - DISABLE :The time counters are disabled\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_Enable(LPC_RTC_T *pRTC, FunctionalState NewState)\r
+{\r
+ IP_RTC_Enable(LPC_RTC, NewState);\r
+}\r
+\r
+/**\r
+ * @brief Enable/Disable Counter increment interrupt for a time type\r
+ * in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param cntrMask : Or'ed bit values for time types (RTC_AMR_CIIR_IM*)\r
+ * @param NewState : ENABLE or DISABLE\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_CntIncrIntConfig(LPC_RTC_T *pRTC, uint32_t cntrMask, FunctionalState NewState)\r
+{\r
+ IP_RTC_CntIncrIntConfig(LPC_RTC, cntrMask, NewState);\r
+}\r
+\r
+/**\r
+ * @brief Enable/Disable Alarm interrupt for a time type\r
+ * in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param alarmMask : Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)\r
+ * @param NewState : ENABLE or DISABLE\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_AlarmIntConfig(LPC_RTC_T *pRTC, uint32_t alarmMask, FunctionalState NewState)\r
+{\r
+ IP_RTC_AlarmIntConfig(LPC_RTC, alarmMask, NewState);\r
+}\r
+\r
+/**\r
+ * @brief Set current time value for a time type in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param Timetype : time field index type to set\r
+ * @param TimeValue : Value to palce in time field\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_SetTime(LPC_RTC_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue)\r
+{\r
+ IP_RTC_SetTime(LPC_RTC, Timetype, TimeValue);\r
+}\r
+\r
+/**\r
+ * @brief Get current time value for a type time type\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param Timetype : Time field index type to get\r
+ * @return Value of time field according to specified time type\r
+ */\r
+STATIC INLINE uint32_t Chip_RTC_GetTime(LPC_RTC_T *pRTC, IP_RTC_TIMEINDEX_T Timetype)\r
+{\r
+ return IP_RTC_GetTime(LPC_RTC, Timetype);\r
+}\r
+\r
+/**\r
+ * @brief Set full time in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param pFullTime : Pointer to full time data\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_SetFullTime(LPC_RTC_T *pRTC, IP_RTC_TIME_T *pFullTime)\r
+{\r
+ IP_RTC_SetFullTime(LPC_RTC, pFullTime);\r
+}\r
+\r
+/**\r
+ * @brief Get full time from the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param pFullTime : Pointer to full time record to fill\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_GetFullTime(LPC_RTC_T *pRTC, IP_RTC_TIME_T *pFullTime)\r
+{\r
+ IP_RTC_GetFullTime(LPC_RTC, pFullTime);\r
+}\r
+\r
+/**\r
+ * @brief Set alarm time value for a time type\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param Timetype : Time index field to set\r
+ * @param ALValue : Alarm time value to set\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_SetAlarmTime(LPC_RTC_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue)\r
+{\r
+ IP_RTC_SetAlarmTime(LPC_RTC, Timetype, ALValue);\r
+}\r
+\r
+/**\r
+ * @brief Get alarm time value for a time type\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param Timetype : Time index field to get\r
+ * @return Value of Alarm time according to specified time type\r
+ */\r
+STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(LPC_RTC_T *pRTC, IP_RTC_TIMEINDEX_T Timetype)\r
+{\r
+ return IP_RTC_GetAlarmTime(LPC_RTC, Timetype);\r
+}\r
+\r
+/**\r
+ * @brief Set full alarm time in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param pFullTime : Pointer to full time record to set alarm\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_SetFullAlarmTime(LPC_RTC_T *pRTC, IP_RTC_TIME_T *pFullTime)\r
+{\r
+ IP_RTC_SetFullAlarmTime(LPC_RTC, pFullTime);\r
+}\r
+\r
+/**\r
+ * @brief Get full alarm time in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param pFullTime : Pointer to full time record to fill\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_GetFullAlarmTime(LPC_RTC_T *pRTC, IP_RTC_TIME_T *pFullTime)\r
+{\r
+ IP_RTC_GetFullAlarmTime(LPC_RTC, pFullTime);\r
+}\r
+\r
+/**\r
+ * @brief Write value to General purpose registers\r
+ * @param pRegFile : RegFile peripheral selected\r
+ * @param index : General purpose register index\r
+ * @param Value : Value to write\r
+ * @return None\r
+ * @note These General purpose registers can be used to store important\r
+ * information when the main power supply is off. The value in these\r
+ * registers is not affected by chip reset. These registers are\r
+ * powered in the RTC power domain.\r
+ */\r
+STATIC INLINE void Chip_REGFILE_Write(LPC_REGFILE_T *pRegFile, uint8_t index, uint32_t Value)\r
+{\r
+ IP_REGFILE_Write(pRegFile, index, Value);\r
+}\r
+\r
+/**\r
+ * @brief Read value from General purpose registers\r
+ * @param pRegFile : RegFile peripheral selected\r
+ * @param index : General purpose register index\r
+ * @return Read Value\r
+ * @note TheseGeneral purpose registers can be used to store important\r
+ * information when the main power supply is off. The value in these\r
+ * registers is not affected by chip reset. These registers are\r
+ * powered in the RTC power domain.\r
+ */\r
+STATIC INLINE uint32_t Chip_REGFILE_Read(LPC_REGFILE_T *pRegFile, uint8_t index)\r
+{\r
+ return IP_REGFILE_Read(pRegFile, index);\r
+}\r
+\r
+/**\r
+ * @brief Enable/Disable calibration counter in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param NewState : New State of this function, should be:\r
+ * - ENABLE :The calibration counter is enabled and counting\r
+ * - DISABLE :The calibration counter is disabled and reset to zero\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_CalibCounterCmd(LPC_RTC_T *pRTC, FunctionalState NewState)\r
+{\r
+ IP_RTC_CalibCounterCmd(LPC_RTC, NewState);\r
+}\r
+\r
+/**\r
+ * @brief Configures Calibration in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param CalibValue : Calibration value, should be in range from 0 to 131,072\r
+ * @param CalibDir : Calibration Direction, should be:\r
+ * - RTC_CALIB_DIR_FORWARD :Forward calibration\r
+ * - RTC_CALIB_DIR_BACKWARD :Backward calibration\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_CalibConfig(LPC_RTC_T *pRTC, uint32_t CalibValue, uint8_t CalibDir)\r
+{\r
+ IP_RTC_CalibConfig(LPC_RTC, CalibValue, CalibDir);\r
+}\r
+\r
+/**\r
+ * @brief Clear specified Location interrupt pending in the RTC peripheral\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param IntType : Interrupt location type, should be:\r
+ * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending.\r
+ * - RTC_INT_ALARM :Clear alarm interrupt pending\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_RTC_ClearIntPending(LPC_RTC_T *pRTC, uint32_t IntType)\r
+{\r
+ IP_RTC_ClearIntPending(LPC_RTC, IntType);\r
+}\r
+\r
+/**\r
+ * @brief Check whether if specified location interrupt in the RTC peripheral is set or not\r
+ * @param pRTC : RTC peripheral selected\r
+ * @param IntType : Interrupt location type, should be:\r
+ * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.\r
+ * - RTC_INT_ALARM: Alarm generated an interrupt.\r
+ * @return New state of specified Location interrupt in RTC peripheral, SET OR RESET\r
+ */\r
+STATIC INLINE IntStatus Chip_RTC_GetIntPending(LPC_RTC_T *pRTC, uint32_t IntType)\r
+{\r
+ return IP_RTC_GetIntPending(LPC_RTC, IntType);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __RTC_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx State Configurable Timer driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SCT_18XX_43XX_H_\r
+#define __SCT_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup SCT_18XX_43XX CHIP: LPC18xx/43xx State Configurable Timer driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize SCT\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @return Nothing\r
+ */\r
+void Chip_SCT_Init(LPC_SCT_T *pSCT);\r
+\r
+/**\r
+ * @brief Shutdown SCT\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @return Nothing\r
+ */\r
+void Chip_SCT_DeInit(LPC_SCT_T *pSCT);\r
+\r
+/**\r
+ * @brief Configure SCT\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param value : SCT Configuration register value\r
+ * @return Nothing\r
+ * Initialise the SCT configuration register with \a value\r
+ */\r
+STATIC INLINE void Chip_SCT_Config(LPC_SCT_T *pSCT, uint32_t value)\r
+{\r
+ IP_SCT_Config(pSCT, value);\r
+}\r
+\r
+/**\r
+ * @brief Set or Clear the Control register\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param value : SCT Control register value\r
+ * @param ena : ENABLE - To set the fields specified by value\r
+ * : DISABLE - To clear the field specified by value\r
+ * @return Nothing\r
+ * Set or clear the control register bits as specified by the \a value\r
+ * parameter. If \a ena is set to ENABLE, the mentioned register fields\r
+ * will be set. If \a ena is set to DISABLE, the mentioned register\r
+ * fields will be cleared\r
+ */\r
+STATIC INLINE void Chip_SCT_ControlSetClr(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena)\r
+{\r
+ IP_SCT_ControlSetClr(pSCT, value, ena);\r
+}\r
+\r
+/**\r
+ * @brief Set the conflict resolution\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param outnum : Output number\r
+ * @param value : Output value\r
+ * - SCT_RES_NOCHANGE :No change\r
+ * - SCT_RES_SET_OUTPUT :Set output\r
+ * - SCT_RES_CLEAR_OUTPUT :Clear output\r
+ * - SCT_RES_TOGGLE_OUTPUT :Toggle output\r
+ * : SCT_RES_NOCHANGE\r
+ * : DISABLE - To clear the field specified by value\r
+ * @return Nothing\r
+ * Set conflict resolution for the output \a outnum\r
+ */\r
+STATIC INLINE void Chip_SCT_ConflictResolutionSet(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value)\r
+{\r
+ IP_SCT_ConflictResolutionSet(pSCT, outnum, value);\r
+}\r
+\r
+/**\r
+ * @brief Clear the SCT event flag\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param even_num : SCT Event number\r
+ * @return Nothing\r
+ * Clear the SCT event flag for the specified event \a even_num\r
+ */\r
+STATIC INLINE void Chip_SCT_EventFlagClear(LPC_SCT_T *pSCT, uint8_t even_num)\r
+{\r
+ IP_SCT_EventFlagClear(pSCT, even_num);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SCT_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SCU_18XX_43XX_H_\r
+#define __SCU_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup SCU_18XX_43XX CHIP: LPC18xx/43xx SCU Driver (configures pin functions)\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief System Control Unit register block\r
+ */\r
+typedef struct {\r
+ __IO uint32_t SFSP[16][32];\r
+ __I uint32_t RESERVED0[256];\r
+ __IO uint32_t SFSCLK[4]; /*!< Pin configuration register for pins CLK0-3 */\r
+ __I uint32_t RESERVED16[28];\r
+ __IO uint32_t SFSUSB; /*!< Pin configuration register for USB */\r
+ __IO uint32_t SFSI2C0; /*!< Pin configuration register for I2C0-bus pins */\r
+ __IO uint32_t ENAIO[3]; /*!< Analog function select registerS */\r
+ __I uint32_t RESERVED17[27];\r
+ __IO uint32_t EMCDELAYCLK; /*!< EMC clock delay register */\r
+ __I uint32_t RESERVED18[63];\r
+ __IO uint32_t PINTSEL0; /*!< Pin interrupt select register for pin interrupts 0 to 3. */\r
+ __IO uint32_t PINTSEL1; /*!< Pin interrupt select register for pin interrupts 4 to 7. */\r
+} LPC_SCU_T;\r
+\r
+/**\r
+ * SCU function and mode selection definitions\r
+ * See the User Manual for specific modes and functions supoprted by the\r
+ * various LPC18xx/43xx devices. Functionality can vary per device.\r
+ */\r
+#define SCU_MODE_MODE_INACT (0x0 << 3) /*!< Disable pull-down and pull-up resistor at resistor at pad */\r
+#define SCU_MODE_MODE_PULLDOWN (0x1 << 3) /*!< Enable pull-down resistor at pad */\r
+#define SCU_MODE_MODE_PULLUP (0x2 << 3) /*!< Enable pull-up resistor at pad */\r
+#define SCU_MODE_MODE_REPEATER (0x3 << 3) /*!< Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */\r
+#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /*!< Enable high-speed slew */\r
+#define SCU_MODE_INBUFF_EN (0x1 << 6) /*!< Enable Input buffer */\r
+#define SCU_MODE_ZIF_DIS (0x1 << 7) /*!< Disable input glitch filter */\r
+#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /*!< Normal drive: 4mA drive strength */\r
+#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /*!< Medium drive: 8mA drive strength */\r
+#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /*!< High drive: 14mA drive strength */\r
+#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /*!< Ultra high- drive: 20mA drive strength */\r
+#define SCU_MODE_FUNC0 0x0 /*!< Selects pin function 0 */\r
+#define SCU_MODE_FUNC1 0x1 /*!< Selects pin function 1 */\r
+#define SCU_MODE_FUNC2 0x2 /*!< Selects pin function 2 */\r
+#define SCU_MODE_FUNC3 0x3 /*!< Selects pin function 3 */\r
+#define SCU_MODE_FUNC4 0x4 /*!< Selects pin function 4 */\r
+#define SCU_MODE_FUNC5 0x5 /*!< Selects pin function 5 */\r
+#define SCU_MODE_FUNC6 0x6 /*!< Selects pin function 6 */\r
+#define SCU_MODE_FUNC7 0x7 /*!< Selects pin function 7 */\r
+#define SCU_PINIO_FAST (SCU_MODE_MODE_PULLUP | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)\r
+\r
+/**\r
+ * SCU function and mode selection definitions (old)\r
+ * For backwards compatibility.\r
+ */\r
+#define MD_PUP (0x0 << 3) /** Disable pull-down and pull-up resistor at resistor at pad */\r
+#define MD_BUK (0x1 << 3) /** Enable pull-down resistor at pad */\r
+#define MD_PLN (0x2 << 3) /** Enable pull-up resistor at pad */\r
+#define MD_PDN (0x3 << 3) /** Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */\r
+#define MD_EHS (0x1 << 5) /** Enable fast slew rate */\r
+#define MD_EZI (0x1 << 6) /** Input buffer enable */\r
+#define MD_ZI (0x1 << 7) /** Disable input glitch filter */\r
+#define MD_EHD0 (0x1 << 8) /** EHD driver strength low bit */\r
+#define MD_EHD1 (0x1 << 8) /** EHD driver strength high bit */\r
+#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)\r
+#define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /** Pin configuration for STANDARD/FAST mode I2C */\r
+#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /** Pin configuration for Fast-mode Plus I2C */\r
+#define FUNC0 0x0 /** Pin function 0 */\r
+#define FUNC1 0x1 /** Pin function 1 */\r
+#define FUNC2 0x2 /** Pin function 2 */\r
+#define FUNC3 0x3 /** Pin function 3 */\r
+#define FUNC4 0x4 /** Pin function 4 */\r
+#define FUNC5 0x5 /** Pin function 5 */\r
+#define FUNC6 0x6 /** Pin function 6 */\r
+#define FUNC7 0x7 /** Pin function 7 */\r
+\r
+#define PORT_OFFSET 0x80 /** Port offset definition */\r
+#define PIN_OFFSET 0x04 /** Pin offset definition */\r
+\r
+/** Returns the SFSP register address in the SCU for a pin and port, recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */\r
+#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))\r
+\r
+/** Returns the address in the SCU for a SFSCLK clock register, recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */\r
+#define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))\r
+\r
+/**\r
+ * @brief Sets I/O Control pin mux\r
+ * @param port : Port number, should be: 0..15\r
+ * @param pin : Pin number, should be: 0..31\r
+ * @param modefunc : OR'ed values or type SCU_MODE_*\r
+ * @return Nothing\r
+ * @note Do not use for clock pins (SFSCLK0 .. SFSCLK4). Use\r
+ * Chip_SCU_ClockPinMux() function for SFSCLKx clock pins.\r
+ */\r
+STATIC INLINE void Chip_SCU_PinMuxSet(uint8_t port, uint8_t pin, uint16_t modefunc)\r
+{\r
+ LPC_SCU->SFSP[port][pin] = modefunc;\r
+}\r
+\r
+/**\r
+ * @brief Configure pin function\r
+ * @param port : Port number, should be: 0..15\r
+ * @param pin : Pin number, should be: 0..31\r
+ * @param mode : OR'ed values or type SCU_MODE_*\r
+ * @param func : Pin function, value of type SCU_MODE_FUNC0 to SCU_MODE_FUNC7\r
+ * @return Nothing\r
+ * @note Do not use for clock pins (SFSCLK0 .. SFSCLK4). Use\r
+ * Chip_SCU_ClockPinMux() function for SFSCLKx clock pins.\r
+ */\r
+STATIC INLINE void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)\r
+{\r
+ Chip_SCU_PinMuxSet(port, pin, (mode | (uint16_t) func));\r
+}\r
+\r
+/**\r
+ * @brief Configure clock pin function (pins SFSCLKx)\r
+ * @param clknum : Clock pin number, should be: 0..3\r
+ * @param modefunc : OR'ed values or type SCU_MODE_*\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SCU_ClockPinMuxSet(uint8_t clknum, uint16_t modefunc)\r
+{\r
+ LPC_SCU->SFSCLK[clknum] = (uint32_t) modefunc;\r
+}\r
+\r
+/**\r
+ * @brief Configure clock pin function (pins SFSCLKx)\r
+ * @param clknum : Clock pin number, should be: 0..3\r
+ * @param mode : OR'ed values or type SCU_MODE_*\r
+ * @param func : Pin function, value of type SCU_MODE_FUNC0 to SCU_MODE_FUNC7\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SCU_ClockPinMux(uint8_t clknum, uint16_t mode, uint8_t func)\r
+{\r
+ LPC_SCU->SFSCLK[clknum] = ((uint32_t) mode | (uint32_t) func);\r
+}\r
+\r
+/**\r
+ * @brief GPIO Interrupt Pin Select\r
+ * @param PortSel : GPIO PINTSEL interrupt, should be: 0 to 7\r
+ * @param PortNum : GPIO port number interrupt, should be: 0 to 7\r
+ * @param PinNum : GPIO pin number Interrupt , should be: 0 to 31\r
+ * @return Nothing\r
+ */\r
+void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum);\r
+\r
+/**\r
+ * @brief I2C Pin Configuration\r
+ * @param I2C0Mode : I2C0 mode, should be:\r
+ * - I2C0_STANDARD_FAST_MODE: Standard/Fast mode transmit\r
+ * - I2C0_FAST_MODE_PLUS: Fast-mode Plus transmit\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode)\r
+{\r
+ LPC_SCU->SFSI2C0 = I2C0Mode;\r
+}\r
+\r
+/**\r
+ * @brief ADC Pin Configuration\r
+ * @param ADC_ID : ADC number\r
+ * @param channel : ADC channel\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel)\r
+{\r
+ LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel;\r
+}\r
+\r
+/**\r
+ * @brief DAC Pin Configuration\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SCU_DAC_Analog_Config(void)\r
+{\r
+ /*Enable analog function DAC on pin P4_4*/\r
+ LPC_SCU->ENAIO[2] |= 1;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SCU_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx SD/SDIO driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SDIF_18XX_43XX_H_\r
+#define __SDIF_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup SDIF_18XX_43XX CHIP: LPC18xx/43xx SD/SDIO driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/** @brief Setup options for the SDIO driver\r
+ */\r
+#define US_TIMEOUT 1000000 /*!< give 1 atleast 1 sec for the card to respond */\r
+#define MS_ACQUIRE_DELAY (10) /*!< inter-command acquire oper condition delay in msec*/\r
+#define INIT_OP_RETRIES 50 /*!< initial OP_COND retries */\r
+#define SET_OP_RETRIES 1000 /*!< set OP_COND retries */\r
+#define SDIO_BUS_WIDTH 4 /*!< Max bus width supported */\r
+#define SD_MMC_ENUM_CLOCK 400000 /*!< Typical enumeration clock rate */\r
+#define MMC_MAX_CLOCK 20000000 /*!< Max MMC clock rate */\r
+#define MMC_LOW_BUS_MAX_CLOCK 26000000 /*!< Type 0 MMC card max clock rate */\r
+#define MMC_HIGH_BUS_MAX_CLOCK 52000000 /*!< Type 1 MMC card max clock rate */\r
+#define SD_MAX_CLOCK 25000000 /*!< Max SD clock rate */\r
+\r
+/**\r
+ * @brief Detect if an SD card is inserted\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return Returns 0 if a card is detected, otherwise 1\r
+ * @note Detect if an SD card is inserted\r
+ * (uses SD_CD pin, returns 0 on card detect)\r
+ */\r
+STATIC INLINE int32_t Chip_SDIF_CardNDetect(LPC_SDMMC_T *pSDMMC)\r
+{\r
+ return IP_SDMMC_CardNDetect(pSDMMC);\r
+}\r
+\r
+/**\r
+ * @brief Detect if write protect is enabled\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return Returns 1 if card is write protected, otherwise 0\r
+ * @note Detect if write protect is enabled\r
+ * (uses SD_WP pin, returns 1 if card is write protected)\r
+ */\r
+STATIC INLINE int32_t Chip_SDIF_CardWpOn(LPC_SDMMC_T *pSDMMC)\r
+{\r
+ return IP_SDMMC_CardWpOn(pSDMMC);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SD/MMC card controller\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return None\r
+ */\r
+void Chip_SDIF_Init(LPC_SDMMC_T *pSDMMC);\r
+\r
+/**\r
+ * @brief Shutdown the SD/MMC card controller\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return None\r
+ */\r
+void Chip_SDIF_DeInit(LPC_SDMMC_T *pSDMMC);\r
+\r
+/**\r
+ * @brief Disable slot power\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return None\r
+ * @note Uses SD_POW pin, set to low.\r
+ */\r
+STATIC INLINE void Chip_SDIF_PowerOff(LPC_SDMMC_T *pSDMMC)\r
+{\r
+ IP_SDMMC_PowerOff(pSDMMC);\r
+}\r
+\r
+/**\r
+ * @brief Enable slot power\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return None\r
+ * @note Uses SD_POW pin, set to high.\r
+ */\r
+STATIC INLINE void Chip_SDIF_PowerOn(LPC_SDMMC_T *pSDMMC)\r
+{\r
+ IP_SDMMC_PowerOn(pSDMMC);\r
+}\r
+\r
+/**\r
+ * @brief Sets the SD interface interrupt mask\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @param iVal : Interrupts to enable, Or'ed values MCI_INT_*\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_SDIF_SetIntMask(LPC_SDMMC_T *pSDMMC, uint32_t iVal)\r
+{\r
+ IP_SDMMC_SetIntMask(pSDMMC, iVal);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current SD status, clears pending ints, and disables all ints\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return Current pending interrupt status of Or'ed values MCI_INT_*\r
+ */\r
+uint32_t Chip_SDIF_GetIntStatus(LPC_SDMMC_T *pSDMMC);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SDIF_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx SD/MMC card driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SDMMC_18XX_43XX_H_\r
+#define __SDMMC_18XX_43XX_H_\r
+\r
+#include "lpc_sdmmc.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup SDMMC_18XX_43XX CHIP: LPC18xx/43xx SD/MMC driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+#define CMD_MASK_RESP (0x3UL << 28)\r
+#define CMD_RESP(r) (((r) & 0x3) << 28)\r
+#define CMD_RESP_R0 (0 << 28)\r
+#define CMD_RESP_R1 (1 << 28)\r
+#define CMD_RESP_R2 (2 << 28)\r
+#define CMD_RESP_R3 (3 << 28)\r
+#define CMD_BIT_AUTO_STOP (1 << 24)\r
+#define CMD_BIT_APP (1 << 23)\r
+#define CMD_BIT_INIT (1 << 22)\r
+#define CMD_BIT_BUSY (1 << 21)\r
+#define CMD_BIT_LS (1 << 20) /* Low speed, used during acquire */\r
+#define CMD_BIT_DATA (1 << 19)\r
+#define CMD_BIT_WRITE (1 << 18)\r
+#define CMD_BIT_STREAM (1 << 17)\r
+#define CMD_MASK_CMD (0xff)\r
+#define CMD_SHIFT_CMD (0)\r
+\r
+#define CMD(c, r) ( ((c) & CMD_MASK_CMD) | CMD_RESP((r)) )\r
+\r
+#define CMD_IDLE CMD(MMC_GO_IDLE_STATE, 0) | CMD_BIT_LS | CMD_BIT_INIT\r
+#define CMD_SD_OP_COND CMD(SD_APP_OP_COND, 1) | CMD_BIT_LS | CMD_BIT_APP\r
+#define CMD_SD_SEND_IF_COND CMD(SD_CMD8, 1) | CMD_BIT_LS\r
+#define CMD_MMC_OP_COND CMD(MMC_SEND_OP_COND, 3) | CMD_BIT_LS | CMD_BIT_INIT\r
+#define CMD_ALL_SEND_CID CMD(MMC_ALL_SEND_CID, 2) | CMD_BIT_LS\r
+#define CMD_MMC_SET_RCA CMD(MMC_SET_RELATIVE_ADDR, 1) | CMD_BIT_LS\r
+#define CMD_SD_SEND_RCA CMD(SD_SEND_RELATIVE_ADDR, 1) | CMD_BIT_LS\r
+#define CMD_SEND_CSD CMD(MMC_SEND_CSD, 2) | CMD_BIT_LS\r
+#define CMD_SEND_EXT_CSD CMD(MMC_SEND_EXT_CSD, 1) | CMD_BIT_LS | CMD_BIT_DATA\r
+#define CMD_DESELECT_CARD CMD(MMC_SELECT_CARD, 0)\r
+#define CMD_SELECT_CARD CMD(MMC_SELECT_CARD, 1)\r
+#define CMD_SET_BLOCKLEN CMD(MMC_SET_BLOCKLEN, 1)\r
+#define CMD_SEND_STATUS CMD(MMC_SEND_STATUS, 1)\r
+#define CMD_READ_SINGLE CMD(MMC_READ_SINGLE_BLOCK, 1) | CMD_BIT_DATA\r
+#define CMD_READ_MULTIPLE CMD(MMC_READ_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_AUTO_STOP\r
+#define CMD_SD_SET_WIDTH CMD(SD_APP_SET_BUS_WIDTH, 1) | CMD_BIT_APP\r
+#define CMD_STOP CMD(MMC_STOP_TRANSMISSION, 1) | CMD_BIT_BUSY\r
+#define CMD_WRITE_SINGLE CMD(MMC_WRITE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE\r
+#define CMD_WRITE_MULTIPLE CMD(MMC_WRITE_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE | CMD_BIT_AUTO_STOP\r
+\r
+/* Card specific setup data */\r
+typedef struct _mci_card_struct {\r
+ sdif_device sdif_dev;\r
+ SDMMC_CARD_T card_info;\r
+} mci_card_struct;\r
+\r
+/**\r
+ * @brief Get card's current state (idle, transfer, program, etc.)\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return Current SD card transfer state\r
+ */\r
+int32_t Chip_SDMMC_GetState(LPC_SDMMC_T *pSDMMC);\r
+\r
+/**\r
+ * @brief Function to enumerate the SD/MMC/SDHC/MMC+ cards\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @param pcardinfo : Pointer to pre-allocated card info structure\r
+ * @return 1 if a card is acquired, otherwise 0\r
+ */\r
+uint32_t Chip_SDMMC_Acquire(LPC_SDMMC_T *pSDMMC, mci_card_struct *pcardinfo);\r
+\r
+/**\r
+ * @brief Get the device size of SD/MMC card (after enumeration)\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return Card size in number of bytes (capacity)\r
+ */\r
+int32_t Chip_SDMMC_GetDeviceSize(LPC_SDMMC_T *pSDMMC);\r
+\r
+/**\r
+ * @brief Get the number of device blocks of SD/MMC card (after enumeration)\r
+ * Since Chip_SDMMC_GetDeviceSize is limited to 32 bits cards with greater than\r
+ * 2 GBytes of data will not be correct, in such cases users can use this function\r
+ * to get the size of the card in blocks.\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @return Number of 512 bytes blocks in the card\r
+ */\r
+int32_t Chip_SDMMC_GetDeviceBlocks(LPC_SDMMC_T *pSDMMC);\r
+\r
+/**\r
+ * @brief Performs the read of data from the SD/MMC card\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @param buffer : Pointer to data buffer to copy to\r
+ * @param start_block : Start block number\r
+ * @param num_blocks : Number of block to read\r
+ * @return Bytes read, or 0 on error\r
+ */\r
+int32_t Chip_SDMMC_ReadBlocks(LPC_SDMMC_T *pSDMMC, void *buffer, int32_t start_block, int32_t num_blocks);\r
+\r
+/**\r
+ * @brief Performs write of data to the SD/MMC card\r
+ * @param pSDMMC : SDMMC peripheral selected\r
+ * @param buffer : Pointer to data buffer to copy to\r
+ * @param start_block : Start block number\r
+ * @param num_blocks : Number of block to write\r
+ * @return Number of bytes actually written, or 0 on error\r
+ */\r
+int32_t Chip_SDMMC_WriteBlocks(LPC_SDMMC_T *pSDMMC, void *buffer, int32_t start_block, int32_t num_blocks);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SDMMC_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx SSP driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SSP_18XX_43XX_H_\r
+#define __SSP_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup SSP_18XX_43XX CHIP: LPC18xx/43xx SSP driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/*\r
+ * @brief SSP clock format\r
+ */\r
+typedef enum CHIP_SSP_CLOCK_FORMAT {\r
+ SSP_CLOCK_CPHA0_CPOL0 = (0 << 6), /**< CPHA = 0, CPOL = 0 */\r
+ SSP_CLOCK_CPHA0_CPOL1 = (1u << 6), /**< CPHA = 0, CPOL = 1 */\r
+ SSP_CLOCK_CPHA1_CPOL0 = (2u << 6), /**< CPHA = 1, CPOL = 0 */\r
+ SSP_CLOCK_CPHA1_CPOL1 = (3u << 6), /**< CPHA = 1, CPOL = 1 */\r
+ SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */\r
+ SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */\r
+ SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */\r
+ SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */\r
+} CHIP_SSP_CLOCK_MODE_T;\r
+\r
+/*\r
+ * @brief SSP frame format\r
+ */\r
+typedef enum CHIP_SSP_FRAME_FORMAT {\r
+ SSP_FRAMEFORMAT_SPI = (0 << 4), /**< Frame format: SPI */\r
+ CHIP_SSP_FRAME_FORMAT_TI = (1u << 4), /**< Frame format: TI SSI */\r
+ SSP_FRAMEFORMAT_MICROWIRE = (2u << 4), /**< Frame format: Microwire */\r
+} CHIP_SSP_FRAME_FORMAT_T;\r
+\r
+/*\r
+ * @brief Number of bits per frame\r
+ */\r
+typedef enum CHIP_SSP_BITS {\r
+ SSP_BITS_4 = (3u << 0), /**< 4 bits/frame */\r
+ SSP_BITS_5 = (4u << 0), /**< 5 bits/frame */\r
+ SSP_BITS_6 = (5u << 0), /**< 6 bits/frame */\r
+ SSP_BITS_7 = (6u << 0), /**< 7 bits/frame */\r
+ SSP_BITS_8 = (7u << 0), /**< 8 bits/frame */\r
+ SSP_BITS_9 = (8u << 0), /**< 9 bits/frame */\r
+ SSP_BITS_10 = (9u << 0), /**< 10 bits/frame */\r
+ SSP_BITS_11 = (10u << 0), /**< 11 bits/frame */\r
+ SSP_BITS_12 = (11u << 0), /**< 12 bits/frame */\r
+ SSP_BITS_13 = (12u << 0), /**< 13 bits/frame */\r
+ SSP_BITS_14 = (13u << 0), /**< 14 bits/frame */\r
+ SSP_BITS_15 = (14u << 0), /**< 15 bits/frame */\r
+ SSP_BITS_16 = (15u << 0), /**< 16 bits/frame */\r
+} CHIP_SSP_BITS_T;\r
+\r
+/*\r
+ * @brief SSP config format\r
+ */\r
+typedef struct SSP_ConfigFormat {\r
+ CHIP_SSP_BITS_T bits; /**< Format config: bits/frame */\r
+ CHIP_SSP_CLOCK_MODE_T clockMode;/**< Format config: clock phase/polarity */\r
+ CHIP_SSP_FRAME_FORMAT_T frameFormat;/**< Format config: SPI/TI/Microwire */\r
+} SSP_ConfigFormat;\r
+\r
+/*\r
+ * @brief SSP mode\r
+ */\r
+typedef enum CHIP_SSP_MODE {\r
+ SSP_MODE_MASTER = (0 << 2), /**< Master mode */\r
+ SSP_MODE_SLAVE = (1u << 2), /**< Slave mode */\r
+} CHIP_SSP_MODE_T;\r
+\r
+/*\r
+ * @brief SPI address\r
+ */\r
+typedef struct {\r
+ uint8_t port;\r
+ uint8_t pin;\r
+} SPI_Address_t;\r
+\r
+/*\r
+ * @brief SSP data setup structure\r
+ */\r
+typedef struct {\r
+ void *tx_data; /**< Pointer to transmit data */\r
+ uint32_t tx_cnt; /**< Transmit counter */\r
+ void *rx_data; /**< Pointer to transmit data */\r
+ uint32_t rx_cnt; /**< Receive counter */\r
+ uint32_t length; /**< Length of transfer data */\r
+} Chip_SSP_DATA_SETUP_T;\r
+\r
+/** SSP configuration parameter defines */\r
+/** Clock phase control bit */\r
+#define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST\r
+#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND\r
+\r
+/** Clock polarity control bit */\r
+/* There's no bug here!!!\r
+ * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.\r
+ * That means the active clock is in HI state.\r
+ * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock\r
+ * high between frames. That means the active clock is in LO state.\r
+ */\r
+#define SSP_CPOL_HI SSP_CR0_CPOL_LO\r
+#define SSP_CPOL_LO SSP_CR0_CPOL_HI\r
+\r
+/** SSP master mode enable */\r
+#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN\r
+#define SSP_MASTER_MODE SSP_CR1_MASTER_EN\r
+\r
+/**\r
+ * @brief Get the current status of SSP controller\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param Stat : Type of status, should be :\r
+ * - SSP_STAT_TFE\r
+ * - SSP_STAT_TNF\r
+ * - SSP_STAT_RNE\r
+ * - SSP_STAT_RFF\r
+ * - SSP_STAT_BSY\r
+ * @return SSP controller status, SET or RESET\r
+ */\r
+STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, IP_SSP_STATUS_T Stat)\r
+{\r
+ return IP_SSP_GetStatus(pSSP, Stat);\r
+}\r
+\r
+/**\r
+ * @brief Enable SSP operation\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)\r
+{\r
+ IP_SSP_Enable(pSSP);\r
+}\r
+\r
+/**\r
+ * @brief Disable SSP operation\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)\r
+{\r
+ IP_SSP_Disable(pSSP);\r
+}\r
+\r
+/**\r
+ * @brief Enable SSP DMA\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SSP_DMA_Enable(LPC_SSP_T *pSSP)\r
+{\r
+ IP_SSP_DMA_Enable(pSSP, SSP_DMA_BITMASK);\r
+}\r
+\r
+/**\r
+ * @brief Disable SSP DMA\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SSP_DMA_Disable(LPC_SSP_T *pSSP)\r
+{\r
+ IP_SSP_DMA_Disable(pSSP, SSP_DMA_BITMASK);\r
+}\r
+\r
+/**\r
+ * @brief Enable loopback mode\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ * @note Serial input is taken from the serial output (MOSI or MISO) rather\r
+ * than the serial input pin\r
+ */\r
+STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)\r
+{\r
+ IP_SSP_EnableLoopBack(pSSP);\r
+}\r
+\r
+/**\r
+ * @brief Disable loopback mode\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ * @note Serial input is taken from the serial output (MOSI or MISO) rather\r
+ * than the serial input pin\r
+ */\r
+STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)\r
+{\r
+ IP_SSP_DisableLoopBack(pSSP);\r
+}\r
+\r
+/**\r
+ * @brief Clean all data in RX FIFO of SSP\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);\r
+\r
+/**\r
+ * @brief SSP Interrupt Read/Write with 8-bit frame width\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified\r
+ * information about transmit/receive data configuration\r
+ * @return SUCCESS or ERROR\r
+ */\r
+Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);\r
+\r
+/**\r
+ * @brief SSP Interrupt Read/Write with 16-bit frame width\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified\r
+ * information about transmit/receive data configuration\r
+ * @return SUCCESS or ERROR\r
+ */\r
+Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);\r
+\r
+/**\r
+ * @brief SSP Polling Read/Write in blocking mode\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified\r
+ * information about transmit/receive data configuration\r
+ * @return Actual data length has been transferred\r
+ *\r
+ * This function can be used in both master and slave mode. It starts with writing phase and after that,\r
+ * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared\r
+ * through xf_setup param.\r
+ */\r
+uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);\r
+\r
+/**\r
+ * @brief SSP Polling Write in blocking mode\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @param buffer : Buffer address\r
+ * @param buffer_len : Buffer length\r
+ * @return Actual data length has been transferred\r
+ *\r
+ * This function can be used in both master and slave mode. First, a writing operation will send\r
+ * the needed data. After that, a dummy reading operation is generated to clear data buffer\r
+ */\r
+uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);\r
+\r
+/**\r
+ * @brief Note here\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @param buffer : Buffer address\r
+ * @param buffer_len : The length of buffer\r
+ * @return Actual data length has been transferred\r
+ *\r
+ * This function can be used in both master and slave mode. First, a dummy writing operation is generated\r
+ * to clear data buffer. After that, a reading operation will receive the needed data\r
+ */\r
+uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);\r
+\r
+/**\r
+ * @brief Initialize the SSP\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_SSP_Init(LPC_SSP_T *pSSP);\r
+\r
+/**\r
+ * @brief Shutdown the SSP\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void Chip_SSP_DeInit(LPC_SSP_T *pSSP);\r
+\r
+/**\r
+ * @brief Set the SSP operating modes, master or slave\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @param master : 1 to set master, 0 to set slave\r
+ * @return Nothing\r
+ */\r
+void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);\r
+\r
+/**\r
+ * @brief Set the clock frequency for SSP interface\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @param bitRate : The SSP bit rate\r
+ * @return Nothing\r
+ */\r
+void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);\r
+\r
+/**\r
+ * @brief Set up the SSP frame format\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @param format : Structure used to format frame\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, SSP_ConfigFormat *format)\r
+{\r
+ IP_SSP_SetFormat(pSSP, format->bits, format->frameFormat, format->clockMode);\r
+}\r
+\r
+/**\r
+ * @brief Enable SSP interrupt\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)\r
+{\r
+ IP_SSP_Int_Enable(pSSP, SSP_TXIM);\r
+}\r
+\r
+/**\r
+ * @brief Disable SSP interrupt\r
+ * @param pSSP : The base SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)\r
+{\r
+ IP_SSP_Int_Disable(pSSP, SSP_TXIM);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SSP_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief 18xx/43xx Timer/PWM control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __TIMER_18XX_43XX_H_\r
+#define __TIMER_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup TIMER_18XX_43XX CHIP: LPC18xx/43xx Timer driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initialize a timer\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @return Nothing\r
+ */\r
+void Chip_TIMER_Init(LPC_TIMER_T *pTMR);\r
+\r
+/**\r
+ * @brief Shutdown a timer\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @return Nothing\r
+ */\r
+void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);\r
+\r
+/**\r
+ * @brief Determine if a match interrupt is pending\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param matchnum : Match interrupt number to check\r
+ * @return false if the interrupt is not pending, otherwise true\r
+ * Determine if the match interrupt for the passed timer and match\r
+ * counter is pending.\r
+ */\r
+STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)\r
+{\r
+ return IP_TIMER_MatchPending(pTMR, matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Determine if a capture interrupt is pending\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capnum : Capture interrupt number to check\r
+ * @return false if the interrupt is not pending, otherwise true\r
+ * Determine if the capture interrupt for the passed capture pin is\r
+ * pending.\r
+ */\r
+STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)\r
+{\r
+ return IP_TIMER_CapturePending(pTMR, capnum);\r
+}\r
+\r
+/**\r
+ * @brief Clears a (pending) match interrupt\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param matchnum : Match interrupt number to clear\r
+ * @return Nothing\r
+ * Clears a pending timer match interrupt.\r
+ */\r
+STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)\r
+{\r
+ IP_TIMER_ClearMatch(pTMR, matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Clears a (pending) capture interrupt\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capnum : Capture interrupt number to clear\r
+ * @return Nothing\r
+ * Clears a pending timer capture interrupt.\r
+ */\r
+STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)\r
+{\r
+ IP_TIMER_ClearCapture(pTMR, capnum);\r
+}\r
+\r
+/**\r
+ * @brief Enables the timer (starts count)\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @return Nothing\r
+ * Enables the timer to start counting.\r
+ */\r
+STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)\r
+{\r
+ IP_TIMER_Enable(pTMR);\r
+}\r
+\r
+/**\r
+ * @brief Disables the timer (stops count)\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @return Nothing\r
+ * Disables the timer to stop counting.\r
+ */\r
+STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)\r
+{\r
+ IP_TIMER_Disable(pTMR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current timer count\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @return Current timer terminal count value\r
+ * Returns the current timer terminal count.\r
+ */\r
+STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)\r
+{\r
+ return IP_TIMER_ReadCount(pTMR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current prescale count\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @return Current timer prescale count value\r
+ * Returns the current prescale count.\r
+ */\r
+STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)\r
+{\r
+ return IP_TIMER_ReadPrescale(pTMR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the prescaler value\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param prescale : Prescale value to set the prescale register to\r
+ * @return Nothing\r
+ * Sets the prescale count value.\r
+ */\r
+STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)\r
+{\r
+ IP_TIMER_PrescaleSet(pTMR, prescale);\r
+}\r
+\r
+/**\r
+ * @brief Sets a timer match value\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param matchnum : Match timer to set match count for\r
+ * @param matchval : Match value for the selected match count\r
+ * @return Nothing\r
+ * Sets ones of the timer match values.\r
+ */\r
+STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)\r
+{\r
+ IP_TIMER_SetMatch(pTMR, matchnum, matchval);\r
+}\r
+\r
+/**\r
+ * @brief Reads a capture register\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capnum : Capture register to read\r
+ * @return The selected capture register value\r
+ * Returns the selected capture register value.\r
+ */\r
+STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)\r
+{\r
+ return IP_TIMER_ReadCapture(pTMR, capnum);\r
+}\r
+\r
+/**\r
+ * @brief Resets the timer terminal and prescale counts to 0\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)\r
+{\r
+ IP_TIMER_Reset(pTMR);\r
+}\r
+\r
+/**\r
+ * @brief Enables a match interrupt that fires when the terminal count\r
+ * matches the match counter value.\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)\r
+{\r
+ IP_TIMER_MatchEnableInt(pTMR, matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Disables a match interrupt for a match counter.\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)\r
+{\r
+ IP_TIMER_MatchDisableInt(pTMR, matchnum);\r
+}\r
+\r
+/**\r
+ * @brief For the specific match counter, enables reset of the terminal count register when a match occurs\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)\r
+{\r
+ IP_TIMER_ResetOnMatchEnable(pTMR, matchnum);\r
+}\r
+\r
+/**\r
+ * @brief For the specific match counter, disables reset of the terminal count register when a match occurs\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)\r
+{\r
+ IP_TIMER_ResetOnMatchDisable(pTMR, matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Enable a match timer to stop the terminal count when a\r
+ * match count equals the terminal count.\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)\r
+{\r
+ IP_TIMER_StopOnMatchEnable(pTMR, matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Disable stop on match for a match timer. Disables a match timer\r
+ * to stop the terminal count when a match count equals the terminal count.\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)\r
+{\r
+ IP_TIMER_StopOnMatchDisable(pTMR, matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Enables capture on on rising edge of selected CAP signal for the\r
+ * selected capture register, enables the selected CAPn.capnum signal to load\r
+ * the capture register with the terminal coount on a rising edge.\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)\r
+{\r
+ IP_TIMER_CaptureRisingEdgeEnable(pTMR, capnum);\r
+}\r
+\r
+/**\r
+ * @brief Disables capture on on rising edge of selected CAP signal. For the\r
+ * selected capture register, disables the selected CAPn.capnum signal to load\r
+ * the capture register with the terminal coount on a rising edge.\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)\r
+{\r
+ IP_TIMER_CaptureRisingEdgeDisable(pTMR, capnum);\r
+}\r
+\r
+/**\r
+ * @brief Enables capture on on falling edge of selected CAP signal. For the\r
+ * selected capture register, enables the selected CAPn.capnum signal to load\r
+ * the capture register with the terminal coount on a falling edge.\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)\r
+{\r
+ IP_TIMER_CaptureFallingEdgeEnable(pTMR, capnum);\r
+}\r
+\r
+/**\r
+ * @brief Disables capture on on falling edge of selected CAP signal. For the\r
+ * selected capture register, disables the selected CAPn.capnum signal to load\r
+ * the capture register with the terminal coount on a falling edge.\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)\r
+{\r
+ IP_TIMER_CaptureFallingEdgeDisable(pTMR, capnum);\r
+}\r
+\r
+/**\r
+ * @brief Enables interrupt on capture of selected CAP signal. For the\r
+ * selected capture register, an interrupt will be generated when the enabled\r
+ * rising or falling edge on CAPn.capnum is detected.\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)\r
+{\r
+ IP_TIMER_CaptureEnableInt(pTMR, capnum);\r
+}\r
+\r
+/**\r
+ * @brief Disables interrupt on capture of selected CAP signal\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)\r
+{\r
+ IP_TIMER_CaptureDisableInt(pTMR, capnum);\r
+}\r
+\r
+/**\r
+ * @brief Sets external match control (MATn.matchnum) pin control\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param initial_state : Initial state of the pin, high(1) or low(0)\r
+ * @param matchState : Selects the match state for the pin\r
+ * @param matchnum : MATn.matchnum signal to use\r
+ * @return Nothing\r
+ * For the pin selected with matchnum, sets the function of the pin that occurs on\r
+ * a terminal count match for the match count.\r
+ */\r
+STATIC INLINE void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,\r
+ IP_TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum)\r
+{\r
+ IP_TIMER_ExtMatchControlSet(pTMR, initial_state, matchState, matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Sets timer count source and edge with the selected passed from CapSrc\r
+ * @param pTMR : Pointer to timer IP register address\r
+ * @param capSrc : timer clock source and edge\r
+ * @param capnum : CAPn.capnum pin to use (if used)\r
+ * @return Nothing\r
+ * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.\r
+ */\r
+STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,\r
+ IP_TIMER_CAP_SRC_STATE_T capSrc,\r
+ int8_t capnum)\r
+{\r
+ IP_TIMER_SetCountClockSrc(pTMR, capSrc, capnum);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __TIMER_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx UART chip driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __UART_18XX_43XX_H_\r
+#define __UART_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup 18XX_43XX CHIP: LPC18xx/43xx UART Driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure data width, parity mode and stop bits\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param Databits : UART Data width, should be:\r
+ * UART_DATABIT_5: UART 5 bit data mode\r
+ * UART_DATABIT_6: UART 6 bit data mode\r
+ * UART_DATABIT_7: UART 7 bit data mode\r
+ * UART_DATABIT_8: UART 8 bit data mode\r
+ * @param Parity : UART Parity mode, should be:\r
+ * UART_PARITY_NONE: No parity\r
+ * UART_PARITY_ODD: Odd parity\r
+ * UART_PARITY_EVEN: Even parity\r
+ * UART_PARITY_SP_1: Forced "1" stick parity\r
+ * UART_PARITY_SP_0: Forced "0" stick parity\r
+ * @param Stopbits : Number of stop bits, should be:\r
+ * UART_STOPBIT_1: One Stop Bit Select\r
+ * UART_STOPBIT_2: Two Stop Bits Select\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART,\r
+ IP_UART_DATABIT_T Databits,\r
+ IP_UART_PARITY_T Parity,\r
+ IP_UART_STOPBIT_T Stopbits)\r
+{\r
+ IP_UART_ConfigData(pUART, Databits, Parity, Stopbits);\r
+}\r
+\r
+/**\r
+ * @brief Send a block of data via UART peripheral\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param txbuf : Pointer to Transmit buffer\r
+ * @param buflen : Length of Transmit buffer\r
+ * @param flag : Flag used in UART transfer, should be NONE_BLOCKING or BLOCKING\r
+ * @return Number of bytes sent\r
+ */\r
+STATIC INLINE uint32_t Chip_UART_Send(LPC_USART_T *pUART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_T flag)\r
+{\r
+ return IP_UART_Send(pUART, txbuf, buflen, flag);\r
+}\r
+\r
+/**\r
+ * @brief Receive a block of data via UART peripheral\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param rxbuf : Pointer to Received buffer\r
+ * @param buflen : Length of Received buffer\r
+ * @param flag : Flag mode, should be NONE_BLOCKING or BLOCKING\r
+ * @return Number of bytes received\r
+ */\r
+STATIC INLINE uint32_t Chip_UART_Receive(LPC_USART_T *pUART,\r
+ uint8_t *rxbuf,\r
+ uint32_t buflen,\r
+ TRANSFER_BLOCK_T flag)\r
+{\r
+ return IP_UART_Receive(pUART, rxbuf, buflen, flag);\r
+}\r
+\r
+/* UART FIFO functions ----------------------------------------------------------*/\r
+/**\r
+ * @brief Configure FIFO function on selected UART peripheral\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param FIFOCfg : Pointer to a UART_FIFO_CFG_T Structure that contains specified information about FIFO configuration\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_UART_FIFOConfig(LPC_USART_T *pUART, UART_FIFO_CFG_T *FIFOCfg)\r
+{\r
+ IP_UART_FIFOConfig(pUART, FIFOCfg);\r
+}\r
+\r
+/**\r
+ * @brief Fills each UART_FIFOInitStruct member with its default value:\r
+ * - FIFO_DMAMode = DISABLE\r
+ * - FIFO_Level = UART_FIFO_TRGLEV0\r
+ * - FIFO_ResetRxBuf = ENABLE\r
+ * - FIFO_ResetTxBuf = ENABLE\r
+ * - FIFO_State = ENABLE\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param UART_FIFOInitStruct : Pointer to a UART_FIFO_CFG_T structure which will be initialized.\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_UART_FIFOConfigStructInit(LPC_USART_T *pUART, UART_FIFO_CFG_T *UART_FIFOInitStruct)\r
+{\r
+ IP_UART_FIFOConfigStructInit(UART_FIFOInitStruct);\r
+}\r
+\r
+/* UART operate functions -------------------------------------------------------*/\r
+/**\r
+ * @brief Enable or disable specified UART interrupt.\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param UARTIntCfg : Specifies the interrupt flag, should be one of the following:\r
+ * - UART_INTCFG_RBR : RBR Interrupt enable\r
+ * - UART_INTCFG_THRE : THR Interrupt enable\r
+ * - UART_INTCFG_RLS : RX line status interrupt enable\r
+ * - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only)\r
+ * - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only)\r
+ * - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt\r
+ * - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt\r
+ * @param NewState : New state of specified UART interrupt type, should be ENALBE or DISALBE\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_UART_IntConfig(LPC_USART_T *pUART, IP_UART_INT_T UARTIntCfg, FunctionalState NewState)\r
+{\r
+ IP_UART_IntConfig(pUART, UARTIntCfg, NewState);\r
+}\r
+\r
+/**\r
+ * @brief Get Source Interrupt\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @return Return the value of IIR register\r
+ */\r
+STATIC INLINE uint32_t Chip_UART_IntGetStatus(LPC_USART_T *pUART)\r
+{\r
+ return IP_UART_IntGetStatus(pUART);\r
+}\r
+\r
+/**\r
+ * @brief Get current value of Line Status register in UART peripheral.\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @return Current value of Line Status register in UART peripheral\r
+ */\r
+STATIC INLINE uint8_t Chip_UART_GetLineStatus(LPC_USART_T *pUART)\r
+{\r
+ return IP_UART_GetLineStatus(pUART);\r
+}\r
+\r
+/**\r
+ * @brief Check whether if UART is busy or not\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @return RESET if UART is not busy, otherwise return SET.\r
+ */\r
+STATIC INLINE FlagStatus Chip_UART_CheckBusy(LPC_USART_T *pUART)\r
+{\r
+ return IP_UART_CheckBusy(pUART);\r
+}\r
+\r
+/**\r
+ * @brief Force BREAK character on UART line, output pin pUART TXD is forced to logic 0\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_UART_ForceBreak(LPC_USART_T *pUART)\r
+{\r
+ IP_UART_ForceBreak(pUART);\r
+}\r
+\r
+/**\r
+ * @brief Transmit a single data through UART peripheral\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param data : Data to transmit (must be 8-bit long)\r
+ * @return Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty)\r
+ */\r
+STATIC INLINE Status Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data)\r
+{\r
+ return IP_UART_SendByte(pUART, data);\r
+}\r
+\r
+/**\r
+ * @brief Receive a single data from UART peripheral\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param *Data : Pointer to Data to receive (must be 8-bit long)\r
+ * @return Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet)\r
+ */\r
+STATIC INLINE Status Chip_UART_ReceiveByte(LPC_USART_T *pUART, uint8_t *Data)\r
+{\r
+ return IP_UART_ReceiveByte(pUART, Data);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the pUART peripheral.\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @return Nothing\r
+ */\r
+void Chip_UART_Init(LPC_USART_T *pUART);\r
+\r
+/**\r
+ * @brief De-initializes the pUART peripheral.\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @return Nothing\r
+ */\r
+void Chip_UART_DeInit(LPC_USART_T *pUART);\r
+\r
+/**\r
+ * @brief Determines best dividers to get a target baud rate\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param baudrate : Desired UART baud rate.\r
+ * @return Error status, could be SUCCESS or ERROR\r
+ */\r
+Status Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate);\r
+\r
+/**\r
+ * @brief Enable/Disable transmission on UART TxD pin\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param NewState : New State of Tx transmission function, should be ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+void Chip_UART_TxCmd(LPC_USART_T *pUART, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Get Interrupt Stream Status\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @return Return the interrupt status, should be:\r
+ * - UART_INTSTS_ERROR\r
+ * - UART_INTSTS_RTR\r
+ * - UART_INTSTS_RTS\r
+ */\r
+IP_UART_INT_STATUS_T Chip_UART_GetIntStatus(LPC_USART_T *pUART);\r
+\r
+/**\r
+ * @brief Uart interrupt service routine (chip layer)\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @return Nothing\r
+ */\r
+void Chip_UART_Interrupt_Handler (LPC_USART_T *pUART);\r
+\r
+/**\r
+ * @brief UART transmit function for interrupt mode (using ring buffers)\r
+ * @param pUART : Selected UART peripheral used to send data, should be UART0\r
+ * @param txbuf : Pointer to Transmit buffer\r
+ * @param buflen : Length of Transmit buffer\r
+ * @return Number of bytes actually sent to the ring buffer\r
+ */\r
+uint32_t Chip_UART_Interrupt_Transmit(LPC_USART_T *pUART, uint8_t *txbuf, uint8_t buflen);\r
+\r
+/**\r
+ * @brief UART read function for interrupt mode (using ring buffers)\r
+ * @param pUART : Selected UART peripheral used to send data, should be UART0\r
+ * @param rxbuf : Pointer to Received buffer\r
+ * @param buflen : Length of Received buffer\r
+ * @return Number of bytes actually read from the ring buffer\r
+ */\r
+uint32_t Chip_UART_Interrupt_Receive(LPC_USART_T *pUART, uint8_t *rxbuf, uint8_t buflen);\r
+\r
+/**\r
+ * @brief Reset Tx and Rx ring buffer (head and tail)\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Nothing\r
+ */\r
+void Chip_UART_InitRingBuffer(LPC_USART_T *pUART);\r
+\r
+/**\r
+ * @brief Start/Stop Auto Baudrate activity\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param ABConfigStruct : A pointer to UART_AB_CFG_T structure that\r
+ * contains specified information about UAR auto baud configuration\r
+ * @param NewState : New State of Auto baudrate activity, should be ENABLE or DISABLE\r
+ * @return Nothing\r
+ * @note Auto-baudrate mode enable bit will be cleared once this mode completed.\r
+ */\r
+STATIC INLINE void Chip_UART_ABCmd(LPC_USART_T *pUART, UART_AB_CFG_T *ABConfigStruct, FunctionalState NewState)\r
+{\r
+ IP_UART_ABCmd(pUART, ABConfigStruct, NewState);\r
+}\r
+\r
+/**\r
+ * @brief Clear Autobaud Interrupt\r
+ * @param pUART : Pointer to selected pUART peripheral\r
+ * @param ABIntType : type of auto-baud interrupt, should be:\r
+ * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt\r
+ * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void Chip_UART_ABClearIntPending(LPC_USART_T *pUART, IP_UART_INT_STATUS_T ABIntType)\r
+{\r
+ IP_UART_ABClearIntPending(pUART, ABIntType);\r
+}\r
+\r
+// FIXME - this function is probably not interrupt related and needs a DoxyGen header\r
+/* UART interrupt service routine */\r
+FlagStatus Chip_UART_GetABEOStatus(LPC_USART_T *pUART);\r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* __UART_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief LPC18xx/43xx WWDT chip driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __WWDT_18XX_43XX_H_\r
+#define __WWDT_18XX_43XX_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup WWDT_18XX_43XX CHIP: LPC18xx/43xx WWDT driver\r
+ * @ingroup CHIP_18XX_43XX_Drivers\r
+ * @{\r
+ */\r
+\r
+/** WDT oscillator frequency value */\r
+#define WDT_OSC (CGU_IRC_FREQ)\r
+\r
+/** Minimum tick count for timer value and window value */\r
+#define WWDT_TICKS_MIN 0xFF\r
+\r
+/** Maximum tick count for timer value and window value */\r
+#define WWDT_TICKS_MAX 0xFFFFFF\r
+\r
+/**\r
+ * @brief Initialize the Watchdog timer\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @return None\r
+ */\r
+void Chip_WWDT_Init(LPC_WWDT_T *pWWDT);\r
+\r
+/**\r
+ * @brief Shutdown the Watchdog timer\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT)\r
+{\r
+ IP_WWDT_DeInit(pWWDT);\r
+}\r
+\r
+/**\r
+ * @brief Set WDT timeout constant value used for feed\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX\r
+ * @return none\r
+ */\r
+STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout)\r
+{\r
+ IP_WWDT_SetTimeOut(pWWDT, timeout);\r
+}\r
+\r
+/**\r
+ * @brief Feed watchdog timer\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @return None\r
+ * @note If this function isn't called, a watchdog timer warning will occur.\r
+ * After the warning, a timeout will occur if a feed has happened.\r
+ */\r
+STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT)\r
+{\r
+ IP_WWDT_Feed(pWWDT);\r
+}\r
+\r
+/**\r
+ * @brief Set WWDT warning interrupt\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @param timeout : WDT warning in ticks, between 0 and 1023\r
+ * @return None\r
+ * @note This is the number of ticks after the watchdog interrupt that the\r
+ * warning interrupt will be generated.\r
+ */\r
+STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout)\r
+{\r
+ IP_WWDT_SetWarning(pWWDT, timeout);\r
+}\r
+\r
+/**\r
+ * @brief Set WWDT window time\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @param timeout : WDT window in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX\r
+ * @return none\r
+ * @note The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()\r
+ * function and this function, with this function defining the last tick before the\r
+ * watchdog window interrupt occurs.\r
+ */\r
+STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout)\r
+{\r
+ IP_WWDT_SetWindow(pWWDT, timeout);\r
+}\r
+\r
+/**\r
+ * @brief Enable watchdog timer options\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @param options : An or'ed set of options of values\r
+ * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT\r
+ * @return None\r
+ * @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |\r
+ * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options\r
+ * are set (or unset) with no other options.\r
+ */\r
+STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options)\r
+{\r
+ IP_WWDT_SetOption(pWWDT, options);\r
+}\r
+\r
+/**\r
+ * @brief Disable/clear watchdog timer options\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @param options : An or'ed set of options of values\r
+ * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT\r
+ * @return None\r
+ * @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |\r
+ * WWDT_WDMOD_WDTOF).\r
+ */\r
+STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options)\r
+{\r
+ IP_WWDT_UnsetOption(pWWDT, options);\r
+}\r
+\r
+/**\r
+ * @brief Enable WWDT activity\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT)\r
+{\r
+ IP_WWDT_Start(pWWDT);\r
+}\r
+\r
+/**\r
+ * @brief Read WWDT status flag\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @return Watchdog status, an Or'ed value of WWDT_WDMOD_*\r
+ */\r
+STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT)\r
+{\r
+ return IP_WWDT_GetStatus(pWWDT);\r
+}\r
+\r
+/**\r
+ * @brief Clear WWDT interrupt status flags\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @param status : Or'ed value of status flag(s) that you want to clear, should be:\r
+ * - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag\r
+ * - WWDT_WDMOD_WDINT: Clear watchdog warning flag\r
+ * @return None\r
+ */\r
+STATIC INLINE void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status)\r
+{\r
+ IP_WWDT_ClearStatusFlag(pWWDT, status);\r
+}\r
+\r
+/**\r
+ * @brief Get the current value of WDT\r
+ * @param pWWDT : The base of WatchDog Timer peripheral on the chip\r
+ * @return current value of WDT\r
+ */\r
+STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT)\r
+{\r
+ return IP_WWDT_GetCurrentCount(pWWDT);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __WWDT_18XX_43XX_H_ */\r
--- /dev/null
+/*\r
+ * @brief Common definitions used in SD/MMC cards\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __LPC_SDMMC_H\r
+#define __LPC_SDMMC_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup CHIP_SDMMC_Definitions CHIP: Common SD/MMC definitions\r
+ * @ingroup CHIP_Common\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief OCR Register definitions\r
+ */\r
+/** Support voltage range 2.0-2.1 (this bit is reserved in SDC)*/\r
+#define SDC_OCR_20_21 (((uint32_t) 1) << 8)\r
+/** Support voltage range 2.1-2.2 (this bit is reserved in SDC)*/\r
+#define SDC_OCR_21_22 (((uint32_t) 1) << 9)\r
+/** Support voltage range 2.2-2.3 (this bit is reserved in SDC)*/\r
+#define SDC_OCR_22_23 (((uint32_t) 1) << 10)\r
+/** Support voltage range 2.3-2.4 (this bit is reserved in SDC)*/\r
+#define SDC_OCR_23_24 (((uint32_t) 1) << 11)\r
+/** Support voltage range 2.4-2.5 (this bit is reserved in SDC)*/\r
+#define SDC_OCR_24_25 (((uint32_t) 1) << 12)\r
+/** Support voltage range 2.5-2.6 (this bit is reserved in SDC)*/\r
+#define SDC_OCR_25_26 (((uint32_t) 1) << 13)\r
+/** Support voltage range 2.6-2.7 (this bit is reserved in SDC)*/\r
+#define SDC_OCR_26_27 (((uint32_t) 1) << 14)\r
+/** Support voltage range 2.7-2.8 */\r
+#define SDC_OCR_27_28 (((uint32_t) 1) << 15)\r
+/** Support voltage range 2.8-2.9*/\r
+#define SDC_OCR_28_29 (((uint32_t) 1) << 16)\r
+/** Support voltage range 2.9-3.0 */\r
+#define SDC_OCR_29_30 (((uint32_t) 1) << 17)\r
+/** Support voltage range 3.0-3.1 */\r
+#define SDC_OCR_30_31 (((uint32_t) 1) << 18)\r
+/** Support voltage range 3.1-3.2 */\r
+#define SDC_OCR_31_32 (((uint32_t) 1) << 19)\r
+/** Support voltage range 3.2-3.3 */\r
+#define SDC_OCR_32_33 (((uint32_t) 1) << 20)\r
+/** Support voltage range 3.3-3.4 */\r
+#define SDC_OCR_33_34 (((uint32_t) 1) << 21)\r
+/** Support voltage range 3.4-3.5 */\r
+#define SDC_OCR_34_35 (((uint32_t) 1) << 22)\r
+/** Support voltage range 3.5-3.6 */\r
+#define SDC_OCR_35_36 (((uint32_t) 1) << 23)\r
+/** Support voltage range 2.7-3.6 */\r
+#define SDC_OCR_27_36 ((uint32_t) 0x00FF8000)\r
+/** Card Capacity Status (CCS). (this bit is reserved in MMC) */\r
+#define SDC_OCR_HC_CCS (((uint32_t) 1) << 30)\r
+/** Card power up status bit */\r
+#define SDC_OCR_IDLE (((uint32_t) 1) << 31)\r
+#define SDC_OCR_BUSY (((uint32_t) 0) << 31)\r
+\r
+/* SD/MMC commands - this matrix shows the command, response types, and\r
+ supported card type for that command.\r
+ Command Number Resp SD MMC\r
+ ----------------------- ------ ----- --- ---\r
+ Reset (go idle) CMD0 NA x x\r
+ Send op condition CMD1 R3 x\r
+ All send CID CMD2 R2 x x\r
+ Send relative address CMD3 R1 x\r
+ Send relative address CMD3 R6 x\r
+ Program DSR CMD4 NA x\r
+ Select/deselect card CMD7 R1b x\r
+ Select/deselect card CMD7 R1 x\r
+ Send CSD CMD9 R2 x x\r
+ Send CID CMD10 R2 x x\r
+ Read data until stop CMD11 R1 x x\r
+ Stop transmission CMD12 R1/b x x\r
+ Send status CMD13 R1 x x\r
+ Go inactive state CMD15 NA x x\r
+ Set block length CMD16 R1 x x\r
+ Read single block CMD17 R1 x x\r
+ Read multiple blocks CMD18 R1 x x\r
+ Write data until stop CMD20 R1 x\r
+ Setblock count CMD23 R1 x\r
+ Write single block CMD24 R1 x x\r
+ Write multiple blocks CMD25 R1 x x\r
+ Program CID CMD26 R1 x\r
+ Program CSD CMD27 R1 x x\r
+ Set write protection CMD28 R1b x x\r
+ Clear write protection CMD29 R1b x x\r
+ Send write protection CMD30 R1 x x\r
+ Erase block start CMD32 R1 x\r
+ Erase block end CMD33 R1 x\r
+ Erase block start CMD35 R1 x\r
+ Erase block end CMD36 R1 x\r
+ Erase blocks CMD38 R1b x\r
+ Fast IO CMD39 R4 x\r
+ Go IRQ state CMD40 R5 x\r
+ Lock/unlock CMD42 R1b x\r
+ Application command CMD55 R1 x\r
+ General command CMD56 R1b x\r
+\r
+ *** SD card application commands - these must be preceded with ***\r
+ *** MMC CMD55 application specific command first ***\r
+ Set bus width ACMD6 R1 x\r
+ Send SD status ACMD13 R1 x\r
+ Send number WR blocks ACMD22 R1 x\r
+ Set WR block erase cnt ACMD23 R1 x\r
+ Send op condition ACMD41 R3 x\r
+ Set clear card detect ACMD42 R1 x\r
+ Send CSR ACMD51 R1 x */\r
+\r
+/**\r
+ * @brief SD/MMC application specific commands for SD cards only - these\r
+ * must be preceded by the SDMMC CMD55 to work correctly\r
+ */\r
+typedef enum {\r
+ SD_SET_BUS_WIDTH, /*!< Set the SD bus width */\r
+ SD_SEND_STATUS, /*!< Send the SD card status */\r
+ SD_SEND_WR_BLOCKS, /*!< Send the number of written clocks */\r
+ SD_SET_ERASE_COUNT, /*!< Set the number of blocks to pre-erase */\r
+ SD_SENDOP_COND, /*!< Send the OCR register (init) */\r
+ SD_CLEAR_CARD_DET, /*!< Set or clear the 50K detect pullup */\r
+ SD_SEND_SCR, /*!< Send the SD configuration register */\r
+ SD_INVALID_APP_CMD /*!< Invalid SD application command */\r
+} SD_APP_CMD_T;\r
+\r
+/**\r
+ * @brief Possible SDMMC response types\r
+ */\r
+typedef enum {\r
+ SDMMC_RESPONSE_R1, /*!< Typical status */\r
+ SDMMC_RESPONSE_R1B, /*!< Typical status with busy */\r
+ SDMMC_RESPONSE_R2, /*!< CID/CSD registers (CMD2 and CMD10) */\r
+ SDMMC_RESPONSE_R3, /*!< OCR register (CMD1, ACMD41) */\r
+ SDMMC_RESPONSE_R4, /*!< Fast IO response word */\r
+ SDMMC_RESPONSE_R5, /*!< Go IRQ state response word */\r
+ SDMMC_RESPONSE_R6, /*!< Published RCA response */\r
+ SDMMC_RESPONSE_NONE /*!< No response expected */\r
+} SDMMC_RESPONSE_T;\r
+\r
+/**\r
+ * @brief Possible SDMMC card state types\r
+ */\r
+typedef enum {\r
+ SDMMC_IDLE_ST = 0, /*!< Idle state */\r
+ SDMMC_READY_ST, /*!< Ready state */\r
+ SDMMC_IDENT_ST, /*!< Identification State */\r
+ SDMMC_STBY_ST, /*!< standby state */\r
+ SDMMC_TRAN_ST, /*!< transfer state */\r
+ SDMMC_DATA_ST, /*!< Sending-data State */\r
+ SDMMC_RCV_ST, /*!< Receive-data State */\r
+ SDMMC_PRG_ST, /*!< Programming State */\r
+ SDMMC_DIS_ST /*!< Disconnect State */\r
+} SDMMC_STATE_T;\r
+\r
+/* Function prototype for event setup function */\r
+typedef void (*SDMMC_EVSETUP_FUNC_T)(void *);\r
+\r
+/* Function prototype for wait for event function */\r
+typedef uint32_t (*SDMMC_EVWAIT_FUNC_T)(void);\r
+\r
+/* Function prototype for milliSecond delay function */\r
+typedef void (*SDMMC_MSDELAY_FUNC_T)(uint32_t);\r
+\r
+/**\r
+ * @brief SD/MMC Card specific setup data structure\r
+ */\r
+typedef struct {\r
+ uint32_t response[4]; /*!< Most recent response */\r
+ uint32_t cid[4]; /*!< CID of acquired card */\r
+ uint32_t csd[4]; /*!< CSD of acquired card */\r
+ uint32_t ext_csd[512 / 4]; /*!< Ext CSD */\r
+ uint32_t card_type; /*!< Card Type */\r
+ uint16_t rca; /*!< Relative address assigned to card */\r
+ uint32_t speed; /*!< Speed */\r
+ uint32_t block_len; /*!< Card sector size */\r
+ uint32_t device_size; /*!< Device Size */\r
+ uint32_t blocknr; /*!< Block Number */\r
+ uint32_t clk_rate; /*! Clock rate */\r
+ SDMMC_EVSETUP_FUNC_T evsetup_cb; /*!< Function to setup event information */\r
+ SDMMC_EVWAIT_FUNC_T waitfunc_cb; /*!< Function to wait for event */\r
+ SDMMC_MSDELAY_FUNC_T msdelay_func; /*!< Function to sleep in ms */\r
+} SDMMC_CARD_T;\r
+\r
+/**\r
+ * @brief SD/MMC commands, arguments and responses\r
+ * Standard SD/MMC commands (3.1) type argument response\r
+ */\r
+/* class 1 */\r
+#define MMC_GO_IDLE_STATE 0 /* bc */\r
+#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */\r
+#define MMC_ALL_SEND_CID 2 /* bcr R2 */\r
+#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */\r
+#define MMC_SET_DSR 4 /* bc [31:16] RCA */\r
+#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */\r
+#define MMC_SEND_EXT_CSD 8 /* bc R1 */\r
+#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */\r
+#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */\r
+#define MMC_STOP_TRANSMISSION 12 /* ac R1b */\r
+#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */\r
+#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */\r
+\r
+/* class 2 */\r
+#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */\r
+#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */\r
+#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */\r
+\r
+/* class 3 */\r
+#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */\r
+\r
+/* class 4 */\r
+#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */\r
+#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */\r
+#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */\r
+#define MMC_PROGRAM_CID 26 /* adtc R1 */\r
+#define MMC_PROGRAM_CSD 27 /* adtc R1 */\r
+\r
+/* class 6 */\r
+#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */\r
+#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */\r
+#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */\r
+\r
+/* class 5 */\r
+#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */\r
+#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */\r
+#define MMC_ERASE 37 /* ac R1b */\r
+#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */\r
+#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */\r
+#define SD_ERASE 38 /* ac R1b */\r
+\r
+/* class 9 */\r
+#define MMC_FAST_IO 39 /* ac <Complex> R4 */\r
+#define MMC_GO_IRQ_STATE 40 /* bcr R5 */\r
+\r
+/* class 7 */\r
+#define MMC_LOCK_UNLOCK 42 /* adtc R1b */\r
+\r
+/* class 8 */\r
+#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */\r
+#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */\r
+\r
+/* SD commands type argument response */\r
+/* class 8 */\r
+/* This is basically the same command as for MMC with some quirks. */\r
+#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */\r
+#define SD_CMD8 8 /* bcr [31:0] OCR R3 */\r
+\r
+/* Application commands */\r
+#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */\r
+#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R1 (R4) */\r
+#define SD_APP_SEND_SCR 51 /* adtc R1 */\r
+\r
+/**\r
+ * @brief MMC status in R1<br>\r
+ * Type<br>\r
+ * e : error bit<br>\r
+ * s : status bit<br>\r
+ * r : detected and set for the actual command response<br>\r
+ * x : detected and set during command execution. the host must poll\r
+ * the card by sending status command in order to read these bits.\r
+ * Clear condition<br>\r
+ * a : according to the card state<br>\r
+ * b : always related to the previous command. Reception of\r
+ * a valid command will clear it (with a delay of one command)<br>\r
+ * c : clear by read<br>\r
+ */\r
+\r
+#define R1_OUT_OF_RANGE (1UL << 31) /* er, c */\r
+#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */\r
+#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */\r
+#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */\r
+#define R1_ERASE_PARAM (1 << 27) /* ex, c */\r
+#define R1_WP_VIOLATION (1 << 26) /* erx, c */\r
+#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */\r
+#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */\r
+#define R1_COM_CRC_ERROR (1 << 23) /* er, b */\r
+#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */\r
+#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */\r
+#define R1_CC_ERROR (1 << 20) /* erx, c */\r
+#define R1_ERROR (1 << 19) /* erx, c */\r
+#define R1_UNDERRUN (1 << 18) /* ex, c */\r
+#define R1_OVERRUN (1 << 17) /* ex, c */\r
+#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */\r
+#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */\r
+#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */\r
+#define R1_ERASE_RESET (1 << 13) /* sr, c */\r
+#define R1_STATUS(x) (x & 0xFFFFE000)\r
+#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */\r
+#define R1_READY_FOR_DATA (1 << 8) /* sx, a */\r
+#define R1_APP_CMD (1 << 5) /* sr, c */\r
+\r
+/**\r
+ * @brief SD/MMC card OCR register bits\r
+ */\r
+#define OCR_ALL_READY (1UL << 31) /* Card Power up status bit */\r
+#define OCR_HC_CCS (1 << 30) /* High capacity card */\r
+#define OCR_VOLTAGE_RANGE_MSK (0x00FF8000)\r
+\r
+#define SD_SEND_IF_ARG 0x000001AA\r
+#define SD_SEND_IF_ECHO_MSK 0x000000FF\r
+#define SD_SEND_IF_RESP 0x000000AA\r
+\r
+/**\r
+ * @brief R3 response definitions\r
+ */\r
+#define CMDRESP_R3_OCR_VAL(n) (((uint32_t) n) & 0xFFFFFF)\r
+#define CMDRESP_R3_S18A (((uint32_t) 1 ) << 24)\r
+#define CMDRESP_R3_HC_CCS (((uint32_t) 1 ) << 30)\r
+#define CMDRESP_R3_INIT_COMPLETE (((uint32_t) 1 ) << 31)\r
+\r
+/**\r
+ * @brief R6 response definitions\r
+ */\r
+#define CMDRESP_R6_RCA_VAL(n) (((uint32_t) (n >> 16)) & 0xFFFF)\r
+#define CMDRESP_R6_CARD_STATUS(n) (((uint32_t) (n & 0x1FFF)) | \\r
+ ((n & (1 << 13)) ? (1 << 19) : 0) | \\r
+ ((n & (1 << 14)) ? (1 << 22) : 0) | \\r
+ ((n & (1 << 15)) ? (1 << 23) : 0))\r
+\r
+/**\r
+ * @brief R7 response definitions\r
+ */\r
+/** Echo-back of check-pattern */\r
+#define CMDRESP_R7_CHECK_PATTERN(n) (((uint32_t) n ) & 0xFF)\r
+/** Voltage accepted */\r
+#define CMDRESP_R7_VOLTAGE_ACCEPTED (((uint32_t) 1 ) << 8)\r
+\r
+/**\r
+ * @brief CMD3 command definitions\r
+ */\r
+/** Card Address */\r
+#define CMD3_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)\r
+\r
+/**\r
+ * @brief CMD7 command definitions\r
+ */\r
+/** Card Address */\r
+#define CMD7_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)\r
+\r
+/**\r
+ * @brief CMD8 command definitions\r
+ */\r
+/** Check pattern */\r
+#define CMD8_CHECKPATTERN(n) (((uint32_t) (n & 0xFF) ) << 0)\r
+/** Recommended pattern */\r
+#define CMD8_DEF_PATTERN (0xAA)\r
+/** Voltage supplied.*/\r
+#define CMD8_VOLTAGESUPPLIED_27_36 (((uint32_t) 1 ) << 8)\r
+\r
+/**\r
+ * @brief CMD9 command definitions\r
+ */\r
+#define CMD9_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)\r
+\r
+/**\r
+ * @brief CMD13 command definitions\r
+ */\r
+#define CMD13_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)\r
+\r
+/**\r
+ * @brief APP_CMD command definitions\r
+ */\r
+#define CMD55_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)\r
+\r
+/**\r
+ * @brief ACMD41 command definitions\r
+ */\r
+#define ACMD41_OCR(n) (((uint32_t) n) & 0xFFFFFF)\r
+#define ACMD41_S18R (((uint32_t) 1 ) << 24)\r
+#define ACMD41_XPC (((uint32_t) 1 ) << 28)\r
+#define ACMD41_HCS (((uint32_t) 1 ) << 30)\r
+\r
+/**\r
+ * @brief ACMD6 command definitions\r
+ */\r
+#define ACMD6_BUS_WIDTH(n) ((uint32_t) n & 0x03)\r
+#define ACMD6_BUS_WIDTH_1 (0)\r
+#define ACMD6_BUS_WIDTH_4 (2)\r
+\r
+/** @brief Card type defines\r
+ */\r
+#define CARD_TYPE_SD (1 << 0)\r
+#define CARD_TYPE_4BIT (1 << 1)\r
+#define CARD_TYPE_8BIT (1 << 2)\r
+#define CARD_TYPE_HC (OCR_HC_CCS)/*!< high capacity card > 2GB */\r
+\r
+/**\r
+ * @brief SD/MMC sector size in bytes\r
+ */\r
+#define MMC_SECTOR_SIZE 512\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __LPC_SDMMC_H */\r
--- /dev/null
+/*\r
+ * @brief Analog comparator driver\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licenser disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __ACMP_001_H_\r
+#define __ACMP_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_ACMP_001 IP: Analog comparator driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Analog Comparator register block structure\r
+ */\r
+typedef struct { /*!< ACMP Structure */\r
+ __IO uint32_t CTRL; /*!< Comparator control register */\r
+ __IO uint32_t LAD; /*!< Voltage ladder register */\r
+} ACMP_001_T;\r
+\r
+#define ACMP_COMPSA_BIT (1 << 6) /* Comparator output control bit */\r
+#define ACMP_COMPSTAT_BIT (1 << 21) /* Comparator status, reflects the state of the comparator output */\r
+#define ACMP_COMPEDGE_BIT (1 << 23) /* Comparator edge-detect status */\r
+#define ACMP_LADENAB_BIT (1 << 0) /* Voltage ladder enable bit */\r
+\r
+/** Edge selection for comparator */\r
+typedef enum IP_ACMP_001_EDGESEL {\r
+ ACMP_EDGESEL_FALLING = (0 << 3), /* Set the COMPEDGE bit on falling edge */\r
+ ACMP_EDGESEL_RISING = (1 << 3), /* Set the COMPEDGE bit on rising edge */\r
+ ACMP_EDGESEL_BOTH = (2 << 3) /* Set the COMPEDGE bit on falling and rising edges */\r
+} IP_ACMP_001_EDGESEL_T;\r
+\r
+/** Hysteresis selection for comparator */\r
+typedef enum IP_ACMP_HYS_001 {\r
+ ACMP_HYS_NONE = (0 << 25), /* No hysteresis (the output will switch as the voltages cross) */\r
+ ACMP_HYS_5MV = (1 << 25), /* 5mV hysteresis */\r
+ ACMP_HYS_10MV = (2 << 25), /* 10mV hysteresis */\r
+ ACMP_HYS_20MV = (3 << 25) /* 20mV hysteresis */\r
+} IP_ACMP_HYS_001_T;\r
+\r
+/**\r
+ * @brief Initializes the ACMP\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ACMP_Init(ACMP_001_T *pACMP) {}\r
+\r
+/**\r
+ * @brief De-initializes the ACMP\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ACMP_Deinit(ACMP_001_T *pACMP) {}\r
+\r
+/**\r
+ * @brief Returns the current comparator status\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @return Status is an Or'ed value of ACMP_COMPSTAT_BIT or ACMP_COMPEDGE_BIT\r
+ */\r
+STATIC INLINE uint32_t IP_ACMP_GetCompStatus(ACMP_001_T *pACMP)\r
+{\r
+ return pACMP->CTRL & (ACMP_COMPSTAT_BIT | ACMP_COMPEDGE_BIT);\r
+}\r
+\r
+/**\r
+ * @brief Clears the ACMP interrupt (EDGECLR bit)\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @return Nothing\r
+ */\r
+void IP_ACMP_EdgeClear(ACMP_001_T *pACMP);\r
+\r
+/**\r
+ * @brief Sets up ACMP edge selection\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @param edgeSel : Edge selection value\r
+ * @return Nothing\r
+ */\r
+void IP_ACMP_SetEdgeSelection(ACMP_001_T *pACMP, IP_ACMP_001_EDGESEL_T edgeSel);\r
+\r
+/**\r
+ * @brief Synchronizes Comparator output to bus clock\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ACMP_EnableSyncCompOut(ACMP_001_T *pACMP)\r
+{\r
+ pACMP->CTRL |= ACMP_COMPSA_BIT;\r
+}\r
+\r
+/**\r
+ * @brief Sets comparator output to be used directly (no sync)\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ACMP_DisableSyncCompOut(ACMP_001_T *pACMP)\r
+{\r
+ pACMP->CTRL &= ~ACMP_COMPSA_BIT;\r
+}\r
+\r
+/**\r
+ * @brief Selects positive voltage input\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @param Posinput : one of the positive input voltage sources\r
+ * @return Nothing\r
+ * @note The caller must pre-shift the Posinput value to the\r
+ * correct bitfield location in the CTRL register.\r
+ */\r
+void IP_ACMP_SetPosVoltRef(ACMP_001_T *pACMP, uint32_t Posinput);\r
+\r
+/**\r
+ * @brief Selects negative voltage input\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @param Neginput : one of the negative input voltage sources\r
+ * @return Nothing\r
+ * @note The caller must pre-shift the Neginput value to the\r
+ * correct bitfield location in the CTRL register.\r
+ */\r
+void IP_ACMP_SetNegVoltRef(ACMP_001_T *pACMP, uint32_t Neginput);\r
+\r
+/**\r
+ * @brief Selects hysteresis level\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @param hys : Selected Hysteresis level\r
+ * @return Nothing\r
+ */\r
+void IP_ACMP_SetHysteresis(ACMP_001_T *pACMP, IP_ACMP_HYS_001_T hys);\r
+\r
+/**\r
+ * @brief Helper function for setting up ACMP control\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @param edgeSel : Edge selection value\r
+ * @param Posinput : one of the positive input voltage sources\r
+ * @param Neginput : one of the negative input voltage sources\r
+ * @param hys : Selected Hysteresis level\r
+ * @return Nothing\r
+ * @note The caller must pre-shift the Posinput and Neginput values to the\r
+ * correct bitfield location in the CTRL register.\r
+ */\r
+void IP_ACMP_SetupAMCPRefs(ACMP_001_T *pACMP, IP_ACMP_001_EDGESEL_T edgeSel,\r
+ uint32_t Posinput, uint32_t Neginput, IP_ACMP_HYS_001_T hys);\r
+\r
+/**\r
+ * @brief Sets up voltage ladder\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @param ladsel : Voltage ladder value\r
+ * @param ladrefVDDCMP : Selects the reference voltage Vref for the voltage ladder\r
+ * : false for VDD, true for VDDCMP pin\r
+ * @return Nothing\r
+ * @note The caller must pre-shift the ladsel value to the\r
+ * correct bitfield location in the LAD register.\r
+ */\r
+void IP_ACMP_SetupVoltLadder(ACMP_001_T *pACMP, uint32_t ladsel, bool ladrefVDDCMP);\r
+\r
+/**\r
+ * @brief Enables voltage ladder\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ACMP_EnableVoltLadder(ACMP_001_T *pACMP)\r
+{\r
+ pACMP->LAD |= ACMP_LADENAB_BIT;\r
+}\r
+\r
+/**\r
+ * @brief Disables voltage ladder\r
+ * @param pACMP : Pointer to Analog Comparator block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ACMP_DisableVoltLadder(ACMP_001_T *pACMP)\r
+{\r
+ pACMP->LAD &= ~ACMP_LADENAB_BIT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __ACMP_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief ADC Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __ADC_001_H_\r
+#define __ADC_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_ADC_001 IP: 10 or 12-bit ADC register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X) || defined(CHIP_LPC1347) || defined(CHIP_LPC175X_6X)\r
+#define ADC_ACC_12BITS\r
+#define ADC_TRIM_SUPPORT\r
+#else\r
+#define ADC_ACC_10BITS\r
+#endif\r
+\r
+/**\r
+ * @brief 10 or 12-bit ADC register block structure\r
+ */\r
+typedef struct { /*!< ADCn Structure */\r
+ __IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */\r
+ __I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */\r
+ __I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */\r
+ __I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */\r
+#if defined(ADC_TRIM_SUPPORT)\r
+ __IO uint32_t ADTRM;\r
+#endif\r
+} IP_ADC_001_T;\r
+\r
+/**\r
+ * @brief ADC register support bitfields and mask\r
+ */\r
+#if defined(ADC_ACC_12BITS)\r
+ #define ADC_DR_RESULT(n) ((((n) >> 4) & 0xFFF)) /*!< Mask for getting the 12 bits ADC data read value */\r
+#else\r
+ #define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the 10 bits ADC data read value */\r
+ #define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */\r
+#endif\r
+\r
+#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */\r
+#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */\r
+#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */\r
+#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */\r
+#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */\r
+#if defined(CHIP_LPC1347)\r
+#define ADC_CR_LPWRMODE ((1UL << 22)) /*!<Enable the low-power ADC mode */\r
+#define ADC_CR_MODE10BIT ((1UL << 23)) /*!<Enable the 10-bit conversion rate mode with high conversion rate. */\r
+#else\r
+#define ADC_CR_PDN ((1UL << 21)) /*!< ADC convert is operational */\r
+#endif\r
+#define ADC_CR_START_MASK ((7UL << 24)) /*!< ADC start mask bits */\r
+#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /*!< Select Start Mode */\r
+#define ADC_CR_START_NOW ((1UL << 24)) /*!< Start conversion now */\r
+#define ADC_CR_START_CTOUT15 ((2UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */\r
+#define ADC_CR_START_CTOUT8 ((3UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */\r
+#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */\r
+#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */\r
+#define ADC_CR_START_MCOA2 ((6UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */\r
+#define ADC_CR_EDGE ((1UL << 27)) /*!< Start conversion on a falling edge on the selected CAP/MAT signal */\r
+#if defined(CHIP_LPC1347)\r
+#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_LPWRMODE | ADC_CR_MODE10BIT)\r
+#elif defined(CHIP_LPC1343)\r
+#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))\r
+#elif defined(ADC_ACC_12BITS)\r
+#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_PDN)\r
+#else\r
+#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)\r
+#endif\r
+\r
+/**\r
+ * @brief ADC status register used for IP drivers\r
+ */\r
+typedef enum IP_ADC_STATUS {\r
+ ADC_DR_DONE_STAT, /*!< ADC data register staus */\r
+ ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */\r
+ ADC_DR_ADINT_STAT /*!< ADC interrupt status */\r
+} IP_ADC_STATUS_T;\r
+\r
+/**\r
+ * @brief Initialize for ADC\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param div : Clock divide value\r
+ * @param bitsAcc : Number of bits of accuracy of the conversion result\r
+ * @param flag : ADC mode flag.\r
+ * @return Nothing\r
+ * @note bitsAcc only make sense in 10-bit converter. And, it should be ADC_3BITS ->ADC_10BITS.\r
+ * ADC mode flag is or-ed bit values of the following flags:\r
+ * - ADC_CR_PDN: The A/D converter is operational. If this flag isn't set, the ADC is in \r
+ * power-down mode. This flag isn't available in LPC13xx.\r
+ * - ADC_CR_LPWRMODE: The analog circuitry is automatically powered-down when no conversions\r
+ * are taking place. This flag is only available in LPC1347.\r
+ * - ADC_CR_MODE10BIT: Enable the 10-bit conversion rate mode with high conversion rate. \r
+ * This flag is only available in LPC1347.\r
+ */\r
+void IP_ADC_Init(IP_ADC_001_T *pADC, uint8_t div, uint8_t bitsAcc, uint32_t flag);\r
+\r
+/**\r
+ * @brief Shutdown ADC\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @return Nothing\r
+ * @note Reset the ADC control and INTEN Register to reset values (disabled)\r
+ */\r
+void IP_ADC_DeInit(IP_ADC_001_T *pADC);\r
+\r
+/**\r
+ * @brief Set burst mode for ADC\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param NewState : ENABLE for burst mode, or DISABLE for normal mode\r
+ * @return Nothing\r
+ */\r
+void IP_ADC_SetBurstMode(IP_ADC_001_T *pADC, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Get the ADC value\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param channel : Channel to be read value, should be 0..7\r
+ * @param data : Data buffer to store the A/D value\r
+ * @return Status : SUCCESS or ERROR\r
+ */\r
+Status IP_ADC_Get_Val(IP_ADC_001_T *pADC, uint8_t channel, uint16_t *data);\r
+\r
+/**\r
+ * @brief Get ADC Channel status from ADC data register\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param channel : Channel number, should be 0..7\r
+ * @param StatusType : Register to read, ADC_DR_DONE_STAT, ADC_DR_OVERRUN_STAT, or ADC_DR_ADINT_STAT\r
+ * @return Channel status, SET or RESET\r
+ */\r
+FlagStatus IP_ADC_GetStatus(IP_ADC_001_T *pADC, uint8_t channel, uint32_t StatusType);\r
+\r
+/**\r
+ * @brief Set the edge start condition\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param edge_mode : 0 = rising, !0 = falling\r
+ * @return Nothing\r
+ */\r
+void IP_ADC_EdgeStartConfig(IP_ADC_001_T *pADC, uint8_t edge_mode);\r
+\r
+/**\r
+ * @brief Enable/Disable ADC channel number\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param channel : Channel number\r
+ * @param NewState : New state, ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+void IP_ADC_SetChannelNumber(IP_ADC_001_T *pADC, uint8_t channel, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Set start mode for ADC\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param start_mode : Start mode choose one of modes in 'ADC_START_*' enumeration type definitions\r
+ * @return Nothing\r
+ */\r
+void IP_ADC_SetStartMode(IP_ADC_001_T *pADC, uint8_t start_mode);\r
+\r
+/**\r
+ * @brief Enable/Disable interrupt for ADC channel\r
+ * @param pADC : The base of ADC peripheral on the chip\r
+ * @param channel : Channel assert the interrupt\r
+ * @param NewState : New state, ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+void IP_ADC_Int_Enable(IP_ADC_001_T *pADC, uint8_t channel, FunctionalState NewState);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __ADC_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Alarm Timer Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __ATIMER_001_H_\r
+#define __ATIMER_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_ATIMER_001 IP: ATimer register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Alarm timer\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Alarm Timer register block structure\r
+ */\r
+typedef struct { /*!< ATIMER Structure */\r
+ __IO uint32_t DOWNCOUNTER; /*!< Downcounter register */\r
+ __IO uint32_t PRESET; /*!< Preset value register */\r
+ __I uint32_t RESERVED0[1012];\r
+ __O uint32_t CLR_EN; /*!< Interrupt clear enable register */\r
+ __O uint32_t SET_EN; /*!< Interrupt set enable register */\r
+ __I uint32_t STATUS; /*!< Status register */\r
+ __I uint32_t ENABLE; /*!< Enable register */\r
+ __O uint32_t CLR_STAT; /*!< Clear register */\r
+ __O uint32_t SET_STAT; /*!< Set register */\r
+} IP_ATIMER_001_T;\r
+\r
+/**\r
+ * @brief Close ATIMER device\r
+ * @param pATimer : Pointer to timer device\r
+ * @return None\r
+ * @note Important: 32KHz clock must be enabled in CREG prior to this call. See\r
+ * the User Manual for more information.\r
+ */\r
+void IP_ATIMER_DeInit(IP_ATIMER_001_T *pATimer);\r
+\r
+/**\r
+ * @brief Clear ATIMER Interrupt Status\r
+ * @param pATimer : Pointer to timer device\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_ATIMER_ClearIntStatus(IP_ATIMER_001_T *pATimer)\r
+{\r
+ pATimer->CLR_STAT = 1;\r
+}\r
+\r
+/**\r
+ * @brief Set ATIMER Interrupt Status\r
+ * @param pATimer : Pointer to timer device\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_ATIMER_SetIntStatus(IP_ATIMER_001_T *pATimer)\r
+{\r
+ pATimer->SET_STAT = 1;\r
+}\r
+/**\r
+ * @brief Enable ATIMER Interrupt\r
+ * @param pATimer : Pointer to timer device\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_ATIMER_IntEnable(IP_ATIMER_001_T *pATimer)\r
+{\r
+ pATimer->SET_EN = 1;\r
+}\r
+\r
+/**\r
+ * @brief Disable ATIMER Interrupt\r
+ * @param pATimer : Pointer to timer device\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_ATIMER_IntDisable(IP_ATIMER_001_T *pATimer)\r
+{\r
+ pATimer->CLR_EN = 1;\r
+}\r
+\r
+/**\r
+ * @brief Update Preset value\r
+ * @param pATimer : Pointer to timer device\r
+ * @param PresetValue updated preset value\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ATIMER_UpdatePresetValue(IP_ATIMER_001_T *pATimer, uint32_t PresetValue)\r
+{\r
+ pATimer->PRESET = PresetValue;\r
+}\r
+\r
+/**\r
+ * @brief Read value of preset register\r
+ * @param pATimer : Pointer to timer/counter device\r
+ * @return Value of capture register\r
+ */\r
+STATIC INLINE uint32_t IP_ATIMER_GetPresetValue(IP_ATIMER_001_T *pATimer)\r
+{\r
+ return pATimer->PRESET;\r
+}\r
+\r
+/**\r
+ * @brief Returns enable state of ATimer interrupt\r
+ * @param pATimer : Pointer to timer/counter device\r
+ * @return !0 if the ATimer interrupt is enabled, otherwise 0\r
+ */\r
+STATIC INLINE uint32_t IP_ATIMER_GetIntEnableState(IP_ATIMER_001_T *pATimer)\r
+{\r
+ return pATimer->ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Returns current pending state of ATimer interrupt\r
+ * @param pATimer : Pointer to timer/counter device\r
+ * @return !0 if the ATimer interrupt is asserted, otherwise 0\r
+ */\r
+STATIC INLINE uint32_t IP_ATIMER_GetIntPendingState(IP_ATIMER_001_T *pATimer)\r
+{\r
+ return pATimer->STATUS;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __ATIMER_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief CAN registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CAN_001_H_\r
+#define __CAN_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_CAN_001 IP: CAN register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Controller Area Network\r
+ * @{\r
+ */\r
+\r
+/** The number of entry in AF RAM region */\r
+#define CANAF_RAM_ENTRY_NUM 512\r
+\r
+/**\r
+ * @brief CAN AF RAM section definitions\r
+ */\r
+typedef enum IP_CAN_AF_RAM_SECTION {\r
+ CANAF_RAM_FULLCAN_SEC, /*!<FullCAN Section*/\r
+ CANAF_RAM_SFF_SEC, /*!<Standard ID Section*/\r
+ CANAF_RAM_SFF_GRP_SEC, /*!<Group Standard ID Section*/\r
+ CANAF_RAM_EFF_SEC, /*!<Extended ID Section*/\r
+ CANAF_RAM_EFF_GRP_SEC, /*!<Group Extended ID Section*/\r
+ CANAF_RAM_SECTION_NUM,\r
+} IP_CAN_AF_RAM_SECTION_T;\r
+\r
+/**\r
+ * @brief CAN acceptance filter RAM register block structure\r
+ */\r
+typedef struct /*!< AF RAM Mask Table */\r
+{\r
+ __IO uint32_t MASK[CANAF_RAM_ENTRY_NUM]; /*!< Acceptance Filter RAM ID mask register */\r
+} IP_CAN_001_AF_RAM_T;\r
+\r
+/**\r
+ * @brief CAN acceptance filter register block structure\r
+ */\r
+typedef struct /*!< CAN AF structure */\r
+{\r
+ __IO uint32_t AFMR; /*!< Acceptance Filter Register */\r
+ __IO uint32_t ENDADDR[CANAF_RAM_SECTION_NUM]; /*!< Start/End Address Registers */\r
+ __I uint32_t LUTERRAD; /*!< LUT Error Address Register */\r
+ __I uint32_t LUTERR; /*!< LUT Error Register */\r
+ __IO uint32_t FCANIE; /*!< Global FullCANInterrupt Enable Register */\r
+ __IO uint32_t FCANIC[2]; /*!< FullCAN Interrupt and Capture Registers */\r
+} IP_CAN_001_AF_T;\r
+\r
+/**\r
+ * @brief Central CAN register block structure\r
+ */\r
+typedef struct /*!< Central CAN structure */\r
+{\r
+ __I uint32_t TXSR; /*!< CAN Central Transmit Status Register */\r
+ __I uint32_t RXSR; /*!< CAN Central Receive Status Register */\r
+ __I uint32_t MSR; /*!< CAN Central Miscellaneous Register */\r
+} IP_CAN_001_CR_T;\r
+\r
+/**\r
+ * @brief CAN Transmit register block structure\r
+ */\r
+typedef struct /*!< CAN Transmit structure */\r
+{\r
+ __IO uint32_t TFI; /*!< CAN Transmit Frame Information register*/\r
+ __IO uint32_t TID; /*!< CAN Transfer Identifier register*/\r
+ __IO uint32_t TD[2]; /*!<CAN Transmit Data register*/\r
+} IP_CAN_001_TX_T;\r
+\r
+/**\r
+ * @brief CAN Receive register block structure\r
+ */\r
+typedef struct /*!< CAN Receive Frame structure */\r
+{\r
+ __IO uint32_t RFS; /*!< Characteristic of the received frame. It includes the following characteristics:\r
+ CAN_RFS_BP: indicate that the current message is received in Bypass mode.\r
+ * CAN_RFS_RTR: indicate the value of Remote Transmission Request bit in the current message.\r
+ * CAN_RFS_FF: indicate that the identifier in the current message is 11-bit or 29-bit identifier.\r
+ Use CAN_RFS_ID_INDEX(RFS value) to get the ID Index of the matched entry in the Lookup Table RAM.\r
+ Use CAN_RFS_DLC(RFS value) to get the Data Length Code field of the current received message.\r
+ */\r
+ __IO uint32_t RID; /*!<Identifier in the received message. Use RFS field to determine if it is 11-bit or 29-bit identifier.*/\r
+ __IO uint32_t RD[2]; /*!< Data bytes of the received message. Use DLC value in RFS fied to determine the number of data bytes.*/\r
+} IP_CAN_001_RX_T;\r
+\r
+/**\r
+ * @brief CAN register block structure\r
+ */\r
+typedef struct /*!< CANn structure */\r
+{\r
+ __IO uint32_t MOD; /*!< CAN Mode Register */\r
+ __O uint32_t CMR; /*!< CAN Command Register */\r
+ __IO uint32_t GSR; /*!< CAN Global Status Register */\r
+ __I uint32_t ICR; /*!< CAN Interrupt and Capture Register */\r
+ __IO uint32_t IER; /*!< CAN Interrupt Enable Register*/\r
+ __IO uint32_t BTR; /*!< CAN Bus Timing Register*/\r
+ __IO uint32_t EWL; /*!< CAN Error Warning Limit Register*/\r
+ __I uint32_t SR; /*!< CAN Status Register*/\r
+ __IO IP_CAN_001_RX_T RX; /*!< CAN Receive Registers*/\r
+ __IO IP_CAN_001_TX_T TX[3]; /*!< CAN Transmit Registers*/\r
+} IP_CAN_001_T;\r
+\r
+/**\r
+ * @brief CAN Mode register definitions\r
+ */\r
+/** CAN Mode Register Bitmask */\r
+#define CAN_MOD_BITMASK (0xBF)\r
+\r
+/** CAN Operationg Mode */\r
+#define CAN_MOD_OPERATION ((uint32_t) 0)\r
+\r
+/** CAN Reset mode */\r
+#define CAN_MOD_RM ((uint32_t) (1 << 0))\r
+\r
+/** CAN Listen Only Mode (Don't send ACK/Message)*/\r
+#define CAN_MOD_LOM ((uint32_t) (1 << 1))\r
+\r
+/** CAN Self Test mode (Don't care ACK after sending message)*/\r
+#define CAN_MOD_STM ((uint32_t) (1 << 2))\r
+\r
+/** CAN Transmit Priority mode (Determine the transmit priority basing on Tx Priority Register)*/\r
+#define CAN_MOD_TPM ((uint32_t) (1 << 3))\r
+\r
+/** CAN Sleep mode */\r
+#define CAN_MOD_SM ((uint32_t) (1 << 4))\r
+\r
+/** CAN Receive Polarity mode (Determine RD is active Low or High).*/\r
+#define CAN_MOD_RPM ((uint32_t) (1 << 5))\r
+\r
+/** CAN Test mode (TD pin will reflects the bit detected on RD pin)*/\r
+#define CAN_MOD_TM ((uint32_t) (1 << 7))\r
+\r
+/**\r
+ * @brief CAN Command register definitions\r
+ */\r
+/** CAN Command Register Bitmask */\r
+#define CAN_CMR_BITMASK (0xFF)\r
+\r
+/** Request to Send message which is available in selected Transmit Buffer*/\r
+#define CAN_CMR_TR ((uint32_t) (1))\r
+\r
+/** Cancel the current transmission or the pending transmission request*/\r
+#define CAN_CMR_AT ((uint32_t) (1 << 1))\r
+\r
+/** Release the information in Receive Buffer */\r
+#define CAN_CMR_RRB ((uint32_t) (1 << 2))\r
+\r
+/** Clear the Data Overrun bit in Status Register(s)*/\r
+#define CAN_CMR_CDO ((uint32_t) (1 << 3))\r
+\r
+/** Self Reception Request.The message sent is received simultaneously. */\r
+#define CAN_CMR_SRR ((uint32_t) (1 << 4))\r
+\r
+/** Select one or multi transmit buffer(s).( n = 0/1/2) */\r
+#define CAN_CMR_STB(n) ((uint32_t) (1 << (n + 5)))\r
+\r
+/**\r
+ * @brief CAN Global Status register definitions\r
+ */\r
+/** CAN Global Status Register Bitmask */\r
+#define CAN_GSR_BITMASK (0xFFFF00FF)\r
+\r
+/** CAN Receive Buffer Status (At least one complete message is received) */\r
+#define CAN_GSR_RBS ((uint32_t) (1))\r
+\r
+/** CAN Data Overrun Status */\r
+#define CAN_GSR_DOS ((uint32_t) (1 << 1))\r
+\r
+/** CAN Transmit Buffer Status (All 3 Transmit Buffers are available)*/\r
+#define CAN_GSR_TBS ((uint32_t) (1 << 2))\r
+\r
+/** CAN Transmit Complete Status (All requested transmission(s) has (have) been successfully completed)*/\r
+#define CAN_GSR_TCS ((uint32_t) (1 << 3))\r
+\r
+/** CAN Receive Status (The CAN controller is receiving a message)*/\r
+#define CAN_GSR_RS ((uint32_t) (1 << 4))\r
+\r
+/** CAN Transmit Status (The CAN controller is sending a message)*/\r
+#define CAN_GSR_TS ((uint32_t) (1 << 5))\r
+\r
+/** CAN Error Status */\r
+#define CAN_GSR_ES ((uint32_t) (1 << 6))\r
+\r
+/** CAN Bus Status (CAN Controller is involed in bus activity or not*/\r
+#define CAN_GSR_BS ((uint32_t) (1 << 7))\r
+\r
+/** CAN Current value of the Rx Error Counter */\r
+#define CAN_GSR_RXERR(n) ((uint32_t) ((n >> 16) & 0xFF)\r
+\r
+/** CAN Current value of the Tx Error Counter */\r
+#define CAN_GSR_TXERR(n) ((uint32_t) ((n >> 24) & 0xFF)\r
+\r
+/**\r
+ * @brief CAN Interrupt and Capture register definitions\r
+ */\r
+/** CAN Interrupt and Capture Registe Bitmask */\r
+#define CAN_ICR_BITMASK (0xFFFF07FF)\r
+\r
+/** CAN Receive Interrupt (A new message was received)*/\r
+#define CAN_ICR_RI ((uint32_t) (1))\r
+\r
+/** CAN Transmit Interrupt (Transmit buffer 1 is available) */\r
+#define CAN_ICR_TI1 ((uint32_t) (1 << 1))\r
+\r
+/** CAN Error Warning Interrupt */\r
+#define CAN_ICR_EI ((uint32_t) (1 << 2))\r
+\r
+/** CAN Data Overrun Interrupt */\r
+#define CAN_ICR_DOI ((uint32_t) (1 << 3))\r
+\r
+/** CAN Wake-Up Interrupt */\r
+#define CAN_ICR_WUI ((uint32_t) (1 << 4))\r
+\r
+/** CAN Error Passive Interrupt */\r
+#define CAN_ICR_EPI ((uint32_t) (1 << 5))\r
+\r
+/** CAN Arbitration Lost Interrupt */\r
+#define CAN_ICR_ALI ((uint32_t) (1 << 6))\r
+\r
+/** CAN Bus Error Interrupt */\r
+#define CAN_ICR_BEI ((uint32_t) (1 << 7))\r
+\r
+/** CAN ID Ready Interrupt */\r
+#define CAN_ICR_IDI ((uint32_t) (1 << 8))\r
+\r
+/** CAN Transmit Interrupt 2 (Transmit buffer 2 is available) */\r
+#define CAN_ICR_TI2 ((uint32_t) (1 << 9))\r
+\r
+/** CAN Transmit Interrupt 3 (Transmit buffer 3 is available)*/\r
+#define CAN_ICR_TI3 ((uint32_t) (1 << 10))\r
+\r
+/** CAN Error Code Capture (Error Location)*/\r
+#define CAN_ICR_ERRBIT_VAL(n) ((uint32_t) (((n) >> 16) & 0x1F))\r
+/** Start of Frame error value */\r
+#define CAN_ICR_ERR_SOF (3)\r
+/** ID28...ID21 Error value */\r
+#define CAN_ICR_ERR_ID28_ID21 (2)\r
+/** ID28...ID21 Error value */\r
+#define CAN_ICR_ERR_ID20_ID18 (6)\r
+/**SRTR Bit Error value */\r
+#define CAN_ICR_ERR_SRTR (4)\r
+/**IDE Bit Error value */\r
+#define CAN_ICR_ERR_IDE (5)\r
+/** ID17...ID13 Error value */\r
+#define CAN_ICR_ERR_ID17_ID13 (7)\r
+/** ID12...ID15 Error value */\r
+#define CAN_ICR_ERR_ID12_ID5 (0x0F)\r
+/** ID4...ID0 Error value */\r
+#define CAN_ICR_ERR_ID4_ID0 (0x0E)\r
+/**RTR Bit Error value */\r
+#define CAN_ICR_ERR_RTR (0x0C)\r
+/**Reserved Bit 1 Error value */\r
+#define CAN_ICR_ERR_ReservedBit_1 (0x0D)\r
+/**Reserved Bit 0 Error value */\r
+#define CAN_ICR_ERR_ReservedBit_0 (0x09)\r
+/** DLC Error value */\r
+#define CAN_ICR_ERR_DLC (0x0B)\r
+/** Data Field Error value */\r
+#define CAN_ICR_ERR_DATA_FIELD (0x0A)\r
+/** CRC Sequence Error value */\r
+#define CAN_ICR_ERR_CRC_SEQ (0x08)\r
+/** CRC Delimiter Error value */\r
+#define CAN_ICR_ERR_CRC_DELIMITER (0x18)\r
+/** ACK Error value */\r
+#define CAN_ICR_ERR_ACK (0x19)\r
+/** ACK Delimiter Error value */\r
+#define CAN_ICR_ERR_ACK_DELIMITER (0x1B)\r
+/** EOF Error value */\r
+#define CAN_ICR_ERR_EOF (0x1A)\r
+/** Intermission Error value */\r
+#define CAN_ICR_ERR_INTERMISSION (0x12)\r
+\r
+/** CAN Error Direction */\r
+#define CAN_ICR_ERRDIR_RECEIVE ((uint32_t) (1 << 21))\r
+\r
+/** CAN Error Type Capture */\r
+#define CAN_ICR_ERRC_VAL(n) ((uint32_t) (((n) >> 22) & 0x3))\r
+#define CAN_ICR_BIT_ERROR (0)\r
+#define CAN_ICR_FORM_ERROR (1)\r
+#define CAN_ICR_STUFF_ERROR (2)\r
+#define CAN_ICR_OTHER_ERROR (3)\r
+\r
+/** CAN Arbitration Lost Capture */\r
+#define CAN_ICR_ALCBIT_VAL(n) ((uint32_t) (((n) >> 24) & 0xFF))\r
+\r
+/**\r
+ * @brief CAN Interrupt Enable register definitions\r
+ */\r
+/** CAN Interrupt Enable Register Bitmask */\r
+#define CAN_IER_BITMASK (0x7FF)\r
+\r
+/** CAN Receive Interrupt Enable */\r
+#define CAN_IER_RIE ((uint32_t) (1))\r
+\r
+/** CAN Transmit Interrupt Enable for buffer 1 */\r
+#define CAN_IER_TIE1 ((uint32_t) (1 << 1))\r
+\r
+/** CAN Error Warning Interrupt Enable */\r
+#define CAN_IER_EIE ((uint32_t) (1 << 2))\r
+\r
+/** CAN Data Overrun Interrupt Enable */\r
+#define CAN_IER_DOIE ((uint32_t) (1 << 3))\r
+\r
+/** CAN Wake-Up Interrupt Enable */\r
+#define CAN_IER_WUIE ((uint32_t) (1 << 4))\r
+\r
+/** CAN Error Passive Interrupt Enable */\r
+#define CAN_IER_EPIE ((uint32_t) (1 << 5))\r
+\r
+/** CAN Arbitration Lost Interrupt Enable */\r
+#define CAN_IER_ALIE ((uint32_t) (1 << 6))\r
+\r
+/** CAN Bus Error Interrupt Enable */\r
+#define CAN_IER_BEIE ((uint32_t) (1 << 7))\r
+\r
+/** CAN ID Ready Interrupt Enable */\r
+#define CAN_IER_IDIE ((uint32_t) (1 << 8))\r
+\r
+/** CAN Transmit Enable Interrupt for Buffer 2 */\r
+#define CAN_IER_TIE2 ((uint32_t) (1 << 9))\r
+\r
+/** CAN Transmit Enable Interrupt for Buffer 3 */\r
+#define CAN_IER_TIE3 ((uint32_t) (1 << 10))\r
+\r
+/**\r
+ * @brief CAN Bus Timing register definitions\r
+ */\r
+/** CAN Bus Timing Register Bitmask */\r
+#define CAN_BTR_BITMASK (0xFFC3FF)\r
+\r
+/** CAN Baudrate Prescaler */\r
+#define CAN_BTR_BRP(n) ((uint32_t) ((n) & 0x3FF))\r
+\r
+/** CAN Synchronization Jump Width */\r
+#define CAN_BTR_SJW(n) ((uint32_t) (((n) & 0x3) << 14))\r
+\r
+/** CAN Time Segment 1 */\r
+#define CAN_BTR_TESG1(n) ((uint32_t) (((n) & 0xF) << 16))\r
+\r
+/** CAN Time Segment 2 */\r
+#define CAN_BTR_TESG2(n) ((uint32_t) (((n) & 0xF) << 20))\r
+\r
+/** CAN Sampling */\r
+#define CAN_BTR_SAM ((uint32_t) (1 << 23))\r
+\r
+/**\r
+ * @brief CAN Error Warning Limit register definitions\r
+ */\r
+/** CAN Error Warning Limit Register Bitmask */\r
+#define CAN_EWL_BITMASK (0xFF)\r
+\r
+/** CAN Error Warning Limit */\r
+#define CAN_EWL_VAL(n) ((uint32_t) ((n) & 0xFF))\r
+\r
+/**\r
+ * @brief CAN Status Registe definitions\r
+ */\r
+/** CAN Status Registe Bitmask */\r
+#define CAN_SR_BITMASK (0xFFFFFF)\r
+\r
+/** CAN Receive Buffer Status (Bit 0, 8, 16 are the same)*/\r
+#define CAN_SR_RBS(n) ((uint32_t) (1 << ((n) * 8)))\r
+\r
+/** CAN Data Overrun Status (Bit 1, 9, 17 are the same)*/\r
+#define CAN_SR_DOS(n) ((uint32_t) (1 << (1 + (n) * 8)))\r
+\r
+/** CAN Transmit Buffer Status (Tx Buffer n=0/1/2 is available)*/\r
+#define CAN_SR_TBS(n) ((uint32_t) (1 << (2 + (n) * 8)))\r
+\r
+/** CAN Transmission Complete Status (The request on Tx Buffer n=0/1/2 has been completed) */\r
+#define CAN_SR_TCS(n) ((uint32_t) (1 << (3 + (n) * 8)))\r
+\r
+/** CAN Receive Status (Bit 4, 12, 20 are the same)*/\r
+#define CAN_SR_RS(n) ((uint32_t) (1 << (4 + (n) * 8)))\r
+\r
+/** CAN Transmit Status (The CAN controller is sending a message in Tx Buffer n=0/1/2) */\r
+#define CAN_SR_TS(n) ((uint32_t) (1 << (5 + (n) * 8)))\r
+\r
+/** CAN Error Status (Bit 6, 14, 22 are the same)*/\r
+#define CAN_SR_ES(n) ((uint32_t) (1 << (6 + (n) * 8)))\r
+\r
+/** CAN Bus Status (Bit 7, 15, 23 are the same)*/\r
+#define CAN_SR_BS(n) ((uint32_t) (1 << (7 + (n) * 8)))\r
+\r
+/**\r
+ * @brief CAN Receive Frame Status register definitions\r
+ */\r
+/** CAN Receive Frame Status Register Bitmask */\r
+#define CAN_RFS_BITMASK (0xC00F07FF)\r
+\r
+/** CAN ID Index */\r
+#define CAN_RFS_ID_INDEX(n) ((uint32_t) ((n) & 0x3FF))\r
+\r
+/** CAN Bypass */\r
+#define CAN_RFS_BP ((uint32_t) (1 << 10))\r
+\r
+/** CAN Data Length Code */\r
+#define CAN_RFS_DLC(n) ((uint32_t) ((n >> 16) & 0x0F))\r
+\r
+/** CAN Remote Transmission Request */\r
+#define CAN_RFS_RTR ((uint32_t) (1 << 30))\r
+\r
+/** CAN control 11 bit or 29 bit Identifier */\r
+#define CAN_RFS_FF ((uint32_t) ((uint32_t) 1 << 31))\r
+\r
+/**\r
+ * @brief CAN Receive Identifier Register definitions\r
+ */\r
+/** CAN 11 bit Identifier */\r
+#define CAN_RID_ID_11(n) ((uint32_t) ((n) & 0x7FF))\r
+\r
+/** CAN 29 bit Identifier */\r
+#define CAN_RID_ID_29(n) ((uint32_t) ((n) & 0x1FFFFFFF))\r
+\r
+/**\r
+ * @brief CAN Transmit Frame Information register definitions\r
+ */\r
+/** CAN Transmit Frame Information Register Bitmask */\r
+#define CAN_TFI_BITMASK (0xC00F00FF)\r
+\r
+/** CAN Priority */\r
+#define CAN_TFI_PRIO(n) ((uint32_t) ((n) & 0xFF))\r
+\r
+/** CAN Data Length Code */\r
+#define CAN_TFI_DLC(n) ((uint32_t) (((n) & 0xF) << 16))\r
+\r
+/** CAN Remote Frame Transmission */\r
+#define CAN_TFI_RTR ((uint32_t) (1 << 30))\r
+\r
+/** CAN control 11-bit or 29-bit Identifier */\r
+#define CAN_TFI_FF ((uint32_t) ((uint32_t) 1 << 31))\r
+\r
+/**\r
+ * @brief CAN Transfer Identifier register definitions\r
+ */\r
+/** CAN 11-bit Identifier */\r
+#define CAN_TID_ID11(n) ((uint32_t) ((n) & 0x7FF))\r
+\r
+/** CAN 11-bit Identifier */\r
+#define CAN_TID_ID29(n) ((uint32_t) ((n) & 0x1FFFFFFF))\r
+\r
+/**\r
+ * @brief CAN Central transmit Status register definitions\r
+ */\r
+/** CAN Central transmit Status Register Bitmask */\r
+#define CAN_TSR_BITMASK (0x30303)\r
+\r
+/** Bit indicate CAN n (0/1) is sending a message */\r
+#define CAN_TSR_TS(n) ((uint32_t) (1 << (n + 0)))\r
+\r
+/** Bit indicate all 3 Tx buffer of CAN n (0/1) are available */\r
+#define CAN_TSR_TBS(n) ((uint32_t) (1 << (n + 8)))\r
+\r
+/** Bit indicate all requested transmissions have been completed successfully by the CAN n(0/1) */\r
+#define CAN_TSR_TCS(n) ((uint32_t) (1 << (n + 16)))\r
+\r
+/**\r
+ * @brief CAN Central Receive Status register definitions\r
+ */\r
+/** CAN Central Receive Status Register Bitmask */\r
+#define CAN_RSR_BITMASK (0x30303)\r
+\r
+/** Bit indicate CAN n (0/1) is receiving a message */\r
+#define CAN_RSR_RS(n) ((uint32_t) (1 << (n + 0)))\r
+\r
+/** Bit indicate a received message is available in CAN n (0/1) */\r
+#define CAN_RSR_RBS(n) ((uint32_t) (1 << (n + 8)))\r
+\r
+/** Bit indicate a message was lost because the preceding message to CAN n(0/1) controller was not\r
+ read out quickly enough*/\r
+#define CAN_RSR_DOS(n) ((uint32_t) (1 << (n + 16)))\r
+\r
+/**\r
+ * @brief CAN Central Miscellaneous Status register definitions\r
+ */\r
+/** CAN Central Receive Status Register Bitmask */\r
+#define CAN_MSR_BITMASK (0x303)\r
+\r
+/** Bit indicate Tx/Rx Error Counter has reached the limit set in CAN n (0/1) */\r
+#define CAN_MSR_E(n) ((uint32_t) (1 << (n + 0)))\r
+\r
+/** Bit indicate CAN n (0/1) is currently involved in bus activities*/\r
+#define CAN_MSR_BS(n) ((uint32_t) (1 << (n + 8)))\r
+\r
+/**\r
+ * @brief Acceptance Filter Mode register definitions\r
+ */\r
+/** CAN Acceptance Filter Operation mode */\r
+#define CANAF_AFMR_OPERATION ((uint32_t) (0))\r
+\r
+/** CAN Acceptance Filter Off mode */\r
+#define CANAF_AFMR_ACCOFF ((uint32_t) (1))\r
+\r
+/** CAN Acceptance File Bypass mode */\r
+#define CANAF_AFMR_ACCBP ((uint32_t) (1 << 1))\r
+\r
+/** FullCAN Mode Enhancements */\r
+#define CANAF_AFMR_EFCAN ((uint32_t) (1 << 2))\r
+\r
+/**\r
+ * @brief Extended Frame Group Start Address register definitions\r
+ */\r
+/** The start address of the table of grouped Extended Identifier */\r
+#define CANAF_ENDADDR(n) ((uint32_t) (((n) & 0x3FF) << 2))\r
+#define CANAF_ENDADDR_VAL(n) ((uint32_t) ((n >> 2) & 0x3FF))\r
+\r
+/**\r
+ * @brief LUT Error Address register definitions\r
+ */\r
+/** CAN Look-Up Table Error Address */\r
+#define CANAF_LUTERRAD(n) ((uint32_t) (((n) & 0x1FF) << 2))\r
+\r
+/**\r
+ * @brief LUT Error register definitions\r
+ */\r
+/** CAN Look-Up Table Error */\r
+#define CANAF_LUTERR ((uint32_t) (1))\r
+\r
+/**\r
+ * @brief Global FullCANInterrupt Enable register definitions\r
+ */\r
+/** Global FullCANInterrupt Enable Register Bitmask */\r
+#define CANAF_FCANIE_BITMASK (0x01)\r
+\r
+/** Global FullCANInterrupt Enable */\r
+#define CANAF_FCANIE ((uint32_t) (1))\r
+\r
+/**\r
+ * @brief FullCAN Message Layout definitions\r
+ */\r
+\r
+/** FF Bit Position*/\r
+#define CANAF_FULLCAN_MSG_FF_POS (31)\r
+/** RTR Bit Position*/\r
+#define CANAF_FULLCAN_MSG_RTR_POS (30)\r
+/** Message Lost Bit Position*/\r
+#define CANAF_FULLCAN_MSG_LOST_POS (26)\r
+/** SEM Bit Position*/\r
+#define CANAF_FULLCAN_MSG_SEM_POS (24)\r
+/** SEM Bit Mask*/\r
+#define CANAF_FULLCAN_MSG_SEM_BITMASK (0x03)\r
+/** DLC Bit Position*/\r
+#define CANAF_FULLCAN_MSG_DLC_POS (16)\r
+/** DLC Bit Mask*/\r
+#define CANAF_FULLCAN_MSG_DLC_BITMASK (0x0F)\r
+/** SCC Bit Position*/\r
+#define CANAF_FULLCAN_MSG_SCC_POS (13)\r
+/** SCC Bit Mask*/\r
+#define CANAF_FULLCAN_MSG_SCC_BITMASK (0x07)\r
+/** 11bit-ID Bit Position*/\r
+#define CANAF_FULLCAN_MSG_ID11_POS (0)\r
+/** 11bit-ID Bit Mask*/\r
+#define CANAF_FULLCAN_MSG_ID11_BITMASK (0x7FF)\r
+\r
+/**\r
+ * @brief FullCAN Message Status\r
+ */\r
+/** AF is updating FullCAN Message*/\r
+#define CANAF_FULCAN_MSG_AF_UPDATING (0x01)\r
+/** AF has finished updating FullCAN Message*/\r
+#define CANAF_FULCAN_MSG_AF_FINISHED (0x03)\r
+/** CPU is in process of reading FullCAN Message*/\r
+#define CANAF_FULCAN_MSG_CPU_READING (0x0)\r
+\r
+/**\r
+ * @brief FullCAN Interrupt and Capture register definitions\r
+ */\r
+/** FullCAN Interrupt and Capture (0-31)*/\r
+#define CANAF_FCAN_IC_INTPND(n) ((n >= 32) ? ((uint32_t) (1 << (n - 32))) : ((uint32_t) (1 << n)))\r
+\r
+/**\r
+ * @brief Standard ID Entry definitions\r
+ */\r
+/** Start position of Controller Number Bits */\r
+#define CAN_STD_ENTRY_CTRL_NO_POS (13 )\r
+/** Mask of Controller Number Bits */\r
+#define CAN_STD_ENTRY_CTRL_NO_MASK (0x07)\r
+/** Start position of Disable bit */\r
+#define CAN_STD_ENTRY_DISABLE_POS (12 )\r
+/** Mask of Disable Bit */\r
+#define CAN_STD_ENTRY_DISABLE_MASK (0x01)\r
+/** Start position of Interrupt Enable bit (FullCAN entry only)*/\r
+#define CAN_STD_ENTRY_IE_POS (11 )\r
+/** Mask of Interrupt Enable bit (FullCAN entry only)*/\r
+#define CAN_STD_ENTRY_IE_MASK (0x01)\r
+/** Start position of ID bit */\r
+#define CAN_STD_ENTRY_ID_POS (0 )\r
+/** Mask of ID Bit */\r
+#define CAN_STD_ENTRY_ID_MASK (0x7FF)\r
+\r
+/**\r
+ * @brief Extended ID Entry definitions\r
+ */\r
+/** Start position of Controller Number Bits */\r
+#define CAN_EXT_ENTRY_CTRL_NO_POS (29 )\r
+/** Mask of Controller Number Bits */\r
+#define CAN_EXT_ENTRY_CTRL_NO_MASK (0x07)\r
+/** Start position of ID bit */\r
+#define CAN_EXT_ENTRY_ID_POS (0 )\r
+/** Mask of ID Bit */\r
+#define CAN_EXT_ENTRY_ID_MASK (0x1FFFFFFF)\r
+\r
+/**\r
+ * @brief CAN Message Type definitions\r
+ */\r
+\r
+/** Remote Message */\r
+#define CAN_REMOTE_MSG ((uint32_t) (1 << 0))\r
+\r
+/** Message use Extend ID*/\r
+#define CAN_EXTEND_ID_USAGE ((uint32_t) (1 << 30))\r
+\r
+/** The maximum data length in CAN Message */\r
+#define CAN_MSG_MAX_DATA_LEN (8)\r
+\r
+/**\r
+ * @brief CAN Buffer ID definition\r
+ */\r
+typedef enum IP_CAN_BUFFER_ID {\r
+ CAN_BUFFER_1 = 0, /*!< Buffer 1 */\r
+ CAN_BUFFER_2, /*!< Buffer 2 */\r
+ CAN_BUFFER_3, /*!< Buffer 3 */\r
+ CAN_BUFFER_LAST, /*!< Last Buffer */\r
+} IP_CAN_BUFFER_ID_T;\r
+\r
+/**\r
+ * @brief CAN Message Object Structure\r
+ */\r
+typedef struct /*!< Message structure */\r
+{\r
+ uint32_t ID; /*!< Message Identifier. If 30th-bit is set, this is 29-bit ID, othewise 11-bit ID */\r
+ uint32_t Type; /*!< Message Type. which can include: - CAN_REMOTE_MSG type*/\r
+ uint32_t DLC; /*!< Message Data Length: 0~8 */\r
+ uint8_t Data[CAN_MSG_MAX_DATA_LEN];/*!< Message Data */\r
+} IP_CAN_MSG_T;\r
+\r
+/**\r
+ * @brief CAN Bus Timing Structure\r
+ */\r
+typedef struct /*!< Bus Timing structure */\r
+{\r
+ uint16_t BRP; /*!< Baud Rate Prescaler */\r
+ uint8_t SJW; /*!< SJW value*/\r
+ uint8_t TESG1; /*!< TESG1 value */\r
+ uint8_t TESG2; /*!< TESG2 value */\r
+ uint8_t SAM; /*!<0: The bus is sampled once, 1: sampled 3 times */\r
+} IP_CAN_BUS_TIMING_T;\r
+\r
+/**\r
+ * @brief Standard ID Entry structure\r
+ */\r
+typedef struct {\r
+ uint8_t CtrlNo; /*!<Controller Number: 0 for CAN1 and 1 for CAN2*/\r
+ uint8_t Disable; /*!< 0(ENABLE)/1(DISABLE): Response On/Off dynamically*/\r
+ uint16_t ID_11; /*!< Standard ID, should be 11-bit value */\r
+} IP_CAN_STD_ID_Entry_T;\r
+\r
+/**\r
+ * @brief Standard ID Range structure\r
+ */\r
+typedef struct {\r
+ IP_CAN_STD_ID_Entry_T LowerID; /*!< Lower ID Bound, should be in 11-bit value*/\r
+ IP_CAN_STD_ID_Entry_T UpperID; /*!< Upper ID Bound, should be in 11-bit value*/\r
+} IP_CAN_STD_ID_RANGE_Entry_T;\r
+\r
+/**\r
+ * @brief Extended ID Entry structure\r
+ */\r
+typedef struct {\r
+ uint8_t CtrlNo; /*!<Controller Number: 0 for CAN1 and 1 for CAN2*/\r
+ uint32_t ID_29; /*!< Extend ID, shoud be 29-bit value */\r
+} IP_CAN_EXT_ID_Entry_T;\r
+\r
+/**\r
+ * @brief Extended ID Range structure\r
+ */\r
+typedef struct {\r
+ IP_CAN_EXT_ID_Entry_T LowerID; /*!< Lower ID Bound, should be in 29-bit value*/\r
+ IP_CAN_EXT_ID_Entry_T UpperID; /*!< Upper ID Bound, should be in 29-bit value*/\r
+} IP_CAN_EXT_ID_RANGE_Entry_T;\r
+\r
+/**\r
+ * @brief Acceptance Filter Section Table structure\r
+ */\r
+typedef struct {\r
+ IP_CAN_STD_ID_Entry_T *FullCANSec; /*!< The pointer to fullCAN section */\r
+ uint16_t FullCANEntryNum; /*!< FullCAN Entry Number */\r
+ IP_CAN_STD_ID_Entry_T *SffSec; /*!< The pointer to individual Standard ID Section */\r
+ uint16_t SffEntryNum; /*!< Standard ID Entry Number */\r
+ IP_CAN_STD_ID_RANGE_Entry_T *SffGrpSec; /*!< The pointer to Group Standard ID Section */\r
+ uint16_t SffGrpEntryNum; /*!< Group Standard ID Entry Number */\r
+ IP_CAN_EXT_ID_Entry_T *EffSec; /*!< The pointer to Extended ID Section */\r
+ uint16_t EffEntryNum; /*!< Extended ID Entry Number */\r
+ IP_CAN_EXT_ID_RANGE_Entry_T *EffGrpSec; /*!< The pointer to Group Extended ID Section */\r
+ uint16_t EffGrpEntryNum; /*!< Group Extended ID Entry Number */\r
+} IP_CAN_AF_LUT_T;\r
+\r
+/**\r
+ * @brief De-initialize the CAN peripheral\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_CAN_DeInit(IP_CAN_001_T *pCAN)\r
+{}\r
+\r
+/**\r
+ * @brief Get current mode register settings of the CAN controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @return Current Mode register value of the CAN Controller (Bit values of CAN_MOD_*)\r
+ */\r
+STATIC INLINE uint32_t IP_CAN_GetMode(IP_CAN_001_T *pCAN)\r
+{\r
+ return pCAN->MOD & CAN_MOD_BITMASK;\r
+}\r
+\r
+/**\r
+ * @brief Set the CAN command request\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @param command : Command request (Or'ed bit values of CAN_CMR_*).\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_CAN_SetCmd(IP_CAN_001_T *pCAN, uint32_t command)\r
+{\r
+ pCAN->CMR = command;\r
+}\r
+\r
+/**\r
+ * @brief Set Error Warning Limit for the CAN Controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @param ewl : expected limit\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_CAN_SetEWL(IP_CAN_001_T *pCAN, uint32_t ewl)\r
+{\r
+ pCAN->EWL = ewl & CAN_EWL_BITMASK;\r
+}\r
+\r
+/**\r
+ * @brief Get Error Warning Limit of the CAN Controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @return Error warning limit value\r
+ */\r
+STATIC INLINE uint8_t IP_CAN_GetEWL(IP_CAN_001_T *pCAN)\r
+{\r
+ return CAN_EWL_VAL(pCAN->EWL);\r
+}\r
+\r
+/**\r
+ * @brief Get global status register contents of the CAN Controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @return Gloabl Status register contents (Or'ed bit values of CAN_GSR_*)\r
+ */\r
+STATIC INLINE uint32_t IP_CAN_GetGlobalStatus(IP_CAN_001_T *pCAN)\r
+{\r
+ return pCAN->GSR;\r
+}\r
+\r
+/**\r
+ * @brief Get the status of the CAN Controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @return Status (Or'ed bit values of CAN_SR_*(n) with n = CAN_BUFFER_1/2/3).\r
+ */\r
+STATIC INLINE uint32_t IP_CAN_GetStatus(IP_CAN_001_T *pCAN)\r
+{\r
+ return pCAN->SR;\r
+}\r
+\r
+/**\r
+ * @brief Enable the given interrupt of the CAN Controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @param IntMask : Interrupt Mask value (Or'ed bit values of CAN_IER_*).\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_CAN_IntEnable(IP_CAN_001_T *pCAN, uint32_t IntMask) {\r
+ pCAN->IER |= IntMask;\r
+}\r
+\r
+/**\r
+ * @brief Disable the given interrupt of the CAN Controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @param IntMask : Interrupt Mask value (Or'ed bit values of CAN_IER_*).\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_CAN_IntDisable(IP_CAN_001_T *pCAN, uint32_t IntMask) {\r
+ pCAN->IER &= (~IntMask) & CAN_IER_BITMASK;\r
+}\r
+\r
+/**\r
+ * @brief Get the interrupt status of the CAN Controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @return Interrupt status (Or'ed bit values of CAN_ICR_* )\r
+ */\r
+STATIC INLINE uint32_t IP_CAN_GetIntStatus(IP_CAN_001_T *pCAN)\r
+{\r
+ return pCAN->ICR;\r
+}\r
+\r
+/**\r
+ * @brief Set CAN AF Mode\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param AFMode : Mode selected (Bit values of CANAF_AFMR_*)\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_CAN_AF_SetMode(IP_CAN_001_AF_T *pCanAF, uint32_t AFMode)\r
+{\r
+ pCanAF->AFMR = AFMode;\r
+}\r
+\r
+/**\r
+ * @brief Get CAN AF Mode\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @return Mode\r
+ */\r
+STATIC INLINE uint32_t IP_CAN_AF_GetMode(IP_CAN_001_AF_T *pCanAF)\r
+{\r
+ return pCanAF->AFMR;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the CAN peripheral\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @return None\r
+ */\r
+void IP_CAN_Init(IP_CAN_001_T *pCAN);\r
+\r
+/**\r
+ * @brief Enable/Disable the specified mode in CAN controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @param Mode : Mode selected (Bit values of CAN_MOD_*)\r
+ * @param NewState : ENABLE: Enable, DISABLE: Disable\r
+ * @return None\r
+ */\r
+void IP_CAN_SetMode(IP_CAN_001_T *pCAN, uint32_t Mode, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Set Bus Timing for the CAN Controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @param pBusTiming : Bus Timing information\r
+ * @return None\r
+ */\r
+void IP_CAN_SetBusTiming(IP_CAN_001_T *pCAN, IP_CAN_BUS_TIMING_T *pBusTiming);\r
+\r
+/**\r
+ * @brief Get message received by the CAN Controller\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @param pMsg : Pointer to the buffer to store the received message\r
+ * @return SUCCESS (message information saved) or ERROR (no message received)\r
+ */\r
+Status IP_CAN_Receive(IP_CAN_001_T *pCAN, IP_CAN_MSG_T *pMsg);\r
+\r
+/**\r
+ * @brief Request the CAN Controller to send message\r
+ * @param pCAN : Pointer to CAN peripheral block\r
+ * @param TxBufID : ID of buffer which will be used for transmit\r
+ * @param pMsg : Pointer to the buffer of message which will be sent\r
+ * @return SUCCESS (message information saved) or ERROR (no message received)\r
+ */\r
+Status IP_CAN_Send(IP_CAN_001_T *pCAN, IP_CAN_BUFFER_ID_T TxBufID, IP_CAN_MSG_T *pMsg);\r
+\r
+/**\r
+ * @brief Initialize CAN Acceptance Filter\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @return Nothing\r
+ */\r
+void IP_CAN_AF_Init(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);\r
+\r
+/**\r
+ * @brief Enable/Disable the interrupts of the CAN Controller in FullCAN Mode\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param NewState : ENABLE to enable/DISABLE to Disable\r
+ * @return Nothing\r
+ */\r
+void IP_CAN_FullCANIntConfig(IP_CAN_001_AF_T *pCanAF, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Get FullCAN interrupt status of the object\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param ObjID : Object ID\r
+ * @return Interrupt Status\r
+ */\r
+uint32_t IP_CAN_GetFullCANIntStatus(IP_CAN_001_AF_T *pCanAF, uint8_t ObjID);\r
+\r
+/**\r
+ * @brief Get FULLCANmessage automatically received by the AF\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param ObjID : Object ID\r
+ * @param pMsg : Pointer to the buffer storing the received message\r
+ * @param pSCC : Pointer to the buffer storing the controller ID of the received message\r
+ * @return SUCCESS (message information saved) or ERROR (no message received)\r
+ */\r
+Status IP_CAN_FullCANReceive(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ uint8_t ObjID, IP_CAN_MSG_T *pMsg, uint8_t *pSCC);\r
+\r
+/**\r
+ * @brief Clear CAN AF LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @return None\r
+ */\r
+void IP_CAN_ClearAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam);\r
+\r
+/**\r
+ * @brief Set CAN AF LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param pAFSections : Pointer to buffer storing AF Section Data\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_SetAFLUT(IP_CAN_001_AF_T *pCanAF, IP_CAN_001_AF_RAM_T *pCanAFRam, IP_CAN_AF_LUT_T *pAFSections);\r
+\r
+/**\r
+ * @brief Insert a FullCAN Entry into the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_InsertFullCANEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ IP_CAN_STD_ID_Entry_T *pEntry);\r
+\r
+/**\r
+ * @brief Insert an individual Standard Entry into the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_InsertIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ IP_CAN_STD_ID_Entry_T *pEntry);\r
+\r
+/**\r
+ * @brief Insert an Group Standard Entry into the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_InsertGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ IP_CAN_STD_ID_RANGE_Entry_T *pEntry);\r
+\r
+/**\r
+ * @brief Insert an individual Extended Entry into the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_InsertIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ IP_CAN_EXT_ID_Entry_T *pEntry);\r
+\r
+/**\r
+ * @brief Insert an Group Extended Entry into the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_InsertGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);\r
+\r
+/**\r
+ * @brief Remove a FullCAN Entry from the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the Full CAN section (started from 0)\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_RemoveFullCANEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ int16_t Position);\r
+\r
+/**\r
+ * @brief Remove an individual Standard Entry from the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the Individual STD section (started from 0)\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_RemoveIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ int16_t Position);\r
+\r
+/**\r
+ * @brief Remove an Group Standard Entry from the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the Group STD section (started from 0)\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_RemoveGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ int16_t Position);\r
+\r
+/**\r
+ * @brief Remove an individual Extended Entry from the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the Individual EXT section (started from 0)\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_RemoveIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ int16_t Position);\r
+\r
+/**\r
+ * @brief Remove an Group Extended Entry from the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the Group EXT section (started from 0)\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_RemoveGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ int16_t Position);\r
+\r
+/**\r
+ * @brief Get the number of entries of the given section\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param SectionID : Section ID\r
+ * @return Number of entries\r
+ */\r
+uint16_t IP_CAN_GetEntriesNum(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ IP_CAN_AF_RAM_SECTION_T SectionID);\r
+\r
+/**\r
+ * @brief Read a FullCAN Entry into from current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the given section (started from 0)\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_ReadFullCANEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ uint16_t Position,\r
+ IP_CAN_STD_ID_Entry_T *pEntry);\r
+\r
+/**\r
+ * @brief Read an individual Standard Entry from the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the given section (started from 0)\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_ReadIndividualSTDEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ uint16_t Position,\r
+ IP_CAN_STD_ID_Entry_T *pEntry);\r
+\r
+/**\r
+ * @brief Read an Group Standard Entry from the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the given section (started from 0)\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_ReadGroupSTDEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ uint16_t Position,\r
+ IP_CAN_STD_ID_RANGE_Entry_T *pEntry);\r
+\r
+/**\r
+ * @brief Read an individual Extended Entry from the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the given section (started from 0)\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_ReadIndividualEXTEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ uint16_t Position,\r
+ IP_CAN_EXT_ID_Entry_T *pEntry);\r
+\r
+/**\r
+ * @brief Read an Group Extended Entry from the current LUT\r
+ * @param pCanAF : Pointer to CAN AF Register block\r
+ * @param pCanAFRam : Pointer to CAN AF RAM Register block\r
+ * @param Position : Position of the entry in the given section (started from 0)\r
+ * @param pEntry : Pointer to the entry which will be inserted\r
+ * @return SUCCESS/ERROR\r
+ */\r
+Status IP_CAN_ReadGroupEXTEntry(IP_CAN_001_AF_T *pCanAF,\r
+ IP_CAN_001_AF_RAM_T *pCanAFRam,\r
+ uint16_t Position,\r
+ IP_CAN_EXT_ID_RANGE_Entry_T *pEntry);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CAN_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief CCAN registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CCAN_001_H_\r
+#define __CCAN_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_CCAN_001 IP: CCAN register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief CCAN message interface register block structure\r
+ */\r
+typedef struct { /*!< C_CAN message interface Structure */\r
+ __IO uint32_t IF_CMDREQ; /*!< Message interface command request */\r
+ union {\r
+ __IO uint32_t IF_CMDMSK_R; /*!< Message interface command mask (read direction) */\r
+ __IO uint32_t IF_CMDMSK_W; /*!< Message interface command mask (write direction) */\r
+ };\r
+\r
+ __IO uint32_t IF_MSK1; /*!< Message interface mask 1 */\r
+ __IO uint32_t IF_MSK2; /*!< Message interface mask 2 */\r
+ __IO uint32_t IF_ARB1; /*!< Message interface arbitration 1 */\r
+ __IO uint32_t IF_ARB2; /*!< Message interface arbitration 2 */\r
+ __IO uint32_t IF_MCTRL; /*!< Message interface message control */\r
+ __IO uint32_t IF_DA1; /*!< Message interface data A1 */\r
+ __IO uint32_t IF_DA2; /*!< Message interface data A2 */\r
+ __IO uint32_t IF_DB1; /*!< Message interface data B1 */\r
+ __IO uint32_t IF_DB2; /*!< Message interface data B2 */\r
+ __I uint32_t RESERVED[13];\r
+} IP_CCAN_001_IF_T;\r
+\r
+/**\r
+ * @brief CCAN Controller Area Network register block structure\r
+ */\r
+typedef struct { /*!< C_CAN Structure */\r
+ __IO uint32_t CNTL; /*!< CAN control */\r
+ __IO uint32_t STAT; /*!< Status register */\r
+ __I uint32_t EC; /*!< Error counter */\r
+ __IO uint32_t BT; /*!< Bit timing register */\r
+ __I uint32_t INT; /*!< Interrupt register */\r
+ __IO uint32_t TEST; /*!< Test register */\r
+ __IO uint32_t BRPE; /*!< Baud rate prescaler extension register */\r
+ __I uint32_t RESERVED0;\r
+ IP_CCAN_001_IF_T IF[2];\r
+ __I uint32_t RESERVED2[8];\r
+ __I uint32_t TXREQ1; /*!< Transmission request 1 */\r
+ __I uint32_t TXREQ2; /*!< Transmission request 2 */\r
+ __I uint32_t RESERVED3[6];\r
+ __I uint32_t ND1; /*!< New data 1 */\r
+ __I uint32_t ND2; /*!< New data 2 */\r
+ __I uint32_t RESERVED4[6];\r
+ __I uint32_t IR1; /*!< Interrupt pending 1 */\r
+ __I uint32_t IR2; /*!< Interrupt pending 2 */\r
+ __I uint32_t RESERVED5[6];\r
+ __I uint32_t MSGV1; /*!< Message valid 1 */\r
+ __I uint32_t MSGV2; /*!< Message valid 2 */\r
+ __I uint32_t RESERVED6[6];\r
+ __IO uint32_t CLKDIV; /*!< CAN clock divider register */\r
+} IP_CCAN_001_T;\r
+\r
+typedef enum IP_CCAN_TEST_MODE {\r
+ CCAN_BASIC_TEST_MODE = 1 << 2,\r
+ CCAN_SILENT_TEST_MODE = 1 << 3,\r
+ CCAN_LOOPBACK_TEST_MODE = 1 << 4\r
+} IP_CCAN_TEST_MODE_T;\r
+\r
+typedef enum IP_CCAN_INT {\r
+ CCAN_MODULE_INT = 1 << 1,\r
+ CCAN_STATUS_CHANGE_INT = 1 << 2,\r
+ CCAN_ERR_INT = 1 << 3\r
+} IP_CCAN_INT_T;\r
+\r
+/**\r
+ * @brief CAN message object structure\r
+ */\r
+typedef struct {\r
+ uint32_t id; /**< ID of message, if bit 30 is set then this is extended frame */\r
+ uint32_t dlc; /**< Message data length */\r
+ uint8_t data[8]; /**< Message data */\r
+} message_object;\r
+typedef enum IP_CCAN_MSG_INTERFACE {\r
+ IF1 = 0x00,\r
+ IF2 = 1,\r
+} IP_CCAN_MSG_INTERFACE_T;\r
+typedef enum IP_CCAN_STATUS {\r
+ CCAN_STAT_LEC = (0x7 << 0),\r
+ CCAN_STAT_TXOK = (1 << 3),\r
+ CCAN_STAT_RXOK = (1 << 4),\r
+ CCAN_STAT_EPASS = (1 << 5),\r
+ CCAN_STAT_EWARN = (1 << 6),\r
+ CCAN_STAT_BOFF = (1 << 7)\r
+} IP_CCAN_STATUS_T;\r
+\r
+/**\r
+ * @brief I2S transmit/receive mode for configuration\r
+ */\r
+typedef enum IP_CCAN_TRX_MODE {\r
+ CCAN_TX_MODE,\r
+ CCAN_RX_MODE,\r
+} IP_CCAN_TRX_MODE_T;\r
+/* Private Macros ---------------------------------------------------------- */\r
+#ifndef __GNUC__\r
+/* Macro for reading and writing to CCAN IF registers */\r
+#define CCAN_IF_Read(LPCx, reg, IFsel) (( ## LPCx ## ->IF ## [IFsel] ## . ## IF ## _ ## reg))\r
+#define CCAN_IF_Write(LPCx, reg, IFsel, val) (( ## LPCx ## ->IF ## [IFsel] ## . ## IF ## _ ## reg) = (val))\r
+#else\r
+#define CCAN_IF_Read(LPCx, reg, IFsel) (LPCx->IF[IFsel].IF ## _ ## reg)\r
+#define CCAN_IF_Write(LPCx, reg, IFsel, val) (LPCx->IF[IFsel].IF ## _ ## reg = val)\r
+#endif\r
+\r
+#define CCAN_STATUS_INT 0x8000\r
+\r
+#define CCAN_TX_DIR 1UL\r
+#define CCAN_RX_DIR 0UL\r
+\r
+/* bit field of IF command mask register */\r
+#define CCAN_DATAB (1 << 0) /* 1 is transfer data byte 4-7 to message object, 0 is not */\r
+#define CCAN_DATAA (1 << 1) /* 1 is transfer data byte 0-3 to message object, 0 is not */\r
+#define CCAN_NEWDAT (1 << 2) /* Clear NEWDAT bit in the message object */\r
+#define CCAN_CLRINTPND (1 << 3)\r
+#define CCAN_CTRL (1 << 4) /* 1 is transfer the CTRL bit to the message object, 0 is not */\r
+#define CCAN_ARB (1 << 5) /* 1 is transfer the ARB bits to the message object, 0 is not */\r
+#define CCAN_MASK (1 << 6) /* 1 is transfer the MASK bit to the message object, 0 is not */\r
+#define CCAN_RW(n) (((n) & 1UL) << 7) /* 0 is READ, 1 is WRITE */\r
+#define CCAN_WR 1UL\r
+#define CCAN_RD 0UL\r
+\r
+/* bit field of IF mask 2 register */\r
+#define CCAN_MASK_MXTD (1 << 15) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */\r
+#define CCAN_MASK_MDIR(n) (((n) & 0x01) << 14) /* 1 direction bit is used in the RX filter unit, 0 is not */\r
+\r
+/* bit field of IF identifier 2 register */\r
+#define CCAN_ID_MVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */\r
+#define CCAN_ID_MTD (1 << 14) /* 1 extended identifier bit is used in the RX filter unit, 0 is not */\r
+#define CCAN_ID_DIR(n) (((n) & 0x01) << 13) /* 1 direction bit is used in the RX filter unit, 0 is not */\r
+\r
+/* bit field of IF message control register */\r
+#define CCAN_NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */\r
+#define CCAN_MLST (1 << 14) /* 1 indicates a message loss. */\r
+#define CCAN_INTP (1 << 13) /* 1 indicates message object is an interrupt source */\r
+#define CCAN_UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */\r
+#define CCAN_TXIE (1 << 11) /* 1 is TX interrupt enabled */\r
+#define CCAN_RXIE (1 << 10) /* 1 is RX interrupt enabled */\r
+\r
+#define CCAN_RMTEN(n) (((n) & 1UL) << 9) /* 1 is remote frame enabled */\r
+\r
+#define CCAN_TXRQ (1 << 8) /* 1 is TxRqst enabled */\r
+#define CCAN_EOB (1 << 7) /* End of buffer, always write to 1 */\r
+#define CCAN_DLC 0x000F /* bit mask for DLC */\r
+\r
+#define CCAN_ID_STD_MASK 0x07FF\r
+#define CCAN_ID_EXT_MASK 0x1FFFFFFF\r
+#define CCAN_DLC_MASK 0x0F\r
+\r
+/* bit field of IF command request n register */\r
+#define CCAN_IFCREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when\r
+ RD/WR done */\r
+/* CAN CTRL register */\r
+#define CCAN_CTRL_INIT (1 << 0)\r
+#define CCAN_CTRL_IE (1 << 1)\r
+#define CCAN_CTRL_SIE (1 << 2)\r
+#define CCAN_CTRL_EIE (1 << 3)\r
+#define CCAN_CTRL_DAR (1 << 5)\r
+#define CCAN_CTRL_CCE (1 << 6)\r
+#define CCAN_CTRL_TEST (1 << 7)\r
+\r
+/**\r
+ * @brief Configure the bit timing for CCAN bus\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param ClkDiv : Set the clock divider\r
+ * @param BaudRatePrescaler : Set the baud rate Prescaler\r
+ * @param SynJumpWidth : Set the synchronization jump width\r
+ * @param Tseg1 : Set the Phase buffer segment 1\r
+ * @param Tseg2 : Set the Phase buffer segment 2\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_TimingCfg (IP_CCAN_001_T *pCCAN,\r
+ uint32_t ClkDiv,\r
+ uint32_t BaudRatePrescaler,\r
+ uint8_t SynJumpWidth,\r
+ uint8_t Tseg1,\r
+ uint8_t Tseg2);\r
+\r
+/**\r
+ * @brief Initialize the CAN controller\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param NewState : New state, ENABLE for starting initialization, DISABLE for normal operation\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_SWInit (IP_CCAN_001_T *pCCAN, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Enable/Disable CCAN Interrupts\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param Int_type : Type of interrupt\r
+ * @param NewState : New state, ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_IntEnable (IP_CCAN_001_T *pCCAN, IP_CCAN_INT_T Int_type, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Enable/Disable automatic retransmission\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param NewState : New state, ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_AutoRetransmitEnable (IP_CCAN_001_T *pCCAN, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Get the current value of the transmit/receive error counter\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be CCAN_TX_MODE or CCAN_RX_MODE\r
+ * @return Current value of the transmit/receive error counter\r
+ */\r
+uint8_t IP_CCAN_GetErrCounter (IP_CCAN_001_T *pCCAN, IP_CCAN_TRX_MODE_T TRMode);\r
+\r
+/**\r
+ * @brief Get the CCAN status register\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @return CCAN status register\r
+ */\r
+uint32_t IP_CCAN_GetStatus (IP_CCAN_001_T *pCCAN);\r
+\r
+/**\r
+ * @brief Set the CCAN status\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param val : Value to be set for status register\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_SetStatus (IP_CCAN_001_T *pCCAN, uint32_t val);\r
+\r
+/**\r
+ * @brief Get the source ID of an interrupt\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @return Interrupt source ID\r
+ */\r
+uint32_t IP_CCAN_Get_IntID (IP_CCAN_001_T *pCCAN);\r
+\r
+/**\r
+ * @brief Enable/Disable test mode in CCAN\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param test_mode : Selected mode, the different test functions may be combined\r
+ * @param NewState : New state, ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_TestModeEnable(IP_CCAN_001_T *pCCAN, IP_CCAN_TEST_MODE_T test_mode, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Clear interrupt pending bit in the message object\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param IFsel : The Message interface to be used\r
+ * @param msg_num : Message number\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_ClearIntPend (IP_CCAN_001_T *pCCAN, IP_CCAN_MSG_INTERFACE_T IFsel, uint8_t msg_num);\r
+\r
+/**\r
+ * @brief Clear new data flag bit in the message object\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param IFsel : The Message interface to be used\r
+ * @param msg_num : Message number\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_Clear_NewDataFlag (IP_CCAN_001_T *pCCAN, IP_CCAN_MSG_INTERFACE_T IFsel, uint8_t msg_num);\r
+\r
+/**\r
+ * @brief Enable/Disable the message object to valid\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param IFsel : The Message interface to be used\r
+ * @param msg_num : Message number\r
+ * @param NewState: New state, ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_SetValidMsg(IP_CCAN_001_T *pCCAN, IP_CCAN_MSG_INTERFACE_T IFsel, uint8_t msg_num, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Check the message objects is valid or not\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @return A 32 bits value, each bit corresponds to a message objects form 0 to 31 (1 is valid, 0 is invalid)\r
+ */\r
+uint32_t IP_CCAN_GetValidMsg(IP_CCAN_001_T *pCCAN);\r
+\r
+/**\r
+ * @brief Get the transmit repuest bit in all message objects\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @return A 32 bits value, each bit corresponds to transmit request bit in message objects\r
+ */\r
+uint32_t IP_CCAN_GetTxRQST(IP_CCAN_001_T *pCCAN);\r
+\r
+/**\r
+ * @brief Set a message into the message object in message RAM\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param IFsel : The Message interface to be used\r
+ * @param direction : Select the message object is used for transmiting or receiving, should be CCAN_TX_DIR or CCAN_RX_DIR\r
+ * @param RemoteEnable: Enable/Disable passives transmit by using remote frame\r
+ * @param msg_num : Message number\r
+ * @param msg_ptr : Pointer of message to be set\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_SetMsgObject (IP_CCAN_001_T *pCCAN,\r
+ IP_CCAN_MSG_INTERFACE_T IFsel,\r
+ uint8_t direction,\r
+ uint32_t RemoteEnable,\r
+ uint8_t msg_num,\r
+ const message_object *msg_ptr);\r
+\r
+/**\r
+ * @brief Get a message object in message RAM into the message buffer\r
+ * @param pCCAN : The base of CCAN peripheral on the chip\r
+ * @param IFsel : The Message interface to be used\r
+ * @param msg_num : The number of message object in message RAM to be get\r
+ * @param msg_buf : Pointer of the message buffer\r
+ * @return Nothing\r
+ */\r
+void IP_CCAN_GetMsgObject (IP_CCAN_001_T *pCCAN,\r
+ IP_CCAN_MSG_INTERFACE_T IFsel,\r
+ uint8_t msg_num,\r
+ message_object *msg_buf);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CCAN_001_H_ */\r
--- /dev/null
+/*
+ * @brief CMP Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMP_001_H_
+#define __CMP_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_CMP_001 IP: Comparator register block and driver
+ * @ingroup IP_Drivers
+ * Comparator
+ * @{
+ */
+/** The number of embeded comparators supported */
+#define CMP_NUM 2
+
+/**
+ * @brief Comparator (CMP) register block structure
+ */
+typedef struct { /*!< Comparator structure */
+ __IO uint32_t CMP_CTRL; /*!< Comparator block control register */
+ __IO uint32_t CMP_CTRLx[CMP_NUM]; /*!< Specific comparator control register */
+} IP_CMP_001_T;
+
+/**
+ * @brief Comparator control definition
+ */
+typedef enum IP_CMP_ENCTRL {
+ CMP_ENCTRL_DISABLE, /*!< Disable */
+ CMP_ENCTRL_DIS_IN_DS_PWD, /*!< Disable in deep sleep mode and power down mode*/
+ CMP_ENCTRL_DIS_IN_PWD, /*!< Disable in power down mode*/
+ CMP_ENCTRL_ENABLE, /*!< Enable/Power-up*/
+} IP_CMP_ENCTRL_T;
+
+/*!< Comparator control register Bitmask */
+#define CMP_CTRL_BITMASK (0xF30F)
+/*!< The comparator current source control bitmask*/
+#define CMP_CTRL_PD_IREF_BITMASK (0x03)
+/*!< Control the comparator current source (n is IP_CMP_ENCTRL_T value)*/
+#define CMP_CTRL_PD_IREF(n) ((((uint32_t) (n)) & 0x03))
+/*!< The comparator bandgap reference control bitmask*/
+#define CMP_CTRL_PD_VBG_BITMASK (((uint32_t) 0x03) << 2)
+/*!< Control the comparator bandgap reference (n is IP_CMP_ENCTRL_T value)*/
+#define CMP_CTRL_PD_VBG(n) ((((uint32_t) (n)) & 0x03) << 2)
+/*!< The CMP_ROSC ouput control bitmask */
+#define CMP_CTRL_ROSC_BITMASK ((uint32_t) 0x300)
+/*!< The CMP_ROSC output is set by CMP1, reset by CMP0 */
+#define CMP_CTRL_ROSCCTL_CMP1 (0x00)
+/*!< The CMP_ROSC output is set by CMP0, reset by CMP1 */
+#define CMP_CTRL_ROSCCTL_CMP0 (((uint32_t) 0x01) << 8)
+/*!< The CMP_ROSC output is reset by the internal chip reset */
+#define CMP_CTRL_EXT_RESET_INTERNAL (0x00)
+/*!< The CMP_ROSC output is reset by the CMP_RESET input */
+#define CMP_CTRL_EXT_RESET_CMPRESET (((uint32_t) 0x01) << 9)
+/*!< Timer Capture input control bitmask */
+#define CMP_CTRL_TIMERCAPTURE_BITMASK ((uint32_t) 0xF000)
+/*!< Selects the comparator 0 level output as the input for Timer0 capture input 2 */
+#define CMP_CTRL_T0CAP2_0LEVEL (0x00)
+/*!< Selects the comparator 1 level output as the input for Timer0 capture input 2 */
+#define CMP_CTRL_T0CAP2_1LEVEL (((uint32_t) 0x01) << 12)
+/*!< Selects the comparator 0 edge output as the input for Timer0 capture input 3 */
+#define CMP_CTRL_T0CAP3_0EDGE (0x00)
+/*!< Selects the comparator 1 edge output as the input for Timer0 capture input 3 */
+#define CMP_CTRL_T0CAP3_1EDGE (((uint32_t) 0x01) << 13)
+/*!< Selects the comparator 1 edge output as the input for Timer1 capture input 2 */
+#define CMP_CTRL_T1CAP2_1EDGE (0x00)
+/*!< Selects the comparator 0 level output as the input for Timer1 capture input 2 */
+#define CMP_CTRL_T1CAP2_0LEVEL (((uint32_t) 0x01) << 14)
+/*!< Selects the comparator 1 level output as the input for Timer1 capture input 3 */
+#define CMP_CTRL_T1CAP3_1LEVEL (0x00)
+/*!< Selects the comparator 0 edge output as the input for Timer1 capture input 3 */
+#define CMP_CTRL_T1CAP3_0EDGE (((uint32_t) 0x01) << 15)
+
+/*!< The comparator x control register Bitmask */
+#define CMP_CTRLx_BITMASK ((uint32_t) 0x1F7FF77F)
+/*!< The comparator x enable bitmask*/
+#define CMP_CTRLx_EN_BITMASK (0x03)
+/*!< Control the comparator x (n is IP_CMP_ENCTRL_T value)*/
+#define CMP_CTRLx_EN(n) ((((uint32_t) (n)) & 0x03))
+/*!< Enable the output of compartor x */
+#define CMP_CTRLx_OE (((uint32_t) 0x01) << 2)
+/*!< The status of compartor x, reflects the comparator x output*/
+#define CMP_CTRLx_STAT (((uint32_t) 0x01) << 3)
+/*!< Comparator VM input control bitmask */
+#define CMP_CTRLx_VM_BITMASK (((uint32_t) 0x07) << 4)
+/*!< Select the VM input*/
+#define CMP_CTRLx_VM(n) ((((uint32_t) (n)) & 0x07) << 4)
+/*!< Comparator VP input control bitmask */
+#define CMP_CTRLx_VP_BITMASK (((uint32_t) 0x07) << 8)
+/*!< Select the VP input */
+#define CMP_CTRLx_VP(n) ((((uint32_t) (n)) & 0x07) << 8)
+/*!< Synchronize the Comparator x output with the internal bus clock for outpur to other peripherals */
+#define CMP_CTRLx_SYNC (((uint32_t) 0x01) << 12)
+/*!< Comparator Hysteresis control bitmask */
+#define CMP_CTRLx_HYS_BITMASK (((uint32_t) 0x03) << 13)
+/*!< Determine the difference required between the comparator inputs before the comparator output switch*/
+#define CMP_CTRLx_HYS(n) ((((uint32_t) (n)) & 0x03) << 13)
+/*!< Interrupt control bitmask */
+#define CMP_CTRLx_INTCTRL_BITMASK ((uint32_t) 0x78000)
+/*!< Comparator output is used as-is for generating interrupts. */
+#define CMP_CTRLx_INTPOL_NORMAL (0x00)
+/*!< Comparator output is used inverted for generating interrupts. */
+#define CMP_CTRLx_INTPOL_INV (((uint32_t) 0x01) << 15)
+/*!< Comparator x interrupt is edge triggered. */
+#define CMP_CTRLx_INTTYPE_EDGE (0x00)
+/*!< Comparator x interrupt is level triggered.*/
+#define CMP_CTRLx_INTTYPE_LEVEL (((uint32_t) 0x01) << 16)
+/*!< Comparator x interrupt edge control bitmask */
+#define CMP_CTRLx_INTEDGE_BITMASK (((uint32_t) 0x03) << 17)
+/*!< Select edge on which triggered interrupt is active*/
+#define CMP_CTRLx_INTEDGE(n) ((((uint32_t) (n)) & 0x03) << 17)
+/*!< Comparator interrupt flag */
+#define CMP_CTRLx_INTFLAG (((uint32_t) 0x01) << 19)
+/*!< The VLAD Enable bitmask*/
+#define CMP_CTRLx_VLADEN_BITMASK (((uint32_t) 0x03) << 20)
+/*!< Control the comparator x (n is IP_CMP_ENCTRL_T value)*/
+#define CMP_CTRLx_VLADEN(n) ((((uint32_t) (n)) & 0x03) << 20)
+/*!< Select VREF_CMP pin as voltage reference for comparator voltage ladder */
+#define CMP_CTRLx_VLADREF_VREFCMP (0x00)
+/*!< Select VDDA pin as voltage reference for comparator voltage ladder */
+#define CMP_CTRLx_VLADREF_VDDA (((uint32_t) 0x01) << 22)
+/*!< Volatge ladder value bitmask */
+#define CMP_CTRLx_VSEL_BITMASK ((uint32_t) ((0x1F) << 24))
+/*!< Voltage ladder value for Comparator */
+#define CMP_CTRLx_VSEL(n) ((((uint32_t) (n)) & 0x1F) << 24)
+
+/**
+ * @brief Comparator VM/VP input definitions
+ */
+typedef enum IP_CMP_INPUT {
+ CMP_INPUT_VREF_DIV, /*!< Vref divider.*/
+ CMP_INPUT_CMPx_IN0, /*!< Use the input 0 of the comparator*/
+ CMP_INPUT_CMPx_IN1, /*!< Use the input 1 of the comparator*/
+ CMP_INPUT_CMPx_IN2, /*!< Use the input 2 of the comparator*/
+ CMP_INPUT_CMPx_IN3, /*!< Use the input 3 of the comparator*/
+ CMP_INPUT_CMP_OTHER_IN0, /*!< Use the input 0 of the other comparator.*/
+ CMP_INPUT_INTERNAL_09VBG, /*!< internal 0.9 V band gap reference.*/
+} IP_CMP_INPUT_T;
+
+/**
+ * @brief Comparator hysteresis selection definitions
+ */
+typedef enum IP_CMP_HYS {
+ CMP_HYS_NONE = CMP_CTRLx_HYS(0), /*!<No hysteresis (the output will switch as the voltages cross) */
+ CMP_HYS_5MV = CMP_CTRLx_HYS(1), /*!< 5mV hysteresis */
+ CMP_HYS_10MV = CMP_CTRLx_HYS(2), /*!< 10mV hysteresis */
+ CMP_HYS_15MV = CMP_CTRLx_HYS(3), /*!< 15mV hysteresis */
+} IP_CMP_HYS_T;
+
+/**
+ * @brief Comparator interrupt edge selection definitions
+ */
+typedef enum IP_CMP_INTEDGE {
+ CMP_INTEDGE_FALLING = CMP_CTRLx_INTEDGE(0), /*!< Interrupt is active on falling edge */
+ CMP_INTEDGE_RISING = CMP_CTRLx_INTEDGE(1), /*!< Interrupt is active on rising edge */
+ CMP_INTEDGE_BOTH = CMP_CTRLx_INTEDGE(2), /*!< Interrupt is active on falling and rising edges */
+} IP_CMP_INTEDGE_T;
+
+/**
+ * @brief Initializes the CMP
+ * @param pCMP : Pointer to Comparator Register block
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_Init(IP_CMP_001_T *pCMP) {}
+
+/**
+ * @brief De-initializes the CMP
+ * @param pCMP : Pointer to Comparator Register block
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_DeInit(IP_CMP_001_T *pCMP) {}
+
+/**
+ * @brief Enables comparator current source
+ * @param pCMP : Pointer to Comparator Register block
+ * @param en : Enable mode
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_EnableCurrentSrc(IP_CMP_001_T *pCMP, IP_CMP_ENCTRL_T en)
+{
+ pCMP->CMP_CTRL = (pCMP->CMP_CTRL & (~CMP_CTRL_PD_IREF_BITMASK)) | CMP_CTRL_PD_IREF(en);
+}
+
+/**
+ * @brief Enables comparator bandgap reference
+ * @param pCMP : Pointer to Comparator Register block
+ * @param en : Enable mode
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_EnableBandGap(IP_CMP_001_T *pCMP, IP_CMP_ENCTRL_T en)
+{
+ pCMP->CMP_CTRL = (pCMP->CMP_CTRL & (~CMP_CTRL_PD_VBG_BITMASK)) | CMP_CTRL_PD_VBG(en);
+}
+
+/**
+ * @brief Control CMP_ROSC
+ * @param pCMP : Pointer to Comparator Register block
+ * @param flag : Or-ed bit value of CMP_CTRL_ROSCCTL_* and CMP_CTRL_EXT_RESET_*
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_ControlROSC(IP_CMP_001_T *pCMP, uint32_t flag)
+{
+ pCMP->CMP_CTRL = (pCMP->CMP_CTRL & (~CMP_CTRL_ROSC_BITMASK)) | flag;
+}
+
+/**
+ * @brief Control CMP_ROSC
+ * @param pCMP : Pointer to Comparator Register block
+ * @param flag : Or-ed bit value of CMP_CTRL_T*CAP*
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_SetTimerCapInput(IP_CMP_001_T *pCMP, uint32_t flag)
+{
+ pCMP->CMP_CTRL = (pCMP->CMP_CTRL & (~CMP_CTRL_TIMERCAPTURE_BITMASK)) | flag;
+}
+
+/**
+ * @brief Sets up voltage ladder
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @param ladSel : Voltage ladder value (0~31).
+ * @param flag :0(CMP_VREF used)/CMP_CTRLx_VLADREF_VDDA (VDDA used)
+ * @return Nothing
+ * @note VREF divider 0 = ladSel*VRef0/31
+ */
+STATIC INLINE void IP_CMP_SetupVoltLadder(IP_CMP_001_T *pCMP, uint8_t id,
+ uint16_t ladSel, uint32_t flag)
+{
+ pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~(CMP_CTRLx_VSEL_BITMASK | CMP_CTRLx_VLADREF_VDDA))) | CMP_CTRLx_VSEL(
+ ladSel) | flag;
+}
+
+/**
+ * @brief Enables voltage ladder
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @param en : Enable mode
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_EnableVoltLadder(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_ENCTRL_T en)
+{
+ pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_VLADEN_BITMASK)) | CMP_CTRLx_VLADEN(en);
+}
+
+/**
+ * @brief Selects positive voltage input
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @param input : Selected input
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_SetPosVoltRef(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_INPUT_T input)
+{
+ pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_VP_BITMASK)) | CMP_CTRLx_VP(input);
+}
+
+/**
+ * @brief Selects negative voltage input
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @param input : Selected input
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_SetNegVoltRef(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_INPUT_T input)
+{
+ pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_VM_BITMASK)) | CMP_CTRLx_VM(input);
+}
+
+/**
+ * @brief Selects hysteresis level
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @param hys : Selected Hysteresis level
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_SetHysteresis(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_HYS_T hys)
+{
+ pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_HYS_BITMASK)) | hys;
+}
+
+/**
+ * @brief Enables specified comparator
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @param en : Enable mode
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_Enable(IP_CMP_001_T *pCMP, uint8_t id, IP_CMP_ENCTRL_T en)
+{
+ pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_EN_BITMASK)) | CMP_CTRLx_EN(en);
+}
+
+/**
+ * @brief Returns the current comparator status
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator Id (0/1)
+ * @return SET/RESET
+ */
+STATIC INLINE FlagStatus IP_CMP_GetCmpStatus(IP_CMP_001_T *pCMP, uint8_t id)
+{
+ return (pCMP->CMP_CTRLx[id] & CMP_CTRLx_STAT) ? SET : RESET;
+}
+
+/**
+ * @brief Enable comparator output
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_EnableOuput(IP_CMP_001_T *pCMP, uint8_t id)
+{
+ pCMP->CMP_CTRLx[id] |= CMP_CTRLx_OE;
+}
+
+/**
+ * @brief Disable comparator output
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_DisableOutput(IP_CMP_001_T *pCMP, uint8_t id)
+{
+ pCMP->CMP_CTRLx[id] &= ~CMP_CTRLx_OE;
+}
+
+/**
+ * @brief Synchronizes Comparator output to bus clock
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_EnableSyncCmpOut(IP_CMP_001_T *pCMP, uint8_t id)
+{
+ pCMP->CMP_CTRLx[id] |= CMP_CTRLx_SYNC;
+}
+
+/**
+ * @brief Sets comparator output to be used directly (no sync)
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_DisableSyncCmpOut(IP_CMP_001_T *pCMP, uint8_t id)
+{
+ pCMP->CMP_CTRLx[id] &= ~CMP_CTRLx_SYNC;
+}
+
+/**
+ * @brief Sets up comparator interrupt
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @param intFlag : Or-ed value of CMP_CTRLx_INTTYPE_*, CMP_CTRLx_INTPOL_*
+ * @param edgeSel : the edge on which interrupt occurs.
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_ConfigInt(IP_CMP_001_T *pCMP, uint8_t id,
+ uint32_t intFlag,
+ IP_CMP_INTEDGE_T edgeSel)
+{
+ pCMP->CMP_CTRLx[id] = (pCMP->CMP_CTRLx[id] & (~CMP_CTRLx_INTCTRL_BITMASK)) | intFlag | edgeSel;
+}
+
+/**
+ * @brief Get the CMP interrupt status
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @return SET/RESET
+ */
+STATIC INLINE FlagStatus IP_CMP_GetIntStatus(IP_CMP_001_T *pCMP, uint8_t id)
+{
+ return (pCMP->CMP_CTRLx[id] & CMP_CTRLx_INTFLAG) ? SET : RESET;
+}
+
+/**
+ * @brief Clears the CMP interrupt status
+ * @param pCMP : Pointer to Comparator Register block
+ * @param id : Comparator ID
+ * @return Nothing
+ */
+STATIC INLINE void IP_CMP_CMP_ClearIntStatus(IP_CMP_001_T *pCMP, uint8_t id)
+{
+ pCMP->CMP_CTRLx[id] |= CMP_CTRLx_INTFLAG;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMP_001_H_ */
--- /dev/null
+/*\r
+ * @brief Cyclic Redundancy Check (CRC) registers and driver functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __CRC_001_H_\r
+#define __CRC_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_CRC_001 IP: CRC register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief CRC register block structure\r
+ */\r
+typedef struct { /*!< CRC Structure */\r
+ __IO uint32_t MODE; /*!< CRC Mode Register */\r
+ __IO uint32_t SEED; /*!< CRC SEED Register */\r
+ union {\r
+ __I uint32_t SUM; /*!< CRC Checksum Register. */\r
+ __O uint32_t WRDATA32; /*!< CRC Data Register: write size 32-bit*/\r
+ __O uint16_t WRDATA16; /*!< CRC Data Register: write size 16-bit*/\r
+ __O uint8_t WRDATA8; /*!< CRC Data Register: write size 8-bit*/\r
+ };\r
+\r
+} IP_CRC_001_T;\r
+\r
+/**\r
+ * @brief CRC MODE register description\r
+ */\r
+#define CRC_MODE_POLY_BITMASK ((0x03)) /** CRC polynomial Bit mask */\r
+#define CRC_MODE_POLY_CCITT (0x00) /** Select CRC-CCITT polynomial */\r
+#define CRC_MODE_POLY_CRC16 (0x01) /** Select CRC-16 polynomial */\r
+#define CRC_MODE_POLY_CRC32 (0x02) /** Select CRC-32 polynomial */\r
+#define CRC_MODE_WRDATA_BITMASK (0x03 << 2) /** CRC WR_Data Config Bit mask */\r
+#define CRC_MODE_WRDATA_BIT_RVS (1 << 2) /** Select Bit order reverse for WR_DATA (per byte) */\r
+#define CRC_MODE_WRDATA_CMPL (1 << 3) /** Select One's complement for WR_DATA */\r
+#define CRC_MODE_SUM_BITMASK (0x03 << 4) /** CRC Sum Config Bit mask */\r
+#define CRC_MODE_SUM_BIT_RVS (1 << 4) /** Select Bit order reverse for CRC_SUM */\r
+#define CRC_MODE_SUM_CMPL (1 << 5) /** Select One's complement for CRC_SUM */\r
+\r
+#define MODE_CFG_CCITT (0x00) /** Pre-defined mode word for default CCITT setup */\r
+#define MODE_CFG_CRC16 (0x15) /** Pre-defined mode word for default CRC16 setup */\r
+#define MODE_CFG_CRC32 (0x36) /** Pre-defined mode word for default CRC32 setup */\r
+\r
+#define CRC_SEED_CCITT (0x0000FFFF)/** Initial seed value for CCITT mode */\r
+#define CRC_SEED_CRC16 (0x00000000)/** Initial seed value for CRC16 mode */\r
+#define CRC_SEED_CRC32 (0xFFFFFFFF)/** Initial seed value for CRC32 mode */\r
+\r
+/*\r
+ * @brief CRC polynomial\r
+ */\r
+typedef enum IP_CRC_001_POLY {\r
+ CRC_POLY_CCITT = CRC_MODE_POLY_CCITT, /**< CRC-CCIT polynomial */\r
+ CRC_POLY_CRC16 = CRC_MODE_POLY_CRC16, /**< CRC-16 polynomial */\r
+ CRC_POLY_CRC32 = CRC_MODE_POLY_CRC32, /**< CRC-32 polynomial */\r
+ CRC_POLY_LAST,\r
+} IP_CRC_001_POLY_T;\r
+\r
+/**\r
+ * @brief Initializes the CRC Engine\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_CRC_Init(IP_CRC_001_T *pCRC) {}\r
+\r
+/**\r
+ * @brief De-initializes the CRC Engine\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_CRC_DeInit(IP_CRC_001_T *pCRC) {}\r
+\r
+/**\r
+ * @brief Select polynomial for CRC Engine\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param poly : CRC polynomial selection\r
+ * @param flags : An Or'ed value of flags that setup the mode\r
+ * @return Nothing\r
+ * @note Flags for setting up the mode word include CRC_MODE_WRDATA_BIT_RVS,\r
+ * CRC_MODE_WRDATA_CMPL, CRC_MODE_SUM_BIT_RVS, and CRC_MODE_SUM_CMPL.\r
+ */\r
+STATIC INLINE void IP_CRC_SetPoly(IP_CRC_001_T *pCRC, IP_CRC_001_POLY_T poly,\r
+ uint32_t flags)\r
+{\r
+ pCRC->MODE = (uint32_t) poly | flags;\r
+}\r
+\r
+/**\r
+ * @brief Sets up the CRC engine with defaults based on the polynomial to be used\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param poly : The enumerated polynomial to be used\r
+ * @return Nothing\r
+ */\r
+void IP_CRC_UseDefaultConfig(IP_CRC_001_T *pCRC, IP_CRC_001_POLY_T poly);\r
+\r
+/**\r
+ * @brief Get mode register of CRC Engine\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @return Current CRC Mode register (Or-ed bits value of CRC_MODE_*)\r
+ */\r
+STATIC INLINE uint32_t IP_CRC_GetMode(IP_CRC_001_T *pCRC)\r
+{\r
+ return pCRC->MODE;\r
+}\r
+\r
+/**\r
+ * @brief Set mode register of CRC Engine\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param mode : mode value to be set in mode register\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_CRC_SetMode(IP_CRC_001_T *pCRC, uint32_t mode)\r
+{\r
+ pCRC->MODE = mode;\r
+}\r
+\r
+/**\r
+ * @brief Set Seed value\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param Seed : selected seed value\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_CRC_SetSeed(IP_CRC_001_T *pCRC, uint32_t Seed)\r
+{\r
+ pCRC->SEED = Seed;\r
+}\r
+\r
+/**\r
+ * @brief Get Seed value.\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @return current seed value\r
+ */\r
+STATIC INLINE uint32_t IP_CRC_GetSeed(IP_CRC_001_T *pCRC)\r
+{\r
+ return pCRC->SEED;\r
+}\r
+\r
+/**\r
+ * @brief Write 8-bit data to CRC WR Data register.\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param data : data to be written\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_CRC_Write8(IP_CRC_001_T *pCRC, uint8_t data)\r
+{\r
+ pCRC->WRDATA8 = data;\r
+}\r
+\r
+/**\r
+ * @brief Write 16-bit data to CRC WR Data register.\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param data : data to be written\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_CRC_Write16(IP_CRC_001_T *pCRC, uint16_t data)\r
+{\r
+ pCRC->WRDATA16 = (uint32_t) data;\r
+}\r
+\r
+/**\r
+ * @brief Write 32-bit data to CRC WR Data register.\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param data : data to be written\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_CRC_Write32(IP_CRC_001_T *pCRC, uint32_t data)\r
+{\r
+ pCRC->WRDATA32 = data;\r
+}\r
+\r
+/**\r
+ * @brief Read current calculated checksum from CRC Engine\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @return Check sum value\r
+ */\r
+STATIC INLINE uint32_t IP_CRC_ReadSum(IP_CRC_001_T *pCRC)\r
+{\r
+ return pCRC->SUM;\r
+}\r
+\r
+/**\r
+ * @brief Convenience function for computing a standard CCITT checksum from an 8-bit data block\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param data : Pointer to the block of 8 bit data\r
+ * @param bytes : The number of bytes pointed to by data\r
+ * @return Computed checksum for the block\r
+ */\r
+uint32_t IP_CRC_CRC8(IP_CRC_001_T *pCRC, const uint8_t *data, uint32_t bytes);\r
+\r
+/**\r
+ * @brief Convenience function for computing a standard CRC16 checksum from 16-bit data block\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param data : Pointer to the block of 16-bit data\r
+ * @param hwords : The number of halfword entries pointed to by data\r
+ * @return Computed checksum for the block\r
+ */\r
+uint32_t IP_CRC_CRC16(IP_CRC_001_T *pCRC, const uint16_t *data, uint32_t hwords);\r
+\r
+/**\r
+ * @brief Convenience function for computing a standard CRC32 checksum from 32-bit data block\r
+ * @param pCRC : Pointer to selected CRC Engine register block structure\r
+ * @param data : Pointer to the block of 32-bit data\r
+ * @param words : The number of 32-bit entries pointed to by data\r
+ * @return Computed checksum for the block\r
+ */\r
+uint32_t IP_CRC_CRC32(IP_CRC_001_T *pCRC, const uint32_t *data, uint32_t words);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CRC_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief DAC Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __DAC_001_H_\r
+#define __DAC_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_DAC_001 IP: DAC register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief DAC register block structure\r
+ */\r
+typedef struct { /*!< DAC Structure */\r
+ __IO uint32_t CR; /*!< DAC register. Holds the conversion data. */\r
+ __IO uint32_t CTRL; /*!< DAC control register. */\r
+ __IO uint32_t CNTVAL; /*!< DAC counter value register. */\r
+} IP_DAC_001_T;\r
+\r
+/** After the selected settling time after this field is written with a\r
+ new VALUE, the voltage on the AOUT pin (with respect to VSSA)\r
+ is VALUE/1024 � VREF */\r
+#define DAC_VALUE(n) ((uint32_t) ((n & 0x3FF) << 6))\r
+/** If this bit = 0: The settling time of the DAC is 1 microsecond max,\r
+ * and the maximum current is 700 microAmpere\r
+ * If this bit = 1: The settling time of the DAC is 2.5 microsecond\r
+ * and the maximum current is 350 microAmpere\r
+ */\r
+#define DAC_BIAS_EN ((uint32_t) (1 << 16))\r
+/** Value to reload interrupt DMA counter */\r
+#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))\r
+\r
+/** DCAR double buffering */\r
+#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))\r
+/** DCAR Time out count enable */\r
+#define DAC_CNT_ENA ((uint32_t) (1 << 2))\r
+/** DCAR DMA access */\r
+#define DAC_DMA_ENA ((uint32_t) (1 << 3))\r
+/** DCAR DACCTRL mask bit */\r
+#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))\r
+\r
+/**\r
+ * @brief Current option in DAC configuration option\r
+ */\r
+typedef enum IP_DAC_CURRENT_OPT {\r
+ DAC_MAX_UPDATE_RATE_1MHz = 0, /*!< Shorter settling times and higher power consumption;\r
+ allows for a maximum update rate of 1 MHz */\r
+ DAC_MAX_UPDATE_RATE_400kHz /*!< Longer settling times and lower power consumption;\r
+ allows for a maximum update rate of 400 kHz */\r
+} IP_DAC_CURRENT_OPT_T;\r
+\r
+/**\r
+ * @brief Initial DAC configuration\r
+ * - Maximum update rate is 1MHz\r
+ * - Value to AOUT is 0\r
+ * @param pDAC : pointer to the DAC peripheral block\r
+ * @return Nothing\r
+ */\r
+void IP_DAC_Init(IP_DAC_001_T *pDAC);\r
+\r
+/**\r
+ * @brief Update value to DAC buffer\r
+ * @param pDAC : pointer to the DAC peripheral block\r
+ * @param dac_value : value 10 bit to be converted to output\r
+ * @return Nothing\r
+ */\r
+void IP_DAC_UpdateValue (IP_DAC_001_T *pDAC, uint32_t dac_value);\r
+\r
+/**\r
+ * @brief Set maximum update rate for DAC\r
+ * @param pDAC : pointer to the DAC peripheral block\r
+ * @param bias : Using Bias value, should be:\r
+ * - 0 is 1MHz\r
+ * - 1 is 400kHz\r
+ * @return Nothing\r
+ */\r
+void IP_DAC_SetBias (IP_DAC_001_T *pDAC, uint32_t bias);\r
+\r
+/**\r
+ * @brief Enables the DMA operation and controls DMA timer\r
+ * @param pDAC : pointer to the DAC peripheral block\r
+ * @param dacFlags : An Or'ed value of the following DAC values:\r
+ * - DAC_DBLBUF_ENA :enable/disable DACR double buffering feature\r
+ * - DAC_CNT_ENA :enable/disable timer out counter\r
+ * - DAC_DMA_ENA :enable/disable DMA access\r
+ * @return Nothing\r
+ * @note Pass an Or'ed value of the DAC flags to enable those options.\r
+ */\r
+STATIC INLINE void IP_DAC_ConfigDAConverterControl(IP_DAC_001_T *pDAC, uint32_t dacFlags)\r
+{\r
+ uint32_t temp;\r
+\r
+ temp = pDAC->CTRL & ~DAC_DACCTRL_MASK;\r
+ pDAC->CTRL = temp | dacFlags;\r
+}\r
+\r
+/**\r
+ * @brief Set reload value for interrupt/DMA counter\r
+ * @param pDAC : pointer to the DAC peripheral block\r
+ * @param time_out : time out to reload for interrupt/DMA counter\r
+ * @return Nothing\r
+ */\r
+void IP_DAC_SetDMATimeOut(IP_DAC_001_T *pDAC, uint32_t time_out);\r
+\r
+/**\r
+ * @brief Get status for interrupt/DMA time out\r
+ * @param pDAC : pointer to the DAC peripheral block\r
+ * @return interrupt/DMA time out status, should be SET or RESET\r
+ */\r
+IntStatus IP_DAC_GetIntStatus(IP_DAC_001_T *pDAC);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __DAC_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief EEPROM registers and driver functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __EEPROM_001_H_\r
+#define __EEPROM_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_EEPROM_001 IP: EEPROM register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Supports 4032 byte EEPROM devices.\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief EEPROM register block structure\r
+ */\r
+typedef struct { /* EEPROM Structure */\r
+ __IO uint32_t CMD; /*!< EEPROM command register */\r
+ __IO uint32_t ADDR; /*!< EEPROM address register */\r
+ __O uint32_t WDATA; /*!< EEPROM write data register */\r
+ __I uint32_t RDATA; /*!< EEPROM read data register */\r
+ __IO uint32_t WSTATE; /*!< EEPROM wait state register */\r
+ __IO uint32_t CLKDIV; /*!< EEPROM clock divider register */\r
+ __IO uint32_t PWRDWN; /*!< EEPROM power-down register */\r
+ uint32_t RESERVED0[975];\r
+ __O uint32_t INTENCLR; /*!< EEPROM interrupt enable clear */\r
+ __O uint32_t INTENSET; /*!< EEPROM interrupt enable set */\r
+ __I uint32_t INTSTAT; /*!< EEPROM interrupt status */\r
+ __I uint32_t INTEN; /*!< EEPROM interrupt enable */\r
+ __O uint32_t INTSTATCLR; /*!< EEPROM interrupt status clear */\r
+ __O uint32_t INTSTATSET; /*!< EEPROM interrupt status set */\r
+} IP_EEPROM_001_T;\r
+\r
+#define EEPROM_PAGE_SIZE 64 /*!< EEPROM byes per page */\r
+#define EEPROM_PAGE_NUM 63 /*!< EEPROM pages */\r
+\r
+/*\r
+ * @brief Macro defines for EEPROM command register\r
+ */\r
+#define EEPROM_CMD_8BITS_READ (0) /*!< EEPROM 8-bit read command */\r
+#define EEPROM_CMD_16BITS_READ (1) /*!< EEPROM 16-bit read command */\r
+#define EEPROM_CMD_32BITS_READ (2) /*!< EEPROM 32-bit read command */\r
+#define EEPROM_CMD_8BITS_WRITE (3) /*!< EEPROM 8-bit write command */\r
+#define EEPROM_CMD_16BITS_WRITE (4) /*!< EEPROM 16-bit write command */\r
+#define EEPROM_CMD_32BITS_WRITE (5) /*!< EEPROM 32-bit write command */\r
+#define EEPROM_CMD_ERASE_PRG_PAGE (6) /*!< EEPROM erase/program command */\r
+#define EEPROM_CMD_RDPREFETCH (1 << 3)/*!< EEPROM read pre-fetch enable */\r
+\r
+/*\r
+ * @brief Macro defines for EEPROM power down register\r
+ */\r
+#define EEPROM_PWRDWN (1 << 0)\r
+\r
+/*\r
+ * @brief Macro defines for EEPROM interrupt related registers\r
+ */\r
+#define EEPROM_INT_ENDOFRW (1 << 26)\r
+#define EEPROM_INT_ENDOFPROG (1 << 28)\r
+\r
+/**\r
+ * @brief EEPROM Mode type definition\r
+ */\r
+typedef enum IP_EEPROM_RWSIZE {\r
+ EEPROM_RWSIZE_8BITS = 1,\r
+ EEPROM_RWSIZE_16BITS = 2,\r
+ EEPROM_RWSIZE_32BITS = 4\r
+} IP_EEPROM_RWSIZE_T;\r
+\r
+/**\r
+ * @brief Select an EEPROM command\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param cmd : EEPROM command.\r
+ * @return Nothing\r
+ * @note cmd is or-ed bits value of EEPROM_CMD_[8|16|32]BITS_READ/EEPROM_CMD_[8|16|32]BITS_WRITE\r
+ * with EEPROM_CMD_RDPREFETCH flag.\r
+ * Read and erase/program operations are started on the EEPROM device as a side-effect of calling this function.\r
+ * Write operations are started as a side-effect of writing data to data register.\r
+ */\r
+STATIC INLINE void IP_EEPROM_SetCmd(IP_EEPROM_001_T *pEEPROM, uint32_t cmd)\r
+{\r
+ pEEPROM->CMD = cmd;\r
+}\r
+\r
+/**\r
+ * @brief Set EEPROM address\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param pageAddr : Page address.\r
+ * @param pageOffset : Page address.\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_EEPROM_SetAddr(IP_EEPROM_001_T *pEEPROM, uint32_t pageAddr, uint32_t pageOffset)\r
+{\r
+ pEEPROM->ADDR = (pageAddr << 6) | pageOffset;\r
+}\r
+\r
+/**\r
+ * @brief Write EEPROM data\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param data : EEPROM data.\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_EEPROM_WriteData(IP_EEPROM_001_T *pEEPROM, uint32_t data)\r
+{\r
+ pEEPROM->WDATA = data;\r
+}\r
+\r
+/**\r
+ * @brief Read EEPROM data\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @return data\r
+ */\r
+STATIC INLINE uint32_t IP_EEPROM_ReadData(IP_EEPROM_001_T *pEEPROM)\r
+{\r
+ return pEEPROM->RDATA;\r
+}\r
+\r
+/**\r
+ * @brief Set EEPROM wait state\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param ws : Wait State value.\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_EEPROM_SetWaitState(IP_EEPROM_001_T *pEEPROM, uint32_t ws)\r
+{\r
+ pEEPROM->WSTATE = ws;\r
+}\r
+\r
+/**\r
+ * @brief Put EEPROM device in power down mode\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_EEPROM_EnablePowerDown(IP_EEPROM_001_T *pEEPROM)\r
+{\r
+ pEEPROM->PWRDWN = EEPROM_PWRDWN;\r
+}\r
+\r
+/**\r
+ * @brief Bring EEPROM device out of power down mode\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @return Nothing\r
+ * @note Any EEPROM operation has to be suspended for 100us while the EEPROM wakes up.\r
+ */\r
+STATIC INLINE void IP_EEPROM_DisablePowerDown(IP_EEPROM_001_T *pEEPROM)\r
+{\r
+ pEEPROM->PWRDWN = 0;\r
+}\r
+\r
+/**\r
+ * @brief Enable EEPROM interrupt\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_EEPROM_EnableInt(IP_EEPROM_001_T *pEEPROM, uint32_t mask)\r
+{\r
+ pEEPROM->INTENSET = mask;\r
+}\r
+\r
+/**\r
+ * @brief Disable EEPROM interrupt\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_EEPROM_DisableInt(IP_EEPROM_001_T *pEEPROM, uint32_t mask)\r
+{\r
+ pEEPROM->INTENCLR = mask;\r
+}\r
+\r
+/**\r
+ * @brief Get the value of the EEPROM interrupt enable register\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @return Or-ed bits value of EEPROM_INT_*\r
+ */\r
+STATIC INLINE uint32_t IP_EEPROM_GetIntEnable(IP_EEPROM_001_T *pEEPROM)\r
+{\r
+ return pEEPROM->INTEN;\r
+}\r
+\r
+/**\r
+ * @brief Get EEPROM interrupt status\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @return Or-ed bits value of EEPROM_INT_*\r
+ */\r
+STATIC INLINE uint32_t IP_EEPROM_GetIntStatus(IP_EEPROM_001_T *pEEPROM)\r
+{\r
+ return pEEPROM->INTSTAT;\r
+}\r
+\r
+/**\r
+ * @brief Set EEPROM interrupt status\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_EEPROM_SetIntStatus(IP_EEPROM_001_T *pEEPROM, uint32_t mask)\r
+{\r
+ pEEPROM->INTSTATSET = mask;\r
+}\r
+\r
+/**\r
+ * @brief Clear EEPROM interrupt status\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_EEPROM_ClearIntStatus(IP_EEPROM_001_T *pEEPROM, uint32_t mask)\r
+{\r
+ pEEPROM->INTSTATCLR = mask;\r
+}\r
+\r
+/**\r
+ * @brief Initializes EEPROM\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param div : clock divide value (pre-minus 1)\r
+ * @return Nothing\r
+ */\r
+void IP_EEPROM_Init(IP_EEPROM_001_T *pEEPROM, uint32_t div);\r
+\r
+/**\r
+ * @brief De-initializes EEPROM\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_EEPROM_DeInit(IP_EEPROM_001_T *pEEPROM)\r
+{\r
+ /* Enable EEPROM power down mode */\r
+ IP_EEPROM_EnablePowerDown(pEEPROM);\r
+}\r
+\r
+/**\r
+ * @brief Erase data in page register\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @return Nothing\r
+ */\r
+void IP_EEPROM_ErasePageRegister(IP_EEPROM_001_T *pEEPROM);\r
+\r
+/**\r
+ * @brief Write data to page register\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param pageOffset : offset of data in page register(0 -> EEPROM_PAGE_SIZE-1)\r
+ * @param pData : buffer that contain data that will be written to buffer\r
+ * @param wsize : The number of bytes in each writting (1/2/4 bytes)\r
+ * @param byteNum : number written data (bytes)\r
+ * @return The bumber of byte written\r
+ * @note The pageOffset must be aligned following selected mode.\r
+ */\r
+uint32_t IP_EEPROM_WritePageRegister(IP_EEPROM_001_T *pEEPROM, uint16_t pageOffset,\r
+ uint8_t *pData, uint8_t wsize, uint32_t byteNum);\r
+\r
+/**\r
+ * @brief Read data from non-volatile memory\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param pageOffset : offset of data in page register(0 -> EEPROM_PAGE_SIZE-1)\r
+ * @param pageAddr : page address (0 ->EEPROM_PAGE_NUM -1 )\r
+ * @param pData : buffer that contain data read from read data register\r
+ * @param rsize : The number of bytes in each reading (1/2/4 bytes)\r
+ * @param byteNum : number of read data (bytes)\r
+ * @return The bumber of byte read\r
+ * @note The pageOffset must be aligned following selected mode.\r
+ */\r
+uint32_t IP_EEPROM_ReadPage(IP_EEPROM_001_T *pEEPROM,\r
+ uint16_t pageOffset,\r
+ uint16_t pageAddr,\r
+ uint8_t *pData,\r
+ uint8_t rsize,\r
+ uint32_t byteNum);\r
+\r
+/**\r
+ * @brief Erase/Program an EEPROM page\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param pageAddr : EEPROM page address (0-62)\r
+ * @return Nothing\r
+ */\r
+void IP_EEPROM_EraseProgramPage(IP_EEPROM_001_T *pEEPROM, uint16_t pageAddr);\r
+\r
+/**\r
+ * @brief Wait for interrupt occurs\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param mask : expected interrupt\r
+ * @return Nothing\r
+ */\r
+void IP_EEPROM_WaitForIntStatus(IP_EEPROM_001_T *pEEPROM, uint32_t mask);\r
+\r
+/**\r
+ * @brief Write data to EEPROM at specific address\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param pageOffset : offset of data in page register(0 -> EEPROM_PAGE_SIZE-1)\r
+ * @param pageAddr : page address (0 ->EEPROM_PAGE_NUM -1 )\r
+ * @param pData : buffer that contain data that will be written to buffer\r
+ * @param wsize : Write size:<br>\r
+ * - EEPROM_RWSIZE_8BITS : 8-bit read/write mode<br>\r
+ * - EEPROM_RWSIZE_16BITS : 16-bit read/write mode<br>\r
+ * - EEPROM_RWSIZE_32BITS : 32-bit read/write mode<br>\r
+ * @param byteNum : number written data (bytes)\r
+ * @return SUCCESS on successful write of data, or ERROR\r
+ * @note The pageOffset must be aligned following selected mode. <br>\r
+ * This function actually write data into EEPROM memory and automatically\r
+ * write into next page if current page is overflowed\r
+ */\r
+Status IP_EEPROM_Write(IP_EEPROM_001_T *pEEPROM,\r
+ uint16_t pageOffset,\r
+ uint16_t pageAddr,\r
+ void *pData,\r
+ IP_EEPROM_RWSIZE_T wsize,\r
+ uint32_t byteNum);\r
+\r
+/**\r
+ * @brief Read data to EEPROM at specific address\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param pageOffset : offset of data in page register(0 -> EEPROM_PAGE_SIZE-1)\r
+ * @param pageAddr : page address (0 ->EEPROM_PAGE_NUM -1 )\r
+ * @param pData : buffer that contain data read from read data register\r
+ * @param rsize : Read size:<br>\r
+ * - EEPROM_RWSIZE_8BITS : 8-bit read/write mode<br>\r
+ * - EEPROM_RWSIZE_16BITS : 16-bit read/write mode<br>\r
+ * - EEPROM_RWSIZE_32BITS : 32-bit read/write mode<br>\r
+ * @param byteNum : number read data (bytes)\r
+ * @return SUCCESS on successful write of data, or ERROR\r
+ * @note The pageOffset must be aligned following selected mode.\r
+ */\r
+Status IP_EEPROM_Read(IP_EEPROM_001_T *pEEPROM,\r
+ uint16_t pageOffset,\r
+ uint16_t pageAddr,\r
+ void *pData,\r
+ IP_EEPROM_RWSIZE_T rsize,\r
+ uint32_t byteNum);\r
+\r
+/**\r
+ * @brief Erase a page at the specific address\r
+ * @param pEEPROM : pointer to EEPROM peripheral block\r
+ * @param pageAddr : EEPROM page address (0-62)\r
+ * @return Nothing\r
+ */\r
+void IP_EEPROM_Erase(IP_EEPROM_001_T *pEEPROM, uint16_t pageAddr);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __EEPROM_001_H_ */\r
--- /dev/null
+/*
+ * @brief EEPROM registers and driver functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __EEPROM_002_H_
+#define __EEPROM_002_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_EEPROM_002 IP: EEPROM register block and driver (002)
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+/**
+ * @brief EEPROM register block structure
+ */
+typedef struct { /* EEPROM Structure */
+ __IO uint32_t CMD; /*!< EEPROM command register */
+ uint32_t RESERVED0;
+ __IO uint32_t RWSTATE; /*!< EEPROM read wait state register */
+ __IO uint32_t AUTOPROG; /*!< EEPROM auto programming register */
+ __IO uint32_t WSTATE; /*!< EEPROM wait state register */
+ __IO uint32_t CLKDIV; /*!< EEPROM clock divider register */
+ __IO uint32_t PWRDWN; /*!< EEPROM power-down register */
+ uint32_t RESERVED2[1007];
+ __O uint32_t INTENCLR; /*!< EEPROM interrupt enable clear */
+ __O uint32_t INTENSET; /*!< EEPROM interrupt enable set */
+ __I uint32_t INTSTAT; /*!< EEPROM interrupt status */
+ __I uint32_t INTEN; /*!< EEPROM interrupt enable */
+ __O uint32_t INTSTATCLR; /*!< EEPROM interrupt status clear */
+ __O uint32_t INTSTATSET; /*!< EEPROM interrupt status set */
+} IP_EEPROM_002_T;
+
+/*
+ * @brief Macro defines for EEPROM command register
+ */
+#define EEPROM_CMD_ERASE_PRG_PAGE (6) /*!< EEPROM erase/program command */
+
+/*
+ * @brief Macro defines for EEPROM Auto Programming register
+ */
+#define EEPROM_AUTOPROG_OFF (0) /*!<Auto programming off */
+#define EEPROM_AUTOPROG_AFT_1WORDWRITTEN (1) /*!< Erase/program cycle is triggered after 1 word is written */
+#define EEPROM_AUTOPROG_AFT_LASTWORDWRITTEN (2) /*!< Erase/program cycle is triggered after a write to AHB
+ address ending with ......1111100 (last word of a page) */
+
+/*
+ * @brief Macro defines for EEPROM power down register
+ */
+#define EEPROM_PWRDWN (1 << 0)
+
+/*
+ * @brief Macro defines for EEPROM interrupt related registers
+ */
+#define EEPROM_INT_ENDOFPROG (1 << 2)
+
+/**
+ * @brief Select an EEPROM command
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param cmd : EEPROM command.
+ * @return Nothing
+ * @note cmd is or-ed bits value of EEPROM_CMD_*
+ */
+STATIC INLINE void IP_EEPROM_SetCmd(IP_EEPROM_002_T *pEEPROM, uint32_t cmd)
+{
+ pEEPROM->CMD = cmd;
+}
+
+/**
+ * @brief Set Auto programming mode
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param mode : Auto programming Mode (Value of EEPROM_AUTOPROG_).
+ * @return Nothing
+ */
+STATIC INLINE void IP_EEPROM_SetAutoProg(IP_EEPROM_002_T *pEEPROM, uint32_t mode)
+{
+ pEEPROM->AUTOPROG = mode;
+}
+
+/**
+ * @brief Set EEPROM Read Wait State value
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param ws : Wait State value.
+ * @return Nothing
+ */
+STATIC INLINE void IP_EEPROM_SetReadWaitState(IP_EEPROM_002_T *pEEPROM, uint32_t ws)
+{
+ pEEPROM->RWSTATE = ws;
+}
+
+/**
+ * @brief Set EEPROM Wait State value
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param ws : Wait State value.
+ * @return Nothing
+ */
+STATIC INLINE void IP_EEPROM_SetWaitState(IP_EEPROM_002_T *pEEPROM, uint32_t ws)
+{
+ pEEPROM->WSTATE = ws;
+}
+
+/**
+ * @brief Put EEPROM device in power down mode
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @return Nothing
+ */
+STATIC INLINE void IP_EEPROM_EnablePowerDown(IP_EEPROM_002_T *pEEPROM)
+{
+ pEEPROM->PWRDWN = EEPROM_PWRDWN;
+}
+
+/**
+ * @brief Bring EEPROM device out of power down mode
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @return Nothing
+ * @note Any EEPROM operation has to be suspended for 100us while the EEPROM wakes up.
+ */
+STATIC INLINE void IP_EEPROM_DisablePowerDown(IP_EEPROM_002_T *pEEPROM)
+{
+ pEEPROM->PWRDWN = 0;
+}
+
+/**
+ * @brief Enable EEPROM interrupt
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return Nothing
+ */
+STATIC INLINE void IP_EEPROM_EnableInt(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
+{
+ pEEPROM->INTENSET = mask;
+}
+
+/**
+ * @brief Disable EEPROM interrupt
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return Nothing
+ */
+STATIC INLINE void IP_EEPROM_DisableInt(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
+{
+ pEEPROM->INTENCLR = mask;
+}
+
+/**
+ * @brief Get the value of the EEPROM interrupt enable register
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @return Or-ed bits value of EEPROM_INT_*
+ */
+STATIC INLINE uint32_t IP_EEPROM_GetIntEnable(IP_EEPROM_002_T *pEEPROM)
+{
+ return pEEPROM->INTEN;
+}
+
+/**
+ * @brief Get EEPROM interrupt status
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @return Or-ed bits value of EEPROM_INT_*
+ */
+STATIC INLINE uint32_t IP_EEPROM_GetIntStatus(IP_EEPROM_002_T *pEEPROM)
+{
+ return pEEPROM->INTSTAT;
+}
+
+/**
+ * @brief Set EEPROM interrupt status
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return Nothing
+ */
+STATIC INLINE void IP_EEPROM_SetIntStatus(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
+{
+ pEEPROM->INTSTATSET = mask;
+}
+
+/**
+ * @brief Clear EEPROM interrupt status
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param mask : interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return Nothing
+ */
+STATIC INLINE void IP_EEPROM_ClearIntStatus(IP_EEPROM_002_T *pEEPROM, uint32_t mask)
+{
+ pEEPROM->INTSTATCLR = mask;
+}
+
+/**
+ * @brief Initializes EEPROM
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param div : clock divide value (pre-minus 1)
+ * @return Nothing
+ */
+void IP_EEPROM_Init(IP_EEPROM_002_T *pEEPROM, uint32_t div);
+
+/**
+ * @brief De-initializes EEPROM
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @return Nothing
+ */
+STATIC INLINE void IP_EEPROM_DeInit(IP_EEPROM_002_T *pEEPROM)
+{
+ /* Enable EEPROM power down mode */
+ IP_EEPROM_EnablePowerDown(pEEPROM);
+}
+
+/**
+ * @brief Erase/Program an EEPROM page
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @return Nothing
+ */
+void IP_EEPROM_EraseProgramPage(IP_EEPROM_002_T *pEEPROM);
+
+/**
+ * @brief Wait for interrupt occurs
+ * @param pEEPROM : pointer to EEPROM peripheral block
+ * @param mask : expected interrupt
+ * @return Nothing
+ */
+void IP_EEPROM_WaitForIntStatus(IP_EEPROM_002_T *pEEPROM, uint32_t mask);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EEPROM_002_H_ */
--- /dev/null
+/*\r
+ * @brief EMC Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __EMC_001_H_\r
+#define __EMC_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_EMC_001 IP: EMC register block and driver\r
+ * @ingroup IP_Drivers\r
+ * External Memory Controller\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief External Memory Controller (EMC) register block structure\r
+ */\r
+typedef struct { /*!< EMC Structure */\r
+ __IO uint32_t CONTROL; /*!< Controls operation of the memory controller. */\r
+ __I uint32_t STATUS; /*!< Provides EMC status information. */\r
+ __IO uint32_t CONFIG; /*!< Configures operation of the memory controller. */\r
+ __I uint32_t RESERVED0[5];\r
+ __IO uint32_t DYNAMICCONTROL; /*!< Controls dynamic memory operation. */\r
+ __IO uint32_t DYNAMICREFRESH; /*!< Configures dynamic memory refresh operation. */\r
+ __IO uint32_t DYNAMICREADCONFIG; /*!< Configures the dynamic memory read strategy. */\r
+ __I uint32_t RESERVED1;\r
+ __IO uint32_t DYNAMICRP; /*!< Selects the precharge command period. */\r
+ __IO uint32_t DYNAMICRAS; /*!< Selects the active to precharge command period. */\r
+ __IO uint32_t DYNAMICSREX; /*!< Selects the self-refresh exit time. */\r
+ __IO uint32_t DYNAMICAPR; /*!< Selects the last-data-out to active command time. */\r
+ __IO uint32_t DYNAMICDAL; /*!< Selects the data-in to active command time. */\r
+ __IO uint32_t DYNAMICWR; /*!< Selects the write recovery time. */\r
+ __IO uint32_t DYNAMICRC; /*!< Selects the active to active command period. */\r
+ __IO uint32_t DYNAMICRFC; /*!< Selects the auto-refresh period. */\r
+ __IO uint32_t DYNAMICXSR; /*!< Selects the exit self-refresh to active command time. */\r
+ __IO uint32_t DYNAMICRRD; /*!< Selects the active bank A to active bank B latency. */\r
+ __IO uint32_t DYNAMICMRD; /*!< Selects the load mode register to active command time. */\r
+ __I uint32_t RESERVED2[9];\r
+ __IO uint32_t STATICEXTENDEDWAIT; /*!< Selects time for long static memory read and write transfers. */\r
+ __I uint32_t RESERVED3[31];\r
+ __IO uint32_t DYNAMICCONFIG0; /*!< Selects the configuration information for dynamic memory chip select n. */\r
+ __IO uint32_t DYNAMICRASCAS0; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
+ __I uint32_t RESERVED4[6];\r
+ __IO uint32_t DYNAMICCONFIG1; /*!< Selects the configuration information for dynamic memory chip select n. */\r
+ __IO uint32_t DYNAMICRASCAS1; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
+ __I uint32_t RESERVED5[6];\r
+ __IO uint32_t DYNAMICCONFIG2; /*!< Selects the configuration information for dynamic memory chip select n. */\r
+ __IO uint32_t DYNAMICRASCAS2; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
+ __I uint32_t RESERVED6[6];\r
+ __IO uint32_t DYNAMICCONFIG3; /*!< Selects the configuration information for dynamic memory chip select n. */\r
+ __IO uint32_t DYNAMICRASCAS3; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */\r
+ __I uint32_t RESERVED7[38];\r
+ __IO uint32_t STATICCONFIG0; /*!< Selects the memory configuration for static chip select n. */\r
+ __IO uint32_t STATICWAITWEN0; /*!< Selects the delay from chip select n to write enable. */\r
+ __IO uint32_t STATICWAITOEN0; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
+ __IO uint32_t STATICWAITRD0; /*!< Selects the delay from chip select n to a read access. */\r
+ __IO uint32_t STATICWAITPAG0; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
+ __IO uint32_t STATICWAITWR0; /*!< Selects the delay from chip select n to a write access. */\r
+ __IO uint32_t STATICWAITTURN0; /*!< Selects bus turnaround cycles */\r
+ __I uint32_t RESERVED8;\r
+ __IO uint32_t STATICCONFIG1; /*!< Selects the memory configuration for static chip select n. */\r
+ __IO uint32_t STATICWAITWEN1; /*!< Selects the delay from chip select n to write enable. */\r
+ __IO uint32_t STATICWAITOEN1; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
+ __IO uint32_t STATICWAITRD1; /*!< Selects the delay from chip select n to a read access. */\r
+ __IO uint32_t STATICWAITPAG1; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
+ __IO uint32_t STATICWAITWR1; /*!< Selects the delay from chip select n to a write access. */\r
+ __IO uint32_t STATICWAITTURN1; /*!< Selects bus turnaround cycles */\r
+ __I uint32_t RESERVED9;\r
+ __IO uint32_t STATICCONFIG2; /*!< Selects the memory configuration for static chip select n. */\r
+ __IO uint32_t STATICWAITWEN2; /*!< Selects the delay from chip select n to write enable. */\r
+ __IO uint32_t STATICWAITOEN2; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
+ __IO uint32_t STATICWAITRD2; /*!< Selects the delay from chip select n to a read access. */\r
+ __IO uint32_t STATICWAITPAG2; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
+ __IO uint32_t STATICWAITWR2; /*!< Selects the delay from chip select n to a write access. */\r
+ __IO uint32_t STATICWAITTURN2; /*!< Selects bus turnaround cycles */\r
+ __I uint32_t RESERVED10;\r
+ __IO uint32_t STATICCONFIG3; /*!< Selects the memory configuration for static chip select n. */\r
+ __IO uint32_t STATICWAITWEN3; /*!< Selects the delay from chip select n to write enable. */\r
+ __IO uint32_t STATICWAITOEN3; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */\r
+ __IO uint32_t STATICWAITRD3; /*!< Selects the delay from chip select n to a read access. */\r
+ __IO uint32_t STATICWAITPAG3; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */\r
+ __IO uint32_t STATICWAITWR3; /*!< Selects the delay from chip select n to a write access. */\r
+ __IO uint32_t STATICWAITTURN3; /*!< Selects bus turnaround cycles */\r
+} IP_EMC_001_T;\r
+\r
+/**\r
+ * @brief EMC register support bitfields and mask\r
+ */\r
+/* Reserve for extending support to ARM9 or nextgen LPC */\r
+#define EMC_SUPPORT_ONLY_PL172 /*!< Reserve for extending support to ARM9 or nextgen LPC */\r
+\r
+#define EMC_CONFIG_ENDIAN_LITTLE (0) /*!< Value for EMC to operate in Little Endian Mode */\r
+#define EMC_CONFIG_ENDIAN_BIG (1) /*!< Value for EMC to operate in Big Endian Mode */\r
+\r
+#define EMC_CONFIG_BUFFER_ENABLE (1 << 19) /*!< EMC Buffer enable bit in EMC Dynamic Configuration register */\r
+#define EMC_CONFIG_WRITE_PROTECT (1 << 20) /*!< EMC Write protect bit in EMC Dynamic Configuration register */\r
+\r
+/* Dynamic Memory Configuration Register Bit Definitions */\r
+#define EMC_DYN_CONFIG_MD_BIT (3) /*!< Memory device bit in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_MD_SDRAM (0 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as SDRAM in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_MD_LPSDRAM (1 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as LPSDRAM in EMC Dynamic Configuration register */\r
+\r
+#define EMC_DYN_CONFIG_LPSDRAM_BIT (12) /*!< LPSDRAM bit in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_LPSDRAM (1 << EMC_DYN_CONFIG_LPSDRAM_BIT) /*!< LPSDRAM value in EMC Dynamic Configuration register */\r
+\r
+#define EMC_DYN_CONFIG_DEV_SIZE_BIT (9) /*!< Device Size starting bit in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 16Mb Device Size value in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 64Mb Device Size value in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 128Mb Device Size value in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 256Mb Device Size value in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 512Mb Device Size value in EMC Dynamic Configuration register */\r
+\r
+#define EMC_DYN_CONFIG_DEV_BUS_BIT (7) /*!< Device bus width starting bit in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DEV_BUS_8 (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 8-bit bus width value in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DEV_BUS_16 (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 16-bit bus width value in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DEV_BUS_32 (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */\r
+\r
+#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT (14) /*!< Device data bus width starting bit in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DATA_BUS_16 (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 16-bit data bus width value in EMC Dynamic Configuration register */\r
+#define EMC_DYN_CONFIG_DATA_BUS_32 (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */\r
+\r
+/*!< Memory configuration values in EMC Dynamic Configuration Register */\r
+#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns */\r
+#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns */\r
+#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns */\r
+#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns */\r
+#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns */\r
+#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns */\r
+#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns */\r
+#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns */\r
+#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns */\r
+#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns */\r
+#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns */\r
+#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS ((0x4 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns */\r
+#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns */\r
+\r
+/*!< Dynamic Memory Mode Register Bit Definition */\r
+#define EMC_DYN_MODE_BURST_LEN_BIT (0) /*!< Starting bit No. of Burst Length in Dynamic Memory Mode Register */\r
+#define EMC_DYN_MODE_BURST_LEN_1 (0) /*!< Value to set Burst Length to 1 in Dynamic Memory Mode Register */\r
+#define EMC_DYN_MODE_BURST_LEN_2 (1) /*!< Value to set Burst Length to 2 in Dynamic Memory Mode Register */\r
+#define EMC_DYN_MODE_BURST_LEN_4 (2) /*!< Value to set Burst Length to 4 in Dynamic Memory Mode Register */\r
+#define EMC_DYN_MODE_BURST_LEN_8 (3) /*!< Value to set Burst Length to 8 in Dynamic Memory Mode Register */\r
+#define EMC_DYN_MODE_BURST_LEN_FULL (7) /*!< Value to set Burst Length to Full in Dynamic Memory Mode Register */\r
+\r
+#define EMC_DYN_MODE_BURST_TYPE_BIT (3) /*!< Burst Type bit in Dynamic Memory Mode Register */\r
+#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Sequential in Dynamic Memory Mode Register */\r
+#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE (1 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Interleaved in Dynamic Memory Mode Register */\r
+\r
+/*!< CAS Latency in Dynamic Mode Register */\r
+#define EMC_DYN_MODE_CAS_BIT (4) /*!< CAS latency starting bit in Dynamic Memory Mode register */\r
+#define EMC_DYN_MODE_CAS_1 (1 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 1 cycle */\r
+#define EMC_DYN_MODE_CAS_2 (2 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 2 cycle */\r
+#define EMC_DYN_MODE_CAS_3 (3 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 3 cycle */\r
+\r
+/*!< Operation Mode in Dynamic Mode register */\r
+#define EMC_DYN_MODE_OPMODE_BIT (7) /*!< Dynamic Mode Operation bit */\r
+#define EMC_DYN_MODE_OPMODE_STANDARD (0 << EMC_DYN_MODE_OPMODE_BIT) /*!< Value for Dynamic standard operation Mode */\r
+\r
+/*!< Write Burst Mode in Dynamic Mode register */\r
+#define EMC_DYN_MODE_WBMODE_BIT (9) /*!< Write Burst Mode bit */\r
+#define EMC_DYN_MODE_WBMODE_PROGRAMMED (0 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode programmed */\r
+#define EMC_DYN_MODE_WBMODE_SINGLE_LOC (1 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode Single LOC */\r
+\r
+/*!< Dynamic Memory Control Register Bit Definitions */\r
+#define EMC_DYN_CONTROL_ENABLE (0x03) /*!< Control Enable value */\r
+\r
+/*!< Static Memory Configuration Register Bit Definitions */\r
+#define EMC_STATIC_CONFIG_MEM_WIDTH_8 (0) /*!< Static Memory Configuration - 8-bit width */\r
+#define EMC_STATIC_CONFIG_MEM_WIDTH_16 (1) /*!< Static Memory Configuration - 16-bit width */\r
+#define EMC_STATIC_CONFIG_MEM_WIDTH_32 (2) /*!< Static Memory Configuration - 32-bit width */\r
+\r
+#define EMC_STATIC_CONFIG_PAGE_MODE_BIT (3) /*!< Page Mode bit No */\r
+#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT) /*!< Value to enable Page Mode */\r
+\r
+#define EMC_STATIC_CONFIG_CS_POL_BIT (6) /*!< Chip Select bit No */\r
+#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH (1 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active High */\r
+#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW (0 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active Low */\r
+\r
+#define EMC_STATIC_CONFIG_BLS_BIT (7) /*!< BLS Configuration bit No */\r
+#define EMC_STATIC_CONFIG_BLS_HIGH (1 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS High Configuration value */\r
+#define EMC_STATIC_CONFIG_BLS_LOW (0 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS Low Configuration value */\r
+\r
+#define EMC_STATIC_CONFIG_EW_BIT (8) /*!< Ext Wait bit No */\r
+#define EMC_STATIC_CONFIG_EW_ENABLE (1 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Enabled value */\r
+#define EMC_STATIC_CONFIG_EW_DISABLE (0 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Diabled value */\r
+\r
+/*!< Q24.8 Fixed Point Helper */\r
+#define Q24_8_FP(x) ((x) * 256)\r
+#define EMC_NANOSECOND(x) Q24_8_FP(x)\r
+#define EMC_CLOCK(x) Q24_8_FP(-(x))\r
+\r
+/**\r
+ * @brief EMC Dynamic Device Configuration structure used for IP drivers\r
+ */\r
+typedef struct {\r
+ uint32_t BaseAddr; /*!< Base Address */\r
+ uint8_t RAS; /*!< RAS value */\r
+ uint32_t ModeRegister; /*!< Mode Register value */\r
+ uint32_t DynConfig; /*!< Dynamic Configuration value */\r
+} IP_EMC_DYN_DEVICE_CONFIG_T;\r
+\r
+/**\r
+ * @brief EMC Dynamic Configure Struct\r
+ */\r
+typedef struct {\r
+ int32_t RefreshPeriod; /*!< Refresh period */\r
+ uint32_t ReadConfig; /*!< Clock*/\r
+ int32_t tRP; /*!< Precharge Command Period */\r
+ int32_t tRAS; /*!< Active to Precharge Command Period */\r
+ int32_t tSREX; /*!< Self Refresh Exit Time */\r
+ int32_t tAPR; /*!< Last Data Out to Active Time */\r
+ int32_t tDAL; /*!< Data In to Active Command Time */\r
+ int32_t tWR; /*!< Write Recovery Time */\r
+ int32_t tRC; /*!< Active to Active Command Period */\r
+ int32_t tRFC; /*!< Auto-refresh Period */\r
+ int32_t tXSR; /*!< Exit Selt Refresh */\r
+ int32_t tRRD; /*!< Active Bank A to Active Bank B Time */\r
+ int32_t tMRD; /*!< Load Mode register command to Active Command */\r
+ IP_EMC_DYN_DEVICE_CONFIG_T DevConfig[4]; /*!< Device Configuration array */\r
+} IP_EMC_DYN_CONFIG_T;\r
+\r
+/**\r
+ * @brief EMC Static Configure Structure\r
+ */\r
+typedef struct {\r
+ uint8_t ChipSelect; /*!< Chip select */\r
+ uint32_t Config; /*!< Configuration value */\r
+ int32_t WaitWen; /*!< Write Enable Wait */\r
+ int32_t WaitOen; /*!< Output Enable Wait */\r
+ int32_t WaitRd; /*!< Read Wait */\r
+ int32_t WaitPage; /*!< Page Access Wait */\r
+ int32_t WaitWr; /*!< Write Wait */\r
+ int32_t WaitTurn; /*!< Turn around wait */\r
+} IP_EMC_STATIC_CONFIG_T;\r
+\r
+/**\r
+ * @brief Initializes the Dynamic Controller\r
+ * @param pEMC : Pointer to EMC peripheral\r
+ * @param Dynamic_Config : Dynamic Memory Configure Struct\r
+ * @param EMC_Clock : Frequency of EMC Clock Out\r
+ * @return None\r
+ * @note Initializes the Dynamic Controller according to the specified parameters\r
+ * in the IP_EMC_DYN_CONFIG_T\r
+ */\r
+void IP_EMC_Dynamic_Init(IP_EMC_001_T *pEMC, IP_EMC_DYN_CONFIG_T *Dynamic_Config, uint32_t EMC_Clock);\r
+\r
+/**\r
+ * @brief Enable Dynamic Memory Controller\r
+ * @param pEMC : Pointer to EMC peripheral\r
+ * @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable\r
+ * @return None\r
+ */\r
+void IP_EMC_Dynamic_Enable(IP_EMC_001_T *pEMC, uint8_t Enable);\r
+\r
+/**\r
+ * @brief Initializes the Static Controller according to the specified\r
+ * parameters in the IP_EMC_STATIC_CONFIG_T\r
+ * @param pEMC : Pointer to EMC peripheral\r
+ * @param Static_Config : Static Memory Configure Struct\r
+ * @param EMC_Clock : Frequency of EMC Clock Out\r
+ * @return None\r
+ */\r
+void IP_EMC_Static_Init(IP_EMC_001_T *pEMC, IP_EMC_STATIC_CONFIG_T *Static_Config, uint32_t EMC_Clock);\r
+\r
+/**\r
+ * @brief Mirror CS1 to CS0 and DYCS0\r
+ * @param pEMC : Pointer to EMC peripheral\r
+ * @param Enable : 1 = Mirror, 0 = Normal Memory Map\r
+ * @return None\r
+ */\r
+void IP_EMC_Mirror(IP_EMC_001_T *pEMC, uint32_t Enable);\r
+\r
+/**\r
+ * @brief Enable EMC\r
+ * @param pEMC : Pointer to EMC peripheral\r
+ * @param Enable : 1 = Enable, 0 = Disable\r
+ * @return None\r
+ */\r
+void IP_EMC_Enable(IP_EMC_001_T *pEMC, uint32_t Enable);\r
+\r
+/**\r
+ * @brief Set EMC LowPower Mode\r
+ * @param pEMC : Pointer to EMC peripheral\r
+ * @param Enable : 1 = Enable, 0 = Disable\r
+ * @return None\r
+ * @note This function should only be called when the memory\r
+ * controller is not busy (bit 0 of the status register is not set).\r
+ */\r
+void IP_EMC_LowPowerMode(IP_EMC_001_T *pEMC, uint32_t Enable);\r
+\r
+/**\r
+ * @brief Initialize EMC\r
+ * @param pEMC : Pointer to EMC peripheral\r
+ * @param Enable : 1 = Enable, 0 = Disable\r
+ * @param ClockRatio : clock out ratio, 0 = 1:1, 1 = 1:2\r
+ * @param EndianMode : Endian Mode, 0 = Little, 1 = Big\r
+ * @return None\r
+ */\r
+void IP_EMC_Init(IP_EMC_001_T *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);\r
+\r
+/**\r
+ * @brief Set Static Memory Extended Wait in Clock\r
+ * @param pEMC : Pointer to EMC peripheral\r
+ * @param Wait16Clks : Number of '16 clock' delay cycles\r
+ * @return None\r
+ */\r
+void IP_EMC_SetStaticExtendedWait(IP_EMC_001_T *pEMC, uint32_t Wait16Clks);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __EMC_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Ethernet control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __ENET_001_H_\r
+#define __ENET_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_ENET_001 IP: Ethernet register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief 10/100 MII & RMII Ethernet with timestamping register block structure\r
+ */\r
+typedef struct { /*!< ETHERNET Structure */\r
+ __IO uint32_t MAC_CONFIG; /*!< MAC configuration register */\r
+ __IO uint32_t MAC_FRAME_FILTER; /*!< MAC frame filter */\r
+ __IO uint32_t MAC_HASHTABLE_HIGH; /*!< Hash table high register */\r
+ __IO uint32_t MAC_HASHTABLE_LOW; /*!< Hash table low register */\r
+ __IO uint32_t MAC_MII_ADDR; /*!< MII address register */\r
+ __IO uint32_t MAC_MII_DATA; /*!< MII data register */\r
+ __IO uint32_t MAC_FLOW_CTRL; /*!< Flow control register */\r
+ __IO uint32_t MAC_VLAN_TAG; /*!< VLAN tag register */\r
+ __I uint32_t RESERVED0;\r
+ __I uint32_t MAC_DEBUG; /*!< Debug register */\r
+ __IO uint32_t MAC_RWAKE_FRFLT; /*!< Remote wake-up frame filter */\r
+ __IO uint32_t MAC_PMT_CTRL_STAT; /*!< PMT control and status */\r
+ __I uint32_t RESERVED1[2];\r
+ __I uint32_t MAC_INTR; /*!< Interrupt status register */\r
+ __IO uint32_t MAC_INTR_MASK; /*!< Interrupt mask register */\r
+ __IO uint32_t MAC_ADDR0_HIGH; /*!< MAC address 0 high register */\r
+ __IO uint32_t MAC_ADDR0_LOW; /*!< MAC address 0 low register */\r
+ __I uint32_t RESERVED2[430];\r
+ __IO uint32_t MAC_TIMESTP_CTRL; /*!< Time stamp control register */\r
+ __IO uint32_t SUBSECOND_INCR; /*!< Sub-second increment register */\r
+ __I uint32_t SECONDS; /*!< System time seconds register */\r
+ __I uint32_t NANOSECONDS; /*!< System time nanoseconds register */\r
+ __IO uint32_t SECONDSUPDATE; /*!< System time seconds update register */\r
+ __IO uint32_t NANOSECONDSUPDATE; /*!< System time nanoseconds update register */\r
+ __IO uint32_t ADDEND; /*!< Time stamp addend register */\r
+ __IO uint32_t TARGETSECONDS; /*!< Target time seconds register */\r
+ __IO uint32_t TARGETNANOSECONDS; /*!< Target time nanoseconds register */\r
+ __IO uint32_t HIGHWORD; /*!< System time higher word seconds register */\r
+ __I uint32_t TIMESTAMPSTAT; /*!< Time stamp status register */\r
+ __IO uint32_t PPSCTRL; /*!< PPS control register */\r
+ __I uint32_t AUXNANOSECONDS; /*!< Auxiliary time stamp nanoseconds register */\r
+ __I uint32_t AUXSECONDS; /*!< Auxiliary time stamp seconds register */\r
+ __I uint32_t RESERVED3[562];\r
+ __IO uint32_t DMA_BUS_MODE; /*!< Bus Mode Register */\r
+ __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< Transmit poll demand register */\r
+ __IO uint32_t DMA_REC_POLL_DEMAND; /*!< Receive poll demand register */\r
+ __IO uint32_t DMA_REC_DES_ADDR; /*!< Receive descriptor list address register */\r
+ __IO uint32_t DMA_TRANS_DES_ADDR; /*!< Transmit descriptor list address register */\r
+ __IO uint32_t DMA_STAT; /*!< Status register */\r
+ __IO uint32_t DMA_OP_MODE; /*!< Operation mode register */\r
+ __IO uint32_t DMA_INT_EN; /*!< Interrupt enable register */\r
+ __I uint32_t DMA_MFRM_BUFOF; /*!< Missed frame and buffer overflow register */\r
+ __IO uint32_t DMA_REC_INT_WDT; /*!< Receive interrupt watchdog timer register */\r
+ __I uint32_t RESERVED4[8];\r
+ __I uint32_t DMA_CURHOST_TRANS_DES; /*!< Current host transmit descriptor register */\r
+ __I uint32_t DMA_CURHOST_REC_DES; /*!< Current host receive descriptor register */\r
+ __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< Current host transmit buffer address register */\r
+ __I uint32_t DMA_CURHOST_REC_BUF; /*!< Current host receive buffer address register */\r
+} IP_ENET_001_T;\r
+\r
+/**\r
+ * @brief MAC_CONFIG register bit defines\r
+ */\r
+#define MAC_CFG_RE (1 << 2) /*!< Receiver enable */\r
+#define MAC_CFG_TE (1 << 3) /*!< Transmitter Enable */\r
+#define MAC_CFG_DF (1 << 4) /*!< Deferral Check */\r
+#define MAC_CFG_BL(n) ((n) << 5) /*!< Back-Off Limit */\r
+#define MAC_CFG_ACS (1 << 7) /*!< Automatic Pad/CRC Stripping */\r
+#define MAC_CFG_LUD (1 << 8) /*!< Link Up/Down, 1 = up */\r
+#define MAC_CFG_DR (1 << 9) /*!< Disable Retry */\r
+#define MAC_CFG_IPC (1 << 10) /*!< Checksum Offload */\r
+#define MAC_CFG_DM (1 << 11) /*!< Duplex Mode, 1 = full, 0 = half */\r
+#define MAC_CFG_LM (1 << 12) /*!< Loopback Mode */\r
+#define MAC_CFG_DO (1 << 13) /*!< Disable Receive Own */\r
+#define MAC_CFG_FES (1 << 14) /*!< Speed, 1 = 100Mbps, 0 = 10Mbos */\r
+#define MAC_CFG_PS (1 << 15) /*!< Port select, must always be 1 */\r
+#define MAC_CFG_DCRS (1 << 16) /*!< Disable carrier sense during transmission */\r
+#define MAC_CFG_IFG(n) ((n) << 17) /*!< Inter-frame gap, 40..96, n incs by 8 */\r
+#define MAC_CFG_JE (1 << 20) /*!< Jumbo Frame Enable */\r
+#define MAC_CFG_JD (1 << 22) /*!< Jabber Disable */\r
+#define MAC_CFG_WD (1 << 23) /*!< Watchdog Disable */\r
+\r
+/**\r
+ * @brief MAC_FRAME_FILTER register bit defines\r
+ */\r
+#define MAC_FF_PR (1 << 0) /*!< Promiscuous Mode */\r
+#define MAC_FF_DAIF (1 << 3) /*!< DA Inverse Filtering */\r
+#define MAC_FF_PM (1 << 4) /*!< Pass All Multicast */\r
+#define MAC_FF_DBF (1 << 5) /*!< Disable Broadcast Frames */\r
+#define MAC_FF_PCF(n) ((n) << 6) /*!< Pass Control Frames, n = see user manual */\r
+#define MAC_FF_SAIF (1 << 8) /*!< SA Inverse Filtering */\r
+#define MAC_FF_SAF (1 << 9) /*!< Source Address Filter Enable */\r
+#define MAC_FF_RA (1UL << 31) /*!< Receive all */\r
+\r
+/**\r
+ * @brief MAC_MII_ADDR register bit defines\r
+ */\r
+#define MAC_MIIA_GB (1 << 0) /*!< MII busy */\r
+#define MAC_MIIA_W (1 << 1) /*!< MII write */\r
+#define MAC_MIIA_CR(n) ((n) << 2) /*!< CSR clock range, n = see manual */\r
+#define MAC_MIIA_GR(n) ((n) << 6) /*!< MII register. n = 0..31 */\r
+#define MAC_MIIA_PA(n) ((n) << 11) /*!< Physical layer address, n = 0..31 */\r
+\r
+/**\r
+ * @brief MAC_MII_DATA register bit defines\r
+ */\r
+#define MAC_MIID_GDMSK (0xFFFF) /*!< MII data mask */\r
+\r
+/**\r
+ * @brief MAC_FLOW_CONTROL register bit defines\r
+ */\r
+#define MAC_FC_FCB (1 << 0) /*!< Flow Control Busy/Backpressure Activate */\r
+#define MAC_FC_TFE (1 << 1) /*!< Transmit Flow Control Enable */\r
+#define MAC_FC_RFE (1 << 2) /*!< Receive Flow Control Enable */\r
+#define MAC_FC_UP (1 << 3) /*!< Unicast Pause Frame Detect */\r
+#define MAC_FC_PLT(n) ((n) << 4) /*!< Pause Low Threshold, n = see manual */\r
+#define MAC_FC_DZPQ (1 << 7) /*!< Disable Zero-Quanta Pause */\r
+#define MAC_FC_PT(n) ((n) << 16) /*!< Pause time */\r
+\r
+/**\r
+ * @brief MAC_VLAN_TAG register bit defines\r
+ */\r
+#define MAC_VT_VL(n) ((n) << 0) /*!< VLAN Tag Identifier for Receive Frames */\r
+#define MAC_VT_ETC (1 << 7) /*!< Enable 12-Bit VLAN Tag Comparison */\r
+\r
+/**\r
+ * @brief MAC_PMT_CTRL_STAT register bit defines\r
+ */\r
+#define MAC_PMT_PD (1 << 0) /*!< Power-down */\r
+#define MAC_PMT_MPE (1 << 1) /*!< Magic packet enable */\r
+#define MAC_PMT_WFE (1 << 2) /*!< Wake-up frame enable */\r
+#define MAC_PMT_MPR (1 << 5) /*!< Magic Packet Received */\r
+#define MAC_PMT_WFR (1 << 6) /*!< Wake-up Frame Received */\r
+#define MAC_PMT_GU (1 << 9) /*!< Global Unicast */\r
+#define MAC_PMT_WFFRPR (1UL << 31) /*!< Wake-up Frame Filter Register Pointer Reset */\r
+\r
+/**\r
+ * @brief MAC_INTR_MASK register bit defines\r
+ */\r
+#define MAC_IM_PMT (1 << 3) /*!< PMT Interrupt Mask */\r
+\r
+/**\r
+ * @brief MAC_ADDR0_HIGH register bit defines\r
+ */\r
+#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */\r
+\r
+/**\r
+ * @brief MAC_ADDR0_HIGH register bit defines\r
+ */\r
+#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */\r
+\r
+/**\r
+ * @brief MAC_TIMESTAMP register bit defines\r
+ */\r
+#define MAC_TS_TSENA (1 << 0) /*!< Time Stamp Enable */\r
+#define MAC_TS_TSCFUP (1 << 1) /*!< Time Stamp Fine or Coarse Update */\r
+#define MAC_TS_TSINIT (1 << 2) /*!< Time Stamp Initialize */\r
+#define MAC_TS_TSUPDT (1 << 3) /*!< Time Stamp Update */\r
+#define MAC_TS_TSTRIG (1 << 4) /*!< Time Stamp Interrupt Trigger Enable */\r
+#define MAC_TS_TSADDR (1 << 5) /*!< Addend Reg Update */\r
+#define MAC_TS_TSENAL (1 << 8) /*!< Enable Time Stamp for All Frames */\r
+#define MAC_TS_TSCTRL (1 << 9) /*!< Time Stamp Digital or Binary rollover control */\r
+#define MAC_TS_TSVER2 (1 << 10) /*!< Enable PTP packet snooping for version 2 format */\r
+#define MAC_TS_TSIPENA (1 << 11) /*!< Enable Time Stamp Snapshot for PTP over Ethernet frames */\r
+#define MAC_TS_TSIPV6E (1 << 12) /*!< Enable Time Stamp Snapshot for IPv6 frames */\r
+#define MAC_TS_TSIPV4E (1 << 13) /*!< Enable Time Stamp Snapshot for IPv4 frames */\r
+#define MAC_TS_TSEVNT (1 << 14) /*!< Enable Time Stamp Snapshot for Event Messages */\r
+#define MAC_TS_TSMSTR (1 << 15) /*!< Enable Snapshot for Messages Relevant to Master */\r
+#define MAC_TS_TSCLKT(n) ((n) << 16) /*!< Select the type of clock node, n = see menual */\r
+#define MAC_TS_TSENMA (1 << 18) /*!< Enable MAC address for PTP frame filtering */\r
+\r
+/**\r
+ * @brief DMA_BUS_MODE register bit defines\r
+ */\r
+#define DMA_BM_SWR (1 << 0) /*!< Software reset */\r
+#define DMA_BM_DA (1 << 1) /*!< DMA arbitration scheme, 1 = TX has priority over TX */\r
+#define DMA_BM_DSL(n) ((n) << 2) /*!< Descriptor skip length, n = see manual */\r
+#define DMA_BM_ATDS (1 << 7) /*!< Alternate (Enhanced) descriptor size */\r
+#define DMA_BM_PBL(n) ((n) << 8) /*!< Programmable burst length, n = see manual */\r
+#define DMA_BM_PR(n) ((n) << 14) /*!< Rx-to-Tx priority ratio, n = see manual */\r
+#define DMA_BM_FB (1 << 16) /*!< Fixed burst */\r
+#define DMA_BM_RPBL(n) ((n) << 17) /*!< RxDMA PBL, n = see manual */\r
+#define DMA_BM_USP (1 << 23) /*!< Use separate PBL */\r
+#define DMA_BM_PBL8X (1 << 24) /*!< 8 x PBL mode */\r
+#define DMA_BM_AAL (1 << 25) /*!< Address-aligned beats */\r
+#define DMA_BM_MB (1 << 26) /*!< Mixed burst */\r
+#define DMA_BM_TXPR (1 << 27) /*!< Transmit DMA has higher priority than receive DMA */\r
+\r
+/**\r
+ * @brief DMA_STAT register bit defines\r
+ */\r
+#define DMA_ST_TI (1 << 0) /*!< Transmit interrupt */\r
+#define DMA_ST_TPS (1 << 1) /*!< Transmit process stopped */\r
+#define DMA_ST_TU (1 << 2) /*!< Transmit buffer unavailable */\r
+#define DMA_ST_TJT (1 << 3) /*!< Transmit jabber timeout */\r
+#define DMA_ST_OVF (1 << 4) /*!< Receive overflow */\r
+#define DMA_ST_UNF (1 << 5) /*!< Transmit underflow */\r
+#define DMA_ST_RI (1 << 6) /*!< Receive interrupt */\r
+#define DMA_ST_RU (1 << 7) /*!< Receive buffer unavailable */\r
+#define DMA_ST_RPS (1 << 8) /*!< Received process stopped */\r
+#define DMA_ST_RWT (1 << 9) /*!< Receive watchdog timeout */\r
+#define DMA_ST_ETI (1 << 10) /*!< Early transmit interrupt */\r
+#define DMA_ST_FBI (1 << 13) /*!< Fatal bus error interrupt */\r
+#define DMA_ST_ERI (1 << 14) /*!< Early receive interrupt */\r
+#define DMA_ST_AIE (1 << 15) /*!< Abnormal interrupt summary */\r
+#define DMA_ST_NIS (1 << 16) /*!< Normal interrupt summary */\r
+#define DMA_ST_ALL (0x1E7FF) /*!< All interrupts */\r
+\r
+/**\r
+ * @brief DMA_OP_MODE register bit defines\r
+ */\r
+#define DMA_OM_SR (1 << 1) /*!< Start/stop receive */\r
+#define DMA_OM_OSF (1 << 2) /*!< Operate on second frame */\r
+#define DMA_OM_RTC(n) ((n) << 3) /*!< Receive threshold control, n = see manual */\r
+#define DMA_OM_FUF (1 << 6) /*!< Forward undersized good frames */\r
+#define DMA_OM_FEF (1 << 7) /*!< Forward error frames */\r
+#define DMA_OM_ST (1 << 13) /*!< Start/Stop Transmission Command */\r
+#define DMA_OM_TTC(n) ((n) << 14) /*!< Transmit threshold control, n = see manual */\r
+#define DMA_OM_FTF (1 << 20) /*!< Flush transmit FIFO */\r
+#define DMA_OM_TSF (1 << 21) /*!< Transmit store and forward */\r
+#define DMA_OM_DFF (1 << 24) /*!< Disable flushing of received frames */\r
+#define DMA_OM_RSF (1 << 25) /*!< Receive store and forward */\r
+#define DMA_OM_DT (1 << 26) /*!< Disable Dropping of TCP/IP Checksum Error Frames */\r
+\r
+/**\r
+ * @brief DMA_INT_EN register bit defines\r
+ */\r
+#define DMA_IE_TIE (1 << 0) /*!< Transmit interrupt enable */\r
+#define DMA_IE_TSE (1 << 1) /*!< Transmit stopped enable */\r
+#define DMA_IE_TUE (1 << 2) /*!< Transmit buffer unavailable enable */\r
+#define DMA_IE_TJE (1 << 3) /*!< Transmit jabber timeout enable */\r
+#define DMA_IE_OVE (1 << 4) /*!< Overflow interrupt enable */\r
+#define DMA_IE_UNE (1 << 5) /*!< Underflow interrupt enable */\r
+#define DMA_IE_RIE (1 << 6) /*!< Receive interrupt enable */\r
+#define DMA_IE_RUE (1 << 7) /*!< Receive buffer unavailable enable */\r
+#define DMA_IE_RSE (1 << 8) /*!< Received stopped enable */\r
+#define DMA_IE_RWE (1 << 9) /*!< Receive watchdog timeout enable */\r
+#define DMA_IE_ETE (1 << 10) /*!< Early transmit interrupt enable */\r
+#define DMA_IE_FBE (1 << 13) /*!< Fatal bus error enable */\r
+#define DMA_IE_ERE (1 << 14) /*!< Early receive interrupt enable */\r
+#define DMA_IE_AIE (1 << 15) /*!< Abnormal interrupt summary enable */\r
+#define DMA_IE_NIE (1 << 16) /*!< Normal interrupt summary enable */\r
+\r
+/**\r
+ * @brief DMA_MFRM_BUFOF register bit defines\r
+ */\r
+#define DMA_MFRM_FMCMSK (0xFFFF) /*!< Number of frames missed mask */\r
+#define DMA_MFRM_OC (1 << 16) /*!< Overflow bit for missed frame counter */\r
+#define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17) /*!< Number of frames missed by the application mask/shift */\r
+#define DMA_MFRM_OF (1 << 28) /*!< Overflow bit for FIFO overflow counter */\r
+\r
+/**\r
+ * @brief Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines\r
+ */\r
+#define TDES_DB (1 << 0) /*!< Deferred Bit */\r
+#define TDES_UF (1 << 1) /*!< Underflow Error */\r
+#define TDES_ED (1 << 2) /*!< Excessive Deferral */\r
+#define TDES_CCMSK(n) (((n) & 0x000000F0) >> 3)/*!< CC: Collision Count (Status field) mask and shift */\r
+#define TDES_VF (1 << 7) /*!< VLAN Frame */\r
+#define TDES_EC (1 << 8) /*!< Excessive Collision */\r
+#define TDES_LC (1 << 9) /*!< Late Collision */\r
+#define TDES_NC (1 << 10) /*!< No Carrier */\r
+#define TDES_LCAR (1 << 11) /*!< Loss of Carrier */\r
+#define TDES_IPE (1 << 12) /*!< IP Payload Error */\r
+#define TDES_FF (1 << 13) /*!< Frame Flushed */\r
+#define TDES_JT (1 << 14) /*!< Jabber Timeout */\r
+#define TDES_ES (1 << 15) /*!< Error Summary */\r
+#define TDES_IHE (1 << 16) /*!< IP Header Error */\r
+#define TDES_TTSS (1 << 17) /*!< Transmit Timestamp Status */\r
+#define TDES_OWN (1UL << 31) /*!< Own Bit */\r
+\r
+/**\r
+ * @brief TRAN_DESC_ENH_T only CTRLSTAT field bit defines\r
+ */\r
+#define TDES_ENH_IC (1UL << 30) /*!< Interrupt on Completion, enhanced descriptor */\r
+#define TDES_ENH_LS (1 << 29) /*!< Last Segment, enhanced descriptor */\r
+#define TDES_ENH_FS (1 << 28) /*!< First Segment, enhanced descriptor */\r
+#define TDES_ENH_DC (1 << 27) /*!< Disable CRC, enhanced descriptor */\r
+#define TDES_ENH_DP (1 << 26) /*!< Disable Pad, enhanced descriptor */\r
+#define TDES_ENH_TTSE (1 << 25) /*!< Transmit Timestamp Enable, enhanced descriptor */\r
+#define TDES_ENH_CIC(n) ((n) << 22) /*!< Checksum Insertion Control, enhanced descriptor */\r
+#define TDES_ENH_TER (1 << 21) /*!< Transmit End of Ring, enhanced descriptor */\r
+#define TDES_ENH_TCH (1 << 20) /*!< Second Address Chained, enhanced descriptor */\r
+\r
+/**\r
+ * @brief TRAN_DESC_T only BSIZE field bit defines\r
+ */\r
+#define TDES_NORM_IC (1UL << 31) /*!< Interrupt on Completion, normal descriptor */\r
+#define TDES_NORM_FS (1 << 30) /*!< First Segment, normal descriptor */\r
+#define TDES_NORM_LS (1 << 29) /*!< Last Segment, normal descriptor */\r
+#define TDES_NORM_CIC(n) ((n) << 27) /*!< Checksum Insertion Control, normal descriptor */\r
+#define TDES_NORM_DC (1 << 26) /*!< Disable CRC, normal descriptor */\r
+#define TDES_NORM_TER (1 << 25) /*!< Transmit End of Ring, normal descriptor */\r
+#define TDES_NORM_TCH (1 << 24) /*!< Second Address Chained, normal descriptor */\r
+#define TDES_NORM_DP (1 << 23) /*!< Disable Pad, normal descriptor */\r
+#define TDES_NORM_TTSE (1 << 22) /*!< Transmit Timestamp Enable, normal descriptor */\r
+#define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */\r
+#define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */\r
+\r
+/**\r
+ * @brief TRAN_DESC_ENH_T only BSIZE field bit defines\r
+ */\r
+#define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */\r
+#define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */\r
+\r
+/**\r
+ * @brief Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines\r
+ */\r
+#define RDES_ESA (1 << 0) /*!< Extended Status Available/Rx MAC Address */\r
+#define RDES_CE (1 << 1) /*!< CRC Error */\r
+#define RDES_DRE (1 << 2) /*!< Dribble Bit Error */\r
+#define RDES_RE (1 << 3) /*!< Receive Error */\r
+#define RDES_RWT (1 << 4) /*!< Receive Watchdog Timeout */\r
+#define RDES_FT (1 << 5) /*!< Frame Type */\r
+#define RDES_LC (1 << 6) /*!< Late Collision */\r
+#define RDES_TSA (1 << 7) /*!< Timestamp Available/IP Checksum Error (Type1) /Giant Frame */\r
+#define RDES_LS (1 << 8) /*!< Last Descriptor */\r
+#define RDES_FS (1 << 9) /*!< First Descriptor */\r
+#define RDES_VLAN (1 << 10) /*!< VLAN Tag */\r
+#define RDES_OE (1 << 11) /*!< Overflow Error */\r
+#define RDES_LE (1 << 12) /*!< Length Error */\r
+#define RDES_SAF (1 << 13) /*!< Source Address Filter Fail */\r
+#define RDES_DE (1 << 14) /*!< Descriptor Error */\r
+#define RDES_ES (1 << 15) /*!< ES: Error Summary */\r
+#define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)/*!< Frame Length mask and shift */\r
+#define RDES_AFM (1 << 30) /*!< Destination Address Filter Fail */\r
+#define RDES_OWN (1UL << 31) /*!< Own Bit */\r
+\r
+/**\r
+ * @brief Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines\r
+ */\r
+#define RDES_DINT (1UL << 31) /*!< Disable interrupt on completion */\r
+\r
+/**\r
+ * @brief REC_DESC_T pnly CTRL field bit defines\r
+ */\r
+#define RDES_NORM_RER (1 << 25) /*!< Receive End of Ring, normal descriptor */\r
+#define RDES_NORM_RCH (1 << 24) /*!< Second Address Chained, normal descriptor */\r
+#define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */\r
+#define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */\r
+\r
+/**\r
+ * @brief REC_DESC_ENH_T only CTRL field bit defines\r
+ */\r
+#define RDES_ENH_RER (1 << 15) /*!< Receive End of Ring, enhanced descriptor */\r
+#define RDES_ENH_RCH (1 << 14) /*!< Second Address Chained, enhanced descriptor */\r
+#define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */\r
+#define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */\r
+\r
+/**\r
+ * @brief REC_DESC_ENH_T only EXTSTAT field bit defines\r
+ */\r
+#define RDES_ENH_IPPL(n) (((n) & 0x7) >> 2) /*!< IP Payload Type mask and shift, enhanced descripto */\r
+#define RDES_ENH_IPHE (1 << 3) /*!< IP Header Error, enhanced descripto */\r
+#define RDES_ENH_IPPLE (1 << 4) /*!< IP Payload Error, enhanced descripto */\r
+#define RDES_ENH_IPCSB (1 << 5) /*!< IP Checksum Bypassed, enhanced descripto */\r
+#define RDES_ENH_IPV4 (1 << 6) /*!< IPv4 Packet Received, enhanced descripto */\r
+#define RDES_ENH_IPV6 (1 << 7) /*!< IPv6 Packet Received, enhanced descripto */\r
+#define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8) /*!< Message Type mask and shift, enhanced descripto */\r
+\r
+/**\r
+ * @brief Maximum size of an ethernet buffer\r
+ */\r
+#define EMAC_ETH_MAX_FLEN (1536)\r
+\r
+/**\r
+ * @brief Structure of a transmit descriptor (without timestamp)\r
+ */\r
+typedef struct {\r
+ __IO uint32_t CTRLSTAT; /*!< TDES control and status word */\r
+ __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */\r
+ __IO uint32_t B1ADD; /*!< Buffer 1 address */\r
+ __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */\r
+} IP_ENET_001_TXDESC_T;\r
+\r
+/**\r
+ * @brief Structure of a enhanced transmit descriptor (with timestamp)\r
+ */\r
+typedef struct {\r
+ __IO uint32_t CTRLSTAT; /*!< TDES control and status word */\r
+ __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */\r
+ __IO uint32_t B1ADD; /*!< Buffer 1 address */\r
+ __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */\r
+ __IO uint32_t TDES4; /*!< Reserved */\r
+ __IO uint32_t TDES5; /*!< Reserved */\r
+ __IO uint32_t TTSL; /*!< Timestamp value low */\r
+ __IO uint32_t TTSH; /*!< Timestamp value high */\r
+} IP_ENET_001_ENHTXDESC_T;\r
+\r
+/**\r
+ * @brief Structure of a receive descriptor (without timestamp)\r
+ */\r
+typedef struct {\r
+ __IO uint32_t STATUS; /*!< RDES status word */\r
+ __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts and control */\r
+ __IO uint32_t B1ADD; /*!< Buffer 1 address */\r
+ __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */\r
+} IP_ENET_001_RXDESC_T;\r
+\r
+/**\r
+ * @brief Structure of a enhanced receive descriptor (with timestamp)\r
+ */\r
+typedef struct {\r
+ __IO uint32_t STATUS; /*!< RDES status word */\r
+ __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts */\r
+ __IO uint32_t B1ADD; /*!< Buffer 1 address */\r
+ __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */\r
+ __IO uint32_t EXTSTAT; /*!< Extended Status */\r
+ __IO uint32_t RDES5; /*!< Reserved */\r
+ __IO uint32_t RTSL; /*!< Timestamp value low */\r
+ __IO uint32_t RTSH; /*!< Timestamp value high */\r
+} IP_ENET_001_ENHRXDESC_T;\r
+\r
+/**\r
+ * @brief Resets the ethernet interface\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Nothing\r
+ * @note Resets the ethernet interface. This should be called prior to\r
+ * IP_ENET_Init with a small delay after this call.\r
+ */\r
+void IP_ENET_Reset(IP_ENET_001_T *pENET);\r
+\r
+/**\r
+ * @brief Sets the address of the interface\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @param macAddr : Pointer to the 6 bytes used for the MAC address\r
+ * @return Nothing\r
+ */\r
+void IP_ENET_SetADDR(IP_ENET_001_T *pENET, const uint8_t *macAddr);\r
+\r
+/**\r
+ * @brief Initialize ethernet interface\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Nothing\r
+ * @note Performs basic initialization of the ethernet interface in a default\r
+ * state. This is enough to place the interface in a usable state, but\r
+ * may require more setup outside this function.\r
+ */\r
+void IP_ENET_Init(IP_ENET_001_T *pENET);\r
+\r
+/**\r
+ * @brief Sets up the PHY link clock divider and PHY address\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @param div : Divider value, may vary per chip\r
+ * @param addr : PHY address, used with MII read and write\r
+ * @return Nothing\r
+ */\r
+void IP_ENET_SetupMII(IP_ENET_001_T *pENET, uint32_t div, uint8_t addr);\r
+\r
+/**\r
+ * @brief De-initialize the ethernet interface\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Nothing\r
+ */\r
+void IP_ENET_DeInit(IP_ENET_001_T *pENET);\r
+\r
+/**\r
+ * @brief Starts a PHY write via the MII\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @param reg : PHY register to write\r
+ * @param data : Data to write to PHY register\r
+ * @return Nothing\r
+ * @note Start a PHY write operation. Does not block, requires calling\r
+ * IP_ENET_IsMIIBusy to determine when write is complete.\r
+ */\r
+void IP_ENET_StartMIIWrite(IP_ENET_001_T *pENET, uint8_t reg, uint16_t data);\r
+\r
+/**\r
+ * @brief Starts a PHY read via the MII\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @param reg : PHY register to read\r
+ * @return Nothing\r
+ * @note Start a PHY read operation. Does not block, requires calling\r
+ * IP_ENET_IsMIIBusy to determine when read is complete and calling\r
+ * IP_ENET_ReadMIIData to get the data.\r
+ */\r
+void IP_ENET_StartMIIRead(IP_ENET_001_T *pENET, uint8_t reg);\r
+\r
+/**\r
+ * @brief Returns MII link (PHY) busy status\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Returns true if busy, otherwise false\r
+ */\r
+bool IP_ENET_IsMIIBusy(IP_ENET_001_T *pENET);\r
+\r
+/**\r
+ * @brief Returns the value read from the PHY\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Read value from PHY\r
+ */\r
+STATIC INLINE uint16_t IP_ENET_ReadMIIData(IP_ENET_001_T *pENET)\r
+{\r
+ return pENET->MAC_MII_DATA;\r
+}\r
+\r
+/**\r
+ * @brief Enables ethernet transmit\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ENET_TXEnable(IP_ENET_001_T *pENET)\r
+{\r
+ pENET->MAC_CONFIG |= MAC_CFG_TE;\r
+ pENET->DMA_OP_MODE |= DMA_OM_ST;\r
+}\r
+\r
+/**\r
+ * @brief Disables ethernet transmit\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ENET_TXDisable(IP_ENET_001_T *pENET)\r
+{\r
+ pENET->MAC_CONFIG &= ~MAC_CFG_TE;\r
+}\r
+\r
+/**\r
+ * @brief Enables ethernet packet reception\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ENET_RXEnable(IP_ENET_001_T *pENET)\r
+{\r
+ pENET->MAC_CONFIG |= MAC_CFG_RE;\r
+ pENET->DMA_OP_MODE |= DMA_OM_SR;\r
+}\r
+\r
+/**\r
+ * @brief Disables ethernet packet reception\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ENET_RXDisable(IP_ENET_001_T *pENET)\r
+{\r
+ pENET->MAC_CONFIG &= ~MAC_CFG_RE;\r
+}\r
+\r
+/**\r
+ * @brief Sets full or half duplex for the interface\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @param full : true to selected full duplex, false for half\r
+ * @return Nothing\r
+ */\r
+void IP_ENET_SetDuplex(IP_ENET_001_T *pENET, bool full);\r
+\r
+/**\r
+ * @brief Sets speed for the interface\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @param speed100 : true to select 100Mbps mode, false for 10Mbps\r
+ * @return Nothing\r
+ */\r
+void IP_ENET_SetSpeed(IP_ENET_001_T *pENET, bool speed100);\r
+\r
+/**\r
+ * @brief Configures the initial ethernet descriptors\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @param pTXDescs : Pointer to TX descriptor list\r
+ * @param pRXDescs : Pointer to RX descriptor list\r
+ * @return Nothing\r
+ */\r
+void IP_ENET_InitDescriptors(IP_ENET_001_T *pENET,\r
+ IP_ENET_001_ENHTXDESC_T *pTXDescs, IP_ENET_001_ENHRXDESC_T *pRXDescs);\r
+\r
+/**\r
+ * @brief Starts receive polling of RX descriptors\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ENET_RXStart(IP_ENET_001_T *pENET)\r
+{\r
+ /* Start receive polling */\r
+ pENET->DMA_REC_POLL_DEMAND = 1;\r
+}\r
+\r
+/**\r
+ * @brief Starts transmit polling of TX descriptors\r
+ * @param pENET : Pointer to selected ENET peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_ENET_TXStart(IP_ENET_001_T *pENET)\r
+{\r
+ /* Start transmit polling */\r
+ pENET->DMA_TRANS_POLL_DEMAND = 1;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __ENET_001_H_ */\r
--- /dev/null
+/*
+ * @brief Flash/EEPROM programming
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __FLASH_EEPROM_001_H
+#define __FLASH_EEPROM_001_H
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_FLASH_EEPROM_001 IP: Flash/EEPROM programming
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC1347)
+#define ERASE_PAGE_SUPPORT
+#define EEPROM_RW_SUPPORT
+#endif
+
+/** The maximum number of flash programing parameters */
+#define FLASH_PARAMETER_NUM (5)
+
+/** The maximum number of flash programing results */
+#define FLASH_RESULT_NUM (4)
+
+/** Flash programming function type */
+typedef void (*FLASH_ENTRY_T)(unsigned int[], unsigned int[]);
+
+/**
+ * @brief Flash command code definitions
+ */
+typedef enum {
+ FLASH_PREPARE = 50, /*!< Prepare sector(s) for write operation */
+ FLASH_COPY_RAM_TO_FLASH = 51, /*!< Copy RAM to Flash */
+ FLASH_ERASE = 52, /*!< Erase sector(s) */
+ FLASH_BLANK_CHECK = 53, /*!< Blank check sector(s) */
+ FLASH_READ_PART_ID = 54, /*!< Read chip part ID */
+ FLASH_READ_BOOT_VER = 55, /*!< Read chip boot code version */
+ FLASH_COMPARE = 56, /*!< Compare memory areas */
+ FLASH_REINVOKE_ISP = 57, /*!< Reinvoke ISP */
+ FLASH_READ_UID = 58, /*!< Read UID */
+#if defined(ERASE_PAGE_SUPPORT)
+ FLASH_ERASE_PAGE = 59, /*!< Erase page */
+#endif
+#if defined(EEPROM_RW_SUPPORT)
+ FLASH_EEPROM_WRITE = 61, /*!< EEPROM Write */
+ FLASH_EEPROM_READ = 62, /*!< EEPROM Read */
+#endif
+} FLASH_CMD_CODE_T;
+
+/**
+ * @brief Flash status code definitions
+ */
+typedef enum {
+ CMD_SUCCESS, /*!< Command is executed successfully. */
+ INVALID_COMMAND, /*!< Invalid command. */
+ SRC_ADDR_ERROR, /*!< Source address is not on a word boundary. */
+ DST_ADDR_ERROR, /*!< Destination address is not on a correct boundary. */
+ SRC_ADDR_NOT_MAPPED, /*!< Source address is not mapped in the memory map. */
+ DST_ADDR_NOT_MAPPED, /*!< Destination address is not mapped in the memory map. */
+ COUNT_ERROR, /*!< Byte count is not multiple of 4 or is not a permitted value. */
+ INVALID_SECTOR, /*!< Sector number is invalid. */
+ SECTOR_NOT_BLANK, /*!< Sector is not blank. */
+ SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, /*!< Command to prepare sector for write operation was not executed. */
+ COMPARE_ERROR, /*!< Source and destination data is not same. */
+ BUSY, /*!< Flash programming hardware interface is busy. */
+} FLASH_STATUS_CODE_T;
+
+/**
+ * @brief Command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+ uint32_t pParams[FLASH_PARAMETER_NUM]; /*!< Parameters*/
+} FLASH_COMMAND_T;
+
+/**
+ * @brief Command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+ uint32_t pResult[FLASH_RESULT_NUM]; /*!< Results*/
+} FLASH_OUTPUT_T;
+
+/* Flash Programming Command Description
+ Command Parameters Return Code Result
+ ----------------------------------------------------------------------------------------------------------
+ FLASH_PREPARE Start Sector Number CMD_SUCCESS None
+ End Sector Number BUSY
+ INVALID_SECTOR
+ FLASH_COPY_RAM2FLASH Destination Flash Addr CMD_SUCCESS None
+ Source RAM Addr SRC_ADDR_ERROR
+ Number of bytes written SRC_ADDR_NOT_MAPPED
+ CCLK in kHz DST_ADDR_NOT_MAPPED
+ COUNT_ERROR
+ SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
+ BUSY
+ FLASH_ERASE Start Sector Number CMD_SUCCESS None
+ Emd Sector Number BUSY
+ CCLK in kHz SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
+ INVALID_SECTOR
+ FLASH_BLANK_CHECK Start Sector Number CMD_SUCCESS Non Blank Sector Offset(if Status code is SECTOR_NOT_BLANK)
+ End Sector Number BUSY Content of non blank word location
+ SECTOR_NOT_BLANK
+ INVALID_SECTOR
+ FLASH_READ_PART_ID None CMD_SUCCESS Part ID
+ FLASH_READ_BOOT_VER None CMD_SUCCESS <byte1(Major)>.<byte0(Minor)>
+ FLASH_COMPARE Destination Addr CMD_SUCCESS Offset of the first mismatch
+ Source Address COMPARE_ERROR
+ Number of bytes compared COUNT_ERROR
+ ADDR_ERROR
+ ADDR_NOT_MAPPED
+ FLASH_REINVOKE_ISP None None None
+ FLASH_READ_UID None CMD_SUCCESS The first 32-bit word
+ The second 32-bit word.
+ The third 32-bit word.
+ The fourth 32-bit word
+ FLASH_ERASE_PAGE Start Page Number CMD_SUCCESS None
+ End Page Number BUSY
+ CCLK in kHz SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
+ INVALID_SECTOR
+ FLASH_EEPROM_WRITE EEPROM Addr CMD_SUCCESS None
+ RAM Addr SRC_ADDR_NOT_MAPPED
+ Number of bytes written DST_ADDR_NOT_MAPPED
+ CCLK in kHz
+ FLASH_EEPROM_READ EEPROM Addr CMD_SUCCESS None
+ RAM Addr SRC_ADDR_NOT_MAPPED
+ Number of bytes read DST_ADDR_NOT_MAPPED
+ CCLK in kHz
+ */
+
+/**
+ * @brief Execute flash programming command
+ * @param entry : Flash Programing entry
+ * @param pCommand : Command information
+ * @param pOutput : Output information
+ * @return Nothing
+ */
+STATIC INLINE void IP_FLASH_Execute(FLASH_ENTRY_T entry, FLASH_COMMAND_T *pCommand, FLASH_OUTPUT_T *pOutput)
+{
+ (entry) ((unsigned int *) pCommand, (unsigned int *) pOutput);
+}
+
+/**
+ * @brief [Prepare sectors] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+ uint32_t start; /*!< Start Sector Number */
+ uint32_t end; /*!<End Sector Number (should be greater than or equal to start sector number).*/
+} FLASH_PREPARE_SECTORS_COMMAND_T;
+
+/**
+ * @brief [Prepare sectors] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+} FLASH_PREPARE_SECTORS_OUTPUT_T;
+
+/**
+ * @brief [Copy Ram to Flash] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+ uint32_t dst; /*!< Destination flash address where data bytes are to be written (256 byte boundary) */
+ uint32_t src; /*!<Source RAM address from which data bytes are to be read (a word boudary).*/
+ uint32_t byteNum; /*!<Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.*/
+ uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
+} FLASH_COPY_RAM_TO_FLASH_COMMAND_T;
+
+/**
+ * @brief [Copy Ram to Flash] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+} FLASH_COPY_RAM_TO_FLASH_OUTPUT_T;
+
+/**
+ * @brief [Erase Sector(s)] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+ uint32_t start; /*!< Start Sector Number */
+ uint32_t end; /*!<End Sector Number (should be greater than or equal to start sector number).*/
+ uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
+} FLASH_ERASE_SECTORS_COMMAND_T;
+
+/**
+ * @brief [Erase Sector(s)] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+} FLASH_ERASE_SECTORS_OUTPUT_T;
+
+/**
+ * @brief [Blank check sector(s)] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+ uint32_t start; /*!< Start Sector Number */
+ uint32_t end; /*!<End Sector Number (should be greater than or equal to start sector number).*/
+} FLASH_BLANK_CHECK_SECTORS_COMMAND_T;
+
+/**
+ * @brief [Blank check sector(s)] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+ uint32_t firstNonBlankLoc; /*!< Offset of the first non blank word location if the Status Code is SECTOR_NOT_BLANK.*/
+ uint32_t firstNonBlankVal; /*!<Contents of non blank word location.*/
+} FLASH_BLANK_CHECK_SECTORS_OUTPUT_T;
+
+/**
+ * @brief [Read Part Identification number] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+} FLASH_READ_PART_ID_COMMAND_T;
+
+/**
+ * @brief [Read Part Identification number] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+ uint32_t partID; /*!< Part Identification Number*/
+} FLASH_READ_PART_ID_OUTPUT_T;
+
+/**
+ * @brief [Read Boot code version number] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+} FLASH_READ_BOOTCODE_VER_COMMAND_T;
+
+/**
+ * @brief [Read Boot code version number] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+ uint8_t minor; /*!< Minor*/
+ uint8_t major; /*!< Major*/
+} FLASH_READ_BOOTCODE_VER_OUTPUT_T;
+
+/**
+ * @brief [Compare memory] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+ uint32_t dst; /*!<Starting flash or RAM address of data bytes to be compared (a word boundary) */
+ uint32_t src; /*!<Starting flash or RAM address of data bytes to be compared (a word boudary).*/
+ uint32_t byteNum; /*!<Number of bytes to be compared; should be a multiple of 4.*/
+} FLASH_COMPARE_MEM_COMMAND_T;
+
+/**
+ * @brief [Compare memory] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+ uint32_t offset; /*!< Offset of the first mismatch if the Status Code is COMPARE_ERROR.*/
+} FLASH_COMPARE_MEM_OUTPUT_T;
+
+/**
+ * @brief [Reinvoke ISP] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+} FLASH_REINVOKE_ISP_COMMAND_T;
+
+/**
+ * @brief [Reinvoke ISP] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+} FLASH_REINVOKE_ISP_OUTPUT_T;
+
+/**
+ * @brief [ReadUID] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+} FLASH_READ_UID_COMMAND_T;
+
+/**
+ * @brief [ReadUID] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+ uint32_t id[4]; /*!< UID*/
+} FLASH_READ_UID_OUTPUT_T;
+
+#if defined(ERASE_PAGE_SUPPORT)
+/**
+ * @brief [Erase page(s)] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+ uint32_t start; /*!< Start Page Number */
+ uint32_t end; /*!<End Page Number (should be greater than or equal to start page number).*/
+ uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
+} FLASH_ERASE_PAGES_COMMAND_T;
+
+/**
+ * @brief [Erase page(s)] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+} FLASH_ERASE_PAGES_OUTPUT_T;
+
+#endif /* defined(ERASE_PAGE_SUPPORT) */
+
+#if defined(EEPROM_RW_SUPPORT)
+/**
+ * @brief [Write EEPROM] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+ uint32_t eepromAddr; /*!< EEPROM address.*/
+ uint32_t ramAddr; /*!< RAM address.*/
+ uint32_t byteNum; /*!<Number of bytes to be written.*/
+ uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
+} EEPROM_WRITE_COMMAND_T;
+
+/**
+ * @brief [Write EEPROM] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+} EEPROM_WRITE_OUTPUT_T;
+
+/**
+ * @brief [Read EEPROM] command parameter table structure
+ */
+typedef struct {
+ uint32_t cmd; /*!< Command code */
+ uint32_t eepromAddr; /*!< EEPROM address.*/
+ uint32_t ramAddr; /*!< RAM address.*/
+ uint32_t byteNum; /*!<Number of bytes to be written.*/
+ uint32_t cclk; /*!<System Clock Frequency (CCLK) in kHz.*/
+} EEPROM_READ_COMMAND_T;
+
+/**
+ * @brief [Read EEPROM] command result table structure
+ */
+typedef struct {
+ uint32_t status; /*!< Status code */
+} EEPROM_READ_OUTPUT_T;
+
+#endif /* defined(EEPROM_RW_SUPPORT) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FLASH_EEPROM_001_H */
--- /dev/null
+/*\r
+ * @brief FPU init code\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __FPU_INIT_H_\r
+#define __FPU_INIT_H_\r
+\r
+#if defined(CORE_M4)\r
+\r
+/**\r
+ * @defgroup IP_FPU_CMX_001 IP: FPU initialization\r
+ * @ingroup IP_Drivers\r
+ * Cortex FPU initialization\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Early initialization of the FPU\r
+ * @return Nothing\r
+ */\r
+void fpuInit(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* #if defined */\r
+\r
+#endif /* __FPU_INIT_H_ */\r
--- /dev/null
+/*\r
+ * @brief Global Input Multiplexer Array control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __GIMA_001_H_\r
+#define __GIMA_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_GIMA_001 IP: GIMA register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Global Input Multiplexer Array\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Global Input Multiplexer Array (GIMA) register block structure\r
+ */\r
+typedef struct { /*!< GIMA Structure */\r
+ __IO uint32_t CAP0_IN[4][4]; /*!< Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */\r
+ __IO uint32_t CTIN_IN[8]; /*!< SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */\r
+ __IO uint32_t VADC_TRIGGER_IN; /*!< VADC trigger input multiplexer (GIMA output 24) */\r
+ __IO uint32_t EVENTROUTER_13_IN; /*!< Event router input 13 multiplexer (GIMA output 25) */\r
+ __IO uint32_t EVENTROUTER_14_IN; /*!< Event router input 14 multiplexer (GIMA output 26) */\r
+ __IO uint32_t EVENTROUTER_16_IN; /*!< Event router input 16 multiplexer (GIMA output 27) */\r
+ __IO uint32_t ADCSTART0_IN; /*!< ADC start0 input multiplexer (GIMA output 28) */\r
+ __IO uint32_t ADCSTART1_IN; /*!< ADC start1 input multiplexer (GIMA output 29) */\r
+} IP_GIMA_001_T;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __GIMA_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief GPDMA Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __GPDMA_001_H_\r
+#define __GPDMA_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_GPDMA_001 IP: GPDMA register block and driver\r
+ * @ingroup IP_Drivers\r
+ * General Purpose DMA\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPDMA Channel register block structure\r
+ */\r
+typedef struct {\r
+ __IO uint32_t SRCADDR; /*!< DMA Channel Source Address Register */\r
+ __IO uint32_t DESTADDR; /*!< DMA Channel Destination Address Register */\r
+ __IO uint32_t LLI; /*!< DMA Channel Linked List Item Register */\r
+ __IO uint32_t CONTROL; /*!< DMA Channel Control Register */\r
+ __IO uint32_t CONFIG; /*!< DMA Channel Configuration Register */\r
+ __I uint32_t RESERVED1[3];\r
+} IP_GPDMA_001_CH_T;\r
+\r
+#define GPDMA_CHANNELS 8\r
+\r
+/**\r
+ * @brief GPDMA register block\r
+ */\r
+typedef struct { /*!< GPDMA Structure */\r
+ __I uint32_t INTSTAT; /*!< DMA Interrupt Status Register */\r
+ __I uint32_t INTTCSTAT; /*!< DMA Interrupt Terminal Count Request Status Register */\r
+ __O uint32_t INTTCCLEAR; /*!< DMA Interrupt Terminal Count Request Clear Register */\r
+ __I uint32_t INTERRSTAT; /*!< DMA Interrupt Error Status Register */\r
+ __O uint32_t INTERRCLR; /*!< DMA Interrupt Error Clear Register */\r
+ __I uint32_t RAWINTTCSTAT; /*!< DMA Raw Interrupt Terminal Count Status Register */\r
+ __I uint32_t RAWINTERRSTAT; /*!< DMA Raw Error Interrupt Status Register */\r
+ __I uint32_t ENBLDCHNS; /*!< DMA Enabled Channel Register */\r
+ __IO uint32_t SOFTBREQ; /*!< DMA Software Burst Request Register */\r
+ __IO uint32_t SOFTSREQ; /*!< DMA Software Single Request Register */\r
+ __IO uint32_t SOFTLBREQ; /*!< DMA Software Last Burst Request Register */\r
+ __IO uint32_t SOFTLSREQ; /*!< DMA Software Last Single Request Register */\r
+ __IO uint32_t CONFIG; /*!< DMA Configuration Register */\r
+ __IO uint32_t SYNC; /*!< DMA Synchronization Register */\r
+ __I uint32_t RESERVED0[50];\r
+ IP_GPDMA_001_CH_T CH[GPDMA_CHANNELS];\r
+} IP_GPDMA_001_T;\r
+\r
+/**\r
+ * @brief Macro defines for DMA channel control registers\r
+ */\r
+#define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0)) /*!< Transfer size*/\r
+#define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12)) /*!< Source burst size*/\r
+#define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15)) /*!< Destination burst size*/\r
+#define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18)) /*!< Source transfer width*/\r
+#define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21)) /*!< Destination transfer width*/\r
+#define GPDMA_DMACCxControl_SI ((1UL << 26)) /*!< Source increment*/\r
+#define GPDMA_DMACCxControl_DI ((1UL << 27)) /*!< Destination increment*/\r
+#if defined(CHIP_LPC43XX) || defined(CHIP_LPC18XX)\r
+#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24)) /*!< Source AHB master select in 18xx43xx*/\r
+#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25)) /*!< Destination AHB master select in 18xx43xx*/\r
+#else\r
+#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0\r
+#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 0\r
+#endif\r
+#define GPDMA_DMACCxControl_Prot1 ((1UL << 28)) /*!< Indicates that the access is in user mode or privileged mode*/\r
+#define GPDMA_DMACCxControl_Prot2 ((1UL << 29)) /*!< Indicates that the access is bufferable or not bufferable*/\r
+#define GPDMA_DMACCxControl_Prot3 ((1UL << 30)) /*!< Indicates that the access is cacheable or not cacheable*/\r
+#define GPDMA_DMACCxControl_I ((1UL << 31)) /*!< Terminal count interrupt enable bit */\r
+\r
+/**\r
+ * @brief Macro defines for DMA Configuration register\r
+ */\r
+#define GPDMA_DMACConfig_E ((0x01)) /*!< DMA Controller enable*/\r
+#define GPDMA_DMACConfig_M ((0x02)) /*!< AHB Master endianness configuration*/\r
+#define GPDMA_DMACConfig_BITMASK ((0x03))\r
+\r
+/**\r
+ * @brief Macro defines for DMA Channel Configuration registers\r
+ */\r
+#define GPDMA_DMACCxConfig_E ((1UL << 0)) /*!< DMA control enable*/\r
+#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1)) /*!< Source peripheral*/\r
+#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6)) /*!< Destination peripheral*/\r
+#define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11)) /*!< This value indicates the type of transfer*/\r
+#define GPDMA_DMACCxConfig_IE ((1UL << 14)) /*!< Interrupt error mask*/\r
+#define GPDMA_DMACCxConfig_ITC ((1UL << 15)) /*!< Terminal count interrupt mask*/\r
+#define GPDMA_DMACCxConfig_L ((1UL << 16)) /*!< Lock*/\r
+#define GPDMA_DMACCxConfig_A ((1UL << 17)) /*!< Active*/\r
+#define GPDMA_DMACCxConfig_H ((1UL << 18)) /*!< Halt*/\r
+\r
+/**\r
+ * @brief GPDMA Interrupt Clear Status\r
+ */\r
+typedef enum IP_GPDMA_STATECLEAR {\r
+ GPDMA_STATCLR_INTTC, /*!< GPDMA Interrupt Terminal Count Request Clear */\r
+ GPDMA_STATCLR_INTERR /*!< GPDMA Interrupt Error Clear */\r
+} IP_GPDMA_STATECLEAR_T;\r
+\r
+/**\r
+ * @brief GPDMA Type of Interrupt Status\r
+ */\r
+typedef enum IP_GPDMA_STATUS {\r
+ GPDMA_STAT_INT, /*!< GPDMA Interrupt Status */\r
+ GPDMA_STAT_INTTC, /*!< GPDMA Interrupt Terminal Count Request Status */\r
+ GPDMA_STAT_INTERR, /*!< GPDMA Interrupt Error Status */\r
+ GPDMA_STAT_RAWINTTC, /*!< GPDMA Raw Interrupt Terminal Count Status */\r
+ GPDMA_STAT_RAWINTERR, /*!< GPDMA Raw Error Interrupt Status */\r
+ GPDMA_STAT_ENABLED_CH /*!< GPDMA Enabled Channel Status */\r
+} IP_GPDMA_STATUS_T;\r
+\r
+/**\r
+ * @brief GPDMA Type of DMA controller\r
+ */\r
+typedef enum IP_GPDMA_FLOW_CONTROL {\r
+ GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), /*!< Memory to memory - DMA control */\r
+ GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), /*!< Memory to peripheral - DMA control */\r
+ GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), /*!< Peripheral to memory - DMA control */\r
+ GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), /*!< Source peripheral to destination peripheral - DMA control */\r
+ GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), /*!< Source peripheral to destination peripheral - destination peripheral control */\r
+ GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), /*!< Memory to peripheral - peripheral control */\r
+ GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), /*!< Peripheral to memory - peripheral control */\r
+ GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) /*!< Source peripheral to destination peripheral - source peripheral control */\r
+} IP_GPDMA_FLOW_CONTROL_T;\r
+\r
+/**\r
+ * @brief GPDMA structure using for DMA configuration\r
+ */\r
+typedef struct {\r
+ uint32_t ChannelNum; /*!< DMA channel number, should be in\r
+ * range from 0 to 7.\r
+ * Note: DMA channel 0 has the highest priority\r
+ * and DMA channel 7 the lowest priority.\r
+ */\r
+ uint32_t TransferSize; /*!< Length/Size of transfer */\r
+ uint32_t TransferWidth; /*!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */\r
+ uint32_t SrcAddr; /*!< Physical Source Address, used in case TransferType is chosen as\r
+ * GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */\r
+ uint32_t DstAddr; /*!< Physical Destination Address, used in case TransferType is chosen as\r
+ * GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */\r
+ uint32_t TransferType; /*!< Transfer Type, should be one of the following:\r
+ * - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control\r
+ * - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control\r
+ * - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control\r
+ * - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control\r
+ */\r
+} GPDMA_Channel_CFG_T;\r
+\r
+/**\r
+ * @brief Initialize the GPDMA\r
+ * @param pGPDMA : The Base Address of GPDMA on the chip\r
+ * @return Nothing\r
+ */\r
+void IP_GPDMA_Init(IP_GPDMA_001_T *pGPDMA);\r
+\r
+/**\r
+ * @brief Create the Control word based on given parameters\r
+ * @param GPDMAChannelConfig : Configuration struct\r
+ * @param GPDMA_LUTPerBurstSrcConn : Peripheral Source burst size\r
+ * @param GPDMA_LUTPerBurstDstConn : Peripheral Destination burst size\r
+ * @param GPDMA_LUTPerWidSrcConn : Peripheral Source transfer width\r
+ * @param GPDMA_LUTPerWidDstConn : Peripheral Destination transfer width\r
+ * @return 32-bit unsigned control value, *can be used while calling IP_GPDMA_Setup()*,\r
+ * ERROR if the transfer type specified in GPDMAChannelConfig is invalid\r
+ * @note Control Word is a 32-bit unsigned value that provides the transfer\r
+ * information like the peripheral number, transfer size etc.,\r
+ */\r
+uint32_t IP_GPDMA_MakeCtrlWord(const GPDMA_Channel_CFG_T *GPDMAChannelConfig,\r
+ uint32_t GPDMA_LUTPerBurstSrcConn,\r
+ uint32_t GPDMA_LUTPerBurstDstConn,\r
+ uint32_t GPDMA_LUTPerWidSrcConn,\r
+ uint32_t GPDMA_LUTPerWidDstConn);\r
+\r
+/**\r
+ * @brief Set up the GPDMA according to the specification configuration details\r
+ * @param pGPDMA : The Base Address of GPDMA on the chip\r
+ * @param GPDMAChannelConfig : Pointer to Configuration struct\r
+ * @param CtrlWord : Control Word *can be obtained using IP_GPDMA_MakeCtrlWord()*\r
+ * @param LinkListItem : Pointer to next descriptor *[0 if no linked list is used]*\r
+ * @param SrcPeripheral : Peripheral Source ID\r
+ * @param DstPeripheral : Peripheral Destination ID\r
+ * @return SUCCESS or ERROR on setup failure\r
+ */\r
+Status IP_GPDMA_Setup(IP_GPDMA_001_T *pGPDMA,\r
+ GPDMA_Channel_CFG_T *GPDMAChannelConfig,\r
+ uint32_t CtrlWord,\r
+ uint32_t LinkListItem,\r
+ uint8_t SrcPeripheral,\r
+ uint8_t DstPeripheral);\r
+\r
+/**\r
+ * @brief Read the status from different registers according to the type\r
+ * @param pGPDMA : The Base Address of GPDMA on the chip\r
+ * @param type : Status mode, should be:\r
+ * - GPDMA_STAT_INT : GPDMA Interrupt Status\r
+ * - GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status\r
+ * - GPDMA_STAT_INTERR : GPDMA Interrupt Error Status\r
+ * - GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status\r
+ * - GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status\r
+ * - GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status\r
+ * @param channel : The GPDMA channel : 0 - 7\r
+ * @return SET is interrupt is pending or RESET if not pending\r
+ */\r
+IntStatus IP_GPDMA_IntGetStatus(IP_GPDMA_001_T *pGPDMA, IP_GPDMA_STATUS_T type, uint8_t channel);\r
+\r
+/**\r
+ * @brief Clear the Interrupt Flag from different registers according to the type\r
+ * @param pGPDMA : The Base Address of GPDMA on the chip\r
+ * @param type : Flag mode, should be:\r
+ * - GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request\r
+ * - GPDMA_STATCLR_INTERR : GPDMA Interrupt Error\r
+ * @param channel : The GPDMA channel : 0 - 7\r
+ * @return Nothing\r
+ */\r
+void IP_GPDMA_ClearIntPending(IP_GPDMA_001_T *pGPDMA, IP_GPDMA_STATECLEAR_T type, uint8_t channel);\r
+\r
+/**\r
+ * @brief Enable or Disable the GPDMA Channel\r
+ * @param pGPDMA : The Base Address of GPDMA on the chip\r
+ * @param channelNum : The GPDMA channel : 0 - 7\r
+ * @param NewState : ENABLE to enable GPDMA or DISABLE to disable GPDMA\r
+ * @return Nothing\r
+ */\r
+void IP_GPDMA_ChannelCmd(IP_GPDMA_001_T *pGPDMA, uint8_t channelNum, FunctionalState NewState);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __GPDMA_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief GPIO Registers and Functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __GPIO_001_H_\r
+#define __GPIO_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_GPIO_001 IP: GPIO register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPIO port register block structure\r
+ */\r
+typedef struct { /*!< GPIO_PORT Structure */\r
+ __IO uint8_t B[128][32]; /*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */\r
+ __IO uint32_t W[32][32]; /*!< Offset 0x1000: Word pin registers port 0 to n */\r
+ __IO uint32_t DIR[32]; /*!< Offset 0x2000: Direction registers port n */\r
+ __IO uint32_t MASK[32]; /*!< Offset 0x2080: Mask register port n */\r
+ __IO uint32_t PIN[32]; /*!< Offset 0x2100: Portpin register port n */\r
+ __IO uint32_t MPIN[32]; /*!< Offset 0x2180: Masked port register port n */\r
+ __IO uint32_t SET[32]; /*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */\r
+ __O uint32_t CLR[32]; /*!< Offset 0x2280: Clear port n */\r
+ __O uint32_t NOT[32]; /*!< Offset 0x2300: Toggle port n */\r
+} IP_GPIO_001_T;\r
+\r
+/**\r
+ * @brief Initialize GPIO block\r
+ * @param pGPIO : The Base Address of the GPIO block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_GPIO_Init(IP_GPIO_001_T *pGPIO)\r
+{}\r
+\r
+/**\r
+ * @brief Set a GPIO port/bit state\r
+ * @param pGPIO : The Base Address of the GPIO block\r
+ * @param Port : GPIO port to set\r
+ * @param Bit : GPIO bit to set\r
+ * @param Setting : true for high, false for low\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_GPIO_WritePortBit(IP_GPIO_001_T *pGPIO, uint32_t Port, uint8_t Bit, bool Setting)\r
+{\r
+ pGPIO->B[Port][Bit] = Setting;\r
+}\r
+\r
+/**\r
+ * @brief Set a GPIO direction\r
+ * @param pGPIO : The Base Address of the GPIO block\r
+ * @param Port : GPIO port to set\r
+ * @param Bit : GPIO bit to set\r
+ * @param Setting : true for output, false for input\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_GPIO_WriteDirBit(IP_GPIO_001_T *pGPIO, uint32_t Port, uint8_t Bit, bool Setting)\r
+{\r
+ if (Setting) {\r
+ pGPIO->DIR[Port] |= 1UL << Bit;\r
+ }\r
+ else {\r
+ pGPIO->DIR[Port] &= ~(1UL << Bit);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Read a GPIO state\r
+ * @param pGPIO : The Base Address of the GPIO block\r
+ * @param Port : GPIO port to read\r
+ * @param Bit : GPIO bit to read\r
+ * @return true of the GPIO is high, false if low\r
+ */\r
+STATIC INLINE bool IP_GPIO_ReadPortBit(IP_GPIO_001_T *pGPIO, uint32_t Port, uint8_t Bit)\r
+{\r
+ return (bool) pGPIO->B[Port][Bit];\r
+}\r
+\r
+/**\r
+ * @brief Read a GPIO direction (out or in)\r
+ * @param pGPIO : The Base Address of the GPIO block\r
+ * @param Port : GPIO port to read\r
+ * @param Bit : GPIO bit to read\r
+ * @return true of the GPIO is an output, false if input\r
+ */\r
+STATIC INLINE bool IP_GPIO_ReadDirBit(IP_GPIO_001_T *pGPIO, uint32_t Port, uint8_t Bit)\r
+{\r
+ return (bool) (((pGPIO->DIR[Port]) >> Bit) & 1);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __GPIO_001_H_ */\r
--- /dev/null
+/*
+ * @brief GPIO Registers and Functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPIO_003_H_
+#define __GPIO_003_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_GPIO_003 IP: GPIO register block and driver (003)
+ * @ingroup IP_Drivers
+ * @{
+ */
+
+/**
+ * @brief GPIO port register block structure
+ */
+typedef struct { /*!< GPIO_PORT Structure */
+ __IO uint32_t DATA[4096]; /*!< Offset: 0x0000 to 0x3FFC Data address masking register (R/W) */
+ uint32_t RESERVED1[4096];
+ __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction register (R/W) */
+ __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense register (R/W) */
+ __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges register (R/W) */
+ __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event register (R/W) */
+ __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask register (R/W) */
+ __I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status register (R/ ) */
+ __I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status register (R/ ) */
+ __O uint32_t IC; /*!< Offset: 0x801C Interrupt clear register (W) */
+} IP_GPIO_003_T;
+
+/**
+ * @brief Initialize GPIO block
+ * @param pGPIO : the base address of the GPIO block
+ * @return Nothing
+ */
+STATIC INLINE void IP_GPIO_Init(IP_GPIO_003_T *pGPIO)
+{}
+
+/**
+ * @brief Write data to port
+ * @param pGPIO : the base address of the GPIO block
+ * @param mask : determines which pins will be written. bits [11:0] address pins PIOn.0~PIOn.11.
+ * If bit's value is 1, the state of the relevant pin is updated. Otherwise, it is unchanged.
+ * @param val : bit values.
+ * @return Nothing
+ * @note mask is in range 0~4095.
+ */
+STATIC INLINE void IP_GPIO_WritePort(IP_GPIO_003_T *pGPIO, uint16_t mask, uint16_t val)
+{
+ pGPIO->DATA[mask] = val;
+}
+
+/**
+ * @brief Set state of pin
+ * @param pGPIO : the base address of the GPIO block
+ * @param pin : pin number (0-11)
+ * @param val : true for high, false for low
+ * @return Nothing
+ */
+STATIC INLINE void IP_GPIO_WritePortBit(IP_GPIO_003_T *pGPIO, uint8_t pin, bool val)
+{
+ pGPIO->DATA[1 << pin] = val << pin;
+}
+
+/**
+ * @brief Read port state
+ * @param pGPIO : the base address of the GPIO block
+ * @return Port value. A 1-bit indicate the relevant pins is high.
+ */
+STATIC INLINE uint32_t IP_GPIO_ReadPort(IP_GPIO_003_T *pGPIO)
+{
+ return pGPIO->DATA[4095];
+}
+
+/**
+ * @brief Read pin state
+ * @param pGPIO : the base address of the GPIO block
+ * @param pin : pin number (0-11)
+ * @return true of the GPIO is high, false if low
+ */
+STATIC INLINE bool IP_GPIO_ReadPortBit(IP_GPIO_003_T *pGPIO, uint8_t pin)
+{
+ return (bool) ((pGPIO->DATA[1 << pin] >> pin) & 1);
+}
+
+/**
+ * @brief Set GPIO direction for a pin
+ * @param pGPIO : the base address of the GPIO block
+ * @param pin : pin number (0-11)
+ * @param dir : true for output, false for input
+ * @return Nothing
+ */
+STATIC INLINE void IP_GPIO_WriteDirBit(IP_GPIO_003_T *pGPIO, uint8_t pin, bool dir)
+{
+ if (dir) {
+ pGPIO->DIR |= 1UL << pin;
+ }
+ else {
+ pGPIO->DIR &= ~(1UL << pin);
+ }
+}
+
+/**
+ * @brief Set GPIO direction for a port
+ * @param pGPIO : the base address of the GPIO block
+ * @param bitVal : bit value
+ * @param dir : true for output, false for input
+ * @return Nothing
+ */
+STATIC INLINE void IP_GPIO_SetDir(IP_GPIO_003_T *pGPIO, uint32_t bitVal, bool dir)
+{
+ if (dir) {
+ pGPIO->DIR |= bitVal;
+ }
+ else {
+ pGPIO->DIR &= ~bitVal;
+ }
+}
+
+/**
+ * @brief Read a GPIO direction (out or in)
+ * @param pGPIO : the base address of the GPIO block
+ * @param pin : pin number (0-11)
+ * @return true of the GPIO is an output, false if input
+ */
+STATIC INLINE bool IP_GPIO_ReadDirBit(IP_GPIO_003_T *pGPIO, uint8_t pin)
+{
+ return (bool) (((pGPIO->DIR) >> pin) & 1);
+}
+
+typedef enum {
+ GPIOPININT_FALLING_EDGE = 0, /*!<Selects interrupt on pin x to be triggered on FALLING level*/
+ GPIOPININT_ACTIVE_LOW_LEVEL = 1, /*!<Selects interrupt on pin x to be triggered on LOW level*/
+ GPIOPININT_RISING_EDGE = (1 << 12), /*!<Selects interrupt on pin x to be triggered on RISING level*/
+ GPIOPININT_ACTIVE_HIGH_LEVEL = 1 | (1 << 12), /*!<Selects interrupt on pin x to be triggered on HIGH level*/
+ GPIOPININT_BOTH_EDGES = (1 << 24), /*!<Selects interrupt on pin x to be triggered on both edges*/
+} IP_GPIOPININT_MODE_T;
+
+/**
+ * @brief Configure GPIO Interrupt
+ * @param pGPIO : pointer to GPIO interrupt register block
+ * @param pin : GPIO port number interrupt
+ * @param mode : Interrupt mode.
+ * @return None
+ */
+void IP_GPIO_IntCmd(IP_GPIO_003_T *pGPIO, uint8_t pin, IP_GPIOPININT_MODE_T mode);
+
+/**
+ * @brief Get GPIO Interrupt Status
+ * @param pGPIO : pointer to GPIO interrupt register block
+ * @param pin : pin number
+ * @return true if interrupt is pending, otherwise false
+ */
+STATIC INLINE bool IP_GPIO_IntGetStatus(IP_GPIO_003_T *pGPIO, uint8_t pin)
+{
+ return (bool) (((pGPIO->RIS) >> pin) & 0x01);
+}
+
+/**
+ * @brief Clear GPIO Interrupt (Edge interrupt cases only)
+ * @param pGPIO : pointer to GPIO interrupt register block
+ * @param pin : pin number
+ * @return None
+ */
+STATIC INLINE void IP_GPIO_IntClear(IP_GPIO_003_T *pGPIO, uint8_t pin)
+{
+ pGPIO->IC |= (1 << pin);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_003_H_ */
--- /dev/null
+/*\r
+ * @brief GPIO Group Interrupt Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __GPIOGRPINT_001_H_\r
+#define __GPIOGRPINT_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_GPIOGRPINT_001 IP: GPIO Grouped Interrupts register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPIO grouped interrupt register block structure\r
+ */\r
+typedef struct { /*!< GPIO_GROUP_INTn Structure */\r
+ __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */\r
+ __I uint32_t RESERVED0[7];\r
+ __IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */\r
+ __IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */\r
+} IP_GPIOGROUPINT_001_T;\r
+\r
+/**\r
+ * @brief GPIO Group Interrupt Pin Initialization\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @param PortComb : GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality)\r
+ * @param PortTrigger : GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered)\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_GPIOGP_IntInit(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger)\r
+{\r
+ pGPIOGPINT->CTRL = ((PortTrigger & 0x1) << 2) | ((PortComb & 0x1) << 1);\r
+}\r
+\r
+/**\r
+ * @brief GPIO Group Interrupt Pin Add to Group\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @param PortNum : GPIO port number, should be 0 to 7\r
+ * @param PinNum : GPIO pin number, should be 0 to 31\r
+ * @param ActiveMode : GPIO active mode, should be 0 (active LOW) and 1 (active HIGH)\r
+ * @return None\r
+ */\r
+void IP_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum, bool ActiveMode);\r
+\r
+/**\r
+ * @brief GPIO Group Interrupt Pin Remove from Group\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @param PortNum : GPIO port number, should be 0 to 7\r
+ * @param PinNum : GPIO pin number, should be 0 to 31\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_T *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum)\r
+{\r
+ /* configure to PORT_ENA register */\r
+ pGPIOGPINT->PORT_ENA[PortNum] &= ~(1 << PinNum);\r
+}\r
+\r
+/**\r
+ * @brief Get GPIO Group Interrupt Get Status\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @return true if interrupt is pending, otherwise false\r
+ */\r
+STATIC INLINE bool IP_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_T *pGPIOGPINT)\r
+{\r
+ return (bool) (pGPIOGPINT->CTRL & 0x01);\r
+}\r
+\r
+/**\r
+ * @brief Clear GPIO Group Interrupt\r
+ * @param pGPIOGPINT : Pointer to GPIOIR register block\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_GPIOGP_IntClear(IP_GPIOGROUPINT_001_T *pGPIOGPINT)\r
+{\r
+ pGPIOGPINT->CTRL |= 0x01;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __GPIOGRPINT_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief GPIO Interrupt Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __GPIOINT_001_H_\r
+#define __GPIOINT_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_GPIOINT_001 IP: GPIO Interrupt register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPIO Interrupt register block structure\r
+ */\r
+typedef struct {\r
+ __I uint32_t Status; /*!< GPIO overall Interrupt Status Register */\r
+ __I uint32_t StatR0; /*!< GPIO Interrupt Status Register 0 for Rising edge */\r
+ __I uint32_t StatF0; /*!< GPIO Interrupt Status Register 0 for Falling edge */\r
+ __O uint32_t Clr0; /*!< GPIO Interrupt Clear Register 0 */\r
+ __IO uint32_t EnR0; /*!< GPIO Interrupt Enable Register 0 for Rising edge */\r
+ __IO uint32_t EnF0; /*!< GPIO Interrupt Enable Register 0 for Falling edge */\r
+ uint32_t RESERVED0[3];\r
+ __I uint32_t StatR2; /*!< GPIO Interrupt Status Register 2 for Rising edge */\r
+ __I uint32_t StatF2; /*!< GPIO Interrupt Status Register 2 for Falling edge */\r
+ __O uint32_t Clr2; /*!< GPIO Interrupt Clear Register 2 */\r
+ __IO uint32_t EnR2; /*!< GPIO Interrupt Enable Register 2 for Rising edge */\r
+ __IO uint32_t EnF2; /*!< GPIO Interrupt Enable Register 2 for Falling edge */\r
+} IP_GPIOINT_001_T;\r
+\r
+typedef enum IP_GPIOPININT_MODE {\r
+ GPIOPININT_RISING_EDGE = 0x01,\r
+ GPIOPININT_FALLING_EDGE = 0x02\r
+} IP_GPIOPININT_MODE_T;\r
+\r
+/**\r
+ * @brief Enable GPIO Interrupt\r
+ * @param pGPIOPININT : Pointer to GPIO interrupt register block\r
+ * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)\r
+ * @param BitValue : GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF\r
+ * @param IntMode : Interrupt mode, 0 = rising edge, 1 = falling edge\r
+ * @return None\r
+ */\r
+void IP_GPIOINT_IntCmd(IP_GPIOINT_001_T *pGPIOPININT, uint8_t PortNum, uint32_t BitValue, IP_GPIOPININT_MODE_T IntMode);\r
+\r
+/**\r
+ * @brief Get GPIO Interrupt Status\r
+ * @param pGPIOPININT : Pointer to GPIO interrupt register block\r
+ * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)\r
+ * @param PinNum : Pin number, should be: 0..30(with port 0) and 0..13 (with port 2)\r
+ * @param IntMode : Interrupt mode, 0 = rising edge, 1 = falling edge\r
+ * @return true if interrupt is pending, otherwise false\r
+ */\r
+bool IP_GPIOINT_IntGetStatus(IP_GPIOINT_001_T *pGPIOPININT,\r
+ uint8_t PortNum,\r
+ uint32_t PinNum,\r
+ IP_GPIOPININT_MODE_T IntMode);\r
+\r
+/**\r
+ * @brief Clear GPIO Interrupt (Edge interrupt cases only)\r
+ * @param pGPIOPININT : Pointer to GPIO interrupt register block\r
+ * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2)\r
+ * @param BitValue : GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF\r
+ * @return None\r
+ */\r
+void IP_GPIOINT_IntClear(IP_GPIOINT_001_T *pGPIOPININT, uint8_t PortNum, uint32_t BitValue);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __GPIOINT_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief GPIO Pin Interrupt Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __GPIOPININT_001_H_\r
+#define __GPIOPININT_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_GPIOPININT_001 IP: GPIO Pin Interrupt register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPIO pin interrupt register block structure\r
+ */\r
+typedef struct { /*!< GPIO_PIN_INT Structure */\r
+ __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */\r
+ __IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */\r
+ __O uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */\r
+ __O uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */\r
+ __IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */\r
+ __O uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */\r
+ __O uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */\r
+ __IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */\r
+ __IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */\r
+ __IO uint32_t IST; /*!< Pin Interrupt Status register */\r
+} IP_GPIOPININT_001_T;\r
+\r
+typedef enum IP_GPIOPININT_MODE {\r
+ GPIOPININT_RISING_EDGE = 0x01,\r
+ GPIOPININT_FALLING_EDGE = 0x02,\r
+ GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,\r
+ GPIOPININT_ACTIVE_LOW_LEVEL = 0x08\r
+} IP_GPIOPININT_MODE_T;\r
+\r
+/**\r
+ * @brief Enable GPIO Interrupt\r
+ * @param pGPIOPININT : Pointer to GPIO interrupt register block\r
+ * @param PortNum : GPIO port number interrupt\r
+ * @param IntMode : Interrupt mode, should be:\r
+ * 0: Rising edge interrupt mode\r
+ * 1: Falling edge interrupt mode\r
+ * 2: Active-High interrupt mode\r
+ * 3: Active-Low interrupt mode\r
+ * @return None\r
+ */\r
+void IP_GPIOPININT_IntCmd(IP_GPIOPININT_001_T *pGPIOPININT, uint8_t PortNum, IP_GPIOPININT_MODE_T IntMode);\r
+\r
+/**\r
+ * @brief Get GPIO Interrupt Status\r
+ * @param pGPIOPININT : Pointer to GPIO interrupt register block\r
+ * @param PortNum : GPIO port number interrupt\r
+ * @return true if interrupt is pending, otherwise false\r
+ */\r
+STATIC INLINE bool IP_GPIOPININT_IntGetStatus(IP_GPIOPININT_001_T *pGPIOPININT, uint8_t PortNum)\r
+{\r
+ return (bool) (((pGPIOPININT->IST) >> PortNum) & 0x01);\r
+}\r
+\r
+/**\r
+ * @brief Clear GPIO Interrupt (Edge interrupt cases only)\r
+ * @param pGPIOPININT : Pointer to GPIO interrupt register block\r
+ * @param PortNum : GPIO port number interrupt\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_GPIOPININT_IntClear(IP_GPIOPININT_001_T *pGPIOPININT, uint8_t PortNum)\r
+{\r
+ if (!(pGPIOPININT->ISEL & (1 << PortNum))) {\r
+ pGPIOPININT->IST |= (1 << PortNum);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __GPIOPININT_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief I2C registers and driver functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __I2C_001_H_\r
+#define __I2C_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_I2C_001 IP: I2C register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief I2C register block structure\r
+ */\r
+typedef struct { /* I2C0 Structure */\r
+ __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */\r
+ __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */\r
+ __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */\r
+ __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
+ __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */\r
+ __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */\r
+ __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */\r
+ __IO uint32_t MMCTRL; /*!< Monitor mode control register. */\r
+ __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
+ __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
+ __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */\r
+ __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */\r
+ __IO uint32_t MASK[4]; /*!< I2C Slave address mask register */\r
+} IP_I2C_001_T;\r
+\r
+/**\r
+ * @brief Return values for SLAVE handler\r
+ * @note\r
+ * Chip drivers will usally be designed to match their events with this value\r
+ */\r
+#define RET_SLAVE_TX 6 /**< Return value, when 1 byte TX'd successfully */\r
+#define RET_SLAVE_RX 5 /**< Return value, when 1 byte RX'd successfully */\r
+#define RET_SLAVE_IDLE 2 /**< Return value, when slave enter idle mode */\r
+#define RET_SLAVE_BUSY 0 /**< Return value, when slave is busy */\r
+\r
+/**\r
+ * @brief I2C state handle return values\r
+ */\r
+#define I2C_STA_STO_RECV 0x20\r
+\r
+/*\r
+ * @brief I2C Control Set register description\r
+ */\r
+#define I2C_I2CONSET_AA ((0x04))/*!< Assert acknowledge flag */\r
+#define I2C_I2CONSET_SI ((0x08))/*!< I2C interrupt flag */\r
+#define I2C_I2CONSET_STO ((0x10))/*!< STOP flag */\r
+#define I2C_I2CONSET_STA ((0x20))/*!< START flag */\r
+#define I2C_I2CONSET_I2EN ((0x40))/*!< I2C interface enable */\r
+\r
+/*\r
+ * @brief I2C Control Clear register description\r
+ */\r
+#define I2C_I2CONCLR_AAC ((1 << 2)) /*!< Assert acknowledge Clear bit */\r
+#define I2C_I2CONCLR_SIC ((1 << 3)) /*!< I2C interrupt Clear bit */\r
+#define I2C_I2CONCLR_STOC ((1 << 4)) /*!< I2C STOP Clear bit */\r
+#define I2C_I2CONCLR_STAC ((1 << 5)) /*!< START flag Clear bit */\r
+#define I2C_I2CONCLR_I2ENC ((1 << 6)) /*!< I2C interface Disable bit */\r
+\r
+/*\r
+ * @brief I2C Common Control register description\r
+ */\r
+#define I2C_CON_AA (1UL << 2) /*!< Assert acknowledge bit */\r
+#define I2C_CON_SI (1UL << 3) /*!< I2C interrupt bit */\r
+#define I2C_CON_STO (1UL << 4) /*!< I2C STOP bit */\r
+#define I2C_CON_STA (1UL << 5) /*!< START flag bit */\r
+#define I2C_CON_I2EN (1UL << 6) /*!< I2C interface bit */\r
+\r
+/*\r
+ * @brief I2C Status Code definition (I2C Status register)\r
+ */\r
+#define I2C_STAT_CODE_BITMASK ((0xF8))/*!< Return Code mask in I2C status register */\r
+#define I2C_STAT_CODE_ERROR ((0xFF))/*!< Return Code error mask in I2C status register */\r
+\r
+/*\r
+ * @brief I2C return status code definitions\r
+ */\r
+#define I2C_I2STAT_NO_INF ((0xF8))/*!< No relevant information */\r
+#define I2C_I2STAT_BUS_ERROR ((0x00))/*!< Bus Error */\r
+\r
+/*\r
+ * @brief I2C Master transmit mode\r
+ */\r
+#define I2C_I2STAT_M_TX_START ((0x08))/*!< A start condition has been transmitted */\r
+#define I2C_I2STAT_M_TX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */\r
+#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))/*!< SLA+W has been transmitted, ACK has been received */\r
+#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))/*!< SLA+W has been transmitted, NACK has been received */\r
+#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))/*!< Data has been transmitted, ACK has been received */\r
+#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))/*!< Data has been transmitted, NACK has been received */\r
+#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */\r
+\r
+/*\r
+ * @brief I2C Master receive mode\r
+ */\r
+#define I2C_I2STAT_M_RX_START ((0x08))/*!< A start condition has been transmitted */\r
+#define I2C_I2STAT_M_RX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */\r
+#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))/*!< Arbitration lost */\r
+#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))/*!< SLA+R has been transmitted, ACK has been received */\r
+#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))/*!< SLA+R has been transmitted, NACK has been received */\r
+#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))/*!< Data has been received, ACK has been returned */\r
+#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))/*!< Data has been received, NACK has been returned */\r
+\r
+/*\r
+ * @brief I2C Slave receive mode\r
+ */\r
+#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))/*!< Own slave address has been received, ACK has been returned */\r
+#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))/*!< Arbitration lost in SLA+R/W as master */\r
+// #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68)) /*!< Own SLA+W has been received, ACK returned */\r
+#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))/*!< General call address has been received, ACK has been returned */\r
+#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */\r
+// #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78)) /*!< General call address has been received, ACK has been returned */\r
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */\r
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */\r
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */\r
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */\r
+#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or\r
+ SLV/TRX (Slave Transmit) */\r
+\r
+/*\r
+ * @brief I2C Slave transmit mode\r
+ */\r
+#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */\r
+#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))/*!< Arbitration lost in SLA+R/W as master */\r
+// #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */\r
+#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))/*!< Data has been transmitted, ACK has been received */\r
+#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))/*!< Data has been transmitted, NACK has been received */\r
+#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */\r
+#define I2C_SLAVE_TIME_OUT 0x10000000UL/*!< Time out in case of using I2C slave mode */\r
+\r
+/*\r
+ * @brief I2C Data register definition\r
+ */\r
+#define I2C_I2DAT_BITMASK ((0xFF))/*!< Mask for I2DAT register */\r
+#define I2C_I2DAT_IDLE_CHAR (0xFF) /*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than\r
+ its sending data length that can be supported */\r
+\r
+/*\r
+ * @brief I2C Monitor mode control register description\r
+ */\r
+#define I2C_I2MMCTRL_MM_ENA ((1 << 0)) /**< Monitor mode enable */\r
+#define I2C_I2MMCTRL_ENA_SCL ((1 << 1)) /**< SCL output enable */\r
+#define I2C_I2MMCTRL_MATCH_ALL ((1 << 2)) /**< Select interrupt register match */\r
+#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */\r
+\r
+/*\r
+ * @brief I2C Data buffer register description\r
+ */\r
+#define I2DATA_BUFFER_BITMASK ((0xFF))/*!< I2C Data buffer register bit mask */\r
+\r
+/*\r
+ * @brief I2C Slave Address registers definition\r
+ */\r
+#define I2C_I2ADR_GC ((1 << 0)) /*!< General Call enable bit */\r
+#define I2C_I2ADR_BITMASK ((0xFF))/*!< I2C Slave Address registers bit mask */\r
+\r
+/*\r
+ * @brief I2C Mask Register definition\r
+ */\r
+#define I2C_I2MASK_MASK(n) ((n & 0xFE))/*!< I2C Mask Register mask field */\r
+\r
+/*\r
+ * @brief I2C SCL HIGH duty cycle Register definition\r
+ */\r
+#define I2C_I2SCLH_BITMASK ((0xFFFF)) /*!< I2C SCL HIGH duty cycle Register bit mask */\r
+\r
+/*\r
+ * @brief I2C SCL LOW duty cycle Register definition\r
+ */\r
+#define I2C_I2SCLL_BITMASK ((0xFFFF)) /*!< I2C SCL LOW duty cycle Register bit mask */\r
+\r
+/*\r
+ * @brief I2C status values\r
+ */\r
+#define I2C_SETUP_STATUS_ARBF (1 << 8) /**< Arbitration false */\r
+#define I2C_SETUP_STATUS_NOACKF (1 << 9) /**< No ACK returned */\r
+#define I2C_SETUP_STATUS_DONE (1 << 10) /**< Status DONE */\r
+\r
+/*\r
+ * @brief I2C state handle return values\r
+ */\r
+#define I2C_OK 0x00\r
+#define I2C_BYTE_SENT 0x01\r
+#define I2C_BYTE_RECV 0x02\r
+#define I2C_LAST_BYTE_RECV 0x04\r
+#define I2C_SEND_END 0x08\r
+#define I2C_RECV_END 0x10\r
+#define I2C_STA_STO_RECV 0x20\r
+\r
+#define I2C_ERR (0x10000000)\r
+#define I2C_NAK_RECV (0x10000000 | 0x01)\r
+\r
+#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)\r
+\r
+/*\r
+ * @brief I2C monitor control configuration defines\r
+ */\r
+#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */\r
+#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */\r
+\r
+/**\r
+ * @brief I2C Slave Identifiers\r
+ */\r
+typedef enum {\r
+ I2C_SLAVE_GENERAL, /**< Slave ID for general calls */\r
+ I2C_SLAVE_0, /**< Slave ID fo Slave Address 0 */\r
+ I2C_SLAVE_1, /**< Slave ID fo Slave Address 1 */\r
+ I2C_SLAVE_2, /**< Slave ID fo Slave Address 2 */\r
+ I2C_SLAVE_3, /**< Slave ID fo Slave Address 3 */\r
+ I2C_SLAVE_NUM_INTERFACE /**< Number of slave interfaces */\r
+} I2C_SLAVE_ID;\r
+\r
+/**\r
+ * @brief I2C transfer status\r
+ */\r
+typedef enum {\r
+ I2C_STATUS_DONE, /**< Transfer done successfully */\r
+ I2C_STATUS_NAK, /**< NAK received during transfer */\r
+ I2C_STATUS_ARBLOST, /**< Aribitration lost during transfer */\r
+ I2C_STATUS_BUSERR, /**< Bus error in I2C transfer */\r
+ I2C_STATUS_BUSY, /**< I2C is busy doing transfer */\r
+} I2C_STATUS_T;\r
+\r
+/**\r
+ * @brief Master transfer data structure definitions\r
+ */\r
+typedef struct {\r
+ uint8_t slaveAddr; /**< 7-bit I2C Slave address */\r
+ const uint8_t *txBuff; /**< Pointer to array of bytes to be transmitted */\r
+ int txSz; /**< Number of bytes in transmit array,\r
+ if 0 only receive transfer will be carried on */\r
+ uint8_t *rxBuff; /**< Pointer memory where bytes received from I2C be stored */\r
+ int rxSz; /**< Number of bytes to received,\r
+ if 0 only transmission we be carried on */\r
+ I2C_STATUS_T status; /**< Status of the current I2C transfer */\r
+} I2C_XFER_T;\r
+\r
+/**\r
+ * @brief Initializes the pI2C peripheral.\r
+ * @param pI2C : Pointer to selected I2Cx peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_I2C_Init(IP_I2C_001_T *pI2C)\r
+{\r
+ /* Set I2C operation to default */\r
+ pI2C->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);\r
+}\r
+\r
+/**\r
+ * @brief De-initializes the I2C peripheral registers to their default reset values.\r
+ * @param pI2C : Pointer to selected I2Cx peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_I2C_DeInit(IP_I2C_001_T *pI2C)\r
+{\r
+ /* Disable I2C control */\r
+ pI2C->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;\r
+}\r
+\r
+/**\r
+ * @brief Set up clock rate for I2Cx.\r
+ * @param pI2C : Pointer to selected I2Cx peripheral\r
+ * @param SCLValue : Value of I2CSCL register\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_I2C_SetClockRate(IP_I2C_001_T *pI2C, uint32_t SCLValue)\r
+{\r
+ pI2C->SCLH = (uint32_t) (SCLValue >> 1);\r
+ pI2C->SCLL = (uint32_t) (SCLValue - pI2C->SCLH);\r
+}\r
+\r
+/**\r
+ * @brief Get current divisor clock value\r
+ * @param pI2C : Pointer to selected I2Cx peripheral\r
+ * @return Clock value divider used by I2C peripheral\r
+ */\r
+STATIC INLINE uint32_t IP_I2C_GetClockDiv(IP_I2C_001_T *pI2C)\r
+{\r
+ return pI2C->SCLH + pI2C->SCLL;\r
+}\r
+\r
+/**\r
+ * @brief Enable I2C and start master transfer\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_I2C_Master_StartXfer(IP_I2C_001_T *pI2C)\r
+{\r
+ /* Reset STA, STO, SI */\r
+ pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;\r
+\r
+ /* Enter to Master Transmitter mode */\r
+ pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;\r
+}\r
+\r
+/**\r
+ * @brief Master transfer state change handler\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @param xfer : Pointer to transfer structure\r
+ * @return\r
+ * 0 when transfer is done, non-zero when transfer is still going on.\r
+ * @note\r
+ * Values pointed to by @a xfer will be changed based on the state\r
+ * that was handled.\r
+ */\r
+int IP_I2C_MasterXfer_StateHandler(IP_I2C_001_T *pI2C, I2C_XFER_T *xfer);\r
+\r
+/**\r
+ * @brief I2C State change checking\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @return 1 when there is a state change, else 0\r
+ */\r
+STATIC INLINE int IP_I2C_IsStateChanged(IP_I2C_001_T *pI2C)\r
+{\r
+ return (pI2C->CONSET & I2C_CON_SI) != 0;\r
+}\r
+\r
+/**\r
+ * @brief Disable I2C peripheral's operation\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_I2C_Disable(IP_I2C_001_T *pI2C)\r
+{\r
+ pI2C->CONCLR = I2C_I2CONCLR_I2ENC;\r
+}\r
+\r
+/**\r
+ * @brief Set OWN slave address for specific slave ID\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @param sid : Slave ID (see #I2C_SLAVE_ID)\r
+ * @param addr : 7-bit slave address from bits (1 - 7)\r
+ * bit 0 having 1 to enable general call, 0 to disable it.\r
+ * @param mask : Address mask\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_I2C_SetSlaveAddress(IP_I2C_001_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)\r
+{\r
+ uint32_t index = (uint32_t) sid - 1;\r
+ pI2C->MASK[index] = mask;\r
+ if (sid == I2C_SLAVE_0) {\r
+ pI2C->ADR0 = addr;\r
+ }\r
+ else {\r
+ volatile uint32_t *abase = &pI2C->ADR1;\r
+ abase[index - 1] = addr;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get current state of the I2C peripheral\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @return Current state code of I2C peripheral\r
+ */\r
+STATIC INLINE int IP_I2C_GetCurrentState(IP_I2C_001_T *pI2C)\r
+{\r
+ return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);\r
+}\r
+\r
+/**\r
+ * @brief Get the slave ID of the active slave\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @return Current active slave id\r
+ */\r
+I2C_SLAVE_ID IP_I2C_GetSlaveIndex(IP_I2C_001_T *pI2C);\r
+\r
+/**\r
+ * @brief Slave transfer state change handler\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @param xfer : Pointer to transfer structure\r
+ * @return\r
+ * #RET_SLAVE_BUSY when transfer is in progress, #RET_SLAVE_IDLE when\r
+ * transfer done and slave enters idle mode, #RET_SLAVE_RX when a byte\r
+ * is received from master, #RET_SLAVE_TX when a byte is sent to master.\r
+ * @note\r
+ * Argument @a xfer must have txBuff and rxBuff pointing to a valid memory\r
+ * except for General call handler which can have txBuff as NULL as the\r
+ * slave will not transfer anything to master using General call address.\r
+ * Structure pointed by @a xfer will have its values changed based on the\r
+ * event that was handled.\r
+ */\r
+int IP_I2C_SlaveXfer_StateHandler(IP_I2C_001_T *pI2C, I2C_XFER_T *xfer);\r
+\r
+/**\r
+ * @brief Enable I2C and enable slave transfers\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_I2C_Slave_StartXfer(IP_I2C_001_T *pI2C)\r
+{\r
+ /* Reset STA, STO, SI */\r
+ pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;\r
+\r
+ /* Enter to Master Transmitter mode */\r
+ pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;\r
+}\r
+\r
+/**\r
+ * @brief Check if I2C bus is free\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @return 1 if I2C bus is free, 0 if busy\r
+ */\r
+STATIC INLINE int IP_I2C_BusFree(IP_I2C_001_T *pI2C)\r
+{\r
+ return !(pI2C->CONSET & I2C_CON_STO);\r
+}\r
+\r
+/**\r
+ * @brief Check if the active state belongs to master mode\r
+ * @param pI2C : Pointer to selected I2C peripheral\r
+ * @return 1 if the I2C is in master mode, 0 if I2C is in slave mode\r
+ */\r
+STATIC INLINE int IP_I2C_IsMasterState(IP_I2C_001_T *pI2C)\r
+{\r
+ return IP_I2C_GetCurrentState(pI2C) < 0x60;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __I2C_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief I2S Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __I2S_001_H_\r
+#define __I2S_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_I2S_001 IP: I2S register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief I2S register block structure\r
+ */\r
+typedef struct { /*!< I2S Structure */\r
+ __IO uint32_t DAO; /*!< I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */\r
+ __IO uint32_t DAI; /*!< I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */\r
+ __O uint32_t TXFIFO; /*!< I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */\r
+ __I uint32_t RXFIFO; /*!< I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */\r
+ __I uint32_t STATE; /*!< I2S Status Feedback Register. Contains status information about the I2S interface */\r
+ __IO uint32_t DMA1; /*!< I2S DMA Configuration Register 1. Contains control information for DMA request 1 */\r
+ __IO uint32_t DMA2; /*!< I2S DMA Configuration Register 2. Contains control information for DMA request 2 */\r
+ __IO uint32_t IRQ; /*!< I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */\r
+ __IO uint32_t TXRATE; /*!< I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */\r
+ __IO uint32_t RXRATE; /*!< I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */\r
+ __IO uint32_t TXBITRATE; /*!< I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */\r
+ __IO uint32_t RXBITRATE; /*!< I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */\r
+ __IO uint32_t TXMODE; /*!< I2S Transmit mode control */\r
+ __IO uint32_t RXMODE; /*!< I2S Receive mode control */\r
+} IP_I2S_001_T;\r
+\r
+/**\r
+ * @brief I2S configuration parameter defines\r
+ */\r
+/** I2S Wordwidth bit */\r
+#define I2S_WORDWIDTH_8 (0UL << 0) /*!< 8 bit Word */\r
+#define I2S_WORDWIDTH_16 (1UL << 0) /*!< 16 bit word */\r
+#define I2S_WORDWIDTH_32 (3UL << 0) /*!< 32 bit word */\r
+\r
+/** I2S Channel bit */\r
+#define I2S_STEREO (0UL << 2) /*!< Stereo audio */\r
+#define I2S_MONO (1UL << 2) /*!< Mono audio */\r
+\r
+/** I2S Master/Slave mode bit */\r
+#define I2S_MASTER_MODE (0UL << 5) /*!< I2S in master mode */\r
+#define I2S_SLAVE_MODE (1UL << 5) /*!< I2S in slave mode */\r
+\r
+/** I2S Stop bit */\r
+#define I2S_STOP_ENABLE (0UL << 3) /*!< I2S stop enable mask */\r
+#define I2S_STOP_DISABLE (1UL << 3) /*!< I2S stop disable mask */\r
+\r
+/** I2S Reset bit */\r
+#define I2S_RESET_ENABLE (1UL << 4) /*!< I2S reset enable mask */\r
+#define I2S_RESET_DISABLE (0UL << 4) /*!< I2S reset disable mask */\r
+\r
+/** I2S Mute bit */\r
+#define I2S_MUTE_ENABLE (1UL << 15) /*!< I2S mute enable mask */\r
+#define I2S_MUTE_DISABLE (0UL << 15) /*!< I2S mute disbale mask */\r
+\r
+/**\r
+ * @brief Macro defines for DAO-Digital Audio Output register\r
+ */\r
+/** I2S wordwide - the number of bytes in data*/\r
+#define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0)) /*!< DAO 8 bit */\r
+#define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1)) /*!< DAO 16 bit */\r
+#define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3)) /*!< DAO 32 bit */\r
+#define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3))\r
+\r
+/** I2S control mono or stereo format */\r
+#define I2S_DAO_MONO ((uint32_t) (1 << 2)) /*!< DAO mono audio mask */\r
+\r
+/** I2S control stop mode */\r
+#define I2S_DAO_STOP ((uint32_t) (1 << 3)) /*!< DAO stop mask */\r
+\r
+/** I2S control reset mode */\r
+#define I2S_DAO_RESET ((uint32_t) (1 << 4)) /*!< DAO reset mask */\r
+\r
+/** I2S control master/slave mode */\r
+#define I2S_DAO_SLAVE ((uint32_t) (1 << 5)) /*!< DAO slave mode mask */\r
+\r
+/** I2S word select half period minus one */\r
+#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6)) /*!< DAO Word select set macro */\r
+#define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) /*!< DAO Word select mask */\r
+\r
+/** I2S control mute mode */\r
+#define I2S_DAO_MUTE ((uint32_t) (1 << 15)) /*!< DAO mute mask */\r
+\r
+/**\r
+ * @brief Macro defines for DAI-Digital Audio Input register\r
+ */\r
+/** I2S wordwide - the number of bytes in data*/\r
+#define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0)) /*!< DAI 8 bit */\r
+#define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1)) /*!< DAI 16 bit */\r
+#define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3)) /*!< DAI 32 bit */\r
+#define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3)) /*!< DAI word wide mask */\r
+\r
+/** I2S control mono or stereo format */\r
+#define I2S_DAI_MONO ((uint32_t) (1 << 2)) /*!< DAI mono mode mask */\r
+\r
+/** I2S control stop mode */\r
+#define I2S_DAI_STOP ((uint32_t) (1 << 3)) /*!< DAI stop bit mask */\r
+\r
+/** I2S control reset mode */\r
+#define I2S_DAI_RESET ((uint32_t) (1 << 4)) /*!< DAI reset bit mask */\r
+\r
+/** I2S control master/slave mode */\r
+#define I2S_DAI_SLAVE ((uint32_t) (1 << 5)) /*!< DAI slave mode mask */\r
+\r
+/** I2S word select half period minus one (9 bits)*/\r
+#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6)) /*!< DAI Word select set macro */\r
+#define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) /*!< DAI Word select mask */\r
+\r
+/**\r
+ * @brief Macro defines for STAT register (Status Feedback register)\r
+ */\r
+#define I2S_STATE_IRQ ((uint32_t) (1))/*!< I2S Status Receive or Transmit Interrupt */\r
+#define I2S_STATE_DMA1 ((uint32_t) (1 << 1)) /*!< I2S Status Receive or Transmit DMA1 */\r
+#define I2S_STATE_DMA2 ((uint32_t) (1 << 2)) /*!< I2S Status Receive or Transmit DMA2 */\r
+#define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))/*!< I2S Status Current level of the Receive FIFO (5 bits)*/\r
+#define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16)) /*!< I2S Status Current level of the Transmit FIFO (5 bits)*/\r
+\r
+/**\r
+ * @brief Macro defines for DMA1 register (DMA1 Configuration register)\r
+ */\r
+#define I2S_DMA1_RX_ENABLE ((uint32_t) (1))/*!< I2S control DMA1 for I2S receive */\r
+#define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control DMA1 for I2S transmit */\r
+#define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) /*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */\r
+#define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) /*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */\r
+\r
+/**\r
+ * @brief Macro defines for DMA2 register (DMA2 Configuration register)\r
+ */\r
+#define I2S_DMA2_RX_ENABLE ((uint32_t) (1))/*!< I2S control DMA2 for I2S receive */\r
+#define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control DMA1 for I2S transmit */\r
+#define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) /*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */\r
+#define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) /*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */\r
+\r
+/**\r
+ * @brief Macro defines for IRQ register (Interrupt Request Control register)\r
+ */\r
+\r
+#define I2S_IRQ_RX_ENABLE ((uint32_t) (1))/*!< I2S control I2S receive interrupt */\r
+#define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1)) /*!< I2S control I2S transmit interrupt */\r
+#define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8)) /*!< I2S set the FIFO level on which to create an irq request */\r
+#define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8))\r
+#define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16)) /*!< I2S set the FIFO level on which to create an irq request */\r
+#define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16))\r
+\r
+/**\r
+ * @brief Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)\r
+ */\r
+#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) /*!< I2S Transmit MCLK rate denominator */\r
+#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< I2S Transmit MCLK rate denominator */\r
+#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) /*!< I2S Receive MCLK rate denominator */\r
+#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< I2S Receive MCLK rate denominator */\r
+\r
+/**\r
+ * @brief Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)\r
+ */\r
+#define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F))\r
+#define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F))\r
+\r
+/**\r
+ * @brief Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)\r
+ */\r
+#define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) /*!< I2S Transmit select clock source (2 bits)*/\r
+#define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) /*!< I2S Transmit control 4-pin mode */\r
+#define I2S_TXMODE_MCENA ((uint32_t) (1 << 3)) /*!< I2S Transmit control the TX_MCLK output */\r
+#define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) /*!< I2S Receive select clock source */\r
+#define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) /*!< I2S Receive control 4-pin mode */\r
+#define I2S_RXMODE_MCENA ((uint32_t) (1 << 3)) /*!< I2S Receive control the TX_MCLK output */\r
+\r
+/**\r
+ * @brief I2S transmit/receive mode for configuration\r
+ */\r
+typedef enum IP_I2S_TRxMode {\r
+ I2S_TX_MODE, /*!< Transmit mode */\r
+ I2S_RX_MODE, /*!< Receive mode */\r
+} IP_I2S_TRxMode_T;\r
+\r
+/**\r
+ * @brief I2S DMA request channel define\r
+ */\r
+typedef enum IP_I2S_DMARequestNumber {\r
+ IP_I2S_DMA_REQUEST_NUMBER_1, /*!< DMA request channel 1 */\r
+ IP_I2S_DMA_REQUEST_NUMBER_2, /*!< DMA request channel 2 */\r
+} IP_I2S_DMARequestNumber_T;\r
+\r
+/**********************************************************************************\r
+ * I2S Init/DeInit functions\r
+ *********************************************************************************/\r
+\r
+/**\r
+ * @brief Initialize for I2S\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+void IP_I2S_Init(IP_I2S_001_T *pI2S);\r
+\r
+/**\r
+ * @brief Shutdown I2S\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @return Nothing\r
+ * @note Reset all relative registers (DMA, transmit/receive control, interrupt) to default value\r
+ */\r
+void IP_I2S_DeInit(IP_I2S_001_T *pI2S);\r
+\r
+/**********************************************************************************\r
+ * I2S configuration functions\r
+ *********************************************************************************/\r
+\r
+/**\r
+ * @brief Set the data width for the specified mode\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param wordwidth : Data width, should be :\r
+ * - I2S_WORDWIDTH_8\r
+ * - I2S_WORDWIDTH_16\r
+ * - I2S_WORDWIDTH_32\r
+ * @return Nothing\r
+ */\r
+void IP_I2S_SetWordWidth(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t wordwidth);\r
+\r
+/**\r
+ * @brief Set I2S data format to mono or stereo\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param mono : Data channel, should be\r
+ * - I2S_STEREO\r
+ * - I2S_MONO\r
+ * @return Nothing\r
+ */\r
+void IP_I2S_SetMono(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mono);\r
+\r
+/**\r
+ * @brief Set I2S interface in master/slave mode\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param mode : Interface mode, should be\r
+ * - I2S_MASTER_MODE\r
+ * - I2S_SLAVE_MODE\r
+ * @return Nothing\r
+ */\r
+void IP_I2S_SetMasterSlaveMode(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mode);\r
+\r
+/**\r
+ * @brief Set the clock frequency for I2S interface\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param mclk_divider : Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface\r
+ * @return Nothing\r
+ * @note The value depends on the audio sample rate desired and the data size and format(stereo/mono) used.\r
+ * For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz\r
+ */\r
+void IP_I2S_SetBitRate(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t mclk_divider);\r
+\r
+/**\r
+ * @brief Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param x_divider : I2S transmit MCLK rate numerator\r
+ * @param y_devider : I2S transmit MCLK rate denominator\r
+ * @return Nothing\r
+ * @note Values of the numerator (X) and the denominator (Y) must be chosen to\r
+ * produce a frequency twice that desired for the transmitter MCLK, which\r
+ * must be an integer multiple of the transmitter bit clock rate.\r
+ * The equation for the fractional rate generator is:\r
+ * MCLK = PCLK * (X/Y) /2\r
+ * Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be\r
+ * greater than or equal to X.\r
+ */\r
+void IP_I2S_SetXYDivider(IP_I2S_001_T *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_devider);\r
+\r
+/**\r
+ * @brief Set word select (WS) half period\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param ws_halfperiod : I2S word select half period minus one\r
+ * @return Nothing\r
+ * @note The Word Select period is configured separately for I2S input and I2S output.\r
+ * For example: if the WS is 64clk period -> ws_halfperiod = 31\r
+ */\r
+void IP_I2S_SetWS_Halfperiod(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t ws_halfperiod);\r
+\r
+/**\r
+ * @brief Set the I2S operating modes\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param clksel : Clock source selection for the receive bit clock divider\r
+ * @param fpin : Receive 4-pin mode selection\r
+ * @param mcena : Enable for the RX_MCLK output\r
+ * @return Nothing\r
+ * @note In addition to master and slave modes, which are independently configurable for\r
+ * the transmitter and the receiver, several different clock sources are possible,\r
+ * including variations that share the clock and/or WS between the transmitter and\r
+ * receiver. It also allows using I2S with fewer pins, typically four.\r
+ */\r
+void IP_I2S_ModeConfig(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena);\r
+\r
+/**\r
+ * @brief Get the current level of the Transmit/Receive FIFO\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @return Current level of the Transmit/Receive FIFO\r
+ */\r
+uint8_t IP_I2S_GetLevel(IP_I2S_001_T *pI2S, uint8_t TRMode);\r
+\r
+/**********************************************************************************\r
+ * I2S operate functions\r
+ *********************************************************************************/\r
+\r
+/**\r
+ * @brief Send a 32-bit data to TXFIFO for transmition\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param data : Data to be transmited\r
+ * @return Nothing\r
+ * @note The function writes to TXFIFO without checking any condition.\r
+ */\r
+void IP_I2S_Send(IP_I2S_001_T *pI2S, uint32_t data);\r
+\r
+/**\r
+ * @brief Get received data from RXFIFO\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @return Data received in RXFIFO\r
+ * @note The function reads from RXFIFO without checking any condition.\r
+ */\r
+uint32_t IP_I2S_Receive(IP_I2S_001_T *pI2S);\r
+\r
+/**\r
+ * @brief Start the I2S\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @return Nothing\r
+ */\r
+void IP_I2S_Start(IP_I2S_001_T *pI2S, uint8_t TRMode);\r
+\r
+/**\r
+ * @brief Disables accesses on FIFOs, places the transmit channel in mute mode\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @return Nothing\r
+ */\r
+void IP_I2S_Pause(IP_I2S_001_T *pI2S, uint8_t TRMode);\r
+\r
+/**\r
+ * @brief Transmit channel sends only zeroes\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @return Nothing\r
+ * @note The data output from I2S transmit channel is always zeroes\r
+ */\r
+STATIC INLINE void IP_I2S_EnableMute(IP_I2S_001_T *pI2S)\r
+{\r
+ pI2S->DAO |= I2S_DAO_MUTE;\r
+}\r
+\r
+/**\r
+ * @brief Un-Mute the I2S channel\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_I2S_DisableMute(IP_I2S_001_T *pI2S)\r
+{\r
+ pI2S->DAO &= ~I2S_DAO_MUTE;\r
+}\r
+\r
+/**\r
+ * @brief Stop I2S asynchronously\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @return Nothing\r
+ * @note Pause, resets the transmit channel and FIFO asynchronously\r
+ */\r
+void IP_I2S_Stop(IP_I2S_001_T *pI2S, uint8_t TRMode);\r
+\r
+/**********************************************************************************\r
+ * I2S DMA functions\r
+ *********************************************************************************/\r
+\r
+/**\r
+ * @brief Set the FIFO level on which to create an DMA request\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param DMANum : I2S DMA request number, should be\r
+ * - IP_I2S_DMA_REQUEST_NUMBER_1\r
+ * - IP_I2S_DMA_REQUEST_NUMBER_2\r
+ * @param depth : FIFO level on which to create an DMA request\r
+ * @return Nothing\r
+ * @note DMA request is generated when rx_depth_dma <= rx_level or tx_depth_dma >= tx_level\r
+ */\r
+void IP_I2S_SetFIFODepthDMA(IP_I2S_001_T *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_T DMANum, uint32_t depth);\r
+\r
+/**\r
+ * @brief Enable/Disable DMA for the I2S\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param DMANum : I2S DMA request number, should be\r
+ * - IP_I2S_DMA_REQUEST_NUMBER_1\r
+ * - IP_I2S_DMA_REQUEST_NUMBER_2\r
+ * @param NewState : ENABLE or DISABLE DMA\r
+ * @return Nothing\r
+ */\r
+void IP_I2S_DMACmd(IP_I2S_001_T *pI2S, IP_I2S_DMARequestNumber_T DMANum, uint8_t TRMode, FunctionalState NewState);\r
+\r
+/**********************************************************************************\r
+ * I2S IRQ functions\r
+ *********************************************************************************/\r
+\r
+/**\r
+ * @brief Enable/Disable interrupt for the I2S\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param NewState : ENABLE or DISABLE Interrupt\r
+ * @return Nothing\r
+ * @note Interrupt request is generated when rx_depth_irq <= rx_level or tx_depth_irq >= tx_level\r
+ */\r
+void IP_I2S_InterruptCmd(IP_I2S_001_T *pI2S, uint8_t TRMode, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Set the FIFO level on which to create an irq request\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @param depth : FIFO level on which to create an irq request\r
+ * @return Nothing\r
+ */\r
+void IP_I2S_SetFIFODepthIRQ(IP_I2S_001_T *pI2S, uint8_t TRMode, uint32_t depth);\r
+\r
+/**\r
+ * @brief Get the status of I2S interrupt\r
+ * @param pI2S : The base of I2S peripheral on the chip\r
+ * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE\r
+ * @return I2S interrupt status, SET or RESET\r
+ */\r
+Status IP_I2S_GetIntStatus(IP_I2S_001_T *pI2S, uint8_t TRMode);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __I2S_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief LCD controller Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __LCD_001_H_\r
+#define __LCD_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_LCD_001 IP: LCD register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief LCD Controller register block structure\r
+ */\r
+typedef struct { /*!< LCD Structure */\r
+ __IO uint32_t TIMH; /*!< Horizontal Timing Control register */\r
+ __IO uint32_t TIMV; /*!< Vertical Timing Control register */\r
+ __IO uint32_t POL; /*!< Clock and Signal Polarity Control register */\r
+ __IO uint32_t LE; /*!< Line End Control register */\r
+ __IO uint32_t UPBASE; /*!< Upper Panel Frame Base Address register */\r
+ __IO uint32_t LPBASE; /*!< Lower Panel Frame Base Address register */\r
+ __IO uint32_t CTRL; /*!< LCD Control register */\r
+ __IO uint32_t INTMSK; /*!< Interrupt Mask register */\r
+ __I uint32_t INTRAW; /*!< Raw Interrupt Status register */\r
+ __I uint32_t INTSTAT; /*!< Masked Interrupt Status register */\r
+ __O uint32_t INTCLR; /*!< Interrupt Clear register */\r
+ __I uint32_t UPCURR; /*!< Upper Panel Current Address Value register */\r
+ __I uint32_t LPCURR; /*!< Lower Panel Current Address Value register */\r
+ __I uint32_t RESERVED0[115];\r
+ __IO uint16_t PAL[256]; /*!< 256x16-bit Color Palette registers */\r
+ __I uint32_t RESERVED1[256];\r
+ __IO uint32_t CRSR_IMG[256];/*!< Cursor Image registers */\r
+ __IO uint32_t CRSR_CTRL; /*!< Cursor Control register */\r
+ __IO uint32_t CRSR_CFG; /*!< Cursor Configuration register */\r
+ __IO uint32_t CRSR_PAL0; /*!< Cursor Palette register 0 */\r
+ __IO uint32_t CRSR_PAL1; /*!< Cursor Palette register 1 */\r
+ __IO uint32_t CRSR_XY; /*!< Cursor XY Position register */\r
+ __IO uint32_t CRSR_CLIP; /*!< Cursor Clip Position register */\r
+ __I uint32_t RESERVED2[2];\r
+ __IO uint32_t CRSR_INTMSK; /*!< Cursor Interrupt Mask register */\r
+ __O uint32_t CRSR_INTCLR; /*!< Cursor Interrupt Clear register */\r
+ __I uint32_t CRSR_INTRAW; /*!< Cursor Raw Interrupt Status register */\r
+ __I uint32_t CRSR_INTSTAT;/*!< Cursor Masked Interrupt Status register */\r
+} IP_LCD_001_T;\r
+\r
+/**\r
+ * @brief LCD Palette entry format\r
+ */\r
+typedef struct {\r
+ uint32_t Rl : 5;\r
+ uint32_t Gl : 5;\r
+ uint32_t Bl : 5;\r
+ uint32_t Il : 1;\r
+ uint32_t Ru : 5;\r
+ uint32_t Gu : 5;\r
+ uint32_t Bu : 5;\r
+ uint32_t Iu : 1;\r
+} LCD_PALETTE_ENTRY_T;\r
+\r
+/**\r
+ * @brief LCD Panel type\r
+ */\r
+typedef enum IP_LCD_PANEL_OPT {\r
+ LCD_TFT = 0x02, /*!< standard TFT */\r
+ LCD_MONO_4 = 0x01, /*!< 4-bit STN mono */\r
+ LCD_MONO_8 = 0x05, /*!< 8-bit STN mono */\r
+ LCD_CSTN = 0x00 /*!< color STN */\r
+} IP_LCD_PANEL_OPT_T;\r
+\r
+/**\r
+ * @brief LCD Color Format\r
+ */\r
+typedef enum IP_LCD_COLOR_FORMAT_OPT {\r
+ LCD_COLOR_FORMAT_RGB = 0,\r
+ LCD_COLOR_FORMAT_BGR\r
+} IP_LCD_COLOR_FORMAT_OPT_T;\r
+\r
+/** LCD Interrupt control mask register bits */\r
+#define LCD_INTMSK_FUFIM 0x2 /*!< FIFO underflow interrupt enable */\r
+#define LCD_INTMSK_LNBUIM 0x4 /*!< LCD next base address update interrupt enable */\r
+#define LCD_INTMSK_VCOMPIM 0x8 /*!< Vertical compare interrupt enable */\r
+#define LCD_INTMSK_BERIM 0x10 /*!< AHB master error interrupt enable */\r
+\r
+#define CLCDC_LCDCTRL_ENABLE _BIT(0) /*!< LCD control enable bit */\r
+#define CLCDC_LCDCTRL_PWR _BIT(11) /*!< LCD control power enable bit */\r
+\r
+/**\r
+ * @brief A structure for LCD Configuration\r
+ */\r
+typedef struct {\r
+ uint8_t HBP; /*!< Horizontal back porch in clocks */\r
+ uint8_t HFP; /*!< Horizontal front porch in clocks */\r
+ uint8_t HSW; /*!< HSYNC pulse width in clocks */\r
+ uint16_t PPL; /*!< Pixels per line */\r
+ uint8_t VBP; /*!< Vertical back porch in clocks */\r
+ uint8_t VFP; /*!< Vertical front porch in clocks */\r
+ uint8_t VSW; /*!< VSYNC pulse width in clocks */\r
+ uint16_t LPP; /*!< Lines per panel */\r
+ uint8_t IOE; /*!< Invert output enable, 1 = invert */\r
+ uint8_t IPC; /*!< Invert panel clock, 1 = invert */\r
+ uint8_t IHS; /*!< Invert HSYNC, 1 = invert */\r
+ uint8_t IVS; /*!< Invert VSYNC, 1 = invert */\r
+ uint8_t ACB; /*!< AC bias frequency in clocks (not used) */\r
+ uint8_t BPP; /*!< Maximum bits per pixel the display supports */\r
+ IP_LCD_PANEL_OPT_T LCD; /*!< LCD panel type */\r
+ IP_LCD_COLOR_FORMAT_OPT_T color_format; /*!<BGR or RGB */\r
+ uint8_t Dual; /*!< Dual panel, 1 = dual panel display */\r
+} LCD_Config_T;\r
+\r
+/**\r
+ * @brief LCD Cursor Size\r
+ */\r
+typedef enum IP_LCD_CURSOR_SIZE_OPT {\r
+ LCD_CURSOR_32x32 = 0,\r
+ LCD_CURSOR_64x64\r
+} IP_LCD_CURSOR_SIZE_OPT_T;\r
+\r
+/**\r
+ * @brief Enable Controller Interrupt\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param ints : OR'ed interrupt bits to enable\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_EnableInts(IP_LCD_001_T *pLCD, uint32_t ints)\r
+{\r
+ pLCD->INTMSK = ints;\r
+}\r
+\r
+/**\r
+ * @brief Disable Controller Interrupt\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param ints : OR'ed interrupt bits to disable\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_DisableInts(IP_LCD_001_T *pLCD, uint32_t ints)\r
+{\r
+ pLCD->INTMSK = pLCD->INTMSK & ~(ints);\r
+}\r
+\r
+/**\r
+ * @brief Clear Controller Interrupt\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param ints : OR'ed interrupt bits to clear\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_ClearInts(IP_LCD_001_T *pLCD, uint32_t ints)\r
+{\r
+ pLCD->INTCLR = pLCD->INTMSK & (ints);\r
+}\r
+\r
+/**\r
+ * @brief Power-on the LCD Panel (power pin)\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_PowerOn(IP_LCD_001_T *pLCD) {\r
+ volatile int i;\r
+ pLCD->CTRL |= CLCDC_LCDCTRL_PWR;\r
+ for (i = 0; i < 1000000; i++) {}\r
+ pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Power-off the LCD Panel (power pin)\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_PowerOff(IP_LCD_001_T *pLCD) {\r
+ volatile int i;\r
+ pLCD->CTRL &= ~CLCDC_LCDCTRL_PWR;\r
+ for (i = 0; i < 1000000; i++) {}\r
+ pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Enable the LCD Controller\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Enable(IP_LCD_001_T *pLCD) {\r
+ pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Enable the LCD Controller\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Disable(IP_LCD_001_T *pLCD) {\r
+ pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame\r
+ * Buffer for Dual Panel\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param buffer : address of buffer\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_SetUPFrameBuffer(IP_LCD_001_T *pLCD, void *buffer)\r
+{\r
+ pLCD->UPBASE = (uint32_t) buffer;\r
+}\r
+\r
+/**\r
+ * @brief Set LCD Lower Panel Frame Buffer for Dual Panel\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param buffer : address of buffer\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_SetLPFrameBuffer(IP_LCD_001_T *pLCD, void *buffer)\r
+{\r
+ pLCD->LPBASE = (uint32_t) buffer;\r
+}\r
+\r
+/**\r
+ * @brief Configure Cursor\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param cursor_size : specify size of cursor\r
+ * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels\r
+ * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels\r
+ * @param sync : cursor sync mode\r
+ * - TRUE :cursor sync to the frame sync pulse\r
+ * - FALSE :cursor async mode\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Cursor_Config(IP_LCD_001_T *pLCD, IP_LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync)\r
+{\r
+ pLCD->CRSR_CFG = ((sync ? 1 : 0) << 1) | cursor_size;\r
+}\r
+\r
+/**\r
+ * @brief Get Internal Cursor Image Buffer Address\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param cursor_num : specify number of cursor is going to be written\r
+ * this param must < 4\r
+ * @return Cursor Image Buffer Address\r
+ */\r
+STATIC INLINE void *IP_LCD_Cursor_GetImageBufferAddress(IP_LCD_001_T *pLCD, uint8_t cursor_num)\r
+{\r
+ return (void *) &(pLCD->CRSR_IMG[cursor_num * 64]);\r
+}\r
+\r
+/**\r
+ * @brief Enable Cursor\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param cursor_num : specify number of cursor is going to be written\r
+ * this param must < 4\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Cursor_Enable(IP_LCD_001_T *pLCD, uint8_t cursor_num) {\r
+ pLCD->CRSR_CTRL = (cursor_num << 4) | 1;\r
+}\r
+\r
+/**\r
+ * @brief Disable Cursor\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param cursor_num : specify number of cursor is going to be written\r
+ * this param must < 4\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Cursor_Disable(IP_LCD_001_T *pLCD, uint8_t cursor_num) {\r
+ pLCD->CRSR_CTRL = (cursor_num << 4);\r
+}\r
+\r
+/**\r
+ * @brief Load Cursor Palette\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param palette_color : cursor palette 0 value\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Cursor_LoadPalette0(IP_LCD_001_T *pLCD, uint32_t palette_color)\r
+{\r
+ /* 7:0 - Red\r
+ 15:8 - Green\r
+ 23:16 - Blue\r
+ 31:24 - Not used*/\r
+ pLCD->CRSR_PAL0 = (uint32_t) palette_color;\r
+}\r
+\r
+/**\r
+ * @brief Load Cursor Palette\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param palette_color : cursor palette 1 value\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Cursor_LoadPalette1(IP_LCD_001_T *pLCD, uint32_t palette_color)\r
+{\r
+ /* 7:0 - Red\r
+ 15:8 - Green\r
+ 23:16 - Blue\r
+ 31:24 - Not used*/\r
+ pLCD->CRSR_PAL1 = (uint32_t) palette_color;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Set Cursor Position\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param x : horizontal position\r
+ * @param y : vertical position\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Cursor_SetPos(IP_LCD_001_T *pLCD, uint16_t x, uint16_t y)\r
+{\r
+ pLCD->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16);\r
+}\r
+\r
+/**\r
+ * @brief Set Cursor Clipping Position\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param x : horizontal position, should be in range: 0..63\r
+ * @param y : vertical position, should be in range: 0..63\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Cursor_SetClip(IP_LCD_001_T *pLCD, uint16_t x, uint16_t y)\r
+{\r
+ pLCD->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8);\r
+}\r
+\r
+/**\r
+ * @brief Load a color Palette entry\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param palette_addr : Address of palette table to load from\r
+ * @param index : palette entry index to load\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_LCD_Color_LoadPalette(IP_LCD_001_T *pLCD, uint32_t *palette_addr, uint32_t index)\r
+{\r
+ pLCD->PAL[index] = *(uint32_t *) palette_addr;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the LCD controller\r
+ * @param pLCD : pointer to LCD Controller Reg Struct\r
+ * @param LCD_ConfigStruct : Pointer to LCD configuration\r
+ * @return LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error\r
+ */\r
+void IP_LCD_Init(IP_LCD_001_T *pLCD, LCD_Config_T *LCD_ConfigStruct);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __LCD_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Common types used in LPC functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __LPC_TYPES_H_\r
+#define __LPC_TYPES_H_\r
+\r
+#include <stdint.h>\r
+#include <stdbool.h>\r
+\r
+/** @defgroup LPC_Types IP: LPC Common Types\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LPC_Types_Public_Types LPC Public Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Boolean Type definition\r
+ */\r
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;\r
+\r
+/**\r
+ * @brief Boolean Type definition\r
+ */\r
+#if !defined(__cplusplus)\r
+// typedef enum {false = 0, true = !false} bool;\r
+#endif\r
+\r
+/**\r
+ * @brief Flag Status and Interrupt Flag Status type definition\r
+ */\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;\r
+#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))\r
+\r
+/**\r
+ * @brief Functional State Definition\r
+ */\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))\r
+\r
+/**\r
+ * @ Status type definition\r
+ */\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;\r
+\r
+/**\r
+ * Read/Write transfer type mode (Block or non-block)\r
+ */\r
+typedef enum {\r
+ NONE_BLOCKING = 0, /**< None Blocking type */\r
+ BLOCKING, /**< Blocking type */\r
+} TRANSFER_BLOCK_T;\r
+\r
+/** Pointer to Function returning Void (any number of parameters) */\r
+typedef void (*PFV)();\r
+\r
+/** Pointer to Function returning int32_t (any number of parameters) */\r
+typedef int32_t (*PFI)();\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPC_Types_Public_Macros LPC Public Macros\r
+ * @{\r
+ */\r
+\r
+/* _BIT(n) sets the bit at position "n"\r
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:\r
+ * e.g., "(_BIT(3) | _BIT(7))".\r
+ */\r
+#undef _BIT\r
+/* Set bit macro */\r
+#define _BIT(n) (1 << (n))\r
+\r
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".\r
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:\r
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"\r
+ */\r
+#undef _SBF\r
+/* Set bit field macro */\r
+#define _SBF(f, v) ((v) << (f))\r
+\r
+/* _BITMASK constructs a symbol with 'field_width' least significant\r
+ * bits set.\r
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF\r
+ * The symbol is intended to be used to limit the bit field width\r
+ * thusly:\r
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.\r
+ * If "any_expression" results in a value that is larger than can be\r
+ * contained in 'x' bits, the bits above 'x - 1' are masked off. When\r
+ * used with the _SBF example above, the example would be written:\r
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))\r
+ * This ensures that the value written to a_reg is no wider than\r
+ * 16 bits, and makes the code easier to read and understand.\r
+ */\r
+#undef _BITMASK\r
+/* Bitmask creation macro */\r
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)\r
+\r
+/* NULL pointer */\r
+#ifndef NULL\r
+#define NULL ((void *) 0)\r
+#endif\r
+\r
+/* Number of elements in an array */\r
+#define NELEMENTS(array) (sizeof(array) / sizeof(array[0]))\r
+\r
+/* Static data/function define */\r
+#define STATIC static\r
+/* External data/function define */\r
+#define EXTERN extern\r
+\r
+#if !defined(MAX)\r
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+#endif\r
+#if !defined(MIN)\r
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Old Type Definition compatibility */\r
+/** @addtogroup LPC_Types_Public_Types\r
+ * @{\r
+ */\r
+\r
+/** LPC type for character type */\r
+typedef char CHAR;\r
+\r
+/** LPC type for 8 bit unsigned value */\r
+typedef uint8_t UNS_8;\r
+\r
+/** LPC type for 8 bit signed value */\r
+typedef int8_t INT_8;\r
+\r
+/** LPC type for 16 bit unsigned value */\r
+typedef uint16_t UNS_16;\r
+\r
+/** LPC type for 16 bit signed value */\r
+typedef int16_t INT_16;\r
+\r
+/** LPC type for 32 bit unsigned value */\r
+typedef uint32_t UNS_32;\r
+\r
+/** LPC type for 32 bit signed value */\r
+typedef int32_t INT_32;\r
+\r
+/** LPC type for 64 bit signed value */\r
+typedef int64_t INT_64;\r
+\r
+/** LPC type for 64 bit unsigned value */\r
+typedef uint64_t UNS_64;\r
+\r
+#ifdef __CODE_RED\r
+#define BOOL_32 bool\r
+#define BOOL_16 bool\r
+#define BOOL_8 bool\r
+#else\r
+/** 32 bit boolean type */\r
+typedef bool BOOL_32;\r
+\r
+/** 16 bit boolean type */\r
+typedef bool BOOL_16;\r
+\r
+/** 8 bit boolean type */\r
+typedef bool BOOL_8;\r
+#endif\r
+\r
+#ifdef __CC_ARM\r
+#define INLINE __inline\r
+#else\r
+#define INLINE inline\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __LPC_TYPES_H_ */\r
--- /dev/null
+/*\r
+ * @brief Motor Control PWM registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __MCPWM_001_H_\r
+#define __MCPWM_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_MCPWM_001 IP: MCPWM register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Motor Control PWM\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Motor Control PWM register block structure\r
+ */\r
+typedef struct { /*!< MCPWM Structure */\r
+ __I uint32_t CON; /*!< PWM Control read address */\r
+ __O uint32_t CON_SET; /*!< PWM Control set address */\r
+ __O uint32_t CON_CLR; /*!< PWM Control clear address */\r
+ __I uint32_t CAPCON; /*!< Capture Control read address */\r
+ __O uint32_t CAPCON_SET; /*!< Capture Control set address */\r
+ __O uint32_t CAPCON_CLR; /*!< Event Control clear address */\r
+ __IO uint32_t TC[3]; /*!< Timer Counter register */\r
+ __IO uint32_t LIM[3]; /*!< Limit register */\r
+ __IO uint32_t MAT[3]; /*!< Match register */\r
+ __IO uint32_t DT; /*!< Dead time register */\r
+ __IO uint32_t CCP; /*!< Communication Pattern register */\r
+ __I uint32_t CAP[3]; /*!< Capture register */\r
+ __I uint32_t INTEN; /*!< Interrupt Enable read address */\r
+ __O uint32_t INTEN_SET; /*!< Interrupt Enable set address */\r
+ __O uint32_t INTEN_CLR; /*!< Interrupt Enable clear address */\r
+ __I uint32_t CNTCON; /*!< Count Control read address */\r
+ __O uint32_t CNTCON_SET; /*!< Count Control set address */\r
+ __O uint32_t CNTCON_CLR; /*!< Count Control clear address */\r
+ __I uint32_t INTF; /*!< Interrupt flags read address */\r
+ __O uint32_t INTF_SET; /*!< Interrupt flags set address */\r
+ __O uint32_t INTF_CLR; /*!< Interrupt flags clear address */\r
+ __O uint32_t CAP_CLR; /*!< Capture clear address */\r
+} IP_MCPWM_001_T;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MCPWM_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Multi-Rate Timer (MRT) registers and driver functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __MRT_001_H_\r
+#define __MRT_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_MRT_001 IP: MRT register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief MRT register block structure\r
+ */\r
+typedef struct {\r
+ __IO uint32_t INTVAL; /*!< Timer interval register */\r
+ __O uint32_t TIMER; /*!< Timer register */\r
+ __IO uint32_t CTRL; /*!< Timer control register */\r
+ __IO uint32_t STAT; /*!< Timer status register */\r
+} IP_MRT_001_T;\r
+\r
+/**\r
+ * @brief MRT register bit fields & masks\r
+ */\r
+/* MRT Time interval register bit fields */\r
+#define IP_MRT_001_INTVAL_IVALUE (0xFFFFFF)\r
+#define IP_MRT_001_INTVAL_LOAD (1 << 31)\r
+\r
+/* MRT Control register bit fields & masks */\r
+#define IP_MRT_001_CTRL_MODE_REPEAT (0x00)\r
+#define IP_MRT_001_CTRL_MODE_ONESHOT (0x01)\r
+#define IP_MRT_001_CTRL_INTEN_MASK (0x01)\r
+#define IP_MRT_001_CTRL_MODE_POS (0x01)\r
+#define IP_MRT_001_CTRL_MODE_MASK (0x06)\r
+#define IP_MRT_001_CTRL_MODE_SHIFT(x) (x << 1)\r
+\r
+/* MRT Status register bit fields & masks */\r
+#define IP_MRT_001_STAT_INTFLAG (0x01)\r
+#define IP_MRT_001_STAT_RUNNING (0x02)\r
+\r
+/**\r
+ * @brief MRT Interrupt Modes enum\r
+ */\r
+typedef enum IP_MRT_001_MODE {\r
+ MRT_MODE_REPEAT = 0, /*!< MRT Repeat interrupt mode */\r
+ MRT_MODE_ONESHOT = 1 /*!< MRT One-shot interrupt mode */\r
+} IP_MRT_001_MODE_T;\r
+\r
+/**\r
+ * @brief Initializes the MRT\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_MRT_Init(void)\r
+{}\r
+\r
+/**\r
+ * @brief De-initializes the MRT Channel\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_MRT_DeInit(void)\r
+{}\r
+\r
+/**\r
+ * @brief Returns the timer time interval value\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return The time interval value\r
+ */\r
+STATIC INLINE uint32_t IP_MRT_GetInterval(IP_MRT_001_T *pMRT)\r
+{\r
+ return (uint32_t) pMRT->INTVAL;\r
+}\r
+\r
+/**\r
+ * @brief Sets the timer time interval value\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @param interval : Time interval value (24-bits)\r
+ * @return Nothing\r
+ * @note Setting bit 31 in time interval register causes the time interval\r
+ * to load immediately, otherwise the load will occur on the\r
+ * next timer cycle\r
+ */\r
+STATIC INLINE void IP_MRT_SetInterval(IP_MRT_001_T *pMRT, uint32_t interval)\r
+{\r
+ pMRT->INTVAL = interval;\r
+}\r
+\r
+/**\r
+ * @brief Returns the current timer value\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return The current timer value\r
+ */\r
+STATIC INLINE uint32_t IP_MRT_GetTimer(IP_MRT_001_T *pMRT)\r
+{\r
+ return (uint32_t) pMRT->TIMER;\r
+}\r
+\r
+/**\r
+ * @brief Returns true if the timer is enabled\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return True if enabled, False if not enabled\r
+ */\r
+STATIC INLINE bool IP_MRT_GetEnabled(IP_MRT_001_T *pMRT)\r
+{\r
+ return (bool) (pMRT->CTRL & IP_MRT_001_CTRL_INTEN_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Enables the timer\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_MRT_SetEnabled(IP_MRT_001_T *pMRT)\r
+{\r
+ pMRT->CTRL |= IP_MRT_001_CTRL_INTEN_MASK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the timer mode (repeat or one-shot).\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return The mode (repeat or one-shot).\r
+ */\r
+STATIC INLINE IP_MRT_001_MODE_T IP_MRT_GetMode(IP_MRT_001_T *pMRT)\r
+{\r
+ return (IP_MRT_001_MODE_T) ((pMRT->CTRL & IP_MRT_001_CTRL_MODE_MASK) >> 1);\r
+}\r
+\r
+/**\r
+ * @brief Sets the timer mode to be repeat or one-shot.\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @param mode : 0 = repeat, 1 = one-shot\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_MRT_SetMode(IP_MRT_001_T *pMRT, IP_MRT_001_MODE_T mode)\r
+{\r
+ pMRT->CTRL |= IP_MRT_001_CTRL_MODE_SHIFT(mode);\r
+}\r
+\r
+/**\r
+ * @brief Returns true if the timer is configured in repeat mode.\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return True if in repeat mode, False if in one-shot mode\r
+ */\r
+STATIC INLINE bool IP_MRT_IsRepeatMode(IP_MRT_001_T *pMRT)\r
+{\r
+ return ((pMRT->CTRL & IP_MRT_001_CTRL_MODE_MASK) > 0) ? false : true;\r
+}\r
+\r
+/**\r
+ * @brief Returns true if the timer is configured in one-shot mode.\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return True if in one-shot mode, False if in repeat mode.\r
+ */\r
+STATIC INLINE bool IP_MRT_IsOneShotMode(IP_MRT_001_T *pMRT)\r
+{\r
+ return ((pMRT->CTRL & IP_MRT_001_CTRL_MODE_MASK) > 0) ? true : false;\r
+}\r
+\r
+/**\r
+ * @brief Returns true if the timer has an interrupt pending.\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return True if interrupt is pending, False if no interrupt is pending.\r
+ */\r
+STATIC INLINE bool IP_MRT_IntPending(IP_MRT_001_T *pMRT)\r
+{\r
+ return (bool) (pMRT->STAT & IP_MRT_001_STAT_INTFLAG);\r
+}\r
+\r
+/**\r
+ * @brief Clears the pending interrupt (if any).\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_MRT_IntClear(IP_MRT_001_T *pMRT)\r
+{\r
+ pMRT->STAT |= IP_MRT_001_STAT_INTFLAG;\r
+}\r
+\r
+/**\r
+ * @brief Returns true if the timer is running.\r
+ * @param pMRT : Pointer to selected MRT Channel\r
+ * @return True if running, False if stopped.\r
+ */\r
+STATIC INLINE bool IP_MRT_Running(IP_MRT_001_T *pMRT)\r
+{\r
+ return (bool) (pMRT->STAT & IP_MRT_001_STAT_RUNNING);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MRT_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Power Management Controller registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __PMC_001_H_\r
+#define __PMC_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_PMC_001 IP: PMC register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Power Management Controller register block structure\r
+ */\r
+typedef struct { /*!< PMC Structure */\r
+ __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< Hardware sleep event enable register */\r
+ __I uint32_t RESERVED0[6];\r
+ __IO uint32_t PD0_SLEEP0_MODE; /*!< Sleep power mode register */\r
+} IP_PMC_001_T;\r
+\r
+/**\r
+ * @brief Power Management Controller power modes\r
+ */\r
+#define PMC_PWR_DEEP_SLEEP_MODE 0x3F00AA\r
+#define PMC_PWR_POWER_DOWN_MODE 0x3FFCBA\r
+#define PMC_PWR_DEEP_POWER_DOWN_MODE 0x3FFF7F\r
+\r
+/**\r
+ * @brief Set power mode in PMC block\r
+ * @param pPMC : Pointer to PMC register block\r
+ * @param PwrMode : Power mode value (PMC_PWR_DEEP_SLEEP_MODE/PMC_PWR_POWER_DOWN_MODE/PMC_PWR_DEEP_POWER_DOWN_MODE)\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_PMC_SetPowerMode(IP_PMC_001_T *pPMC, uint32_t PwrMode)\r
+{\r
+ pPMC->PD0_SLEEP0_MODE = PwrMode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __PMC_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Quadrature Encoder Interface Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __QEI_001_H_\r
+#define __QEI_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_QEI_001 IP: QEI register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Quadrature Encoder Interface\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Quadrature Encoder Interface register block structure\r
+ */\r
+typedef struct { /*!< QEI Structure */\r
+ __O uint32_t CON; /*!< Control register */\r
+ __I uint32_t STAT; /*!< Encoder status register */\r
+ __IO uint32_t CONF; /*!< Configuration register */\r
+ __I uint32_t POS; /*!< Position register */\r
+ __IO uint32_t MAXPOS; /*!< Maximum position register */\r
+ __IO uint32_t CMPOS0; /*!< position compare register 0 */\r
+ __IO uint32_t CMPOS1; /*!< position compare register 1 */\r
+ __IO uint32_t CMPOS2; /*!< position compare register 2 */\r
+ __I uint32_t INXCNT; /*!< Index count register */\r
+ __IO uint32_t INXCMP0; /*!< Index compare register 0 */\r
+ __IO uint32_t LOAD; /*!< Velocity timer reload register */\r
+ __I uint32_t TIME; /*!< Velocity timer register */\r
+ __I uint32_t VEL; /*!< Velocity counter register */\r
+ __I uint32_t CAP; /*!< Velocity capture register */\r
+ __IO uint32_t VELCOMP; /*!< Velocity compare register */\r
+ __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */\r
+ __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */\r
+ __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */\r
+ __IO uint32_t WINDOW; /*!< Index acceptance window register */\r
+ __IO uint32_t INXCMP1; /*!< Index compare register 1 */\r
+ __IO uint32_t INXCMP2; /*!< Index compare register 2 */\r
+ __I uint32_t RESERVED0[993];\r
+ __O uint32_t IEC; /*!< Interrupt enable clear register */\r
+ __O uint32_t IES; /*!< Interrupt enable set register */\r
+ __I uint32_t INTSTAT; /*!< Interrupt status register */\r
+ __I uint32_t IE; /*!< Interrupt enable register */\r
+ __O uint32_t CLR; /*!< Interrupt status clear register */\r
+ __O uint32_t SET; /*!< Interrupt status set register */\r
+} IP_QEI_001_T;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __QEI_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Register File registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __REGFILE_001_H_\r
+#define __REGFILE_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_REGFILE_001 IP: REGFILE register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Register File\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Register File register block structure\r
+ */\r
+typedef struct {\r
+#if defined(CHIP_LPC18XX)|| defined(CHIP_LPC43XX)\r
+ __IO uint32_t REGFILE[64]; /*!< General purpose storage register */\r
+#elif defined(CHIP_LPC175X_6X)|| defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X)\r
+ __IO uint32_t REGFILE[5]; /*!< General purpose storage register */\r
+#endif\r
+} IP_REGFILE_001_T;\r
+\r
+/**\r
+ * @brief Write value to General purpose registers\r
+ * @param pREG : Pointer to regfile block\r
+ * @param index : General purpose register index\r
+ * @param value : Value to write\r
+ * @return None\r
+ * @note These General purpose registers can be used to store important\r
+ * information when the main power supply is off. The value in these\r
+ * registers is not affected by chip reset. These registers are usually\r
+ * powered in the RTC power domain.\r
+ */\r
+STATIC INLINE void IP_REGFILE_Write(IP_REGFILE_001_T *pREG, int index, uint32_t value)\r
+{\r
+ pREG->REGFILE[index] = value;\r
+}\r
+\r
+/**\r
+ * @brief Read value from General purpose registers\r
+ * @param pREG : Pointer to regfile block\r
+ * @param index : General purpose register index\r
+ * @return Read value\r
+ * @note These General purpose registers can be used to store important\r
+ * information when the main power supply is off. The value in these\r
+ * registers is not affected by chip reset. These registers are usually\r
+ * powered in the RTC power domain.\r
+ */\r
+STATIC INLINE uint32_t IP_REGFILE_Read(IP_REGFILE_001_T *pREG, int index)\r
+{\r
+ return pREG->REGFILE[index];\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __REGFILE_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Repetitive Interrupt Timer registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __RITIMER_001_H_\r
+#define __RITIMER_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_RITIMER_001 IP: RITimer register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Repetitive Interrupt Timer\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Repetitive Interrupt Timer register block structure\r
+ */\r
+typedef struct { /*!< RITIMER Structure */\r
+ __IO uint32_t COMPVAL; /*!< Compare register */\r
+ __IO uint32_t MASK; /*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */\r
+ __IO uint32_t CTRL; /*!< Control register. */\r
+ __IO uint32_t COUNTER; /*!< 32-bit counter */\r
+#if defined(CHIP_LPC1347)\r
+ __IO uint32_t COMPVAL_H; /*!< Compare upper register */\r
+ __IO uint32_t MASK_H; /*!< Mask upper register */\r
+ __I uint32_t RESERVED0[1]; \r
+ __IO uint32_t COUNTER_H; /*!< Counter upper register */\r
+#endif\r
+} IP_RITIMER_001_T;\r
+\r
+/**\r
+ * @brief RITIMER register support bitfields and mask\r
+ */\r
+\r
+/*\r
+ * RIT control register\r
+ */\r
+/** Set by H/W when the counter value equals the masked compare value */\r
+#define RIT_CTRL_INT ((uint32_t) (1))\r
+/** Set timer enable clear to 0 when the counter value equals the masked compare value */\r
+#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))\r
+/** Set timer enable on debug */\r
+#define RIT_CTRL_ENBR ((uint32_t) _BIT(2))\r
+/** Set timer enable */\r
+#define RIT_CTRL_TEN ((uint32_t) _BIT(3))\r
+\r
+/**\r
+ * @brief Initialize the RIT\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @return None\r
+ */\r
+void IP_RIT_Init(IP_RITIMER_001_T *pRITimer);\r
+\r
+/**\r
+ * @brief DeInitialize the RIT\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @return None\r
+ */\r
+void IP_RIT_DeInit(IP_RITIMER_001_T *pRITimer);\r
+\r
+/**\r
+ * @brief Enable Timer\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_RIT_Enable(IP_RITIMER_001_T *pRITimer)\r
+{\r
+ pRITimer->CTRL |= RIT_CTRL_TEN;\r
+}\r
+\r
+/**\r
+ * @brief Disable Timer\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_RIT_Disable(IP_RITIMER_001_T *pRITimer)\r
+{\r
+ pRITimer->CTRL &= ~RIT_CTRL_TEN;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Timer Enable on debug\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_RIT_TimerDebugEnable(IP_RITIMER_001_T *pRITimer)\r
+{\r
+ pRITimer->CTRL |= RIT_CTRL_ENBR;\r
+}\r
+\r
+/**\r
+ * @brief Timer Disable on debug\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_RIT_TimerDebugDisable(IP_RITIMER_001_T *pRITimer)\r
+{\r
+ pRITimer->CTRL &= ~RIT_CTRL_ENBR;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Check whether interrupt flag is set or not\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @return Current interrupt status, could be SET or UNSET\r
+ */\r
+IntStatus IP_RIT_GetIntStatus(IP_RITIMER_001_T *pRITimer);\r
+\r
+/**\r
+ * @brief Set a tick value for the interrupt to time out\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @param val : value (in ticks) of the interrupt to be set\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_RIT_SetCOMPVAL(IP_RITIMER_001_T *pRITimer, uint32_t val)\r
+{\r
+ pRITimer->COMPVAL = val;\r
+}\r
+\r
+/**\r
+ * @brief Enables or clears the RIT or interrupt\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @param val : RIT to be set, one or more RIT_CTRL_* values\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_RIT_EnableCTRL(IP_RITIMER_001_T *pRITimer, uint32_t val)\r
+{\r
+ pRITimer->CTRL |= val;\r
+}\r
+\r
+/**\r
+ * @brief Get the RIT Counter value\r
+ * @param pRITimer : RIT peripheral selected\r
+ * @return the counter value\r
+ */\r
+STATIC INLINE uint32_t IP_RIT_GetCounter(IP_RITIMER_001_T *pRITimer)\r
+{\r
+ return pRITimer->COUNTER;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __RITIMER_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Real Time Clock registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __RTC_001_H_\r
+#define __RTC_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_RTC_001 IP: RTC register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Real Time Clock\r
+ * @{\r
+ */\r
+\r
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)\r
+#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */\r
+#endif\r
+/**\r
+ * @brief RTC time type option\r
+ */\r
+typedef enum IP_RTC_TIMEINDEX {\r
+ RTC_TIMETYPE_SECOND, /*!< Second */\r
+ RTC_TIMETYPE_MINUTE, /*!< Month */\r
+ RTC_TIMETYPE_HOUR, /*!< Hour */\r
+ RTC_TIMETYPE_DAYOFMONTH, /*!< Day of month */\r
+ RTC_TIMETYPE_DAYOFWEEK, /*!< Day of week */\r
+ RTC_TIMETYPE_DAYOFYEAR, /*!< Day of year */\r
+ RTC_TIMETYPE_MONTH, /*!< Month */\r
+ RTC_TIMETYPE_YEAR, /*!< Year */\r
+ RTC_TIMETYPE_LAST\r
+} IP_RTC_TIMEINDEX_T;\r
+\r
+#if RTC_EV_SUPPORT\r
+/**\r
+ * @brief Event Channel Identifier definitions\r
+ */\r
+typedef enum IP_RTC_EV_CHANNEL {\r
+ RTC_EV_CHANNEL_1 = 0,\r
+ RTC_EV_CHANNEL_2,\r
+ RTC_EV_CHANNEL_3,\r
+ RTC_EV_CHANNEL_NUM,\r
+} IP_RTC_EV_CHANNEL_T;\r
+#endif /*RTC_EV_SUPPORT*/\r
+\r
+/**\r
+ * @brief Real Time Clock register block structure\r
+ */\r
+typedef struct { /*!< RTC Structure */\r
+ __IO uint32_t ILR; /*!< Interrupt Location Register */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t CCR; /*!< Clock Control Register */\r
+ __IO uint32_t CIIR; /*!< Counter Increment Interrupt Register */\r
+ __IO uint32_t AMR; /*!< Alarm Mask Register */\r
+ __I uint32_t CTIME[3]; /*!< Consolidated Time Register 0,1,2 */\r
+ __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /*!< Timer field registers */\r
+ __IO uint32_t CALIBRATION; /*!< Calibration Value Register */\r
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X) || defined(CHIP_LPC175X_6X)\r
+ __IO uint32_t GPREG[5]; /*!< General Purpose Storage Registers */\r
+ __IO uint32_t RTC_AUXEN; /*!< RTC Auxiliary Enable register */\r
+ __IO uint32_t RTC_AUX; /*!< RTC Auxiliary control register*/\r
+#else\r
+ __I uint32_t RESERVED1[7];\r
+#endif\r
+ __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /*!< Alarm field registers */\r
+#if RTC_EV_SUPPORT\r
+ __IO uint32_t ERSTATUS; /*!< Event Monitor/Recorder Status register*/\r
+ __IO uint32_t ERCONTROL; /*!< Event Monitor/Recorder Control register*/\r
+ __I uint32_t ERCOUNTERS; /*!< Event Monitor/Recorder Counters register*/\r
+ __I uint32_t RESERVED2;\r
+ __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /*!<Event Monitor/Recorder First Stamp registers*/\r
+ __I uint32_t RESERVED3;\r
+ __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /*!<Event Monitor/Recorder Last Stamp registers*/\r
+#endif /*RTC_EV_SUPPORT*/\r
+} IP_RTC_001_T;\r
+\r
+/**\r
+ * @brief ILR register definitions\r
+ */\r
+/** ILR register mask */\r
+#define RTC_ILR_BITMASK ((0x00000003))\r
+/** Bit inform the source interrupt is counter increment*/\r
+#define RTC_IRL_RTCCIF ((1 << 0))\r
+/** Bit inform the source interrupt is alarm match*/\r
+#define RTC_IRL_RTCALF ((1 << 1))\r
+\r
+/**\r
+ * @brief CCR register definitions\r
+ */\r
+/** CCR register mask */\r
+#define RTC_CCR_BITMASK ((0x00000013))\r
+/** Clock enable */\r
+#define RTC_CCR_CLKEN ((1 << 0))\r
+/** Clock reset */\r
+#define RTC_CCR_CTCRST ((1 << 1))\r
+/** Calibration counter enable */\r
+#define RTC_CCR_CCALEN ((1 << 4))\r
+\r
+/**\r
+ * @brief CIIR and AMR register definitions\r
+ */\r
+/** Counter Increment Interrupt bit for second */\r
+#define RTC_AMR_CIIR_IMSEC ((1 << 0))\r
+/** Counter Increment Interrupt bit for minute */\r
+#define RTC_AMR_CIIR_IMMIN ((1 << 1))\r
+/** Counter Increment Interrupt bit for hour */\r
+#define RTC_AMR_CIIR_IMHOUR ((1 << 2))\r
+/** Counter Increment Interrupt bit for day of month */\r
+#define RTC_AMR_CIIR_IMDOM ((1 << 3))\r
+/** Counter Increment Interrupt bit for day of week */\r
+#define RTC_AMR_CIIR_IMDOW ((1 << 4))\r
+/** Counter Increment Interrupt bit for day of year */\r
+#define RTC_AMR_CIIR_IMDOY ((1 << 5))\r
+/** Counter Increment Interrupt bit for month */\r
+#define RTC_AMR_CIIR_IMMON ((1 << 6))\r
+/** Counter Increment Interrupt bit for year */\r
+#define RTC_AMR_CIIR_IMYEAR ((1 << 7))\r
+/** CIIR bit mask */\r
+#define RTC_AMR_CIIR_BITMASK ((0xFF))\r
+\r
+/**\r
+ * @brief RTC_AUX register definitions\r
+ */\r
+/** RTC Oscillator Fail detect flag */\r
+#define RTC_AUX_RTC_OSCF ((1 << 4))\r
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC407X_8X)\r
+/** RTC_ALARM pin control flag */\r
+#define RTC_AUX_RTC_PDOUT ((1 << 6)) \r
+#endif\r
+\r
+/**\r
+ * @brief RTC_AUXEN register definitions\r
+ */\r
+/** Oscillator Fail Detect interrupt enable*/\r
+#define RTC_AUXEN_RTC_OSCFEN ((1 << 4))\r
+\r
+/**\r
+ * @brief Consolidated Time Register 0 definitions\r
+ */\r
+#define RTC_CTIME0_SECONDS_MASK ((0x3F))\r
+#define RTC_CTIME0_MINUTES_MASK ((0x3F00))\r
+#define RTC_CTIME0_HOURS_MASK ((0x1F0000))\r
+#define RTC_CTIME0_DOW_MASK ((0x7000000))\r
+\r
+/**\r
+ * @brief Consolidated Time Register 1 definitions\r
+ */\r
+#define RTC_CTIME1_DOM_MASK ((0x1F))\r
+#define RTC_CTIME1_MONTH_MASK ((0xF00))\r
+#define RTC_CTIME1_YEAR_MASK ((0xFFF0000))\r
+\r
+/**\r
+ * @brief Consolidated Time Register 2 definitions\r
+ */\r
+#define RTC_CTIME2_DOY_MASK ((0xFFF))\r
+\r
+/**\r
+ * @brief Time Counter Group and Alarm register group\r
+ */\r
+/** SEC register mask */\r
+#define RTC_SEC_MASK (0x0000003F)\r
+/** MIN register mask */\r
+#define RTC_MIN_MASK (0x0000003F)\r
+/** HOUR register mask */\r
+#define RTC_HOUR_MASK (0x0000001F)\r
+/** DOM register mask */\r
+#define RTC_DOM_MASK (0x0000001F)\r
+/** DOW register mask */\r
+#define RTC_DOW_MASK (0x00000007)\r
+/** DOY register mask */\r
+#define RTC_DOY_MASK (0x000001FF)\r
+/** MONTH register mask */\r
+#define RTC_MONTH_MASK (0x0000000F)\r
+/** YEAR register mask */\r
+#define RTC_YEAR_MASK (0x00000FFF)\r
+\r
+#define RTC_SECOND_MAX 59 /*!< Maximum value of second */\r
+#define RTC_MINUTE_MAX 59 /*!< Maximum value of minute*/\r
+#define RTC_HOUR_MAX 23 /*!< Maximum value of hour*/\r
+#define RTC_MONTH_MIN 1 /*!< Minimum value of month*/\r
+#define RTC_MONTH_MAX 12 /*!< Maximum value of month*/\r
+#define RTC_DAYOFMONTH_MIN 1 /*!< Minimum value of day of month*/\r
+#define RTC_DAYOFMONTH_MAX 31 /*!< Maximum value of day of month*/\r
+#define RTC_DAYOFWEEK_MAX 6 /*!< Maximum value of day of week*/\r
+#define RTC_DAYOFYEAR_MIN 1 /*!< Minimum value of day of year*/\r
+#define RTC_DAYOFYEAR_MAX 366 /*!< Maximum value of day of year*/\r
+#define RTC_YEAR_MAX 4095/*!< Maximum value of year*/\r
+\r
+/**\r
+ * @brief Calibration register\r
+ */\r
+/** Calibration value */\r
+#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))\r
+/** Calibration direction */\r
+#define RTC_CALIBRATION_LIBDIR ((1 << 17))\r
+/** Calibration max value */\r
+#define RTC_CALIBRATION_MAX ((0x20000))\r
+/** Calibration definitions */\r
+#define RTC_CALIB_DIR_FORWARD ((uint8_t) (0))\r
+#define RTC_CALIB_DIR_BACKWARD ((uint8_t) (1))\r
+\r
+#if RTC_EV_SUPPORT\r
+/**\r
+ * @brief Event Monitor/Recorder Control register\r
+ */\r
+/** Event Monitor/Recorder Control register mask */\r
+#define RTC_ERCTRL_BITMASK ((uint32_t) 0xC0F03C0F)\r
+/** Enable event interrupt and wakeup */\r
+#define RTC_ERCTRL_INTWAKE_EN ((uint32_t) (1 << 0))\r
+/** Enables automatically clearing the RTC general purpose registers when an event occurs*/\r
+#define RTC_ERCTRL_GPCLEAR_EN ((uint32_t) (1 << 1))\r
+/** Select polarity for a channel event on the input pin.*/\r
+#define RTC_ERCTRL_POL_NEGATIVE (0) /* Event as positive edge */\r
+#define RTC_ERCTRL_POL_POSITIVE ((uint32_t) (1 << 2)) /* Event as negative edge */\r
+/** Enable event input.*/\r
+#define RTC_ERCTRL_INPUT_EN ((uint32_t) (1 << 3))\r
+/** Configure a specific channel */\r
+#define RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch) ((uint32_t) (0x0F << (10 * ch)))\r
+#define RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) ((uint32_t) (flag << (10 * ch)))\r
+\r
+/** Enable Event Monitor/Recorder and select its operating frequency.*/\r
+#define RTC_ERCTRL_MODE_MASK (((uint32_t) 3) << 30)\r
+#define RTC_ERCTRL_MODE_CLK_DISABLE (((uint32_t) 0) << 30)\r
+#define RTC_ERCTRL_MODE_16HZ (((uint32_t) 1) << 30)\r
+#define RTC_ERCTRL_MODE_64HZ (((uint32_t) 2) << 30)\r
+#define RTC_ERCTRL_MODE_1KHZ (((uint32_t) 3) << 30)\r
+#define RTC_ERCTRL_MODE(n) (((uint32_t) n) << 30)\r
+\r
+/**\r
+ * @brief Event Monitor/Recorder Status register\r
+ */\r
+/** Event Flag for a specific channel */\r
+#define RTC_ERSTATUS_CHANNEL_EV(ch) ((uint32_t) (1 << ch)) /* At least 1 event has occurred on a specific channel */\r
+/** General purpose registers have been asynchronous cleared. */\r
+#define RTC_ERSTATUS_GPCLEARED ((uint32_t) (1 << 3))\r
+/** An interrupt/wakeup request is pending.*/\r
+#define RTC_ERSTATUS_WAKEUP ((uint32_t) (((uint32_t) 1) << 31))\r
+\r
+/**\r
+ * @brief Event Monitor/Recorder Counter register\r
+ */\r
+/** Value of the counter for Events occurred on a specific channel */\r
+#define RTC_ER_COUNTER(ch, n) ((uint32_t) ((n >> (8 * ch)) & 0x07))\r
+\r
+/**\r
+ * @brief Event Monitor/Recorder TimeStamp register\r
+ */\r
+#define RTC_ER_TIMESTAMP_SEC(n) ((uint32_t) (n & 0x3F))\r
+#define RTC_ER_TIMESTAMP_MIN(n) ((uint32_t) ((n >> 6) & 0x3F))\r
+#define RTC_ER_TIMESTAMP_HOUR(n) ((uint32_t) ((n >> 12) & 0x1F))\r
+#define RTC_ER_TIMESTAMP_DOY(n) ((uint32_t) ((n >> 17) & 0x1FF))\r
+\r
+/**\r
+ * @brief Event Monitor/Recorder Mode definition\r
+ */\r
+typedef enum IP_RTC_EV_MODE {\r
+ RTC_EV_MODE_DISABLE = 0, /*!< Event Monitor/Recoder is disabled */\r
+ RTC_EV_MODE_ENABLE_16HZ = 1, /*!< Event Monitor/Recoder is enabled and use 16Hz sample clock for event input */\r
+ RTC_EV_MODE_ENABLE_64HZ = 2, /*!< Event Monitor/Recoder is enabled and use 64Hz sample clock for event input */\r
+ RTC_EV_MODE_ENABLE_1KHZ = 3, /*!< Event Monitor/Recoder is enabled and use 1kHz sample clock for event input */\r
+ RTC_EV_MODE_LAST,\r
+} IP_RTC_EV_MODE_T;\r
+\r
+/**\r
+ * @brief Event Monitor/Recorder Timestamp structure\r
+ */\r
+typedef struct {\r
+ uint8_t sec; /*!< Second */\r
+ uint8_t min; /*!< Minute */\r
+ uint8_t hour; /*!< Hour */\r
+ uint16_t dayofyear; /*!< Day of year */\r
+} IP_RTC_EV_TIMESTAMP_T;\r
+\r
+#endif /*RTC_EV_SUPPORT*/\r
+\r
+/**\r
+ * @brief RTC enumeration\r
+ */\r
+\r
+/** @brief RTC interrupt source */\r
+typedef enum IP_RTC_INT_OPT {\r
+ RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */\r
+ RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */\r
+} IP_RTC_INT_OPT_T;\r
+\r
+typedef struct {\r
+ uint32_t time[RTC_TIMETYPE_LAST];\r
+} IP_RTC_TIME_T;\r
+\r
+/**\r
+ * @brief Initialize the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @return None\r
+ */\r
+void IP_RTC_Init(IP_RTC_001_T *pRTC);\r
+\r
+/**\r
+ * @brief De-initialize the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_RTC_DeInit(IP_RTC_001_T *pRTC)\r
+{\r
+ pRTC->CCR = 0x00;\r
+}\r
+\r
+/**\r
+ * @brief Reset clock tick counter in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @return None\r
+ */\r
+void IP_RTC_ResetClockTickCounter(IP_RTC_001_T *pRTC);\r
+\r
+/**\r
+ * @brief Start/Stop RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param NewState : ENABLE or DISABLE\r
+ * @return None\r
+ */\r
+void IP_RTC_Enable(IP_RTC_001_T *pRTC, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Enable/Disable Counter increment interrupt for a time type in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param cntrMask : Or'ed bit values for time types (RTC_AMR_CIIR_IM*)\r
+ * @param NewState : ENABLE or DISABLE\r
+ * @return None\r
+ */\r
+void IP_RTC_CntIncrIntConfig(IP_RTC_001_T *pRTC, uint32_t cntrMask, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Enable/Disable Alarm interrupt for a time type in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param alarmMask : Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)\r
+ * @param NewState : ENABLE or DISABLE\r
+ * @return None\r
+ */\r
+void IP_RTC_AlarmIntConfig(IP_RTC_001_T *pRTC, uint32_t alarmMask, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Set current time value for a time type in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param Timetype : time field index type to set\r
+ * @param TimeValue : Value to palce in time field\r
+ * @return None\r
+ */\r
+void IP_RTC_SetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue);\r
+\r
+/**\r
+ * @brief Get current time value for a type time type\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param Timetype : Time field index type to get\r
+ * @return Value of time field according to specified time type\r
+ */\r
+uint32_t IP_RTC_GetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype);\r
+\r
+/**\r
+ * @brief Set full time in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param pFullTime : Pointer to full time data\r
+ * @return None\r
+ */\r
+void IP_RTC_SetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);\r
+\r
+/**\r
+ * @brief Get full time from the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param pFullTime : Pointer to full time record to fill\r
+ * @return None\r
+ */\r
+void IP_RTC_GetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);\r
+\r
+/**\r
+ * @brief Set alarm time value for a time type\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param Timetype : Time index field to set\r
+ * @param ALValue : Alarm time value to set\r
+ * @return None\r
+ */\r
+void IP_RTC_SetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue);\r
+\r
+/**\r
+ * @brief Get alarm time value for a time type\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param Timetype : Time index field to get\r
+ * @return Value of Alarm time according to specified time type\r
+ */\r
+uint32_t IP_RTC_GetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype);\r
+\r
+/**\r
+ * @brief Set full alarm time in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param pFullTime : Pointer to full time record to set alarm\r
+ * @return None\r
+ */\r
+void IP_RTC_SetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);\r
+\r
+/**\r
+ * @brief Get full alarm time in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param pFullTime : Pointer to full time record to fill\r
+ * @return None\r
+ */\r
+void IP_RTC_GetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime);\r
+\r
+/**\r
+ * @brief Enable/Disable calibration counter in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param NewState : New State of this function, should be:\r
+ * - ENABLE :The calibration counter is enabled and counting\r
+ * - DISABLE :The calibration counter is disabled and reset to zero\r
+ * @return None\r
+ */\r
+void IP_RTC_CalibCounterCmd(IP_RTC_001_T *pRTC, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Configures Calibration in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param CalibValue : Calibration value, should be in range from 0 to 131,072\r
+ * @param CalibDir : Calibration Direction, should be:\r
+ * - RTC_CALIB_DIR_FORWARD :Forward calibration\r
+ * - RTC_CALIB_DIR_BACKWARD :Backward calibration\r
+ * @return None\r
+ */\r
+void IP_RTC_CalibConfig(IP_RTC_001_T *pRTC, uint32_t CalibValue, uint8_t CalibDir);\r
+\r
+/**\r
+ * @brief Clear specified Location interrupt pending in the RTC peripheral\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param IntType : Interrupt location type, should be:\r
+ * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending.\r
+ * - RTC_INT_ALARM :Clear alarm interrupt pending\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_RTC_ClearIntPending(IP_RTC_001_T *pRTC, uint32_t IntType)\r
+{\r
+ pRTC->ILR = IntType;\r
+}\r
+\r
+/**\r
+ * @brief Check whether if specified location interrupt in the\r
+ * RTC peripheral is set or not\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param IntType : Interrupt location type, should be:\r
+ * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.\r
+ * - RTC_INT_ALARM: Alarm generated an interrupt.\r
+ * @return Current state of specified interrupt in RTC peripheral, SET or RESET\r
+ */\r
+STATIC INLINE IntStatus IP_RTC_GetIntPending(IP_RTC_001_T *pRTC, uint32_t IntType)\r
+{\r
+ return (pRTC->ILR & IntType) ? SET : RESET;\r
+}\r
+\r
+#if RTC_EV_SUPPORT\r
+\r
+/**\r
+ * @brief Configure a specific event channel\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param ch : channel number\r
+ * @param flag : configuration flag\r
+ * @return None\r
+ * @note Flags is or-ed bit values of RTC_ERCTRL_INTWAKE_EN,RTC_ERCTRL_GPCLEAR_EN,\r
+ * RTC_ERCTRL_POL_POSITIVE and RTC_ERCTRL_INPUT_EN.\r
+ */\r
+STATIC INLINE void IP_RTC_EV_Config(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch, uint32_t flag)\r
+{\r
+ uint32_t temp;\r
+\r
+ temp = pRTC->ERCONTROL & (~(RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch))) & RTC_ERCTRL_BITMASK;\r
+ pRTC->ERCONTROL = temp | (RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) & RTC_ERCTRL_BITMASK);\r
+}\r
+\r
+/**\r
+ * @brief Enable/Disable Event Monitor/Recorder and select its operating clock\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param mode : selected mode\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_RTC_EV_SetMode(IP_RTC_001_T *pRTC, IP_RTC_EV_MODE_T mode)\r
+{\r
+ uint32_t temp;\r
+\r
+ temp = pRTC->ERCONTROL & (~RTC_ERCTRL_MODE_MASK) & RTC_ERCTRL_BITMASK;\r
+ pRTC->ERCONTROL = temp | RTC_ERCTRL_MODE(mode);\r
+}\r
+\r
+/**\r
+ * @brief Get Event Monitor/Recorder Status\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @return Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP\r
+ */\r
+STATIC INLINE uint32_t IP_RTC_EV_GetStatus(IP_RTC_001_T *pRTC)\r
+{\r
+ return pRTC->ERSTATUS & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);\r
+}\r
+\r
+/**\r
+ * @brief Clear Event Monitor/Recorder Status\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param flag : Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_RTC_EV_ClearStatus(IP_RTC_001_T *pRTC, uint32_t flag)\r
+{\r
+ pRTC->ERSTATUS = flag & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);\r
+}\r
+\r
+/**\r
+ * @brief Get status of a specific event channel\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param ch : channel number\r
+ * @return SET (At least 1 event occurred on the channel), RESET: no event occured.\r
+ */\r
+STATIC INLINE FlagStatus IP_RTC_EV_GetChannelStatus(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch)\r
+{\r
+ return (pRTC->ERSTATUS & RTC_ERSTATUS_CHANNEL_EV(ch)) ? SET : RESET;\r
+}\r
+\r
+/**\r
+ * @brief Clear status of a specific event channel\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param ch : channel number\r
+ * @return Nothing.\r
+ */\r
+STATIC INLINE void IP_RTC_EV_ClearChannelStatus(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch)\r
+{\r
+ pRTC->ERSTATUS = RTC_ERSTATUS_CHANNEL_EV(ch);\r
+}\r
+\r
+/**\r
+ * @brief Get counter value of a specific event channel\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param ch : channel number\r
+ * @return counter value\r
+ */\r
+STATIC INLINE uint8_t IP_RTC_EV_GetCounter(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch)\r
+{\r
+ return RTC_ER_COUNTER(ch, pRTC->ERCOUNTERS);\r
+}\r
+\r
+/**\r
+ * @brief Get first time stamp of a specific event channel\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param ch : channel number\r
+ * @param pTimeStamp : pointer to Timestamp buffer\r
+ * @return Nothing.\r
+ */\r
+void IP_RTC_EV_GetFirstTimeStamp(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch, IP_RTC_EV_TIMESTAMP_T *pTimeStamp);\r
+\r
+/**\r
+ * @brief Get last time stamp of a specific event channel\r
+ * @param pRTC : pointer to RTC peripheral block\r
+ * @param ch : channel number\r
+ * @param pTimeStamp : pointer to Timestamp buffer\r
+ * @return Nothing.\r
+ */\r
+void IP_RTC_EV_GetLastTimeStamp(IP_RTC_001_T *pRTC, IP_RTC_EV_CHANNEL_T ch, IP_RTC_EV_TIMESTAMP_T *pTimeStamp);\r
+\r
+#endif /*RTC_EV_SUPPORT*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __RTC_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief State Configurable Timer registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SCT_001_H_\r
+#define __SCT_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_SCT_001 IP: SCT register block and driver\r
+ * @ingroup IP_Drivers\r
+ * State Configurable Timer\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief SCT Module configuration\r
+ */\r
+#define CONFIG_SCT_nEV (16) /*!< Number of events */\r
+#define CONFIG_SCT_nRG (16) /*!< Number of match/compare registers */\r
+#define CONFIG_SCT_nOU (16) /*!< Number of outputs */\r
+\r
+/**\r
+ * @brief State Configurable Timer register block structure\r
+ */\r
+typedef struct {\r
+ __IO uint32_t CONFIG; /*!< Configuration Register */\r
+ union {\r
+ __IO uint32_t CTRL_U; /*!< Control Register */\r
+ struct {\r
+ __IO uint16_t CTRL_L; /*!< Low control register */\r
+ __IO uint16_t CTRL_H; /*!< High control register */\r
+ };\r
+\r
+ };\r
+\r
+ __IO uint16_t LIMIT_L; /*!< limit register for counter L */\r
+ __IO uint16_t LIMIT_H; /*!< limit register for counter H */\r
+ __IO uint16_t HALT_L; /*!< halt register for counter L */\r
+ __IO uint16_t HALT_H; /*!< halt register for counter H */\r
+ __IO uint16_t STOP_L; /*!< stop register for counter L */\r
+ __IO uint16_t STOP_H; /*!< stop register for counter H */\r
+ __IO uint16_t START_L; /*!< start register for counter L */\r
+ __IO uint16_t START_H; /*!< start register for counter H */\r
+ uint32_t RESERVED1[10]; /*!< 0x03C reserved */\r
+ union {\r
+ __IO uint32_t COUNT_U; /*!< counter register */\r
+ struct {\r
+ __IO uint16_t COUNT_L; /*!< counter register for counter L */\r
+ __IO uint16_t COUNT_H; /*!< counter register for counter H */\r
+ };\r
+\r
+ };\r
+\r
+ __IO uint16_t STATE_L; /*!< state register for counter L */\r
+ __IO uint16_t STATE_H; /*!< state register for counter H */\r
+ __I uint32_t INPUT; /*!< input register */\r
+ __IO uint16_t REGMODE_L; /*!< match - capture registers mode register L */\r
+ __IO uint16_t REGMODE_H; /*!< match - capture registers mode register H */\r
+ __IO uint32_t OUTPUT; /*!< output register */\r
+ __IO uint32_t OUTPUTDIRCTRL; /*!< output counter direction Control Register */\r
+ __IO uint32_t RES; /*!< conflict resolution register */\r
+ __IO uint32_t DMA0REQUEST; /*!< DMA0 Request Register */\r
+ __IO uint32_t DMA1REQUEST; /*!< DMA1 Request Register */\r
+ uint32_t RESERVED2[35];\r
+ __IO uint32_t EVEN; /*!< event enable register */\r
+ __IO uint32_t EVFLAG; /*!< event flag register */\r
+ __IO uint32_t CONEN; /*!< conflict enable register */\r
+ __IO uint32_t CONFLAG; /*!< conflict flag register */\r
+ union {\r
+ __IO union { /*!< ... Match / Capture value */\r
+ uint32_t U; /*!< SCTMATCH[i].U Unified 32-bit register */\r
+ struct {\r
+ uint16_t L; /*!< SCTMATCH[i].L Access to L value */\r
+ uint16_t H; /*!< SCTMATCH[i].H Access to H value */\r
+ };\r
+\r
+ } MATCH[CONFIG_SCT_nRG];\r
+\r
+ __I union {\r
+ uint32_t U; /*!< SCTCAP[i].U Unified 32-bit register */\r
+ struct {\r
+ uint16_t L; /*!< SCTCAP[i].L Access to L value */\r
+ uint16_t H; /*!< SCTCAP[i].H Access to H value */\r
+ };\r
+\r
+ } CAP[CONFIG_SCT_nRG];\r
+\r
+ };\r
+\r
+ uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /*!< ...-0x17C reserved */\r
+ union {\r
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /*!< 0x180-... Match Value L counter */\r
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /*!< 0x180-... Capture Value L counter */\r
+ };\r
+\r
+ uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /*!< ...-0x1BE reserved */\r
+ union {\r
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Match Value H counter */\r
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Capture Value H counter */\r
+ };\r
+\r
+ uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /*!< ...-0x1FE reserved */\r
+ union {\r
+ __IO union { /*!< 0x200-... Match Reload / Capture Control value */\r
+ uint32_t U; /*!< SCTMATCHREL[i].U Unified 32-bit register */\r
+ struct {\r
+ uint16_t L; /*!< SCTMATCHREL[i].L Access to L value */\r
+ uint16_t H; /*!< SCTMATCHREL[i].H Access to H value */\r
+ };\r
+\r
+ } MATCHREL[CONFIG_SCT_nRG];\r
+\r
+ __IO union {\r
+ uint32_t U; /*!< SCTCAPCTRL[i].U Unified 32-bit register */\r
+ struct {\r
+ uint16_t L; /*!< SCTCAPCTRL[i].L Access to L value */\r
+ uint16_t H; /*!< SCTCAPCTRL[i].H Access to H value */\r
+ };\r
+\r
+ } CAPCTRL[CONFIG_SCT_nRG];\r
+\r
+ };\r
+\r
+ uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /*!< ...-0x27C reserved */\r
+ union {\r
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Match Reload value L counter */\r
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Capture Control value L counter */\r
+ };\r
+\r
+ uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /*!< ...-0x2BE reserved */\r
+ union {\r
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Match Reload value H counter */\r
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Capture Control value H counter */\r
+ };\r
+\r
+ uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /*!< ...-0x2FE reserved */\r
+ __IO struct { /*!< 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/\r
+ uint32_t STATE; /*!< Event State Register */\r
+ uint32_t CTRL; /*!< Event Control Register */\r
+ } EVENT[CONFIG_SCT_nEV];\r
+\r
+ uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /*!< ...-0x4FC reserved */\r
+ __IO struct { /*!< 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */\r
+ uint32_t SET; /*!< Output n Set Register */\r
+ uint32_t CLR; /*!< Output n Clear Register */\r
+ } OUT[CONFIG_SCT_nOU];\r
+\r
+ uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /*!< ...-0x7F8 reserved */\r
+ __I uint32_t MODULECONTENT; /*!< 0x7FC Module Content */\r
+} IP_SCT_001_T;\r
+\r
+/**\r
+ * @brief Macro defines for SCT configuration register\r
+ */\r
+#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /*!< Operate as 2 16-bit counters */\r
+#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /*!< Operate as 1 32-bit counter */\r
+\r
+#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /*!< Bus clock */\r
+#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /*!< SCT clock */\r
+#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /*!< Input clock selected in CLKSEL field */\r
+#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /*!< Input clock edge selected in CLKSEL field */\r
+\r
+#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /*!< Operate as 1 32-bit counter */\r
+#define SCT_CONFIG_NORELOADH (0x1 << 8) /*!< Operate as 1 32-bit counter */\r
+\r
+/*\r
+ * @brief Macro defines for SCT control register\r
+ */\r
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for low or unified counter */\r
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1\r
+\r
+#define SCT_CTRL_STOP_L (1 << 1) /*!< Stop low counter */\r
+#define SCT_CTRL_HALT_L (1 << 2) /*!< Halt low counter */\r
+#define SCT_CTRL_CLRCTR_L (1 << 3) /*!< Clear low or unified counter */\r
+#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /*!< Bidirectional bit */\r
+#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /*!< Prescale clock for low or unified counter */\r
+\r
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /*!< Direction for high counter */\r
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1\r
+#define SCT_CTRL_STOP_H (1 << 17) /*!< Stop high counter */\r
+#define SCT_CTRL_HALT_H (1 << 18) /*!< Halt high counter */\r
+#define SCT_CTRL_CLRCTR_H (1 << 19) /*!< Clear high counter */\r
+#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)\r
+#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /*!< Prescale clock for high counter */\r
+\r
+/*\r
+ * @brief Macro defines for SCT Conflict resolution register\r
+ */\r
+#define SCT_RES_NOCHANGE (0)\r
+#define SCT_RES_SET_OUTPUT (1)\r
+#define SCT_RES_CLEAR_OUTPUT (2)\r
+#define SCT_RES_TOGGLE_OUTPUT (3)\r
+\r
+/**\r
+ * @brief Set the value in SCT unified count register\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param count : SCT count value\r
+ * @return Nothing\r
+ * @note Writes 32-bit value into SCT unified count register\r
+ */\r
+STATIC INLINE void IP_SCT_SetCount(IP_SCT_001_T *pSCT, uint32_t count)\r
+{\r
+ pSCT->COUNT_U = count;\r
+}\r
+\r
+/**\r
+ * @brief Set the value in SCT Lower count register\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param count : SCT count value\r
+ * @return Nothing\r
+ * @note Writes 16-bit value into SCT Lower count register\r
+ */\r
+STATIC INLINE void IP_SCT_SetCountL(IP_SCT_001_T *pSCT, uint16_t count)\r
+{\r
+ pSCT->COUNT_L = count;\r
+}\r
+\r
+/**\r
+ * @brief Set the value in SCT Higher count register\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param count : SCT count value\r
+ * @return Nothing\r
+ * @note Writes 16-bit value into SCT Higher count register\r
+ */\r
+STATIC INLINE void IP_SCT_SetCountH(IP_SCT_001_T *pSCT, uint16_t count)\r
+{\r
+ pSCT->COUNT_H = count;\r
+}\r
+\r
+/**\r
+ * @brief Set the match value in SCT Unified match register\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param n : Match register number\r
+ * @param count : SCT match count value\r
+ * @return Nothing\r
+ * @note Writes 32-bit value into SCT unified match register\r
+ */\r
+STATIC INLINE void IP_SCT_SetMatchCount(IP_SCT_001_T *pSCT, uint32_t n, uint32_t count)\r
+{\r
+ pSCT->MATCH[n].U = count;\r
+}\r
+\r
+/**\r
+ * @brief Set the match reload value in SCT Unified match reload register\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param n : Match register number\r
+ * @param count : SCT match reload count value\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SCT_SetMatchReload(IP_SCT_001_T *pSCT, uint32_t n, uint32_t count)\r
+{\r
+ pSCT->MATCHREL[n].U = count;\r
+}\r
+\r
+/**\r
+ * @brief Enable the interrupt for the specified event\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param evt : Event value\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SCT_EventIntEnable(IP_SCT_001_T *pSCT, uint32_t evt)\r
+{\r
+ pSCT->EVEN |= evt;\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt for the specified event\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param evt : Event value\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SCT_EventIntDisable(IP_SCT_001_T *pSCT, uint32_t evt)\r
+{\r
+ pSCT->EVEN &= ~(evt);\r
+}\r
+\r
+/**\r
+ * @brief Clear the specified event flag\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param evt : Event value\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SCT_ClearEventFlag(IP_SCT_001_T *pSCT, uint32_t evt)\r
+{\r
+ pSCT->EVFLAG |= evt;\r
+}\r
+\r
+/**\r
+ * @brief Configure SCT\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param value : SCT Configuration register value\r
+ * @return Nothing\r
+ * @note Initialise the SCT configuration register with the \a value\r
+ */\r
+void IP_SCT_Config(IP_SCT_001_T *pSCT, uint32_t value);\r
+\r
+/**\r
+ * @brief Set or Clear the Control register\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param value : SCT Control register value\r
+ * @param ena : ENABLE - To set the fields specified by value\r
+ * : DISABLE - To clear the field specified by value\r
+ * @return Nothing\r
+ * @note Set or clear the control register bits as specified by \a value.\r
+ * If \a ena is set to ENABLE, the mentioned register fields\r
+ * will be set. If a\ ena is set to DISABLE, the mentioned register\r
+ * fields will be cleared\r
+ */\r
+void IP_SCT_ControlSetClr(IP_SCT_001_T *pSCT, uint32_t value, FunctionalState ena);\r
+\r
+/**\r
+ * @brief Set the conflict resolution\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param outnum : Output number\r
+ * @param value : Output value\r
+ * - SCT_RES_NOCHANGE :No change\r
+ * - SCT_RES_SET_OUTPUT :Set output\r
+ * - SCT_RES_CLEAR_OUTPUT :Clear output\r
+ * - SCT_RES_TOGGLE_OUTPUT :Toggle output\r
+ * : SCT_RES_NOCHANGE\r
+ * : DISABLE - To clear the field specified by value\r
+ * @return Nothing\r
+ * @note Set conflict resolution value for the output \a outnum\r
+ */\r
+void IP_SCT_ConflictResolutionSet(IP_SCT_001_T *pSCT, uint8_t outnum, uint8_t value);\r
+\r
+/**\r
+ * @brief Clear the SCT event flag\r
+ * @param pSCT : Pointer to SCT register block\r
+ * @param even_num : SCT Event number\r
+ * @return Nothing\r
+ * @note Clear the SCT event flag for the event \a even_num\r
+ */\r
+void IP_SCT_EventFlagClear(IP_SCT_001_T *pSCT, uint8_t even_num);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SCT_001_H_ */\r
--- /dev/null
+/*
+ * @brief SD Card Interface Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SDC_001_H_
+#define __SDC_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_SDC_001 IP: SDC register block and driver
+ * @ingroup IP_Drivers
+ * SD/MMC card Interface
+ * @{
+ */
+
+/**
+ * @brief SD/MMC card Interface (SDC) register block structure
+ */
+typedef struct {
+ __IO uint32_t POWER; /*!< Power Control register */
+ __IO uint32_t CLOCK; /*!< Clock control regsiter */
+ __IO uint32_t ARGUMENT; /*!< Command argument register */
+ __IO uint32_t COMMAND; /*!< Command register */
+ __I uint32_t RESPCMD; /*!< Command response register */
+ __I uint32_t RESPONSE[4]; /*!< Response registers */
+ __IO uint32_t DATATIMER; /*!< Data timer register */
+ __IO uint32_t DATALENGTH; /*!< Data length register */
+ __IO uint32_t DATACTRL; /*!< Data control register */
+ __I uint32_t DATACNT; /*!< Data count register */
+ __I uint32_t STATUS; /*!< Status register */
+ __O uint32_t CLEAR; /*!< Clear register */
+ __IO uint32_t MASK0; /*!< Mask 0 register */
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT; /*!< FIFO count register */
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO[16]; /*!< FIFO registers */
+} IP_SDC_001_T;
+
+/**
+ * @brief SDC Power Control Register bit definitions
+ */
+/** SDC Power Control Register Bitmask */
+#define SDC_PWR_BITMASK ((uint32_t) 0xC3)
+/** SDC Power Control Bit Mask */
+#define SDC_PWR_CTRL_BITMASK (((uint32_t) 0x03) << 0)
+/** SDC Power Control */
+#define SDC_PWR_CTRL(n) (((uint32_t) (n & 0x03)) << 0)
+/** SD_CMD Output Control */
+#define SDC_PWR_OPENDRAIN (((uint32_t) 1) << 6)
+/** Rod Control */
+#define SDC_PWR_ROD (((uint32_t) 1) << 7)
+
+/**
+ * @brief SDC Clock Control Register bit definitions
+ */
+/** SDC Clock Control Register Bitmask */
+#define SDC_CLOCK_BITMASK ((uint32_t) 0xFFF)
+/** SDC Clock Divider Bitmask */
+#define SDC_CLOCK_CLKDIV_BITMASK (((uint32_t) 0xFF ) << 0)
+/** Set SDC Clock Divide value */
+#define SDC_CLOCK_CLKDIV(n) (((uint32_t) (n & 0x0FF)) << 0)
+
+/**
+ * @brief SDC Command Register bit definitions
+ */
+/** SDC Command Register Bitmask */
+#define SDC_COMMAND_BITMASK ((uint32_t) 0x7FF)
+/** SDC Command Index Bitmask */
+#define SDC_COMMAND_INDEX_BITMASK ((uint32_t) 0x3F)
+/** Set SDC Command Index */
+#define SDC_COMMAND_INDEX(n) ((uint32_t) n & 0x3F)
+/** No response is expected */
+#define SDC_COMMAND_NO_RSP (((uint32_t) 0 ) << 6)
+/** Short response is expected */
+#define SDC_COMMAND_SHORT_RSP (((uint32_t) 1 ) << 6)
+/** Long response is expected */
+#define SDC_COMMAND_LONG_RSP (((uint32_t) 3 ) << 6)
+/** Response bit mask */
+#define SDC_COMMAND_RSP_BITMASK (((uint32_t) 3 ) << 6)
+/** Mark that command timer is disabled and CPSM waits for interrupt request */
+#define SDC_COMMAND_INTERRUPT (((uint32_t) 1 ) << 8)
+/** Mark that CPSM waits for CmdPend before starting sending a command*/
+#define SDC_COMMAND_PENDING (((uint32_t) 1 ) << 9)
+/** Enable CPSM */
+#define SDC_COMMAND_ENABLE (((uint32_t) 1 ) << 10)
+
+/**
+ * @brief SDC Command Response Register bit definitions
+ */
+/** SDC Command Response value */
+#define SDC_RESPCOMMAND_VAL(n) ((uint32_t) n & 0x3F)
+
+/**
+ * @brief SDC Data Length Register bit definitions
+ */
+/** SDC Data Length set */
+#define SDC_DATALENGTH_LEN(n) ((uint32_t) n & 0xFFFF)
+
+/**
+ * @brief SDC Data Control Register bit definitions
+ */
+/** SDC Data Control Register Bitmask */
+#define SDC_DATACTRL_BITMASK ((uint32_t) 0xFF)
+/** Enable Data Transfer */
+#define SDC_DATACTRL_ENABLE (((uint32_t) 1 ) << 0)
+/** Mark that Data is transfer from card to controller */
+#define SDC_DATACTRL_DIR_FROMCARD (((uint32_t) 1 ) << 1)
+/** Mark that Data is transfer from controller to card */
+#define SDC_DATACTRL_DIR_TOCARD ((uint32_t) 0)
+/** Mark that the transfer mode is Stream Data Transfer */
+#define SDC_DATACTRL_XFER_MODE_STREAM (((uint32_t) 1 ) << 2)
+/** Mark that the transfer mode is Block Data Transfer */
+#define SDC_DATACTRL_XFER_MODE_BLOCK ((uint32_t) 0)
+/** Enable DMA */
+#define SDC_DATACTRL_DMA_ENABLE (((uint32_t) 1 ) << 3)
+/** Set Data Block size */
+#define SDC_DATACTRL_BLOCKSIZE(n) (((uint32_t) (n & 0x0F) ) << 4)
+/** Get Data Block size value */
+#define SDC_DATACTRL_BLOCKSIZE_VAL(n) (((uint32_t) 1) << n)
+
+/**
+ * @brief SDC Data Counter Register bit definitions
+ */
+#define SDC_DATACNT_VAL(n) ((uint32_t) n & 0xFFFF)
+
+/**
+ * @brief SDC Status Register bit definitions
+ */
+/** Command Response received (CRC check failed) */
+#define SDC_STATUS_CMDCRCFAIL (((uint32_t) 1 ) << 0)
+/** Data block sent/received (CRC check failed). */
+#define SDC_STATUS_DATACRCFAIL (((uint32_t) 1 ) << 1)
+/** Command response timeout.. */
+#define SDC_STATUS_CMDTIMEOUT (((uint32_t) 1 ) << 2)
+/** Data timeout. */
+#define SDC_STATUS_DATATIMEOUT (((uint32_t) 1 ) << 3)
+/** Transmit FIFO underrun error. */
+#define SDC_STATUS_TXUNDERRUN (((uint32_t) 1 ) << 4)
+/** Receive FIFO overrun error. */
+#define SDC_STATUS_RXOVERRUN (((uint32_t) 1 ) << 5)
+/** Command response received (CRC check passed). */
+#define SDC_STATUS_CMDRESPEND (((uint32_t) 1 ) << 6)
+/** Command sent (no response required).*/
+#define SDC_STATUS_CMDSENT (((uint32_t) 1 ) << 7)
+/** Data end (data counter is zero).*/
+#define SDC_STATUS_DATAEND (((uint32_t) 1 ) << 8)
+/** Start bit not detected on all data signals in wide bus mode..*/
+#define SDC_STATUS_STARTBITERR (((uint32_t) 1 ) << 9)
+/** Data block sent/received (CRC check passed).*/
+#define SDC_STATUS_DATABLOCKEND (((uint32_t) 1 ) << 10)
+/** Command transfer in progress.*/
+#define SDC_STATUS_CMDACTIVE (((uint32_t) 1 ) << 11)
+/** Data transmit in progress.*/
+#define SDC_STATUS_TXACTIVE (((uint32_t) 1 ) << 12)
+/** Data receive in progress.*/
+#define SDC_STATUS_RXACTIVE (((uint32_t) 1 ) << 13)
+/** Transmit FIFO half empty.*/
+#define SDC_STATUS_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
+/** Receive FIFO half full.*/
+#define SDC_STATUS_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
+/** Transmit FIFO full.*/
+#define SDC_STATUS_TXFIFOFULL (((uint32_t) 1 ) << 16)
+/** Receive FIFO full.*/
+#define SDC_STATUS_RXFIFOFULL (((uint32_t) 1 ) << 17)
+/** Transmit FIFO empty.*/
+#define SDC_STATUS_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
+/** Receive FIFO empty.*/
+#define SDC_STATUS_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
+/** Data available in transmit FIFO.*/
+#define SDC_STATUS_TXDATAAVLBL (((uint32_t) 1 ) << 20)
+/** Data available in receive FIFO.*/
+#define SDC_STATUS_RXDATAAVLBL (((uint32_t) 1 ) << 21)
+/** Command Error Status */
+#define SDC_STATUS_CMDERR (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)
+/** Data Error Status */
+#define SDC_STATUS_DATAERR (SDC_STATUS_DATACRCFAIL | SDC_STATUS_DATATIMEOUT | SDC_STATUS_TXUNDERRUN \
+ | SDC_STATUS_RXOVERRUN | SDC_STATUS_STARTBITERR)
+/** FIFO Status*/
+#define SDC_STATUS_FIFO (SDC_STATUS_TXFIFOHALFEMPTY | SDC_STATUS_RXFIFOHALFFULL \
+ | SDC_STATUS_TXFIFOFULL | SDC_STATUS_RXFIFOFULL \
+ | SDC_STATUS_TXFIFOEMPTY | SDC_STATUS_RXFIFOEMPTY \
+ | SDC_STATUS_DATABLOCKEND)
+
+/** Data Transfer Status*/
+#define SDC_STATUS_DATA (SDC_STATUS_DATAEND )
+
+/**
+ * @brief SDC Clear Register bit definitions
+ */
+/** Clear all status flag*/
+#define SDC_CLEAR_ALL ((uint32_t) 0x7FF)
+/** Clears CmdCrcFail flag.*/
+#define SDC_CLEAR_CMDCRCFAIL (((uint32_t) 1 ) << 0)
+/** Clears DataCrcFail flag. */
+#define SDC_CLEAR_DATACRCFAIL (((uint32_t) 1 ) << 1)
+/** Clears CmdTimeOut flag. */
+#define SDC_CLEAR_CMDTIMEOUT (((uint32_t) 1 ) << 2)
+/** Clears DataTimeOut flag. */
+#define SDC_CLEAR_DATATIMEOUT (((uint32_t) 1 ) << 3)
+/** Clears TxUnderrun flag. */
+#define SDC_CLEAR_TXUNDERRUN (((uint32_t) 1 ) << 4)
+/**Clears RxOverrun flag. */
+#define SDC_CLEAR_RXOVERRUN (((uint32_t) 1 ) << 5)
+/** Clears CmdRespEnd flag. */
+#define SDC_CLEAR_CMDRESPEND (((uint32_t) 1 ) << 6)
+/** Clears CmdSent flag.*/
+#define SDC_CLEAR_CMDSENT (((uint32_t) 1 ) << 7)
+/**Clears DataEnd flag.*/
+#define SDC_CLEAR_DATAEND (((uint32_t) 1 ) << 8)
+/** Clears StartBitErr flag.*/
+#define SDC_CLEAR_STARTBITERR (((uint32_t) 1 ) << 9)
+/** Clears DataBlockEnd flag.*/
+#define SDC_CLEAR_DATABLOCKEND (((uint32_t) 1 ) << 10)
+
+/**
+ * @brief SDC Interrupt Mask Register bit definitions
+ */
+/** Mask CmdCrcFail flag.*/
+#define SDC_MASK0_CMDCRCFAIL (((uint32_t) 1 ) << 0)
+/** Mask DataCrcFail flag. */
+#define SDC_MASK0_DATACRCFAIL (((uint32_t) 1 ) << 1)
+/** Mask CmdTimeOut flag. */
+#define SDC_MASK0_CMDTIMEOUT (((uint32_t) 1 ) << 2)
+/** Mask DataTimeOut flag. */
+#define SDC_MASK0_DATATIMEOUT (((uint32_t) 1 ) << 3)
+/** Mask TxUnderrun flag. */
+#define SDC_MASK0_TXUNDERRUN (((uint32_t) 1 ) << 4)
+/** Mask RxOverrun flag. */
+#define SDC_MASK0_RXOVERRUN (((uint32_t) 1 ) << 5)
+/** Mask CmdRespEnd flag. */
+#define SDC_MASK0_CMDRESPEND (((uint32_t) 1 ) << 6)
+/** Mask CmdSent flag.*/
+#define SDC_MASK0_CMDSENT (((uint32_t) 1 ) << 7)
+/** Mask DataEnd flag.*/
+#define SDC_MASK0_DATAEND (((uint32_t) 1 ) << 8)
+/** Mask StartBitErr flag.*/
+#define SDC_MASK0_STARTBITERR (((uint32_t) 1 ) << 9)
+/** Mask DataBlockEnd flag.*/
+#define SDC_MASK0_DATABLOCKEND (((uint32_t) 1 ) << 10)
+/** Mask CmdActive flag.*/
+#define SDC_MASK0_CMDACTIVE (((uint32_t) 1 ) << 11)
+/** Mask TxActive flag.*/
+#define SDC_MASK0_TXACTIVE (((uint32_t) 1 ) << 12)
+/** Mask RxActive flag.*/
+#define SDC_MASK0_RXACTIVE (((uint32_t) 1 ) << 13)
+/** Mask TxFifoHalfEmpty flag.*/
+#define SDC_MASK0_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
+/** Mask RxFifoHalfFull flag.*/
+#define SDC_MASK0_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
+/** Mask TxFifoFull flag.*/
+#define SDC_MASK0_TXFIFOFULL (((uint32_t) 1 ) << 16)
+/** Mask RxFifoFull flag.*/
+#define SDC_MASK0_RXFIFOFULL (((uint32_t) 1 ) << 17)
+/** Mask TxFifoEmpty flag.*/
+#define SDC_MASK0_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
+/** Mask RxFifoEmpty flag.*/
+#define SDC_MASK0_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
+/** Mask TxDataAvlbl flag.*/
+#define SDC_MASK0_TXDATAAVLBL (((uint32_t) 1 ) << 20)
+/** Mask RxDataAvlbl flag.*/
+#define SDC_MASK0_RXDATAAVLBL (((uint32_t) 1 ) << 21)
+/** CMD error interrupt mask */
+#define SDC_MASK0_CMDERR (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)
+/** Data Transmit Error interrupt mask */
+#define SDC_MASK0_TXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_TXUNDERRUN | \
+ SDC_MASK0_STARTBITERR)
+
+/** Data Receive Error interrupt mask */
+#define SDC_MASK0_RXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_RXOVERRUN | \
+ SDC_MASK0_STARTBITERR)
+/** TX FIFO interrupt mask*/
+#define SDC_MASK0_TXFIFO (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )
+/** RX FIFO interrupt mask*/
+#define SDC_MASK0_RXFIFO (SDC_MASK0_RXFIFOHALFFULL | SDC_MASK0_DATABLOCKEND )
+
+/** Data Transfer interrupt mask*/
+#define SDC_MASK0_DATA (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )
+
+/**
+ * @brief SDC FIFO Counter Register bit definitions
+ */
+#define SDC_FIFOCNT_VAL(n) ((uint32_t) n & 0x7FFF)
+
+/* The number of bytes used to store card status*/
+#define SDC_CARDSTATUS_BYTENUM ((uint32_t) 4)
+
+/**
+ * @brief SDC Power Control Options
+ */
+typedef enum IP_SDC_001_PWR_CTRL {
+ SDC_POWER_OFF = 0, /*!< Power-off */
+ SDC_POWER_UP = 2, /*!< Power-up */
+ SDC_POWER_ON = 3, /*!< Power-on */
+} IP_SDC_001_PWR_CTRL_T;
+
+/**
+ * @brief SDC Clock Control Options
+ */
+typedef enum IP_SDC_001_CLOCK_CTRL {
+ SDC_CLOCK_ENABLE = 8, /*!< Enable SD Card Bus Clock */
+ SDC_CLOCK_POWER_SAVE = 9, /*!< Disable SD_CLK output when bus is idle */
+ SDC_CLOCK_DIVIDER_BYPASS = 10, /*!< Enable bypass of clock divide logic */
+ SDC_CLOCK_WIDEBUS_MODE = 11, /*!< Enable wide bus mode (SD_DAT[3:0] is used instead of SD_DAT[0]) */
+} IP_SDC_001_CLOCK_CTRL_T;
+
+/**
+ * @brief SDC Response type
+ */
+typedef enum IP_SDC_001_RESPONSE {
+ SDC_NO_RESPONSE = SDC_COMMAND_NO_RSP, /*!< No response */
+ SDC_SHORT_RESPONSE = SDC_COMMAND_SHORT_RSP, /*!< Short response */
+ SDC_LONG_RESPONSE = SDC_COMMAND_LONG_RSP, /*!< Long response */
+} IP_SDC_001_RESPONSE_T;
+
+/**
+ * @brief SDC Data Transfer Direction definitions
+ */
+typedef enum IP_SDC_001_TRANSFER_DIR {
+ SDC_TRANSFER_DIR_FROMCARD = SDC_DATACTRL_DIR_FROMCARD, /*!< Transfer from card */
+ SDC_TRANSFER_DIR_TOCARD = SDC_DATACTRL_DIR_TOCARD, /*!< Transfer to card */
+} IP_SDC_001_TRANSFER_DIR_T;
+
+/**
+ * @brief SDC Data Transfer Mode definitions
+ */
+typedef enum IP_SDC_001_TRANSFER_MODE {
+ SDC_TRANSFER_MODE_STREAM = SDC_DATACTRL_XFER_MODE_STREAM, /*!< Stream transfer mode */
+ SDC_TRANSFER_MODE_BLOCK = SDC_DATACTRL_XFER_MODE_BLOCK, /*!< Block transfer mode */
+} IP_SDC_001_TRANSFER_MODE_T;
+
+/**
+ * @brief SDC Data Block size definitions (in bytes)
+ */
+typedef enum IP_SDC_001_BLOCK_SIZE {
+ SDC_BLOCK_SIZE_1 = 0, /*!< Block size - 1 byte */
+ SDC_BLOCK_SIZE_2, /*!< Block size - 2 bytes */
+ SDC_BLOCK_SIZE_4, /*!< Block size - 4 bytes */
+ SDC_BLOCK_SIZE_8, /*!< Block size - 8 bytes */
+ SDC_BLOCK_SIZE_16, /*!< Block size - 16 bytes */
+ SDC_BLOCK_SIZE_32, /*!< Block size - 32 bytes */
+ SDC_BLOCK_SIZE_64, /*!< Block size - 64 bytes */
+ SDC_BLOCK_SIZE_128, /*!< Block size - 128 bytes */
+ SDC_BLOCK_SIZE_256, /*!< Block size - 256 bytes */
+ SDC_BLOCK_SIZE_512, /*!< Block size - 512 bytes */
+ SDC_BLOCK_SIZE_1024, /*!< Block size - 1024 bytes */
+ SDC_BLOCK_SIZE_2048, /*!< Block size - 2048 bytes */
+} IP_SDC_001_BLOCK_SIZE_T;
+
+/**
+ * @brief SDC Command Response structure
+ */
+typedef struct {
+ uint8_t CmdIndex; /*!< Command Index of the command response received */
+ uint32_t Data[SDC_CARDSTATUS_BYTENUM]; /* Card Status which can be stored in 1 or 4 bytes */
+} IP_SDC_001_RESP_T;
+
+/**
+ * @brief SDC Data Transfer Setup structure
+ */
+typedef struct {
+ uint16_t BlockNum; /*!< The number of block which will be transfered */
+ IP_SDC_001_BLOCK_SIZE_T BlockSize; /*!< Data Block Length */
+ IP_SDC_001_TRANSFER_DIR_T Dir; /*!< Direction */
+ IP_SDC_001_TRANSFER_MODE_T Mode; /*!< Mode */
+ bool DMAUsed; /*!< true: DMA used */
+ uint32_t Timeout; /*!< Data Transfer timeout periods (in Card Bus Clock)*/
+} IP_SDC_001_DATA_TRANSFER_T;
+
+/**
+ * @brief Set the power state of SDC peripheral
+ * @param pSDC : Pointer to SDC register block
+ * @param pwrMode : Power mode
+ * @param flag : Output control flag
+ * @return Nothing
+ * @note When the external power supply is switched on, the software first enters the power-up
+ * state, and waits until the supply output is stable before moving to the power-on state.
+ * During the power-up state, SD_PWR is set HIGH. The card bus outlets are disabled
+ * during both states.
+ * flag is or-ed bit value of SDC_PWR_OPENDRAIN and SDC_PWR_ROD
+ */
+void IP_SDC_PowerControl(IP_SDC_001_T *pSDC, IP_SDC_001_PWR_CTRL_T pwrMode, uint32_t flag);
+
+/**
+ * @brief Set clock divider value for SDC peripheral
+ * @param pSDC : Pointer to SDC register block
+ * @param div : clock divider
+ * @return Nothing
+ * @note While the SD card interface is in identification mode, the SD_CLK frequency must be less
+ * than 400 kHz. The clock frequency can be changed to the maximum card bus frequency
+ * when relative card addresses are assigned to all cards.
+ * SD_CLK frequency = MCLK / [2x(ClkDiv+1)].
+ */
+void IP_SDC_SetClockDiv(IP_SDC_001_T *pSDC, uint8_t div);
+
+/**
+ * @brief Set or Reset clock control of SDC peripheral
+ * @param pSDC : Pointer to SDC register block
+ * @param ctrlType : Clock Control type
+ * @param NewState : New State to set
+ * @return Nothing
+ */
+void IP_SDC_ClockControl(IP_SDC_001_T *pSDC, IP_SDC_001_CLOCK_CTRL_T ctrlType,
+ FunctionalState NewState);
+
+/**
+ * @brief Set SDC Command Information
+ * @param pSDC : Pointer to SDC register block
+ * @param Cmd : Command value
+ * @param Arg : Argument for the command
+ * @return Nothing
+ */
+void IP_SDC_SetCommand(IP_SDC_001_T *pSDC, uint32_t Cmd, uint32_t Arg);
+
+/**
+ * @brief Reset SDC Command Information
+ * @param pSDC : Pointer to SDC register block
+ * @return Nothing
+ */
+void IP_SDC_ResetCommand(IP_SDC_001_T *pSDC);
+
+/**
+ * @brief Get SDC Response
+ * @param pSDC : Pointer to SDC register block
+ * @param pResp : Pointer to buffer storing response data
+ * @return Nothing
+ */
+void IP_SDC_GetResp(IP_SDC_001_T *pSDC, IP_SDC_001_RESP_T *pResp);
+
+/**
+ * @brief Set SDC Data Timeout Period
+ * @param pSDC : Pointer to SDC register block
+ * @param timeout : Data timeout value in card bus clock periods
+ * @return Nothing
+ */
+STATIC INLINE void IP_SDC_SetDataTimer(IP_SDC_001_T *pSDC, uint32_t timeout)
+{
+ pSDC->DATATIMER = timeout;
+}
+
+/**
+ * @brief Set SDC Data Transfer Information
+ * @param pSDC : Pointer to SDC register block
+ * @param pTransfer : Pointer to Data Transfer structure
+ * @return Nothing
+ */
+void IP_SDC_SetDataTransfer(IP_SDC_001_T *pSDC, IP_SDC_001_DATA_TRANSFER_T *pTransfer);
+
+/**
+ * @brief Write Data to FIFO
+ * @param pSDC : Pointer to SDC register block
+ * @param pSrc : Pointer to data buffer
+ * @param bFirstHalf : true (write to the first half of FIFO) false (write to the second half of FIFO)
+ * @return Nothing
+ */
+void IP_SDC_WriteFIFO(IP_SDC_001_T *pSDC, uint32_t *pSrc, bool bFirstHalf);
+
+/**
+ * @brief Write Data to FIFO
+ * @param pSDC : Pointer to SDC register block
+ * @param pDst : The buffer hold the data read
+ * @param bFirstHalf : true (read the first half of FIFO) false (read the second half of FIFO)
+ * @return Nothing
+ */
+void IP_SDC_ReadFIFO(IP_SDC_001_T *pSDC, uint32_t *pDst, bool bFirstHalf);
+
+/**
+ * @brief Get status of SDC Peripheral
+ * @param pSDC : Pointer to SDC register block
+ * @return Status (Or-ed bit value of SDC_STATUS_*)
+ */
+STATIC INLINE uint32_t IP_SDC_GetStatus(IP_SDC_001_T *pSDC)
+{
+ return pSDC->STATUS;
+}
+
+/**
+ * @brief Clear status of SDC Peripheral
+ * @param pSDC : Pointer to SDC register block
+ * @param flag : Status flag(s) to be cleared (Or-ed bit value of SDC_CLEAR_*)
+ * @return None
+ */
+STATIC INLINE void IP_SDC_ClearStatus(IP_SDC_001_T *pSDC, uint32_t flag)
+{
+ pSDC->CLEAR = flag;
+}
+
+/**
+ * @brief Set interrupt mask for SDC Peripheral
+ * @param pSDC : Pointer to SDC register block
+ * @param mask : Interrupt mask (Or-ed bit value of SDC_MASK0_*)
+ * @return None
+ */
+STATIC INLINE void IP_SDC_SetIntMask(IP_SDC_001_T *pSDC, uint32_t mask)
+{
+ pSDC->MASK0 = mask;
+}
+
+/**
+ * @brief Initialize the SDC card controller
+ * @param pSDC : Pointer to SDC register block
+ * @return None
+ */
+void IP_SDC_Init(IP_SDC_001_T *pSDC);
+
+/**
+ * @brief Deinitialise the SDC peripheral
+ * @param pSDC : Pointer to SDC register block
+ * @return None
+ */
+STATIC INLINE void IP_SDC_DeInit(IP_SDC_001_T *pSDC)
+{
+ IP_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SDC_001_H_ */
--- /dev/null
+/*\r
+ * @brief SD/SDIO (MCI) registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SDMMC_001_H_\r
+#define __SDMMC_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_SDMMC_001 IP: SDMMC register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief SD/MMC & SDIO register block structure\r
+ */\r
+typedef struct { /*!< SDMMC Structure */\r
+ __IO uint32_t CTRL; /*!< Control Register */\r
+ __IO uint32_t PWREN; /*!< Power Enable Register */\r
+ __IO uint32_t CLKDIV; /*!< Clock Divider Register */\r
+ __IO uint32_t CLKSRC; /*!< SD Clock Source Register */\r
+ __IO uint32_t CLKENA; /*!< Clock Enable Register */\r
+ __IO uint32_t TMOUT; /*!< Timeout Register */\r
+ __IO uint32_t CTYPE; /*!< Card Type Register */\r
+ __IO uint32_t BLKSIZ; /*!< Block Size Register */\r
+ __IO uint32_t BYTCNT; /*!< Byte Count Register */\r
+ __IO uint32_t INTMASK; /*!< Interrupt Mask Register */\r
+ __IO uint32_t CMDARG; /*!< Command Argument Register */\r
+ __IO uint32_t CMD; /*!< Command Register */\r
+ __I uint32_t RESP0; /*!< Response Register 0 */\r
+ __I uint32_t RESP1; /*!< Response Register 1 */\r
+ __I uint32_t RESP2; /*!< Response Register 2 */\r
+ __I uint32_t RESP3; /*!< Response Register 3 */\r
+ __I uint32_t MINTSTS; /*!< Masked Interrupt Status Register */\r
+ __IO uint32_t RINTSTS; /*!< Raw Interrupt Status Register */\r
+ __I uint32_t STATUS; /*!< Status Register */\r
+ __IO uint32_t FIFOTH; /*!< FIFO Threshold Watermark Register */\r
+ __I uint32_t CDETECT; /*!< Card Detect Register */\r
+ __I uint32_t WRTPRT; /*!< Write Protect Register */\r
+ __IO uint32_t GPIO; /*!< General Purpose Input/Output Register */\r
+ __I uint32_t TCBCNT; /*!< Transferred CIU Card Byte Count Register */\r
+ __I uint32_t TBBCNT; /*!< Transferred Host to BIU-FIFO Byte Count Register */\r
+ __IO uint32_t DEBNCE; /*!< Debounce Count Register */\r
+ __IO uint32_t USRID; /*!< User ID Register */\r
+ __I uint32_t VERID; /*!< Version ID Register */\r
+ __I uint32_t RESERVED0;\r
+ __IO uint32_t UHS_REG; /*!< UHS-1 Register */\r
+ __IO uint32_t RST_N; /*!< Hardware Reset */\r
+ __I uint32_t RESERVED1;\r
+ __IO uint32_t BMOD; /*!< Bus Mode Register */\r
+ __O uint32_t PLDMND; /*!< Poll Demand Register */\r
+ __IO uint32_t DBADDR; /*!< Descriptor List Base Address Register */\r
+ __IO uint32_t IDSTS; /*!< Internal DMAC Status Register */\r
+ __IO uint32_t IDINTEN; /*!< Internal DMAC Interrupt Enable Register */\r
+ __I uint32_t DSCADDR; /*!< Current Host Descriptor Address Register */\r
+ __I uint32_t BUFADDR; /*!< Current Buffer Descriptor Address Register */\r
+} IP_SDMMC_001_T;\r
+\r
+/** @brief SDIO DMA descriptor control (des0) register defines\r
+ */\r
+#define MCI_DMADES0_OWN (1UL << 31) /*!< DMA owns descriptor bit */\r
+#define MCI_DMADES0_CES (1 << 30) /*!< Card Error Summary bit */\r
+#define MCI_DMADES0_ER (1 << 5) /*!< End of descriptopr ring bit */\r
+#define MCI_DMADES0_CH (1 << 4) /*!< Second address chained bit */\r
+#define MCI_DMADES0_FS (1 << 3) /*!< First descriptor bit */\r
+#define MCI_DMADES0_LD (1 << 2) /*!< Last descriptor bit */\r
+#define MCI_DMADES0_DIC (1 << 1) /*!< Disable interrupt on completion bit */\r
+\r
+/** @brief SDIO DMA descriptor size (des1) register defines\r
+ */\r
+#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */\r
+#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */\r
+#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */\r
+\r
+/** @brief SDIO control register defines\r
+ */\r
+#define MCI_CTRL_USE_INT_DMAC (1 << 25) /*!< Use internal DMA */\r
+#define MCI_CTRL_CARDV_MASK (0x7 << 16) /*!< SD_VOLT[2:0} pins output state mask */\r
+#define MCI_CTRL_CEATA_INT_EN (1 << 11) /*!< Enable CE-ATA interrupts */\r
+#define MCI_CTRL_SEND_AS_CCSD (1 << 10) /*!< Send auto-stop */\r
+#define MCI_CTRL_SEND_CCSD (1 << 9) /*!< Send CCSD */\r
+#define MCI_CTRL_ABRT_READ_DATA (1 << 8) /*!< Abort read data */\r
+#define MCI_CTRL_SEND_IRQ_RESP (1 << 7) /*!< Send auto-IRQ response */\r
+#define MCI_CTRL_READ_WAIT (1 << 6) /*!< Assert read-wait for SDIO */\r
+#define MCI_CTRL_INT_ENABLE (1 << 4) /*!< Global interrupt enable */\r
+#define MCI_CTRL_DMA_RESET (1 << 2) /*!< Reset internal DMA */\r
+#define MCI_CTRL_FIFO_RESET (1 << 1) /*!< Reset data FIFO pointers */\r
+#define MCI_CTRL_RESET (1 << 0) /*!< Reset controller */\r
+\r
+/** @brief SDIO Power Enable register defines\r
+ */\r
+#define MCI_POWER_ENABLE 0x1 /*!< Enable slot power signal (SD_POW) */\r
+\r
+/** @brief SDIO Clock divider register defines\r
+ */\r
+#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) /*!< Set cklock divider */\r
+\r
+/** @brief SDIO Clock source register defines\r
+ */\r
+#define MCI_CLKSRC_CLKDIV0 0\r
+#define MCI_CLKSRC_CLKDIV1 1\r
+#define MCI_CLKSRC_CLKDIV2 2\r
+#define MCI_CLKSRC_CLKDIV3 3\r
+#define MCI_CLK_SOURCE(clksrc) (clksrc) /*!< Set cklock divider source */\r
+\r
+/** @brief SDIO Clock Enable register defines\r
+ */\r
+#define MCI_CLKEN_LOW_PWR (1 << 16) /*!< Enable clock idle for slot */\r
+#define MCI_CLKEN_ENABLE (1 << 0) /*!< Enable slot clock */\r
+\r
+/** @brief SDIO time-out register defines\r
+ */\r
+#define MCI_TMOUT_DATA(clks) ((clks) << 8) /*!< Data timeout clocks */\r
+#define MCI_TMOUT_DATA_MSK 0xFFFFFF00\r
+#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */\r
+#define MCI_TMOUT_RESP_MSK 0xFF\r
+\r
+/** @brief SDIO card-type register defines\r
+ */\r
+#define MCI_CTYPE_8BIT (1 << 16) /*!< Enable 4-bit mode */\r
+#define MCI_CTYPE_4BIT (1 << 0) /*!< Enable 8-bit mode */\r
+\r
+/** @brief SDIO Interrupt status & mask register defines\r
+ */\r
+#define MCI_INT_SDIO (1 << 16) /*!< SDIO interrupt */\r
+#define MCI_INT_EBE (1 << 15) /*!< End-bit error */\r
+#define MCI_INT_ACD (1 << 14) /*!< Auto command done */\r
+#define MCI_INT_SBE (1 << 13) /*!< Start bit error */\r
+#define MCI_INT_HLE (1 << 12) /*!< Hardware locked error */\r
+#define MCI_INT_FRUN (1 << 11) /*!< FIFO overrun/underrun error */\r
+#define MCI_INT_HTO (1 << 10) /*!< Host data starvation error */\r
+#define MCI_INT_DTO (1 << 9) /*!< Data timeout error */\r
+#define MCI_INT_RTO (1 << 8) /*!< Response timeout error */\r
+#define MCI_INT_DCRC (1 << 7) /*!< Data CRC error */\r
+#define MCI_INT_RCRC (1 << 6) /*!< Response CRC error */\r
+#define MCI_INT_RXDR (1 << 5) /*!< RX data ready */\r
+#define MCI_INT_TXDR (1 << 4) /*!< TX data needed */\r
+#define MCI_INT_DATA_OVER (1 << 3) /*!< Data transfer over */\r
+#define MCI_INT_CMD_DONE (1 << 2) /*!< Command done */\r
+#define MCI_INT_RESP_ERR (1 << 1) /*!< Command response error */\r
+#define MCI_INT_CD (1 << 0) /*!< Card detect */\r
+\r
+/** @brief SDIO Command register defines\r
+ */\r
+#define MCI_CMD_START (1UL << 31) /*!< Start command */\r
+#define MCI_CMD_VOLT_SWITCH (1 << 28) /*!< Voltage switch bit */\r
+#define MCI_CMD_BOOT_MODE (1 << 27) /*!< Boot mode */\r
+#define MCI_CMD_DISABLE_BOOT (1 << 26) /*!< Disable boot */\r
+#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25) /*!< Expect boot ack */\r
+#define MCI_CMD_ENABLE_BOOT (1 << 24) /*!< Enable boot */\r
+#define MCI_CMD_CCS_EXP (1 << 23) /*!< CCS expected */\r
+#define MCI_CMD_CEATA_RD (1 << 22) /*!< CE-ATA read in progress */\r
+#define MCI_CMD_UPD_CLK (1 << 21) /*!< Update clock register only */\r
+#define MCI_CMD_INIT (1 << 15) /*!< Send init sequence */\r
+#define MCI_CMD_STOP (1 << 14) /*!< Stop/abort command */\r
+#define MCI_CMD_PRV_DAT_WAIT (1 << 13) /*!< Wait before send */\r
+#define MCI_CMD_SEND_STOP (1 << 12) /*!< Send auto-stop */\r
+#define MCI_CMD_STRM_MODE (1 << 11) /*!< Stream transfer mode */\r
+#define MCI_CMD_DAT_WR (1 << 10) /*!< Read(0)/Write(1) selection */\r
+#define MCI_CMD_DAT_EXP (1 << 9) /*!< Data expected */\r
+#define MCI_CMD_RESP_CRC (1 << 8) /*!< Check response CRC */\r
+#define MCI_CMD_RESP_LONG (1 << 7) /*!< Response length */\r
+#define MCI_CMD_RESP_EXP (1 << 6) /*!< Response expected */\r
+#define MCI_CMD_INDX(n) ((n) & 0x1F)\r
+\r
+/** @brief SDIO status register definess\r
+ */\r
+#define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)\r
+\r
+/** @brief SDIO FIFO threshold defines\r
+ */\r
+#define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)\r
+#define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)\r
+#define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)\r
+#define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)\r
+#define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)\r
+#define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)\r
+#define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)\r
+#define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)\r
+#define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)\r
+#define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)\r
+\r
+/** @brief Bus mode register defines\r
+ */\r
+#define MCI_BMOD_PBL1 (0 << 8) /*!< Burst length = 1 */\r
+#define MCI_BMOD_PBL4 (1 << 8) /*!< Burst length = 4 */\r
+#define MCI_BMOD_PBL8 (2 << 8) /*!< Burst length = 8 */\r
+#define MCI_BMOD_PBL16 (3 << 8) /*!< Burst length = 16 */\r
+#define MCI_BMOD_PBL32 (4 << 8) /*!< Burst length = 32 */\r
+#define MCI_BMOD_PBL64 (5 << 8) /*!< Burst length = 64 */\r
+#define MCI_BMOD_PBL128 (6 << 8) /*!< Burst length = 128 */\r
+#define MCI_BMOD_PBL256 (7 << 8) /*!< Burst length = 256 */\r
+#define MCI_BMOD_DE (1 << 7) /*!< Enable internal DMAC */\r
+#define MCI_BMOD_DSL(len) ((len) << 2) /*!< Descriptor skip length */\r
+#define MCI_BMOD_FB (1 << 1) /*!< Fixed bursts */\r
+#define MCI_BMOD_SWR (1 << 0) /*!< Software reset of internal registers */\r
+\r
+/** @brief Commonly used definitions\r
+ */\r
+#define SD_FIFO_SZ 32 /*!< Size of SDIO FIFOs (32-bit wide) */\r
+\r
+/** Function prototype for SD interface IRQ callback */\r
+typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);\r
+\r
+/** Function prototype for SD detect and write protect status check */\r
+typedef int32_t (*PSCHECK_FUNC_T)(void);\r
+\r
+/** Function prototype for SD slot power enable or slot reset */\r
+typedef void (*PS_POWER_FUNC_T)(int32_t enable);\r
+\r
+/** @brief SDIO chained DMA descriptor\r
+ */\r
+typedef struct {\r
+ volatile uint32_t des0; /*!< Control and status */\r
+ volatile uint32_t des1; /*!< Buffer size(s) */\r
+ volatile uint32_t des2; /*!< Buffer address pointer 1 */\r
+ volatile uint32_t des3; /*!< Buffer address pointer 2 */\r
+} pSDMMC_DMA_T;\r
+\r
+/** @brief SDIO device type\r
+ */\r
+typedef struct _sdif_device {\r
+ /* MCI_IRQ_CB_FUNC_T irq_cb; */\r
+ pSDMMC_DMA_T mci_dma_dd[1 + (0x100000 / MCI_DMADES1_MAXTR)];\r
+ /* uint32_t sdio_clk_rate; */\r
+ /* uint32_t sdif_slot_clk_rate; */\r
+ /* int32_t clock_enabled; */\r
+} sdif_device;\r
+\r
+/**\r
+ * @brief Initializes the MCI card controller\r
+ * @param pSDMMC Pointer to IP_SDMMC_001_T structure\r
+ * @return None\r
+ */\r
+void IP_SDMMC_Init(IP_SDMMC_001_T *pSDMMC);\r
+\r
+/**\r
+ * @brief Close the MCI\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @return None\r
+ */\r
+void IP_SDMMC_DeInit(IP_SDMMC_001_T *pSDMMC);\r
+\r
+/**\r
+ * @brief Set block size for transfer\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param bytes : block size in bytes\r
+ * @return None\r
+ */\r
+void IP_SDMMC_SetBlkSize(IP_SDMMC_001_T *pSDMMC, uint32_t bytes);\r
+\r
+/**\r
+ * @brief Reset card in slot\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param reset : Sets SD_RST to passed state\r
+ * @return None\r
+ * @note Reset card in slot, must manually de-assert reset after assertion\r
+ * (Uses SD_RST pin, set per reset parameter state)\r
+ */\r
+void IP_SDMMC_Reset(IP_SDMMC_001_T *pSDMMC, int32_t reset);\r
+\r
+/**\r
+ * @brief Enable slot power\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @return None\r
+ * @note Uses SD_POW pin, set to high.\r
+ */\r
+STATIC INLINE void IP_SDMMC_PowerOn(IP_SDMMC_001_T *pSDMMC)\r
+{\r
+ pSDMMC->PWREN = 1;\r
+}\r
+\r
+/**\r
+ * @brief Disable slot power\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @return None\r
+ * @note Uses SD_POW pin, set to low.\r
+ */\r
+STATIC INLINE void IP_SDMMC_PowerOff(IP_SDMMC_001_T *pSDMMC)\r
+{\r
+ pSDMMC->PWREN = 0;\r
+}\r
+\r
+/**\r
+ * @brief Detect if write protect is enabled\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @return Returns 1 if card is write protected, otherwise 0\r
+ * @note Detect if write protect is enabled\r
+ * (uses SD_WP pin, returns 1 if card is write protected)\r
+ */\r
+STATIC INLINE int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_T *pSDMMC)\r
+{\r
+ return (pSDMMC->WRTPRT & 1);\r
+}\r
+\r
+/**\r
+ * @brief Detect if an SD card is inserted\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @return Returns 0 if a card is detected, otherwise 1\r
+ * @note Detect if an SD card is inserted\r
+ * (uses SD_CD pin, returns 0 on card detect)\r
+ */\r
+STATIC INLINE int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_T *pSDMMC)\r
+{\r
+ return (pSDMMC->CDETECT & 1);\r
+}\r
+\r
+/**\r
+ * @brief Function to send command to Card interface unit (CIU)\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param cmd : Command with all flags set\r
+ * @param arg : Argument for the command\r
+ * @return TRUE on times-out, otherwise FALSE\r
+ */\r
+int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_T *pSDMMC, uint32_t cmd, uint32_t arg);\r
+\r
+/**\r
+ * @brief Read the response from the last command\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param resp : Pointer to response array to fill\r
+ * @return None\r
+ */\r
+void IP_SDMMC_GetResponse(IP_SDMMC_001_T *pSDMMC, uint32_t *resp);\r
+\r
+/**\r
+ * @brief Sets the SD bus clock speed\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param clk_rate : Input clock rate into the IP block\r
+ * @param speed : Desired clock speed to the card\r
+ * @return None\r
+ */\r
+void IP_SDMMC_SetClock(IP_SDMMC_001_T *pSDMMC, uint32_t clk_rate, uint32_t speed);\r
+\r
+/**\r
+ * @brief Function to set card type\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param ctype : card type\r
+ * @return None\r
+ */\r
+void IP_SDMMC_SetCardType(IP_SDMMC_001_T *pSDMMC, uint32_t ctype);\r
+\r
+/**\r
+ * @brief Function to clear interrupt & FIFOs\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @return None\r
+ */\r
+void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_T *pSDMMC);\r
+\r
+/**\r
+ * @brief Returns the raw SD interface interrupt status\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @return Raw interrupt status of Or'ed values MCI_INT_*\r
+ */\r
+uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_T *pSDMMC);\r
+\r
+/**\r
+ * @brief Sets the raw SD interface interrupt status\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param iVal : Raw interrupts to set, Or'ed values MCI_INT_*\r
+ * @return None\r
+ */\r
+void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_T *pSDMMC, uint32_t iVal);\r
+\r
+/**\r
+ * @brief Sets the SD interface interrupt mask\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param iVal : Interrupts to enable, Or'ed values MCI_INT_*\r
+ * @return None\r
+ */\r
+void IP_SDMMC_SetIntMask(IP_SDMMC_001_T *pSDMMC, uint32_t iVal);\r
+\r
+/**\r
+ * @brief Setup DMA descriptors\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param psdif_dev : SD interface device\r
+ * @param addr : Address of buffer (source or destination)\r
+ * @param size : size of buffer in bytes (64K max)\r
+ * @return None\r
+ */\r
+void IP_SDMMC_DmaSetup(IP_SDMMC_001_T *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size);\r
+\r
+/**\r
+ * @brief Set block size and byte count for transfer\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param blk_size: block size and byte count in bytes\r
+ * @return None\r
+ */\r
+void IP_SDMMC_SetBlkSizeByteCnt(IP_SDMMC_001_T *pSDMMC, uint32_t blk_size);\r
+\r
+/**\r
+ * @brief Set byte count for transfer\r
+ * @param pSDMMC : Pointer to IP_SDMMC_001_T structure\r
+ * @param bytes : block size and byte count in bytes\r
+ * @return None\r
+ */\r
+void IP_SDMMC_SetByteCnt(IP_SDMMC_001_T *pSDMMC, uint32_t bytes);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SDMMC_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Serial GPIO registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SGPIO_001_H_\r
+#define __SGPIO_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_SGPIO_001 IP: SGPIO register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Serial GPIO\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Serial GPIO register block structure\r
+ */\r
+typedef struct { /*!< SGPIO Structure */\r
+ __IO uint32_t OUT_MUX_CFG[16]; /*!< Pin multiplexer configurationregisters. */\r
+ __IO uint32_t SGPIO_MUX_CFG[16]; /*!< SGPIO multiplexer configuration registers. */\r
+ __IO uint32_t SLICE_MUX_CFG[16]; /*!< Slice multiplexer configuration registers. */\r
+ __IO uint32_t REG[16]; /*!< Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */\r
+ __IO uint32_t REG_SS[16]; /*!< Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */\r
+ __IO uint32_t PRESET[16]; /*!< Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */\r
+ __IO uint32_t COUNT[16]; /*!< Down counter, counts down each clock cycle. */\r
+ __IO uint32_t POS[16]; /*!< Each time COUNT0 reaches 0x0 */\r
+ __IO uint32_t MASK_A; /*!< Mask for pattern match function of slice A */\r
+ __IO uint32_t MASK_H; /*!< Mask for pattern match function of slice H */\r
+ __IO uint32_t MASK_I; /*!< Mask for pattern match function of slice I */\r
+ __IO uint32_t MASK_P; /*!< Mask for pattern match function of slice P */\r
+ __I uint32_t GPIO_INREG; /*!< GPIO input status register */\r
+ __IO uint32_t GPIO_OUTREG; /*!< GPIO output control register */\r
+ __IO uint32_t GPIO_OENREG; /*!< GPIO OE control register */\r
+ __IO uint32_t CTRL_ENABLED; /*!< Enables the slice COUNT counter */\r
+ __IO uint32_t CTRL_DISABLED; /*!< Disables the slice COUNT counter */\r
+ __I uint32_t RESERVED0[823];\r
+ __O uint32_t CLR_EN_0; /*!< Shift clock interrupt clear mask */\r
+ __O uint32_t SET_EN_0; /*!< Shift clock interrupt set mask */\r
+ __I uint32_t ENABLE_0; /*!< Shift clock interrupt enable */\r
+ __I uint32_t STATUS_0; /*!< Shift clock interrupt status */\r
+ __O uint32_t CTR_STATUS_0; /*!< Shift clock interrupt clear status */\r
+ __O uint32_t SET_STATUS_0; /*!< Shift clock interrupt set status */\r
+ __I uint32_t RESERVED1[2];\r
+ __O uint32_t CLR_EN_1; /*!< Capture clock interrupt clear mask */\r
+ __O uint32_t SET_EN_1; /*!< Capture clock interrupt set mask */\r
+ __I uint32_t ENABLE_1; /*!< Capture clock interrupt enable */\r
+ __I uint32_t STATUS_1; /*!< Capture clock interrupt status */\r
+ __O uint32_t CTR_STATUS_1; /*!< Capture clock interrupt clear status */\r
+ __O uint32_t SET_STATUS_1; /*!< Capture clock interrupt set status */\r
+ __I uint32_t RESERVED2[2];\r
+ __O uint32_t CLR_EN_2; /*!< Pattern match interrupt clear mask */\r
+ __O uint32_t SET_EN_2; /*!< Pattern match interrupt set mask */\r
+ __I uint32_t ENABLE_2; /*!< Pattern match interrupt enable */\r
+ __I uint32_t STATUS_2; /*!< Pattern match interrupt status */\r
+ __O uint32_t CTR_STATUS_2; /*!< Pattern match interrupt clear status */\r
+ __O uint32_t SET_STATUS_2; /*!< Pattern match interrupt set status */\r
+ __I uint32_t RESERVED3[2];\r
+ __O uint32_t CLR_EN_3; /*!< Input interrupt clear mask */\r
+ __O uint32_t SET_EN_3; /*!< Input bit match interrupt set mask */\r
+ __I uint32_t ENABLE_3; /*!< Input bit match interrupt enable */\r
+ __I uint32_t STATUS_3; /*!< Input bit match interrupt status */\r
+ __O uint32_t CTR_STATUS_3; /*!< Input bit match interrupt clear status */\r
+ __O uint32_t SET_STATUS_3; /*!< Shift clock interrupt set status */\r
+} IP_SGPIO_001_T;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SGPIO_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief SPI registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SPI_001_H_\r
+#define __SPI_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_SPI_001 IP: SPI register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief SPI register block structure\r
+ */\r
+typedef struct { /*!< SPI Structure */\r
+ __IO uint32_t CR; /*!< SPI Control Register. This register controls the operation of the SPI. */\r
+ __I uint32_t SR; /*!< SPI Status Register. This register shows the status of the SPI. */\r
+ __IO uint32_t DR; /*!< SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */\r
+ __IO uint32_t CCR; /*!< SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */\r
+ __I uint32_t RESERVED0[3];\r
+ __IO uint32_t INT; /*!< SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */\r
+} IP_SPI_001_T;\r
+\r
+/*\r
+ * Macro defines for SPI Control register\r
+ */\r
+/* SPI CFG Register BitMask */\r
+#define SPI_CR_BITMASK ((uint32_t) 0xFFC)\r
+/** Enable of controlling the number of bits per transfer */\r
+#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))\r
+/** Mask of field of bit controlling */\r
+#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)\r
+/** Set the number of bits per a transfer */\r
+#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */\r
+/** SPI Clock Phase Select*/\r
+#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/\r
+#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/\r
+/** SPI Clock Polarity Select*/\r
+#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/\r
+#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/\r
+/** SPI Slave Mode Select */\r
+#define SPI_CR_SLAVE_EN ((uint32_t) 0)\r
+/** SPI Master Mode Select */\r
+#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))\r
+/** SPI MSB First mode enable */\r
+#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/\r
+/** SPI LSB First mode enable */\r
+#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/\r
+/** SPI interrupt enable */\r
+#define SPI_CR_INT_EN ((uint32_t) (1 << 7))\r
+\r
+/*\r
+ * Macro defines for SPI Status register\r
+ */\r
+/** SPI STAT Register BitMask */\r
+#define SPI_SR_BITMASK ((uint32_t) 0xF8)\r
+/** Slave abort Flag */\r
+#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */\r
+/* Mode fault Flag */\r
+#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */\r
+/** Read overrun flag*/\r
+#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */\r
+/** Write collision flag. */\r
+#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */\r
+/** SPI transfer complete flag. */\r
+#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */\r
+/** SPI error flag */\r
+#define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)\r
+/*\r
+ * Macro defines for SPI Test Control Register register\r
+ */\r
+/*Enable SPI Test Mode */\r
+#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))\r
+\r
+/*\r
+ * Macro defines for SPI Interrupt register\r
+ */\r
+/** SPI interrupt flag */\r
+#define SPI_INT_SPIF ((uint32_t) (1 << 0))\r
+\r
+/**\r
+ * Macro defines for SPI Data register\r
+ */\r
+/** Receiver Data */\r
+#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))\r
+\r
+/** @brief SPI Mode*/\r
+typedef enum IP_SPI_MODE {\r
+ SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */\r
+ SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */\r
+} IP_SPI_MODE_T;\r
+\r
+/** @brief SPI Clock Mode*/\r
+typedef enum IP_SPI_CLOCK_MODE {\r
+ SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 0 */\r
+ SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 1 */\r
+ SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 0 */\r
+ SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 1 */\r
+ SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,/**< alias */\r
+ SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,/**< alias */\r
+ SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,/**< alias */\r
+ SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,/**< alias */\r
+} IP_SPI_CLOCK_MODE_T;\r
+\r
+/** @brief SPI Data Order Mode*/\r
+typedef enum IP_SPI_DATA_ORDER {\r
+ SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */\r
+ SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */\r
+} IP_SPI_DATA_ORDER_T;\r
+\r
+/*\r
+ * @brief Number of bits per frame\r
+ */\r
+typedef enum IP_SPI_BITS {\r
+ SPI_BITS_8 = SPI_CR_BITS(8), /**< 8 bits/frame */\r
+ SPI_BITS_9 = SPI_CR_BITS(9), /**< 9 bits/frame */\r
+ SPI_BITS_10 = SPI_CR_BITS(10), /**< 10 bits/frame */\r
+ SPI_BITS_11 = SPI_CR_BITS(11), /**< 11 bits/frame */\r
+ SPI_BITS_12 = SPI_CR_BITS(12), /**< 12 bits/frame */\r
+ SPI_BITS_13 = SPI_CR_BITS(13), /**< 13 bits/frame */\r
+ SPI_BITS_14 = SPI_CR_BITS(14), /**< 14 bits/frame */\r
+ SPI_BITS_15 = SPI_CR_BITS(15), /**< 15 bits/frame */\r
+ SPI_BITS_16 = SPI_CR_BITS(16), /**< 16 bits/frame */\r
+} IP_SPI_BITS_T;\r
+\r
+/**\r
+ * @brief Get the current status of SPI controller\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @return SPI Status (Or-ed bit value of SPI_SR_*)\r
+ * @note See user manual about how status bits are cleared.\r
+ */\r
+STATIC INLINE uint32_t IP_SPI_GetStatus(IP_SPI_001_T *pSPI)\r
+{\r
+ return pSPI->SR;\r
+}\r
+\r
+/**\r
+ * @brief Enable the interrupt for the SPI\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SPI_IntEnable(IP_SPI_001_T *pSPI)\r
+{\r
+ pSPI->CR |= SPI_CR_INT_EN;\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt for the SPI\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SPI_IntDisable(IP_SPI_001_T *pSPI)\r
+{\r
+ pSPI->CR &= ~SPI_CR_INT_EN;\r
+}\r
+\r
+/**\r
+ * @brief Get the interrupt status\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @return SPI interrupt Status (Or-ed bit value of SPI_INT_*)\r
+ */\r
+STATIC INLINE uint32_t IP_SPI_GetIntStatus(IP_SPI_001_T *pSPI)\r
+{\r
+ return pSPI->INT;\r
+}\r
+\r
+/**\r
+ * @brief Clear the interrupt status\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @param mask : SPI interrupt mask (Or-ed bit value of SPI_INT_*)\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SPI_ClearIntStatus(IP_SPI_001_T *pSPI, uint32_t mask)\r
+{\r
+ pSPI->INT = mask;\r
+}\r
+\r
+/**\r
+ * @brief Send SPI 16-bit data\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @param data : Transmit Data\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SPI_SendFrame(IP_SPI_001_T *pSPI, uint16_t data)\r
+{\r
+ pSPI->DR = SPI_DR_DATA(data);\r
+}\r
+\r
+/**\r
+ * @brief Get received SPI data\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @return receive data\r
+ */\r
+STATIC INLINE uint16_t IP_SPI_ReceiveFrame(IP_SPI_001_T *pSPI)\r
+{\r
+ return SPI_DR_DATA(pSPI->DR);\r
+}\r
+\r
+/**\r
+ * @brief Set up output clocks per bit for SPI bus\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @param counter : the number of SPI peripheral clock cycles that make up an SPI clock\r
+ * @return Nothing\r
+ * @note The counter must be an even number greater than or equal to 8. <br>\r
+ * The SPI SCK rate = PCLK_SPI / counter.\r
+ */\r
+STATIC INLINE void IP_SPI_SetClockCounter(IP_SPI_001_T *pSPI, uint32_t counter)\r
+{\r
+ pSPI->CCR = counter;\r
+}\r
+\r
+/**\r
+ * @brief Set up the SPI frame format\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @param bits : The number of bits transferred in each frame.\r
+ * @param clockMode : Select Clock polarity and Clock phase, should be : <br>\r
+ * - SPI_CLOCK_CPHA0_CPOL0<br>\r
+ * - SPI_CLOCK_CPHA0_CPOL1<br>\r
+ * - SPI_CLOCK_CPHA1_CPOL0<br>\r
+ * - SPI_CLOCK_CPHA1_CPOL1<br>\r
+ * or SPI_CLOCK_MODE*\r
+ * @param order : Data order (MSB first/LSB first).\r
+ * @return Nothing\r
+ * @note Note: The clockFormat is only used in SPI mode\r
+ */\r
+STATIC INLINE void IP_SPI_SetFormat(IP_SPI_001_T *pSPI, IP_SPI_BITS_T bits,\r
+ IP_SPI_CLOCK_MODE_T clockMode, IP_SPI_DATA_ORDER_T order)\r
+{\r
+ pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | bits | clockMode | order;\r
+}\r
+\r
+/**\r
+ * @brief Get the number of bits transferred in each frame\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @return the number of bits transferred in each frame\r
+ */\r
+STATIC INLINE IP_SPI_BITS_T IP_SPI_GetDataSize(IP_SPI_001_T *pSPI)\r
+{\r
+ return (pSPI->CR & SPI_CR_BIT_EN) ? ((IP_SPI_BITS_T) (pSPI->CR & SPI_CR_BITS_MASK)) : SPI_BITS_8;\r
+}\r
+\r
+/**\r
+ * @brief Get the current CPHA & CPOL setting\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @return CPHA & CPOL setting\r
+ */\r
+STATIC INLINE IP_SPI_CLOCK_MODE_T IP_SPI_GetClockMode(IP_SPI_001_T *pSPI)\r
+{\r
+ return (IP_SPI_CLOCK_MODE_T) (pSPI->CR & (3 << 3));\r
+}\r
+\r
+/**\r
+ * @brief Set the SPI working as master or slave mode\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @param mode : Operating mode\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SPI_SetMode(IP_SPI_001_T *pSPI, IP_SPI_MODE_T mode)\r
+{\r
+ pSPI->CR = (pSPI->CR & (~(1 << 5))) | mode;\r
+}\r
+\r
+/**\r
+ * @brief Set the SPI working as master or slave mode\r
+ * @param pSPI : The base of SPI peripheral on the chip\r
+ * @return Operating mode\r
+ */\r
+STATIC INLINE IP_SPI_MODE_T IP_SPI_GetMode(IP_SPI_001_T *pSPI)\r
+{\r
+ return (IP_SPI_MODE_T) (pSPI->CR & (1 << 5));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SPI_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief SSP Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __SSP_001_H_\r
+#define __SSP_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_SSP_001 IP: SSP register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief SSP register block structure\r
+ */\r
+typedef struct { /*!< SSPn Structure */\r
+ __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */\r
+ __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */\r
+ __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */\r
+ __I uint32_t SR; /*!< Status Register */\r
+ __IO uint32_t CPSR; /*!< Clock Prescale Register */\r
+ __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */\r
+ __I uint32_t RIS; /*!< Raw Interrupt Status Register */\r
+ __I uint32_t MIS; /*!< Masked Interrupt Status Register */\r
+ __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */\r
+#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \\r
+ !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)\r
+ __IO uint32_t DMACR; /*!< SSPn DMA control register */\r
+#endif\r
+} IP_SSP_001_T;\r
+\r
+/**\r
+ * Macro defines for CR0 register\r
+ */\r
+\r
+/** SSP data size select, must be 4 bits to 16 bits */\r
+#define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))\r
+/** SSP control 0 Motorola SPI mode */\r
+#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))\r
+/** SSP control 0 TI synchronous serial mode */\r
+#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))\r
+/** SSP control 0 National Micro-wire mode */\r
+#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))\r
+/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the\r
+ bus clock high between frames, (0) = low */\r
+#define SSP_CR0_CPOL_LO ((uint32_t) (0))\r
+#define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))\r
+/** SPI clock out phase bit (used in SPI mode only), (1) = captures data\r
+ on the second clock transition of the frame, (0) = first */\r
+#define SSP_CR0_CPHA_FIRST ((uint32_t) (0))\r
+#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))\r
+/** SSP serial clock rate value load macro, divider rate is\r
+ PERIPH_CLK / (cpsr * (SCR + 1)) */\r
+#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))\r
+/** SSP CR0 bit mask */\r
+#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))\r
+/** SSP CR0 bit mask */\r
+#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))\r
+/** SSP serial clock rate value load macro, divider rate is\r
+ PERIPH_CLK / (cpsr * (SCR + 1)) */\r
+#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))\r
+\r
+/**\r
+ * Macro defines for CR1 register\r
+ */\r
+\r
+/** SSP control 1 loopback mode enable bit */\r
+#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))\r
+/** SSP control 1 enable bit */\r
+#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))\r
+/** SSP control 1 slave enable */\r
+#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))\r
+#define SSP_CR1_MASTER_EN ((uint32_t) (0))\r
+/** SSP control 1 slave out disable bit, disables transmit line in slave\r
+ mode */\r
+#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))\r
+/** SSP CR1 bit mask */\r
+#define SSP_CR1_BITMASK ((uint32_t) (0x0F))\r
+\r
+/** SSP CPSR bit mask */\r
+#define SSP_CPSR_BITMASK ((uint32_t) (0xFF))\r
+/**\r
+ * Macro defines for DR register\r
+ */\r
+\r
+/** SSP data bit mask */\r
+#define SSP_DR_BITMASK(n) ((n) & 0xFFFF)\r
+\r
+/**\r
+ * Macro defines for SR register\r
+ */\r
+\r
+/** SSP SR bit mask */\r
+#define SSP_SR_BITMASK ((uint32_t) (0x1F))\r
+\r
+/** ICR bit mask */\r
+#define SSP_ICR_BITMASK ((uint32_t) (0x03))\r
+\r
+/**\r
+ * @brief SSP Type of Status\r
+ */\r
+typedef enum IP_SSP_STATUS {\r
+ SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */\r
+ SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */\r
+ SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */\r
+ SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */\r
+ SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */\r
+} IP_SSP_STATUS_T;\r
+\r
+/**\r
+ * @brief SSP Type of Interrupt Mask\r
+ */\r
+typedef enum IP_SSP_INTMASK {\r
+ SSP_RORIM = ((uint32_t)(1 << 0)), /**< Overun */\r
+ SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */\r
+ SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */\r
+ SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */\r
+ SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),\r
+} IP_SSP_INTMASK_T;\r
+\r
+/**\r
+ * @brief SSP Type of Mask Interrupt Status\r
+ */\r
+typedef enum IP_SSP_MASKINTSTATUS {\r
+ SSP_RORMIS = ((uint32_t)(1 << 0)), /**< Overun */\r
+ SSP_RTMIS = ((uint32_t)(1 << 1)), /**< TimeOut */\r
+ SSP_RXMIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */\r
+ SSP_TXMIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */\r
+ SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),\r
+} IP_SSP_MASKINTSTATUS_T;\r
+\r
+/**\r
+ * @brief SSP Type of Raw Interrupt Status\r
+ */\r
+typedef enum IP_SSP_RAWINTSTATUS {\r
+ SSP_RORRIS = ((uint32_t)(1 << 0)), /**< Overun */\r
+ SSP_RTRIS = ((uint32_t)(1 << 1)), /**< TimeOut */\r
+ SSP_RXRIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */\r
+ SSP_TXRIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */\r
+ SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),\r
+} IP_SSP_RAWINTSTATUS_T;\r
+\r
+typedef enum IP_SSP_INTCLEAR {\r
+ SSP_RORIC = 0x0,\r
+ SSP_RTIC = 0x1,\r
+ SSP_INT_CLEAR_BITMASK = 0x3,\r
+} IP_SSP_INTCLEAR_T;\r
+\r
+typedef enum IP_SSP_DMA {\r
+ SSP_DMA_RX = (1u), /**< DMA RX Enable */\r
+ SSP_DMA_TX = (1u << 1), /**< DMA TX Enable */\r
+ SSP_DMA_BITMASK = ((uint32_t)(0x3)),\r
+} IP_SSP_DMA_T;\r
+\r
+/**\r
+ * @brief Disable SSP operation\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ * @note The SSP controller is disabled\r
+ */\r
+STATIC INLINE void IP_SSP_DeInit(IP_SSP_001_T *pSSP)\r
+{\r
+ pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;\r
+}\r
+\r
+/**\r
+ * @brief Enable SSP operation\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SSP_Enable(IP_SSP_001_T *pSSP)\r
+{\r
+ pSSP->CR1 |= SSP_CR1_SSP_EN;\r
+}\r
+\r
+/**\r
+ * @brief Disable SSP operation\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SSP_Disable(IP_SSP_001_T *pSSP)\r
+{\r
+ pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;\r
+}\r
+\r
+/**\r
+ * @brief Enable loopback mode\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ * @note Serial input is taken from the serial output (MOSI or MISO) rather\r
+ * than the serial input pin\r
+ */\r
+STATIC INLINE void IP_SSP_EnableLoopBack(IP_SSP_001_T *pSSP)\r
+{\r
+ pSSP->CR1 |= SSP_CR1_LBM_EN;\r
+}\r
+\r
+/**\r
+ * @brief Disable loopback mode\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return Nothing\r
+ * @note Serial input is taken from the serial output (MOSI or MISO) rather\r
+ * than the serial input pin\r
+ */\r
+STATIC INLINE void IP_SSP_DisableLoopBack(IP_SSP_001_T *pSSP)\r
+{\r
+ pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;\r
+}\r
+\r
+/**\r
+ * @brief Get the current status of SSP controller\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param Stat : Type of status, should be :\r
+ * - SSP_STAT_TFE\r
+ * - SSP_STAT_TNF\r
+ * - SSP_STAT_RNE\r
+ * - SSP_STAT_RFF\r
+ * - SSP_STAT_BSY\r
+ * @return SSP controller status, SET or RESET\r
+ */\r
+STATIC INLINE FlagStatus IP_SSP_GetStatus(IP_SSP_001_T *pSSP, IP_SSP_STATUS_T Stat)\r
+{\r
+ return (pSSP->SR & Stat) ? SET : RESET;\r
+}\r
+\r
+/**\r
+ * @brief Get the masked interrupt status\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return SSP Masked Interrupt Status Register value\r
+ * @note The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)\r
+ */\r
+STATIC INLINE uint32_t IP_SSP_GetIntStatus(IP_SSP_001_T *pSSP)\r
+{\r
+ return pSSP->MIS;\r
+}\r
+\r
+/**\r
+ * @brief Get the raw interrupt status\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param RawInt : Interrupt condition to be get status, shoud be :\r
+ * - SSP_RORRIS\r
+ * - SSP_RTRIS\r
+ * - SSP_RXRIS\r
+ * - SSP_TXRIS\r
+ * @return Raw interrupt status corresponding to interrupt condition , SET or RESET\r
+ * @note Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled\r
+ */\r
+STATIC INLINE IntStatus IP_SSP_GetRawIntStatus(IP_SSP_001_T *pSSP, IP_SSP_RAWINTSTATUS_T RawInt)\r
+{\r
+ return (pSSP->RIS & RawInt) ? SET : RESET;\r
+}\r
+\r
+/**\r
+ * @brief Get the number of bits transferred in each frame\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return the number of bits transferred in each frame minus one\r
+ * @note The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer\r
+ */\r
+STATIC INLINE uint8_t IP_SSP_GetDataSize(IP_SSP_001_T *pSSP)\r
+{\r
+ return SSP_CR0_DSS(pSSP->CR0);\r
+}\r
+\r
+/**\r
+ * @brief Clear the corresponding interrupt condition(s) in the SSP controller\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param IntClear: Type of cleared interrupt, should be :\r
+ * - SSP_RORIC\r
+ * - SSP_RTIC\r
+ * @return Nothing\r
+ * @note Software can clear one or more interrupt condition(s) in the SSP controller\r
+ */\r
+STATIC INLINE void IP_SSP_ClearIntPending(IP_SSP_001_T *pSSP, IP_SSP_INTCLEAR_T IntClear)\r
+{\r
+ pSSP->ICR = IntClear;\r
+}\r
+\r
+/**\r
+ * @brief Enable interrupt for the SSP\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param IntType : Type of interrupt condition to be enable/disable, should be :\r
+ * - SSP_RORIM\r
+ * - SSP_RTIM\r
+ * - SSP_RXIM\r
+ * - SSP_TXIM\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SSP_Int_Enable(IP_SSP_001_T *pSSP, IP_SSP_INTMASK_T IntType)\r
+{\r
+ pSSP->IMSC |= IntType;\r
+}\r
+\r
+/**\r
+ * @brief Disable interrupt for the SSP\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param IntType : Type of interrupt condition to be enable/disable, should be :\r
+ * - SSP_RORIM\r
+ * - SSP_RTIM\r
+ * - SSP_RXIM\r
+ * - SSP_TXIM\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SSP_Int_Disable(IP_SSP_001_T *pSSP, IP_SSP_INTMASK_T IntType)\r
+{\r
+ pSSP->IMSC &= (~IntType);\r
+}\r
+\r
+/**\r
+ * @brief Get received SSP data\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @return SSP 16-bit data received\r
+ */\r
+STATIC INLINE uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_T *pSSP)\r
+{\r
+ return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));\r
+}\r
+\r
+/**\r
+ * @brief Send SSP 16-bit data\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param tx_data : SSP 16-bit data to be transmited\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SSP_SendFrame(IP_SSP_001_T *pSSP, uint16_t tx_data)\r
+{\r
+ pSSP->DR = SSP_DR_BITMASK(tx_data);\r
+}\r
+\r
+/**\r
+ * @brief Set up output clocks per bit for SSP bus\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param clk_rate fs: The number of prescaler-output clocks per bit on the bus, minus one\r
+ * @param prescale : The factor by which the Prescaler divides the SSP peripheral clock PCLK\r
+ * @return Nothing\r
+ * @note The bit frequency is PCLK / (prescale x[clk_rate+1])\r
+ */\r
+void IP_SSP_Set_ClockRate(IP_SSP_001_T *pSSP, uint32_t clk_rate, uint32_t prescale);\r
+\r
+/**\r
+ * @brief Set up the SSP frame format\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param bits : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16\r
+ * @param frameFormat : Frame format, should be :\r
+ * - SSP_FRAMEFORMAT_SPI\r
+ * - SSP_FRAME_FORMAT_TI\r
+ * - SSP_FRAMEFORMAT_MICROWIRE\r
+ * @param clockMode : Select Clock polarity and Clock phase, should be :\r
+ * - SSP_CLOCK_CPHA0_CPOL0\r
+ * - SSP_CLOCK_CPHA0_CPOL1\r
+ * - SSP_CLOCK_CPHA1_CPOL0\r
+ * - SSP_CLOCK_CPHA1_CPOL1\r
+ * @return Nothing\r
+ * @note Note: The clockFormat is only used in SPI mode\r
+ */\r
+STATIC INLINE void IP_SSP_SetFormat(IP_SSP_001_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)\r
+{\r
+ pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;\r
+}\r
+\r
+/**\r
+ * @brief Set the SSP working as master or slave mode\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param mode : Operating mode, should be\r
+ * - SSP_MODE_MASTER\r
+ * - SSP_MODE_SLAVE\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SSP_Set_Mode(IP_SSP_001_T *pSSP, uint32_t mode)\r
+{\r
+ pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;\r
+}\r
+\r
+#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \\r
+ !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)\r
+/**\r
+ * @brief Enable DMA for SSP\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param flag : DMA flag for transmit/receive SSP, should be\r
+ * - SSP_DMA_RX\r
+ * - SSP_DMA_TX\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SSP_DMA_Enable(IP_SSP_001_T *pSSP, IP_SSP_DMA_T flag)\r
+{\r
+ pSSP->DMACR |= flag;\r
+}\r
+\r
+/**\r
+ * @brief Disable DMA for SSP\r
+ * @param pSSP : The base of SSP peripheral on the chip\r
+ * @param flag : DMA flag for transmit/receive SSP, should be\r
+ * - SSP_DMA_RX\r
+ * - SSP_DMA_TX\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_SSP_DMA_Disable(IP_SSP_001_T *pSSP, IP_SSP_DMA_T flag)\r
+{\r
+ pSSP->DMACR &= ~flag;\r
+}\r
+\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SSP_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief 32-bit Timer/PWM registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __TIMER_001_H_\r
+#define __TIMER_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_TIMER_001 IP: Timer register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief 32-bit Standard timer register block structure\r
+ */\r
+typedef struct { /*!< TIMERn Structure */\r
+ __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */\r
+ __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */\r
+ __IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */\r
+ __IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */\r
+ __IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */\r
+ __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */\r
+ __IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */\r
+ __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */\r
+ __IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */\r
+ __IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */\r
+ __I uint32_t RESERVED0[12];\r
+ __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */\r
+#if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11AXX) || \\r
+ defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)\r
+ __IO uint32_t PWMC;\r
+#endif\r
+} IP_TIMER_001_T;\r
+\r
+/** Macro to clear interrupt pending */\r
+#define TIMER_IR_CLR(n) _BIT(n)\r
+\r
+/** Macro for getting a timer match interrupt bit */\r
+#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))\r
+/** Macro for getting a capture event interrupt bit */\r
+#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))\r
+\r
+/** Timer/counter enable bit */\r
+#define TIMER_ENABLE ((uint32_t) (1 << 0))\r
+/** Timer/counter reset bit */\r
+#define TIMER_RESET ((uint32_t) (1 << 1))\r
+\r
+/** Bit location for interrupt on MRx match, n = 0 to 3 */\r
+#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))\r
+/** Bit location for reset on MRx match, n = 0 to 3 */\r
+#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))\r
+/** Bit location for stop on MRx match, n = 0 to 3 */\r
+#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))\r
+\r
+/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */\r
+#define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))\r
+/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */\r
+#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))\r
+/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */\r
+#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))\r
+\r
+/**\r
+ * @brief Determine if a match interrupt is pending\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param matchnum : Match interrupt number to check\r
+ * @return false if the interrupt is not pending, otherwise true\r
+ * @note Determine if the match interrupt for the passed timer and match\r
+ * counter is pending.\r
+ */\r
+STATIC INLINE bool IP_TIMER_MatchPending(IP_TIMER_001_T *pTimer, int8_t matchnum)\r
+{\r
+ return (bool) ((pTimer->IR & TIMER_MATCH_INT(matchnum)) != 0);\r
+}\r
+\r
+/**\r
+ * @brief Determine if a capture interrupt is pending\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capnum : Capture interrupt number to check\r
+ * @return false if the interrupt is not pending, otherwise true\r
+ * @note Determine if the capture interrupt for the passed capture pin is\r
+ * pending.\r
+ */\r
+STATIC INLINE bool IP_TIMER_CapturePending(IP_TIMER_001_T *pTimer, int8_t capnum)\r
+{\r
+ return (bool) ((pTimer->IR & TIMER_CAP_INT(capnum)) != 0);\r
+}\r
+\r
+/**\r
+ * @brief Clears a (pending) match interrupt\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param matchnum : Match interrupt number to clear\r
+ * @return Nothing\r
+ * @note Clears a pending timer match interrupt.\r
+ */\r
+STATIC INLINE void IP_TIMER_ClearMatch(IP_TIMER_001_T *pTimer, int8_t matchnum)\r
+{\r
+ pTimer->IR = TIMER_IR_CLR(matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Clears a (pending) capture interrupt\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capnum : Capture interrupt number to clear\r
+ * @return Nothing\r
+ * @note Clears a pending timer capture interrupt.\r
+ */\r
+STATIC INLINE void IP_TIMER_ClearCapture(IP_TIMER_001_T *pTimer, int8_t capnum)\r
+{\r
+ pTimer->IR = (0x10 << capnum);\r
+}\r
+\r
+/**\r
+ * @brief Enables the timer (starts count)\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @return Nothing\r
+ * @note Enables the timer to start counting.\r
+ */\r
+STATIC INLINE void IP_TIMER_Enable(IP_TIMER_001_T *pTimer)\r
+{\r
+ pTimer->TCR |= TIMER_ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Disables the timer (stops count)\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @return Nothing\r
+ * @note Disables the timer to stop counting.\r
+ */\r
+STATIC INLINE void IP_TIMER_Disable(IP_TIMER_001_T *pTimer)\r
+{\r
+ pTimer->TCR &= ~TIMER_ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Returns the current timer count\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @return Current timer terminal count value\r
+ * @note Returns the current timer terminal count.\r
+ */\r
+STATIC INLINE uint32_t IP_TIMER_ReadCount(IP_TIMER_001_T *pTimer)\r
+{\r
+ return pTimer->TC;\r
+}\r
+\r
+/**\r
+ * @brief Returns the current prescale count\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @return Current timer prescale count value\r
+ * @note Returns the current prescale count.\r
+ */\r
+STATIC INLINE uint32_t IP_TIMER_ReadPrescale(IP_TIMER_001_T *pTimer)\r
+{\r
+ return pTimer->PC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the prescaler value\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param prescale : Prescale value to set the prescale register to\r
+ * @return Nothing\r
+ * @note Sets the prescale count value.\r
+ */\r
+STATIC INLINE void IP_TIMER_PrescaleSet(IP_TIMER_001_T *pTimer, uint32_t prescale)\r
+{\r
+ pTimer->PR = prescale;\r
+}\r
+\r
+/**\r
+ * @brief Sets a timer match value\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param matchnum : Match timer to set match count for\r
+ * @param matchval : Match value for the selected match count\r
+ * @return Nothing\r
+ * @note Sets ones of the timer match values.\r
+ */\r
+STATIC INLINE void IP_TIMER_SetMatch(IP_TIMER_001_T *pTimer, int8_t matchnum, uint32_t matchval)\r
+{\r
+ pTimer->MR[matchnum] = matchval;\r
+}\r
+\r
+/**\r
+ * @brief Reads a capture register\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capnum : Capture register to read\r
+ * @return The selected capture register value\r
+ * @note Returns the selected capture register value.\r
+ */\r
+STATIC INLINE uint32_t IP_TIMER_ReadCapture(IP_TIMER_001_T *pTimer, int8_t capnum)\r
+{\r
+ return pTimer->CR[capnum];\r
+}\r
+\r
+/**\r
+ * @brief Resets the timer terminal and prescale counts to 0\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @return Nothing\r
+ */\r
+void IP_TIMER_Reset(IP_TIMER_001_T *pTimer);\r
+\r
+/**\r
+ * @brief Enables a match interrupt that fires when the terminal count\r
+ * matches the match counter value.\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_MatchEnableInt(IP_TIMER_001_T *pTimer, int8_t matchnum)\r
+{\r
+ pTimer->MCR |= TIMER_INT_ON_MATCH(matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Disables a match interrupt for a match counter.\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_MatchDisableInt(IP_TIMER_001_T *pTimer, int8_t matchnum)\r
+{\r
+ pTimer->MCR &= ~TIMER_INT_ON_MATCH(matchnum);\r
+}\r
+\r
+/**\r
+ * @brief For the specific match counter, enables reset of the terminal count register when a match occurs\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_ResetOnMatchEnable(IP_TIMER_001_T *pTimer, int8_t matchnum)\r
+{\r
+ pTimer->MCR |= TIMER_RESET_ON_MATCH(matchnum);\r
+}\r
+\r
+/**\r
+ * @brief For the specific match counter, disables reset of the terminal count register when a match occurs\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_ResetOnMatchDisable(IP_TIMER_001_T *pTimer, int8_t matchnum)\r
+{\r
+ pTimer->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Enable a match timer to stop the terminal count when a\r
+ * match count equals the terminal count.\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_StopOnMatchEnable(IP_TIMER_001_T *pTimer, int8_t matchnum)\r
+{\r
+ pTimer->MCR |= TIMER_STOP_ON_MATCH(matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Disable stop on match for a match timer. Disables a match timer\r
+ * to stop the terminal count when a match count equals the terminal count.\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param matchnum : Match timer, 0 to 3\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_StopOnMatchDisable(IP_TIMER_001_T *pTimer, int8_t matchnum)\r
+{\r
+ pTimer->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);\r
+}\r
+\r
+/**\r
+ * @brief Enables capture on on rising edge of selected CAP signal for the\r
+ * selected capture register, enables the selected CAPn.capnum signal to load\r
+ * the capture register with the terminal coount on a rising edge.\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_CaptureRisingEdgeEnable(IP_TIMER_001_T *pTimer, int8_t capnum)\r
+{\r
+ pTimer->CCR |= TIMER_CAP_RISING(capnum);\r
+}\r
+\r
+/**\r
+ * @brief Disables capture on on rising edge of selected CAP signal. For the\r
+ * selected capture register, disables the selected CAPn.capnum signal to load\r
+ * the capture register with the terminal coount on a rising edge.\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_CaptureRisingEdgeDisable(IP_TIMER_001_T *pTimer, int8_t capnum)\r
+{\r
+ pTimer->CCR &= ~TIMER_CAP_RISING(capnum);\r
+}\r
+\r
+/**\r
+ * @brief Enables capture on on falling edge of selected CAP signal. For the\r
+ * selected capture register, enables the selected CAPn.capnum signal to load\r
+ * the capture register with the terminal coount on a falling edge.\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_CaptureFallingEdgeEnable(IP_TIMER_001_T *pTimer, int8_t capnum)\r
+{\r
+ pTimer->CCR |= TIMER_CAP_FALLING(capnum);\r
+}\r
+\r
+/**\r
+ * @brief Disables capture on on falling edge of selected CAP signal. For the\r
+ * selected capture register, disables the selected CAPn.capnum signal to load\r
+ * the capture register with the terminal coount on a falling edge.\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_CaptureFallingEdgeDisable(IP_TIMER_001_T *pTimer, int8_t capnum)\r
+{\r
+ pTimer->CCR &= ~TIMER_CAP_FALLING(capnum);\r
+}\r
+\r
+/**\r
+ * @brief Enables interrupt on capture of selected CAP signal. For the\r
+ * selected capture register, an interrupt will be generated when the enabled\r
+ * rising or falling edge on CAPn.capnum is detected.\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_CaptureEnableInt(IP_TIMER_001_T *pTimer, int8_t capnum)\r
+{\r
+ pTimer->CCR |= TIMER_INT_ON_CAP(capnum);\r
+}\r
+\r
+/**\r
+ * @brief Disables interrupt on capture of selected CAP signal\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capnum : Capture signal/register to use\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_TIMER_CaptureDisableInt(IP_TIMER_001_T *pTimer, int8_t capnum)\r
+{\r
+ pTimer->CCR &= ~TIMER_INT_ON_CAP(capnum);\r
+}\r
+\r
+/**\r
+ * @brief Standard timer initial match pin state and change state\r
+ */\r
+typedef enum IP_TIMER_PIN_MATCH_STATE {\r
+ TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */\r
+ TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */\r
+ TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */\r
+ TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */\r
+} IP_TIMER_PIN_MATCH_STATE_T;\r
+\r
+/**\r
+ * @brief Sets external match control (MATn.matchnum) pin control\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param initial_state : Initial state of the pin, high(1) or low(0)\r
+ * @param matchState : Selects the match state for the pin\r
+ * @param matchnum : MATn.matchnum signal to use\r
+ * @return Nothing\r
+ * @note For the pin selected with matchnum, sets the function of the pin that occurs on\r
+ * a terminal count match for the match count.\r
+ */\r
+void IP_TIMER_ExtMatchControlSet(IP_TIMER_001_T *pTimer, int8_t initial_state,\r
+ IP_TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);\r
+\r
+/**\r
+ * @brief Standard timer clock and edge for count source\r
+ */\r
+typedef enum IP_TIMER_CAP_SRC_STATE {\r
+ TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */\r
+ TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */\r
+ TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */\r
+ TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */\r
+} IP_TIMER_CAP_SRC_STATE_T;\r
+\r
+/**\r
+ * @brief Sets timer count source and edge with the selected passed from CapSrc\r
+ * @param pTimer : Pointer to timer IP register address\r
+ * @param capSrc : timer clock source and edge\r
+ * @param capnum : CAPn.capnum pin to use (if used)\r
+ * @return Nothing\r
+ * @note If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.\r
+ */\r
+void IP_TIMER_SetCountClockSrc(IP_TIMER_001_T *pTimer,\r
+ IP_TIMER_CAP_SRC_STATE_T capSrc, int8_t capnum);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __TIMER_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief UART/USART Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __USART_001_H_\r
+#define __USART_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_USART_001 IP: USART register block and driver\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief USART register block structure\r
+ */\r
+typedef struct { /*!< USARTn Structure */\r
+\r
+ union {\r
+ __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */\r
+ __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */\r
+ __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */\r
+ };\r
+\r
+ union {\r
+ __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */\r
+ __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */\r
+ };\r
+\r
+ union {\r
+ __O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */\r
+ __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */\r
+ };\r
+\r
+ __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */\r
+ __IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */\r
+ __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */\r
+ __I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */\r
+ __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */\r
+ __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */\r
+ __IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */\r
+ __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */\r
+ __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */\r
+ __IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */\r
+ uint32_t RESERVED0[3];\r
+ __IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */\r
+ __I uint32_t RESERVED1[1];\r
+ __IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */\r
+ __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */\r
+ __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */\r
+ __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */\r
+ union {\r
+ __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */\r
+ __I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */\r
+ };\r
+\r
+#if !defined CHIP_LPC11XX\r
+ __IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */\r
+#endif\r
+} IP_USART_001_T;\r
+\r
+#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) /*!< UART time-out definitions in case of using Read/Write function with Blocking Flag mode */\r
+\r
+#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */\r
+\r
+/* --------------------- BIT DEFINITIONS -------------------------------------- */\r
+/**\r
+ * @brief Macro defines for UARTn Receiver Buffer Register\r
+ */\r
+#define UART_RBR_MASKBIT ((uint8_t) 0xFF) /*!< UART Received Buffer mask bit (8 bits) */\r
+\r
+/**\r
+ * @brief Macro defines for UARTn Transmit Holding Register\r
+ */\r
+#define UART_THR_MASKBIT ((uint8_t) 0xFF) /*!< UART Transmit Holding mask bit (8 bits) */\r
+\r
+/**\r
+ * @brief Macro defines for UARTn Divisor Latch LSB register\r
+ */\r
+#define UART_LOAD_DLL(div) ((div) & 0xFF) /*!< Macro for loading least significant halfs of divisors */\r
+#define UART_DLL_MASKBIT ((uint8_t) 0xFF) /*!< Divisor latch LSB bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UARTn Divisor Latch MSB register\r
+ */\r
+#define UART_DLM_MASKBIT ((uint8_t) 0xFF) /*!< Divisor latch MSB bit mask */\r
+#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*!< Macro for loading most significant halfs of divisors */\r
+\r
+/**\r
+ * @brief Macro defines for UART interrupt enable register\r
+ */\r
+#define UART_IER_RBRINT_EN ((uint32_t) (1 << 0)) /*!< RBR Interrupt enable*/\r
+#define UART_IER_THREINT_EN ((uint32_t) (1 << 1)) /*!< THR Interrupt enable*/\r
+#define UART_IER_RLSINT_EN ((uint32_t) (1 << 2)) /*!< RX line status interrupt enable*/\r
+#define UART_IER_MSINT_EN ((uint32_t) (1 << 3)) /*!< Modem status interrupt enable */\r
+#define UART_IER_CTSINT_EN ((uint32_t) (1 << 7)) /*!< CTS1 signal transition interrupt enable */\r
+#define UART_IER_ABEOINT_EN ((uint32_t) (1 << 8)) /*!< Enables the end of auto-baud interrupt */\r
+#define UART_IER_ABTOINT_EN ((uint32_t) (1 << 9)) /*!< Enables the auto-baud time-out interrupt */\r
+#define UART_IER_BITMASK ((uint32_t) (0x307)) /*!< UART interrupt enable register bit mask */\r
+#define UART1_IER_BITMASK ((uint32_t) (0x38F)) /*!< UART1 interrupt enable register bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART interrupt identification register\r
+ */\r
+#define UART_IIR_INTSTAT_PEND ((uint32_t) (1 << 0)) /*!<Interrupt Status - Active low */\r
+#define UART_IIR_INTID_RLS ((uint32_t) (3 << 1)) /*!<Interrupt identification: Receive line status*/\r
+#define UART_IIR_INTID_RDA ((uint32_t) (2 << 1)) /*!<Interrupt identification: Receive data available*/\r
+#define UART_IIR_INTID_CTI ((uint32_t) (6 << 1)) /*!<Interrupt identification: Character time-out indicator*/\r
+#define UART_IIR_INTID_THRE ((uint32_t) (1 << 1)) /*!<Interrupt identification: THRE interrupt*/\r
+#define UART_IIR_INTID_MODEM ((uint32_t) (0 << 1)) /*!<Interrupt identification: Modem interrupt*/\r
+#define UART_IIR_INTID_MASK ((uint32_t) (7 << 1)) /*!<Interrupt identification: Interrupt ID mask */\r
+#define UART_IIR_FIFO_EN ((uint32_t) (3 << 6)) /*!<These bits are equivalent to UnFCR[0] */\r
+#define UART_IIR_ABEO_INT ((uint32_t) (1 << 8)) /*!< End of auto-baud interrupt */\r
+#define UART_IIR_ABTO_INT ((uint32_t) (1 << 9)) /*!< Auto-baud time-out interrupt */\r
+#define UART_IIR_BITMASK ((uint32_t) (0x3CF)) /*!< UART interrupt identification register bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART FIFO control register\r
+ */\r
+#define UART_FCR_FIFO_EN ((uint8_t) (1 << 0)) /*!< UART FIFO enable */\r
+#define UART_FCR_RX_RS ((uint8_t) (1 << 1)) /*!< UART FIFO RX reset */\r
+#define UART_FCR_TX_RS ((uint8_t) (1 << 2)) /*!< UART FIFO TX reset */\r
+#define UART_FCR_DMAMODE_SEL ((uint8_t) (1 << 3)) /*!< UART DMA mode selection */\r
+#define UART_FCR_TRG_LEV0 ((uint8_t) (0)) /*!< UART FIFO trigger level 0: 1 character */\r
+#define UART_FCR_TRG_LEV1 ((uint8_t) (1 << 6)) /*!< UART FIFO trigger level 1: 4 character */\r
+#define UART_FCR_TRG_LEV2 ((uint8_t) (2 << 6)) /*!< UART FIFO trigger level 2: 8 character */\r
+#define UART_FCR_TRG_LEV3 ((uint8_t) (3 << 6)) /*!< UART FIFO trigger level 3: 14 character */\r
+#define UART_FCR_BITMASK ((uint8_t) (0xCF)) /*!< UART FIFO control bit mask */\r
+#define UART_TX_FIFO_SIZE (16)\r
+\r
+/**\r
+ * @brief Macro defines for UART line control register\r
+ */\r
+#define UART_LCR_WLEN5 ((uint8_t) (0)) /*!< UART 5 bit data mode */\r
+#define UART_LCR_WLEN6 ((uint8_t) (1 << 0)) /*!< UART 6 bit data mode */\r
+#define UART_LCR_WLEN7 ((uint8_t) (2 << 0)) /*!< UART 7 bit data mode */\r
+#define UART_LCR_WLEN8 ((uint8_t) (3 << 0)) /*!< UART 8 bit data mode */\r
+#define UART_LCR_SBS_1BIT ((uint8_t) (0 << 2)) /*!< UART One Stop Bit Select */\r
+#define UART_LCR_SBS_2BIT ((uint8_t) (1 << 2)) /*!< UART Two Stop Bits Select */\r
+#define UART_LCR_PARITY_EN ((uint8_t) (1 << 3)) /*!< UART Parity Enable */\r
+#define UART_LCR_PARITY_DIS ((uint8_t) (0 << 3)) /*!< UART Parity Disable */\r
+#define UART_LCR_PARITY_ODD ((uint8_t) (0)) /*!< UART Odd Parity Select */\r
+#define UART_LCR_PARITY_EVEN ((uint8_t) (1 << 4)) /*!< UART Even Parity Select */\r
+#define UART_LCR_PARITY_F_1 ((uint8_t) (2 << 4)) /*!< UART force 1 stick parity */\r
+#define UART_LCR_PARITY_F_0 ((uint8_t) (3 << 4)) /*!< UART force 0 stick parity */\r
+#define UART_LCR_BREAK_EN ((uint8_t) (1 << 6)) /*!< UART Transmission Break enable */\r
+#define UART_LCR_DLAB_EN ((uint8_t) (1 << 7)) /*!< UART Divisor Latches Access bit enable */\r
+#define UART_LCR_BITMASK ((uint8_t) (0xFF)) /*!< UART line control bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART Modem control register\r
+ */\r
+#define UART_MCR_DTR_CTRL ((uint8_t) (1 << 0)) /*!< Source for modem output pin DTR */\r
+#define UART_MCR_RTS_CTRL ((uint8_t) (1 << 1)) /*!< Source for modem output pin RTS */\r
+#define UART_MCR_LOOPB_EN ((uint8_t) (1 << 4)) /*!< Loop back mode select */\r
+#define UART_MCR_AUTO_RTS_EN ((uint8_t) (1 << 6)) /*!< Enable Auto RTS flow-control */\r
+#define UART_MCR_AUTO_CTS_EN ((uint8_t) (1 << 7)) /*!< Enable Auto CTS flow-control */\r
+#define UART_MCR_BITMASK ((uint8_t) (0x0F3)) /*!< UART1 bit mask value */\r
+\r
+/**\r
+ * @brief Macro defines for UART line status register\r
+ */\r
+#define UART_LSR_RDR ((uint8_t) (1 << 0)) /*!<Line status register: Receive data ready*/\r
+#define UART_LSR_OE ((uint8_t) (1 << 1)) /*!<Line status register: Overrun error*/\r
+#define UART_LSR_PE ((uint8_t) (1 << 2)) /*!<Line status register: Parity error*/\r
+#define UART_LSR_FE ((uint8_t) (1 << 3)) /*!<Line status register: Framing error*/\r
+#define UART_LSR_BI ((uint8_t) (1 << 4)) /*!<Line status register: Break interrupt*/\r
+#define UART_LSR_THRE ((uint8_t) (1 << 5)) /*!<Line status register: Transmit holding register empty*/\r
+#define UART_LSR_TEMT ((uint8_t) (1 << 6)) /*!<Line status register: Transmitter empty*/\r
+#define UART_LSR_RXFE ((uint8_t) (1 << 7)) /*!<Error in RX FIFO*/\r
+#define UART_LSR_BITMASK ((uint8_t) (0xFF)) /*!<UART Line status bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART Modem status register\r
+ */\r
+#define UART_MSR_DELTA_CTS ((uint8_t) (1 << 0)) /*!< Set upon state change of input CTS */\r
+#define UART_MSR_DELTA_DSR ((uint8_t) (1 << 1)) /*!< Set upon state change of input DSR */\r
+#define UART_MSR_LO2HI_RI ((uint8_t) (1 << 2)) /*!< Set upon low to high transition of input RI */\r
+#define UART_MSR_DELTA_DCD ((uint8_t) (1 << 3)) /*!< Set upon state change of input DCD */\r
+#define UART_MSR_CTS ((uint8_t) (1 << 4)) /*!< Clear To Send State */\r
+#define UART_MSR_DSR ((uint8_t) (1 << 5)) /*!< Data Set Ready State */\r
+#define UART_MSR_RI ((uint8_t) (1 << 6)) /*!< Ring Indicator State */\r
+#define UART_MSR_DCD ((uint8_t) (1 << 7)) /*!< Data Carrier Detect State */\r
+#define UART_MSR_BITMASK ((uint8_t) (0xFF)) /*!< MSR register bit-mask value */\r
+\r
+/**\r
+ * @brief Macro defines for UART Scratch Pad register\r
+ */\r
+#define UART_SCR_BIMASK ((uint8_t) (0xFF)) /*!< UART Scratch Pad bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART Auto baudrate control register\r
+ */\r
+#define UART_ACR_START ((uint32_t) (1 << 0)) /*!< UART Auto-baud start */\r
+#define UART_ACR_MODE ((uint32_t) (1 << 1)) /*!< UART Auto baudrate Mode 1 */\r
+#define UART_ACR_AUTO_RESTART ((uint32_t) (1 << 2)) /*!< UART Auto baudrate restart */\r
+#define UART_ACR_ABEOINT_CLR ((uint32_t) (1 << 8)) /*!< UART End of auto-baud interrupt clear */\r
+#define UART_ACR_ABTOINT_CLR ((uint32_t) (1 << 9)) /*!< UART Auto-baud time-out interrupt clear */\r
+#define UART_ACR_BITMASK ((uint32_t) (0x307)) /*!< UART Auto Baudrate register bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART IrDA control register\r
+ */\r
+#define UART_ICR_IRDAEN ((uint32_t) (1 << 0)) /*!< IrDA mode enable */\r
+#define UART_ICR_IRDAINV ((uint32_t) (1 << 1)) /*!< IrDA serial input inverted */\r
+#define UART_ICR_FIXPULSE_EN ((uint32_t) (1 << 2)) /*!< IrDA fixed pulse width mode */\r
+#define UART_ICR_PULSEDIV(n) ((uint32_t) ((n & 0x07) << 3)) /*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */\r
+#define UART_ICR_BITMASK ((uint32_t) (0x3F)) /*!< UART IRDA bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART half duplex register\r
+ */\r
+#define UART_HDEN_HDEN ((uint32_t) (1 << 0)) /*!< enable half-duplex mode*/\r
+\r
+/**\r
+ * @brief Macro defines for UART smart card interface control register\r
+ */\r
+#define UART_SCICTRL_SCIEN ((uint32_t) (1 << 0)) /*!< enable asynchronous half-duplex smart card interface*/\r
+#define UART_SCICTRL_NACKDIS ((uint32_t) (1 << 1)) /*!< NACK response is inhibited*/\r
+#define UART_SCICTRL_PROTSEL_T1 ((uint32_t) (1 << 2)) /*!< ISO7816-3 protocol T1 is selected*/\r
+#define UART_SCICTRL_TXRETRY(n) ((uint32_t) ((n & 0x07) << 5)) /*!< number of retransmission*/\r
+#define UART_SCICTRL_GUARDTIME(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< Extra guard time*/\r
+\r
+/**\r
+ * @brief Macro defines for UART synchronous control register\r
+ */\r
+#define UART_SYNCCTRL_SYNC ((uint32_t) (1 << 0)) /*!< enable synchronous mode*/\r
+#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t) (1 << 1)) /*!< synchronous master mode*/\r
+#define UART_SYNCCTRL_FES ((uint32_t) (1 << 2)) /*!< sample on falling edge*/\r
+#define UART_SYNCCTRL_TSBYPASS ((uint32_t) (1 << 3)) /*!< to be defined*/\r
+#define UART_SYNCCTRL_CSCEN ((uint32_t) (1 << 4)) /*!< continuous running clock enable (master mode only)*/\r
+#define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t) (1 << 5)) /*!< do not send start/stop bit*/\r
+#define UART_SYNCCTRL_CCCLR ((uint32_t) (1 << 6)) /*!< stop continuous clock*/\r
+\r
+/**\r
+ * @brief Macro defines for UART Fractional divider register\r
+ */\r
+#define UART_FDR_DIVADDVAL(n) ((uint32_t) (n & 0x0F)) /*!< Baud-rate generation pre-scaler divisor */\r
+#define UART_FDR_MULVAL(n) ((uint32_t) ((n << 4) & 0xF0)) /*!< Baud-rate pre-scaler multiplier value */\r
+#define UART_FDR_BITMASK ((uint32_t) (0xFF)) /*!< UART Fractional Divider register bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART Tx Enable register\r
+ */\r
+#define UART_TER1_TXEN ((uint8_t) (1 << 7)) /*!< Transmit enable bit */\r
+#define UART_TER1_BITMASK ((uint8_t) (0x80)) /*!< UART Transmit Enable Register bit mask */\r
+#define UART_TER2_TXEN ((uint8_t) (1 << 0)) /*!< Transmit enable bit */\r
+#define UART_TER2_BITMASK ((uint8_t) (0x01)) /*!< UART Transmit Enable Register bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART1 RS485 Control register\r
+ */\r
+#define UART_RS485CTRL_NMM_EN ((uint32_t) (1 << 0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */\r
+#define UART_RS485CTRL_RX_DIS ((uint32_t) (1 << 1)) /*!< The receiver is disabled */\r
+#define UART_RS485CTRL_AADEN ((uint32_t) (1 << 2)) /*!< Auto Address Detect (AAD) is enabled */\r
+#define UART_RS485CTRL_SEL_DTR ((uint32_t) (1 << 3)) /*!< If direction control is enabled (bit DCTRL = 1), pin DTR is\r
+ used for direction control */\r
+#define UART_RS485CTRL_DCTRL_EN ((uint32_t) (1 << 4)) /*!< Enable Auto Direction Control */\r
+#define UART_RS485CTRL_OINV_1 ((uint32_t) (1 << 5)) /*!< This bit reverses the polarity of the direction\r
+ control signal on the RTS (or DTR) pin. The direction control pin\r
+ will be driven to logic "1" when the transmitter has data to be sent */\r
+#define UART_RS485CTRL_BITMASK ((uint32_t) (0x3F)) /*!< RS485 control bit-mask value */\r
+\r
+/**\r
+ * @brief Macro defines for UART1 RS-485 Address Match register\r
+ */\r
+#define UART_RS485ADRMATCH_BITMASK ((uint8_t) (0xFF)) /*!< Bit mask value */\r
+\r
+/**\r
+ * @brief Macro defines for UART1 RS-485 Delay value register\r
+ */\r
+#define UART_RS485DLY_BITMASK ((uint8_t) (0xFF)) /*!< Bit mask value */\r
+\r
+/**\r
+ * @brief Macro defines for UART FIFO Level register\r
+ */\r
+#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t) (n & 0x0F)) /*!< Reflects the current level of the UART receiver FIFO */\r
+#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t) ((n >> 8) & 0x0F)) /*!< Reflects the current level of the UART transmitter FIFO */\r
+#define UART_FIFOLVL_BITMASK ((uint32_t) (0x0F0F)) /*!< UART FIFO Level Register bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for Ring Buffer\r
+ */\r
+#define UART_RING_BUFSIZE 256 /*!< buffer size definition */\r
+#define __BUF_MASK (UART_RING_BUFSIZE - 1) /*!< Buf mask */\r
+#define __BUF_IS_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 1) & __BUF_MASK)) /*!< Check buf is full or not */\r
+#define __BUF_WILL_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 2) & __BUF_MASK)) /*!< Check buf will be full in next receiving or not */\r
+#define __BUF_IS_EMPTY(head, tail) ((head & __BUF_MASK) == (tail & __BUF_MASK)) /*!< Check buf is empty */\r
+#define __BUF_RESET(bufidx) (bufidx = 0) /*!< Reset buf */\r
+#define __BUF_INCR(bufidx) (bufidx = (bufidx + 1) & __BUF_MASK) /*!< Increase buf */\r
+\r
+/**\r
+ * @brief UART Ring buffer structure\r
+ */\r
+typedef struct {\r
+ __IO uint32_t tx_head; /*!< UART Tx ring buffer head index */\r
+ __IO uint32_t tx_tail; /*!< UART Tx ring buffer tail index */\r
+ __IO uint32_t rx_head; /*!< UART Rx ring buffer head index */\r
+ __IO uint32_t rx_tail; /*!< UART Rx ring buffer tail index */\r
+ __IO uint8_t tx[UART_RING_BUFSIZE]; /*!< UART Tx data ring buffer */\r
+ __IO uint8_t rx[UART_RING_BUFSIZE]; /*!< UART Rx data ring buffer */\r
+} UART_RingBuffer_T;\r
+\r
+/**\r
+ * @brief UART Line Status Type definition\r
+ */\r
+typedef enum IP_UART_LS {\r
+ UART_LINESTAT_RDR = UART_LSR_RDR, /*!< Line status register: Receive data ready*/\r
+ UART_LINESTAT_OE = UART_LSR_OE, /*!< Line status register: Overrun error*/\r
+ UART_LINESTAT_PE = UART_LSR_PE, /*!< Line status register: Parity error*/\r
+ UART_LINESTAT_FE = UART_LSR_FE, /*!< Line status register: Framing error*/\r
+ UART_LINESTAT_BI = UART_LSR_BI, /*!< Line status register: Break interrupt*/\r
+ UART_LINESTAT_THRE = UART_LSR_THRE, /*!< Line status register: Transmit holding register empty*/\r
+ UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!< Line status register: Transmitter empty*/\r
+ UART_LINESTAT_RXFE = UART_LSR_RXFE /*!< Error in RX FIFO*/\r
+} IP_UART_LS_T;\r
+\r
+/**\r
+ * @brief UART Full modem - Signal states definition\r
+ */\r
+typedef enum IP_UART_SIGNAL_STATE {\r
+ INACTIVE = 0, /*!< In-active state */\r
+ ACTIVE = !INACTIVE /*!< Active state */\r
+} IP_UART_SIGNAL_STATE_T;\r
+\r
+/**\r
+ * @brief UART modem status type definition\r
+ */\r
+typedef enum IP_UART_MODEM_STAT {\r
+ UART_MODEM_STAT_DELTA_CTS = UART_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */\r
+ UART_MODEM_STAT_DELTA_DSR = UART_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */\r
+ UART_MODEM_STAT_LO2HI_RI = UART_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */\r
+ UART_MODEM_STAT_DELTA_DCD = UART_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */\r
+ UART_MODEM_STAT_CTS = UART_MSR_CTS, /*!< Clear To Send State */\r
+ UART_MODEM_STAT_DSR = UART_MSR_DSR, /*!< Data Set Ready State */\r
+ UART_MODEM_STAT_RI = UART_MSR_RI, /*!< Ring Indicator State */\r
+ UART_MODEM_STAT_DCD = UART_MSR_DCD /*!< Data Carrier Detect State */\r
+} IP_UART_MODEM_STAT_T;\r
+\r
+/**\r
+ * @brief Modem output pin type definition\r
+ */\r
+typedef enum IP_UART_MODEM_PIN {\r
+ UART_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */\r
+ UART_MODEM_PIN_RTS /*!< Source for modem output pin RTS */\r
+} IP_UART_MODEM_PIN_T;\r
+\r
+/**\r
+ * @brief UART Modem mode type definition\r
+ */\r
+typedef enum IP_UART_MODEM_MODE {\r
+ UART_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */\r
+ UART_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */\r
+ UART_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */\r
+} IP_UART_MODEM_MODE_T;\r
+\r
+/**\r
+ * @brief UART Interrupt Type definitions\r
+ */\r
+typedef enum IP_UART_INT {\r
+ UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/\r
+ UART_INTCFG_THRE, /*!< THR Interrupt enable*/\r
+ UART_INTCFG_RLS, /*!< RX line status interrupt enable*/\r
+ UART_INTCFG_MS, /*!< Modem status interrupt enable */\r
+ UART_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable */\r
+ UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */\r
+ UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */\r
+} IP_UART_INT_T;\r
+\r
+/**\r
+ * @brief UART Parity type definitions\r
+ */\r
+typedef enum IP_UART_PARITY {\r
+ UART_PARITY_NONE = 0, /*!< No parity */\r
+ UART_PARITY_ODD = (4 << 3), /*!< Odd parity */\r
+ UART_PARITY_EVEN = (5 << 3), /*!< Even parity */\r
+ UART_PARITY_SP_1 = (6 << 3), /*!< Forced "1" stick parity */\r
+ UART_PARITY_SP_0 = (7 << 3) /*!< Forced "0" stick parity */\r
+} IP_UART_PARITY_T;\r
+\r
+/**\r
+ * @brief FIFO Level type definitions\r
+ */\r
+typedef enum IP_UART_FITO_LEVEL {\r
+ UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */\r
+ UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */\r
+ UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */\r
+ UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */\r
+} IP_UART_FITO_LEVEL_T;\r
+\r
+/**\r
+ * @brief UART Stop bit type definitions\r
+ */\r
+typedef enum IP_UART_STOPBIT {\r
+ UART_STOPBIT_1 = 0, /*!< UART One Stop Bit Select */\r
+ UART_STOPBIT_2 = (1 << 2) /*!< UART Two Stop Bits Select */\r
+} IP_UART_STOPBIT_T;\r
+\r
+/**\r
+ * @brief UART Databit type definitions\r
+ */\r
+typedef enum IP_UART_DATABIT {\r
+ UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */\r
+ UART_DATABIT_6, /*!< UART 6 bit data mode */\r
+ UART_DATABIT_7, /*!< UART 7 bit data mode */\r
+ UART_DATABIT_8 /*!< UART 8 bit data mode */\r
+} IP_UART_DATABIT_T;\r
+\r
+/**\r
+ * @brief UART ID\r
+ */\r
+typedef enum IP_UART_ID {\r
+ UART_0 = 0,\r
+ UART_1,\r
+ UART_2,\r
+ UART_3,\r
+ UART_4,\r
+} IP_UART_ID_T;\r
+\r
+/**\r
+ * @brief UART Interrupt Status\r
+ */\r
+typedef enum IP_UART_INT_STATUS {\r
+ UART_INTSTS_ERROR = 1 << 0, /*!< UART Interrupt Error*/\r
+ UART_INTSTS_RTS = 1 << 1, /*!< UART Interrupt status: Ready to Send*/\r
+ UART_INTSTS_RTR = 1 << 2, /*!< UART Interrupt status: Ready to Receive*/\r
+ UART_INTSTS_ABEO = UART_IIR_ABEO_INT, /*!< UART End of auto-baud interrupt */\r
+ UART_INTSTS_ABTO = UART_IIR_ABTO_INT /*!< UART Auto-baud time-out interrupt */\r
+} IP_UART_INT_STATUS_T;\r
+\r
+/**\r
+ * @brief UART Auto-baudrate mode type definition\r
+ */\r
+typedef enum IP_UART_AB_MODE {\r
+ UART_AUTOBAUD_MODE0 = 0, /*!< UART Auto baudrate Mode 0 */\r
+ UART_AUTOBAUD_MODE1, /*!< UART Auto baudrate Mode 1 */\r
+} IP_UART_AB_MODE_T;\r
+\r
+/**\r
+ * @brief Auto Baudrate mode configuration type definition\r
+ */\r
+typedef struct {\r
+ IP_UART_AB_MODE_T ABMode; /*!< Autobaudrate mode */\r
+ FunctionalState AutoRestart; /*!< Auto Restart state */\r
+} UART_AB_CFG_T;\r
+\r
+/**\r
+ * @brief UART FIFO Configuration Structure definition\r
+ */\r
+typedef struct {\r
+ FunctionalState FIFO_ResetRxBuf; /*!< Reset Rx FIFO command state , should be:\r
+ - ENABLE: Reset Rx FIFO in UART\r
+ - DISABLE: Do not reset Rx FIFO in UART\r
+ */\r
+ FunctionalState FIFO_ResetTxBuf; /*!< Reset Tx FIFO command state , should be:\r
+ - ENABLE: Reset Tx FIFO in UART\r
+ - DISABLE: Do not reset Tx FIFO in UART\r
+ */\r
+ FunctionalState FIFO_DMAMode; /*!< DMA mode, should be:\r
+ - ENABLE: Enable DMA mode in UART\r
+ - DISABLE: Disable DMA mode in UART\r
+ */\r
+ IP_UART_FITO_LEVEL_T FIFO_Level; /*!< Rx FIFO trigger level, should be:\r
+ - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character\r
+ - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character\r
+ - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character\r
+ - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character\r
+ */\r
+} UART_FIFO_CFG_T;\r
+\r
+/**\r
+ * @brief Initializes the UARTx peripheral according to the specified parameters in the UART_ConfigStruct.\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param UARTPort : UART ID type\r
+ * @return Nothing\r
+ */\r
+void IP_UART_Init(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort);\r
+\r
+/**\r
+ * @brief De-initializes the UARTx peripheral registers to their default reset values.\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param UARTPort : UART ID type\r
+ * @return Nothing\r
+ */\r
+void IP_UART_DeInit(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort);\r
+\r
+/**\r
+ * @brief Determines best dividers to get a target clock rate\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param baudrate : Desired UART baud rate.\r
+ * @param uClk : Current Uart Block Clock.\r
+ * @return Error status, could be SUCCESS or ERROR\r
+ */\r
+Status IP_UART_SetBaud(IP_USART_001_T *pUART, uint32_t baudrate, uint32_t uClk);\r
+\r
+/**\r
+ * @brief Configure data width, parity mode and stop bits\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param Databits : UART Data width, should be:\r
+ * UART_DATABIT_5: UART 5 bit data mode\r
+ * UART_DATABIT_6: UART 6 bit data mode\r
+ * UART_DATABIT_7: UART 7 bit data mode\r
+ * UART_DATABIT_8: UART 8 bit data mode\r
+ * @param Parity : UART Parity mode, should be:\r
+ * UART_PARITY_NONE: No parity\r
+ * UART_PARITY_ODD: Odd parity\r
+ * UART_PARITY_EVEN: Even parity\r
+ * UART_PARITY_SP_1: Forced "1" stick parity\r
+ * UART_PARITY_SP_0: Forced "0" stick parity\r
+ * @param Stopbits : Number of stop bits, should be:\r
+ * UART_STOPBIT_1: One Stop Bit Select\r
+ * UART_STOPBIT_2: Two Stop Bits Select\r
+ * @return Nothing\r
+ */\r
+void IP_UART_ConfigData(IP_USART_001_T *pUART,\r
+ IP_UART_DATABIT_T Databits,\r
+ IP_UART_PARITY_T Parity,\r
+ IP_UART_STOPBIT_T Stopbits);\r
+\r
+/* UART Send/Receive functions -------------------------------------------------*/\r
+/**\r
+ * @brief Transmit a single data through UART peripheral\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param data : Data to transmit (must be 8-bit long)\r
+ * @return Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty)\r
+ */\r
+Status IP_UART_SendByte(IP_USART_001_T *pUART, uint8_t data);\r
+\r
+/**\r
+ * @brief Receive a single data from UART peripheral\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param *Data : Pointer to Data to receive (must be 8-bit long)\r
+ * @return Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet)\r
+ */\r
+Status IP_UART_ReceiveByte(IP_USART_001_T *pUART, uint8_t *Data);\r
+\r
+/**\r
+ * @brief Send a block of data via UART peripheral\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param txbuf : Pointer to Transmit buffer\r
+ * @param buflen : Length of Transmit buffer\r
+ * @param flag : Flag used in UART transfer, should be NONE_BLOCKING or BLOCKING\r
+ * @return Number of bytes sent\r
+ *\r
+ * Note: when using UART in BLOCKING mode, a time-out condition is used\r
+ * via defined symbol UART_BLOCKING_TIMEOUT.\r
+ */\r
+uint32_t IP_UART_Send(IP_USART_001_T *pUART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_T flag);\r
+\r
+/**\r
+ * @brief Receive a block of data via UART peripheral\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param rxbuf : Pointer to Received buffer\r
+ * @param buflen : Length of Received buffer\r
+ * @param flag : Flag mode, should be NONE_BLOCKING or BLOCKING\r
+ * @return Number of bytes received\r
+ * @note\r
+ * Note: when using UART in BLOCKING mode, a time-out condition is used\r
+ * via defined symbol UART_BLOCKING_TIMEOUT.\r
+ */\r
+uint32_t IP_UART_Receive(IP_USART_001_T *pUART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_T flag);\r
+\r
+/* UART operate functions -------------------------------------------------------*/\r
+/**\r
+ * @brief Enable or disable specified UART interrupt.\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param UARTIntCfg : Specifies the interrupt flag, should be one of the following:\r
+ * - UART_INTCFG_RBR : RBR Interrupt enable\r
+ * - UART_INTCFG_THRE : THR Interrupt enable\r
+ * - UART_INTCFG_RLS : RX line status interrupt enable\r
+ * - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only)\r
+ * - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only)\r
+ * - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt\r
+ * - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt\r
+ * @param NewState : New state of specified UART interrupt type, should be:\r
+ * - ENALBE : Enable this UART interrupt type\r
+ * - DISALBE : Disable this UART interrupt type\r
+ * @return Nothing\r
+ */\r
+void IP_UART_IntConfig(IP_USART_001_T *pUART, IP_UART_INT_T UARTIntCfg, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Get Source Interrupt\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @return Return the value of IIR register\r
+ */\r
+uint32_t IP_UART_IntGetStatus(IP_USART_001_T *pUART);\r
+\r
+/**\r
+ * @brief Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @return Nothing\r
+ */\r
+void IP_UART_ForceBreak(IP_USART_001_T *pUART);\r
+\r
+/**\r
+ * @brief Get current value of Line Status register in UART peripheral.\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @return Current value of Line Status register in UART peripheral\r
+ * @note\r
+ * The return value of this function must be ANDed with each member in UART_LS_T\r
+ * enumeration to determine current flag status corresponding to each Line status type. Because\r
+ * some flags in Line Status register will be cleared after reading, the next reading Line\r
+ * Status register could not be correct. So this function used to read Line status register\r
+ * in one time only, then the return value used to check all flags.\r
+ */\r
+uint8_t IP_UART_GetLineStatus(IP_USART_001_T *pUART);\r
+\r
+/**\r
+ * @brief Check whether if UART is busy or not\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @return RESET if UART is not busy, otherwise return SET.\r
+ */\r
+FlagStatus IP_UART_CheckBusy(IP_USART_001_T *pUART);\r
+\r
+/**\r
+ * @brief Enable/Disable transmission on UART TxD pin\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param UARTPort : UART ID type\r
+ * @param NewState : New State of Tx transmission function, should be ENABLE or DISABLE\r
+ * @return Nothing\r
+ */\r
+void IP_UART_TxCmd(IP_USART_001_T *pUART, IP_UART_ID_T UARTPort, FunctionalState NewState);\r
+\r
+/* UART FIFO functions ----------------------------------------------------------*/\r
+/**\r
+ * @brief Configure FIFO function on selected UART peripheral\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param FIFOCfg : Pointer to a UART_FIFO_CFG_T Structure that contains specified information about FIFO configuration\r
+ * @return Nothing\r
+ */\r
+void IP_UART_FIFOConfig(IP_USART_001_T *pUART, UART_FIFO_CFG_T *FIFOCfg);\r
+\r
+/**\r
+ * @brief Fills each UART_FIFOInitStruct member with its default value:\r
+ * - FIFO_DMAMode = DISABLE\r
+ * - FIFO_Level = UART_FIFO_TRGLEV0\r
+ * - FIFO_ResetRxBuf = ENABLE\r
+ * - FIFO_ResetTxBuf = ENABLE\r
+ * - FIFO_State = ENABLE\r
+ * @param UART_FIFOInitStruct : Pointer to a UART_FIFO_CFG_T structure which will be initialized.\r
+ * @return Nothing\r
+ */\r
+void IP_UART_FIFOConfigStructInit(UART_FIFO_CFG_T *UART_FIFOInitStruct);\r
+\r
+/**\r
+ * @brief Start/Stop Auto Baudrate activity\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param ABConfigStruct : A pointer to UART_AB_CFG_T structure that\r
+ * contains specified information about UAR auto baud configuration\r
+ * @param NewState : New State of Auto baudrate activity, should be ENABLE or DISABLE\r
+ * @return Nothing\r
+ * @note Auto-baudrate mode enable bit will be cleared once this mode completed.\r
+ */\r
+void IP_UART_ABCmd(IP_USART_001_T *pUART, UART_AB_CFG_T *ABConfigStruct, FunctionalState NewState);\r
+\r
+/**\r
+ * @brief Clear Autobaud Interrupt\r
+ * @param pUART : Pointer to selected UARTx peripheral\r
+ * @param ABIntType : type of auto-baud interrupt, should be:\r
+ * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt\r
+ * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt\r
+ * @return Nothing\r
+ */\r
+void IP_UART_ABClearIntPending(IP_USART_001_T *pUART, IP_UART_INT_STATUS_T ABIntType);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __USART_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief UART/USART Registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __USART_004_H_\r
+#define __USART_004_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_USART_004 IP: USART register block and driver (004)\r
+ * @ingroup IP_Drivers\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief USART register block structure\r
+ */\r
+typedef struct { /*!< USARTn Structure */\r
+\r
+ union {\r
+ __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */\r
+ __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */\r
+ __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */\r
+ };\r
+\r
+ union {\r
+ __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */\r
+ __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */\r
+ };\r
+\r
+ union {\r
+ __O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */\r
+ __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */\r
+ };\r
+\r
+ __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */\r
+ __IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */\r
+ __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */\r
+ __I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */\r
+ __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */\r
+ __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */\r
+ __IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */\r
+ __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */\r
+\r
+ __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */\r
+ __IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */\r
+ uint32_t RESERVED0[3];\r
+ __IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */\r
+ __I uint32_t RESERVED1[1];\r
+ __IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */\r
+\r
+ __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */\r
+ __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */\r
+ __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */\r
+\r
+ union {\r
+ __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */\r
+ __I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */\r
+ };\r
+\r
+ __IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */\r
+} IP_USART_001_T;\r
+\r
+#define UART_RBR_MASKBIT (0xFF) /*!< UART Received Buffer mask bit (8 bits) */\r
+\r
+/**\r
+ * @brief Basic UART initialization\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Nothing\r
+ * @note This function performs very basic UART initialization\r
+ */\r
+void IP_UART_Init(IP_USART_001_T *pUART);\r
+\r
+/**\r
+ * @brief UART de-initialization\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_UART_DeInit(IP_USART_001_T *pUART) {}\r
+\r
+/**\r
+ * @brief Transmit a single byte through the UART peripheral\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param data : Byte to transmit\r
+ * @return Nothing\r
+ * @note This function attempts to place a byte into the UART transmit\r
+ * FIFO or transmit hold register regard regardless of UART state.\r
+ */\r
+STATIC INLINE void IP_UART_SendByte(IP_USART_001_T *pUART, const uint8_t data)\r
+{\r
+ pUART->THR = (uint32_t) data;\r
+}\r
+\r
+/**\r
+ * @brief Get a single data from UART peripheral\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return A single byte of data read\r
+ * @note This function reads a byte from the UART receive FIFO or\r
+ * receive hold register regard regardless of UART state.\r
+ */\r
+STATIC INLINE uint8_t IP_UART_ReadByte(IP_USART_001_T *pUART)\r
+{\r
+ return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);\r
+}\r
+\r
+/**\r
+ * @brief Macro defines for UART interrupt enable register\r
+ */\r
+#define UART_IER_RBRINT (1 << 0) /*!< RBR Interrupt enable*/\r
+#define UART_IER_THREINT (1 << 1) /*!< THR Interrupt enable*/\r
+#define UART_IER_RLSINT (1 << 2) /*!< RX line status interrupt enable*/\r
+#define UART_IER_MSINT (1 << 3) /*!< Modem status interrupt enable */\r
+#define UART_IER_CTSINT (1 << 7) /*!< CTS1 signal transition interrupt enable */\r
+#define UART_IER_ABEOINT (1 << 8) /*!< Enables the end of auto-baud interrupt */\r
+#define UART_IER_ABTOINT (1 << 9) /*!< Enables the auto-baud time-out interrupt */\r
+#define UART_IER_BITMASK (0x307) /*!< UART interrupt enable register bit mask */\r
+#define UART1_IER_BITMASK (0x38F) /*!< UART1 interrupt enable register bit mask */\r
+\r
+/**\r
+ * @brief Enable UART interrupts\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param intMask : Or'ed Interrupts to enable in the Interrupt Enable Register (IER)\r
+ * @return Nothing\r
+ * @note Use an Or'ed value of UART_IER_* definitions with this call\r
+ * to enable specific UART interrupts. The Divisor Latch Access Bit\r
+ * (DLAB) in LCR must be cleared in order to access the IER register.\r
+ * This function doesn't alter the DLAB state.\r
+ */\r
+STATIC INLINE void IP_UART_IntEnable(IP_USART_001_T *pUART, uint32_t intMask)\r
+{\r
+ pUART->IER |= intMask;\r
+}\r
+\r
+/**\r
+ * @brief Disable UART interrupts\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param intMask : Or'ed Interrupts to disable in the Interrupt Enable Register (IER)\r
+ * @return Nothing\r
+ * @note Use an Or'ed value of UART_IER_* definitions with this call\r
+ * to disable specific UART interrupts. The Divisor Latch Access Bit\r
+ * (DLAB) in LCR must be cleared in order to access the IER register.\r
+ * This function doesn't alter the DLAB state.\r
+ */\r
+STATIC INLINE void IP_UART_IntDisable(IP_USART_001_T *pUART, uint32_t intMask)\r
+{\r
+ pUART->IER &= ~intMask;\r
+}\r
+\r
+/**\r
+ * @brief Macro defines for UART interrupt identification register\r
+ */\r
+#define UART_IIR_INTSTAT_PEND (1 << 0) /*!<Interrupt Status - Active low */\r
+#define UART_IIR_INTID_RLS (3 << 1) /*!<Interrupt identification: Receive line status*/\r
+#define UART_IIR_INTID_RDA (2 << 1) /*!<Interrupt identification: Receive data available*/\r
+#define UART_IIR_INTID_CTI (6 << 1) /*!<Interrupt identification: Character time-out indicator*/\r
+#define UART_IIR_INTID_THRE (1 << 1) /*!<Interrupt identification: THRE interrupt*/\r
+#define UART_IIR_INTID_MODEM (0 << 1) /*!<Interrupt identification: Modem interrupt*/\r
+#define UART_IIR_INTID_MASK (7 << 1) /*!<Interrupt identification: Interrupt ID mask */\r
+#define UART_IIR_FIFO_EN (3 << 6) /*!<These bits are equivalent to UnFCR[0] */\r
+#define UART_IIR_ABEO_INT (1 << 8) /*!< End of auto-baud interrupt */\r
+#define UART_IIR_ABTO_INT (1 << 9) /*!< Auto-baud time-out interrupt */\r
+#define UART_IIR_BITMASK (0x3CF) /*!< UART interrupt identification register bit mask */\r
+\r
+/**\r
+ * @brief Read the Interrupt Identification Register (IIR)\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Current pending interrupt status per the IIR register\r
+ */\r
+STATIC INLINE uint32_t IP_UART_ReadIntIDReg(IP_USART_001_T *pUART)\r
+{\r
+ return pUART->IIR;\r
+}\r
+\r
+/**\r
+ * @brief Macro defines for UART FIFO control register\r
+ */\r
+#define UART_FCR_FIFO_EN (1 << 0) /*!< UART FIFO enable */\r
+#define UART_FCR_RX_RS (1 << 1) /*!< UART FIFO RX reset */\r
+#define UART_FCR_TX_RS (1 << 2) /*!< UART FIFO TX reset */\r
+#define UART_FCR_DMAMODE_SEL (1 << 3) /*!< UART DMA mode selection */\r
+#define UART_FCR_TRG_LEV0 (0) /*!< UART FIFO trigger level 0: 1 character */\r
+#define UART_FCR_TRG_LEV1 (1 << 6) /*!< UART FIFO trigger level 1: 4 character */\r
+#define UART_FCR_TRG_LEV2 (2 << 6) /*!< UART FIFO trigger level 2: 8 character */\r
+#define UART_FCR_TRG_LEV3 (3 << 6) /*!< UART FIFO trigger level 3: 14 character */\r
+#define UART_FCR_BITMASK (0xCF) /*!< UART FIFO control bit mask */\r
+#define UART_TX_FIFO_SIZE (16)\r
+\r
+/**\r
+ * @brief Setup the UART FIFOs\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param fcr : FIFO control register setup OR'ed flags\r
+ * @return Nothing\r
+ * @note Use an Or'ed value of UART_FCR_* definitions with this call\r
+ * to select specific options.\r
+ */\r
+STATIC INLINE void IP_UART_SetupFIFOS(IP_USART_001_T *pUART, uint32_t fcr)\r
+{\r
+ pUART->FCR = fcr;\r
+}\r
+\r
+/**\r
+ * @brief Macro defines for UART line control register\r
+ */\r
+#define UART_LCR_WLEN5 (0) /*!< UART 5 bit data mode */\r
+#define UART_LCR_WLEN6 (1 << 0) /*!< UART 6 bit data mode */\r
+#define UART_LCR_WLEN7 (2 << 0) /*!< UART 7 bit data mode */\r
+#define UART_LCR_WLEN8 (3 << 0) /*!< UART 8 bit data mode */\r
+#define UART_LCR_SBS_1BIT (0 << 2) /*!< UART One Stop Bit Select */\r
+#define UART_LCR_SBS_2BIT (1 << 2) /*!< UART Two Stop Bits Select */\r
+#define UART_LCR_PARITY_EN (1 << 3) /*!< UART Parity Enable */\r
+#define UART_LCR_PARITY_DIS (0 << 3) /*!< UART Parity Disable */\r
+#define UART_LCR_PARITY_ODD (0) /*!< UART Odd Parity Select */\r
+#define UART_LCR_PARITY_EVEN (1 << 4) /*!< UART Even Parity Select */\r
+#define UART_LCR_PARITY_F_1 (2 << 4) /*!< UART force 1 stick parity */\r
+#define UART_LCR_PARITY_F_0 (3 << 4) /*!< UART force 0 stick parity */\r
+#define UART_LCR_BREAK_EN (1 << 6) /*!< UART Transmission Break enable */\r
+#define UART_LCR_DLAB_EN (1 << 7) /*!< UART Divisor Latches Access bit enable */\r
+#define UART_LCR_BITMASK (0xFF) /*!< UART line control bit mask */\r
+\r
+/**\r
+ * @brief Setup the UART operation mode in the Line Control Register (LCR)\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param lcr : OR'ed flags\r
+ * @return Nothing\r
+ * @note Sets up the UART transmit mode (data bits, stop bits, parity,\r
+ * and break). Use an Or'ed value of UART_LCR_* definitions with this\r
+ * call to select specific options. Unless the UART_LCR_DLAB_EN\r
+ * option is passed in lcd, DLAB will be cleared and divisor access\r
+ * will be disabled.\r
+ */\r
+STATIC INLINE void IP_UART_SetMode(IP_USART_001_T *pUART, uint32_t lcr)\r
+{\r
+ pUART->LCR = lcr;\r
+}\r
+\r
+/**\r
+ * @brief Enable access to Divisor Latches\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_UART_EnableDivisorAccess(IP_USART_001_T *pUART)\r
+{\r
+ pUART->LCR |= UART_LCR_DLAB_EN;\r
+}\r
+\r
+/**\r
+ * @brief Disable access to Divisor Latches\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_UART_DisableDivisorAccess(IP_USART_001_T *pUART)\r
+{\r
+ pUART->LCR &= ~UART_LCR_DLAB_EN;\r
+}\r
+\r
+#define UART_DLL_MASKBIT (0xFF) /*!< Divisor latch LSB (DLL) bit mask */\r
+#define UART_DLM_MASKBIT (0xFF) /*!< Divisor latch MSB (DLM) bit mask */\r
+\r
+/**\r
+ * @brief Set LSB and MSB divisor latch registers\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param dll : Divisor Latch LSB value\r
+ * @param dlm : Divisor Latch MSB value\r
+ * @return Nothing\r
+ * @note The Divisor Latch Access Bit (DLAB) in LCR must be set in\r
+ * order to access the USART Divisor Latches. This function\r
+ * doesn't alter the DLAB state.\r
+ */\r
+STATIC INLINE void IP_UART_SetDivisorLatches(IP_USART_001_T *pUART, uint8_t dll, uint8_t dlm)\r
+{\r
+ pUART->DLL = (uint32_t) dll;\r
+ pUART->DLM = (uint32_t) dlm;\r
+}\r
+\r
+/**\r
+ * @brief Macro defines for UART Modem control register\r
+ */\r
+#define UART_MCR_DTR_CTRL (1 << 0) /*!< Source for modem output pin DTR */\r
+#define UART_MCR_RTS_CTRL (1 << 1) /*!< Source for modem output pin RTS */\r
+#define UART_MCR_LOOPB_EN (1 << 4) /*!< Loop back mode select */\r
+#define UART_MCR_AUTO_RTS_EN (1 << 6) /*!< Enable Auto RTS flow-control */\r
+#define UART_MCR_AUTO_CTS_EN (1 << 7) /*!< Enable Auto CTS flow-control */\r
+#define UART_MCR_BITMASK (0x0F3) /*!< UART1 bit mask value */\r
+\r
+/**\r
+ * @brief Return modem control register/status\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Modem control register (status)\r
+ * @note Mask bits of the returned status value with UART_MCR_*\r
+ * definitions for specific statuses.\r
+ */\r
+STATIC INLINE uint32_t IP_UART_ReadModemControl(IP_USART_001_T *pUART)\r
+{\r
+ return pUART->MCR;\r
+}\r
+\r
+/**\r
+ * @brief Set modem control register/status\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param mcr : Modem control register flags to set\r
+ * @return Nothing\r
+ * @note Use an Or'ed value of UART_MCR_* definitions with this\r
+ * call to set specific options.\r
+ */\r
+STATIC INLINE void IP_UART_SetModemControl(IP_USART_001_T *pUART, uint32_t mcr)\r
+{\r
+ pUART->MCR |= mcr;\r
+}\r
+\r
+/**\r
+ * @brief Clear modem control register/status\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param mcr : Modem control register flags to clear\r
+ * @return Nothing\r
+ * @note Use an Or'ed value of UART_MCR_* definitions with this\r
+ * call to clear specific options.\r
+ */\r
+STATIC INLINE void IP_UART_ClearModemControl(IP_USART_001_T *pUART, uint32_t mcr)\r
+{\r
+ pUART->MCR &= ~mcr;\r
+}\r
+\r
+/**\r
+ * @brief Macro defines for UART line status register\r
+ */\r
+#define UART_LSR_RDR (1 << 0) /*!< Line status register: Receive data ready */\r
+#define UART_LSR_OE (1 << 1) /*!< Line status register: Overrun error */\r
+#define UART_LSR_PE (1 << 2) /*!< Line status register: Parity error */\r
+#define UART_LSR_FE (1 << 3) /*!< Line status register: Framing error */\r
+#define UART_LSR_BI (1 << 4) /*!< Line status register: Break interrupt */\r
+#define UART_LSR_THRE (1 << 5) /*!< Line status register: Transmit holding register empty */\r
+#define UART_LSR_TEMT (1 << 6) /*!< Line status register: Transmitter empty */\r
+#define UART_LSR_RXFE (1 << 7) /*!< Error in RX FIFO */\r
+#define UART_LSR_BITMASK (0xFF) /*!< UART Line status bit mask */\r
+\r
+/**\r
+ * @brief Return Line Status register/status (LSR)\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Line Status register (status)\r
+ * @note Mask bits of the returned status value with UART_LSR_*\r
+ * definitions for specific statuses.\r
+ */\r
+STATIC INLINE uint32_t IP_UART_ReadLineStatus(IP_USART_001_T *pUART)\r
+{\r
+ return pUART->LSR;\r
+}\r
+\r
+/**\r
+ * @brief Macro defines for UART Modem status register\r
+ */\r
+#define UART_MSR_DELTA_CTS (1 << 0) /*!< Set upon state change of input CTS */\r
+#define UART_MSR_DELTA_DSR (1 << 1) /*!< Set upon state change of input DSR */\r
+#define UART_MSR_LO2HI_RI (1 << 2) /*!< Set upon low to high transition of input RI */\r
+#define UART_MSR_DELTA_DCD (1 << 3) /*!< Set upon state change of input DCD */\r
+#define UART_MSR_CTS (1 << 4) /*!< Clear To Send State */\r
+#define UART_MSR_DSR (1 << 5) /*!< Data Set Ready State */\r
+#define UART_MSR_RI (1 << 6) /*!< Ring Indicator State */\r
+#define UART_MSR_DCD (1 << 7) /*!< Data Carrier Detect State */\r
+#define UART_MSR_BITMASK (0xFF) /*!< MSR register bit-mask value */\r
+\r
+/**\r
+ * @brief Return Modem Status register/status (MSR)\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Modem Status register (status)\r
+ * @note Mask bits of the returned status value with UART_MSR_*\r
+ * definitions for specific statuses.\r
+ */\r
+STATIC INLINE uint32_t IP_UART_ReadModemStatus(IP_USART_001_T *pUART)\r
+{\r
+ return pUART->MSR;\r
+}\r
+\r
+/**\r
+ * @brief Write a byte to the scratchpad register\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param data : Byte value to write\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_UART_SetScratch(IP_USART_001_T *pUART, uint8_t data)\r
+{\r
+ pUART->SCR = (uint32_t) data;\r
+}\r
+\r
+/**\r
+ * @brief Returns current byte value in the scratchpad register\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Byte value read from scratchpad register\r
+ */\r
+STATIC INLINE uint8_t IP_UART_ReadScratch(IP_USART_001_T *pUART)\r
+{\r
+ return (uint8_t) (pUART->SCR & 0xFF);\r
+}\r
+\r
+/**\r
+ * @brief Macro defines for UART Auto baudrate control register\r
+ */\r
+#define UART_ACR_START (1 << 0) /*!< UART Auto-baud start */\r
+#define UART_ACR_MODE (1 << 1) /*!< UART Auto baudrate Mode 1 */\r
+#define UART_ACR_AUTO_RESTART (1 << 2) /*!< UART Auto baudrate restart */\r
+#define UART_ACR_ABEOINT_CLR (1 << 8) /*!< UART End of auto-baud interrupt clear */\r
+#define UART_ACR_ABTOINT_CLR (1 << 9) /*!< UART Auto-baud time-out interrupt clear */\r
+#define UART_ACR_BITMASK (0x307) /*!< UART Auto Baudrate register bit mask */\r
+\r
+/**\r
+ * @brief Set autobaud register options\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param acr : Or'ed values to set for ACR register\r
+ * @return Nothing\r
+ * @note Use an Or'ed value of UART_ACR_* definitions with this\r
+ * call to set specific options.\r
+ */\r
+STATIC INLINE void IP_UART_SetAutoBaudReg(IP_USART_001_T *pUART, uint32_t acr)\r
+{\r
+ pUART->ACR |= acr;\r
+}\r
+\r
+/**\r
+ * @brief Clear autobaud register options\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param acr : Or'ed values to clear for ACR register\r
+ * @return Nothing\r
+ * @note Use an Or'ed value of UART_ACR_* definitions with this\r
+ * call to clear specific options.\r
+ */\r
+STATIC INLINE void IP_UART_ClearAutoBaudReg(IP_USART_001_T *pUART, uint32_t acr)\r
+{\r
+ pUART->ACR &= ~acr;\r
+}\r
+\r
+/**\r
+ * @brief Enable transmission on UART TxD pin\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_UART_TXEnable(IP_USART_001_T *pUART)\r
+{\r
+ pUART->TER1 = (1 << 7);\r
+}\r
+\r
+/**\r
+ * @brief Disable transmission on UART TxD pin\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_UART_TXDisable(IP_USART_001_T *pUART)\r
+{\r
+ pUART->TER1 = 0;\r
+}\r
+\r
+/**\r
+ * @brief Macro defines for UART1 RS485 Control register\r
+ */\r
+#define UART_RS485CTRL_NMM_EN (1 << 0) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */\r
+#define UART_RS485CTRL_RX_DIS (1 << 1) /*!< The receiver is disabled */\r
+#define UART_RS485CTRL_AADEN (1 << 2) /*!< Auto Address Detect (AAD) is enabled */\r
+#define UART_RS485CTRL_SEL_DTR (1 << 3) /*!< If direction control is enabled (bit DCTRL = 1), pin DTR is\r
+ used for direction control */\r
+#define UART_RS485CTRL_DCTRL_EN (1 << 4) /*!< Enable Auto Direction Control */\r
+#define UART_RS485CTRL_OINV_1 (1 << 5) /*!< This bit reverses the polarity of the direction\r
+ control signal on the RTS (or DTR) pin. The direction control pin\r
+ will be driven to logic "1" when the transmitter has data to be sent */\r
+#define UART_RS485CTRL_BITMASK (0x3F) /*!< RS485 control bit-mask value */\r
+\r
+/**\r
+ * @brief Set RS485 control register options\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param ctrl : Or'ed values to set for RS485 control register\r
+ * @return Nothing\r
+ * @note Use an Or'ed value of UART_RS485CTRL_* definitions with this\r
+ * call to set specific options.\r
+ */\r
+STATIC INLINE void IP_UART_SetRS485Flags(IP_USART_001_T *pUART, uint32_t ctrl)\r
+{\r
+ pUART->RS485CTRL |= ctrl;\r
+}\r
+\r
+/**\r
+ * @brief Clear RS485 control register options\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param ctrl : Or'ed values to clear for RS485 control register\r
+ * @return Nothing\r
+ * @note Use an Or'ed value of UART_RS485CTRL_* definitions with this\r
+ * call to clear specific options.\r
+ */\r
+STATIC INLINE void IP_UART_ClearRS485Flags(IP_USART_001_T *pUART, uint32_t ctrl)\r
+{\r
+ pUART->RS485CTRL &= ~ctrl;\r
+}\r
+\r
+/**\r
+ * @brief Set RS485 address match value\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param addr : Address match value for RS-485/EIA-485 mode\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_UART_SetRS485Addr(IP_USART_001_T *pUART, uint8_t addr)\r
+{\r
+ pUART->RS485ADRMATCH = (uint32_t) addr;\r
+}\r
+\r
+/**\r
+ * @brief Read RS485 address match value\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return Address match value for RS-485/EIA-485 mode\r
+ */\r
+STATIC INLINE uint8_t IP_UART_GetRS485Addr(IP_USART_001_T *pUART)\r
+{\r
+ return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);\r
+}\r
+\r
+/**\r
+ * @brief Set RS485 direction control (RTS or DTR) delay value\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param dly : direction control (RTS or DTR) delay value\r
+ * @return Nothing\r
+ * @note This delay time is in periods of the baud clock. Any delay\r
+ * time from 0 to 255 bit times may be programmed.\r
+ */\r
+STATIC INLINE void IP_UART_SetRS485Delay(IP_USART_001_T *pUART, uint8_t dly)\r
+{\r
+ pUART->RS485DLY = (uint32_t) dly;\r
+}\r
+\r
+/**\r
+ * @brief Read RS485 direction control (RTS or DTR) delay value\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @return direction control (RTS or DTR) delay value\r
+ * @note This delay time is in periods of the baud clock. Any delay\r
+ * time from 0 to 255 bit times may be programmed.\r
+ */\r
+STATIC INLINE uint8_t IP_UART_GetRS485Delay(IP_USART_001_T *pUART)\r
+{\r
+ return (uint8_t) (pUART->RS485DLY & 0xFF);\r
+}\r
+\r
+/**\r
+ * @brief Determines and sets best dividers to get a target bit rate\r
+ * @param pUART : Pointer to selected UART peripheral\r
+ * @param baudrate : Target baud rate (baud rate = bit rate)\r
+ * @param uClk : Clock rate into UART peripheral\r
+ * @return The actual baud rate, or 0 if no rate can be found\r
+ * @note Once you've computed your baud rate, you can remove this function\r
+ * to make your image smaller.\r
+ */\r
+uint32_t IP_UART_SetBaud(IP_USART_001_T *pUART, uint32_t baudrate, uint32_t uClk);\r
+\r
+#if 0 // FIXME\r
+// FIXME\r
+// FDR handled at chip layer\r
+// OSR not ready\r
+// TER1 not ready\r
+// HDEN handled at chip layer\r
+// SCICTRL handled at chip layer\r
+// TER2 handled at chip layer\r
+\r
+/**\r
+ * @brief Macro defines for UART IrDA control register\r
+ */\r
+#define UART_ICR_IRDAEN ((uint32_t) (1 << 0)) /*!< IrDA mode enable */\r
+#define UART_ICR_IRDAINV ((uint32_t) (1 << 1)) /*!< IrDA serial input inverted */\r
+#define UART_ICR_FIXPULSE_EN ((uint32_t) (1 << 2)) /*!< IrDA fixed pulse width mode */\r
+#define UART_ICR_PULSEDIV(n) ((uint32_t) ((n & 0x07) << 3)) /*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */\r
+#define UART_ICR_BITMASK ((uint32_t) (0x3F)) /*!< UART IRDA bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART half duplex register\r
+ */\r
+#define UART_HDEN_HDEN ((uint32_t) (1 << 0)) /*!< enable half-duplex mode*/\r
+\r
+/**\r
+ * @brief Macro defines for UART smart card interface control register\r
+ */\r
+#define UART_SCICTRL_SCIEN ((uint32_t) (1 << 0)) /*!< enable asynchronous half-duplex smart card interface*/\r
+#define UART_SCICTRL_NACKDIS ((uint32_t) (1 << 1)) /*!< NACK response is inhibited*/\r
+#define UART_SCICTRL_PROTSEL_T1 ((uint32_t) (1 << 2)) /*!< ISO7816-3 protocol T1 is selected*/\r
+#define UART_SCICTRL_TXRETRY(n) ((uint32_t) ((n & 0x07) << 5)) /*!< number of retransmission*/\r
+#define UART_SCICTRL_GUARDTIME(n) ((uint32_t) ((n & 0xFF) << 8)) /*!< Extra guard time*/\r
+\r
+/**\r
+ * @brief Macro defines for UART Fractional divider register\r
+ */\r
+#define UART_FDR_DIVADDVAL(n) ((uint32_t) (n & 0x0F)) /*!< Baud-rate generation pre-scaler divisor */\r
+#define UART_FDR_MULVAL(n) ((uint32_t) ((n << 4) & 0xF0)) /*!< Baud-rate pre-scaler multiplier value */\r
+#define UART_FDR_BITMASK ((uint32_t) (0xFF)) /*!< UART Fractional Divider register bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART Tx Enable register\r
+ */\r
+#define UART_TER1_TXEN ((uint8_t) (1 << 7)) /*!< Transmit enable bit */\r
+#define UART_TER1_BITMASK ((uint8_t) (0x80)) /*!< UART Transmit Enable Register bit mask */\r
+#define UART_TER2_TXEN ((uint8_t) (1 << 0)) /*!< Transmit enable bit */\r
+#define UART_TER2_BITMASK ((uint8_t) (0x01)) /*!< UART Transmit Enable Register bit mask */\r
+\r
+/**\r
+ * @brief Macro defines for UART synchronous control register\r
+ */\r
+#define UART_SYNCCTRL_SYNC ((uint32_t) (1 << 0)) /*!< enable synchronous mode*/\r
+#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t) (1 << 1)) /*!< synchronous master mode*/\r
+#define UART_SYNCCTRL_FES ((uint32_t) (1 << 2)) /*!< sample on falling edge*/\r
+#define UART_SYNCCTRL_TSBYPASS ((uint32_t) (1 << 3)) /*!< to be defined*/\r
+#define UART_SYNCCTRL_CSCEN ((uint32_t) (1 << 4)) /*!< continuous running clock enable (master mode only)*/\r
+#define UART_SYNCCTRL_STARTSTOPDISABLE ((uint32_t) (1 << 5)) /*!< do not send start/stop bit*/\r
+#define UART_SYNCCTRL_CCCLR ((uint32_t) (1 << 6)) /*!< stop continuous clock*/\r
+\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __USART_004_H_ */\r
--- /dev/null
+/*
+ * @brief USB registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __USB_001_H_
+#define __USB_001_H_
+
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IP_USB_001 IP: USB Device, Host, & OTG register block and driver
+ * @ingroup IP_Drivers
+ * USB Device, Host, & OTG
+ * Note:
+ * @{
+ */
+
+/**
+ * @brief USB register block structure
+ */
+typedef struct
+{
+ __I uint32_t Revision; /* USB Host Registers */
+ __IO uint32_t Control;
+ __IO uint32_t CommandStatus;
+ __IO uint32_t InterruptStatus;
+ __IO uint32_t InterruptEnable;
+ __IO uint32_t InterruptDisable;
+ __IO uint32_t HCCA;
+ __I uint32_t PeriodCurrentED;
+ __IO uint32_t ControlHeadED;
+ __IO uint32_t ControlCurrentED;
+ __IO uint32_t BulkHeadED;
+ __IO uint32_t BulkCurrentED;
+ __I uint32_t DoneHead;
+ __IO uint32_t FmInterval;
+ __I uint32_t FmRemaining;
+ __I uint32_t FmNumber;
+ __IO uint32_t PeriodicStart;
+ __IO uint32_t LSTreshold;
+ __IO uint32_t RhDescriptorA;
+ __IO uint32_t RhDescriptorB;
+ __IO uint32_t RhStatus;
+ __IO uint32_t RhPortStatus1;
+ __IO uint32_t RhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t IntSt; /* USB On-The-Go Registers */
+ __IO uint32_t IntEn;
+ __O uint32_t IntSet;
+ __O uint32_t IntClr;
+ __IO uint32_t StCtrl;
+ __IO uint32_t Tmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t DevIntEn;
+ __O uint32_t DevIntClr;
+ __O uint32_t DevIntSet;
+
+ __O uint32_t CmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t CmdData;
+
+ __I uint32_t RxData; /* USB Device Transfer Registers */
+ __O uint32_t TxData;
+ __I uint32_t RxPLen;
+ __O uint32_t TxPLen;
+ __IO uint32_t Ctrl;
+ __O uint32_t DevIntPri;
+
+ __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t EpIntEn;
+ __O uint32_t EpIntClr;
+ __O uint32_t EpIntSet;
+ __O uint32_t EpIntPri;
+
+ __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t EpInd;
+ __IO uint32_t MaxPSize;
+
+ __I uint32_t DMARSt; /* USB Device DMA Registers */
+ __O uint32_t DMARClr;
+ __O uint32_t DMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t UDCAH;
+ __I uint32_t EpDMASt;
+ __O uint32_t EpDMAEn;
+ __O uint32_t EpDMADis;
+ __I uint32_t DMAIntSt;
+ __IO uint32_t DMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t EoTIntSt;
+ __O uint32_t EoTIntClr;
+ __O uint32_t EoTIntSet;
+ __I uint32_t NDDRIntSt;
+ __O uint32_t NDDRIntClr;
+ __O uint32_t NDDRIntSet;
+ __I uint32_t SysErrIntSt;
+ __O uint32_t SysErrIntClr;
+ __O uint32_t SysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __IO uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} IP_USB_001_T;
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_001_H_ */
+
--- /dev/null
+/*\r
+ * @brief High-Speed USB registers and control functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __USBHS_001_H_\r
+#define __USBHS_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_USBHS_001 IP: USBHS Device, Host, & OTG register block and driver\r
+ * @ingroup IP_Drivers\r
+ * USB High-Speed Device, Host, & OTG\r
+ * Note: On the LPC18xx and LPC43xx, only USB0 supports OTG\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief USB High-Speed register block structure\r
+ */\r
+typedef struct { /*!< USB Structure */\r
+ __I uint32_t RESERVED0[64];\r
+ __I uint32_t CAPLENGTH; /*!< Capability register length */\r
+ __I uint32_t HCSPARAMS; /*!< Host controller structural parameters */\r
+ __I uint32_t HCCPARAMS; /*!< Host controller capability parameters */\r
+ __I uint32_t RESERVED1[5];\r
+ __I uint32_t DCIVERSION; /*!< Device interface version number */\r
+ __I uint32_t RESERVED2[7];\r
+ union {\r
+ __IO uint32_t USBCMD_H; /*!< USB command (host mode) */\r
+ __IO uint32_t USBCMD_D; /*!< USB command (device mode) */\r
+ };\r
+\r
+ union {\r
+ __IO uint32_t USBSTS_H; /*!< USB status (host mode) */\r
+ __IO uint32_t USBSTS_D; /*!< USB status (device mode) */\r
+ };\r
+\r
+ union {\r
+ __IO uint32_t USBINTR_H; /*!< USB interrupt enable (host mode) */\r
+ __IO uint32_t USBINTR_D; /*!< USB interrupt enable (device mode) */\r
+ };\r
+\r
+ union {\r
+ __IO uint32_t FRINDEX_H; /*!< USB frame index (host mode) */\r
+ __I uint32_t FRINDEX_D; /*!< USB frame index (device mode) */\r
+ };\r
+\r
+ __I uint32_t RESERVED3;\r
+ union {\r
+ __IO uint32_t PERIODICLISTBASE; /*!< Frame list base address */\r
+ __IO uint32_t DEVICEADDR; /*!< USB device address */\r
+ };\r
+\r
+ union {\r
+ __IO uint32_t ASYNCLISTADDR; /*!< Address of endpoint list in memory (host mode) */\r
+ __IO uint32_t ENDPOINTLISTADDR; /*!< Address of endpoint list in memory (device mode) */\r
+ };\r
+\r
+ __IO uint32_t TTCTRL; /*!< Asynchronous buffer status for embedded TT (host mode) */\r
+ __IO uint32_t BURSTSIZE; /*!< Programmable burst size */\r
+ __IO uint32_t TXFILLTUNING; /*!< Host transmit pre-buffer packet tuning (host mode) */\r
+ __I uint32_t RESERVED4[2];\r
+ __IO uint32_t ULPIVIEWPORT; /*!< ULPI viewport */\r
+ __IO uint32_t BINTERVAL; /*!< Length of virtual frame */\r
+ __IO uint32_t ENDPTNAK; /*!< Endpoint NAK (device mode) */\r
+ __IO uint32_t ENDPTNAKEN; /*!< Endpoint NAK Enable (device mode) */\r
+ __I uint32_t RESERVED5;\r
+ union {\r
+ __IO uint32_t PORTSC1_H; /*!< Port 1 status/control (host mode) */\r
+ __IO uint32_t PORTSC1_D; /*!< Port 1 status/control (device mode) */\r
+ };\r
+\r
+ __I uint32_t RESERVED6[7];\r
+ __IO uint32_t OTGSC; /*!< OTG status and control */\r
+ union {\r
+ __IO uint32_t USBMODE_H; /*!< USB mode (host mode) */\r
+ __IO uint32_t USBMODE_D; /*!< USB mode (device mode) */\r
+ };\r
+\r
+ __IO uint32_t ENDPTSETUPSTAT; /*!< Endpoint setup status */\r
+ __IO uint32_t ENDPTPRIME; /*!< Endpoint initialization */\r
+ __IO uint32_t ENDPTFLUSH; /*!< Endpoint de-initialization */\r
+ __I uint32_t ENDPTSTAT; /*!< Endpoint status */\r
+ __IO uint32_t ENDPTCOMPLETE; /*!< Endpoint complete */\r
+ __IO uint32_t ENDPTCTRL[6]; /*!< Endpoint control 0 */\r
+} IP_USBHS_001_T;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __USBHS_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Self Wakeup Timer (WKT) registers and functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __WKT_001_H_\r
+#define __WKT_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_WKT_001 IP: Self Wakeup Timer (WKT) register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Self Wakeup Timer\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Self wake-up timer register block structure\r
+ */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 Alarm/Wakeup Timer Control register */\r
+ uint32_t Reserved[2];\r
+ __IO uint32_t COUNT; /*!< Offset: 0x000C Alarm/Wakeup Timer Counter register */\r
+} IP_WKT_001_T;\r
+\r
+/**\r
+ * WKT Control register bit fields & masks\r
+ */\r
+#define WKT_CTRL_CLKSEL ((uint32_t) (1 << 0)) /*!< Select the self wake-up timer clock source */\r
+#define WKT_CTRL_ALARMFLAG ((uint32_t) (1 << 1)) /*!< Wake-up or alarm timer flag */\r
+#define WKT_CTRL_CLEARCTR ((uint32_t) (1 << 2)) /*!< Clears the self wake-up timer */\r
+\r
+/**\r
+ * WKT Clock source values enum\r
+ */\r
+typedef enum IP_WKT_CLKSRC {\r
+ IP_WKT_CLKSRC_DIVIRC = 0, /*!< Divided IRC clock - runs at 750kHz */\r
+ IP_WKT_CLKSRC_10KHZ = 1 /*!< Low power clock - runs at 10kHz */\r
+} IP_WKT_CLKSRC_T;\r
+\r
+/**\r
+ * @brief Clear WKT interrupt status\r
+ * @param pWKT : Pointer to WKT register block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_WKT_ClearIntStatus(IP_WKT_001_T *pWKT)\r
+{\r
+ if ( pWKT->CTRL & WKT_CTRL_ALARMFLAG ) {\r
+ pWKT->CTRL |= WKT_CTRL_ALARMFLAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Clear and stop WKT counter\r
+ * @param pWKT : Pointer to WKT register block\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_WKT_Stop(IP_WKT_001_T *pWKT)\r
+{\r
+ pWKT->CTRL |= WKT_CTRL_CLEARCTR;\r
+}\r
+\r
+/**\r
+ * @brief Set the WKT clock source\r
+ * @param pWKT : Pointer to WKT register block\r
+ * @param clkSrc : WKT Clock source(WKT_CLKSRC_10KHZ or WKT_CLKSRC_DIVIRC)\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_WKT_SetClockSource(IP_WKT_001_T *pWKT, IP_WKT_CLKSRC_T clkSrc)\r
+{\r
+ if (clkSrc == IP_WKT_CLKSRC_10KHZ) {\r
+ pWKT->CTRL |= WKT_CTRL_CLKSEL; /* using Low Power clock 10kHz */\r
+ }\r
+ else {\r
+ pWKT->CTRL &= ~WKT_CTRL_CLKSEL; /* using Divided IRC clock 750kHz */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the WKT counter value & start the counter\r
+ * @param pWKT : Pointer to WKT register block\r
+ * @param cntVal : WKT Counter value\r
+ * @return Nothing\r
+ */\r
+STATIC INLINE void IP_WKT_Start(IP_WKT_001_T *pWKT, uint32_t cntVal)\r
+{\r
+ pWKT->COUNT = cntVal;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __WKT_001_H_ */\r
--- /dev/null
+/*\r
+ * @brief Windowed Watchdog Timer Registers and functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __WWDT_001_H_\r
+#define __WWDT_001_H_\r
+\r
+#include "sys_config.h"\r
+#include "cmsis.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/** @defgroup IP_WWDT_001 IP: WWDT register block and driver\r
+ * @ingroup IP_Drivers\r
+ * Windowed Watchdog\r
+ * @{\r
+ */\r
+#if !defined(CHIP_LPC175X_6X) && !defined(CHIP_LPC11CXX) && !defined(CHIP_LPC1343)\r
+#define WATCHDOG_WINDOW_SUPPORT\r
+#endif\r
+\r
+#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC175X_6X) \\r
+ || defined(CHIP_LPC1347)\r
+#define WATCHDOG_CLKSEL_SUPPORT\r
+#endif\r
+\r
+/**\r
+ * @brief Windowed Watchdog register block structure\r
+ */\r
+typedef struct { /*!< WWDT Structure */\r
+ __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */\r
+ __IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */\r
+ __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */\r
+ __I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */\r
+#ifdef WATCHDOG_CLKSEL_SUPPORT\r
+ __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */\r
+#else\r
+ __I uint32_t RESERVED0;\r
+#endif\r
+#ifdef WATCHDOG_WINDOW_SUPPORT\r
+ __IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */\r
+ __IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */\r
+#endif\r
+} IP_WWDT_001_T;\r
+\r
+/**\r
+ * @brief Watchdog Mode register definitions\r
+ */\r
+/** Watchdog Mode Bitmask */\r
+#define WWDT_WDMOD_BITMASK ((uint32_t) 0x1F)\r
+/** WWDT interrupt enable bit */\r
+#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0))\r
+/** WWDT interrupt enable bit */\r
+#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1))\r
+/** WWDT time out flag bit */\r
+#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2))\r
+/** WDT Time Out flag bit */\r
+#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3))\r
+#if !defined(CHIP_LPC175X_6X)\r
+/** WWDT Protect flag bit */\r
+#define WWDT_WDMOD_WDPROTECT ((uint32_t) (1 << 4))\r
+#endif\r
+#if defined(WATCHDOG_CLKSEL_SUPPORT)\r
+/**\r
+ * @brief Watchdog Timer Clock Source Selection register definitions\r
+ */\r
+/** Clock source select bitmask */\r
+#define WWDT_CLKSEL_BITMASK ((uint32_t) 0x10000003)\r
+/** Clock source select */\r
+#define WWDT_CLKSEL_SOURCE(n) ((uint32_t) (n & 0x03))\r
+/** Lock the clock source selection */\r
+#define WWDT_CLKSEL_LOCK ((uint32_t) (1 << 31))\r
+#endif /* defined(WATCHDOG_CLKSEL_SUPPORT) */\r
+\r
+/**\r
+ * @brief Initialize the Watchdog Timer\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @return None\r
+ */\r
+void IP_WWDT_Init(IP_WWDT_001_T *pWWDT);\r
+\r
+/**\r
+ * @brief De-initialize the Watchdog Timer\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_WWDT_DeInit(IP_WWDT_001_T *pWWDT)\r
+{}\r
+\r
+/**\r
+ * @brief Set WDT timeout constant value used for feed\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @param timeout : WDT timeout in ticks\r
+ * @return none\r
+ */\r
+STATIC INLINE void IP_WWDT_SetTimeOut(IP_WWDT_001_T *pWWDT, uint32_t timeout)\r
+{\r
+ pWWDT->TC = timeout;\r
+}\r
+\r
+#if defined(WATCHDOG_CLKSEL_SUPPORT)\r
+/**\r
+ * @brief Clock selection for Watchdog Timer\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @param src : Clock source selection (Or-ed value of WWDT_CLKSEL_*)\r
+ * @return none\r
+ */\r
+STATIC INLINE void IP_WWDT_SelClockSource(IP_WWDT_001_T *pWWDT, uint32_t src)\r
+{\r
+ pWWDT->CLKSEL = src & WWDT_CLKSEL_BITMASK;\r
+}\r
+\r
+#endif /*WATCHDOG_CLKSEL_SUPPORT*/\r
+\r
+/**\r
+ * @brief Feed watchdog timer\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @return None\r
+ * @note If this function isn't called, a watchdog timer warning will occur.\r
+ * After the warning, a timeout will occur if a feed has happened.\r
+ */\r
+STATIC INLINE void IP_WWDT_Feed(IP_WWDT_001_T *pWWDT)\r
+{\r
+ pWWDT->FEED = 0xAA;\r
+ pWWDT->FEED = 0x55;\r
+}\r
+\r
+#if defined(WATCHDOG_WINDOW_SUPPORT)\r
+/**\r
+ * @brief Set WWDT warning interrupt\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @param timeout : WDT warning in ticks, between 0 and 1023\r
+ * @return None\r
+ * @note This is the number of ticks after the watchdog interrupt that the\r
+ * warning interrupt will be generated.\r
+ */\r
+STATIC INLINE void IP_WWDT_SetWarning(IP_WWDT_001_T *pWWDT, uint32_t timeout)\r
+{\r
+ pWWDT->WARNINT = timeout;\r
+}\r
+\r
+/**\r
+ * @brief Set WWDT window time\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @param timeout : WDT timeout in ticks\r
+ * @return none\r
+ * @note The watchdog timer must be fed between the timeout from the IP_WWDT_SetTimeOut()\r
+ * function and this function, with this function defining the last tick before the\r
+ * watchdog window interrupt occurs.\r
+ */\r
+STATIC INLINE void IP_WWDT_SetWindow(IP_WWDT_001_T *pWWDT, uint32_t timeout)\r
+{\r
+ pWWDT->WINDOW = timeout;\r
+}\r
+\r
+#endif /* defined(WATCHDOG_WINDOW_SUPPORT) */\r
+\r
+/**\r
+ * @brief Enable watchdog timer options\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @param options : An or'ed set of options of values\r
+ * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT\r
+ * @return None\r
+ * @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |\r
+ * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options\r
+ * are set (or unset) with no other options.\r
+ */\r
+STATIC INLINE void IP_WWDT_SetOption(IP_WWDT_001_T *pWWDT, uint32_t options)\r
+{\r
+ pWWDT->MOD |= options;\r
+}\r
+\r
+/**\r
+ * @brief Disable/clear watchdog timer options\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @param options : An or'ed set of options of values\r
+ * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT\r
+ * @return None\r
+ * @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |\r
+ * WWDT_WDMOD_WDTOF).\r
+ */\r
+STATIC INLINE void IP_WWDT_UnsetOption(IP_WWDT_001_T *pWWDT, uint32_t options)\r
+{\r
+ pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK;\r
+}\r
+\r
+/**\r
+ * @brief Enable WWDT activity\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @return None\r
+ */\r
+STATIC INLINE void IP_WWDT_Start(IP_WWDT_001_T *pWWDT)\r
+{\r
+ IP_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN);\r
+ IP_WWDT_Feed(pWWDT);\r
+}\r
+\r
+/**\r
+ * @brief Read WWDT status flag\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @return Watchdog status, an Or'ed value of WWDT_WDMOD_*\r
+ */\r
+STATIC INLINE uint32_t IP_WWDT_GetStatus(IP_WWDT_001_T *pWWDT)\r
+{\r
+ return pWWDT->MOD;\r
+}\r
+\r
+/**\r
+ * @brief Clear WWDT interrupt status flags\r
+ * @param pWWDT : pointer to WWDT register block\r
+ * @param status : Or'ed value of status flag(s) that you want to clear, should be:\r
+ * - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag\r
+ * - WWDT_WDMOD_WDINT: Clear watchdog warning flag\r
+ * @return None\r
+ */\r
+void IP_WWDT_ClearStatusFlag(IP_WWDT_001_T *pWWDT, uint32_t status);\r
+\r
+/**\r
+ * @brief Get the current value of WDT\r
+ * @return current value of WDT\r
+ */\r
+STATIC INLINE uint32_t IP_WWDT_GetCurrentCount(IP_WWDT_001_T *pWWDT)\r
+{\r
+ return pWWDT->TV;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __WWDT_001_H_ */\r
+++ /dev/null
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: cdcuser.c\r
- * Purpose: USB Communication Device Class User module\r
- * Version: V1.10\r
- *----------------------------------------------------------------------------\r
-* This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else\r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#include "lpc_types.h"\r
-\r
-#include "usb.h"\r
-#include "usbhw.h"\r
-#include "usbcfg.h"\r
-#include "usbcore.h"\r
-#include "cdc.h"\r
-#include "cdcuser.h"\r
-\r
-#ifdef __ICCARM__\r
-#pragma data_alignment=4\r
-#define __align(x)\r
-#elif defined ( __GNUC__ )\r
-#define __align(x) __attribute__((aligned(x)))\r
-#endif\r
-\r
-unsigned char __align(4) BulkBufOut [USB_CDC_BUFSIZE]; // Buffer to store USB OUT packet\r
-\r
-#ifdef __ICCARM__\r
-#undef __align(x)\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
- We need a buffer for incomming data on USB port because USB receives\r
- much faster than UART transmits\r
- *---------------------------------------------------------------------------*/\r
-/* Buffer masks */\r
-#define CDC_BUF_SIZE (64) // Output buffer in bytes (power 2)\r
- // large enough for file transfer\r
-#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul)\r
-\r
-/* Buffer read / write macros */\r
-#define CDC_BUF_RESET(cdcBuf) (cdcBuf.rdIdx = cdcBuf.wrIdx = 0)\r
-#define CDC_BUF_WR(cdcBuf, dataIn) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.wrIdx++] = (dataIn))\r
-#define CDC_BUF_RD(cdcBuf) (cdcBuf.data[CDC_BUF_MASK & cdcBuf.rdIdx++])\r
-#define CDC_BUF_EMPTY(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx)\r
-#define CDC_BUF_FULL(cdcBuf) (cdcBuf.rdIdx == cdcBuf.wrIdx+1)\r
-#define CDC_BUF_COUNT(cdcBuf) (CDC_BUF_MASK & (cdcBuf.wrIdx - cdcBuf.rdIdx))\r
-\r
-\r
-// CDC output buffer\r
-typedef struct __CDC_BUF_T {\r
- unsigned char data[CDC_BUF_SIZE];\r
- unsigned int wrIdx;\r
- unsigned int rdIdx;\r
-} CDC_BUF_T;\r
-\r
-CDC_BUF_T CDC_OutBuf; // buffer for all CDC Out data\r
-\r
-/*----------------------------------------------------------------------------\r
- read data from CDC_OutBuf\r
- *---------------------------------------------------------------------------*/\r
-int CDC_RdOutBuf (char *buffer, const int *length) {\r
- int bytesToRead, bytesRead;\r
-\r
- /* Read *length bytes, block if *bytes are not avaialable */\r
- bytesToRead = *length;\r
- bytesToRead = (bytesToRead < (*length)) ? bytesToRead : (*length);\r
- bytesRead = bytesToRead;\r
-\r
- // ... add code to check for underrun\r
-\r
- while (bytesToRead--) {\r
- *buffer++ = CDC_BUF_RD(CDC_OutBuf);\r
- }\r
- return (bytesRead);\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- write data to CDC_OutBuf\r
- *---------------------------------------------------------------------------*/\r
-int CDC_WrOutBuf (const char *buffer, int length) {\r
- int bytesWritten;\r
-\r
- // ... add code to check for overwrite\r
-\r
- for( bytesWritten = 0; bytesWritten < length; bytesWritten++ ) {\r
- CDC_BUF_WR(CDC_OutBuf, *buffer++); // Copy Data to buffer\r
- }\r
-\r
- return (bytesWritten);\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
- check if character(s) are available at CDC_OutBuf\r
- *---------------------------------------------------------------------------*/\r
-int CDC_OutBufAvailChar (int *availChar) {\r
-\r
- *availChar = CDC_BUF_COUNT(CDC_OutBuf);\r
-\r
- return (0);\r
-}\r
-/* end Buffer handling */\r
-\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SendEncapsulatedCommand Request Callback\r
- Called automatically on CDC SEND_ENCAPSULATED_COMMAND Request\r
- Parameters: None (global SetupPacket and EP0Buf)\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SendEncapsulatedCommand (void) {\r
-\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC GetEncapsulatedResponse Request Callback\r
- Called automatically on CDC Get_ENCAPSULATED_RESPONSE Request\r
- Parameters: None (global SetupPacket and EP0Buf)\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_GetEncapsulatedResponse (void) {\r
-\r
- /* ... add code to handle request */\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SetCommFeature Request Callback\r
- Called automatically on CDC Set_COMM_FATURE Request\r
- Parameters: FeatureSelector\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector) {\r
-\r
- /* ... add code to handle request */\r
- ( void ) wFeatureSelector;\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC GetCommFeature Request Callback\r
- Called automatically on CDC Get_COMM_FATURE Request\r
- Parameters: FeatureSelector\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector) {\r
-\r
- /* ... add code to handle request */\r
- ( void ) wFeatureSelector;\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC ClearCommFeature Request Callback\r
- Called automatically on CDC CLEAR_COMM_FATURE Request\r
- Parameters: FeatureSelector\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector) {\r
-\r
- /* ... add code to handle request */\r
- ( void ) wFeatureSelector;\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SetLineCoding Request Callback\r
- Called automatically on CDC SET_LINE_CODING Request\r
- Parameters: none (global SetupPacket and EP0Buf)\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SetLineCoding (void) {\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC GetLineCoding Request Callback\r
- Called automatically on CDC GET_LINE_CODING Request\r
- Parameters: None (global SetupPacket and EP0Buf)\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_GetLineCoding (void) {\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SetControlLineState Request Callback\r
- Called automatically on CDC SET_CONTROL_LINE_STATE Request\r
- Parameters: ControlSignalBitmap\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap) {\r
-\r
- /* ... add code to handle request */\r
- ( void ) wControlSignalBitmap;\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC SendBreak Request Callback\r
- Called automatically on CDC Set_COMM_FATURE Request\r
- Parameters: 0xFFFF start of Break\r
- 0x0000 stop of Break\r
- 0x#### Duration of Break\r
- Return Value: TRUE - Success, FALSE - Error\r
- *---------------------------------------------------------------------------*/\r
-uint32_t CDC_SendBreak (unsigned short wDurationOfBreak) {\r
-\r
- /* ... add code to handle request */\r
- ( void ) wDurationOfBreak;\r
- return (TRUE);\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC_BulkIn call on DataIn Request\r
- Parameters: none\r
- Return Value: none\r
- *---------------------------------------------------------------------------*/\r
-void CDC_BulkIn(void) {\r
-}\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- CDC_BulkOut call on DataOut Request\r
- Parameters: none\r
- Return Value: none\r
- *---------------------------------------------------------------------------*/\r
-void CDC_BulkOut(void) {\r
- int numBytesRead;\r
-\r
- // get data from USB into intermediate buffer\r
- numBytesRead = USB_ReadEP(CDC_DEP_OUT, &BulkBufOut[0]);\r
-\r
- // ... add code to check for overwrite\r
-\r
- // store data in a buffer to transmit it over serial interface\r
- CDC_WrOutBuf ((char *)&BulkBufOut[0], numBytesRead);\r
- vCDCNewDataNotify();\r
-}\r
-\r
-void CDC_BulkOutNak(void){\r
-\r
- USB_ReadReqEP(CDC_DEP_OUT, &BulkBufOut[0], 64);\r
-}\r
+++ /dev/null
-/*----------------------------------------------------------------------------
- * U S B - K e r n e l
- *----------------------------------------------------------------------------
- * Name: CDC.h
- * Purpose: USB Communication Device Class Definitions
- * Version: V1.20
- *----------------------------------------------------------------------------
- * This software is supplied "AS IS" without any warranties, express,
- * implied or statutory, including but not limited to the implied
- * warranties of fitness for purpose, satisfactory quality and
- * noninfringement. Keil extends you a royalty-free right to reproduce
- * and distribute executable files created using this software for use
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing
- * else gives you the right to use this software.
- *
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
- *---------------------------------------------------------------------------*/
-
-#ifndef __CDC_H
-#define __CDC_H
-#include "lpc_types.h"
-
-#if defined ( __GNUC__ )
-#define __packed __attribute__((__packed__))
-#endif
-/*----------------------------------------------------------------------------
- * Definitions based on usbcdc11.pdf (www.usb.org)
- *---------------------------------------------------------------------------*/
-// Communication device class specification version 1.10
-#define CDC_V1_10 0x0110
-
-// Communication interface class code
-// (usbcdc11.pdf, 4.2, Table 15)
-#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02
-
-// Communication interface class subclass codes
-// (usbcdc11.pdf, 4.3, Table 16)
-#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01
-#define CDC_ABSTRACT_CONTROL_MODEL 0x02
-#define CDC_TELEPHONE_CONTROL_MODEL 0x03
-#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04
-#define CDC_CAPI_CONTROL_MODEL 0x05
-#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06
-#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07
-
-// Communication interface class control protocol codes
-// (usbcdc11.pdf, 4.4, Table 17)
-#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01
-
-// Data interface class code
-// (usbcdc11.pdf, 4.5, Table 18)
-#define CDC_DATA_INTERFACE_CLASS 0x0A
-
-// Data interface class protocol codes
-// (usbcdc11.pdf, 4.7, Table 19)
-#define CDC_PROTOCOL_ISDN_BRI 0x30
-#define CDC_PROTOCOL_HDLC 0x31
-#define CDC_PROTOCOL_TRANSPARENT 0x32
-#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50
-#define CDC_PROTOCOL_Q921_DATA_LINK 0x51
-#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52
-#define CDC_PROTOCOL_V42 0x90
-#define CDC_PROTOCOL_EURO_ISDN 0x91
-#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92
-#define CDC_PROTOCOL_CAPI 0x93
-#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD
-#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE
-
-// Type values for bDescriptorType field of functional descriptors
-// (usbcdc11.pdf, 5.2.3, Table 24)
-#define CDC_CS_INTERFACE 0x24
-#define CDC_CS_ENDPOINT 0x25
-
-// Type values for bDescriptorSubtype field of functional descriptors
-// (usbcdc11.pdf, 5.2.3, Table 25)
-#define CDC_HEADER 0x00
-#define CDC_CALL_MANAGEMENT 0x01
-#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02
-#define CDC_DIRECT_LINE_MANAGEMENT 0x03
-#define CDC_TELEPHONE_RINGER 0x04
-#define CDC_REPORTING_CAPABILITIES 0x05
-#define CDC_UNION 0x06
-#define CDC_COUNTRY_SELECTION 0x07
-#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08
-#define CDC_USB_TERMINAL 0x09
-#define CDC_NETWORK_CHANNEL 0x0A
-#define CDC_PROTOCOL_UNIT 0x0B
-#define CDC_EXTENSION_UNIT 0x0C
-#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D
-#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E
-#define CDC_ETHERNET_NETWORKING 0x0F
-#define CDC_ATM_NETWORKING 0x10
-
-// CDC class-specific request codes
-// (usbcdc11.pdf, 6.2, Table 46)
-// see Table 45 for info about the specific requests.
-#define CDC_SEND_ENCAPSULATED_COMMAND 0x00
-#define CDC_GET_ENCAPSULATED_RESPONSE 0x01
-#define CDC_SET_COMM_FEATURE 0x02
-#define CDC_GET_COMM_FEATURE 0x03
-#define CDC_CLEAR_COMM_FEATURE 0x04
-#define CDC_SET_AUX_LINE_STATE 0x10
-#define CDC_SET_HOOK_STATE 0x11
-#define CDC_PULSE_SETUP 0x12
-#define CDC_SEND_PULSE 0x13
-#define CDC_SET_PULSE_TIME 0x14
-#define CDC_RING_AUX_JACK 0x15
-#define CDC_SET_LINE_CODING 0x20
-#define CDC_GET_LINE_CODING 0x21
-#define CDC_SET_CONTROL_LINE_STATE 0x22
-#define CDC_SEND_BREAK 0x23
-#define CDC_SET_RINGER_PARMS 0x30
-#define CDC_GET_RINGER_PARMS 0x31
-#define CDC_SET_OPERATION_PARMS 0x32
-#define CDC_GET_OPERATION_PARMS 0x33
-#define CDC_SET_LINE_PARMS 0x34
-#define CDC_GET_LINE_PARMS 0x35
-#define CDC_DIAL_DIGITS 0x36
-#define CDC_SET_UNIT_PARAMETER 0x37
-#define CDC_GET_UNIT_PARAMETER 0x38
-#define CDC_CLEAR_UNIT_PARAMETER 0x39
-#define CDC_GET_PROFILE 0x3A
-#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
-#define CDC_SET_ETHERNET_PMP_FILTER 0x41
-#define CDC_GET_ETHERNET_PMP_FILTER 0x42
-#define CDC_SET_ETHERNET_PACKET_FILTER 0x43
-#define CDC_GET_ETHERNET_STATISTIC 0x44
-#define CDC_SET_ATM_DATA_FORMAT 0x50
-#define CDC_GET_ATM_DEVICE_STATISTICS 0x51
-#define CDC_SET_ATM_DEFAULT_VC 0x52
-#define CDC_GET_ATM_VC_STATISTICS 0x53
-
-// Communication feature selector codes
-// (usbcdc11.pdf, 6.2.2..6.2.4, Table 47)
-#define CDC_ABSTRACT_STATE 0x01
-#define CDC_COUNTRY_SETTING 0x02
-
-// Feature Status returned for ABSTRACT_STATE Selector
-// (usbcdc11.pdf, 6.2.3, Table 48)
-#define CDC_IDLE_SETTING (1 << 0)
-#define CDC_DATA_MULTPLEXED_STATE (1 << 1)
-
-
-// Control signal bitmap values for the SetControlLineState request
-// (usbcdc11.pdf, 6.2.14, Table 51)
-#define CDC_DTE_PRESENT (1 << 0)
-#define CDC_ACTIVATE_CARRIER (1 << 1)
-
-// CDC class-specific notification codes
-// (usbcdc11.pdf, 6.3, Table 68)
-// see Table 67 for Info about class-specific notifications
-#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00
-#define CDC_RESPONSE_AVAILABLE 0x01
-#define CDC_AUX_JACK_HOOK_STATE 0x08
-#define CDC_RING_DETECT 0x09
-#define CDC_NOTIFICATION_SERIAL_STATE 0x20
-#define CDC_CALL_STATE_CHANGE 0x28
-#define CDC_LINE_STATE_CHANGE 0x29
-#define CDC_CONNECTION_SPEED_CHANGE 0x2A
-
-// UART state bitmap values (Serial state notification).
-// (usbcdc11.pdf, 6.3.5, Table 69)
-#define CDC_SERIAL_STATE_OVERRUN (1 << 6) // receive data overrun error has occurred
-#define CDC_SERIAL_STATE_PARITY (1 << 5) // parity error has occurred
-#define CDC_SERIAL_STATE_FRAMING (1 << 4) // framing error has occurred
-#define CDC_SERIAL_STATE_RING (1 << 3) // state of ring signal detection
-#define CDC_SERIAL_STATE_BREAK (1 << 2) // state of break detection
-#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) // state of transmission carrier
-#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) // state of receiver carrier
-
-
-/*----------------------------------------------------------------------------
- * Structures based on usbcdc11.pdf (www.usb.org)
- *---------------------------------------------------------------------------*/
-
-// Header functional descriptor
-// (usbcdc11.pdf, 5.2.3.1)
-// This header must precede any list of class-specific descriptors.
-
-#if defined ( __CC_ARM )
-typedef __packed struct _CDC_HEADER_DESCRIPTOR{
-#elif defined ( __GNUC__ )
-typedef struct __packed _CDC_HEADER_DESCRIPTOR{
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _CDC_HEADER_DESCRIPTOR {
-#endif
- uint8_t bFunctionLength; // size of this descriptor in bytes
- uint8_t bDescriptorType; // CS_INTERFACE descriptor type
- uint8_t bDescriptorSubtype; // Header functional descriptor subtype
- uint16_t bcdCDC; // USB CDC specification release version
-} CDC_HEADER_DESCRIPTOR;
-
-//Call management functional descriptor
-// (usbcdc11.pdf, 5.2.3.2)
-// Describes the processing of calls for the communication class interface.
-#if defined ( __CC_ARM )
-typedef __packed struct _CDC_CALL_MANAGEMENT_DESCRIPTOR{
-#elif defined ( __GNUC__ )
-typedef struct __packed _CDC_CALL_MANAGEMENT_DESCRIPTOR{
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR {
-#endif
- uint8_t bFunctionLength; // size of this descriptor in bytes
- uint8_t bDescriptorType; // CS_INTERFACE descriptor type
- uint8_t bDescriptorSubtype; // call management functional descriptor subtype
- uint8_t bmCapabilities; // capabilities that this configuration supports
- uint8_t bDataInterface; // interface number of the data class interface used for call management (optional)
-} CDC_CALL_MANAGEMENT_DESCRIPTOR;
-
-// Abstract control management functional descriptor
-// (usbcdc11.pdf, 5.2.3.3)
-// Describes the command supported by the communication interface class with the Abstract Control Model subclass code.
-#if defined ( __CC_ARM )
-typedef __packed struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{
-#elif defined ( __GNUC__ )
-typedef struct __packed _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR{
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR {
-#endif
- uint8_t bFunctionLength; // size of this descriptor in bytes
- uint8_t bDescriptorType; // CS_INTERFACE descriptor type
- uint8_t bDescriptorSubtype; // abstract control management functional descriptor subtype
- uint8_t bmCapabilities; // capabilities supported by this configuration
-} CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR;
-
-// Union functional descriptors
-// (usbcdc11.pdf, 5.2.3.8)
-// Describes the relationship between a group of interfaces that can be considered to form a functional unit.
-#if defined ( __CC_ARM )
-typedef __packed struct _CDC_UNION_DESCRIPTOR{
-#elif defined ( __GNUC__ )
-typedef struct __packed _CDC_UNION_DESCRIPTOR{
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _CDC_UNION_DESCRIPTOR {
-#endif
- uint8_t bFunctionLength; // size of this descriptor in bytes
- uint8_t bDescriptorType; // CS_INTERFACE descriptor type
- uint8_t bDescriptorSubtype; // union functional descriptor subtype
- uint8_t bMasterInterface; // interface number designated as master
-} CDC_UNION_DESCRIPTOR;
-
-// Union functional descriptors with one slave interface
-// (usbcdc11.pdf, 5.2.3.8)
-#if defined ( __CC_ARM )
-typedef __packed struct _CDC_UNION_1SLAVE_DESCRIPTOR{
-#elif defined ( __GNUC__ )
-typedef struct __packed _CDC_UNION_1SLAVE_DESCRIPTOR{
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR {
-#endif
- CDC_UNION_DESCRIPTOR sUnion; // Union functional descriptor
- uint8_t bSlaveInterfaces[1]; // Slave interface 0
-} CDC_UNION_1SLAVE_DESCRIPTOR;
-
-// Line coding structure
-// Format of the data returned when a GetLineCoding request is received
-// (usbcdc11.pdf, 6.2.13)
-#if defined ( __CC_ARM )
-typedef __packed struct _CDC_LINE_CODING{
-#elif defined ( __GNUC__ )
-typedef struct __packed _CDC_LINE_CODING{
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _CDC_LINE_CODING {
-#endif
- uint32_t dwDTERate; // Data terminal rate in bits per second
- uint8_t bCharFormat; // Number of stop bits
- uint8_t bParityType; // Parity bit type
- uint8_t bDataBits; // Number of data bits
-} CDC_LINE_CODING;
-
-// Notification header
-// Data sent on the notification endpoint must follow this header.
-// see USB_SETUP_PACKET in file usb.h
-typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER;
-
-#endif /* __CDC_H */
-
+++ /dev/null
-/*----------------------------------------------------------------------------\r
- * U S B - K e r n e l\r
- *----------------------------------------------------------------------------\r
- * Name: cdcuser.h\r
- * Purpose: USB Communication Device Class User module Definitions\r
- * Version: V1.10\r
- *----------------------------------------------------------------------------\r
- * This software is supplied "AS IS" without any warranties, express,\r
- * implied or statutory, including but not limited to the implied\r
- * warranties of fitness for purpose, satisfactory quality and\r
- * noninfringement. Keil extends you a royalty-free right to reproduce\r
- * and distribute executable files created using this software for use\r
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else\r
- * gives you the right to use this software.\r
- *\r
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-\r
-#ifndef __CDCUSER_H__\r
-#define __CDCUSER_H__\r
-\r
-/* CDC buffer handling */\r
-extern int CDC_RdOutBuf (char *buffer, const int *length);\r
-extern int CDC_WrOutBuf (const char *buffer, int length);\r
-extern int CDC_OutBufAvailChar (int *availChar);\r
-extern void CDC_WaitNewData ( void );\r
-\r
-\r
-/* CDC Data In/Out Endpoint Address */\r
-#define CDC_DEP_IN 0x82\r
-#define CDC_DEP_OUT 0x02\r
-\r
-/* CDC Communication In Endpoint Address */\r
-#define CDC_CEP_IN 0x81\r
-\r
-/* CDC Requests Callback Functions */\r
-extern uint32_t CDC_SendEncapsulatedCommand (void);\r
-extern uint32_t CDC_GetEncapsulatedResponse (void);\r
-extern uint32_t CDC_SetCommFeature (unsigned short wFeatureSelector);\r
-extern uint32_t CDC_GetCommFeature (unsigned short wFeatureSelector);\r
-extern uint32_t CDC_ClearCommFeature (unsigned short wFeatureSelector);\r
-extern uint32_t CDC_GetLineCoding (void);\r
-extern uint32_t CDC_SetLineCoding (void);\r
-extern uint32_t CDC_SetControlLineState (unsigned short wControlSignalBitmap);\r
-extern uint32_t CDC_SendBreak (unsigned short wDurationOfBreak);\r
-\r
-/* CDC Bulk Callback Functions */\r
-extern void CDC_BulkIn (void);\r
-extern void CDC_BulkOut (void);\r
-extern void CDC_BulkOutNak (void);\r
-\r
-/* CDC Notification Callback Function */\r
-extern void CDC_NotificationIn (void);\r
-\r
-/* CDC Initializtion Function */\r
-extern void CDC_Init (char portNum);\r
-\r
-/* CDC prepare the SERAIAL_STATE */\r
-extern unsigned short CDC_GetSerialState (void);\r
-\r
-/* CDC New data Notification Function */\r
-extern void vCDCNewDataNotify();\r
-\r
-/* flow control */\r
-extern unsigned short CDC_DepInEmpty; // DataEndPoint IN empty\r
-\r
-#endif /* __CDCUSER_H__ */\r
-\r
+++ /dev/null
-/**********************************************************************
-* $Id$ lpc43xx_libcfg.h 2011-06-02
-*//**
-* @file lpc43xx_libcfg.h
-* @brief Library configuration file
-* @version 1.0
-* @date 02. June. 2011
-* @author NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#ifndef lpc43xx_LIBCFG_H_
-#define lpc43xx_LIBCFG_H_
-
-#include "lpc_types.h"
-
-
-/************************** DEBUG MODE DEFINITIONS *********************************/
-/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
- the "CHECK_PARAM" macro in the FW library code */
-
-#define DEBUG
-
-
-/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
-
-/* Comment the line below to disable the specific peripheral inclusion */
-
-/* GPIO ------------------------------- */
-#define _GPIO
-
-/* EXTI ------------------------------- */
-//#define _EXTI
-
-/* UART ------------------------------- */
-#define _UART
-#define _UART0
-#define _UART1
-#define _UART2
-#define _UART3
-
-/* SPI ------------------------------- */
-//#define _SPI
-
-/* SSP ------------------------------- */
-//#define _SSP
-//#define _SSP0
-//#define _SSP1
-
-/* SYSTICK --------------------------- */
-//#define _SYSTICK
-
-/* I2C ------------------------------- */
-//#define _I2C
-//#define _I2C0
-//#define _I2C1
-//#define _I2C2
-
-/* TIMER ------------------------------- */
-//#define _TIM
-
-/* WDT ------------------------------- */
-//#define _WDT
-
-
-/* GPDMA ------------------------------- */
-//#define _GPDMA
-
-
-/* DAC ------------------------------- */
-//#define _DAC
-
-/* DAC ------------------------------- */
-//#define _ADC
-
-
-/* PWM ------------------------------- */
-//#define _PWM
-//#define _PWM1
-
-/* RTC ------------------------------- */
-//#define _RTC
-
-/* I2S ------------------------------- */
-//#define _I2S
-
-/* USB device ------------------------------- */
-#define _USBDEV
-//#define _USB_DMA
-
-/* QEI ------------------------------- */
-//#define _QEI
-
-/* MCPWM ------------------------------- */
-//#define _MCPWM
-
-/* CAN--------------------------------*/
-//#define _CAN
-
-/* RIT ------------------------------- */
-//#define _RIT
-
-/* EMAC ------------------------------ */
-//#define _EMAC
-
-/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
-
-#ifdef DEBUG
-/*******************************************************************************
-* @brief The CHECK_PARAM macro is used for function's parameters check.
-* It is used only if the library is compiled in DEBUG mode.
-* @param[in] expr - If expr is false, it calls check_failed() function
-* which reports the name of the source file and the source
-* line number of the call that failed.
-* - If expr is true, it returns no value.
-* @return None
-*******************************************************************************/
-#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
-#else
-#define CHECK_PARAM(expr)
-#endif /* DEBUG */
-
-
-
-/************************** GLOBAL/PUBLIC FUNCTION DECLARATION *********************************/
-
-#ifdef DEBUG
-void check_failed(uint8_t *file, uint32_t line);
-#endif
-
-
-#endif /* lpc43xx_LIBCFG_H_ */
+++ /dev/null
-/**********************************************************************
-* $Id$ usb.h 2011-06-02
-*//**
-* @file usb.h
-* @brief USB Definitions
-* @version 1.0
-* @date 02. June. 2011
-* @author NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#ifndef __USB_H__
-#define __USB_H__
-
-#include "usbcfg.h"
-
-#ifdef USE_USB0
-#define LPC_USB LPC_USB0 // Use USB0
-#else
-#define LPC_USB LPC_USB1 // Use USB1
-#endif
-#if defined ( __GNUC__ )
-#define __packed __attribute__((__packed__))
-#endif
-
-#if defined ( __CC_ARM )
-typedef __packed union {
-#elif defined ( __GNUC__ )
-typedef union __packed {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef union {
-#endif
- uint16_t W;
-#if defined ( __CC_ARM )
- __packed struct {
-#elif defined ( __GNUC__ )
- struct __packed {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
- struct {
-#endif
- uint8_t L;
- uint8_t H;
- } WB;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-} WORD_BYTE;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-
-/* bmRequestType.Dir */
-#define REQUEST_HOST_TO_DEVICE 0
-#define REQUEST_DEVICE_TO_HOST 1
-
-/* bmRequestType.Type */
-#define REQUEST_STANDARD 0
-#define REQUEST_CLASS 1
-#define REQUEST_VENDOR 2
-#define REQUEST_RESERVED 3
-
-/* bmRequestType.Recipient */
-#define REQUEST_TO_DEVICE 0
-#define REQUEST_TO_INTERFACE 1
-#define REQUEST_TO_ENDPOINT 2
-#define REQUEST_TO_OTHER 3
-
-/* bmRequestType Definition */
-#if defined ( __CC_ARM )
-typedef __packed union _REQUEST_TYPE {
-#elif defined ( __GNUC__ )
-typedef union __packed _REQUEST_TYPE {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef union _REQUEST_TYPE {
-#endif
-#if defined ( __CC_ARM )
- __packed struct _BM {
-#elif defined ( __GNUC__ )
- struct __packed _BM {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
- struct _BM {
-#endif
- uint8_t Recipient : 5;
- uint8_t Type : 2;
- uint8_t Dir : 1;
- } BM;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
- uint8_t B;
-} REQUEST_TYPE;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-/* USB Standard Request Codes */
-#define USB_REQUEST_GET_STATUS 0
-#define USB_REQUEST_CLEAR_FEATURE 1
-#define USB_REQUEST_SET_FEATURE 3
-#define USB_REQUEST_SET_ADDRESS 5
-#define USB_REQUEST_GET_DESCRIPTOR 6
-#define USB_REQUEST_SET_DESCRIPTOR 7
-#define USB_REQUEST_GET_CONFIGURATION 8
-#define USB_REQUEST_SET_CONFIGURATION 9
-#define USB_REQUEST_GET_INTERFACE 10
-#define USB_REQUEST_SET_INTERFACE 11
-#define USB_REQUEST_SYNC_FRAME 12
-
-/* USB GET_STATUS Bit Values */
-#define USB_GETSTATUS_SELF_POWERED 0x01
-#define USB_GETSTATUS_REMOTE_WAKEUP 0x02
-#define USB_GETSTATUS_ENDPOINT_STALL 0x01
-
-/* USB Standard Feature selectors */
-#define USB_FEATURE_ENDPOINT_STALL 0
-#define USB_FEATURE_REMOTE_WAKEUP 1
-#define USB_FEATURE_TEST_MODE 2
-
-/* USB Default Control Pipe Setup Packet */
-#if defined ( __CC_ARM )
-typedef __packed struct _USB_SETUP_PACKET {
-#elif defined ( __GNUC__ )
-typedef struct __packed _USB_SETUP_PACKET {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _USB_SETUP_PACKET {
-#endif
- REQUEST_TYPE bmRequestType;
- uint8_t bRequest;
- WORD_BYTE wValue;
- WORD_BYTE wIndex;
- uint16_t wLength;
-} USB_SETUP_PACKET;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-
-/* USB Descriptor Types */
-#define USB_DEVICE_DESCRIPTOR_TYPE 1
-#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2
-#define USB_STRING_DESCRIPTOR_TYPE 3
-#define USB_INTERFACE_DESCRIPTOR_TYPE 4
-#define USB_ENDPOINT_DESCRIPTOR_TYPE 5
-#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6
-#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7
-#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8
-#define USB_OTG_DESCRIPTOR_TYPE 9
-#define USB_DEBUG_DESCRIPTOR_TYPE 10
-#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11
-
-/* USB Device Classes */
-#define USB_DEVICE_CLASS_RESERVED 0x00
-#define USB_DEVICE_CLASS_AUDIO 0x01
-#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02
-#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03
-#define USB_DEVICE_CLASS_MONITOR 0x04
-#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05
-#define USB_DEVICE_CLASS_POWER 0x06
-#define USB_DEVICE_CLASS_PRINTER 0x07
-#define USB_DEVICE_CLASS_STORAGE 0x08
-#define USB_DEVICE_CLASS_HUB 0x09
-#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF
-#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF
-
-/* bmAttributes in Configuration Descriptor */
-#define USB_CONFIG_POWERED_MASK 0x40
-#define USB_CONFIG_BUS_POWERED 0x80
-#define USB_CONFIG_SELF_POWERED 0xC0
-#define USB_CONFIG_REMOTE_WAKEUP 0x20
-
-/* bMaxPower in Configuration Descriptor */
-#define USB_CONFIG_POWER_MA(mA) ((mA)/2)
-
-/* bEndpointAddress in Endpoint Descriptor */
-#define USB_ENDPOINT_DIRECTION_MASK 0x80
-#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00)
-#define USB_ENDPOINT_IN(addr) ((addr) | 0x80)
-
-/* bmAttributes in Endpoint Descriptor */
-#define USB_ENDPOINT_TYPE_MASK 0x03
-#define USB_ENDPOINT_TYPE_CONTROL 0x00
-#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01
-#define USB_ENDPOINT_TYPE_BULK 0x02
-#define USB_ENDPOINT_TYPE_INTERRUPT 0x03
-#define USB_ENDPOINT_SYNC_MASK 0x0C
-#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00
-#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04
-#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08
-#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C
-#define USB_ENDPOINT_USAGE_MASK 0x30
-#define USB_ENDPOINT_USAGE_DATA 0x00
-#define USB_ENDPOINT_USAGE_FEEDBACK 0x10
-#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20
-#define USB_ENDPOINT_USAGE_RESERVED 0x30
-
-/* USB Standard Device Descriptor */
-#if defined ( __CC_ARM )
-typedef __packed struct _USB_DEVICE_DESCRIPTOR {
-#elif defined ( __GNUC__ )
-typedef struct __packed _USB_DEVICE_DESCRIPTOR {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _USB_DEVICE_DESCRIPTOR {
-#endif
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t bcdUSB;
- uint8_t bDeviceClass;
- uint8_t bDeviceSubClass;
- uint8_t bDeviceProtocol;
- uint8_t bMaxPacketSize0;
- uint16_t idVendor;
- uint16_t idProduct;
- uint16_t bcdDevice;
- uint8_t iManufacturer;
- uint8_t iProduct;
- uint8_t iSerialNumber;
- uint8_t bNumConfigurations;
-} USB_DEVICE_DESCRIPTOR;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-/* USB 2.0 Device Qualifier Descriptor */
-#if defined ( __CC_ARM )
-typedef __packed struct _USB_DEVICE_QUALIFIER_DESCRIPTOR {
-#elif defined ( __GNUC__ )
-typedef struct __packed _USB_DEVICE_QUALIFIER_DESCRIPTOR {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR {
-#endif
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t bcdUSB;
- uint8_t bDeviceClass;
- uint8_t bDeviceSubClass;
- uint8_t bDeviceProtocol;
- uint8_t bMaxPacketSize0;
- uint8_t bNumConfigurations;
- uint8_t bReserved;
-} USB_DEVICE_QUALIFIER_DESCRIPTOR;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-/* USB Standard Configuration Descriptor */
-#if defined ( __CC_ARM )
-typedef __packed struct _USB_CONFIGURATION_DESCRIPTOR {
-#elif defined ( __GNUC__ )
-typedef struct __packed _USB_CONFIGURATION_DESCRIPTOR {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _USB_CONFIGURATION_DESCRIPTOR {
-#endif
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t wTotalLength;
- uint8_t bNumInterfaces;
- uint8_t bConfigurationValue;
- uint8_t iConfiguration;
- uint8_t bmAttributes;
- uint8_t bMaxPower;
-} USB_CONFIGURATION_DESCRIPTOR;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-/* USB Standard Interface Descriptor */
-#if defined ( __CC_ARM )
-typedef __packed struct _USB_INTERFACE_DESCRIPTOR {
-#elif defined ( __GNUC__ )
-typedef struct __packed _USB_INTERFACE_DESCRIPTOR {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _USB_INTERFACE_DESCRIPTOR {
-#endif
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bInterfaceNumber;
- uint8_t bAlternateSetting;
- uint8_t bNumEndpoints;
- uint8_t bInterfaceClass;
- uint8_t bInterfaceSubClass;
- uint8_t bInterfaceProtocol;
- uint8_t iInterface;
-} USB_INTERFACE_DESCRIPTOR;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-/* USB Standard Endpoint Descriptor */
-#if defined ( __CC_ARM )
-typedef __packed struct _USB_ENDPOINT_DESCRIPTOR {
-#elif defined ( __GNUC__ )
-typedef struct __packed _USB_ENDPOINT_DESCRIPTOR {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _USB_ENDPOINT_DESCRIPTOR {
-#endif
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bEndpointAddress;
- uint8_t bmAttributes;
- uint16_t wMaxPacketSize;
- uint8_t bInterval;
-} USB_ENDPOINT_DESCRIPTOR;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-/* USB String Descriptor */
-#if defined ( __CC_ARM )
-typedef __packed struct _USB_STRING_DESCRIPTOR {
-#elif defined ( __GNUC__ )
-typedef struct __packed _USB_STRING_DESCRIPTOR {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _USB_STRING_DESCRIPTOR {
-#endif
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t bString/*[]*/;
-} USB_STRING_DESCRIPTOR;
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-/* USB Common Descriptor */
-#if defined ( __CC_ARM )
-typedef __packed struct _USB_COMMON_DESCRIPTOR {
-#elif defined ( __GNUC__ )
-typedef struct __packed _USB_COMMON_DESCRIPTOR {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _USB_COMMON_DESCRIPTOR {
-#endif
- uint8_t bLength;
- uint8_t bDescriptorType;
-} USB_COMMON_DESCRIPTOR;
-
-/* USB Other Speed Configuration */
-#if defined ( __CC_ARM )
-typedef __packed struct _USB_OTHER_SPEED_CONFIGURATION {
-#elif defined ( __GNUC__ )
-typedef struct __packed _USB_OTHER_SPEED_CONFIGURATION {
-#elif defined ( __IAR_SYSTEMS_ICC__ )
-#pragma pack(1)
-typedef struct _USB_OTHER_SPEED_CONFIGURATION {
-#endif
-
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t wTotalLength;
- uint8_t bNumInterfaces;
- uint8_t bConfigurationValue;
- uint8_t IConfiguration;
- uint8_t bmAttributes;
- uint8_t bMaxPower;
-} USB_OTHER_SPEED_CONFIGURATION;
-
-
-/* USB Endpoint Callback Events */
-#define USB_EVT_SETUP 1 /* Setup Packet */
-#define USB_EVT_OUT 2 /* OUT Packet */
-#define USB_EVT_IN 3 /* IN Packet */
-#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */
-#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */
-#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */
-#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */
-#define USB_EVT_OUT_DMA_EOT 8 /* DMA OUT EP - End of Transfer */
-#define USB_EVT_IN_DMA_EOT 9 /* DMA IN EP - End of Transfer */
-#define USB_EVT_OUT_DMA_NDR 10 /* DMA OUT EP - New Descriptor Request */
-#define USB_EVT_IN_DMA_NDR 11 /* DMA IN EP - New Descriptor Request */
-#define USB_EVT_OUT_DMA_ERR 12 /* DMA OUT EP - Error */
-#define USB_EVT_IN_DMA_ERR 13 /* DMA IN EP - Error */
-
-/* call back structure */
-typedef struct _USB_INIT_
-{
- uint32_t ep0_maxp;
- /* USB Device Events Callback Functions */
- void (* USB_Power_Event)(uint32_t power);
- void (* USB_Reset_Event)(void);
- void (* USB_Suspend_Event)(void);
- void (* USB_Resume_Event)(void);
- void (* USB_WakeUp_Event)(void);
- void (* USB_SOF_Event)(void);
- void (* USB_Error_Event)(uint32_t error);
- /* USB Core Events Callback Functions */
- void (* USB_Configure_Event)(void);
- void (* USB_Interface_Event)(void);
- void (* USB_Feature_Event)(void);
- /* USB Endpoint Events Callback Pointers */
- void (* USB_P_EP[4])(uint32_t event);
-} LPC_USBDRV_INIT_T;
-
-#ifdef __IAR_SYSTEMS_ICC__
-#pragma pack()
-#endif
-
-#endif /* __USB_H__ */
+++ /dev/null
-/*----------------------------------------------------------------------------
- * U S B - K e r n e l
- *----------------------------------------------------------------------------
- * Name: usbcfg.h
- * Purpose: USB Custom Configuration
- * Version: V1.20
- *----------------------------------------------------------------------------
- * This software is supplied "AS IS" without any warranties, express,
- * implied or statutory, including but not limited to the implied
- * warranties of fitness for purpose, satisfactory quality and
- * noninfringement. Keil extends you a royalty-free right to reproduce
- * and distribute executable files created using this software for use
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing
- * else gives you the right to use this software.
- *
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
- *----------------------------------------------------------------------------
- * History:
- * V1.20 Added vendor specific support
- * V1.00 Initial Version
- *----------------------------------------------------------------------------*/
-
-#ifndef __USBCFG_H__
-#define __USBCFG_H__
-
-
-//*** <<< Use Configuration Wizard in Context Menu >>> ***
-
-
-/*
-// <h> USB Configuration
-// <o0> USB Power
-// <i> Default Power Setting
-// <0=> Bus-powered
-// <1=> Self-powered
-// <o1> Max Number of Interfaces <1-256>
-// <o2> Max Number of Endpoints <1-32>
-// <o3> Max Endpoint 0 Packet Size
-// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
-// </h>
-*/
-
-#define USB_POWER 1
-#define USB_IF_NUM 1
-#define USB_EP_NUM 4
-#define USB_MAX_PACKET0 64
-
-
-/*
-// <h> USB Event Handlers
-// <h> Device Events
-// <o0.0> Power Event
-// <o1.0> Reset Event
-// <o2.0> Suspend Event
-// <o3.0> Resume Event
-// <o4.0> Remote Wakeup Event
-// <o5.0> Start of Frame Event
-// <o6.0> Error Event
-// </h>
-// <h> Endpoint Events
-// <o7.0> Endpoint 0 Event
-// <o7.1> Endpoint 1 Event
-// <o7.2> Endpoint 2 Event
-// <o7.3> Endpoint 3 Event
-// <o7.4> Endpoint 4 Event
-// </h>
-// <h> USB Core Events
-// <o8.0> Set Configuration Event
-// <o9.0> Set Interface Event
-// <o10.0> Set/Clear Feature Event
-// </h>
-// </h>
-*/
-
-#define USB_POWER_EVENT 0
-#define USB_RESET_EVENT 1
-#define USB_SUSPEND_EVENT 1
-#define USB_RESUME_EVENT 1
-#define USB_WAKEUP_EVENT 0
-#define USB_SOF_EVENT 0
-#define USB_ERROR_EVENT 0
-#define USB_EP_EVENT 0x0007
-#define USB_CONFIGURE_EVENT 1
-#define USB_INTERFACE_EVENT 0
-#define USB_FEATURE_EVENT 0
-
-
-/*
-// <e0> USB Class Support
-// <i> enables USB Class specific Requests
-// <e1> Human Interface Device (HID)
-// <o2> Interface Number <0-255>
-// </e>
-// <e3> Mass Storage
-// <o4> Interface Number <0-255>
-// </e>
-// <e5> Audio Device
-// <o6> Control Interface Number <0-255>
-// <o7> Streaming Interface 1 Number <0-255>
-// <o8> Streaming Interface 2 Number <0-255>
-// </e>
-// <e9> Communication Device
-// <o10> Control Interface Number <0-255>
-// <o11> Bulk Interface Number <0-255>
-// <o12> Max Communication Device Buffer Size
-// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
-// </e>
-// </e>
-*/
-
-#define USB_CLASS 1
-#define USB_HID 0
-#define USB_HID_IF_NUM 0
-#define USB_MSC 0
-#define USB_MSC_IF_NUM 0
-#define USB_AUDIO 0
-#define USB_ADC_CIF_NUM 0
-#define USB_ADC_SIF1_NUM 1
-#define USB_ADC_SIF2_NUM 2
-#define USB_CDC 1
-#define USB_CDC_CIF_NUM 0
-#define USB_CDC_DIF_NUM 1
-#define USB_CDC_BUFSIZE 64
-
-/*
-// <e0> USB Vendor Support
-// <i> enables USB Vendor specific Requests
-// </e>
-*/
-#define USB_VENDOR 0
-
-#define USE_USB0
-
-
-#endif /* __USBCFG_H__ */
+++ /dev/null
-/*----------------------------------------------------------------------------
- * U S B - K e r n e l
- *----------------------------------------------------------------------------
- * Name: usbcore.h
- * Purpose: USB Core Definitions
- * Version: V1.20
- *----------------------------------------------------------------------------
- * This software is supplied "AS IS" without any warranties, express,
- * implied or statutory, including but not limited to the implied
- * warranties of fitness for purpose, satisfactory quality and
- * noninfringement. Keil extends you a royalty-free right to reproduce
- * and distribute executable files created using this software for use
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else
- * gives you the right to use this software.
- *
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
- *---------------------------------------------------------------------------*/
-
-#ifndef __USBCORE_H__
-#define __USBCORE_H__
-
-
-/* USB Endpoint Data Structure */
-typedef struct _USB_EP_DATA {
- uint8_t *pData;
- uint16_t Count;
-} USB_EP_DATA;
-
-/* USB Core Global Variables */
-extern uint16_t USB_DeviceStatus;
-extern uint8_t USB_DeviceAddress;
-extern uint8_t USB_Configuration;
-extern uint32_t USB_EndPointMask;
-extern uint32_t USB_EndPointHalt;
-extern uint32_t USB_EndPointStall;
-extern uint8_t USB_AltSetting[USB_IF_NUM];
-
-/* USB Endpoint 0 Buffer */
-extern uint8_t EP0Buf[USB_MAX_PACKET0];
-
-/* USB Endpoint 0 Data Info */
-extern USB_EP_DATA EP0Data;
-
-/* USB Setup Packet */
-extern USB_SETUP_PACKET SetupPacket;
-
-/* USB Core Functions */
-extern void USB_ResetCore (void);
-
-
-#endif /* __USBCORE_H__ */
+++ /dev/null
-/*----------------------------------------------------------------------------
- * U S B - K e r n e l
- *----------------------------------------------------------------------------
- * Name: usbdesc.h
- * Purpose: USB Descriptors Definitions
- * Version: V1.20
- *----------------------------------------------------------------------------
- * This software is supplied "AS IS" without any warranties, express,
- * implied or statutory, including but not limited to the implied
- * warranties of fitness for purpose, satisfactory quality and
- * noninfringement. Keil extends you a royalty-free right to reproduce
- * and distribute executable files created using this software for use
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else
- * gives you the right to use this software.
- *
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
- *---------------------------------------------------------------------------*/
-
-#ifndef __USBDESC_H__
-#define __USBDESC_H__
-
-
-#define WBVAL(x) (x & 0xFF),((x >> 8) & 0xFF)
-
-#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))
-#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))
-#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))
-#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))
-#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR))
-#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION))
-
-extern const uint8_t USB_DeviceDescriptor[];
-extern const uint8_t USB_FSConfigDescriptor[];
-extern const uint8_t USB_HSConfigDescriptor[];
-extern const uint8_t USB_StringDescriptor[];
-extern const uint8_t USB_DeviceQualifier[];
-extern const uint8_t USB_FSOtherSpeedConfiguration[];
-extern const uint8_t USB_HSOtherSpeedConfiguration[];
-
-
-#endif /* __USBDESC_H__ */
+++ /dev/null
-/*----------------------------------------------------------------------------
- * U S B - K e r n e l
- *----------------------------------------------------------------------------
- * Name: usbhw.h
- * Purpose: USB Hardware Layer Definitions
- * Version: V1.20
- *----------------------------------------------------------------------------
- * This software is supplied "AS IS" without any warranties, express,
- * implied or statutory, including but not limited to the implied
- * warranties of fitness for purpose, satisfactory quality and
- * noninfringement. Keil extends you a royalty-free right to reproduce
- * and distribute executable files created using this software for use
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing
- * else gives you the right to use this software.
- *
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
- *----------------------------------------------------------------------------
- * History:
- * V1.20 Added USB_ClearEPBuf
- * V1.00 Initial Version
- *----------------------------------------------------------------------------*/
-
-#ifndef __USBHW_H__
-#define __USBHW_H__
-#include "usb.h"
-/* dTD Transfer Description */
-typedef volatile struct
-{
- volatile uint32_t next_dTD;
- volatile uint32_t total_bytes ;
- volatile uint32_t buffer0;
- volatile uint32_t buffer1;
- volatile uint32_t buffer2;
- volatile uint32_t buffer3;
- volatile uint32_t buffer4;
- volatile uint32_t reserved;
-} DTD_T;
-
-/* dQH Queue Head */
-typedef volatile struct
-{
- volatile uint32_t cap;
- volatile uint32_t curr_dTD;
- volatile uint32_t next_dTD;
- volatile uint32_t total_bytes;
- volatile uint32_t buffer0;
- volatile uint32_t buffer1;
- volatile uint32_t buffer2;
- volatile uint32_t buffer3;
- volatile uint32_t buffer4;
- volatile uint32_t reserved;
- volatile uint32_t setup[2];
- volatile uint32_t gap[4];
-} DQH_T;
-
-/* bit defines for USBCMD register */
-#define USBCMD_RS (1<<0)
-#define USBCMD_RST (1<<1)
-#define USBCMD_ATDTW (1<<12)
-#define USBCMD_SUTW (1<<13)
-
-/* bit defines for USBSTS register */
-#define USBSTS_UI (1<<0)
-#define USBSTS_UEI (1<<1)
-#define USBSTS_PCI (1<<2)
-#define USBSTS_URI (1<<6)
-#define USBSTS_SRI (1<<7)
-#define USBSTS_SLI (1<<8)
-#define USBSTS_NAKI (1<<16)
-
-/* bit defines for DEVICEADDR register */
-#define USBDEV_ADDR_AD (1<<24)
-#define USBDEV_ADDR(n) (((n) & 0x7F)<<25)
-
-/* bit defines for PRTSC1 register */
-#define USBPRTS_CCS (1<<0)
-#define USBPRTS_PE (1<<2)
-#define USBPRTS_FPR (1<<6)
-#define USBPRTS_SUSP (1<<7)
-#define USBPRTS_PR (1<<8)
-#define USBPRTS_HSP (1<<9)
-#define USBPRTS_PLPSCD (1<<23)
-#define USBPRTS_PFSC (1<<24)
-
-/* bit defines for USBMODE register */
-#define USBMODE_CM_IDLE (0x0<<0)
-#define USBMODE_CM_DEV (0x2<<0)
-#define USBMODE_CM_HOST (0x3<<0)
-#define USBMODE_SLOM (1<<3)
-#define USBMODE_SDIS (1<<4)
-
-/* bit defines for EP registers*/
-#define USB_EP_BITPOS(n) (((n) & 0x80)? (0x10 | ((n) & 0x7)) : ((n) & 0x7))
-
-/* bit defines EPcontrol registers*/
-#define EPCTRL_RXS (1<<0)
-#define EPCTRL_RX_TYPE(n) (((n) & 0x3)<<2)
-#define EPCTRL_RX_CTL (0<<2)
-#define EPCTRL_RX_ISO (1<<2)
-#define EPCTRL_RX_BLK (2<<2)
-#define EPCTRL_RXI (1<<5)
-#define EPCTRL_RXR (1<<6)
-#define EPCTRL_RXE (1<<7)
-#define EPCTRL_TXS (1<<16)
-#define EPCTRL_TX_TYPE(n) (((n) & 0x3)<<18)
-#define EPCTRL_TX_CTL (0<<18)
-#define EPCTRL_TX_ISO (1<<18)
-#define EPCTRL_TX_BLK (2<<18)
-#define EPCTRL_TX_INT (3<<18)
-#define EPCTRL_TXI (1<<21)
-#define EPCTRL_TXR (1<<22)
-#define EPCTRL_TXE (1<<23)
-
-/* dQH field and bit defines */
-/* Temp fixed on max, should be taken out of table */
-#define QH_MAX_CTRL_PAYLOAD 0x03ff
-#define QH_MAX_PKT_LEN_POS 16
-#define QH_MAXP(n) (((n) & 0x3FF)<<16)
-#define QH_IOS (1<<15)
-#define QH_ZLT (1<<29)
-
-/* dTD field and bit defines */
-#define TD_NEXT_TERMINATE (1<<0)
-#define TD_IOC (1<<15)
-
-/* Total physical enpoints*/
-#define EP_NUM_MAX 8
-
-
-/* USB Hardware Functions */
-extern void USB_Init (LPC_USBDRV_INIT_T* cbs);
-extern void USB_Connect (uint32_t con);
-extern void USB_Reset (void);
-extern void USB_Suspend (void);
-extern void USB_Resume (void);
-extern void USB_WakeUp (void);
-extern void USB_WakeUpCfg (uint32_t cfg);
-extern void USB_SetAddress (uint32_t adr);
-extern void USB_Configure (uint32_t cfg);
-extern void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD);
-extern void USB_DirCtrlEP (uint32_t dir);
-extern void USB_EnableEP (uint32_t EPNum);
-extern void USB_DisableEP (uint32_t EPNum);
-extern void USB_ResetEP (uint32_t EPNum);
-extern void USB_SetStallEP (uint32_t EPNum);
-extern void USB_ClrStallEP (uint32_t EPNum);
-extern void USB_ClearEPBuf (uint32_t EPNum);
-extern uint32_t USB_SetTestMode(uint8_t mode);
-extern uint32_t USB_ReadEP (uint32_t EPNum, uint8_t *pData);
-extern uint32_t USB_ReadReqEP(uint32_t EPNum, uint8_t *pData, uint32_t len);
-extern uint32_t USB_ReadSetupPkt(uint32_t, uint32_t *);
-extern uint32_t USB_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt);
-extern uint32_t USB_GetFrame (void);
-//extern void USB_ISR(void) __irq;
-
-#endif /* __USBHW_H__ */
+++ /dev/null
-/*----------------------------------------------------------------------------
- * U S B - K e r n e l
- *----------------------------------------------------------------------------
- * Name: usbuser.h
- * Purpose: USB Custom User Definitions
- * Version: V1.20
- *----------------------------------------------------------------------------
- * This software is supplied "AS IS" without any warranties, express,
- * implied or statutory, including but not limited to the implied
- * warranties of fitness for purpose, satisfactory quality and
- * noninfringement. Keil extends you a royalty-free right to reproduce
- * and distribute executable files created using this software for use
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing
- * else gives you the right to use this software.
- *
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
- *---------------------------------------------------------------------------*/
-
-#ifndef __USBUSER_H__
-#define __USBUSER_H__
-
-
-/* USB Device Events Callback Functions */
-extern void USB_Power_Event (uint32_t power);
-extern void USB_Reset_Event (void);
-extern void USB_Suspend_Event (void);
-extern void USB_Resume_Event (void);
-extern void USB_WakeUp_Event (void);
-extern void USB_SOF_Event (void);
-extern void USB_Error_Event (uint32_t error);
-
-/* USB Endpoint Events Callback Pointers */
-extern void (* const USB_P_EP[USB_EP_NUM])(uint32_t event);
-
-/* USB Endpoint Events Callback Functions */
-extern void USB_EndPoint0 (uint32_t event);
-extern void USB_EndPoint1 (uint32_t event);
-extern void USB_EndPoint2 (uint32_t event);
-extern void USB_EndPoint3 (uint32_t event);
-extern void USB_EndPoint4 (uint32_t event);
-extern void USB_EndPoint5 (uint32_t event);
-
-/* USB Core Events Callback Functions */
-extern void USB_Configure_Event (void);
-extern void USB_Interface_Event (void);
-extern void USB_Feature_Event (void);
-
-
-#endif /* __USBUSER_H__ */
+++ /dev/null
-; \r
-; Keil - An ARM Company Comunication Device Class driver installation file\r
-; (C)2007 Copyright \r
-;\r
-\r
-[Version] \r
-Signature="$Windows NT$" \r
-Class=Ports\r
-ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} \r
-Provider=%Keil% \r
-LayoutFile=layout.inf\r
-DriverVer=01/06/07\r
-\r
-[Manufacturer] \r
-%Keil%=DeviceList,NT,NTamd64\r
-\r
-[DestinationDirs]\r
-DefaultDestDir=12\r
-\r
-[SourceDisksFiles]\r
-\r
-[SourceDisksNames]\r
-\r
-[DeviceList.NT] \r
-%DESCRIPTION%=LPC18xxUSB, USB\VID_1FC9&PID_2002 \r
-[DeviceList.NTamd64]\r
-%DESCRIPTION%=LPC18xxUSB, USB\VID_1FC9&PID_2002\r
-\r
-;------------------------------------------------------------------------------\r
-; Windows Sections\r
-;------------------------------------------------------------------------------\r
-\r
-[LPC18xxUSB.NT] \r
-Include=mdmcpq.inf\r
-CopyFiles=FakeModemCopyFileSection\r
-AddReg=LPC18xxUSB.NT.AddReg\r
-\r
-[LPC18xxUSB.NT.AddReg] \r
-HKR,,DevLoader,,*ntkern \r
-HKR,,NTMPDriver,,usbser.sys \r
-HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" \r
-\r
-[LPC18xxUSB.NT.Services] \r
-AddService=usbser, 0x00000002, DriverService.NT\r
-\r
-[DriverService.NT] \r
-DisplayName=%DESCRIPTION% \r
-ServiceType=1\r
-StartType=3\r
-ErrorControl=1\r
-ServiceBinary=%12%\usbser.sys \r
-LoadOrderGroup = Base\r
-\r
-;------------------------------------------------------------------------------\r
-; String Definitions\r
-;------------------------------------------------------------------------------\r
-\r
-[Strings] \r
-NXP="NXP - Founded by Philips"\r
-DESCRIPTION="LPC18xx USB VCom Port" \r
+++ /dev/null
-;
-; Keil - An ARM Company Comunication Device Class driver installation file
-; (C)2007 Copyright
-;
-
-[Version]
-Signature="$Windows NT$"
-Class=Ports
-ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
-Provider=%Keil%
-;LayoutFile=layout.inf
-DriverVer=01/06/07
-
-[Manufacturer]
-%Keil%=DeviceList
-
-[DestinationDirs]
-DefaultDestDir=12
-
-[SourceDisksFiles]
-
-[SourceDisksNames]
-
-[DeviceList]
-%DESCRIPTION%=LPC18xxUSB, USB\VID_1FC9&PID_2002
-
-;------------------------------------------------------------------------------
-; Windows 2000/XP Sections
-;------------------------------------------------------------------------------
-
-[LPC18xxUSB.nt]
-include=mdmcpq.inf
-CopyFiles=DriverCopyFiles
-AddReg=LPC18xxUSB.nt.AddReg
-
-[DriverCopyFiles]
-usbser.sys,,,0x20
-
-[LPC18xxUSB.nt.AddReg]
-HKR,,DevLoader,,*ntkern
-HKR,,NTMPDriver,,usbser.sys
-HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
-
-[LPC18xxUSB.nt.Services]
-include=mdmcpq.inf
-AddService=usbser, 0x00000002, DriverService
-
-
-[LPC18xxUSB.nt.HW]
-include=mdmcpq.inf
-
-[DriverService]
-DisplayName=%DESCRIPTION%
-ServiceType=1
-StartType=3
-ErrorControl=1
-ServiceBinary=%12%\usbser.sys
-
-;------------------------------------------------------------------------------
-; String Definitions
-;------------------------------------------------------------------------------
-
-[Strings]
-NXP="NXP - Founded by Philips"
-DESCRIPTION="LPC18xx USB VCom Port"
+++ /dev/null
-/*----------------------------------------------------------------------------
- * U S B - K e r n e l
- *----------------------------------------------------------------------------
- * Name: usbcore.c
- * Purpose: USB Core Module
- * Version: V1.20
- *----------------------------------------------------------------------------
- * This software is supplied "AS IS" without any warranties, express,
- * implied or statutory, including but not limited to the implied
- * warranties of fitness for purpose, satisfactory quality and
- * noninfringement. Keil extends you a royalty-free right to reproduce
- * and distribute executable files created using this software for use
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing
- * else gives you the right to use this software.
- *
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
- *----------------------------------------------------------------------------
- * History:
- * V1.20 Added vendor specific requests
- * Changed string descriptor handling
- * Reworked Endpoint0
- * V1.00 Initial Version
- *----------------------------------------------------------------------------*/
-#include "lpc18xx.H"
-#include "lpc_types.h"
-
-#include "usb.h"
-#include "usbcfg.h"
-#include "usbhw.h"
-#include "usbcore.h"
-#include "usbdesc.h"
-#include "usbuser.h"
-
-#if (USB_CLASS)
-
-#if (USB_AUDIO)
-#include "audio.h"
-#include "adcuser.h"
-#endif
-
-#if (USB_HID)
-#include "hid.h"
-#include "hiduser.h"
-#endif
-
-#if (USB_MSC)
-#include "msc.h"
-#include "mscuser.h"
-extern MSC_CSW CSW;
-#endif
-
-#if (USB_CDC)
-#include "cdc.h"
-#include "cdcuser.h"
-#endif
-
-#endif
-
-#if (USB_VENDOR)
-#include "vendor.h"
-#endif
-
-#ifdef __CC_ARM
-#pragma diag_suppress 111,177,1441
-#endif
-
-#if defined ( __GNUC__ )
-#define __packed __attribute__((__packed__))
-#endif
-
-uint16_t USB_DeviceStatus;
-uint8_t USB_DeviceAddress;
-uint8_t USB_Configuration;
-uint32_t USB_EndPointMask;
-uint32_t USB_EndPointHalt;
-uint32_t USB_EndPointStall; /* EP must stay stalled */
-uint8_t USB_NumInterfaces;
-uint8_t USB_AltSetting[USB_IF_NUM];
-
-USB_EP_DATA EP0Data;
-
-#pragma pack(4)
-uint8_t EP0Buf[USB_MAX_PACKET0];
-USB_SETUP_PACKET SetupPacket;
-
-extern volatile uint32_t DevStatusFS2HS;
-
-/*
- * Reset USB Core
- * Parameters: None
- * Return Value: None
- */
-
-void USB_ResetCore (void) {
-
- USB_DeviceStatus = USB_POWER;
- USB_DeviceAddress = 0;
- USB_Configuration = 0;
- USB_EndPointMask = 0x00010001;
- USB_EndPointHalt = 0x00000000;
- USB_EndPointStall = 0x00000000;
-}
-
-
-/*
- * USB Request - Setup Stage
- * Parameters: None (global SetupPacket)
- * Return Value: None
- */
-
-void USB_SetupStage (void) {
- USB_ReadSetupPkt(0x00, (uint32_t *)&SetupPacket);
-}
-
-
-/*
- * USB Request - Data In Stage
- * Parameters: None (global EP0Data)
- * Return Value: None
- */
-
-void USB_DataInStage (void) {
- uint32_t cnt;
-
- if (EP0Data.Count > USB_MAX_PACKET0) {
- cnt = USB_MAX_PACKET0;
- } else {
- cnt = EP0Data.Count;
- }
- cnt = USB_WriteEP(0x80, EP0Data.pData, cnt);
- EP0Data.pData += cnt;
- EP0Data.Count -= cnt;
-}
-
-
-/*
- * USB Request - Data Out Stage
- * Parameters: None (global EP0Data)
- * Return Value: None
- */
-
-void USB_DataOutStage (void) {
- uint32_t cnt;
-
- cnt = USB_ReadEP(0x00, EP0Data.pData);
- EP0Data.pData += cnt;
- EP0Data.Count -= cnt;
-}
-
-
-/*
- * USB Request - Status In Stage
- * Parameters: None
- * Return Value: None
- */
-
-void USB_StatusInStage (void) {
- USB_WriteEP(0x80, NULL, 0);
-}
-
-
-/*
- * USB Request - Status Out Stage
- * Parameters: None
- * Return Value: None
- */
-
-void USB_StatusOutStage (void) {
- USB_ReadEP(0x00, EP0Buf);
-}
-
-
-/*
- * Get Status USB Request
- * Parameters: None (global SetupPacket)
- * Return Value: TRUE - Success, FALSE - Error
- */
-
-INLINE uint32_t USB_ReqGetStatus (void) {
- uint32_t n, m;
-
- switch (SetupPacket.bmRequestType.BM.Recipient) {
- case REQUEST_TO_DEVICE:
- EP0Data.pData = (uint8_t *)&USB_DeviceStatus;
- break;
- case REQUEST_TO_INTERFACE:
- if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) {
- *((__packed uint16_t *)EP0Buf) = 0;
- EP0Data.pData = EP0Buf;
- } else {
- return (FALSE);
- }
- break;
- case REQUEST_TO_ENDPOINT:
- n = SetupPacket.wIndex.WB.L & 0x8F;
- m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
- if (((USB_Configuration != 0) || ((n & 0x0F) == 0)) && (USB_EndPointMask & m)) {
- *((__packed uint16_t *)EP0Buf) = (USB_EndPointHalt & m) ? 1 : 0;
- EP0Data.pData = EP0Buf;
- } else {
- return (FALSE);
- }
- break;
- default:
- return (FALSE);
- }
- return (TRUE);
-}
-
-
-/*
- * Set/Clear Feature USB Request
- * Parameters: sc: 0 - Clear, 1 - Set
- * (global SetupPacket)
- * Return Value: TRUE - Success, FALSE - Error
- */
-
-INLINE uint32_t USB_ReqSetClrFeature (uint32_t sc) {
- uint32_t n, m;
-
- switch (SetupPacket.bmRequestType.BM.Recipient) {
- case REQUEST_TO_DEVICE:
- if (SetupPacket.wValue.W == USB_FEATURE_REMOTE_WAKEUP) {
- if (sc) {
- USB_WakeUpCfg(TRUE);
- USB_DeviceStatus |= USB_GETSTATUS_REMOTE_WAKEUP;
- } else {
- USB_WakeUpCfg(FALSE);
- USB_DeviceStatus &= ~USB_GETSTATUS_REMOTE_WAKEUP;
- }
- } else if (SetupPacket.wValue.W == USB_FEATURE_TEST_MODE) {
- return USB_SetTestMode(SetupPacket.wIndex.WB.H);
- } else {
- return (FALSE);
- }
- break;
- case REQUEST_TO_INTERFACE:
- return (FALSE);
- case REQUEST_TO_ENDPOINT:
- n = SetupPacket.wIndex.WB.L & 0x8F;
- m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
- if ((USB_Configuration != 0) && ((n & 0x0F) != 0) && (USB_EndPointMask & m)) {
- if (SetupPacket.wValue.W == USB_FEATURE_ENDPOINT_STALL) {
- if (sc) {
- USB_SetStallEP(n);
- USB_EndPointHalt |= m;
- } else {
- if ((USB_EndPointStall & m) != 0) {
- return (TRUE);
- }
- USB_ClrStallEP(n);
-#if (USB_MSC)
- if ((n == MSC_EP_IN) && ((USB_EndPointHalt & m) != 0)) {
- /* Compliance Test: rewrite CSW after unstall */
- if (CSW.dSignature == MSC_CSW_Signature) {
- USB_WriteEP(MSC_EP_IN, (uint8_t *)&CSW, sizeof(CSW));
- }
- }
-#endif
- USB_EndPointHalt &= ~m;
- }
- } else {
- return (FALSE);
- }
- } else {
- return (FALSE);
- }
- break;
- default:
- return (FALSE);
- }
- return (TRUE);
-}
-
-
-/*
- * Set Address USB Request
- * Parameters: None (global SetupPacket)
- * Return Value: TRUE - Success, FALSE - Error
- */
-
-INLINE uint32_t USB_ReqSetAddress (void) {
-
- switch (SetupPacket.bmRequestType.BM.Recipient) {
- case REQUEST_TO_DEVICE:
- USB_DeviceAddress = 0x80 | SetupPacket.wValue.WB.L;
- break;
- default:
- return (FALSE);
- }
- return (TRUE);
-}
-
-
-/*
- * Get Descriptor USB Request
- * Parameters: None (global SetupPacket)
- * Return Value: TRUE - Success, FALSE - Error
- */
-
-INLINE uint32_t USB_ReqGetDescriptor (void) {
- uint8_t *pD;
- uint32_t len, n;
-
- switch (SetupPacket.bmRequestType.BM.Recipient) {
- case REQUEST_TO_DEVICE:
- switch (SetupPacket.wValue.WB.H) {
- case USB_DEVICE_DESCRIPTOR_TYPE:
- EP0Data.pData = (uint8_t *)USB_DeviceDescriptor;
- len = USB_DEVICE_DESC_SIZE;
- break;
- case USB_CONFIGURATION_DESCRIPTOR_TYPE:
- if ( DevStatusFS2HS == FALSE ) {
- pD = (uint8_t *)USB_FSConfigDescriptor;
- } else {
- pD = (uint8_t *)USB_HSConfigDescriptor;
- }
- for (n = 0; n != SetupPacket.wValue.WB.L; n++) {
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength != 0) {
- pD += ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
- }
- }
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bLength == 0) {
- return (FALSE);
- }
- EP0Data.pData = pD;
- len = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
- break;
- case USB_STRING_DESCRIPTOR_TYPE:
- pD = (uint8_t *)USB_StringDescriptor;
- for (n = 0; n != SetupPacket.wValue.WB.L; n++) {
- if (((USB_STRING_DESCRIPTOR *)pD)->bLength != 0) {
- pD += ((USB_STRING_DESCRIPTOR *)pD)->bLength;
- }
- }
- if (((USB_STRING_DESCRIPTOR *)pD)->bLength == 0) {
- return (FALSE);
- }
- EP0Data.pData = pD;
- len = ((USB_STRING_DESCRIPTOR *)pD)->bLength;
- break;
- case USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE:
- /* USB Chapter 9. page 9.6.2 */
- if ( DevStatusFS2HS == FALSE ) {
- return (FALSE);
- }
- else
- {
- EP0Data.pData = (uint8_t *)USB_DeviceQualifier;
- len = USB_DEVICE_QUALI_SIZE;
- }
- break;
- case USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE:
- if ( DevStatusFS2HS == TRUE ) {
- pD = (uint8_t *)USB_FSOtherSpeedConfiguration;
- } else {
- pD = (uint8_t *)USB_HSOtherSpeedConfiguration;
- }
-
- for (n = 0; n != SetupPacket.wValue.WB.L; n++) {
- if (((USB_OTHER_SPEED_CONFIGURATION *)pD)->bLength != 0) {
- pD += ((USB_OTHER_SPEED_CONFIGURATION *)pD)->wTotalLength;
- }
- }
- if (((USB_OTHER_SPEED_CONFIGURATION *)pD)->bLength == 0) {
- return (FALSE);
- }
- EP0Data.pData = pD;
- len = ((USB_OTHER_SPEED_CONFIGURATION *)pD)->wTotalLength;
- break;
- default:
- return (FALSE);
- }
- break;
- case REQUEST_TO_INTERFACE:
- switch (SetupPacket.wValue.WB.H) {
-#if USB_HID
- case HID_HID_DESCRIPTOR_TYPE:
- if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) {
- return (FALSE); /* Only Single HID Interface is supported */
- }
- if ( DevStatusFS2HS == FALSE ) {
- EP0Data.pData = (uint8_t *)USB_FSConfigDescriptor + HID_DESC_OFFSET;
- } else {
- EP0Data.pData = (uint8_t *)USB_HSConfigDescriptor + HID_DESC_OFFSET;
- }
- len = HID_DESC_SIZE;
- break;
- case HID_REPORT_DESCRIPTOR_TYPE:
- if (SetupPacket.wIndex.WB.L != USB_HID_IF_NUM) {
- return (FALSE); /* Only Single HID Interface is supported */
- }
- EP0Data.pData = (uint8_t *)HID_ReportDescriptor;
- len = HID_ReportDescSize;
- break;
- case HID_PHYSICAL_DESCRIPTOR_TYPE:
- return (FALSE); /* HID Physical Descriptor is not supported */
-#endif
- default:
- return (FALSE);
- }
- break;
- default:
- return (FALSE);
- }
-
- if (EP0Data.Count > len) {
- EP0Data.Count = len;
- }
-
- return (TRUE);
-}
-
-
-/*
- * Get Configuration USB Request
- * Parameters: None (global SetupPacket)
- * Return Value: TRUE - Success, FALSE - Error
- */
-
-INLINE uint32_t USB_ReqGetConfiguration (void) {
-
- switch (SetupPacket.bmRequestType.BM.Recipient) {
- case REQUEST_TO_DEVICE:
- EP0Data.pData = &USB_Configuration;
- break;
- default:
- return (FALSE);
- }
- return (TRUE);
-}
-
-
-/*
- * Set Configuration USB Request
- * Parameters: None (global SetupPacket)
- * Return Value: TRUE - Success, FALSE - Error
- */
-
-INLINE uint32_t USB_ReqSetConfiguration (void) {
- USB_COMMON_DESCRIPTOR *pD;
- uint32_t alt = 0;
- uint32_t n, m;
- uint32_t new_addr;
- switch (SetupPacket.bmRequestType.BM.Recipient) {
- case REQUEST_TO_DEVICE:
-
- if (SetupPacket.wValue.WB.L) {
- if ( DevStatusFS2HS == FALSE ) {
- pD = (USB_COMMON_DESCRIPTOR *)USB_FSConfigDescriptor;
- } else {
- pD = (USB_COMMON_DESCRIPTOR *)USB_HSConfigDescriptor;
- }
- while (pD->bLength) {
- switch (pD->bDescriptorType) {
- case USB_CONFIGURATION_DESCRIPTOR_TYPE:
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue == SetupPacket.wValue.WB.L) {
- USB_Configuration = SetupPacket.wValue.WB.L;
- USB_NumInterfaces = ((USB_CONFIGURATION_DESCRIPTOR *)pD)->bNumInterfaces;
- for (n = 0; n < USB_IF_NUM; n++) {
- USB_AltSetting[n] = 0;
- }
- for (n = 1; n < USB_EP_NUM; n++) {
- if (USB_EndPointMask & (1 << n)) {
- USB_DisableEP(n);
- }
- if (USB_EndPointMask & ((1 << 16) << n)) {
- USB_DisableEP(n | 0x80);
- }
- }
- USB_EndPointMask = 0x00010001;
- USB_EndPointHalt = 0x00000000;
- USB_EndPointStall= 0x00000000;
- USB_Configure(TRUE);
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bmAttributes & USB_CONFIG_POWERED_MASK) {
- USB_DeviceStatus |= USB_GETSTATUS_SELF_POWERED;
- } else {
- USB_DeviceStatus &= ~USB_GETSTATUS_SELF_POWERED;
- }
- } else {
- new_addr = (uint32_t)pD + ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
- pD = (USB_COMMON_DESCRIPTOR*)new_addr;
- continue;
- }
- break;
- case USB_INTERFACE_DESCRIPTOR_TYPE:
- alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;
- break;
- case USB_ENDPOINT_DESCRIPTOR_TYPE:
- if (alt == 0) {
- n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;
- m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
- USB_EndPointMask |= m;
- USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD);
- USB_EnableEP(n);
- USB_ResetEP(n);
- }
- break;
- }
- new_addr = (uint32_t)pD + pD->bLength;
- pD = (USB_COMMON_DESCRIPTOR*)new_addr;
- }
- }
- else {
- USB_Configuration = 0;
- for (n = 1; n < USB_EP_NUM; n++) {
- if (USB_EndPointMask & (1 << n)) {
- USB_DisableEP(n);
- }
- if (USB_EndPointMask & ((1 << 16) << n)) {
- USB_DisableEP(n | 0x80);
- }
- }
- USB_EndPointMask = 0x00010001;
- USB_EndPointHalt = 0x00000000;
- USB_EndPointStall = 0x00000000;
- USB_Configure(FALSE);
- }
-
- if (USB_Configuration != SetupPacket.wValue.WB.L) {
- return (FALSE);
- }
- break;
- default:
- return (FALSE);
- }
- return (TRUE);
-}
-
-
-/*
- * Get Interface USB Request
- * Parameters: None (global SetupPacket)
- * Return Value: TRUE - Success, FALSE - Error
- */
-
-INLINE uint32_t USB_ReqGetInterface (void) {
-
- switch (SetupPacket.bmRequestType.BM.Recipient) {
- case REQUEST_TO_INTERFACE:
- if ((USB_Configuration != 0) && (SetupPacket.wIndex.WB.L < USB_NumInterfaces)) {
- EP0Data.pData = USB_AltSetting + SetupPacket.wIndex.WB.L;
- } else {
- return (FALSE);
- }
- break;
- default:
- return (FALSE);
- }
- return (TRUE);
-}
-
-
-/*
- * Set Interface USB Request
- * Parameters: None (global SetupPacket)
- * Return Value: TRUE - Success, FALSE - Error
- */
-
-INLINE uint32_t USB_ReqSetInterface (void) {
- USB_COMMON_DESCRIPTOR *pD;
- uint32_t ifn = 0, alt = 0, old = 0, msk = 0;
- uint32_t n, m;
- uint32_t set, new_addr;
-
- switch (SetupPacket.bmRequestType.BM.Recipient) {
- case REQUEST_TO_INTERFACE:
- if (USB_Configuration == 0) return (FALSE);
- set = FALSE;
- if ( DevStatusFS2HS == FALSE ) {
- pD = (USB_COMMON_DESCRIPTOR *)USB_FSConfigDescriptor;
- } else {
- pD = (USB_COMMON_DESCRIPTOR *)USB_HSConfigDescriptor;
- }
- while (pD->bLength) {
- switch (pD->bDescriptorType) {
- case USB_CONFIGURATION_DESCRIPTOR_TYPE:
- if (((USB_CONFIGURATION_DESCRIPTOR *)pD)->bConfigurationValue != USB_Configuration) {
- new_addr = (uint32_t)pD + ((USB_CONFIGURATION_DESCRIPTOR *)pD)->wTotalLength;
- pD = (USB_COMMON_DESCRIPTOR*)new_addr;
- continue;
- }
- break;
- case USB_INTERFACE_DESCRIPTOR_TYPE:
- ifn = ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber;
- alt = ((USB_INTERFACE_DESCRIPTOR *)pD)->bAlternateSetting;
- msk = 0;
- if ((ifn == SetupPacket.wIndex.WB.L) && (alt == SetupPacket.wValue.WB.L)) {
- set = TRUE;
- old = USB_AltSetting[ifn];
- USB_AltSetting[ifn] = (uint8_t)alt;
- }
- break;
- case USB_ENDPOINT_DESCRIPTOR_TYPE:
- if (ifn == SetupPacket.wIndex.WB.L) {
- n = ((USB_ENDPOINT_DESCRIPTOR *)pD)->bEndpointAddress & 0x8F;
- m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n);
- if (alt == SetupPacket.wValue.WB.L) {
- USB_EndPointMask |= m;
- USB_EndPointHalt &= ~m;
- USB_ConfigEP((USB_ENDPOINT_DESCRIPTOR *)pD);
- USB_EnableEP(n);
- USB_ResetEP(n);
- msk |= m;
- }
- else if ((alt == old) && ((msk & m) == 0)) {
- USB_EndPointMask &= ~m;
- USB_EndPointHalt &= ~m;
- USB_DisableEP(n);
- }
- }
- break;
- }
- new_addr = (uint32_t)pD + pD->bLength;
- pD = (USB_COMMON_DESCRIPTOR*)new_addr;
- }
- break;
- default:
- return (FALSE);
- }
-
- return (set);
-}
-
-
-/*
- * USB Endpoint 0 Event Callback
- * Parameters: event
- * Return Value: none
- */
-
-void USB_EndPoint0 (uint32_t event) {
-
- switch (event) {
- case USB_EVT_SETUP:
- USB_SetupStage();
- USB_DirCtrlEP(SetupPacket.bmRequestType.BM.Dir);
- EP0Data.Count = SetupPacket.wLength; /* Number of bytes to transfer */
- switch (SetupPacket.bmRequestType.BM.Type) {
-
- case REQUEST_STANDARD:
- switch (SetupPacket.bRequest) {
- case USB_REQUEST_GET_STATUS:
- if (!USB_ReqGetStatus()) {
- goto stall_i;
- }
- USB_DataInStage();
- break;
-
- case USB_REQUEST_CLEAR_FEATURE:
- if (!USB_ReqSetClrFeature(0)) {
- goto stall_i;
- }
- USB_StatusInStage();
-#if USB_FEATURE_EVENT
- USB_Feature_Event();
-#endif
- break;
-
- case USB_REQUEST_SET_FEATURE:
- if (!USB_ReqSetClrFeature(1)) {
- goto stall_i;
- }
- USB_StatusInStage();
-#if USB_FEATURE_EVENT
- USB_Feature_Event();
-#endif
- break;
-
- case USB_REQUEST_SET_ADDRESS:
- if (!USB_ReqSetAddress()) {
- goto stall_i;
- }
- USB_StatusInStage();
- break;
-
- case USB_REQUEST_GET_DESCRIPTOR:
- if (!USB_ReqGetDescriptor()) {
- goto stall_i;
- }
- USB_DataInStage();
- break;
-
- case USB_REQUEST_SET_DESCRIPTOR:
-/*stall_o:*/ USB_SetStallEP(0x00); /* not supported */
- EP0Data.Count = 0;
- break;
-
- case USB_REQUEST_GET_CONFIGURATION:
- if (!USB_ReqGetConfiguration()) {
- goto stall_i;
- }
- USB_DataInStage();
- break;
-
- case USB_REQUEST_SET_CONFIGURATION:
- if (!USB_ReqSetConfiguration()) {
- goto stall_i;
- }
- USB_StatusInStage();
-#if USB_CONFIGURE_EVENT
- USB_Configure_Event();
-#endif
- break;
-
- case USB_REQUEST_GET_INTERFACE:
- if (!USB_ReqGetInterface()) {
- goto stall_i;
- }
- USB_DataInStage();
- break;
-
- case USB_REQUEST_SET_INTERFACE:
- if (!USB_ReqSetInterface()) {
- goto stall_i;
- }
- USB_StatusInStage();
-#if USB_INTERFACE_EVENT
- USB_Interface_Event();
-#endif
- break;
-
- default:
- goto stall_i;
- }
- break; /* end case REQUEST_STANDARD */
-
-#if USB_CLASS
- case REQUEST_CLASS:
- switch (SetupPacket.bmRequestType.BM.Recipient) {
-
- case REQUEST_TO_DEVICE:
- goto stall_i; /* not supported */
-
- case REQUEST_TO_INTERFACE:
-#if USB_HID
- if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */
- switch (SetupPacket.bRequest) {
- case HID_REQUEST_GET_REPORT:
- if (HID_GetReport()) {
- EP0Data.pData = EP0Buf; /* point to data to be sent */
- USB_DataInStage(); /* send requested data */
- goto setup_class_ok;
- }
- break;
- case HID_REQUEST_SET_REPORT:
- EP0Data.pData = EP0Buf; /* data to be received */
- goto setup_class_ok;
- case HID_REQUEST_GET_IDLE:
- if (HID_GetIdle()) {
- EP0Data.pData = EP0Buf; /* point to data to be sent */
- USB_DataInStage(); /* send requested data */
- goto setup_class_ok;
- }
- break;
- case HID_REQUEST_SET_IDLE:
- if (HID_SetIdle()) {
- USB_StatusInStage(); /* send Acknowledge */
- goto setup_class_ok;
- }
- break;
- case HID_REQUEST_GET_PROTOCOL:
- if (HID_GetProtocol()) {
- EP0Data.pData = EP0Buf; /* point to data to be sent */
- USB_DataInStage(); /* send requested data */
- goto setup_class_ok;
- }
- break;
- case HID_REQUEST_SET_PROTOCOL:
- if (HID_SetProtocol()) {
- USB_StatusInStage(); /* send Acknowledge */
- goto setup_class_ok;
- }
- break;
- }
- }
-#endif /* USB_HID */
-#if USB_MSC
- if (SetupPacket.wIndex.WB.L == USB_MSC_IF_NUM) { /* IF number correct? */
- switch (SetupPacket.bRequest) {
- case MSC_REQUEST_RESET:
- if ((SetupPacket.wValue.W == 0) && /* RESET with invalid parameters -> STALL */
- (SetupPacket.wLength == 0)) {
- if (MSC_Reset()) {
- USB_StatusInStage();
- goto setup_class_ok;
- }
- }
- break;
- case MSC_REQUEST_GET_MAX_LUN:
- if ((SetupPacket.wValue.W == 0) && /* GET_MAX_LUN with invalid parameters -> STALL */
- (SetupPacket.wLength == 1)) {
- if (MSC_GetMaxLUN()) {
- EP0Data.pData = EP0Buf;
- USB_DataInStage();
- goto setup_class_ok;
- }
- }
- break;
- }
- }
-#endif /* USB_MSC */
-#if USB_AUDIO
- if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */
- (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) ||
- (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) {
- switch (SetupPacket.bRequest) {
- case AUDIO_REQUEST_GET_CUR:
- case AUDIO_REQUEST_GET_MIN:
- case AUDIO_REQUEST_GET_MAX:
- case AUDIO_REQUEST_GET_RES:
- if (ADC_IF_GetRequest()) {
- EP0Data.pData = EP0Buf; /* point to data to be sent */
- USB_DataInStage(); /* send requested data */
- goto setup_class_ok;
- }
- break;
- case AUDIO_REQUEST_SET_CUR:
-// case AUDIO_REQUEST_SET_MIN:
-// case AUDIO_REQUEST_SET_MAX:
-// case AUDIO_REQUEST_SET_RES:
- EP0Data.pData = EP0Buf; /* data to be received */
- goto setup_class_ok;
- }
- }
-#endif /* USB_AUDIO */
-#if USB_CDC
- if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */
- (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) {
- switch (SetupPacket.bRequest) {
- case CDC_SEND_ENCAPSULATED_COMMAND:
- EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */
- goto setup_class_ok;
- case CDC_GET_ENCAPSULATED_RESPONSE:
- if (CDC_GetEncapsulatedResponse()) {
- EP0Data.pData = EP0Buf; /* point to data to be sent */
- USB_DataInStage(); /* send requested data */
- goto setup_class_ok;
- }
- break;
- case CDC_SET_COMM_FEATURE:
- EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */
- goto setup_class_ok;
- case CDC_GET_COMM_FEATURE:
- if (CDC_GetCommFeature(SetupPacket.wValue.W)) {
- EP0Data.pData = EP0Buf; /* point to data to be sent */
- USB_DataInStage(); /* send requested data */
- goto setup_class_ok;
- }
- break;
- case CDC_CLEAR_COMM_FEATURE:
- if (CDC_ClearCommFeature(SetupPacket.wValue.W)) {
- USB_StatusInStage(); /* send Acknowledge */
- goto setup_class_ok;
- }
- break;
- case CDC_SET_LINE_CODING:
- EP0Data.pData = EP0Buf; /* data to be received, see USB_EVT_OUT */
- goto setup_class_ok;
- case CDC_GET_LINE_CODING:
- if (CDC_GetLineCoding()) {
- EP0Data.pData = EP0Buf; /* point to data to be sent */
- USB_DataInStage(); /* send requested data */
- goto setup_class_ok;
- }
- break;
- case CDC_SET_CONTROL_LINE_STATE:
- if (CDC_SetControlLineState(SetupPacket.wValue.W)) {
- USB_StatusInStage(); /* send Acknowledge */
- goto setup_class_ok;
- }
- break;
- case CDC_SEND_BREAK:
- if (CDC_SendBreak(SetupPacket.wValue.W)) {
- USB_StatusInStage(); /* send Acknowledge */
- goto setup_class_ok;
- }
- break;
- }
- }
-#endif /* USB_CDC */
- goto stall_i; /* not supported */
- /* end case REQUEST_TO_INTERFACE */
-
- case REQUEST_TO_ENDPOINT:
-#if USB_AUDIO
- switch (SetupPacket.bRequest) {
- case AUDIO_REQUEST_GET_CUR:
- case AUDIO_REQUEST_GET_MIN:
- case AUDIO_REQUEST_GET_MAX:
- case AUDIO_REQUEST_GET_RES:
- if (ADC_EP_GetRequest()) {
- EP0Data.pData = EP0Buf; /* point to data to be sent */
- USB_DataInStage(); /* send requested data */
- goto setup_class_ok;
- }
- break;
- case AUDIO_REQUEST_SET_CUR:
-// case AUDIO_REQUEST_SET_MIN:
-// case AUDIO_REQUEST_SET_MAX:
-// case AUDIO_REQUEST_SET_RES:
- EP0Data.pData = EP0Buf; /* data to be received */
- goto setup_class_ok;
- }
-#endif /* USB_AUDIO */
- goto stall_i;
- /* end case REQUEST_TO_ENDPOINT */
-
- default:
- goto stall_i;
- }
-setup_class_ok: /* request finished successfully */
- break; /* end case REQUEST_CLASS */
-#endif /* USB_CLASS */
-
-#if USB_VENDOR
- case REQUEST_VENDOR:
- switch (SetupPacket.bmRequestType.BM.Recipient) {
-
- case REQUEST_TO_DEVICE:
- if (!USB_ReqVendorDev(TRUE)) {
- goto stall_i; /* not supported */
- }
- break;
-
- case REQUEST_TO_INTERFACE:
- if (!USB_ReqVendorIF(TRUE)) {
- goto stall_i; /* not supported */
- }
- break;
-
- case REQUEST_TO_ENDPOINT:
- if (!USB_ReqVendorEP(TRUE)) {
- goto stall_i; /* not supported */
- }
- break;
-
- default:
- goto stall_i;
- }
-
- if (SetupPacket.wLength) {
- if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) {
- USB_DataInStage();
- }
- } else {
- USB_StatusInStage();
- }
-
- break; /* end case REQUEST_VENDOR */
-#endif /* USB_VENDOR */
-
- default:
-stall_i: USB_SetStallEP(0x80);
- EP0Data.Count = 0;
- break;
- }
- break; /* end case USB_EVT_SETUP */
-
- case USB_EVT_OUT_NAK:
- if (SetupPacket.bmRequestType.BM.Dir == 0)
- {
- USB_ReadReqEP(0x00, EP0Data.pData, EP0Data.Count);
- }
- else
- {
- /* might be zero length pkt */
- USB_ReadReqEP(0x00, EP0Data.pData, 0);
- }
- break;
- case USB_EVT_OUT:
- if (SetupPacket.bmRequestType.BM.Dir == REQUEST_HOST_TO_DEVICE) {
- if (EP0Data.Count) { /* still data to receive ? */
- USB_DataOutStage(); /* receive data */
- if (EP0Data.Count == 0) { /* data complete ? */
- switch (SetupPacket.bmRequestType.BM.Type) {
-
- case REQUEST_STANDARD:
- goto stall_i; /* not supported */
-
-#if (USB_CLASS)
- case REQUEST_CLASS:
- switch (SetupPacket.bmRequestType.BM.Recipient) {
- case REQUEST_TO_DEVICE:
- goto stall_i; /* not supported */
-
- case REQUEST_TO_INTERFACE:
-#if USB_HID
- if (SetupPacket.wIndex.WB.L == USB_HID_IF_NUM) { /* IF number correct? */
- switch (SetupPacket.bRequest) {
- case HID_REQUEST_SET_REPORT:
- if (HID_SetReport()) {
- USB_StatusInStage(); /* send Acknowledge */
- goto out_class_ok;
- }
- break;
- }
- }
-#endif /* USB_HID */
-#if USB_AUDIO
- if ((SetupPacket.wIndex.WB.L == USB_ADC_CIF_NUM) || /* IF number correct? */
- (SetupPacket.wIndex.WB.L == USB_ADC_SIF1_NUM) ||
- (SetupPacket.wIndex.WB.L == USB_ADC_SIF2_NUM)) {
- switch (SetupPacket.bRequest) {
- case AUDIO_REQUEST_SET_CUR:
-// case AUDIO_REQUEST_SET_MIN:
-// case AUDIO_REQUEST_SET_MAX:
-// case AUDIO_REQUEST_SET_RES:
- if (ADC_IF_SetRequest()) {
- USB_StatusInStage(); /* send Acknowledge */
- goto out_class_ok;
- }
- break;
- }
- }
-#endif /* USB_AUDIO */
-#if USB_CDC
- if ((SetupPacket.wIndex.WB.L == USB_CDC_CIF_NUM) || /* IF number correct? */
- (SetupPacket.wIndex.WB.L == USB_CDC_DIF_NUM)) {
- switch (SetupPacket.bRequest) {
- case CDC_SEND_ENCAPSULATED_COMMAND:
- if (CDC_SendEncapsulatedCommand()) {
- USB_StatusInStage(); /* send Acknowledge */
- goto out_class_ok;
- }
- break;
- case CDC_SET_COMM_FEATURE:
- if (CDC_SetCommFeature(SetupPacket.wValue.W)) {
- USB_StatusInStage(); /* send Acknowledge */
- goto out_class_ok;
- }
- break;
- case CDC_SET_LINE_CODING:
- if (CDC_SetLineCoding()) {
- USB_StatusInStage(); /* send Acknowledge */
- goto out_class_ok;
- }
- break;
- }
- }
-#endif /* USB_CDC */
- goto stall_i;
- /* end case REQUEST_TO_INTERFACE */
-
- case REQUEST_TO_ENDPOINT:
-#if USB_AUDIO
- switch (SetupPacket.bRequest) {
- case AUDIO_REQUEST_SET_CUR:
-// case AUDIO_REQUEST_SET_MIN:
-// case AUDIO_REQUEST_SET_MAX:
-// case AUDIO_REQUEST_SET_RES:
- if (ADC_EP_SetRequest()) {
- USB_StatusInStage(); /* send Acknowledge */
- goto out_class_ok;
- }
- break;
- }
-#endif /* USB_AUDIO */
- goto stall_i;
- /* end case REQUEST_TO_ENDPOINT */
-
- default:
- goto stall_i;
- }
-out_class_ok: /* request finished successfully */
- break; /* end case REQUEST_CLASS */
-#endif /* USB_CLASS */
-
-#if USB_VENDOR
- case REQUEST_VENDOR:
- switch (SetupPacket.bmRequestType.BM.Recipient) {
-
- case REQUEST_TO_DEVICE:
- if (!USB_ReqVendorDev(FALSE)) {
- goto stall_i; /* not supported */
- }
- break;
-
- case REQUEST_TO_INTERFACE:
- if (!USB_ReqVendorIF(FALSE)) {
- goto stall_i; /* not supported */
- }
- break;
-
- case REQUEST_TO_ENDPOINT:
- if (!USB_ReqVendorEP(FALSE)) {
- goto stall_i; /* not supported */
- }
- break;
-
- default:
- goto stall_i;
- }
-
- USB_StatusInStage();
-
- break; /* end case REQUEST_VENDOR */
-#endif /* USB_VENDOR */
-
- default:
- goto stall_i;
- }
- }
- }
- } else {
- USB_StatusOutStage(); /* receive Acknowledge */
- }
- break; /* end case USB_EVT_OUT */
-
- case USB_EVT_IN :
- if (SetupPacket.bmRequestType.BM.Dir == REQUEST_DEVICE_TO_HOST) {
- USB_DataInStage(); /* send data */
- } else {
- if (USB_DeviceAddress & 0x80) {
- USB_DeviceAddress &= 0x7F;
- USB_SetAddress(USB_DeviceAddress);
- }
- }
- break; /* end case USB_EVT_IN */
-
- case USB_EVT_OUT_STALL:
- USB_ClrStallEP(0x00);
- break;
-
- case USB_EVT_IN_STALL:
- USB_ClrStallEP(0x80);
- break;
-
- }
-}
+++ /dev/null
-/*----------------------------------------------------------------------------
- * U S B - K e r n e l
- *----------------------------------------------------------------------------
- * Name: usbdesc.c
- * Purpose: USB Descriptors
- * Version: V1.20
- *----------------------------------------------------------------------------
- * This software is supplied "AS IS" without any warranties, express,
- * implied or statutory, including but not limited to the implied
- * warranties of fitness for purpose, satisfactory quality and
- * noninfringement. Keil extends you a royalty-free right to reproduce
- * and distribute executable files created using this software for use
- * on NXP Semiconductors LPC microcontroller devices only. Nothing else
- * gives you the right to use this software.
- *
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
- *----------------------------------------------------------------------------
- * History:
- * V1.20 Changed string descriptor handling
- * V1.00 Initial Version
- *----------------------------------------------------------------------------*/
-#include "lpc18xx.H"
-#include "lpc_types.h"
-
-#include "usb.h"
-#include "cdc.h"
-#include "usbcfg.h"
-#include "usbdesc.h"
-
-
-/* USB Standard Device Descriptor */
-const uint8_t USB_DeviceDescriptor[] = {
- USB_DEVICE_DESC_SIZE, /* bLength */
- USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */
- WBVAL(0x0200), /* 2.0 */ /* bcdUSB */
- USB_DEVICE_CLASS_COMMUNICATIONS, /* bDeviceClass CDC*/
- 0x00, /* bDeviceSubClass */
- 0x00, /* bDeviceProtocol */
- USB_MAX_PACKET0, /* bMaxPacketSize0 */
- WBVAL(0x1FC9), /* idVendor */
- WBVAL(0x2002), /* idProduct */
- WBVAL(0x0100), /* 1.00 */ /* bcdDevice */
- 0x01, /* iManufacturer */
- 0x02, /* iProduct */
- 0x03, /* iSerialNumber */
- 0x01 /* bNumConfigurations: one possible configuration*/
-};
-
-/* USB FSConfiguration Descriptor */
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-const uint8_t USB_FSConfigDescriptor[] = {
-/* Configuration 1 */
- USB_CONFIGUARTION_DESC_SIZE, /* bLength */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
- WBVAL(( /* wTotalLength */
- 1*USB_CONFIGUARTION_DESC_SIZE +
- 1*USB_INTERFACE_DESC_SIZE + /* communication interface */
- 0x0013 + /* CDC functions */
- 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */
- 1*USB_INTERFACE_DESC_SIZE + /* data interface */
- 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */
- )),
- 0x02, /* bNumInterfaces */
- 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */
- 0x00, /* iConfiguration: no string to describe this configuration */
- USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */
-/*USB_CONFIG_REMOTE_WAKEUP*/,
- USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */
-/* Interface 0, Alternate Setting 0, Communication class interface descriptor */
- USB_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoint used */
- CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */
- CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */
- 0x00, /* bInterfaceProtocol: no protocol used */
- 0x5E, /* iInterface: */
-/*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */
- WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */
-/*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */
- 0x01, /* bmCapabilities: device handles call management */
- 0x01, /* bDataInterface: CDC data IF ID */
-/*Abstract Control Management Functional Descriptor*/
- 0x04, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */
-/*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_UNION, /* bDescriptorSubtype: Union func desc */
- USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */
- USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */
-/*Endpoint 1 Descriptor*/ /* event notification (optional) */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_IN(1), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
- WBVAL(0x0010), /* wMaxPacketSize */
- 0x02, /* 2ms */ /* bInterval */
-/* Interface 1, Alternate Setting 0, Data class interface descriptor*/
- USB_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: no alternate setting */
- 0x02, /* bNumEndpoints: two endpoints used */
- CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */
- 0x00, /* bInterfaceSubClass: no subclass available */
- 0x00, /* bInterfaceProtocol: no protocol used */
- 0x5E, /* iInterface: */
-/* Endpoint, EP2 Bulk Out */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_OUT(2), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
- 0x00, /* bInterval: ignore for Bulk transfer */
-/* Endpoint, EP2 Bulk In */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_IN(2), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
- 0x00, /* bInterval: ignore for Bulk transfer */
-/* Terminator */
- 0 /* bLength */
- /* bLength */
-};
-
-/* USB HSConfiguration Descriptor */
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-const uint8_t USB_HSConfigDescriptor[] = {
-/* Configuration 1 */
- USB_CONFIGUARTION_DESC_SIZE, /* bLength */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
- WBVAL(( /* wTotalLength */
- 1*USB_CONFIGUARTION_DESC_SIZE +
- 1*USB_INTERFACE_DESC_SIZE + /* communication interface */
- 0x0013 + /* CDC functions */
- 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */
- 1*USB_INTERFACE_DESC_SIZE + /* data interface */
- 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */
- )),
- 0x02, /* bNumInterfaces */
- 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */
- 0x00, /* iConfiguration: no string to describe this configuration */
- USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */
-/*USB_CONFIG_REMOTE_WAKEUP*/,
- USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */
-/* Interface 0, Alternate Setting 0, Communication class interface descriptor */
- USB_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoint used */
- CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */
- CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */
- 0x00, /* bInterfaceProtocol: no protocol used */
- 0x5E, /* iInterface: */
-/*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */
- WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */
-/*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */
- 0x01, /* bmCapabilities: device handles call management */
- 0x01, /* bDataInterface: CDC data IF ID */
-/*Abstract Control Management Functional Descriptor*/
- 0x04, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */
-/*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_UNION, /* bDescriptorSubtype: Union func desc */
- USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */
- USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */
-/*Endpoint 1 Descriptor*/ /* event notification (optional) */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_IN(1), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
- WBVAL(0x0010), /* wMaxPacketSize */
- 0x02, /* 2ms */ /* bInterval */
-/* Interface 1, Alternate Setting 0, Data class interface descriptor*/
- USB_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: no alternate setting */
- 0x02, /* bNumEndpoints: two endpoints used */
- CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */
- 0x00, /* bInterfaceSubClass: no subclass available */
- 0x00, /* bInterfaceProtocol: no protocol used */
- 0x5E, /* iInterface: */
-/* Endpoint, EP2 Bulk Out */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_OUT(2), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
- 0x00, /* bInterval: ignore for Bulk transfer */
-/* Endpoint, EP2 Bulk In */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_IN(2), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
- 0x00, /* bInterval: ignore for Bulk transfer */
-/* Terminator */
- 0 /* bLength */
- /* bLength */
-};
-
-/* USB String Descriptor (optional) */
-const uint8_t USB_StringDescriptor[] = {
-/* Index 0x00: LANGID Codes */
- 0x04, /* bLength */
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
- WBVAL(0x0409), /* US English */ /* wLANGID */
-/* Index 0x01: Manufacturer */
- (16*2 + 2), /* bLength (13 Char + Type + lenght) */
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
- 'N',0,
- 'G',0,
- 'X',0,
- ' ',0,
- 'T',0,
- 'E',0,
- 'C',0,
- 'H',0,
- 'N',0,
- 'O',0,
- 'L',0,
- 'O',0,
- 'G',0,\r
- 'I',0,\r
- 'E',0,\r
- 'S',0,
-/* Index 0x02: Product */
- (17*2 + 2), /* bLength ( 17 Char + Type + lenght) */
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
- 'N',0,
- 'G',0,
- 'X',0,
- ' ',0,
- 'L',0,
- 'P',0,
- 'C',0,
- '1',0,
- '8',0,
- 'x',0,
- 'x',0,
- ' ',0,
- 'V',0,
- 'C',0,
- 'O',0,
- 'M',0,
- ' ',0,
-/* Index 0x03: Serial Number */
- (12*2 + 2), /* bLength (12 Char + Type + lenght) */
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
- 'D',0,
- 'E',0,
- 'M',0,
- 'O',0,
- '0',0,
- '0',0,
- '0',0,
- '0',0,
- '0',0,
- '0',0,
- '0',0,
- '0',0,
-/* Index 0x04: Interface 0, Alternate Setting 0 */
- ( 4*2 + 2), /* bLength (4 Char + Type + lenght) */
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
- 'V',0,
- 'C',0,
- 'O',0,
- 'M',0,
-};
-
-/* USB Device Qualifier */
-const uint8_t USB_DeviceQualifier[] = {
- USB_DEVICE_QUALI_SIZE, /* bLength */
- USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE, /* bDescriptorType */
- WBVAL(0x0200), /* 2.00 */ /* bcdUSB */
- 0x00, /* bDeviceClass */
- 0x00, /* bDeviceSubClass */
- 0x00, /* bDeviceProtocol */
- USB_MAX_PACKET0, /* bMaxPacketSize0 */
- 0x01, /* bNumOtherSpeedConfigurations */
- 0x00 /* bReserved */
-};
-
-/* USB Configuration Descriptor */
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-const uint8_t USB_FSOtherSpeedConfiguration[] = {
-/* Configuration 1 */
- USB_CONFIGUARTION_DESC_SIZE, /* bLength */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
- WBVAL(( /* wTotalLength */
- 1*USB_CONFIGUARTION_DESC_SIZE +
- 1*USB_INTERFACE_DESC_SIZE + /* communication interface */
- 0x0013 + /* CDC functions */
- 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */
- 1*USB_INTERFACE_DESC_SIZE + /* data interface */
- 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */
- )),
- 0x02, /* bNumInterfaces */
- 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */
- 0x00, /* iConfiguration: no string to describe this configuration */
- USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */
-/*USB_CONFIG_REMOTE_WAKEUP*/,
- USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */
-/* Interface 0, Alternate Setting 0, Communication class interface descriptor */
- USB_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoint used */
- CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */
- CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */
- 0x00, /* bInterfaceProtocol: no protocol used */
- 0x5E, /* iInterface: */
-/*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */
- WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */
-/*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */
- 0x01, /* bmCapabilities: device handles call management */
- 0x01, /* bDataInterface: CDC data IF ID */
-/*Abstract Control Management Functional Descriptor*/
- 0x04, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */
-/*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_UNION, /* bDescriptorSubtype: Union func desc */
- USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */
- USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */
-/*Endpoint 1 Descriptor*/ /* event notification (optional) */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_IN(1), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
- WBVAL(0x0010), /* wMaxPacketSize */
- 0x02, /* 2ms */ /* bInterval */
-/* Interface 1, Alternate Setting 0, Data class interface descriptor*/
- USB_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: no alternate setting */
- 0x02, /* bNumEndpoints: two endpoints used */
- CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */
- 0x00, /* bInterfaceSubClass: no subclass available */
- 0x00, /* bInterfaceProtocol: no protocol used */
- 0x5E, /* iInterface: */
-/* Endpoint, EP2 Bulk Out */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_OUT(2), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
- 0x00, /* bInterval: ignore for Bulk transfer */
-/* Endpoint, EP2 Bulk In */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_IN(2), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
- 0x00, /* bInterval: ignore for Bulk transfer */
-/* Terminator */
- 0 /* bLength */
-};
-
-/* USB Configuration Descriptor */
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-const uint8_t USB_HSOtherSpeedConfiguration[] = {
-/* Configuration 1 */
- USB_CONFIGUARTION_DESC_SIZE, /* bLength */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
- WBVAL(( /* wTotalLength */
- 1*USB_CONFIGUARTION_DESC_SIZE +
- 1*USB_INTERFACE_DESC_SIZE + /* communication interface */
- 0x0013 + /* CDC functions */
- 1*USB_ENDPOINT_DESC_SIZE + /* interrupt endpoint */
- 1*USB_INTERFACE_DESC_SIZE + /* data interface */
- 2*USB_ENDPOINT_DESC_SIZE /* bulk endpoints */
- )),
- 0x02, /* bNumInterfaces */
- 0x01, /* bConfigurationValue: 0x01 is used to select this configuration */
- 0x00, /* iConfiguration: no string to describe this configuration */
- USB_CONFIG_BUS_POWERED /*|*/ /* bmAttributes */
-/*USB_CONFIG_REMOTE_WAKEUP*/,
- USB_CONFIG_POWER_MA(100), /* bMaxPower, device power consumption is 100 mA */
-/* Interface 0, Alternate Setting 0, Communication class interface descriptor */
- USB_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_CDC_CIF_NUM, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoint used */
- CDC_COMMUNICATION_INTERFACE_CLASS, /* bInterfaceClass: Communication Interface Class */
- CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass: Abstract Control Model */
- 0x00, /* bInterfaceProtocol: no protocol used */
- 0x5E, /* iInterface: */
-/*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_HEADER, /* bDescriptorSubtype: Header Func Desc */
- WBVAL(CDC_V1_10), /* 1.10 */ /* bcdCDC */
-/*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_CALL_MANAGEMENT, /* bDescriptorSubtype: Call Management Func Desc */
- 0x01, /* bmCapabilities: device handles call management */
- 0x01, /* bDataInterface: CDC data IF ID */
-/*Abstract Control Management Functional Descriptor*/
- 0x04, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities: SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported */
-/*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */
- CDC_UNION, /* bDescriptorSubtype: Union func desc */
- USB_CDC_CIF_NUM, /* bMasterInterface: Communication class interface is master */
- USB_CDC_DIF_NUM, /* bSlaveInterface0: Data class interface is slave 0 */
-/*Endpoint 1 Descriptor*/ /* event notification (optional) */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_IN(1), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
- WBVAL(0x0010), /* wMaxPacketSize */
- 0x02, /* 2ms */ /* bInterval */
-/* Interface 1, Alternate Setting 0, Data class interface descriptor*/
- USB_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_CDC_DIF_NUM, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: no alternate setting */
- 0x02, /* bNumEndpoints: two endpoints used */
- CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass: Data Interface Class */
- 0x00, /* bInterfaceSubClass: no subclass available */
- 0x00, /* bInterfaceProtocol: no protocol used */
- 0x5E, /* iInterface: */
-/* Endpoint, EP2 Bulk Out */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_OUT(2), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
- 0x00, /* bInterval: ignore for Bulk transfer */
-/* Endpoint, EP2 Bulk In */
- USB_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- USB_ENDPOINT_IN(2), /* bEndpointAddress */
- USB_ENDPOINT_TYPE_BULK, /* bmAttributes */
- WBVAL(USB_CDC_BUFSIZE), /* wMaxPacketSize */
- 0x00, /* bInterval: ignore for Bulk transfer */
-/* Terminator */
- 0 /* bLength */
-};
+++ /dev/null
-/**********************************************************************
-* $Id$ usbhw.c 2011-06-02
-*//**
-* @file usbhw.c
-* @brief USB Hardware Layer Module for NXP's lpc43xx MCU
-* @version 1.0
-* @date 02. June. 2011
-* @author NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-#include <string.h>
-#include "lpc18xx.H" /* lpc43xx definitions */
-#include "lpc_types.h"
-#include "usb.h"
-#include "usbhw.h"
-#include "usbcfg.h"
-#include "usbcore.h"
-#include "lpc18xx_scu.h"
-#include "lpc18xx_cgu.h"
-#include "FreeRTOS.h"
-#ifdef __CC_ARM
-#pragma diag_suppress 1441
-#endif
-
-#ifdef __ICCARM__
-#pragma data_alignment=2048
-DQH_T ep_QH[EP_NUM_MAX];
-#pragma data_alignment=32
-DTD_T ep_TD[EP_NUM_MAX];
-#pragma data_alignment=4
-#elif defined ( __GNUC__ )
-#define __align(x) __attribute__((aligned(x)))
-DQH_T ep_QH[EP_NUM_MAX] __attribute__((aligned(2048)));
-DTD_T ep_TD[EP_NUM_MAX] __attribute__((aligned(32)));
-#else
-DQH_T __align(2048) ep_QH[EP_NUM_MAX];
-DTD_T __align(32) ep_TD[EP_NUM_MAX];
-#endif
-
-
-static uint32_t ep_read_len[4];
-volatile uint32_t DevStatusFS2HS = FALSE;
-LPC_USBDRV_INIT_T g_drv;
-
-/*
- * Get Endpoint Physical Address
- * Parameters: EPNum: Endpoint Number
- * EPNum.0..3: Address
- * EPNum.7: Dir
- * Return Value: Endpoint Physical Address
- */
-
-uint32_t EPAdr (uint32_t EPNum) {
- uint32_t val;
-
- val = (EPNum & 0x0F) << 1;
- if (EPNum & 0x80) {
- val += 1;
- }
- return (val);
-}
-
-/*
- * USB Initialize Function
- * Called by the User to initialize USB
- * Return Value: None
- */
-
-void USB_Init (LPC_USBDRV_INIT_T* cbs)
-{
- memcpy(&g_drv, cbs, sizeof(LPC_USBDRV_INIT_T));
- /*maxp for EP0 should be atleast 8 */
- if( g_drv.ep0_maxp == 0)
- g_drv.ep0_maxp = 64;
-
-#ifdef USE_USB0
- scu_pinmux(0x8,1,MD_PLN_FAST,FUNC1); // 0: motocon pcap0_1 1: usb0 usb0_ind1 2: nc 3: gpio4 gpio4_1
- scu_pinmux(0x8,2,MD_PLN_FAST,FUNC1); // 0: motocon pcap0_0 1: usb0 usb0_ind0 2: nc 3: gpio4 gpio4_2
-#endif
-#ifdef USE_USB0
- CGU_SetPLL0();
- CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE);
- CGU_EntityConnect(CGU_CLKSRC_PLL0, CGU_BASE_USB0);
-#else
- CGU_SetPLL1(5);
- CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
- CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_USB1);\r
- /* enable USB phy */
- LPC_CREG->CREG0 &= ~(1 << 5);
- /* enable USB1_DP and USB1_DN on chip FS phy */
- LPC_SCU->SFSUSB = 0x12;
- /* enable USB1_VBUS */
- scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);
-
-#endif
- /* Turn on the phy */
-#ifdef USE_USB0
- LPC_CREG->CREG0 &= ~(1<<5);
-#endif
- /* reset the controller */
- LPC_USB->USBCMD_D = USBCMD_RST;
- /* wait for reset to complete */
- while (LPC_USB->USBCMD_D & USBCMD_RST);
-
- /* Program the controller to be the USB device controller */
- LPC_USB->USBMODE_D = USBMODE_CM_DEV
- | USBMODE_SDIS
- | USBMODE_SLOM ;
-
- /* set OTG transcever in proper state, device is present
- on the port(CCS=1), port enable/disable status change(PES=1). */
-#ifdef USE_USB0
- LPC_USB->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
-#else
- /* force full speed */
- LPC_USB->PORTSC1_D |= (1<<24);
-#endif
-
-#ifdef USE_USB0
- NVIC_EnableIRQ(USB0_IRQn); // enable USB0 interrrupts
- NVIC_SetPriority(USB0_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );
-#else
- NVIC_EnableIRQ(USB1_IRQn); // enable USB1 interrrupts
- NVIC_SetPriority(USB0_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
- USB_Reset();
- USB_SetAddress(0);
- return;
-}
-
-/*
- * USB Connect Function
- * Called by the User to Connect/Disconnect USB
- * Parameters: con: Connect/Disconnect
- * Return Value: None
- */
-void USB_Connect (uint32_t con) {
- if (con)
- LPC_USB->USBCMD_D |= USBCMD_RS;
- else
- LPC_USB->USBCMD_D &= ~USBCMD_RS;
-}
-
-
-/*
- * USB Reset Function
- * Called automatically on USB Reset
- * Return Value: None
- */
-
-void USB_Reset (void)
-{
- uint32_t i;
-
- DevStatusFS2HS = FALSE;
- /* disable all EPs */
- LPC_USB->ENDPTCTRL0 &= ~(EPCTRL_RXE | EPCTRL_TXE);
- LPC_USB->ENDPTCTRL2 &= ~(EPCTRL_RXE | EPCTRL_TXE);
- LPC_USB->ENDPTCTRL3 &= ~(EPCTRL_RXE | EPCTRL_TXE);
-
- /* Clear all pending interrupts */
- LPC_USB->ENDPTNAK = 0xFFFFFFFF;
- LPC_USB->ENDPTNAKEN = 0;
- LPC_USB->USBSTS_D = 0xFFFFFFFF;
- LPC_USB->ENDPTSETUPSTAT = LPC_USB->ENDPTSETUPSTAT;
- LPC_USB->ENDPTCOMPLETE = LPC_USB->ENDPTCOMPLETE;
- while (LPC_USB->ENDPTPRIME) /* Wait until all bits are 0 */
- {
- }
- LPC_USB->ENDPTFLUSH = 0xFFFFFFFF;
- while (LPC_USB->ENDPTFLUSH); /* Wait until all bits are 0 */
-
-
- /* Set the interrupt Threshold control interval to 0 */
- LPC_USB->USBCMD_D &= ~0x00FF0000;
-
- /* Zero out the Endpoint queue heads */
- memset((void*)ep_QH, 0, EP_NUM_MAX * sizeof(DQH_T));
- /* Zero out the device transfer descriptors */
- memset((void*)ep_TD, 0, EP_NUM_MAX * sizeof(DTD_T));
- memset((void*)ep_read_len, 0, sizeof(ep_read_len));
- /* Configure the Endpoint List Address */
- /* make sure it in on 64 byte boundary !!! */
- /* init list address */
- LPC_USB->ENDPOINTLISTADDR = (uint32_t)ep_QH;
- /* Initialize device queue heads for non ISO endpoint only */
- for (i = 0; i < EP_NUM_MAX; i++)
- {
- ep_QH[i].next_dTD = (uint32_t)&ep_TD[i];
- }
- /* Enable interrupts */
- LPC_USB->USBINTR_D = USBSTS_UI
- | USBSTS_UEI
- | USBSTS_PCI
- | USBSTS_URI
- | USBSTS_SLI
- | USBSTS_NAKI;
-// LPC_USB->usbintr |= (0x1<<7); /* Test SOF */
- /* enable ep0 IN and ep0 OUT */
- ep_QH[0].cap = QH_MAXP(g_drv.ep0_maxp)
- | QH_IOS
- | QH_ZLT;
- ep_QH[1].cap = QH_MAXP(g_drv.ep0_maxp)
- | QH_IOS
- | QH_ZLT;
- /* enable EP0 */
- LPC_USB->ENDPTCTRL0 = EPCTRL_RXE | EPCTRL_RXR | EPCTRL_TXE | EPCTRL_TXR;
- return;
-
-}
-
-
-/*
- * USB Suspend Function
- * Called automatically on USB Suspend
- * Return Value: None
- */
-
-void USB_Suspend (void) {
- /* Performed by Hardware */
-}
-
-
-/*
- * USB Resume Function
- * Called automatically on USB Resume
- * Return Value: None
- */
-
-void USB_Resume (void) {
- /* Performed by Hardware */
-}
-
-
-/*
- * USB Remote Wakeup Function
- * Called automatically on USB Remote Wakeup
- * Return Value: None
- */
-
-void USB_WakeUp (void) {
-
- //if (USB_DeviceStatus & USB_GETSTATUS_REMOTE_WAKEUP)
- {
- /* Set FPR bit in PORTSCX reg p63 */
- LPC_USB->PORTSC1_D |= USBPRTS_FPR ;
- }
-}
-
-
-/*
- * USB Remote Wakeup Configuration Function
- * Parameters: cfg: Enable/Disable
- * Return Value: None
- */
-
-void USB_WakeUpCfg (uint32_t cfg) {
- ( void ) cfg;
- /* Not needed */
-}
-
-
-/*
- * USB Set Address Function
- * Parameters: adr: USB Address
- * Return Value: None
- */
-
-void USB_SetAddress (uint32_t adr) {
- LPC_USB->DEVICEADDR = USBDEV_ADDR(adr);
- LPC_USB->DEVICEADDR |= USBDEV_ADDR_AD;
-}
-
-/*
-* USB set test mode Function
-* Parameters: mode: test mode
-* Return Value: TRUE if supported else FALSE
-*/
-
-uint32_t USB_SetTestMode(uint8_t mode)
-{
- uint32_t portsc;
-
- if ((mode > 0) && (mode < 8))
- {
- portsc = LPC_USB->PORTSC1_D & ~(0xF << 16);
-
- LPC_USB->PORTSC1_D = portsc | (mode << 16);
- return TRUE;
- }
- return (FALSE);
-}
-
-/*
- * USB Configure Function
- * Parameters: cfg: Configure/Deconfigure
- * Return Value: None
- */
-
-void USB_Configure (uint32_t cfg) {
- ( void ) cfg;
-}
-
-
-/*
- * Configure USB Endpoint according to Descriptor
- * Parameters: pEPD: Pointer to Endpoint Descriptor
- * Return Value: None
- */
-
-void USB_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) {
- uint32_t num, lep;
- uint32_t ep_cfg;
- uint8_t bmAttributes;
-
- lep = pEPD->bEndpointAddress & 0x7F;
- num = EPAdr(pEPD->bEndpointAddress);
-
- ep_cfg = ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep];
- /* mask the attributes we are not-intersetd in */
- bmAttributes = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK;
- /* set EP type */
- if (bmAttributes != USB_ENDPOINT_TYPE_ISOCHRONOUS)
- {
- /* init EP capabilities */
- ep_QH[num].cap = QH_MAXP(pEPD->wMaxPacketSize)
- | QH_IOS | QH_ZLT ;
- /* The next DTD pointer is INVALID */
- ep_TD[num].next_dTD = 0x01 ;
- }
- else
- {
- /* init EP capabilities */
- ep_QH[num].cap = QH_MAXP(0x400) | QH_ZLT;
- }
- /* setup EP control register */
- if (pEPD->bEndpointAddress & 0x80)
- {
- ep_cfg &= ~0xFFFF0000;
- ep_cfg |= EPCTRL_TX_TYPE(bmAttributes)
- | EPCTRL_TXR;
- }
- else
- {
- ep_cfg &= ~0xFFFF;
- ep_cfg |= EPCTRL_RX_TYPE(bmAttributes)
- | EPCTRL_RXR;
- }
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] = ep_cfg;
- return;
-}
-
-/*
- * Set Direction for USB Control Endpoint
- * Parameters: dir: Out (dir == 0), In (dir <> 0)
- * Return Value: None
- */
-
-void USB_DirCtrlEP (uint32_t dir) {
- /* Not needed */
- ( void ) dir;
-}
-
-
-/*
- * Enable USB Endpoint
- * Parameters: EPNum: Endpoint Number
- * EPNum.0..3: Address
- * EPNum.7: Dir
- * Return Value: None
- */
-
-void USB_EnableEP (uint32_t EPNum) {
- uint32_t lep, bitpos;
-
- lep = EPNum & 0x0F;
-
- if (EPNum & 0x80)
- {
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXE;
- }
- else
- {
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXE;
- /* enable NAK interrupt */
- bitpos = USB_EP_BITPOS(EPNum);
- LPC_USB->ENDPTNAKEN |= (1<<bitpos);
- }
-}
-
-/*
- * Disable USB Endpoint
- * Parameters: EPNum: Endpoint Number
- * EPNum.0..3: Address
- * EPNum.7: Dir
- * Return Value: None
- */
-
-void USB_DisableEP (uint32_t EPNum) {
- uint32_t lep, bitpos;
-
- lep = EPNum & 0x0F;
- if (EPNum & 0x80)
- {
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] &= ~EPCTRL_TXE;
- }
- else
- {
- /* disable NAK interrupt */
- bitpos = USB_EP_BITPOS(EPNum);
- LPC_USB->ENDPTNAKEN &= ~(1<<bitpos);
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] &= ~EPCTRL_RXE;
- }
-}
-
-/*
- * Reset USB Endpoint
- * Parameters: EPNum: Endpoint Number
- * EPNum.0..3: Address
- * EPNum.7: Dir
- * Return Value: None
- */
-
-void USB_ResetEP (uint32_t EPNum) {
- uint32_t bit_pos = USB_EP_BITPOS(EPNum);
- uint32_t lep = EPNum & 0x0F;
-
- /* flush EP buffers */
- LPC_USB->ENDPTFLUSH = (1<<bit_pos);
- while (LPC_USB->ENDPTFLUSH & (1<<bit_pos));
- /* reset data toggles */
- if (EPNum & 0x80)
- {
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXR;
- }
- else
- {
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXR;
- }
-}
-
-/*
- * Set Stall for USB Endpoint
- * Parameters: EPNum: Endpoint Number
- * EPNum.0..3: Address
- * EPNum.7: Dir
- * Return Value: None
- */
-
-void USB_SetStallEP (uint32_t EPNum) {
- uint32_t lep;
-
- lep = EPNum & 0x0F;
- if (EPNum & 0x80)
- {
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXS;
- }
- else
- {
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXS;
- }
-}
-
-/*
- * Clear Stall for USB Endpoint
- * Parameters: EPNum: Endpoint Number
- * EPNum.0..3: Address
- * EPNum.7: Dir
- * Return Value: None
- */
-
-void USB_ClrStallEP (uint32_t EPNum) {
- uint32_t lep;
-
- lep = EPNum & 0x0F;
- if (EPNum & 0x80)
- {
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] &= ~EPCTRL_TXS;
- /* reset data toggle */
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_TXR;
- }
- else
- {
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] &= ~EPCTRL_RXS;
- /* reset data toggle */
- ((uint32_t*)&(LPC_USB->ENDPTCTRL0))[lep] |= EPCTRL_RXR;
- }
-}
-
-/*
- * Process DTD
- * Parameters: EPNum: Endpoint Number
- * EPNum.0..3: Address
- * EPNum.7: Dir
- * Buffer pointer
- * Transfer buffer size
- * Return Value: None
- */
-void USB_ProgDTD(uint32_t Edpt, uint32_t ptrBuff, uint32_t TsfSize)
-{
- DTD_T* pDTD;
-
- pDTD = (DTD_T*)&ep_TD[ Edpt ];
-
- /* Zero out the device transfer descriptors */
- memset((void*)pDTD, 0, sizeof(DTD_T));
- /* The next DTD pointer is INVALID */
- pDTD->next_dTD = 0x01 ;
-
- /* Length */
- pDTD->total_bytes = ((TsfSize & 0x7fff) << 16);
- pDTD->total_bytes |= TD_IOC ;
- pDTD->total_bytes |= 0x80 ;
-
- pDTD->buffer0 = ptrBuff;
- pDTD->buffer1 = (ptrBuff + 0x1000) & 0xfffff000;
- pDTD->buffer2 = (ptrBuff + 0x2000) & 0xfffff000;
- pDTD->buffer3 = (ptrBuff + 0x3000) & 0xfffff000;
- pDTD->buffer4 = (ptrBuff + 0x4000) & 0xfffff000;
-
- ep_QH[Edpt].next_dTD = (uint32_t)(&ep_TD[ Edpt ]);
- ep_QH[Edpt].total_bytes &= (~0xC0) ;
-}
-
-/*
-* Read USB Endpoint Data
-* Parameters: EPNum: Endpoint Number
-* EPNum.0..3: Address
-* EPNum.7: Dir
-* pData: Pointer to Data Buffer
-* Return Value: Number of bytes read
-*/
-uint32_t USB_ReadSetupPkt(uint32_t EPNum, uint32_t *pData)
-{
- uint32_t setup_int, cnt = 0;
- uint32_t num = EPAdr(EPNum);
-
- setup_int = LPC_USB->ENDPTSETUPSTAT ;
- /* Clear the setup interrupt */
- LPC_USB->ENDPTSETUPSTAT = setup_int;
-
- /* ********************************** */
- /* Check if we have received a setup */
- /* ********************************** */
- if (setup_int & (1<<0)) /* Check only for bit 0 */
- /* No setup are admitted on other endpoints than 0 */
- {
- do
- {
- /* Setup in a setup - must considere only the second setup */
- /*- Set the tripwire */
- LPC_USB->USBCMD_D |= USBCMD_SUTW ;
-
- /* Transfer Set-up data to the gtmudsCore_Request buffer */
- pData[0] = ep_QH[num].setup[0];
- pData[1] = ep_QH[num].setup[1];
- cnt = 8;
-
- }
- while (!(LPC_USB->USBCMD_D & USBCMD_SUTW)) ;
-
- /* setup in a setup - Clear the tripwire */
- LPC_USB->USBCMD_D &= (~USBCMD_SUTW);
- }
- while ((setup_int = LPC_USB->ENDPTSETUPSTAT) != 0)
- {
- /* Clear the setup interrupt */
- LPC_USB->ENDPTSETUPSTAT = setup_int;
- }
- return cnt;
-}
-
-/*
-* Enque read request
-* Parameters: EPNum: Endpoint Number
-* EPNum.0..3: Address
-* EPNum.7: Dir
-* pData: Pointer to Data Buffer
-* Return Value: Number of bytes read
-*/
-
-uint32_t USB_ReadReqEP(uint32_t EPNum, uint8_t *pData, uint32_t len)
-{
- uint32_t num = EPAdr(EPNum);
- uint32_t n = USB_EP_BITPOS(EPNum);
-
- USB_ProgDTD(num, (uint32_t)pData, len);
- ep_read_len[EPNum & 0x0F] = len;
- /* prime the endpoint for read */
- LPC_USB->ENDPTPRIME |= (1<<n);
- return len;
-}
-/*
-* Read USB Endpoint Data
-* Parameters: EPNum: Endpoint Number
-* EPNum.0..3: Address
-* EPNum.7: Dir
-* pData: Pointer to Data Buffer
-* Return Value: Number of bytes read
-*/
-
-uint32_t USB_ReadEP(uint32_t EPNum, uint8_t *pData)
-{
- uint32_t cnt, n;
- DTD_T* pDTD ;
-
- ( void ) pData;
-
- n = EPAdr(EPNum);
- pDTD = (DTD_T*)&ep_TD[n];
-
- /* return the total bytes read */
- cnt = (pDTD->total_bytes >> 16) & 0x7FFF;
- cnt = ep_read_len[EPNum & 0x0F] - cnt;
- return (cnt);
-}
-
-/*
-* Write USB Endpoint Data
-* Parameters: EPNum: Endpoint Number
-* EPNum.0..3: Address
-* EPNum.7: Dir
-* pData: Pointer to Data Buffer
-* cnt: Number of bytes to write
-* Return Value: Number of bytes written
-*/
-uint32_t USB_WriteEP(uint32_t EPNum, uint8_t *pData, uint32_t cnt)
-{
- uint32_t x = 0, n = USB_EP_BITPOS(EPNum);
-
- USB_ProgDTD(EPAdr(EPNum), (uint32_t)pData, cnt);
- /* prime the endpoint for transmit */
- LPC_USB->ENDPTPRIME |= (1<<n);
- /* check if priming succeeded */
- while ((LPC_USB->ENDPTPRIME & (1<<n))&&(++x<0xffff));/*_RB_ Fix for hang here. */
- return (cnt);
-}
-
-/*
- * USB Interrupt Service Routine
- */
-#ifdef USE_USB0
-void USB0_IRQHandler (void)
-#else
-void USB1_IRQHandler (void)
-#endif
-{
- uint32_t disr, val, n;
-
- disr = LPC_USB->USBSTS_D; /* Device Interrupt Status */
- LPC_USB->USBSTS_D = disr;
-
-// printf("USB interrupt: 0x%08x\n",disr);
-
-// LPC_UART1->THR = 'U';
-// LPC_UART1->THR = 'S';
-// LPC_UART1->THR = 'B';
-// LPC_UART1->THR = '\n';
-
-
- /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */
- if (disr & USBSTS_URI) /* Reset */
- {
-// LPC_UART1->THR = 'R';
-// LPC_UART1->THR = '\n';
- USB_Reset();
- if (g_drv.USB_Reset_Event)
- g_drv.USB_Reset_Event();
- return;
- //goto isr_end;
- }
-
- if (disr & USBSTS_SLI) /* Suspend */
- {
-// LPC_UART1->THR = 'U';
-// LPC_UART1->THR = '\n';
- if (g_drv.USB_Suspend_Event)
- g_drv.USB_Suspend_Event();
- }
-
- if (disr & USBSTS_PCI) /* Resume */
- {
-// LPC_UART1->THR = 'P';
-// LPC_UART1->THR = '\n';
- /* check if device isoperating in HS mode or full speed */
- if (LPC_USB->PORTSC1_D & (1<<9))
- DevStatusFS2HS = TRUE;
-
- if (g_drv.USB_Resume_Event)
- g_drv.USB_Resume_Event();
- }
-
- /* handle setup status interrupts */
- val = LPC_USB->ENDPTSETUPSTAT;
- /* Only EP0 will have setup packets so call EP0 handler */
- if (val)
- {
-// LPC_UART1->THR = 'S';
-// LPC_UART1->THR = '\n';
- /* Clear the endpoint complete CTRL OUT & IN when */
- /* a Setup is received */
- LPC_USB->ENDPTCOMPLETE = 0x00010001;
- /* enable NAK inetrrupts */
- LPC_USB->ENDPTNAKEN |= 0x00010001;
- if (g_drv.USB_P_EP[0]){
-// LPC_UART1->THR = 's';
-// LPC_UART1->THR = '\n';
- g_drv.USB_P_EP[0](USB_EVT_SETUP);
- }
- }
-
- /* handle completion interrupts */
- val = LPC_USB->ENDPTCOMPLETE;
- if (val)
- {
-// LPC_UART1->THR = 'C';
-// LPC_UART1->THR = '\n';
-
- LPC_USB->ENDPTNAK = val;
- for (n = 0; n < EP_NUM_MAX / 2; n++)
- {
- if (val & (1<<n))
- {
- if (g_drv.USB_P_EP[n])
- g_drv.USB_P_EP[n](USB_EVT_OUT);
-
- LPC_USB->ENDPTCOMPLETE = (1<<n);
- }
- if (val & (1<<(n + 16)))
- {
- ep_TD [(n << 1) + 1 ].total_bytes &= 0xC0;
- if (g_drv.USB_P_EP[n])
- g_drv.USB_P_EP[n](USB_EVT_IN);
- LPC_USB->ENDPTCOMPLETE = (1<<(n + 16));
- }
- }
- }
-
- if (disr & USBSTS_NAKI)
- {
-// LPC_UART1->THR = 'N';
-// LPC_UART1->THR = '\n';
- val = LPC_USB->ENDPTNAK;
- val &= LPC_USB->ENDPTNAKEN;
- /* handle NAK interrupts */
- if (val)
- {
- for (n = 0; n < EP_NUM_MAX / 2; n++)
- {
- if (val & (1<<n))
- {
- if (g_drv.USB_P_EP[n])
- g_drv.USB_P_EP[n](USB_EVT_OUT_NAK);
- }
- if (val & (1<<(n + 16)))
- {
- if (g_drv.USB_P_EP[n])
- g_drv.USB_P_EP[n](USB_EVT_IN_NAK);
- }
- }
- LPC_USB->ENDPTNAK = val;
- }
- }
-
- /* Start of Frame Interrupt */
- if (disr & USBSTS_SRI)
- {
-// LPC_UART1->THR = 'F';
-// LPC_UART1->THR = '\n';
- if (g_drv.USB_SOF_Event)
- g_drv.USB_SOF_Event();
- }
-
- /* Error Interrupt */
- if (disr & USBSTS_UEI)
- {
-// LPC_UART1->THR = 'E';
-// LPC_UART1->THR = '\n';
- if (g_drv.USB_Error_Event)
- g_drv.USB_Error_Event(disr);
- }
-
-// LPC_UART1->THR = 'r';
-// LPC_UART1->THR = '\n';
-//isr_end:
-// LPC_VIC->VectAddr = 0; /* Acknowledge Interrupt */
- return;
-}
+++ /dev/null
-/*----------------------------------------------------------------------------
- * U S B - K e r n e l
- *----------------------------------------------------------------------------
- * Name: usbuser.c
- * Purpose: USB Custom User Module
- * Version: V1.20
- *----------------------------------------------------------------------------
- * This software is supplied "AS IS" without any warranties, express,
- * implied or statutory, including but not limited to the implied
- * warranties of fitness for purpose, satisfactory quality and
- * noninfringement. Keil extends you a royalty-free right to reproduce
- * and distribute executable files created using this software for use
- * on NXP Semiconductors LPC family microcontroller devices only. Nothing
- * else gives you the right to use this software.
- *
- * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
- *---------------------------------------------------------------------------*/
-
-#include "lpc18xx.H"
-#include "lpc_types.h"
-
-#include "usb.h"
-#include "usbcfg.h"
-#include "usbhw.h"
-#include "usbcore.h"
-#include "usbuser.h"
-#include "cdcuser.h"
-
-
-
-/*
- * USB Power Event Callback
- * Called automatically on USB Power Event
- * Parameter: power: On(TRUE)/Off(FALSE)
- */
-
-#if USB_POWER_EVENT
-void USB_Power_Event (uint32_t power) {
-}
-#endif
-
-
-/*
- * USB Reset Event Callback
- * Called automatically on USB Reset Event
- */
-
-#if USB_RESET_EVENT
-void USB_Reset_Event (void) {
- USB_ResetCore();
-}
-#endif
-
-
-/*
- * USB Suspend Event Callback
- * Called automatically on USB Suspend Event
- */
-
-#if USB_SUSPEND_EVENT
-void USB_Suspend_Event (void) {
-}
-#endif
-
-
-/*
- * USB Resume Event Callback
- * Called automatically on USB Resume Event
- */
-
-#if USB_RESUME_EVENT
-void USB_Resume_Event (void) {
-}
-#endif
-
-
-/*
- * USB Remote Wakeup Event Callback
- * Called automatically on USB Remote Wakeup Event
- */
-
-#if USB_WAKEUP_EVENT
-void USB_WakeUp_Event (void) {
-}
-#endif
-
-
-/*
- * USB Start of Frame Event Callback
- * Called automatically on USB Start of Frame Event
- */
-
-#if USB_SOF_EVENT
-void USB_SOF_Event (void) {
-}
-#endif
-
-
-/*
- * USB Error Event Callback
- * Called automatically on USB Error Event
- * Parameter: error: Error Code
- */
-
-#if USB_ERROR_EVENT
-void USB_Error_Event (uint32_t error) {
-}
-#endif
-
-
-/*
- * USB Set Configuration Event Callback
- * Called automatically on USB Set Configuration Request
- */
-
-#if USB_CONFIGURE_EVENT
-void USB_Configure_Event (void) {
-
- if (USB_Configuration) { /* Check if USB is configured */
- /* add your code here */
- }
-}
-#endif
-
-
-/*
- * USB Set Interface Event Callback
- * Called automatically on USB Set Interface Request
- */
-
-#if USB_INTERFACE_EVENT
-void USB_Interface_Event (void) {
-}
-#endif
-
-
-/*
- * USB Set/Clear Feature Event Callback
- * Called automatically on USB Set/Clear Feature Request
- */
-
-#if USB_FEATURE_EVENT
-void USB_Feature_Event (void) {
-}
-#endif
-
-
-#define P_EP(n) ((USB_EP_EVENT & (1 << (n))) ? USB_EndPoint##n : NULL)
-
-/* USB Endpoint Events Callback Pointers */
-void (* const USB_P_EP[USB_EP_NUM]) (uint32_t event) = {
- P_EP(0),
- P_EP(1),
- P_EP(2),
- P_EP(3),
-};
-
-
-/*
- * USB Endpoint 1 Event Callback
- * Called automatically on USB Endpoint 1 Event
- * Parameter: event
- */
-
-void USB_EndPoint1 (uint32_t event) {
- ( void ) event;
-}
-
-
-/*
- * USB Endpoint 2 Event Callback
- * Called automatically on USB Endpoint 2 Event
- * Parameter: event
- */
-
-void USB_EndPoint2 (uint32_t event) {
- switch (event) {
- case USB_EVT_OUT_NAK:
- CDC_BulkOutNak();
- break;
- case USB_EVT_OUT:
- CDC_BulkOut (); /* data received from Host */
- break;
- case USB_EVT_IN:
- CDC_BulkIn (); /* data expected from Host */
- break;
- }
-}
-
-
-/*
- * USB Endpoint 3 Event Callback
- * Called automatically on USB Endpoint 3 Event
- * Parameter: event
- */
-
-void USB_EndPoint3 (uint32_t event) {
- ( void ) event;
-}
-
-
-/*
- * USB Endpoint 4 Event Callback
- * Called automatically on USB Endpoint 4 Event
- * Parameter: event
- */
-
-void USB_EndPoint4 (uint32_t event) {
- ( void ) event;
-}
-
-
-/*
- * USB Endpoint 5 Event Callback
- * Called automatically on USB Endpoint 5 Event
- * Parameter: event
- */
-
-void USB_EndPoint5 (uint32_t event) {
- ( void ) event;
-}
-//*****************************************************************************\r
+// *****************************************************************************\r
// +--+\r
// | ++----+\r
// +-++ |\r
// | +--+--+\r
// +----+ Copyright (c) 2011-12 Code Red Technologies Ltd.\r
//\r
-// Microcontroller Startup code for use with Red Suite\r
+// LPC43xx Microcontroller Startup code for use with Red Suite\r
//\r
-// Version : 120126\r
+// Version : 120430\r
//\r
// Software License Agreement\r
//\r
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH\r
// CODE RED TECHNOLOGIES LTD.\r
//\r
-//*****************************************************************************\r
-#if defined (__cplusplus)\r
+// *****************************************************************************\r
+\r
+#include "stdint.h"\r
+\r
+#if defined(__cplusplus)\r
#ifdef __REDLIB__\r
#error Redlib does not support C++\r
#else\r
-//*****************************************************************************\r
+// *****************************************************************************\r
//\r
// The entry point for the C++ library startup\r
//\r
-//*****************************************************************************\r
+// *****************************************************************************\r
extern "C" {\r
- extern void __libc_init_array(void);\r
+extern void __libc_init_array(void);\r
+\r
}\r
#endif\r
#endif\r
\r
#define WEAK __attribute__ ((weak))\r
-#define ALIAS(f) __attribute__ ((weak, alias (#f)))\r
+#define ALIAS(f) __attribute__ ((weak, alias(# f)))\r
\r
// Code Red - if CMSIS is being used, then SystemInit() routine\r
// will be called by startup code rather than in application's main()\r
-#if defined (__USE_CMSIS)\r
-#include "LPC18xx.h"\r
-#endif\r
+extern void SystemInit(void);\r
\r
-//*****************************************************************************\r
-#if defined (__cplusplus)\r
+// *****************************************************************************\r
+#if defined(__cplusplus)\r
extern "C" {\r
#endif\r
\r
-#include <stdint.h>\r
-\r
-//*****************************************************************************\r
+// *****************************************************************************\r
//\r
// Forward declaration of the default handlers. These are aliased.\r
// When the application defines a handler (with the same name), this will\r
// automatically take precedence over these weak definitions\r
//\r
-//*****************************************************************************\r
- void ResetISR(void);\r
+// *****************************************************************************\r
+void ResetISR(void);\r
WEAK void NMI_Handler(void);\r
-WEAK void HardFault_Handler(void);// __attribute__((naked));\r
+WEAK void HardFault_Handler(void);\r
WEAK void MemManage_Handler(void);\r
WEAK void BusFault_Handler(void);\r
WEAK void UsageFault_Handler(void);\r
-WEAK void SVCall_Handler(void);\r
+WEAK void SVC_Handler(void);\r
WEAK void DebugMon_Handler(void);\r
WEAK void PendSV_Handler(void);\r
WEAK void SysTick_Handler(void);\r
//\r
//*****************************************************************************\r
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void MX_CORE_IRQHandler(void) ALIAS(IntDefaultHandler);\r
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLASHEEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);\r
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);\r
void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);\r
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);\r
void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SPI_IRQHandler (void) ALIAS(IntDefaultHandler);\r
void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);\r
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);\r
// The vector table.\r
// This relies on the linker script to place at correct location in memory.\r
//\r
-//*****************************************************************************\r
-extern void (* const g_pfnVectors[])(void);\r
+// *****************************************************************************\r
+extern void(*const g_pfnVectors[]) (void);\r
__attribute__ ((section(".isr_vector")))\r
-void (* const g_pfnVectors[])(void) = {\r
- // Core Level - CM3\r
- &_vStackTop, // The initial stack pointer\r
- ResetISR, // The reset handler\r
- NMI_Handler, // The NMI handler\r
- HardFault_Handler, // The hard fault handler\r
- MemManage_Handler, // The MPU fault handler\r
- BusFault_Handler, // The bus fault handler\r
- UsageFault_Handler, // The usage fault handler\r
- 0, // Reserved\r
- 0, // Reserved\r
- 0, // Reserved\r
- 0, // Reserved\r
- SVCall_Handler, // SVCall handler\r
- DebugMon_Handler, // Debug monitor handler\r
- 0, // Reserved\r
- PendSV_Handler, // The PendSV handler\r
- SysTick_Handler, // The SysTick handler\r
-\r
- // Chip Level - LPC18\r
- DAC_IRQHandler, // 16\r
- 0, // 17\r
- DMA_IRQHandler, // 18\r
- 0, // 19\r
- 0, // 20\r
- ETH_IRQHandler, // 21\r
- SDIO_IRQHandler, // 22\r
- LCD_IRQHandler, // 23\r
- USB0_IRQHandler, // 24\r
- USB1_IRQHandler, // 25\r
- SCT_IRQHandler, // 26\r
- RIT_IRQHandler, // 27\r
- TIMER0_IRQHandler, // 28\r
- TIMER1_IRQHandler, // 29\r
- TIMER2_IRQHandler, // 30\r
- TIMER3_IRQHandler, // 31\r
- MCPWM_IRQHandler, // 32\r
- ADC0_IRQHandler, // 33\r
- I2C0_IRQHandler, // 34\r
- I2C1_IRQHandler, // 35\r
- 0, // 36\r
- ADC1_IRQHandler, // 37\r
- SSP0_IRQHandler, // 38\r
- SSP1_IRQHandler, // 39\r
- UART0_IRQHandler, // 40\r
- UART1_IRQHandler, // 41\r
- UART2_IRQHandler, // 42\r
- UART3_IRQHandler, // 43\r
- I2S0_IRQHandler, // 44\r
- I2S1_IRQHandler, // 45\r
- SPIFI_IRQHandler, // 46\r
- SGPIO_IRQHandler, // 47\r
- GPIO0_IRQHandler, // 48\r
- GPIO1_IRQHandler, // 49\r
- GPIO2_IRQHandler, // 50\r
- GPIO3_IRQHandler, // 51\r
- GPIO4_IRQHandler, // 52\r
- GPIO5_IRQHandler, // 53\r
- GPIO6_IRQHandler, // 54\r
- GPIO7_IRQHandler, // 55\r
- GINT0_IRQHandler, // 56\r
- GINT1_IRQHandler, // 57\r
- EVRT_IRQHandler, // 58\r
- CAN1_IRQHandler, // 59\r
- 0, // 60\r
- 0, // 61\r
- ATIMER_IRQHandler, // 62\r
- RTC_IRQHandler, // 63\r
- 0, // 64\r
- WDT_IRQHandler, // 65\r
- 0, // 66\r
- CAN0_IRQHandler, // 67\r
- QEI_IRQHandler, // 68\r
+void(*const g_pfnVectors[]) (void) = {\r
+ // Core Level - CM4/CM3\r
+ &_vStackTop, // The initial stack pointer\r
+ ResetISR, // The reset handler\r
+ NMI_Handler, // The NMI handler\r
+ HardFault_Handler, // The hard fault handler\r
+ MemManage_Handler, // The MPU fault handler\r
+ BusFault_Handler, // The bus fault handler\r
+ UsageFault_Handler, // The usage fault handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ SVC_Handler, // SVCall handler\r
+ DebugMon_Handler, // Debug monitor handler\r
+ 0, // Reserved\r
+ PendSV_Handler, // The PendSV handler\r
+ SysTick_Handler, // The SysTick handler\r
+\r
+ // Chip Level - LPC18xx/43xx\r
+ DAC_IRQHandler, // 16 D/A Converter\r
+ MX_CORE_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY)\r
+ DMA_IRQHandler, // 18 General Purpose DMA\r
+ 0, // 19 Reserved\r
+ FLASHEEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts\r
+ ETH_IRQHandler, // 21 Ethernet\r
+ SDIO_IRQHandler, // 22 SD/MMC\r
+ LCD_IRQHandler, // 23 LCD\r
+ USB0_IRQHandler, // 24 USB0\r
+ USB1_IRQHandler, // 25 USB1\r
+ SCT_IRQHandler, // 26 State Configurable Timer\r
+ RIT_IRQHandler, // 27 Repetitive Interrupt Timer\r
+ TIMER0_IRQHandler, // 28 Timer0\r
+ TIMER1_IRQHandler, // 29 Timer 1\r
+ TIMER2_IRQHandler, // 30 Timer 2\r
+ TIMER3_IRQHandler, // 31 Timer 3\r
+ MCPWM_IRQHandler, // 32 Motor Control PWM\r
+ ADC0_IRQHandler, // 33 A/D Converter 0\r
+ I2C0_IRQHandler, // 34 I2C0\r
+ I2C1_IRQHandler, // 35 I2C1\r
+ SPI_IRQHandler, // 36 SPI (LPC43XX ONLY)\r
+ ADC1_IRQHandler, // 37 A/D Converter 1\r
+ SSP0_IRQHandler, // 38 SSP0 \r
+ SSP1_IRQHandler, // 39 SSP1\r
+ UART0_IRQHandler, // 40 UART0\r
+ UART1_IRQHandler, // 41 UART1\r
+ UART2_IRQHandler, // 42 UART2\r
+ UART3_IRQHandler, // 43 USRT3\r
+ I2S0_IRQHandler, // 44 I2S0\r
+ I2S1_IRQHandler, // 45 I2S1\r
+ SPIFI_IRQHandler, // 46 SPI Flash Interface\r
+ SGPIO_IRQHandler, // 47 SGPIO (LPC43XX ONLY)\r
+ GPIO0_IRQHandler, // 48 GPIO0\r
+ GPIO1_IRQHandler, // 49 GPIO1\r
+ GPIO2_IRQHandler, // 50 GPIO2\r
+ GPIO3_IRQHandler, // 51 GPIO3 \r
+ GPIO4_IRQHandler, // 52 GPIO4\r
+ GPIO5_IRQHandler, // 53 GPIO5\r
+ GPIO6_IRQHandler, // 54 GPIO6\r
+ GPIO7_IRQHandler, // 55 GPIO7\r
+ GINT0_IRQHandler, // 56 GINT0\r
+ GINT1_IRQHandler, // 57 GINT1\r
+ EVRT_IRQHandler, // 58 Event Router\r
+ CAN1_IRQHandler, // 59 C_CAN1\r
+ 0, // 60 Reserved\r
+ 0, // 61 Reserved \r
+ ATIMER_IRQHandler, // 62 ATIMER\r
+ RTC_IRQHandler, // 63 RTC\r
+ 0, // 64 Reserved\r
+ WDT_IRQHandler, // 65 WDT\r
+ 0, // 66 Reserved\r
+ CAN0_IRQHandler, // 67 C_CAN0\r
+ QEI_IRQHandler, // 68 QEI\r
};\r
\r
//*****************************************************************************\r
#include "CDCCommandConsole.h"\r
\r
/* Library includes. */\r
-#include "LPC18xx.h"\r
+#include "cmsis.h"\r
+#include "Board_API.h"\r
\r
/* The size of the stack and the priority used by the two echo client tasks. */\r
#define mainECHO_CLIENT_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )\r
/* The size of the stack and the priority used by the USB CDC command console\r
task. */\r
#define mainCDC_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )\r
-#define mainCDC_COMMAND_CONSOLE_TASK_PRIORITY ( 4U )\r
+#define mainCDC_COMMAND_CONSOLE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
\r
/*\r
* Register commands that can be used with FreeRTOS+CLI. The commands are\r
\r
int main( void )\r
{\r
+ /* Hardware setup. */\r
+ Board_Init();\r
+\r
/* The examples assume that all priority bits are assigned as preemption\r
priority bits. */\r
NVIC_SetPriorityGrouping( 0UL );\r
projects / freertos / commitdiff
