pcie1_hose.region_count = 1;
 #endif
-               printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
+               printf ("PCIE1: connected to Slot as %s (base addr %lx)\n",
                                pcie_ep ? "Endpoint" : "Root Complex",
                                pci_info[num].regs);
 
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 
        puts("\n");
        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
                SET_STD_PCI_INFO(pci_info[num], 1);
                pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-               printf ("\n    PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+               printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
                        (pci_32) ? 32 : 64,
                        (pci_speed == 33333000) ? "33" :
                        (pci_speed == 66666000) ? "66" : "unknown",
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pci1_hose, first_free_busno);
        } else {
-               printf ("    PCI: disabled\n");
+               printf("PCI1: disabled\n");
        }
 
        puts("\n");
                SET_STD_PCI_INFO(pci_info[num], 2);
                pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
 
-               puts ("    PCI2\n");
+               puts("PCI2\n");
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pci1_hose, first_free_busno);
        } else {
-               printf ("    PCI2: disabled\n");
+               printf("PCI2: disabled\n");
        }
        puts("\n");
 #else
 
                                LAW_TRGT_IF_PCIE_1);
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("    PCIE1 connected to Slot 1 as %s (base addr %lx)\n",
+               printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n",
                                pcie_ep ? "End Point" : "Root Complex",
                                pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
                                LAW_TRGT_IF_PCIE_2);
                SET_STD_PCIE_INFO(pci_info[num], 2);
                pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-               printf("    PCIE2 connected to Slot 3 as %s (base addr %lx)\n",
+               printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n",
                                pcie_ep ? "End Point" : "Root Complex",
                                pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                &pcie2_hose, first_free_busno);
        } else {
-               printf ("    PCIE2: disabled\n");
+               printf("PCIE2: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
                                LAW_TRGT_IF_PCIE_3);
                SET_STD_PCIE_INFO(pci_info[num], 3);
                pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-               printf("    PCIE3 connected to Slot 2 as %s (base addr %lx)\n",
+               printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n",
                                pcie_ep ? "End Point" : "Root Complex",
                                pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                &pcie3_hose, first_free_busno);
        } else {
-               printf ("    PCIE3: disabled\n");
+               printf("PCIE3: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
                                LAW_TRGT_IF_PCIE_4);
                SET_STD_PCIE_INFO(pci_info[num], 4);
                pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
-               printf("    PCIE4 connected to as %s (base addr %lx)\n",
+               printf("PCIE4: connected to as %s (base addr %lx)\n",
                                pcie_ep ? "End Point" : "Root Complex",
                                pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                &pcie4_hose, first_free_busno);
        } else {
-               printf ("    PCIE4: disabled\n");
+               printf("PCIE4: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
 
                                LAW_TRGT_IF_PCIE_3);
                SET_STD_PCIE_INFO(pci_info[num], 3);
                pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-               printf ("    PCIE3 connected to Slot3 as %s (base address %lx)\n",
+               printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
                        pcie_ep ? "Endpoint" : "Root Complex",
                        pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie3_hose, first_free_busno);
        } else {
-               printf ("    PCIE3: disabled\n");
+               printf("PCIE3: disabled\n");
        }
 
        puts("\n");
                                LAW_TRGT_IF_PCIE_1);
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf ("    PCIE1 connected to Slot1 as %s (base address %lx)\n",
+               printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
                        pcie_ep ? "Endpoint" : "Root Complex",
                        pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 
        puts("\n");
                                LAW_TRGT_IF_PCIE_2);
                SET_STD_PCIE_INFO(pci_info[num], 2);
                pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-               printf ("    PCIE2 connected to Slot 2 as %s (base address %lx)\n",
+               printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
                        pcie_ep ? "Endpoint" : "Root Complex",
                        pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie2_hose, first_free_busno);
        } else {
-               printf ("    PCIE2: disabled\n");
+               printf("PCIE2: disabled\n");
        }
 
        puts("\n");
                                LAW_TRGT_IF_PCI);
                SET_STD_PCI_INFO(pci_info[num], 1);
                pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-               printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+               printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
                        (pci_32) ? 32 : 64,
                        (pci_speed == 33333000) ? "33" :
                        (pci_speed == 66666000) ? "66" : "unknown",
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pci1_hose, first_free_busno);
        } else {
-               printf ("    PCI: disabled\n");
+               printf("PCI: disabled\n");
        }
 
        puts("\n");
 
        puts("Board: ADS\n");
 
 #ifdef CONFIG_PCI
-       printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+       printf("PCI1: 32 bit, %d MHz (compiled)\n",
               CONFIG_SYS_CLK_FREQ / 1000000);
 #else
-       printf("    PCI1: disabled\n");
+       printf("PCI1: disabled\n");
 #endif
 
        /*
 
                MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
                MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
 
-       printf ("    PCI1: %d bit, %s MHz, %s\n",
+       printf("PCI1: %d bit, %s MHz, %s\n",
                (pci1_32) ? 32 : 64,
                (pci1_speed == 33000000) ? "33" :
                (pci1_speed == 66000000) ? "66" : "unknown",
                pci1_clk_sel ? "sync" : "async");
 
        if (pci_dual) {
-               printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+               printf("PCI2: 32 bit, 66 MHz, %s\n",
                        pci2_clk_sel ? "sync" : "async");
        } else {
-               printf ("    PCI2: disabled\n");
+               printf("PCI2: disabled\n");
        }
 
        /*
 
 
                pcie3_hose.region_count = 1;
 #endif
-               printf ("    PCIE3 connected to ULI as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie3_hose, first_free_busno);
 
                 */
                in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
        } else {
-               printf ("    PCIE3: disabled\n");
+               printf("PCIE3: disabled\n");
        }
        puts("\n");
 #else
 
                pcie1_hose.region_count = 1;
 #endif
-               printf ("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+               printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
                                pcie_ep ? "Endpoint" : "Root Complex",
                                pci_info[num].regs);
 
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 
        puts("\n");
 
                pcie2_hose.region_count = 1;
 #endif
-               printf ("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie2_hose, first_free_busno);
        } else {
-               printf ("    PCIE2: disabled\n");
+               printf("PCIE2: disabled\n");
        }
 
        puts("\n");
        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
                SET_STD_PCI_INFO(pci_info[num], 1);
                pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-               printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+               printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
                        (pci_32) ? 32 : 64,
                        (pci_speed == 33333000) ? "33" :
                        (pci_speed == 66666000) ? "66" : "unknown",
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pci1_hose, first_free_busno);
        } else {
-               printf ("    PCI: disabled\n");
+               printf("PCI: disabled\n");
        }
 
        puts("\n");
 
        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
                SET_STD_PCI_INFO(pci_info[num], 1);
                pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-               printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+               printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
                        (pci_32) ? 32 : 64,
                        (pci_speed == 33333000) ? "33" :
                        (pci_speed == 66666000) ? "66" : "unknown",
                }
 #endif
        } else {
-               printf ("    PCI: disabled\n");
+               printf("PCI: disabled\n");
        }
 
        puts("\n");
        uint pci2_clk_sel = porpllsr & 0x4000;  /* PORPLLSR[17] */
        uint pci_dual = get_pci_dual ();        /* PCI DUAL in CM_PCI[3] */
        if (pci_dual) {
-               printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+               printf("PCI2: 32 bit, 66 MHz, %s\n",
                        pci2_clk_sel ? "sync" : "async");
        } else {
-               printf ("    PCI2: disabled\n");
+               printf("PCI2: disabled\n");
        }
 }
 #else
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
 
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 
        puts("\n");
 
                MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
                MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
 
-       printf ("    PCI1: %d bit, %s MHz, %s\n",
+       printf("PCI1: %d bit, %s MHz, %s\n",
                (pci1_32) ? 32 : 64,
                (pci1_speed == 33000000) ? "33" :
                (pci1_speed == 66000000) ? "66" : "unknown",
                pci1_clk_sel ? "sync" : "async");
 
        if (pci_dual) {
-               printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+               printf("PCI2: 32 bit, 66 MHz, %s\n",
                        pci2_clk_sel ? "sync" : "async");
        } else {
-               printf ("    PCI2: disabled\n");
+               printf("PCI2: disabled\n");
        }
 
        /*
 
        puts("Board: ADS\n");
 
 #ifdef CONFIG_PCI
-       printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+       printf("PCI1: 32 bit, %d MHz (compiled)\n",
               CONFIG_SYS_CLK_FREQ / 1000000);
 #else
-       printf("    PCI1: disabled\n");
+       printf("PCI1: disabled\n");
 #endif
 
        /*
 
        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
                SET_STD_PCI_INFO(pci_info[num], 1);
                pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-               printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+               printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
                        (pci_32) ? 32 : 64,
                        (pci_speed == 33333000) ? "33" :
                        (pci_speed == 66666000) ? "66" : "unknown",
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pci1_hose, first_free_busno);
        } else {
-               printf ("    PCI: disabled\n");
+               printf("PCI: disabled\n");
        }
 
        puts("\n");
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
+               printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
                                pcie_ep ? "Endpoint" : "Root Complex",
                                pci_info[num].regs);
 
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 
        puts("\n");
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 
        puts("\n");
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
                SET_STD_PCIE_INFO(pci_info[num], 3);
                pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-               printf ("    PCIE3 connected to ULI as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie3_hose, first_free_busno);
                /*
                        in_be32(p);
                }
        } else {
-               printf ("    PCIE3: disabled\n");
+               printf("PCIE3: disabled\n");
        }
        puts("\n");
 #else
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
                SET_STD_PCIE_INFO(pci_info[num], 2);
                pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-               printf ("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie2_hose, first_free_busno);
        } else {
-               printf ("    PCIE2: disabled\n");
+               printf("PCIE2: disabled\n");
        }
 
        puts("\n");
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf ("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+               printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
                                pcie_ep ? "Endpoint" : "Root Complex",
                                pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 
        puts("\n");
 
        if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf ("    PCIE1 connected to ULI as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
 
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 
        puts("\n");
        if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
                SET_STD_PCIE_INFO(pci_info[num], 2);
                pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-               printf ("    PCIE2 connected to Slot as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE2: connected to Slot as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie2_hose, first_free_busno);
        } else {
-               printf ("    PCIE2: disabled\n");
+               printf("PCIE2: disabled\n");
        }
 
        puts("\n");
        if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
                SET_STD_PCI_INFO(pci_info[num], 1);
                pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-               printf(" PCI connected to PCI slots as %s" \
+               printf("PCI: connected to PCI slots as %s" \
                        " (base address %lx)\n",
                        pci_agent ? "Agent" : "Host",
                        pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pci1_hose, first_free_busno);
        } else {
-               printf ("    PCI: disabled\n");
+               printf("PCI: disabled\n");
        }
 
        puts("\n");
 
        if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("    PCIE1 connected to ULI as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
 
                                       + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
 
        } else {
-               puts("    PCIE1: disabled\n");
+               puts("PCIE1: disabled\n");
        }
 #else
-       puts("    PCIE1: disabled\n");
+       puts("PCIE1: disabled\n");
 #endif /* CONFIG_PCIE1 */
 
 #ifdef CONFIG_PCIE2
        SET_STD_PCIE_INFO(pci_info[num], 2);
        pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-       printf("    PCIE2 connected as %s (base addr %lx)\n",
-                       pcie_ep ? "Endpoint" : "Root Complex",
-                       pci_info[num].regs);
+       printf("PCIE2: connected as %s (base addr %lx)\n",
+               pcie_ep ? "Endpoint" : "Root Complex",
+               pci_info[num].regs);
        first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                &pcie2_hose, first_free_busno);
 #else
-       puts("    PCIE2: disabled\n");
+       puts("PCIE2: disabled\n");
 #endif /* CONFIG_PCIE2 */
 
 }
 
        set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
        set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
        is_endpoint = fsl_setup_hose(hose, info->regs);
-       printf("    PCIE%u connected to %s as %s (base addr %lx)\n",
+       printf("PCIE%u: connected to %s as %s (base addr %lx)\n",
               info->pci_num, connected,
               is_endpoint ? "Endpoint" : "Root Complex", info->regs);
        bus_number = fsl_pci_init_port(info, hose, bus_number);
                SET_STD_PCIE_INFO(pci_info, 1);
                configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
        } else {
-               printf("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
                SET_STD_PCIE_INFO(pci_info, 2);
                configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
        } else {
-               printf("    PCIE2: disabled\n");
+               printf("PCIE2: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
                SET_STD_PCIE_INFO(pci_info, 3);
                configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
        } else {
-               printf("    PCIE3: disabled\n");
+               printf("PCIE3: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
                SET_STD_PCIE_INFO(pci_info[num], 2);
                pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-               printf("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie2_hose, first_free_busno);
        } else {
-               printf ("    PCIE2: disabled\n");
+               printf("PCIE2: disabled\n");
        }
        puts("\n");
 #else
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
        puts("\n");
 #else
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
                SET_STD_PCIE_INFO(pci_info[num], 2);
                pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-               printf("    PCIE2 connected to ULI as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie2_hose, first_free_busno);
 
                }
 #endif
        } else {
-               printf("    PCIE2: disabled\n");
+               printf("PCIE2: disabled\n");
        }
        puts("\n");
 #else
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
                SET_STD_PCIE_INFO(pci_info[num], 3);
                pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-               printf("    PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie3_hose, first_free_busno);
        } else {
-               printf("    PCIE3: disabled\n");
+               printf("PCIE3: disabled\n");
        }
        puts("\n");
 #else
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
        puts("\n");
 #else
 
        puts("Board: MicroSys PM854\n");
 
 #ifdef CONFIG_PCI
-       printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+       printf("PCI1: 32 bit, %d MHz (compiled)\n",
               CONFIG_SYS_CLK_FREQ / 1000000);
 #else
-       printf("    PCI1: disabled\n");
+       printf("PCI1: disabled\n");
 #endif
 
        /*
 
        puts("Board: MicroSys PM856\n");
 
 #ifdef CONFIG_PCI
-       printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+       printf("PCI1: 32 bit, %d MHz (compiled)\n",
               CONFIG_SYS_CLK_FREQ / 1000000);
 #else
-       printf("    PCI1: disabled\n");
+       printf("PCI1: disabled\n");
 #endif
 
        /*
 
                uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
                uint pci_speed = CONFIG_SYS_CLK_FREQ;   /* get_clock_freq() */
 
-               printf ("    PCI host: %d bit, %s MHz, %s, %s\n",
+               printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
                        (pci_32) ? 32 : 64,
                        (pci_speed == 33000000) ? "33" :
                        (pci_speed == 66000000) ? "66" : "unknown",
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pci1_hose, first_free_busno);
        } else {
-               printf ("    PCI: disabled\n");
+               printf("PCI: disabled\n");
        }
 
        puts("\n");
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
                SET_STD_PCIE_INFO(pci_info[num], 1);
-               printf ("    PCIE at base address %lx\n", pci_info[num].regs);
+               printf("PCIE: base address %lx\n", pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE: disabled\n");
+               printf("PCIE: disabled\n");
        }
 
        puts("\n");
 
        if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("    PCIE1 connected as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE1: connected as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               puts("    PCIE1: disabled\n");
+               puts("PCIE1: disabled\n");
        }
 #else
-       puts("    PCIE1: disabled\n");
+       puts("PCIE1: disabled\n");
 #endif /* CONFIG_PCIE1 */
 
 #ifdef CONFIG_PCIE2
 
        SET_STD_PCIE_INFO(pci_info[num], 2);
        pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-       printf("    PCIE2 connected as %s (base addr %lx)\n",
-                       pcie_ep ? "Endpoint" : "Root Complex",
-                       pci_info[num].regs);
+       printf("PCIE2: connected as %s (base addr %lx)\n",
+               pcie_ep ? "Endpoint" : "Root Complex",
+               pci_info[num].regs);
        first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                &pcie2_hose, first_free_busno);
 #else
-       puts("    PCIE2: disabled\n");
+       puts("PCIE2: disabled\n");
 #endif /* CONFIG_PCIE2 */
 }
 
 
        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
                SET_STD_PCI_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-               printf ("\n   PCI1:  %d bit, %s MHz, %s, %s, %s\n",
+               printf("PCI1:  %d bit, %s MHz, %s, %s, %s\n",
                        (pci_32) ? 32 : 64,
                        (pci_speed == 33333333) ? "33" :
                        (pci_speed == 66666666) ? "66" : "unknown",
                }
 #endif
        } else {
-               printf("    PCI1: disabled\n");
+               printf("PCI1: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("    PCIE1 connected as %s\n",
+               printf("PCIE1: connected as %s\n",
                        pcie_ep ? "Endpoint" : "Root Complex");
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
 
        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
                SET_STD_PCI_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-               printf("\n    PCI1: %d bit %s, %s %d MHz, %s, %s\n",
+               printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
                        pci_32 ? 32 : 64,
                        pcix ? "PCIX" : "PCI",
                        pci_spd_norm ? ">=" : "<=",
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pci1_hose, first_free_busno);
        } else {
-               printf("    PCI1: disabled\n");
+               printf("PCI1: disabled\n");
        }
 #elif defined CONFIG_MPC8548
        /* PCI1 not present on MPC8572 */
        if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("    PCIE1 connected as %s\n",
+               printf("PCIE1: connected as %s\n",
                        pcie_ep ? "Endpoint" : "Root Complex");
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
        if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
                SET_STD_PCIE_INFO(pci_info[num], 2);
                pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-               printf("    PCIE2 connected as %s\n",
+               printf("PCIE2: connected as %s\n",
                        pcie_ep ? "Endpoint" : "Root Complex");
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie2_hose, first_free_busno);
        } else {
-               printf("    PCIE2: disabled\n");
+               printf("PCIE2: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
        if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
                SET_STD_PCIE_INFO(pci_info[num], 3);
                pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-               printf("    PCIE3 connected as %s\n",
+               printf("PCIE3: connected as %s\n",
                        pcie_ep ? "Endpoint" : "Root Complex");
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie3_hose, first_free_busno);
        } else {
-               printf("    PCIE3: disabled\n");
+               printf("PCIE3: disabled\n");
        }
 #else
        setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
 
         * 1 == pci agent or pcie end-point
         */
        if (!temp8) {
-               printf("               Scanning PCI bus %02x\n",
+               printf("           Scanning PCI bus %02x\n",
                        hose->current_busno);
                hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
        } else {
-               debug("               Not scanning PCI bus %02x. PI=%x\n",
+               debug("           Not scanning PCI bus %02x. PI=%x\n",
                        hose->current_busno, temp8);
                hose->last_busno = hose->current_busno;
        }
        }
 
        pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
-       printf("    PCI%s%x on bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
-                       "E" : "", pci_info->pci_num,
-                       hose->first_busno, hose->last_busno);
+       printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
+               "E" : "", pci_info->pci_num,
+               hose->first_busno, hose->last_busno);
 
        return(hose->last_busno + 1);
 }