--- /dev/null
+*.d
+*.o
+*.bin
+*.map
+*.axf
# IBDAP-CMSIS-DAP
Armstart's CMSIS-DAP firmware implementation in gcc and makefile.
+
+[http://www.armstart.com](http://www.armstart.com)
+
+[IBDAP](https://hackaday.io/project/6578-ibdap-affordable-cmsis-dap-jtagswd-debug-probe) is a fully CMSIS-DAP compatible debug adapter. It provides vendor independent debug interface between your PC over USB and target ARM device over JTAG/SWD pins. You can do debugging functions like stepping, breakpoints, watch points and firmware download etc. It's fully supported by Keil, OpenOCD, GNU GDB, IAR and other commonly used debugging tools.
+
+# Why IBDAP?
+
+Debug adapters are expensive, some could cost thousands of dollars, some may not be compatible among different vendors. Luckily, ARM standardized the debugging interface which is called CMSIS-DAP and released the firmware implementation on some processors, however, you still need a Keil MDK Professional edition software in order to build the firmware, even the open source one provided by mbed and the price for Keil Professional is intimidating. All these barriers has become the first issue that every inventor is facing, and we need a solution!
+IBDAP's objective is to become an affordable open source & open hardware CMSIS-DAP JTAG/SWD debug probe implementation using gcc & makefile. Anyone can modify and embed a debug probe on its own device easily with everything under its control.
+
+Besides being functioning as a JTAG/SWD debug probe, IBDAP could also be used as a general development board. It has an ARM Cortex M0 processor running at 48Mhz and has peripherals like UART, I2C, SPI, USB. It can be used in many applications like USB audio devices, USB mouse/keyboards, USB mass storage devices, USB-TTL adapter device and many many more. Moreover, the 10-bit high precision ADC peripheral also makes IBDAP an ideal device for any sensor projects.
+
+
+
--- /dev/null
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2015
+ * Generated linker script file for LPC11U35/501
+ * Created from generic_c.ld (7.7.2 ())
+ * By LPCXpresso v7.7.2 [Build 379] [2015-03-31] on Wed Jun 24 20:31:09 EDT 2015
+ */
+
+
+INCLUDE "IBDAP_lib.ld"
+INCLUDE "IBDAP_mem.ld"
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ } >MFlash64
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+
+ } > MFlash64
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash64
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash64
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamUsb2 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamUsb2)
+ *(.data.$RAM2*)
+ *(.data.$RamUsb2*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ } > RamUsb2 AT>MFlash64
+
+ /* DATA section for SRAM1_2 */
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM3 = .) ;
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$SRAM1_2)
+ *(.data.$RAM3*)
+ *(.data.$SRAM1_2*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM3 = .) ;
+ } > SRAM1_2 AT>MFlash64
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc8
+
+
+ /* Main DATA section (RamLoc8) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc8 AT>MFlash64
+
+ /* BSS section for RamUsb2 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ *(.bss.$RAM2*)
+ *(.bss.$RamUsb2*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_bss_RAM2 = .) ;
+ } > RamUsb2
+ /* BSS section for SRAM1_2 */
+ .bss_RAM3 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM3 = .) ;
+ *(.bss.$RAM3*)
+ *(.bss.$SRAM1_2*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_bss_RAM3 = .) ;
+ } > SRAM1_2
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc8
+
+ /* NOINIT section for RamUsb2 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2
+ /* NOINIT section for SRAM1_2 */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM3*)
+ *(.noinit.$SRAM1_2*)
+ . = ALIGN(4) ;
+ } > SRAM1_2
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
+}
--- /dev/null
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-13
+ * (c) NXP Semiconductors 2013-2015
+ * Generated linker script file for LPC11U35/501
+ * Created from LibIncTemplate.ld (7.7.2 ())
+ * By LPCXpresso v7.7.2 [Build 379] [2015-03-31] on Wed Jun 24 20:31:09 EDT 2015
+ */
+
+
+ GROUP(
+ libgcc.a
+ libc_nano.a
+ libm.a
+ )
--- /dev/null
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2015
+ * (c) NXP Semiconductors 2013-2015
+ * Linker script memory definitions
+ * Created from LinkMemoryTemplate
+ * By LPCXpresso v7.7.2 [Build 379] [2015-03-31] on Wed Jun 24 20:31:09 EDT 2015)
+*/
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes */
+ RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes */
+ RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */
+ SRAM1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */
+
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash64 = 0x0 + 0x10000;
+ __top_RamLoc8 = 0x10000000 + 0x2000;
+ __top_RamUsb2 = 0x20004000 + 0x800;
+ __top_SRAM1_2 = 0x20000000 + 0x800;
+
+
+
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All Target
+all: IBDAP.axf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+
+
+# Tool invocations
+IBDAP.axf: $(OBJS) $(USER_OBJS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: MCU Linker'
+ arm-none-eabi-gcc -nostdlib -Xlinker -Map="IBDAP.map" -Xlinker --gc-sections -Xlinker --trace -mcpu=cortex-m0 -mthumb -T "IBDAP.ld" -o "IBDAP.axf" $(OBJS) $(USER_OBJS) $(LIBS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+ $(MAKE) --no-print-directory post-build
+
+# Other Targets
+clean:
+ -$(RM) $(OBJS)$(C_DEPS)$(EXECUTABLES) IBDAP.axf IBDAP.bin IBDAP.map
+ -@echo ' '
+
+post-build:
+ -@echo 'Performing post-build steps'
+ -arm-none-eabi-size "IBDAP.axf" ; arm-none-eabi-objcopy -v -O binary "IBDAP.axf" "IBDAP.bin" ; ./checksum -p LPC11U35_501 -d "IBDAP.bin"
+ -@echo ' '
+
+.PHONY: all clean dependents
+.SECONDARY: post-build
+
+-include ../makefile.targets
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+O_SRCS :=
+C_SRCS :=
+S_SRCS :=
+S_UPPER_SRCS :=
+OBJ_SRCS :=
+ASM_SRCS :=
+OBJS :=
+C_DEPS :=
+EXECUTABLES :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+src \
+
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../src/DAP.c \
+../src/IBDAP.c \
+../src/JTAG_DP.c \
+../src/SW_DP.c \
+../src/cr_startup_lpc11uxx.c \
+../src/crp.c \
+../src/system_LPC11Uxx.c \
+../src/uart.c \
+../src/usb_desc.c \
+../src/usb_driver.c
+
+OBJS += \
+./src/DAP.o \
+./src/IBDAP.o \
+./src/JTAG_DP.o \
+./src/SW_DP.o \
+./src/cr_startup_lpc11uxx.o \
+./src/crp.o \
+./src/system_LPC11Uxx.o \
+./src/uart.o \
+./src/usb_desc.o \
+./src/usb_driver.o
+
+C_DEPS += \
+./src/DAP.d \
+./src/IBDAP.d \
+./src/JTAG_DP.d \
+./src/SW_DP.d \
+./src/cr_startup_lpc11uxx.d \
+./src/crp.d \
+./src/system_LPC11Uxx.d \
+./src/uart.d \
+./src/usb_desc.d \
+./src/usb_driver.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+src/%.o: ../src/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -DNDEBUG -DCORE_M0 -D__USE_CMSIS -D__LPC11UXX__ -I"/home/yliu/projects/ib51822/IBDAP-FW/Firmware/IBDAP/inc" -I"/home/yliu/projects/ib51822/IBDAP-FW/Firmware/IBDAP/inc/usbd" -Os -g -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m0 -mthumb -v -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -MT"$(@:%.o=%.d)" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+src/system_LPC11Uxx.o: ../src/system_LPC11Uxx.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: MCU C Compiler'
+ arm-none-eabi-gcc -DNDEBUG -DCORE_M0 -D__USE_CMSIS -D__LPC11UXX__ -I"/home/yliu/projects/ib51822/IBDAP-FW/Firmware/IBDAP/inc" -I"/home/yliu/projects/ib51822/IBDAP-FW/Firmware/IBDAP/inc/usbd" -Os -g -Wall -c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -mcpu=cortex-m0 -mthumb -v -MMD -MP -MF"$(@:%.o=%.d)" -MT"src/system_LPC11Uxx.d" -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
--- /dev/null
+/******************************************************************************\r
+ * @file DAP.h\r
+ * @brief CMSIS-DAP Definitions\r
+ * @version V1.00\r
+ * @date 31. May 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __DAP_H__\r
+#define __DAP_H__\r
+\r
+\r
+// DAP Command IDs\r
+#define ID_DAP_Info 0x00\r
+#define ID_DAP_LED 0x01\r
+#define ID_DAP_Connect 0x02\r
+#define ID_DAP_Disconnect 0x03\r
+#define ID_DAP_TransferConfigure 0x04\r
+#define ID_DAP_Transfer 0x05\r
+#define ID_DAP_TransferBlock 0x06\r
+#define ID_DAP_TransferAbort 0x07\r
+#define ID_DAP_WriteABORT 0x08\r
+#define ID_DAP_Delay 0x09\r
+#define ID_DAP_ResetTarget 0x0A\r
+#define ID_DAP_SWJ_Pins 0x10\r
+#define ID_DAP_SWJ_Clock 0x11\r
+#define ID_DAP_SWJ_Sequence 0x12\r
+#define ID_DAP_SWD_Configure 0x13\r
+#define ID_DAP_JTAG_Sequence 0x14\r
+#define ID_DAP_JTAG_Configure 0x15\r
+#define ID_DAP_JTAG_IDCODE 0x16\r
+\r
+// DAP Vendor Command IDs\r
+#define ID_DAP_Vendor0 0x80\r
+#define ID_DAP_Vendor1 0x81\r
+#define ID_DAP_Vendor2 0x82\r
+#define ID_DAP_Vendor3 0x83\r
+#define ID_DAP_Vendor4 0x84\r
+#define ID_DAP_Vendor5 0x85\r
+#define ID_DAP_Vendor6 0x86\r
+#define ID_DAP_Vendor7 0x87\r
+#define ID_DAP_Vendor8 0x88\r
+#define ID_DAP_Vendor9 0x89\r
+#define ID_DAP_Vendor10 0x8A\r
+#define ID_DAP_Vendor11 0x8B\r
+#define ID_DAP_Vendor12 0x8C\r
+#define ID_DAP_Vendor13 0x8D\r
+#define ID_DAP_Vendor14 0x8E\r
+#define ID_DAP_Vendor15 0x8F\r
+#define ID_DAP_Vendor16 0x90\r
+#define ID_DAP_Vendor17 0x91\r
+#define ID_DAP_Vendor18 0x92\r
+#define ID_DAP_Vendor19 0x93\r
+#define ID_DAP_Vendor20 0x94\r
+#define ID_DAP_Vendor21 0x95\r
+#define ID_DAP_Vendor22 0x96\r
+#define ID_DAP_Vendor23 0x97\r
+#define ID_DAP_Vendor24 0x98\r
+#define ID_DAP_Vendor25 0x99\r
+#define ID_DAP_Vendor26 0x9A\r
+#define ID_DAP_Vendor27 0x9B\r
+#define ID_DAP_Vendor28 0x9C\r
+#define ID_DAP_Vendor29 0x9D\r
+#define ID_DAP_Vendor30 0x9E\r
+#define ID_DAP_Vendor31 0x9F\r
+\r
+#define ID_DAP_Invalid 0xFF\r
+\r
+// DAP Status Code\r
+#define DAP_OK 0\r
+#define DAP_ERROR 0xFF\r
+\r
+// DAP ID\r
+#define DAP_ID_VENDOR 1\r
+#define DAP_ID_PRODUCT 2\r
+#define DAP_ID_SER_NUM 3\r
+#define DAP_ID_FW_VER 4\r
+#define DAP_ID_DEVICE_VENDOR 5\r
+#define DAP_ID_DEVICE_NAME 6\r
+#define DAP_ID_CAPABILITIES 0xF0\r
+#define DAP_ID_PACKET_COUNT 0xFE\r
+#define DAP_ID_PACKET_SIZE 0xFF\r
+\r
+// DAP LEDs\r
+#define DAP_LED_DEBUGGER_CONNECTED 0\r
+#define DAP_LED_TARGET_RUNNING 1\r
+\r
+// DAP Port\r
+#define DAP_PORT_AUTODETECT 0 // Autodetect Port\r
+#define DAP_PORT_DISABLED 0 // Port Disabled (I/O pins in High-Z)\r
+#define DAP_PORT_SWD 1 // SWD Port (SWCLK, SWDIO) + nRESET\r
+#define DAP_PORT_JTAG 2 // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET\r
+\r
+// DAP SWJ Pins\r
+#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK\r
+#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS\r
+#define DAP_SWJ_TDI 2 // TDI\r
+#define DAP_SWJ_TDO 3 // TDO\r
+#define DAP_SWJ_nTRST 5 // nTRST\r
+#define DAP_SWJ_nRESET 7 // nRESET\r
+\r
+// DAP Transfer Request\r
+#define DAP_TRANSFER_APnDP (1<<0)\r
+#define DAP_TRANSFER_RnW (1<<1)\r
+#define DAP_TRANSFER_A2 (1<<2)\r
+#define DAP_TRANSFER_A3 (1<<3)\r
+#define DAP_TRANSFER_MATCH_VALUE (1<<4)\r
+#define DAP_TRANSFER_MATCH_MASK (1<<5)\r
+\r
+// DAP Transfer Response\r
+#define DAP_TRANSFER_OK (1<<0)\r
+#define DAP_TRANSFER_WAIT (1<<1)\r
+#define DAP_TRANSFER_FAULT (1<<2)\r
+#define DAP_TRANSFER_ERROR (1<<3)\r
+#define DAP_TRANSFER_MISMATCH (1<<4)\r
+\r
+\r
+// Debug Port Register Addresses\r
+#define DP_IDCODE 0x00 // IDCODE Register (SW Read only)\r
+#define DP_ABORT 0x00 // Abort Register (SW Write only)\r
+#define DP_CTRL_STAT 0x04 // Control & Status\r
+#define DP_WCR 0x04 // Wire Control Register (SW Only)\r
+#define DP_SELECT 0x08 // Select Register (JTAG R/W & SW W)\r
+#define DP_RESEND 0x08 // Resend (SW Read Only)\r
+#define DP_RDBUFF 0x0C // Read Buffer (Read Only)\r
+\r
+// JTAG IR Codes\r
+#define JTAG_ABORT 0x08\r
+#define JTAG_DPACC 0x0A\r
+#define JTAG_APACC 0x0B\r
+#define JTAG_IDCODE 0x0E\r
+#define JTAG_BYPASS 0x0F\r
+\r
+// JTAG Sequence Info\r
+#define JTAG_SEQUENCE_TCK 0x3F // TCK count\r
+#define JTAG_SEQUENCE_TMS 0x40 // TMS value\r
+#define JTAG_SEQUENCE_TDO 0x80 // TDO capture\r
+\r
+\r
+#include <stddef.h>\r
+#include <stdint.h>\r
+\r
+// DAP Data structure\r
+typedef struct {\r
+ uint8_t debug_port; // Debug Port\r
+ uint8_t fast_clock; // Fast Clock Flag\r
+ uint32_t clock_delay; // Clock Delay\r
+ struct { // Transfer Configuration\r
+ uint8_t idle_cycles; // Idle cycles after transfer\r
+ uint16_t retry_count; // Number of retries after WAIT response\r
+ uint16_t match_retry; // Number of retries if read value does not match\r
+ uint32_t match_mask; // Match Mask\r
+ } transfer;\r
+#if (DAP_SWD != 0)\r
+ struct { // SWD Configuration\r
+ uint8_t turnaround; // Turnaround period\r
+ uint8_t data_phase; // Always generate Data Phase\r
+ } swd_conf;\r
+#endif\r
+#if (DAP_JTAG != 0)\r
+ struct { // JTAG Device Chain\r
+ uint8_t count; // Number of devices\r
+ uint8_t index; // Device index (device at TDO has index 0)\r
+#if (DAP_JTAG_DEV_CNT != 0)\r
+ uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits\r
+ uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR\r
+ uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR\r
+#endif\r
+ } jtag_dev;\r
+#endif\r
+} DAP_Data_t;\r
+\r
+extern DAP_Data_t DAP_Data; // DAP Data\r
+extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag\r
+\r
+\r
+// Functions\r
+extern void SWJ_Sequence (uint32_t count, uint8_t *data);\r
+extern void JTAG_Sequence (uint32_t info, uint8_t *tdi, uint8_t *tdo);\r
+extern void JTAG_IR (uint32_t ir);\r
+extern uint32_t JTAG_ReadIDCode (void);\r
+extern void JTAG_WriteAbort (uint32_t data);\r
+extern uint8_t JTAG_Transfer (uint32_t request, uint32_t *data);\r
+extern uint8_t SWD_Transfer (uint32_t request, uint32_t *data);\r
+\r
+extern void Delayms (uint32_t delay);\r
+\r
+extern uint32_t DAP_ProcessVendorCommand (uint8_t *request, uint8_t *response);\r
+\r
+extern uint32_t DAP_ProcessCommand (uint8_t *request, uint8_t *response);\r
+extern void DAP_Setup (void);\r
+\r
+// Configurable delay for clock generation\r
+#ifndef DELAY_SLOW_CYCLES\r
+#define DELAY_SLOW_CYCLES 3 // Number of cycles for one iteration\r
+#endif\r
+static __forceinline void PIN_DELAY_SLOW (uint32_t delay) {\r
+ int32_t count;\r
+\r
+ count = delay;\r
+ while (--count);\r
+}\r
+\r
+// Fixed delay for fast clock generation\r
+#ifndef DELAY_FAST_CYCLES\r
+#define DELAY_FAST_CYCLES 0 // Number of cycles: 0..3\r
+#endif\r
+static __forceinline void PIN_DELAY_FAST (void) {\r
+#if (DELAY_FAST_CYCLES >= 1)\r
+ __nop();\r
+#endif\r
+#if (DELAY_FAST_CYCLES >= 2)\r
+ __nop();\r
+#endif\r
+#if (DELAY_FAST_CYCLES >= 3)\r
+ __nop();\r
+#endif\r
+}\r
+\r
+\r
+#endif /* __DAP_H__ */\r
--- /dev/null
+/**************************************************************************//**
+ * @file DAP_config.h
+ * @brief IBDAP DAP config for LPC11U35
+ * @version V0.1
+ * @date 08. May 2015
+ *
+ * @note
+ * Copyright (C) 2015 Armstart. All rights reserved.
+ *
+ * @par
+ *
+ * @par
+ *
+ ******************************************************************************/
+
+#ifndef __DAP_CONFIG_H__
+#define __DAP_CONFIG_H__
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
+\ingroup DAP_ConfigIO_gr
+@{
+Provides definitions about:
+ - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
+ - Debug Unit communication packet size.
+ - Debug Access Port communication mode (JTAG or SWD).
+ - Optional information about a connected Target Device (for Evaluation Boards).
+*/
+
+#ifdef __USE_CMSIS
+#include "LPC11Uxx.h"
+#endif
+
+#include "compiler.h"
+
+/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
+/// This value is used to calculate the SWD/JTAG clock speed.
+#define CPU_CLOCK 48000000 ///< Specifies the CPU Clock in Hz
+
+/// Number of processor cycles for I/O Port write operations.
+/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
+/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
+/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
+/// requrired.
+#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
+
+/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
+
+/// Indicate that JTAG communication mode is available at the Debug Port.
+/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
+
+/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
+/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
+#define DAP_JTAG_DEV_CNT 8 ///< Maximum number of JTAG devices on scan chain
+
+/// Default communication mode on the Debug Access Port.
+/// Used for the command \ref DAP_Connect when Port Default mode is selected.
+#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
+
+/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
+/// Used to initialize the default SWD/JTAG clock frequency.
+/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
+#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz.
+
+/// Maximum Package Size for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
+#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed.
+
+/// Maximum Package Buffers for Command and Response data.
+/// This configuration settings is used to optimized the communication performance with the
+/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
+/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
+#define DAP_PACKET_COUNT 8 ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+
+
+/// Debug Unit is connected to fixed Target Device.
+/// The Debug Unit may be part of an evaluation board and always connected to a fixed
+/// known device. In this case a Device Vendor and Device Name string is stored which
+/// may be used by the debugger or IDE to configure device parameters.
+#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
+
+#if TARGET_DEVICE_FIXED
+#define TARGET_DEVICE_VENDOR "ARMSTART" ///< String indicating the Silicon Vendor
+#define TARGET_DEVICE_NAME "IBDAP-LPC11U35 CMSIS-DAP" ///< String indicating the Target Device
+#endif
+
+///@}
+
+
+// Peripheral register bit masks (used for pin inits)
+#define FUNC_0 0
+#define FUNC_1 1
+#define PULL_DOWN_ENABLED (1 << 3)
+#define PULL_UP_ENABLED (2 << 3)
+#define OPENDRAIN (1 << 10)
+
+// Debug Port I/O Pins
+// For LPC11Uxx DAPs all SWD and JTAG pins are on GPIO port 0
+// Default is mbed HDK reference design with LPC11U35/501
+// SWCLK/TCK Pin PIO0_7
+#define PIN_SWCLK_IN_BIT 7
+#define PIN_SWCLK (1 << PIN_SWCLK_IN_BIT)
+#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_7
+
+// SWDIO/TMS In/Out Pin PIO0_8
+#define PIN_SWDIO_IN_BIT 8
+#define PIN_SWDIO (1 << PIN_SWDIO_IN_BIT)
+#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8
+
+// nRESET Pin PIO0_2
+#define PIN_nRESET_IN_BIT 2
+#define PIN_nRESET (1 << PIN_nRESET_IN_BIT)
+#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2
+
+#if (DAP_JTAG != 0)
+
+// TDI Pin PIO0_17
+#define PIN_TDI_IN_BIT 17
+#define PIN_TDI (1 << PIN_TDI_IN_BIT)
+#define PIN_TDI_IOCON LPC_IOCON->PIO0_17
+
+// SWO/TDO Pin PIO0_9
+#define PIN_TDO_IN_BIT 9
+#define PIN_TDO (1 << PIN_TDO_IN_BIT)
+#define PIN_TDO_IOCON LPC_IOCON->PIO0_9
+#endif // (DAP_JTAG != 0)
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
+\ingroup DAP_ConfigIO_gr
+@{
+
+Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
+interface of a device. The following I/O Pins are provided:
+
+JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
+---------------------------- | -------------------- | ---------------------------------------------
+TCK: Test Clock | SWCLK: Clock | Output Push/Pull
+TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
+TDI: Test Data Input | | Output Push/Pull
+TDO: Test Data Output | | Input
+nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
+nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
+
+
+DAP Hardware I/O Pin Access Functions
+-------------------------------------
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
+
+For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
+of the same I/O port. The following SWDIO I/O Pin functions are provided:
+ - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
+ - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
+ - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
+ - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
+*/
+
+
+// Configure DAP I/O pins ------------------------------
+
+/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
+Configures the DAP Hardware I/O pins for JTAG mode:
+ - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
+ - TDO to input mode.
+*/
+static __inline void PORT_JTAG_SETUP (void) {
+#if (DAP_JTAG != 0)
+ LPC_GPIO->SET[0] = PIN_TDI;
+ LPC_GPIO->DIR[0] |= PIN_TDI;
+ LPC_GPIO->DIR[0] &= ~PIN_TDO;
+#endif
+}
+
+/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
+Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
+ - SWCLK, SWDIO, nRESET to output mode and set to default high level.
+ - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
+*/
+static __inline void PORT_SWD_SETUP (void) {
+ LPC_GPIO->SET[0] = PIN_SWCLK;
+ LPC_GPIO->SET[0] = PIN_SWDIO;
+#if defined(CONF_OPENDRAIN)
+ // open drain logic
+ LPC_GPIO->DIR[0] &= ~PIN_nRESET;
+ LPC_GPIO->CLR[0] = PIN_nRESET;
+ LPC_GPIO->DIR[0] |= (PIN_SWCLK | PIN_SWDIO);
+#else
+ LPC_GPIO->SET[0] = PIN_nRESET;
+ LPC_GPIO->DIR[0] |= (PIN_SWCLK | PIN_SWDIO | PIN_nRESET);
+#endif
+}
+
+/** Disable JTAG/SWD I/O Pins.
+Disables the DAP Hardware I/O pins which configures:
+ - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
+*/
+static __inline void PORT_OFF (void) {
+ LPC_GPIO->CLR[0] = PIN_SWCLK;
+ LPC_GPIO->CLR[0] = PIN_SWDIO;
+#if defined(CONF_OPENDRAIN)
+ // open drain logic
+ LPC_GPIO->DIR[0] &= ~PIN_nRESET; // reset not an output
+ LPC_GPIO->CLR[0] = PIN_nRESET;
+ LPC_GPIO->DIR[0] |= (PIN_SWCLK | PIN_SWDIO);
+#else
+ LPC_GPIO->SET[0] = PIN_nRESET;
+ LPC_GPIO->DIR[0] |= (PIN_SWCLK | PIN_SWDIO | PIN_nRESET);
+#endif
+}
+
+
+// SWCLK/TCK I/O pin -------------------------------------
+
+/** SWCLK/TCK I/O pin: Get Input.
+\return Current status of the SWCLK/TCK DAP hardware I/O pin.
+*/
+static __forceinline uint32_t PIN_SWCLK_TCK_IN (void) {
+ return LPC_GPIO->B[PIN_SWCLK_IN_BIT] & 0x1;
+}
+
+/** SWCLK/TCK I/O pin: Set Output to High.
+Set the SWCLK/TCK DAP hardware I/O pin to high level.
+*/
+static __forceinline void PIN_SWCLK_TCK_SET (void) {
+ LPC_GPIO->SET[0] = (PIN_SWCLK);
+}
+
+/** SWCLK/TCK I/O pin: Set Output to Low.
+Set the SWCLK/TCK DAP hardware I/O pin to low level.
+*/
+static __forceinline void PIN_SWCLK_TCK_CLR (void) {
+ LPC_GPIO->CLR[0] = (PIN_SWCLK);
+}
+
+
+// SWDIO/TMS Pin I/O --------------------------------------
+
+/** SWDIO/TMS I/O pin: Get Input.
+\return Current status of the SWDIO/TMS DAP hardware I/O pin.
+*/
+static __forceinline uint32_t PIN_SWDIO_TMS_IN (void) {
+ return LPC_GPIO->B[PIN_SWDIO_IN_BIT] & 0x1;
+}
+
+/** SWDIO/TMS I/O pin: Set Output to High.
+Set the SWDIO/TMS DAP hardware I/O pin to high level.
+*/
+static __forceinline void PIN_SWDIO_TMS_SET (void) {
+ LPC_GPIO->SET[0] = (PIN_SWDIO);
+}
+
+/** SWDIO/TMS I/O pin: Set Output to Low.
+Set the SWDIO/TMS DAP hardware I/O pin to low level.
+*/
+static __forceinline void PIN_SWDIO_TMS_CLR (void) {
+ LPC_GPIO->CLR[0] = (PIN_SWDIO);
+}
+
+/** SWDIO I/O pin: Get Input (used in SWD mode only).
+\return Current status of the SWDIO DAP hardware I/O pin.
+*/
+static __forceinline uint32_t PIN_SWDIO_IN (void) {
+ return LPC_GPIO->B[PIN_SWDIO_IN_BIT] & 0x1;
+}
+
+/** SWDIO I/O pin: Set Output (used in SWD mode only).
+\param bit Output value for the SWDIO DAP hardware I/O pin.
+*/
+static __forceinline void PIN_SWDIO_OUT (uint32_t bit){
+ if (bit & 0x1)
+ LPC_GPIO->SET[0] = (PIN_SWDIO);
+ else
+ LPC_GPIO->CLR[0] = (PIN_SWDIO);
+}
+
+/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to output mode. This function is
+called prior \ref PIN_SWDIO_OUT function calls.
+*/
+static __forceinline void PIN_SWDIO_OUT_ENABLE (void) {
+ LPC_GPIO->DIR[0] |= (PIN_SWDIO);
+}
+
+/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
+Configure the SWDIO DAP hardware I/O pin to input mode. This function is
+called prior \ref PIN_SWDIO_IN function calls.
+*/
+static __forceinline void PIN_SWDIO_OUT_DISABLE (void) {
+ LPC_GPIO->DIR[0] &= ~(PIN_SWDIO);
+}
+
+
+// TDI Pin I/O ---------------------------------------------
+
+/** TDI I/O pin: Get Input.
+\return Current status of the TDI DAP hardware I/O pin.
+*/
+static __forceinline uint32_t PIN_TDI_IN (void) {
+#if (DAP_JTAG != 0)
+ return LPC_GPIO->B[PIN_TDI_IN_BIT] & 0x1;
+#else
+ return (0); // Not available
+#endif
+}
+
+/** TDI I/O pin: Set Output.
+\param bit Output value for the TDI DAP hardware I/O pin.
+*/
+static __forceinline void PIN_TDI_OUT (uint32_t bit) {
+#if (DAP_JTAG != 0)
+ if (bit & 0x1)
+ LPC_GPIO->SET[0] = (PIN_TDI);
+ else
+ LPC_GPIO->CLR[0] = (PIN_TDI);
+#else
+ ; // Not available
+#endif
+}
+
+
+// TDO Pin I/O ---------------------------------------------
+
+/** TDO I/O pin: Get Input.
+\return Current status of the TDO DAP hardware I/O pin.
+*/
+static __forceinline uint32_t PIN_TDO_IN (void) {
+#if (DAP_JTAG != 0)
+ return LPC_GPIO->B[PIN_TDO_IN_BIT] & 0x1;
+#else
+ return (0); // Not available
+#endif
+}
+
+
+// nTRST Pin I/O -------------------------------------------
+
+/** nTRST I/O pin: Get Input.
+\return Current status of the nTRST DAP hardware I/O pin.
+*/
+static __forceinline uint32_t PIN_nTRST_IN (void) {
+ return (0); // Not available
+}
+
+/** nTRST I/O pin: Set Output.
+\param bit JTAG TRST Test Reset pin status:
+ - 0: issue a JTAG TRST Test Reset.
+ - 1: release JTAG TRST Test Reset.
+*/
+static __forceinline void PIN_nTRST_OUT (uint32_t bit) {
+ ; // Not available
+}
+
+// nRESET Pin I/O------------------------------------------
+
+/** nRESET I/O pin: Get Input.
+\return Current status of the nRESET DAP hardware I/O pin.
+*/
+static __forceinline uint32_t PIN_nRESET_IN (void) {
+ return LPC_GPIO->B[PIN_nRESET_IN_BIT] & 0x1;
+}
+
+/** nRESET I/O pin: Set Output.
+\param bit target device hardware reset pin status:
+ - 0: issue a device hardware reset.
+ - 1: release device hardware reset.
+*/
+static __forceinline void PIN_nRESET_OUT (uint32_t bit) {
+#if defined(CONF_OPENDRAIN)
+ // open drain logic
+ if (bit) LPC_GPIO->DIR[0] &= ~PIN_nRESET; // input (pulled high external)
+ else LPC_GPIO->DIR[0] |= PIN_nRESET; // output (low)
+#else
+ if (bit)
+ LPC_GPIO->SET[0] = (PIN_nRESET);
+ else
+ LPC_GPIO->CLR[0] = (PIN_nRESET);
+#endif
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
+
+It is recommended to provide the following LEDs for status indication:
+ - Connect LED: is active when the DAP hardware is connected to a debugger.
+ - Running LED: is active when the debugger has put the target device into running state.
+*/
+
+/** Debug Unit: Set status of Connected LED.
+\param bit status of the Connect LED.
+ - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
+ - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
+*/
+static __inline void LED_CONNECTED_OUT (uint32_t bit) {
+}
+
+/** Debug Unit: Set status Target Running LED.
+\param bit status of the Target Running LED.
+ - 1: Target Running LED ON: program execution in target started.
+ - 0: Target Running LED OFF: program execution in target stopped.
+*/
+static __inline void LED_RUNNING_OUT (uint32_t bit) {
+ ; // Not available
+}
+
+///@}
+
+
+//**************************************************************************************************
+/**
+\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
+\ingroup DAP_ConfigIO_gr
+@{
+
+CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
+*/
+
+/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
+Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
+ - I/O clock system enabled.
+ - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
+ - for nTRST, nRESET a weak pull-up (if available) is enabled.
+ - LED output pins are enabled and LEDs are turned off.
+*/
+static __inline void DAP_SETUP (void) {
+ // Configure I/O pins
+ PIN_SWCLK_TCK_IOCON = FUNC_0 | PULL_UP_ENABLED; // SWCLK/TCK
+ PIN_SWDIO_TMS_IOCON = FUNC_0 | PULL_UP_ENABLED; // SWDIO/TMS
+#if !defined(CONF_OPENDRAIN)
+ PIN_nRESET_IOCON = FUNC_0 | PULL_UP_ENABLED; // nRESET
+#else
+ PIN_nRESET_IOCON = FUNC_0 | OPENDRAIN; // nRESET
+#endif
+#if (DAP_JTAG != 0)
+ PIN_TDI_IOCON = FUNC_0 | PULL_UP_ENABLED; // TDI
+ PIN_TDO_IOCON = FUNC_0 | PULL_UP_ENABLED; // TDO
+#endif
+}
+
+/** Reset Target Device with custom specific I/O pin or command sequence.
+This function allows the optional implementation of a device specific reset sequence.
+It is called when the command \ref DAP_ResetTarget and is for example required
+when a device needs a time-critical unlock sequence that enables the debug port.
+\return 0 = no device specific reset sequence is implemented.\n
+ 1 = a device specific reset sequence is implemented.
+*/
+static __inline uint32_t RESET_TARGET (void) {
+ return (0); // change to '1' when a device reset sequence is implemented
+}
+
+///@}
+
+
+#endif /* __DAP_CONFIG_H__ */
--- /dev/null
+\r
+/****************************************************************************************************//**\r
+ * @file LPC11Uxx.h\r
+ *\r
+ *\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for\r
+ * default LPC11Uxx Device Series\r
+ *\r
+ * @version V0.1\r
+ * @date 21. March 2011\r
+ *\r
+ * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45\r
+ *\r
+ * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,\r
+ * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40\r
+ *\r
+ *******************************************************************************************************/\r
+\r
+// ################################################################################\r
+// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000\r
+// ################################################################################\r
+\r
+/** @addtogroup NXP\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup LPC11Uxx\r
+ * @{\r
+ */\r
+\r
+#ifndef __LPC11UXX_H__\r
+#define __LPC11UXX_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #pragma anon_unions\r
+#endif\r
+\r
+ /* Interrupt Number Definition */\r
+\r
+typedef enum {\r
+// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------\r
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */\r
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
+// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------\r
+FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */\r
+ FLEX_INT1_IRQn = 1,\r
+ FLEX_INT2_IRQn = 2,\r
+ FLEX_INT3_IRQn = 3,\r
+ FLEX_INT4_IRQn = 4, \r
+ FLEX_INT5_IRQn = 5, \r
+ FLEX_INT6_IRQn = 6, \r
+ FLEX_INT7_IRQn = 7, \r
+ GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */\r
+ GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */\r
+ Reserved0_IRQn = 10, /*!< Reserved Interrupt */\r
+ Reserved1_IRQn = 11, \r
+ Reserved2_IRQn = 12, \r
+ Reserved3_IRQn = 13, \r
+ SSP1_IRQn = 14, /*!< SSP1 Interrupt */\r
+ I2C_IRQn = 15, /*!< I2C Interrupt */\r
+ TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */\r
+ TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */\r
+ TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */\r
+ TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */\r
+ SSP0_IRQn = 20, /*!< SSP0 Interrupt */\r
+ UART_IRQn = 21, /*!< UART Interrupt */\r
+ USB_IRQn = 22, /*!< USB IRQ Interrupt */\r
+ USB_FIQn = 23, /*!< USB FIQ Interrupt */\r
+ ADC_IRQn = 24, /*!< A/D Converter Interrupt */\r
+ WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ \r
+ BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */\r
+ FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */\r
+ Reserved4_IRQn = 28, /*!< Reserved Interrupt */\r
+ Reserved5_IRQn = 29, /*!< Reserved Interrupt */\r
+ USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */\r
+ Reserved6_IRQn = 31, /*!< Reserved Interrupt */\r
+} IRQn_Type;\r
+\r
+\r
+/** @addtogroup Configuration_of_CMSIS\r
+ * @{\r
+ */\r
+\r
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */\r
+\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+/** @} */ /* End of group Configuration_of_CMSIS */\r
+\r
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */\r
+#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */\r
+\r
+/** @addtogroup Device_Peripheral_Registers\r
+ * @{\r
+ */\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- I2C -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40000000) I2C Structure */\r
+ __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */\r
+ __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */\r
+ __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */\r
+ __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */\r
+ __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */\r
+ __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */\r
+ __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/\r
+ __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/\r
+ __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/\r
+ __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/\r
+ __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/\r
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */\r
+union{\r
+ __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */\r
+ struct{\r
+ __IO uint32_t MASK0;\r
+ __IO uint32_t MASK1;\r
+ __IO uint32_t MASK2;\r
+ __IO uint32_t MASK3;\r
+ };\r
+ };\r
+} LPC_I2C_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- WWDT -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40004000) WWDT Structure */\r
+ __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/\r
+ __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */\r
+ __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */\r
+ __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */\r
+ __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */\r
+ __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */\r
+ __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */\r
+} LPC_WWDT_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- USART -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40008000) USART Structure */\r
+ \r
+ union {\r
+ __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */\r
+ __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */\r
+ __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */\r
+ __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */\r
+ };\r
+ \r
+ union {\r
+ __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */\r
+ __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */\r
+ };\r
+ __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */\r
+ __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */\r
+ __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */\r
+ __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */\r
+ __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */\r
+ __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */\r
+ __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */\r
+ __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */\r
+ __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */\r
+ __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */\r
+ __I uint32_t RESERVED0[3];\r
+ __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */\r
+ __I uint32_t RESERVED1;\r
+ __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */\r
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */\r
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */\r
+ __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */\r
+ __IO uint32_t SYNCCTRL; \r
+} LPC_USART_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- Timer -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3 \r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */\r
+ __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */\r
+ __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */\r
+ __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */\r
+ __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */\r
+ __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */\r
+ __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */\r
+ union {\r
+ __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */\r
+ struct{\r
+ __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */\r
+ __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */\r
+ __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */\r
+ __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */\r
+ };\r
+ };\r
+ __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */\r
+ union{\r
+ __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */\r
+ struct{\r
+ __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */\r
+ __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */\r
+ __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */\r
+ __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */\r
+ };\r
+ };\r
+__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */\r
+ __I uint32_t RESERVED0[12];\r
+ __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */\r
+ __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */\r
+} LPC_CTxxBx_Type;\r
+\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- ADC -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */\r
+ __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */\r
+ __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */\r
+ __I uint32_t RESERVED0[1];\r
+ __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */\r
+ union{\r
+ __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/\r
+ struct{\r
+ __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/\r
+ __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/\r
+ __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/\r
+ __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/\r
+ __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/\r
+ __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/\r
+ __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/\r
+ __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/\r
+ };\r
+ };\r
+ __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */\r
+} LPC_ADC_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- PMU -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40038000) PMU Structure */\r
+ __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */\r
+ union{\r
+ __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */\r
+ struct{\r
+ __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */\r
+ __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */\r
+ __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */\r
+ __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */\r
+ };\r
+ };\r
+} LPC_PMU_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- FLASHCTRL -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */\r
+ __I uint32_t RESERVED0[4];\r
+ __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */\r
+ __I uint32_t RESERVED1[3];\r
+ __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */\r
+ __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */\r
+ __I uint32_t RESERVED2[1];\r
+ __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */\r
+ __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */\r
+ __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */\r
+ __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */\r
+ __I uint32_t RESERVED3[1001];\r
+ __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */\r
+ __I uint32_t RESERVED4[1];\r
+ __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */\r
+} LPC_FLASHCTRL_Type;\r
+\r
+\r
+#define FLASHCFG_20MHZ_CPU 0 /*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock*/\r
+#define FLASHCFG_40MHZ_CPU 1 /*!< Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock*/\r
+#define FLASHCFG_50MHZ_CPU 2 /*!< Flash accesses use 3 CPU clocks. Use for up to 50 MHz CPU clock*/\r
+\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- SSP0/1 -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40040000) SSP0 Structure */\r
+ __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */\r
+ __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */\r
+ __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */\r
+ __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */\r
+ __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */\r
+ __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */\r
+ __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */\r
+ __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */\r
+ __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */\r
+} LPC_SSPx_Type;\r
+\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- IOCONFIG -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */\r
+ __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */\r
+ __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */\r
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */\r
+ __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */\r
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */\r
+ __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */\r
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */\r
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */\r
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */\r
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */\r
+ __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */\r
+ __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */\r
+ __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */\r
+ __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */\r
+ __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */\r
+ __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */\r
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */\r
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */\r
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */\r
+ __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */\r
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */\r
+ __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */\r
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */\r
+ __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */\r
+ __IO uint32_t PIO1_0; /*!< Offset: 0x060 */\r
+ __IO uint32_t PIO1_1; \r
+ __IO uint32_t PIO1_2; \r
+ __IO uint32_t PIO1_3; \r
+ __IO uint32_t PIO1_4; /*!< Offset: 0x070 */\r
+ __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */\r
+ __IO uint32_t PIO1_6; \r
+ __IO uint32_t PIO1_7; \r
+ __IO uint32_t PIO1_8; /*!< Offset: 0x080 */\r
+ __IO uint32_t PIO1_9; \r
+ __IO uint32_t PIO1_10; \r
+ __IO uint32_t PIO1_11; \r
+ __IO uint32_t PIO1_12; /*!< Offset: 0x090 */\r
+ __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */\r
+ __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */\r
+ __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */\r
+ __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */\r
+ __IO uint32_t PIO1_17;\r
+ __IO uint32_t PIO1_18;\r
+ __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */\r
+ __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */\r
+ __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */\r
+ __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */\r
+ __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */\r
+ __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */\r
+ __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */\r
+ __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */\r
+ __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */\r
+ __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */\r
+ __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */\r
+ __IO uint32_t PIO1_30;\r
+ __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */\r
+} LPC_IOCON_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- SYSCON -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)\r
+ */\r
+\r
+typedef struct { //*!< (@ 0x40048000) SYSCON Structure\r
+ __IO uint32_t SYSMEMREMAP; /*!< System Memory remap register */\r
+ __IO uint32_t PRESETCTRL; /*!< Peripheral reset Control register */\r
+ __IO uint32_t SYSPLLCTRL; /*!< System PLL control register */\r
+ __I uint32_t SYSPLLSTAT; /*!< System PLL status register */\r
+ __IO uint32_t USBPLLCTRL; /*!< USB PLL control register, LPC11UXX only*/\r
+ __I uint32_t USBPLLSTAT; /*!< USB PLL status register, LPC11UXX only */\r
+ __I uint32_t RESERVED1[2];\r
+ __IO uint32_t SYSOSCCTRL; /*!< System Oscillator control register */\r
+ __IO uint32_t WDTOSCCTRL; /*!< Watchdog Oscillator control register */\r
+ __IO uint32_t IRCCTRL; /*!< IRC control register, not on LPC11UXX and LPC11EXX */\r
+ __IO uint32_t LFOSCCTRL; /*!< LF oscillator control, LPC11AXX only */\r
+ __IO uint32_t SYSRSTSTAT; /*!< System Reset Status register */\r
+ __I uint32_t RESERVED2[3];\r
+ __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select register */\r
+ __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable register*/\r
+ __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select register, LPC11UXX only */\r
+ __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable register, LPC11UXX only */\r
+ __I uint32_t RESERVED3[8];\r
+ __IO uint32_t MAINCLKSEL; /*!< Main clock source select register */\r
+ __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable register */\r
+ __IO uint32_t SYSAHBCLKDIV; /*!< System Clock divider register */\r
+ __I uint32_t RESERVED4;\r
+ __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control register */\r
+ __I uint32_t RESERVED5[4];\r
+ __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider register */\r
+ __IO uint32_t USARTCLKDIV; /*!< UART clock divider register */\r
+ __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider register, not on CHIP_LPC110X, CHIP_LPC11XXLV */\r
+ __I uint32_t RESERVED6[8];\r
+ __IO uint32_t USBCLKSEL; /*!< USB clock source select register, LPC11UXX only */\r
+ __IO uint32_t USBCLKUEN; /*!< USB clock source update enable register, LPC11UXX only */\r
+ __IO uint32_t USBCLKDIV; /*!< USB clock source divider register, LPC11UXX only */\r
+ __I uint32_t RESERVED7;\r
+ __IO uint32_t WDTCLKSEL; /*!< WDT clock source select register, some parts only */\r
+ __IO uint32_t WDTCLKUEN; /*!< WDT clock source update enable register, some parts only */\r
+ __IO uint32_t WDTCLKDIV; /*!< WDT clock divider register, some parts only */\r
+ __I uint32_t RESERVED8;\r
+ __IO uint32_t CLKOUTSEL; /*!< Clock out source select register, not on LPC1102/04 */\r
+ __IO uint32_t CLKOUTUEN; /*!< Clock out source update enable register, not on LPC1102/04 */\r
+ __IO uint32_t CLKOUTDIV; /*!< Clock out divider register, not on LPC1102/04 */\r
+ __I uint32_t RESERVED9[5];\r
+ __I uint32_t PIOPORCAP[2];/*!< POR captured PIO status registers, index 1 on LPC1102/04 */\r
+ __I uint32_t RESERVED10[18];\r
+ __IO uint32_t BODCTRL; /*!< Brown Out Detect register */\r
+ __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration register */\r
+ __I uint32_t RESERVED11[6];\r
+ __IO uint32_t IRQLATENCY; /*!< IRQ delay register, on LPC11UXX and LPC11EXX only */\r
+ __IO uint32_t NMISRC; /*!< NMI source control register,some parts only */\r
+ __IO uint32_t PINTSEL[8]; /*!< GPIO pin interrupt select register 0-7, not on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */\r
+ __IO uint32_t USBCLKCTRL; /*!< USB clock control register, LPC11UXX only */\r
+ __I uint32_t USBCLKST; /*!< USB clock status register, LPC11UXX only */\r
+ __I uint32_t RESERVED12[24];\r
+ __IO uint32_t STARTAPRP0; /*!< Start loigc 0 interrupt wake up enable register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */\r
+ __IO uint32_t STARTERP0; /*!< Start loigc signal enable register 0, not on LPC11AXX */\r
+ __IO uint32_t STARTRSRP0CLR; /*!< Start loigc reset register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */\r
+ __IO uint32_t STARTSRP0; /*!< Start loigc status register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */\r
+ __I uint32_t RESERVED13;\r
+ __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake up enable register 1, on LPC11UXX and LPC11EXX only */\r
+ __I uint32_t RESERVED14[6];\r
+ __IO uint32_t PDSLEEPCFG; /*!< Power down states in deep sleep mode register, not on LPC11AXX */\r
+ __IO uint32_t PDWAKECFG; /*!< Power down states in wake up from deep sleep register, not on LPC11AXX */\r
+ __IO uint32_t PDRUNCFG; /*!< Power configuration register*/\r
+ __I uint32_t RESERVED15[110];\r
+ __I uint32_t DEVICEID; /*!< Device ID register */\r
+ /*\r
+ __IO uint32_t SYSMEMREMAP; //!< (@ 0x40048000) System memory remap\r
+ __IO uint32_t PRESETCTRL; //!< (@ 0x40048004) Peripheral reset control\r
+ __IO uint32_t SYSPLLCTRL; //!< (@ 0x40048008) System PLL control\r
+ __I uint32_t SYSPLLSTAT; //!< (@ 0x4004800C) System PLL status\r
+ __IO uint32_t USBPLLCTRL; //!< (@ 0x40048010) USB PLL control\r
+ __I uint32_t USBPLLSTAT; //!< (@ 0x40048014) USB PLL status\r
+ __I uint32_t RESERVED0[2];\r
+ __IO uint32_t SYSOSCCTRL; //!< (@ 0x40048020) System oscillator control\r
+ __IO uint32_t WDTOSCCTRL; //!< (@ 0x40048024) Watchdog oscillator control\r
+ __I uint32_t RESERVED1[2];\r
+ __IO uint32_t SYSRSTSTAT; //!< (@ 0x40048030) System reset status register\r
+ __I uint32_t RESERVED2[3];\r
+ __IO uint32_t SYSPLLCLKSEL; //!< (@ 0x40048040) System PLL clock source select\r
+ __IO uint32_t SYSPLLCLKUEN; //!< (@ 0x40048044) System PLL clock source update enable\r
+ __IO uint32_t USBPLLCLKSEL; //!< (@ 0x40048048) USB PLL clock source select\r
+ __IO uint32_t USBPLLCLKUEN; //!< (@ 0x4004804C) USB PLL clock source update enable\r
+ __I uint32_t RESERVED3[8];\r
+ __IO uint32_t MAINCLKSEL; //!< (@ 0x40048070) Main clock source select\r
+ __IO uint32_t MAINCLKUEN; //!< (@ 0x40048074) Main clock source update enable\r
+ __IO uint32_t SYSAHBCLKDIV; //!< (@ 0x40048078) System clock divider\r
+ __I uint32_t RESERVED4[1];\r
+ __IO uint32_t SYSAHBCLKCTRL; //!< (@ 0x40048080) System clock control\r
+ __I uint32_t RESERVED5[4];\r
+ __IO uint32_t SSP0CLKDIV; //!< (@ 0x40048094) SSP0 clock divider\r
+ __IO uint32_t UARTCLKDIV; //!< (@ 0x40048098) UART clock divider\r
+ __IO uint32_t SSP1CLKDIV; //!< (@ 0x4004809C) SSP1 clock divider\r
+ __I uint32_t RESERVED6[8];\r
+ __IO uint32_t USBCLKSEL; //!< (@ 0x400480C0) USB clock source select\r
+ __IO uint32_t USBCLKUEN; //!< (@ 0x400480C4) USB clock source update enable\r
+ __IO uint32_t USBCLKDIV; //!< (@ 0x400480C8) USB clock source divider\r
+ __I uint32_t RESERVED7[5];\r
+ __IO uint32_t CLKOUTSEL; //!< (@ 0x400480E0) CLKOUT clock source select\r
+ __IO uint32_t CLKOUTUEN; //!< (@ 0x400480E4) CLKOUT clock source update enable\r
+ __IO uint32_t CLKOUTDIV; //!< (@ 0x400480E8) CLKOUT clock divider\r
+ __I uint32_t RESERVED8[5];\r
+ __I uint32_t PIOPORCAP0; //!< (@ 0x40048100) POR captured PIO status 0\r
+ __I uint32_t PIOPORCAP1; //!< (@ 0x40048104) POR captured PIO status 1\r
+ __I uint32_t RESERVED9[18];\r
+ __IO uint32_t BODCTRL; //!< (@ 0x40048150) Brown-Out Detect\r
+ __IO uint32_t SYSTCKCAL; //!< (@ 0x40048154) System tick counter calibration\r
+ __I uint32_t RESERVED10[6];\r
+ __IO uint32_t IRQLATENCY; //!< (@ 0x40048170) IQR delay\r
+ __IO uint32_t NMISRC; //!< (@ 0x40048174) NMI Source Control\r
+ __IO uint32_t PINTSEL[8]; //!< (@ 0x40048178) GPIO Pin Interrupt Select register 0\r
+ __IO uint32_t USBCLKCTRL; //!< (@ 0x40048198) USB clock control\r
+ __I uint32_t USBCLKST; //!< (@ 0x4004819C) USB clock status\r
+ __I uint32_t RESERVED11[25];\r
+ __IO uint32_t STARTERP0; //!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0\r
+ __I uint32_t RESERVED12[3];\r
+ __IO uint32_t STARTERP1; //!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1\r
+ __I uint32_t RESERVED13[6];\r
+ __IO uint32_t PDSLEEPCFG; //!< (@ 0x40048230) Power-down states in deep-sleep mode\r
+ __IO uint32_t PDAWAKECFG; //!< (@ 0x40048234) Power-down states for wake-up from deep-sleep\r
+ __IO uint32_t PDRUNCFG; //!< (@ 0x40048238) Power configuration register\r
+ __I uint32_t RESERVED14[110];\r
+ __I uint32_t DEVICE_ID; //!< (@ 0x400483F4) Device ID\r
+ */\r
+} LPC_SYSCON_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- GPIO_PIN_INT -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */\r
+ __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */\r
+ __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */\r
+ __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */\r
+ __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */\r
+ __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */\r
+ __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */\r
+ __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */\r
+ __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */\r
+ __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */\r
+ __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */\r
+} LPC_GPIO_PIN_INT_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- GPIO_GROUP_INT0/1 -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */\r
+ __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */\r
+ __I uint32_t RESERVED0[7];\r
+ __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */\r
+ __I uint32_t RESERVED1[6];\r
+ __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */\r
+} LPC_GPIO_GROUP_INTx_Type;\r
+\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- USB -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40080000) USB Structure */\r
+ __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */\r
+ __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */\r
+ __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */\r
+ __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */\r
+ __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */\r
+ __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */\r
+ __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */\r
+ __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */\r
+ __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */\r
+ __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */\r
+ __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */\r
+ __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */\r
+ __I uint32_t RESERVED0[1];\r
+ __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */\r
+} LPC_USB_Type;\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- GPIO_PORT -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)\r
+ */\r
+\r
+typedef struct { \r
+ union {\r
+ struct {\r
+ __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */\r
+ __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */\r
+ };\r
+ __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */\r
+ };\r
+ __I uint32_t RESERVED0[1008];\r
+ union {\r
+ struct {\r
+ __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */\r
+ __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */\r
+ };\r
+ __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */\r
+ };\r
+ uint32_t RESERVED1[960];\r
+ __IO uint32_t DIR[2]; /* 0x2000 */\r
+ uint32_t RESERVED2[30];\r
+ __IO uint32_t MASK[2]; /* 0x2080 */\r
+ uint32_t RESERVED3[30];\r
+ __IO uint32_t PIN[2]; /* 0x2100 */\r
+ uint32_t RESERVED4[30];\r
+ __IO uint32_t MPIN[2]; /* 0x2180 */\r
+ uint32_t RESERVED5[30];\r
+ __IO uint32_t SET[2]; /* 0x2200 */\r
+ uint32_t RESERVED6[30];\r
+ __O uint32_t CLR[2]; /* 0x2280 */\r
+ uint32_t RESERVED7[30];\r
+ __O uint32_t NOT[2]; /* 0x2300 */\r
+} LPC_GPIO_Type;\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #pragma no_anon_unions\r
+#endif\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- Peripheral memory map -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+#define LPC_I2C_BASE (0x40000000)\r
+#define LPC_WWDT_BASE (0x40004000)\r
+#define LPC_USART_BASE (0x40008000)\r
+#define LPC_CT16B0_BASE (0x4000C000)\r
+#define LPC_CT16B1_BASE (0x40010000)\r
+#define LPC_CT32B0_BASE (0x40014000)\r
+#define LPC_CT32B1_BASE (0x40018000)\r
+#define LPC_ADC_BASE (0x4001C000)\r
+#define LPC_PMU_BASE (0x40038000)\r
+#define LPC_FLASHCTRL_BASE (0x4003C000)\r
+#define LPC_SSP0_BASE (0x40040000)\r
+#define LPC_SSP1_BASE (0x40058000)\r
+#define LPC_IOCON_BASE (0x40044000)\r
+#define LPC_SYSCON_BASE (0x40048000)\r
+#define LPC_GPIO_PIN_INT_BASE (0x4004C000)\r
+#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)\r
+#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)\r
+#define LPC_USB_BASE (0x40080000)\r
+#define LPC_GPIO_BASE (0x50000000)\r
+\r
+\r
+// ------------------------------------------------------------------------------------------------\r
+// ----- Peripheral declaration -----\r
+// ------------------------------------------------------------------------------------------------\r
+\r
+#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)\r
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)\r
+#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)\r
+#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)\r
+#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)\r
+#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)\r
+#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)\r
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)\r
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)\r
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)\r
+#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)\r
+#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)\r
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)\r
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)\r
+#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)\r
+#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)\r
+#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)\r
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)\r
+#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)\r
+\r
+\r
+/** @} */ /* End of group Device_Peripheral_Registers */\r
+/** @} */ /* End of group (null) */\r
+/** @} */ /* End of group LPC11Uxx */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif \r
+\r
+\r
+#endif // __LPC11UXX_H__\r
--- /dev/null
+/*
+ * @brief Configuration file needed for USB ROM stack based applications.
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+#include "lpc_types.h"
+#include "error.h"
+#include "usbd_rom_api.h"
+
+#ifndef __APP_USB_CFG_H_
+#define __APP_USB_CFG_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @ingroup EXAMPLES_USBDROM_11UXX_HID_GENERIC
+ * @{
+ */
+
+/* HID In/Out Endpoint Address */
+#define HID_EP_IN 0x81
+#define HID_EP_OUT 0x01
+
+/* The following manifest constants are used to define this memory area to be used
+ by USBD ROM stack.
+ */
+#define USB_STACK_MEM_BASE 0x20004000
+#define USB_STACK_MEM_SIZE 0x0800
+
+/* Manifest constants used by USBD ROM stack. These values SHOULD NOT BE CHANGED
+ for advance features which require usage of USB_CORE_CTRL_T structure.
+ Since these are the values used for compiling USB stack.
+ */
+#define USB_MAX_IF_NUM 8 /*!< Max interface number used for building USBDL_Lib. DON'T CHANGE. */
+#define USB_MAX_EP_NUM 5 /*!< Max number of EP used for building USBD ROM. DON'T CHANGE. */
+#define USB_MAX_PACKET0 64 /*!< Max EP0 packet size used for building USBD ROM. DON'T CHANGE. */
+#define USB_FS_MAX_BULK_PACKET 64 /*!< MAXP for FS bulk EPs used for building USBD ROM. DON'T CHANGE. */
+#define USB_HS_MAX_BULK_PACKET 512 /*!< MAXP for HS bulk EPs used for building USBD ROM. DON'T CHANGE. */
+#define USB_DFU_XFER_SIZE 2048 /*!< Max DFU transfer size used for building USBD ROM. DON'T CHANGE. */
+
+/* USB descriptor arrays defined *_desc.c file */
+extern const uint8_t USB_DeviceDescriptor[];
+extern uint8_t USB_FsConfigDescriptor[];
+extern const uint8_t USB_StringDescriptor[];
+extern const uint8_t USB_DeviceQualifier[];
+
+// HID
+extern const uint8_t HID_ReportDescriptor[];
+extern const uint8_t hid_report_size;
+
+/**
+ * @brief Find the address of interface descriptor for given class type.
+ * @param pDesc : Pointer to configuration descriptor in which the desired class
+ * interface descriptor to be found.
+ * @param intfClass : Interface class type to be searched.
+ * @return If found returns the address of requested interface else returns NULL.
+ */
+extern USB_INTERFACE_DESCRIPTOR *find_IntfDesc(const uint8_t *pDesc, uint32_t intfClass);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APP_USB_CFG_H_ */
--- /dev/null
+/*
+ * compiler.h
+ *
+ * Created on: Jun 18, 2015
+ * Author: yliu
+ */
+
+#ifndef COMPILER_H_
+#define COMPILER_H_
+
+#if defined ( __GNUC__ )
+#define __ALWAYS_INLINE __attribute__((always_inline))
+#define __forceinline __ALWAYS_INLINE
+#define __weak __attribute__ ((weak))
+#endif
+
+
+
+#endif /* COMPILER_H_ */
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0.h\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version V3.20\r
+ * @date 25. February 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M0\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0_REV\r
+ #define __CM0_REV 0x0000\r
+ #warning "__CM0_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M0 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M0 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V3.20\r
+ * @date 25. February 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V3.20\r
+ * @date 05. March 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constrant "l"\r
+ * Otherwise, use general registers, specified by constrant "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32 - op2)); \r
+}\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/*
+ * @brief Error code returned by Boot ROM drivers/library functions
+ * @ingroup Common
+ *
+ * This file contains unified error codes to be used across driver,
+ * middleware, applications, hal and demo software.
+ *
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LPC_ERROR_H__
+#define __LPC_ERROR_H__
+
+/** Error code returned by Boot ROM drivers/library functions
+*
+* Error codes are a 32-bit value with :
+* - The 16 MSB contains the peripheral code number
+* - The 16 LSB contains an error code number associated to that peripheral
+*
+*/
+typedef enum
+{
+ /**\b 0x00000000*/ LPC_OK=0, /**< enum value returned on Success */
+ /**\b 0xFFFFFFFF*/ ERR_FAILED = -1, /**< enum value returned on general failure */
+ /**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2, /**< enum value returned on general timeout */
+ /**\b 0xFFFFFFFD*/ ERR_BUSY = -3, /**< enum value returned when resource is busy */
+
+ /* ISP related errors */
+ ERR_ISP_BASE = 0x00000000,
+ /*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1,
+ /*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */
+ /*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */
+ /*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED,
+ /*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED,
+ /*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */
+ /*0x00000007*/ ERR_ISP_INVALID_SECTOR,
+ /*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK,
+ /*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,
+ /*0x0000000A*/ ERR_ISP_COMPARE_ERROR,
+ /*0x0000000B*/ ERR_ISP_BUSY, /* Flash programming hardware interface is busy */
+ /*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */
+ /*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */
+ /*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED,
+ /*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */
+ /*0x00000010*/ ERR_ISP_INVALID_CODE, /* Unlock code is invalid */
+ /*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE,
+ /*0x00000012*/ ERR_ISP_INVALID_STOP_BIT,
+ /*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED,
+
+ /* ROM API related errors */
+ ERR_API_BASE = 0x00010000,
+ /**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1, /**< Invalid parameters*/
+ /**\b 0x00010002*/ ERR_API_INVALID_PARAM1, /**< PARAM1 is invalid */
+ /**\b 0x00010003*/ ERR_API_INVALID_PARAM2, /**< PARAM2 is invalid */
+ /**\b 0x00010004*/ ERR_API_INVALID_PARAM3, /**< PARAM3 is invalid */
+ /**\b 0x00010005*/ ERR_API_MOD_INIT, /**< API is called before module init */
+
+ /* SPIFI API related errors */
+ ERR_SPIFI_BASE = 0x00020000,
+ /*0x00020001*/ ERR_SPIFI_DEVICE_ERROR =ERR_SPIFI_BASE+1,
+ /*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR,
+ /*0x00020003*/ ERR_SPIFI_TIMEOUT,
+ /*0x00020004*/ ERR_SPIFI_OPERAND_ERROR,
+ /*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM,
+ /*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT,
+ /*0x00020007*/ ERR_SPIFI_UNKNOWN_ID,
+ /*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE,
+ /*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG,
+
+ /* Security API related errors */
+ ERR_SEC_BASE = 0x00030000,
+ /*0x00030001*/ ERR_SEC_AES_WRONG_CMD=ERR_SEC_BASE+1,
+ /*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED,
+ /*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,
+
+
+ /* USB device stack related errors */
+ ERR_USBD_BASE = 0x00040000,
+ /**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1, /**< invalid request */
+ /**\b 0x00040002*/ ERR_USBD_UNHANDLED, /**< Callback did not process the event */
+ /**\b 0x00040003*/ ERR_USBD_STALL, /**< Stall the endpoint on which the call back is called */
+ /**\b 0x00040004*/ ERR_USBD_SEND_ZLP, /**< Send ZLP packet on the endpoint on which the call back is called */
+ /**\b 0x00040005*/ ERR_USBD_SEND_DATA, /**< Send data packet on the endpoint on which the call back is called */
+ /**\b 0x00040006*/ ERR_USBD_BAD_DESC, /**< Bad descriptor*/
+ /**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC,/**< Bad config descriptor*/
+ /**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC,/**< Bad interface descriptor*/
+ /**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/
+ /**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF, /**< Bad alignment of buffer passed. */
+ /**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR, /**< Too many class handlers. */
+
+ /* CGU related errors */
+ ERR_CGU_BASE = 0x00050000,
+ /*0x00050001*/ ERR_CGU_NOT_IMPL=ERR_CGU_BASE+1,
+ /*0x00050002*/ ERR_CGU_INVALID_PARAM,
+ /*0x00050003*/ ERR_CGU_INVALID_SLICE,
+ /*0x00050004*/ ERR_CGU_OUTPUT_GEN,
+ /*0x00050005*/ ERR_CGU_DIV_SRC,
+ /*0x00050006*/ ERR_CGU_DIV_VAL,
+ /*0x00050007*/ ERR_CGU_SRC
+
+} ErrorCode_t;
+
+
+#ifndef offsetof
+#define offsetof(s,m) (int)&(((s *)0)->m)\r
+#endif\r
+
+#define COMPILE_TIME_ASSERT(pred) switch(0){case 0:case pred:;}
+
+#endif /* __LPC_ERROR_H__ */
--- /dev/null
+/*\r
+ * @brief Common types used in LPC functions\r
+ *\r
+ * @note\r
+ * Copyright(C) NXP Semiconductors, 2012\r
+ * All rights reserved.\r
+ *\r
+ * @par\r
+ * Software that is described herein is for illustrative purposes only\r
+ * which provides customers with programming information regarding the\r
+ * LPC products. This software is supplied "AS IS" without any warranties of\r
+ * any kind, and NXP Semiconductors and its licensor disclaim any and\r
+ * all warranties, express or implied, including all implied warranties of\r
+ * merchantability, fitness for a particular purpose and non-infringement of\r
+ * intellectual property rights. NXP Semiconductors assumes no responsibility\r
+ * or liability for the use of the software, conveys no license or rights under any\r
+ * patent, copyright, mask work right, or any other intellectual property rights in\r
+ * or to any products. NXP Semiconductors reserves the right to make changes\r
+ * in the software without notification. NXP Semiconductors also makes no\r
+ * representation or warranty that such application will be suitable for the\r
+ * specified use without further testing or modification.\r
+ *\r
+ * @par\r
+ * Permission to use, copy, modify, and distribute this software and its\r
+ * documentation is hereby granted, under NXP Semiconductors' and its\r
+ * licensor's relevant copyrights in the software, without fee, provided that it\r
+ * is used in conjunction with NXP Semiconductors microcontrollers. This\r
+ * copyright, permission, and disclaimer notice must appear in all copies of\r
+ * this code.\r
+ */\r
+\r
+#ifndef __LPC_TYPES_H_\r
+#define __LPC_TYPES_H_\r
+\r
+#include <stdint.h>\r
+#include <stdbool.h>\r
+\r
+/** @defgroup LPC_Types CHIP: LPC Common Types\r
+ * @ingroup CHIP_Common\r
+ * @{\r
+ */\r
+\r
+/** @defgroup LPC_Types_Public_Types LPC Public Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Boolean Type definition\r
+ */\r
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;\r
+\r
+/**\r
+ * @brief Boolean Type definition\r
+ */\r
+#if !defined(__cplusplus)\r
+// typedef enum {false = 0, true = !false} bool;\r
+#endif\r
+\r
+/**\r
+ * @brief Flag Status and Interrupt Flag Status type definition\r
+ */\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;\r
+#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))\r
+\r
+/**\r
+ * @brief Functional State Definition\r
+ */\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))\r
+\r
+/**\r
+ * @ Status type definition\r
+ */\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;\r
+\r
+/**\r
+ * Read/Write transfer type mode (Block or non-block)\r
+ */\r
+typedef enum {\r
+ NONE_BLOCKING = 0, /**< None Blocking type */\r
+ BLOCKING, /**< Blocking type */\r
+} TRANSFER_BLOCK_T;\r
+\r
+/** Pointer to Function returning Void (any number of parameters) */\r
+typedef void (*PFV)();\r
+\r
+/** Pointer to Function returning int32_t (any number of parameters) */\r
+typedef int32_t (*PFI)();\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LPC_Types_Public_Macros LPC Public Macros\r
+ * @{\r
+ */\r
+\r
+/* _BIT(n) sets the bit at position "n"\r
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:\r
+ * e.g., "(_BIT(3) | _BIT(7))".\r
+ */\r
+#undef _BIT\r
+/* Set bit macro */\r
+#define _BIT(n) (1 << (n))\r
+\r
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".\r
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:\r
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"\r
+ */\r
+#undef _SBF\r
+/* Set bit field macro */\r
+#define _SBF(f, v) ((v) << (f))\r
+\r
+/* _BITMASK constructs a symbol with 'field_width' least significant\r
+ * bits set.\r
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF\r
+ * The symbol is intended to be used to limit the bit field width\r
+ * thusly:\r
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.\r
+ * If "any_expression" results in a value that is larger than can be\r
+ * contained in 'x' bits, the bits above 'x - 1' are masked off. When\r
+ * used with the _SBF example above, the example would be written:\r
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))\r
+ * This ensures that the value written to a_reg is no wider than\r
+ * 16 bits, and makes the code easier to read and understand.\r
+ */\r
+#undef _BITMASK\r
+/* Bitmask creation macro */\r
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)\r
+\r
+/* NULL pointer */\r
+#ifndef NULL\r
+#define NULL ((void *) 0)\r
+#endif\r
+\r
+/* Number of elements in an array */\r
+#define NELEMENTS(array) (sizeof(array) / sizeof(array[0]))\r
+\r
+/* Static data/function define */\r
+#define STATIC static\r
+/* External data/function define */\r
+#define EXTERN extern\r
+\r
+#if !defined(MAX)\r
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+#endif\r
+#if !defined(MIN)\r
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Old Type Definition compatibility */\r
+/** @addtogroup LPC_Types_Public_Types\r
+ * @{\r
+ */\r
+\r
+/** LPC type for character type */\r
+typedef char CHAR;\r
+\r
+/** LPC type for 8 bit unsigned value */\r
+typedef uint8_t UNS_8;\r
+\r
+/** LPC type for 8 bit signed value */\r
+typedef int8_t INT_8;\r
+\r
+/** LPC type for 16 bit unsigned value */\r
+typedef uint16_t UNS_16;\r
+\r
+/** LPC type for 16 bit signed value */\r
+typedef int16_t INT_16;\r
+\r
+/** LPC type for 32 bit unsigned value */\r
+typedef uint32_t UNS_32;\r
+\r
+/** LPC type for 32 bit signed value */\r
+typedef int32_t INT_32;\r
+\r
+/** LPC type for 64 bit signed value */\r
+typedef int64_t INT_64;\r
+\r
+/** LPC type for 64 bit unsigned value */\r
+typedef uint64_t UNS_64;\r
+\r
+#ifdef __CODE_RED\r
+#define BOOL_32 bool\r
+#define BOOL_16 bool\r
+#define BOOL_8 bool\r
+#else\r
+/** 32 bit boolean type */\r
+typedef bool BOOL_32;\r
+\r
+/** 16 bit boolean type */\r
+typedef bool BOOL_16;\r
+\r
+/** 8 bit boolean type */\r
+typedef bool BOOL_8;\r
+#endif\r
+\r
+#ifdef __CC_ARM\r
+#define INLINE __inline\r
+#else\r
+#define INLINE inline\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __LPC_TYPES_H_ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_LPC11Uxx.h\r
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File\r
+ * for the NXP LPC11Uxx Device Series\r
+ * @version V1.10\r
+ * @date 24. November 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_LPC11Uxx_H\r
+#define __SYSTEM_LPC11Uxx_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemCoreClock variable.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Updates the SystemCoreClock with current core Clock \r
+ * retrieved from cpu registers.\r
+ */\r
+extern void SystemCoreClockUpdate (void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SYSTEM_LPC11Uxx_H */\r
--- /dev/null
+/*
+ * uart.h
+ *
+ * Created on: Jun 26, 2015
+ * Author: yliu
+ */
+
+#ifndef UART_H_
+#define UART_H_
+
+
+
+#endif /* UART_H_ */
--- /dev/null
+/*
+ * usb_driver.h
+ *
+ * Created on: Jun 18, 2015
+ * Author: yliu
+ */
+
+#ifndef USB_DRIVER_H_
+#define USB_DRIVER_H_
+
+
+#include "app_usbd_cfg.h"
+#include "usbd_rom_api.h"
+
+
+typedef struct {
+ const uint32_t usbdApiBase; /*!< USBD API function table base address */
+ const uint32_t reserved0; /*!< Reserved */
+ const uint32_t candApiBase; /*!< CAN API function table base address */
+ const uint32_t pwrApiBase; /*!< Power API function table base address */
+ const uint32_t reserved1; /*!< Reserved */
+ const uint32_t reserved2; /*!< Reserved */
+ const uint32_t reserved3; /*!< Reserved */
+ const uint32_t reserved4; /*!< Reserved */
+} LPC_ROM_API_T;
+
+
+
+#define LPC_ROM_API_BASE_LOC 0x1FFF1FF8
+#define LPC_ROM_API (*((LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC))
+
+
+typedef ErrorCode_t (*HID_GetReport_Func_T)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length);
+typedef ErrorCode_t (*HID_SetReport_Func_T)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);
+typedef ErrorCode_t (*HID_EpIn_Hdlr_Func_T) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
+typedef ErrorCode_t (*HID_EpOut_Hdlr_Func_T) (USBD_HANDLE_T hUsb, void* data, uint32_t event);
+
+void init_usb_clock ();
+void init_usb_power ();
+int init_usb_driver (USBD_API_INIT_PARAM_T *usb_param);
+int init_usb_hid (USBD_API_INIT_PARAM_T *usb_param,
+ HID_GetReport_Func_T getreport_fun, HID_SetReport_Func_T setreport_fun,
+ HID_EpIn_Hdlr_Func_T epin_hdlr_fun, HID_EpOut_Hdlr_Func_T epout_hdlr_fun,
+ uint8_t** report_saddr, int report_size);
+
+void connect_to_usb_bus ();
+void disconnect_to_usb_bus ();
+
+
+extern USBD_HANDLE_T g_usb_hnd;
+
+
+#endif /* USB_DRIVER_H_ */
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd.h 575 2012-11-20 01:35:56Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* USB Definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+#ifndef __USBD_H__\r
+#define __USBD_H__\r
+\r
+/** \file\r
+ * \brief Common definitions and declarations for the USB stack.\r
+ *\r
+ * Common definitions and declarations for the USB stack.\r
+ * \addtogroup USBD_Core \r
+ * @{\r
+ */\r
+\r
+#include "lpc_types.h"\r
+\r
+#if defined(__GNUC__)\r
+/* As per http://gcc.gnu.org/onlinedocs/gcc/Attribute-Syntax.html#Attribute-Syntax,\r
+6.29 Attributes Syntax\r
+"An attribute specifier list may appear as part of a struct, union or\r
+enum specifier. It may go either immediately after the struct, union\r
+or enum keyword, or after the closing brace. The former syntax is\r
+preferred. Where attribute specifiers follow the closing brace, they\r
+are considered to relate to the structure, union or enumerated type\r
+defined, not to any enclosing declaration the type specifier appears\r
+in, and the type defined is not complete until after the attribute\r
+specifiers."\r
+So use POST_PACK immediately after struct keyword\r
+*/\r
+#define PRE_PACK\r
+#define POST_PACK __attribute__((__packed__))\r
+#define ALIGNED(n) __attribute__((aligned (n)))\r
+\r
+#elif defined(__arm)\r
+#define PRE_PACK __packed\r
+#define POST_PACK\r
+#define ALIGNED(n) __align(n)\r
+\r
+#elif defined(__ICCARM__)\r
+#define PRE_PACK __packed\r
+#define POST_PACK\r
+#define PRAGMA_ALIGN_4096 _Pragma("data_alignment=4096")\r
+#define PRAGMA_ALIGN_2048 _Pragma("data_alignment=2048")\r
+#define PRAGMA_ALIGN_256 _Pragma("data_alignment=256")\r
+#define PRAGMA_ALIGN_128 _Pragma("data_alignment=128")\r
+#define PRAGMA_ALIGN_64 _Pragma("data_alignment=64")\r
+#define PRAGMA_ALIGN_48 _Pragma("data_alignment=48")\r
+#define PRAGMA_ALIGN_32 _Pragma("data_alignment=32")\r
+#define PRAGMA_ALIGN_4 _Pragma("data_alignment=4")\r
+#define ALIGNED(n) PRAGMA_ALIGN_##n\r
+\r
+#pragma diag_suppress=Pe021\r
+#endif\r
+\r
+/** Structure to pack lower and upper byte to form 16 bit word. */\r
+PRE_PACK struct POST_PACK _WB_T\r
+{\r
+ uint8_t L; /**< lower byte */\r
+ uint8_t H; /**< upper byte */\r
+};\r
+/** Structure to pack lower and upper byte to form 16 bit word.*/\r
+typedef struct _WB_T WB_T;\r
+\r
+/** Union of \ref _WB_T struct and 16 bit word.*/\r
+PRE_PACK union POST_PACK __WORD_BYTE\r
+{\r
+ uint16_t W; /**< data member to do 16 bit access */\r
+ WB_T WB; /**< data member to do 8 bit access */\r
+} ;\r
+/** Union of \ref _WB_T struct and 16 bit word.*/\r
+typedef union __WORD_BYTE WORD_BYTE;\r
+\r
+/** bmRequestType.Dir defines \r
+ * @{ \r
+ */\r
+/** Request from host to device */\r
+#define REQUEST_HOST_TO_DEVICE 0\r
+/** Request from device to host */\r
+#define REQUEST_DEVICE_TO_HOST 1\r
+/** @} */\r
+\r
+/** bmRequestType.Type defines \r
+ * @{ \r
+ */\r
+/** Standard Request */\r
+#define REQUEST_STANDARD 0\r
+/** Class Request */\r
+#define REQUEST_CLASS 1\r
+/** Vendor Request */\r
+#define REQUEST_VENDOR 2\r
+/** Reserved Request */\r
+#define REQUEST_RESERVED 3\r
+/** @} */\r
+\r
+/** bmRequestType.Recipient defines \r
+ * @{ \r
+ */\r
+/** Request to device */\r
+#define REQUEST_TO_DEVICE 0\r
+/** Request to interface */\r
+#define REQUEST_TO_INTERFACE 1\r
+/** Request to endpoint */\r
+#define REQUEST_TO_ENDPOINT 2\r
+/** Request to other */\r
+#define REQUEST_TO_OTHER 3\r
+/** @} */\r
+\r
+/** Structure to define 8 bit USB request.*/\r
+PRE_PACK struct POST_PACK _BM_T\r
+{\r
+ uint8_t Recipient : 5; /**< Recipient type. */\r
+ uint8_t Type : 2; /**< Request type. */\r
+ uint8_t Dir : 1; /**< Direction type. */\r
+};\r
+/** Structure to define 8 bit USB request.*/\r
+typedef struct _BM_T BM_T;\r
+\r
+/** Union of \ref _BM_T struct and 8 bit byte.*/\r
+PRE_PACK union POST_PACK _REQUEST_TYPE\r
+{\r
+ uint8_t B; /**< byte wide access memeber */\r
+ BM_T BM; /**< bitfield structure access memeber */\r
+} ;\r
+/** Union of \ref _BM_T struct and 8 bit byte.*/\r
+typedef union _REQUEST_TYPE REQUEST_TYPE;\r
+\r
+/** USB Standard Request Codes \r
+ * @{ \r
+ */\r
+/** GET_STATUS request */\r
+#define USB_REQUEST_GET_STATUS 0\r
+/** CLEAR_FEATURE request */\r
+#define USB_REQUEST_CLEAR_FEATURE 1\r
+/** SET_FEATURE request */\r
+#define USB_REQUEST_SET_FEATURE 3\r
+/** SET_ADDRESS request */\r
+#define USB_REQUEST_SET_ADDRESS 5\r
+/** GET_DESCRIPTOR request */\r
+#define USB_REQUEST_GET_DESCRIPTOR 6\r
+/** SET_DESCRIPTOR request */\r
+#define USB_REQUEST_SET_DESCRIPTOR 7\r
+/** GET_CONFIGURATION request */\r
+#define USB_REQUEST_GET_CONFIGURATION 8\r
+/** SET_CONFIGURATION request */\r
+#define USB_REQUEST_SET_CONFIGURATION 9\r
+/** GET_INTERFACE request */\r
+#define USB_REQUEST_GET_INTERFACE 10\r
+/** SET_INTERFACE request */\r
+#define USB_REQUEST_SET_INTERFACE 11\r
+/** SYNC_FRAME request */\r
+#define USB_REQUEST_SYNC_FRAME 12\r
+/** @} */\r
+\r
+/** USB GET_STATUS Bit Values \r
+ * @{ \r
+ */\r
+/** SELF_POWERED status*/\r
+#define USB_GETSTATUS_SELF_POWERED 0x01\r
+/** REMOTE_WAKEUP capable status*/\r
+#define USB_GETSTATUS_REMOTE_WAKEUP 0x02\r
+/** ENDPOINT_STALL status*/\r
+#define USB_GETSTATUS_ENDPOINT_STALL 0x01\r
+/** @} */\r
+\r
+/** USB Standard Feature selectors \r
+ * @{ \r
+ */\r
+/** ENDPOINT_STALL feature*/\r
+#define USB_FEATURE_ENDPOINT_STALL 0\r
+/** REMOTE_WAKEUP feature*/\r
+#define USB_FEATURE_REMOTE_WAKEUP 1\r
+/** TEST_MODE feature*/\r
+#define USB_FEATURE_TEST_MODE 2\r
+/** @} */\r
+\r
+/** USB Default Control Pipe Setup Packet*/\r
+PRE_PACK struct POST_PACK _USB_SETUP_PACKET\r
+{\r
+ REQUEST_TYPE bmRequestType; /**< This bitmapped field identifies the characteristics\r
+ of the specific request. \sa _BM_T.\r
+ */\r
+ uint8_t bRequest; /**< This field specifies the particular request. The \r
+ Type bits in the bmRequestType field modify the meaning \r
+ of this field. \sa USBD_REQUEST.\r
+ */\r
+ WORD_BYTE wValue; /**< Used to pass a parameter to the device, specific\r
+ to the request.\r
+ */\r
+ WORD_BYTE wIndex; /**< Used to pass a parameter to the device, specific\r
+ to the request. The wIndex field is often used in \r
+ requests to specify an endpoint or an interface.\r
+ */\r
+ uint16_t wLength; /**< This field specifies the length of the data \r
+ transferred during the second phase of the control \r
+ transfer.\r
+ */\r
+} ;\r
+/** USB Default Control Pipe Setup Packet*/\r
+typedef struct _USB_SETUP_PACKET USB_SETUP_PACKET;\r
+\r
+\r
+/** USB Descriptor Types \r
+ * @{ \r
+ */\r
+/** Device descriptor type */\r
+#define USB_DEVICE_DESCRIPTOR_TYPE 1\r
+/** Configuration descriptor type */\r
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2\r
+/** String descriptor type */\r
+#define USB_STRING_DESCRIPTOR_TYPE 3\r
+/** Interface descriptor type */\r
+#define USB_INTERFACE_DESCRIPTOR_TYPE 4\r
+/** Endpoint descriptor type */\r
+#define USB_ENDPOINT_DESCRIPTOR_TYPE 5\r
+/** Device qualifier descriptor type */\r
+#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6\r
+/** Other speed configuration descriptor type */\r
+#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7\r
+/** Interface power descriptor type */\r
+#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8\r
+/** OTG descriptor type */\r
+#define USB_OTG_DESCRIPTOR_TYPE 9\r
+/** Debug descriptor type */\r
+#define USB_DEBUG_DESCRIPTOR_TYPE 10\r
+/** Interface association descriptor type */\r
+#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11\r
+/** @} */\r
+\r
+/** USB Device Classes \r
+ * @{ \r
+ */\r
+/** Reserved device class */\r
+#define USB_DEVICE_CLASS_RESERVED 0x00\r
+/** Audio device class */\r
+#define USB_DEVICE_CLASS_AUDIO 0x01\r
+/** Communications device class */\r
+#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02\r
+/** Human interface device class */\r
+#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03\r
+/** monitor device class */\r
+#define USB_DEVICE_CLASS_MONITOR 0x04\r
+/** physical interface device class */\r
+#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05\r
+/** power device class */\r
+#define USB_DEVICE_CLASS_POWER 0x06\r
+/** Printer device class */\r
+#define USB_DEVICE_CLASS_PRINTER 0x07\r
+/** Storage device class */\r
+#define USB_DEVICE_CLASS_STORAGE 0x08\r
+/** Hub device class */\r
+#define USB_DEVICE_CLASS_HUB 0x09\r
+/** miscellaneous device class */\r
+#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEF\r
+/** Application device class */\r
+#define USB_DEVICE_CLASS_APP 0xFE\r
+/** Vendor specific device class */\r
+#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF\r
+/** @} */\r
+\r
+/** bmAttributes in Configuration Descriptor \r
+ * @{ \r
+ */\r
+/** Power field mask */\r
+#define USB_CONFIG_POWERED_MASK 0x40\r
+/** Bus powered */\r
+#define USB_CONFIG_BUS_POWERED 0x80\r
+/** Self powered */\r
+#define USB_CONFIG_SELF_POWERED 0xC0\r
+/** remote wakeup */\r
+#define USB_CONFIG_REMOTE_WAKEUP 0x20\r
+/** @} */\r
+\r
+/** bMaxPower in Configuration Descriptor */\r
+#define USB_CONFIG_POWER_MA(mA) ((mA)/2)\r
+\r
+/** bEndpointAddress in Endpoint Descriptor \r
+ * @{ \r
+ */\r
+/** Endopint address mask */\r
+#define USB_ENDPOINT_DIRECTION_MASK 0x80\r
+/** Macro to convert OUT endopint number to endpoint address value. */\r
+#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00)\r
+/** Macro to convert IN endopint number to endpoint address value. */\r
+#define USB_ENDPOINT_IN(addr) ((addr) | 0x80)\r
+/** @} */\r
+\r
+/** bmAttributes in Endpoint Descriptor \r
+ * @{ \r
+ */\r
+/** Endopint type mask */\r
+#define USB_ENDPOINT_TYPE_MASK 0x03\r
+/** Control Endopint type */\r
+#define USB_ENDPOINT_TYPE_CONTROL 0x00\r
+/** isochronous Endopint type */\r
+#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01\r
+/** bulk Endopint type */\r
+#define USB_ENDPOINT_TYPE_BULK 0x02\r
+/** interrupt Endopint type */\r
+#define USB_ENDPOINT_TYPE_INTERRUPT 0x03\r
+/** Endopint sync type mask */\r
+#define USB_ENDPOINT_SYNC_MASK 0x0C\r
+/** no synchronization Endopint */\r
+#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00\r
+/** Asynchronous sync Endopint */\r
+#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04\r
+/** Adaptive sync Endopint */\r
+#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08\r
+/** Synchronous sync Endopint */\r
+#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C\r
+/** Endopint usage type mask */\r
+#define USB_ENDPOINT_USAGE_MASK 0x30\r
+/** Endopint data usage type */\r
+#define USB_ENDPOINT_USAGE_DATA 0x00\r
+/** Endopint feedback usage type */\r
+#define USB_ENDPOINT_USAGE_FEEDBACK 0x10\r
+/** Endopint implicit feedback usage type */\r
+#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20\r
+/** Endopint reserved usage type */\r
+#define USB_ENDPOINT_USAGE_RESERVED 0x30\r
+/** @} */\r
+\r
+/** Control endopint EP0's maximum packet size in high-speed mode.*/\r
+#define USB_ENDPOINT_0_HS_MAXP 64\r
+/** Control endopint EP0's maximum packet size in low-speed mode.*/\r
+#define USB_ENDPOINT_0_LS_MAXP 8\r
+/** Bulk endopint's maximum packet size in high-speed mode.*/\r
+#define USB_ENDPOINT_BULK_HS_MAXP 512\r
+\r
+/** USB Standard Device Descriptor */\r
+PRE_PACK struct POST_PACK _USB_DEVICE_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes. */\r
+ uint8_t bDescriptorType; /**< DEVICE Descriptor Type. */\r
+ uint16_t bcdUSB; /**< BUSB Specification Release Number in\r
+ Binary-Coded Decimal (i.e., 2.10 is 210H).\r
+ This field identifies the release of the USB\r
+ Specification with which the device and its\r
+ descriptors are compliant.\r
+ */\r
+ uint8_t bDeviceClass; /**< Class code (assigned by the USB-IF).\r
+ If this field is reset to zero, each interface\r
+ within a configuration specifies its own\r
+ class information and the various\r
+ interfaces operate independently.\n\r
+ If this field is set to a value between 1 and\r
+ FEH, the device supports different class\r
+ specifications on different interfaces and\r
+ the interfaces may not operate\r
+ independently. This value identifies the\r
+ class definition used for the aggregate\r
+ interfaces. \n\r
+ If this field is set to FFH, the device class\r
+ is vendor-specific.\r
+ */\r
+ uint8_t bDeviceSubClass; /**< Subclass code (assigned by the USB-IF).\r
+ These codes are qualified by the value of\r
+ the bDeviceClass field. \n\r
+ If the bDeviceClass field is reset to zero,\r
+ this field must also be reset to zero. \n\r
+ If the bDeviceClass field is not set to FFH,\r
+ all values are reserved for assignment by\r
+ the USB-IF. \r
+ */\r
+ uint8_t bDeviceProtocol; /**< Protocol code (assigned by the USB-IF).\r
+ These codes are qualified by the value of\r
+ the bDeviceClass and the\r
+ bDeviceSubClass fields. If a device\r
+ supports class-specific protocols on a\r
+ device basis as opposed to an interface\r
+ basis, this code identifies the protocols\r
+ that the device uses as defined by the\r
+ specification of the device class. \n\r
+ If this field is reset to zero, the device\r
+ does not use class-specific protocols on a\r
+ device basis. However, it may use classspecific\r
+ protocols on an interface basis. \n\r
+ If this field is set to FFH, the device uses a\r
+ vendor-specific protocol on a device basis. \r
+ */\r
+ uint8_t bMaxPacketSize0; /**< Maximum packet size for endpoint zero\r
+ (only 8, 16, 32, or 64 are valid). For HS devices\r
+ is fixed to 64.\r
+ */\r
+\r
+ uint16_t idVendor; /**< Vendor ID (assigned by the USB-IF). */\r
+ uint16_t idProduct; /**< Product ID (assigned by the manufacturer). */\r
+ uint16_t bcdDevice; /**< Device release number in binary-coded decimal. */\r
+ uint8_t iManufacturer; /**< Index of string descriptor describing manufacturer. */\r
+ uint8_t iProduct; /**< Index of string descriptor describing product. */\r
+ uint8_t iSerialNumber; /**< Index of string descriptor describing the device\92s \r
+ serial number.\r
+ */\r
+ uint8_t bNumConfigurations; /**< Number of possible configurations. */\r
+} ;\r
+/** USB Standard Device Descriptor */\r
+typedef struct _USB_DEVICE_DESCRIPTOR USB_DEVICE_DESCRIPTOR;\r
+\r
+/** USB 2.0 Device Qualifier Descriptor */\r
+PRE_PACK struct POST_PACK _USB_DEVICE_QUALIFIER_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of descriptor */\r
+ uint8_t bDescriptorType; /**< Device Qualifier Type */\r
+ uint16_t bcdUSB; /**< USB specification version number (e.g., 0200H for V2.00) */\r
+ uint8_t bDeviceClass; /**< Class Code */\r
+ uint8_t bDeviceSubClass; /**< SubClass Code */\r
+ uint8_t bDeviceProtocol; /**< Protocol Code */\r
+ uint8_t bMaxPacketSize0; /**< Maximum packet size for other speed */\r
+ uint8_t bNumConfigurations; /**< Number of Other-speed Configurations */\r
+ uint8_t bReserved; /**< Reserved for future use, must be zero */\r
+} ;\r
+/** USB 2.0 Device Qualifier Descriptor */\r
+typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR USB_DEVICE_QUALIFIER_DESCRIPTOR;\r
+\r
+/** USB Standard Configuration Descriptor */\r
+PRE_PACK struct POST_PACK _USB_CONFIGURATION_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /**< CONFIGURATION Descriptor Type*/\r
+ uint16_t wTotalLength; /**< Total length of data returned for this\r
+ configuration. Includes the combined length\r
+ of all descriptors (configuration, interface,\r
+ endpoint, and class- or vendor-specific)\r
+ returned for this configuration.*/\r
+ uint8_t bNumInterfaces; /**< Number of interfaces supported by this configuration*/\r
+ uint8_t bConfigurationValue; /**< Value to use as an argument to the\r
+ SetConfiguration() request to select this \r
+ configuration. */\r
+ uint8_t iConfiguration; /**< Index of string descriptor describing this\r
+ configuration*/\r
+ uint8_t bmAttributes; /**< Configuration characteristics \n\r
+ D7: Reserved (set to one)\n\r
+ D6: Self-powered \n\r
+ D5: Remote Wakeup \n\r
+ D4...0: Reserved (reset to zero) \n\r
+ D7 is reserved and must be set to one for\r
+ historical reasons. \n\r
+ A device configuration that uses power from\r
+ the bus and a local source reports a non-zero\r
+ value in bMaxPower to indicate the amount of\r
+ bus power required and sets D6. The actual\r
+ power source at runtime may be determined\r
+ using the GetStatus(DEVICE) request (see\r
+ USB 2.0 spec Section 9.4.5). \n\r
+ If a device configuration supports remote\r
+ wakeup, D5 is set to one.*/\r
+ uint8_t bMaxPower; /**< Maximum power consumption of the USB\r
+ device from the bus in this specific\r
+ configuration when the device is fully\r
+ operational. Expressed in 2 mA units\r
+ (i.e., 50 = 100 mA). \n\r
+ Note: A device configuration reports whether\r
+ the configuration is bus-powered or selfpowered.\r
+ Device status reports whether the\r
+ device is currently self-powered. If a device is\r
+ disconnected from its external power source, it\r
+ updates device status to indicate that it is no\r
+ longer self-powered. \n\r
+ A device may not increase its power draw\r
+ from the bus, when it loses its external power\r
+ source, beyond the amount reported by its\r
+ configuration. \n\r
+ If a device can continue to operate when\r
+ disconnected from its external power source, it\r
+ continues to do so. If the device cannot\r
+ continue to operate, it fails operations it can\r
+ no longer support. The USB System Software\r
+ may determine the cause of the failure by\r
+ checking the status and noting the loss of the\r
+ device\92s power source.*/\r
+} ;\r
+/** USB Standard Configuration Descriptor */\r
+typedef struct _USB_CONFIGURATION_DESCRIPTOR USB_CONFIGURATION_DESCRIPTOR;\r
+\r
+/** USB Standard Interface Association Descriptor */\r
+PRE_PACK struct POST_PACK _USB_IAD_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes*/\r
+ uint8_t bDescriptorType; /**< INTERFACE ASSOCIATION Descriptor Type*/\r
+ uint8_t bFirstInterface; /**< Interface number of the first interface that is\r
+ associated with this function.*/\r
+ uint8_t bInterfaceCount; /**< Number of contiguous interfaces that are\r
+ associated with this function. */\r
+ uint8_t bFunctionClass; /**< Class code (assigned by USB-IF). \n\r
+ A value of zero is not allowed in this descriptor.\r
+ If this field is FFH, the function class is vendorspecific.\r
+ All other values are reserved for assignment by\r
+ the USB-IF.*/\r
+ uint8_t bFunctionSubClass; /**< Subclass code (assigned by USB-IF). \n\r
+ If the bFunctionClass field is not set to FFH all\r
+ values are reserved for assignment by the USBIF.*/\r
+ uint8_t bFunctionProtocol; /**< Protocol code (assigned by the USB). \n\r
+ These codes are qualified by the values of the\r
+ bFunctionClass and bFunctionSubClass fields.*/\r
+ uint8_t iFunction; /**< Index of string descriptor describing this function.*/\r
+} ;\r
+/** USB Standard Interface Association Descriptor */\r
+typedef struct _USB_IAD_DESCRIPTOR USB_IAD_DESCRIPTOR;\r
+\r
+/** USB Standard Interface Descriptor */\r
+PRE_PACK struct POST_PACK _USB_INTERFACE_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes*/\r
+ uint8_t bDescriptorType; /**< INTERFACE Descriptor Type*/\r
+ uint8_t bInterfaceNumber; /**< Number of this interface. Zero-based\r
+ value identifying the index in the array of\r
+ concurrent interfaces supported by this\r
+ configuration.*/\r
+ uint8_t bAlternateSetting; /**< Value used to select this alternate setting\r
+ for the interface identified in the prior field*/\r
+ uint8_t bNumEndpoints; /**< Number of endpoints used by this\r
+ interface (excluding endpoint zero). If this\r
+ value is zero, this interface only uses the\r
+ Default Control Pipe.*/\r
+ uint8_t bInterfaceClass; /**< Class code (assigned by the USB-IF). \n\r
+ A value of zero is reserved for future\r
+ standardization. \n\r
+ If this field is set to FFH, the interface\r
+ class is vendor-specific. \n\r
+ All other values are reserved for\r
+ assignment by the USB-IF.*/\r
+ uint8_t bInterfaceSubClass; /**< Subclass code (assigned by the USB-IF). \n\r
+ These codes are qualified by the value of\r
+ the bInterfaceClass field. \n\r
+ If the bInterfaceClass field is reset to zero,\r
+ this field must also be reset to zero. \n\r
+ If the bInterfaceClass field is not set to\r
+ FFH, all values are reserved for\r
+ assignment by the USB-IF.*/\r
+ uint8_t bInterfaceProtocol; /**< Protocol code (assigned by the USB). \n\r
+ These codes are qualified by the value of\r
+ the bInterfaceClass and the\r
+ bInterfaceSubClass fields. If an interface\r
+ supports class-specific requests, this code\r
+ identifies the protocols that the device\r
+ uses as defined by the specification of the\r
+ device class. \n\r
+ If this field is reset to zero, the device\r
+ does not use a class-specific protocol on\r
+ this interface. \n\r
+ If this field is set to FFH, the device uses\r
+ a vendor-specific protocol for this\r
+ interface.*/\r
+ uint8_t iInterface; /**< Index of string descriptor describing this interface*/\r
+} ;\r
+/** USB Standard Interface Descriptor */\r
+typedef struct _USB_INTERFACE_DESCRIPTOR USB_INTERFACE_DESCRIPTOR;\r
+\r
+/** USB Standard Endpoint Descriptor */\r
+PRE_PACK struct POST_PACK _USB_ENDPOINT_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes*/\r
+ uint8_t bDescriptorType; /**< ENDPOINT Descriptor Type*/\r
+ uint8_t bEndpointAddress; /**< The address of the endpoint on the USB device\r
+ described by this descriptor. The address is\r
+ encoded as follows: \n\r
+ Bit 3...0: The endpoint number \n\r
+ Bit 6...4: Reserved, reset to zero \n\r
+ Bit 7: Direction, ignored for control endpoints\r
+ 0 = OUT endpoint\r
+ 1 = IN endpoint. \n \sa USBD_ENDPOINT_ADR_Type*/\r
+ uint8_t bmAttributes; /**< This field describes the endpoint\92s attributes when it is\r
+ configured using the bConfigurationValue. \n\r
+ Bits 1..0: Transfer Type\r
+ \li 00 = Control\r
+ \li 01 = Isochronous\r
+ \li 10 = Bulk\r
+ \li 11 = Interrupt \n\r
+ If not an isochronous endpoint, bits 5..2 are reserved\r
+ and must be set to zero. If isochronous, they are\r
+ defined as follows: \n\r
+ Bits 3..2: Synchronization Type\r
+ \li 00 = No Synchronization\r
+ \li 01 = Asynchronous\r
+ \li 10 = Adaptive\r
+ \li 11 = Synchronous \n\r
+ Bits 5..4: Usage Type\r
+ \li 00 = Data endpoint\r
+ \li 01 = Feedback endpoint\r
+ \li 10 = Implicit feedback Data endpoint\r
+ \li 11 = Reserved \n\r
+ Refer to Chapter 5 of USB 2.0 specification for more information. \n\r
+ All other bits are reserved and must be reset to zero.\r
+ Reserved bits must be ignored by the host.\r
+ \n \sa USBD_EP_ATTR_Type*/\r
+ uint16_t wMaxPacketSize; /**< Maximum packet size this endpoint is capable of\r
+ sending or receiving when this configuration is\r
+ selected. \n\r
+ For isochronous endpoints, this value is used to\r
+ reserve the bus time in the schedule, required for the\r
+ per-(micro)frame data payloads. The pipe may, on an\r
+ ongoing basis, actually use less bandwidth than that\r
+ reserved. The device reports, if necessary, the actual\r
+ bandwidth used via its normal, non-USB defined\r
+ mechanisms. \n\r
+ For all endpoints, bits 10..0 specify the maximum\r
+ packet size (in bytes). \n\r
+ For high-speed isochronous and interrupt endpoints: \n\r
+ Bits 12..11 specify the number of additional transaction\r
+ opportunities per microframe: \n\r
+ \li 00 = None (1 transaction per microframe)\r
+ \li 01 = 1 additional (2 per microframe)\r
+ \li 10 = 2 additional (3 per microframe)\r
+ \li 11 = Reserved \n\r
+ Bits 15..13 are reserved and must be set to zero.*/\r
+ uint8_t bInterval; /**< Interval for polling endpoint for data transfers.\r
+ Expressed in frames or microframes depending on the\r
+ device operating speed (i.e., either 1 millisecond or\r
+ 125 µs units). \r
+ \li For full-/high-speed isochronous endpoints, this value\r
+ must be in the range from 1 to 16. The bInterval value\r
+ is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a\r
+ bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \r
+ \li For full-/low-speed interrupt endpoints, the value of\r
+ this field may be from 1 to 255.\r
+ \li For high-speed interrupt endpoints, the bInterval value\r
+ is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a\r
+ bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value\r
+ must be from 1 to 16.\r
+ \li For high-speed bulk/control OUT endpoints, the\r
+ bInterval must specify the maximum NAK rate of the\r
+ endpoint. A value of 0 indicates the endpoint never\r
+ NAKs. Other values indicate at most 1 NAK each\r
+ bInterval number of microframes. This value must be\r
+ in the range from 0 to 255. \n\r
+ Refer to Chapter 5 of USB 2.0 specification for more information.\r
+ */\r
+} ;\r
+/** USB Standard Endpoint Descriptor */\r
+typedef struct _USB_ENDPOINT_DESCRIPTOR USB_ENDPOINT_DESCRIPTOR;\r
+\r
+/** USB String Descriptor */\r
+PRE_PACK struct POST_PACK _USB_STRING_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes*/\r
+ uint8_t bDescriptorType; /**< STRING Descriptor Type*/\r
+ uint16_t bString/*[]*/; /**< UNICODE encoded string */\r
+} ;\r
+/** USB String Descriptor */\r
+typedef struct _USB_STRING_DESCRIPTOR USB_STRING_DESCRIPTOR;\r
+\r
+/** USB Common Descriptor */\r
+PRE_PACK struct POST_PACK _USB_COMMON_DESCRIPTOR\r
+{\r
+ uint8_t bLength; /**< Size of this descriptor in bytes*/\r
+ uint8_t bDescriptorType; /**< Descriptor Type*/\r
+} ;\r
+/** USB Common Descriptor */\r
+typedef struct _USB_COMMON_DESCRIPTOR USB_COMMON_DESCRIPTOR;\r
+\r
+/** USB Other Speed Configuration */\r
+PRE_PACK struct POST_PACK _USB_OTHER_SPEED_CONFIGURATION\r
+{\r
+ uint8_t bLength; /**< Size of descriptor*/\r
+ uint8_t bDescriptorType; /**< Other_speed_Configuration Type*/\r
+ uint16_t wTotalLength; /**< Total length of data returned*/\r
+ uint8_t bNumInterfaces; /**< Number of interfaces supported by this speed configuration*/\r
+ uint8_t bConfigurationValue; /**< Value to use to select configuration*/\r
+ uint8_t IConfiguration; /**< Index of string descriptor*/\r
+ uint8_t bmAttributes; /**< Same as Configuration descriptor*/\r
+ uint8_t bMaxPower; /**< Same as Configuration descriptor*/\r
+} ;\r
+/** USB Other Speed Configuration */\r
+typedef struct _USB_OTHER_SPEED_CONFIGURATION USB_OTHER_SPEED_CONFIGURATION;\r
+\r
+/** \ingroup USBD_Core \r
+ * USB device stack/module handle. \r
+ */\r
+typedef void* USBD_HANDLE_T;\r
+\r
+#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF)\r
+#define B3VAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF),(((x) >> 16) & 0xFF)\r
+\r
+#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))\r
+#define USB_CONFIGURATION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))\r
+#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))\r
+#define USB_INTERFACE_ASSOC_DESC_SIZE (sizeof(USB_IAD_DESCRIPTOR))\r
+#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))\r
+#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR))\r
+#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION))\r
+\r
+/** @}*/\r
+\r
+#endif /* __USBD_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_audio.h 165 2011-04-14 17:41:11Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* USB Audio Device Class Definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+#ifndef __AUDIO_H__\r
+#define __AUDIO_H__\r
+\r
+\r
+/* Audio Interface Subclass Codes */\r
+#define AUDIO_SUBCLASS_UNDEFINED 0x00\r
+#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01\r
+#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02\r
+#define AUDIO_SUBCLASS_MIDISTREAMING 0x03\r
+\r
+/* Audio Interface Protocol Codes */\r
+#define AUDIO_PROTOCOL_UNDEFINED 0x00\r
+\r
+\r
+/* Audio Descriptor Types */\r
+#define AUDIO_UNDEFINED_DESCRIPTOR_TYPE 0x20\r
+#define AUDIO_DEVICE_DESCRIPTOR_TYPE 0x21\r
+#define AUDIO_CONFIGURATION_DESCRIPTOR_TYPE 0x22\r
+#define AUDIO_STRING_DESCRIPTOR_TYPE 0x23\r
+#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24\r
+#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25\r
+\r
+\r
+/* Audio Control Interface Descriptor Subtypes */\r
+#define AUDIO_CONTROL_UNDEFINED 0x00\r
+#define AUDIO_CONTROL_HEADER 0x01\r
+#define AUDIO_CONTROL_INPUT_TERMINAL 0x02\r
+#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03\r
+#define AUDIO_CONTROL_MIXER_UNIT 0x04\r
+#define AUDIO_CONTROL_SELECTOR_UNIT 0x05\r
+#define AUDIO_CONTROL_FEATURE_UNIT 0x06\r
+#define AUDIO_CONTROL_PROCESSING_UNIT 0x07\r
+#define AUDIO_CONTROL_EXTENSION_UNIT 0x08\r
+\r
+/* Audio Streaming Interface Descriptor Subtypes */\r
+#define AUDIO_STREAMING_UNDEFINED 0x00\r
+#define AUDIO_STREAMING_GENERAL 0x01\r
+#define AUDIO_STREAMING_FORMAT_TYPE 0x02\r
+#define AUDIO_STREAMING_FORMAT_SPECIFIC 0x03\r
+\r
+/* Audio Endpoint Descriptor Subtypes */\r
+#define AUDIO_ENDPOINT_UNDEFINED 0x00\r
+#define AUDIO_ENDPOINT_GENERAL 0x01\r
+\r
+\r
+/* Audio Descriptor Sizes */\r
+#define AUDIO_CONTROL_INTERFACE_DESC_SZ(n) 0x08+n\r
+#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07\r
+#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C\r
+#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09\r
+#define AUDIO_MIXER_UNIT_DESC_SZ(p,n) 0x0A+p+n\r
+#define AUDIO_SELECTOR_UNIT_DESC_SZ(p) 0x06+p\r
+#define AUDIO_FEATURE_UNIT_DESC_SZ(ch,n) 0x07+(ch+1)*n\r
+#define AUDIO_PROCESSING_UNIT_DESC_SZ(p,n,x) 0x0D+p+n+x\r
+#define AUDIO_EXTENSION_UNIT_DESC_SZ(p,n) 0x0D+p+n\r
+#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09\r
+#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07\r
+\r
+\r
+/* Audio Processing Unit Process Types */\r
+#define AUDIO_UNDEFINED_PROCESS 0x00\r
+#define AUDIO_UP_DOWN_MIX_PROCESS 0x01\r
+#define AUDIO_DOLBY_PROLOGIC_PROCESS 0x02\r
+#define AUDIO_3D_STEREO_PROCESS 0x03\r
+#define AUDIO_REVERBERATION_PROCESS 0x04\r
+#define AUDIO_CHORUS_PROCESS 0x05\r
+#define AUDIO_DYN_RANGE_COMP_PROCESS 0x06\r
+\r
+\r
+/* Audio Request Codes */\r
+#define AUDIO_REQUEST_UNDEFINED 0x00\r
+#define AUDIO_REQUEST_SET_CUR 0x01\r
+#define AUDIO_REQUEST_GET_CUR 0x81\r
+#define AUDIO_REQUEST_SET_MIN 0x02\r
+#define AUDIO_REQUEST_GET_MIN 0x82\r
+#define AUDIO_REQUEST_SET_MAX 0x03\r
+#define AUDIO_REQUEST_GET_MAX 0x83\r
+#define AUDIO_REQUEST_SET_RES 0x04\r
+#define AUDIO_REQUEST_GET_RES 0x84\r
+#define AUDIO_REQUEST_SET_MEM 0x05\r
+#define AUDIO_REQUEST_GET_MEM 0x85\r
+#define AUDIO_REQUEST_GET_STAT 0xFF\r
+\r
+\r
+/* Audio Control Selector Codes */\r
+#define AUDIO_CONTROL_UNDEFINED 0x00 /* Common Selector */\r
+\r
+/* Terminal Control Selectors */\r
+#define AUDIO_COPY_PROTECT_CONTROL 0x01\r
+\r
+/* Feature Unit Control Selectors */\r
+#define AUDIO_MUTE_CONTROL 0x01\r
+#define AUDIO_VOLUME_CONTROL 0x02\r
+#define AUDIO_BASS_CONTROL 0x03\r
+#define AUDIO_MID_CONTROL 0x04\r
+#define AUDIO_TREBLE_CONTROL 0x05\r
+#define AUDIO_GRAPHIC_EQUALIZER_CONTROL 0x06\r
+#define AUDIO_AUTOMATIC_GAIN_CONTROL 0x07\r
+#define AUDIO_DELAY_CONTROL 0x08\r
+#define AUDIO_BASS_BOOST_CONTROL 0x09\r
+#define AUDIO_LOUDNESS_CONTROL 0x0A\r
+\r
+/* Processing Unit Control Selectors: */\r
+#define AUDIO_ENABLE_CONTROL 0x01 /* Common Selector */\r
+#define AUDIO_MODE_SELECT_CONTROL 0x02 /* Common Selector */\r
+\r
+/* - Up/Down-mix Control Selectors */\r
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */\r
+/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */\r
+\r
+/* - Dolby Prologic Control Selectors */\r
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */\r
+/* AUDIO_MODE_SELECT_CONTROL 0x02 Common Selector */\r
+\r
+/* - 3D Stereo Extender Control Selectors */\r
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */\r
+#define AUDIO_SPACIOUSNESS_CONTROL 0x02\r
+\r
+/* - Reverberation Control Selectors */\r
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */\r
+#define AUDIO_REVERB_LEVEL_CONTROL 0x02\r
+#define AUDIO_REVERB_TIME_CONTROL 0x03\r
+#define AUDIO_REVERB_FEEDBACK_CONTROL 0x04\r
+\r
+/* - Chorus Control Selectors */\r
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */\r
+#define AUDIO_CHORUS_LEVEL_CONTROL 0x02\r
+#define AUDIO_SHORUS_RATE_CONTROL 0x03\r
+#define AUDIO_CHORUS_DEPTH_CONTROL 0x04\r
+\r
+/* - Dynamic Range Compressor Control Selectors */\r
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */\r
+#define AUDIO_COMPRESSION_RATE_CONTROL 0x02\r
+#define AUDIO_MAX_AMPL_CONTROL 0x03\r
+#define AUDIO_THRESHOLD_CONTROL 0x04\r
+#define AUDIO_ATTACK_TIME_CONTROL 0x05\r
+#define AUDIO_RELEASE_TIME_CONTROL 0x06\r
+\r
+/* Extension Unit Control Selectors */\r
+/* AUDIO_ENABLE_CONTROL 0x01 Common Selector */\r
+\r
+/* Endpoint Control Selectors */\r
+#define AUDIO_SAMPLING_FREQ_CONTROL 0x01\r
+#define AUDIO_PITCH_CONTROL 0x02\r
+\r
+\r
+/* Audio Format Specific Control Selectors */\r
+\r
+/* MPEG Control Selectors */\r
+#define AUDIO_MPEG_CONTROL_UNDEFINED 0x00\r
+#define AUDIO_MPEG_DUAL_CHANNEL_CONTROL 0x01\r
+#define AUDIO_MPEG_SECOND_STEREO_CONTROL 0x02\r
+#define AUDIO_MPEG_MULTILINGUAL_CONTROL 0x03\r
+#define AUDIO_MPEG_DYN_RANGE_CONTROL 0x04\r
+#define AUDIO_MPEG_SCALING_CONTROL 0x05\r
+#define AUDIO_MPEG_HILO_SCALING_CONTROL 0x06\r
+\r
+/* AC-3 Control Selectors */\r
+#define AUDIO_AC3_CONTROL_UNDEFINED 0x00\r
+#define AUDIO_AC3_MODE_CONTROL 0x01\r
+#define AUDIO_AC3_DYN_RANGE_CONTROL 0x02\r
+#define AUDIO_AC3_SCALING_CONTROL 0x03\r
+#define AUDIO_AC3_HILO_SCALING_CONTROL 0x04\r
+\r
+\r
+/* Audio Format Types */\r
+#define AUDIO_FORMAT_TYPE_UNDEFINED 0x00\r
+#define AUDIO_FORMAT_TYPE_I 0x01\r
+#define AUDIO_FORMAT_TYPE_II 0x02\r
+#define AUDIO_FORMAT_TYPE_III 0x03\r
+\r
+\r
+/* Audio Format Type Descriptor Sizes */\r
+#define AUDIO_FORMAT_TYPE_I_DESC_SZ(n) 0x08+(n*3)\r
+#define AUDIO_FORMAT_TYPE_II_DESC_SZ(n) 0x09+(n*3)\r
+#define AUDIO_FORMAT_TYPE_III_DESC_SZ(n) 0x08+(n*3)\r
+#define AUDIO_FORMAT_MPEG_DESC_SIZE 0x09\r
+#define AUDIO_FORMAT_AC3_DESC_SIZE 0x0A\r
+\r
+\r
+/* Audio Data Format Codes */\r
+\r
+/* Audio Data Format Type I Codes */\r
+#define AUDIO_FORMAT_TYPE_I_UNDEFINED 0x0000\r
+#define AUDIO_FORMAT_PCM 0x0001\r
+#define AUDIO_FORMAT_PCM8 0x0002\r
+#define AUDIO_FORMAT_IEEE_FLOAT 0x0003\r
+#define AUDIO_FORMAT_ALAW 0x0004\r
+#define AUDIO_FORMAT_MULAW 0x0005\r
+\r
+/* Audio Data Format Type II Codes */\r
+#define AUDIO_FORMAT_TYPE_II_UNDEFINED 0x1000\r
+#define AUDIO_FORMAT_MPEG 0x1001\r
+#define AUDIO_FORMAT_AC3 0x1002\r
+\r
+/* Audio Data Format Type III Codes */\r
+#define AUDIO_FORMAT_TYPE_III_UNDEFINED 0x2000\r
+#define AUDIO_FORMAT_IEC1937_AC3 0x2001\r
+#define AUDIO_FORMAT_IEC1937_MPEG1_L1 0x2002\r
+#define AUDIO_FORMAT_IEC1937_MPEG1_L2_3 0x2003\r
+#define AUDIO_FORMAT_IEC1937_MPEG2_NOEXT 0x2003\r
+#define AUDIO_FORMAT_IEC1937_MPEG2_EXT 0x2004\r
+#define AUDIO_FORMAT_IEC1937_MPEG2_L1_LS 0x2005\r
+#define AUDIO_FORMAT_IEC1937_MPEG2_L2_3 0x2006\r
+\r
+\r
+/* Predefined Audio Channel Configuration Bits */\r
+#define AUDIO_CHANNEL_M 0x0000 /* Mono */\r
+#define AUDIO_CHANNEL_L 0x0001 /* Left Front */\r
+#define AUDIO_CHANNEL_R 0x0002 /* Right Front */\r
+#define AUDIO_CHANNEL_C 0x0004 /* Center Front */\r
+#define AUDIO_CHANNEL_LFE 0x0008 /* Low Freq. Enhance. */\r
+#define AUDIO_CHANNEL_LS 0x0010 /* Left Surround */\r
+#define AUDIO_CHANNEL_RS 0x0020 /* Right Surround */\r
+#define AUDIO_CHANNEL_LC 0x0040 /* Left of Center */\r
+#define AUDIO_CHANNEL_RC 0x0080 /* Right of Center */\r
+#define AUDIO_CHANNEL_S 0x0100 /* Surround */\r
+#define AUDIO_CHANNEL_SL 0x0200 /* Side Left */\r
+#define AUDIO_CHANNEL_SR 0x0400 /* Side Right */\r
+#define AUDIO_CHANNEL_T 0x0800 /* Top */\r
+\r
+\r
+/* Feature Unit Control Bits */\r
+#define AUDIO_CONTROL_MUTE 0x0001\r
+#define AUDIO_CONTROL_VOLUME 0x0002\r
+#define AUDIO_CONTROL_BASS 0x0004\r
+#define AUDIO_CONTROL_MID 0x0008\r
+#define AUDIO_CONTROL_TREBLE 0x0010\r
+#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020\r
+#define AUDIO_CONTROL_AUTOMATIC_GAIN 0x0040\r
+#define AUDIO_CONTROL_DEALY 0x0080\r
+#define AUDIO_CONTROL_BASS_BOOST 0x0100\r
+#define AUDIO_CONTROL_LOUDNESS 0x0200\r
+\r
+/* Processing Unit Control Bits: */\r
+#define AUDIO_CONTROL_ENABLE 0x0001 /* Common Bit */\r
+#define AUDIO_CONTROL_MODE_SELECT 0x0002 /* Common Bit */\r
+\r
+/* - Up/Down-mix Control Bits */\r
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */\r
+/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */\r
+\r
+/* - Dolby Prologic Control Bits */\r
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */\r
+/* AUDIO_CONTROL_MODE_SELECT 0x0002 Common Bit */\r
+\r
+/* - 3D Stereo Extender Control Bits */\r
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */\r
+#define AUDIO_CONTROL_SPACIOUSNESS 0x0002\r
+\r
+/* - Reverberation Control Bits */\r
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */\r
+#define AUDIO_CONTROL_REVERB_TYPE 0x0002\r
+#define AUDIO_CONTROL_REVERB_LEVEL 0x0004\r
+#define AUDIO_CONTROL_REVERB_TIME 0x0008\r
+#define AUDIO_CONTROL_REVERB_FEEDBACK 0x0010\r
+\r
+/* - Chorus Control Bits */\r
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */\r
+#define AUDIO_CONTROL_CHORUS_LEVEL 0x0002\r
+#define AUDIO_CONTROL_SHORUS_RATE 0x0004\r
+#define AUDIO_CONTROL_CHORUS_DEPTH 0x0008\r
+\r
+/* - Dynamic Range Compressor Control Bits */\r
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */\r
+#define AUDIO_CONTROL_COMPRESSION_RATE 0x0002\r
+#define AUDIO_CONTROL_MAX_AMPL 0x0004\r
+#define AUDIO_CONTROL_THRESHOLD 0x0008\r
+#define AUDIO_CONTROL_ATTACK_TIME 0x0010\r
+#define AUDIO_CONTROL_RELEASE_TIME 0x0020\r
+\r
+/* Extension Unit Control Bits */\r
+/* AUDIO_CONTROL_ENABLE 0x0001 Common Bit */\r
+\r
+/* Endpoint Control Bits */\r
+#define AUDIO_CONTROL_SAMPLING_FREQ 0x01\r
+#define AUDIO_CONTROL_PITCH 0x02\r
+#define AUDIO_MAX_PACKETS_ONLY 0x80\r
+\r
+\r
+/* Audio Terminal Types */\r
+\r
+/* USB Terminal Types */\r
+#define AUDIO_TERMINAL_USB_UNDEFINED 0x0100\r
+#define AUDIO_TERMINAL_USB_STREAMING 0x0101\r
+#define AUDIO_TERMINAL_USB_VENDOR_SPECIFIC 0x01FF\r
+\r
+/* Input Terminal Types */\r
+#define AUDIO_TERMINAL_INPUT_UNDEFINED 0x0200\r
+#define AUDIO_TERMINAL_MICROPHONE 0x0201\r
+#define AUDIO_TERMINAL_DESKTOP_MICROPHONE 0x0202\r
+#define AUDIO_TERMINAL_PERSONAL_MICROPHONE 0x0203\r
+#define AUDIO_TERMINAL_OMNI_DIR_MICROPHONE 0x0204\r
+#define AUDIO_TERMINAL_MICROPHONE_ARRAY 0x0205\r
+#define AUDIO_TERMINAL_PROCESSING_MIC_ARRAY 0x0206\r
+\r
+/* Output Terminal Types */\r
+#define AUDIO_TERMINAL_OUTPUT_UNDEFINED 0x0300\r
+#define AUDIO_TERMINAL_SPEAKER 0x0301\r
+#define AUDIO_TERMINAL_HEADPHONES 0x0302\r
+#define AUDIO_TERMINAL_HEAD_MOUNTED_AUDIO 0x0303\r
+#define AUDIO_TERMINAL_DESKTOP_SPEAKER 0x0304\r
+#define AUDIO_TERMINAL_ROOM_SPEAKER 0x0305\r
+#define AUDIO_TERMINAL_COMMUNICATION_SPEAKER 0x0306\r
+#define AUDIO_TERMINAL_LOW_FREQ_SPEAKER 0x0307\r
+\r
+/* Bi-directional Terminal Types */\r
+#define AUDIO_TERMINAL_BIDIRECTIONAL_UNDEFINED 0x0400\r
+#define AUDIO_TERMINAL_HANDSET 0x0401\r
+#define AUDIO_TERMINAL_HEAD_MOUNTED_HANDSET 0x0402\r
+#define AUDIO_TERMINAL_SPEAKERPHONE 0x0403\r
+#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOSUPRESS 0x0404\r
+#define AUDIO_TERMINAL_SPEAKERPHONE_ECHOCANCEL 0x0405\r
+\r
+/* Telephony Terminal Types */\r
+#define AUDIO_TERMINAL_TELEPHONY_UNDEFINED 0x0500\r
+#define AUDIO_TERMINAL_PHONE_LINE 0x0501\r
+#define AUDIO_TERMINAL_TELEPHONE 0x0502\r
+#define AUDIO_TERMINAL_DOWN_LINE_PHONE 0x0503\r
+\r
+/* External Terminal Types */\r
+#define AUDIO_TERMINAL_EXTERNAL_UNDEFINED 0x0600\r
+#define AUDIO_TERMINAL_ANALOG_CONNECTOR 0x0601\r
+#define AUDIO_TERMINAL_DIGITAL_AUDIO_INTERFACE 0x0602\r
+#define AUDIO_TERMINAL_LINE_CONNECTOR 0x0603\r
+#define AUDIO_TERMINAL_LEGACY_AUDIO_CONNECTOR 0x0604\r
+#define AUDIO_TERMINAL_SPDIF_INTERFACE 0x0605\r
+#define AUDIO_TERMINAL_1394_DA_STREAM 0x0606\r
+#define AUDIO_TERMINAL_1394_DA_STREAM_TRACK 0x0607\r
+\r
+/* Embedded Function Terminal Types */\r
+#define AUDIO_TERMINAL_EMBEDDED_UNDEFINED 0x0700\r
+#define AUDIO_TERMINAL_CALIBRATION_NOISE 0x0701\r
+#define AUDIO_TERMINAL_EQUALIZATION_NOISE 0x0702\r
+#define AUDIO_TERMINAL_CD_PLAYER 0x0703\r
+#define AUDIO_TERMINAL_DAT 0x0704\r
+#define AUDIO_TERMINAL_DCC 0x0705\r
+#define AUDIO_TERMINAL_MINI_DISK 0x0706\r
+#define AUDIO_TERMINAL_ANALOG_TAPE 0x0707\r
+#define AUDIO_TERMINAL_PHONOGRAPH 0x0708\r
+#define AUDIO_TERMINAL_VCR_AUDIO 0x0709\r
+#define AUDIO_TERMINAL_VIDEO_DISC_AUDIO 0x070A\r
+#define AUDIO_TERMINAL_DVD_AUDIO 0x070B\r
+#define AUDIO_TERMINAL_TV_TUNER_AUDIO 0x070C\r
+#define AUDIO_TERMINAL_SATELLITE_RECEIVER_AUDIO 0x070D\r
+#define AUDIO_TERMINAL_CABLE_TUNER_AUDIO 0x070E\r
+#define AUDIO_TERMINAL_DSS_AUDIO 0x070F\r
+#define AUDIO_TERMINAL_RADIO_RECEIVER 0x0710\r
+#define AUDIO_TERMINAL_RADIO_TRANSMITTER 0x0711\r
+#define AUDIO_TERMINAL_MULTI_TRACK_RECORDER 0x0712\r
+#define AUDIO_TERMINAL_SYNTHESIZER 0x0713\r
+\r
+\r
+#endif /* __AUDIO_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_cdc.h 165 2011-04-14 17:41:11Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* USB Communication Device Class User module Definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+#ifndef __CDC_H\r
+#define __CDC_H\r
+\r
+#include "usbd.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions based on usbcdc11.pdf (www.usb.org)\r
+ *---------------------------------------------------------------------------*/\r
+/* Communication device class specification version 1.10 */\r
+#define CDC_V1_10 0x0110\r
+\r
+/* Communication interface class code */\r
+/* (usbcdc11.pdf, 4.2, Table 15) */\r
+#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02\r
+\r
+/* Communication interface class subclass codes */\r
+/* (usbcdc11.pdf, 4.3, Table 16) */\r
+#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01\r
+#define CDC_ABSTRACT_CONTROL_MODEL 0x02\r
+#define CDC_TELEPHONE_CONTROL_MODEL 0x03\r
+#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04\r
+#define CDC_CAPI_CONTROL_MODEL 0x05\r
+#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06\r
+#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07\r
+\r
+/* Communication interface class control protocol codes */\r
+/* (usbcdc11.pdf, 4.4, Table 17) */\r
+#define CDC_PROTOCOL_COMMON_AT_COMMANDS 0x01\r
+\r
+/* Data interface class code */\r
+/* (usbcdc11.pdf, 4.5, Table 18) */\r
+#define CDC_DATA_INTERFACE_CLASS 0x0A\r
+\r
+/* Data interface class protocol codes */\r
+/* (usbcdc11.pdf, 4.7, Table 19) */\r
+#define CDC_PROTOCOL_ISDN_BRI 0x30\r
+#define CDC_PROTOCOL_HDLC 0x31\r
+#define CDC_PROTOCOL_TRANSPARENT 0x32\r
+#define CDC_PROTOCOL_Q921_MANAGEMENT 0x50\r
+#define CDC_PROTOCOL_Q921_DATA_LINK 0x51\r
+#define CDC_PROTOCOL_Q921_MULTIPLEXOR 0x52\r
+#define CDC_PROTOCOL_V42 0x90\r
+#define CDC_PROTOCOL_EURO_ISDN 0x91\r
+#define CDC_PROTOCOL_V24_RATE_ADAPTATION 0x92\r
+#define CDC_PROTOCOL_CAPI 0x93\r
+#define CDC_PROTOCOL_HOST_BASED_DRIVER 0xFD\r
+#define CDC_PROTOCOL_DESCRIBED_IN_PUFD 0xFE\r
+\r
+/* Type values for bDescriptorType field of functional descriptors */\r
+/* (usbcdc11.pdf, 5.2.3, Table 24) */\r
+#define CDC_CS_INTERFACE 0x24\r
+#define CDC_CS_ENDPOINT 0x25\r
+\r
+/* Type values for bDescriptorSubtype field of functional descriptors */\r
+/* (usbcdc11.pdf, 5.2.3, Table 25) */\r
+#define CDC_HEADER 0x00\r
+#define CDC_CALL_MANAGEMENT 0x01\r
+#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02\r
+#define CDC_DIRECT_LINE_MANAGEMENT 0x03\r
+#define CDC_TELEPHONE_RINGER 0x04\r
+#define CDC_REPORTING_CAPABILITIES 0x05\r
+#define CDC_UNION 0x06\r
+#define CDC_COUNTRY_SELECTION 0x07\r
+#define CDC_TELEPHONE_OPERATIONAL_MODES 0x08\r
+#define CDC_USB_TERMINAL 0x09\r
+#define CDC_NETWORK_CHANNEL 0x0A\r
+#define CDC_PROTOCOL_UNIT 0x0B\r
+#define CDC_EXTENSION_UNIT 0x0C\r
+#define CDC_MULTI_CHANNEL_MANAGEMENT 0x0D\r
+#define CDC_CAPI_CONTROL_MANAGEMENT 0x0E\r
+#define CDC_ETHERNET_NETWORKING 0x0F\r
+#define CDC_ATM_NETWORKING 0x10\r
+\r
+/* CDC class-specific request codes */\r
+/* (usbcdc11.pdf, 6.2, Table 46) */\r
+/* see Table 45 for info about the specific requests. */\r
+#define CDC_SEND_ENCAPSULATED_COMMAND 0x00\r
+#define CDC_GET_ENCAPSULATED_RESPONSE 0x01\r
+#define CDC_SET_COMM_FEATURE 0x02\r
+#define CDC_GET_COMM_FEATURE 0x03\r
+#define CDC_CLEAR_COMM_FEATURE 0x04\r
+#define CDC_SET_AUX_LINE_STATE 0x10\r
+#define CDC_SET_HOOK_STATE 0x11\r
+#define CDC_PULSE_SETUP 0x12\r
+#define CDC_SEND_PULSE 0x13\r
+#define CDC_SET_PULSE_TIME 0x14\r
+#define CDC_RING_AUX_JACK 0x15\r
+#define CDC_SET_LINE_CODING 0x20\r
+#define CDC_GET_LINE_CODING 0x21\r
+#define CDC_SET_CONTROL_LINE_STATE 0x22\r
+#define CDC_SEND_BREAK 0x23\r
+#define CDC_SET_RINGER_PARMS 0x30\r
+#define CDC_GET_RINGER_PARMS 0x31\r
+#define CDC_SET_OPERATION_PARMS 0x32\r
+#define CDC_GET_OPERATION_PARMS 0x33\r
+#define CDC_SET_LINE_PARMS 0x34\r
+#define CDC_GET_LINE_PARMS 0x35\r
+#define CDC_DIAL_DIGITS 0x36\r
+#define CDC_SET_UNIT_PARAMETER 0x37\r
+#define CDC_GET_UNIT_PARAMETER 0x38\r
+#define CDC_CLEAR_UNIT_PARAMETER 0x39\r
+#define CDC_GET_PROFILE 0x3A\r
+#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40\r
+#define CDC_SET_ETHERNET_PMP_FILTER 0x41\r
+#define CDC_GET_ETHERNET_PMP_FILTER 0x42\r
+#define CDC_SET_ETHERNET_PACKET_FILTER 0x43\r
+#define CDC_GET_ETHERNET_STATISTIC 0x44\r
+#define CDC_SET_ATM_DATA_FORMAT 0x50\r
+#define CDC_GET_ATM_DEVICE_STATISTICS 0x51\r
+#define CDC_SET_ATM_DEFAULT_VC 0x52\r
+#define CDC_GET_ATM_VC_STATISTICS 0x53\r
+\r
+/* Communication feature selector codes */\r
+/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */\r
+#define CDC_ABSTRACT_STATE 0x01\r
+#define CDC_COUNTRY_SETTING 0x02\r
+\r
+/* Feature Status returned for ABSTRACT_STATE Selector */\r
+/* (usbcdc11.pdf, 6.2.3, Table 48) */\r
+#define CDC_IDLE_SETTING (1 << 0)\r
+#define CDC_DATA_MULTPLEXED_STATE (1 << 1)\r
+\r
+\r
+/* Control signal bitmap values for the SetControlLineState request */\r
+/* (usbcdc11.pdf, 6.2.14, Table 51) */\r
+#define CDC_DTE_PRESENT (1 << 0)\r
+#define CDC_ACTIVATE_CARRIER (1 << 1)\r
+\r
+/* CDC class-specific notification codes */\r
+/* (usbcdc11.pdf, 6.3, Table 68) */\r
+/* see Table 67 for Info about class-specific notifications */\r
+#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00\r
+#define CDC_RESPONSE_AVAILABLE 0x01\r
+#define CDC_AUX_JACK_HOOK_STATE 0x08\r
+#define CDC_RING_DETECT 0x09\r
+#define CDC_NOTIFICATION_SERIAL_STATE 0x20\r
+#define CDC_CALL_STATE_CHANGE 0x28\r
+#define CDC_LINE_STATE_CHANGE 0x29\r
+#define CDC_CONNECTION_SPEED_CHANGE 0x2A\r
+\r
+/* UART state bitmap values (Serial state notification). */\r
+/* (usbcdc11.pdf, 6.3.5, Table 69) */\r
+#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */\r
+#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */\r
+#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */\r
+#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */\r
+#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */\r
+#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */\r
+#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Structures based on usbcdc11.pdf (www.usb.org)\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/* Header functional descriptor */\r
+/* (usbcdc11.pdf, 5.2.3.1) */\r
+/* This header must precede any list of class-specific descriptors. */\r
+PRE_PACK struct POST_PACK _CDC_HEADER_DESCRIPTOR{\r
+ uint8_t bFunctionLength; /* size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */\r
+ uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */\r
+ uint16_t bcdCDC; /* USB CDC specification release version */\r
+};\r
+typedef struct _CDC_HEADER_DESCRIPTOR CDC_HEADER_DESCRIPTOR;\r
+\r
+/* Call management functional descriptor */\r
+/* (usbcdc11.pdf, 5.2.3.2) */\r
+/* Describes the processing of calls for the communication class interface. */\r
+PRE_PACK struct POST_PACK _CDC_CALL_MANAGEMENT_DESCRIPTOR {\r
+ uint8_t bFunctionLength; /* size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */\r
+ uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */\r
+ uint8_t bmCapabilities; /* capabilities that this configuration supports */\r
+ uint8_t bDataInterface; /* interface number of the data class interface used for call management (optional) */\r
+};\r
+typedef struct _CDC_CALL_MANAGEMENT_DESCRIPTOR CDC_CALL_MANAGEMENT_DESCRIPTOR;\r
+\r
+/* Abstract control management functional descriptor */\r
+/* (usbcdc11.pdf, 5.2.3.3) */\r
+/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */\r
+PRE_PACK struct POST_PACK _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR {\r
+ uint8_t bFunctionLength; /* size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */\r
+ uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */\r
+ uint8_t bmCapabilities; /* capabilities supported by this configuration */\r
+};\r
+typedef struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR;\r
+\r
+/* Union functional descriptors */\r
+/* (usbcdc11.pdf, 5.2.3.8) */\r
+/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */\r
+PRE_PACK struct POST_PACK _CDC_UNION_DESCRIPTOR {\r
+ uint8_t bFunctionLength; /* size of this descriptor in bytes */\r
+ uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */\r
+ uint8_t bDescriptorSubtype; /* union functional descriptor subtype */\r
+ uint8_t bMasterInterface; /* interface number designated as master */\r
+};\r
+typedef struct _CDC_UNION_DESCRIPTOR CDC_UNION_DESCRIPTOR;\r
+\r
+/* Union functional descriptors with one slave interface */\r
+/* (usbcdc11.pdf, 5.2.3.8) */\r
+PRE_PACK struct POST_PACK _CDC_UNION_1SLAVE_DESCRIPTOR {\r
+ CDC_UNION_DESCRIPTOR sUnion; /* Union functional descriptor */\r
+ uint8_t bSlaveInterfaces[1]; /* Slave interface 0 */\r
+};\r
+typedef struct _CDC_UNION_1SLAVE_DESCRIPTOR CDC_UNION_1SLAVE_DESCRIPTOR;\r
+\r
+/* Line coding structure */\r
+/* Format of the data returned when a GetLineCoding request is received */\r
+/* (usbcdc11.pdf, 6.2.13) */\r
+PRE_PACK struct POST_PACK _CDC_LINE_CODING {\r
+ uint32_t dwDTERate; /* Data terminal rate in bits per second */\r
+ uint8_t bCharFormat; /* Number of stop bits */\r
+ uint8_t bParityType; /* Parity bit type */\r
+ uint8_t bDataBits; /* Number of data bits */\r
+};\r
+typedef struct _CDC_LINE_CODING CDC_LINE_CODING;\r
+\r
+/* Notification header */\r
+/* Data sent on the notification endpoint must follow this header. */\r
+/* see USB_SETUP_PACKET in file usb.h */\r
+typedef USB_SETUP_PACKET CDC_NOTIFICATION_HEADER;\r
+\r
+#endif /* __CDC_H */\r
+\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_cdcuser.h 331 2012-08-09 18:54:34Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* USB Communication Device Class User module Definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+#ifndef __CDCUSER_H__\r
+#define __CDCUSER_H__\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "usbd_cdc.h"\r
+\r
+/** \file\r
+ * \brief Communication Device Class (CDC) API structures and function prototypes.\r
+ *\r
+ * Definition of functions exported by ROM based CDC function driver.\r
+ *\r
+ */\r
+\r
+/** \ingroup Group_USBD\r
+ * @defgroup USBD_CDC Communication Device Class (CDC) Function Driver\r
+ * \section Sec_CDCModDescription Module Description\r
+ * CDC Class Function Driver module. This module contains an internal implementation of the USB CDC Class.\r
+ *\r
+ * User applications can use this class driver instead of implementing the CDC-ACM class manually\r
+ * via the low-level USBD_HW and USBD_Core APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB CDC-ACM Class.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ We need a buffer for incoming data on USB port because USB receives\r
+ much faster than UART transmits\r
+ *---------------------------------------------------------------------------*/\r
+/* Buffer masks */\r
+#define CDC_BUF_SIZE (128) /* Output buffer in bytes (power 2) */\r
+ /* large enough for file transfer */\r
+#define CDC_BUF_MASK (CDC_BUF_SIZE-1ul)\r
+\r
+/** \brief Communication Device Class function driver initialization parameter data structure.\r
+ * \ingroup USBD_CDC\r
+ *\r
+ * \details This data structure is used to pass initialization parameters to the \r
+ * Communication Device Class function driver's init function.\r
+ *\r
+ */\r
+typedef struct USBD_CDC_INIT_PARAM\r
+{\r
+ /* memory allocation params */\r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. \note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 4 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use. \r
+ \note The \em mem_size should be greater than the size \r
+ returned by USBD_CDC_API::GetMemSize() routine.*/\r
+ /** Pointer to the control interface descriptor within the descriptor\r
+ * array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T \r
+ * structure. The stack assumes both HS and FS use same BULK endpoints. \r
+ */\r
+ uint8_t* cif_intf_desc;\r
+ /** Pointer to the data interface descriptor within the descriptor\r
+ * array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T \r
+ * structure. The stack assumes both HS and FS use same BULK endpoints. \r
+ */\r
+ uint8_t* dif_intf_desc;\r
+\r
+ /* user defined functions */\r
+\r
+ /* required functions */\r
+ /** \r
+ * Communication Interface Class specific get request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends CIC management element get requests.\r
+ * \note Applications implementing Abstract Control Model subclass can set this\r
+ * param to NULL. As the default driver parses ACM requests and calls the\r
+ * individual ACM call-back routines defined in this structure. For all other subclasses\r
+ * this routine should be provided by the application.\r
+ * \n\r
+ * The setup packet data (\em pSetup) is passed to the call-back so that application\r
+ * can extract the CIC request type and other associated data. By default the stack\r
+ * will assign \em pBuffer pointer to \em EP0Buff allocated at init. The application\r
+ * code can directly write data into this buffer as long as data is less than 64 byte.\r
+ * If more data has to be sent then application code should update \em pBuffer pointer\r
+ * and length accordingly.\r
+ * \r
+ * \r
+ * \param[in] hCdc Handle to CDC function driver. \r
+ * \param[in] pSetup Pointer to setup packet received from host.\r
+ * \param[in, out] pBuffer Pointer to a pointer of data buffer containing request data. \r
+ * Pointer-to-pointer is used to implement zero-copy buffers. \r
+ * See \ref USBD_ZeroCopy for more details on zero-copy concept.\r
+ * \param[in, out] length Amount of data to be sent back to host.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CIC_GetRequest)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length); \r
+ \r
+ /** \r
+ * Communication Interface Class specific set request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends a CIC management element requests.\r
+ * \note Applications implementing Abstract Control Model subclass can set this\r
+ * param to NULL. As the default driver parses ACM requests and calls the\r
+ * individual ACM call-back routines defined in this structure. For all other subclasses\r
+ * this routine should be provided by the application.\r
+ * \n\r
+ * The setup packet data (\em pSetup) is passed to the call-back so that application can\r
+ * extract the CIC request type and other associated data. If a set request has data associated,\r
+ * then this call-back is called twice.\r
+ * -# First when setup request is received, at this time application code could update\r
+ * \em pBuffer pointer to point to the intended destination. The length param is set to 0\r
+ * so that application code knows this is first time. By default the stack will\r
+ * assign \em pBuffer pointer to \em EP0Buff allocated at init. Note, if data length is \r
+ * greater than 64 bytes and application code doesn't update \em pBuffer pointer the \r
+ * stack will send STALL condition to host.\r
+ * -# Second when the data is received from the host. This time the length param is set\r
+ * with number of data bytes received.\r
+ * \r
+ * \param[in] hCdc Handle to CDC function driver. \r
+ * \param[in] pSetup Pointer to setup packet received from host.\r
+ * \param[in, out] pBuffer Pointer to a pointer of data buffer containing request data. \r
+ * Pointer-to-pointer is used to implement zero-copy buffers. \r
+ * See \ref USBD_ZeroCopy for more details on zero-copy concept.\r
+ * \param[in] length Amount of data copied to destination buffer.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CIC_SetRequest)( USBD_HANDLE_T hCdc, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);\r
+\r
+ /** \r
+ * Communication Device Class specific BULK IN endpoint handler.\r
+ *\r
+ * The application software should provide the BULK IN endpoint handler.\r
+ * Applications should transfer data depending on the communication protocol type set in descriptors. \r
+ * \n\r
+ * \note \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CDC_BulkIN_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+ /** \r
+ * Communication Device Class specific BULK OUT endpoint handler.\r
+ *\r
+ * The application software should provide the BULK OUT endpoint handler.\r
+ * Applications should transfer data depending on the communication protocol type set in descriptors. \r
+ * \n\r
+ * \note \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CDC_BulkOUT_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+ /**\r
+ * Abstract control model(ACM) subclass specific SEND_ENCAPSULATED_COMMAND request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a SEND_ENCAPSULATED_COMMAND set request.\r
+ *\r
+ * \param[in] hCdc Handle to CDC function driver.\r
+ * \param[in] buffer Pointer to the command buffer.\r
+ * \param[in] len Length of the command buffer.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * \retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*SendEncpsCmd) (USBD_HANDLE_T hCDC, uint8_t* buffer, uint16_t len);\r
+\r
+ /**\r
+ * Abstract control model(ACM) subclass specific GET_ENCAPSULATED_RESPONSE request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a GET_ENCAPSULATED_RESPONSE request.\r
+ *\r
+ * \param[in] hCdc Handle to CDC function driver.\r
+ * \param[in, out] buffer Pointer to a pointer of data buffer containing response data.\r
+ * Pointer-to-pointer is used to implement zero-copy buffers.\r
+ * See \ref USBD_ZeroCopy for more details on zero-copy concept.\r
+ * \param[in, out] len Amount of data to be sent back to host.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * \retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*GetEncpsResp) (USBD_HANDLE_T hCDC, uint8_t** buffer, uint16_t* len);\r
+\r
+ /**\r
+ * Abstract control model(ACM) subclass specific SET_COMM_FEATURE request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a SET_COMM_FEATURE set request.\r
+ *\r
+ * \param[in] hCdc Handle to CDC function driver.\r
+ * \param[in] feature Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47.\r
+ * \param[in] buffer Pointer to the settings buffer for the specified communication feature.\r
+ * \param[in] len Length of the request buffer.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * \retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*SetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t* buffer, uint16_t len);\r
+\r
+ /**\r
+ * Abstract control model(ACM) subclass specific GET_COMM_FEATURE request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a GET_ENCAPSULATED_RESPONSE request.\r
+ *\r
+ * \param[in] hCdc Handle to CDC function driver.\r
+ * \param[in] feature Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47.\r
+ * \param[in, out] buffer Pointer to a pointer of data buffer containing current settings\r
+ * for the communication feature.\r
+ * Pointer-to-pointer is used to implement zero-copy buffers.\r
+ * \param[in, out] len Amount of data to be sent back to host.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * \retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*GetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t** pBuffer, uint16_t* len);\r
+\r
+ /**\r
+ * Abstract control model(ACM) subclass specific CLEAR_COMM_FEATURE request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a CLEAR_COMM_FEATURE request. In the call-back the application\r
+ * should Clears the settings for a particular communication feature.\r
+ *\r
+ * \param[in] hCdc Handle to CDC function driver.\r
+ * \param[in] feature Communication feature type. See usbcdc11.pdf, section 6.2.4, Table 47.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * \retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*ClrCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature);\r
+\r
+ /**\r
+ * Abstract control model(ACM) subclass specific SET_CONTROL_LINE_STATE request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a SET_CONTROL_LINE_STATE request. RS-232 signal used to tell the DCE\r
+ * device the DTE device is now present\r
+ *\r
+ * \param[in] hCdc Handle to CDC function driver.\r
+ * \param[in] state The state value uses bitmap values defined in usbcdc11.pdf,\r
+ * section 6.2.14, Table 51.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * \retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*SetCtrlLineState) (USBD_HANDLE_T hCDC, uint16_t state);\r
+\r
+ /**\r
+ * Abstract control model(ACM) subclass specific SEND_BREAK request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a SEND_BREAK request.\r
+ *\r
+ * \param[in] hCdc Handle to CDC function driver.\r
+ * \param[in] mstime Duration of Break signal in milliseconds. If mstime is FFFFh, then\r
+ * the application should send break until another SendBreak request is received\r
+ * with the wValue of 0000h.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * \retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*SendBreak) (USBD_HANDLE_T hCDC, uint16_t mstime);\r
+\r
+ /**\r
+ * Abstract control model(ACM) subclass specific SET_LINE_CODING request call-back function.\r
+ *\r
+ * This function is provided by the application software. This function gets called\r
+ * when host sends a SET_LINE_CODING request. The application should configure the device\r
+ * per DTE rate, stop-bits, parity, and number-of-character bits settings provided in\r
+ * command buffer. See usbcdc11.pdf, section 6.2.13, table 50 for detail of the command buffer.\r
+ *\r
+ * \param[in] hCdc Handle to CDC function driver.\r
+ * \param[in] line_coding Pointer to the CDC_LINE_CODING command buffer.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line.\r
+ * \retval ERR_USBD_xxx For other error conditions.\r
+ *\r
+ */\r
+ ErrorCode_t (*SetLineCode) (USBD_HANDLE_T hCDC, CDC_LINE_CODING* line_coding);\r
+\r
+ /** \r
+ * Optional Communication Device Class specific INTERRUPT IN endpoint handler.\r
+ *\r
+ * The application software should provide the INT IN endpoint handler.\r
+ * Applications should transfer data depending on the communication protocol type set in descriptors. \r
+ * \n\r
+ * \note \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CDC_InterruptEP_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+ /** \r
+ * Optional user override-able function to replace the default CDC class handler.\r
+ *\r
+ * The application software could override the default EP0 class handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_CDC_API::Init().\r
+ * \n\r
+ * \note \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*CDC_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+} USBD_CDC_INIT_PARAM_T;\r
+\r
+/** \brief CDC class API functions structure.\r
+ * \ingroup USBD_CDC\r
+ *\r
+ * This module exposes functions which interact directly with USB device controller hardware.\r
+ *\r
+ */\r
+typedef struct USBD_CDC_API\r
+{\r
+ /** \fn uint32_t GetMemSize(USBD_CDC_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the CDC function driver module.\r
+ * \r
+ * This function is called by application layer before calling pUsbApi->CDC->Init(), to allocate memory used \r
+ * by CDC function driver module. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller. \r
+ * \note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * \param[in] param Structure containing CDC function driver module initialization parameters.\r
+ * \return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_CDC_INIT_PARAM_T* param);\r
+ \r
+ /** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param)\r
+ * Function to initialize CDC function driver module.\r
+ * \r
+ * This function is called by application layer to initialize CDC function driver module.\r
+ *\r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in, out] param Structure containing CDC function driver module initialization parameters.\r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success\r
+ * \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte \r
+ * aligned or smaller than required. \r
+ * \retval ERR_API_INVALID_PARAM2 Either CDC_Write() or CDC_Read() or\r
+ * CDC_Verify() callbacks are not defined. \r
+ * \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. \r
+ * \retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed. \r
+ */\r
+ ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param, USBD_HANDLE_T* phCDC);\r
+\r
+ /** \fn ErrorCode_t SendNotification(USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data)\r
+ * Function to send CDC class notifications to host. \r
+ * \r
+ * This function is called by application layer to send CDC class notifications to host. \r
+ * See usbcdc11.pdf, section 6.3, Table 67 for various notification types the CDC device can send.\r
+ * \note The current version of the driver only supports following notifications allowed by ACM subclass:\r
+ * CDC_NOTIFICATION_NETWORK_CONNECTION, CDC_RESPONSE_AVAILABLE, CDC_NOTIFICATION_SERIAL_STATE.\r
+ * \n \r
+ * For all other notifications application should construct the notification buffer appropriately\r
+ * and call hw->USB_WriteEP() for interrupt endpoint associated with the interface.\r
+ *\r
+ * \param[in] hCdc Handle to CDC function driver. \r
+ * \param[in] bNotification Notification type allowed by ACM subclass. Should be CDC_NOTIFICATION_NETWORK_CONNECTION,\r
+ * CDC_RESPONSE_AVAILABLE or CDC_NOTIFICATION_SERIAL_STATE. For all other types ERR_API_INVALID_PARAM2\r
+ * is returned. See usbcdc11.pdf, section 3.6.2.1, table 5.\r
+ * \param[in] data Data associated with notification. \r
+ * \n For CDC_NOTIFICATION_NETWORK_CONNECTION a non-zero data value is interpreted as connected state.\r
+ * \n For CDC_RESPONSE_AVAILABLE this parameter is ignored.\r
+ * \n For CDC_NOTIFICATION_SERIAL_STATE the data should use bitmap values defined in usbcdc11.pdf, \r
+ * section 6.3.5, Table 69.\r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success\r
+ * \retval ERR_API_INVALID_PARAM2 If unsupported notification type is passed. \r
+ * \r
+ */\r
+ ErrorCode_t (*SendNotification)(USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data);\r
+\r
+} USBD_CDC_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+/** @cond ADVANCED_API */\r
+\r
+typedef struct _CDC_CTRL_T\r
+{\r
+ USB_CORE_CTRL_T* pUsbCtrl;\r
+ /* notification buffer */\r
+ uint8_t notice_buf[12];\r
+ CDC_LINE_CODING line_coding;\r
+ uint8_t pad0;\r
+\r
+ uint8_t cif_num; /* control interface number */\r
+ uint8_t dif_num; /* data interface number */\r
+ uint8_t epin_num; /* BULK IN endpoint number */\r
+ uint8_t epout_num; /* BULK OUT endpoint number */\r
+ uint8_t epint_num; /* Interrupt IN endpoint number */\r
+ uint8_t pad[3];\r
+ /* user defined functions */\r
+ ErrorCode_t (*SendEncpsCmd) (USBD_HANDLE_T hCDC, uint8_t* buffer, uint16_t len);\r
+ ErrorCode_t (*GetEncpsResp) (USBD_HANDLE_T hCDC, uint8_t** buffer, uint16_t* len);\r
+ ErrorCode_t (*SetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t* buffer, uint16_t len);\r
+ ErrorCode_t (*GetCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature, uint8_t** pBuffer, uint16_t* len);\r
+ ErrorCode_t (*ClrCommFeature) (USBD_HANDLE_T hCDC, uint16_t feature);\r
+ ErrorCode_t (*SetCtrlLineState) (USBD_HANDLE_T hCDC, uint16_t state);\r
+ ErrorCode_t (*SendBreak) (USBD_HANDLE_T hCDC, uint16_t state);\r
+ ErrorCode_t (*SetLineCode) (USBD_HANDLE_T hCDC, CDC_LINE_CODING* line_coding);\r
+\r
+ /* virtual functions */\r
+ ErrorCode_t (*CIC_GetRequest)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length); \r
+ ErrorCode_t (*CIC_SetRequest)( USBD_HANDLE_T hCdc, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);\r
+\r
+}USB_CDC_CTRL_T;\r
+\r
+/** @cond DIRECT_API */\r
+extern uint32_t mwCDC_GetMemSize(USBD_CDC_INIT_PARAM_T* param);\r
+extern ErrorCode_t mwCDC_init(USBD_HANDLE_T hUsb, USBD_CDC_INIT_PARAM_T* param, USBD_HANDLE_T* phCDC);\r
+extern ErrorCode_t mwCDC_SendNotification (USBD_HANDLE_T hCdc, uint8_t bNotification, uint16_t data); \r
+/** @endcond */\r
+\r
+/** @endcond */\r
+\r
+\r
+\r
+\r
+\r
+#endif /* __CDCUSER_H__ */ \r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_core.h 331 2012-08-09 18:54:34Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* USB core controller structure definitions and function prototypes.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+#ifndef __MW_USBD_CORE_H__\r
+#define __MW_USBD_CORE_H__\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "app_usbd_cfg.h"\r
+\r
+/** \file\r
+ * \brief ROM API for USB device stack.\r
+ *\r
+ * Definition of functions exported by core layer of ROM based USB device stack.\r
+ *\r
+ */\r
+\r
+/** \ingroup Group_USBD\r
+ * @defgroup USBD_Core USB Core Layer\r
+ * \section Sec_CoreModDescription Module Description\r
+ * The USB Core Layer implements the device abstraction defined in the <em> Universal Serial Bus Specification, </em>\r
+ * for applications to interact with the USB device interface on the device. The software in this layer responds to \r
+ * standard requests and returns standard descriptors. In current stack the Init() routine part of \r
+ * \ref USBD_HW_API_T structure initializes both hardware layer and core layer.\r
+ */\r
+\r
+\r
+/* function pointer types */\r
+\r
+/** \ingroup USBD_Core \r
+ * \typedef USB_CB_T\r
+ * \brief USB device stack's event callback function type.\r
+ *\r
+ * The USB device stack exposes several event triggers through callback to application layer. The\r
+ * application layer can register methods to be called when such USB event happens.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx Other error conditions. \r
+ * \r
+ */\r
+typedef ErrorCode_t (*USB_CB_T) (USBD_HANDLE_T hUsb);\r
+\r
+/** \ingroup USBD_Core \r
+ * \typedef USB_PARAM_CB_T\r
+ * \brief USB device stack's event callback function type.\r
+ *\r
+ * The USB device stack exposes several event triggers through callback to application layer. The\r
+ * application layer can register methods to be called when such USB event happens.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] param1 Extra information related to the event. \r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+typedef ErrorCode_t (*USB_PARAM_CB_T) (USBD_HANDLE_T hUsb, uint32_t param1);\r
+\r
+/** \ingroup USBD_Core\r
+ * \typedef USB_EP_HANDLER_T\r
+ * \brief USBD setup request and endpoint event handler type.\r
+ *\r
+ * The application layer should define the custom class's EP0 handler with function signature. \r
+ * The stack calls all the registered class handlers on any EP0 event before going through default \r
+ * handling of the event. This gives the class handlers to implement class specific request handlers\r
+ * and also to override the default stack handling for a particular event targeted to the interface.\r
+ * If an event is not handled by the callback the function should return ERR_USBD_UNHANDLED. For all\r
+ * other return codes the stack assumes that callback has taken care of the event and hence will not\r
+ * process the event any further and issues a STALL condition on EP0 indicating error to the host.\r
+ * \n\r
+ * For endpoint interrupt handler the return value is ignored by the stack.\r
+ * \n\r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+typedef ErrorCode_t (*USB_EP_HANDLER_T)(USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+\r
+/** \ingroup USBD_Core \r
+ * \brief USB descriptors data structure.\r
+ * \ingroup USBD_Core\r
+ *\r
+ * \details This structure is used as part of USB device stack initialization\r
+ * parameter structure \ref USBD_API_INIT_PARAM_T. This structure contains\r
+ * pointers to various descriptor arrays needed by the stack. These descriptors\r
+ * are reported to USB host as part of enumerations process.\r
+ *\r
+ * \note All descriptor pointers assigned in this structure should be on 4 byte\r
+ * aligned address boundary.\r
+ */\r
+typedef struct _USB_CORE_DESCS_T\r
+{\r
+ uint8_t *device_desc; /**< Pointer to USB device descriptor */\r
+ uint8_t *string_desc; /**< Pointer to array of USB string descriptors */\r
+ uint8_t *full_speed_desc; /**< Pointer to USB device configuration descriptor\r
+ * when device is operating in full speed mode.\r
+ */\r
+ uint8_t *high_speed_desc; /**< Pointer to USB device configuration descriptor\r
+ * when device is operating in high speed mode. For\r
+ * full-speed only implementation this pointer should\r
+ * be same as full_speed_desc.\r
+ */\r
+ uint8_t *device_qualifier; /**< Pointer to USB device qualifier descriptor. For\r
+ * full-speed only implementation this pointer should\r
+ * be set to null (0).\r
+ */\r
+} USB_CORE_DESCS_T;\r
+\r
+/** \brief USB device stack initialization parameter data structure.\r
+ * \ingroup USBD_Core\r
+ *\r
+ * \details This data structure is used to pass initialization parameters to the \r
+ * USB device stack's init function.\r
+ *\r
+ */\r
+typedef struct USBD_API_INIT_PARAM\r
+{\r
+ uint32_t usb_reg_base; /**< USB device controller's base register address. */ \r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. \note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 2048 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use. \r
+ \note The \em mem_size should be greater than the size \r
+ returned by USBD_HW_API::GetMemSize() routine.*/\r
+ uint8_t max_num_ep; /**< max number of endpoints supported by the USB device \r
+ controller instance (specified by \em usb_reg_base field)\r
+ to which this instance of stack is attached. \r
+ */\r
+ uint8_t pad0[3];\r
+ /* USB Device Events Callback Functions */\r
+ /** Event for USB interface reset. This event fires when the USB host requests that the device \r
+ * reset its interface. This event fires after the control endpoint has been automatically\r
+ * configured by the library.\r
+ * \n\r
+ * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will prevent the device from enumerating correctly or operate properly.\r
+ *\r
+ */\r
+ USB_CB_T USB_Reset_Event;\r
+\r
+ /** Event for USB suspend. This event fires when the USB host suspends the device by halting its\r
+ * transmission of Start Of Frame pulses to the device. This is generally hooked in order to move\r
+ * the device over to a low power state until the host wakes up the device. \r
+ * \n\r
+ * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will cause other system issues.\r
+ */\r
+ USB_CB_T USB_Suspend_Event;\r
+\r
+ /** Event for USB wake up or resume. This event fires when a the USB device interface is suspended \r
+ * and the host wakes up the device by supplying Start Of Frame pulses. This is generally\r
+ * hooked to pull the user application out of a low power state and back into normal operating\r
+ * mode. \r
+ * \n\r
+ * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will cause other system issues.\r
+ *\r
+ */\r
+ USB_CB_T USB_Resume_Event;\r
+\r
+ /** Reserved parameter should be set to zero. */\r
+ USB_CB_T reserved_sbz;\r
+\r
+ /** Event for USB Start Of Frame detection, when enabled. This event fires at the start of each USB\r
+ * frame, once per millisecond in full-speed mode or once per 125 microseconds in high-speed mode,\r
+ * and is synchronized to the USB bus. \r
+ *\r
+ * This event is time-critical; it is run once per millisecond (full-speed mode) and thus long handlers \r
+ * will significantly degrade device performance. This event should only be enabled when needed to \r
+ * reduce device wake-ups.\r
+ *\r
+ * \note This event is not normally active - it must be manually enabled and disabled via the USB interrupt\r
+ * register.\r
+ * \n\n\r
+ */ \r
+ USB_CB_T USB_SOF_Event;\r
+\r
+ /** Event for remote wake-up configuration, when enabled. This event fires when the USB host\r
+ * request the device to configure itself for remote wake-up capability. The USB host sends\r
+ * this request to device which report remote wake-up capable in their device descriptors,\r
+ * before going to low-power state. The application layer should implement this callback if\r
+ * they have any special on board circuit to trigger remote wake up event. Also application\r
+ * can use this callback to differentiate the following SUSPEND event is caused by cable plug-out\r
+ * or host SUSPEND request. The device can wake-up host only after receiving this callback and\r
+ * remote wake-up feature is enabled by host. To signal remote wake-up the device has to generate\r
+ * resume signaling on bus by calling usapi.hw->WakeUp() routine.\r
+ *\r
+ * \n\n\r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] param1 When 0 - Clear the wake-up configuration, 1 - Enable the wake-up configuration.\r
+ * \return The call back should return \ref ErrorCode_t type to indicate success or error condition.\r
+ */ \r
+ USB_PARAM_CB_T USB_WakeUpCfg;\r
+\r
+ /** Reserved parameter should be set to zero. */\r
+ USB_PARAM_CB_T USB_Power_Event;\r
+\r
+ /** Event for error condition. This event fires when USB device controller detect \r
+ * an error condition in the system. \r
+ *\r
+ * \n\n\r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] param1 USB device interrupt status register. \r
+ * \return The call back should return \ref ErrorCode_t type to indicate success or error condition.\r
+ */ \r
+ USB_PARAM_CB_T USB_Error_Event;\r
+\r
+ /* USB Core Events Callback Functions */\r
+ /** Event for USB configuration number changed. This event fires when a the USB host changes the\r
+ * selected configuration number. On receiving configuration change request from host, the stack\r
+ * enables/configures the endpoints needed by the new configuration before calling this callback\r
+ * function.\r
+ * \n\r
+ * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will prevent the device from enumerating correctly or operate properly.\r
+ *\r
+ */\r
+ USB_CB_T USB_Configure_Event;\r
+\r
+ /** Event for USB interface setting changed. This event fires when a the USB host changes the\r
+ * interface setting to one of alternate interface settings. On receiving interface change \r
+ * request from host, the stack enables/configures the endpoints needed by the new alternate \r
+ * interface setting before calling this callback function.\r
+ * \n\r
+ * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will prevent the device from enumerating correctly or operate properly.\r
+ *\r
+ */\r
+ USB_CB_T USB_Interface_Event;\r
+\r
+ /** Event for USB feature changed. This event fires when a the USB host send set/clear feature\r
+ * request. The stack handles this request for USB_FEATURE_REMOTE_WAKEUP, USB_FEATURE_TEST_MODE\r
+ * and USB_FEATURE_ENDPOINT_STALL features only. On receiving feature request from host, the \r
+ * stack handle the request appropriately and then calls this callback function.\r
+ * \n\r
+ * \note This event is called from USB_ISR context and hence is time-critical. Having delays in this\r
+ * callback will prevent the device from enumerating correctly or operate properly.\r
+ *\r
+ */\r
+ USB_CB_T USB_Feature_Event;\r
+\r
+ /* cache and MMU translation functions */\r
+ /** Reserved parameter for future use. should be set to zero. */\r
+ uint32_t (* virt_to_phys)(void* vaddr);\r
+ /** Reserved parameter for future use. should be set to zero. */\r
+ void (* cache_flush)(uint32_t* start_adr, uint32_t* end_adr);\r
+\r
+} USBD_API_INIT_PARAM_T;\r
+\r
+\r
+/** \brief USBD stack Core API functions structure.\r
+ * \ingroup USBD_Core\r
+ *\r
+ * \details This module exposes functions which interact directly with USB device stack's core layer.\r
+ * The application layer uses this component when it has to implement custom class function driver or \r
+ * standard class function driver which is not part of the current USB device stack.\r
+ * The functions exposed by this interface are to register class specific EP0 handlers and corresponding\r
+ * utility functions to manipulate EP0 state machine of the stack. This interface also exposes\r
+ * function to register custom endpoint interrupt handler.\r
+ *\r
+ */\r
+typedef struct USBD_CORE_API \r
+{\r
+ /** \fn ErrorCode_t RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data)\r
+ * Function to register class specific EP0 event handler with USB device stack.\r
+ *\r
+ * The application layer uses this function when it has to register the custom class's EP0 handler. \r
+ * The stack calls all the registered class handlers on any EP0 event before going through default \r
+ * handling of the event. This gives the class handlers to implement class specific request handlers\r
+ * and also to override the default stack handling for a particular event targeted to the interface.\r
+ * Check \ref USB_EP_HANDLER_T for more details on how the callback function should be implemented. Also\r
+ * application layer could use this function to register EP0 handler which responds to vendor specific \r
+ * requests.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] pfn Class specific EP0 handler function.\r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success\r
+ * \retval ERR_USBD_TOO_MANY_CLASS_HDLR(0x0004000c) The number of class handlers registered is \r
+ greater than the number of handlers allowed by the stack.\r
+ * \r
+ */\r
+ ErrorCode_t (*RegisterClassHandler)(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data);\r
+\r
+ /** \fn ErrorCode_t RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data)\r
+ * Function to register interrupt/event handler for the requested endpoint with USB device stack.\r
+ *\r
+ * The application layer uses this function to register the endpoint event handler. \r
+ * The stack calls all the registered endpoint handlers when \r
+ * - USB_EVT_OUT or USB_EVT_OUT_NAK events happen for OUT endpoint. \r
+ * - USB_EVT_IN or USB_EVT_IN_NAK events happen for IN endpoint.\r
+ * Check USB_EP_HANDLER_T for more details on how the callback function should be implemented.\r
+ * \note By default endpoint _NAK events are not enabled. Application should call \ref USBD_HW_API_T::EnableEvent\r
+ * for the corresponding endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] ep_index Endpoint index. Computed as \r
+ * - For OUT endpoints = 2 * endpoint number eg. for EP2_OUT it is 4.\r
+ * - For IN endopoints = (2 * endpoint number) + 1 eg. for EP2_IN it is 5.\r
+ * \param[in] pfn Endpoint event handler function.\r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success\r
+ * \retval ERR_API_INVALID_PARAM2 ep_index is outside the boundary ( < 2 * USBD_API_INIT_PARAM_T::max_num_ep). \r
+ * \r
+ */\r
+ ErrorCode_t (*RegisterEpHandler)(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data);\r
+ \r
+ /** \fn void SetupStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in setup state.\r
+ *\r
+ * This function is called by USB stack and the application layer to \r
+ * set the EP0 state machine in setup state. This function will read\r
+ * the setup packet received from USB host into stack's buffer. \r
+ * \n\r
+ * \note This interface is provided to users to invoke this function in other \r
+ * scenarios which are not handle by current stack. In most user applications \r
+ * this function is not called directly.Also this function can be used by \r
+ * users who are selectively modifying the USB device stack's standard handlers \r
+ * through callback interface exposed by the stack.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return Nothing.\r
+ */\r
+ void (*SetupStage )(USBD_HANDLE_T hUsb); \r
+ \r
+ /** \fn void DataInStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in data_in state.\r
+ *\r
+ * This function is called by USB stack and the application layer to \r
+ * set the EP0 state machine in data_in state. This function will write\r
+ * the data present in EP0Data buffer to EP0 FIFO for transmission to host.\r
+ * \n\r
+ * \note This interface is provided to users to invoke this function in other \r
+ * scenarios which are not handle by current stack. In most user applications \r
+ * this function is not called directly.Also this function can be used by \r
+ * users who are selectively modifying the USB device stack's standard handlers \r
+ * through callback interface exposed by the stack.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return Nothing.\r
+ */\r
+ void (*DataInStage)(USBD_HANDLE_T hUsb);\r
+\r
+ /** \fn void DataOutStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in data_out state.\r
+ *\r
+ * This function is called by USB stack and the application layer to \r
+ * set the EP0 state machine in data_out state. This function will read\r
+ * the control data (EP0 out packets) received from USB host into EP0Data buffer. \r
+ * \n\r
+ * \note This interface is provided to users to invoke this function in other \r
+ * scenarios which are not handle by current stack. In most user applications \r
+ * this function is not called directly.Also this function can be used by \r
+ * users who are selectively modifying the USB device stack's standard handlers \r
+ * through callback interface exposed by the stack.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return Nothing.\r
+ */\r
+ void (*DataOutStage)(USBD_HANDLE_T hUsb); \r
+\r
+ /** \fn void StatusInStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in status_in state.\r
+ *\r
+ * This function is called by USB stack and the application layer to \r
+ * set the EP0 state machine in status_in state. This function will send\r
+ * zero length IN packet on EP0 to host, indicating positive status. \r
+ * \n\r
+ * \note This interface is provided to users to invoke this function in other \r
+ * scenarios which are not handle by current stack. In most user applications \r
+ * this function is not called directly.Also this function can be used by \r
+ * users who are selectively modifying the USB device stack's standard handlers \r
+ * through callback interface exposed by the stack.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return Nothing.\r
+ */\r
+ void (*StatusInStage)(USBD_HANDLE_T hUsb); \r
+ /** \fn void StatusOutStage(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in status_out state.\r
+ *\r
+ * This function is called by USB stack and the application layer to \r
+ * set the EP0 state machine in status_out state. This function will read\r
+ * the zero length OUT packet received from USB host on EP0. \r
+ * \n\r
+ * \note This interface is provided to users to invoke this function in other \r
+ * scenarios which are not handle by current stack. In most user applications \r
+ * this function is not called directly.Also this function can be used by \r
+ * users who are selectively modifying the USB device stack's standard handlers \r
+ * through callback interface exposed by the stack.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return Nothing.\r
+ */\r
+ void (*StatusOutStage)(USBD_HANDLE_T hUsb);\r
+\r
+ /** \fn void StallEp0(USBD_HANDLE_T hUsb)\r
+ * Function to set EP0 state machine in stall state.\r
+ *\r
+ * This function is called by USB stack and the application layer to \r
+ * generate STALL signaling on EP0 endpoint. This function will also\r
+ * reset the EP0Data buffer. \r
+ * \n\r
+ * \note This interface is provided to users to invoke this function in other \r
+ * scenarios which are not handle by current stack. In most user applications \r
+ * this function is not called directly.Also this function can be used by \r
+ * users who are selectively modifying the USB device stack's standard handlers \r
+ * through callback interface exposed by the stack.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return Nothing.\r
+ */\r
+ void (*StallEp0)(USBD_HANDLE_T hUsb);\r
+\r
+} USBD_CORE_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+\r
+ /** @cond ADVANCED_API */\r
+\r
+/* forward declaration */\r
+struct _USB_CORE_CTRL_T;\r
+typedef struct _USB_CORE_CTRL_T USB_CORE_CTRL_T;\r
+\r
+/* USB device Speed status defines */\r
+#define USB_FULL_SPEED 0\r
+#define USB_HIGH_SPEED 1\r
+\r
+/* USB Endpoint Data Structure */\r
+typedef struct _USB_EP_DATA\r
+{\r
+ uint8_t *pData;\r
+ uint16_t Count;\r
+ uint16_t pad0;\r
+} USB_EP_DATA;\r
+\r
+\r
+/* USB core controller data structure */\r
+struct _USB_CORE_CTRL_T\r
+{\r
+ /* override-able function pointers ~ c++ style virtual functions*/\r
+ USB_CB_T USB_EvtSetupHandler;\r
+ USB_CB_T USB_EvtOutHandler;\r
+ USB_PARAM_CB_T USB_ReqVendor;\r
+ USB_CB_T USB_ReqGetStatus;\r
+ USB_CB_T USB_ReqGetDescriptor;\r
+ USB_CB_T USB_ReqGetConfiguration;\r
+ USB_CB_T USB_ReqSetConfiguration;\r
+ USB_CB_T USB_ReqGetInterface;\r
+ USB_CB_T USB_ReqSetInterface;\r
+ USB_PARAM_CB_T USB_ReqSetClrFeature;\r
+\r
+ /* USB Device Events Callback Functions */\r
+ USB_CB_T USB_Reset_Event;\r
+ USB_CB_T USB_Suspend_Event;\r
+ USB_CB_T USB_Resume_Event;\r
+ USB_CB_T USB_SOF_Event;\r
+ USB_PARAM_CB_T USB_Power_Event;\r
+ USB_PARAM_CB_T USB_Error_Event;\r
+ USB_PARAM_CB_T USB_WakeUpCfg;\r
+\r
+ /* USB Core Events Callback Functions */\r
+ USB_CB_T USB_Configure_Event;\r
+ USB_CB_T USB_Interface_Event;\r
+ USB_CB_T USB_Feature_Event;\r
+\r
+ /* cache and MMU translation functions */\r
+ uint32_t (* virt_to_phys)(void* vaddr);\r
+ void (* cache_flush)(uint32_t* start_adr, uint32_t* end_adr);\r
+\r
+ /* event handlers for endpoints. */\r
+ USB_EP_HANDLER_T ep_event_hdlr[2 * USB_MAX_EP_NUM];\r
+ void* ep_hdlr_data[2 * USB_MAX_EP_NUM];\r
+\r
+ /* USB class handlers */\r
+ USB_EP_HANDLER_T ep0_hdlr_cb[USB_MAX_IF_NUM];\r
+ void* ep0_cb_data[USB_MAX_IF_NUM];\r
+ uint8_t num_ep0_hdlrs;\r
+ /* USB Core data Variables */\r
+ uint8_t max_num_ep; /* max number of endpoints supported by the HW */\r
+ uint8_t device_speed;\r
+ uint8_t num_interfaces;\r
+ uint8_t device_addr;\r
+ uint8_t config_value;\r
+ uint16_t device_status;\r
+ uint8_t *device_desc;\r
+ uint8_t *string_desc;\r
+ uint8_t *full_speed_desc;\r
+ uint8_t *high_speed_desc;\r
+ uint8_t *device_qualifier;\r
+ uint32_t ep_mask;\r
+ uint32_t ep_halt;\r
+ uint32_t ep_stall;\r
+ uint8_t alt_setting[USB_MAX_IF_NUM];\r
+ /* HW driver data pointer */\r
+ void* hw_data;\r
+\r
+ /* USB Endpoint 0 Data Info */\r
+ USB_EP_DATA EP0Data;\r
+\r
+ /* USB Endpoint 0 Buffer */\r
+ //ALIGNED(4)\r
+ uint8_t EP0Buf[64];\r
+\r
+ /* USB Setup Packet */\r
+ //ALIGNED(4)\r
+ USB_SETUP_PACKET SetupPacket;\r
+\r
+};\r
+\r
+/* USB Core Functions */\r
+extern void mwUSB_InitCore(USB_CORE_CTRL_T* pCtrl, USB_CORE_DESCS_T* pdescr, USBD_API_INIT_PARAM_T* param);\r
+extern void mwUSB_ResetCore(USBD_HANDLE_T hUsb);\r
+\r
+/* inline functions */\r
+static INLINE void USB_SetSpeedMode(USB_CORE_CTRL_T* pCtrl, uint8_t mode)\r
+{\r
+ pCtrl->device_speed = mode; \r
+}\r
+\r
+static INLINE bool USB_IsConfigured(USBD_HANDLE_T hUsb)\r
+{\r
+ USB_CORE_CTRL_T* pCtrl = (USB_CORE_CTRL_T*) hUsb;\r
+ return (bool) (pCtrl->config_value != 0); \r
+}\r
+\r
+/** @cond DIRECT_API */\r
+/* midleware API */\r
+extern ErrorCode_t mwUSB_RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data);\r
+extern ErrorCode_t mwUSB_RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data);\r
+extern void mwUSB_SetupStage (USBD_HANDLE_T hUsb); \r
+extern void mwUSB_DataInStage(USBD_HANDLE_T hUsb);\r
+extern void mwUSB_DataOutStage(USBD_HANDLE_T hUsb); \r
+extern void mwUSB_StatusInStage(USBD_HANDLE_T hUsb); \r
+extern void mwUSB_StatusOutStage(USBD_HANDLE_T hUsb);\r
+extern void mwUSB_StallEp0(USBD_HANDLE_T hUsb);\r
+extern ErrorCode_t mwUSB_RegisterClassHandler(USBD_HANDLE_T hUsb, USB_EP_HANDLER_T pfn, void* data);\r
+extern ErrorCode_t mwUSB_RegisterEpHandler(USBD_HANDLE_T hUsb, uint32_t ep_index, USB_EP_HANDLER_T pfn, void* data);\r
+extern void mwUSB_SetupStage (USBD_HANDLE_T hUsb); \r
+extern void mwUSB_DataInStage(USBD_HANDLE_T hUsb);\r
+extern void mwUSB_DataOutStage(USBD_HANDLE_T hUsb); \r
+extern void mwUSB_StatusInStage(USBD_HANDLE_T hUsb); \r
+extern void mwUSB_StatusOutStage(USBD_HANDLE_T hUsb);\r
+extern void mwUSB_StallEp0(USBD_HANDLE_T hUsb);\r
+/** @endcond */\r
+\r
+/** @endcond */\r
+\r
+#endif /* __MW_USBD_CORE_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_desc.h 165 2011-04-14 17:41:11Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* USB Descriptors Definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+#ifndef __USBDESC_H__\r
+#define __USBDESC_H__\r
+\r
+#include "usbd.h"\r
+\r
+#define WBVAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF)\r
+#define B3VAL(x) ((x) & 0xFF),(((x) >> 8) & 0xFF),(((x) >> 16) & 0xFF)\r
+\r
+#define USB_DEVICE_DESC_SIZE (sizeof(USB_DEVICE_DESCRIPTOR))\r
+#define USB_CONFIGUARTION_DESC_SIZE (sizeof(USB_CONFIGURATION_DESCRIPTOR))\r
+#define USB_INTERFACE_DESC_SIZE (sizeof(USB_INTERFACE_DESCRIPTOR))\r
+#define USB_ENDPOINT_DESC_SIZE (sizeof(USB_ENDPOINT_DESCRIPTOR))\r
+#define USB_DEVICE_QUALI_SIZE (sizeof(USB_DEVICE_QUALIFIER_DESCRIPTOR))\r
+#define USB_OTHER_SPEED_CONF_SIZE (sizeof(USB_OTHER_SPEED_CONFIGURATION))\r
+\r
+//#define HID_DESC_SIZE (sizeof(HID_DESCRIPTOR))\r
+//#define HID_REPORT_DESC_SIZE (sizeof(HID_ReportDescriptor))\r
+\r
+extern const uint8_t HID_ReportDescriptor[];\r
+extern const uint16_t HID_ReportDescSize;\r
+extern const uint16_t HID_DescOffset;\r
+\r
+\r
+#endif /* __USBDESC_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_dfu.h 331 2012-08-09 18:54:34Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* Device Firmware Upgrade (DFU) module.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+#ifndef __MW_USBD_DFU_H__\r
+#define __MW_USBD_DFU_H__\r
+\r
+#include "usbd.h"\r
+\r
+/** \file\r
+ * \brief Device Firmware Upgrade (DFU) class descriptors.\r
+ *\r
+ * Definition of DFU class descriptors and their bit defines.\r
+ *\r
+ */\r
+\r
+/**\r
+ * If USB device is only DFU capable, DFU Interface number is always 0.\r
+ * if USB device is (DFU + Other Class (Audio/Mass Storage/HID), DFU \r
+ * Interface number should also be 0 in this implementation.\r
+ */ \r
+#define USB_DFU_IF_NUM 0x0\r
+\r
+#define USB_DFU_DESCRIPTOR_TYPE 0x21\r
+#define USB_DFU_DESCRIPTOR_SIZE 9\r
+#define USB_DFU_SUBCLASS 0x01\r
+\r
+/* DFU class-specific requests (Section 3, DFU Rev 1.1) */\r
+#define USB_REQ_DFU_DETACH 0x00\r
+#define USB_REQ_DFU_DNLOAD 0x01\r
+#define USB_REQ_DFU_UPLOAD 0x02\r
+#define USB_REQ_DFU_GETSTATUS 0x03\r
+#define USB_REQ_DFU_CLRSTATUS 0x04\r
+#define USB_REQ_DFU_GETSTATE 0x05\r
+#define USB_REQ_DFU_ABORT 0x06\r
+\r
+#define DFU_STATUS_OK 0x00\r
+#define DFU_STATUS_errTARGET 0x01\r
+#define DFU_STATUS_errFILE 0x02\r
+#define DFU_STATUS_errWRITE 0x03\r
+#define DFU_STATUS_errERASE 0x04\r
+#define DFU_STATUS_errCHECK_ERASED 0x05\r
+#define DFU_STATUS_errPROG 0x06\r
+#define DFU_STATUS_errVERIFY 0x07\r
+#define DFU_STATUS_errADDRESS 0x08\r
+#define DFU_STATUS_errNOTDONE 0x09\r
+#define DFU_STATUS_errFIRMWARE 0x0a\r
+#define DFU_STATUS_errVENDOR 0x0b\r
+#define DFU_STATUS_errUSBR 0x0c\r
+#define DFU_STATUS_errPOR 0x0d\r
+#define DFU_STATUS_errUNKNOWN 0x0e\r
+#define DFU_STATUS_errSTALLEDPKT 0x0f\r
+\r
+enum dfu_state {\r
+ DFU_STATE_appIDLE = 0,\r
+ DFU_STATE_appDETACH = 1,\r
+ DFU_STATE_dfuIDLE = 2,\r
+ DFU_STATE_dfuDNLOAD_SYNC = 3,\r
+ DFU_STATE_dfuDNBUSY = 4,\r
+ DFU_STATE_dfuDNLOAD_IDLE = 5,\r
+ DFU_STATE_dfuMANIFEST_SYNC = 6,\r
+ DFU_STATE_dfuMANIFEST = 7,\r
+ DFU_STATE_dfuMANIFEST_WAIT_RST= 8,\r
+ DFU_STATE_dfuUPLOAD_IDLE = 9,\r
+ DFU_STATE_dfuERROR = 10\r
+};\r
+\r
+#define DFU_EP0_NONE 0\r
+#define DFU_EP0_UNHANDLED 1\r
+#define DFU_EP0_STALL 2\r
+#define DFU_EP0_ZLP 3\r
+#define DFU_EP0_DATA 4\r
+\r
+#define USB_DFU_CAN_DOWNLOAD (1 << 0)\r
+#define USB_DFU_CAN_UPLOAD (1 << 1)\r
+#define USB_DFU_MANIFEST_TOL (1 << 2)\r
+#define USB_DFU_WILL_DETACH (1 << 3)\r
+\r
+PRE_PACK struct POST_PACK _USB_DFU_FUNC_DESCRIPTOR {\r
+ uint8_t bLength;\r
+ uint8_t bDescriptorType;\r
+ uint8_t bmAttributes;\r
+ uint16_t wDetachTimeOut;\r
+ uint16_t wTransferSize;\r
+ uint16_t bcdDFUVersion;\r
+};\r
+typedef struct _USB_DFU_FUNC_DESCRIPTOR USB_DFU_FUNC_DESCRIPTOR;\r
+\r
+PRE_PACK struct POST_PACK _DFU_STATUS {\r
+ uint8_t bStatus;\r
+ uint8_t bwPollTimeout[3];\r
+ uint8_t bState;\r
+ uint8_t iString;\r
+};\r
+typedef struct _DFU_STATUS DFU_STATUS_T;\r
+\r
+#define DFU_FUNC_DESC_SIZE sizeof(USB_DFU_FUNC_DESCRIPTOR)\r
+#define DFU_GET_STATUS_SIZE 0x6 \r
+\r
+\r
+#endif /* __MW_USBD_DFU_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_dfuuser.h 331 2012-08-09 18:54:34Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* Device Firmware Upgrade Class Custom User Module Definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+#ifndef __DFUUSER_H__\r
+#define __DFUUSER_H__\r
+\r
+#include "usbd.h"\r
+#include "usbd_dfu.h"\r
+#include "usbd_core.h"\r
+\r
+/** \file\r
+ * \brief Device Firmware Upgrade (DFU) API structures and function prototypes.\r
+ *\r
+ * Definition of functions exported by ROM based DFU function driver.\r
+ *\r
+ */\r
+\r
+\r
+/** \ingroup Group_USBD\r
+ * @defgroup USBD_DFU Device Firmware Upgrade (DFU) Class Function Driver\r
+ * \section Sec_MSCModDescription Module Description\r
+ * DFU Class Function Driver module. This module contains an internal implementation of the USB DFU Class.\r
+ * User applications can use this class driver instead of implementing the DFU class manually\r
+ * via the low-level USBD_HW and USBD_Core APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB DFU Class.\r
+ */\r
+\r
+/** \brief USB descriptors data structure.\r
+ * \ingroup USBD_DFU\r
+ *\r
+ * \details This module exposes functions which interact directly with USB device stack's core layer.\r
+ * The application layer uses this component when it has to implement custom class function driver or \r
+ * standard class function driver which is not part of the current USB device stack.\r
+ * The functions exposed by this interface are to register class specific EP0 handlers and corresponding\r
+ * utility functions to manipulate EP0 state machine of the stack. This interface also exposes\r
+ * function to register custom endpoint interrupt handler.\r
+ *\r
+ */\r
+typedef struct USBD_DFU_INIT_PARAM\r
+{\r
+ /* memory allocation params */\r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. \note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 4 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use. \r
+ \note The \em mem_size should be greater than the size \r
+ returned by USBD_DFU_API::GetMemSize() routine.*/\r
+ /* DFU paramas */\r
+ uint16_t wTransferSize; /**< DFU transfer block size in number of bytes.\r
+ This value should match the value set in DFU descriptor\r
+ provided as part of the descriptor array \r
+ (\em high_speed_desc) passed to Init() through \r
+ \ref USB_CORE_DESCS_T structure. */\r
+\r
+ uint16_t pad;\r
+ /** Pointer to the DFU interface descriptor within the descriptor\r
+ * array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T \r
+ * structure. \r
+ */\r
+ uint8_t* intf_desc;\r
+ /* user defined functions */\r
+ /** \r
+ * DFU Write callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends a write command. For application using zero-copy buffer scheme\r
+ * this function is called for the first time with \em length parameter set to 0.\r
+ * The application code should update the buffer pointer.\r
+ * \r
+ * \param[in] block_num Destination start address. \r
+ * \param[in, out] src Pointer to a pointer to the source of data. Pointer-to-pointer\r
+ * is used to implement zero-copy buffers. See \ref USBD_ZeroCopy\r
+ * for more details on zero-copy concept.\r
+ * \param[out] bwPollTimeout Pointer to a 3 byte buffer which the callback implementer\r
+ * should fill with the amount of minimum time, in milliseconds, \r
+ * that the host should wait before sending a subsequent\r
+ * DFU_GETSTATUS request. \r
+ * \param[in] length Number of bytes to be written.\r
+ * \return Returns DFU_STATUS_ values defined in mw_usbd_dfu.h. \r
+ * \r
+ */\r
+ uint8_t (*DFU_Write)( uint32_t block_num, uint8_t** src, uint32_t length, uint8_t* bwPollTimeout);\r
+\r
+ /** \r
+ * DFU Read callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends a read command.\r
+ * \r
+ * \param[in] block_num Destination start address. \r
+ * \param[in, out] dst Pointer to a pointer to the source of data. Pointer-to-pointer\r
+ * is used to implement zero-copy buffers. See \ref USBD_ZeroCopy\r
+ * for more details on zero-copy concept.\r
+ * \param[in] length Amount of data copied to destination buffer.\r
+ * \return Returns \r
+ * - DFU_STATUS_ values defined in mw_usbd_dfu.h to return error conditions. \r
+ * - 0 if there is no more data to be read. Stack will send EOF frame and set \r
+ * DFU state-machine to dfuIdle state.\r
+ * - length of the data copied, should be greater than or equal to 16. If the data copied\r
+ * is less than DFU \em wTransferSize the stack will send EOF frame and \r
+ * goes to dfuIdle state.\r
+ * \r
+ */\r
+ uint32_t (*DFU_Read)( uint32_t block_num, uint8_t** dst, uint32_t length);\r
+\r
+ /** \r
+ * DFU done callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * after firmware download completes.\r
+ * \r
+ * \return Nothing. \r
+ * \r
+ */\r
+ void (*DFU_Done)(void);\r
+\r
+ /** \r
+ * DFU detach callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * after USB_REQ_DFU_DETACH is received. Applications which set USB_DFU_WILL_DETACH\r
+ * bit in DFU descriptor should define this function. As part of this function\r
+ * application can call Connect() routine to disconnect and then connect back with \r
+ * host. For application which rely on WinUSB based host application should use this\r
+ * feature since USB reset can be invoked only by kernel drivers on Windows host. \r
+ * By implementing this feature host doen't have to issue reset instead the device\r
+ * has to do it automatically by disconnect and connect procedure.\r
+ * \r
+ * \param[in] hUsb Handle DFU control structure. \r
+ * \return Nothing. \r
+ * \r
+ */\r
+ void (*DFU_Detach)(USBD_HANDLE_T hUsb);\r
+\r
+ /** \r
+ * Optional user override-able function to replace the default DFU class handler.\r
+ *\r
+ * The application software could override the default EP0 class handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_DFU_API::Init().\r
+ * \n\r
+ * \note \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*DFU_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+} USBD_DFU_INIT_PARAM_T;\r
+\r
+\r
+/** \brief DFU class API functions structure.\r
+ * \ingroup USBD_DFU\r
+ *\r
+ * This module exposes functions which interact directly with USB device controller hardware.\r
+ *\r
+ */\r
+typedef struct USBD_DFU_API\r
+{\r
+ /** \fn uint32_t GetMemSize(USBD_DFU_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the DFU function driver module.\r
+ * \r
+ * This function is called by application layer before calling pUsbApi->dfu->Init(), to allocate memory used \r
+ * by DFU function driver module. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller. \r
+ * \note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * \param[in] param Structure containing DFU function driver module initialization parameters.\r
+ * \return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_DFU_INIT_PARAM_T* param);\r
+\r
+ /** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param)\r
+ * Function to initialize DFU function driver module.\r
+ * \r
+ * This function is called by application layer to initialize DFU function driver module. \r
+ *\r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in, out] param Structure containing DFU function driver module initialization parameters.\r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success\r
+ * \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte aligned or smaller than required. \r
+ * \retval ERR_API_INVALID_PARAM2 Either DFU_Write() or DFU_Done() or DFU_Read() call-backs are not defined.\r
+ * \retval ERR_USBD_BAD_DESC \r
+ * - USB_DFU_DESCRIPTOR_TYPE is not defined immediately after \r
+ * interface descriptor.\r
+ * - wTransferSize in descriptor doesn't match the value passed \r
+ * in param->wTransferSize.\r
+ * - DFU_Detach() is not defined while USB_DFU_WILL_DETACH is set \r
+ * in DFU descriptor.\r
+ * \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. \r
+ */\r
+ ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param, uint32_t init_state);\r
+\r
+} USBD_DFU_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+/** @cond ADVANCED_API */\r
+\r
+typedef struct _USBD_DFU_CTRL_T\r
+{\r
+ /*ALIGNED(4)*/ DFU_STATUS_T dfu_req_get_status;\r
+ uint16_t pad;\r
+ uint8_t dfu_state;\r
+ uint8_t dfu_status;\r
+ uint8_t download_done;\r
+ uint8_t if_num; /* interface number */\r
+\r
+ uint8_t* xfr_buf;\r
+ USB_DFU_FUNC_DESCRIPTOR* dfu_desc;\r
+\r
+ USB_CORE_CTRL_T* pUsbCtrl;\r
+ /* user defined functions */\r
+ /* return DFU_STATUS_ values defined in mw_usbd_dfu.h */\r
+ uint8_t (*DFU_Write)( uint32_t block_num, uint8_t** src, uint32_t length, uint8_t* bwPollTimeout);\r
+ /* return \r
+ * DFU_STATUS_ : values defined in mw_usbd_dfu.h in case of errors\r
+ * 0 : If end of memory reached\r
+ * length : Amount of data copied to destination buffer\r
+ */\r
+ uint32_t (*DFU_Read)( uint32_t block_num, uint8_t** dst, uint32_t length);\r
+ /* callback called after download is finished */\r
+ void (*DFU_Done)(void);\r
+ /* callback called after USB_REQ_DFU_DETACH is recived */\r
+ void (*DFU_Detach)(USBD_HANDLE_T hUsb);\r
+\r
+} USBD_DFU_CTRL_T;\r
+\r
+/** @cond DIRECT_API */\r
+uint32_t mwDFU_GetMemSize(USBD_DFU_INIT_PARAM_T* param);\r
+extern ErrorCode_t mwDFU_init(USBD_HANDLE_T hUsb, USBD_DFU_INIT_PARAM_T* param, uint32_t init_state);\r
+/** @endcond */\r
+\r
+/** @endcond */\r
+\r
+#endif /* __DFUUSER_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id: mw_usbd_hid.h.rca 1.2 Tue Nov 1 11:45:07 2011 nlv09221 Experimental $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* HID Definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+#ifndef __HID_H__\r
+#define __HID_H__\r
+\r
+#include "usbd.h"\r
+\r
+/** \file\r
+ * \brief Common definitions and declarations for the library USB HID Class driver.\r
+ *\r
+ * Common definitions and declarations for the library USB HID Class driver.\r
+ * \addtogroup USBD_HID \r
+ * @{\r
+ */\r
+\r
+\r
+/** HID Subclass Codes \r
+ * @{ \r
+ */\r
+/** Descriptor Subclass value indicating that the device or interface does not implement a HID boot protocol. */\r
+#define HID_SUBCLASS_NONE 0x00\r
+/** Descriptor Subclass value indicating that the device or interface implements a HID boot protocol. */\r
+#define HID_SUBCLASS_BOOT 0x01\r
+/** @} */\r
+\r
+/** HID Protocol Codes \r
+ * @{ \r
+ */\r
+/** Descriptor Protocol value indicating that the device or interface does not belong to a HID boot protocol. */\r
+#define HID_PROTOCOL_NONE 0x00\r
+/** Descriptor Protocol value indicating that the device or interface belongs to the Keyboard HID boot protocol. */\r
+#define HID_PROTOCOL_KEYBOARD 0x01\r
+/** Descriptor Protocol value indicating that the device or interface belongs to the Mouse HID boot protocol. */\r
+#define HID_PROTOCOL_MOUSE 0x02\r
+/** @} */\r
+\r
+\r
+\r
+/** Descriptor Types \r
+ * @{ \r
+ */\r
+/** Descriptor header type value, to indicate a HID class HID descriptor. */\r
+#define HID_HID_DESCRIPTOR_TYPE 0x21\r
+/** Descriptor header type value, to indicate a HID class HID report descriptor. */\r
+#define HID_REPORT_DESCRIPTOR_TYPE 0x22\r
+/** Descriptor header type value, to indicate a HID class HID Physical descriptor. */\r
+#define HID_PHYSICAL_DESCRIPTOR_TYPE 0x23\r
+/** @} */\r
+\r
+\r
+/** \brief HID class-specific HID Descriptor.\r
+ *\r
+ * Type define for the HID class-specific HID descriptor, to describe the HID device's specifications. Refer to the HID\r
+ * specification for details on the structure elements.\r
+ *\r
+ */\r
+PRE_PACK struct POST_PACK _HID_DESCRIPTOR {\r
+ uint8_t bLength; /**< Size of the descriptor, in bytes. */\r
+ uint8_t bDescriptorType; /**< Type of HID descriptor. */\r
+ uint16_t bcdHID; /**< BCD encoded version that the HID descriptor and device complies to. */\r
+ uint8_t bCountryCode; /**< Country code of the localized device, or zero if universal. */\r
+ uint8_t bNumDescriptors; /**< Total number of HID report descriptors for the interface. */\r
+ \r
+ PRE_PACK struct POST_PACK _HID_DESCRIPTOR_LIST {\r
+ uint8_t bDescriptorType; /**< Type of HID report. */\r
+ uint16_t wDescriptorLength; /**< Length of the associated HID report descriptor, in bytes. */\r
+ } DescriptorList[1]; /**< Array of one or more descriptors */\r
+} ;\r
+/** HID class-specific HID Descriptor. */\r
+typedef struct _HID_DESCRIPTOR HID_DESCRIPTOR;\r
+\r
+#define HID_DESC_SIZE sizeof(HID_DESCRIPTOR)\r
+\r
+/** HID Request Codes \r
+ * @{ \r
+ */\r
+#define HID_REQUEST_GET_REPORT 0x01\r
+#define HID_REQUEST_GET_IDLE 0x02\r
+#define HID_REQUEST_GET_PROTOCOL 0x03\r
+#define HID_REQUEST_SET_REPORT 0x09\r
+#define HID_REQUEST_SET_IDLE 0x0A\r
+#define HID_REQUEST_SET_PROTOCOL 0x0B\r
+/** @} */\r
+\r
+/** HID Report Types \r
+ * @{ \r
+ */\r
+#define HID_REPORT_INPUT 0x01\r
+#define HID_REPORT_OUTPUT 0x02\r
+#define HID_REPORT_FEATURE 0x03\r
+/** @} */\r
+\r
+\r
+/** Usage Pages \r
+ * @{ \r
+ */\r
+#define HID_USAGE_PAGE_UNDEFINED 0x00\r
+#define HID_USAGE_PAGE_GENERIC 0x01\r
+#define HID_USAGE_PAGE_SIMULATION 0x02\r
+#define HID_USAGE_PAGE_VR 0x03\r
+#define HID_USAGE_PAGE_SPORT 0x04\r
+#define HID_USAGE_PAGE_GAME 0x05\r
+#define HID_USAGE_PAGE_DEV_CONTROLS 0x06\r
+#define HID_USAGE_PAGE_KEYBOARD 0x07\r
+#define HID_USAGE_PAGE_LED 0x08\r
+#define HID_USAGE_PAGE_BUTTON 0x09\r
+#define HID_USAGE_PAGE_ORDINAL 0x0A\r
+#define HID_USAGE_PAGE_TELEPHONY 0x0B\r
+#define HID_USAGE_PAGE_CONSUMER 0x0C\r
+#define HID_USAGE_PAGE_DIGITIZER 0x0D\r
+#define HID_USAGE_PAGE_UNICODE 0x10\r
+#define HID_USAGE_PAGE_ALPHANUMERIC 0x14\r
+/** @} */\r
+\r
+\r
+/** Generic Desktop Page (0x01) \r
+ * @{ \r
+ */\r
+#define HID_USAGE_GENERIC_POINTER 0x01\r
+#define HID_USAGE_GENERIC_MOUSE 0x02\r
+#define HID_USAGE_GENERIC_JOYSTICK 0x04\r
+#define HID_USAGE_GENERIC_GAMEPAD 0x05\r
+#define HID_USAGE_GENERIC_KEYBOARD 0x06\r
+#define HID_USAGE_GENERIC_KEYPAD 0x07\r
+#define HID_USAGE_GENERIC_X 0x30\r
+#define HID_USAGE_GENERIC_Y 0x31\r
+#define HID_USAGE_GENERIC_Z 0x32\r
+#define HID_USAGE_GENERIC_RX 0x33\r
+#define HID_USAGE_GENERIC_RY 0x34\r
+#define HID_USAGE_GENERIC_RZ 0x35\r
+#define HID_USAGE_GENERIC_SLIDER 0x36\r
+#define HID_USAGE_GENERIC_DIAL 0x37\r
+#define HID_USAGE_GENERIC_WHEEL 0x38\r
+#define HID_USAGE_GENERIC_HATSWITCH 0x39\r
+#define HID_USAGE_GENERIC_COUNTED_BUFFER 0x3A\r
+#define HID_USAGE_GENERIC_BYTE_COUNT 0x3B\r
+#define HID_USAGE_GENERIC_MOTION_WAKEUP 0x3C\r
+#define HID_USAGE_GENERIC_VX 0x40\r
+#define HID_USAGE_GENERIC_VY 0x41\r
+#define HID_USAGE_GENERIC_VZ 0x42\r
+#define HID_USAGE_GENERIC_VBRX 0x43\r
+#define HID_USAGE_GENERIC_VBRY 0x44\r
+#define HID_USAGE_GENERIC_VBRZ 0x45\r
+#define HID_USAGE_GENERIC_VNO 0x46\r
+#define HID_USAGE_GENERIC_SYSTEM_CTL 0x80\r
+#define HID_USAGE_GENERIC_SYSCTL_POWER 0x81\r
+#define HID_USAGE_GENERIC_SYSCTL_SLEEP 0x82\r
+#define HID_USAGE_GENERIC_SYSCTL_WAKE 0x83\r
+#define HID_USAGE_GENERIC_SYSCTL_CONTEXT_MENU 0x84\r
+#define HID_USAGE_GENERIC_SYSCTL_MAIN_MENU 0x85\r
+#define HID_USAGE_GENERIC_SYSCTL_APP_MENU 0x86\r
+#define HID_USAGE_GENERIC_SYSCTL_HELP_MENU 0x87\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_EXIT 0x88\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_SELECT 0x89\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_RIGHT 0x8A\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_LEFT 0x8B\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_UP 0x8C\r
+#define HID_USAGE_GENERIC_SYSCTL_MENU_DOWN 0x8D\r
+/** @} */\r
+\r
+/** Simulation Controls Page (0x02) \r
+ * @{ \r
+ */\r
+#define HID_USAGE_SIMULATION_RUDDER 0xBA\r
+#define HID_USAGE_SIMULATION_THROTTLE 0xBB\r
+/** @} */\r
+\r
+/* Virtual Reality Controls Page (0x03) */\r
+/* ... */\r
+\r
+/* Sport Controls Page (0x04) */\r
+/* ... */\r
+\r
+/* Game Controls Page (0x05) */\r
+/* ... */\r
+\r
+/* Generic Device Controls Page (0x06) */\r
+/* ... */\r
+\r
+/** Keyboard/Keypad Page (0x07) \r
+ * @{ \r
+ */\r
+/** Error "keys" */\r
+#define HID_USAGE_KEYBOARD_NOEVENT 0x00\r
+#define HID_USAGE_KEYBOARD_ROLLOVER 0x01\r
+#define HID_USAGE_KEYBOARD_POSTFAIL 0x02\r
+#define HID_USAGE_KEYBOARD_UNDEFINED 0x03\r
+\r
+/** Letters */\r
+#define HID_USAGE_KEYBOARD_aA 0x04\r
+#define HID_USAGE_KEYBOARD_zZ 0x1D\r
+\r
+/** Numbers */\r
+#define HID_USAGE_KEYBOARD_ONE 0x1E\r
+#define HID_USAGE_KEYBOARD_ZERO 0x27\r
+\r
+#define HID_USAGE_KEYBOARD_RETURN 0x28\r
+#define HID_USAGE_KEYBOARD_ESCAPE 0x29\r
+#define HID_USAGE_KEYBOARD_DELETE 0x2A\r
+\r
+/** Funtion keys */\r
+#define HID_USAGE_KEYBOARD_F1 0x3A\r
+#define HID_USAGE_KEYBOARD_F12 0x45\r
+\r
+#define HID_USAGE_KEYBOARD_PRINT_SCREEN 0x46\r
+\r
+/** Modifier Keys */\r
+#define HID_USAGE_KEYBOARD_LCTRL 0xE0\r
+#define HID_USAGE_KEYBOARD_LSHFT 0xE1\r
+#define HID_USAGE_KEYBOARD_LALT 0xE2\r
+#define HID_USAGE_KEYBOARD_LGUI 0xE3\r
+#define HID_USAGE_KEYBOARD_RCTRL 0xE4\r
+#define HID_USAGE_KEYBOARD_RSHFT 0xE5\r
+#define HID_USAGE_KEYBOARD_RALT 0xE6\r
+#define HID_USAGE_KEYBOARD_RGUI 0xE7\r
+#define HID_USAGE_KEYBOARD_SCROLL_LOCK 0x47\r
+#define HID_USAGE_KEYBOARD_NUM_LOCK 0x53\r
+#define HID_USAGE_KEYBOARD_CAPS_LOCK 0x39\r
+/** @} */\r
+\r
+/* ... */\r
+\r
+/** LED Page (0x08) \r
+ * @{ \r
+ */\r
+#define HID_USAGE_LED_NUM_LOCK 0x01\r
+#define HID_USAGE_LED_CAPS_LOCK 0x02\r
+#define HID_USAGE_LED_SCROLL_LOCK 0x03\r
+#define HID_USAGE_LED_COMPOSE 0x04\r
+#define HID_USAGE_LED_KANA 0x05\r
+#define HID_USAGE_LED_POWER 0x06\r
+#define HID_USAGE_LED_SHIFT 0x07\r
+#define HID_USAGE_LED_DO_NOT_DISTURB 0x08\r
+#define HID_USAGE_LED_MUTE 0x09\r
+#define HID_USAGE_LED_TONE_ENABLE 0x0A\r
+#define HID_USAGE_LED_HIGH_CUT_FILTER 0x0B\r
+#define HID_USAGE_LED_LOW_CUT_FILTER 0x0C\r
+#define HID_USAGE_LED_EQUALIZER_ENABLE 0x0D\r
+#define HID_USAGE_LED_SOUND_FIELD_ON 0x0E\r
+#define HID_USAGE_LED_SURROUND_FIELD_ON 0x0F\r
+#define HID_USAGE_LED_REPEAT 0x10\r
+#define HID_USAGE_LED_STEREO 0x11\r
+#define HID_USAGE_LED_SAMPLING_RATE_DETECT 0x12\r
+#define HID_USAGE_LED_SPINNING 0x13\r
+#define HID_USAGE_LED_CAV 0x14\r
+#define HID_USAGE_LED_CLV 0x15\r
+#define HID_USAGE_LED_RECORDING_FORMAT_DET 0x16\r
+#define HID_USAGE_LED_OFF_HOOK 0x17\r
+#define HID_USAGE_LED_RING 0x18\r
+#define HID_USAGE_LED_MESSAGE_WAITING 0x19\r
+#define HID_USAGE_LED_DATA_MODE 0x1A\r
+#define HID_USAGE_LED_BATTERY_OPERATION 0x1B\r
+#define HID_USAGE_LED_BATTERY_OK 0x1C\r
+#define HID_USAGE_LED_BATTERY_LOW 0x1D\r
+#define HID_USAGE_LED_SPEAKER 0x1E\r
+#define HID_USAGE_LED_HEAD_SET 0x1F\r
+#define HID_USAGE_LED_HOLD 0x20\r
+#define HID_USAGE_LED_MICROPHONE 0x21\r
+#define HID_USAGE_LED_COVERAGE 0x22\r
+#define HID_USAGE_LED_NIGHT_MODE 0x23\r
+#define HID_USAGE_LED_SEND_CALLS 0x24\r
+#define HID_USAGE_LED_CALL_PICKUP 0x25\r
+#define HID_USAGE_LED_CONFERENCE 0x26\r
+#define HID_USAGE_LED_STAND_BY 0x27\r
+#define HID_USAGE_LED_CAMERA_ON 0x28\r
+#define HID_USAGE_LED_CAMERA_OFF 0x29\r
+#define HID_USAGE_LED_ON_LINE 0x2A\r
+#define HID_USAGE_LED_OFF_LINE 0x2B\r
+#define HID_USAGE_LED_BUSY 0x2C\r
+#define HID_USAGE_LED_READY 0x2D\r
+#define HID_USAGE_LED_PAPER_OUT 0x2E\r
+#define HID_USAGE_LED_PAPER_JAM 0x2F\r
+#define HID_USAGE_LED_REMOTE 0x30\r
+#define HID_USAGE_LED_FORWARD 0x31\r
+#define HID_USAGE_LED_REVERSE 0x32\r
+#define HID_USAGE_LED_STOP 0x33\r
+#define HID_USAGE_LED_REWIND 0x34\r
+#define HID_USAGE_LED_FAST_FORWARD 0x35\r
+#define HID_USAGE_LED_PLAY 0x36\r
+#define HID_USAGE_LED_PAUSE 0x37\r
+#define HID_USAGE_LED_RECORD 0x38\r
+#define HID_USAGE_LED_ERROR 0x39\r
+#define HID_USAGE_LED_SELECTED_INDICATOR 0x3A\r
+#define HID_USAGE_LED_IN_USE_INDICATOR 0x3B\r
+#define HID_USAGE_LED_MULTI_MODE_INDICATOR 0x3C\r
+#define HID_USAGE_LED_INDICATOR_ON 0x3D\r
+#define HID_USAGE_LED_INDICATOR_FLASH 0x3E\r
+#define HID_USAGE_LED_INDICATOR_SLOW_BLINK 0x3F\r
+#define HID_USAGE_LED_INDICATOR_FAST_BLINK 0x40\r
+#define HID_USAGE_LED_INDICATOR_OFF 0x41\r
+#define HID_USAGE_LED_FLASH_ON_TIME 0x42\r
+#define HID_USAGE_LED_SLOW_BLINK_ON_TIME 0x43\r
+#define HID_USAGE_LED_SLOW_BLINK_OFF_TIME 0x44\r
+#define HID_USAGE_LED_FAST_BLINK_ON_TIME 0x45\r
+#define HID_USAGE_LED_FAST_BLINK_OFF_TIME 0x46\r
+#define HID_USAGE_LED_INDICATOR_COLOR 0x47\r
+#define HID_USAGE_LED_RED 0x48\r
+#define HID_USAGE_LED_GREEN 0x49\r
+#define HID_USAGE_LED_AMBER 0x4A\r
+#define HID_USAGE_LED_GENERIC_INDICATOR 0x4B\r
+/** @} */\r
+\r
+/* Button Page (0x09) \r
+ */\r
+/* There is no need to label these usages. */\r
+\r
+/* Ordinal Page (0x0A) \r
+ */\r
+/* There is no need to label these usages. */\r
+\r
+/** Telephony Device Page (0x0B) \r
+ * @{ \r
+ */\r
+#define HID_USAGE_TELEPHONY_PHONE 0x01\r
+#define HID_USAGE_TELEPHONY_ANSWERING_MACHINE 0x02\r
+#define HID_USAGE_TELEPHONY_MESSAGE_CONTROLS 0x03\r
+#define HID_USAGE_TELEPHONY_HANDSET 0x04\r
+#define HID_USAGE_TELEPHONY_HEADSET 0x05\r
+#define HID_USAGE_TELEPHONY_KEYPAD 0x06\r
+#define HID_USAGE_TELEPHONY_PROGRAMMABLE_BUTTON 0x07\r
+/** @} */\r
+/* ... */\r
+\r
+/** Consumer Page (0x0C) \r
+ * @{ \r
+ */\r
+#define HID_USAGE_CONSUMER_CONTROL 0x01\r
+#define HID_USAGE_CONSUMER_FAST_FORWARD 0xB3\r
+#define HID_USAGE_CONSUMER_REWIND 0xB4\r
+#define HID_USAGE_CONSUMER_PLAY_PAUSE 0xCD\r
+#define HID_USAGE_CONSUMER_VOLUME_INCREMENT 0xE9\r
+#define HID_USAGE_CONSUMER_VOLUME_DECREMENT 0xEA\r
+/** @} */\r
+/* ... */\r
+\r
+/* and others ... */\r
+\r
+\r
+/** HID Report Item Macros \r
+ * @{ \r
+ */\r
+/** Main Items */\r
+#define HID_Input(x) 0x81,x\r
+#define HID_Output(x) 0x91,x\r
+#define HID_Feature(x) 0xB1,x\r
+#define HID_Collection(x) 0xA1,x\r
+#define HID_EndCollection 0xC0\r
+\r
+/** Data (Input, Output, Feature) */\r
+#define HID_Data 0<<0\r
+#define HID_Constant 1<<0\r
+#define HID_Array 0<<1\r
+#define HID_Variable 1<<1\r
+#define HID_Absolute 0<<2\r
+#define HID_Relative 1<<2\r
+#define HID_NoWrap 0<<3\r
+#define HID_Wrap 1<<3\r
+#define HID_Linear 0<<4\r
+#define HID_NonLinear 1<<4\r
+#define HID_PreferredState 0<<5\r
+#define HID_NoPreferred 1<<5\r
+#define HID_NoNullPosition 0<<6\r
+#define HID_NullState 1<<6\r
+#define HID_NonVolatile 0<<7\r
+#define HID_Volatile 1<<7\r
+\r
+/** Collection Data */\r
+#define HID_Physical 0x00\r
+#define HID_Application 0x01\r
+#define HID_Logical 0x02\r
+#define HID_Report 0x03\r
+#define HID_NamedArray 0x04\r
+#define HID_UsageSwitch 0x05\r
+#define HID_UsageModifier 0x06\r
+\r
+/** Global Items */\r
+#define HID_UsagePage(x) 0x05,x\r
+#define HID_UsagePageVendor(x) 0x06,x,0xFF\r
+#define HID_LogicalMin(x) 0x15,x\r
+#define HID_LogicalMinS(x) 0x16,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_LogicalMinL(x) 0x17,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_LogicalMax(x) 0x25,x\r
+#define HID_LogicalMaxS(x) 0x26,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_LogicalMaxL(x) 0x27,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_PhysicalMin(x) 0x35,x\r
+#define HID_PhysicalMinS(x) 0x36,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_PhysicalMinL(x) 0x37,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_PhysicalMax(x) 0x45,x\r
+#define HID_PhysicalMaxS(x) 0x46,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_PhysicalMaxL(x) 0x47,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_UnitExponent(x) 0x55,x\r
+#define HID_Unit(x) 0x65,x\r
+#define HID_UnitS(x) 0x66,(x&0xFF),((x>>8)&0xFF)\r
+#define HID_UnitL(x) 0x67,(x&0xFF),((x>>8)&0xFF),((x>>16)&0xFF),((x>>24)&0xFF)\r
+#define HID_ReportSize(x) 0x75,x\r
+#define HID_ReportID(x) 0x85,x\r
+#define HID_ReportCount(x) 0x95,x\r
+#define HID_Push 0xA0\r
+#define HID_Pop 0xB0\r
+\r
+/** Local Items */\r
+#define HID_Usage(x) 0x09,x\r
+#define HID_UsageMin(x) 0x19,x\r
+#define HID_UsageMax(x) 0x29,x\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+#endif /* __HID_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_hiduser.h 331 2012-08-09 18:54:34Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* HID Custom User Module Definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+#ifndef __HIDUSER_H__\r
+#define __HIDUSER_H__\r
+\r
+#include "usbd.h"\r
+#include "usbd_hid.h"\r
+#include "usbd_core.h"\r
+\r
+/** \file\r
+ * \brief Human Interface Device (HID) API structures and function prototypes.\r
+ *\r
+ * Definition of functions exported by ROM based HID function driver.\r
+ *\r
+ */\r
+\r
+/** \ingroup Group_USBD\r
+ * @defgroup USBD_HID HID Class Function Driver\r
+ * \section Sec_HIDModDescription Module Description\r
+ * HID Class Function Driver module. This module contains an internal implementation of the USB HID Class.\r
+ * User applications can use this class driver instead of implementing the HID class manually\r
+ * via the low-level HW and core APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB HID Class.\r
+ */\r
+\r
+/** \brief HID report descriptor data structure. \r
+ * \ingroup USBD_HID\r
+ *\r
+ * \details This structure is used as part of HID function driver initialization \r
+ * parameter structure \ref USBD_HID_INIT_PARAM. This structure contains\r
+ * details of a report type supported by the application. An application\r
+ * can support multiple report types as a single HID device. The application\r
+ * should define this report type data structure per report it supports and\r
+ * the array of report types to USBD_HID_API::init() through \ref USBD_HID_INIT_PARAM\r
+ * structure. \r
+ *\r
+ * \note All descriptor pointers assigned in this structure should be on 4 byte\r
+ * aligned address boundary. \r
+ *\r
+ */\r
+typedef struct _HID_REPORT_T {\r
+ uint16_t len; /**< Size of the report descriptor in bytes. */ \r
+ uint8_t idle_time; /**< This value is used by stack to respond to Set_Idle & \r
+ GET_Idle requests for the specified report ID. The value\r
+ of this field specified the rate at which duplicate reports \r
+ are generated for the specified Report ID. For example, a \r
+ device with two input reports could specify an idle rate of \r
+ 20 milliseconds for report ID 1 and 500 milliseconds for \r
+ report ID 2.\r
+ */\r
+ uint8_t __pad; /**< Padding space. */\r
+ uint8_t* desc; /**< Report descriptor. */\r
+} USB_HID_REPORT_T;\r
+\r
+/** \brief USB descriptors data structure. \r
+ * \ingroup USBD_HID\r
+ *\r
+ * \details This module exposes functions which interact directly with USB device stack's core layer.\r
+ * The application layer uses this component when it has to implement custom class function driver or \r
+ * standard class function driver which is not part of the current USB device stack.\r
+ * The functions exposed by this interface are to register class specific EP0 handlers and corresponding\r
+ * utility functions to manipulate EP0 state machine of the stack. This interface also exposes\r
+ * function to register custom endpoint interrupt handler.\r
+ *\r
+ */\r
+typedef struct USBD_HID_INIT_PARAM\r
+{\r
+ /* memory allocation params */\r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. \note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 4 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use. \r
+ \note The \em mem_size should be greater than the size \r
+ returned by USBD_HID_API::GetMemSize() routine.*/\r
+ /* HID paramas */\r
+ uint8_t max_reports; /**< Number of HID reports supported by this instance\r
+ of HID class driver. \r
+ */\r
+ uint8_t pad[3];\r
+ uint8_t* intf_desc; /**< Pointer to the HID interface descriptor within the \r
+ descriptor array (\em high_speed_desc) passed to Init()\r
+ through \ref USB_CORE_DESCS_T structure. \r
+ */\r
+ USB_HID_REPORT_T* report_data; /**< Pointer to an array of HID report descriptor\r
+ data structure (\ref USB_HID_REPORT_T). The number\r
+ of elements in the array should be same a \em max_reports\r
+ value. The stack uses this array to respond to \r
+ requests received for various HID report descriptor\r
+ information. \note This array should be of global scope.\r
+ */\r
+\r
+ /* user defined functions */\r
+ /* required functions */\r
+ /** \r
+ * HID get report callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends a HID_REQUEST_GET_REPORT request. The setup packet data (\em pSetup)\r
+ * is passed to the callback so that application can extract the report ID, report\r
+ * type and other information need to generate the report. \note HID reports are sent\r
+ * via interrupt IN endpoint also. This function is called only when report request\r
+ * is received on control endpoint. Application should implement \em HID_EpIn_Hdlr to\r
+ * send reports to host via interrupt IN endpoint.\r
+ * \r
+ * \r
+ * \param[in] hHid Handle to HID function driver. \r
+ * \param[in] pSetup Pointer to setup packet received from host.\r
+ * \param[in, out] pBuffer Pointer to a pointer of data buffer containing report data. \r
+ * Pointer-to-pointer is used to implement zero-copy buffers. \r
+ * See \ref USBD_ZeroCopy for more details on zero-copy concept.\r
+ * \param[in] length Amount of data copied to destination buffer.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*HID_GetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length); \r
+ \r
+ /** \r
+ * HID set report callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends a HID_REQUEST_SET_REPORT request. The setup packet data (\em pSetup)\r
+ * is passed to the callback so that application can extract the report ID, report\r
+ * type and other information need to modify the report. An application might choose \r
+ * to ignore input Set_Report requests as meaningless. Alternatively these reports \r
+ * could be used to reset the origin of a control (that is, current position should \r
+ * report zero).\r
+ * \r
+ * \param[in] hHid Handle to HID function driver. \r
+ * \param[in] pSetup Pointer to setup packet received from host.\r
+ * \param[in, out] pBuffer Pointer to a pointer of data buffer containing report data. \r
+ * Pointer-to-pointer is used to implement zero-copy buffers. \r
+ * See \ref USBD_ZeroCopy for more details on zero-copy concept.\r
+ * \param[in] length Amount of data copied to destination buffer.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*HID_SetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);\r
+ \r
+ /* optional functions */\r
+ \r
+ /** \r
+ * Optional callback function to handle HID_GetPhysDesc request.\r
+ *\r
+ * The application software could provide this callback HID_GetPhysDesc handler to\r
+ * handle get physical descriptor requests sent by the host. When host requests \r
+ * Physical Descriptor set 0, application should return a special descriptor\r
+ * identifying the number of descriptor sets and their sizes. A Get_Descriptor \r
+ * request with the Physical Index equal to 1 should return the first Physical \r
+ * Descriptor set. A device could possibly have alternate uses for its items. \r
+ * These can be enumerated by issuing subsequent Get_Descriptor requests while \r
+ * incrementing the Descriptor Index. A device should return the last descriptor\r
+ * set to requests with an index greater than the last number defined in the HID \r
+ * descriptor.\r
+ * \note Applications which don't have physical descriptor should set this data member\r
+ * to zero before calling the USBD_HID_API::Init().\r
+ * \n\r
+ * \r
+ * \param[in] hHid Handle to HID function driver. \r
+ * \param[in] pSetup Pointer to setup packet received from host.\r
+ * \param[in] pBuf Pointer to a pointer of data buffer containing physical descriptor \r
+ * data. If the physical descriptor is in USB accessible memory area\r
+ * application could just update the pointer or else it should copy \r
+ * the descriptor to the address pointed by this pointer.\r
+ * \param[in] length Amount of data copied to destination buffer or descriptor length.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*HID_GetPhysDesc)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);\r
+\r
+ /** \r
+ * Optional callback function to handle HID_REQUEST_SET_IDLE request.\r
+ *\r
+ * The application software could provide this callback to handle HID_REQUEST_SET_IDLE\r
+ * requests sent by the host. This callback is provided to applications to adjust\r
+ * timers associated with various reports, which are sent to host over interrupt \r
+ * endpoint. The setup packet data (\em pSetup) is passed to the callback so that\r
+ * application can extract the report ID, report type and other information need \r
+ * to modify the report's idle time.\r
+ * \note Applications which don't send reports on Interrupt endpoint or don't\r
+ * have idle time between reports should set this data member to zero before \r
+ * calling the USBD_HID_API::Init().\r
+ * \n\r
+ * \r
+ * \param[in] hHid Handle to HID function driver. \r
+ * \param[in] pSetup Pointer to setup packet received from host.\r
+ * \param[in] idleTime Idle time to be set for the specified report.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*HID_SetIdle)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t idleTime); \r
+ \r
+ /** \r
+ * Optional callback function to handle HID_REQUEST_SET_PROTOCOL request.\r
+ *\r
+ * The application software could provide this callback to handle HID_REQUEST_SET_PROTOCOL\r
+ * requests sent by the host. This callback is provided to applications to adjust\r
+ * modes of their code between boot mode and report mode. \r
+ * \note Applications which don't support protocol modes should set this data member\r
+ * to zero before calling the USBD_HID_API::Init().\r
+ * \n\r
+ * \r
+ * \param[in] hHid Handle to HID function driver. \r
+ * \param[in] pSetup Pointer to setup packet received from host.\r
+ * \param[in] protocol Protocol mode. \r
+ * 0 = Boot Protocol\r
+ * 1 = Report Protocol\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*HID_SetProtocol)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t protocol); \r
+ \r
+ /** \r
+ * Optional Interrupt IN endpoint event handler.\r
+ *\r
+ * The application software could provide Interrupt IN endpoint event handler. \r
+ * Application which send reports to host on interrupt endpoint should provide\r
+ * an endpoint event handler through this data member. This data member is\r
+ * ignored if the interface descriptor \em intf_desc doesn't have any IN interrupt \r
+ * endpoint descriptor associated. \r
+ * \n\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Handle to HID function driver. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should return \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*HID_EpIn_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+ /** \r
+ * Optional Interrupt OUT endpoint event handler.\r
+ *\r
+ * The application software could provide Interrupt OUT endpoint event handler. \r
+ * Application which receives reports from host on interrupt endpoint should provide\r
+ * an endpoint event handler through this data member. This data member is\r
+ * ignored if the interface descriptor \em intf_desc doesn't have any OUT interrupt \r
+ * endpoint descriptor associated. \r
+ * \n\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Handle to HID function driver. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should return \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*HID_EpOut_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+ /* user override-able function */\r
+ /** \r
+ * Optional user override-able function to replace the default HID_GetReportDesc handler.\r
+ *\r
+ * The application software could override the default HID_GetReportDesc handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_HID_API::Init() and also provide report data array\r
+ * \em report_data field.\r
+ * \n\r
+ * \note \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*HID_GetReportDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);\r
+ /** \r
+ * Optional user override-able function to replace the default HID class handler.\r
+ *\r
+ * The application software could override the default EP0 class handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_HID_API::Init().\r
+ * \n\r
+ * \note \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*HID_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+} USBD_HID_INIT_PARAM_T;\r
+\r
+/** \brief HID class API functions structure.\r
+ * \ingroup USBD_HID\r
+ *\r
+ * This structure contains pointers to all the function exposed by HID function driver module.\r
+ *\r
+ */\r
+typedef struct USBD_HID_API \r
+{\r
+ /** \fn uint32_t GetMemSize(USBD_HID_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the HID function driver module.\r
+ * \r
+ * This function is called by application layer before calling pUsbApi->hid->Init(), to allocate memory used \r
+ * by HID function driver module. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller. \r
+ * \note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * \param[in] param Structure containing HID function driver module initialization parameters.\r
+ * \return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_HID_INIT_PARAM_T* param);\r
+\r
+ /** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param)\r
+ * Function to initialize HID function driver module.\r
+ * \r
+ * This function is called by application layer to initialize HID function driver \r
+ * module. On successful initialization the function returns a handle to HID \r
+ * function driver module in passed param structure. \r
+ *\r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in, out] param Structure containing HID function driver module \r
+ * initialization parameters.\r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success\r
+ * \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte \r
+ * aligned or smaller than required. \r
+ * \retval ERR_API_INVALID_PARAM2 Either HID_GetReport() or HID_SetReport()\r
+ * callback are not defined. \r
+ * \retval ERR_USBD_BAD_DESC HID_HID_DESCRIPTOR_TYPE is not defined \r
+ * immediately after interface descriptor. \r
+ * \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. \r
+ * \retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed. \r
+ */\r
+ ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param);\r
+\r
+} USBD_HID_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+/** @cond ADVANCED_API */\r
+\r
+typedef struct _HID_CTRL_T {\r
+ /* pointer to controller */\r
+ USB_CORE_CTRL_T* pUsbCtrl;\r
+ /* descriptor pointers */\r
+ uint8_t* hid_desc;\r
+ USB_HID_REPORT_T* report_data;\r
+\r
+ uint8_t protocol;\r
+ uint8_t if_num; /* interface number */\r
+ uint8_t epin_adr; /* IN interrupt endpoint */\r
+ uint8_t epout_adr; /* OUT interrupt endpoint */\r
+\r
+ /* user defined functions */\r
+ ErrorCode_t (*HID_GetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length); \r
+ ErrorCode_t (*HID_SetReport)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length);\r
+ ErrorCode_t (*HID_GetPhysDesc)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);\r
+ ErrorCode_t (*HID_SetIdle)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t idleTime); \r
+ ErrorCode_t (*HID_SetProtocol)( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t protocol); \r
+\r
+ /* virtual overridable functions */ \r
+ ErrorCode_t (*HID_GetReportDesc)(USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuf, uint16_t* length);\r
+\r
+}USB_HID_CTRL_T;\r
+\r
+/** @cond DIRECT_API */\r
+extern uint32_t mwHID_GetMemSize(USBD_HID_INIT_PARAM_T* param);\r
+extern ErrorCode_t mwHID_init(USBD_HANDLE_T hUsb, USBD_HID_INIT_PARAM_T* param);\r
+/** @endcond */\r
+\r
+/** @endcond */\r
+\r
+#endif /* __HIDUSER_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_hw.h 331 2012-08-09 18:54:34Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* USB Hardware Function prototypes.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+#ifndef __USBHW_H__\r
+#define __USBHW_H__\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "usbd_core.h"\r
+\r
+/** \file\r
+ * \brief USB Hardware Function prototypes.\r
+ *\r
+ * Definition of functions exported by ROM based Device Controller Driver (DCD).\r
+ *\r
+ */\r
+\r
+/** \ingroup Group_USBD\r
+ * @defgroup USBD_HW USB Device Controller Driver \r
+ * \section Sec_HWModDescription Module Description\r
+ * The Device Controller Driver Layer implements the routines to deal directly with the hardware. \r
+ */\r
+\r
+/** \ingroup USBD_HW\r
+* USB Endpoint/class handler Callback Events. \r
+* \r
+*/\r
+enum USBD_EVENT_T {\r
+ USB_EVT_SETUP =1, /**< 1 Setup Packet received */\r
+ USB_EVT_OUT, /**< 2 OUT Packet received */\r
+ USB_EVT_IN, /**< 3 IN Packet sent */\r
+ USB_EVT_OUT_NAK, /**< 4 OUT Packet - Not Acknowledged */\r
+ USB_EVT_IN_NAK, /**< 5 IN Packet - Not Acknowledged */\r
+ USB_EVT_OUT_STALL, /**< 6 OUT Packet - Stalled */\r
+ USB_EVT_IN_STALL, /**< 7 IN Packet - Stalled */\r
+ USB_EVT_OUT_DMA_EOT, /**< 8 DMA OUT EP - End of Transfer */\r
+ USB_EVT_IN_DMA_EOT, /**< 9 DMA IN EP - End of Transfer */\r
+ USB_EVT_OUT_DMA_NDR, /**< 10 DMA OUT EP - New Descriptor Request */\r
+ USB_EVT_IN_DMA_NDR, /**< 11 DMA IN EP - New Descriptor Request */\r
+ USB_EVT_OUT_DMA_ERR, /**< 12 DMA OUT EP - Error */\r
+ USB_EVT_IN_DMA_ERR, /**< 13 DMA IN EP - Error */\r
+ USB_EVT_RESET, /**< 14 Reset event recieved */\r
+ USB_EVT_SOF, /**< 15 Start of Frame event */\r
+ USB_EVT_DEV_STATE, /**< 16 Device status events */\r
+ USB_EVT_DEV_ERROR /**< 17 Device error events */\r
+};\r
+\r
+/** \r
+ * \brief Hardware API functions structure.\r
+ * \ingroup USBD_HW\r
+ *\r
+ * This module exposes functions which interact directly with USB device controller hardware.\r
+ *\r
+ */\r
+typedef struct USBD_HW_API\r
+{\r
+ /** \fn uint32_t GetMemSize(USBD_API_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the USB device stack's DCD and core layers.\r
+ * \r
+ * This function is called by application layer before calling pUsbApi->hw->Init(), to allocate memory used\r
+ * by DCD and core layers. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller. \r
+ * \note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * \param[in] param Structure containing USB device stack initialization parameters.\r
+ * \return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_API_INIT_PARAM_T* param);\r
+ \r
+ /** \fn ErrorCode_t Init(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param)\r
+ * Function to initialize USB device stack's DCD and core layers.\r
+ * \r
+ * This function is called by application layer to initialize USB hardware and core layers. \r
+ * On successful initialization the function returns a handle to USB device stack which should\r
+ * be passed to the rest of the functions. \r
+ *\r
+ * \param[in,out] phUsb Pointer to the USB device stack handle of type USBD_HANDLE_T. \r
+ * \param[in] pDesc Structure containing pointers to various descriptor arrays needed by the stack.\r
+ * These descriptors are reported to USB host as part of enumerations process.\r
+ * \param[in] param Structure containing USB device stack initialization parameters.\r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK(0) On success\r
+ * \retval ERR_USBD_BAD_MEM_BUF(0x0004000b) When insufficient memory buffer is passed or memory\r
+ * is not aligned on 2048 boundary.\r
+ */\r
+ ErrorCode_t (*Init)(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param);\r
+ \r
+ /** \fn void Connect(USBD_HANDLE_T hUsb, uint32_t con)\r
+ * Function to make USB device visible/invisible on the USB bus.\r
+ *\r
+ * This function is called after the USB initialization. This function uses the soft connect\r
+ * feature to make the device visible on the USB bus. This function is called only after the\r
+ * application is ready to handle the USB data. The enumeration process is started by the\r
+ * host after the device detection. The driver handles the enumeration process according to\r
+ * the USB descriptors passed in the USB initialization function.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] con States whether to connect (1) or to disconnect (0).\r
+ * \return Nothing.\r
+ */\r
+ void (*Connect)(USBD_HANDLE_T hUsb, uint32_t con);\r
+ \r
+ /** \fn void ISR(USBD_HANDLE_T hUsb)\r
+ * Function to USB device controller interrupt events.\r
+ * \r
+ * When the user application is active the interrupt handlers are mapped in the user flash\r
+ * space. The user application must provide an interrupt handler for the USB interrupt and\r
+ * call this function in the interrupt handler routine. The driver interrupt handler takes\r
+ * appropriate action according to the data received on the USB bus. \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return Nothing.\r
+ */\r
+ void (*ISR)(USBD_HANDLE_T hUsb);\r
+\r
+ /** \fn void Reset(USBD_HANDLE_T hUsb)\r
+ * Function to Reset USB device stack and hardware controller.\r
+ * \r
+ * Reset USB device stack and hardware controller. Disables all endpoints except EP0.\r
+ * Clears all pending interrupts and resets endpoint transfer queues.\r
+ * This function is called internally by pUsbApi->hw->init() and from reset event.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return Nothing.\r
+ */\r
+ void (*Reset)(USBD_HANDLE_T hUsb);\r
+ \r
+ /** \fn void ForceFullSpeed(USBD_HANDLE_T hUsb, uint32_t cfg)\r
+ * Function to force high speed USB device to operate in full speed mode.\r
+ *\r
+ * This function is useful for testing the behavior of current device when connected\r
+ * to a full speed only hosts.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] cfg When 1 - set force full-speed or \r
+ * 0 - clear force full-speed.\r
+ * \return Nothing.\r
+ */\r
+ void (*ForceFullSpeed )(USBD_HANDLE_T hUsb, uint32_t cfg);\r
+ \r
+ /** \fn void WakeUpCfg(USBD_HANDLE_T hUsb, uint32_t cfg)\r
+ * Function to configure USB device controller to wake-up host on remote events.\r
+ *\r
+ * This function is called by application layer to configure the USB device controller \r
+ * to wakeup on remote events. It is recommended to call this function from users's \r
+ * USB_WakeUpCfg() callback routine registered with stack. \r
+ * \note User's USB_WakeUpCfg() is registered with stack by setting the USB_WakeUpCfg member \r
+ * of USBD_API_INIT_PARAM_T structure before calling pUsbApi->hw->Init() routine.\r
+ * Certain USB device controllers needed to keep some clocks always on to generate \r
+ * resume signaling through pUsbApi->hw->WakeUp(). This hook is provided to support \r
+ * such controllers. In most controllers cases this is an empty routine.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] cfg When 1 - Configure controller to wake on remote events or \r
+ * 0 - Configure controller not to wake on remote events.\r
+ * \return Nothing.\r
+ */\r
+ void (*WakeUpCfg)(USBD_HANDLE_T hUsb, uint32_t cfg);\r
+ \r
+ /** \fn void SetAddress(USBD_HANDLE_T hUsb, uint32_t adr)\r
+ * Function to set USB address assigned by host in device controller hardware.\r
+ *\r
+ * This function is called automatically when USB_REQUEST_SET_ADDRESS request is received \r
+ * by the stack from USB host.\r
+ * This interface is provided to users to invoke this function in other scenarios which are not \r
+ * handle by current stack. In most user applications this function is not called directly.\r
+ * Also this function can be used by users who are selectively modifying the USB device stack's \r
+ * standard handlers through callback interface exposed by the stack. \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] adr USB bus Address to which the device controller should respond. Usually \r
+ * assigned by the USB host.\r
+ * \return Nothing.\r
+ */\r
+ void (*SetAddress)(USBD_HANDLE_T hUsb, uint32_t adr);\r
+\r
+ /** \fn void Configure(USBD_HANDLE_T hUsb, uint32_t cfg)\r
+ * Function to configure device controller hardware with selected configuration.\r
+ *\r
+ * This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received \r
+ * by the stack from USB host.\r
+ * This interface is provided to users to invoke this function in other scenarios which are not \r
+ * handle by current stack. In most user applications this function is not called directly.\r
+ * Also this function can be used by users who are selectively modifying the USB device stack's \r
+ * standard handlers through callback interface exposed by the stack. \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] cfg Configuration index. \r
+ * \return Nothing.\r
+ */\r
+ void (*Configure)(USBD_HANDLE_T hUsb, uint32_t cfg);\r
+\r
+ /** \fn void ConfigEP(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD)\r
+ * Function to configure USB Endpoint according to descriptor.\r
+ *\r
+ * This function is called automatically when USB_REQUEST_SET_CONFIGURATION request is received \r
+ * by the stack from USB host. All the endpoints associated with the selected configuration\r
+ * are configured.\r
+ * This interface is provided to users to invoke this function in other scenarios which are not \r
+ * handle by current stack. In most user applications this function is not called directly.\r
+ * Also this function can be used by users who are selectively modifying the USB device stack's \r
+ * standard handlers through callback interface exposed by the stack. \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] pEPD Endpoint descriptor structure defined in USB 2.0 specification.\r
+ * \return Nothing.\r
+ */\r
+ void (*ConfigEP)(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD);\r
+\r
+ /** \fn void DirCtrlEP(USBD_HANDLE_T hUsb, uint32_t dir)\r
+ * Function to set direction for USB control endpoint EP0.\r
+ *\r
+ * This function is called automatically by the stack on need basis.\r
+ * This interface is provided to users to invoke this function in other scenarios which are not \r
+ * handle by current stack. In most user applications this function is not called directly.\r
+ * Also this function can be used by users who are selectively modifying the USB device stack's \r
+ * standard handlers through callback interface exposed by the stack. \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] cfg When 1 - Set EP0 in IN transfer mode \r
+ * 0 - Set EP0 in OUT transfer mode\r
+ * \return Nothing.\r
+ */\r
+ void (*DirCtrlEP)(USBD_HANDLE_T hUsb, uint32_t dir);\r
+\r
+ /** \fn void EnableEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to enable selected USB endpoint.\r
+ *\r
+ * This function enables interrupts on selected endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number as per USB specification. \r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \return Nothing.\r
+ */\r
+ void (*EnableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** \fn void DisableEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to disable selected USB endpoint.\r
+ *\r
+ * This function disables interrupts on selected endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number as per USB specification. \r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \return Nothing.\r
+ */\r
+ void (*DisableEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** \fn void ResetEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to reset selected USB endpoint.\r
+ *\r
+ * This function flushes the endpoint buffers and resets data toggle logic.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number as per USB specification. \r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \return Nothing.\r
+ */\r
+ void (*ResetEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** \fn void SetStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to STALL selected USB endpoint.\r
+ *\r
+ * Generates STALL signaling for requested endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number as per USB specification. \r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \return Nothing.\r
+ */\r
+ void (*SetStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** \fn void ClrStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum)\r
+ * Function to clear STALL state for the requested endpoint.\r
+ *\r
+ * This function clears STALL state for the requested endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number as per USB specification. \r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \return Nothing.\r
+ */\r
+ void (*ClrStallEP)(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+\r
+ /** \fn ErrorCode_t SetTestMode(USBD_HANDLE_T hUsb, uint8_t mode)\r
+ * Function to set high speed USB device controller in requested test mode.\r
+ *\r
+ * USB-IF requires the high speed device to be put in various test modes\r
+ * for electrical testing. This USB device stack calls this function whenever\r
+ * it receives USB_REQUEST_CLEAR_FEATURE request for USB_FEATURE_TEST_MODE. \r
+ * Users can put the device in test mode by directly calling this function.\r
+ * Returns ERR_USBD_INVALID_REQ when device controller is full-speed only.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] mode Test mode defined in USB 2.0 electrical testing specification.\r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK(0) - On success\r
+ * \retval ERR_USBD_INVALID_REQ(0x00040001) - Invalid test mode or \r
+ * Device controller is full-speed only.\r
+ */\r
+ ErrorCode_t (*SetTestMode)(USBD_HANDLE_T hUsb, uint8_t mode); \r
+\r
+ /** \fn uint32_t ReadEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData)\r
+ * Function to read data received on the requested endpoint.\r
+ *\r
+ * This function is called by USB stack and the application layer to read the data\r
+ * received on the requested endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number as per USB specification. \r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \param[in,out] pData Pointer to the data buffer where data is to be copied. \r
+ * \return Returns the number of bytes copied to the buffer.\r
+ */\r
+ uint32_t (*ReadEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData);\r
+\r
+ /** \fn uint32_t ReadReqEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len)\r
+ * Function to queue read request on the specified endpoint.\r
+ *\r
+ * This function is called by USB stack and the application layer to queue a read request\r
+ * on the specified endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number as per USB specification. \r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \param[in,out] pData Pointer to the data buffer where data is to be copied. This buffer\r
+ * address should be accessible by USB DMA master.\r
+ * \param[in] len Length of the buffer passed. \r
+ * \return Returns the length of the requested buffer.\r
+ */\r
+ uint32_t (*ReadReqEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len);\r
+\r
+ /** \fn uint32_t ReadSetupPkt(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t *pData)\r
+ * Function to read setup packet data received on the requested endpoint.\r
+ *\r
+ * This function is called by USB stack and the application layer to read setup packet data\r
+ * received on the requested endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number as per USB specification. \r
+ * ie. An EP0_IN is represented by 0x80 number.\r
+ * \param[in,out] pData Pointer to the data buffer where data is to be copied. \r
+ * \return Returns the number of bytes copied to the buffer.\r
+ */\r
+ uint32_t (*ReadSetupPkt)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t *pData);\r
+\r
+ /** \fn uint32_t WriteEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt)\r
+ * Function to write data to be sent on the requested endpoint.\r
+ *\r
+ * This function is called by USB stack and the application layer to send data\r
+ * on the requested endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number as per USB specification. \r
+ * ie. An EP1_IN is represented by 0x81 number.\r
+ * \param[in] pData Pointer to the data buffer from where data is to be copied. \r
+ * \param[in] cnt Number of bytes to write. \r
+ * \return Returns the number of bytes written.\r
+ */\r
+ uint32_t (*WriteEP)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt);\r
+\r
+ /** \fn void WakeUp(USBD_HANDLE_T hUsb)\r
+ * Function to generate resume signaling on bus for remote host wakeup.\r
+ *\r
+ * This function is called by application layer to remotely wakeup host controller \r
+ * when system is in suspend state. Application should indicate this remote wakeup\r
+ * capability by setting USB_CONFIG_REMOTE_WAKEUP in bmAttributes of Configuration \r
+ * Descriptor. Also this routine will generate resume signalling only if host\r
+ * enables USB_FEATURE_REMOTE_WAKEUP by sending SET_FEATURE request before suspending\r
+ * the bus.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \return Nothing.\r
+ */\r
+ void (*WakeUp)(USBD_HANDLE_T hUsb);\r
+\r
+ /** \fn void EnableEvent(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable)\r
+ * Function to enable/disable selected USB event.\r
+ *\r
+ * This function enables interrupts on selected endpoint.\r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] EPNum Endpoint number corresponding to the event.\r
+ * ie. An EP1_IN is represented by 0x81 number. For device events \r
+ * set this param to 0x0. \r
+ * \param[in] event_type Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \param[in] enable 1 - enable event, 0 - disable event.\r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK(0) - On success\r
+ * \retval ERR_USBD_INVALID_REQ(0x00040001) - Invalid event type.\r
+ */\r
+ ErrorCode_t (*EnableEvent)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable);\r
+\r
+} USBD_HW_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes used by stack internally\r
+ *-----------------------------------------------------------------------------*/\r
+/** @cond DIRECT_API */\r
+\r
+/* Driver functions */\r
+uint32_t hwUSB_GetMemSize(USBD_API_INIT_PARAM_T* param);\r
+ErrorCode_t hwUSB_Init(USBD_HANDLE_T* phUsb, USB_CORE_DESCS_T* pDesc, USBD_API_INIT_PARAM_T* param);\r
+void hwUSB_Connect(USBD_HANDLE_T hUsb, uint32_t con);\r
+void hwUSB_ISR(USBD_HANDLE_T hUsb);\r
+\r
+/* USB Hardware Functions */\r
+extern void hwUSB_Reset(USBD_HANDLE_T hUsb);\r
+extern void hwUSB_ForceFullSpeed (USBD_HANDLE_T hUsb, uint32_t con);\r
+extern void hwUSB_WakeUpCfg(USBD_HANDLE_T hUsb, uint32_t cfg);\r
+extern void hwUSB_SetAddress(USBD_HANDLE_T hUsb, uint32_t adr);\r
+extern void hwUSB_Configure(USBD_HANDLE_T hUsb, uint32_t cfg);\r
+extern void hwUSB_ConfigEP(USBD_HANDLE_T hUsb, USB_ENDPOINT_DESCRIPTOR *pEPD);\r
+extern void hwUSB_DirCtrlEP(USBD_HANDLE_T hUsb, uint32_t dir);\r
+extern void hwUSB_EnableEP(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+extern void hwUSB_DisableEP(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+extern void hwUSB_ResetEP(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+extern void hwUSB_SetStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+extern void hwUSB_ClrStallEP(USBD_HANDLE_T hUsb, uint32_t EPNum);\r
+extern ErrorCode_t hwUSB_SetTestMode(USBD_HANDLE_T hUsb, uint8_t mode); /* for FS only devices return ERR_USBD_INVALID_REQ */\r
+extern uint32_t hwUSB_ReadEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData);\r
+extern uint32_t hwUSB_ReadReqEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t len);\r
+extern uint32_t hwUSB_ReadSetupPkt(USBD_HANDLE_T hUsb, uint32_t, uint32_t *);\r
+extern uint32_t hwUSB_WriteEP(USBD_HANDLE_T hUsb, uint32_t EPNum, uint8_t *pData, uint32_t cnt);\r
+\r
+/* generate resume signaling on the bus */\r
+extern void hwUSB_WakeUp(USBD_HANDLE_T hUsb);\r
+extern ErrorCode_t hwUSB_EnableEvent(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable);\r
+/* TODO implement following routines\r
+- function to program TD and queue them to ep Qh\r
+*/\r
+\r
+/** @endcond */\r
+\r
+\r
+#endif /* __USBHW_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_msc.h 331 2012-08-09 18:54:34Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* Mass Storage Class definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+\r
+#ifndef __MSC_H__\r
+#define __MSC_H__\r
+\r
+#include "usbd.h"\r
+\r
+/** \file\r
+ * \brief Mass Storage class (MSC) descriptors.\r
+ *\r
+ * Definition of MSC class descriptors and their bit defines.\r
+ *\r
+ */\r
+\r
+/* MSC Subclass Codes */\r
+#define MSC_SUBCLASS_RBC 0x01\r
+#define MSC_SUBCLASS_SFF8020I_MMC2 0x02\r
+#define MSC_SUBCLASS_QIC157 0x03\r
+#define MSC_SUBCLASS_UFI 0x04\r
+#define MSC_SUBCLASS_SFF8070I 0x05\r
+#define MSC_SUBCLASS_SCSI 0x06\r
+\r
+/* MSC Protocol Codes */\r
+#define MSC_PROTOCOL_CBI_INT 0x00\r
+#define MSC_PROTOCOL_CBI_NOINT 0x01\r
+#define MSC_PROTOCOL_BULK_ONLY 0x50\r
+\r
+\r
+/* MSC Request Codes */\r
+#define MSC_REQUEST_RESET 0xFF\r
+#define MSC_REQUEST_GET_MAX_LUN 0xFE\r
+\r
+\r
+/* MSC Bulk-only Stage */\r
+#define MSC_BS_CBW 0 /* Command Block Wrapper */\r
+#define MSC_BS_DATA_OUT 1 /* Data Out Phase */\r
+#define MSC_BS_DATA_IN 2 /* Data In Phase */\r
+#define MSC_BS_DATA_IN_LAST 3 /* Data In Last Phase */\r
+#define MSC_BS_DATA_IN_LAST_STALL 4 /* Data In Last Phase with Stall */\r
+#define MSC_BS_CSW 5 /* Command Status Wrapper */\r
+#define MSC_BS_ERROR 6 /* Error */\r
+\r
+\r
+/* Bulk-only Command Block Wrapper */\r
+PRE_PACK struct POST_PACK _MSC_CBW\r
+{\r
+ uint32_t dSignature;\r
+ uint32_t dTag;\r
+ uint32_t dDataLength;\r
+ uint8_t bmFlags;\r
+ uint8_t bLUN;\r
+ uint8_t bCBLength;\r
+ uint8_t CB[16];\r
+} ;\r
+typedef struct _MSC_CBW MSC_CBW;\r
+\r
+/* Bulk-only Command Status Wrapper */\r
+PRE_PACK struct POST_PACK _MSC_CSW\r
+{\r
+ uint32_t dSignature;\r
+ uint32_t dTag;\r
+ uint32_t dDataResidue;\r
+ uint8_t bStatus;\r
+} ;\r
+typedef struct _MSC_CSW MSC_CSW;\r
+\r
+#define MSC_CBW_Signature 0x43425355\r
+#define MSC_CSW_Signature 0x53425355\r
+\r
+\r
+/* CSW Status Definitions */\r
+#define CSW_CMD_PASSED 0x00\r
+#define CSW_CMD_FAILED 0x01\r
+#define CSW_PHASE_ERROR 0x02\r
+\r
+\r
+/* SCSI Commands */\r
+#define SCSI_TEST_UNIT_READY 0x00\r
+#define SCSI_REQUEST_SENSE 0x03\r
+#define SCSI_FORMAT_UNIT 0x04\r
+#define SCSI_INQUIRY 0x12\r
+#define SCSI_MODE_SELECT6 0x15\r
+#define SCSI_MODE_SENSE6 0x1A\r
+#define SCSI_START_STOP_UNIT 0x1B\r
+#define SCSI_MEDIA_REMOVAL 0x1E\r
+#define SCSI_READ_FORMAT_CAPACITIES 0x23\r
+#define SCSI_READ_CAPACITY 0x25\r
+#define SCSI_READ10 0x28\r
+#define SCSI_WRITE10 0x2A\r
+#define SCSI_VERIFY10 0x2F\r
+#define SCSI_READ12 0xA8\r
+#define SCSI_WRITE12 0xAA\r
+#define SCSI_MODE_SELECT10 0x55\r
+#define SCSI_MODE_SENSE10 0x5A\r
+\r
+\r
+#endif /* __MSC_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_mscuser.h 577 2012-11-20 01:42:04Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* Mass Storage Class Custom User Module definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+#ifndef __MSCUSER_H__\r
+#define __MSCUSER_H__\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "usbd_msc.h"\r
+#include "usbd_core.h"\r
+#include "app_usbd_cfg.h"\r
+\r
+/** \file\r
+ * \brief Mass Storage Class (MSC) API structures and function prototypes.\r
+ *\r
+ * Definition of functions exported by ROM based MSC function driver.\r
+ *\r
+ */\r
+\r
+/** \ingroup Group_USBD\r
+ * @defgroup USBD_MSC Mass Storage Class (MSC) Function Driver\r
+ * \section Sec_MSCModDescription Module Description\r
+ * MSC Class Function Driver module. This module contains an internal implementation of the USB MSC Class.\r
+ * User applications can use this class driver instead of implementing the MSC class manually\r
+ * via the low-level USBD_HW and USBD_Core APIs.\r
+ *\r
+ * This module is designed to simplify the user code by exposing only the required interface needed to interface with\r
+ * Devices using the USB MSC Class.\r
+ */\r
+\r
+/** \brief Mass Storage class function driver initialization parameter data structure.\r
+ * \ingroup USBD_MSC\r
+ *\r
+ * \details This data structure is used to pass initialization parameters to the \r
+ * Mass Storage class function driver's init function.\r
+ *\r
+ */\r
+typedef struct USBD_MSC_INIT_PARAM\r
+{\r
+ /* memory allocation params */\r
+ uint32_t mem_base; /**< Base memory location from where the stack can allocate\r
+ data and buffers. \note The memory address set in this field\r
+ should be accessible by USB DMA controller. Also this value\r
+ should be aligned on 4 byte boundary.\r
+ */\r
+ uint32_t mem_size; /**< The size of memory buffer which stack can use. \r
+ \note The \em mem_size should be greater than the size \r
+ returned by USBD_MSC_API::GetMemSize() routine.*/\r
+ /* mass storage params */\r
+ uint8_t* InquiryStr; /**< Pointer to the 28 character string. This string is \r
+ sent in response to the SCSI Inquiry command. \note The data \r
+ pointed by the pointer should be of global scope. \r
+ */\r
+ uint32_t BlockCount; /**< Number of blocks present in the mass storage device */\r
+ uint32_t BlockSize; /**< Block size in number of bytes */\r
+ uint32_t MemorySize; /**< Memory size in number of bytes */\r
+ /** Pointer to the interface descriptor within the descriptor\r
+ * array (\em high_speed_desc) passed to Init() through \ref USB_CORE_DESCS_T \r
+ * structure. The stack assumes both HS and FS use same BULK endpoints. \r
+ */\r
+\r
+ uint8_t* intf_desc;\r
+ /* user defined functions */\r
+\r
+ /** \r
+ * MSC Write callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends a write command.\r
+ * \r
+ * \param[in] offset Destination start address. \r
+ * \param[in, out] src Pointer to a pointer to the source of data. Pointer-to-pointer\r
+ * is used to implement zero-copy buffers. See \ref USBD_ZeroCopy\r
+ * for more details on zero-copy concept.\r
+ * \param[in] length Number of bytes to be written.\r
+ * \return Nothing. \r
+ * \r
+ */\r
+ void (*MSC_Write)( uint32_t offset, uint8_t** src, uint32_t length, uint32_t high_offset); \r
+ /** \r
+ * MSC Read callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends a read command.\r
+ * \r
+ * \param[in] offset Source start address. \r
+ * \param[in, out] dst Pointer to a pointer to the source of data. The MSC function drivers \r
+ * implemented in stack are written with zero-copy model. Meaning the stack doesn't make an \r
+ * extra copy of buffer before writing/reading data from USB hardware FIFO. Hence the \r
+ * parameter is pointer to a pointer containing address buffer (<em>uint8_t** dst</em>). \r
+ * So that the user application can update the buffer pointer instead of copying data to \r
+ * address pointed by the parameter. /note The updated buffer address should be accessible\r
+ * by USB DMA master. If user doesn't want to use zero-copy model, then the user should copy\r
+ * data to the address pointed by the passed buffer pointer parameter and shouldn't change \r
+ * the address value. See \ref USBD_ZeroCopy for more details on zero-copy concept.\r
+ * \param[in] length Number of bytes to be read.\r
+ * \return Nothing. \r
+ * \r
+ */\r
+ void (*MSC_Read)( uint32_t offset, uint8_t** dst, uint32_t length, uint32_t high_offset);\r
+ /** \r
+ * MSC Verify callback function.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends a verify command. The callback function should compare the buffer\r
+ * with the destination memory at the requested offset and \r
+ * \r
+ * \param[in] offset Destination start address. \r
+ * \param[in] buf Buffer containing the data sent by the host.\r
+ * \param[in] length Number of bytes to verify.\r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK If data in the buffer matches the data at destination\r
+ * \retval ERR_FAILED At least one byte is different.\r
+ * \r
+ */\r
+ ErrorCode_t (*MSC_Verify)( uint32_t offset, uint8_t buf[], uint32_t length, uint32_t high_offset);\r
+ /** \r
+ * Optional callback function to optimize MSC_Write buffer transfer.\r
+ *\r
+ * This function is provided by the application software. This function gets called \r
+ * when host sends SCSI_WRITE10/SCSI_WRITE12 command. The callback function should \r
+ * update the \em buff_adr pointer so that the stack transfers the data directly\r
+ * to the target buffer. /note The updated buffer address should be accessible\r
+ * by USB DMA master. If user doesn't want to use zero-copy model, then the user \r
+ * should not update the buffer pointer. See \ref USBD_ZeroCopy for more details\r
+ * on zero-copy concept.\r
+ * \r
+ * \param[in] offset Destination start address. \r
+ * \param[in,out] buf Buffer containing the data sent by the host.\r
+ * \param[in] length Number of bytes to write.\r
+ * \return Nothing. \r
+ * \r
+ */\r
+ void (*MSC_GetWriteBuf)( uint32_t offset, uint8_t** buff_adr, uint32_t length, uint32_t high_offset); \r
+\r
+ /** \r
+ * Optional user override-able function to replace the default MSC class handler.\r
+ *\r
+ * The application software could override the default EP0 class handler with their\r
+ * own by providing the handler function address as this data member of the parameter\r
+ * structure. Application which like the default handler should set this data member\r
+ * to zero before calling the USBD_MSC_API::Init().\r
+ * \n\r
+ * \note \r
+ * \r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in] data Pointer to the data which will be passed when callback function is called by the stack. \r
+ * \param[in] event Type of endpoint event. See \ref USBD_EVENT_T for more details.\r
+ * \return The call back should returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success.\r
+ * \retval ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line. \r
+ * \retval ERR_USBD_xxx For other error conditions. \r
+ * \r
+ */\r
+ ErrorCode_t (*MSC_Ep0_Hdlr) (USBD_HANDLE_T hUsb, void* data, uint32_t event);\r
+\r
+ uint64_t MemorySize64;\r
+ \r
+} USBD_MSC_INIT_PARAM_T;\r
+\r
+/** \brief MSC class API functions structure.\r
+ * \ingroup USBD_MSC\r
+ *\r
+ * This module exposes functions which interact directly with USB device controller hardware.\r
+ *\r
+ */\r
+typedef struct USBD_MSC_API\r
+{\r
+ /** \fn uint32_t GetMemSize(USBD_MSC_INIT_PARAM_T* param)\r
+ * Function to determine the memory required by the MSC function driver module.\r
+ * \r
+ * This function is called by application layer before calling pUsbApi->msc->Init(), to allocate memory used \r
+ * by MSC function driver module. The application should allocate the memory which is accessible by USB\r
+ * controller/DMA controller. \r
+ * \note Some memory areas are not accessible by all bus masters.\r
+ *\r
+ * \param[in] param Structure containing MSC function driver module initialization parameters.\r
+ * \return Returns the required memory size in bytes.\r
+ */\r
+ uint32_t (*GetMemSize)(USBD_MSC_INIT_PARAM_T* param);\r
+ \r
+ /** \fn ErrorCode_t init(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param)\r
+ * Function to initialize MSC function driver module.\r
+ * \r
+ * This function is called by application layer to initialize MSC function driver module.\r
+ *\r
+ * \param[in] hUsb Handle to the USB device stack. \r
+ * \param[in, out] param Structure containing MSC function driver module initialization parameters.\r
+ * \return Returns \ref ErrorCode_t type to indicate success or error condition.\r
+ * \retval LPC_OK On success\r
+ * \retval ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4-byte \r
+ * aligned or smaller than required. \r
+ * \retval ERR_API_INVALID_PARAM2 Either MSC_Write() or MSC_Read() or\r
+ * MSC_Verify() callbacks are not defined. \r
+ * \retval ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed. \r
+ * \retval ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed. \r
+ */\r
+ ErrorCode_t (*init)(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param);\r
+\r
+} USBD_MSC_API_T;\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Private functions & structures prototypes\r
+ *-----------------------------------------------------------------------------*/\r
+/** @cond ADVANCED_API */\r
+\r
+typedef struct _MSC_CTRL_T\r
+{\r
+ /* If it's a USB HS, the max packet is 512, if it's USB FS,\r
+ the max packet is 64. Use 512 for both HS and FS. */\r
+ /*ALIGNED(4)*/ uint8_t BulkBuf[USB_HS_MAX_BULK_PACKET]; /* Bulk In/Out Buffer */\r
+ /*ALIGNED(4)*/MSC_CBW CBW; /* Command Block Wrapper */\r
+ /*ALIGNED(4)*/MSC_CSW CSW; /* Command Status Wrapper */\r
+\r
+ USB_CORE_CTRL_T* pUsbCtrl;\r
+ \r
+ uint64_t Offset; /* R/W Offset */\r
+ uint32_t Length; /* R/W Length */\r
+ uint32_t BulkLen; /* Bulk In/Out Length */\r
+ uint8_t* rx_buf;\r
+ \r
+ uint8_t BulkStage; /* Bulk Stage */\r
+ uint8_t if_num; /* interface number */\r
+ uint8_t epin_num; /* BULK IN endpoint number */\r
+ uint8_t epout_num; /* BULK OUT endpoint number */\r
+ uint32_t MemOK; /* Memory OK */\r
+\r
+ uint8_t* InquiryStr;\r
+ uint32_t BlockCount;\r
+ uint32_t BlockSize;\r
+ uint64_t MemorySize;\r
+ /* user defined functions */\r
+ void (*MSC_Write)( uint32_t offset, uint8_t** src, uint32_t length, uint32_t high_offset); \r
+ void (*MSC_Read)( uint32_t offset, uint8_t** dst, uint32_t length, uint32_t high_offset);\r
+ ErrorCode_t (*MSC_Verify)( uint32_t offset, uint8_t src[], uint32_t length, uint32_t high_offset);\r
+ /* optional call back for MSC_Write optimization */\r
+ void (*MSC_GetWriteBuf)( uint32_t offset, uint8_t** buff_adr, uint32_t length, uint32_t high_offset); \r
+\r
+\r
+}USB_MSC_CTRL_T;\r
+\r
+/** @cond DIRECT_API */\r
+extern uint32_t mwMSC_GetMemSize(USBD_MSC_INIT_PARAM_T* param);\r
+extern ErrorCode_t mwMSC_init(USBD_HANDLE_T hUsb, USBD_MSC_INIT_PARAM_T* param);\r
+/** @endcond */\r
+\r
+/** @endcond */\r
+\r
+\r
+#endif /* __MSCUSER_H__ */\r
--- /dev/null
+/***********************************************************************\r
+* $Id:: mw_usbd_rom_api.h 331 2012-08-09 18:54:34Z usb10131 $\r
+*\r
+* Project: USB device ROM Stack\r
+*\r
+* Description:\r
+* ROM API Module definitions.\r
+*\r
+***********************************************************************\r
+* Copyright(C) 2011, NXP Semiconductor\r
+* All rights reserved.\r
+*\r
+* Software that is described herein is for illustrative purposes only\r
+* which provides customers with programming information regarding the\r
+* products. This software is supplied "AS IS" without any warranties.\r
+* NXP Semiconductors assumes no responsibility or liability for the\r
+* use of the software, conveys no license or title under any patent,\r
+* copyright, or mask work right to the product. NXP Semiconductors\r
+* reserves the right to make changes in the software without\r
+* notification. NXP Semiconductors also make no representation or\r
+* warranty that such application will be suitable for the specified\r
+* use without further testing or modification.\r
+**********************************************************************/\r
+#ifndef __MW_USBD_ROM_API_H\r
+#define __MW_USBD_ROM_API_H\r
+/** \file\r
+ * \brief ROM API for USB device stack.\r
+ *\r
+ * Definition of functions exported by ROM based USB device stack.\r
+ *\r
+ */\r
+\r
+#include "error.h"\r
+#include "usbd.h"\r
+#include "usbd_hw.h"\r
+#include "usbd_core.h"\r
+#include "usbd_mscuser.h"\r
+#include "usbd_dfuuser.h"\r
+#include "usbd_hiduser.h"\r
+#include "usbd_cdcuser.h"\r
+\r
+/** \brief Main USBD API functions structure.\r
+ * \ingroup Group_USBD\r
+ *\r
+ * This structure contains pointer to various USB Device stack's sub-module \r
+ * function tables. This structure is used as main entry point to access\r
+ * various methods (grouped in sub-modules) exposed by ROM based USB device \r
+ * stack.\r
+ *\r
+ */\r
+typedef struct USBD_API \r
+{\r
+ const USBD_HW_API_T* hw; /**< Pointer to function table which exposes functions \r
+ which interact directly with USB device stack's core \r
+ layer.*/\r
+ const USBD_CORE_API_T* core; /**< Pointer to function table which exposes functions \r
+ which interact directly with USB device controller \r
+ hardware.*/\r
+ const USBD_MSC_API_T* msc; /**< Pointer to function table which exposes functions \r
+ provided by MSC function driver module.\r
+ */\r
+ const USBD_DFU_API_T* dfu; /**< Pointer to function table which exposes functions \r
+ provided by DFU function driver module.\r
+ */\r
+ const USBD_HID_API_T* hid; /**< Pointer to function table which exposes functions \r
+ provided by HID function driver module.\r
+ */\r
+ const USBD_CDC_API_T* cdc; /**< Pointer to function table which exposes functions \r
+ provided by CDC-ACM function driver module.\r
+ */\r
+ const uint32_t* reserved6; /**< Reserved for future function driver module.\r
+ */\r
+ const uint32_t version; /**< Version identifier of USB ROM stack. The version is\r
+ defined as 0x0CHDMhCC where each nibble represents version\r
+ number of the corresponding component.\r
+ CC - 7:0 - 8bit core version number\r
+ h - 11:8 - 4bit hardware interface version number\r
+ M - 15:12 - 4bit MSC class module version number\r
+ D - 19:16 - 4bit DFU class module version number\r
+ H - 23:20 - 4bit HID class module version number\r
+ C - 27:24 - 4bit CDC class module version number\r
+ H - 31:28 - 4bit reserved \r
+ */\r
+\r
+} USBD_API_T;\r
+\r
+/* Applications using USBD ROM API should define this instance. The pointer should be assigned a value computed based on chip definitions. */ \r
+extern const USBD_API_T* g_pUsbApi;\r
+#define USBD_API g_pUsbApi\r
+\r
+#endif /*__MW_USBD_ROM_API_H*/\r
+\r
--- /dev/null
+interface cmsis-dap
+source [find target/lpc11xx.cfg]
+adapter_khz 1000
+reset_config srst_only
+$_TARGETNAME configure -event gdb-attach {
+ echo "Halting target"
+ halt
+}
--- /dev/null
+/******************************************************************************\r
+ * @file DAP.c\r
+ * @brief CMSIS-DAP Commands\r
+ * @version V1.00\r
+ * @date 31. May 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <string.h>\r
+#include "DAP_config.h"\r
+#include "DAP.h"\r
+\r
+\r
+#define DAP_FW_VER "1.0" // Firmware Version\r
+\r
+\r
+#if (DAP_PACKET_SIZE < 64)\r
+#error "Minimum Packet Size is 64"\r
+#endif\r
+#if (DAP_PACKET_SIZE > 32768)\r
+#error "Maximum Packet Size is 32768"\r
+#endif\r
+#if (DAP_PACKET_COUNT < 1)\r
+#error "Minimum Packet Count is 1"\r
+#endif\r
+#if (DAP_PACKET_COUNT > 255)\r
+#error "Maximum Packet Count is 255"\r
+#endif\r
+\r
+\r
+// Clock Macros\r
+\r
+#define MAX_SWJ_CLOCK(delay_cycles) \\r
+ (CPU_CLOCK/2 / (IO_PORT_WRITE_CYCLES + delay_cycles))\r
+\r
+#define CLOCK_DELAY(swj_clock) \\r
+ ((CPU_CLOCK/2 / swj_clock) - IO_PORT_WRITE_CYCLES)\r
+\r
+\r
+ DAP_Data_t DAP_Data; // DAP Data\r
+volatile uint8_t DAP_TransferAbort; // Trasfer Abort Flag\r
+\r
+\r
+#ifdef DAP_VENDOR\r
+const char DAP_Vendor [] = DAP_VENDOR;\r
+#endif\r
+#ifdef DAP_PRODUCT\r
+const char DAP_Product[] = DAP_PRODUCT;\r
+#endif\r
+#ifdef DAP_SER_NUM\r
+const char DAP_SerNum [] = DAP_SER_NUM;\r
+#endif\r
+const char DAP_FW_Ver [] = DAP_FW_VER;\r
+\r
+#if TARGET_DEVICE_FIXED\r
+const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR;\r
+const char TargetDeviceName [] = TARGET_DEVICE_NAME;\r
+#endif\r
+\r
+\r
+// Get DAP Information\r
+// id: info identifier\r
+// info: pointer to info data\r
+// return: number of bytes in info data\r
+static uint8_t DAP_Info(uint8_t id, uint8_t *info) {\r
+ uint8_t length = 0;\r
+\r
+ switch (id) {\r
+ case DAP_ID_VENDOR:\r
+#ifdef DAP_VENDOR\r
+ memcpy(info, DAP_Vendor, sizeof(DAP_Vendor));\r
+ length = sizeof(DAP_Vendor);\r
+#endif\r
+ break;\r
+ case DAP_ID_PRODUCT:\r
+#ifdef DAP_PRODUCT\r
+ memcpy(info, DAP_Product, sizeof(DAP_Product));\r
+ length = sizeof(DAP_Product);\r
+#endif\r
+ break;\r
+ case DAP_ID_SER_NUM:\r
+#ifdef DAP_SER_NUM\r
+ memcpy(info, DAP_SerNum, sizeof(DAP_SerNum));\r
+ length = sizeof(DAP_SerNum);\r
+#endif\r
+ break;\r
+ case DAP_ID_FW_VER:\r
+ memcpy(info, DAP_FW_Ver, sizeof(DAP_FW_Ver));\r
+ length = sizeof(DAP_FW_Ver);\r
+ break;\r
+ case DAP_ID_DEVICE_VENDOR:\r
+#if TARGET_DEVICE_FIXED\r
+ memcpy(info, TargetDeviceVendor, sizeof(TargetDeviceVendor));\r
+ length = sizeof(TargetDeviceVendor);\r
+#endif\r
+ break;\r
+ case DAP_ID_DEVICE_NAME:\r
+#if TARGET_DEVICE_FIXED\r
+ memcpy(info, TargetDeviceName, sizeof(TargetDeviceName));\r
+ length = sizeof(TargetDeviceName);\r
+#endif\r
+ break;\r
+ case DAP_ID_CAPABILITIES:\r
+ info[0] = ((DAP_SWD != 0) ? (1 << 0) : 0) |\r
+ ((DAP_JTAG != 0) ? (1 << 1) : 0);\r
+ length = 1;\r
+ break;\r
+ case DAP_ID_PACKET_SIZE:\r
+ info[0] = (uint8_t)(DAP_PACKET_SIZE >> 0);\r
+ info[1] = (uint8_t)(DAP_PACKET_SIZE >> 8);\r
+ length = 2;\r
+ break;\r
+ case DAP_ID_PACKET_COUNT:\r
+ info[0] = DAP_PACKET_COUNT;\r
+ length = 1;\r
+ break;\r
+ }\r
+\r
+ return (length);\r
+}\r
+\r
+\r
+// Timer Functions\r
+\r
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))\r
+\r
+// Start Timer\r
+static __inline void TIMER_START (uint32_t usec) {\r
+ SysTick->VAL = 0;\r
+ SysTick->LOAD = usec * CPU_CLOCK/1000000;\r
+ SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) |\r
+ (1 << SysTick_CTRL_CLKSOURCE_Pos);\r
+}\r
+\r
+// Stop Timer\r
+static __inline void TIMER_STOP (void) {\r
+ SysTick->CTRL = 0;\r
+}\r
+\r
+// Check if Timer expired\r
+static __inline uint32_t TIMER_EXPIRED (void) {\r
+ return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) ? 1 : 0);\r
+}\r
+\r
+#endif\r
+\r
+\r
+// Delay for specified time\r
+// delay: delay time in ms\r
+void Delayms(uint32_t delay) {\r
+ delay *= (CPU_CLOCK/1000 + (DELAY_SLOW_CYCLES-1)) / DELAY_SLOW_CYCLES;\r
+ PIN_DELAY_SLOW(delay);\r
+}\r
+\r
+\r
+// Process Delay command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+static uint32_t DAP_Delay(uint8_t *request, uint8_t *response) {\r
+ uint32_t delay;\r
+\r
+ delay = *(request+0) | (*(request+1) << 8);\r
+ delay *= (CPU_CLOCK/1000000 + (DELAY_SLOW_CYCLES-1)) / DELAY_SLOW_CYCLES;\r
+\r
+ PIN_DELAY_SLOW(delay);\r
+\r
+ *response = DAP_OK;\r
+ return (1);\r
+}\r
+\r
+\r
+// Process LED command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+static uint32_t DAP_LED(uint8_t *request, uint8_t *response) {\r
+\r
+ switch (*request) {\r
+ case DAP_LED_DEBUGGER_CONNECTED:\r
+ LED_CONNECTED_OUT((*(request+1) & 1));\r
+ break;\r
+ case DAP_LED_TARGET_RUNNING:\r
+ LED_RUNNING_OUT((*(request+1) & 1));\r
+ break;\r
+ default:\r
+ *response = DAP_ERROR;\r
+ return (1);\r
+ }\r
+\r
+ *response = DAP_OK;\r
+ return (1);\r
+}\r
+\r
+\r
+// Process Connect command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+static uint32_t DAP_Connect(uint8_t *request, uint8_t *response) {\r
+ uint32_t port;\r
+\r
+ if (*request == DAP_PORT_AUTODETECT) {\r
+ port = DAP_DEFAULT_PORT;\r
+ } else {\r
+ port = *request;\r
+ }\r
+ \r
+ switch (port) {\r
+#if (DAP_SWD != 0)\r
+ case DAP_PORT_SWD:\r
+ DAP_Data.debug_port = DAP_PORT_SWD;\r
+ PORT_SWD_SETUP();\r
+ break;\r
+#endif\r
+#if (DAP_JTAG != 0)\r
+ case DAP_PORT_JTAG:\r
+ DAP_Data.debug_port = DAP_PORT_JTAG;\r
+ PORT_JTAG_SETUP();\r
+ break;\r
+#endif\r
+ default:\r
+ *response = DAP_PORT_DISABLED;\r
+ return (1);\r
+ }\r
+\r
+ *response = port;\r
+ return (1);\r
+}\r
+\r
+\r
+// Process Disconnect command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+static uint32_t DAP_Disconnect(uint8_t *response) {\r
+\r
+ DAP_Data.debug_port = DAP_PORT_DISABLED;\r
+ PORT_OFF();\r
+\r
+ *response = DAP_OK;\r
+ return (1);\r
+}\r
+\r
+\r
+// Process Reset Target command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+static uint32_t DAP_ResetTarget(uint8_t *response) {\r
+\r
+ *(response+1) = RESET_TARGET();\r
+ *(response+0) = DAP_OK;\r
+ return (2);\r
+}\r
+\r
+\r
+// Process SWJ Pins command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))\r
+static uint32_t DAP_SWJ_Pins(uint8_t *request, uint8_t *response) {\r
+ uint32_t value;\r
+ uint32_t select;\r
+ uint32_t wait;\r
+ \r
+ value = *(request+0);\r
+ select = *(request+1); \r
+ wait = (*(request+2) << 0) |\r
+ (*(request+3) << 8) |\r
+ (*(request+4) << 16) |\r
+ (*(request+5) << 24);\r
+\r
+ if (select & (1 << DAP_SWJ_SWCLK_TCK)) {\r
+ if (value & (1 << DAP_SWJ_SWCLK_TCK)) {\r
+ PIN_SWCLK_TCK_SET();\r
+ } else {\r
+ PIN_SWCLK_TCK_CLR();\r
+ }\r
+ }\r
+ if (select & (1 << DAP_SWJ_SWDIO_TMS)) {\r
+ if (value & (1 << DAP_SWJ_SWDIO_TMS)) {\r
+ PIN_SWDIO_TMS_SET();\r
+ } else {\r
+ PIN_SWDIO_TMS_CLR();\r
+ }\r
+ }\r
+ if (select & (1 << DAP_SWJ_TDI)) {\r
+ PIN_TDI_OUT(value >> DAP_SWJ_TDI);\r
+ }\r
+ if (select & (1 << DAP_SWJ_nTRST)) {\r
+ PIN_nTRST_OUT(value >> DAP_SWJ_nTRST);\r
+ }\r
+ if (select & (1 << DAP_SWJ_nRESET)) {\r
+ PIN_nRESET_OUT(value >> DAP_SWJ_nRESET);\r
+ }\r
+\r
+ if (wait) {\r
+ if (wait > 3000000) wait = 3000000;\r
+ TIMER_START(wait);\r
+ do {\r
+ if (select & (1 << DAP_SWJ_SWCLK_TCK)) {\r
+ if ((value >> DAP_SWJ_SWCLK_TCK) ^ PIN_SWCLK_TCK_IN()) continue;\r
+ }\r
+ if (select & (1 << DAP_SWJ_SWDIO_TMS)) {\r
+ if ((value >> DAP_SWJ_SWDIO_TMS) ^ PIN_SWDIO_TMS_IN()) continue;\r
+ }\r
+ if (select & (1 << DAP_SWJ_TDI)) {\r
+ if ((value >> DAP_SWJ_TDI) ^ PIN_TDI_IN()) continue;\r
+ }\r
+ if (select & (1 << DAP_SWJ_nTRST)) {\r
+ if ((value >> DAP_SWJ_nTRST) ^ PIN_nTRST_IN()) continue;\r
+ }\r
+ if (select & (1 << DAP_SWJ_nRESET)) {\r
+ if ((value >> DAP_SWJ_nRESET) ^ PIN_nRESET_IN()) continue;\r
+ }\r
+ break;\r
+ } while (!TIMER_EXPIRED());\r
+ TIMER_STOP();\r
+ }\r
+\r
+ value = (PIN_SWCLK_TCK_IN() << DAP_SWJ_SWCLK_TCK) |\r
+ (PIN_SWDIO_TMS_IN() << DAP_SWJ_SWDIO_TMS) |\r
+ (PIN_TDI_IN() << DAP_SWJ_TDI) |\r
+ (PIN_TDO_IN() << DAP_SWJ_TDO) |\r
+ (PIN_nTRST_IN() << DAP_SWJ_nTRST) |\r
+ (PIN_nRESET_IN() << DAP_SWJ_nRESET);\r
+\r
+ *response = (uint8_t)value;\r
+ return (1);\r
+}\r
+#endif\r
+\r
+\r
+// Process SWJ Clock command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))\r
+static uint32_t DAP_SWJ_Clock(uint8_t *request, uint8_t *response) {\r
+ uint32_t clock;\r
+ uint32_t delay;\r
+\r
+ clock = (*(request+0) << 0) |\r
+ (*(request+1) << 8) |\r
+ (*(request+2) << 16) |\r
+ (*(request+3) << 24);\r
+\r
+ if (clock == 0) {\r
+ *response = DAP_ERROR;\r
+ return (1);\r
+ }\r
+\r
+ if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) {\r
+ DAP_Data.fast_clock = 1;\r
+ DAP_Data.clock_delay = 1;\r
+ } else {\r
+ DAP_Data.fast_clock = 0;\r
+\r
+ delay = (CPU_CLOCK/2 + (clock - 1)) / clock;\r
+ if (delay > IO_PORT_WRITE_CYCLES) {\r
+ delay -= IO_PORT_WRITE_CYCLES;\r
+ delay = (delay + (DELAY_SLOW_CYCLES - 1)) / DELAY_SLOW_CYCLES;\r
+ } else {\r
+ delay = 1;\r
+ }\r
+\r
+ DAP_Data.clock_delay = delay;\r
+ }\r
+\r
+ *response = DAP_OK;\r
+ return (1);\r
+}\r
+#endif\r
+\r
+\r
+// Process SWJ Sequence command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))\r
+static uint32_t DAP_SWJ_Sequence(uint8_t *request, uint8_t *response) {\r
+ uint32_t count;\r
+\r
+ count = *request++;\r
+ if (count == 0) count = 256;\r
+\r
+ SWJ_Sequence(count, request);\r
+\r
+ *response = DAP_OK;\r
+ return (1);\r
+}\r
+#endif\r
+\r
+\r
+// Process SWD Configure command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_SWD != 0)\r
+static uint32_t DAP_SWD_Configure(uint8_t *request, uint8_t *response) {\r
+ uint8_t value;\r
+\r
+ value = *request;\r
+ DAP_Data.swd_conf.turnaround = (value & 0x03) + 1;\r
+ DAP_Data.swd_conf.data_phase = (value & 0x04) ? 1 : 0;\r
+ \r
+ *response = DAP_OK;\r
+\r
+ return (1);\r
+}\r
+#endif\r
+\r
+\r
+// Process SWD Abort command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_SWD != 0)\r
+static uint32_t DAP_SWD_Abort(uint8_t *request, uint8_t *response) {\r
+ uint32_t data;\r
+\r
+ if (DAP_Data.debug_port != DAP_PORT_SWD) {\r
+ *response = DAP_ERROR;\r
+ return (1);\r
+ }\r
+\r
+ // Load data (Ignore DAP index)\r
+ data = (*(request+1) << 0) |\r
+ (*(request+2) << 8) |\r
+ (*(request+3) << 16) |\r
+ (*(request+4) << 24);\r
+\r
+ // Write Abort register\r
+ SWD_Transfer(DP_ABORT, &data);\r
+ *response = DAP_OK;\r
+\r
+ return (1);\r
+}\r
+#endif\r
+\r
+\r
+// Process JTAG Sequence command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_JTAG != 0)\r
+static uint32_t DAP_JTAG_Sequence(uint8_t *request, uint8_t *response) {\r
+ uint32_t sequence_info;\r
+ uint32_t sequence_count;\r
+ uint32_t response_count;\r
+ uint32_t count;\r
+\r
+ *response++ = DAP_OK;\r
+ response_count = 1;\r
+\r
+ sequence_count = *request++;\r
+ while (sequence_count--) {\r
+ sequence_info = *request++;\r
+ JTAG_Sequence(sequence_info, request, response);\r
+ count = sequence_info & JTAG_SEQUENCE_TCK;\r
+ if (count == 0) count = 64;\r
+ count = (count + 7) / 8;\r
+ request += count;\r
+ if (sequence_info & JTAG_SEQUENCE_TDO) {\r
+ response += count;\r
+ response_count += count;\r
+ }\r
+ }\r
+\r
+ return (response_count);\r
+}\r
+#endif\r
+\r
+\r
+// Process JTAG Configure command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_JTAG != 0)\r
+static uint32_t DAP_JTAG_Configure(uint8_t *request, uint8_t *response) {\r
+ uint32_t count;\r
+ uint32_t length;\r
+ uint32_t bits;\r
+ uint32_t n;\r
+\r
+ count = *request++;\r
+ DAP_Data.jtag_dev.count = count;\r
+\r
+ bits = 0;\r
+ for (n = 0; n < count; n++) {\r
+ length = *request++;\r
+ DAP_Data.jtag_dev.ir_length[n] = length;\r
+ DAP_Data.jtag_dev.ir_before[n] = bits;\r
+ bits += length;\r
+ }\r
+ for (n = 0; n < count; n++) {\r
+ bits -= DAP_Data.jtag_dev.ir_length[n];\r
+ DAP_Data.jtag_dev.ir_after[n] = bits;\r
+ }\r
+\r
+ *response = DAP_OK;\r
+ return (1);\r
+}\r
+#endif\r
+\r
+\r
+// Process JTAG IDCODE command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_JTAG != 0)\r
+static uint32_t DAP_JTAG_IDCode(uint8_t *request, uint8_t *response) {\r
+ uint32_t data;\r
+\r
+ if (DAP_Data.debug_port != DAP_PORT_JTAG) {\r
+err:*response = DAP_ERROR;\r
+ return (1);\r
+ }\r
+\r
+ // Device index (JTAP TAP)\r
+ DAP_Data.jtag_dev.index = *request;\r
+ if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) goto err;\r
+\r
+ // Select JTAG chain\r
+ JTAG_IR(JTAG_IDCODE);\r
+\r
+ // Read IDCODE register\r
+ data = JTAG_ReadIDCode();\r
+\r
+ // Store Data\r
+ *(response+0) = DAP_OK;\r
+ *(response+1) = (uint8_t)(data >> 0);\r
+ *(response+2) = (uint8_t)(data >> 8);\r
+ *(response+3) = (uint8_t)(data >> 16);\r
+ *(response+4) = (uint8_t)(data >> 24);\r
+\r
+ return (1+4);\r
+}\r
+#endif\r
+\r
+\r
+// Process JTAG Abort command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_JTAG != 0)\r
+static uint32_t DAP_JTAG_Abort(uint8_t *request, uint8_t *response) {\r
+ uint32_t data;\r
+\r
+ if (DAP_Data.debug_port != DAP_PORT_JTAG) {\r
+err:*response = DAP_ERROR;\r
+ return (1);\r
+ }\r
+\r
+ // Device index (JTAP TAP)\r
+ DAP_Data.jtag_dev.index = *request;\r
+ if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) goto err;\r
+\r
+ // Select JTAG chain\r
+ JTAG_IR(JTAG_ABORT);\r
+\r
+ // Load data\r
+ data = (*(request+1) << 0) |\r
+ (*(request+2) << 8) |\r
+ (*(request+3) << 16) |\r
+ (*(request+4) << 24);\r
+\r
+ // Write Abort register\r
+ JTAG_WriteAbort(data);\r
+ *response = DAP_OK;\r
+\r
+ return (1);\r
+}\r
+#endif\r
+\r
+\r
+// Process Transfer Configure command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+static uint32_t DAP_TransferConfigure(uint8_t *request, uint8_t *response) {\r
+\r
+ DAP_Data.transfer.idle_cycles = *(request+0);\r
+ DAP_Data.transfer.retry_count = *(request+1) | (*(request+2) << 8);\r
+ DAP_Data.transfer.match_retry = *(request+3) | (*(request+4) << 8);\r
+ \r
+ *response = DAP_OK;\r
+\r
+ return (1);\r
+}\r
+\r
+\r
+// Process SWD Transfer command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_SWD != 0)\r
+static uint32_t DAP_SWD_Transfer(uint8_t *request, uint8_t *response) {\r
+ uint32_t request_count;\r
+ uint32_t request_value;\r
+ uint32_t response_count;\r
+ uint32_t response_value;\r
+ uint8_t *response_head;\r
+ uint32_t post_read;\r
+ uint32_t check_write;\r
+ uint32_t match_value;\r
+ uint32_t match_retry;\r
+ uint32_t retry;\r
+ uint32_t data;\r
+\r
+ response_count = 0;\r
+ response_value = 0;\r
+ response_head = response;\r
+ response += 2;\r
+\r
+ DAP_TransferAbort = 0;\r
+\r
+ post_read = 0;\r
+ check_write = 0;\r
+\r
+ request++; // Ignore DAP index\r
+\r
+ request_count = *request++;\r
+ while (request_count--) {\r
+ request_value = *request++;\r
+ if (request_value & DAP_TRANSFER_RnW) {\r
+ // Read register\r
+ if (post_read) {\r
+ // Read was posted before\r
+ retry = DAP_Data.transfer.retry_count;\r
+ if ((request_value & (DAP_TRANSFER_APnDP | DAP_TRANSFER_MATCH_VALUE)) == DAP_TRANSFER_APnDP) {\r
+ // Read previous AP data and post next AP read\r
+ do {\r
+ response_value = SWD_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ } else {\r
+ // Read previous AP data\r
+ do {\r
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ post_read = 0;\r
+ }\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ // Store previous AP data\r
+ *response++ = (uint8_t) data;\r
+ *response++ = (uint8_t)(data >> 8);\r
+ *response++ = (uint8_t)(data >> 16);\r
+ *response++ = (uint8_t)(data >> 24);\r
+ }\r
+ if (request_value & DAP_TRANSFER_MATCH_VALUE) {\r
+ // Read with value match\r
+ match_value = (*(request+0) << 0) |\r
+ (*(request+1) << 8) |\r
+ (*(request+2) << 16) |\r
+ (*(request+3) << 24);\r
+ request += 4;\r
+ match_retry = DAP_Data.transfer.match_retry;\r
+ if (request_value & DAP_TRANSFER_APnDP) {\r
+ // Post AP read\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(request_value, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ }\r
+ do {\r
+ // Read register until its value matches or retry counter expires\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort);\r
+ if ((data & DAP_Data.transfer.match_mask) != match_value) {\r
+ response_value |= DAP_TRANSFER_MISMATCH;\r
+ }\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ } else {\r
+ // Normal read\r
+ retry = DAP_Data.transfer.retry_count;\r
+ if (request_value & DAP_TRANSFER_APnDP) {\r
+ // Read AP register\r
+ if (post_read == 0) {\r
+ // Post AP read\r
+ do {\r
+ response_value = SWD_Transfer(request_value, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ post_read = 1;\r
+ }\r
+ } else {\r
+ // Read DP register\r
+ do {\r
+ response_value = SWD_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ // Store data\r
+ *response++ = (uint8_t) data;\r
+ *response++ = (uint8_t)(data >> 8);\r
+ *response++ = (uint8_t)(data >> 16);\r
+ *response++ = (uint8_t)(data >> 24);\r
+ }\r
+ }\r
+ check_write = 0;\r
+ } else {\r
+ // Write register\r
+ if (post_read) {\r
+ // Read previous data\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ // Store previous data\r
+ *response++ = (uint8_t) data;\r
+ *response++ = (uint8_t)(data >> 8);\r
+ *response++ = (uint8_t)(data >> 16);\r
+ *response++ = (uint8_t)(data >> 24);\r
+ post_read = 0;\r
+ }\r
+ // Load data\r
+ data = (*(request+0) << 0) |\r
+ (*(request+1) << 8) |\r
+ (*(request+2) << 16) |\r
+ (*(request+3) << 24);\r
+ request += 4;\r
+ if (request_value & DAP_TRANSFER_MATCH_MASK) {\r
+ // Write match mask\r
+ DAP_Data.transfer.match_mask = data;\r
+ response_value = DAP_TRANSFER_OK;\r
+ } else {\r
+ // Write DP/AP register\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ check_write = 1;\r
+ }\r
+ }\r
+ response_count++;\r
+ if (DAP_TransferAbort) break;\r
+ }\r
+\r
+ if (response_value == DAP_TRANSFER_OK) {\r
+ if (post_read) {\r
+ // Read previous data\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) goto end;\r
+ // Store previous data\r
+ *response++ = (uint8_t) data;\r
+ *response++ = (uint8_t)(data >> 8);\r
+ *response++ = (uint8_t)(data >> 16);\r
+ *response++ = (uint8_t)(data >> 24);\r
+ } else if (check_write) {\r
+ // Check last write\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ }\r
+ }\r
+\r
+end:\r
+ *(response_head+0) = (uint8_t)response_count;\r
+ *(response_head+1) = (uint8_t)response_value;\r
+\r
+ return (response - response_head);\r
+}\r
+#endif\r
+\r
+\r
+// Process JTAG Transfer command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_JTAG != 0)\r
+static uint32_t DAP_JTAG_Transfer(uint8_t *request, uint8_t *response) {\r
+ uint32_t request_count;\r
+ uint32_t request_value;\r
+ uint32_t request_ir;\r
+ uint32_t response_count;\r
+ uint32_t response_value;\r
+ uint8_t *response_head;\r
+ uint32_t post_read;\r
+ uint32_t match_value;\r
+ uint32_t match_retry;\r
+ uint32_t retry;\r
+ uint32_t data;\r
+ uint32_t ir;\r
+\r
+ response_count = 0;\r
+ response_value = 0;\r
+ response_head = response;\r
+ response += 2;\r
+\r
+ DAP_TransferAbort = 0;\r
+\r
+ ir = 0;\r
+ post_read = 0;\r
+\r
+ // Device index (JTAP TAP)\r
+ DAP_Data.jtag_dev.index = *request++;\r
+ if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) goto end;\r
+\r
+ request_count = *request++;\r
+ while (request_count--) {\r
+ request_value = *request++;\r
+ request_ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC;\r
+ if (request_value & DAP_TRANSFER_RnW) {\r
+ // Read register\r
+ if (post_read) {\r
+ // Read was posted before\r
+ retry = DAP_Data.transfer.retry_count;\r
+ if ((ir == request_ir) && ((request_value & DAP_TRANSFER_MATCH_VALUE) == 0)) {\r
+ // Read previous data and post next read\r
+ do {\r
+ response_value = JTAG_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ } else {\r
+ // Select JTAG chain\r
+ if (ir != JTAG_DPACC) {\r
+ ir = JTAG_DPACC;\r
+ JTAG_IR(ir);\r
+ }\r
+ // Read previous data\r
+ do {\r
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ post_read = 0;\r
+ }\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ // Store previous data\r
+ *response++ = (uint8_t) data;\r
+ *response++ = (uint8_t)(data >> 8);\r
+ *response++ = (uint8_t)(data >> 16);\r
+ *response++ = (uint8_t)(data >> 24);\r
+ }\r
+ if (request_value & DAP_TRANSFER_MATCH_VALUE) {\r
+ // Read with value match\r
+ match_value = (*(request+0) << 0) |\r
+ (*(request+1) << 8) |\r
+ (*(request+2) << 16) |\r
+ (*(request+3) << 24);\r
+ request += 4;\r
+ match_retry = DAP_Data.transfer.match_retry;\r
+ // Select JTAG chain\r
+ if (ir != request_ir) {\r
+ ir = request_ir;\r
+ JTAG_IR(ir);\r
+ }\r
+ // Post DP/AP read\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(request_value, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ do {\r
+ // Read register until its value matches or retry counter expires\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort);\r
+ if ((data & DAP_Data.transfer.match_mask) != match_value) {\r
+ response_value |= DAP_TRANSFER_MISMATCH;\r
+ }\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ } else {\r
+ // Normal read\r
+ if (post_read == 0) {\r
+ // Select JTAG chain\r
+ if (ir != request_ir) {\r
+ ir = request_ir;\r
+ JTAG_IR(ir);\r
+ }\r
+ // Post DP/AP read\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(request_value, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ post_read = 1;\r
+ }\r
+ }\r
+ } else {\r
+ // Write register\r
+ if (post_read) {\r
+ // Select JTAG chain\r
+ if (ir != JTAG_DPACC) {\r
+ ir = JTAG_DPACC;\r
+ JTAG_IR(ir);\r
+ }\r
+ // Read previous data\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ // Store previous data\r
+ *response++ = (uint8_t) data;\r
+ *response++ = (uint8_t)(data >> 8);\r
+ *response++ = (uint8_t)(data >> 16);\r
+ *response++ = (uint8_t)(data >> 24);\r
+ post_read = 0;\r
+ }\r
+ // Load data\r
+ data = (*(request+0) << 0) |\r
+ (*(request+1) << 8) |\r
+ (*(request+2) << 16) |\r
+ (*(request+3) << 24);\r
+ request += 4;\r
+ if (request_value & DAP_TRANSFER_MATCH_MASK) {\r
+ // Write match mask\r
+ DAP_Data.transfer.match_mask = data;\r
+ response_value = DAP_TRANSFER_OK;\r
+ } else {\r
+ // Select JTAG chain\r
+ if (ir != request_ir) {\r
+ ir = request_ir;\r
+ JTAG_IR(ir);\r
+ }\r
+ // Write DP/AP register\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) break;\r
+ }\r
+ }\r
+ response_count++;\r
+ if (DAP_TransferAbort) break;\r
+ }\r
+\r
+ if (response_value == DAP_TRANSFER_OK) {\r
+ // Select JTAG chain\r
+ if (ir != JTAG_DPACC) {\r
+ ir = JTAG_DPACC;\r
+ JTAG_IR(ir);\r
+ }\r
+ if (post_read) {\r
+ // Read previous data\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) goto end;\r
+ // Store previous data\r
+ *response++ = (uint8_t) data;\r
+ *response++ = (uint8_t)(data >> 8);\r
+ *response++ = (uint8_t)(data >> 16);\r
+ *response++ = (uint8_t)(data >> 24);\r
+ } else {\r
+ // Check last write\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ }\r
+ }\r
+\r
+end:\r
+ *(response_head+0) = (uint8_t)response_count;\r
+ *(response_head+1) = (uint8_t)response_value;\r
+\r
+ return (response - response_head);\r
+}\r
+#endif\r
+\r
+\r
+// Process SWD Transfer Block command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_SWD != 0)\r
+static uint32_t DAP_SWD_TransferBlock(uint8_t *request, uint8_t *response) {\r
+ uint32_t request_count;\r
+ uint32_t request_value;\r
+ uint32_t response_count;\r
+ uint32_t response_value;\r
+ uint8_t *response_head;\r
+ uint32_t retry;\r
+ uint32_t data;\r
+\r
+ response_count = 0;\r
+ response_value = 0;\r
+ response_head = response;\r
+ response += 3;\r
+\r
+ DAP_TransferAbort = 0;\r
+\r
+ request++; // Ignore DAP index\r
+\r
+ request_count = *request | (*(request+1) << 8);\r
+ request += 2;\r
+ if (request_count == 0) goto end;\r
+\r
+ request_value = *request++;\r
+ if (request_value & DAP_TRANSFER_RnW) {\r
+ // Read register block\r
+ if (request_value & DAP_TRANSFER_APnDP) {\r
+ // Post AP read\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(request_value, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) goto end;\r
+ }\r
+ while (request_count--) {\r
+ // Read DP/AP register\r
+ if ((request_count == 0) && (request_value & DAP_TRANSFER_APnDP)) {\r
+ // Last AP read\r
+ request_value = DP_RDBUFF | DAP_TRANSFER_RnW;\r
+ }\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) goto end;\r
+ // Store data\r
+ *response++ = (uint8_t) data;\r
+ *response++ = (uint8_t)(data >> 8);\r
+ *response++ = (uint8_t)(data >> 16);\r
+ *response++ = (uint8_t)(data >> 24);\r
+ response_count++;\r
+ }\r
+ } else {\r
+ // Write register block\r
+ while (request_count--) {\r
+ // Load data\r
+ data = (*(request+0) << 0) |\r
+ (*(request+1) << 8) |\r
+ (*(request+2) << 16) |\r
+ (*(request+3) << 24);\r
+ request += 4;\r
+ // Write DP/AP register\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) goto end;\r
+ response_count++;\r
+ }\r
+ // Check last write\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ }\r
+\r
+end:\r
+ *(response_head+0) = (uint8_t)(response_count >> 0);\r
+ *(response_head+1) = (uint8_t)(response_count >> 8);\r
+ *(response_head+2) = (uint8_t) response_value;\r
+\r
+ return (response - response_head);\r
+}\r
+#endif\r
+\r
+\r
+// Process JTAG Transfer Block command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+#if (DAP_JTAG != 0)\r
+static uint32_t DAP_JTAG_TransferBlock(uint8_t *request, uint8_t *response) {\r
+ uint32_t request_count;\r
+ uint32_t request_value;\r
+ uint32_t response_count;\r
+ uint32_t response_value;\r
+ uint8_t *response_head;\r
+ uint32_t retry;\r
+ uint32_t data;\r
+ uint32_t ir;\r
+\r
+ response_count = 0;\r
+ response_value = 0;\r
+ response_head = response;\r
+ response += 3;\r
+\r
+ DAP_TransferAbort = 0;\r
+\r
+ // Device index (JTAP TAP)\r
+ DAP_Data.jtag_dev.index = *request++;\r
+ if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) goto end;\r
+\r
+ request_count = *request | (*(request+1) << 8);\r
+ request += 2;\r
+ if (request_count == 0) goto end;\r
+\r
+ request_value = *request++;\r
+\r
+ // Select JTAG chain\r
+ ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC;\r
+ JTAG_IR(ir);\r
+\r
+ if (request_value & DAP_TRANSFER_RnW) {\r
+ // Post read\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(request_value, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) goto end;\r
+ // Read register block\r
+ while (request_count--) {\r
+ // Read DP/AP register\r
+ if (request_count == 0) {\r
+ // Last read\r
+ if (ir != JTAG_DPACC) {\r
+ JTAG_IR(JTAG_DPACC);\r
+ }\r
+ request_value = DP_RDBUFF | DAP_TRANSFER_RnW;\r
+ }\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) goto end;\r
+ // Store data\r
+ *response++ = (uint8_t) data;\r
+ *response++ = (uint8_t)(data >> 8);\r
+ *response++ = (uint8_t)(data >> 16);\r
+ *response++ = (uint8_t)(data >> 24);\r
+ response_count++;\r
+ }\r
+ } else {\r
+ // Write register block\r
+ while (request_count--) {\r
+ // Load data\r
+ data = (*(request+0) << 0) |\r
+ (*(request+1) << 8) |\r
+ (*(request+2) << 16) |\r
+ (*(request+3) << 24);\r
+ request += 4;\r
+ // Write DP/AP register\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(request_value, &data);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ if (response_value != DAP_TRANSFER_OK) goto end;\r
+ response_count++;\r
+ }\r
+ // Check last write\r
+ if (ir != JTAG_DPACC) {\r
+ JTAG_IR(JTAG_DPACC);\r
+ }\r
+ retry = DAP_Data.transfer.retry_count;\r
+ do {\r
+ response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL);\r
+ } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);\r
+ }\r
+\r
+end:\r
+ *(response_head+0) = (uint8_t)(response_count >> 0);\r
+ *(response_head+1) = (uint8_t)(response_count >> 8);\r
+ *(response_head+2) = (uint8_t) response_value;\r
+\r
+ return (response - response_head);\r
+}\r
+#endif\r
+\r
+\r
+// Process DAP Vendor command and prepare response\r
+// Default function (can be overridden)\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+__weak uint32_t DAP_ProcessVendorCommand(uint8_t *request, uint8_t *response) {\r
+ *response = ID_DAP_Invalid;\r
+ return (1);\r
+}\r
+\r
+\r
+// Process DAP command and prepare response\r
+// request: pointer to request data\r
+// response: pointer to response data\r
+// return: number of bytes in response\r
+uint32_t DAP_ProcessCommand(uint8_t *request, uint8_t *response) {\r
+ uint32_t num;\r
+\r
+ if ((*request >= ID_DAP_Vendor0) && (*request <= ID_DAP_Vendor31)) {\r
+ return DAP_ProcessVendorCommand(request, response);\r
+ }\r
+\r
+ *response++ = *request;\r
+\r
+ switch (*request++) {\r
+ case ID_DAP_Info:\r
+ num = DAP_Info(*request, response+1);\r
+ *response = num;\r
+ return (2 + num);\r
+ case ID_DAP_LED:\r
+ num = DAP_LED(request, response);\r
+ break;\r
+ case ID_DAP_Connect:\r
+ num = DAP_Connect(request, response);\r
+ break;\r
+ case ID_DAP_Disconnect:\r
+ num = DAP_Disconnect(response);\r
+ break;\r
+ case ID_DAP_Delay:\r
+ num = DAP_Delay(request, response);\r
+ break;\r
+ case ID_DAP_ResetTarget:\r
+ num = DAP_ResetTarget(response);\r
+ break;\r
+\r
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))\r
+ case ID_DAP_SWJ_Pins:\r
+ num = DAP_SWJ_Pins(request, response);\r
+ break;\r
+ case ID_DAP_SWJ_Clock:\r
+ num = DAP_SWJ_Clock(request, response);\r
+ break;\r
+ case ID_DAP_SWJ_Sequence:\r
+ num = DAP_SWJ_Sequence(request, response);\r
+ break;\r
+#else\r
+ case ID_DAP_SWJ_Pins:\r
+ case ID_DAP_SWJ_Clock:\r
+ case ID_DAP_SWJ_Sequence:\r
+ *response = DAP_ERROR;\r
+ return (2);\r
+#endif\r
+\r
+#if (DAP_SWD != 0)\r
+ case ID_DAP_SWD_Configure:\r
+ num = DAP_SWD_Configure(request, response);\r
+ break;\r
+#else\r
+ case ID_DAP_SWD_Configure:\r
+ *response = DAP_ERROR;\r
+ return (2);\r
+#endif\r
+\r
+#if (DAP_JTAG != 0)\r
+ case ID_DAP_JTAG_Sequence:\r
+ num = DAP_JTAG_Sequence(request, response);\r
+ break;\r
+ case ID_DAP_JTAG_Configure:\r
+ num = DAP_JTAG_Configure(request, response);\r
+ break;\r
+ case ID_DAP_JTAG_IDCODE:\r
+ num = DAP_JTAG_IDCode(request, response);\r
+ break;\r
+#else\r
+ case ID_DAP_JTAG_Sequence:\r
+ case ID_DAP_JTAG_Configure:\r
+ case ID_DAP_JTAG_IDCODE:\r
+ *response = DAP_ERROR;\r
+ return (2);\r
+#endif\r
+\r
+ case ID_DAP_TransferConfigure:\r
+ num = DAP_TransferConfigure(request, response);\r
+ break;\r
+\r
+ case ID_DAP_Transfer:\r
+ switch (DAP_Data.debug_port) {\r
+#if (DAP_SWD != 0)\r
+ case DAP_PORT_SWD:\r
+ num = DAP_SWD_Transfer (request, response);\r
+ break;\r
+#endif\r
+#if (DAP_JTAG != 0)\r
+ case DAP_PORT_JTAG:\r
+ num = DAP_JTAG_Transfer(request, response);\r
+ break;\r
+#endif\r
+ default:\r
+ *(response+0) = 0; // Response count\r
+ *(response+1) = 0; // Response value\r
+ num = 2;\r
+ }\r
+ break;\r
+\r
+ case ID_DAP_TransferBlock:\r
+ switch (DAP_Data.debug_port) {\r
+#if (DAP_SWD != 0)\r
+ case DAP_PORT_SWD:\r
+ num = DAP_SWD_TransferBlock (request, response);\r
+ break;\r
+#endif\r
+#if (DAP_JTAG != 0)\r
+ case DAP_PORT_JTAG:\r
+ num = DAP_JTAG_TransferBlock(request, response);\r
+ break;\r
+#endif\r
+ default:\r
+ *(response+0) = 0; // Response count [7:0]\r
+ *(response+1) = 0; // Response count[15:8]\r
+ *(response+2) = 0; // Response value\r
+ num = 3;\r
+ }\r
+ break;\r
+\r
+ case ID_DAP_WriteABORT:\r
+ switch (DAP_Data.debug_port) {\r
+#if (DAP_SWD != 0)\r
+ case DAP_PORT_SWD:\r
+ num = DAP_SWD_Abort (request, response);\r
+ break;\r
+#endif\r
+#if (DAP_JTAG != 0)\r
+ case DAP_PORT_JTAG:\r
+ num = DAP_JTAG_Abort(request, response);\r
+ break;\r
+#endif\r
+ default:\r
+ *response = DAP_ERROR;\r
+ return (2);\r
+ }\r
+ break;\r
+\r
+ default:\r
+ *(response-1) = ID_DAP_Invalid;\r
+ return (1);\r
+ }\r
+\r
+ return (1 + num);\r
+}\r
+\r
+\r
+// Setup DAP\r
+void DAP_Setup(void) {\r
+\r
+ // Default settings (only non-zero values)\r
+//DAP_Data.debug_port = 0;\r
+//DAP_Data.fast_clock = 0;\r
+ DAP_Data.clock_delay = CLOCK_DELAY(DAP_DEFAULT_SWJ_CLOCK);\r
+//DAP_Data.transfer.idle_cycles = 0;\r
+ DAP_Data.transfer.retry_count = 100;\r
+//DAP_Data.transfer.match_retry = 0;\r
+//DAP_Data.transfer.match_mask = 0x000000;\r
+#if (DAP_SWD != 0)\r
+ DAP_Data.swd_conf.turnaround = 1;\r
+//DAP_Data.swd_conf.data_phase = 0;\r
+#endif\r
+#if (DAP_JTAG != 0)\r
+//DAP_Data.jtag_dev.count = 0;\r
+#endif\r
+\r
+ DAP_SETUP(); // Device specific setup\r
+}\r
--- /dev/null
+/*
+===============================================================================
+ Name : IBDAP.c
+ Author : $(author)
+ Version :
+ Copyright : $(copyright)
+ Description : main definition
+===============================================================================
+*/
+
+#ifdef __USE_CMSIS
+#include "LPC11Uxx.h"
+#endif
+
+#include "DAP_config.h"
+
+#include "DAP.h"
+
+#include "usb_driver.h"
+
+
+
+#define TICKRATE_100msec (10)
+#define TICKRATE_10msec (100)
+#define TICKRATE_1msec (1000)
+
+#define TICKRATE TICKRATE_1msec
+
+// Connected LED RED PIN 21: PIO0_11
+#define LED_ERROR_PORT 0
+#define LED_ERROR_BIT 11
+#define IOCON_ERROR_REG (LPC_IOCON->TDI_PIO0_11)
+
+void indicator_code (int code);
+
+void init_error_led () {
+ IOCON_ERROR_REG = 1 | 1 << 4 | 1 << 7;
+ LPC_GPIO->DIR[LED_ERROR_PORT] |= 1 << LED_ERROR_BIT;
+ LPC_GPIO->SET[LED_ERROR_PORT] = 1 << LED_ERROR_BIT;
+}
+
+INLINE void LED_ERROR_ON () {
+ LPC_GPIO->CLR[LED_ERROR_PORT] = 1 << LED_ERROR_BIT;
+}
+
+INLINE void LED_ERROR_OFF () {
+ LPC_GPIO->SET[LED_ERROR_PORT] = 1 << LED_ERROR_BIT;
+}
+
+
+static volatile uint32_t sys_time = 0;
+
+
+void SysTick_Handler () {
+ sys_time++;
+}
+
+void sleep_ms (int ms) {
+
+ int e = sys_time * (1000/TICKRATE) + ms;
+ while ((sys_time * (1000/TICKRATE)) <= e) {
+ __WFI ();
+ }
+}
+
+// HID callbacks and buffer
+
+typedef struct _IBDAP_HND_T {
+ volatile uint8_t usb_outs_end_idx;
+ volatile uint8_t usb_outs_start_idx;
+ uint8_t usb_outs[DAP_PACKET_COUNT][DAP_PACKET_SIZE];
+ volatile uint8_t usb_ins_end_idx;
+ volatile uint8_t usb_ins_start_idx;
+ volatile uint8_t usb_ins_busy;
+ uint8_t usb_ins[DAP_PACKET_COUNT][DAP_PACKET_SIZE];
+}IBDAP_HND_T;
+
+IBDAP_HND_T* ibdap = 0;
+
+
+ErrorCode_t DAP_GetReport_Callback( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t* length) {
+ return LPC_OK;
+}
+
+ErrorCode_t DAP_SetReport_Callback( USBD_HANDLE_T hHid, USB_SETUP_PACKET* pSetup, uint8_t** pBuffer, uint16_t length) {
+ return LPC_OK;
+}
+
+ErrorCode_t DAP_EpInOut_Hdlr_Callback (USBD_HANDLE_T hUsb, void* data, uint32_t event) {
+ USB_HID_CTRL_T *pHidCtrl = (USB_HID_CTRL_T *) data;
+ switch (event) {
+ case USB_EVT_IN:
+ if (ibdap->usb_ins_start_idx == ibdap->usb_ins_end_idx) {
+ ibdap->usb_ins_busy = 0;
+ break;
+ }
+ USBD_API->hw->WriteEP(hUsb, pHidCtrl->epin_adr, ibdap->usb_ins[ibdap->usb_ins_start_idx], DAP_PACKET_SIZE);
+ ibdap->usb_ins_start_idx = (ibdap->usb_ins_start_idx+1) % DAP_PACKET_COUNT;
+ //LED_RUNNING_OUT (1);
+ //LED_CONNECTED_OUT (0);
+ break;
+ case USB_EVT_OUT:
+ USBD_API->hw->ReadEP(hUsb, pHidCtrl->epout_adr, ibdap->usb_outs[ibdap->usb_outs_end_idx]);
+ ibdap->usb_outs_end_idx = (ibdap->usb_outs_end_idx+1) % DAP_PACKET_COUNT;
+ //LED_CONNECTED_OUT (1);
+ //LED_RUNNING_OUT (0);
+ break;
+ }
+ return LPC_OK;
+}
+
+void suspend () {
+ while (1) {
+ LED_ERROR_ON ();
+ sleep_ms (1000);
+ LED_ERROR_OFF ();
+ sleep_ms (1000);
+ }
+}
+
+void error_code (int code) {
+ LED_ERROR_ON ();
+ while (1) {
+ if (code & 0x01 && !(code & 0x02 )) { // code == 1
+ LED_CONNECTED_OUT (1);
+ LED_RUNNING_OUT (0);
+ sleep_ms (1000);
+ LED_CONNECTED_OUT (0);
+ } else if (!(code & 0x01) && (code & 0x02)) { // code == 2
+ LED_CONNECTED_OUT (0);
+ LED_RUNNING_OUT (1);
+ sleep_ms (1000);
+ LED_RUNNING_OUT (0);
+ } else if ((code & 0x01) == 3) {
+ LED_CONNECTED_OUT (1);
+ LED_RUNNING_OUT (1);
+ sleep_ms (1000);
+ LED_CONNECTED_OUT (0);
+ LED_RUNNING_OUT (0);
+ } else {
+ LED_CONNECTED_OUT (1);
+ LED_RUNNING_OUT (0);
+ sleep_ms (1000);
+ LED_CONNECTED_OUT (0);
+ LED_RUNNING_OUT (1);
+ }
+
+ sleep_ms (1000);
+ }
+}
+
+void indicator_code (int code) {
+ LED_ERROR_OFF ();
+ while (1) {
+ if (code & 0x01 && !(code & 0x02 )) { // code == 1
+ LED_CONNECTED_OUT (1);
+ LED_RUNNING_OUT (0);
+ sleep_ms (1000);
+ LED_CONNECTED_OUT (0);
+ } else if (!(code & 0x01) && (code & 0x02)) { // code == 2
+ LED_CONNECTED_OUT (0);
+ LED_RUNNING_OUT (1);
+ sleep_ms (1000);
+ LED_RUNNING_OUT (0);
+ } else if ((code & 0x01) == 3) {
+ LED_CONNECTED_OUT (1);
+ LED_RUNNING_OUT (1);
+ sleep_ms (1000);
+ LED_CONNECTED_OUT (0);
+ LED_RUNNING_OUT (0);
+ } else {
+ LED_CONNECTED_OUT (1);
+ LED_RUNNING_OUT (0);
+ sleep_ms (1000);
+ LED_CONNECTED_OUT (0);
+ LED_RUNNING_OUT (1);
+ }
+
+ sleep_ms (1000);
+ }
+}
+// TODO: insert other definitions and declarations here
+
+void device_boot() {
+ LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 6; // enable gpio clock
+}
+
+int main(void) {
+
+ device_boot();
+
+ USBD_API_INIT_PARAM_T usb_param;
+
+ SysTick_Config(SystemCoreClock / TICKRATE);
+
+ init_error_led ();
+
+ DAP_Setup ();
+
+
+ init_usb_clock ();
+ init_usb_power ();
+ if (init_usb_driver (&usb_param)) {
+ // printf error;
+ // LED error;
+ suspend ();
+ return -1;
+ }
+
+ if (init_usb_hid (&usb_param,
+ &DAP_GetReport_Callback, &DAP_SetReport_Callback,
+ &DAP_EpInOut_Hdlr_Callback, &DAP_EpInOut_Hdlr_Callback,
+ (uint8_t**)&ibdap, sizeof (IBDAP_HND_T))) {
+ // printf error;
+ // LED error;
+ error_code (1);
+ return -1;
+ }
+
+ connect_to_usb_bus ();
+ //LED_ERROR_ON ();
+ while (1) {
+ /*
+ LED_ERROR_ON ();
+ sleep_ms (500);
+ LED_ERROR_OFF ();
+ sleep_ms (1000);
+ */
+ if (ibdap->usb_outs_start_idx == ibdap->usb_outs_end_idx) {
+ //LED_ERROR_ON ();
+ __WFI ();
+ continue;
+ } else {
+ LED_CONNECTED_OUT (1);
+ }
+ //LED_ERROR_OFF ();
+ DAP_ProcessCommand (ibdap->usb_outs[ibdap->usb_outs_start_idx], ibdap->usb_ins[ibdap->usb_ins_end_idx]);
+ ibdap->usb_outs_start_idx = (ibdap->usb_outs_start_idx+1) % DAP_PACKET_COUNT;
+ ibdap->usb_ins_end_idx = (ibdap->usb_ins_end_idx+1) % DAP_PACKET_COUNT;
+ if (!ibdap->usb_ins_busy) { // kickstart
+ ibdap->usb_ins_busy = 1;
+ uint8_t idx = ibdap->usb_ins_start_idx;
+ ibdap->usb_ins_start_idx = (ibdap->usb_ins_start_idx+1) % DAP_PACKET_COUNT;
+ USBD_API->hw->WriteEP(g_usb_hnd, HID_EP_IN, ibdap->usb_ins[idx], DAP_PACKET_SIZE);
+
+ //LED_RUNNING_OUT (1);
+ //LED_CONNECTED_OUT (0);
+ }
+
+ }
+}
--- /dev/null
+/******************************************************************************\r
+ * @file JTAG_DP.c\r
+ * @brief CMSIS-DAP JTAG DP I/O\r
+ * @version V1.00\r
+ * @date 31. May 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include "DAP_config.h"\r
+#include "DAP.h"\r
+\r
+\r
+// JTAG Macros\r
+\r
+#define PIN_TCK_SET PIN_SWCLK_TCK_SET\r
+#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR\r
+#define PIN_TMS_SET PIN_SWDIO_TMS_SET\r
+#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR\r
+\r
+#define JTAG_CYCLE_TCK() \\r
+ PIN_TCK_CLR(); \\r
+ PIN_DELAY(); \\r
+ PIN_TCK_SET(); \\r
+ PIN_DELAY()\r
+\r
+#define JTAG_CYCLE_TDI(tdi) \\r
+ PIN_TDI_OUT(tdi); \\r
+ PIN_TCK_CLR(); \\r
+ PIN_DELAY(); \\r
+ PIN_TCK_SET(); \\r
+ PIN_DELAY()\r
+\r
+#define JTAG_CYCLE_TDO(tdo) \\r
+ PIN_TCK_CLR(); \\r
+ PIN_DELAY(); \\r
+ tdo = PIN_TDO_IN(); \\r
+ PIN_TCK_SET(); \\r
+ PIN_DELAY()\r
+\r
+#define JTAG_CYCLE_TDIO(tdi,tdo) \\r
+ PIN_TDI_OUT(tdi); \\r
+ PIN_TCK_CLR(); \\r
+ PIN_DELAY(); \\r
+ tdo = PIN_TDO_IN(); \\r
+ PIN_TCK_SET(); \\r
+ PIN_DELAY()\r
+\r
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)\r
+\r
+\r
+#if (DAP_JTAG != 0)\r
+\r
+\r
+// Generate JTAG Sequence\r
+// info: sequence information\r
+// tdi: pointer to TDI generated data\r
+// tdo: pointer to TDO captured data\r
+// return: none\r
+void JTAG_Sequence (uint32_t info, uint8_t *tdi, uint8_t *tdo) {\r
+ uint32_t i_val;\r
+ uint32_t o_val;\r
+ uint32_t bit;\r
+ uint32_t n, k;\r
+\r
+ n = info & JTAG_SEQUENCE_TCK;\r
+ if (n == 0) n = 64;\r
+\r
+ if (info & JTAG_SEQUENCE_TMS) {\r
+ PIN_TMS_SET();\r
+ } else {\r
+ PIN_TMS_CLR();\r
+ }\r
+\r
+ while (n) {\r
+ i_val = *tdi++;\r
+ o_val = 0;\r
+ for (k = 8; k && n; k--, n--) {\r
+ JTAG_CYCLE_TDIO(i_val, bit);\r
+ i_val >>= 1;\r
+ o_val >>= 1;\r
+ o_val |= bit << 7;\r
+ }\r
+ o_val >>= k;\r
+ if (info & JTAG_SEQUENCE_TDO) {\r
+ *tdo++ = o_val;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+// JTAG Set IR\r
+// ir: IR value\r
+// return: none\r
+#define JTAG_IR_Function(speed) /**/ \\r
+void JTAG_IR_##speed (uint32_t ir) { \\r
+ uint32_t n; \\r
+ \\r
+ PIN_TMS_SET(); \\r
+ JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \\r
+ JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \\r
+ PIN_TMS_CLR(); \\r
+ JTAG_CYCLE_TCK(); /* Capture-IR */ \\r
+ JTAG_CYCLE_TCK(); /* Shift-IR */ \\r
+ \\r
+ PIN_TDI_OUT(1); \\r
+ for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \\r
+ JTAG_CYCLE_TCK(); /* Bypass before data */ \\r
+ } \\r
+ for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1; n; n--) { \\r
+ JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \\r
+ ir >>= 1; \\r
+ } \\r
+ n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \\r
+ if (n) { \\r
+ JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \\r
+ PIN_TDI_OUT(1); \\r
+ for (--n; n; n--) { \\r
+ JTAG_CYCLE_TCK(); /* Bypass after data */ \\r
+ } \\r
+ PIN_TMS_SET(); \\r
+ JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \\r
+ } else { \\r
+ PIN_TMS_SET(); \\r
+ JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \\r
+ } \\r
+ \\r
+ JTAG_CYCLE_TCK(); /* Update-IR */ \\r
+ PIN_TMS_CLR(); \\r
+ JTAG_CYCLE_TCK(); /* Idle */ \\r
+ PIN_TDI_OUT(1); \\r
+}\r
+\r
+\r
+// JTAG Transfer I/O\r
+// request: A[3:2] RnW APnDP\r
+// data: DATA[31:0]\r
+// return: ACK[2:0]\r
+#define JTAG_TransferFunction(speed) /**/ \\r
+uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \\r
+ uint32_t ack; \\r
+ uint32_t bit; \\r
+ uint32_t val; \\r
+ uint32_t n; \\r
+ \\r
+ PIN_TMS_SET(); \\r
+ JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \\r
+ PIN_TMS_CLR(); \\r
+ JTAG_CYCLE_TCK(); /* Capture-DR */ \\r
+ JTAG_CYCLE_TCK(); /* Shift-DR */ \\r
+ \\r
+ for (n = DAP_Data.jtag_dev.index; n; n--) { \\r
+ JTAG_CYCLE_TCK(); /* Bypass before data */ \\r
+ } \\r
+ \\r
+ JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \\r
+ ack = bit << 1; \\r
+ JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \\r
+ ack |= bit << 0; \\r
+ JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \\r
+ ack |= bit << 2; \\r
+ \\r
+ if (ack != DAP_TRANSFER_OK) { \\r
+ /* Exit on error */ \\r
+ PIN_TMS_SET(); \\r
+ JTAG_CYCLE_TCK(); /* Exit1-DR */ \\r
+ goto exit; \\r
+ } \\r
+ \\r
+ if (request & DAP_TRANSFER_RnW) { \\r
+ /* Read Transfer */ \\r
+ val = 0; \\r
+ for (n = 31; n; n--) { \\r
+ JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \\r
+ val |= bit << 31; \\r
+ val >>= 1; \\r
+ } \\r
+ n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1; \\r
+ if (n) { \\r
+ JTAG_CYCLE_TDO(bit); /* Get D31 */ \\r
+ for (--n; n; n--) { \\r
+ JTAG_CYCLE_TCK(); /* Bypass after data */ \\r
+ } \\r
+ PIN_TMS_SET(); \\r
+ JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \\r
+ } else { \\r
+ PIN_TMS_SET(); \\r
+ JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \\r
+ } \\r
+ val |= bit << 31; \\r
+ if (data) *data = val; \\r
+ } else { \\r
+ /* Write Transfer */ \\r
+ val = *data; \\r
+ for (n = 31; n; n--) { \\r
+ JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \\r
+ val >>= 1; \\r
+ } \\r
+ n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1; \\r
+ if (n) { \\r
+ JTAG_CYCLE_TDI(val); /* Set D31 */ \\r
+ for (--n; n; n--) { \\r
+ JTAG_CYCLE_TCK(); /* Bypass after data */ \\r
+ } \\r
+ PIN_TMS_SET(); \\r
+ JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \\r
+ } else { \\r
+ PIN_TMS_SET(); \\r
+ JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \\r
+ } \\r
+ } \\r
+ \\r
+exit: \\r
+ JTAG_CYCLE_TCK(); /* Update-DR */ \\r
+ PIN_TMS_CLR(); \\r
+ JTAG_CYCLE_TCK(); /* Idle */ \\r
+ PIN_TDI_OUT(1); \\r
+ \\r
+ /* Idle cycles */ \\r
+ n = DAP_Data.transfer.idle_cycles; \\r
+ while (n--) { \\r
+ JTAG_CYCLE_TCK(); /* Idle */ \\r
+ } \\r
+ \\r
+ return (ack); \\r
+}\r
+\r
+\r
+#undef PIN_DELAY\r
+#define PIN_DELAY() PIN_DELAY_FAST()\r
+JTAG_IR_Function(Fast);\r
+JTAG_TransferFunction(Fast);\r
+\r
+#undef PIN_DELAY\r
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)\r
+JTAG_IR_Function(Slow);\r
+JTAG_TransferFunction(Slow);\r
+\r
+\r
+// JTAG Read IDCODE register\r
+// return: value read\r
+uint32_t JTAG_ReadIDCode (void) {\r
+ uint32_t bit;\r
+ uint32_t val;\r
+ uint32_t n;\r
+\r
+ PIN_TMS_SET();\r
+ JTAG_CYCLE_TCK(); /* Select-DR-Scan */\r
+ PIN_TMS_CLR();\r
+ JTAG_CYCLE_TCK(); /* Capture-DR */\r
+ JTAG_CYCLE_TCK(); /* Shift-DR */\r
+\r
+ for (n = DAP_Data.jtag_dev.index; n; n--) {\r
+ JTAG_CYCLE_TCK(); /* Bypass before data */\r
+ }\r
+\r
+ val = 0;\r
+ for (n = 31; n; n--) {\r
+ JTAG_CYCLE_TDO(bit); /* Get D0..D30 */\r
+ val |= bit << 31;\r
+ val >>= 1;\r
+ }\r
+ PIN_TMS_SET();\r
+ JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */\r
+ val |= bit << 31;\r
+\r
+ JTAG_CYCLE_TCK(); /* Update-DR */\r
+ PIN_TMS_CLR();\r
+ JTAG_CYCLE_TCK(); /* Idle */\r
+\r
+ return (val);\r
+}\r
+\r
+\r
+// JTAG Write ABORT register\r
+// data: value to write\r
+// return: none\r
+void JTAG_WriteAbort (uint32_t data) {\r
+ uint32_t n;\r
+\r
+ PIN_TMS_SET();\r
+ JTAG_CYCLE_TCK(); /* Select-DR-Scan */\r
+ PIN_TMS_CLR();\r
+ JTAG_CYCLE_TCK(); /* Capture-DR */\r
+ JTAG_CYCLE_TCK(); /* Shift-DR */\r
+\r
+ for (n = DAP_Data.jtag_dev.index; n; n--) {\r
+ JTAG_CYCLE_TCK(); /* Bypass before data */\r
+ }\r
+\r
+ PIN_TDI_OUT(0);\r
+ JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */\r
+ JTAG_CYCLE_TCK(); /* Set A2=0 */\r
+ JTAG_CYCLE_TCK(); /* Set A3=0 */\r
+\r
+ for (n = 31; n; n--) {\r
+ JTAG_CYCLE_TDI(data); /* Set D0..D30 */\r
+ data >>= 1;\r
+ }\r
+ n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1;\r
+ if (n) {\r
+ JTAG_CYCLE_TDI(data); /* Set D31 */\r
+ for (--n; n; n--) {\r
+ JTAG_CYCLE_TCK(); /* Bypass after data */\r
+ }\r
+ PIN_TMS_SET();\r
+ JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */\r
+ } else {\r
+ PIN_TMS_SET();\r
+ JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */\r
+ }\r
+\r
+ JTAG_CYCLE_TCK(); /* Update-DR */\r
+ PIN_TMS_CLR();\r
+ JTAG_CYCLE_TCK(); /* Idle */\r
+ PIN_TDI_OUT(1);\r
+}\r
+\r
+\r
+// JTAG Set IR\r
+// ir: IR value\r
+// return: none\r
+void JTAG_IR (uint32_t ir) {\r
+ if (DAP_Data.fast_clock) {\r
+ JTAG_IR_Fast(ir);\r
+ } else {\r
+ JTAG_IR_Slow(ir);\r
+ }\r
+}\r
+\r
+\r
+// JTAG Transfer I/O\r
+// request: A[3:2] RnW APnDP\r
+// data: DATA[31:0]\r
+// return: ACK[2:0]\r
+uint8_t JTAG_Transfer(uint32_t request, uint32_t *data) {\r
+ if (DAP_Data.fast_clock) {\r
+ return JTAG_TransferFast(request, data);\r
+ } else {\r
+ return JTAG_TransferSlow(request, data);\r
+ }\r
+}\r
+\r
+\r
+#endif /* (DAP_JTAG != 0) */\r
--- /dev/null
+/******************************************************************************\r
+ * @file SW_DP.c\r
+ * @brief CMSIS-DAP SW DP I/O\r
+ * @version V1.00\r
+ * @date 31. May 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include "DAP_config.h"\r
+#include "DAP.h"\r
+\r
+\r
+// SW Macros\r
+\r
+#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET\r
+#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR\r
+\r
+#define SW_CLOCK_CYCLE() \\r
+ PIN_SWCLK_CLR(); \\r
+ PIN_DELAY(); \\r
+ PIN_SWCLK_SET(); \\r
+ PIN_DELAY()\r
+\r
+#define SW_WRITE_BIT(bit) \\r
+ PIN_SWDIO_OUT(bit); \\r
+ PIN_SWCLK_CLR(); \\r
+ PIN_DELAY(); \\r
+ PIN_SWCLK_SET(); \\r
+ PIN_DELAY()\r
+\r
+#define SW_READ_BIT(bit) \\r
+ PIN_SWCLK_CLR(); \\r
+ PIN_DELAY(); \\r
+ bit = PIN_SWDIO_IN(); \\r
+ PIN_SWCLK_SET(); \\r
+ PIN_DELAY()\r
+\r
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)\r
+\r
+\r
+// Generate SWJ Sequence\r
+// count: sequence bit count\r
+// data: pointer to sequence bit data\r
+// return: none\r
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))\r
+void SWJ_Sequence (uint32_t count, uint8_t *data) {\r
+ uint32_t val;\r
+ uint32_t n;\r
+\r
+ val = 0;\r
+ n = 0;\r
+ while (count--) {\r
+ if (n == 0) {\r
+ val = *data++;\r
+ n = 8;\r
+ }\r
+ if (val & 1) {\r
+ PIN_SWDIO_TMS_SET();\r
+ } else {\r
+ PIN_SWDIO_TMS_CLR();\r
+ }\r
+ SW_CLOCK_CYCLE();\r
+ val >>= 1;\r
+ n--;\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+#if (DAP_SWD != 0)\r
+\r
+\r
+// SWD Transfer I/O\r
+// request: A[3:2] RnW APnDP\r
+// data: DATA[31:0]\r
+// return: ACK[2:0]\r
+#define SWD_TransferFunction(speed) /**/ \\r
+uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) { \\r
+ uint32_t ack; \\r
+ uint32_t bit; \\r
+ uint32_t val; \\r
+ uint32_t parity; \\r
+ \\r
+ uint32_t n; \\r
+ \\r
+ /* Packet Request */ \\r
+ parity = 0; \\r
+ SW_WRITE_BIT(1); /* Start Bit */ \\r
+ bit = request >> 0; \\r
+ SW_WRITE_BIT(bit); /* APnDP Bit */ \\r
+ parity += bit; \\r
+ bit = request >> 1; \\r
+ SW_WRITE_BIT(bit); /* RnW Bit */ \\r
+ parity += bit; \\r
+ bit = request >> 2; \\r
+ SW_WRITE_BIT(bit); /* A2 Bit */ \\r
+ parity += bit; \\r
+ bit = request >> 3; \\r
+ SW_WRITE_BIT(bit); /* A3 Bit */ \\r
+ parity += bit; \\r
+ SW_WRITE_BIT(parity); /* Parity Bit */ \\r
+ SW_WRITE_BIT(0); /* Stop Bit */ \\r
+ SW_WRITE_BIT(1); /* Park Bit */ \\r
+ \\r
+ /* Turnaround */ \\r
+ PIN_SWDIO_OUT_DISABLE(); \\r
+ for (n = DAP_Data.swd_conf.turnaround; n; n--) { \\r
+ SW_CLOCK_CYCLE(); \\r
+ } \\r
+ \\r
+ /* Acknowledge response */ \\r
+ SW_READ_BIT(bit); \\r
+ ack = bit << 0; \\r
+ SW_READ_BIT(bit); \\r
+ ack |= bit << 1; \\r
+ SW_READ_BIT(bit); \\r
+ ack |= bit << 2; \\r
+ \\r
+ if (ack == DAP_TRANSFER_OK) { /* OK response */ \\r
+ /* Data transfer */ \\r
+ if (request & DAP_TRANSFER_RnW) { \\r
+ /* Read data */ \\r
+ val = 0; \\r
+ parity = 0; \\r
+ for (n = 32; n; n--) { \\r
+ SW_READ_BIT(bit); /* Read RDATA[0:31] */ \\r
+ parity += bit; \\r
+ val >>= 1; \\r
+ val |= bit << 31; \\r
+ } \\r
+ SW_READ_BIT(bit); /* Read Parity */ \\r
+ if ((parity ^ bit) & 1) { \\r
+ ack = DAP_TRANSFER_ERROR; \\r
+ } \\r
+ if (data) *data = val; \\r
+ /* Turnaround */ \\r
+ for (n = DAP_Data.swd_conf.turnaround; n; n--) { \\r
+ SW_CLOCK_CYCLE(); \\r
+ } \\r
+ PIN_SWDIO_OUT_ENABLE(); \\r
+ } else { \\r
+ /* Turnaround */ \\r
+ for (n = DAP_Data.swd_conf.turnaround; n; n--) { \\r
+ SW_CLOCK_CYCLE(); \\r
+ } \\r
+ PIN_SWDIO_OUT_ENABLE(); \\r
+ /* Write data */ \\r
+ val = *data; \\r
+ parity = 0; \\r
+ for (n = 32; n; n--) { \\r
+ SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \\r
+ parity += val; \\r
+ val >>= 1; \\r
+ } \\r
+ SW_WRITE_BIT(parity); /* Write Parity Bit */ \\r
+ } \\r
+ /* Idle cycles */ \\r
+ n = DAP_Data.transfer.idle_cycles; \\r
+ if (n) { \\r
+ PIN_SWDIO_OUT(0); \\r
+ for (; n; n--) { \\r
+ SW_CLOCK_CYCLE(); \\r
+ } \\r
+ } \\r
+ PIN_SWDIO_OUT(1); \\r
+ return (ack); \\r
+ } \\r
+ \\r
+ if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { \\r
+ /* WAIT or FAULT response */ \\r
+ if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0)) { \\r
+ for (n = 32+1; n; n--) { \\r
+ SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \\r
+ } \\r
+ } \\r
+ /* Turnaround */ \\r
+ for (n = DAP_Data.swd_conf.turnaround; n; n--) { \\r
+ SW_CLOCK_CYCLE(); \\r
+ } \\r
+ PIN_SWDIO_OUT_ENABLE(); \\r
+ if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0)) { \\r
+ PIN_SWDIO_OUT(0); \\r
+ for (n = 32+1; n; n--) { \\r
+ SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \\r
+ } \\r
+ } \\r
+ PIN_SWDIO_OUT(1); \\r
+ return (ack); \\r
+ } \\r
+ \\r
+ /* Protocol error */ \\r
+ for (n = DAP_Data.swd_conf.turnaround + 32 + 1; n; n--) { \\r
+ SW_CLOCK_CYCLE(); /* Back off data phase */ \\r
+ } \\r
+ PIN_SWDIO_OUT(1); \\r
+ return (ack); \\r
+}\r
+\r
+\r
+#undef PIN_DELAY\r
+#define PIN_DELAY() PIN_DELAY_FAST()\r
+SWD_TransferFunction(Fast);\r
+\r
+#undef PIN_DELAY\r
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)\r
+SWD_TransferFunction(Slow);\r
+\r
+\r
+// SWD Transfer I/O\r
+// request: A[3:2] RnW APnDP\r
+// data: DATA[31:0]\r
+// return: ACK[2:0]\r
+uint8_t SWD_Transfer(uint32_t request, uint32_t *data) {\r
+ if (DAP_Data.fast_clock) {\r
+ return SWD_TransferFast(request, data);\r
+ } else {\r
+ return SWD_TransferSlow(request, data);\r
+ }\r
+}\r
+\r
+\r
+#endif /* (DAP_SWD != 0) */\r
--- /dev/null
+//*****************************************************************************\r
+// LPC11Uxx Microcontroller Startup code for use with LPCXpresso IDE\r
+//\r
+// Version : 141204\r
+//*****************************************************************************\r
+//\r
+// Copyright(C) NXP Semiconductors, 2013-2014\r
+// All rights reserved.\r
+//\r
+// Software that is described herein is for illustrative purposes only\r
+// which provides customers with programming information regarding the\r
+// LPC products. This software is supplied "AS IS" without any warranties of\r
+// any kind, and NXP Semiconductors and its licensor disclaim any and\r
+// all warranties, express or implied, including all implied warranties of\r
+// merchantability, fitness for a particular purpose and non-infringement of\r
+// intellectual property rights. NXP Semiconductors assumes no responsibility\r
+// or liability for the use of the software, conveys no license or rights under any\r
+// patent, copyright, mask work right, or any other intellectual property rights in\r
+// or to any products. NXP Semiconductors reserves the right to make changes\r
+// in the software without notification. NXP Semiconductors also makes no\r
+// representation or warranty that such application will be suitable for the\r
+// specified use without further testing or modification.\r
+//\r
+// Permission to use, copy, modify, and distribute this software and its\r
+// documentation is hereby granted, under NXP Semiconductors' and its\r
+// licensor's relevant copyrights in the software, without fee, provided that it\r
+// is used in conjunction with NXP Semiconductors microcontrollers. This\r
+// copyright, permission, and disclaimer notice must appear in all copies of\r
+// this code.\r
+//*****************************************************************************\r
+\r
+#if defined (__cplusplus)\r
+#ifdef __REDLIB__\r
+#error Redlib does not support C++\r
+#else\r
+//*****************************************************************************\r
+//\r
+// The entry point for the C++ library startup\r
+//\r
+//*****************************************************************************\r
+extern "C" {\r
+ extern void __libc_init_array(void);\r
+}\r
+#endif\r
+#endif\r
+\r
+#define WEAK __attribute__ ((weak))\r
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))\r
+\r
+//*****************************************************************************\r
+#if defined (__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+//*****************************************************************************\r
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)\r
+// Declaration of external SystemInit function\r
+extern void SystemInit(void);\r
+#endif\r
+\r
+// Patch the AEABI integer divide functions to use MCU's romdivide library\r
+#ifdef __USE_ROMDIVIDE\r
+// Location in memory that holds the address of the ROM Driver table\r
+#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x1FFF1FF8))\r
+// Variables to store addresses of idiv and udiv functions within MCU ROM\r
+unsigned int *pDivRom_idiv;\r
+unsigned int *pDivRom_uidiv;\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default handlers. These are aliased.\r
+// When the application defines a handler (with the same name), this will \r
+// automatically take precedence over these weak definitions\r
+//\r
+//*****************************************************************************\r
+ void ResetISR(void);\r
+WEAK void NMI_Handler(void);\r
+WEAK void HardFault_Handler(void);\r
+WEAK void SVC_Handler(void);\r
+WEAK void PendSV_Handler(void);\r
+WEAK void SysTick_Handler(void);\r
+WEAK void IntDefaultHandler(void);\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the specific IRQ handlers. These are aliased\r
+// to the IntDefaultHandler, which is a 'forever' loop. When the application\r
+// defines a handler (with the same name), this will automatically take\r
+// precedence over these weak definitions\r
+//\r
+//*****************************************************************************\r
+void FLEX_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void FLEX_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void FLEX_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void FLEX_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void FLEX_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void FLEX_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void FLEX_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void FLEX_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void I2C_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void UART_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void USB_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void USB_FIQHandler (void) ALIAS(IntDefaultHandler);\r
+void ADC_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void WDT_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void BOD_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);\r
+\r
+//*****************************************************************************\r
+// The entry point for the application.\r
+// __main() is the entry point for redlib based applications\r
+// main() is the entry point for newlib based applications\r
+//*****************************************************************************\r
+#if defined (__REDLIB__)\r
+extern void __main(void);\r
+#else\r
+extern int main(void);\r
+#endif\r
+//*****************************************************************************\r
+//\r
+// External declaration for the pointer to the stack top from the Linker Script\r
+//\r
+//*****************************************************************************\r
+extern void _vStackTop(void);\r
+\r
+//*****************************************************************************\r
+#if defined (__cplusplus)\r
+} // extern "C"\r
+#endif\r
+//*****************************************************************************\r
+//\r
+// The vector table. Note that the proper constructs must be placed on this to\r
+// ensure that it ends up at physical address 0x0000.0000.\r
+//\r
+//*****************************************************************************\r
+extern void (* const g_pfnVectors[])(void);\r
+__attribute__ ((section(".isr_vector")))\r
+void (* const g_pfnVectors[])(void) = {\r
+ &_vStackTop, // The initial stack pointer\r
+ ResetISR, // The reset handler\r
+ NMI_Handler, // The NMI handler\r
+ HardFault_Handler, // The hard fault handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ SVC_Handler, // SVCall handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ PendSV_Handler, // The PendSV handler\r
+ SysTick_Handler, // The SysTick handler\r
+\r
+ // LPC11U specific handlers\r
+ FLEX_INT0_IRQHandler, // 0 - GPIO pin interrupt 0\r
+ FLEX_INT1_IRQHandler, // 1 - GPIO pin interrupt 1\r
+ FLEX_INT2_IRQHandler, // 2 - GPIO pin interrupt 2\r
+ FLEX_INT3_IRQHandler, // 3 - GPIO pin interrupt 3\r
+ FLEX_INT4_IRQHandler, // 4 - GPIO pin interrupt 4\r
+ FLEX_INT5_IRQHandler, // 5 - GPIO pin interrupt 5\r
+ FLEX_INT6_IRQHandler, // 6 - GPIO pin interrupt 6\r
+ FLEX_INT7_IRQHandler, // 7 - GPIO pin interrupt 7\r
+ GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt\r
+ GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt\r
+ 0, // 10 - Reserved\r
+ 0, // 11 - Reserved\r
+ 0, // 12 - Reserved\r
+ 0, // 13 - Reserved\r
+ SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt\r
+ I2C_IRQHandler, // 15 - I2C0\r
+ TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)\r
+ TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)\r
+ TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)\r
+ TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)\r
+ SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt\r
+ UART_IRQHandler, // 21 - UART0\r
+ USB_IRQHandler, // 22 - USB IRQ\r
+ USB_FIQHandler, // 23 - USB FIQ\r
+ ADC_IRQHandler, // 24 - ADC (A/D Converter)\r
+ WDT_IRQHandler, // 25 - WDT (Watchdog Timer)\r
+ BOD_IRQHandler, // 26 - BOD (Brownout Detect)\r
+ FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller\r
+ 0, // 28 - Reserved\r
+ 0, // 29 - Reserved\r
+ USBWakeup_IRQHandler, // 30 - USB wake-up interrupt\r
+ 0, // 31 - Reserved\r
+};\r
+\r
+//*****************************************************************************\r
+// Functions to carry out the initialization of RW and BSS data sections. These\r
+// are written as separate functions rather than being inlined within the\r
+// ResetISR() function in order to cope with MCUs with multiple banks of\r
+// memory.\r
+//*****************************************************************************\r
+__attribute__ ((section(".after_vectors")))\r
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {\r
+ unsigned int *pulDest = (unsigned int*) start;\r
+ unsigned int *pulSrc = (unsigned int*) romstart;\r
+ unsigned int loop;\r
+ for (loop = 0; loop < len; loop = loop + 4)\r
+ *pulDest++ = *pulSrc++;\r
+}\r
+\r
+__attribute__ ((section(".after_vectors")))\r
+void bss_init(unsigned int start, unsigned int len) {\r
+ unsigned int *pulDest = (unsigned int*) start;\r
+ unsigned int loop;\r
+ for (loop = 0; loop < len; loop = loop + 4)\r
+ *pulDest++ = 0;\r
+}\r
+\r
+//*****************************************************************************\r
+// The following symbols are constructs generated by the linker, indicating\r
+// the location of various points in the "Global Section Table". This table is\r
+// created by the linker via the Code Red managed linker script mechanism. It\r
+// contains the load address, execution address and length of each RW data\r
+// section and the execution and length of each BSS (zero initialized) section.\r
+//*****************************************************************************\r
+extern unsigned int __data_section_table;\r
+extern unsigned int __data_section_table_end;\r
+extern unsigned int __bss_section_table;\r
+extern unsigned int __bss_section_table_end;\r
+\r
+//*****************************************************************************\r
+// Reset entry point for your code.\r
+// Sets up a simple runtime environment and initializes the C/C++\r
+// library.\r
+//*****************************************************************************\r
+__attribute__ ((section(".after_vectors")))\r
+void\r
+ResetISR(void) {\r
+\r
+\r
+\r
+ //\r
+ // Copy the data sections from flash to SRAM.\r
+ //\r
+ unsigned int LoadAddr, ExeAddr, SectionLen;\r
+ unsigned int *SectionTableAddr;\r
+\r
+ // Load base address of Global Section Table\r
+ SectionTableAddr = &__data_section_table;\r
+\r
+ // Copy the data sections from flash to SRAM.\r
+ while (SectionTableAddr < &__data_section_table_end) {\r
+ LoadAddr = *SectionTableAddr++;\r
+ ExeAddr = *SectionTableAddr++;\r
+ SectionLen = *SectionTableAddr++;\r
+ data_init(LoadAddr, ExeAddr, SectionLen);\r
+ }\r
+ // At this point, SectionTableAddr = &__bss_section_table;\r
+ // Zero fill the bss segment\r
+ while (SectionTableAddr < &__bss_section_table_end) {\r
+ ExeAddr = *SectionTableAddr++;\r
+ SectionLen = *SectionTableAddr++;\r
+ bss_init(ExeAddr, SectionLen);\r
+ }\r
+\r
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)\r
+ SystemInit();\r
+#endif\r
+\r
+#if defined (__cplusplus)\r
+ //\r
+ // Call C++ library initialisation\r
+ //\r
+ __libc_init_array();\r
+#endif\r
+\r
+#if defined (__REDLIB__)\r
+ // Call the Redlib library, which in turn calls main()\r
+ __main() ;\r
+#else\r
+ main();\r
+#endif\r
+ //\r
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop\r
+ //\r
+ while (1) {\r
+ ;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+// Default exception handlers. Override the ones here by defining your own\r
+// handler routines in your application code.\r
+//*****************************************************************************\r
+__attribute__ ((section(".after_vectors")))\r
+void NMI_Handler(void)\r
+{\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+__attribute__ ((section(".after_vectors")))\r
+void HardFault_Handler(void)\r
+{\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+__attribute__ ((section(".after_vectors")))\r
+void SVC_Handler(void)\r
+{\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+__attribute__ ((section(".after_vectors")))\r
+void PendSV_Handler(void)\r
+{\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+__attribute__ ((section(".after_vectors")))\r
+void SysTick_Handler(void)\r
+{\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Processor ends up here if an unexpected interrupt occurs or a specific\r
+// handler is not present in the application code.\r
+//\r
+//*****************************************************************************\r
+__attribute__ ((section(".after_vectors")))\r
+void IntDefaultHandler(void)\r
+{\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
--- /dev/null
+//*****************************************************************************\r
+// crp.c\r
+//\r
+// Source file to create CRP word expected by LPCXpresso IDE linker\r
+//*****************************************************************************\r
+//\r
+// Copyright(C) NXP Semiconductors, 2013\r
+// All rights reserved.\r
+//\r
+// Software that is described herein is for illustrative purposes only\r
+// which provides customers with programming information regarding the\r
+// LPC products. This software is supplied "AS IS" without any warranties of\r
+// any kind, and NXP Semiconductors and its licensor disclaim any and\r
+// all warranties, express or implied, including all implied warranties of\r
+// merchantability, fitness for a particular purpose and non-infringement of\r
+// intellectual property rights. NXP Semiconductors assumes no responsibility\r
+// or liability for the use of the software, conveys no license or rights under any\r
+// patent, copyright, mask work right, or any other intellectual property rights in\r
+// or to any products. NXP Semiconductors reserves the right to make changes\r
+// in the software without notification. NXP Semiconductors also makes no\r
+// representation or warranty that such application will be suitable for the\r
+// specified use without further testing or modification.\r
+//\r
+// Permission to use, copy, modify, and distribute this software and its\r
+// documentation is hereby granted, under NXP Semiconductors' and its\r
+// licensor's relevant copyrights in the software, without fee, provided that it\r
+// is used in conjunction with NXP Semiconductors microcontrollers. This\r
+// copyright, permission, and disclaimer notice must appear in all copies of\r
+// this code.\r
+//*****************************************************************************\r
+\r
+#if defined (__CODE_RED)\r
+#include <NXP/crp.h>\r
+// Variable to store CRP value in. Will be placed automatically\r
+// by the linker when "Enable Code Read Protect" selected.\r
+// See crp.h header for more information\r
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_LPC11Uxx.c\r
+ * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File\r
+ * for the NXP LPC13xx Device Series\r
+ * @version V1.10\r
+ * @date 24. November 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#include <stdint.h>\r
+#include "LPC11Uxx.h"\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+/*--------------------- Clock Configuration ----------------------------------\r
+//\r
+// <e> Clock Configuration\r
+// <h> System Oscillator Control Register (SYSOSCCTRL)\r
+// <o1.0> BYPASS: System Oscillator Bypass Enable\r
+// <i> If enabled then PLL input (sys_osc_clk) is fed\r
+// <i> directly from XTALIN and XTALOUT pins.\r
+// <o1.9> FREQRANGE: System Oscillator Frequency Range\r
+// <i> Determines frequency range for Low-power oscillator.\r
+// <0=> 1 - 20 MHz\r
+// <1=> 15 - 25 MHz\r
+// </h>\r
+//\r
+// <h> Watchdog Oscillator Control Register (WDTOSCCTRL)\r
+// <o2.0..4> DIVSEL: Select Divider for Fclkana\r
+// <i> wdt_osc_clk = Fclkana/ (2 � (1 + DIVSEL))\r
+// <0-31>\r
+// <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)\r
+// <0=> Undefined\r
+// <1=> 0.5 MHz\r
+// <2=> 0.8 MHz\r
+// <3=> 1.1 MHz\r
+// <4=> 1.4 MHz\r
+// <5=> 1.6 MHz\r
+// <6=> 1.8 MHz\r
+// <7=> 2.0 MHz\r
+// <8=> 2.2 MHz\r
+// <9=> 2.4 MHz\r
+// <10=> 2.6 MHz\r
+// <11=> 2.7 MHz\r
+// <12=> 2.9 MHz\r
+// <13=> 3.1 MHz\r
+// <14=> 3.2 MHz\r
+// <15=> 3.4 MHz\r
+// </h>\r
+//\r
+// <h> System PLL Control Register (SYSPLLCTRL)\r
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)\r
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz\r
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz\r
+// <o3.0..4> MSEL: Feedback Divider Selection\r
+// <i> M = MSEL + 1\r
+// <0-31>\r
+// <o3.5..6> PSEL: Post Divider Selection\r
+// <0=> P = 1\r
+// <1=> P = 2\r
+// <2=> P = 4\r
+// <3=> P = 8\r
+// </h>\r
+//\r
+// <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)\r
+// <o4.0..1> SEL: System PLL Clock Source\r
+// <0=> IRC Oscillator\r
+// <1=> System Oscillator\r
+// <2=> Reserved\r
+// <3=> Reserved\r
+// </h>\r
+//\r
+// <h> Main Clock Source Select Register (MAINCLKSEL)\r
+// <o5.0..1> SEL: Clock Source for Main Clock\r
+// <0=> IRC Oscillator\r
+// <1=> Input Clock to System PLL\r
+// <2=> WDT Oscillator\r
+// <3=> System PLL Clock Out\r
+// </h>\r
+//\r
+// <h> System AHB Clock Divider Register (SYSAHBCLKDIV)\r
+// <o6.0..7> DIV: System AHB Clock Divider\r
+// <i> Divides main clock to provide system clock to core, memories, and peripherals.\r
+// <i> 0 = is disabled\r
+// <0-255>\r
+// </h>\r
+//\r
+// <h> USB PLL Control Register (USBPLLCTRL)\r
+// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)\r
+// <i> F_clkin must be in the range of 10 MHz to 25 MHz\r
+// <i> F_CCO must be in the range of 156 MHz to 320 MHz\r
+// <o7.0..4> MSEL: Feedback Divider Selection\r
+// <i> M = MSEL + 1\r
+// <0-31>\r
+// <o7.5..6> PSEL: Post Divider Selection\r
+// <0=> P = 1\r
+// <1=> P = 2\r
+// <2=> P = 4\r
+// <3=> P = 8\r
+// </h>\r
+//\r
+// <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)\r
+// <o8.0..1> SEL: USB PLL Clock Source\r
+// <i> USB PLL clock source must be switched to System Oscillator for correct USB operation\r
+// <0=> IRC Oscillator\r
+// <1=> System Oscillator\r
+// <2=> Reserved\r
+// <3=> Reserved\r
+// </h>\r
+//\r
+// <h> USB Clock Source Select Register (USBCLKSEL)\r
+// <o9.0..1> SEL: System PLL Clock Source\r
+// <0=> USB PLL out\r
+// <1=> Main clock\r
+// <2=> Reserved\r
+// <3=> Reserved\r
+// </h>\r
+//\r
+// <h> USB Clock Divider Register (USBCLKDIV)\r
+// <o10.0..7> DIV: USB Clock Divider\r
+// <i> Divides USB clock to 48 MHz.\r
+// <i> 0 = is disabled\r
+// <0-255>\r
+// </h>\r
+// </e>\r
+*/\r
+#define CLOCK_SETUP 1\r
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000\r
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000\r
+#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000\r
+#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000\r
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000\r
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001\r
+#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000\r
+#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000\r
+#define USBCLKSEL_Val 0x00000000 // Reset: 0x000\r
+#define USBCLKDIV_Val 0x00000000 // Reset: 0x001\r
+\r
+#define PDRUNCFGUSEMASK 0x0000E800\r
+#define PDRUNCFGMASKTMP 0x000005FF\r
+\r
+/*\r
+//-------- <<< end of configuration section >>> ------------------------------\r
+*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ Check the register settings\r
+ *----------------------------------------------------------------------------*/\r
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))\r
+#define CHECK_RSVD(val, mask) (val & mask)\r
+\r
+/* Clock Configuration -------------------------------------------------------*/\r
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))\r
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))\r
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))\r
+ #error "SYSPLLCLKSEL: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))\r
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))\r
+ #error "MAINCLKSEL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))\r
+ #error "SYSAHBCLKDIV: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))\r
+ #error "USBPLLCLKSEL: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))\r
+ #error "USBPLLCTRL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))\r
+ #error "USBCLKSEL: Value out of range!"\r
+#endif\r
+\r
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))\r
+ #error "USBCLKDIV: Value out of range!"\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ DEFINES\r
+ *----------------------------------------------------------------------------*/\r
+ \r
+/*----------------------------------------------------------------------------\r
+ Define clocks\r
+ *----------------------------------------------------------------------------*/\r
+#define __XTAL (12000000UL) /* Oscillator frequency */\r
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */\r
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */\r
+\r
+\r
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)\r
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)\r
+\r
+#if (CLOCK_SETUP) /* Clock Setup */\r
+ #if (__FREQSEL == 0)\r
+ #define __WDT_OSC_CLK ( 0) /* undefined */\r
+ #elif (__FREQSEL == 1)\r
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)\r
+ #elif (__FREQSEL == 2)\r
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)\r
+ #elif (__FREQSEL == 3)\r
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)\r
+ #elif (__FREQSEL == 4)\r
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)\r
+ #elif (__FREQSEL == 5)\r
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)\r
+ #elif (__FREQSEL == 6)\r
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)\r
+ #elif (__FREQSEL == 7)\r
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)\r
+ #elif (__FREQSEL == 8)\r
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)\r
+ #elif (__FREQSEL == 9)\r
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)\r
+ #elif (__FREQSEL == 10)\r
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)\r
+ #elif (__FREQSEL == 11)\r
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)\r
+ #elif (__FREQSEL == 12)\r
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)\r
+ #elif (__FREQSEL == 13)\r
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)\r
+ #elif (__FREQSEL == 14)\r
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)\r
+ #else\r
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)\r
+ #endif\r
+\r
+ /* sys_pllclkin calculation */\r
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)\r
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)\r
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)\r
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)\r
+ #else\r
+ #define __SYS_PLLCLKIN (0)\r
+ #endif\r
+\r
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))\r
+\r
+ /* main clock calculation */\r
+ #if ((MAINCLKSEL_Val & 0x03) == 0)\r
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)\r
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)\r
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)\r
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)\r
+ #if (__FREQSEL == 0)\r
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"\r
+ #else\r
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)\r
+ #endif\r
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)\r
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)\r
+ #else\r
+ #define __MAIN_CLOCK (0)\r
+ #endif\r
+\r
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) \r
+\r
+#else\r
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)\r
+#endif // CLOCK_SETUP \r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock functions\r
+ *----------------------------------------------------------------------------*/\r
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */\r
+{\r
+ uint32_t wdt_osc = 0;\r
+\r
+ /* Determine clock frequency according to clock register values */\r
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {\r
+ case 0: wdt_osc = 0; break;\r
+ case 1: wdt_osc = 500000; break;\r
+ case 2: wdt_osc = 800000; break;\r
+ case 3: wdt_osc = 1100000; break;\r
+ case 4: wdt_osc = 1400000; break;\r
+ case 5: wdt_osc = 1600000; break;\r
+ case 6: wdt_osc = 1800000; break;\r
+ case 7: wdt_osc = 2000000; break;\r
+ case 8: wdt_osc = 2200000; break;\r
+ case 9: wdt_osc = 2400000; break;\r
+ case 10: wdt_osc = 2600000; break;\r
+ case 11: wdt_osc = 2700000; break;\r
+ case 12: wdt_osc = 2900000; break;\r
+ case 13: wdt_osc = 3100000; break;\r
+ case 14: wdt_osc = 3200000; break;\r
+ case 15: wdt_osc = 3400000; break;\r
+ }\r
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;\r
+ \r
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {\r
+ case 0: /* Internal RC oscillator */\r
+ SystemCoreClock = __IRC_OSC_CLK;\r
+ break;\r
+ case 1: /* Input Clock to System PLL */\r
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {\r
+ case 0: /* Internal RC oscillator */\r
+ SystemCoreClock = __IRC_OSC_CLK;\r
+ break;\r
+ case 1: /* System oscillator */\r
+ SystemCoreClock = __SYS_OSC_CLK;\r
+ break;\r
+ case 2: /* Reserved */\r
+ case 3: /* Reserved */\r
+ SystemCoreClock = 0;\r
+ break;\r
+ }\r
+ break;\r
+ case 2: /* WDT Oscillator */\r
+ SystemCoreClock = wdt_osc;\r
+ break;\r
+ case 3: /* System PLL Clock Out */\r
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {\r
+ case 0: /* Internal RC oscillator */\r
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {\r
+ SystemCoreClock = __IRC_OSC_CLK;\r
+ } else {\r
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);\r
+ }\r
+ break;\r
+ case 1: /* System oscillator */\r
+ if (LPC_SYSCON->SYSPLLCTRL & 0x180) {\r
+ SystemCoreClock = __SYS_OSC_CLK;\r
+ } else {\r
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);\r
+ }\r
+ break;\r
+ case 2: /* Reserved */\r
+ case 3: /* Reserved */\r
+ SystemCoreClock = 0;\r
+ break;\r
+ }\r
+ break;\r
+ }\r
+\r
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; \r
+\r
+}\r
+\r
+__INLINE void SYSCTL_PowerDown(uint32_t powerdownmask)\r
+{\r
+ uint32_t pdrun;\r
+\r
+ pdrun = LPC_SYSCON->PDRUNCFG & PDRUNCFGMASKTMP;\r
+ pdrun |= (powerdownmask & PDRUNCFGMASKTMP);\r
+ LPC_SYSCON->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);\r
+}\r
+\r
+__INLINE void SYSCTL_PowerUp(uint32_t powerupmask)\r
+{\r
+ uint32_t pdrun;\r
+\r
+ pdrun = LPC_SYSCON->PDRUNCFG & PDRUNCFGMASKTMP;\r
+ pdrun &= ~(powerupmask & PDRUNCFGMASKTMP);\r
+\r
+ LPC_SYSCON->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);\r
+}\r
+\r
+__STATIC_INLINE void FLASH_SetFLASHAccess(uint32_t clks)\r
+{\r
+ uint32_t tmp = LPC_FLASHCTRL->FLASHCFG & (~(0x3));\r
+\r
+ /* Don't alter upper bits */\r
+ LPC_FLASHCTRL->FLASHCFG = tmp | clks;\r
+}\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System.\r
+ */\r
+void SystemInit (void) {\r
+ volatile uint32_t i;\r
+\r
+#if (CLOCK_SETUP) /* Clock Setup */\r
+\r
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)\r
+ //LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */\r
+ SYSCTL_PowerUp ((1 << 5));\r
+ //LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;\r
+ for (i = 0; i < 0x100; i++) __NOP();\r
+#endif\r
+\r
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */\r
+ LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */\r
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01;\r
+ //while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */\r
+\r
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */\r
+ SYSCTL_PowerDown (1 << 7);\r
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;\r
+ //LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */\r
+ SYSCTL_PowerUp ((1 << 7));\r
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */\r
+#endif\r
+\r
+#if (((MAINCLKSEL_Val & 0x03) == 2) )\r
+ SYSCTL_PowerDown (1 << 6);\r
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;\r
+ //LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */\r
+ SYSCTL_PowerUp ((1 << 6));\r
+ for (i = 0; i < 200; i++) __NOP();\r
+#endif\r
+\r
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;\r
+\r
+ FLASH_SetFLASHAccess (FLASHCFG_50MHZ_CPU);\r
+\r
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */\r
+ LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */\r
+ LPC_SYSCON->MAINCLKUEN = 0x01;\r
+ //while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */\r
+\r
+#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */\r
+ //SYSCTL_PowerDown (1 << 8);\r
+ LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */\r
+ LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */\r
+ LPC_SYSCON->USBPLLCLKUEN = 0x01;\r
+ //while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */\r
+ LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;\r
+ SYSCTL_PowerUp (1 << 8);\r
+ while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */\r
+ //LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */\r
+\r
+#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */\r
+ SYSCTL_PowerDown (1 << 10);\r
+ LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */\r
+ LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */\r
+ //LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */\r
+ SYSCTL_PowerUp (1 << 10);\r
+#endif\r
+\r
+\r
+\r
+#else /* USB clock is not used */ \r
+ LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */\r
+ LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */\r
+#endif\r
+\r
+#endif\r
+\r
+ /* System clock to the IOCON needs to be enabled or\r
+ most of the I/O related peripherals won't work. */\r
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);\r
+\r
+ LPC_IOCON->PIO0_3 = 1; // USB_VBUS\r
+ LPC_IOCON->PIO0_6 = 1; // USB_CONNECT\r
+\r
+ LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 26;\r
+\r
+}\r
--- /dev/null
+/*
+ * uart.c
+ *
+ * Created on: Jun 26, 2015
+ * Author: yliu
+ */
+
+#include "LPC11Uxx.h"
+
+void init_uart () {
+ /*
+ LPC_IOCON->PIO0_18 = 1; // PIO0_18 used for RXD
+ LPC_IOCON->PIO0_19 = 1; // PIO0_19 used for TXD
+
+ // Setup UART for 115.2K8N1
+ Chip_UART_Init(LPC_USART);
+ LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 12;
+ Chip_UART_SetBaud(LPC_USART, 115200);
+ Chip_UART_ConfigData(LPC_USART, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT));
+ Chip_UART_SetupFIFOS(LPC_USART, (UART_FCR_FIFO_EN | UART_FCR_TRG_LEV2));
+ Chip_UART_TXEnable(LPC_USART);
+ */
+}
--- /dev/null
+/*
+ * usb_desc.c
+ *
+ * Created on: Jun 18, 2015
+ * Author: yliu
+ */
+
+#include "compiler.h"
+#include "app_usbd_cfg.h"
+#include "DAP_config.h"
+
+ALIGNED(4) const uint8_t HID_ReportDescriptor[] = {
+ HID_UsagePageVendor(0x00),
+ HID_Usage(0x01),
+ HID_Collection(HID_Application),
+ HID_LogicalMin(0), /* value range: 0 - 0xFF */
+ HID_LogicalMaxS(0xFF),
+ HID_ReportSize(8), /* 8 bits */
+ HID_ReportCount(DAP_PACKET_SIZE),
+ HID_Usage(0x01),
+ HID_Input(HID_Data | HID_Variable | HID_Absolute),
+ HID_ReportCount(DAP_PACKET_SIZE),
+ HID_Usage(0x01),
+ HID_Output(HID_Data | HID_Variable | HID_Absolute),
+ HID_ReportCount(1),
+ HID_Usage(0x01),
+ HID_Feature(HID_Data | HID_Variable | HID_Absolute),
+ HID_EndCollection,
+};
+
+const uint8_t hid_report_size = sizeof (HID_ReportDescriptor);
+
+
+/**
+ * USB Standard Device Descriptor
+ */
+ALIGNED(4) const uint8_t USB_DeviceDescriptor[] = {
+ USB_DEVICE_DESC_SIZE, /* bLength */
+ USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(0x0200), /* bcdUSB 2.0 */
+ 0x00, /* bDeviceClass */
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceProtocol */
+ USB_MAX_PACKET0, /* bMaxPacketSize0 */
+ WBVAL(0x1FC9), /* idVendor */
+ WBVAL(0x0081), /* idProduct */
+ WBVAL(0x0100), /* bcdDevice */
+ 0x01, /* iManufacturer */
+ 0x02, /* iProduct */
+ 0x03, /* iSerialNumber */
+ 0x01 /* bNumConfigurations */
+};
+
+/**
+ * USB FSConfiguration Descriptor
+ * All Descriptors (Configuration, Interface, Endpoint, Class, Vendor)
+ */
+ALIGNED(4) uint8_t USB_FsConfigDescriptor[] = {
+ /* Configuration 1 */
+ USB_CONFIGURATION_DESC_SIZE, /* bLength */
+ USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL( /* wTotalLength */
+ USB_CONFIGURATION_DESC_SIZE +
+ USB_INTERFACE_DESC_SIZE +
+ HID_DESC_SIZE +
+ USB_ENDPOINT_DESC_SIZE +
+ USB_ENDPOINT_DESC_SIZE
+ ),
+ 0x01, /* bNumInterfaces */
+ 0x01, /* bConfigurationValue */
+ 0x00, /* iConfiguration */
+ USB_CONFIG_SELF_POWERED, /* bmAttributes */
+ USB_CONFIG_POWER_MA(100), /* bMaxPower */
+
+ /* Interface 0, Alternate Setting 0, HID Class */
+ USB_INTERFACE_DESC_SIZE, /* bLength */
+ USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 0x00, /* bInterfaceNumber */
+ 0x00, /* bAlternateSetting */
+ 0x02, /* bNumEndpoints */
+ USB_DEVICE_CLASS_HUMAN_INTERFACE, /* bInterfaceClass */
+ HID_SUBCLASS_NONE, /* bInterfaceSubClass */
+ HID_PROTOCOL_NONE, /* bInterfaceProtocol */
+ 0x04, /* iInterface */
+ /* HID Class Descriptor */
+ /* HID_DESC_OFFSET = 0x0012 */
+ HID_DESC_SIZE, /* bLength */
+ HID_HID_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(0x0111), /* bcdHID : 1.11*/
+ 0x00, /* bCountryCode */
+ 0x01, /* bNumDescriptors */
+ HID_REPORT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(sizeof(HID_ReportDescriptor)), /* wDescriptorLength */
+ /* Endpoint, HID Interrupt In */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ HID_EP_IN, /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
+ WBVAL(64), /* wMaxPacketSize */
+ 0x01, /* 1ms */ /* bInterval */
+ /* Endpoint, HID Interrupt Out */
+ USB_ENDPOINT_DESC_SIZE, /* bLength */
+ USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
+ HID_EP_OUT, /* bEndpointAddress */
+ USB_ENDPOINT_TYPE_INTERRUPT, /* bmAttributes */
+ WBVAL(64), /* wMaxPacketSize */
+ 0x01, /* bInterval: 1ms */
+ /* Terminator */
+ 0 /* bLength */
+};
+
+/**
+ * USB String Descriptor (optional)
+ */
+const uint8_t USB_StringDescriptor[] = {
+ /* Index 0x00: LANGID Codes */
+ 0x04, /* bLength */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ WBVAL(0x0409), /* wLANGID : US English*/
+ /* Index 0x01: Manufacturer */
+ (8 * 2 + 2), /* bLength (8 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'A', 0,
+ 'R', 0,
+ 'M', 0,
+ 'S', 0,
+ 'T', 0,
+ 'A', 0,
+ 'R', 0,
+ 'T', 0,
+ /* Index 0x02: Product */
+ (24 * 2 + 2), /* bLength (24 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'I', 0,
+ 'B', 0,
+ 'D', 0,
+ 'A', 0,
+ 'P', 0,
+ '-', 0,
+ 'L', 0,
+ 'P', 0,
+ 'C', 0,
+ '1', 0,
+ '1', 0,
+ 'U', 0,
+ '3', 0,
+ '5', 0,
+ ' ', 0,
+ 'C', 0,
+ 'M', 0,
+ 'S', 0,
+ 'I', 0,
+ 'S', 0,
+ '-', 0,
+ 'D', 0,
+ 'A', 0,
+ 'P', 0,
+ /* Index 0x03: Serial Number */
+ (11 * 2 + 2), /* bLength (13 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'I', 0,
+ 'B', 0,
+ 'D', 0,
+ 'A', 0,
+ 'P', 0,
+ '2', 0,
+ '0', 0,
+ '1', 0,
+ '5', 0,
+ '0', 0,
+ '7', 0,
+ /* Index 0x04: Interface 0, Alternate Setting 0 */
+ (3 * 2 + 2), /* bLength (3 Char + Type + lenght) */
+ USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
+ 'H', 0,
+ 'I', 0,
+ 'D', 0,
+};
--- /dev/null
+/*
+ * usb_driver.c
+ *
+ * Created on: Jun 18, 2015
+ * Author: yliu
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __USE_CMSIS
+#include "LPC11Uxx.h"
+#endif
+
+
+#include "usb_driver.h"
+
+#define PDRUNCFGUSEMASK 0x0000E800
+#define PDRUNCFGMASKTMP 0x000005FF
+
+USBD_HANDLE_T g_usb_hnd;
+const USBD_API_T *g_pUsbApi;
+
+
+/* Find the address of interface descriptor for given class type. */
+USB_INTERFACE_DESCRIPTOR *find_IntfDesc(const uint8_t *pDesc, uint32_t intfClass)
+{
+ USB_COMMON_DESCRIPTOR *pD;
+ USB_INTERFACE_DESCRIPTOR *pIntfDesc = 0;
+ uint32_t next_desc_adr;
+
+ pD = (USB_COMMON_DESCRIPTOR *) pDesc;
+ next_desc_adr = (uint32_t) pDesc;
+
+ while (pD->bLength) {
+ /* is it interface descriptor */
+ if (pD->bDescriptorType == USB_INTERFACE_DESCRIPTOR_TYPE) {
+
+ pIntfDesc = (USB_INTERFACE_DESCRIPTOR *) pD;
+ /* did we find the right interface descriptor */
+ if (pIntfDesc->bInterfaceClass == intfClass) {
+ break;
+ }
+ }
+ pIntfDesc = 0;
+ next_desc_adr = (uint32_t) pD + pD->bLength;
+ pD = (USB_COMMON_DESCRIPTOR *) next_desc_adr;
+ }
+
+ return pIntfDesc;
+}
+
+
+
+
+void init_usb_clock () {
+ // no need to do this: LPC_SYSCON->PDRUNCFG &= ~(1 << 8);
+ // system_LPC11Uxx.c done that already.
+ // configure SYSAHBCLKCTRL
+
+ // no need to do this: enabled in ResetISR()
+ //LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 26; // ram1 clock source enable
+ //LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 27; // usbram clock source enable
+ // conf usb main clock
+ LPC_SYSCON->USBCLKSEL = 0;
+ LPC_SYSCON->USBCLKUEN = 0;
+ LPC_SYSCON->USBCLKUEN = 1;
+ LPC_SYSCON->USBCLKDIV = 1;
+
+ LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 14; // usb clock source
+ //LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 26;
+ LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 27;
+}
+
+void init_usb_power () {
+ uint32_t pdrun;
+ pdrun = LPC_SYSCON->PDRUNCFG & PDRUNCFGMASKTMP;
+ pdrun &= ~((1 << 10) & PDRUNCFGMASKTMP);
+ LPC_SYSCON->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);
+}
+
+void USB_IRQHandler(void) {
+ uint32_t *addr = (uint32_t *) LPC_USB->EPLISTSTART;
+
+ /* WORKAROUND for artf32289 ROM driver BUG:
+ As part of USB specification the device should respond
+ with STALL condition for any unsupported setup packet. The host will send
+ new setup packet/request on seeing STALL condition for EP0 instead of sending
+ a clear STALL request. Current driver in ROM doesn't clear the STALL
+ condition on new setup packet which should be fixed.
+ */
+ if ( LPC_USB->DEVCMDSTAT & (1 << 8) ) { /* if setup packet is received */
+ addr[0] &= ~(1 << 29); /* clear EP0_OUT stall */
+ addr[2] &= ~(1 << 29); /* clear EP0_IN stall */
+ }
+ USBD_API->hw->ISR(g_usb_hnd);
+}
+
+int init_usb_driver (USBD_API_INIT_PARAM_T *usb_param) {
+ USB_CORE_DESCS_T desc;
+ ErrorCode_t ret = LPC_OK;
+
+ g_pUsbApi = (const USBD_API_T *) LPC_ROM_API->usbdApiBase;
+ memset((void *) usb_param, 0, sizeof(USBD_API_INIT_PARAM_T));
+ usb_param->usb_reg_base = LPC_USB_BASE;
+ /* WORKAROUND for artf44835 ROM driver BUG:
+ Code clearing STALL bits in endpoint reset routine corrupts memory area
+ next to the endpoint control data. For example When EP0, EP1_IN, EP1_OUT,
+ EP2_IN are used we need to specify 3 here. But as a workaround for this
+ issue specify 4. So that extra EPs control structure acts as padding buffer
+ to avoid data corruption. Corruption of padding memory doesn’t affect the
+ stack/program behaviour.
+ */
+ usb_param->max_num_ep = 2 + 1;
+ usb_param->mem_base = USB_STACK_MEM_BASE;
+ usb_param->mem_size = USB_STACK_MEM_SIZE;
+
+ desc.device_desc = (uint8_t *) USB_DeviceDescriptor;
+ desc.string_desc = (uint8_t *) USB_StringDescriptor;
+
+ desc.high_speed_desc = USB_FsConfigDescriptor;
+ desc.full_speed_desc = USB_FsConfigDescriptor;
+ desc.device_qualifier = 0;
+
+ ret = USBD_API->hw->Init(&g_usb_hnd, &desc, usb_param);
+ if (ret != LPC_OK) return -1;
+
+ usb_param->mem_base = USB_STACK_MEM_BASE + (USB_STACK_MEM_SIZE - usb_param->mem_size);
+ return 0;
+}
+
+
+
+int init_usb_hid (USBD_API_INIT_PARAM_T *usb_param,
+ HID_GetReport_Func_T getreport_fun, HID_SetReport_Func_T setreport_fun,
+ HID_EpIn_Hdlr_Func_T epin_hdlr_fun, HID_EpOut_Hdlr_Func_T epout_hdlr_fun,
+ uint8_t** report_saddr, int report_size) {
+ USBD_HID_INIT_PARAM_T hid_param;
+ USB_HID_REPORT_T reports_data[1];
+ ErrorCode_t ret = LPC_OK;
+
+ memset((void *) &hid_param, 0, sizeof(USBD_HID_INIT_PARAM_T));
+ hid_param.max_reports = 1;
+
+ /* Init reports_data */
+ reports_data[0].len = hid_report_size;
+ reports_data[0].idle_time = 0;
+ reports_data[0].desc = (uint8_t *) &HID_ReportDescriptor[0];
+
+ USB_INTERFACE_DESCRIPTOR *pIntfDesc = (USB_INTERFACE_DESCRIPTOR *) &USB_FsConfigDescriptor[sizeof(USB_CONFIGURATION_DESCRIPTOR)];
+
+ if ((pIntfDesc == 0) || (pIntfDesc->bInterfaceClass != USB_DEVICE_CLASS_HUMAN_INTERFACE)) {
+ return -1;
+ }
+
+ hid_param.mem_base = usb_param->mem_base;
+ hid_param.mem_size = usb_param->mem_size;
+ hid_param.intf_desc = (uint8_t *) pIntfDesc;
+ /* user defined functions */
+ hid_param.HID_GetReport = getreport_fun;
+ hid_param.HID_SetReport = setreport_fun;
+ hid_param.HID_EpIn_Hdlr = epin_hdlr_fun;
+ hid_param.HID_EpOut_Hdlr = epout_hdlr_fun;
+ hid_param.report_data = reports_data;
+
+ ret = USBD_API->hid->init(g_usb_hnd, &hid_param);
+ if (ret != LPC_OK) return -2;
+ /* allocate USB accessable memory space for report data */
+ *report_saddr = (uint8_t *) hid_param.mem_base;
+ memset (hid_param.mem_base, 0, report_size);
+ hid_param.mem_base += report_size;
+ hid_param.mem_size -= report_size;
+ /* update memory variables */
+ usb_param->mem_base = hid_param.mem_base;
+ usb_param->mem_size = hid_param.mem_size;
+ return 0;
+}
+
+void connect_to_usb_bus () {
+ NVIC_EnableIRQ (USB_IRQn);
+ USBD_API->hw->Connect (g_usb_hnd, 1);
+}
+
+void disconnect_to_usb_bus () {
+ USBD_API->hw->Connect (g_usb_hnd, 0);
+ NVIC_DisableIRQ (USB_IRQn);
+}
projects / armstart-ibdap / commitdiff