memset( pcReceivedString, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );\r
\r
/* Has any data been sent by the client? */\r
- xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, xTicksToBlock );\r
+ xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, portMAX_DELAY );\r
\r
- /* Should always receive data as a delay was used. */\r
+ /* Should always receive data as max delay was used. */\r
configASSERT( xReceivedLength > 0 );\r
\r
/* Echo the received data back to the client. */\r
/* The number of bytes of storage in the stream buffers used in this test. */\r
#define sbSTREAM_BUFFER_LENGTH_BYTES ( ( size_t ) 30 )\r
\r
+/* Stream buffer length one. */\r
+#define sbSTREAM_BUFFER_LENGTH_ONE ( ( size_t ) 1 )\r
+\r
/* Start and end ASCII characters used in data sent to the buffers. */\r
#define sbASCII_SPACE 32\r
#define sbASCII_TILDA 126\r
xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );\r
prvSingleTaskTests( xTempStreamBuffer );\r
vStreamBufferDelete( xTempStreamBuffer );\r
+\r
+ /* The following are tests for a stream buffer of size one. */\r
+ /* Create a buffer of size one. */\r
+ xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_ONE, sbTRIGGER_LEVEL_1 );\r
+ /* Ensure that the buffer was created successfully. */\r
+ configASSERT( xTempStreamBuffer );\r
+\r
+ /* Send one byte to the buffer. */\r
+ ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK );\r
+ /* Ensure that the byte was sent successfully. */\r
+ configASSERT( ux == 1 );\r
+ /* Try sending another byte to the buffer. */\r
+ ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK );\r
+ /* Make sure that send failed as the buffer is full. */\r
+ configASSERT( ux == 0 );\r
+\r
+ /* Receive one byte from the buffer. */\r
+ memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );\r
+ ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK );\r
+ /* Ensure that the receive was successful. */\r
+ configASSERT( ux == 1 );\r
+ /* Ensure that the correct data was received. */\r
+ configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] );\r
+ /* Try receiving another byte from the buffer. */\r
+ ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK );\r
+ /* Ensure that the receive failed as the buffer is empty. */\r
+ configASSERT( ux == 0 );\r
+\r
+ /* Try sending two bytes to the buffer. Since the size of the\r
+ * buffer is one, we must not be able to send more than one. */\r
+ ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 2, sbDONT_BLOCK );\r
+ /* Ensure that only one byte was sent. */\r
+ configASSERT( ux == 1 );\r
+\r
+ /* Try receiving two bytes from the buffer. Since the size of the\r
+ * buffer is one, we must not be able to get more than one. */\r
+ memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );\r
+ ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 2, sbDONT_BLOCK );\r
+ /* Ensure that only one byte was received. */\r
+ configASSERT( ux == 1 );\r
+ /* Ensure that the correct data was received. */\r
+ configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] );\r
+\r
+ /* Delete the buffer. */\r
+ vStreamBufferDelete( xTempStreamBuffer );\r
}\r
}\r
/*-----------------------------------------------------------*/\r
memset( pcReceivedString, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );\r
\r
/* Has any data been sent by the client? */\r
- xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, xTicksToBlock );\r
+ xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, portMAX_DELAY );\r
\r
- /* Should always receive data as a delay was used. */\r
+ /* Should always receive data as max delay was used. */\r
prvCheckExpectedState( xReceivedLength > 0 );\r
\r
/* Echo the received data back to the client. */\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
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+ </storageModule>\r
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+ </storageModule>\r
+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
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+ <name>RTOSDemo</name>\r
+ <comment></comment>\r
+ <projects>\r
+ <project>XtensaInfo</project>\r
+ </projects>\r
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+ <link>\r
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+ <link>\r
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+ </link>\r
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+ <type>1</type>\r
+ <locationURI>PARENT-1-PROJECT_LOC/Common/Minimal/StreamBufferInterrupt.c</locationURI>\r
+ </link>\r
+ <link>\r
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+ <type>1</type>\r
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+ </link>\r
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+ </link>\r
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+ <type>1</type>\r
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+ </link>\r
+ <link>\r
+ <name>CommonDemoTasks/countsem.c</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-1-PROJECT_LOC/Common/Minimal/countsem.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>CommonDemoTasks/death.c</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-1-PROJECT_LOC/Common/Minimal/death.c</locationURI>\r
+ </link>\r
+ <link>\r
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+ <type>1</type>\r
+ <locationURI>PARENT-1-PROJECT_LOC/Common/Minimal/flop.c</locationURI>\r
+ </link>\r
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+ </link>\r
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+ </link>\r
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+ <type>1</type>\r
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+ <locationURI>PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c</locationURI>\r
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+ <link>\r
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+ <locationURI>PARENT-2-PROJECT_LOC/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+</projectDescription>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>\r
+<BuildTarget version="1.0" tool="xtensa">\r
+ <BuildSettings>\r
+ <BaseSettings path="project">\r
+ <LinkerOptions>\r
+ <LinkerSupport value="sim" key="-mlsp=" custom="false"/>\r
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+ </BaseSettings>\r
+ </BuildSettings>\r
+</BuildTarget>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
+<BuildTarget tool="xtensa" version="1.0">
+ <BuildSettings>
+ <BaseSettings path="project">
+ <CompilerOptions>
+ <FlagValueMapOptions>
+ <FlagValueMapEntry>
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+ </FlagValueMapEntry>
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+ </CompilerOptions>
+ <AssemblerOptions>
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+ </AssemblerOptions>
+ <LinkerOptions>
+ <BooleanMapOptions>
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+ </LinkerOptions>
+ </BaseSettings>
+ </BuildSettings>
+</BuildTarget>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<xxProperties>\r
+<propertyGroup name="project.information">\r
+<version value="3.0"/>\r
+</propertyGroup>\r
+<propertyGroup name="build.property">\r
+<buildTarget defaultTarget="Debug"/>\r
+</propertyGroup>\r
+<propertyGroup name="build.exclusion.data">\r
+<buildExclusionDatas>\r
+<exclusionSet name="Default" selected="1">\r
+<excludedEntry data="/.*/bin/.*"/>\r
+</exclusionSet>\r
+</buildExclusionDatas>\r
+</propertyGroup>\r
+<propertyGroup name="build.auto.includes">\r
+<exportDirs autoConsumeDirs="true" includeDepDirs="true" mode="auto"/>\r
+</propertyGroup>\r
+<propertyGroup name="library.dependencies"/>\r
+<propertyGroup name="build.custom.steps"/>\r
+</xxProperties>\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+\r
+/* Required for configuration-dependent settings */\r
+#include "xtensa_config.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * Note that the default heap size is deliberately kept small so that\r
+ * the build is more likely to succeed for configurations with limited\r
+ * memory.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+\r
+#ifdef SMALL_TEST\r
+#define configUSE_TICK_HOOK 0\r
+#else\r
+#define configUSE_TICK_HOOK 1\r
+#endif\r
+\r
+#define configTICK_RATE_HZ ( 1000 )\r
+\r
+/* Default clock rate for simulator */\r
+#define configCPU_CLOCK_HZ 10000000 //_RB_ was 2MHz\r
+\r
+/* This has impact on speed of search for highest priority */\r
+#ifdef SMALL_TEST\r
+#define configMAX_PRIORITIES ( 7 )\r
+#else\r
+#define configMAX_PRIORITIES ( 7 ) //_RB_\r
+#endif\r
+\r
+/* Minimal stack size. This may need to be increased for your application */\r
+/* NOTE: The FreeRTOS demos may not work reliably with stack size < 4KB. */\r
+/* The Xtensa-specific examples should be fine with XT_STACK_MIN_SIZE. */\r
+#if !(defined XT_STACK_MIN_SIZE)\r
+#error XT_STACK_MIN_SIZE not defined, did you include xtensa_config.h ?\r
+#endif\r
+\r
+#ifdef SMALL_TEST\r
+#define configMINIMAL_STACK_SIZE (XT_STACK_MIN_SIZE)\r
+#else\r
+#define configMINIMAL_STACK_SIZE (XT_STACK_MIN_SIZE > 4096 ? XT_STACK_MIN_SIZE : 4096)\r
+#endif\r
+\r
+/* The Xtensa port uses a separate interrupt stack. Adjust the stack size */\r
+/* to suit the needs of your specific application. */\r
+#ifndef configISR_STACK_SIZE\r
+#define configISR_STACK_SIZE 2048\r
+#endif\r
+\r
+/* Minimal heap size to make sure examples can run on memory limited\r
+ configs. Adjust this to suit your system. */\r
+#ifdef SMALL_TEST\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) (16 * 1024) )\r
+#else\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) (512 * 1024) )\r
+#endif\r
+\r
+#define configMAX_TASK_NAME_LEN ( 8 )\r
+#define configUSE_TRACE_FACILITY 1 /* Used by vTaskList in main.c */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0 /* Used by vTaskList in main.c */\r
+#define configUSE_TRACE_FACILITY_2 0 /* Provided by Xtensa port patch */\r
+#define configBENCHMARK 0 /* Provided by Xtensa port patch */\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+\r
+#ifdef SMALL_TEST\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configCHECK_FOR_STACK_OVERFLOW 0\r
+#else\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#endif\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+ to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+#define INCLUDE_xTaskAbortDelay 1\r
+#define INCLUDE_xTaskGetHandle 1\r
+#define INCLUDE_xSemaphoreGetMutexHolder 1\r
+\r
+/* The priority at which the tick interrupt runs. This should probably be\r
+ kept at 1. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS.org API functions can\r
+ be called. Only API functions that end in ...FromISR() can be used within\r
+ interrupts. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL\r
+\r
+/* XT_USE_THREAD_SAFE_CLIB is defined in xtensa_config.h and can be\r
+ overridden from the compiler/make command line. The small test\r
+ however always disables C lib thread safety to minimize size. */\r
+#ifdef SMALL_TEST\r
+ #define configUSE_NEWLIB_REENTRANT 0\r
+#else\r
+#if (XT_USE_THREAD_SAFE_CLIB > 0u)\r
+ #if XT_HAVE_THREAD_SAFE_CLIB\r
+ #define configUSE_NEWLIB_REENTRANT 0 //_RB_ 1\r
+ #else\r
+ #error "Error: thread-safe C library support not available for this C library."\r
+ #endif\r
+#else\r
+ #define configUSE_NEWLIB_REENTRANT 0\r
+#endif\r
+#endif\r
+\r
+/* Test FreeRTOS timers (with timer task) and more. */\r
+/* Some files don't compile if this flag is disabled */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+#define configTIMER_QUEUE_LENGTH 10\r
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE\r
+\r
+#ifdef SMALL_TEST\r
+#define INCLUDE_xTimerPendFunctionCall 0\r
+#define INCLUDE_eTaskGetState 0\r
+#define configUSE_QUEUE_SETS 0\r
+#else\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define configUSE_QUEUE_SETS 1\r
+#endif\r
+\r
+/* Specific config for XTENSA (these can be deleted and they will take default values) */\r
+\r
+#if (!defined XT_SIMULATOR) && (!defined XT_BOARD)\r
+#define configXT_SIMULATOR 1 /* Simulator mode */\r
+#define configXT_BOARD 0 /* Board mode */\r
+#endif\r
+\r
+#ifndef SMALL_TEST\r
+\r
+#if (!defined XT_INTEXC_HOOKS)\r
+#define configXT_INTEXC_HOOKS 1 /* Exception hooks used by certain tests */\r
+#endif\r
+\r
+#if configUSE_TRACE_FACILITY_2\r
+#define configASSERT_2 1 /* Specific to Xtensa port */\r
+#endif\r
+\r
+#endif\r
+\r
+/* It is a good idea to define configASSERT() while developing. configASSERT()\r
+uses the same semantics as the standard C assert() macro. */\r
+#if !defined __ASSEMBLER__\r
+ extern void vAssertCalled( unsigned long ulLine, const char * const pcFileName );\r
+#endif\r
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __LINE__, __FILE__ )\r
+\r
+#define configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN ( 2 )\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* Xtensa includes. */\r
+#include <xtensa/corebits.h>\r
+#include <xtensa/config/system.h>\r
+#include <xtensa_api.h>\r
+#include <xtensa/hal.h>\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Check if Timer1 is available. */\r
+#if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED\r
+ #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL\r
+ #define SECOND_TIMER_AVAILABLE 1\r
+ #endif\r
+#endif\r
+\r
+#ifndef SECOND_TIMER_AVAILABLE\r
+ #define SECOND_TIMER_AVAILABLE 0\r
+#endif\r
+\r
+/* Timer0 is used to drive systick and therefore we use Timer1\r
+ * as second interrupt which runs on a higher priority than\r
+ * Timer0. This ensures that systick will get interrupted by\r
+ * this timer and hence we can test interrupt nesting. */\r
+#define SECOND_TIMER_INDEX 1\r
+\r
+/* Frequency of the second timer - This timer is configured at\r
+ * a frequency offset of 17 from the systick timer. */\r
+#define SECOND_TIMER_TICK_RATE_HZ ( configTICK_RATE_HZ + 17 )\r
+#define SECOND_TIMER_TICK_DIVISOR ( configCPU_CLOCK_HZ / SECOND_TIMER_TICK_RATE_HZ )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Defined in main_full.c. */\r
+extern BaseType_t xTimerForQueueTestInitialized;\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt handler for timer interrupt. */\r
+#if( SECOND_TIMER_AVAILABLE == 1 )\r
+ static void prvTimer2Handler( void *arg );\r
+#endif /* SECOND_TIMER_AVAILABLE */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+unsigned currentCycleCount, firstComparatorValue;\r
+\r
+ /* Inform the tick hook function that it can access queues now. */\r
+ xTimerForQueueTestInitialized = pdTRUE;\r
+\r
+ #if( SECOND_TIMER_AVAILABLE == 1 )\r
+ {\r
+ /* Install the interrupt handler for second timer. */\r
+ xt_set_interrupt_handler( XCHAL_TIMER1_INTERRUPT, prvTimer2Handler, NULL );\r
+\r
+ /* Read the current cycle count. */\r
+ currentCycleCount = xthal_get_ccount();\r
+\r
+ /* Calculate time of the first timer interrupt. */\r
+ firstComparatorValue = currentCycleCount + SECOND_TIMER_TICK_DIVISOR;\r
+\r
+ /* Set the comparator. */\r
+ xthal_set_ccompare( SECOND_TIMER_INDEX, firstComparatorValue );\r
+\r
+ /* Enable timer interrupt. */\r
+ xt_ints_on( ( 1 << XCHAL_TIMER1_INTERRUPT ) );\r
+ }\r
+ #endif /* SECOND_TIMER_AVAILABLE */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Xtensa timers work by comparing a cycle counter with a preset value. Once the match occurs\r
+ * an interrupt is generated, and the handler has to set a new cycle count into the comparator.\r
+ * To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,\r
+ * not the time the interrupt was serviced. However if a timer interrupt is ever serviced more\r
+ * than one tick late, it is necessary to process multiple ticks until the new cycle count is\r
+ * in the future, otherwise the next timer interrupt would not occur until after the cycle\r
+ * counter had wrapped (2^32 cycles later).\r
+\r
+do {\r
+ ticks++;\r
+ old_ccompare = read_ccompare_i();\r
+ write_ccompare_i( old_ccompare + divisor );\r
+ service one tick;\r
+ diff = read_ccount() - old_ccompare;\r
+} while ( diff > divisor );\r
+*/\r
+#if( SECOND_TIMER_AVAILABLE == 1 )\r
+\r
+ static void prvTimer2Handler( void *arg )\r
+ {\r
+ unsigned oldComparatorValue, newComparatorValue, currentCycleCount;\r
+\r
+ /* Unused arguments. */\r
+ ( void )arg;\r
+\r
+ do\r
+ {\r
+ /* Read old comparator value. */\r
+ oldComparatorValue = xthal_get_ccompare( SECOND_TIMER_INDEX );\r
+\r
+ /* Calculate the new comparator value. */\r
+ newComparatorValue = oldComparatorValue + SECOND_TIMER_TICK_DIVISOR;\r
+\r
+ /* Update comparator and clear interrupt. */\r
+ xthal_set_ccompare( SECOND_TIMER_INDEX, newComparatorValue );\r
+\r
+ /* Process. */\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+\r
+ /* Ensure comparator update is complete. */\r
+ xthal_icache_sync();\r
+\r
+ /* Read current cycle count to check if we need to process more\r
+ * ticks to catch up. */\r
+ currentCycleCount = xthal_get_ccount();\r
+\r
+ } while( ( currentCycleCount - oldComparatorValue ) > SECOND_TIMER_TICK_DIVISOR );\r
+ }\r
+\r
+#endif /* SECOND_TIMER_AVAILABLE */\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+void vTimer2Handler_C( void );\r
+\r
+#endif /* INT_QUEUE_TIMER_H */\r
+\r
--- /dev/null
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * This project provides two demo applications. A simple blinky style project,
+ * and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two.
+ * The simply blinky demo is implemented and described in main_blinky.c. The
+ * more comprehensive test and demo application is implemented and described in
+ * main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and FreeRTOS hook functions.
+ *
+ *******************************************************************************
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* This project provides two demo applications. A simple blinky style demo
+application, and a more comprehensive test and demo application. The
+mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is used to select between the two.
+
+If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is 1 then the blinky demo will be built.
+The blinky demo is implemented and described in main_blinky.c.
+
+If mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not 1 then the comprehensive test and
+demo application will be built. The comprehensive test and demo application is
+implemented and described in main_full.c. */
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
+
+/*-----------------------------------------------------------*/
+
+/*
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+extern void main_blinky( void );
+extern void main_full( void );
+
+/*
+ * Prototypes for the standard FreeRTOS application hook (callback) functions
+ * implemented within this file. See http://www.freertos.org/a00016.html .
+ */
+void vApplicationMallocFailedHook( void );
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
+void vApplicationTickHook( void );
+
+/*
+ * Only the comprehensive demo uses application hook (callback) functions. See
+ * http://www.freertos.org/a00016.html for more information.
+ */
+void vFullDemoTickHookFunction( void );
+
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
+ of this file. */
+ #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
+ {
+ main_blinky();
+ }
+ #else
+ {
+ main_full();
+ }
+ #endif
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* vApplicationMallocFailedHook() will only be called if
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ function that will get called if a call to pvPortMalloc() fails.
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ timer or semaphore is created. It is also called by various parts of the
+ demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then the
+ size of the heap available to pvPortMalloc() is defined by
+ configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize()
+ API function can be used to query the size of free heap space that remains
+ (although it does not provide information on how the remaining heap might be
+ fragmented). See http://www.freertos.org/a00111.html for more
+ information. */
+ vAssertCalled( __LINE__, __FILE__ );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
+ function is called if a stack overflow is detected. This function is
+ provided as an example only as stack overflow checking does not function
+ when running the FreeRTOS Windows port. */
+ vAssertCalled( __LINE__, __FILE__ );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+ /* This function will be called by each tick interrupt if
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
+ added here, but the tick hook is called from an interrupt context, so
+ code must not attempt to block, and only the interrupt safe FreeRTOS API
+ functions can be used (those that end in FromISR()). */
+
+ #if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 )
+ {
+ vFullDemoTickHookFunction();
+ }
+ #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( unsigned long ulLine, const char * const pcFileName )
+{
+static BaseType_t xPrinted = pdFALSE;
+volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0;
+
+ /* Called if an assertion passed to configASSERT() fails. See
+ http://www.freertos.org/a00110.html#configASSERT for more information. */
+
+ /* Parameters are not used. */
+ ( void ) ulLine;
+ ( void ) pcFileName;
+
+ printf( "ASSERT! Line %ld, file %s\r\n", ulLine, pcFileName );
+
+ taskENTER_CRITICAL();
+ {
+ /* You can step out of this function to debug the assertion by using
+ the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero
+ value. */
+ while( ulSetToNonZeroInDebuggerToContinue == 0 )
+ {
+ __asm volatile( "NOP" );
+ __asm volatile( "NOP" );
+ }
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.1\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/******************************************************************************\r
+ * NOTE 1: Windows will not be running the FreeRTOS demo threads continuously, so\r
+ * do not expect to get real time behaviour from the FreeRTOS Windows port, or\r
+ * this demo application. Also, the timing information in the FreeRTOS+Trace\r
+ * logs have no meaningful units. See the documentation page for the Windows\r
+ * port for further information:\r
+ * http://www.freertos.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html\r
+ *\r
+ * NOTE 2: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky version. Console output\r
+ * is used in place of the normal LED toggling.\r
+ *\r
+ * NOTE 3: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, are defined\r
+ * in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, one software timer, and two tasks. It then\r
+ * starts the scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. It uses vTaskDelayUntil() to create a periodic task that sends\r
+ * the value 100 to the queue every 200 milliseconds (please read the notes\r
+ * above regarding the accuracy of timing under Windows).\r
+ *\r
+ * The Queue Send Software Timer:\r
+ * The timer is an auto-reload timer with a period of two seconds. The timer's\r
+ * callback function writes the value 200 to the queue. The callback function\r
+ * is implemented by prvQueueSendTimerCallback() within this file.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() waits for data to arrive on the queue.\r
+ * When data is received, the task checks the value of the data, then outputs a\r
+ * message to indicate if the data came from the queue send task or the queue\r
+ * send software timer.\r
+ *\r
+ * Expected Behaviour:\r
+ * - The queue send task writes to the queue every 200ms, so every 200ms the\r
+ * queue receive task will output a message indicating that data was received\r
+ * on the queue from the queue send task.\r
+ * - The queue send software timer has a period of two seconds, and is reset\r
+ * each time a key is pressed. So if two seconds expire without a key being\r
+ * pressed then the queue receive task will output a message indicating that\r
+ * data was received on the queue from the queue send software timer.\r
+ *\r
+ * NOTE: Console input and output relies on Windows system calls, which can\r
+ * interfere with the execution of the FreeRTOS Windows port. This demo only\r
+ * uses Windows system call occasionally. Heavier use of Windows system calls\r
+ * can crash the port.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The times are converted from\r
+milliseconds to ticks using the pdMS_TO_TICKS() macro. */\r
+#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL )\r
+#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL )\r
+\r
+/* The number of items the queue can hold at once. */\r
+#define mainQUEUE_LENGTH ( 2 )\r
+\r
+/* The values sent to the queue receive task from the queue send task and the\r
+queue send software timer respectively. */\r
+#define mainVALUE_SENT_FROM_TASK ( 100UL )\r
+#define mainVALUE_SENT_FROM_TIMER ( 200UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * The callback function executed when the software timer expires.\r
+ */\r
+static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/* A software timer that is started from the tick hook. */\r
+static TimerHandle_t xTimer = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*** SEE THE COMMENTS AT THE TOP OF THIS FILE ***/\r
+void main_blinky( void )\r
+{\r
+const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS;\r
+\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this simple case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY,/* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Create the software timer, but don't start it yet. */\r
+ xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */\r
+ xTimerPeriod, /* The period of the software timer in ticks. */\r
+ pdTRUE, /* xAutoReload is set to pdTRUE. */\r
+ NULL, /* The timer's ID is not used. */\r
+ prvQueueSendTimerCallback );/* The function executed when the timer expires. */\r
+\r
+ if( xTimer != NULL )\r
+ {\r
+ xTimerStart( xTimer, 0 );\r
+ }\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS;\r
+const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK;\r
+\r
+ /* Prevent the compiler warning about the unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again.\r
+ The block time is specified in ticks, pdMS_TO_TICKS() was used to\r
+ convert a time specified in milliseconds into a time specified in ticks.\r
+ While in the Blocked state this task will not consume any CPU time. */\r
+ vTaskDelayUntil( &xNextWakeTime, xBlockTime );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ write to the console. 0 is used as the block time so the send operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ have at least one space at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle )\r
+{\r
+const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER;\r
+\r
+ /* This is the software timer callback function. The software timer has a\r
+ period of two seconds and is reset each time a key is pressed. This\r
+ callback function will execute if the timer expires, which will only happen\r
+ if a key is not pressed for two seconds. */\r
+\r
+ /* Avoid compiler warnings resulting from the unused parameter. */\r
+ ( void ) xTimerHandle;\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ write out a message. This function is called from the timer/daemon task, so\r
+ must not block. Hence the block time is set to 0. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+uint32_t ulReceivedValue;\r
+\r
+ /* Prevent the compiler warning about the unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. It will not use any CPU time while it is in the\r
+ Blocked state. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it an expected value? Normally calling printf() from a task is not\r
+ a good idea. Here there is lots of stack space and only one task is\r
+ using console IO so it is ok. However, note the comments at the top of\r
+ this file about the risks of making Windows system calls (such as \r
+ console output) from a FreeRTOS task. */\r
+ if( ulReceivedValue == mainVALUE_SENT_FROM_TASK )\r
+ {\r
+ printf( "Message received from task\r\n" );\r
+ }\r
+ else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER )\r
+ {\r
+ printf( "Message received from software timer\r\n" );\r
+ }\r
+ else\r
+ {\r
+ printf( "Unexpected message\r\n" );\r
+ }\r
+\r
+ fflush( stdout );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.1\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * main() creates all the demo application tasks, then starts the scheduler.\r
+ * The web documentation provides more details of the standard demo application\r
+ * tasks, which provide no particular functionality but do provide a good\r
+ * example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" task - This only executes every five seconds but has a high priority\r
+ * to ensure it gets processor time. Its main function is to check that all the\r
+ * standard demo tasks are still operational. While no errors have been\r
+ * discovered the check task will print out "OK" and the current simulated tick\r
+ * time. If an error is discovered in the execution of a task then the check\r
+ * task will print out an appropriate error message.\r
+ *\r
+ */\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+\r
+/* Kernel includes. */\r
+#include <FreeRTOS.h>\r
+#include <task.h>\r
+#include <queue.h>\r
+#include <timers.h>\r
+#include <semphr.h>\r
+\r
+/* Standard demo includes. */\r
+#include "BlockQ.h"\r
+#include "integer.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+#include "flop.h"\r
+#include "TimerDemo.h"\r
+#include "countsem.h"\r
+#include "death.h"\r
+#include "QueueSet.h"\r
+#include "QueueOverwrite.h"\r
+#include "EventGroupsDemo.h"\r
+#include "IntSemTest.h"\r
+#include "TaskNotify.h"\r
+#include "QueueSetPolling.h"\r
+#include "StaticAllocation.h"\r
+#include "blocktim.h"\r
+#include "AbortDelay.h"\r
+#include "MessageBufferDemo.h"\r
+#include "StreamBufferDemo.h"\r
+#include "StreamBufferInterrupt.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/* Parameters that are passed into the register check tasks solely for the\r
+purpose of ensuring parameters are passed into tasks correctly. */\r
+#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )\r
+#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )\r
+\r
+/* Whether or not to enable interrupt queue tests. */\r
+#define mainENABLE_INT_QUEUE_TESTS ( 0 )\r
+\r
+/* The task that periodically checks that all the standard demo tasks are\r
+ * still executing and error free.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/* Tasks that implement register tests. */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+\r
+/* Functions implemented in assembly file regtest_xtensa.S. */\r
+extern void vRegTest1( void );\r
+extern void vRegTest2( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The variable into which error messages are latched. */\r
+static char *pcStatusMessage = "No errors";\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check task. If the variables keep incrementing,\r
+then the register check tasks have not discovered any errors. If a variable\r
+stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL;\r
+\r
+/* The following variable is used to communicate whether the timers for the\r
+IntQueue tests have been Initialized. This is needed to ensure that the queues\r
+are accessed from the tick hook only after they have been created in the\r
+interrupt queue test. */\r
+volatile BaseType_t xTimerForQueueTestInitialized = pdFALSE;\r
+/*-----------------------------------------------------------*/\r
+\r
+int main_full( void )\r
+{\r
+ /* Start the check task as described at the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ #if( mainENABLE_INT_QUEUE_TESTS == 0 )\r
+ {\r
+ /* Create the standard demo tasks. */\r
+ vStartTaskNotifyTask();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+\r
+ vStartQueuePeekTasks();\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartQueueSetTasks();\r
+\r
+ vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
+ vStartEventGroupTasks();\r
+ vStartInterruptSemaphoreTasks();\r
+ vStartQueueSetPollingTask();\r
+ vCreateBlockTimeTasks();\r
+\r
+ #if( configUSE_PREEMPTION != 0 )\r
+ {\r
+ /* Don't expect these tasks to pass when preemption is not used. */\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+ }\r
+ #endif\r
+\r
+ vCreateAbortDelayTasks();\r
+ vStartMessageBufferTasks( configMINIMAL_STACK_SIZE );\r
+\r
+ vStartStreamBufferTasks();\r
+ vStartStreamBufferInterruptDemo();\r
+\r
+ /* Create the register check tasks, as described at the top of this file */\r
+ xTaskCreate( prvRegTest1Task, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation. This then allows them to\r
+ ascertain whether or not the correct/expected number of tasks are running at\r
+ any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+ }\r
+ #else /* mainENABLE_INT_QUEUE_TESTS */\r
+ {\r
+ /* Start interrupt queue test tasks. */\r
+ vStartInterruptQueueTasks();\r
+ }\r
+ #endif /* mainENABLE_INT_QUEUE_TESTS */\r
+\r
+ /* Start the scheduler itself. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never get here unless there was not enough heap space to create\r
+ the idle and other system tasks. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const TickType_t xCycleFrequency = pdMS_TO_TICKS( 5000UL );\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+\r
+ /* Just to remove compiler warning. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, xCycleFrequency );\r
+\r
+ #if( mainENABLE_INT_QUEUE_TESTS == 0 )\r
+ {\r
+ /* Check the standard demo tasks are running without error. */\r
+ #if( configUSE_PREEMPTION != 0 )\r
+ {\r
+ /* These tasks are only created when preemption is used. */\r
+ if( xAreTimerDemoTasksStillRunning( xCycleFrequency ) != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: TimerDemo";\r
+ }\r
+ }\r
+ #endif\r
+\r
+ if( xAreTaskNotificationTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: Notification";\r
+ }\r
+ else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: BlockQueue";\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: SemTest";\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: PollQueue";\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: IntMath";\r
+ }\r
+ else if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: GenQueue";\r
+ }\r
+ else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: QueuePeek";\r
+ }\r
+ else if( xAreMathsTaskStillRunning() != pdPASS )\r
+ {\r
+ pcStatusMessage = "Error: Flop";\r
+ }\r
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: RecMutex";\r
+ }\r
+ else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: CountSem";\r
+ }\r
+ else if( xAreQueueSetTasksStillRunning() != pdPASS )\r
+ {\r
+ pcStatusMessage = "Error: Queue set";\r
+ }\r
+ else if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
+ {\r
+ pcStatusMessage = "Error: Queue overwrite";\r
+ }\r
+ else if( xAreEventGroupTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: EventGroup";\r
+ }\r
+ else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: IntSem";\r
+ }\r
+ else if( xAreQueueSetPollTasksStillRunning() != pdPASS )\r
+ {\r
+ pcStatusMessage = "Error: Queue set polling";\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdPASS )\r
+ {\r
+ pcStatusMessage = "Error: Block time";\r
+ }\r
+ else if( xAreAbortDelayTestTasksStillRunning() != pdPASS )\r
+ {\r
+ pcStatusMessage = "Error: Abort delay";\r
+ }\r
+ else if( xAreMessageBufferTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: MessageBuffer";\r
+ }\r
+ else if( xAreStreamBufferTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: StreamBuffer";\r
+ }\r
+ else if( xIsInterruptStreamBufferDemoStillRunning() != pdPASS )\r
+ {\r
+ pcStatusMessage = "Error: Stream buffer interrupt";\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: Death";\r
+ }\r
+ else if( ulLastRegTest1Value == ulRegTest1Counter )\r
+ {\r
+ pcStatusMessage = "Error: Reg Test 1";\r
+ }\r
+ else if( ulLastRegTest2Value == ulRegTest2Counter )\r
+ {\r
+ pcStatusMessage = "Error: Reg Test 2";\r
+ }\r
+\r
+ /* Update register test counters. */\r
+ ulLastRegTest1Value = ulRegTest1Counter;\r
+ ulLastRegTest2Value = ulRegTest2Counter;\r
+ }\r
+ #else /* mainENABLE_INT_QUEUE_TESTS */\r
+ {\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ pcStatusMessage = "Error: IntQueue";\r
+ }\r
+ }\r
+ #endif /* mainENABLE_INT_QUEUE_TESTS */\r
+\r
+ /* This is the only task that uses stdout so its ok to call printf()\r
+ directly. */\r
+ printf( "%s - tick count %zu - free heap %zu - min free heap %zu\r\n", pcStatusMessage,\r
+ xTaskGetTickCount(),\r
+ xPortGetFreeHeapSize(),\r
+ xPortGetMinimumEverFreeHeapSize() );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Called by vApplicationTickHook(), which is defined in main.c. */\r
+void vFullDemoTickHookFunction( void )\r
+{\r
+TaskHandle_t xTimerTask;\r
+\r
+ #if( mainENABLE_INT_QUEUE_TESTS == 0 )\r
+ {\r
+ /* Exercise using task notifications from an interrupt. */\r
+ xNotifyTaskFromISR();\r
+\r
+ /* Write to a queue that is in use as part of the queue set demo to\r
+ * demonstrate using queue sets from an ISR. */\r
+ vQueueSetAccessQueueSetFromISR();\r
+\r
+ /* Call the periodic queue overwrite from ISR demo. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+\r
+ /* Exercise event groups from interrupts. */\r
+ vPeriodicEventGroupsProcessing();\r
+\r
+ /* Exercise giving mutexes from an interrupt. */\r
+ vInterruptSemaphorePeriodicTest();\r
+\r
+ /* Queue set access from interrupt. */\r
+ vQueueSetPollingInterruptAccess();\r
+\r
+ /* Call the periodic timer test, which tests the timer API functions that\r
+ can be called from an ISR. */\r
+ #if( configUSE_PREEMPTION != 0 )\r
+ {\r
+ /* Only created when preemption is used. */\r
+ vTimerPeriodicISRTests();\r
+ }\r
+ #endif\r
+\r
+ /* Writes to stream buffer byte by byte to test the stream buffer trigger\r
+ level functionality. */\r
+ vPeriodicStreamBufferProcessing();\r
+\r
+ /* Writes a string to a string buffer four bytes at a time to demonstrate\r
+ a stream being sent from an interrupt to a task. */\r
+ vBasicStreamBufferSendFromISR();\r
+ }\r
+ #else /* mainENABLE_INT_QUEUE_TESTS */\r
+ {\r
+ /* Access queues from interrupt. Make sure to access after the queues have\r
+ been created. */\r
+ if( xTimerForQueueTestInitialized == pdTRUE )\r
+ {\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+ }\r
+ }\r
+ #endif /* mainENABLE_INT_QUEUE_TESTS */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembly, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembly. */\r
+ vRegTest1();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check task will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembly, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembly. */\r
+ vRegTest2();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check task will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.0.1\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#include "FreeRTOSConfig.h"\r
+//#include "ISR_Support.h"\r
+\r
+ .extern ulRegTest1Counter\r
+ .extern ulRegTest2Counter\r
+ .extern vPortYield\r
+ \r
+ .global vRegTest1\r
+ .global vRegTest2\r
+\r
+ .text\r
+ .align 4\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vRegTest1:\r
+\r
+ /* Set initial values into the general purpose registers. */\r
+ /* a0 = return address, a1 = stack pointer. */\r
+#ifdef __XTENSA_WINDOWED_ABI__\r
+ entry a1, 64\r
+ s32i a0, a1, 0 /* Save return address */\r
+#else\r
+ addi a1, a1, -64\r
+ s32i a0, a1, 0 /* Save return address */\r
+ s32i a12, a1, 4 /* Save callee-saved regs if call0 ABI */\r
+ s32i a13, a1, 8\r
+ s32i a14, a1, 12\r
+ s32i a15, a1, 16\r
+#endif\r
+ movi a2, 0x11111111\r
+ movi a3, 0x22222222\r
+ movi a4, 0x33333333\r
+ movi a5, 0x44444444\r
+ movi a6, 0x55555555\r
+ movi a7, 0x66666666\r
+ movi a8, 0x77777777\r
+ movi a9, 0x88888888\r
+ movi a10, 0x99999999\r
+ movi a11, 0xaaaaaaaa\r
+ movi a12, 0xbbbbbbbb\r
+ movi a13, 0xcccccccc\r
+ movi a14, 0xdddddddd\r
+ movi a15, 0xeeeeeeee\r
+\r
+_RegTest1Loop:\r
+\r
+ /* Loop checking the values originally loaded into the general purpose\r
+ registers remain through the life of the task. */\r
+ movi a0, 0x11111111\r
+ bne a0, a2, _RegTest1Error\r
+ movi a0, 0x22222222\r
+ bne a0, a3, _RegTest1Error\r
+ movi a0, 0x33333333\r
+ bne a0, a4, _RegTest1Error\r
+ movi a0, 0x44444444\r
+ bne a0, a5, _RegTest1Error\r
+ movi a0, 0x55555555\r
+ bne a0, a6, _RegTest1Error\r
+ movi a0, 0x66666666\r
+ bne a0, a7, _RegTest1Error\r
+ movi a0, 0x77777777\r
+ bne a0, a8, _RegTest1Error\r
+ movi a0, 0x88888888\r
+ bne a0, a9, _RegTest1Error\r
+ movi a0, 0x99999999\r
+ bne a0, a10, _RegTest1Error\r
+ movi a0, 0xaaaaaaaa\r
+ bne a0, a11, _RegTest1Error\r
+ movi a0, 0xbbbbbbbb\r
+ bne a0, a12, _RegTest1Error\r
+ movi a0, 0xcccccccc\r
+ bne a0, a13, _RegTest1Error\r
+ movi a0, 0xdddddddd\r
+ bne a0, a14, _RegTest1Error\r
+ movi a0, 0xeeeeeeee\r
+ bne a0, a15, _RegTest1Error\r
+\r
+ /* Incrememnt the loop counter to prove this task has not gone into the\r
+ error null loop. */\r
+ s32i a2, a1, 20\r
+ movi a2, ulRegTest1Counter\r
+ l32i a0, a2, 0\r
+ addi a0, a0, 1\r
+ s32i a0, a2, 0\r
+ l32i a2, a1, 20\r
+\r
+ /* Loop again. */\r
+ j _RegTest1Loop\r
+\r
+_RegTest1Error:\r
+.L1:\r
+ j .L1\r
+\r
+\r
+ .align 4\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vRegTest2:\r
+\r
+ /* Set initial values into the general purpose registers. */\r
+ /* a0 = return address, a1 = stack pointer. */\r
+#ifdef __XTENSA_WINDOWED_ABI__\r
+ entry a1, 64\r
+ s32i a0, a1, 0 /* Save return address */\r
+#else\r
+ addi a1, a1, -64\r
+ s32i a0, a1, 0 /* Save return address */\r
+ s32i a12, a1, 4 /* Save callee-saved regs if call0 ABI */\r
+ s32i a13, a1, 8\r
+ s32i a14, a1, 12\r
+ s32i a15, a1, 16\r
+#endif\r
+\r
+_ReInit:\r
+\r
+ movi a2, 0x01010101\r
+ movi a3, 0x02020202\r
+ movi a4, 0x03030303\r
+ movi a5, 0x04040404\r
+ movi a6, 0x05050505\r
+ movi a7, 0x06060606\r
+ movi a8, 0x07070707\r
+ movi a9, 0x08080808\r
+ movi a10, 0x09090909\r
+ movi a11, 0x0a0a0a0a\r
+ movi a12, 0x0b0b0b0b\r
+ movi a13, 0x0c0c0c0c\r
+ movi a14, 0x0d0d0d0d\r
+ movi a15, 0x0e0e0e0e\r
+\r
+_RegTest2Loop:\r
+\r
+ /* Loop checking the values originally loaded into the general purpose\r
+ registers remain through the life of the task. */\r
+ movi a0, 0x01010101\r
+ bne a0, a2, _RegTest1Error\r
+ movi a0, 0x02020202\r
+ bne a0, a3, _RegTest1Error\r
+ movi a0, 0x03030303\r
+ bne a0, a4, _RegTest1Error\r
+ movi a0, 0x04040404\r
+ bne a0, a5, _RegTest1Error\r
+ movi a0, 0x05050505\r
+ bne a0, a6, _RegTest1Error\r
+ movi a0, 0x06060606\r
+ bne a0, a7, _RegTest1Error\r
+ movi a0, 0x07070707\r
+ bne a0, a8, _RegTest1Error\r
+ movi a0, 0x08080808\r
+ bne a0, a9, _RegTest1Error\r
+ movi a0, 0x09090909\r
+ bne a0, a10, _RegTest1Error\r
+ movi a0, 0x0a0a0a0a\r
+ bne a0, a11, _RegTest1Error\r
+ movi a0, 0x0b0b0b0b\r
+ bne a0, a12, _RegTest1Error\r
+ movi a0, 0x0c0c0c0c\r
+ bne a0, a13, _RegTest1Error\r
+ movi a0, 0x0d0d0d0d\r
+ bne a0, a14, _RegTest1Error\r
+ movi a0, 0x0e0e0e0e\r
+ bne a0, a15, _RegTest1Error\r
+\r
+ /* Force a yield from one of the reg test tasks to increase coverage. */\r
+ /* IMPORTANT: this call will trash some number of registers. Branch */\r
+ /* to _ReInit to set things up again. */\r
+#ifdef __XTENSA_WINDOWED_ABI__\r
+ call8 vPortYield\r
+#else\r
+ call0 vPortYield\r
+#endif\r
+\r
+ /* Increment the loop counter to prove this task has not gone into the\r
+ error null loop. */\r
+ s32i a2, a1, 20\r
+ movi a2, ulRegTest2Counter\r
+ l32i a0, a2, 0\r
+ addi a0, a0, 1\r
+ s32i a0, a2, 0\r
+ l32i a2, a1, 20\r
+\r
+ /* Loop again. */\r
+ j _ReInit /* See comments above */\r
+ /* j _RegTest2Loop */\r
+\r
+_RegTest2Error:\r
+.L2:\r
+ j .L2\r
+\r
--- /dev/null
+### Makefile to build the FreeRTOS library ###\r
+\r
+# Build target (options: sim, board)\r
+\r
+TARGET = sim\r
+SMALL =\r
+\r
+# Tools\r
+\r
+CC = xt-xcc\r
+AS = xt-xcc\r
+AR = xt-ar\r
+XT_CORE = $(patsubst %-params,%,$(notdir $(shell xt-xcc --show-config=core)))\r
+CONFIGDIR = $(shell xt-xcc --show-config=config)\r
+\r
+# For platform-specific commands\r
+\r
+include $(CONFIGDIR)/misc/hostenv.mk\r
+\r
+# Source code and build locations\r
+\r
+SRCROOT = $(subst /,$(S),$(CURDIR))\r
+TSTROOT = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)demos$(S)cadence$(S)sim$(SMALL))\r
+BLDROOT = $(TSTROOT)$(S)build\r
+BLDDIR = $(BLDROOT)$(S)$(XT_CORE)\r
+\r
+FR_SRCDIR = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..)\r
+FR_SRCDIR2 = $(FR_SRCDIR)$(S)portable$(S)MemMang\r
+XT_SRCDIR = $(SRCROOT)\r
+\r
+vpath %.c $(FR_SRCDIR) $(FR_SRCDIR2) $(XT_SRCDIR)\r
+vpath %.S $(XT_SRCDIR)\r
+\r
+# File lists\r
+\r
+FR_C_FILES = $(notdir $(wildcard $(FR_SRCDIR)/*.c)) $(notdir $(wildcard $(FR_SRCDIR2)/*.c))\r
+XT_C_FILES = $(notdir $(wildcard $(XT_SRCDIR)/*.c))\r
+XT_S_FILES = $(notdir $(wildcard $(XT_SRCDIR)/*.S))\r
+\r
+# List of all .o files that will go into the library\r
+\r
+LIB_C_O = $(patsubst %.c,%.o,$(XT_C_FILES) $(FR_C_FILES))\r
+LIB_S_O = $(patsubst %.S,%.o,$(XT_S_FILES))\r
+LIB_O_LIST = $(addprefix $(BLDDIR)/,$(LIB_C_O) $(LIB_S_O))\r
+\r
+# Output files\r
+\r
+OSLIB = $(BLDDIR)$(S)libfreertos.a\r
+\r
+# Build options\r
+\r
+ifeq ($(TARGET),sim)\r
+DFLAGS = -DXT_SIMULATOR\r
+endif\r
+ifeq ($(TARGET),board)\r
+DFLAGS = -DXT_BOARD\r
+endif\r
+\r
+IFLAGS = \\r
+ -I$(FR_SRCDIR)$(S)..$(S)include -I$(FR_SRCDIR)$(S)..$(S)include$(S)private \\r
+ -I$(XT_SRCDIR) -I$(TSTROOT)$(S)common$(S)config_files -I$(BLDDIR)\r
+\r
+CFLAGS = -O2 -g\r
+CCFLAGS = $(CFLAGS) -Wall -mno-coproc -mlongcalls -ffunction-sections -mno-l32r-flix $(DFLAGS)\r
+ASFLAGS = $(CCFLAGS)\r
+\r
+# Include dependency rules (generated using -MD)\r
+\r
+-include $(wildcard $(BLDDIR)/*.d)\r
+\r
+# Targets\r
+\r
+all : mkdir $(OSLIB)\r
+\r
+mkdir : $(BLDDIR)/.mkdir\r
+\r
+$(BLDDIR)/.mkdir :\r
+ @$(MKPATH) $(BLDDIR)\r
+ @echo "" > $@\r
+ -$(CP) $(CONFIGDIR)/xtensa-elf/include/sys/reent.h $(BLDDIR)/reent.h\r
+\r
+$(OSLIB) : $(LIB_O_LIST)\r
+ $(AR) -rs $@ $^\r
+\r
+$(BLDDIR)/%.o : %.c\r
+ $(CC) $(CCFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<\r
+\r
+$(BLDDIR)/%.o : %.S\r
+ $(CC) $(ASFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<\r
+\r
+clean :\r
+ $(RM_R) $(BLDDIR)\r
+\r
+clean_all :\r
+ $(RM_R) $(BLDROOT)\r
+\r
+.PHONY : all mkdir clean clean_all\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*******************************************************************************\r
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <xtensa/config/core.h>\r
+\r
+#include "xtensa_rtos.h"\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+\r
+/* Defined in portasm.h */\r
+extern void _frxt_tick_timer_init(void);\r
+\r
+/* Defined in xtensa_context.S */\r
+extern void _xt_coproc_init(void);\r
+/*-----------------------------------------------------------*/\r
+\r
+/* We require the address of the pxCurrentTCB variable, but don't want to know\r
+any details of its type. */\r
+typedef void TCB_t;\r
+extern volatile TCB_t * volatile pxCurrentTCB;\r
+\r
+unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting\r
+unsigned port_interruptNesting = 0; // Interrupt nesting level\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+// User exception dispatcher when exiting\r
+void _xt_user_exit(void);\r
+\r
+/*\r
+ * Stack initialization\r
+ */\r
+#if portUSING_MPU_WRAPPERS\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
+#else\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+#endif\r
+{\r
+ StackType_t *sp, *tp;\r
+ XtExcFrame *frame;\r
+ #if XCHAL_CP_NUM > 0\r
+ uint32_t *p;\r
+ #endif\r
+\r
+ /* Create interrupt stack frame aligned to 16 byte boundary */\r
+ sp = (StackType_t *) (((UBaseType_t)(pxTopOfStack + 1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);\r
+\r
+ /* Clear the entire frame (do not use memset() because we don't depend on C library) */\r
+ for (tp = sp; tp <= pxTopOfStack; ++tp)\r
+ *tp = 0;\r
+\r
+ frame = (XtExcFrame *) sp;\r
+\r
+ /* Explicitly initialize certain saved registers */\r
+ frame->pc = (UBaseType_t) pxCode; /* task entrypoint */\r
+ frame->a0 = 0; /* to terminate GDB backtrace */\r
+ frame->a1 = (UBaseType_t) sp + XT_STK_FRMSZ; /* physical top of stack frame */\r
+ frame->exit = (UBaseType_t) _xt_user_exit; /* user exception exit dispatcher */\r
+\r
+ /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */\r
+ /* Also set entry point argument parameter. */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ frame->a2 = (UBaseType_t) pvParameters;\r
+ frame->ps = PS_UM | PS_EXCM;\r
+ #else\r
+ /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */\r
+ frame->a6 = (UBaseType_t) pvParameters;\r
+ frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);\r
+ #endif\r
+\r
+ #ifdef XT_USE_SWPRI\r
+ /* Set the initial virtual priority mask value to all 1's. */\r
+ frame->vpri = 0xFFFFFFFF;\r
+ #endif\r
+\r
+ #if XCHAL_CP_NUM > 0\r
+ /* Init the coprocessor save area (see xtensa_context.h) */\r
+ /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.\r
+ * //p = (uint32_t *) xMPUSettings->coproc_area;\r
+ */\r
+ p = (uint32_t *)(((uint32_t) pxTopOfStack - XT_CP_SIZE) & ~0xf);\r
+ p[0] = 0;\r
+ p[1] = 0;\r
+ p[2] = (((uint32_t) p) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN;\r
+ #endif\r
+\r
+ return sp;\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the Xtensa port will get stopped. If required simply\r
+ disable the tick interrupt here. */\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+ // Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored\r
+\r
+ #if XCHAL_CP_NUM > 0\r
+ /* Initialize co-processor management for tasks. Leave CPENABLE alone. */\r
+ _xt_coproc_init();\r
+ #endif\r
+\r
+ /* Init the tick divisor value */\r
+ _xt_tick_divisor_init();\r
+\r
+ /* Setup the hardware to generate the tick. */\r
+ _frxt_tick_timer_init();\r
+\r
+ #if XT_USE_THREAD_SAFE_CLIB\r
+ // Init C library\r
+ vPortClibInit();\r
+ #endif\r
+\r
+ port_xSchedulerRunning = 1;\r
+\r
+ // Cannot be directly called from C; never returns\r
+ __asm__ volatile ("call0 _frxt_dispatch\n");\r
+\r
+ /* Should not get here. */\r
+ return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortSysTickHandler( void )\r
+{\r
+ BaseType_t ret;\r
+ unsigned interruptMask;\r
+\r
+ portbenchmarkIntLatency();\r
+\r
+ /* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be\r
+ * disabled before calling xTaskIncrementTick as it access the\r
+ * kernel lists. */\r
+ interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ ret = xTaskIncrementTick();\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );\r
+\r
+ portYIELD_FROM_ISR( ret );\r
+\r
+ return ret;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.\r
+ */\r
+#if portUSING_MPU_WRAPPERS\r
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+{\r
+ #if XCHAL_CP_NUM > 0\r
+ xMPUSettings->coproc_area = (StackType_t*)((((uint32_t)(pxBottomOfStack + ulStackDepth - 1)) - XT_CP_SIZE ) & ~0xf);\r
+\r
+\r
+ /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to\r
+ * clear the stack area after we return. This is done in pxPortInitialiseStack().\r
+ */\r
+ #endif\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+//-----------------------------------------------------------------------------\r
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+//-----------------------------------------------------------------------------\r
+*/\r
+\r
+#include "xtensa_rtos.h"\r
+\r
+#define TOPOFSTACK_OFFS 0x00 /* StackType_t *pxTopOfStack */\r
+#define CP_TOPOFSTACK_OFFS 0x04 /* xMPU_SETTINGS.coproc_area */\r
+\r
+.extern pxCurrentTCB\r
+\r
+\r
+/*\r
+*******************************************************************************\r
+* Interrupt stack. The size of the interrupt stack is determined by the config\r
+* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h\r
+*******************************************************************************\r
+*/\r
+ .data\r
+ .align 16\r
+ .global port_IntStack\r
+port_IntStack:\r
+ .space configISR_STACK_SIZE\r
+port_IntStackTop:\r
+ .word 0\r
+port_switch_flag:\r
+ .word 0\r
+\r
+ .text\r
+/*\r
+*******************************************************************************\r
+* _frxt_setup_switch\r
+* void _frxt_setup_switch(void);\r
+* \r
+* Sets an internal flag indicating that a task switch is required on return\r
+* from interrupt handling.\r
+* \r
+*******************************************************************************\r
+*/\r
+ .global _frxt_setup_switch\r
+ .type _frxt_setup_switch,@function\r
+ .align 4\r
+_frxt_setup_switch:\r
+\r
+ ENTRY(16)\r
+\r
+ movi a2, port_switch_flag\r
+ movi a3, 1\r
+ s32i a3, a2, 0\r
+\r
+ RET(16)\r
+\r
+/*\r
+*******************************************************************************\r
+* _frxt_int_enter\r
+* void _frxt_int_enter(void)\r
+*\r
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for\r
+* freeRTOS. Saves the rest of the interrupt context (not already saved).\r
+* May only be called from assembly code by the 'call0' instruction, with\r
+* interrupts disabled.\r
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.\r
+*\r
+*******************************************************************************\r
+*/\r
+ .globl _frxt_int_enter\r
+ .type _frxt_int_enter,@function\r
+ .align 4\r
+_frxt_int_enter:\r
+\r
+ /* Save a12-13 in the stack frame as required by _xt_context_save. */\r
+ s32i a12, a1, XT_STK_A12\r
+ s32i a13, a1, XT_STK_A13\r
+\r
+ /* Save return address in a safe place (free a0). */\r
+ mov a12, a0\r
+\r
+ /* Save the rest of the interrupted context (preserves A12-13). */\r
+ call0 _xt_context_save\r
+\r
+ /*\r
+ Save interrupted task's SP in TCB only if not nesting.\r
+ Manage nesting directly rather than call the generic IntEnter()\r
+ (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).\r
+ */\r
+ movi a2, port_xSchedulerRunning\r
+ movi a3, port_interruptNesting\r
+ l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */\r
+ beqz a2, 1f /* scheduler not running, no tasks */\r
+ l32i a2, a3, 0 /* a2 = port_interruptNesting */\r
+ addi a2, a2, 1 /* increment nesting count */\r
+ s32i a2, a3, 0 /* save nesting count */\r
+ bnei a2, 1, .Lnested /* !=0 before incr, so nested */\r
+\r
+ movi a2, pxCurrentTCB\r
+ l32i a2, a2, 0 /* a2 = current TCB */\r
+ beqz a2, 1f\r
+ s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */\r
+ movi a1, port_IntStackTop /* a1 = top of intr stack */\r
+\r
+.Lnested:\r
+1:\r
+ mov a0, a12 /* restore return addr and return */\r
+ ret\r
+\r
+/*\r
+*******************************************************************************\r
+* _frxt_int_exit\r
+* void _frxt_int_exit(void)\r
+*\r
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for\r
+* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context\r
+* switching, restore the (possibly) new task's context, and return to the\r
+* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.\r
+* May only be called from assembly code by the 'call0' instruction. Does not\r
+* return to caller.\r
+* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.\r
+*\r
+*******************************************************************************\r
+*/\r
+ .globl _frxt_int_exit\r
+ .type _frxt_int_exit,@function\r
+ .align 4\r
+_frxt_int_exit:\r
+\r
+ movi a2, port_xSchedulerRunning\r
+ movi a3, port_interruptNesting\r
+ rsil a0, XCHAL_EXCM_LEVEL /* lock out interrupts */\r
+ l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */\r
+ beqz a2, .Lnoswitch /* scheduler not running, no tasks */\r
+ l32i a2, a3, 0 /* a2 = port_interruptNesting */\r
+ addi a2, a2, -1 /* decrement nesting count */\r
+ s32i a2, a3, 0 /* save nesting count */\r
+ bnez a2, .Lnesting /* !=0 after decr so still nested */\r
+\r
+ movi a2, pxCurrentTCB\r
+ l32i a2, a2, 0 /* a2 = current TCB */\r
+ beqz a2, 1f /* no task ? go to dispatcher */\r
+ l32i a1, a2, TOPOFSTACK_OFFS /* SP = pxCurrentTCB->pxTopOfStack */\r
+\r
+ movi a2, port_switch_flag /* address of switch flag */\r
+ l32i a3, a2, 0 /* a3 = port_switch_flag */\r
+ beqz a3, .Lnoswitch /* flag = 0 means no switch reqd */\r
+ movi a3, 0\r
+ s32i a3, a2, 0 /* zero out the flag for next time */\r
+\r
+1:\r
+ /*\r
+ Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.\r
+ However a12-13 were already saved by _frxt_int_enter().\r
+ */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ s32i a14, a1, XT_STK_A14\r
+ s32i a15, a1, XT_STK_A15\r
+ #endif\r
+\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ call0 vPortYieldFromInt /* call dispatch inside the function; never returns */\r
+ #else\r
+ call4 vPortYieldFromInt /* this one returns */\r
+ call0 _frxt_dispatch /* tail-call dispatcher */\r
+ /* Never returns here. */\r
+ #endif\r
+\r
+.Lnoswitch:\r
+ /*\r
+ If we came here then about to resume the interrupted task.\r
+ */\r
+\r
+.Lnesting:\r
+ /*\r
+ We come here only if there was no context switch, that is if this\r
+ is a nested interrupt, or the interrupted task was not preempted.\r
+ In either case there's no need to load the SP.\r
+ */\r
+\r
+ /* Restore full context from interrupt stack frame */\r
+ call0 _xt_context_restore\r
+\r
+ /*\r
+ Must return via the exit dispatcher corresponding to the entrypoint from which\r
+ this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt\r
+ stack frame is deallocated in the exit dispatcher.\r
+ */\r
+ l32i a0, a1, XT_STK_EXIT\r
+ ret\r
+\r
+\r
+/*\r
+**********************************************************************************************************\r
+* _frxt_timer_int\r
+* void _frxt_timer_int(void)\r
+*\r
+* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.\r
+* Called every timer interrupt.\r
+* Manages the tick timer and calls xPortSysTickHandler() every tick.\r
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.\r
+*\r
+* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.\r
+*\r
+**********************************************************************************************************\r
+*/\r
+ .globl _frxt_timer_int\r
+ .type _frxt_timer_int,@function\r
+ .align 4\r
+_frxt_timer_int:\r
+\r
+ /*\r
+ Xtensa timers work by comparing a cycle counter with a preset value. Once the match occurs\r
+ an interrupt is generated, and the handler has to set a new cycle count into the comparator.\r
+ To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,\r
+ not the time the interrupt was serviced. However if a timer interrupt is ever serviced more\r
+ than one tick late, it is necessary to process multiple ticks until the new cycle count is\r
+ in the future, otherwise the next timer interrupt would not occur until after the cycle\r
+ counter had wrapped (2^32 cycles later).\r
+\r
+ do {\r
+ ticks++;\r
+ old_ccompare = read_ccompare_i();\r
+ write_ccompare_i( old_ccompare + divisor );\r
+ service one tick;\r
+ diff = read_ccount() - old_ccompare;\r
+ } while ( diff > divisor );\r
+ */\r
+\r
+ ENTRY(16)\r
+\r
+.L_xt_timer_int_catchup:\r
+\r
+ /* Update the timer comparator for the next tick. */\r
+ #ifdef XT_CLOCK_FREQ\r
+ movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */\r
+ #else\r
+ movi a3, _xt_tick_divisor\r
+ l32i a2, a3, 0 /* a2 = comparator increment */\r
+ #endif\r
+ rsr a3, XT_CCOMPARE /* a3 = old comparator value */\r
+ add a4, a3, a2 /* a4 = new comparator value */\r
+ wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */\r
+ esync\r
+\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ /* Preserve a2 and a3 across C calls. */\r
+ s32i a2, sp, 4\r
+ s32i a3, sp, 8\r
+ #endif\r
+\r
+ /* Call the FreeRTOS tick handler (see port.c). */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ call0 xPortSysTickHandler\r
+ #else\r
+ call4 xPortSysTickHandler\r
+ #endif\r
+\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ /* Restore a2 and a3. */\r
+ l32i a2, sp, 4\r
+ l32i a3, sp, 8\r
+ #endif\r
+\r
+ /* Check if we need to process more ticks to catch up. */\r
+ esync /* ensure comparator update complete */\r
+ rsr a4, CCOUNT /* a4 = cycle count */\r
+ sub a4, a4, a3 /* diff = ccount - old comparator */\r
+ blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */\r
+\r
+ RET(16)\r
+\r
+ /*\r
+**********************************************************************************************************\r
+* _frxt_tick_timer_init\r
+* void _frxt_tick_timer_init(void)\r
+*\r
+* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).\r
+* Callable from C (obeys ABI conventions on entry).\r
+*\r
+**********************************************************************************************************\r
+*/\r
+ .globl _frxt_tick_timer_init\r
+ .type _frxt_tick_timer_init,@function\r
+ .align 4\r
+_frxt_tick_timer_init:\r
+\r
+ ENTRY(16)\r
+\r
+ /* Set up the periodic tick timer (assume enough time to complete init). */\r
+ #ifdef XT_CLOCK_FREQ\r
+ movi a3, XT_TICK_DIVISOR\r
+ #else\r
+ movi a2, _xt_tick_divisor\r
+ l32i a3, a2, 0\r
+ #endif\r
+ rsr a2, CCOUNT /* current cycle count */\r
+ add a2, a2, a3 /* time of first timer interrupt */\r
+ wsr a2, XT_CCOMPARE /* set the comparator */\r
+\r
+ /*\r
+ Enable the timer interrupt at the device level. Don't write directly\r
+ to the INTENABLE register because it may be virtualized.\r
+ */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ movi a2, XT_TIMER_INTEN\r
+ call0 xt_ints_on\r
+ #else\r
+ movi a6, XT_TIMER_INTEN\r
+ call4 xt_ints_on\r
+ #endif\r
+\r
+ RET(16)\r
+\r
+/*\r
+**********************************************************************************************************\r
+* DISPATCH THE HIGH READY TASK\r
+* void _frxt_dispatch(void)\r
+*\r
+* Switch context to the highest priority ready task, restore its state and dispatch control to it.\r
+*\r
+* This is a common dispatcher that acts as a shared exit path for all the context switch functions\r
+* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher\r
+* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).\r
+*\r
+* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see\r
+* comments on stack frames in xtensa_context.h). This function restores the state accordingly.\r
+* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.\r
+* If restoring a task that was preempted, restores all state including the task's CPENABLE.\r
+*\r
+* Entry:\r
+* pxCurrentTCB points to the TCB of the task to suspend,\r
+* Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.\r
+*\r
+* Exit:\r
+* If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().\r
+* If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.\r
+*\r
+**********************************************************************************************************\r
+*/\r
+ .globl _frxt_dispatch\r
+ .type _frxt_dispatch,@function\r
+ .align 4\r
+_frxt_dispatch:\r
+\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ call0 vTaskSwitchContext // Get next TCB to resume\r
+ movi a2, pxCurrentTCB\r
+ #else\r
+ movi a2, pxCurrentTCB\r
+ call4 vTaskSwitchContext // Get next TCB to resume\r
+ #endif\r
+ l32i a3, a2, 0\r
+ l32i sp, a3, TOPOFSTACK_OFFS /* SP = next_TCB->pxTopOfStack; */\r
+ s32i a3, a2, 0\r
+\r
+ /* Determine the type of stack frame. */\r
+ l32i a2, sp, XT_STK_EXIT /* exit dispatcher or solicited flag */\r
+ bnez a2, .L_frxt_dispatch_stk\r
+\r
+.L_frxt_dispatch_sol:\r
+\r
+ /* Solicited stack frame. Restore minimal context and return from vPortYield(). */\r
+ l32i a3, sp, XT_SOL_PS\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ l32i a12, sp, XT_SOL_A12\r
+ l32i a13, sp, XT_SOL_A13\r
+ l32i a14, sp, XT_SOL_A14\r
+ l32i a15, sp, XT_SOL_A15\r
+ #endif\r
+ l32i a0, sp, XT_SOL_PC\r
+ #if XCHAL_CP_NUM > 0\r
+ /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */\r
+ rsync\r
+ #endif\r
+ /* As soons as PS is restored, interrupts can happen. No need to sync PS. */\r
+ wsr a3, PS\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ addi sp, sp, XT_SOL_FRMSZ\r
+ ret\r
+ #else\r
+ retw\r
+ #endif\r
+\r
+.L_frxt_dispatch_stk:\r
+\r
+ #if XCHAL_CP_NUM > 0\r
+ /* Restore CPENABLE from task's co-processor save area. */\r
+ movi a3, pxCurrentTCB /* cp_state = */\r
+ l32i a3, a3, 0\r
+ l32i a2, a3, CP_TOPOFSTACK_OFFS /* StackType_t *pxStack; */\r
+ l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */\r
+ wsr a3, CPENABLE\r
+ #endif\r
+\r
+ /* Interrupt stack frame. Restore full context and return to exit dispatcher. */\r
+ call0 _xt_context_restore\r
+\r
+ /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ l32i a14, sp, XT_STK_A14\r
+ l32i a15, sp, XT_STK_A15\r
+ #endif\r
+\r
+ #if XCHAL_CP_NUM > 0\r
+ /* Ensure wsr.CPENABLE has completed. */\r
+ rsync\r
+ #endif\r
+\r
+ /*\r
+ Must return via the exit dispatcher corresponding to the entrypoint from which\r
+ this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt\r
+ stack frame is deallocated in the exit dispatcher.\r
+ */\r
+ l32i a0, sp, XT_STK_EXIT\r
+ ret\r
+\r
+\r
+/*\r
+**********************************************************************************************************\r
+* PERFORM A SOLICTED CONTEXT SWITCH (from a task)\r
+* void vPortYield(void)\r
+*\r
+* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,\r
+* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch\r
+*\r
+* At Entry:\r
+* pxCurrentTCB points to the TCB of the task to suspend\r
+* Callable from C (obeys ABI conventions on entry).\r
+*\r
+* Does not return to caller.\r
+*\r
+**********************************************************************************************************\r
+*/\r
+ .globl vPortYield\r
+ .type vPortYield,@function\r
+ .align 4\r
+vPortYield:\r
+\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ addi sp, sp, -XT_SOL_FRMSZ\r
+ #else\r
+ entry sp, XT_SOL_FRMSZ\r
+ #endif\r
+\r
+ rsr a2, PS\r
+ s32i a0, sp, XT_SOL_PC\r
+ s32i a2, sp, XT_SOL_PS\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ s32i a12, sp, XT_SOL_A12 /* save callee-saved registers */\r
+ s32i a13, sp, XT_SOL_A13\r
+ s32i a14, sp, XT_SOL_A14\r
+ s32i a15, sp, XT_SOL_A15\r
+ #else\r
+ /* Spill register windows. Calling xthal_window_spill() causes extra */\r
+ /* spills and reloads, so we will set things up to call the _nw version */\r
+ /* instead to save cycles. */\r
+ movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) /* spills a4-a7 if needed */\r
+ and a2, a2, a6 /* clear WOE, INTLEVEL */\r
+ addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */\r
+ wsr a2, PS\r
+ rsync\r
+ call0 xthal_window_spill_nw\r
+ l32i a2, sp, XT_SOL_PS /* restore PS */\r
+ wsr a2, PS\r
+ #endif\r
+\r
+ rsil a2, XCHAL_EXCM_LEVEL /* disable low/med interrupts */\r
+\r
+ #if XCHAL_CP_NUM > 0\r
+ /* Save coprocessor callee-saved state (if any). At this point CPENABLE */\r
+ /* should still reflect which CPs were in use (enabled). */\r
+ call0 _xt_coproc_savecs\r
+ #endif\r
+\r
+ movi a2, pxCurrentTCB\r
+ movi a3, 0\r
+ l32i a2, a2, 0 /* a2 = pxCurrentTCB */\r
+ s32i a3, sp, XT_SOL_EXIT /* 0 to flag as solicited frame */\r
+ s32i sp, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */\r
+\r
+ #if XCHAL_CP_NUM > 0\r
+ /* Clear CPENABLE, also in task's co-processor state save area. */\r
+ l32i a2, a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state */\r
+ movi a3, 0\r
+ wsr a3, CPENABLE\r
+ beqz a2, 1f\r
+ s16i a3, a2, XT_CPENABLE /* clear saved cpenable */\r
+1:\r
+ #endif\r
+\r
+ /* Tail-call dispatcher. */\r
+ call0 _frxt_dispatch\r
+ /* Never reaches here. */\r
+\r
+\r
+/*\r
+**********************************************************************************************************\r
+* PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)\r
+* void vPortYieldFromInt(void)\r
+*\r
+* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher\r
+* _frxt_dispatch() to perform the actual context switch.\r
+*\r
+* At Entry:\r
+* Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.\r
+* pxCurrentTCB points to the TCB of the task to suspend,\r
+* Callable from C (obeys ABI conventions on entry).\r
+*\r
+* At Exit:\r
+* Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.\r
+* Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.\r
+*\r
+**********************************************************************************************************\r
+*/\r
+ .globl vPortYieldFromInt\r
+ .type vPortYieldFromInt,@function\r
+ .align 4\r
+vPortYieldFromInt:\r
+\r
+ ENTRY(16)\r
+\r
+ #if XCHAL_CP_NUM > 0\r
+ /* Save CPENABLE in task's co-processor save area, and clear CPENABLE. */\r
+ movi a3, pxCurrentTCB /* cp_state = */\r
+ l32i a3, a3, 0\r
+ l32i a2, a3, CP_TOPOFSTACK_OFFS\r
+\r
+ rsr a3, CPENABLE\r
+ s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */\r
+ movi a3, 0\r
+ wsr a3, CPENABLE /* disable all co-processors */\r
+ #endif\r
+\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ /* Tail-call dispatcher. */\r
+ call0 _frxt_dispatch\r
+ /* Never reaches here. */\r
+ #else\r
+ RET(16)\r
+ #endif\r
+\r
+/*\r
+**********************************************************************************************************\r
+* _frxt_task_coproc_state\r
+* void _frxt_task_coproc_state(void)\r
+*\r
+* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.\r
+*\r
+* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).\r
+* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.\r
+* Returns in A15 a pointer to the base of the co-processor state save area for the current task.\r
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.\r
+*\r
+**********************************************************************************************************\r
+*/\r
+#if XCHAL_CP_NUM > 0\r
+\r
+ .globl _frxt_task_coproc_state\r
+ .type _frxt_task_coproc_state,@function\r
+ .align 4\r
+_frxt_task_coproc_state:\r
+\r
+ movi a15, port_xSchedulerRunning /* if (port_xSchedulerRunning */\r
+ l32i a15, a15, 0\r
+ beqz a15, 1f\r
+ movi a15, port_interruptNesting /* && port_interruptNesting == 0 */\r
+ l32i a15, a15, 0\r
+ bnez a15, 1f\r
+ movi a15, pxCurrentTCB\r
+ l32i a15, a15, 0 /* && pxCurrentTCB != 0) { */\r
+ beqz a15, 2f\r
+ l32i a15, a15, CP_TOPOFSTACK_OFFS\r
+ ret\r
+\r
+1: movi a15, 0\r
+2: ret\r
+\r
+#endif /* XCHAL_CP_NUM > 0 */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+/*\r
+ * This utility helps benchmarking interrupt latency and context switches.\r
+ * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.\r
+ * You will also need to download the FreeRTOS_trace patch that contains\r
+ * portbenchmark.c and the complete version of portbenchmark.h\r
+ */\r
+\r
+#ifndef PORTBENCHMARK_H\r
+#define PORTBENCHMARK_H\r
+\r
+#if configBENCHMARK\r
+ #error "You need to download the FreeRTOS_trace patch that overwrites this file"\r
+#endif\r
+\r
+#define portbenchmarkINTERRUPT_DISABLE()\r
+#define portbenchmarkINTERRUPT_RESTORE(newstate)\r
+#define portbenchmarkIntLatency()\r
+#define portbenchmarkIntWait()\r
+#define portbenchmarkReset()\r
+#define portbenchmarkPrint()\r
+\r
+#endif /* PORTBENCHMARK */\r
--- /dev/null
+/*******************************************************************************\r
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+\r
+#if XT_USE_THREAD_SAFE_CLIB\r
+\r
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB\r
+\r
+#include <errno.h>\r
+#include <sys/reent.h>\r
+\r
+#include "semphr.h"\r
+\r
+typedef SemaphoreHandle_t _Rmtx;\r
+\r
+//-----------------------------------------------------------------------------\r
+// Override this and set to nonzero to enable locking.\r
+//-----------------------------------------------------------------------------\r
+int32_t _xclib_use_mt = 1;\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Init lock.\r
+//-----------------------------------------------------------------------------\r
+void\r
+_Mtxinit(_Rmtx * mtx)\r
+{\r
+ *mtx = xSemaphoreCreateRecursiveMutex();\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Destroy lock.\r
+//-----------------------------------------------------------------------------\r
+void\r
+_Mtxdst(_Rmtx * mtx)\r
+{\r
+ if ((mtx != NULL) && (*mtx != NULL)) {\r
+ vSemaphoreDelete(*mtx);\r
+ }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Lock.\r
+//-----------------------------------------------------------------------------\r
+void\r
+_Mtxlock(_Rmtx * mtx)\r
+{\r
+ if ((mtx != NULL) && (*mtx != NULL)) {\r
+ xSemaphoreTakeRecursive(*mtx, portMAX_DELAY);\r
+ }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Unlock.\r
+//-----------------------------------------------------------------------------\r
+void\r
+_Mtxunlock(_Rmtx * mtx)\r
+{\r
+ if ((mtx != NULL) && (*mtx != NULL)) {\r
+ xSemaphoreGiveRecursive(*mtx);\r
+ }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Called by malloc() to allocate blocks of memory from the heap.\r
+//-----------------------------------------------------------------------------\r
+void *\r
+_sbrk_r (struct _reent * reent, int32_t incr)\r
+{\r
+ extern char _end;\r
+ extern char _heap_sentry;\r
+ static char * _heap_sentry_ptr = &_heap_sentry;\r
+ static char * heap_ptr;\r
+ char * base;\r
+\r
+ if (!heap_ptr)\r
+ heap_ptr = (char *) &_end;\r
+\r
+ base = heap_ptr;\r
+ if (heap_ptr + incr >= _heap_sentry_ptr) {\r
+ reent->_errno = ENOMEM;\r
+ return (char *) -1;\r
+ }\r
+\r
+ heap_ptr += incr;\r
+ return base;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Global initialization for C library.\r
+//-----------------------------------------------------------------------------\r
+void\r
+vPortClibInit(void)\r
+{\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Per-thread cleanup stub provided for linking, does nothing.\r
+//-----------------------------------------------------------------------------\r
+void\r
+_reclaim_reent(void * ptr)\r
+{\r
+}\r
+\r
+#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */\r
+\r
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB\r
+\r
+#include <errno.h>\r
+#include <malloc.h>\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+#include "semphr.h"\r
+\r
+static SemaphoreHandle_t xClibMutex;\r
+static uint32_t ulClibInitDone = 0;\r
+\r
+//-----------------------------------------------------------------------------\r
+// Get C library lock.\r
+//-----------------------------------------------------------------------------\r
+void\r
+__malloc_lock(struct _reent * ptr)\r
+{\r
+ if (!ulClibInitDone)\r
+ return;\r
+\r
+ xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Release C library lock.\r
+//-----------------------------------------------------------------------------\r
+void\r
+__malloc_unlock(struct _reent * ptr)\r
+{\r
+ if (!ulClibInitDone)\r
+ return;\r
+\r
+ xSemaphoreGiveRecursive(xClibMutex);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Lock for environment. Since we have only one global lock we can just call\r
+// the malloc() lock function.\r
+//-----------------------------------------------------------------------------\r
+void\r
+__env_lock(struct _reent * ptr)\r
+{\r
+ __malloc_lock(ptr);\r
+}\r
+\r
+\r
+//-----------------------------------------------------------------------------\r
+// Unlock environment.\r
+//-----------------------------------------------------------------------------\r
+void\r
+__env_unlock(struct _reent * ptr)\r
+{\r
+ __malloc_unlock(ptr);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Called by malloc() to allocate blocks of memory from the heap.\r
+//-----------------------------------------------------------------------------\r
+void *\r
+_sbrk_r (struct _reent * reent, int32_t incr)\r
+{\r
+ extern char _end;\r
+ extern char _heap_sentry;\r
+ static char * _heap_sentry_ptr = &_heap_sentry;\r
+ static char * heap_ptr;\r
+ char * base;\r
+\r
+ if (!heap_ptr)\r
+ heap_ptr = (char *) &_end;\r
+\r
+ base = heap_ptr;\r
+ if (heap_ptr + incr >= _heap_sentry_ptr) {\r
+ reent->_errno = ENOMEM;\r
+ return (char *) -1;\r
+ }\r
+\r
+ heap_ptr += incr;\r
+ return base;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Global initialization for C library.\r
+//-----------------------------------------------------------------------------\r
+void\r
+vPortClibInit(void)\r
+{\r
+ configASSERT(!ulClibInitDone);\r
+\r
+ xClibMutex = xSemaphoreCreateRecursiveMutex();\r
+ ulClibInitDone = 1;\r
+}\r
+\r
+#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */\r
+\r
+#endif /* XT_USE_THREAD_SAFE_CLIB */\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifndef __ASSEMBLER__\r
+\r
+#include <stdint.h>\r
+\r
+#include <xtensa/tie/xt_core.h>\r
+#include <xtensa/hal.h>\r
+#include <xtensa/config/core.h>\r
+#include <xtensa/config/system.h> /* required for XSHAL_CLIB */\r
+#include <xtensa/xtruntime.h>\r
+\r
+//#include "xtensa_context.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+\r
+#define portCHAR int8_t\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG int32_t\r
+#define portSHORT int16_t\r
+#define portSTACK_TYPE uint8_t\r
+#define portBASE_TYPE int\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef portBASE_TYPE BaseType_t;\r
+typedef unsigned portBASE_TYPE UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+// portbenchmark\r
+#include "portbenchmark.h"\r
+\r
+/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */\r
+// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.\r
+#define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)\r
+#define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)\r
+\r
+// These can be nested\r
+#define portCRITICAL_NESTING_IN_TCB 1 // For now, let FreeRTOS' (tasks.c) manage critical nesting\r
+void vTaskEnterCritical(void);\r
+void vTaskExitCritical(void);\r
+#define portENTER_CRITICAL() vTaskEnterCritical()\r
+#define portEXIT_CRITICAL() vTaskExitCritical()\r
+\r
+// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack.\r
+// They can be called from interrupts too.\r
+static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; }\r
+#define portEXIT_CRITICAL_NESTED(state) do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)\r
+\r
+// These FreeRTOS versions are similar to the nested versions above\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() portENTER_CRITICAL_NESTED()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state) portEXIT_CRITICAL_NESTED(state)\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 4\r
+#define portNOP() XT_NOP()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Fine resolution time */\r
+#define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount()\r
+\r
+/* Kernel utilities. */\r
+void vPortYield( void );\r
+void _frxt_setup_switch( void );\r
+#define portYIELD() vPortYield()\r
+#define portYIELD_FROM_ISR( x ) if( ( x ) != 0 ) { _frxt_setup_switch(); }\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+// When coprocessors are defined, we to maintain a pointer to coprocessors area.\r
+// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:\r
+// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.\r
+// The field is normally used for memory protection. FreeRTOS should create another general purpose field.\r
+typedef struct {\r
+ #if XCHAL_CP_NUM > 0\r
+ volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST\r
+ #endif\r
+\r
+ #if portUSING_MPU_WRAPPERS\r
+ // Define here mpu_settings, which is port dependent\r
+ int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet\r
+ #endif\r
+\r
+ #if configUSE_TRACE_FACILITY_2\r
+ struct {\r
+ // Cf. porttraceStamp()\r
+ int taskstamp; /* Stamp from inside task to see where we are */\r
+ int taskstampcount; /* A counter usually incremented when we restart the task's loop */\r
+ } porttrace;\r
+ #endif\r
+} xMPU_SETTINGS;\r
+\r
+// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)\r
+#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS // If MPU wrappers not used, we still need to allocate coproc area\r
+ #undef portUSING_MPU_WRAPPERS\r
+ #define portUSING_MPU_WRAPPERS 1 // Enable it to allocate coproc area\r
+ #define MPU_WRAPPERS_H // Override mpu_wrapper.h to disable unwanted code\r
+ #define PRIVILEGED_FUNCTION\r
+ #define PRIVILEGED_DATA\r
+#endif\r
+\r
+// porttrace\r
+#if configUSE_TRACE_FACILITY_2\r
+#include "porttrace.h"\r
+#endif\r
+\r
+// configASSERT_2 if requested\r
+#if configASSERT_2\r
+#include <stdio.h>\r
+void exit(int);\r
+#define configASSERT( x ) if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }\r
+#endif\r
+\r
+\r
+/* C library support -- only XCLIB and NEWLIB are supported. */\r
+\r
+/* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be\r
+ defined to be > 0 somewhere above or on the command line. */\r
+\r
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB)\r
+extern void vPortClibInit(void);\r
+\r
+// No cleanup necessary at this time.\r
+#define portCLEAN_UP_TCB(pxTCB)\r
+#endif // XCLIB support\r
+\r
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB)\r
+extern void vPortClibInit(void);\r
+\r
+// This C library cleanup is not currently done by FreeRTOS when deleting a task\r
+#include <stdio.h>\r
+#define portCLEAN_UP_TCB(pxTCB) vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent))\r
+static inline void vPortCleanUpTcbClib(struct _reent *ptr)\r
+{\r
+ FILE * fp = &(ptr->__sf[0]);\r
+ int i;\r
+ for (i = 0; i < 3; ++i, ++fp) {\r
+ fp->_close = NULL;\r
+ }\r
+}\r
+#endif // NEWLIB support\r
+\r
+#endif // __ASSEMBLER__\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+\r
+/*\r
+ * This utility helps tracing the entering and exiting from tasks. It maintains a circular buffer\r
+ * of tasks in the order they execute, and their execution time.\r
+ * In order to enable it, set configUSE_TRACE_FACILITY_2 to 1 in FreeRTOSConfig.h.\r
+ * You will also need to download the FreeRTOS_trace patch that contains\r
+ * porttrace.c and the complete version of porttrace.h\r
+ */\r
+\r
+#ifndef PORTTRACE_H\r
+#define PORTTRACE_H\r
+\r
+#if configUSE_TRACE_FACILITY_2\r
+ #error "You need to download the FreeRTOS_trace patch that overwrites this file"\r
+#endif\r
+\r
+#define porttracePrint(nelements)\r
+#define porttraceStamp(stamp, count_incr)\r
+\r
+#endif /* PORTTRACE_H */\r
--- /dev/null
+ FreeRTOS Port for Xtensa Configurable and Diamond Processors\r
+ ============================================================\r
+\r
+ FreeRTOS Kernel Version 10.0.0\r
+\r
+\r
+Introduction\r
+------------\r
+\r
+This document describes the Xtensa port for FreeRTOS multitasking RTOS.\r
+For an introduction to FreeRTOS itself, please refer to FreeRTOS\r
+documentation.\r
+\r
+This port currently works with FreeRTOS kernel version 10.0.0.\r
+\r
+\r
+Xtensa Configuration Requirements and Restrictions\r
+--------------------------------------------------\r
+\r
+The Xtensa configurable architecture supports a vast space of processor\r
+features. This port supports all of them, including custom processor\r
+extensions defined in the TIE language, with certain minimum\r
+requirements. You must use Xtensa Tools to compile and link FreeRTOS and\r
+your application for your Xtensa configuration. The port uses the Xtensa\r
+Hardware Abstraction Layer (HAL) to adapt to your Xtensa configuration.\r
+NOTE: It may be possible to build and run this with the open-source \r
+xtensa-linux tools provided you have the correct overlay for your Xtensa\r
+configuration. However, this has not been tested and is currently not\r
+supported by Cadence.\r
+\r
+This port includes optional reentrancy support for the 'newlib' and\r
+'xclib' C runtime libraries distributed with Xtensa Tools, providing\r
+thread-safety on a per task basis (for use in tasks only, not interrupt\r
+handlers).\r
+\r
+NOTE: At this time only 'newlib' and 'xclib' C libraries are supported\r
+for thread safety. The 'uclibc' library is not reentrant and does not\r
+provide thread safety at this time. However, if you are not concerned\r
+with reentrancy then you can use any of these libraries.\r
+\r
+This port also includes a simple example application that may run on\r
+a supported board or the Xtensa instruction set simulator (ISS). There\r
+are also a couple of test programs used in maintaining the port, which\r
+serve as additional examples.\r
+\r
+FreeRTOS for Xtensa configurable processors requires the following minimum \r
+processor configuration options:\r
+- Timer interrupt option with at least one interruptible timer.\r
+- Interrupt option (implied by the timer interrupt option).\r
+- Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported.\r
+ All 'Diamond', 'Xtensa 6', 'Xtensa LX' and 'Xtensa LX2' processors and\r
+ most 'Xtensa T1050' processors are configured with XEA2.\r
+All Diamond processor cores meet these requirements and are supported.\r
+\r
+Minimal support for certain evaluation boards is provided via a board\r
+independent XTBSP API implemented by a board specific library distributed\r
+with the Xtensa Tools. This provides the board clock frequency and basic\r
+polled drivers for the display and console device. Note that XTBSP\r
+is not a tradtional RTOS "board support package" with RTOS specific\r
+interrupt-driven drivers - it is not specific to any RTOS. Note that\r
+FreeRTOS can run on any Xtensa or Diamond board without this board support\r
+(a "raw" platform), but you will have to provide the clock frequency\r
+and drivers for any on-board devices you want to use.\r
+\r
+\r
+Installation\r
+------------\r
+\r
+The Xtensa port of FreeRTOS is available at this location:\r
+\r
+ https://github.com/foss-xtensa/amazon-freertos\r
+\r
+This download includes the core FreeRTOS source and include files needed\r
+to build the port. You can also download the official release of FreeRTOS\r
+version 1.0.0 or later from this location:\r
+\r
+ https://github.com/aws/amazon-freertos\r
+\r
+The Xtensa port files are currently not included in the official package.\r
+\r
+All source is provided along with a Makefile that works for any host\r
+platform supported by Xtensa Tools (Windows, Linux). These instructions\r
+are written for Windows users, but can easily be understood and adapted\r
+to other host platforms.\r
+\r
+First install the FreeRTOS common package in a directory of your choosing.\r
+The structure of that package will look like this:\r
+\r
+<install directory>\r
+|-- demos\r
+| `-- cadence\r
+| `-- sim\r
+| |-- common\r
+| | |-- application_code\r
+| | | `-- cadence_code\r
+| | `-- config_files\r
+| `-- xplorer\r
+`-- lib\r
+ |-- FreeRTOS\r
+ | `-- portable\r
+ | |-- Common\r
+ | |-- MemMang\r
+ | `-- XCC\r
+ | `-- Xtensa\r
+ `-- include\r
+ `-- private\r
+\r
+The Xtensa Tools are available from Cadence as part of a processor\r
+license. Be sure you have installed the Xtensa Tools and your processor\r
+configuration.\r
+\r
+\r
+Building FreeRTOS for Xtensa\r
+----------------------------\r
+\r
+To build the FreeRTOS library and the example programs, go into the\r
+directory 'demos/cadence/sim' and use the makefile in that directory.\r
+"make all" will build all the examples. There is another makefile in\r
+the 'lib/FreeRTOS/portable/XCC/Xtensa' directory that builds just the\r
+FreeRTOS library.\r
+\r
+By default, you will build for the Xtensa instruction set simulator. If\r
+you have a supported emulation board, you can build to run on that. You\r
+can also build to run on a raw Xtensa core with no board support, a\r
+good starting point for supporting your own target platform. Cadence\r
+recommends doing functional development on the simulator because it\r
+is easier to debug with, then move to a board if/when you need to test\r
+hardware drivers or real-time performance.\r
+\r
+The provided makefile simplifies building FreeRTOS and the example\r
+for your Xtensa configuration and platform (ISS, board, etc.). There\r
+are detailed instructions in the comments at the top of the makefile.\r
+\r
+The makefiles work on Windows and Linux and support incremental builds.\r
+The build for each Xtensa configuration and target platform is placed in\r
+a subdirectory so several core and platform builds can co-exist even with\r
+incremental rebuilds. You may specify the root of the build area (if tou\r
+want it to be elsewhere than under the source tree) by defining BLDROOT\r
+either in the make command or your shell environment.\r
+\r
+\r
+Building the FreeRTOS Library\r
+-----------------------------\r
+\r
+First, be sure you have installed Xtensa Tools and your processor\r
+configuration, and be sure that Xtensa Tools are in your search path.\r
+You can use xt-make, which comes with the Xtensa Tools, to run the\r
+makefiles.\r
+\r
+Change directories to the Xtensa port directory:\r
+\r
+> cd lib/FreeRTOS/portable/XCC/Xtensa\r
+\r
+Now build the FreeRTOS RTOS as a library (libfreertos.a) as follows:\r
+\r
+> xt-make\r
+\r
+which by default builds for the simulator (TARGET=sim), or:\r
+\r
+> xt-make TARGET=board\r
+\r
+which builds for a supported board. Note that the board type does not\r
+need to be specified when building the FreeRTOS library.\r
+\r
+If you are building for an Xtensa processor configuration that is not the\r
+default you selected when you installed Xtensa Tools, you need to define the \r
+environment variable XTENSA_CORE. If your configuration is not in the \r
+default registry you selected when you installed Xtensa Tools, you also\r
+need to define the environment variable XTENSA_SYSTEM. See tools manuals.\r
+You can avoid defining these in your environment if you pass the variables \r
+you need to redefine into xt-make as follows:\r
+\r
+> xt-make XTENSA_CORE=<your_config_name> XTENSA_SYSTEM=<your_registry> ...\r
+\r
+There are more details about build options in the comment in the Makefile.\r
+\r
+After the library has been built, you must link your application with this\r
+library in order to use FreeRTOS.\r
+\r
+\r
+Building the FreeRTOS Examples\r
+------------------------------\r
+\r
+The provided examples are designed to run on the Xtensa instruction set\r
+simulator (ISS) or a supported evaluation board programmed with your\r
+Xtensa processor configuration.\r
+\r
+To build the examples for the default platform (simulator):\r
+\r
+> cd demos/cadence/sim\r
+\r
+> xt-make all\r
+\r
+which is the same as\r
+\r
+> xt-make all TARGET=sim\r
+\r
+The boards currently supported are the Xilinx ML605 and KC705 FPGA\r
+development boards. To target these boards, type\r
+\r
+> xt-make all TARGET=ml605\r
+\r
+or\r
+\r
+> xt-make all TARGET=kc705\r
+\r
+To build in a location other than the default, specify the new location\r
+using the BLDROOT variable. Note that this makefile will invoke the \r
+FreeRTOS library build makefile automatically, passing on the relevant\r
+parameters based on what you specified.\r
+\r
+You can override the default compilation options by specifying the new\r
+options via CFLAGS. For example:\r
+\r
+> xt-make all TARGET=sim CFLAGS="-O2 -Os -g"\r
+\r
+This compiles the examples and links them with the FreeRTOS library\r
+libfreertos.a and the appropriate linker-support package (LSP) for your\r
+target platform (you can override the LSP by adding LSP=<lsp> to the\r
+xt-make command line). The resulting ELF files can be downloaded and\r
+executed on the target. The example binaries appear in the platform\r
+specific subdirectory described earlier.\r
+\r
+To build your application with thread-safe C library support, you\r
+need to make certain modifications to the application to plug in and\r
+invoke the reentrancy support. This allows each task to use the library\r
+without interference with other tasks (it is not safe for interrupt\r
+handlers to call the C library).\r
+\r
+First, you must define\r
+\r
+ XT_USE_THREAD_SAFE_CLIB\r
+\r
+to a nonzero value either in xtensa_config.h or on the compiler's command\r
+line. Note that the default xtensa_config.h provided with this port does\r
+define this to 1 if either newlib or xclib is detected.\r
+\r
+Then, you must also make sure to allocate extra space on the stack for\r
+each task that will use the C library reentrant functions. This extra\r
+space is to be allocated over and above the actual stack space required\r
+by the task itself. The define\r
+\r
+ XT_STACK_EXTRA_CLIB\r
+\r
+specifies the amount of extra space to be added on to the stack to allow\r
+saving the context for the C library as well as the coprocessors if any.\r
+E.g. if your task requires 2000 bytes of stack space, you must allocate\r
+(2000 + XT_STACK_EXTRA_CLIB) bytes for the stack.\r
+\r
+\r
+IMPORTANT NOTE\r
+--------------\r
+\r
+The header file FreeRTOS.h, which is a part of the core FreeRTOS sources,\r
+includes <reent.h> if thread safety for the C libraries is enabled. For\r
+xclib, this file exists in <sys/reent.h> and so is reported as missing.\r
+To work around this, the makefiles supplied with this port will copy the\r
+reent.h header into the build directory during the build process. If you\r
+use a different build process, then you must make sure to copy this file\r
+to a location that is included in the list of include paths. This can be\r
+the build directory or the directory that contains the Xtensa port source\r
+files.\r
+\r
+\r
+Running or Debugging an Application\r
+-----------------------------------\r
+\r
+To execute the example application on the simulator:\r
+\r
+> xt-run [--turbo] example.exe\r
+\r
+The option --turbo provides much faster, but non-cycle-accurate simulation\r
+(the --turbo option is only available with Xtensa Tools version 7 or later).\r
+\r
+\r
+To execute on the simulator using the Xplorer GUI based debugger:\r
+\r
+> xplorer --debug example.exe\r
+\r
+\r
+To execute on a supported evaluation board, download example.exe per\r
+instructions in the tools manuals. Be sure the board has been programmed\r
+with the correct configuration and is set up to boot from RAM and debug\r
+a downloaded program! Optionally you may connect a terminal or terminal\r
+emulator to the serial port on the board with settings as described in\r
+the board user manual, and see the output of printf on the terminal.\r
+\r
+To obtain I/O on a "raw" platform such as an unsupported board, you need\r
+to provide low level I/O drivers (eg. inbyte() and outbyte() for character\r
+I/O if you want to use printf etc.). You can run "raw" executables on\r
+any Xtensa platform, including simulator and any board, but you will not\r
+see any behavior specific to the platform (eg. display, printed output,\r
+stopping simulation at end of program). You can, while debugging, use a\r
+debugger mechanism called GDBIO to obtain basic I/O. To use GDBIO, link\r
+with the gdbio LSP. Refer to Xtensa tools documentation for details.\r
+\r
+\r
+Task Stack Sizes\r
+----------------\r
+\r
+The application must ensure that every task has enough space for its\r
+stack. Each task needs enough space for its own use, its own interrupt\r
+stack frame (defined in xtensa_context.h) and space to save coprocessor\r
+state, if any. Several factors influence the size of the stack required,\r
+including the compiler optimization level and the use of the C library.\r
+Calls to standard output functions such as printf() can use up a lot of\r
+stack space. The tool xt-stack-usage is helpful in determining safe stack\r
+sizes for your application.\r
+\r
+Some macros are provided in xtensa_config.h to help determine the stack\r
+size for tasks that do and do not use the C library. Use these as the\r
+basis for each task's stack size. They are minimum requirements taking\r
+into account your configuration and use of the C library. In particular,\r
+the define\r
+\r
+ XT_STACK_MIN_SIZE\r
+\r
+defines the minimum stack size for any task. Be very careful if you try\r
+to use a stack size smaller than this minimum. Stack overruns can cause\r
+all kinds of hard-to-debug errors. It is recommended that you enable the\r
+FreeRTOS stack checking features during development.\r
+\r
+WARNING: The newlib printf() function uses a lot of stack space. Be very\r
+careful in using it. Optionally you can use the 'libxtutil' library for\r
+output - it implements a subset of printf() that has smaller code size\r
+and uses far less stack space. More information about this library is in\r
+the Xtensa Tools documentation.\r
+\r
+\r
+Interrupt Stack\r
+---------------\r
+\r
+Beginning with port version 1.2, the port uses a separate interrupt stack\r
+for handling interrupts. Thus, it is no longer necessary for each task to\r
+reserve space on its stack to handle interrupts. The size of the interrupt\r
+stack is controlled by the parameter "configISR_STACK_SIZE" defined in\r
+FreeRTOSConfig.h. Define this carefully to match your system requirements.\r
+\r
+\r
+Assembler / Compiler Switches\r
+-----------------------------\r
+\r
+The following are compiler switches are used by the provided\r
+Makefile in building the FreeRTOS library and example application.\r
+These can be modified by editing the Makefile or by overriding the\r
+CFLAGS variable in the make command line, for example:\r
+\r
+> xt-make CFLAGS="-O2 -DXT_USE_THREAD_SAFE_CLIB"\r
+\r
+ -g Specifies debug information.\r
+ -c Specifies object code generation.\r
+ -On Sets compiler optimization level n (default -O0).\r
+ -mlongcalls Allows assembler and linker to convert call \r
+ instructions to longer indirect call sequences \r
+ when target is out of range.\r
+ -x assembler-with-cpp Passes .s and .S files through C preprocessor.\r
+ -Dmacro Define a preprocessor macro with no value.\r
+ -Dmacro=value Define a preprocessor macro with a value.\r
+\r
+See the compiler / linker documentation for a full list of switches and\r
+their use.\r
+\r
+Many definitions can be provided at compile-time via the -D option \r
+without editing the source code. Here are some of the more useful ones:\r
+\r
+ XT_USE_THREAD_SAFE_CLIB Enable support for the reentrancy to provide\r
+ thread-safety for the newlib and xclib libraries\r
+ supplied with Xtensa Tools. Default ON.\r
+\r
+ Note, the follwing defines are unique to the Xtensa port so have names\r
+ beginning with "XT_".\r
+\r
+ XT_SIMULATOR Set this if building to run on the simulator.\r
+ Takes advantage of certain simulator control\r
+ and reporting facilities, and adjusts timing \r
+ of periodic tick to provide a more acceptable\r
+ performance in simulation (see XT_CLOCK_FREQ).\r
+ Set by default unless PLATFORM is overridden.\r
+\r
+ XT_BOARD Set this if building for a supported board.\r
+ Be sure to specify the correct LSP for the\r
+ board. See the example makefile for usage.\r
+\r
+ XT_CLOCK_FREQ=freq Specifies the target processor's clock \r
+ frequency in Hz. Used primarily to set the \r
+ timer that generates the periodic interrupt.\r
+ Defaults are provided and may be edited in\r
+ xtensa_timer.h (see comments there also).\r
+ Default for simulator provides more acceptable\r
+ performance, but cannot provide real-time\r
+ performance due to variation in simulation\r
+ speed per host platform and insufficient \r
+ cycles between interrupts to process them.\r
+ Supported board platforms by default leave \r
+ this undefined and compute the clock frequency \r
+ at initialization unless this is explicitly \r
+ defined.\r
+\r
+ XT_TICK_PER_SEC=n Specifies the frequency of the periodic tick.\r
+\r
+ XT_TIMER_INDEX=n Specifies which timer to use for periodic tick.\r
+ Set this if your Xtensa processor configuration \r
+ provides more than one suitable timer and you \r
+ want to override the default. See xtensa_timer.h .\r
+\r
+ XT_INTEXC_HOOKS Enables hooks in interrupt vector handlers\r
+ to support dynamic installation of exception\r
+ and interrupt handlers. Disabled by default.\r
+\r
+ XT_USE_OVLY Enable code overlay support. It uses a mutex,\r
+ hence configUSE_MUTEX must be enabled. This\r
+ option is currently unsupported.\r
+\r
+ XT_USE_SWPRI Enable software prioritization of interrupts.\r
+ Enabling this will prioritize interrupts with\r
+ higher bit numbers over those with lower bit\r
+ numbers at the same level. This works only for\r
+ low and medium priority interrupts that can be\r
+ dispatched to C handlers.\r
+\r
+\r
+Register Usage and Stack Frames\r
+-------------------------------\r
+\r
+The Xtensa architecture specifies two ABIs that determine how the general\r
+purpose registers a0-a15 are used: the standard windowed ABI use with\r
+the Xtensa windowed register file architecture, and the optional and\r
+more conventional Call0 ABI (required for Xtensa configurations without\r
+a windowed register file).\r
+\r
+Xtensa processors may have other special registers (including co-processor\r
+registers and other TIE "states") that are independent of this choice\r
+of ABI. See Xtensa documentation for more details.\r
+\r
+In the windowed ABI the registers of the current window are used as follows:\r
+ a0 = return address\r
+ a1 = stack pointer (alias sp)\r
+ a2 = first argument and result of call (in simple cases)\r
+ a3-7 = second through sixth arguments of call (in simple cases).\r
+ Note that complex or large arguments are passed on the\r
+ stack. Details are in the Xtensa Tools manuals.\r
+ a8-a15 = available for use as temporaries.\r
+There are no callee-save registers. The windowed hardware automatically\r
+saves registers a0-a3 on a call4, a0-a8 on a call8, a0-a12 on a call12,\r
+by rotating the register window. Hardware triggers window overflow and\r
+underflow exceptions as necessary when registers outside the current \r
+window need to be spilled to preallocated space in the stack frame, or\r
+restored. Complete details are in the Xtensa manuals. The entire windowed\r
+register file is saved and restored on interrupt or task context switch.\r
+\r
+The Call0 ABI does not make use of register windows, relying instead\r
+on a fixed set of 16 registers without window rotation.\r
+The Call0 ABI is more conventional and uses registers as follows:\r
+ a0 = return address\r
+ a1 = stack pointer (alias sp)\r
+ a2 = first argument and result of call (in simple cases)\r
+ a3-7 = second through sixth arguments of call (in simple cases).\r
+ Note that complex or large arguments are passed on the\r
+ stack. Details are in the Xtensa Tools manuals.\r
+ a8-a11 = scratch.\r
+ a12-a15 = callee-save (a function must preserve these for its caller).\r
+On a FreeRTOS API call, callee-save registers are saved only when a task\r
+context switch occurs, and other registers are not saved at all (the caller\r
+does not expect them to be preserved). On an interrupt, callee-saved\r
+registers might only be saved and restored when a task context-switch\r
+occurs, but all other registers are always saved and restored.\r
+\r
+An Xtensa processor has other special registers independent of the ABI,\r
+depending on the configuration (including co-processor registers and other\r
+TIE state) that are part of the task context. FreeRTOS preserves all such\r
+registers over an unsolicited context-switch triggered by an interrupt.\r
+However it does NOT preserve these over a solicited context-switch during\r
+a FreeRTOS API call. This bears some explanation. These special registers\r
+are either ignored by the compiler or treated as caller-saved, meaning\r
+that if kept "live" over a function call (ie. need to be preserved)\r
+they must be saved and restored by the caller. Since solicited entry to\r
+FreeRTOS is always made by a function call, FreeRTOS assumes the caller\r
+has saved any of these registers that are "live". FreeRTOS avoids a lot\r
+of overhead by not having to save and restore every special register\r
+(there can be many) on every solicited context switch.\r
+\r
+As a consequence, the application developer should NOT assume that special\r
+registers are preserved over a FreeRTOS API call such as vTaskDelay().\r
+If multiple tasks use a register, the caller must save and restore it.\r
+\r
+The saved context stack frames for context switches that occur as\r
+a result of interrupt handling (interrupt frame) or from task-level\r
+API calls (solicited frame) are described in human readable form in\r
+xtensa_context.h . All suspended tasks have one of these two types\r
+of stack frames. The top of the suspended task's stack is pointed to\r
+by pxCurrentTCB->pxTopOfStack. A special location common to both stack\r
+frames differentiates solicited and interrupt stack frames.\r
+\r
+\r
+Improving Performance, Footprint, or Ease of Debugging\r
+------------------------------------------------------\r
+\r
+By default FreeRTOS for Xtensa is built with debug (-g) and without\r
+compiler optimizations (-O0). This makes debugging easier. Of course,\r
+-O0 costs performance and usually also increases stack usage. To make\r
+FreeRTOS run faster you can change the Makefile to enable the desired\r
+optimizations or set a predefined optimization level (-O<level>) .\r
+\r
+Maximum performance is achieved with -O3 -ipa, but that might increase \r
+the footprint substantially. A good compromise is -O2. See the compiler\r
+manual for details.\r
+\r
+Minimal footprint is achieved by optimizing for space with -Os, at the\r
+cost of some performance. See the compiler manual for details.\r
+\r
+The Xtensa architecture port-specific assembly files are coded with no\r
+file-scope labels inside functions (all labels inside functions begin with\r
+".L"). This allows a profiler to accurately associate an address with a\r
+function, and also allows the debugger's stack trace to show the correct\r
+function wherever the program counter is within that function. However\r
+there are some tradeoffs in debugging. Local (".L") labels are not\r
+visible to the debugger, so the following limitations may be observed\r
+during debugging:\r
+- You cannot set a breakpoint on a local label inside a function.\r
+- Disassembly will show the entire function, but will get out of sync and\r
+ show incorrect opcodes if it crosses any padding before an aligned local\r
+ branch target (".L" label, not ".Ln"). Restart disassembly specifying an\r
+ address range explicitly between points where there is padding.\r
+Since FreeRTOS is provided in source form, it is not difficult to remove\r
+the ".L" and ".Ln" prefixes from local labels if you want them visible.\r
+They can also be made visible by passing the '-L' option to the assembler\r
+and linker (see the assembler and linker manuals for details).\r
+\r
+\r
+Interrupt and Exception Handling\r
+--------------------------------\r
+\r
+FreeRTOS provides a complete set of efficient exception and first-level\r
+interrupt handlers installed at the appropriate exception and interrupt\r
+vector locations. The Xtensa architecture supports several different\r
+classes of exceptions and interrupts. Being a configurable architecture,\r
+many of these are optional, and the vector locations are determined by\r
+your processor configuration. (Note that Diamond cores are pre-configured\r
+with specific vector locations.) The handlers provided use conditional\r
+compilation to adapt to your processor configuration and include only \r
+the code that is needed.\r
+\r
+Xtensa vector locations may reside almost anywhere, including in ROM.\r
+The amount of code space available at each of these locations is\r
+often very small (e.g. due to following vectors). A small stub of\r
+code installed at the vector jumps to the corresponding handler,\r
+usually in RAM. The exception and interrupt handlers are defined in\r
+xtensa_vectors.S. They are not specific to FreeRTOS, but call into\r
+FreeRTOS where appropriate via macros defined in xtensa_rtos.h .\r
+\r
+The handlers provided for low and medium priority interrupts are just\r
+dispatchers that save relevant state and call user-definable handlers.\r
+See the files xtensa_vectors.S and xtensa_api.h for more details of how\r
+to create and install application-specific user interrupt handlers.\r
+Similarly, user-defined handlers can be installed for exceptions (other\r
+than a few which are always handled by the OS).\r
+\r
+The high priority interrupt handlers provided may be considered templates\r
+into which the application adds code to service specific interrupts.\r
+The places where application handlers should be inserted are tagged with\r
+the comment "USER_EDIT" in xtensa_vectors.S.\r
+\r
+This FreeRTOS port supports strict priority-based nesting of interrupts.\r
+An interrupt may only nest on top of one of strictly lower priority.\r
+Equal priority interrupts concurrently pending are handled in an\r
+application-defined sequence before any lower priority interrupts\r
+are handled. During interrupt and exception handling, the processor's\r
+interrupt level (PS.INTLEVEL) is used to control the interrupt priority\r
+level that can be accepted; interrupt sources are not controlled\r
+individually by FreeRTOS (the application is free to access the INTENABLE\r
+register directly to enable/disable individual interrupts, eg. using\r
+Xtensa HAL services). This approach provides the most deterministic\r
+bounds on interrupt latency (for a given priority) and stack depth.\r
+\r
+Software prioritization of interrupts at the same priority is controlled\r
+by the definition of XT_USE_SWPRI. See above for a description of this\r
+parameter.\r
+\r
+The following subsections describe the handling of each class of exception\r
+and interrupt in more detail. Many have nothing to do with FreeRTOS but\r
+are mentioned because there is code to handle them in xtensa_vectors.S.\r
+\r
+User Exception and Interrupt Handler (Low/Medium Priority):\r
+\r
+ All Xtensa 'general exceptions' come to the user, kernel, or double\r
+ exception vector. The exception type is identified by the EXCCAUSE\r
+ special register (level 1 interrupts are one particular cause of a\r
+ general exception). This port sets up PS to direct all such exceptions\r
+ to the user vector. Exceptions taken at the other two vectors usually\r
+ indicate a kernel or application bug.\r
+\r
+ Level 1 interrupts are identified at the beginning of the handler\r
+ and are dispatched to a dedicated handler. Then, syscall and alloca\r
+ exceptions are identified and dispatched to special handlers described\r
+ below. After this, coprocessor exceptions are identified and dispatched\r
+ to the coprocessor handler.\r
+\r
+ Any remaining exceptions are processed as follows:\r
+\r
+ Having allocated the exception stack frame, the user exception handler\r
+ saves the current task state and sets up a C environment and enables\r
+ the high-priority class of interrupts (which do not interact with\r
+ FreeRTOS), then reads EXCCAUSE and uses the cause (number) to index\r
+ into a table of user-specified handlers. The correct handler is then\r
+ called. If the handler returns, the context is restored and control is\r
+ returned to the code that caused the exception. The user-defined handler\r
+ may alter the saved context, or any other system state, that allows the\r
+ faulting instruction to be retried.\r
+\r
+ If the cause is a level 1 (low-priority) or medium-priority interrupt,\r
+ the handler enables all interrupts above that priority level after\r
+ saving the task context. It then sets up the environment for C code\r
+ and then calls the handler (found in the handler table) for the\r
+ interrupt number. If the user has not specified a handler, then the\r
+ default handler will be called, which will terminate the program.\r
+\r
+ If the interrupt is for the system timer, it calls a special interrupt\r
+ handler for the system timer tick, which calls _frxt_timer_int then\r
+ clears its bit from the mask. This interrupt cannot be hooked by the\r
+ user-defined handler.\r
+\r
+ Finally, the handler calls _frxt_int_exit to allow FreeRTOS to perform\r
+ any scheduling necessary and return either to the interrupted task\r
+ or another.\r
+\r
+ If software prioritization is enabled, the handler will re-enable all\r
+ interrupts at the same level that are numerically higher than the current\r
+ one, before calling the user handler. This allows a higher priority\r
+ interrupt to pre-empt the lower priority handler.\r
+\r
+Medium Priority Interrupt Handlers:\r
+\r
+ Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL,\r
+ a configuration-specific maximum interrupt level affected by the global\r
+ 'exception mode' bit in the processor status word (PS.EXCM).\r
+ Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class.\r
+ The Xtensa hardware documentation considers medium priority interrupts\r
+ to be a special case of high-priority interrupts, but from a software\r
+ perspective they are very different.\r
+\r
+ Dispatch of medium-priority interrupts is discussed in the section\r
+ above.\r
+\r
+High Priority Interrupt Handlers:\r
+\r
+ High priority interrupts are those strictly above XCHAL_EXCM_LEVEL, \r
+ a configuration-specific maximum interrupt level affected by the \r
+ global 'exception mode' bit in the processor status word (PS.EXCM).\r
+ High priority handlers may not directly interact with FreeRTOS at all,\r
+ and are described here only for the sake of completeness. They must\r
+ be coded in assembler (may not be coded in C) and are intended to be \r
+ used for handling extremely high frequency hardware events that need\r
+ to be handled in only a few cycles. A high priority interrupt handler\r
+ may trigger a software interrupt at a medium or low priority level to\r
+ occasionally signal FreeRTOS. Please see Xtensa documentation.\r
+\r
+ There is a separate vector and a few special registers for each high\r
+ priority interrupt, providing for fast dispatch and efficient nesting\r
+ on top of lower priority interrupts. Handlers are templates included\r
+ only for the vectors that exist in your Xtensa processor configuration.\r
+ These templates are written for only one interrupt per high priority \r
+ level to minimize latency servicing very fast time-critical interrupts.\r
+ The vector code jumps to the corresponding first-level interrupt handler,\r
+ which then executes application-provided assembler code before returning\r
+ quickly to the interrupted task or lower priority handler.\r
+\r
+Kernel Exception Handler:\r
+\r
+ Kernel mode is not used in this port of FreeRTOS, and therefore kernel\r
+ exceptions should not happen. A stub is provided for the vector that\r
+ triggers the debugger (if connected) or calls _xt_panic to freeze the \r
+ processor should a kernel exception occur.\r
+\r
+Alloca Exception Handler:\r
+\r
+ Alloca exceptions are generated by the 'movsp' instruction, which\r
+ is used only in the windowed ABI. Its purpose is to allocate some\r
+ space on top of the stack. Because the window hardware may have\r
+ spilled some registers to the 16 byte "base save" area below the\r
+ stack pointer, it is necessary to protect those values. The alloca\r
+ handler accomplishes this quickly without setting up an interrupt\r
+ frame or entering FreeRTOS, by emulating a register underflow and\r
+ re-executing 'movsp'.\r
+\r
+Syscall Exception Handler:\r
+\r
+ Syscall exceptions are generated by a 'syscall' instruction.\r
+ The windowed ABI specifies that executing this instruction with\r
+ a value of zero in register a2 must spill any unsaved registers\r
+ in the windowed register file to their pre-determined locations\r
+ on the caller's stack. The handler does exactly that, and skips\r
+ over the 'syscall' instruction before returning to the caller.\r
+ If a2 is non-zero, the handler returns a2 == -1 to the caller.\r
+\r
+Co-Processor Exception Handler:\r
+\r
+ A co-processor exception is generated when a task accesses a\r
+ co-processor that it does not "own". Ownership represents which\r
+ task's state is currently in the co-processor. Co-processors are\r
+ context-switched "lazily" (on demand) only when a non-owning task\r
+ uses a co-processor instruction, otherwise a task retains ownership\r
+ even when it is preempted from the main processor. The co-processor\r
+ exception handler performs the context-switch and manages ownership.\r
+\r
+ Co-processors may not be used by any code outside the context of a\r
+ task. A co-processor exception triggered by code that is not part\r
+ of a running task is a fatal error and FreeRTOS for Xtensa will panic.\r
+ This restriction is intended to reduce the overhead of saving and \r
+ restoring co-processor state (which can be quite large) and in \r
+ particular remove that overhead from interrupt handlers.\r
+\r
+Debug Exception Handler:\r
+\r
+ A debug exception is caused as a result of running code, such as by\r
+ a 'break' instruction or hardware breakpoints and watchpoints, or\r
+ as a result of an external debug interrupt, such as from an OCD based\r
+ debugger or multiprocessor debug events ("breakin/breakout"). If the\r
+ processor is running in OCD mode under control of an OCD-based debugger,\r
+ the trigger event immediately halts the processor and gives control to\r
+ the OCD debugger. Otherwise control is transferred to the debug vector.\r
+ The debug vector handler calls the simulator if running on the ISS,\r
+ which then takes control and interacts with any attached debugger.\r
+ If running on hardware and not in OCD mode, debug exceptions are not\r
+ expected, so the debug handler calls _xt_panic to freeze the processor.\r
+\r
+Double Exception Handler:\r
+\r
+ A double exception is a general exception that happens while the\r
+ processor is in exception mode (PS.EXCM set), and thus indicates a\r
+ bug in kernel code. The double exception vector handler triggers\r
+ the debugger (if connected) or calls _xt_panic to freeze the \r
+ processor.\r
+\r
+Window Overflow and Underflow Exception Handlers:\r
+\r
+ Window overflow and underflow handlers are required for use of the\r
+ windowed ABI. Each has its own dedicated vector and highly optimized\r
+ code that is independent of OS. See Xtensa documentation for details.\r
+\r
+Hooks for Dynamic Installation of Handlers:\r
+\r
+ Optional hooks are provided in the user exception and low level\r
+ interrupt handler and all medium and high priority interrupt handlers,\r
+ to dynamically install a handler function (which may be coded in C,\r
+ unless in a high-priority interrupt handler). These hooks are enabled\r
+ and used by automatic regression tests, they are not part of a normal\r
+ FreeRTOS build. However an application is free to take advantage of\r
+ them. The interrupt/exception hooks are described in xtensa_rtos.h .\r
+\r
+ It is recommended that the application not make use of these hooks, but\r
+ rather use xt_set_interrupt_handler() and xt_set_exception_handler()\r
+ to install application-specific handlers. This method is more convenient\r
+ and allows arguments to be passed to the handlers. Software prioritization\r
+ of interrupts works only with this method. See xtensa_api.h for details.\r
+\r
+Overlay Support\r
+\r
+ Code overlays are currently not supported for FreeRTOS. This will be\r
+ supported in a future release. Make sure that the option XT_USE_OVLY is\r
+ never defined when building.\r
+\r
+\r
+-End-\r
+\r
--- /dev/null
+/*******************************************************************************\r
+Copyright (c) 2006-2015 Cadence Design Systems Inc.\r
+\r
+Permission is hereby granted, free of charge, to any person obtaining\r
+a copy of this software and associated documentation files (the\r
+"Software"), to deal in the Software without restriction, including\r
+without limitation the rights to use, copy, modify, merge, publish,\r
+distribute, sublicense, and/or sell copies of the Software, and to\r
+permit persons to whom the Software is furnished to do so, subject to\r
+the following conditions:\r
+\r
+The above copyright notice and this permission notice shall be included\r
+in all copies or substantial portions of the Software.\r
+\r
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+ Xtensa-specific API for RTOS ports.\r
+******************************************************************************/\r
+\r
+#ifndef __XTENSA_API_H__\r
+#define __XTENSA_API_H__\r
+\r
+#include <xtensa/hal.h>\r
+\r
+#include "xtensa_context.h"\r
+\r
+\r
+/* Typedef for C-callable interrupt handler function */\r
+typedef void (*xt_handler)(void *);\r
+\r
+/* Typedef for C-callable exception handler function */\r
+typedef void (*xt_exc_handler)(XtExcFrame *);\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Call this function to set a handler for the specified exception.\r
+\r
+ n - Exception number (type)\r
+ f - Handler function address, NULL to uninstall handler.\r
+\r
+ The handler will be passed a pointer to the exception frame, which is created\r
+ on the stack of the thread that caused the exception.\r
+\r
+ If the handler returns, the thread context will be restored and the faulting\r
+ instruction will be retried. Any values in the exception frame that are\r
+ modified by the handler will be restored as part of the context. For details\r
+ of the exception frame structure see xtensa_context.h.\r
+-------------------------------------------------------------------------------\r
+*/\r
+extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Call this function to set a handler for the specified interrupt.\r
+ \r
+ n - Interrupt number.\r
+ f - Handler function address, NULL to uninstall handler.\r
+ arg - Argument to be passed to handler.\r
+-------------------------------------------------------------------------------\r
+*/\r
+extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Call this function to enable the specified interrupts.\r
+\r
+ mask - Bit mask of interrupts to be enabled.\r
+\r
+ Returns the previous state of the interrupt enables.\r
+-------------------------------------------------------------------------------\r
+*/\r
+extern unsigned int xt_ints_on(unsigned int mask);\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Call this function to disable the specified interrupts.\r
+\r
+ mask - Bit mask of interrupts to be disabled.\r
+\r
+ Returns the previous state of the interrupt enables.\r
+-------------------------------------------------------------------------------\r
+*/\r
+extern unsigned int xt_ints_off(unsigned int mask);\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Call this function to set the specified (s/w) interrupt.\r
+-------------------------------------------------------------------------------\r
+*/\r
+static inline void xt_set_intset(unsigned int arg)\r
+{\r
+ xthal_set_intset(arg);\r
+}\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Call this function to clear the specified (s/w or edge-triggered)\r
+ interrupt.\r
+-------------------------------------------------------------------------------\r
+*/\r
+static inline void xt_set_intclear(unsigned int arg)\r
+{\r
+ xthal_set_intclear(arg);\r
+}\r
+\r
+\r
+#endif /* __XTENSA_API_H__ */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+\r
+ Configuration-specific information for Xtensa build. This file must be\r
+ included in FreeRTOSConfig.h to properly set up the config-dependent\r
+ parameters correctly.\r
+\r
+ NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must\r
+ be defined to be > 0 somewhere above or on the command line.\r
+\r
+*******************************************************************************/\r
+\r
+#ifndef XTENSA_CONFIG_H\r
+#define XTENSA_CONFIG_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <xtensa/hal.h>\r
+#include <xtensa/config/core.h>\r
+#include <xtensa/config/system.h> /* required for XSHAL_CLIB */\r
+\r
+#include "xtensa_context.h"\r
+\r
+\r
+/*-----------------------------------------------------------------------------\r
+* STACK REQUIREMENTS\r
+*\r
+* This section defines the minimum stack size, and the extra space required to\r
+* be allocated for saving coprocessor state and/or C library state information\r
+* (if thread safety is enabled for the C library). The sizes are in bytes.\r
+*\r
+* Stack sizes for individual tasks should be derived from these minima based on\r
+* the maximum call depth of the task and the maximum level of interrupt nesting.\r
+* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based\r
+* on the requirement for a task that calls nothing else but can be interrupted.\r
+* This assumes that interrupt handlers do not call more than a few levels deep.\r
+* If this is not true, i.e. one or more interrupt handlers make deep calls then\r
+* the minimum must be increased.\r
+*\r
+* If the Xtensa processor configuration includes coprocessors, then space is \r
+* allocated to save the coprocessor state on the stack.\r
+*\r
+* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB\r
+* is defined) then space is allocated to save the C library context in the TCB.\r
+* \r
+* Allocating insufficient stack space is a common source of hard-to-find errors.\r
+* During development, it is best to enable the FreeRTOS stack checking features.\r
+*\r
+* Usage:\r
+* \r
+* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe\r
+* use of the C library. This will require extra stack\r
+* space to be allocated for tasks that use the C library\r
+* reentrant functions. See below for more information.\r
+* \r
+* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them\r
+* support thread safety. Check your core configuration to see which C library\r
+* was chosen for your system.\r
+* \r
+* XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended\r
+* that you do not use a stack smaller than this for any\r
+* task. In case you want to use stacks smaller than this\r
+* size, you must verify that the smaller size(s) will work\r
+* under all operating conditions.\r
+*\r
+* XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task\r
+* that does not make C library reentrant calls. Add this\r
+* to the amount of stack space required by the task itself.\r
+*\r
+* XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state.\r
+*\r
+-----------------------------------------------------------------------------*/\r
+\r
+/* Extra space required for interrupt/exception hooks. */\r
+#ifdef XT_INTEXC_HOOKS\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ #define STK_INTEXC_EXTRA 0x200\r
+ #else\r
+ #define STK_INTEXC_EXTRA 0x180\r
+ #endif\r
+#else\r
+ #define STK_INTEXC_EXTRA 0\r
+#endif\r
+\r
+/* Check C library thread safety support and compute size of C library save area.\r
+ For the supported libraries, we enable thread safety by default, and this can\r
+ be overridden from the compiler/make command line. */\r
+#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB)\r
+ #ifndef XT_USE_THREAD_SAFE_CLIB\r
+ #define XT_USE_THREAD_SAFE_CLIB 1\r
+ #endif\r
+#else\r
+ #define XT_USE_THREAD_SAFE_CLIB 0\r
+#endif\r
+\r
+#if XT_USE_THREAD_SAFE_CLIB > 0u\r
+ #if XSHAL_CLIB == XTHAL_CLIB_XCLIB\r
+ #define XT_HAVE_THREAD_SAFE_CLIB 1\r
+ #if !defined __ASSEMBLER__\r
+ #include <sys/reent.h>\r
+ #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16))\r
+ #define XT_CLIB_GLOBAL_PTR _reent_ptr\r
+ #define _REENT_INIT_PTR _init_reent\r
+ #define _impure_ptr _reent_ptr\r
+\r
+ void _reclaim_reent(void * ptr);\r
+ #endif\r
+ #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB\r
+ #define XT_HAVE_THREAD_SAFE_CLIB 1\r
+ #if !defined __ASSEMBLER__\r
+ #include <sys/reent.h>\r
+ #define XT_CLIB_CONTEXT_AREA_SIZE ((sizeof(struct _reent) + 15) + (-16))\r
+ #define XT_CLIB_GLOBAL_PTR _impure_ptr\r
+ #endif\r
+ #else\r
+ #define XT_HAVE_THREAD_SAFE_CLIB 0\r
+ #error The selected C runtime library is not thread safe.\r
+ #endif\r
+#else\r
+ #define XT_CLIB_CONTEXT_AREA_SIZE 0\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ Extra size -- interrupt frame plus coprocessor save area plus hook space.\r
+ NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.\r
+------------------------------------------------------------------------------*/\r
+#ifdef __XTENSA_CALL0_ABI__\r
+ #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)\r
+#else\r
+ #define XT_XTRA_SIZE (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ Space allocated for user code -- function calls and local variables.\r
+ NOTE: This number can be adjusted to suit your needs. You must verify that the\r
+ amount of space you reserve is adequate for the worst-case conditions in your\r
+ application.\r
+ NOTE: The windowed ABI requires more stack, since space has to be reserved\r
+ for spilling register windows.\r
+------------------------------------------------------------------------------*/\r
+#ifdef __XTENSA_CALL0_ABI__\r
+ #define XT_USER_SIZE 0x200\r
+#else\r
+ #define XT_USER_SIZE 0x400\r
+#endif\r
+\r
+/* Minimum recommended stack size. */\r
+#define XT_STACK_MIN_SIZE ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))\r
+\r
+/* OS overhead with and without C library thread context. */\r
+#define XT_STACK_EXTRA (XT_XTRA_SIZE)\r
+#define XT_STACK_EXTRA_CLIB (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* XTENSA_CONFIG_H */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+Copyright (c) 2006-2015 Cadence Design Systems Inc.\r
+\r
+Permission is hereby granted, free of charge, to any person obtaining\r
+a copy of this software and associated documentation files (the\r
+"Software"), to deal in the Software without restriction, including\r
+without limitation the rights to use, copy, modify, merge, publish,\r
+distribute, sublicense, and/or sell copies of the Software, and to\r
+permit persons to whom the Software is furnished to do so, subject to\r
+the following conditions:\r
+\r
+The above copyright notice and this permission notice shall be included\r
+in all copies or substantial portions of the Software.\r
+\r
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+\r
+ XTENSA CONTEXT SAVE AND RESTORE ROUTINES\r
+\r
+Low-level Call0 functions for handling generic context save and restore of\r
+registers not specifically addressed by the interrupt vectors and handlers.\r
+Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).\r
+Except for the calls to RTOS functions, this code is generic to Xtensa.\r
+\r
+Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-\r
+save regs (A12-A15), which is always the case if the handlers are coded in C.\r
+However A12, A13 are made available as scratch registers for interrupt dispatch\r
+code, so are presumed saved anyway, and are always restored even in Call0 ABI.\r
+Only A14, A15 are truly handled as callee-save regs.\r
+\r
+Because Xtensa is a configurable architecture, this port supports all user\r
+generated configurations (except restrictions stated in the release notes).\r
+This is accomplished by conditional compilation using macros and functions\r
+defined in the Xtensa HAL (hardware adaptation layer) for your configuration.\r
+Only the processor state included in your configuration is saved and restored,\r
+including any processor state added by user configuration options or TIE.\r
+\r
+*******************************************************************************/\r
+\r
+/* Warn nicely if this file gets named with a lowercase .s instead of .S: */\r
+#define NOERROR #\r
+NOERROR: .error "C preprocessor needed for this file: make sure its filename\\r
+ ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."\r
+\r
+\r
+#include "xtensa_rtos.h"\r
+\r
+#ifdef XT_USE_OVLY\r
+#include <xtensa/overlay_os_asm.h>\r
+#endif\r
+\r
+ .text\r
+\r
+/*******************************************************************************\r
+\r
+_xt_context_save\r
+\r
+ !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!\r
+\r
+Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the\r
+interrupt stack frame defined in xtensa_rtos.h.\r
+Its counterpart is _xt_context_restore (which also restores A12, A13).\r
+\r
+Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.\r
+This function preserves A12 & A13 in order to provide the caller with 2 scratch \r
+regs that need not be saved over the call to this function. The choice of which\r
+2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,\r
+to avoid moving data more than necessary. Caller can assign regs accordingly.\r
+\r
+Entry Conditions:\r
+ A0 = Return address in caller.\r
+ A1 = Stack pointer of interrupted thread or handler ("interruptee").\r
+ Original A12, A13 have already been saved in the interrupt stack frame.\r
+ Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the \r
+ point of interruption.\r
+ If windowed ABI, PS.EXCM = 1 (exceptions disabled).\r
+\r
+Exit conditions:\r
+ A0 = Return address in caller.\r
+ A1 = Stack pointer of interrupted thread or handler ("interruptee").\r
+ A12, A13 as at entry (preserved).\r
+ If windowed ABI, PS.EXCM = 1 (exceptions disabled).\r
+\r
+*******************************************************************************/\r
+\r
+ .global _xt_context_save\r
+ .type _xt_context_save,@function\r
+ .align 4\r
+_xt_context_save:\r
+\r
+ s32i a2, sp, XT_STK_A2\r
+ s32i a3, sp, XT_STK_A3\r
+ s32i a4, sp, XT_STK_A4\r
+ s32i a5, sp, XT_STK_A5\r
+ s32i a6, sp, XT_STK_A6\r
+ s32i a7, sp, XT_STK_A7\r
+ s32i a8, sp, XT_STK_A8\r
+ s32i a9, sp, XT_STK_A9\r
+ s32i a10, sp, XT_STK_A10\r
+ s32i a11, sp, XT_STK_A11\r
+\r
+ /*\r
+ Call0 ABI callee-saved regs a12-15 do not need to be saved here.\r
+ a12-13 are the caller's responsibility so it can use them as scratch.\r
+ So only need to save a14-a15 here for Windowed ABI (not Call0).\r
+ */\r
+ #ifndef __XTENSA_CALL0_ABI__\r
+ s32i a14, sp, XT_STK_A14\r
+ s32i a15, sp, XT_STK_A15\r
+ #endif\r
+\r
+ rsr a3, SAR\r
+ s32i a3, sp, XT_STK_SAR\r
+\r
+ #if XCHAL_HAVE_LOOPS\r
+ rsr a3, LBEG\r
+ s32i a3, sp, XT_STK_LBEG\r
+ rsr a3, LEND\r
+ s32i a3, sp, XT_STK_LEND\r
+ rsr a3, LCOUNT\r
+ s32i a3, sp, XT_STK_LCOUNT\r
+ #endif\r
+\r
+ #if XT_USE_SWPRI\r
+ /* Save virtual priority mask */\r
+ movi a3, _xt_vpri_mask\r
+ l32i a3, a3, 0\r
+ s32i a3, sp, XT_STK_VPRI\r
+ #endif\r
+\r
+ #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)\r
+ mov a9, a0 /* preserve ret addr */\r
+ #endif\r
+\r
+ #ifndef __XTENSA_CALL0_ABI__\r
+ /*\r
+ To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.\r
+ Need to save a9,12,13 temporarily (in frame temps) and recover originals.\r
+ Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow\r
+ and underflow exceptions disabled (assured by PS.EXCM == 1).\r
+ */\r
+ s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */\r
+ s32i a13, sp, XT_STK_TMP1 \r
+ s32i a9, sp, XT_STK_TMP2 \r
+\r
+ /*\r
+ Save the overlay state if we are supporting overlays. Since we just saved\r
+ three registers, we can conveniently use them here. Note that as of now,\r
+ overlays only work for windowed calling ABI.\r
+ */\r
+ #ifdef XT_USE_OVLY\r
+ l32i a9, sp, XT_STK_PC /* recover saved PC */\r
+ _xt_overlay_get_state a9, a12, a13\r
+ s32i a9, sp, XT_STK_OVLY /* save overlay state */\r
+ #endif\r
+\r
+ l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */\r
+ l32i a13, sp, XT_STK_A13\r
+ l32i a9, sp, XT_STK_A9\r
+ addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */\r
+ call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */\r
+ addi sp, sp, -XT_STK_FRMSZ\r
+ l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */\r
+ l32i a13, sp, XT_STK_TMP1 \r
+ l32i a9, sp, XT_STK_TMP2 \r
+ #endif\r
+\r
+ #if XCHAL_EXTRA_SA_SIZE > 0\r
+ /* \r
+ NOTE: Normally the xthal_save_extra_nw macro only affects address\r
+ registers a2-a5. It is theoretically possible for Xtensa processor\r
+ designers to write TIE that causes more address registers to be\r
+ affected, but it is generally unlikely. If that ever happens,\r
+ more registers need to be saved/restored around this macro invocation.\r
+ Here we assume a9,12,13 are preserved.\r
+ Future Xtensa tools releases might limit the regs that can be affected.\r
+ */\r
+ addi a2, sp, XT_STK_EXTRA /* where to save it */\r
+ # if XCHAL_EXTRA_SA_ALIGN > 16\r
+ movi a3, -XCHAL_EXTRA_SA_ALIGN\r
+ and a2, a2, a3 /* align dynamically >16 bytes */\r
+ # endif\r
+ call0 xthal_save_extra_nw /* destroys a0,2,3,4,5 */\r
+ #endif\r
+\r
+ #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)\r
+ mov a0, a9 /* retrieve ret addr */\r
+ #endif\r
+\r
+ ret\r
+\r
+/*******************************************************************************\r
+\r
+_xt_context_restore\r
+\r
+ !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!\r
+\r
+Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0\r
+ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt \r
+stack frame defined in xtensa_rtos.h .\r
+Its counterpart is _xt_context_save (whose caller saved A12, A13).\r
+\r
+Caller is responsible to restore PC, PS, A0, A1 (SP).\r
+\r
+Entry Conditions:\r
+ A0 = Return address in caller.\r
+ A1 = Stack pointer of interrupted thread or handler ("interruptee").\r
+\r
+Exit conditions:\r
+ A0 = Return address in caller.\r
+ A1 = Stack pointer of interrupted thread or handler ("interruptee").\r
+ Other processor state except PC, PS, A0, A1 (SP), is as at the point \r
+ of interruption.\r
+\r
+*******************************************************************************/\r
+\r
+ .global _xt_context_restore\r
+ .type _xt_context_restore,@function\r
+ .align 4\r
+_xt_context_restore:\r
+\r
+ #if XCHAL_EXTRA_SA_SIZE > 0\r
+ /* \r
+ NOTE: Normally the xthal_restore_extra_nw macro only affects address\r
+ registers a2-a5. It is theoretically possible for Xtensa processor\r
+ designers to write TIE that causes more address registers to be\r
+ affected, but it is generally unlikely. If that ever happens,\r
+ more registers need to be saved/restored around this macro invocation.\r
+ Here we only assume a13 is preserved.\r
+ Future Xtensa tools releases might limit the regs that can be affected.\r
+ */\r
+ mov a13, a0 /* preserve ret addr */\r
+ addi a2, sp, XT_STK_EXTRA /* where to find it */\r
+ # if XCHAL_EXTRA_SA_ALIGN > 16\r
+ movi a3, -XCHAL_EXTRA_SA_ALIGN\r
+ and a2, a2, a3 /* align dynamically >16 bytes */\r
+ # endif\r
+ call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */\r
+ mov a0, a13 /* retrieve ret addr */\r
+ #endif\r
+\r
+ #if XCHAL_HAVE_LOOPS\r
+ l32i a2, sp, XT_STK_LBEG\r
+ l32i a3, sp, XT_STK_LEND\r
+ wsr a2, LBEG\r
+ l32i a2, sp, XT_STK_LCOUNT\r
+ wsr a3, LEND\r
+ wsr a2, LCOUNT\r
+ #endif\r
+\r
+ #ifdef XT_USE_OVLY\r
+ /*\r
+ If we are using overlays, this is a good spot to check if we need\r
+ to restore an overlay for the incoming task. Here we have a bunch\r
+ of registers to spare. Note that this step is going to use a few\r
+ bytes of storage below SP (SP-20 to SP-32) if an overlay is going\r
+ to be restored.\r
+ */\r
+ l32i a2, sp, XT_STK_PC /* retrieve PC */\r
+ l32i a3, sp, XT_STK_PS /* retrieve PS */\r
+ l32i a4, sp, XT_STK_OVLY /* retrieve overlay state */\r
+ l32i a5, sp, XT_STK_A1 /* retrieve stack ptr */\r
+ _xt_overlay_check_map a2, a3, a4, a5, a6\r
+ s32i a2, sp, XT_STK_PC /* save updated PC */\r
+ s32i a3, sp, XT_STK_PS /* save updated PS */\r
+ #endif\r
+\r
+ #ifdef XT_USE_SWPRI\r
+ /* Restore virtual interrupt priority and interrupt enable */\r
+ movi a3, _xt_intdata\r
+ l32i a4, a3, 0 /* a4 = _xt_intenable */\r
+ l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */\r
+ and a4, a4, a5\r
+ wsr a4, INTENABLE /* update INTENABLE */\r
+ s32i a5, a3, 4 /* restore _xt_vpri_mask */\r
+ #endif\r
+\r
+ l32i a3, sp, XT_STK_SAR\r
+ l32i a2, sp, XT_STK_A2\r
+ wsr a3, SAR\r
+ l32i a3, sp, XT_STK_A3\r
+ l32i a4, sp, XT_STK_A4\r
+ l32i a5, sp, XT_STK_A5\r
+ l32i a6, sp, XT_STK_A6\r
+ l32i a7, sp, XT_STK_A7\r
+ l32i a8, sp, XT_STK_A8\r
+ l32i a9, sp, XT_STK_A9\r
+ l32i a10, sp, XT_STK_A10\r
+ l32i a11, sp, XT_STK_A11\r
+\r
+ /*\r
+ Call0 ABI callee-saved regs a12-15 do not need to be restored here.\r
+ However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), \r
+ so need to be restored anyway, despite being callee-saved in Call0.\r
+ */\r
+ l32i a12, sp, XT_STK_A12\r
+ l32i a13, sp, XT_STK_A13\r
+ #ifndef __XTENSA_CALL0_ABI__\r
+ l32i a14, sp, XT_STK_A14\r
+ l32i a15, sp, XT_STK_A15\r
+ #endif\r
+\r
+ ret\r
+\r
+\r
+/*******************************************************************************\r
+\r
+_xt_coproc_init\r
+\r
+Initializes global co-processor management data, setting all co-processors\r
+to "unowned". Leaves CPENABLE as it found it (does NOT clear it).\r
+\r
+Called during initialization of the RTOS, before any threads run.\r
+\r
+This may be called from normal Xtensa single-threaded application code which\r
+might use co-processors. The Xtensa run-time initialization enables all \r
+co-processors. They must remain enabled here, else a co-processor exception\r
+might occur outside of a thread, which the exception handler doesn't expect.\r
+\r
+Entry Conditions:\r
+ Xtensa single-threaded run-time environment is in effect.\r
+ No thread is yet running.\r
+\r
+Exit conditions:\r
+ None.\r
+\r
+Obeys ABI conventions per prototype:\r
+ void _xt_coproc_init(void)\r
+\r
+*******************************************************************************/\r
+\r
+#if XCHAL_CP_NUM > 0\r
+\r
+ .global _xt_coproc_init\r
+ .type _xt_coproc_init,@function\r
+ .align 4\r
+_xt_coproc_init:\r
+ ENTRY0\r
+\r
+ /* Initialize thread co-processor ownerships to 0 (unowned). */\r
+ movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */\r
+ addi a3, a2, XCHAL_CP_MAX << 2 /* a3 = top+1 of owner array */\r
+ movi a4, 0 /* a4 = 0 (unowned) */\r
+1: s32i a4, a2, 0\r
+ addi a2, a2, 4\r
+ bltu a2, a3, 1b\r
+\r
+ RET0\r
+\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+\r
+_xt_coproc_release\r
+\r
+Releases any and all co-processors owned by a given thread. The thread is \r
+identified by it's co-processor state save area defined in xtensa_context.h .\r
+\r
+Must be called before a thread's co-proc save area is deleted to avoid\r
+memory corruption when the exception handler tries to save the state.\r
+May be called when a thread terminates or completes but does not delete\r
+the co-proc save area, to avoid the exception handler having to save the \r
+thread's co-proc state before another thread can use it (optimization).\r
+\r
+Entry Conditions:\r
+ A2 = Pointer to base of co-processor state save area.\r
+\r
+Exit conditions:\r
+ None.\r
+\r
+Obeys ABI conventions per prototype:\r
+ void _xt_coproc_release(void * coproc_sa_base)\r
+\r
+*******************************************************************************/\r
+\r
+#if XCHAL_CP_NUM > 0\r
+\r
+ .global _xt_coproc_release\r
+ .type _xt_coproc_release,@function\r
+ .align 4\r
+_xt_coproc_release:\r
+ ENTRY0 /* a2 = base of save area */\r
+\r
+ movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */\r
+ addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */\r
+ movi a5, 0 /* a5 = 0 (unowned) */\r
+\r
+ rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */\r
+\r
+1: l32i a7, a3, 0 /* a7 = owner at a3 */\r
+ bne a2, a7, 2f /* if (coproc_sa_base == owner) */\r
+ s32i a5, a3, 0 /* owner = unowned */\r
+2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */\r
+ bltu a3, a4, 1b /* repeat until end of array */\r
+\r
+3: wsr a6, PS /* restore interrupts */\r
+\r
+ RET0\r
+\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+_xt_coproc_savecs\r
+\r
+If there is a current thread and it has a coprocessor state save area, then\r
+save all callee-saved state into this area. This function is called from the\r
+solicited context switch handler. It calls a system-specific function to get\r
+the coprocessor save area base address.\r
+\r
+Entry conditions:\r
+ - The thread being switched out is still the current thread.\r
+ - CPENABLE state reflects which coprocessors are active.\r
+ - Registers have been saved/spilled already.\r
+\r
+Exit conditions:\r
+ - All necessary CP callee-saved state has been saved.\r
+ - Registers a2-a7, a13-a15 have been trashed.\r
+\r
+Must be called from assembly code only, using CALL0.\r
+*******************************************************************************/\r
+#if XCHAL_CP_NUM > 0\r
+\r
+ .extern _xt_coproc_sa_offset /* external reference */\r
+\r
+ .global _xt_coproc_savecs\r
+ .type _xt_coproc_savecs,@function\r
+ .align 4\r
+_xt_coproc_savecs:\r
+\r
+ /* At entry, CPENABLE should be showing which CPs are enabled. */\r
+\r
+ rsr a2, CPENABLE /* a2 = which CPs are enabled */\r
+ beqz a2, .Ldone /* quick exit if none */\r
+ mov a14, a0 /* save return address */\r
+ call0 XT_RTOS_CP_STATE /* get address of CP save area */\r
+ mov a0, a14 /* restore return address */\r
+ beqz a15, .Ldone /* if none then nothing to do */\r
+ s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */\r
+ movi a13, _xt_coproc_sa_offset /* array of CP save offsets */\r
+ l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */\r
+\r
+#if XCHAL_CP0_SA_SIZE\r
+ bbci.l a2, 0, 2f /* CP 0 not enabled */\r
+ l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */\r
+ add a3, a14, a15 /* a3 = save area for CP 0 */\r
+ xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP1_SA_SIZE\r
+ bbci.l a2, 1, 2f /* CP 1 not enabled */\r
+ l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */\r
+ add a3, a14, a15 /* a3 = save area for CP 1 */\r
+ xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP2_SA_SIZE\r
+ bbci.l a2, 2, 2f\r
+ l32i a14, a13, 8\r
+ add a3, a14, a15\r
+ xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP3_SA_SIZE\r
+ bbci.l a2, 3, 2f\r
+ l32i a14, a13, 12\r
+ add a3, a14, a15\r
+ xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP4_SA_SIZE\r
+ bbci.l a2, 4, 2f\r
+ l32i a14, a13, 16\r
+ add a3, a14, a15\r
+ xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP5_SA_SIZE\r
+ bbci.l a2, 5, 2f\r
+ l32i a14, a13, 20\r
+ add a3, a14, a15\r
+ xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP6_SA_SIZE\r
+ bbci.l a2, 6, 2f\r
+ l32i a14, a13, 24\r
+ add a3, a14, a15\r
+ xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP7_SA_SIZE\r
+ bbci.l a2, 7, 2f\r
+ l32i a14, a13, 28\r
+ add a3, a14, a15\r
+ xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+.Ldone:\r
+ ret\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+_xt_coproc_restorecs\r
+\r
+Restore any callee-saved coprocessor state for the incoming thread.\r
+This function is called from coprocessor exception handling, when giving\r
+ownership to a thread that solicited a context switch earlier. It calls a\r
+system-specific function to get the coprocessor save area base address.\r
+\r
+Entry conditions:\r
+ - The incoming thread is set as the current thread.\r
+ - CPENABLE is set up correctly for all required coprocessors.\r
+ - a2 = mask of coprocessors to be restored.\r
+\r
+Exit conditions:\r
+ - All necessary CP callee-saved state has been restored.\r
+ - CPENABLE - unchanged.\r
+ - Registers a2-a7, a13-a15 have been trashed.\r
+\r
+Must be called from assembly code only, using CALL0.\r
+*******************************************************************************/\r
+#if XCHAL_CP_NUM > 0\r
+\r
+ .global _xt_coproc_restorecs\r
+ .type _xt_coproc_restorecs,@function\r
+ .align 4\r
+_xt_coproc_restorecs:\r
+\r
+ mov a14, a0 /* save return address */\r
+ call0 XT_RTOS_CP_STATE /* get address of CP save area */\r
+ mov a0, a14 /* restore return address */\r
+ beqz a15, .Ldone2 /* if none then nothing to do */\r
+ l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */\r
+ xor a3, a3, a2 /* clear the ones being restored */\r
+ s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */\r
+ movi a13, _xt_coproc_sa_offset /* array of CP save offsets */\r
+ l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */\r
+ \r
+#if XCHAL_CP0_SA_SIZE\r
+ bbci.l a2, 0, 2f /* CP 0 not enabled */\r
+ l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */\r
+ add a3, a14, a15 /* a3 = save area for CP 0 */\r
+ xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2: \r
+#endif\r
+\r
+#if XCHAL_CP1_SA_SIZE\r
+ bbci.l a2, 1, 2f /* CP 1 not enabled */\r
+ l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */\r
+ add a3, a14, a15 /* a3 = save area for CP 1 */\r
+ xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP2_SA_SIZE\r
+ bbci.l a2, 2, 2f\r
+ l32i a14, a13, 8\r
+ add a3, a14, a15\r
+ xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP3_SA_SIZE\r
+ bbci.l a2, 3, 2f\r
+ l32i a14, a13, 12\r
+ add a3, a14, a15\r
+ xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP4_SA_SIZE\r
+ bbci.l a2, 4, 2f\r
+ l32i a14, a13, 16\r
+ add a3, a14, a15\r
+ xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP5_SA_SIZE\r
+ bbci.l a2, 5, 2f\r
+ l32i a14, a13, 20\r
+ add a3, a14, a15\r
+ xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP6_SA_SIZE\r
+ bbci.l a2, 6, 2f\r
+ l32i a14, a13, 24\r
+ add a3, a14, a15\r
+ xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+#if XCHAL_CP7_SA_SIZE\r
+ bbci.l a2, 7, 2f\r
+ l32i a14, a13, 28\r
+ add a3, a14, a15\r
+ xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL\r
+2:\r
+#endif\r
+\r
+.Ldone2:\r
+ ret\r
+\r
+#endif\r
+\r
--- /dev/null
+/*******************************************************************************\r
+Copyright (c) 2006-2015 Cadence Design Systems Inc.\r
+\r
+Permission is hereby granted, free of charge, to any person obtaining\r
+a copy of this software and associated documentation files (the\r
+"Software"), to deal in the Software without restriction, including\r
+without limitation the rights to use, copy, modify, merge, publish,\r
+distribute, sublicense, and/or sell copies of the Software, and to\r
+permit persons to whom the Software is furnished to do so, subject to\r
+the following conditions:\r
+\r
+The above copyright notice and this permission notice shall be included\r
+in all copies or substantial portions of the Software.\r
+\r
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+\r
+ XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES\r
+\r
+This header contains definitions and macros for use primarily by Xtensa\r
+RTOS assembly coded source files. It includes and uses the Xtensa hardware\r
+abstraction layer (HAL) to deal with config specifics. It may also be\r
+included in C source files.\r
+\r
+!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!\r
+\r
+NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.\r
+\r
+*******************************************************************************/\r
+\r
+#ifndef XTENSA_CONTEXT_H\r
+#define XTENSA_CONTEXT_H\r
+\r
+#ifdef __ASSEMBLER__\r
+#include <xtensa/coreasm.h>\r
+#endif\r
+\r
+#include <xtensa/config/tie.h>\r
+#include <xtensa/corebits.h>\r
+#include <xtensa/config/system.h>\r
+\r
+\r
+/* Align a value up to nearest n-byte boundary, where n is a power of 2. */\r
+#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Macros that help define structures for both C and assembler.\r
+-------------------------------------------------------------------------------\r
+*/\r
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)\r
+\r
+#define STRUCT_BEGIN .pushsection .text; .struct 0\r
+#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size\r
+#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n)\r
+#define STRUCT_END(sname) sname##Size:; .popsection\r
+\r
+#else\r
+\r
+#define STRUCT_BEGIN typedef struct {\r
+#define STRUCT_FIELD(ctype,size,asname,name) ctype name;\r
+#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];\r
+#define STRUCT_END(sname) } sname;\r
+\r
+#endif //_ASMLANGUAGE || __ASSEMBLER__\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT\r
+\r
+ A stack frame of this structure is allocated for any interrupt or exception.\r
+ It goes on the current stack. If the RTOS has a system stack for handling \r
+ interrupts, every thread stack must allow space for just one interrupt stack \r
+ frame, then nested interrupt stack frames go on the system stack.\r
+\r
+ The frame includes basic registers (explicit) and "extra" registers introduced \r
+ by user TIE or the use of the MAC16 option in the user's Xtensa config.\r
+ The frame size is minimized by omitting regs not applicable to user's config.\r
+\r
+ For Windowed ABI, this stack frame includes the interruptee's base save area,\r
+ another base save area to manage gcc nested functions, and a little temporary \r
+ space to help manage the spilling of the register windows.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+STRUCT_BEGIN\r
+STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */\r
+STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */\r
+STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */\r
+STRUCT_FIELD (long, 4, XT_STK_A0, a0)\r
+STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */\r
+STRUCT_FIELD (long, 4, XT_STK_A2, a2)\r
+STRUCT_FIELD (long, 4, XT_STK_A3, a3)\r
+STRUCT_FIELD (long, 4, XT_STK_A4, a4)\r
+STRUCT_FIELD (long, 4, XT_STK_A5, a5)\r
+STRUCT_FIELD (long, 4, XT_STK_A6, a6)\r
+STRUCT_FIELD (long, 4, XT_STK_A7, a7)\r
+STRUCT_FIELD (long, 4, XT_STK_A8, a8)\r
+STRUCT_FIELD (long, 4, XT_STK_A9, a9)\r
+STRUCT_FIELD (long, 4, XT_STK_A10, a10)\r
+STRUCT_FIELD (long, 4, XT_STK_A11, a11)\r
+STRUCT_FIELD (long, 4, XT_STK_A12, a12)\r
+STRUCT_FIELD (long, 4, XT_STK_A13, a13)\r
+STRUCT_FIELD (long, 4, XT_STK_A14, a14)\r
+STRUCT_FIELD (long, 4, XT_STK_A15, a15)\r
+STRUCT_FIELD (long, 4, XT_STK_SAR, sar)\r
+STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)\r
+STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)\r
+#if XCHAL_HAVE_LOOPS\r
+STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg)\r
+STRUCT_FIELD (long, 4, XT_STK_LEND, lend)\r
+STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)\r
+#endif\r
+#ifndef __XTENSA_CALL0_ABI__\r
+/* Temporary space for saving stuff during window spill */\r
+STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0)\r
+STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1)\r
+STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2)\r
+#endif\r
+#ifdef XT_USE_SWPRI\r
+/* Storage for virtual priority mask */\r
+STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri)\r
+#endif\r
+#ifdef XT_USE_OVLY\r
+/* Storage for overlay state */\r
+STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly)\r
+#endif\r
+STRUCT_END(XtExcFrame)\r
+\r
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)\r
+#define XT_STK_NEXT1 XtExcFrameSize\r
+#else\r
+#define XT_STK_NEXT1 sizeof(XtExcFrame)\r
+#endif\r
+\r
+/* Allocate extra storage if needed */\r
+#if XCHAL_EXTRA_SA_SIZE != 0\r
+\r
+#if XCHAL_EXTRA_SA_ALIGN <= 16\r
+#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)\r
+#else\r
+/* If need more alignment than stack, add space for dynamic alignment */\r
+#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)\r
+#endif\r
+#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)\r
+\r
+#else\r
+\r
+#define XT_STK_NEXT2 XT_STK_NEXT1 \r
+\r
+#endif\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ This is the frame size. Add space for 4 registers (interruptee's base save\r
+ area) and some space for gcc nested functions if any.\r
+-------------------------------------------------------------------------------\r
+*/\r
+#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ SOLICITED STACK FRAME FOR A THREAD\r
+\r
+ A stack frame of this structure is allocated whenever a thread enters the \r
+ RTOS kernel intentionally (and synchronously) to submit to thread scheduling.\r
+ It goes on the current thread's stack.\r
+\r
+ The solicited frame only includes registers that are required to be preserved\r
+ by the callee according to the compiler's ABI conventions, some space to save \r
+ the return address for returning to the caller, and the caller's PS register.\r
+\r
+ For Windowed ABI, this stack frame includes the caller's base save area.\r
+\r
+ Note on XT_SOL_EXIT field:\r
+ It is necessary to distinguish a solicited from an interrupt stack frame.\r
+ This field corresponds to XT_STK_EXIT in the interrupt stack frame and is\r
+ always at the same offset (0). It can be written with a code (usually 0) \r
+ to distinguish a solicted frame from an interrupt frame. An RTOS port may\r
+ opt to ignore this field if it has another way of distinguishing frames.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+STRUCT_BEGIN\r
+#ifdef __XTENSA_CALL0_ABI__\r
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)\r
+STRUCT_FIELD (long, 4, XT_SOL_PC, pc)\r
+STRUCT_FIELD (long, 4, XT_SOL_PS, ps)\r
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)\r
+STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */\r
+STRUCT_FIELD (long, 4, XT_SOL_A13, a13)\r
+STRUCT_FIELD (long, 4, XT_SOL_A14, a14)\r
+STRUCT_FIELD (long, 4, XT_SOL_A15, a15)\r
+#else\r
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)\r
+STRUCT_FIELD (long, 4, XT_SOL_PC, pc)\r
+STRUCT_FIELD (long, 4, XT_SOL_PS, ps)\r
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)\r
+STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */\r
+STRUCT_FIELD (long, 4, XT_SOL_A1, a1)\r
+STRUCT_FIELD (long, 4, XT_SOL_A2, a2)\r
+STRUCT_FIELD (long, 4, XT_SOL_A3, a3)\r
+#endif\r
+STRUCT_END(XtSolFrame)\r
+\r
+/* Size of solicited stack frame */\r
+#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize)\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ CO-PROCESSOR STATE SAVE AREA FOR A THREAD\r
+\r
+ The RTOS must provide an area per thread to save the state of co-processors\r
+ when that thread does not have control. Co-processors are context-switched\r
+ lazily (on demand) only when a new thread uses a co-processor instruction,\r
+ otherwise a thread retains ownership of the co-processor even when it loses\r
+ control of the processor. An Xtensa co-processor exception is triggered when\r
+ any co-processor instruction is executed by a thread that is not the owner,\r
+ and the context switch of that co-processor is then peformed by the handler.\r
+ Ownership represents which thread's state is currently in the co-processor.\r
+\r
+ Co-processors may not be used by interrupt or exception handlers. If an \r
+ co-processor instruction is executed by an interrupt or exception handler,\r
+ the co-processor exception handler will trigger a kernel panic and freeze.\r
+ This restriction is introduced to reduce the overhead of saving and restoring\r
+ co-processor state (which can be quite large) and in particular remove that\r
+ overhead from interrupt handlers.\r
+\r
+ The co-processor state save area may be in any convenient per-thread location\r
+ such as in the thread control block or above the thread stack area. It need\r
+ not be in the interrupt stack frame since interrupts don't use co-processors.\r
+\r
+ Along with the save area for each co-processor, two bitmasks with flags per \r
+ co-processor (laid out as in the CPENABLE reg) help manage context-switching\r
+ co-processors as efficiently as possible:\r
+\r
+ XT_CPENABLE\r
+ The contents of a non-running thread's CPENABLE register.\r
+ It represents the co-processors owned (and whose state is still needed)\r
+ by the thread. When a thread is preempted, its CPENABLE is saved here.\r
+ When a thread solicits a context-swtich, its CPENABLE is cleared - the\r
+ compiler has saved the (caller-saved) co-proc state if it needs to.\r
+ When a non-running thread loses ownership of a CP, its bit is cleared.\r
+ When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.\r
+ Avoids co-processor exceptions when no change of ownership is needed.\r
+\r
+ XT_CPSTORED\r
+ A bitmask with the same layout as CPENABLE, a bit per co-processor.\r
+ Indicates whether the state of each co-processor is saved in the state \r
+ save area. When a thread enters the kernel, only the state of co-procs\r
+ still enabled in CPENABLE is saved. When the co-processor exception \r
+ handler assigns ownership of a co-processor to a thread, it restores \r
+ the saved state only if this bit is set, and clears this bit.\r
+\r
+ XT_CP_CS_ST\r
+ A bitmask with the same layout as CPENABLE, a bit per co-processor.\r
+ Indicates whether callee-saved state is saved in the state save area.\r
+ Callee-saved state is saved by itself on a solicited context switch,\r
+ and restored when needed by the coprocessor exception handler.\r
+ Unsolicited switches will cause the entire coprocessor to be saved\r
+ when necessary.\r
+\r
+ XT_CP_ASA\r
+ Pointer to the aligned save area. Allows it to be aligned more than\r
+ the overall save area (which might only be stack-aligned or TCB-aligned).\r
+ Especially relevant for Xtensa cores configured with a very large data\r
+ path that requires alignment greater than 16 bytes (ABI stack alignment).\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+#if XCHAL_CP_NUM > 0\r
+\r
+/* Offsets of each coprocessor save area within the 'aligned save area': */\r
+#define XT_CP0_SA 0\r
+#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)\r
+#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)\r
+#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)\r
+#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)\r
+#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)\r
+#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)\r
+#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)\r
+#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)\r
+\r
+/* Offsets within the overall save area: */\r
+#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */\r
+#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */\r
+#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */\r
+#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */\r
+/* Overall size allows for dynamic alignment: */\r
+#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)\r
+#else\r
+#define XT_CP_SIZE 0\r
+#endif\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN\r
+\r
+ Convenient where the frame size requirements are the same for both ABIs.\r
+ ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).\r
+ ENTRY0, RET0 are for frameless functions (no locals, no calls).\r
+\r
+ where size = size of stack frame in bytes (must be >0 and aligned to 16).\r
+ For framed functions the frame is created and the return address saved at\r
+ base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).\r
+ For frameless functions, there is no frame and return address remains in a0.\r
+ Note: Because CPP macros expand to a single line, macros requiring multi-line \r
+ expansions are implemented as assembler macros.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+#ifdef __ASSEMBLER__\r
+#ifdef __XTENSA_CALL0_ABI__\r
+ /* Call0 */\r
+ #define ENTRY(sz) entry1 sz\r
+ .macro entry1 size=0x10\r
+ addi sp, sp, -\size\r
+ s32i a0, sp, 0\r
+ .endm\r
+ #define ENTRY0 \r
+ #define RET(sz) ret1 sz\r
+ .macro ret1 size=0x10\r
+ l32i a0, sp, 0\r
+ addi sp, sp, \size\r
+ ret\r
+ .endm\r
+ #define RET0 ret\r
+#else\r
+ /* Windowed */\r
+ #define ENTRY(sz) entry sp, sz\r
+ #define ENTRY0 entry sp, 0x10\r
+ #define RET(sz) retw\r
+ #define RET0 retw\r
+#endif\r
+#endif\r
+\r
+\r
+#endif /* XTENSA_CONTEXT_H */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+\r
+ XTENSA INITIALIZATION ROUTINES CODED IN C\r
+\r
+This file contains miscellaneous Xtensa RTOS-generic initialization functions\r
+that are implemented in C.\r
+\r
+*******************************************************************************/\r
+\r
+\r
+#ifdef XT_BOARD\r
+#include <xtensa/xtbsp.h>\r
+#endif\r
+\r
+#include "xtensa_rtos.h"\r
+\r
+#ifdef XT_RTOS_TIMER_INT\r
+\r
+unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */\r
+\r
+/*\r
+Compute and initialize at run-time the tick divisor (the number of \r
+processor clock cycles in an RTOS tick, used to set the tick timer).\r
+Called when the processor clock frequency is not known at compile-time.\r
+*/\r
+void _xt_tick_divisor_init(void)\r
+{\r
+#ifdef XT_CLOCK_FREQ\r
+\r
+ _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC);\r
+\r
+#else\r
+\r
+ #ifdef XT_BOARD\r
+ _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;\r
+ #else\r
+ #error "No way to obtain processor clock frequency"\r
+ #endif /* XT_BOARD */\r
+\r
+#endif /* XT_CLOCK_FREQ */\r
+}\r
+\r
+#endif /* XT_RTOS_TIMER_INT */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+Copyright (c) 2006-2015 Cadence Design Systems Inc.\r
+\r
+Permission is hereby granted, free of charge, to any person obtaining\r
+a copy of this software and associated documentation files (the\r
+"Software"), to deal in the Software without restriction, including\r
+without limitation the rights to use, copy, modify, merge, publish,\r
+distribute, sublicense, and/or sell copies of the Software, and to\r
+permit persons to whom the Software is furnished to do so, subject to\r
+the following conditions:\r
+\r
+The above copyright notice and this permission notice shall be included\r
+in all copies or substantial portions of the Software.\r
+\r
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+ Xtensa-specific interrupt and exception functions for RTOS ports.\r
+ Also see xtensa_intr_asm.S.\r
+******************************************************************************/\r
+\r
+#include <stdlib.h>\r
+\r
+#include <xtensa/config/core.h>\r
+\r
+#include "xtensa_api.h"\r
+\r
+\r
+#if XCHAL_HAVE_EXCEPTIONS\r
+\r
+/* Handler table is in xtensa_intr_asm.S */\r
+\r
+extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];\r
+\r
+\r
+/*\r
+ Default handler for unhandled exceptions.\r
+*/\r
+void xt_unhandled_exception(XtExcFrame *frame)\r
+{\r
+ exit(-1);\r
+}\r
+\r
+\r
+/*\r
+ This function registers a handler for the specified exception.\r
+ The function returns the address of the previous handler.\r
+ On error, it returns 0.\r
+*/\r
+xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)\r
+{\r
+ xt_exc_handler old;\r
+\r
+ if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )\r
+ return 0; /* invalid exception number */\r
+\r
+ old = _xt_exception_table[n];\r
+\r
+ if (f) {\r
+ _xt_exception_table[n] = f;\r
+ }\r
+ else {\r
+ _xt_exception_table[n] = &xt_unhandled_exception;\r
+ }\r
+\r
+ return ((old == &xt_unhandled_exception) ? 0 : old);\r
+}\r
+\r
+#endif\r
+\r
+#if XCHAL_HAVE_INTERRUPTS\r
+\r
+/* Handler table is in xtensa_intr_asm.S */\r
+\r
+typedef struct xt_handler_table_entry {\r
+ void * handler;\r
+ void * arg;\r
+} xt_handler_table_entry;\r
+\r
+extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS];\r
+\r
+\r
+/*\r
+ Default handler for unhandled interrupts.\r
+*/\r
+void xt_unhandled_interrupt(void * arg)\r
+{\r
+ exit(-1);\r
+}\r
+\r
+\r
+/*\r
+ This function registers a handler for the specified interrupt. The "arg"\r
+ parameter specifies the argument to be passed to the handler when it is\r
+ invoked. The function returns the address of the previous handler.\r
+ On error, it returns 0.\r
+*/\r
+xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)\r
+{\r
+ xt_handler_table_entry * entry;\r
+ xt_handler old;\r
+\r
+ if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )\r
+ return 0; /* invalid interrupt number */\r
+ if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )\r
+ return 0; /* priority level too high to safely handle in C */\r
+\r
+ entry = _xt_interrupt_table + n;\r
+ old = entry->handler;\r
+\r
+ if (f) {\r
+ entry->handler = f;\r
+ entry->arg = arg;\r
+ }\r
+ else {\r
+ entry->handler = &xt_unhandled_interrupt;\r
+ entry->arg = (void*)n;\r
+ }\r
+\r
+ return ((old == &xt_unhandled_interrupt) ? 0 : old);\r
+}\r
+\r
+\r
+#endif /* XCHAL_HAVE_INTERRUPTS */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+Copyright (c) 2006-2015 Cadence Design Systems Inc.\r
+\r
+Permission is hereby granted, free of charge, to any person obtaining\r
+a copy of this software and associated documentation files (the\r
+"Software"), to deal in the Software without restriction, including\r
+without limitation the rights to use, copy, modify, merge, publish,\r
+distribute, sublicense, and/or sell copies of the Software, and to\r
+permit persons to whom the Software is furnished to do so, subject to\r
+the following conditions:\r
+\r
+The above copyright notice and this permission notice shall be included\r
+in all copies or substantial portions of the Software.\r
+\r
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+ Xtensa interrupt handling data and assembly routines.\r
+ Also see xtensa_intr.c and xtensa_vectors.S.\r
+******************************************************************************/\r
+\r
+#include <xtensa/hal.h>\r
+#include <xtensa/config/core.h>\r
+\r
+#include "xtensa_context.h"\r
+\r
+#if XCHAL_HAVE_INTERRUPTS\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ INTENABLE virtualization information.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+ .data\r
+ .global _xt_intdata\r
+ .align 8\r
+_xt_intdata:\r
+ .global _xt_intenable\r
+ .type _xt_intenable,@object\r
+ .size _xt_intenable,4\r
+ .global _xt_vpri_mask\r
+ .type _xt_vpri_mask,@object\r
+ .size _xt_vpri_mask,4\r
+\r
+_xt_intenable: .word 0 /* Virtual INTENABLE */\r
+_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Table of C-callable interrupt handlers for each interrupt. Note that not all\r
+ slots can be filled, because interrupts at level > EXCM_LEVEL will not be\r
+ dispatched to a C handler by default.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+ .data\r
+ .global _xt_interrupt_table\r
+ .align 8\r
+\r
+_xt_interrupt_table:\r
+\r
+ .set i, 0\r
+ .rept XCHAL_NUM_INTERRUPTS\r
+ .word xt_unhandled_interrupt /* handler address */\r
+ .word i /* handler arg (default: intnum) */\r
+ .set i, i+1\r
+ .endr\r
+\r
+#endif /* XCHAL_HAVE_INTERRUPTS */\r
+\r
+\r
+#if XCHAL_HAVE_EXCEPTIONS\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Table of C-callable exception handlers for each exception. Note that not all\r
+ slots will be active, because some exceptions (e.g. coprocessor exceptions)\r
+ are always handled by the OS and cannot be hooked by user handlers.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+ .data\r
+ .global _xt_exception_table\r
+ .align 4\r
+\r
+_xt_exception_table:\r
+ .rept XCHAL_EXCCAUSE_NUM\r
+ .word xt_unhandled_exception /* handler address */\r
+ .endr\r
+\r
+#endif\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ unsigned int xt_ints_on ( unsigned int mask )\r
+\r
+ Enables a set of interrupts. Does not simply set INTENABLE directly, but\r
+ computes it as a function of the current virtual priority.\r
+ Can be called from interrupt handlers.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+ .text\r
+ .align 4\r
+ .global xt_ints_on\r
+ .type xt_ints_on,@function\r
+\r
+xt_ints_on:\r
+\r
+ ENTRY0\r
+#if XCHAL_HAVE_INTERRUPTS\r
+ movi a3, 0\r
+ movi a4, _xt_intdata\r
+ xsr a3, INTENABLE /* Disables all interrupts */\r
+ rsync\r
+ l32i a3, a4, 0 /* a3 = _xt_intenable */\r
+ l32i a6, a4, 4 /* a6 = _xt_vpri_mask */\r
+ or a5, a3, a2 /* a5 = _xt_intenable | mask */\r
+ s32i a5, a4, 0 /* _xt_intenable |= mask */\r
+ and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */\r
+ wsr a5, INTENABLE /* Reenable interrupts */\r
+ mov a2, a3 /* Previous mask */\r
+#else\r
+ movi a2, 0 /* Return zero */\r
+#endif\r
+ RET0\r
+\r
+ .size xt_ints_on, . - xt_ints_on\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ unsigned int xt_ints_off ( unsigned int mask )\r
+\r
+ Disables a set of interrupts. Does not simply set INTENABLE directly,\r
+ but computes it as a function of the current virtual priority.\r
+ Can be called from interrupt handlers.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+ .text\r
+ .align 4\r
+ .global xt_ints_off\r
+ .type xt_ints_off,@function\r
+\r
+xt_ints_off:\r
+\r
+ ENTRY0\r
+#if XCHAL_HAVE_INTERRUPTS\r
+ movi a3, 0\r
+ movi a4, _xt_intdata\r
+ xsr a3, INTENABLE /* Disables all interrupts */\r
+ rsync\r
+ l32i a3, a4, 0 /* a3 = _xt_intenable */\r
+ l32i a6, a4, 4 /* a6 = _xt_vpri_mask */\r
+ or a5, a3, a2 /* a5 = _xt_intenable | mask */\r
+ xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */\r
+ s32i a5, a4, 0 /* _xt_intenable &= ~mask */\r
+ and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */\r
+ wsr a5, INTENABLE /* Reenable interrupts */\r
+ mov a2, a3 /* Previous mask */\r
+#else\r
+ movi a2, 0 /* return zero */\r
+#endif\r
+ RET0\r
+\r
+ .size xt_ints_off, . - xt_ints_off\r
+\r
+\r
--- /dev/null
+// xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS.\r
+\r
+// Copyright (c) 2015-2015 Cadence Design Systems Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+\r
+#if configUSE_MUTEX\r
+\r
+/* Mutex object that controls access to the overlay. Currently only one\r
+ * overlay region is supported so one mutex suffices.\r
+ */\r
+static SemaphoreHandle_t xt_overlay_mutex;\r
+\r
+\r
+/* This function should be overridden to provide OS specific init such\r
+ * as the creation of a mutex lock that can be used for overlay locking.\r
+ * Typically this mutex would be set up with priority inheritance. See\r
+ * overlay manager documentation for more details.\r
+ */\r
+void xt_overlay_init_os(void)\r
+{\r
+ /* Create the mutex for overlay access. Priority inheritance is\r
+ * required.\r
+ */\r
+ xt_overlay_mutex = xSemaphoreCreateMutex();\r
+}\r
+\r
+\r
+/* This function locks access to shared overlay resources, typically\r
+ * by acquiring a mutex.\r
+ */\r
+void xt_overlay_lock(void)\r
+{\r
+ xSemaphoreTake(xt_overlay_mutex, 0);\r
+}\r
+\r
+\r
+/* This function releases access to shared overlay resources, typically\r
+ * by unlocking a mutex.\r
+ */\r
+void xt_overlay_unlock(void)\r
+{\r
+ xSemaphoreGive(xt_overlay_mutex);\r
+}\r
+\r
+#endif\r
--- /dev/null
+/*******************************************************************************\r
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+\r
+ RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES\r
+ (FreeRTOS Port)\r
+\r
+This header is the primary glue between generic Xtensa RTOS support\r
+sources and a specific RTOS port for Xtensa. It contains definitions\r
+and macros for use primarily by Xtensa assembly coded source files.\r
+\r
+Macros in this header map callouts from generic Xtensa files to specific\r
+RTOS functions. It may also be included in C source files.\r
+\r
+Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa \r
+architecture, using the Xtensa hardware abstraction layer (HAL) to deal \r
+with configuration specifics.\r
+\r
+Should be included by all Xtensa generic and RTOS port-specific sources.\r
+\r
+*******************************************************************************/\r
+\r
+#ifndef XTENSA_RTOS_H\r
+#define XTENSA_RTOS_H\r
+\r
+#ifdef __ASSEMBLER__\r
+#include <xtensa/coreasm.h>\r
+#else\r
+#include <xtensa/config/core.h>\r
+#endif\r
+\r
+#include <xtensa/corebits.h>\r
+#include <xtensa/config/system.h>\r
+#include <xtensa/simcall.h>\r
+\r
+/*\r
+Include any RTOS specific definitions that are needed by this header.\r
+*/\r
+#include <FreeRTOSConfig.h>\r
+\r
+/*\r
+Convert FreeRTOSConfig definitions to XTENSA definitions.\r
+However these can still be overridden from the command line.\r
+*/\r
+\r
+#ifndef XT_SIMULATOR\r
+ #if configXT_SIMULATOR\r
+ #define XT_SIMULATOR 1 /* Simulator mode */\r
+ #endif\r
+#endif\r
+\r
+#ifndef XT_BOARD\r
+ #if configXT_BOARD\r
+ #define XT_BOARD 1 /* Board mode */\r
+ #endif\r
+#endif\r
+\r
+#ifndef XT_TIMER_INDEX\r
+ #if defined configXT_TIMER_INDEX\r
+ #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */\r
+ #endif\r
+#endif\r
+\r
+#ifndef XT_INTEXC_HOOKS\r
+ #if configXT_INTEXC_HOOKS\r
+ #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */\r
+ #endif\r
+#endif\r
+\r
+#if (!XT_SIMULATOR) && (!XT_BOARD)\r
+ #error Either XT_SIMULATOR or XT_BOARD must be defined.\r
+#endif\r
+\r
+\r
+/*\r
+Name of RTOS (for messages).\r
+*/\r
+#define XT_RTOS_NAME FreeRTOS\r
+\r
+/*\r
+Check some Xtensa configuration requirements and report error if not met.\r
+Error messages can be customize to the RTOS port.\r
+*/\r
+\r
+#if !XCHAL_HAVE_XEA2\r
+#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+\r
+RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.\r
+\r
+Define callout macros used in generic Xtensa code to interact with the RTOS.\r
+The macros are simply the function names for use in calls from assembler code.\r
+Some of these functions may call back to generic functions in xtensa_context.h .\r
+\r
+*******************************************************************************/\r
+\r
+/*\r
+Inform RTOS of entry into an interrupt handler that will affect it. \r
+Allows RTOS to manage switch to any system stack and count nesting level.\r
+Called after minimal context has been saved, with interrupts disabled.\r
+RTOS port can call0 _xt_context_save to save the rest of the context.\r
+May only be called from assembly code by the 'call0' instruction.\r
+*/\r
+// void XT_RTOS_INT_ENTER(void)\r
+#define XT_RTOS_INT_ENTER _frxt_int_enter\r
+\r
+/*\r
+Inform RTOS of completion of an interrupt handler, and give control to\r
+RTOS to perform thread/task scheduling, switch back from any system stack\r
+and restore the context, and return to the exit dispatcher saved in the\r
+stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore\r
+to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,\r
+leaving only a minimal part of the context to be restored by the exit\r
+dispatcher. This function does not return to the place it was called from.\r
+May only be called from assembly code by the 'call0' instruction.\r
+*/\r
+// void XT_RTOS_INT_EXIT(void)\r
+#define XT_RTOS_INT_EXIT _frxt_int_exit\r
+\r
+/*\r
+Inform RTOS of the occurrence of a tick timer interrupt.\r
+If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.\r
+May be coded in or called from C or assembly, per ABI conventions.\r
+RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).\r
+*/\r
+// void XT_RTOS_TIMER_INT(void)\r
+#define XT_RTOS_TIMER_INT _frxt_timer_int\r
+#define XT_TICK_PER_SEC configTICK_RATE_HZ\r
+\r
+/*\r
+Return in a15 the base address of the co-processor state save area for the \r
+thread that triggered a co-processor exception, or 0 if no thread was running.\r
+The state save area is structured as defined in xtensa_context.h and has size \r
+XT_CP_SIZE. Co-processor instructions should only be used in thread code, never\r
+in interrupt handlers or the RTOS kernel. May only be called from assembly code\r
+and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. \r
+The implementation may use only a2-4, a15 (all other regs must be preserved).\r
+*/\r
+// void* XT_RTOS_CP_STATE(void)\r
+#define XT_RTOS_CP_STATE _frxt_task_coproc_state\r
+\r
+\r
+/*******************************************************************************\r
+\r
+HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.\r
+\r
+This Xtensa RTOS port provides hooks for dynamically installing exception\r
+and interrupt handlers to facilitate automated testing where each test\r
+case can install its own handler for user exceptions and each interrupt\r
+priority (level). This consists of an array of function pointers indexed\r
+by interrupt priority, with index 0 being the user exception handler hook.\r
+Each entry in the array is initially 0, and may be replaced by a function \r
+pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.\r
+\r
+The handler for low and medium priority obeys ABI conventions so may be coded\r
+in C. For the exception handler, the cause is the contents of the EXCCAUSE\r
+reg, and the result is -1 if handled, else the cause (still needs handling).\r
+For interrupt handlers, the cause is a mask of pending enabled interrupts at\r
+that level, and the result is the same mask with the bits for the handled\r
+interrupts cleared (those not cleared still need handling). This allows a test\r
+case to either pre-handle or override the default handling for the exception\r
+or interrupt level (see xtensa_vectors.S).\r
+\r
+High priority handlers (including NMI) must be coded in assembly, are always\r
+called by 'call0' regardless of ABI, must preserve all registers except a0,\r
+and must not use or modify the interrupted stack. The hook argument 'cause'\r
+is not passed and the result is ignored, so as not to burden the caller with\r
+saving and restoring a2 (it assumes only one interrupt per level - see the\r
+discussion in high priority interrupts in xtensa_vectors.S). The handler\r
+therefore should be coded to prototype 'void h(void)' even though it plugs\r
+into an array of handlers of prototype 'unsigned h(unsigned)'.\r
+\r
+To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.\r
+\r
+*******************************************************************************/\r
+\r
+#define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)\r
+\r
+#ifndef __ASSEMBLER__\r
+typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);\r
+extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+\r
+CONVENIENCE INCLUSIONS.\r
+\r
+Ensures RTOS specific files need only include this one Xtensa-generic header.\r
+These headers are included last so they can use the RTOS definitions above.\r
+\r
+*******************************************************************************/\r
+\r
+#include "xtensa_context.h"\r
+\r
+#ifdef XT_RTOS_TIMER_INT\r
+#include "xtensa_timer.h"\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+\r
+Xtensa Port Version.\r
+\r
+*******************************************************************************/\r
+\r
+#define XTENSA_PORT_VERSION 1.6\r
+#define XTENSA_PORT_VERSION_STRING "1.6"\r
+\r
+#endif /* XTENSA_RTOS_H */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.\r
+//\r
+// Permission is hereby granted, free of charge, to any person obtaining\r
+// a copy of this software and associated documentation files (the\r
+// "Software"), to deal in the Software without restriction, including\r
+// without limitation the rights to use, copy, modify, merge, publish,\r
+// distribute, sublicense, and/or sell copies of the Software, and to\r
+// permit persons to whom the Software is furnished to do so, subject to\r
+// the following conditions:\r
+//\r
+// The above copyright notice and this permission notice shall be included\r
+// in all copies or substantial portions of the Software.\r
+//\r
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+\r
+ XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY\r
+\r
+This header contains definitions and macros for use primarily by Xtensa\r
+RTOS assembly coded source files. It includes and uses the Xtensa hardware\r
+abstraction layer (HAL) to deal with config specifics. It may also be\r
+included in C source files.\r
+\r
+User may edit to modify timer selection and to specify clock frequency and\r
+tick duration to match timer interrupt to the real-time tick duration.\r
+\r
+If the RTOS has no timer interrupt, then there is no tick timer and the\r
+clock frequency is irrelevant, so all of these macros are left undefined\r
+and the Xtensa core configuration need not have a timer.\r
+\r
+*******************************************************************************/\r
+\r
+#ifndef XTENSA_TIMER_H\r
+#define XTENSA_TIMER_H\r
+\r
+#ifdef __ASSEMBLER__\r
+#include <xtensa/coreasm.h>\r
+#endif\r
+\r
+#include <xtensa/corebits.h>\r
+#include <xtensa/config/system.h>\r
+\r
+#include "xtensa_rtos.h" /* in case this wasn't included directly */\r
+\r
+#include <FreeRTOSConfig.h>\r
+\r
+/*\r
+Select timer to use for periodic tick, and determine its interrupt number \r
+and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,\r
+in which case its validity is checked (it must exist in this core and must \r
+not be on a high priority interrupt - an error will be reported in invalid).\r
+Otherwise select the first low or medium priority interrupt timer available.\r
+*/\r
+#if XCHAL_NUM_TIMERS == 0\r
+\r
+ #error "This Xtensa configuration is unsupported, it has no timers."\r
+\r
+#else\r
+\r
+#ifndef XT_TIMER_INDEX\r
+ #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED\r
+ #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL\r
+ #undef XT_TIMER_INDEX\r
+ #define XT_TIMER_INDEX 3\r
+ #endif\r
+ #endif\r
+ #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED\r
+ #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL\r
+ #undef XT_TIMER_INDEX\r
+ #define XT_TIMER_INDEX 2\r
+ #endif\r
+ #endif\r
+ #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED\r
+ #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL\r
+ #undef XT_TIMER_INDEX\r
+ #define XT_TIMER_INDEX 1\r
+ #endif\r
+ #endif\r
+ #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED\r
+ #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL\r
+ #undef XT_TIMER_INDEX\r
+ #define XT_TIMER_INDEX 0\r
+ #endif\r
+ #endif\r
+#endif\r
+#ifndef XT_TIMER_INDEX\r
+ #error "There is no suitable timer in this Xtensa configuration."\r
+#endif\r
+\r
+#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX)\r
+#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)\r
+#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM)\r
+#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM)\r
+\r
+#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED\r
+ #error "The timer selected by XT_TIMER_INDEX does not exist in this core."\r
+#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL\r
+ #error "The timer interrupt cannot be high priority (use medium or low)."\r
+#endif\r
+\r
+#endif /* XCHAL_NUM_TIMERS */\r
+\r
+/*\r
+Set processor clock frequency, used to determine clock divisor for timer tick.\r
+User should BE SURE TO ADJUST THIS for the Xtensa platform being used.\r
+If using a supported board via the board-independent API defined in xtbsp.h,\r
+this may be left undefined and frequency and tick divisor will be computed \r
+and cached during run-time initialization.\r
+\r
+NOTE ON SIMULATOR:\r
+Under the Xtensa instruction set simulator, the frequency can only be estimated \r
+because it depends on the speed of the host and the version of the simulator.\r
+Also because it runs much slower than hardware, it is not possible to achieve\r
+real-time performance for most applications under the simulator. A frequency\r
+too low does not allow enough time between timer interrupts, starving threads.\r
+To obtain a more convenient but non-real-time tick duration on the simulator, \r
+compile with xt-xcc option "-DXT_SIMULATOR".\r
+Adjust this frequency to taste (it's not real-time anyway!).\r
+*/\r
+#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)\r
+#define XT_CLOCK_FREQ configCPU_CLOCK_HZ\r
+#endif\r
+\r
+#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)\r
+ #error "XT_CLOCK_FREQ must be defined for the target platform."\r
+#endif\r
+\r
+/*\r
+Default number of timer "ticks" per second (default 100 for 10ms tick).\r
+RTOS may define this in its own way (if applicable) in xtensa_rtos.h.\r
+User may redefine this to an optimal value for the application, either by\r
+editing this here or in xtensa_rtos.h, or compiling with xt-xcc option\r
+"-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.\r
+*/\r
+#ifndef XT_TICK_PER_SEC\r
+#define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */\r
+#endif\r
+\r
+/*\r
+Derivation of clock divisor for timer tick and interrupt (one per tick).\r
+*/\r
+#ifdef XT_CLOCK_FREQ\r
+#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC)\r
+#endif\r
+\r
+#ifndef __ASSEMBLER__\r
+extern unsigned _xt_tick_divisor;\r
+extern void _xt_tick_divisor_init(void);\r
+#endif\r
+\r
+#endif /* XTENSA_TIMER_H */\r
+\r
--- /dev/null
+/*******************************************************************************\r
+Copyright (c) 2006-2015 Cadence Design Systems Inc.\r
+\r
+Permission is hereby granted, free of charge, to any person obtaining\r
+a copy of this software and associated documentation files (the\r
+"Software"), to deal in the Software without restriction, including\r
+without limitation the rights to use, copy, modify, merge, publish,\r
+distribute, sublicense, and/or sell copies of the Software, and to\r
+permit persons to whom the Software is furnished to do so, subject to\r
+the following conditions:\r
+\r
+The above copyright notice and this permission notice shall be included\r
+in all copies or substantial portions of the Software.\r
+\r
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\r
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,\r
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE\r
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+--------------------------------------------------------------------------------\r
+\r
+ XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS\r
+\r
+ Xtensa low level exception and interrupt vectors and handlers for an RTOS.\r
+\r
+ Interrupt handlers and user exception handlers support interaction with\r
+ the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and\r
+ after user's specific interrupt handlers. These macros are defined in\r
+ xtensa_<rtos>.h to call suitable functions in a specific RTOS.\r
+\r
+ Users can install application-specific interrupt handlers for low and\r
+ medium level interrupts, by calling xt_set_interrupt_handler(). These\r
+ handlers can be written in C, and must obey C calling convention. The\r
+ handler table is indexed by the interrupt number. Each handler may be\r
+ provided with an argument. \r
+\r
+ Note that the system timer interrupt is handled specially, and is\r
+ dispatched to the RTOS-specific handler. This timer cannot be hooked\r
+ by application code.\r
+\r
+ Optional hooks are also provided to install a handler per level at \r
+ run-time, made available by compiling this source file with \r
+ '-DXT_INTEXC_HOOKS' (useful for automated testing).\r
+\r
+!! This file is a template that usually needs to be modified to handle !!\r
+!! application specific interrupts. Search USER_EDIT for helpful comments !!\r
+!! on where to insert handlers and how to write them. !!\r
+\r
+ Users can also install application-specific exception handlers in the\r
+ same way, by calling xt_set_exception_handler(). One handler slot is\r
+ provided for each exception type. Note that some exceptions are handled\r
+ by the porting layer itself, and cannot be taken over by application\r
+ code in this manner. These are the alloca, syscall, and coprocessor\r
+ exceptions.\r
+\r
+ The exception handlers can be written in C, and must follow C calling\r
+ convention. Each handler is passed a pointer to an exception frame as\r
+ its single argument. The exception frame is created on the stack, and\r
+ holds the saved context of the thread that took the exception. If the\r
+ handler returns, the context will be restored and the instruction that\r
+ caused the exception will be retried. If the handler makes any changes\r
+ to the saved state in the exception frame, the changes will be applied\r
+ when restoring the context.\r
+\r
+ Because Xtensa is a configurable architecture, this port supports all user\r
+ generated configurations (except restrictions stated in the release notes).\r
+ This is accomplished by conditional compilation using macros and functions\r
+ defined in the Xtensa HAL (hardware adaptation layer) for your configuration.\r
+ Only the relevant parts of this file will be included in your RTOS build.\r
+ For example, this file provides interrupt vector templates for all types and\r
+ all priority levels, but only the ones in your configuration are built.\r
+\r
+ NOTES on the use of 'call0' for long jumps instead of 'j':\r
+ 1. This file should be assembled with the -mlongcalls option to xt-xcc.\r
+ 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to\r
+ a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the\r
+ distance from the call to the destination. The linker then relaxes\r
+ it back to 'call0 dest' if it determines that dest is within range.\r
+ This allows more flexibility in locating code without the performance\r
+ overhead of the 'l32r' literal data load in cases where the destination\r
+ is in range of 'call0'. There is an additional benefit in that 'call0'\r
+ has a longer range than 'j' due to the target being word-aligned, so \r
+ the 'l32r' sequence is less likely needed.\r
+ 3. The use of 'call0' with -mlongcalls requires that register a0 not be \r
+ live at the time of the call, which is always the case for a function \r
+ call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.\r
+ 4. This use of 'call0' is independent of the C function call ABI.\r
+\r
+*******************************************************************************/\r
+\r
+#include "xtensa_rtos.h"\r
+\r
+\r
+/* Enable stack backtrace across exception/interrupt - see below */\r
+#define XT_DEBUG_BACKTRACE 1\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ Defines used to access _xtos_interrupt_table.\r
+--------------------------------------------------------------------------------\r
+*/\r
+#define XIE_HANDLER 0\r
+#define XIE_ARG 4\r
+#define XIE_SIZE 8\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ Macro extract_msb - return the input with only the highest bit set.\r
+\r
+ Input : "ain" - Input value, clobbered.\r
+ Output : "aout" - Output value, has only one bit set, MSB of "ain".\r
+ The two arguments must be different AR registers.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .macro extract_msb aout ain\r
+1:\r
+ addi \aout, \ain, -1 /* aout = ain - 1 */\r
+ and \ain, \ain, \aout /* ain = ain & aout */\r
+ bnez \ain, 1b /* repeat until ain == 0 */\r
+ addi \aout, \aout, 1 /* return aout + 1 */\r
+ .endm\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ Macro dispatch_c_isr - dispatch interrupts to user ISRs.\r
+ This will dispatch to user handlers (if any) that are registered in the\r
+ XTOS dispatch table (_xtos_interrupt_table). These handlers would have\r
+ been registered by calling _xtos_set_interrupt_handler(). There is one\r
+ exception - the timer interrupt used by the OS will not be dispatched\r
+ to a user handler - this must be handled by the caller of this macro.\r
+\r
+ Level triggered and software interrupts are automatically deasserted by\r
+ this code.\r
+\r
+ ASSUMPTIONS:\r
+ -- PS.INTLEVEL is set to "level" at entry\r
+ -- PS.EXCM = 0, C calling enabled\r
+\r
+ NOTE: For CALL0 ABI, a12-a15 have not yet been saved.\r
+\r
+ NOTE: This macro will use registers a0 and a2-a6. The arguments are:\r
+ level -- interrupt level\r
+ mask -- interrupt bitmask for this level\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .macro dispatch_c_isr level mask\r
+\r
+ /* Get mask of pending, enabled interrupts at this level into a2. */\r
+\r
+.L_xt_user_int_&level&:\r
+ rsr a2, INTENABLE\r
+ rsr a3, INTERRUPT\r
+ movi a4, \mask\r
+ and a2, a2, a3\r
+ and a2, a2, a4\r
+ beqz a2, 9f /* nothing to do */\r
+\r
+ /* This bit of code provides a nice debug backtrace in the debugger.\r
+ It does take a few more instructions, so undef XT_DEBUG_BACKTRACE\r
+ if you want to save the cycles.\r
+ */\r
+ #if XT_DEBUG_BACKTRACE\r
+ #ifndef __XTENSA_CALL0_ABI__\r
+ rsr a0, EPC_1 + \level - 1 /* return address */\r
+ movi a4, 0xC0000000 /* constant with top 2 bits set (call size) */\r
+ or a0, a0, a4 /* set top 2 bits */\r
+ addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef XT_INTEXC_HOOKS\r
+ /* Call interrupt hook if present to (pre)handle interrupts. */\r
+ movi a4, _xt_intexc_hooks\r
+ l32i a4, a4, \level << 2\r
+ beqz a4, 2f\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ callx0 a4\r
+ beqz a2, 9f\r
+ #else\r
+ mov a6, a2\r
+ callx4 a4\r
+ beqz a6, 9f\r
+ mov a2, a6\r
+ #endif\r
+2:\r
+ #endif\r
+\r
+ /* Now look up in the dispatch table and call user ISR if any. */\r
+ /* If multiple bits are set then MSB has highest priority. */\r
+\r
+ extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */\r
+\r
+ #ifdef XT_USE_SWPRI\r
+ /* Enable all interrupts at this level that are numerically higher\r
+ than the one we just selected, since they are treated as higher\r
+ priority.\r
+ */\r
+ movi a3, \mask /* a3 = all interrupts at this level */\r
+ add a2, a4, a4 /* a2 = a4 << 1 */\r
+ addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */\r
+ and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */\r
+ movi a3, _xt_intdata\r
+ l32i a6, a3, 4 /* a6 = _xt_vpri_mask */\r
+ neg a2, a2\r
+ addi a2, a2, -1 /* a2 = mask to apply */\r
+ and a5, a6, a2 /* mask off all bits <= a4 bit */\r
+ s32i a5, a3, 4 /* update _xt_vpri_mask */\r
+ rsr a3, INTENABLE\r
+ and a3, a3, a2 /* mask off all bits <= a4 bit */\r
+ wsr a3, INTENABLE\r
+ rsil a3, \level - 1 /* lower interrupt level by 1 */\r
+ #endif\r
+\r
+ movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */\r
+ wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */\r
+ beq a3, a4, 7f /* if timer interrupt then skip table */\r
+\r
+ find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */\r
+\r
+ movi a4, _xt_interrupt_table\r
+ addx8 a3, a3, a4 /* a3 = address of interrupt table entry */\r
+ l32i a4, a3, XIE_HANDLER /* a4 = handler address */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ mov a12, a6 /* save in callee-saved reg */\r
+ l32i a2, a3, XIE_ARG /* a2 = handler arg */\r
+ callx0 a4 /* call handler */\r
+ mov a2, a12\r
+ #else\r
+ mov a2, a6 /* save in windowed reg */\r
+ l32i a6, a3, XIE_ARG /* a6 = handler arg */\r
+ callx4 a4 /* call handler */\r
+ #endif\r
+\r
+ #ifdef XT_USE_SWPRI\r
+ j 8f\r
+ #else\r
+ j .L_xt_user_int_&level& /* check for more interrupts */\r
+ #endif\r
+\r
+7:\r
+\r
+ .ifeq XT_TIMER_INTPRI - \level\r
+.L_xt_user_int_timer_&level&:\r
+ /*\r
+ Interrupt handler for the RTOS tick timer if at this level.\r
+ We'll be reading the interrupt state again after this call\r
+ so no need to preserve any registers except a6 (vpri_mask).\r
+ */\r
+\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ mov a12, a6\r
+ call0 XT_RTOS_TIMER_INT\r
+ mov a2, a12\r
+ #else\r
+ mov a2, a6\r
+ call4 XT_RTOS_TIMER_INT\r
+ #endif\r
+ .endif\r
+\r
+ #ifdef XT_USE_SWPRI\r
+ j 8f\r
+ #else\r
+ j .L_xt_user_int_&level& /* check for more interrupts */\r
+ #endif\r
+\r
+ #ifdef XT_USE_SWPRI\r
+8:\r
+ /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from\r
+ virtual _xt_intenable which _could_ have changed during interrupt\r
+ processing. */\r
+\r
+ movi a3, _xt_intdata\r
+ l32i a4, a3, 0 /* a4 = _xt_intenable */\r
+ s32i a2, a3, 4 /* update _xt_vpri_mask */\r
+ and a4, a4, a2 /* a4 = masked intenable */\r
+ wsr a4, INTENABLE /* update INTENABLE */\r
+ #endif\r
+\r
+9:\r
+ /* done */\r
+\r
+ .endm\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ Panic handler.\r
+ Should be reached by call0 (preferable) or jump only. If call0, a0 says where \r
+ from. If on simulator, display panic message and abort, else loop indefinitely.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .text\r
+ .global _xt_panic\r
+ .type _xt_panic,@function\r
+ .align 4\r
+\r
+_xt_panic:\r
+ #ifdef XT_SIMULATOR\r
+ addi a4, a0, -3 /* point to call0 */\r
+ movi a3, _xt_panic_message\r
+ movi a2, SYS_log_msg\r
+ simcall\r
+ movi a2, SYS_gdb_abort\r
+ simcall\r
+ #else\r
+ rsil a2, XCHAL_EXCM_LEVEL /* disable all low & med ints */\r
+1: j 1b /* loop infinitely */\r
+ #endif\r
+\r
+ .section .rodata, "a"\r
+ .align 4\r
+\r
+_xt_panic_message:\r
+ .string "\n*** _xt_panic() was called from 0x%08x or jumped to. ***\n"\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ Hooks to dynamically install handlers for exceptions and interrupts.\r
+ Allows automated regression frameworks to install handlers per test.\r
+ Consists of an array of function pointers indexed by interrupt level, \r
+ with index 0 containing the entry for user exceptions.\r
+ Initialized with all 0s, meaning no handler is installed at each level.\r
+ See comment in xtensa_rtos.h for more details.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ #ifdef XT_INTEXC_HOOKS\r
+ .data\r
+ .global _xt_intexc_hooks\r
+ .type _xt_intexc_hooks,@object\r
+ .align 4\r
+\r
+_xt_intexc_hooks:\r
+ .fill XT_INTEXC_HOOK_NUM, 4, 0\r
+ #endif\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS\r
+ (except window exception vectors).\r
+\r
+ Each vector goes at a predetermined location according to the Xtensa\r
+ hardware configuration, which is ensured by its placement in a special\r
+ section known to the Xtensa linker support package (LSP). It performs\r
+ the minimum necessary before jumping to the handler in the .text section.\r
+\r
+ The corresponding handler goes in the normal .text section. It sets up\r
+ the appropriate stack frame, saves a few vector-specific registers and\r
+ calls XT_RTOS_INT_ENTER to save the rest of the interrupted context\r
+ and enter the RTOS, then sets up a C environment. It then calls the\r
+ user's interrupt handler code (which may be coded in C) and finally \r
+ calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.\r
+\r
+ While XT_RTOS_INT_EXIT does not return directly to the interruptee,\r
+ eventually the RTOS scheduler will want to dispatch the interrupted\r
+ task or handler. The scheduler will return to the exit point that was\r
+ saved in the interrupt stack frame at XT_STK_EXIT.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Debug Exception.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+#if XCHAL_HAVE_DEBUG\r
+\r
+ .begin literal_prefix .DebugExceptionVector\r
+ .section .DebugExceptionVector.text, "ax"\r
+ .global _DebugExceptionVector\r
+ .align 4\r
+\r
+_DebugExceptionVector:\r
+\r
+ #ifdef XT_SIMULATOR\r
+ /*\r
+ In the simulator, let the debugger (if any) handle the debug exception,\r
+ or simply stop the simulation:\r
+ */\r
+ wsr a2, EXCSAVE+XCHAL_DEBUGLEVEL /* save a2 where sim expects it */\r
+ movi a2, SYS_gdb_enter_sktloop\r
+ simcall /* have ISS handle debug exc. */\r
+ #elif 0 /* change condition to 1 to use the HAL minimal debug handler */\r
+ wsr a3, EXCSAVE+XCHAL_DEBUGLEVEL\r
+ movi a3, xthal_debugexc_defhndlr_nw /* use default debug handler */\r
+ jx a3\r
+ #else\r
+ wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* save original a0 somewhere */\r
+ call0 _xt_panic /* does not return */\r
+ rfi XCHAL_DEBUGLEVEL /* make a0 point here not later */\r
+ #endif\r
+\r
+ .end literal_prefix\r
+\r
+#endif\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Double Exception.\r
+Double exceptions are not a normal occurrence. They indicate a bug of some kind.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR\r
+\r
+ .begin literal_prefix .DoubleExceptionVector\r
+ .section .DoubleExceptionVector.text, "ax"\r
+ .global _DoubleExceptionVector\r
+ .align 4\r
+\r
+_DoubleExceptionVector:\r
+\r
+ #if XCHAL_HAVE_DEBUG\r
+ break 1, 4 /* unhandled double exception */\r
+ #endif\r
+ call0 _xt_panic /* does not return */\r
+ rfde /* make a0 point here not later */\r
+\r
+ .end literal_prefix\r
+\r
+#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Kernel Exception (including Level 1 Interrupt from kernel mode).\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .begin literal_prefix .KernelExceptionVector\r
+ .section .KernelExceptionVector.text, "ax"\r
+ .global _KernelExceptionVector\r
+ .align 4\r
+\r
+_KernelExceptionVector:\r
+\r
+ wsr a0, EXCSAVE_1 /* preserve a0 */\r
+ call0 _xt_kernel_exc /* kernel exception handler */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .align 4\r
+\r
+_xt_kernel_exc:\r
+ #if XCHAL_HAVE_DEBUG\r
+ break 1, 0 /* unhandled kernel exception */\r
+ #endif\r
+ call0 _xt_panic /* does not return */\r
+ rfe /* make a0 point here not there */\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+User Exception (including Level 1 Interrupt from user mode).\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .begin literal_prefix .UserExceptionVector\r
+ .section .UserExceptionVector.text, "ax"\r
+ .global _UserExceptionVector\r
+ .type _UserExceptionVector,@function\r
+ .align 4\r
+\r
+_UserExceptionVector:\r
+\r
+ wsr a0, EXCSAVE_1 /* preserve a0 */\r
+ call0 _xt_user_exc /* user exception handler */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ .end literal_prefix\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ Insert some waypoints for jumping beyond the signed 8-bit range of\r
+ conditional branch instructions, so the conditional branchces to specific\r
+ exception handlers are not taken in the mainline. Saves some cycles in the\r
+ mainline.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .text\r
+\r
+ #if XCHAL_HAVE_WINDOWED\r
+ .align 4\r
+_xt_to_alloca_exc:\r
+ call0 _xt_alloca_exc /* in window vectors section */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+ #endif\r
+\r
+ .align 4\r
+_xt_to_syscall_exc:\r
+ call0 _xt_syscall_exc\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ #if XCHAL_CP_NUM > 0\r
+ .align 4\r
+_xt_to_coproc_exc:\r
+ call0 _xt_coproc_exc\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+ #endif\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ User exception handler.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .type _xt_user_exc,@function\r
+ .align 4\r
+\r
+_xt_user_exc:\r
+\r
+ /* If level 1 interrupt then jump to the dispatcher */\r
+ rsr a0, EXCCAUSE\r
+ beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1\r
+\r
+ /* Handle any coprocessor exceptions. Rely on the fact that exception\r
+ numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.\r
+ */\r
+ #if XCHAL_CP_NUM > 0\r
+ bgeui a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc\r
+ #endif\r
+\r
+ /* Handle alloca and syscall exceptions */\r
+ #if XCHAL_HAVE_WINDOWED\r
+ beqi a0, EXCCAUSE_ALLOCA, _xt_to_alloca_exc\r
+ #endif\r
+ beqi a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc\r
+\r
+ /* Handle all other exceptions. All can have user-defined handlers. */\r
+ /* NOTE: we'll stay on the user stack for exception handling. */\r
+\r
+ /* Allocate exception frame and save minimal context. */\r
+ mov a0, sp\r
+ addi sp, sp, -XT_STK_FRMSZ\r
+ s32i a0, sp, XT_STK_A1\r
+ #if XCHAL_HAVE_WINDOWED\r
+ s32e a0, sp, -12 /* for debug backtrace */\r
+ #endif\r
+ rsr a0, PS /* save interruptee's PS */\r
+ s32i a0, sp, XT_STK_PS\r
+ rsr a0, EPC_1 /* save interruptee's PC */\r
+ s32i a0, sp, XT_STK_PC\r
+ rsr a0, EXCSAVE_1 /* save interruptee's a0 */\r
+ s32i a0, sp, XT_STK_A0\r
+ #if XCHAL_HAVE_WINDOWED\r
+ s32e a0, sp, -16 /* for debug backtrace */\r
+ #endif\r
+ s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */\r
+ s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */\r
+ call0 _xt_context_save\r
+\r
+ /* Save exc cause and vaddr into exception frame */\r
+ rsr a0, EXCCAUSE\r
+ s32i a0, sp, XT_STK_EXCCAUSE\r
+ rsr a0, EXCVADDR\r
+ s32i a0, sp, XT_STK_EXCVADDR\r
+\r
+ /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM\r
+ #else\r
+ movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE\r
+ #endif\r
+ wsr a0, PS\r
+\r
+ #ifdef XT_DEBUG_BACKTRACE\r
+ #ifndef __XTENSA_CALL0_ABI__\r
+ rsr a0, EPC_1 /* return address for debug backtrace */\r
+ movi a5, 0xC0000000 /* constant with top 2 bits set (call size) */\r
+ rsync /* wait for WSR.PS to complete */\r
+ or a0, a0, a5 /* set top 2 bits */\r
+ addx2 a0, a5, a0 /* clear top bit -- thus simulating call4 size */\r
+ #else\r
+ rsync /* wait for WSR.PS to complete */\r
+ #endif\r
+ #endif\r
+\r
+ rsr a2, EXCCAUSE /* recover exc cause */\r
+\r
+ #ifdef XT_INTEXC_HOOKS\r
+ /*\r
+ Call exception hook to pre-handle exceptions (if installed).\r
+ Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).\r
+ */\r
+ movi a4, _xt_intexc_hooks\r
+ l32i a4, a4, 0 /* user exception hook index 0 */\r
+ beqz a4, 1f\r
+.Ln_xt_user_exc_call_hook:\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ callx0 a4\r
+ beqi a2, -1, .L_xt_user_done\r
+ #else\r
+ mov a6, a2\r
+ callx4 a4\r
+ beqi a6, -1, .L_xt_user_done\r
+ mov a2, a6\r
+ #endif\r
+1:\r
+ #endif\r
+\r
+ rsr a2, EXCCAUSE /* recover exc cause */\r
+ movi a3, _xt_exception_table\r
+ addx4 a4, a2, a3 /* a4 = address of exception table entry */\r
+ l32i a4, a4, 0 /* a4 = handler address */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ mov a2, sp /* a2 = pointer to exc frame */\r
+ callx0 a4 /* call handler */\r
+ #else\r
+ mov a6, sp /* a6 = pointer to exc frame */\r
+ callx4 a4 /* call handler */\r
+ #endif\r
+\r
+.L_xt_user_done:\r
+\r
+ /* Restore context and return */\r
+ call0 _xt_context_restore\r
+ l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */\r
+ wsr a0, PS\r
+ l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */\r
+ wsr a0, EPC_1\r
+ l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */\r
+ l32i sp, sp, XT_STK_A1 /* remove exception frame */\r
+ rsync /* ensure PS and EPC written */\r
+ rfe /* PS.EXCM is cleared */\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT\r
+ on entry and used to return to a thread or interrupted interrupt handler.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .global _xt_user_exit\r
+ .type _xt_user_exit,@function\r
+ .align 4\r
+_xt_user_exit:\r
+ l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */\r
+ wsr a0, PS\r
+ l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */\r
+ wsr a0, EPC_1\r
+ l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */\r
+ l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */\r
+ rsync /* ensure PS and EPC written */\r
+ rfe /* PS.EXCM is cleared */\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Syscall Exception Handler (jumped to from User Exception Handler).\r
+Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).\r
+Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .text\r
+ .type _xt_syscall_exc,@function\r
+ .align 4\r
+_xt_syscall_exc:\r
+\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ /*\r
+ Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.\r
+ Use a minimal stack frame (16B) to save A2 & A3 for scratch.\r
+ PS.EXCM could be cleared here, but unlikely to improve worst-case latency.\r
+ rsr a0, PS\r
+ addi a0, a0, -PS_EXCM_MASK\r
+ wsr a0, PS\r
+ */\r
+ addi sp, sp, -16\r
+ s32i a2, sp, 8\r
+ s32i a3, sp, 12\r
+ #else /* Windowed ABI */\r
+ /*\r
+ Save necessary context and spill the register windows.\r
+ PS.EXCM is still set and must remain set until after the spill.\r
+ Reuse context save function though it saves more than necessary.\r
+ For this reason, a full interrupt stack frame is allocated.\r
+ */\r
+ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */\r
+ s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */\r
+ s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */\r
+ call0 _xt_context_save\r
+ #endif\r
+\r
+ /*\r
+ Grab the interruptee's PC and skip over the 'syscall' instruction.\r
+ If it's at the end of a zero-overhead loop and it's not on the last\r
+ iteration, decrement loop counter and skip to beginning of loop.\r
+ */\r
+ rsr a2, EPC_1 /* a2 = PC of 'syscall' */\r
+ addi a3, a2, 3 /* ++PC */\r
+ #if XCHAL_HAVE_LOOPS\r
+ rsr a0, LEND /* if (PC == LEND */\r
+ bne a3, a0, 1f\r
+ rsr a0, LCOUNT /* && LCOUNT != 0) */\r
+ beqz a0, 1f /* { */\r
+ addi a0, a0, -1 /* --LCOUNT */\r
+ rsr a3, LBEG /* PC = LBEG */\r
+ wsr a0, LCOUNT /* } */\r
+ #endif\r
+1: wsr a3, EPC_1 /* update PC */\r
+\r
+ /* Restore interruptee's context and return from exception. */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ l32i a2, sp, 8\r
+ l32i a3, sp, 12\r
+ addi sp, sp, 16\r
+ #else\r
+ call0 _xt_context_restore\r
+ addi sp, sp, XT_STK_FRMSZ\r
+ #endif\r
+ movi a0, -1\r
+ movnez a2, a0, a2 /* return -1 if not syscall 0 */\r
+ rsr a0, EXCSAVE_1\r
+ rfe\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Co-Processor Exception Handler (jumped to from User Exception Handler).\r
+These exceptions are generated by co-processor instructions, which are only\r
+allowed in thread code (not in interrupts or kernel code). This restriction is \r
+deliberately imposed to reduce the burden of state-save/restore in interrupts.\r
+--------------------------------------------------------------------------------\r
+*/\r
+#if XCHAL_CP_NUM > 0\r
+\r
+ .section .rodata, "a"\r
+\r
+/* Offset to CP n save area in thread's CP save area. */\r
+ .global _xt_coproc_sa_offset\r
+ .type _xt_coproc_sa_offset,@object\r
+ .align 16 /* minimize crossing cache boundaries */\r
+_xt_coproc_sa_offset:\r
+ .word XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA\r
+ .word XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA\r
+\r
+/* Bitmask for CP n's CPENABLE bit. */\r
+ .type _xt_coproc_mask,@object\r
+ .align 16,,8 /* try to keep it all in one cache line */\r
+ .set i, 0\r
+_xt_coproc_mask:\r
+ .rept XCHAL_CP_MAX\r
+ .long (i<<16) | (1<<i) // upper 16-bits = i, lower = bitmask\r
+ .set i, i+1\r
+ .endr\r
+\r
+ .data\r
+\r
+/* Owner thread of CP n, identified by thread's CP save area (0 = unowned). */\r
+ .global _xt_coproc_owner_sa\r
+ .type _xt_coproc_owner_sa,@object\r
+ .align 16,,XCHAL_CP_MAX<<2 /* minimize crossing cache boundaries */\r
+_xt_coproc_owner_sa:\r
+ .space XCHAL_CP_MAX << 2\r
+\r
+ .text\r
+\r
+\r
+ .align 4\r
+.L_goto_invalid:\r
+ j .L_xt_coproc_invalid /* not in a thread (invalid) */\r
+ .align 4\r
+.L_goto_done:\r
+ j .L_xt_coproc_done\r
+\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+ Coprocessor exception handler.\r
+ At entry, only a0 has been saved (in EXCSAVE_1).\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .type _xt_coproc_exc,@function\r
+ .align 4\r
+\r
+_xt_coproc_exc:\r
+\r
+ /* Allocate interrupt stack frame and save minimal context. */\r
+ mov a0, sp /* sp == a1 */\r
+ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */\r
+ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */\r
+ #if XCHAL_HAVE_WINDOWED\r
+ s32e a0, sp, -12 /* for debug backtrace */\r
+ #endif\r
+ rsr a0, PS /* save interruptee's PS */\r
+ s32i a0, sp, XT_STK_PS\r
+ rsr a0, EPC_1 /* save interruptee's PC */\r
+ s32i a0, sp, XT_STK_PC\r
+ rsr a0, EXCSAVE_1 /* save interruptee's a0 */\r
+ s32i a0, sp, XT_STK_A0\r
+ #if XCHAL_HAVE_WINDOWED\r
+ s32e a0, sp, -16 /* for debug backtrace */\r
+ #endif\r
+ movi a0, _xt_user_exit /* save exit point for dispatch */\r
+ s32i a0, sp, XT_STK_EXIT\r
+\r
+ rsr a0, EXCCAUSE\r
+ s32i a5, sp, XT_STK_A5 /* save a5 */\r
+ addi a5, a0, -EXCCAUSE_CP0_DISABLED /* a5 = CP index */\r
+\r
+ /* Save a few more of interruptee's registers (a5 was already saved). */\r
+ s32i a2, sp, XT_STK_A2\r
+ s32i a3, sp, XT_STK_A3\r
+ s32i a4, sp, XT_STK_A4\r
+ s32i a15, sp, XT_STK_A15\r
+\r
+ /* Get co-processor state save area of new owner thread. */\r
+ call0 XT_RTOS_CP_STATE /* a15 = new owner's save area */\r
+ beqz a15, .L_goto_invalid /* not in a thread (invalid) */\r
+\r
+ /* Enable the co-processor's bit in CPENABLE. */\r
+ movi a0, _xt_coproc_mask\r
+ rsr a4, CPENABLE /* a4 = CPENABLE */\r
+ addx4 a0, a5, a0 /* a0 = &_xt_coproc_mask[n] */\r
+ l32i a0, a0, 0 /* a0 = (n << 16) | (1 << n) */\r
+ movi a3, _xt_coproc_owner_sa /* (placed here for load slot) */\r
+ extui a2, a0, 0, 16 /* coprocessor bitmask portion */\r
+ or a4, a4, a2 /* a4 = CPENABLE | (1 << n) */\r
+ wsr a4, CPENABLE\r
+\r
+ /* Get old coprocessor owner thread (save area ptr) and assign new one. */\r
+ addx4 a3, a5, a3 /* a3 = &_xt_coproc_owner_sa[n] */\r
+ l32i a2, a3, 0 /* a2 = old owner's save area */\r
+ s32i a15, a3, 0 /* _xt_coproc_owner_sa[n] = new */\r
+ rsync /* ensure wsr.CPENABLE is complete */\r
+\r
+ /* Only need to context switch if new owner != old owner. */\r
+ beq a15, a2, .L_goto_done /* new owner == old, we're done */\r
+\r
+ /* If no old owner then nothing to save. */\r
+ beqz a2, .L_check_new\r
+\r
+ /* If old owner not actively using CP then nothing to save. */\r
+ l16ui a4, a2, XT_CPENABLE /* a4 = old owner's CPENABLE */\r
+ bnone a4, a0, .L_check_new /* old owner not using CP */\r
+\r
+.L_save_old:\r
+ /* Save old owner's coprocessor state. */\r
+\r
+ movi a5, _xt_coproc_sa_offset\r
+\r
+ /* Mark old owner state as no longer active (CPENABLE bit n clear). */\r
+ xor a4, a4, a0 /* clear CP bit in CPENABLE */\r
+ s16i a4, a2, XT_CPENABLE /* update old owner's CPENABLE */\r
+\r
+ extui a4, a0, 16, 5 /* a4 = CP index = n */\r
+ addx4 a5, a4, a5 /* a5 = &_xt_coproc_sa_offset[n] */\r
+\r
+ /* Mark old owner state as saved (CPSTORED bit n set). */\r
+ l16ui a4, a2, XT_CPSTORED /* a4 = old owner's CPSTORED */\r
+ l32i a5, a5, 0 /* a5 = XT_CP[n]_SA offset */\r
+ or a4, a4, a0 /* set CP in old owner's CPSTORED */\r
+ s16i a4, a2, XT_CPSTORED /* update old owner's CPSTORED */\r
+ l32i a2, a2, XT_CP_ASA /* ptr to actual (aligned) save area */\r
+ extui a3, a0, 16, 5 /* a3 = CP index = n */\r
+ add a2, a2, a5 /* a2 = old owner's area for CP n */\r
+\r
+ /*\r
+ The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.\r
+ It is theoretically possible for Xtensa processor designers to write TIE \r
+ that causes more address registers to be affected, but it is generally \r
+ unlikely. If that ever happens, more registers needs to be saved/restored\r
+ around this macro invocation, and the value in a15 needs to be recomputed.\r
+ */\r
+ xchal_cpi_store_funcbody\r
+\r
+.L_check_new:\r
+ /* Check if any state has to be restored for new owner. */\r
+ /* NOTE: a15 = new owner's save area, cannot be zero when we get here. */\r
+\r
+ l16ui a3, a15, XT_CPSTORED /* a3 = new owner's CPSTORED */\r
+ movi a4, _xt_coproc_sa_offset\r
+ bnone a3, a0, .L_check_cs /* full CP not saved, check callee-saved */\r
+ xor a3, a3, a0 /* CPSTORED bit is set, clear it */\r
+ s16i a3, a15, XT_CPSTORED /* update new owner's CPSTORED */\r
+\r
+ /* Adjust new owner's save area pointers to area for CP n. */\r
+ extui a3, a0, 16, 5 /* a3 = CP index = n */\r
+ addx4 a4, a3, a4 /* a4 = &_xt_coproc_sa_offset[n] */\r
+ l32i a4, a4, 0 /* a4 = XT_CP[n]_SA */\r
+ l32i a5, a15, XT_CP_ASA /* ptr to actual (aligned) save area */\r
+ add a2, a4, a5 /* a2 = new owner's area for CP */\r
+\r
+ /*\r
+ The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.\r
+ It is theoretically possible for Xtensa processor designers to write TIE \r
+ that causes more address registers to be affected, but it is generally \r
+ unlikely. If that ever happens, more registers needs to be saved/restored\r
+ around this macro invocation.\r
+ */\r
+ xchal_cpi_load_funcbody\r
+\r
+ /* Restore interruptee's saved registers. */\r
+ /* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */\r
+.L_xt_coproc_done:\r
+ l32i a15, sp, XT_STK_A15\r
+ l32i a5, sp, XT_STK_A5\r
+ l32i a4, sp, XT_STK_A4\r
+ l32i a3, sp, XT_STK_A3\r
+ l32i a2, sp, XT_STK_A2\r
+ call0 _xt_user_exit /* return via exit dispatcher */\r
+ /* Never returns here - call0 is used as a jump (see note at top) */\r
+\r
+.L_check_cs:\r
+ /* a0 = CP mask in low bits, a15 = new owner's save area */\r
+ l16ui a2, a15, XT_CP_CS_ST /* a2 = mask of CPs saved */\r
+ bnone a2, a0, .L_xt_coproc_done /* if no match then done */\r
+ and a2, a2, a0 /* a2 = which CPs to restore */\r
+ extui a2, a2, 0, 8 /* extract low 8 bits */\r
+ s32i a6, sp, XT_STK_A6 /* save extra needed regs */\r
+ s32i a7, sp, XT_STK_A7\r
+ s32i a13, sp, XT_STK_A13\r
+ s32i a14, sp, XT_STK_A14\r
+ call0 _xt_coproc_restorecs /* restore CP registers */\r
+ l32i a6, sp, XT_STK_A6 /* restore saved registers */\r
+ l32i a7, sp, XT_STK_A7\r
+ l32i a13, sp, XT_STK_A13\r
+ l32i a14, sp, XT_STK_A14\r
+ j .L_xt_coproc_done\r
+\r
+ /* Co-processor exception occurred outside a thread (not supported). */\r
+.L_xt_coproc_invalid:\r
+ #if XCHAL_HAVE_DEBUG\r
+ break 1, 1 /* unhandled user exception */\r
+ #endif\r
+ call0 _xt_panic /* not in a thread (invalid) */\r
+ /* never returns */\r
+\r
+\r
+#endif /* XCHAL_CP_NUM */\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+ .text \r
+ .type _xt_lowint1,@function\r
+ .align 4\r
+\r
+_xt_lowint1:\r
+ mov a0, sp /* sp == a1 */\r
+ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */\r
+ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */\r
+ rsr a0, PS /* save interruptee's PS */\r
+ s32i a0, sp, XT_STK_PS\r
+ rsr a0, EPC_1 /* save interruptee's PC */\r
+ s32i a0, sp, XT_STK_PC\r
+ rsr a0, EXCSAVE_1 /* save interruptee's a0 */\r
+ s32i a0, sp, XT_STK_A0\r
+ movi a0, _xt_user_exit /* save exit point for dispatch */\r
+ s32i a0, sp, XT_STK_EXIT\r
+\r
+ /* Save rest of interrupt context and enter RTOS. */\r
+ call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */\r
+\r
+ /* !! We are now on the RTOS system stack !! */ \r
+\r
+ /* Set up PS for C, enable interrupts above this level and clear EXCM. */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ movi a0, PS_INTLEVEL(1) | PS_UM\r
+ #else \r
+ movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE\r
+ #endif\r
+ wsr a0, PS\r
+ rsync\r
+\r
+ /* OK to call C code at this point, dispatch user ISRs */\r
+\r
+ dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK\r
+\r
+ /* Done handling interrupts, transfer control to OS */\r
+ call0 XT_RTOS_INT_EXIT /* does not return directly here */\r
+\r
+\r
+/*\r
+-------------------------------------------------------------------------------\r
+ MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS.\r
+\r
+ Medium priority interrupts are by definition those with priority greater\r
+ than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by\r
+ setting PS.EXCM and therefore can easily support a C environment for\r
+ handlers in C, and interact safely with an RTOS.\r
+\r
+ Each vector goes at a predetermined location according to the Xtensa\r
+ hardware configuration, which is ensured by its placement in a special\r
+ section known to the Xtensa linker support package (LSP). It performs\r
+ the minimum necessary before jumping to the handler in the .text section.\r
+\r
+ The corresponding handler goes in the normal .text section. It sets up\r
+ the appropriate stack frame, saves a few vector-specific registers and\r
+ calls XT_RTOS_INT_ENTER to save the rest of the interrupted context\r
+ and enter the RTOS, then sets up a C environment. It then calls the\r
+ user's interrupt handler code (which may be coded in C) and finally \r
+ calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.\r
+\r
+ While XT_RTOS_INT_EXIT does not return directly to the interruptee,\r
+ eventually the RTOS scheduler will want to dispatch the interrupted\r
+ task or handler. The scheduler will return to the exit point that was\r
+ saved in the interrupt stack frame at XT_STK_EXIT.\r
+-------------------------------------------------------------------------------\r
+*/\r
+\r
+#if XCHAL_EXCM_LEVEL >= 2\r
+\r
+ .begin literal_prefix .Level2InterruptVector\r
+ .section .Level2InterruptVector.text, "ax"\r
+ .global _Level2Vector\r
+ .type _Level2Vector,@function\r
+ .align 4\r
+_Level2Vector:\r
+ wsr a0, EXCSAVE_2 /* preserve a0 */\r
+ call0 _xt_medint2 /* load interrupt handler */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_medint2,@function\r
+ .align 4\r
+_xt_medint2:\r
+ mov a0, sp /* sp == a1 */\r
+ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */\r
+ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */\r
+ rsr a0, EPS_2 /* save interruptee's PS */\r
+ s32i a0, sp, XT_STK_PS\r
+ rsr a0, EPC_2 /* save interruptee's PC */\r
+ s32i a0, sp, XT_STK_PC\r
+ rsr a0, EXCSAVE_2 /* save interruptee's a0 */\r
+ s32i a0, sp, XT_STK_A0\r
+ movi a0, _xt_medint2_exit /* save exit point for dispatch */\r
+ s32i a0, sp, XT_STK_EXIT\r
+\r
+ /* Save rest of interrupt context and enter RTOS. */\r
+ call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */\r
+\r
+ /* !! We are now on the RTOS system stack !! */\r
+\r
+ /* Set up PS for C, enable interrupts above this level and clear EXCM. */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ movi a0, PS_INTLEVEL(2) | PS_UM\r
+ #else\r
+ movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE\r
+ #endif\r
+ wsr a0, PS\r
+ rsync\r
+\r
+ /* OK to call C code at this point, dispatch user ISRs */\r
+\r
+ dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK\r
+\r
+ /* Done handling interrupts, transfer control to OS */\r
+ call0 XT_RTOS_INT_EXIT /* does not return directly here */\r
+\r
+ /*\r
+ Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT\r
+ on entry and used to return to a thread or interrupted interrupt handler.\r
+ */\r
+ .global _xt_medint2_exit\r
+ .type _xt_medint2_exit,@function\r
+ .align 4\r
+_xt_medint2_exit:\r
+ /* Restore only level-specific regs (the rest were already restored) */\r
+ l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */\r
+ wsr a0, EPS_2\r
+ l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */\r
+ wsr a0, EPC_2\r
+ l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */\r
+ l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */\r
+ rsync /* ensure EPS and EPC written */\r
+ rfi 2\r
+\r
+#endif /* Level 2 */\r
+\r
+#if XCHAL_EXCM_LEVEL >= 3\r
+\r
+ .begin literal_prefix .Level3InterruptVector\r
+ .section .Level3InterruptVector.text, "ax"\r
+ .global _Level3Vector\r
+ .type _Level3Vector,@function\r
+ .align 4\r
+_Level3Vector:\r
+ wsr a0, EXCSAVE_3 /* preserve a0 */\r
+ call0 _xt_medint3 /* load interrupt handler */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_medint3,@function\r
+ .align 4\r
+_xt_medint3:\r
+ mov a0, sp /* sp == a1 */\r
+ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */\r
+ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */\r
+ rsr a0, EPS_3 /* save interruptee's PS */\r
+ s32i a0, sp, XT_STK_PS\r
+ rsr a0, EPC_3 /* save interruptee's PC */\r
+ s32i a0, sp, XT_STK_PC\r
+ rsr a0, EXCSAVE_3 /* save interruptee's a0 */\r
+ s32i a0, sp, XT_STK_A0\r
+ movi a0, _xt_medint3_exit /* save exit point for dispatch */\r
+ s32i a0, sp, XT_STK_EXIT\r
+\r
+ /* Save rest of interrupt context and enter RTOS. */\r
+ call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */\r
+\r
+ /* !! We are now on the RTOS system stack !! */\r
+\r
+ /* Set up PS for C, enable interrupts above this level and clear EXCM. */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ movi a0, PS_INTLEVEL(3) | PS_UM\r
+ #else\r
+ movi a0, PS_INTLEVEL(3) | PS_UM | PS_WOE\r
+ #endif\r
+ wsr a0, PS\r
+ rsync\r
+\r
+ /* OK to call C code at this point, dispatch user ISRs */\r
+\r
+ dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK\r
+\r
+ /* Done handling interrupts, transfer control to OS */\r
+ call0 XT_RTOS_INT_EXIT /* does not return directly here */\r
+\r
+ /*\r
+ Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT\r
+ on entry and used to return to a thread or interrupted interrupt handler.\r
+ */\r
+ .global _xt_medint3_exit\r
+ .type _xt_medint3_exit,@function\r
+ .align 4\r
+_xt_medint3_exit:\r
+ /* Restore only level-specific regs (the rest were already restored) */\r
+ l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */\r
+ wsr a0, EPS_3\r
+ l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */\r
+ wsr a0, EPC_3\r
+ l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */\r
+ l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */\r
+ rsync /* ensure EPS and EPC written */\r
+ rfi 3\r
+\r
+#endif /* Level 3 */\r
+\r
+#if XCHAL_EXCM_LEVEL >= 4\r
+\r
+ .begin literal_prefix .Level4InterruptVector\r
+ .section .Level4InterruptVector.text, "ax"\r
+ .global _Level4Vector\r
+ .type _Level4Vector,@function\r
+ .align 4\r
+_Level4Vector:\r
+ wsr a0, EXCSAVE_4 /* preserve a0 */\r
+ call0 _xt_medint4 /* load interrupt handler */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_medint4,@function\r
+ .align 4\r
+_xt_medint4:\r
+ mov a0, sp /* sp == a1 */\r
+ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */\r
+ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */\r
+ rsr a0, EPS_4 /* save interruptee's PS */\r
+ s32i a0, sp, XT_STK_PS\r
+ rsr a0, EPC_4 /* save interruptee's PC */\r
+ s32i a0, sp, XT_STK_PC\r
+ rsr a0, EXCSAVE_4 /* save interruptee's a0 */\r
+ s32i a0, sp, XT_STK_A0\r
+ movi a0, _xt_medint4_exit /* save exit point for dispatch */\r
+ s32i a0, sp, XT_STK_EXIT\r
+\r
+ /* Save rest of interrupt context and enter RTOS. */\r
+ call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */\r
+\r
+ /* !! We are now on the RTOS system stack !! */\r
+\r
+ /* Set up PS for C, enable interrupts above this level and clear EXCM. */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ movi a0, PS_INTLEVEL(4) | PS_UM\r
+ #else\r
+ movi a0, PS_INTLEVEL(4) | PS_UM | PS_WOE\r
+ #endif\r
+ wsr a0, PS\r
+ rsync\r
+\r
+ /* OK to call C code at this point, dispatch user ISRs */\r
+\r
+ dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK\r
+\r
+ /* Done handling interrupts, transfer control to OS */\r
+ call0 XT_RTOS_INT_EXIT /* does not return directly here */\r
+\r
+ /*\r
+ Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT\r
+ on entry and used to return to a thread or interrupted interrupt handler.\r
+ */\r
+ .global _xt_medint4_exit\r
+ .type _xt_medint4_exit,@function\r
+ .align 4\r
+_xt_medint4_exit:\r
+ /* Restore only level-specific regs (the rest were already restored) */\r
+ l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */\r
+ wsr a0, EPS_4\r
+ l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */\r
+ wsr a0, EPC_4\r
+ l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */\r
+ l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */\r
+ rsync /* ensure EPS and EPC written */\r
+ rfi 4\r
+\r
+#endif /* Level 4 */\r
+\r
+#if XCHAL_EXCM_LEVEL >= 5\r
+\r
+ .begin literal_prefix .Level5InterruptVector\r
+ .section .Level5InterruptVector.text, "ax"\r
+ .global _Level5Vector\r
+ .type _Level5Vector,@function\r
+ .align 4\r
+_Level5Vector:\r
+ wsr a0, EXCSAVE_5 /* preserve a0 */\r
+ call0 _xt_medint5 /* load interrupt handler */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_medint5,@function\r
+ .align 4\r
+_xt_medint5:\r
+ mov a0, sp /* sp == a1 */\r
+ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */\r
+ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */\r
+ rsr a0, EPS_5 /* save interruptee's PS */\r
+ s32i a0, sp, XT_STK_PS\r
+ rsr a0, EPC_5 /* save interruptee's PC */\r
+ s32i a0, sp, XT_STK_PC\r
+ rsr a0, EXCSAVE_5 /* save interruptee's a0 */\r
+ s32i a0, sp, XT_STK_A0\r
+ movi a0, _xt_medint5_exit /* save exit point for dispatch */\r
+ s32i a0, sp, XT_STK_EXIT\r
+\r
+ /* Save rest of interrupt context and enter RTOS. */\r
+ call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */\r
+\r
+ /* !! We are now on the RTOS system stack !! */\r
+\r
+ /* Set up PS for C, enable interrupts above this level and clear EXCM. */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ movi a0, PS_INTLEVEL(5) | PS_UM\r
+ #else\r
+ movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE\r
+ #endif\r
+ wsr a0, PS\r
+ rsync\r
+\r
+ /* OK to call C code at this point, dispatch user ISRs */\r
+\r
+ dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK\r
+\r
+ /* Done handling interrupts, transfer control to OS */\r
+ call0 XT_RTOS_INT_EXIT /* does not return directly here */\r
+\r
+ /*\r
+ Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT\r
+ on entry and used to return to a thread or interrupted interrupt handler.\r
+ */\r
+ .global _xt_medint5_exit\r
+ .type _xt_medint5_exit,@function\r
+ .align 4\r
+_xt_medint5_exit:\r
+ /* Restore only level-specific regs (the rest were already restored) */\r
+ l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */\r
+ wsr a0, EPS_5\r
+ l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */\r
+ wsr a0, EPC_5\r
+ l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */\r
+ l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */\r
+ rsync /* ensure EPS and EPC written */\r
+ rfi 5\r
+\r
+#endif /* Level 5 */\r
+\r
+#if XCHAL_EXCM_LEVEL >= 6\r
+\r
+ .begin literal_prefix .Level6InterruptVector\r
+ .section .Level6InterruptVector.text, "ax"\r
+ .global _Level6Vector\r
+ .type _Level6Vector,@function\r
+ .align 4\r
+_Level6Vector:\r
+ wsr a0, EXCSAVE_6 /* preserve a0 */\r
+ call0 _xt_medint6 /* load interrupt handler */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_medint6,@function\r
+ .align 4\r
+_xt_medint6:\r
+ mov a0, sp /* sp == a1 */\r
+ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */\r
+ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */\r
+ rsr a0, EPS_6 /* save interruptee's PS */\r
+ s32i a0, sp, XT_STK_PS\r
+ rsr a0, EPC_6 /* save interruptee's PC */\r
+ s32i a0, sp, XT_STK_PC\r
+ rsr a0, EXCSAVE_6 /* save interruptee's a0 */\r
+ s32i a0, sp, XT_STK_A0\r
+ movi a0, _xt_medint6_exit /* save exit point for dispatch */\r
+ s32i a0, sp, XT_STK_EXIT\r
+\r
+ /* Save rest of interrupt context and enter RTOS. */\r
+ call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */\r
+\r
+ /* !! We are now on the RTOS system stack !! */\r
+\r
+ /* Set up PS for C, enable interrupts above this level and clear EXCM. */\r
+ #ifdef __XTENSA_CALL0_ABI__\r
+ movi a0, PS_INTLEVEL(6) | PS_UM\r
+ #else\r
+ movi a0, PS_INTLEVEL(6) | PS_UM | PS_WOE\r
+ #endif\r
+ wsr a0, PS\r
+ rsync\r
+\r
+ /* OK to call C code at this point, dispatch user ISRs */\r
+\r
+ dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK\r
+\r
+ /* Done handling interrupts, transfer control to OS */\r
+ call0 XT_RTOS_INT_EXIT /* does not return directly here */\r
+\r
+ /*\r
+ Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT\r
+ on entry and used to return to a thread or interrupted interrupt handler.\r
+ */\r
+ .global _xt_medint6_exit\r
+ .type _xt_medint6_exit,@function\r
+ .align 4\r
+_xt_medint6_exit:\r
+ /* Restore only level-specific regs (the rest were already restored) */\r
+ l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */\r
+ wsr a0, EPS_6\r
+ l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */\r
+ wsr a0, EPC_6\r
+ l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */\r
+ l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */\r
+ rsync /* ensure EPS and EPC written */\r
+ rfi 6\r
+\r
+#endif /* Level 6 */\r
+\r
+\r
+/*******************************************************************************\r
+\r
+HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS\r
+\r
+High priority interrupts are by definition those with priorities greater\r
+than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority\r
+interrupts cannot interact with the RTOS, that is they must save all regs\r
+they use and not call any RTOS function.\r
+\r
+A further restriction imposed by the Xtensa windowed architecture is that\r
+high priority interrupts must not modify the stack area even logically\r
+"above" the top of the interrupted stack (they need to provide their\r
+own stack or static save area).\r
+\r
+Cadence Design Systems recommends high priority interrupt handlers be coded in assembly\r
+and used for purposes requiring very short service times.\r
+\r
+Here are templates for high priority (level 2+) interrupt vectors.\r
+They assume only one interrupt per level to avoid the burden of identifying\r
+which interrupts at this level are pending and enabled. This allows for \r
+minimum latency and avoids having to save/restore a2 in addition to a0.\r
+If more than one interrupt per high priority level is configured, this burden\r
+is on the handler which in any case must provide a way to save and restore\r
+registers it uses without touching the interrupted stack.\r
+\r
+Each vector goes at a predetermined location according to the Xtensa\r
+hardware configuration, which is ensured by its placement in a special\r
+section known to the Xtensa linker support package (LSP). It performs\r
+the minimum necessary before jumping to the handler in the .text section.\r
+\r
+*******************************************************************************/\r
+\r
+/*\r
+Currently only shells for high priority interrupt handlers are provided\r
+here. However a template and example can be found in the Cadence Design Systems tools\r
+documentation: "Microprocessor Programmer's Guide".\r
+*/\r
+\r
+#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2\r
+\r
+ .begin literal_prefix .Level2InterruptVector\r
+ .section .Level2InterruptVector.text, "ax"\r
+ .global _Level2Vector\r
+ .type _Level2Vector,@function\r
+ .align 4\r
+_Level2Vector:\r
+ wsr a0, EXCSAVE_2 /* preserve a0 */\r
+ call0 _xt_highint2 /* load interrupt handler */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_highint2,@function\r
+ .align 4\r
+_xt_highint2:\r
+\r
+ #ifdef XT_INTEXC_HOOKS\r
+ /* Call interrupt hook if present to (pre)handle interrupts. */\r
+ movi a0, _xt_intexc_hooks\r
+ l32i a0, a0, 2<<2\r
+ beqz a0, 1f\r
+.Ln_xt_highint2_call_hook:\r
+ callx0 a0 /* must NOT disturb stack! */\r
+1:\r
+ #endif\r
+\r
+ /* USER_EDIT:\r
+ ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.\r
+ */\r
+\r
+ .align 4\r
+.L_xt_highint2_exit:\r
+ rsr a0, EXCSAVE_2 /* restore a0 */\r
+ rfi 2\r
+\r
+#endif /* Level 2 */\r
+\r
+#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3\r
+\r
+ .begin literal_prefix .Level3InterruptVector\r
+ .section .Level3InterruptVector.text, "ax"\r
+ .global _Level3Vector\r
+ .type _Level3Vector,@function\r
+ .align 4\r
+_Level3Vector:\r
+ wsr a0, EXCSAVE_3 /* preserve a0 */\r
+ call0 _xt_highint3 /* load interrupt handler */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_highint3,@function\r
+ .align 4\r
+_xt_highint3:\r
+\r
+ #ifdef XT_INTEXC_HOOKS\r
+ /* Call interrupt hook if present to (pre)handle interrupts. */\r
+ movi a0, _xt_intexc_hooks\r
+ l32i a0, a0, 3<<2\r
+ beqz a0, 1f\r
+.Ln_xt_highint3_call_hook:\r
+ callx0 a0 /* must NOT disturb stack! */\r
+1:\r
+ #endif\r
+\r
+ /* USER_EDIT:\r
+ ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.\r
+ */\r
+\r
+ .align 4\r
+.L_xt_highint3_exit:\r
+ rsr a0, EXCSAVE_3 /* restore a0 */\r
+ rfi 3\r
+\r
+#endif /* Level 3 */\r
+\r
+#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4\r
+\r
+ .begin literal_prefix .Level4InterruptVector\r
+ .section .Level4InterruptVector.text, "ax"\r
+ .global _Level4Vector\r
+ .type _Level4Vector,@function\r
+ .align 4\r
+_Level4Vector:\r
+ wsr a0, EXCSAVE_4 /* preserve a0 */\r
+ call0 _xt_highint4 /* load interrupt handler */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_highint4,@function\r
+ .align 4\r
+_xt_highint4:\r
+\r
+ #ifdef XT_INTEXC_HOOKS\r
+ /* Call interrupt hook if present to (pre)handle interrupts. */\r
+ movi a0, _xt_intexc_hooks\r
+ l32i a0, a0, 4<<2\r
+ beqz a0, 1f\r
+.Ln_xt_highint4_call_hook:\r
+ callx0 a0 /* must NOT disturb stack! */\r
+1:\r
+ #endif\r
+\r
+ /* USER_EDIT:\r
+ ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.\r
+ */\r
+\r
+ .align 4\r
+.L_xt_highint4_exit:\r
+ rsr a0, EXCSAVE_4 /* restore a0 */\r
+ rfi 4\r
+\r
+#endif /* Level 4 */\r
+\r
+#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5\r
+\r
+ .begin literal_prefix .Level5InterruptVector\r
+ .section .Level5InterruptVector.text, "ax"\r
+ .global _Level5Vector\r
+ .type _Level5Vector,@function\r
+ .align 4\r
+_Level5Vector:\r
+ wsr a0, EXCSAVE_5 /* preserve a0 */\r
+ call0 _xt_highint5 /* load interrupt handler */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_highint5,@function\r
+ .align 4\r
+_xt_highint5:\r
+\r
+ #ifdef XT_INTEXC_HOOKS\r
+ /* Call interrupt hook if present to (pre)handle interrupts. */\r
+ movi a0, _xt_intexc_hooks\r
+ l32i a0, a0, 5<<2\r
+ beqz a0, 1f\r
+.Ln_xt_highint5_call_hook:\r
+ callx0 a0 /* must NOT disturb stack! */\r
+1:\r
+ #endif\r
+\r
+ /* USER_EDIT:\r
+ ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.\r
+ */\r
+\r
+ .align 4\r
+.L_xt_highint5_exit:\r
+ rsr a0, EXCSAVE_5 /* restore a0 */\r
+ rfi 5\r
+\r
+#endif /* Level 5 */\r
+\r
+#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6\r
+\r
+ .begin literal_prefix .Level6InterruptVector\r
+ .section .Level6InterruptVector.text, "ax"\r
+ .global _Level6Vector\r
+ .type _Level6Vector,@function\r
+ .align 4\r
+_Level6Vector:\r
+ wsr a0, EXCSAVE_6 /* preserve a0 */\r
+ call0 _xt_highint6 /* load interrupt handler */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_highint6,@function\r
+ .align 4\r
+_xt_highint6:\r
+\r
+ #ifdef XT_INTEXC_HOOKS\r
+ /* Call interrupt hook if present to (pre)handle interrupts. */\r
+ movi a0, _xt_intexc_hooks\r
+ l32i a0, a0, 6<<2\r
+ beqz a0, 1f\r
+.Ln_xt_highint6_call_hook:\r
+ callx0 a0 /* must NOT disturb stack! */\r
+1:\r
+ #endif\r
+\r
+ /* USER_EDIT:\r
+ ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.\r
+ */\r
+\r
+ .align 4\r
+.L_xt_highint6_exit:\r
+ rsr a0, EXCSAVE_6 /* restore a0 */\r
+ rfi 6\r
+\r
+#endif /* Level 6 */\r
+\r
+#if XCHAL_HAVE_NMI\r
+\r
+ .begin literal_prefix .NMIExceptionVector\r
+ .section .NMIExceptionVector.text, "ax"\r
+ .global _NMIExceptionVector\r
+ .type _NMIExceptionVector,@function\r
+ .align 4\r
+_NMIExceptionVector:\r
+ wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */\r
+ call0 _xt_nmi /* load interrupt handler */\r
+ /* never returns here - call0 is used as a jump (see note at top) */\r
+\r
+ .end literal_prefix\r
+\r
+ .text\r
+ .type _xt_nmi,@function\r
+ .align 4\r
+_xt_nmi:\r
+\r
+ #ifdef XT_INTEXC_HOOKS\r
+ /* Call interrupt hook if present to (pre)handle interrupts. */\r
+ movi a0, _xt_intexc_hooks\r
+ l32i a0, a0, XCHAL_NMILEVEL<<2\r
+ beqz a0, 1f\r
+.Ln_xt_nmi_call_hook:\r
+ callx0 a0 /* must NOT disturb stack! */\r
+1:\r
+ #endif\r
+\r
+ /* USER_EDIT:\r
+ ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE.\r
+ */\r
+\r
+ .align 4\r
+.L_xt_nmi_exit:\r
+ rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */\r
+ rfi XCHAL_NMILEVEL\r
+\r
+#endif /* NMI */\r
+\r
+\r
+/*******************************************************************************\r
+\r
+WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER\r
+\r
+Here is the code for each window overflow/underflow exception vector and \r
+(interspersed) efficient code for handling the alloca exception cause.\r
+Window exceptions are handled entirely in the vector area and are very\r
+tight for performance. The alloca exception is also handled entirely in \r
+the window vector area so comes at essentially no cost in code size.\r
+Users should never need to modify them and Cadence Design Systems recommends \r
+they do not.\r
+\r
+Window handlers go at predetermined vector locations according to the\r
+Xtensa hardware configuration, which is ensured by their placement in a\r
+special section known to the Xtensa linker support package (LSP). Since\r
+their offsets in that section are always the same, the LSPs do not define\r
+a section per vector.\r
+\r
+These things are coded for XEA2 only (XEA1 is not supported).\r
+\r
+Note on Underflow Handlers:\r
+The underflow handler for returning from call[i+1] to call[i]\r
+must preserve all the registers from call[i+1]'s window.\r
+In particular, a0 and a1 must be preserved because the RETW instruction\r
+will be reexecuted (and may even underflow if an intervening exception\r
+has flushed call[i]'s registers).\r
+Registers a2 and up may contain return values.\r
+\r
+*******************************************************************************/\r
+\r
+#if XCHAL_HAVE_WINDOWED\r
+\r
+ .section .WindowVectors.text, "ax"\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Window Overflow Exception for Call4.\r
+\r
+Invoked if a call[i] referenced a register (a4-a15)\r
+that contains data from ancestor call[j];\r
+call[j] had done a call4 to call[j+1].\r
+On entry here:\r
+ window rotated to call[j] start point;\r
+ a0-a3 are registers to be saved;\r
+ a4-a15 must be preserved;\r
+ a5 is call[j+1]'s stack pointer.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .org 0x0\r
+ .global _WindowOverflow4\r
+_WindowOverflow4:\r
+\r
+ s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */\r
+ s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */\r
+ s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */\r
+ s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */\r
+ rfwo /* rotates back to call[i] position */\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Window Underflow Exception for Call4\r
+\r
+Invoked by RETW returning from call[i+1] to call[i]\r
+where call[i]'s registers must be reloaded (not live in ARs);\r
+where call[i] had done a call4 to call[i+1].\r
+On entry here:\r
+ window rotated to call[i] start point;\r
+ a0-a3 are undefined, must be reloaded with call[i].reg[0..3];\r
+ a4-a15 must be preserved (they are call[i+1].reg[0..11]);\r
+ a5 is call[i+1]'s stack pointer.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .org 0x40\r
+ .global _WindowUnderflow4\r
+_WindowUnderflow4:\r
+\r
+ l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */\r
+ l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */\r
+ l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */\r
+ l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */\r
+ rfwu\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Handle alloca exception generated by interruptee executing 'movsp'.\r
+This uses space between the window vectors, so is essentially "free".\r
+All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,\r
+and PS.EXCM has been set by the exception hardware (can't be interrupted).\r
+The fact the alloca exception was taken means the registers associated with\r
+the base-save area have been spilled and will be restored by the underflow\r
+handler, so those 4 registers are available for scratch.\r
+The code is optimized to avoid unaligned branches and minimize cache misses.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .align 4\r
+ .global _xt_alloca_exc\r
+_xt_alloca_exc:\r
+\r
+ rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */\r
+ rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */\r
+ rsr a2, PS\r
+ extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS\r
+ xor a3, a3, a4 /* bits changed from old to current windowbase */\r
+ rsr a4, EXCSAVE_1 /* restore original a0 (now in a4) */\r
+ slli a3, a3, XCHAL_PS_OWB_SHIFT\r
+ xor a2, a2, a3 /* flip changed bits in old window base */\r
+ wsr a2, PS /* update PS.OWB to new window base */\r
+ rsync\r
+\r
+ _bbci.l a4, 31, _WindowUnderflow4\r
+ rotw -1 /* original a0 goes to a8 */\r
+ _bbci.l a8, 30, _WindowUnderflow8\r
+ rotw -1\r
+ j _WindowUnderflow12\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Window Overflow Exception for Call8\r
+\r
+Invoked if a call[i] referenced a register (a4-a15)\r
+that contains data from ancestor call[j];\r
+call[j] had done a call8 to call[j+1].\r
+On entry here:\r
+ window rotated to call[j] start point;\r
+ a0-a7 are registers to be saved;\r
+ a8-a15 must be preserved;\r
+ a9 is call[j+1]'s stack pointer.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .org 0x80\r
+ .global _WindowOverflow8\r
+_WindowOverflow8:\r
+\r
+ s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */\r
+ l32e a0, a1, -12 /* a0 <- call[j-1]'s sp\r
+ (used to find end of call[j]'s frame) */\r
+ s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */\r
+ s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */\r
+ s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */\r
+ s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */\r
+ s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */\r
+ s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */\r
+ s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */\r
+ rfwo /* rotates back to call[i] position */\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Window Underflow Exception for Call8\r
+\r
+Invoked by RETW returning from call[i+1] to call[i]\r
+where call[i]'s registers must be reloaded (not live in ARs);\r
+where call[i] had done a call8 to call[i+1].\r
+On entry here:\r
+ window rotated to call[i] start point;\r
+ a0-a7 are undefined, must be reloaded with call[i].reg[0..7];\r
+ a8-a15 must be preserved (they are call[i+1].reg[0..7]);\r
+ a9 is call[i+1]'s stack pointer.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .org 0xC0\r
+ .global _WindowUnderflow8\r
+_WindowUnderflow8:\r
+\r
+ l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */\r
+ l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */\r
+ l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */\r
+ l32e a7, a1, -12 /* a7 <- call[i-1]'s sp\r
+ (used to find end of call[i]'s frame) */\r
+ l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */\r
+ l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */\r
+ l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */\r
+ l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */\r
+ l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */\r
+ rfwu\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Window Overflow Exception for Call12\r
+\r
+Invoked if a call[i] referenced a register (a4-a15)\r
+that contains data from ancestor call[j];\r
+call[j] had done a call12 to call[j+1].\r
+On entry here:\r
+ window rotated to call[j] start point;\r
+ a0-a11 are registers to be saved;\r
+ a12-a15 must be preserved;\r
+ a13 is call[j+1]'s stack pointer.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .org 0x100\r
+ .global _WindowOverflow12\r
+_WindowOverflow12:\r
+\r
+ s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */\r
+ l32e a0, a1, -12 /* a0 <- call[j-1]'s sp\r
+ (used to find end of call[j]'s frame) */\r
+ s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */\r
+ s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */\r
+ s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */\r
+ s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */\r
+ s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */\r
+ s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */\r
+ s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */\r
+ s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */\r
+ s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */\r
+ s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */\r
+ s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */\r
+ rfwo /* rotates back to call[i] position */\r
+\r
+/*\r
+--------------------------------------------------------------------------------\r
+Window Underflow Exception for Call12\r
+\r
+Invoked by RETW returning from call[i+1] to call[i]\r
+where call[i]'s registers must be reloaded (not live in ARs);\r
+where call[i] had done a call12 to call[i+1].\r
+On entry here:\r
+ window rotated to call[i] start point;\r
+ a0-a11 are undefined, must be reloaded with call[i].reg[0..11];\r
+ a12-a15 must be preserved (they are call[i+1].reg[0..3]);\r
+ a13 is call[i+1]'s stack pointer.\r
+--------------------------------------------------------------------------------\r
+*/\r
+\r
+ .org 0x140\r
+ .global _WindowUnderflow12\r
+_WindowUnderflow12:\r
+\r
+ l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */\r
+ l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */\r
+ l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */\r
+ l32e a11, a1, -12 /* a11 <- call[i-1]'s sp\r
+ (used to find end of call[i]'s frame) */\r
+ l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */\r
+ l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */\r
+ l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */\r
+ l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */\r
+ l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */\r
+ l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */\r
+ l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */\r
+ l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */\r
+ l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */\r
+ rfwu\r
+\r
+#endif /* XCHAL_HAVE_WINDOWED */\r
+\r
(that is, it will hold discrete messages with a little meta data that\r
says how big the next message is) check the buffer will be large enough\r
to hold at least one message. */\r
- configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );\r
+ if( xIsMessageBuffer == pdTRUE )\r
+ {\r
+ configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );\r
+ }\r
+ else\r
+ {\r
+ configASSERT( xBufferSizeBytes > 0 );\r
+ }\r
configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );\r
\r
/* A trigger level of 0 would cause a waiting task to unblock even when\r
projects / freertos / commitdiff