MIPS: Clear hazard between TagLo writes & cache ops

Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index e61432ee9c611a9c3e3d7e25dcf80cbdd990ec1f..53e903a27ea97df9faf11c50ec48e7edb1b126bd 100644 (file)
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -293,6 +293,7 @@ l2_init:
 l1_init:
        mtc0            zero, CP0_TAGLO
        mtc0            zero, CP0_TAGLO, 2
+       ehb
 
        /*
         * The caches are probably in an indeterminate state, so we force good