static bool ChibiOS_detect_rtos(struct target *target);
static int ChibiOS_create(struct target *target);
static int ChibiOS_update_threads(struct rtos *rtos);
-static int ChibiOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
+static int ChibiOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+ struct rtos_reg **reg_list, int *num_regs);
static int ChibiOS_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[]);
struct rtos_type ChibiOS_rtos = {
return 0;
}
-static int ChibiOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list)
+static int ChibiOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+ struct rtos_reg **reg_list, int *num_regs)
{
int retval;
const struct ChibiOS_params *param;
uint32_t stack_ptr = 0;
- *hex_reg_list = NULL;
if ((rtos == NULL) || (thread_id == 0) ||
(rtos->rtos_specific_params == NULL))
return -1;
return retval;
}
- return rtos_generic_stack_read(rtos->target, param->stacking_info, stack_ptr, hex_reg_list);
+ return rtos_generic_stack_read(rtos->target, param->stacking_info, stack_ptr, reg_list, num_regs);
}
static int ChibiOS_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
static bool FreeRTOS_detect_rtos(struct target *target);
static int FreeRTOS_create(struct target *target);
static int FreeRTOS_update_threads(struct rtos *rtos);
-static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
+static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+ struct rtos_reg **reg_list, int *num_regs);
static int FreeRTOS_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[]);
struct rtos_type FreeRTOS_rtos = {
return 0;
}
-static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list)
+static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+ struct rtos_reg **reg_list, int *num_regs)
{
int retval;
const struct FreeRTOS_params *param;
int64_t stack_ptr = 0;
- *hex_reg_list = NULL;
if (rtos == NULL)
return -1;
return retval;
}
if ((LR_svc & 0x10) == 0)
- return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f_fpu, stack_ptr, hex_reg_list);
+ return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f_fpu, stack_ptr, reg_list, num_regs);
else
- return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f, stack_ptr, hex_reg_list);
+ return rtos_generic_stack_read(rtos->target, param->stacking_info_cm4f, stack_ptr, reg_list, num_regs);
} else
- return rtos_generic_stack_read(rtos->target, param->stacking_info_cm3, stack_ptr, hex_reg_list);
+ return rtos_generic_stack_read(rtos->target, param->stacking_info_cm3, stack_ptr, reg_list, num_regs);
}
static int FreeRTOS_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
static bool ThreadX_detect_rtos(struct target *target);
static int ThreadX_create(struct target *target);
static int ThreadX_update_threads(struct rtos *rtos);
-static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
+static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs);
static int ThreadX_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[]);
#define ARM926EJS_REGISTERS_SIZE_SOLICITED (11 * 4)
static const struct stack_register_offset rtos_threadx_arm926ejs_stack_offsets_solicited[] = {
- { -1, 32 }, /* r0 */
- { -1, 32 }, /* r1 */
- { -1, 32 }, /* r2 */
- { -1, 32 }, /* r3 */
- { 0x08, 32 }, /* r4 */
- { 0x0C, 32 }, /* r5 */
- { 0x10, 32 }, /* r6 */
- { 0x14, 32 }, /* r7 */
- { 0x18, 32 }, /* r8 */
- { 0x1C, 32 }, /* r9 */
- { 0x20, 32 }, /* r10 */
- { 0x24, 32 }, /* r11 */
- { -1, 32 }, /* r12 */
- { -2, 32 }, /* sp (r13) */
- { 0x28, 32 }, /* lr (r14) */
- { -1, 32 }, /* pc (r15) */
- /*{ -1, 32 },*/ /* lr (r14) */
- /*{ 0x28, 32 },*/ /* pc (r15) */
- { 0x04, 32 }, /* xPSR */
+ { 0, -1, 32 }, /* r0 */
+ { 1, -1, 32 }, /* r1 */
+ { 2, -1, 32 }, /* r2 */
+ { 3, -1, 32 }, /* r3 */
+ { 4, 0x08, 32 }, /* r4 */
+ { 5, 0x0C, 32 }, /* r5 */
+ { 6, 0x10, 32 }, /* r6 */
+ { 7, 0x14, 32 }, /* r7 */
+ { 8, 0x18, 32 }, /* r8 */
+ { 9, 0x1C, 32 }, /* r9 */
+ { 10, 0x20, 32 }, /* r10 */
+ { 11, 0x24, 32 }, /* r11 */
+ { 12, -1, 32 }, /* r12 */
+ { 13, -2, 32 }, /* sp (r13) */
+ { 14, 0x28, 32 }, /* lr (r14) */
+ { 15, -1, 32 }, /* pc (r15) */
+ /*{ 16, -1, 32 },*/ /* lr (r14) */
+ /*{ 17, 0x28, 32 },*/ /* pc (r15) */
+ { 16, 0x04, 32 }, /* xPSR */
};
#define ARM926EJS_REGISTERS_SIZE_INTERRUPT (17 * 4)
static const struct stack_register_offset rtos_threadx_arm926ejs_stack_offsets_interrupt[] = {
- { 0x08, 32 }, /* r0 */
- { 0x0C, 32 }, /* r1 */
- { 0x10, 32 }, /* r2 */
- { 0x14, 32 }, /* r3 */
- { 0x18, 32 }, /* r4 */
- { 0x1C, 32 }, /* r5 */
- { 0x20, 32 }, /* r6 */
- { 0x24, 32 }, /* r7 */
- { 0x28, 32 }, /* r8 */
- { 0x2C, 32 }, /* r9 */
- { 0x30, 32 }, /* r10 */
- { 0x34, 32 }, /* r11 */
- { 0x38, 32 }, /* r12 */
- { -2, 32 }, /* sp (r13) */
- { 0x3C, 32 }, /* lr (r14) */
- { 0x40, 32 }, /* pc (r15) */
- { 0x04, 32 }, /* xPSR */
+ { 0, 0x08, 32 }, /* r0 */
+ { 1, 0x0C, 32 }, /* r1 */
+ { 2, 0x10, 32 }, /* r2 */
+ { 3, 0x14, 32 }, /* r3 */
+ { 4, 0x18, 32 }, /* r4 */
+ { 5, 0x1C, 32 }, /* r5 */
+ { 6, 0x20, 32 }, /* r6 */
+ { 7, 0x24, 32 }, /* r7 */
+ { 8, 0x28, 32 }, /* r8 */
+ { 9, 0x2C, 32 }, /* r9 */
+ { 10, 0x30, 32 }, /* r10 */
+ { 11, 0x34, 32 }, /* r11 */
+ { 12, 0x38, 32 }, /* r12 */
+ { 13, -2, 32 }, /* sp (r13) */
+ { 14, 0x3C, 32 }, /* lr (r14) */
+ { 15, 0x40, 32 }, /* pc (r15) */
+ { 16, 0x04, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_threadx_arm926ejs_stacking[] = {
return 0;
}
-static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list)
+static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+ struct rtos_reg **reg_list, int *num_regs)
{
int retval;
const struct ThreadX_params *param;
- *hex_reg_list = NULL;
-
if (rtos == NULL)
return -1;
return -6;
}
- return rtos_generic_stack_read(rtos->target, stacking_info, stack_ptr, hex_reg_list);
+ return rtos_generic_stack_read(rtos->target, stacking_info, stack_ptr, reg_list, num_regs);
}
static int ThreadX_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
static bool eCos_detect_rtos(struct target *target);
static int eCos_create(struct target *target);
static int eCos_update_threads(struct rtos *rtos);
-static int eCos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
+static int eCos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, struct rtos_reg **reg_list, int *num_regs);
static int eCos_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[]);
struct eCos_thread_state {
return 0;
}
-static int eCos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list)
+static int eCos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+ struct rtos_reg **reg_list, int *num_regs)
{
int retval;
const struct eCos_params *param;
- *hex_reg_list = NULL;
-
if (rtos == NULL)
return -1;
return rtos_generic_stack_read(rtos->target,
param->stacking_info,
stack_ptr,
- hex_reg_list);
+ reg_list,
+ num_regs);
}
return -1;
static bool embKernel_detect_rtos(struct target *target);
static int embKernel_create(struct target *target);
static int embKernel_update_threads(struct rtos *rtos);
-static int embKernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
+static int embKernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+ struct rtos_reg **reg_list, int *num_regs);
static int embKernel_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[]);
struct rtos_type embKernel_rtos = {
return 0;
}
-static int embKernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list)
+static int embKernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+ struct rtos_reg **reg_list, int *num_regs)
{
int retval;
const struct embKernel_params *param;
int64_t stack_ptr = 0;
- *hex_reg_list = NULL;
if (rtos == NULL)
return -1;
return retval;
}
- return rtos_generic_stack_read(rtos->target, param->stacking_info, stack_ptr, hex_reg_list);
+ return rtos_generic_stack_read(rtos->target, param->stacking_info, stack_ptr, reg_list, num_regs);
}
static int embKernel_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
return ERROR_OK;
}
-static char *reg_converter(char *buffer, void *reg, int size)
-{
- int i;
-
- for (i = 0; i < size; i++)
- buffer += sprintf(buffer, "%02x", ((uint8_t *) reg)[i]);
-
- return buffer;
-}
-
int fill_buffer(struct target *target, uint32_t addr, uint8_t *buffer)
{
}
static int linux_os_thread_reg_list(struct rtos *rtos,
- int64_t thread_id, char **hex_reg_list)
+ int64_t thread_id, struct rtos_reg **reg_list, int *num_regs)
{
struct target *target = rtos->target;
struct linux_os *linux_os = (struct linux_os *)
target->rtos->rtos_specific_params;
- int i = 0;
struct current_thread *tmp = linux_os->current_threads;
struct current_thread *next;
- char *hex_string;
int found = 0;
int retval;
/* check if a current thread is requested */
next = next->next;
} while ((found == 0) && (next != tmp) && (next != NULL));
- if (found == 1) {
- /* search target to perfom the access */
- struct reg **reg_list;
- int reg_list_size, reg_packet_size = 0;
- struct target_list *head;
- head = target->head;
- found = 0;
- do {
- if (head->target->coreid == next->core_id) {
-
- target = head->target;
- found = 1;
- } else
- head = head->next;
-
- } while ((head != (struct target_list *)NULL) && (found == 0));
-
- if (found == 0) {
- LOG_ERROR
- (
- "current thread %" PRIx64 ": no target to perform access of core id %" PRIx32,
- thread_id,
- next->core_id);
- return ERROR_FAIL;
- }
-
- /*LOG_INFO("thread %lx current on core %x",thread_id,
- * target->coreid);*/
- retval =
- target_get_gdb_reg_list(target, ®_list, ®_list_size,
- REG_CLASS_GENERAL);
-
- if (retval != ERROR_OK)
- return retval;
-
- for (i = 0; i < reg_list_size; i++)
- reg_packet_size += reg_list[i]->size;
-
- assert(reg_packet_size > 0);
+ if (found == 0) {
+ LOG_ERROR("could not find thread: %" PRIx64, thread_id);
+ return ERROR_FAIL;
+ }
- *hex_reg_list = malloc(DIV_ROUND_UP(reg_packet_size, 8) * 2);
+ /* search target to perfom the access */
+ struct reg **gdb_reg_list;
+ struct target_list *head;
+ head = target->head;
+ found = 0;
+ do {
+ if (head->target->coreid == next->core_id) {
- hex_string = *hex_reg_list;
+ target = head->target;
+ found = 1;
+ } else
+ head = head->next;
- for (i = 0; i < reg_list_size; i++) {
- if (!reg_list[i]->valid)
- reg_list[i]->type->get(reg_list[i]);
+ } while ((head != (struct target_list *)NULL) && (found == 0));
- hex_string = reg_converter(hex_string,
- reg_list[i]->value,
- (reg_list[i]->size) / 8);
- }
+ if (found == 0) {
+ LOG_ERROR
+ (
+ "current thread %" PRIx64 ": no target to perform access of core id %" PRIx32,
+ thread_id,
+ next->core_id);
+ return ERROR_FAIL;
+ }
- free(reg_list);
+ /*LOG_INFO("thread %lx current on core %x",thread_id, target->coreid);*/
+ retval = target_get_gdb_reg_list(target, &gdb_reg_list, num_regs, REG_CLASS_GENERAL);
+ if (retval != ERROR_OK)
+ return retval;
- } else {
- struct threads *temp = linux_os->thread_list;
- *hex_reg_list = calloc(1, 500 * sizeof(char));
- hex_string = *hex_reg_list;
+ *reg_list = calloc(*num_regs, sizeof(struct rtos_reg));
- for (i = 0; i < 16; i++)
- hex_string += sprintf(hex_string, "%02x", 0);
+ for (int i = 0; i < *num_regs; ++i) {
+ if (!gdb_reg_list[i]->valid)
+ gdb_reg_list[i]->type->get(gdb_reg_list[i]);
- while ((temp != NULL) &&
- (temp->threadid != target->rtos->current_threadid))
- temp = temp->next;
+ (*reg_list)[i].number = gdb_reg_list[i]->number;
+ (*reg_list)[i].size = gdb_reg_list[i]->size;
- if (temp != NULL) {
- if (temp->context == NULL)
- temp->context = cpu_context_read(target,
- temp->
- base_addr,
- &temp->
- thread_info_addr);
-
- hex_string =
- reg_converter(hex_string, &temp->context->R4, 4);
- hex_string =
- reg_converter(hex_string, &temp->context->R5, 4);
- hex_string =
- reg_converter(hex_string, &temp->context->R6, 4);
- hex_string =
- reg_converter(hex_string, &temp->context->R7, 4);
- hex_string =
- reg_converter(hex_string, &temp->context->R8, 4);
- hex_string =
- reg_converter(hex_string, &temp->context->R9, 4);
-
- for (i = 0; i < 4; i++) /*R10 = 0x0 */
- hex_string += sprintf(hex_string, "%02x", 0);
-
- hex_string =
- reg_converter(hex_string, &temp->context->FP, 4);
- hex_string =
- reg_converter(hex_string, &temp->context->IP, 4);
- hex_string =
- reg_converter(hex_string, &temp->context->SP, 4);
-
- for (i = 0; i < 4; i++)
- hex_string += sprintf(hex_string, "%02x", 0);
-
- hex_string =
- reg_converter(hex_string, &temp->context->PC, 4);
-
- for (i = 0; i < 100; i++) /*100 */
- hex_string += sprintf(hex_string, "%02x", 0);
-
- uint32_t cpsr = 0x00000000;
- reg_converter(hex_string, &cpsr, 4);
- }
+ buf_cpy(gdb_reg_list[i]->value, (*reg_list)[i].value, (*reg_list)[i].size);
}
+
return ERROR_OK;
}
static int mqx_get_thread_reg_list(
struct rtos *rtos,
int64_t thread_id,
- char **hex_reg_list
+ struct rtos_reg **reg_list,
+ int *num_regs
)
{
int64_t stack_ptr = 0;
uint32_t task_queue_size = 0;
uint32_t kernel_data_addr = 0;
- *hex_reg_list = NULL;
if (thread_id == 0) {
LOG_ERROR("MQX RTOS - invalid threadid: 0x%X", (int)thread_id);
return ERROR_FAIL;
return ERROR_FAIL;
}
return rtos_generic_stack_read(
- rtos->target, ((struct mqx_params *)rtos->rtos_specific_params)->stacking_info, stack_ptr, hex_reg_list
+ rtos->target, ((struct mqx_params *)rtos->rtos_specific_params)->stacking_info, stack_ptr, reg_list, num_regs
);
}
/* see arch/arm/include/armv7-m/irq_cmnvector.h */
static const struct stack_register_offset nuttx_stack_offsets_cortex_m[] = {
- { 0x28, 32 }, /* r0 */
- { 0x2c, 32 }, /* r1 */
- { 0x30, 32 }, /* r2 */
- { 0x34, 32 }, /* r3 */
- { 0x08, 32 }, /* r4 */
- { 0x0c, 32 }, /* r5 */
- { 0x10, 32 }, /* r6 */
- { 0x14, 32 }, /* r7 */
- { 0x18, 32 }, /* r8 */
- { 0x1c, 32 }, /* r9 */
- { 0x20, 32 }, /* r10 */
- { 0x24, 32 }, /* r11 */
- { 0x38, 32 }, /* r12 */
- { 0, 32 }, /* sp */
- { 0x3c, 32 }, /* lr */
- { 0x40, 32 }, /* pc */
- { 0x44, 32 }, /* xPSR */
+ { ARMV7M_R0, 0x28, 32 }, /* r0 */
+ { ARMV7M_R1, 0x2c, 32 }, /* r1 */
+ { ARMV7M_R2, 0x30, 32 }, /* r2 */
+ { ARMV7M_R3, 0x34, 32 }, /* r3 */
+ { ARMV7M_R4, 0x08, 32 }, /* r4 */
+ { ARMV7M_R5, 0x0c, 32 }, /* r5 */
+ { ARMV7M_R6, 0x10, 32 }, /* r6 */
+ { ARMV7M_R7, 0x14, 32 }, /* r7 */
+ { ARMV7M_R8, 0x18, 32 }, /* r8 */
+ { ARMV7M_R9, 0x1c, 32 }, /* r9 */
+ { ARMV7M_R10, 0x20, 32 }, /* r10 */
+ { ARMV7M_R11, 0x24, 32 }, /* r11 */
+ { ARMV7M_R12, 0x38, 32 }, /* r12 */
+ { ARMV7M_R13, 0, 32 }, /* sp */
+ { ARMV7M_R14, 0x3c, 32 }, /* lr */
+ { ARMV7M_PC, 0x40, 32 }, /* pc */
+ { ARMV7M_xPSR, 0x44, 32 }, /* xPSR */
};
};
static const struct stack_register_offset nuttx_stack_offsets_cortex_m_fpu[] = {
- { 0x6c, 32 }, /* r0 */
- { 0x70, 32 }, /* r1 */
- { 0x74, 32 }, /* r2 */
- { 0x78, 32 }, /* r3 */
- { 0x08, 32 }, /* r4 */
- { 0x0c, 32 }, /* r5 */
- { 0x10, 32 }, /* r6 */
- { 0x14, 32 }, /* r7 */
- { 0x18, 32 }, /* r8 */
- { 0x1c, 32 }, /* r9 */
- { 0x20, 32 }, /* r10 */
- { 0x24, 32 }, /* r11 */
- { 0x7c, 32 }, /* r12 */
- { 0, 32 }, /* sp */
- { 0x80, 32 }, /* lr */
- { 0x84, 32 }, /* pc */
- { 0x88, 32 }, /* xPSR */
+ { ARMV7M_R0, 0x6c, 32 }, /* r0 */
+ { ARMV7M_R1, 0x70, 32 }, /* r1 */
+ { ARMV7M_R2, 0x74, 32 }, /* r2 */
+ { ARMV7M_R3, 0x78, 32 }, /* r3 */
+ { ARMV7M_R4, 0x08, 32 }, /* r4 */
+ { ARMV7M_R5, 0x0c, 32 }, /* r5 */
+ { ARMV7M_R6, 0x10, 32 }, /* r6 */
+ { ARMV7M_R7, 0x14, 32 }, /* r7 */
+ { ARMV7M_R8, 0x18, 32 }, /* r8 */
+ { ARMV7M_R9, 0x1c, 32 }, /* r9 */
+ { ARMV7M_R10, 0x20, 32 }, /* r10 */
+ { ARMV7M_R11, 0x24, 32 }, /* r11 */
+ { ARMV7M_R12, 0x7c, 32 }, /* r12 */
+ { ARMV7M_R13, 0, 32 }, /* sp */
+ { ARMV7M_R14, 0x80, 32 }, /* lr */
+ { ARMV7M_PC, 0x84, 32 }, /* pc */
+ { ARMV7M_xPSR, 0x88, 32 }, /* xPSR */
};
static const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu = {
* thread_id = tcb address;
*/
static int nuttx_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
- char **hex_reg_list) {
+ struct rtos_reg **reg_list, int *num_regs)
+{
int retval;
- *hex_reg_list = NULL;
-
/* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4F */
bool cm4_fpu_enabled = false;
struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
stacking = &nuttx_stacking_cortex_m;
return rtos_generic_stack_read(rtos->target, stacking,
- (uint32_t)thread_id + xcpreg_offset, hex_reg_list);
+ (uint32_t)thread_id + xcpreg_offset, reg_list, num_regs);
}
static int nuttx_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
return GDB_THREAD_PACKET_NOT_CONSUMED;
}
+static int rtos_put_gdb_reg_list(struct connection *connection,
+ struct rtos_reg *reg_list, int num_regs)
+{
+ size_t num_bytes = 1; /* NUL */
+ for (int i = 0; i < num_regs; ++i)
+ num_bytes += DIV_ROUND_UP(reg_list[i].size, 8) * 2;
+
+ char *hex = malloc(num_bytes);
+ char *hex_p = hex;
+
+ for (int i = 0; i < num_regs; ++i) {
+ size_t count = DIV_ROUND_UP(reg_list[i].size, 8);
+ size_t n = hexify(hex_p, reg_list[i].value, count, num_bytes);
+ hex_p += n;
+ num_bytes -= n;
+ }
+
+ gdb_put_packet(connection, hex, strlen(hex));
+ free(hex);
+
+ return ERROR_OK;
+}
+
+int rtos_get_gdb_reg(struct connection *connection, int reg_num)
+{
+ struct target *target = get_target_from_connection(connection);
+ int64_t current_threadid = target->rtos->current_threadid;
+ if ((target->rtos != NULL) && (current_threadid != -1) &&
+ (current_threadid != 0) &&
+ ((current_threadid != target->rtos->current_thread) ||
+ (target->smp))) { /* in smp several current thread are possible */
+ struct rtos_reg *reg_list;
+ int num_regs;
+
+ LOG_DEBUG("RTOS: getting register %d for thread 0x%" PRIx64
+ ", target->rtos->current_thread=0x%" PRIx64 "\r\n",
+ reg_num,
+ current_threadid,
+ target->rtos->current_thread);
+
+ int retval = target->rtos->type->get_thread_reg_list(target->rtos,
+ current_threadid,
+ ®_list,
+ &num_regs);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("RTOS: failed to get register list");
+ return retval;
+ }
+
+ for (int i = 0; i < num_regs; ++i) {
+ if (reg_list[i].number == (uint32_t)reg_num) {
+ rtos_put_gdb_reg_list(connection, reg_list + i, 1);
+ free(reg_list);
+ return ERROR_OK;
+ }
+ }
+
+ free(reg_list);
+ }
+ return ERROR_FAIL;
+}
+
int rtos_get_gdb_reg_list(struct connection *connection)
{
struct target *target = get_target_from_connection(connection);
(current_threadid != 0) &&
((current_threadid != target->rtos->current_thread) ||
(target->smp))) { /* in smp several current thread are possible */
- char *hex_reg_list;
+ struct rtos_reg *reg_list;
+ int num_regs;
LOG_DEBUG("RTOS: getting register list for thread 0x%" PRIx64
", target->rtos->current_thread=0x%" PRIx64 "\r\n",
int retval = target->rtos->type->get_thread_reg_list(target->rtos,
current_threadid,
- &hex_reg_list);
+ ®_list,
+ &num_regs);
if (retval != ERROR_OK) {
LOG_ERROR("RTOS: failed to get register list");
return retval;
}
- if (hex_reg_list != NULL) {
- gdb_put_packet(connection, hex_reg_list, strlen(hex_reg_list));
- free(hex_reg_list);
- return ERROR_OK;
- }
+ rtos_put_gdb_reg_list(connection, reg_list, num_regs);
+ free(reg_list);
+
+ return ERROR_OK;
}
return ERROR_FAIL;
}
int rtos_generic_stack_read(struct target *target,
const struct rtos_register_stacking *stacking,
int64_t stack_ptr,
- char **hex_reg_list)
+ struct rtos_reg **reg_list,
+ int *num_regs)
{
- int list_size = 0;
- char *tmp_str_ptr;
- int64_t new_stack_ptr;
- int i;
int retval;
if (stack_ptr == 0) {
LOG_OUTPUT("%02X", stack_data[i]);
LOG_OUTPUT("\r\n");
#endif
- for (i = 0; i < stacking->num_output_registers; i++)
- list_size += stacking->register_offsets[i].width_bits/8;
- *hex_reg_list = malloc(list_size*2 + 1);
- tmp_str_ptr = *hex_reg_list;
+
+ int64_t new_stack_ptr;
if (stacking->calculate_process_stack != NULL) {
new_stack_ptr = stacking->calculate_process_stack(target,
stack_data, stacking, stack_ptr);
new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
stacking->stack_registers_size;
}
- for (i = 0; i < stacking->num_output_registers; i++) {
- int j;
- for (j = 0; j < stacking->register_offsets[i].width_bits/8; j++) {
- if (stacking->register_offsets[i].offset == -1)
- tmp_str_ptr += sprintf(tmp_str_ptr, "%02x", 0);
- else if (stacking->register_offsets[i].offset == -2)
- tmp_str_ptr += sprintf(tmp_str_ptr, "%02x",
- ((uint8_t *)&new_stack_ptr)[j]);
- else
- tmp_str_ptr += sprintf(tmp_str_ptr, "%02x",
- stack_data[stacking->register_offsets[i].offset + j]);
- }
+
+ *reg_list = calloc(stacking->num_output_registers, sizeof(struct rtos_reg));
+ *num_regs = stacking->num_output_registers;
+
+ for (int i = 0; i < stacking->num_output_registers; ++i) {
+ (*reg_list)[i].number = stacking->register_offsets[i].number;
+ (*reg_list)[i].size = stacking->register_offsets[i].width_bits;
+
+ int offset = stacking->register_offsets[i].offset;
+ if (offset == -2)
+ buf_cpy(&new_stack_ptr, (*reg_list)[i].value, (*reg_list)[i].size);
+ else if (offset != -1)
+ buf_cpy(stack_data + offset, (*reg_list)[i].value, (*reg_list)[i].size);
}
+
free(stack_data);
/* LOG_OUTPUT("Output register string: %s\r\n", *hex_reg_list); */
return ERROR_OK;
void *rtos_specific_params;
};
+struct rtos_reg {
+ uint32_t number;
+ uint32_t size;
+ uint8_t value[8];
+};
+
struct rtos_type {
const char *name;
bool (*detect_rtos)(struct target *target);
int (*create)(struct target *target);
int (*smp_init)(struct target *target);
int (*update_threads)(struct rtos *rtos);
- int (*get_thread_reg_list)(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
+ int (*get_thread_reg_list)(struct rtos *rtos, int64_t thread_id,
+ struct rtos_reg **reg_list, int *num_regs);
int (*get_symbol_list_to_lookup)(symbol_table_elem_t *symbol_list[]);
int (*clean)(struct target *target);
char * (*ps_command)(struct target *target);
};
struct stack_register_offset {
+ unsigned short number; /* register number */
signed short offset; /* offset in bytes from stack head, or -1 to indicate
* register is not stacked, or -2 to indicate this is the
* stack pointer register */
int rtos_generic_stack_read(struct target *target,
const struct rtos_register_stacking *stacking,
int64_t stack_ptr,
- char **hex_reg_list);
+ struct rtos_reg **reg_list,
+ int *num_regs);
int rtos_try_next(struct target *target);
int gdb_thread_packet(struct connection *connection, char const *packet, int packet_size);
+int rtos_get_gdb_reg(struct connection *connection, int reg_num);
int rtos_get_gdb_reg_list(struct connection *connection);
int rtos_update_threads(struct target *target);
void rtos_free_threadlist(struct rtos *rtos);
#include "target/armv7m.h"
static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
- { -1, 32 }, /* r0 */
- { -1, 32 }, /* r1 */
- { -1, 32 }, /* r2 */
- { -1, 32 }, /* r3 */
- { 0x00, 32 }, /* r4 */
- { 0x04, 32 }, /* r5 */
- { 0x08, 32 }, /* r6 */
- { 0x0c, 32 }, /* r7 */
- { 0x10, 32 }, /* r8 */
- { 0x14, 32 }, /* r9 */
- { 0x18, 32 }, /* r10 */
- { 0x1c, 32 }, /* r11 */
- { -1, 32 }, /* r12 */
- { -2, 32 }, /* sp */
- { -1, 32 }, /* lr */
- { 0x20, 32 }, /* pc */
- { -1, 32 }, /* xPSR */
+ { ARMV7M_R0, -1, 32 }, /* r0 */
+ { ARMV7M_R1, -1, 32 }, /* r1 */
+ { ARMV7M_R2, -1, 32 }, /* r2 */
+ { ARMV7M_R3, -1, 32 }, /* r3 */
+ { ARMV7M_R4, 0x00, 32 }, /* r4 */
+ { ARMV7M_R5, 0x04, 32 }, /* r5 */
+ { ARMV7M_R6, 0x08, 32 }, /* r6 */
+ { ARMV7M_R7, 0x0c, 32 }, /* r7 */
+ { ARMV7M_R8, 0x10, 32 }, /* r8 */
+ { ARMV7M_R9, 0x14, 32 }, /* r9 */
+ { ARMV7M_R10, 0x18, 32 }, /* r10 */
+ { ARMV7M_R11, 0x1c, 32 }, /* r11 */
+ { ARMV7M_R12, -1, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, -1, 32 }, /* lr */
+ { ARMV7M_PC, 0x20, 32 }, /* pc */
+ { ARMV7M_xPSR, -1, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking = {
};
static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_fpu[ARMV7M_NUM_CORE_REGS] = {
- { -1, 32 }, /* r0 */
- { -1, 32 }, /* r1 */
- { -1, 32 }, /* r2 */
- { -1, 32 }, /* r3 */
- { 0x40, 32 }, /* r4 */
- { 0x44, 32 }, /* r5 */
- { 0x48, 32 }, /* r6 */
- { 0x4c, 32 }, /* r7 */
- { 0x50, 32 }, /* r8 */
- { 0x54, 32 }, /* r9 */
- { 0x58, 32 }, /* r10 */
- { 0x5c, 32 }, /* r11 */
- { -1, 32 }, /* r12 */
- { -2, 32 }, /* sp */
- { -1, 32 }, /* lr */
- { 0x60, 32 }, /* pc */
- { -1, 32 }, /* xPSR */
+ { ARMV7M_R0, -1, 32 }, /* r0 */
+ { ARMV7M_R1, -1, 32 }, /* r1 */
+ { ARMV7M_R2, -1, 32 }, /* r2 */
+ { ARMV7M_R3, -1, 32 }, /* r3 */
+ { ARMV7M_R4, 0x40, 32 }, /* r4 */
+ { ARMV7M_R5, 0x44, 32 }, /* r5 */
+ { ARMV7M_R6, 0x48, 32 }, /* r6 */
+ { ARMV7M_R7, 0x4c, 32 }, /* r7 */
+ { ARMV7M_R8, 0x50, 32 }, /* r8 */
+ { ARMV7M_R9, 0x54, 32 }, /* r9 */
+ { ARMV7M_R10, 0x58, 32 }, /* r10 */
+ { ARMV7M_R11, 0x5c, 32 }, /* r11 */
+ { ARMV7M_R12, -1, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, -1, 32 }, /* lr */
+ { ARMV7M_PC, 0x60, 32 }, /* pc */
+ { ARMV7M_xPSR, -1, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking_w_fpu = {
#include "target/armv7m.h"
static const struct stack_register_offset rtos_eCos_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
- { 0x0c, 32 }, /* r0 */
- { 0x10, 32 }, /* r1 */
- { 0x14, 32 }, /* r2 */
- { 0x18, 32 }, /* r3 */
- { 0x1c, 32 }, /* r4 */
- { 0x20, 32 }, /* r5 */
- { 0x24, 32 }, /* r6 */
- { 0x28, 32 }, /* r7 */
- { 0x2c, 32 }, /* r8 */
- { 0x30, 32 }, /* r9 */
- { 0x34, 32 }, /* r10 */
- { 0x38, 32 }, /* r11 */
- { 0x3c, 32 }, /* r12 */
- { -2, 32 }, /* sp */
- { -1, 32 }, /* lr */
- { 0x40, 32 }, /* pc */
- { -1, 32 }, /* xPSR */
+ { ARMV7M_R0, 0x0c, 32 }, /* r0 */
+ { ARMV7M_R1, 0x10, 32 }, /* r1 */
+ { ARMV7M_R2, 0x14, 32 }, /* r2 */
+ { ARMV7M_R3, 0x18, 32 }, /* r3 */
+ { ARMV7M_R4, 0x1c, 32 }, /* r4 */
+ { ARMV7M_R5, 0x20, 32 }, /* r5 */
+ { ARMV7M_R6, 0x24, 32 }, /* r6 */
+ { ARMV7M_R7, 0x28, 32 }, /* r7 */
+ { ARMV7M_R8, 0x2c, 32 }, /* r8 */
+ { ARMV7M_R9, 0x30, 32 }, /* r9 */
+ { ARMV7M_R10, 0x34, 32 }, /* r10 */
+ { ARMV7M_R11, 0x38, 32 }, /* r11 */
+ { ARMV7M_R12, 0x3c, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, -1, 32 }, /* lr */
+ { ARMV7M_PC, 0x40, 32 }, /* pc */
+ { ARMV7M_xPSR, -1, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_eCos_Cortex_M3_stacking = {
#include "rtos_standard_stackings.h"
static const struct stack_register_offset rtos_embkernel_Cortex_M_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
- { 0x24, 32 }, /* r0 */
- { 0x28, 32 }, /* r1 */
- { 0x2c, 32 }, /* r2 */
- { 0x30, 32 }, /* r3 */
- { 0x00, 32 }, /* r4 */
- { 0x04, 32 }, /* r5 */
- { 0x08, 32 }, /* r6 */
- { 0x0c, 32 }, /* r7 */
- { 0x10, 32 }, /* r8 */
- { 0x14, 32 }, /* r9 */
- { 0x18, 32 }, /* r10 */
- { 0x1c, 32 }, /* r11 */
- { 0x34, 32 }, /* r12 */
- { -2, 32 }, /* sp */
- { 0x38, 32 }, /* lr */
- { 0x3c, 32 }, /* pc */
- { 0x40, 32 }, /* xPSR */
+ { ARMV7M_R0, 0x24, 32 }, /* r0 */
+ { ARMV7M_R1, 0x28, 32 }, /* r1 */
+ { ARMV7M_R2, 0x2c, 32 }, /* r2 */
+ { ARMV7M_R3, 0x30, 32 }, /* r3 */
+ { ARMV7M_R4, 0x00, 32 }, /* r4 */
+ { ARMV7M_R5, 0x04, 32 }, /* r5 */
+ { ARMV7M_R6, 0x08, 32 }, /* r6 */
+ { ARMV7M_R7, 0x0c, 32 }, /* r7 */
+ { ARMV7M_R8, 0x10, 32 }, /* r8 */
+ { ARMV7M_R9, 0x14, 32 }, /* r9 */
+ { ARMV7M_R10, 0x18, 32 }, /* r10 */
+ { ARMV7M_R11, 0x1c, 32 }, /* r11 */
+ { ARMV7M_R12, 0x34, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, 0x38, 32 }, /* lr */
+ { ARMV7M_PC, 0x3c, 32 }, /* pc */
+ { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_embkernel_Cortex_M_stacking = {
*/
static const struct stack_register_offset rtos_mqx_arm_v7m_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
- { 0x2C, 32 }, /* r0 */
- { 0x30, 32 }, /* r1 */
- { 0x34, 32 }, /* r2 */
- { 0x38, 32 }, /* r3 */
- { 0x08, 32 }, /* r4 */
- { 0x0C, 32 }, /* r5 */
- { 0x10, 32 }, /* r6 */
- { 0x14, 32 }, /* r7 */
- { 0x18, 32 }, /* r8 */
- { 0x1C, 32 }, /* r9 */
- { 0x20, 32 }, /* r10 */
- { 0x24, 32 }, /* r11 */
- { 0x3C, 32 }, /* r12 */
- { -2 , 32 }, /* sp */
- { 0x28, 32 }, /* lr */
- { 0x44, 32 }, /* pc */
- { 0x48, 32 }, /* xPSR */
+ { ARMV7M_R0, 0x2C, 32 }, /* r0 */
+ { ARMV7M_R1, 0x30, 32 }, /* r1 */
+ { ARMV7M_R2, 0x34, 32 }, /* r2 */
+ { ARMV7M_R3, 0x38, 32 }, /* r3 */
+ { ARMV7M_R4, 0x08, 32 }, /* r4 */
+ { ARMV7M_R5, 0x0C, 32 }, /* r5 */
+ { ARMV7M_R6, 0x10, 32 }, /* r6 */
+ { ARMV7M_R7, 0x14, 32 }, /* r7 */
+ { ARMV7M_R8, 0x18, 32 }, /* r8 */
+ { ARMV7M_R9, 0x1C, 32 }, /* r9 */
+ { ARMV7M_R10, 0x20, 32 }, /* r10 */
+ { ARMV7M_R11, 0x24, 32 }, /* r11 */
+ { ARMV7M_R12, 0x3C, 32 }, /* r12 */
+ { ARMV7M_R13, -2 , 32 }, /* sp */
+ { ARMV7M_R14, 0x28, 32 }, /* lr */
+ { ARMV7M_PC, 0x44, 32 }, /* pc */
+ { ARMV7M_xPSR, 0x48, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_mqx_arm_v7m_stacking = {
#include "target/armv7m.h"
static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
- { 0x20, 32 }, /* r0 */
- { 0x24, 32 }, /* r1 */
- { 0x28, 32 }, /* r2 */
- { 0x2c, 32 }, /* r3 */
- { 0x00, 32 }, /* r4 */
- { 0x04, 32 }, /* r5 */
- { 0x08, 32 }, /* r6 */
- { 0x0c, 32 }, /* r7 */
- { 0x10, 32 }, /* r8 */
- { 0x14, 32 }, /* r9 */
- { 0x18, 32 }, /* r10 */
- { 0x1c, 32 }, /* r11 */
- { 0x30, 32 }, /* r12 */
- { -2, 32 }, /* sp */
- { 0x34, 32 }, /* lr */
- { 0x38, 32 }, /* pc */
- { 0x3c, 32 }, /* xPSR */
+ { ARMV7M_R0, 0x20, 32 }, /* r0 */
+ { ARMV7M_R1, 0x24, 32 }, /* r1 */
+ { ARMV7M_R2, 0x28, 32 }, /* r2 */
+ { ARMV7M_R3, 0x2c, 32 }, /* r3 */
+ { ARMV7M_R4, 0x00, 32 }, /* r4 */
+ { ARMV7M_R5, 0x04, 32 }, /* r5 */
+ { ARMV7M_R6, 0x08, 32 }, /* r6 */
+ { ARMV7M_R7, 0x0c, 32 }, /* r7 */
+ { ARMV7M_R8, 0x10, 32 }, /* r8 */
+ { ARMV7M_R9, 0x14, 32 }, /* r9 */
+ { ARMV7M_R10, 0x18, 32 }, /* r10 */
+ { ARMV7M_R11, 0x1c, 32 }, /* r11 */
+ { ARMV7M_R12, 0x30, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, 0x34, 32 }, /* lr */
+ { ARMV7M_PC, 0x38, 32 }, /* pc */
+ { ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_standard_Cortex_M4F_stack_offsets[] = {
- { 0x24, 32 }, /* r0 */
- { 0x28, 32 }, /* r1 */
- { 0x2c, 32 }, /* r2 */
- { 0x30, 32 }, /* r3 */
- { 0x00, 32 }, /* r4 */
- { 0x04, 32 }, /* r5 */
- { 0x08, 32 }, /* r6 */
- { 0x0c, 32 }, /* r7 */
- { 0x10, 32 }, /* r8 */
- { 0x14, 32 }, /* r9 */
- { 0x18, 32 }, /* r10 */
- { 0x1c, 32 }, /* r11 */
- { 0x34, 32 }, /* r12 */
- { -2, 32 }, /* sp */
- { 0x38, 32 }, /* lr */
- { 0x3c, 32 }, /* pc */
- { 0x40, 32 }, /* xPSR */
+ { ARMV7M_R0, 0x24, 32 }, /* r0 */
+ { ARMV7M_R1, 0x28, 32 }, /* r1 */
+ { ARMV7M_R2, 0x2c, 32 }, /* r2 */
+ { ARMV7M_R3, 0x30, 32 }, /* r3 */
+ { ARMV7M_R4, 0x00, 32 }, /* r4 */
+ { ARMV7M_R5, 0x04, 32 }, /* r5 */
+ { ARMV7M_R6, 0x08, 32 }, /* r6 */
+ { ARMV7M_R7, 0x0c, 32 }, /* r7 */
+ { ARMV7M_R8, 0x10, 32 }, /* r8 */
+ { ARMV7M_R9, 0x14, 32 }, /* r9 */
+ { ARMV7M_R10, 0x18, 32 }, /* r10 */
+ { ARMV7M_R11, 0x1c, 32 }, /* r11 */
+ { ARMV7M_R12, 0x34, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, 0x38, 32 }, /* lr */
+ { ARMV7M_PC, 0x3c, 32 }, /* pc */
+ { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_standard_Cortex_M4F_FPU_stack_offsets[] = {
- { 0x64, 32 }, /* r0 */
- { 0x68, 32 }, /* r1 */
- { 0x6c, 32 }, /* r2 */
- { 0x70, 32 }, /* r3 */
- { 0x00, 32 }, /* r4 */
- { 0x04, 32 }, /* r5 */
- { 0x08, 32 }, /* r6 */
- { 0x0c, 32 }, /* r7 */
- { 0x10, 32 }, /* r8 */
- { 0x14, 32 }, /* r9 */
- { 0x18, 32 }, /* r10 */
- { 0x1c, 32 }, /* r11 */
- { 0x74, 32 }, /* r12 */
- { -2, 32 }, /* sp */
- { 0x78, 32 }, /* lr */
- { 0x7c, 32 }, /* pc */
- { 0x80, 32 }, /* xPSR */
+ { ARMV7M_R0, 0x64, 32 }, /* r0 */
+ { ARMV7M_R1, 0x68, 32 }, /* r1 */
+ { ARMV7M_R2, 0x6c, 32 }, /* r2 */
+ { ARMV7M_R3, 0x70, 32 }, /* r3 */
+ { ARMV7M_R4, 0x00, 32 }, /* r4 */
+ { ARMV7M_R5, 0x04, 32 }, /* r5 */
+ { ARMV7M_R6, 0x08, 32 }, /* r6 */
+ { ARMV7M_R7, 0x0c, 32 }, /* r7 */
+ { ARMV7M_R8, 0x10, 32 }, /* r8 */
+ { ARMV7M_R9, 0x14, 32 }, /* r9 */
+ { ARMV7M_R10, 0x18, 32 }, /* r10 */
+ { ARMV7M_R11, 0x1c, 32 }, /* r11 */
+ { ARMV7M_R12, 0x74, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, 0x78, 32 }, /* lr */
+ { ARMV7M_PC, 0x7c, 32 }, /* pc */
+ { ARMV7M_xPSR, 0x80, 32 }, /* xPSR */
};
static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
- { 0x08, 32 }, /* r0 (a1) */
- { 0x0c, 32 }, /* r1 (a2) */
- { 0x10, 32 }, /* r2 (a3) */
- { 0x14, 32 }, /* r3 (a4) */
- { 0x18, 32 }, /* r4 (v1) */
- { 0x1c, 32 }, /* r5 (v2) */
- { 0x20, 32 }, /* r6 (v3) */
- { 0x24, 32 }, /* r7 (v4) */
- { 0x28, 32 }, /* r8 (a1) */
- { 0x2c, 32 }, /* r9 (sb) */
- { 0x30, 32 }, /* r10 (sl) */
- { 0x34, 32 }, /* r11 (fp) */
- { 0x38, 32 }, /* r12 (ip) */
- { -2, 32 }, /* sp */
- { 0x3c, 32 }, /* lr */
- { 0x40, 32 }, /* pc */
- { -1, 96 }, /* FPA1 */
- { -1, 96 }, /* FPA2 */
- { -1, 96 }, /* FPA3 */
- { -1, 96 }, /* FPA4 */
- { -1, 96 }, /* FPA5 */
- { -1, 96 }, /* FPA6 */
- { -1, 96 }, /* FPA7 */
- { -1, 96 }, /* FPA8 */
- { -1, 32 }, /* FPS */
- { 0x04, 32 }, /* CSPR */
+ { 0, 0x08, 32 }, /* r0 (a1) */
+ { 1, 0x0c, 32 }, /* r1 (a2) */
+ { 2, 0x10, 32 }, /* r2 (a3) */
+ { 3, 0x14, 32 }, /* r3 (a4) */
+ { 4, 0x18, 32 }, /* r4 (v1) */
+ { 5, 0x1c, 32 }, /* r5 (v2) */
+ { 6, 0x20, 32 }, /* r6 (v3) */
+ { 7, 0x24, 32 }, /* r7 (v4) */
+ { 8, 0x28, 32 }, /* r8 (a1) */
+ { 10, 0x2c, 32 }, /* r9 (sb) */
+ { 11, 0x30, 32 }, /* r10 (sl) */
+ { 12, 0x34, 32 }, /* r11 (fp) */
+ { 13, 0x38, 32 }, /* r12 (ip) */
+ { 14, -2, 32 }, /* sp */
+ { 15, 0x3c, 32 }, /* lr */
+ { 16, 0x40, 32 }, /* pc */
+ { 17, -1, 96 }, /* FPA1 */
+ { 18, -1, 96 }, /* FPA2 */
+ { 19, -1, 96 }, /* FPA3 */
+ { 20, -1, 96 }, /* FPA4 */
+ { 21, -1, 96 }, /* FPA5 */
+ { 22, -1, 96 }, /* FPA6 */
+ { 23, -1, 96 }, /* FPA7 */
+ { 24, -1, 96 }, /* FPA8 */
+ { 25, -1, 32 }, /* FPS */
+ { 26, 0x04, 32 }, /* CSPR */
};
static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offsets[] = {
- { 0x88, 32 }, /* R0 */
- { 0x8C, 32 }, /* R1 */
- { 0x14, 32 }, /* R2 */
- { 0x18, 32 }, /* R3 */
- { 0x1C, 32 }, /* R4 */
- { 0x20, 32 }, /* R5 */
- { 0x24, 32 }, /* R6 */
- { 0x28, 32 }, /* R7 */
- { 0x2C, 32 }, /* R8 */
- { 0x30, 32 }, /* R9 */
- { 0x34, 32 }, /* R10 */
- { 0x38, 32 }, /* R11 */
- { 0x3C, 32 }, /* R12 */
- { 0x40, 32 }, /* R13 */
- { 0x44, 32 }, /* R14 */
- { 0x48, 32 }, /* R15 */
- { 0x4C, 32 }, /* R16 */
- { 0x50, 32 }, /* R17 */
- { 0x54, 32 }, /* R18 */
- { 0x58, 32 }, /* R19 */
- { 0x5C, 32 }, /* R20 */
- { 0x60, 32 }, /* R21 */
- { 0x64, 32 }, /* R22 */
- { 0x68, 32 }, /* R23 */
- { 0x6C, 32 }, /* R24 */
- { 0x70, 32 }, /* R25 */
- { 0x74, 32 }, /* R26 */
- { 0x78, 32 }, /* R27 */
- { 0x7C, 32 }, /* R28 */
- { 0x80, 32 }, /* R29 */
- { 0x84, 32 }, /* R30 (LP) */
- { 0x00, 32 }, /* R31 (SP) */
- { 0x04, 32 }, /* PSW */
- { 0x08, 32 }, /* IPC */
- { 0x0C, 32 }, /* IPSW */
- { 0x10, 32 }, /* IFC_LP */
+ { 0, 0x88, 32 }, /* R0 */
+ { 1, 0x8C, 32 }, /* R1 */
+ { 2, 0x14, 32 }, /* R2 */
+ { 3, 0x18, 32 }, /* R3 */
+ { 4, 0x1C, 32 }, /* R4 */
+ { 5, 0x20, 32 }, /* R5 */
+ { 6, 0x24, 32 }, /* R6 */
+ { 7, 0x28, 32 }, /* R7 */
+ { 8, 0x2C, 32 }, /* R8 */
+ { 9, 0x30, 32 }, /* R9 */
+ { 10, 0x34, 32 }, /* R10 */
+ { 11, 0x38, 32 }, /* R11 */
+ { 12, 0x3C, 32 }, /* R12 */
+ { 13, 0x40, 32 }, /* R13 */
+ { 14, 0x44, 32 }, /* R14 */
+ { 15, 0x48, 32 }, /* R15 */
+ { 16, 0x4C, 32 }, /* R16 */
+ { 17, 0x50, 32 }, /* R17 */
+ { 18, 0x54, 32 }, /* R18 */
+ { 19, 0x58, 32 }, /* R19 */
+ { 20, 0x5C, 32 }, /* R20 */
+ { 21, 0x60, 32 }, /* R21 */
+ { 22, 0x64, 32 }, /* R22 */
+ { 23, 0x68, 32 }, /* R23 */
+ { 24, 0x6C, 32 }, /* R24 */
+ { 25, 0x70, 32 }, /* R25 */
+ { 26, 0x74, 32 }, /* R26 */
+ { 27, 0x78, 32 }, /* R27 */
+ { 28, 0x7C, 32 }, /* R28 */
+ { 29, 0x80, 32 }, /* R29 */
+ { 30, 0x84, 32 }, /* R30 (LP) */
+ { 31, 0x00, 32 }, /* R31 (SP) */
+ { 32, 0x04, 32 }, /* PSW */
+ { 33, 0x08, 32 }, /* IPC */
+ { 34, 0x0C, 32 }, /* IPSW */
+ { 35, 0x10, 32 }, /* IFC_LP */
};
static int64_t rtos_generic_stack_align(struct target *target,
#include <target/armv7m.h>
static const struct stack_register_offset rtos_uCOS_III_Cortex_M_stack_offsets[] = {
- { 0x20, 32 }, /* r0 */
- { 0x24, 32 }, /* r1 */
- { 0x28, 32 }, /* r2 */
- { 0x2c, 32 }, /* r3 */
- { 0x00, 32 }, /* r4 */
- { 0x04, 32 }, /* r5 */
- { 0x08, 32 }, /* r6 */
- { 0x0c, 32 }, /* r7 */
- { 0x10, 32 }, /* r8 */
- { 0x14, 32 }, /* r9 */
- { 0x18, 32 }, /* r10 */
- { 0x1c, 32 }, /* r11 */
- { 0x30, 32 }, /* r12 */
- { -2, 32 }, /* sp */
- { 0x34, 32 }, /* lr */
- { 0x38, 32 }, /* pc */
- { 0x3c, 32 }, /* xPSR */
+ { ARMV7M_R0, 0x20, 32 }, /* r0 */
+ { ARMV7M_R1, 0x24, 32 }, /* r1 */
+ { ARMV7M_R2, 0x28, 32 }, /* r2 */
+ { ARMV7M_R3, 0x2c, 32 }, /* r3 */
+ { ARMV7M_R4, 0x00, 32 }, /* r4 */
+ { ARMV7M_R5, 0x04, 32 }, /* r5 */
+ { ARMV7M_R6, 0x08, 32 }, /* r6 */
+ { ARMV7M_R7, 0x0c, 32 }, /* r7 */
+ { ARMV7M_R8, 0x10, 32 }, /* r8 */
+ { ARMV7M_R9, 0x14, 32 }, /* r9 */
+ { ARMV7M_R10, 0x18, 32 }, /* r10 */
+ { ARMV7M_R11, 0x1c, 32 }, /* r11 */
+ { ARMV7M_R12, 0x30, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, 0x34, 32 }, /* lr */
+ { ARMV7M_PC, 0x38, 32 }, /* pc */
+ { ARMV7M_xPSR, 0x3c, 32 }, /* xPSR */
};
const struct rtos_register_stacking rtos_uCOS_III_Cortex_M_stacking = {
return ERROR_OK;
}
-static int uCOS_III_get_thread_reg_list(struct rtos *rtos, threadid_t threadid, char **hex_reg_list)
+static int uCOS_III_get_thread_reg_list(struct rtos *rtos, threadid_t threadid,
+ struct rtos_reg **reg_list, int *num_regs)
{
struct uCOS_III_params *params = rtos->rtos_specific_params;
int retval;
return rtos_generic_stack_read(rtos->target,
params->stacking_info,
stack_address,
- hex_reg_list);
+ reg_list,
+ num_regs);
}
static int uCOS_III_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
LOG_DEBUG("-");
#endif
+ if ((target->rtos != NULL) && (ERROR_OK == rtos_get_gdb_reg(connection, reg_num)))
+ return ERROR_OK;
+
retval = target_get_gdb_reg_list(target, ®_list, ®_list_size,
REG_CLASS_ALL);
if (retval != ERROR_OK)
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