]> git.sur5r.net Git - u-boot/commitdiff
rockchip: rk3036: fix pll config for correct frequency
authorKever Yang <kever.yang@rock-chips.com>
Thu, 30 Nov 2017 08:51:19 +0000 (16:51 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Thu, 30 Nov 2017 21:55:27 +0000 (22:55 +0100)
There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c

index 460dd6074e607c00e5c565ec7c8ae697d1d97f71..1d3fc1a62285007edeb7523ea597e8f3962cd4a3 100644 (file)
@@ -34,10 +34,11 @@ struct rk3036_sdram_priv {
        struct rk3036_ddr_config ddr_config;
 };
 
-/* use integer mode, 396MHz dpll setting
+/*
+ * use integer mode, dpll output 792MHz and ddr get 396MHz
  * refdiv, fbdiv, postdiv1, postdiv2
  */
-const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
+const struct pll_div dpll_init_cfg = {1, 66, 2, 1};
 
 /* 396Mhz ddr timing */
 const struct rk3036_ddr_timing ddr_timing = {0x18c,