Stefan Roese [Wed, 6 Jun 2007 09:42:13 +0000 (11:42 +0200)]
ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board
This patch adds NAND booting support for the AMCC Acadia eval board.
Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.
I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
Stefan Roese [Fri, 1 Jun 2007 13:58:19 +0000 (15:58 +0200)]
ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHz
This patch undoes the patch by Jeff Mann with commit-id ada4697d. As
suggested by AMCC it is not recommended to dynamically change the EBC
speed after bootup. So we undo this change to be on the safe side.
Stefan Roese [Fri, 1 Jun 2007 13:27:11 +0000 (15:27 +0200)]
ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board
This patch adds NAND booting support for the AMCC Bamboo eval board.
Since the NAND-SPL boot image is limited to 4kbytes, this version
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
supported, since the setup code for I2C DIMM autodetection and
configuration is too big for this NAND bootloader.
Stefan Roese [Fri, 1 Jun 2007 13:15:12 +0000 (15:15 +0200)]
NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.c
This patch adds hardware ECC support to the NDFC driver. It also
changes the register access from using the "simple" in32/out32
functions to the in_be32/out_be32 functions, which make sure
that the access is correctly synced. This is the only recommended
access to SoC registers in the current Linux kernel.
Stefan Roese [Fri, 1 Jun 2007 13:12:15 +0000 (15:12 +0200)]
NAND: Update nand_ecc.c to latest Linux version
This patch updates the nand_ecc code to the latest Linux version.
The main reason for this is the more compact code. This makes
it possible to include the ECC code into the NAND bootloader
image (NAND_SPL) for PPC4xx.
Bartlomiej Sieka [Sun, 27 May 2007 15:03:37 +0000 (17:03 +0200)]
Motion-PRO: Update EEPROM's page write bits and write delay.
Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A
have a page write capability of two bytes", and "This device offers fast (1ms)
byte write". Add 3ms of extra delay.
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which
networking does not function. This commit switches PHY to TX mode by clearing
the FX_SEL bit of Mode Control Register. It also reverses commit 008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
Bartlomiej Sieka [Sun, 27 May 2007 14:53:43 +0000 (16:53 +0200)]
MPC5xxx: Change names of defines related to IPB and PCI clocks.
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining
them does not cause PCI or IPB clocks to run at the specified speed.
Instead, they configure divisors used to calculate said clocks. This
patch renames the defines according to their real function.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
Stefan Roese [Thu, 24 May 2007 06:22:09 +0000 (08:22 +0200)]
ppc4xx: Update AMCC Acadia support for board revision 1.1
This patch updates the Acadia (405EZ) support for the new 1.1 board
revision. It also adds support for NAND FLASH via the 4xx NDFC.
Please note that the jumper J7 must be in position 2-3 for this
NAND support. Position 1-2 is for NAND booting only. NAND booting
support will follow later.
Jeffrey Mann [Wed, 16 May 2007 11:23:10 +0000 (13:23 +0200)]
[PATCH] Run new sequoia boards with an EBC speed of 83MHz
Because the Sequoia board does not boot with an EBC faster than 66MHz,
the clock divider are changed after the initial boot process.
This allows for maximum clocking speeds to be achieved on newer boards.
Sequoia boards with 666.66 MHz processors require that the EBC divider
be set to 3 in order to start the initial boot process at a slower EBC
speed. After the initial boot process, the divider can be set back to 2,
which will cause the boards to run at 83.333MHz. This is backward
compatible with boards with 533.33 MHz processors, as these boards will
already be set with an EBC divider of 2.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
[MPC5xxx] There are networking problems on the Motion-PRO board with
current PHY initalization code (tftp timeouts all the time). This commit
temporarily disables PHY initalization sequence to make the networking
operational, until a fix is found.
Timur Tabi [Sat, 5 May 2007 06:12:30 +0000 (08:12 +0200)]
5xxx: write MAC address to mac-address and local-mac-address
Some device trees have a mac-address property, some have local-mac-address,
and some have both. To support all of these device trees, ftp_cpu_setup()
should write the MAC address to mac-address and local-mac-address, if they
exist.
Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
[PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message
MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up
message. Use PVR to distinguish between the two variants, and print proper CPU
information.
Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com> Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Sergei Shtylyov [Mon, 23 Apr 2007 13:30:39 +0000 (15:30 +0200)]
[PATCH] Avoid assigning PCI resources from zero address
If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE
core complains and IDE drivers fails to work. Also, assigning zero to a BAR
was illegal according to PCI 2.1 (the later revisions seem to have excluded the
sentence about "0" being considered an invalid address) -- so, use a reasonable
starting value of 0x1000 (that's what the most Linux archs are using).
Alternatively, one might have fixed the calls to pci_set_region() individually
(some code even seems to have taken care of this issue) but that would have
been a lot more work. :-)
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Acked-by: Stefan Roese <sr@denx.de>
Mike Frysinger [Mon, 23 Apr 2007 11:54:24 +0000 (13:54 +0200)]
[patch] use unsigned char in smc91111 driver for mac
the v_mac variable in the smc91111 driver is declared as a signed char ...
this causes problems when one of the bytes in the MAC is "signed" like 0xE0
because when it gets printed out, you get a display like:
0xFFFFFFE0 and that's no good
Jeffrey Mann [Sat, 5 May 2007 06:32:14 +0000 (08:32 +0200)]
ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHz
The AMCC Secquoia board has been changed in a new revision from using a
33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD
indicates the difference. This patch reads that bit and uses the correct
clock speed for the board. This code is backward compatable will all
prior boards. All prior boards will be read as 33.000.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Sat, 5 May 2007 06:29:01 +0000 (08:29 +0200)]
ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
for the 4k NAND boot image so define bus_frequency to 133MHz here
which is save for the refresh counter setup.
Thomas Knobloch [Sat, 5 May 2007 05:04:42 +0000 (07:04 +0200)]
NAND: Wrong calculation of page number in nand_block_bad()
In case that there is no memory based bad block table available the
function nand_block_checkbad() in drivers/mtd/nand/nand_base.c will call
nand_block_bad() directly. When parameter 'getchip' is set to zero,
nand_block_bad() will not right shift the offset to calculate the
correct page number.
Signed-off-by: Thomas Knobloch <knobloch@siemens.com> Signed-off-by: Stefan Roese <sr@denx.de>
Wolfgang Denk [Thu, 3 May 2007 14:34:41 +0000 (16:34 +0200)]
Update board configuration for STX GP3SSA board:
Enable hush shell, environment in flash rather in EEPROM,
more user-friendly default environment, etc.
The simple EEPROM environment can be selected easily in the board
config file.
Andy Fleming [Sat, 24 Feb 2007 07:08:13 +0000 (01:08 -0600)]
Cleaned up some 85xx PCI bugs
* Cleaned up the CDS PCI Config Tables and added NULL entries to
the end
* Fixed PCIe LAWBAR assignemt to use the cpu-relative address
* Fixed 85xx PCI code to assign powar region sizes based on the
config values (rather than hard-coding them)
* Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address
Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Mon, 23 Apr 2007 07:54:25 +0000 (02:54 -0500)]
Add support for the 8568 MDS board
This included some changes to common files:
* Add 8568 processor SVR to various places
* Add support for setting the qe bus-frequency value in the dts
* Add the 8568MDS target to the Makefile
Signed-off-by: Andy Fleming <afleming@freescale.com>
David Updegraff [Fri, 20 Apr 2007 19:34:48 +0000 (14:34 -0500)]
Add support for treating unknown PHYs as generic PHYs.
When bringing up u-boot on new boards, PHY support sometimes gets
neglected. Most PHYs don't really need any special support,
though. By adding a generic entry that always matches if nothing
else does, we can provide support for "unsupported" PHYs for the
tsec.
The generic PHY driver supports most PHYs, including gigabit.
Signed-off-by: David Updegraff <dave@cray.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Timur Tabi [Mon, 30 Apr 2007 18:59:50 +0000 (13:59 -0500)]
Fix memory initialization on MPC8349E-mITX
Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP.
This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary
on some ITX boards, notably those with a revision 3.1 CPU.
Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into
ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined.
Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Michael Benedict <MBenedict@twacs.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
James Yang [Fri, 16 Mar 2007 18:02:53 +0000 (13:02 -0500)]
Rewrote picos_to_clk() to avoid rounding errors.
Clarified that conversion is to DRAM clocks rather than platform clocks.
Made function static to spd_sdram.c.
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
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