]> git.sur5r.net Git - u-boot/commitdiff
ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board
authorStefan Roese <sr@denx.de>
Fri, 1 Jun 2007 13:27:11 +0000 (15:27 +0200)
committerStefan Roese <sr@denx.de>
Fri, 1 Jun 2007 13:27:11 +0000 (15:27 +0200)
This patch adds NAND booting support for the AMCC Bamboo eval board.
Since the NAND-SPL boot image is limited to 4kbytes, this version
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
supported, since the setup code for I2C DIMM autodetection and
configuration is too big for this NAND bootloader.

Signed-off-by: Stefan Roese <sr@denx.de>
MAKEALL
Makefile
cpu/ppc4xx/start.S
include/configs/bamboo.h
nand_spl/board/amcc/bamboo/Makefile [new file with mode: 0644]
nand_spl/board/amcc/bamboo/config.mk [new file with mode: 0644]
nand_spl/board/amcc/bamboo/sdram.c [new file with mode: 0644]
nand_spl/board/amcc/bamboo/u-boot.lds [new file with mode: 0644]

diff --git a/MAKEALL b/MAKEALL
index 47f20307064820cb265af111667cfed4a66bed85..23402a298debb3d736c738c6253d35d9cfe20f5f 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -76,21 +76,21 @@ LIST_8xx="  \
 
 LIST_4xx="     \
        acadia          ADCIOP          alpr            AP1000          \
-       AR405           ASH405          bamboo          bubinga         \
-       CANBT           CMS700          CPCI2DP         CPCI405         \
-       CPCI4052        CPCI405AB       CPCI405DT       CPCI440         \
-       CPCIISER4       CRAYL1          csb272          csb472          \
-       DASA_SIM        DP405           DU405           ebony           \
-       ERIC            EXBITGEN        G2000           HH405           \
-       HUB405          JSE             KAREF           katmai          \
-       luan            METROBOX        MIP405          MIP405T         \
-       ML2             ml300           ocotea          OCRTC           \
-       ORSG            p3p440          PCI405          pcs440ep        \
-       PIP405          PLU405          PMC405          PPChameleonEVB  \
-       sbc405          sc3             sequoia         sequoia_nand    \
-       taishan         VOH405          VOM405          W7OLMC          \
-       W7OLMG          walnut          WUH405          XPEDITE1K       \
-       yellowstone     yosemite        yucca                           \
+       AR405           ASH405          bamboo          bamboo_nand     \
+       bubinga         CANBT           CMS700          CPCI2DP         \
+       CPCI405         CPCI4052        CPCI405AB       CPCI405DT       \
+       CPCI440         CPCIISER4       CRAYL1          csb272          \
+       csb472          DASA_SIM        DP405           DU405           \
+       ebony           ERIC            EXBITGEN        G2000           \
+       HH405           HUB405          JSE             KAREF           \
+       katmai          luan            METROBOX        MIP405          \
+       MIP405T         ML2             ml300           ocotea          \
+       OCRTC           ORSG            p3p440          PCI405          \
+       pcs440ep        PIP405          PLU405          PMC405          \
+       PPChameleonEVB  sbc405          sc3             sequoia         \
+       sequoia_nand    taishan         VOH405          VOM405          \
+       W7OLMC          W7OLMG          walnut          WUH405          \
+       XPEDITE1K       yellowstone     yosemite        yucca           \
 "
 
 #########################################################################
index 8e551eb555d12cf5e910b455872f01ee330c9042..99f38afb6f7ffcce3a8f342181b5f473cd985012 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1035,6 +1035,16 @@ ASH405_config:   unconfig
 bamboo_config: unconfig
        @$(MKCONFIG) $(@:_config=) ppc ppc4xx bamboo amcc
 
+bamboo_nand_config:    unconfig
+       @mkdir -p $(obj)include
+       @mkdir -p $(obj)nand_spl
+       @mkdir -p $(obj)board/amcc/bamboo
+       @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+       @echo "Compile NAND boot image for bamboo"
+       @$(MKCONFIG) -a bamboo ppc ppc4xx bamboo amcc
+       @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/bamboo/config.tmp
+       @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
 bubinga_config:        unconfig
        @$(MKCONFIG) $(@:_config=) ppc ppc4xx bubinga amcc
 
index 3b1586c0ae3d12df74ee3bfdb69cf1c5ccf9929f..fe14ecd7bfe78cba3dcc7a850d481e498f8b0ec9 100644 (file)
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
 
+#define function_prolog(func_name)      .text; \
+                                       .align 2; \
+                                       .globl func_name; \
+                                       func_name:
+#define function_epilog(func_name)      .type func_name,@function; \
+                                       .size func_name,.-func_name
+
 /* We don't want the  MMU yet.
 */
 #undef MSR_KERNEL
@@ -388,8 +395,9 @@ rsttlb:     tlbwe   r0,r1,0x0000    /* Invalidate all entries (V=0)*/
 2:
 
 #if defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
        /*
-        * Enable internal SRAM
+        * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
         */
        lis     r2,0x7fff
        ori     r2,r2,0xffff
@@ -399,6 +407,45 @@ rsttlb:    tlbwe   r0,r1,0x0000    /* Invalidate all entries (V=0)*/
        mfdcr   r1,isram0_pmeg
        and     r1,r1,r2                /* Disable pwr mgmt */
        mtdcr   isram0_pmeg,r1
+#endif
+#if defined(CONFIG_440EP)
+       /*
+        * On 440EP with no internal SRAM, we setup SDRAM very early
+        * and copy the NAND_SPL to SDRAM and jump to it
+        */
+       /* Clear Dcache to use as RAM */
+       addis   r3,r0,CFG_INIT_RAM_ADDR@h
+       ori     r3,r3,CFG_INIT_RAM_ADDR@l
+       addis   r4,r0,CFG_INIT_RAM_END@h
+       ori     r4,r4,CFG_INIT_RAM_END@l
+       rlwinm. r5,r4,0,27,31
+       rlwinm  r5,r4,27,5,31
+       beq     ..d_ran3
+       addi    r5,r5,0x0001
+..d_ran3:
+       mtctr   r5
+..d_ag3:
+       dcbz    r0,r3
+       addi    r3,r3,32
+       bdnz    ..d_ag3
+       /*----------------------------------------------------------------*/
+       /* Setup the stack in internal SRAM */
+       /*----------------------------------------------------------------*/
+       lis     r1,CFG_INIT_RAM_ADDR@h
+       ori     r1,r1,CFG_INIT_SP_OFFSET@l
+       li      r0,0
+       stwu    r0,-4(r1)
+       stwu    r0,-4(r1)               /* Terminate call chain */
+
+       stwu    r1,-8(r1)               /* Save back chain and move SP */
+       lis     r0,RESET_VECTOR@h       /* Address of reset vector */
+       ori     r0,r0, RESET_VECTOR@l
+       stwu    r1,-8(r1)               /* Save back chain and move SP */
+       stw     r0,+12(r1)              /* Save return addr (underflow vect) */
+       sync
+       bl      early_sdram_init
+       sync
+#endif /* CONFIG_440EP */
 
        /*
         * Copy SPL from cache into internal SRAM
@@ -429,7 +476,7 @@ spl_loop:
 start_ram:
        sync
        isync
-#endif
+#endif /* CONFIG_NAND_SPL */
 
        bl      3f
        b       _start
@@ -1137,7 +1184,6 @@ crit_return:
        lwz     r1,GPR1(r1)
        SYNC
        rfci
-#endif /* CONFIG_NAND_SPL */
 
 /* Cache functions.
 */
@@ -1254,24 +1300,6 @@ wr_tcr:
        mtspr   tcr, r3
        blr
 
-/*------------------------------------------------------------------------------- */
-/* Function:    in8 */
-/* Description:         Input 8 bits */
-/*------------------------------------------------------------------------------- */
-       .globl  in8
-in8:
-       lbz     r3,0x0000(r3)
-       blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:    out8 */
-/* Description:         Output 8 bits */
-/*------------------------------------------------------------------------------- */
-       .globl  out8
-out8:
-       stb     r4,0x0000(r3)
-       blr
-
 /*------------------------------------------------------------------------------- */
 /* Function:    out16 */
 /* Description:         Output 16 bits */
@@ -1290,15 +1318,6 @@ out16r:
        sthbrx  r4,r0,r3
        blr
 
-/*------------------------------------------------------------------------------- */
-/* Function:    out32 */
-/* Description:         Output 32 bits */
-/*------------------------------------------------------------------------------- */
-       .globl  out32
-out32:
-       stw     r4,0x0000(r3)
-       blr
-
 /*------------------------------------------------------------------------------- */
 /* Function:    out32r */
 /* Description:         Byte reverse and output 32 bits */
@@ -1326,15 +1345,6 @@ in16r:
        lhbrx   r3,r0,r3
        blr
 
-/*------------------------------------------------------------------------------- */
-/* Function:    in32 */
-/* Description:         Input 32 bits */
-/*------------------------------------------------------------------------------- */
-       .globl  in32
-in32:
-       lwz     3,0x0000(3)
-       blr
-
 /*------------------------------------------------------------------------------- */
 /* Function:    in32r */
 /* Description:         Input 32 bits and byte reverse */
@@ -1377,9 +1387,6 @@ ppcSync:
        sync
        blr
 
-/*------------------------------------------------------------------------------*/
-
-#ifndef CONFIG_NAND_SPL
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -1644,8 +1651,88 @@ trap_reloc:
        stw     r0, 4(r7)
 
        blr
+
+#if defined(CONFIG_440)
+/*----------------------------------------------------------------------------+
+| dcbz_area.
++----------------------------------------------------------------------------*/
+       function_prolog(dcbz_area)
+       rlwinm. r5,r4,0,27,31
+       rlwinm  r5,r4,27,5,31
+       beq     ..d_ra2
+       addi    r5,r5,0x0001
+..d_ra2:mtctr   r5
+..d_ag2:dcbz    r0,r3
+       addi    r3,r3,32
+       bdnz    ..d_ag2
+       sync
+       blr
+       function_epilog(dcbz_area)
+
+/*----------------------------------------------------------------------------+
+| dflush.  Assume 32K at vector address is cachable.
++----------------------------------------------------------------------------*/
+       function_prolog(dflush)
+       mfmsr   r9
+       rlwinm  r8,r9,0,15,13
+       rlwinm  r8,r8,0,17,15
+       mtmsr   r8
+       addi    r3,r0,0x0000
+       mtspr   dvlim,r3
+       mfspr   r3,ivpr
+       addi    r4,r0,1024
+       mtctr   r4
+..dflush_loop:
+       lwz     r6,0x0(r3)
+       addi    r3,r3,32
+       bdnz    ..dflush_loop
+       addi    r3,r3,-32
+       mtctr   r4
+..ag:   dcbf    r0,r3
+       addi    r3,r3,-32
+       bdnz    ..ag
+       sync
+       mtmsr   r9
+       blr
+       function_epilog(dflush)
+#endif /* CONFIG_440 */
 #endif /* CONFIG_NAND_SPL */
 
+/*------------------------------------------------------------------------------- */
+/* Function:    in8 */
+/* Description:         Input 8 bits */
+/*------------------------------------------------------------------------------- */
+       .globl  in8
+in8:
+       lbz     r3,0x0000(r3)
+       blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:    out8 */
+/* Description:         Output 8 bits */
+/*------------------------------------------------------------------------------- */
+       .globl  out8
+out8:
+       stb     r4,0x0000(r3)
+       blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:    out32 */
+/* Description:         Output 32 bits */
+/*------------------------------------------------------------------------------- */
+       .globl  out32
+out32:
+       stw     r4,0x0000(r3)
+       blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:    in32 */
+/* Description:         Input 32 bits */
+/*------------------------------------------------------------------------------- */
+       .globl  in32
+in32:
+       lwz     3,0x0000(3)
+       blr
 
 /**************************************************************************/
 /* PPC405EP specific stuff                                               */
@@ -1892,13 +1979,6 @@ pll_wait:
 #endif /* CONFIG_405EP */
 
 #if defined(CONFIG_440)
-#define function_prolog(func_name)      .text; \
-                                       .align 2; \
-                                       .globl func_name; \
-                                       func_name:
-#define function_epilog(func_name)      .type func_name,@function; \
-                                       .size func_name,.-func_name
-
 /*----------------------------------------------------------------------------+
 | mttlb3.
 +----------------------------------------------------------------------------*/
@@ -1946,47 +2026,4 @@ pll_wait:
        TLBRE(3,3,0)
        blr
        function_epilog(mftlb1)
-
-/*----------------------------------------------------------------------------+
-| dcbz_area.
-+----------------------------------------------------------------------------*/
-       function_prolog(dcbz_area)
-       rlwinm. r5,r4,0,27,31
-       rlwinm  r5,r4,27,5,31
-       beq     ..d_ra2
-       addi    r5,r5,0x0001
-..d_ra2:mtctr   r5
-..d_ag2:dcbz    r0,r3
-       addi    r3,r3,32
-       bdnz    ..d_ag2
-       sync
-       blr
-       function_epilog(dcbz_area)
-
-/*----------------------------------------------------------------------------+
-| dflush.  Assume 32K at vector address is cachable.
-+----------------------------------------------------------------------------*/
-       function_prolog(dflush)
-       mfmsr   r9
-       rlwinm  r8,r9,0,15,13
-       rlwinm  r8,r8,0,17,15
-       mtmsr   r8
-       addi    r3,r0,0x0000
-       mtspr   dvlim,r3
-       mfspr   r3,ivpr
-       addi    r4,r0,1024
-       mtctr   r4
-..dflush_loop:
-       lwz     r6,0x0(r3)
-       addi    r3,r3,32
-       bdnz    ..dflush_loop
-       addi    r3,r3,-32
-       mtctr   r4
-..ag:   dcbf    r0,r3
-       addi    r3,r3,-32
-       bdnz    ..ag
-       sync
-       mtmsr   r9
-       blr
-       function_epilog(dflush)
 #endif /* CONFIG_440 */
index db58a9fa74a204f2f7b14d02690962b5cd2c42dd..763d1c7a8b48632df13d9868ddf4c958362ca71e 100644 (file)
@@ -50,7 +50,7 @@
  *----------------------------------------------------------------------*/
 #define CFG_MONITOR_LEN                (384 * 1024)    /* Reserve 384 kB for Monitor   */
 #define CFG_MALLOC_LEN         (256 * 1024)    /* Reserve 256 kB for malloc()  */
-#define CFG_MONITOR_BASE       (-CFG_MONITOR_LEN)
+#define CFG_MONITOR_BASE       TEXT_BASE
 #define CFG_SDRAM_BASE         0x00000000          /* _must_ be 0      */
 #define CFG_FLASH_BASE         0xfff00000          /* start of FLASH   */
 #define CFG_PCI_MEMBASE                0xa0000000          /* mapped pci memory*/
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CFG_ENV_IS_IN_FLASH     1      /* use FLASH for environment vars       */
 #else
-#define CFG_ENV_IS_IN_EEPROM   1       /* use EEPROM for environment vars      */
+#define CFG_ENV_IS_IN_NAND     1       /* use NAND for environment vars        */
+#define CFG_ENV_IS_EMBEDDED    1       /* use embedded environment */
 #endif
 
 /*-----------------------------------------------------------------------
 
 #ifdef CFG_ENV_IS_IN_FLASH
 #define CFG_ENV_SECT_SIZE      0x10000         /* size of one complete sector  */
-#define CFG_ENV_ADDR           (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR           ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 #define        CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 
 /* Address and size of Redundant Environment Sector    */
 #define CFG_ENV_SIZE_REDUND    (CFG_ENV_SIZE)
 #endif /* CFG_ENV_IS_IN_FLASH */
 
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller.        sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC  0xfffff000      /* SPL location                 */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10)       /* SPL size                     */
+#define CFG_NAND_BOOT_SPL_DST  0x00800000      /* Copy SPL here                */
+#define CFG_NAND_U_BOOT_DST    0x01000000      /* Load NUB to this addr        */
+#define CFG_NAND_U_BOOT_START  CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CFG_NAND_BOOT_SPL_DELTA        (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS   (16 << 10)      /* Offset to RAM U-Boot image   */
+#define CFG_NAND_U_BOOT_SIZE   (384 << 10)     /* Size of RAM U-Boot image     */
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE     512             /* NAND chip page size          */
+#define CFG_NAND_BLOCK_SIZE    (16 << 10)      /* NAND chip block size         */
+#define CFG_NAND_PAGE_COUNT    32              /* NAND chip page count         */
+#define CFG_NAND_BAD_BLOCK_POS 5               /* Location of bad block marker */
+#define CFG_NAND_4_ADDR_CYCLE  1               /* Fourth addr used (>32MB)     */
+
+#define CFG_NAND_ECCSIZE       256
+#define CFG_NAND_ECCBYTES      3
+#define CFG_NAND_ECCSTEPS      (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE       16
+#define CFG_NAND_ECCTOTAL      (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS                {0, 1, 2, 3, 6, 7}
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE           CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET         (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND  (CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
-#define CFG_MAX_NAND_DEVICE    1
-#define NAND_MAX_CHIPS         1
-#define CFG_NAND_CS            1
+#define CFG_MAX_NAND_DEVICE    2
+#define NAND_MAX_CHIPS         CFG_MAX_NAND_DEVICE
 #define CFG_NAND_BASE          (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_BASE_LIST     { CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
 #define CFG_NAND_SELECT_DEVICE  1      /* nand driver supports mutipl. chips   */
 
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS            1
+#else
+#define CFG_NAND_CS            0               /* NAND chip connected to CSx   */
+/* Memory Bank 0 (NAND-FLASH) initialization                                   */
+#define CFG_EBC_PB0AP          0x018003c0
+#define CFG_EBC_PB0CR          (CFG_NAND_ADDR | 0x1c000)
+#endif
+
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------------- */
 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 #undef CONFIG_DDR_ECC                  /* don't use ECC                        */
 #define CFG_SIMULATE_SPD_EEPROM        0xff    /* simulate spd eeprom on this address  */
-#define SPD_EEPROM_ADDRESS      {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define SPD_EEPROM_ADDRESS     {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define CFG_MBYTES_SDRAM       (64)    /* 64MB fixed size for early-sdram-init */
 
 /*-----------------------------------------------------------------------
  * I2C
diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile
new file mode 100644 (file)
index 0000000..0df86f9
--- /dev/null
@@ -0,0 +1,100 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS        = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS  = start.o init.o resetvec.o
+COBJS  = nand_boot.o nand_ecc.o ndfc.o sdram.o
+
+SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR  := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj        := $(OBJTREE)/nand_spl/
+
+ALL    = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:   $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+       $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:      $(nandobj)u-boot-spl
+       $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:  $(OBJS)
+       cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+               -Map $(nandobj)u-boot-spl.map \
+               -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+# from cpu directory
+$(obj)ndfc.c:
+       @rm -f $(obj)ndfc.c
+       ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
+
+$(obj)resetvec.S:
+       @rm -f $(obj)resetvec.S
+       ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+
+$(obj)start.S:
+       @rm -f $(obj)start.S
+       ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+
+# from board directory
+$(obj)init.S:
+       @rm -f $(obj)init.S
+       ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S
+
+# from nand_spl directory
+$(obj)nand_boot.c:
+       @rm -f $(obj)nand_boot.c
+       ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+
+# from drivers/nand directory
+$(obj)nand_ecc.c:
+       @rm -f $(obj)nand_ecc.c
+       ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
+
+#########################################################################
+
+$(obj)%.o:     $(obj)%.S
+       $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:     $(obj)%.c
+       $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/amcc/bamboo/config.mk b/nand_spl/board/amcc/bamboo/config.mk
new file mode 100644 (file)
index 0000000..f7ec751
--- /dev/null
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EP Reference Platform (Bamboo) board
+#
+
+#
+# TEXT_BASE for SPL:
+#
+# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
+# in the last 4kBytes of memory space in cache.
+# We will copy this SPL into instruction-cache in start.S. So we set
+# TEXT_BASE to starting address in i-cache here.
+#
+TEXT_BASE = 0x00800000
+
+# PAD_TO used to generate a 16kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 0x4000
+PAD_TO = 0x00804000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c
new file mode 100644 (file)
index 0000000..4f09072
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+static void wait_init_complete(void)
+{
+       u32 val;
+
+       do {
+               mfsdram(mem_mcsts, val);
+       } while (!(val & 0x80000000));
+}
+
+/*
+ * early_sdram_init()
+ *
+ * As the name already indicates, this function is called very early
+ * from start.S and configures the SDRAM with fixed values. This is needed,
+ * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
+ * not enough free space to implement the complete I2C SPD DDR autodetection
+ * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
+ * when booting from NAND flash.
+ */
+void early_sdram_init(void)
+{
+       /*
+        * Soft-reset SDRAM controller.
+        */
+       mtsdr(sdr_srst, SDR0_SRST_DMC);
+       mtsdr(sdr_srst, 0x00000000);
+
+       /*
+        * Disable memory controller.
+        */
+       mtsdram(mem_cfg0, 0x00000000);
+
+       /*
+        * Setup some default
+        */
+       mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
+       mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
+       mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal)         */
+       mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0                */
+       mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0    */
+
+       /*
+        * Following for CAS Latency = 2.5 @ 133 MHz PLB
+        */
+       mtsdram(mem_b0cr, 0x00082001);
+       mtsdram(mem_tr0, 0x41094012);
+       mtsdram(mem_tr1, 0x8080083d);   /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
+       mtsdram(mem_rtr, 0x04100000);   /* Interval 7.8µs @ 133MHz PLB  */
+       mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM*/
+
+       /*
+        * Enable the controller, then wait for DCEN to complete
+        */
+       mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/
+       wait_init_complete();
+}
+
+long int initdram(int board_type)
+{
+       /*
+        * Nothing to do here, just return size of fixed SDRAM setup
+        */
+       return CFG_MBYTES_SDRAM << 20;
+}
diff --git a/nand_spl/board/amcc/bamboo/u-boot.lds b/nand_spl/board/amcc/bamboo/u-boot.lds
new file mode 100644 (file)
index 0000000..28228f8
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc:common)
+SECTIONS
+{
+  .resetvec 0x00800FFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .text      :
+  {
+    start.o    (.text)
+    init.o     (.text)
+    nand_boot.o        (.text)
+    sdram.o    (.text)
+    ndfc.o     (.text)
+
+    *(.text)
+    *(.fixup)
+  }
+  _etext = .;
+
+  .data    :
+  {
+    *(.rodata*)
+    *(.data*)
+    *(.sdata*)
+    __got2_start = .;
+    *(.got2)
+    __got2_end = .;
+  }
+
+  _edata  =  .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss)
+   *(.bss)
+  }
+
+  _end = . ;
+}